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authorJoshua Bakita <bakitajoshua@gmail.com>2023-10-29 13:07:40 -0400
committerJoshua Bakita <bakitajoshua@gmail.com>2023-10-29 13:10:52 -0400
commit2c5337a24f7f2d02989dfb733c55d6d8c7e90493 (patch)
treeb9f1028cb443b03190b710c0d7ee640bf5958631 /include/nvgpu/hw/gm20b
parentaa06f84f03cba7ad1aae5cd527355bb3d8c152a6 (diff)
Update includes to L4T r32.7.4 and drop nvgpu/gk20a.h dependency
Also add instructions for updating `include/`. These files are now only needed to build on Linux 4.9-based Tegra platforms.
Diffstat (limited to 'include/nvgpu/hw/gm20b')
-rw-r--r--include/nvgpu/hw/gm20b/hw_gr_gm20b.h14
1 files changed, 13 insertions, 1 deletions
diff --git a/include/nvgpu/hw/gm20b/hw_gr_gm20b.h b/include/nvgpu/hw/gm20b/hw_gr_gm20b.h
index 5bbb3b9..79ad326 100644
--- a/include/nvgpu/hw/gm20b/hw_gr_gm20b.h
+++ b/include/nvgpu/hw/gm20b/hw_gr_gm20b.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2014-2023, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -1396,6 +1396,10 @@ static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void)
1396{ 1396{
1397 return 0x00502400U; 1397 return 0x00502400U;
1398} 1398}
1399static inline u32 gr_gpc0_gpccs_ctxsw_mailbox__size_1_v(void)
1400{
1401 return 0x00000010U;
1402}
1399static inline u32 gr_fecs_ctxsw_idlestate_r(void) 1403static inline u32 gr_fecs_ctxsw_idlestate_r(void)
1400{ 1404{
1401 return 0x00409420U; 1405 return 0x00409420U;
@@ -2344,6 +2348,14 @@ static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_m(void)
2344{ 2348{
2345 return 0x1U << 4U; 2349 return 0x1U << 4U;
2346} 2350}
2351static inline u32 gr_gpcs_tpcs_tex_m_dbg2_tex_rd_coalesce_en_f(u32 v)
2352{
2353 return (v & 0x1U) << 5U;
2354}
2355static inline u32 gr_gpcs_tpcs_tex_m_dbg2_tex_rd_coalesce_en_m(void)
2356{
2357 return 0x1U << 5U;
2358}
2347static inline u32 gr_gpccs_falcon_addr_r(void) 2359static inline u32 gr_gpccs_falcon_addr_r(void)
2348{ 2360{
2349 return 0x0041a0acU; 2361 return 0x0041a0acU;