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authorJoshua Bakita <bakitajoshua@gmail.com>2023-10-29 13:07:40 -0400
committerJoshua Bakita <bakitajoshua@gmail.com>2023-10-29 13:10:52 -0400
commit2c5337a24f7f2d02989dfb733c55d6d8c7e90493 (patch)
treeb9f1028cb443b03190b710c0d7ee640bf5958631 /include/nvgpu/gk20a.h
parentaa06f84f03cba7ad1aae5cd527355bb3d8c152a6 (diff)
Update includes to L4T r32.7.4 and drop nvgpu/gk20a.h dependency
Also add instructions for updating `include/`. These files are now only needed to build on Linux 4.9-based Tegra platforms.
Diffstat (limited to 'include/nvgpu/gk20a.h')
-rw-r--r--include/nvgpu/gk20a.h8
1 files changed, 6 insertions, 2 deletions
diff --git a/include/nvgpu/gk20a.h b/include/nvgpu/gk20a.h
index aa95969..19bfaee 100644
--- a/include/nvgpu/gk20a.h
+++ b/include/nvgpu/gk20a.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2011-2022, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * GK20A Graphics 4 * GK20A Graphics
5 * 5 *
@@ -517,6 +517,7 @@ struct gpu_ops {
517 u32 *priv_addr_table, 517 u32 *priv_addr_table,
518 u32 *priv_addr_table_index); 518 u32 *priv_addr_table_index);
519 u32 (*fecs_ctxsw_mailbox_size)(void); 519 u32 (*fecs_ctxsw_mailbox_size)(void);
520 u32 (*gpc0_gpccs_ctxsw_mailbox_size)(void);
520 int (*init_sw_bundle64)(struct gk20a *g); 521 int (*init_sw_bundle64)(struct gk20a *g);
521 int (*alloc_global_ctx_buffers)(struct gk20a *g); 522 int (*alloc_global_ctx_buffers)(struct gk20a *g);
522 int (*map_global_ctx_buffers)(struct gk20a *g, 523 int (*map_global_ctx_buffers)(struct gk20a *g,
@@ -719,7 +720,7 @@ struct gpu_ops {
719 struct ch_state *ch_state); 720 struct ch_state *ch_state);
720 u32 (*intr_0_error_mask)(struct gk20a *g); 721 u32 (*intr_0_error_mask)(struct gk20a *g);
721 int (*is_preempt_pending)(struct gk20a *g, u32 id, 722 int (*is_preempt_pending)(struct gk20a *g, u32 id,
722 unsigned int id_type); 723 unsigned int id_type, bool preempt_retries_left);
723 void (*init_pbdma_intr_descs)(struct fifo_gk20a *f); 724 void (*init_pbdma_intr_descs)(struct fifo_gk20a *f);
724 int (*reset_enable_hw)(struct gk20a *g); 725 int (*reset_enable_hw)(struct gk20a *g);
725 int (*setup_userd)(struct channel_gk20a *c); 726 int (*setup_userd)(struct channel_gk20a *c);
@@ -1079,6 +1080,7 @@ struct gpu_ops {
1079 u32 (*pmu_pg_supported_engines_list)(struct gk20a *g); 1080 u32 (*pmu_pg_supported_engines_list)(struct gk20a *g);
1080 u32 (*pmu_pg_engines_feature_list)(struct gk20a *g, 1081 u32 (*pmu_pg_engines_feature_list)(struct gk20a *g,
1081 u32 pg_engine_id); 1082 u32 pg_engine_id);
1083 int (*pmu_process_pg_event)(struct gk20a *g, void *pmumsg);
1082 bool (*pmu_is_lpwr_feature_supported)(struct gk20a *g, 1084 bool (*pmu_is_lpwr_feature_supported)(struct gk20a *g,
1083 u32 feature_id); 1085 u32 feature_id);
1084 int (*pmu_lpwr_enable_pg)(struct gk20a *g, bool pstate_lock); 1086 int (*pmu_lpwr_enable_pg)(struct gk20a *g, bool pstate_lock);
@@ -1793,6 +1795,8 @@ bool gk20a_check_poweron(struct gk20a *g);
1793int gk20a_prepare_poweroff(struct gk20a *g); 1795int gk20a_prepare_poweroff(struct gk20a *g);
1794int gk20a_finalize_poweron(struct gk20a *g); 1796int gk20a_finalize_poweron(struct gk20a *g);
1795 1797
1798int nvgpu_wait_for_stall_interrupts(struct gk20a *g, u32 timeout);
1799int nvgpu_wait_for_nonstall_interrupts(struct gk20a *g, u32 timeout);
1796void nvgpu_wait_for_deferred_interrupts(struct gk20a *g); 1800void nvgpu_wait_for_deferred_interrupts(struct gk20a *g);
1797 1801
1798struct gk20a * __must_check gk20a_get(struct gk20a *g); 1802struct gk20a * __must_check gk20a_get(struct gk20a *g);