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authorJoshua Bakita <bakitajoshua@gmail.com>2024-09-25 16:09:09 -0400
committerJoshua Bakita <bakitajoshua@gmail.com>2024-09-25 16:09:09 -0400
commitf347fde22f1297e4f022600d201780d5ead78114 (patch)
tree76be305d6187003a1e0486ff6e91efb1062ae118 /include/gk20a/ce2_gk20a.h
parent8340d234d78a7d0f46c11a584de538148b78b7cb (diff)
Delete no-longer-needed nvgpu headersHEADmasterjbakita-wip
The dependency on these was removed in commit 8340d234.
Diffstat (limited to 'include/gk20a/ce2_gk20a.h')
-rw-r--r--include/gk20a/ce2_gk20a.h156
1 files changed, 0 insertions, 156 deletions
diff --git a/include/gk20a/ce2_gk20a.h b/include/gk20a/ce2_gk20a.h
deleted file mode 100644
index df3a0e8..0000000
--- a/include/gk20a/ce2_gk20a.h
+++ /dev/null
@@ -1,156 +0,0 @@
1/*
2 * drivers/video/tegra/host/gk20a/fifo_gk20a.h
3 *
4 * GK20A graphics copy engine (gr host)
5 *
6 * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 */
26#ifndef NVGPU_GK20A_CE2_GK20A_H
27#define NVGPU_GK20A_CE2_GK20A_H
28
29struct channel_gk20a;
30struct tsg_gk20a;
31
32void gk20a_ce2_isr(struct gk20a *g, u32 inst_id, u32 pri_base);
33u32 gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base);
34
35/* CE command utility macros */
36#define NVGPU_CE_LOWER_ADDRESS_OFFSET_MASK 0xffffffff
37#define NVGPU_CE_UPPER_ADDRESS_OFFSET_MASK 0xff
38
39#define NVGPU_CE_MAX_INFLIGHT_JOBS 32
40#define NVGPU_CE_MAX_COMMAND_BUFF_BYTES_PER_KICKOFF 256
41
42/* dma launch_flags */
43enum {
44 /* location */
45 NVGPU_CE_SRC_LOCATION_COHERENT_SYSMEM = (1 << 0),
46 NVGPU_CE_SRC_LOCATION_NONCOHERENT_SYSMEM = (1 << 1),
47 NVGPU_CE_SRC_LOCATION_LOCAL_FB = (1 << 2),
48 NVGPU_CE_DST_LOCATION_COHERENT_SYSMEM = (1 << 3),
49 NVGPU_CE_DST_LOCATION_NONCOHERENT_SYSMEM = (1 << 4),
50 NVGPU_CE_DST_LOCATION_LOCAL_FB = (1 << 5),
51
52 /* memory layout */
53 NVGPU_CE_SRC_MEMORY_LAYOUT_PITCH = (1 << 6),
54 NVGPU_CE_SRC_MEMORY_LAYOUT_BLOCKLINEAR = (1 << 7),
55 NVGPU_CE_DST_MEMORY_LAYOUT_PITCH = (1 << 8),
56 NVGPU_CE_DST_MEMORY_LAYOUT_BLOCKLINEAR = (1 << 9),
57
58 /* transfer type */
59 NVGPU_CE_DATA_TRANSFER_TYPE_PIPELINED = (1 << 10),
60 NVGPU_CE_DATA_TRANSFER_TYPE_NON_PIPELINED = (1 << 11),
61};
62
63/* CE operation mode */
64enum {
65 NVGPU_CE_PHYS_MODE_TRANSFER = (1 << 0),
66 NVGPU_CE_MEMSET = (1 << 1),
67};
68
69/* CE app state machine flags */
70enum {
71 NVGPU_CE_ACTIVE = (1 << 0),
72 NVGPU_CE_SUSPEND = (1 << 1),
73};
74
75/* gpu context state machine flags */
76enum {
77 NVGPU_CE_GPU_CTX_ALLOCATED = (1 << 0),
78 NVGPU_CE_GPU_CTX_DELETED = (1 << 1),
79};
80
81/* global ce app db */
82struct gk20a_ce_app {
83 bool initialised;
84 struct nvgpu_mutex app_mutex;
85 int app_state;
86
87 struct nvgpu_list_node allocated_contexts;
88 u32 ctx_count;
89 u32 next_ctx_id;
90};
91
92/* ce context db */
93struct gk20a_gpu_ctx {
94 struct gk20a *g;
95 u32 ctx_id;
96 struct nvgpu_mutex gpu_ctx_mutex;
97 int gpu_ctx_state;
98
99 /* tsg related data */
100 struct tsg_gk20a *tsg;
101
102 /* channel related data */
103 struct channel_gk20a *ch;
104 struct vm_gk20a *vm;
105
106 /* cmd buf mem_desc */
107 struct nvgpu_mem cmd_buf_mem;
108 struct gk20a_fence *postfences[NVGPU_CE_MAX_INFLIGHT_JOBS];
109
110 struct nvgpu_list_node list;
111
112 u32 cmd_buf_read_queue_offset;
113};
114
115static inline struct gk20a_gpu_ctx *
116gk20a_gpu_ctx_from_list(struct nvgpu_list_node *node)
117{
118 return (struct gk20a_gpu_ctx *)
119 ((uintptr_t)node - offsetof(struct gk20a_gpu_ctx, list));
120};
121
122/* global CE app related apis */
123int gk20a_init_ce_support(struct gk20a *g);
124void gk20a_ce_suspend(struct gk20a *g);
125void gk20a_ce_destroy(struct gk20a *g);
126
127/* CE app utility functions */
128u32 gk20a_ce_create_context(struct gk20a *g,
129 int runlist_id,
130 int timeslice,
131 int runlist_level);
132int gk20a_ce_execute_ops(struct gk20a *g,
133 u32 ce_ctx_id,
134 u64 src_buf,
135 u64 dst_buf,
136 u64 size,
137 unsigned int payload,
138 int launch_flags,
139 int request_operation,
140 u32 submit_flags,
141 struct gk20a_fence **gk20a_fence_out);
142void gk20a_ce_delete_context_priv(struct gk20a *g,
143 u32 ce_ctx_id);
144void gk20a_ce_delete_context(struct gk20a *g,
145 u32 ce_ctx_id);
146int gk20a_ce_prepare_submit(u64 src_buf,
147 u64 dst_buf,
148 u64 size,
149 u32 *cmd_buf_cpu_va,
150 u32 max_cmd_buf_size,
151 unsigned int payload,
152 int launch_flags,
153 int request_operation,
154 u32 dma_copy_class);
155
156#endif /*NVGPU_GK20A_CE2_GK20A_H*/