Delete no-longer-needed nvgpu headers

The dependency on these was removed in commit 8340d234.

29 files changed, 0 insertions, 23506 deletions

diff --git a/include/gk20a/ce2_gk20a.c b/include/gk20a/ce2_gk20a.c
deleted file mode 100644
index 2a40b08..0000000
--- a/include/gk20a/ce2_gk20a.c
+++ /dev/null
@@ -1,576 +0,0 @@
-/*
- * GK20A Graphics Copy Engine  (gr host)
- *
- * Copyright (c) 2011-2019, NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#include <nvgpu/kmem.h>
-#include <nvgpu/dma.h>
-#include <nvgpu/os_sched.h>
-#include <nvgpu/log.h>
-#include <nvgpu/enabled.h>
-#include <nvgpu/io.h>
-#include <nvgpu/utils.h>
-#include <nvgpu/channel.h>
-#include <nvgpu/power_features/cg.h>
-
-#include "gk20a.h"
-#include "gk20a/fence_gk20a.h"
-
-#include <nvgpu/hw/gk20a/hw_ce2_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_pbdma_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_ccsr_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_ram_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_top_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_gr_gk20a.h>
-#include <nvgpu/barrier.h>
-
-/*
- * Copy engine defines line size in pixels
- */
-#define MAX_CE_SHIFT    31      /* 4Gpixels -1 */
-#define MAX_CE_MASK     ((u32) (~(~0U << MAX_CE_SHIFT)))
-#define MAX_CE_ALIGN(a) (a & MAX_CE_MASK)
-
-
-static u32 ce2_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr)
-{
-        nvgpu_log(g, gpu_dbg_intr, "ce2 non-blocking pipe interrupt\n");
-
-        return ce2_intr_status_nonblockpipe_pending_f();
-}
-
-static u32 ce2_blockpipe_isr(struct gk20a *g, u32 fifo_intr)
-{
-        nvgpu_log(g, gpu_dbg_intr, "ce2 blocking pipe interrupt\n");
-
-        return ce2_intr_status_blockpipe_pending_f();
-}
-
-static u32 ce2_launcherr_isr(struct gk20a *g, u32 fifo_intr)
-{
-        nvgpu_log(g, gpu_dbg_intr, "ce2 launch error interrupt\n");
-
-        return ce2_intr_status_launcherr_pending_f();
-}
-
-void gk20a_ce2_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
-{
-        u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r());
-        u32 clear_intr = 0;
-
-        nvgpu_log(g, gpu_dbg_intr, "ce2 isr %08x\n", ce2_intr);
-
-        /* clear blocking interrupts: they exibit broken behavior */
-        if (ce2_intr & ce2_intr_status_blockpipe_pending_f()) {
-                clear_intr |= ce2_blockpipe_isr(g, ce2_intr);
-        }
-
-        if (ce2_intr & ce2_intr_status_launcherr_pending_f()) {
-                clear_intr |= ce2_launcherr_isr(g, ce2_intr);
-        }
-
-        gk20a_writel(g, ce2_intr_status_r(), clear_intr);
-        return;
-}
-
-u32 gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
-{
-        u32 ops = 0;
-        u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r());
-
-        nvgpu_log(g, gpu_dbg_intr, "ce2 nonstall isr %08x\n", ce2_intr);
-
-        if (ce2_intr & ce2_intr_status_nonblockpipe_pending_f()) {
-                gk20a_writel(g, ce2_intr_status_r(),
-                        ce2_nonblockpipe_isr(g, ce2_intr));
-                ops |= (GK20A_NONSTALL_OPS_WAKEUP_SEMAPHORE |
-                        GK20A_NONSTALL_OPS_POST_EVENTS);
-        }
-        return ops;
-}
-
-/* static CE app api */
-static void gk20a_ce_put_fences(struct gk20a_gpu_ctx *ce_ctx)
-{
-        u32 i;
-
-        for (i = 0; i < NVGPU_CE_MAX_INFLIGHT_JOBS; i++) {
-                struct gk20a_fence **fence = &ce_ctx->postfences[i];
-                if (*fence) {
-                        gk20a_fence_put(*fence);
-                }
-                *fence = NULL;
-        }
-}
-
-/* assume this api should need to call under nvgpu_mutex_acquire(&ce_app->app_mutex) */
-static void gk20a_ce_delete_gpu_context(struct gk20a_gpu_ctx *ce_ctx)
-{
-        struct nvgpu_list_node *list = &ce_ctx->list;
-
-        ce_ctx->gpu_ctx_state = NVGPU_CE_GPU_CTX_DELETED;
-
-        nvgpu_mutex_acquire(&ce_ctx->gpu_ctx_mutex);
-
-        if (nvgpu_mem_is_valid(&ce_ctx->cmd_buf_mem)) {
-                gk20a_ce_put_fences(ce_ctx);
-                nvgpu_dma_unmap_free(ce_ctx->vm, &ce_ctx->cmd_buf_mem);
-        }
-
-        /*
-         * free the channel
-         * gk20a_channel_close() will also unbind the channel from TSG
-         */
-        gk20a_channel_close(ce_ctx->ch);
-        nvgpu_ref_put(&ce_ctx->tsg->refcount, gk20a_tsg_release);
-
-        /* housekeeping on app */
-        if (list->prev && list->next) {
-                nvgpu_list_del(list);
-        }
-
-        nvgpu_mutex_release(&ce_ctx->gpu_ctx_mutex);
-        nvgpu_mutex_destroy(&ce_ctx->gpu_ctx_mutex);
-
-        nvgpu_kfree(ce_ctx->g, ce_ctx);
-}
-
-static inline unsigned int gk20a_ce_get_method_size(int request_operation,
-                        u64 size)
-{
-        /* failure size */
-        unsigned int methodsize = UINT_MAX;
-        unsigned int iterations = 0;
-        u32 shift;
-        u64 chunk = size;
-        u32 height, width;
-
-        while (chunk) {
-                iterations++;
-
-                shift = MAX_CE_ALIGN(chunk) ? __ffs(MAX_CE_ALIGN(chunk)) :
-                                                MAX_CE_SHIFT;
-                width = chunk >> shift;
-                height = 1 << shift;
-                width = MAX_CE_ALIGN(width);
-