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* ntb: initialize max_mw for Atom before using itDaniel Verkamp2015-06-11
| | | | | | | | | | | | | | | | | | | Commit ab760a0 (ntb: Adding split BAR support for Haswell platforms) changed ntb_device's mw from a fixed-size array into a pointer that is allocated based on limits.max_mw; however, on Atom platforms, max_mw is not initialized until ntb_device_setup(), which happens after the allocation. Fill out max_mw in ntb_atom_detect() to match ntb_xeon_detect(); this happens before the use of max_mw in the ndev->mw allocation. Fixes a null pointer dereference on Atom platforms with ntb hardware. v2: fix typo (mw_max should be max_mw) Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com> Acked-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* ntb: iounmap MW reg and vbase in error pathJon Mason2015-06-08
| | | | | | | | | The MW regbase and vbase(s) were not being freed if an error occurred in the vbase allocation loop. This is corrected by updating the error path for the allocation loop to err4. Reported-by: Julia Lawall <julia.lawall@lip6.fr> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* ntb: Adding split BAR support for Haswell platformsDave Jiang2014-10-17
| | | | | | | | | On the Haswell platform, a split BAR option to allow creation of 2 32bit BARs (4 and 5) from the 64bit BAR 4. Adding support for this new option. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* ntb: use errata flag set via DID to implement workaroundDave Jiang2014-10-17
| | | | | | | | | Instead of using a module parameter, we should detect the errata via PCI DID and then set an appropriate flag. This will be used for additional errata later on. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* ntb: conslidate reading of PPD to move platform detection earlierDave Jiang2014-10-17
| | | | | | | | To simplify some of the platform detection code. Move the platform detection to a function to be called earlier. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* ntb: move platform detection to separate functionDave Jiang2014-10-17
| | | | | | | | Move the platform detection function to separate functions to allow easier maintenence. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* NTB: debugfs device entryJon Mason2014-10-17
| | | | | | | Create a debugfs entry for the NTB device to log the basic device info, as well as display the error count on a number of registers. Signed-off-by: Jon Mason <jon.mason@intel.com>
* ntb: Add alignment check to meet hardware requirementDave Jiang2014-09-14
| | | | | | | | | | | | The NTB translate register must have the value to be BAR size aligned. This alignment check make sure that the DMA memory allocated has the proper alignment. Another requirement for NTB to function properly with memory window BAR size greater or equal to 4M is to use the CMA feature in 3.16 kernel with the appropriate CONFIG_CMA_ALIGNMENT and CONFIG_CMA_SIZE_MBYTES set. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* NTB: correct the spread of queues over mw'sJon Mason2014-09-14
| | | | | | | | The detection of an uneven number of queues on the given memory windows was not correct. The mw_num is zero based and the mod should be division to spread them evenly over the mw's. Signed-off-by: Jon Mason <jon.mason@intel.com>
* ntb: Use pci_enable_msix_range() instead of pci_enable_msix()Alexander Gordeev2014-04-07
| | | | | | | | | | | | As result of deprecation of MSI-X/MSI enablement functions pci_enable_msix() and pci_enable_msi_block() all drivers using these two interfaces need to be updated to use the new pci_enable_msi_range() or pci_enable_msi_exact() and pci_enable_msix_range() or pci_enable_msix_exact() interfaces. Signed-off-by: Alexander Gordeev <agordeev@redhat.com> Signed-off-by: Jon Mason <jon.mason@intel.com>
* ntb: Split ntb_setup_msix() into separate BWD/SNB routinesAlexander Gordeev2014-04-07
| | | | | | | | | | | | | This is an cleanup effort to make ntb_setup_msix() more readable - use ntb_setup_bwd_msix() to init MSI-Xs on BWD hardware and ntb_setup_snb_msix() - on SNB hardware. Function ntb_setup_snb_msix() also initializes MSI-Xs the way it should has been done - looping pci_enable_msix() until success or failure. Signed-off-by: Alexander Gordeev <agordeev@redhat.com> Signed-off-by: Jon Mason <jon.mason@intel.com>
* ntb: Use pci_msix_vec_count() to obtain number of MSI-XsAlexander Gordeev2014-04-07
| | | | | Signed-off-by: Alexander Gordeev <agordeev@redhat.com> Signed-off-by: Jon Mason <jon.mason@intel.com>
* NTB: Code Style Clean-upJon Mason2014-04-07
| | | | | | Some white space and 80 char overruns corrected. Signed-off-by: Jon Mason <jon.mason@intel.com>
* NTB: client event cleanupJon Mason2014-04-07
| | | | | | Provide a better event interface between the client and transport Signed-off-by: Jon Mason <jon.mason@intel.com>
* ntb: Fix leakage of ntb_device::msix_entries[] arrayAlexander Gordeev2014-04-07
| | | | | Signed-off-by: Alexander Gordeev <agordeev@redhat.com> Signed-off-by: Jon Mason <jon.mason@intel.com>
* NTB: Fix typo in setting one translation registerRoland Dreier2014-04-07
| | | | | | | | | | | | | In the code for Xeon devices in back-to-back mode with xeon_errata_workaround disabled, the downstream device puts the wrong value in SNB_B2B_XLAT_OFFSETL (SNB_MBAR01_DSD_ADDR vs. SNB_MBAR01_USD_ADDR). This was spotted while reading code, since the typo has no practical effect, at least for now: the low 32 bits of both constants are actually identical anyway. However, it's clearer and safer to use the right name. Signed-off-by: Roland Dreier <roland@purestorage.com> Signed-off-by: Jon Mason <jon.mason@intel.com>
* Merge tag 'ntb-3.13' of git://github.com/jonmason/ntbLinus Torvalds2013-11-26
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull non-transparent bridge updates from Jon Mason: "NTB driver bug fixes to address a missed call to pci_enable_msix, NTB-RP Link Up issue, Xeon Doorbell errata workaround, ntb_transport link down race, and correct dmaengine_get/put usage. Also, clean-ups to remove duplicate defines and document a hardware errata. Finally, some changes to improve performance" * tag 'ntb-3.13' of git://github.com/jonmason/ntb: NTB: Disable interrupts and poll under high load NTB: Enable Snoop on Primary Side NTB: Document HW errata NTB: remove duplicate defines NTB: correct dmaengine_get/put usage NTB: Fix ntb_transport link down race ntb: Fix missed call to pci_enable_msix() NTB: Fix NTB-RP Link Up NTB: Xeon Doorbell errata workaround
| * NTB: Disable interrupts and poll under high loadJon Mason2013-11-20
| | | | | | | | | | | | Disable interrupts and poll under high load Signed-off-by: Jon Mason <jon.mason@intel.com>
| * NTB: Enable Snoop on Primary SideJon Mason2013-11-20
| | | | | | | | | | | | | | | | | | | | Enable Snoop from Primary to Secondary side on BAR23 and BAR45 on all TLPs. Previously, Snoop was only enabled from Secondary to Primary side. This can have a performance improvement on some workloads. Also, make the code more obvious about how the link is being enabled. Signed-off-by: Jon Mason <jon.mason@intel.com>
| * NTB: Document HW errataJon Mason2013-11-20
| | | | | | | | | | | | | | Add a comment describing the necessary ordering of modifications to the NTB Limit and Base registers. Signed-off-by: Jon Mason <jon.mason@intel.com>
| * NTB: remove duplicate definesMichael Opdenacker2013-11-20
| | | | | | | | | | | | | | Remove duplicate defines in drivers/ntb/ntb_regs.h Signed-off-by: Michael Opdenacker <michael.opdenacker@free-electrons.com> Signed-off-by: Jon Mason <jon.mason@intel.com>
| * NTB: correct dmaengine_get/put usageJon Mason2013-11-20
| | | | | | | | | | | | | | | | | | dmaengine_get() causes the initialization of the per-cpu channel tables. It needs to be called prior to dma_find_channel(). Initial version by Dan Williams <dan.j.williams@intel.com> Signed-off-by: Jon Mason <jon.mason@intel.com>
| * NTB: Fix ntb_transport link down raceJon Mason2013-11-20
| | | | | | | | | | | | | | | | | | | | | | A WARN_ON is being hit in ntb_qp_link_work due to the NTB transport link being down while the ntb qp link is still active. This is caused by the transport link being brought down prior to the qp link worker thread being terminated. To correct this, shutdown the qp's prior to bringing the transport link down. Also, only call the qp worker thread if it is in interrupt context, otherwise call the function directly. Signed-off-by: Jon Mason <jon.mason@intel.com>
| * ntb: Fix missed call to pci_enable_msix()Alexander Gordeev2013-11-20
| | | | | | | | | | | | | | | | | | | | Current MSI-X enablement code assumes MSI-Xs were successfully allocated in case less than requested vectors were available. That assumption is wrong, since MSI-Xs should be enabled with a repeated call to pci_enable_msix(). This update fixes this. Signed-off-by: Alexander Gordeev <agordeev@redhat.com> Signed-off-by: Jon Mason <jon.mason@intel.com>
| * NTB: Fix NTB-RP Link UpJon Mason2013-11-20
| | | | | | | | | | | | | | | | | | | | The Xeon NTB-RP setup, the transparent side does not get a link up/down interrupt. Since the presence of a NTB device on the transparent side means that we have a NTB link up, we can work around the lack of an interrupt by simply calling the link up function to notify the upper layers. Signed-off-by: Jon Mason <jon.mason@intel.com>
| * NTB: Xeon Doorbell errata workaroundJon Mason2013-11-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Modifications to the 14th bit of the B2BDOORBELL register will not be mirrored to the remote system due to a hardware issue. To get around the issue, shrink the number of available doorbell bits by 1. The max number of doorbells was being used as a way to referencing the Link Doorbell bit. Since this would no longer work, the driver must now explicitly reference that bit. This does not affect the xeon_errata_workaround case, as it is not using the b2bdoorbell register. Signed-off-by: Jon Mason <jon.mason@intel.com>
* | dmaengine: remove DMA unmap flagsBartlomiej Zolnierkiewicz2013-11-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove no longer needed DMA unmap flags: - DMA_COMPL_SKIP_SRC_UNMAP - DMA_COMPL_SKIP_DEST_UNMAP - DMA_COMPL_SRC_UNMAP_SINGLE - DMA_COMPL_DEST_UNMAP_SINGLE Cc: Vinod Koul <vinod.koul@intel.com> Cc: Tomasz Figa <t.figa@samsung.com> Cc: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Jon Mason <jon.mason@intel.com> Acked-by: Mark Brown <broonie@linaro.org> [djbw: clean up straggling skip unmap flags in ntb] Signed-off-by: Dan Williams <dan.j.williams@intel.com>
* | NTB: convert to dmaengine_unmap_dataBartlomiej Zolnierkiewicz2013-11-14
|/ | | | | | | | | | | | | Use the generic unmap object to unmap dma buffers. Cc: Vinod Koul <vinod.koul@intel.com> Cc: Tomasz Figa <t.figa@samsung.com> Cc: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Jon Mason <jon.mason@intel.com> [djbw: fix up unmap len, and GFP flags] Signed-off-by: Dan Williams <dan.j.williams@intel.com>
* ntb: clean up unnecessary MSI/MSI-X capability findYijing Wang2013-09-05
| | | | | | | | | | | | PCI core will initialize device MSI/MSI-X capability in pci_msi_init_pci_dev(). So device driver should use pci_dev->msi_cap/msix_cap to determine whether the device support MSI/MSI-X instead of using pci_find_capability(pci_dev, PCI_CAP_ID_MSI/MSIX). Access to PCIe device config space again will consume more time. Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Jon Mason <jon.mason@intel.com>
* NTB: Update VersionJon Mason2013-09-05
| | | | | | Update NTB version to 1.0 Signed-off-by: Jon Mason <jon.mason@intel.com>
* NTB: Comment FixJon Mason2013-09-05
| | | | | | | Add "data" ntb_register_db_callback parameter description comment and correct poor spelling. Signed-off-by: Jon Mason <jon.mason@intel.com>
* NTB: Remove unused variableJon Mason2013-09-05
| | | | | | Remove unused pci_dev variable from ntb_transport_free() Signed-off-by: Jon Mason <jon.mason@intel.com>
* NTB: Remove References of non-B2B BWD HWJon Mason2013-09-05
| | | | | | | NTB-RP is not a supported configuration on BWD hardware. Remove the code attempting to set it up. Signed-off-by: Jon Mason <jon.mason@intel.com>
* NTB: NTB-RP supportJon Mason2013-09-05
| | | | | | | | | | | | | | | | | | | | | | Add support for Non-Transparent Bridge connected to a PCI-E Root Port on the remote system (also known as NTB-RP mode). This allows for a NTB enabled system to be connected to a non-NTB enabled system/slot. Modifications to the registers and BARs/MWs on the Secondary side by the remote system are reflected into registers on the Primary side for the local system. Similarly, modifications of registers and BARs/MWs on Primary side by the local system are reflected into registers on the Secondary side for the Remote System. This allows communication between the 2 sides via these registers and BARs/MWs. Note: there is not a fix for the Xeon Errata (that was already worked around in NTB-B2B mode) for NTB-RP mode. Due to this limitation, NTB-RP will not work on the Secondary side with the Xeon Errata workaround enabled. To get around this, disable the workaround via the xeon_errata_workaround=0 modparm. However, this can cause the hang described in the errata. Signed-off-by: Jon Mason <jon.mason@intel.com>
* NTB: Rename Variables for NTB-RPJon Mason2013-09-05
| | | | | | | | | Many variable names in the NTB driver refer to the primary or secondary side. However, these variables will be used to access the reverse case when in NTB-RP mode. Make these names more generic in anticipation of NTB-RP support. Signed-off-by: Jon Mason <jon.mason@intel.com>
* NTB: Use DMA Engine to Transmit and ReceiveJon Mason2013-09-05
| | | | | | | | | Allocate and use a DMA engine channel to transmit and receive data over NTB. If none is allocated, fall back to using the CPU to transfer data. Signed-off-by: Jon Mason <jon.mason@intel.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
* NTB: Enable 32bit SupportJon Mason2013-09-03
| | | | | | | | Correct the issues on NTB that prevented it from working on x86_32 and modify the Kconfig to allow it to be permitted to be used in that environment as well. Signed-off-by: Jon Mason <jon.mason@intel.com>
* NTB: Update Device IDsJon Mason2013-09-03
| | | | | | | | | | | | | | | | | Add support for new Intel NTB devices on upcoming Xeon hardware. Since the Xeon hardware design is already in place in the driver, all that is needed are the new device ids. Remove the device IDs for NTB devs running in Transparent Bridge mode, as this driver is not being used for those devices. Rename the device IDs for NTB devs running in NTB-RP mode to better identify their usage model. "PS" to denote the Primary Side of NTB, and "SS" to denote the secondary side. The primary side is the interface exposed to the local system, and the secondary side is the interface exposed to the remote system. Signed-off-by: Jon Mason <jon.mason@intel.com>
* NTB: BWD Link RecoveryJon Mason2013-09-03
| | | | | | | | | | | | | | | The BWD NTB device will drop the link if an error is encountered on the point-to-point PCI bridge. The link will stay down until all errors are cleared and the link is re-established. On link down, check to see if the error is detected, if so do the necessary housekeeping to try and recover from the error and reestablish the link. There is a potential race between the 2 NTB devices recovering at the same time. If the times are synchronized, the link will not recover and the driver will be stuck in this loop forever. Add a random interval to the recovery time to prevent this race. Signed-off-by: Jon Mason <jon.mason@intel.com>
* NTB: Xeon Errata WorkaroundJon Mason2013-09-03
| | | | | | | | | | | | | | | | | | | | There is a Xeon hardware errata related to writes to SDOORBELL or B2BDOORBELL in conjunction with inbound access to NTB MMIO Space, which may hang the system. To workaround this issue, use one of the memory windows to access the interrupt and scratch pad registers on the remote system. This bypasses the issue, but removes one of the memory windows from use by the transport. This reduction of MWs necessitates adding some logic to determine the number of available MWs. Since some NTB usage methodologies may have unidirectional traffic, the ability to disable the workaround via modparm has been added. See BF113 in http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/xeon-c5500-c3500-spec-update.pdf See BT119 in http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/xeon-e5-family-spec-update.pdf Signed-off-by: Jon Mason <jon.mason@intel.com>
* NTB: Correct debugfs to work with more than 1 NTB DeviceJon Mason2013-09-03
| | | | | | | | | | | | Debugfs was setup in NTB to only have a single debugfs directory. This resulted in the leaking of debugfs directories and files when multiple NTB devices were present, due to each device stomping on the variables containing the previous device's values (thus preventing them from being freed on cleanup). Correct this by creating a secondary directory of the PCI BDF for each device present, and nesting the previously existing information in those directories. Signed-off-by: Jon Mason <jon.mason@intel.com>
* NTB: Correct USD/DSD IdentificationJon Mason2013-09-03
| | | | | | | | Due to ambiguous documentation, the USD/DSD identification is backward when compared to the setting in BIOS. Correct the bits to match the BIOS setting. Signed-off-by: Jon Mason <jon.mason@intel.com>
* NTB: Correct Number of Scratch Pad RegistersJon Mason2013-09-03
| | | | | | | | The NTB Xeon hardware has 16 scratch pad registers and 16 back-to-back scratch pad registers. Correct the #define to represent this and update the variable names to reflect their usage. Signed-off-by: Jon Mason <jon.mason@intel.com>
* NTB: Add Error Handling in ntb_device_setupJon Mason2013-09-03
| | | | | | | | | | | If an error is encountered in ntb_device_setup, it is possible that the spci_cmd isn't populated. Writes to the offset can result in a NULL pointer dereference. This issue is easily encountered by running in NTB-RP mode, as it currently is not supported and will generate an error. To get around this issue, return if an error is encountered prior to attempting to write to the spci_cmd offset. Signed-off-by: Jon Mason <jon.mason@intel.com>
* NTB: Multiple NTB client fixJon Mason2013-05-15
| | | | | | | | | Fix issue with adding multiple ntb client devices to the ntb virtual bus. Previously, multiple devices would be added with the same name, resulting in crashes. To get around this issue, add a unique number to the device when it is added. Signed-off-by: Jon Mason <jon.mason@intel.com>
* NTB: memcpy lockup workaroundJon Mason2013-05-15
| | | | | | | | The system will appear to lockup for long periods of time due to the NTB driver spending too much time in memcpy. Avoid this by reducing the number of packets that can be serviced on a given interrupt. Signed-off-by: Jon Mason <jon.mason@intel.com>
* NTB: Correctly handle receive buffers of the minimal sizeJon Mason2013-05-15
| | | | | | | | | The ring logic of the NTB receive buffer/transmit memory window requires there to be at least 2 payload sized allotments. For the minimal size case, split the buffer into two and set the transport_mtu to the appropriate size. Signed-off-by: Jon Mason <jon.mason@intel.com>
* NTB: reset tx_index on link toggleJon Mason2013-05-15
| | | | | | | | | If the NTB link toggles, the driver could stop receiving due to the tx_index not being set to 0 on the transmitting size on a link-up event. This is due to the driver expecting the incoming data to start at the beginning of the receive buffer and not at a random place. Signed-off-by: Jon Mason <jon.mason@intel.com>
* NTB: Link toggle memory leakJon Mason2013-05-15
| | | | | | | | | | Each link-up will allocate a new NTB receive buffer when the NTB properties are negotiated with the remote system. These allocations did not check for existing buffers and thus did not free them. Now, the driver will check for an existing buffer and free it if not of the correct size, before trying to alloc a new one. Signed-off-by: Jon Mason <jon.mason@intel.com>
* NTB: Handle 64bit BAR sizesJon Mason2013-05-15
| | | | | | | | | | 64bit BAR sizes are permissible with an NTB device. To support them various modifications and clean-ups were required, most significantly using 2 32bit scratch pad registers for each BAR. Also, modify the driver to allow more than 2 Memory Windows. Signed-off-by: Jon Mason <jon.mason@intel.com>
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