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path: root/arch/arm/mach-omap2/clock34xx.h
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* OMAP2/3 GPTIMER: allow system tick GPTIMER to be changed in board-*.c filesPaul Walmsley2009-04-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a function omap2_gp_clockevent_set_gptimer() for board-*.c files to use in .init_irq functions to configure the system tick GPTIMER. Practical choices at this point are GPTIMER1 or GPTIMER12. Both of these timers are in the WKUP powerdomain, and so are unaffected by chip power management. GPTIMER1 can use sys_clk as a source, for applications where a high-resolution timer is more important than power management. GPTIMER12 has the special property that it has the secure 32kHz oscillator as its source clock, which may be less prone to glitches than the off-chip 32kHz oscillator. But on HS devices, it may not be available for Linux use. It appears that most boards are fine with GPTIMER1, but BeagleBoard should use GPTIMER12 when using a 32KiHz timer source, due to hardware bugs in revisions B4 and below. Modify board-omap3beagle.c to use GPTIMER12. This patch originally used a Kbuild config option to select the GPTIMER, but was changed to allow this to be specified in board-*.c files, per Tony's request. Kalle Vallo <kalle.valo@nokia.com> found a bug in an earlier version of this patch - thanks Kalle. Tested on Beagle rev B4 ES2.1, with and without CONFIG_OMAP_32K_TIMER, and 3430SDP. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Cc: Kalle Valo <kalle.valo@nokia.com>
* OMAP3: clock: Camera module doesn't have IDLEST bitSergio Aguirre2009-04-23
| | | | | | | | | | | This patch avoids waiting for the camera module to become ready, since it doesn't have IDLEST bit. Based on a earlier hack done by Paul Walmsley on Sep 9 2008 on linux-omap tree. Signed-off-by: Sergio Aguirre <saaguirre@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* [ARM] omap: add support for bypassing DPLLsRussell King2009-02-19
| | | | | | | | | | | | | | | | | | | | This roughly corresponds with OMAP commits: 7d06c48, 3241b19, 88b5d9b, 18a5500, 9c909ac, 5c6497b, 8b1f0bd, 2ac1da8. For both OMAP2 and OMAP3, we note the reference and bypass clocks in the DPLL data structure. Whenever we modify the DPLL rate, we first ensure that both the reference and bypass clocks are enabled. Then, we decide whether to use the reference and DPLL, or the bypass clock if the desired rate is identical to the bypass rate, and program the DPLL appropriately. Finally, we update the clock's parent, and then disable the unused clocks. This keeps the parents correctly balanced, and more importantly ensures that the bypass clock is running whenever we reprogram the DPLL. This is especially important because the procedure for reprogramming the DPLL involves switching to the bypass clock. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] omap: arrange for clock recalc methods to return the rateRussell King2009-02-14
| | | | | | | | | | | | | linux-omap source commit 33d000c99ee393fe2042f93e8422f94976d276ce introduces a way to "dry run" clock changes before they're committed. However, this involves putting logic to handle this into each and every recalc function, and unfortunately due to the caching, led to some bugs. Solve both of issues by making the recalc methods always return the clock rate for the clock, which the caller decides what to do with. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] omap: create a proper tree of clocksRussell King2009-02-08
| | | | | | | | | | | Traditionally, we've tracked the parent/child relationships between clk structures by setting the child's parent member to point at the upstream clock. As a result, when decending the tree, we have had to scan all clocks to find the children. Avoid this wasteful scanning by keeping a list of the clock's children. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] OMAP3 clock: add omap3_core_dpll_m2_set_rate()Paul Walmsley2009-02-08
| | | | | | | | | | | | | | | | | | | Add the omap3_core_dpll_m2_set_rate() function to the OMAP3 clock code, which calls into the SRAM function omap3_sram_configure_core_dpll() to change the CORE DPLL M2 divider. (SRAM code is necessary since rate changes on clocks upstream from the SDRC can glitch SDRAM accesses.) Use this function for the set_rate function pointer in the dpll3_m2_ck struct clk. With this function in place, PM/OPP code should be able to alter SDRAM speed via code similar to: clk_set_rate(&dpll3_m2_ck, target_rate). linux-omap source commit is 7f8b2b0f4fe52238c67d79dedcd2794dcef4dddd. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] OMAP3 clock: avoid invalid FREQSEL values during DPLL rate roundingPaul Walmsley2009-02-08
| | | | | | | | | | | | | | | | | | | | | | | | | | The DPLL FREQSEL jitter correction bits are set based on a table in the 34xx TRM, Table 4-38, according to the DPLL's internal clock frequency "Fint." Several Fint frequency ranges are missing from this table. Previously, we allowed these Fint frequency ranges to be selected in the rate rounding code, but did not change the FREQSEL bits. Correspondence with the OMAP hardware team indicates that Fint values not in the table should not be used. So, prevent them from being selected during DPLL rate rounding. This removes warnings and also can prevent the chip from locking up. The first pass through the rate rounding code will update the DPLL max and min dividers appropriately, so later rate rounding passes will run faster than the first. Peter de Schrijver <peter.de-schrijver@nokia.com> put up with several test cycles of this patch - thanks Peter. linux-omap source commit is f9c1b82f55b60fc39eaa6e7aa1fbe380c0ffe2e9. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Peter de Schrijver <peter.de-schrijver@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] OMAP3 clock: convert dpll_data.idlest_bit to idlest_maskPaul Walmsley2009-02-08
| | | | | | | | | | | | | | Convert struct dpll_data.idlest_bit field to idlest_mask. Needed since OMAP2 uses two bits for DPLL IDLEST rather than one. While here, add the missing idlest_* fields for DPLL3. linux-omap source commits are 25bab0f176b0a97be18a1b38153f266c3a155784 and b0f7fd17db2aaf8e6e9a2732ae3f4de0874db01c. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] OMAP3 clock: DPLL{1,2}_FCLK clksel can divide by 4Paul Walmsley2009-02-08
| | | | | | | | | | | | OMAP34xx ES2 TRM Delta G to H states that the divider for DPLL1_FCLK and DPLL2_FCLK can divide by 4 in addition to dividing by 1 and 2. Encode this into the OMAP3 clock framework. linux-omap source commit is 050684c18f2ea0b08fdd5233a0cd3c7f96e00a0e. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] OMAP3 PRCM: add DPLL1-5 powerdomains, clockdomains; mark clocksPaul Walmsley2009-02-08
| | | | | | | | | | | | | | Each DPLL exists in its own powerdomain (cf 34xx TRM figure 4-18) and clockdomain; so, create powerdomain and clockdomain structures for them. Mark each DPLL clock as belonging to their respective DPLL clockdomain. cf. 34xx TRM Table 4-27 (among other references). linux-omap source commits are acdb615850b9b4f7d1ab68133a16be8c8c0e7419 and a8798a48f33e9268dcc7f30a4b4a3ce4220fe0c9. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] OMAP3 clock: move sys_clkout2 clk to core_clkdmPaul Walmsley2009-02-08
| | | | | | | | | | | sys_clkout2 belongs in the core_clkdm (3430 TRM section 4.7.2.2). It's not clear whether it actually is in the CORE clockdomain, or whether it is technically in a different clockdomain; but this is closer to reality than the present configuration. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] OMAP: Make dpll4_m4_ck programmable with clk_set_rate()Paul Walmsley2009-02-08
| | | | | | | | | | | | | | | | | Filling the set_rate and round_rate fields of dpll4_m4_ck makes this clock programmable through clk_set_rate(). This is needed to give omapfb control over the dss1_alwon_fck rate. This patch includes a fix from Tomi Valkeinen <tomi.valkeinen@nokia.com>. linux-omap source commits are e42218d45afbc3e654e289e021e6b80c657b16c2 and 9d211b761b3cdf7736602ecf7e68f8a298c13278. Signed-off-by: Måns Rullgård <mans@mansr.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] OMAP: Add CSI2 clock struct for handling it with clock APISergio Aguirre2009-02-08
| | | | | | | | | | | Add CSI2 clock struct for handling it with clock API when TI PM is disabled. linux-omap source commit is 8b20f4498928459276bd3366e3381ad595d23432. Signed-off-by: Sergio Aguirre <saaguirre@ti.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] OMAP2: Fix definition of SGX clock register bitsDaniel Stone2009-02-08
| | | | | | | | | | | | | | | The GFX/SGX functional and interface clocks have different masks, for some unknown reason, so split EN_SGX_SHIFT into one each for fclk and iclk. Correct according to the TRM and the far more important 'does this actually work at all?' metric. linux-omap source commit is de1121fdb899f762b9e717f44eaf3fae7c00cd3e. Signed-off-by: Daniel Stone <daniel.stone@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] OMAP3 clock: fix 96MHz clocksPaul Walmsley2009-02-08
| | | | | | | | | | | | | | | | Fix some bugs in the OMAP3 clock tree pertaining to the 96MHz clocks. The 96MHz portion of the clock tree should now have reasonable fidelity to the 34xx TRM Rev I. One remaining question mark: it's not clear exactly which 96MHz source clock the USIM uses. This patch sticks with the previous setting, which seems reasonable. linux-omap source commit is 15c706e8179ce238c3ba70a25846a36b73bd2359. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] OMAP3: move USBHOST SAR handling from clock framework to powerdomain layerPaul Walmsley2009-02-08
| | | | | | | | | | | | | | | | | | Remove usbhost_sar_fclk from the OMAP3 clock framework. The bit that the clock was tweaking doesn't actually enable or disable a clock; it controls whether the hardware will save and restore USBHOST state when the powerdomain changes state. (That happens to coincidentally enable a clock for the duration of the operation, hence the earlier confusion.) In place of the clock, mark the USBHOST powerdomain as supporting hardware save-and-restore functionality. linux-omap source commit is f3ceac86a9d425d101d606d87a5af44afef27179. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] OMAP2/3: Add non-CORE DPLL rate set code and M, N programmingPaul Walmsley2009-02-08
| | | | | | | | | | | | | | | | Add non-CORE DPLL rate set code and M,N programming for OMAP3. Connect it to OMAP34xx DPLLs 1, 2, 4, 5 via the clock framework. You may see some warnings on rate sets from the freqsel code. The table that TI presented in the 3430 TRM Rev F does not cover Fint < 750000, which definitely occurs in practice. However, the lack of this freqsel case does not appear to impair the DPLL rate change. linux-omap source commit is 689fe67c6d1ad8f52f7f7b139a3274b79bf3e784. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] omap: convert OMAP3 to use clkdevRussell King2009-02-08
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] omap: move propagate_rate() calls into generic omap clock codeRussell King2009-02-08
| | | | | | | | | propagate_rate() is recursive, so it makes sense to minimise the amount of stack which is used for each recursion. So, rather than recursing back into it from the ->recalc functions if RATE_PROPAGATES is set, do that test at the higher level. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] omap: don't use clkops_omap2_dflt_wait for non-ICLK/FCLK clocksRussell King2009-02-08
| | | | | | | | | | | | | | | | | The original code in omap2_clk_wait_ready() used to check the low 8 bits to determine whether they were within the FCLKEN or ICLKEN registers. Specifically, the test is satisfied when these offsets are used: CM_FCLKEN, CM_FCLKEN1, CM_CLKEN, OMAP24XX_CM_FCLKEN2, CM_ICLKEN, CM_ICLKEN1, CM_ICLKEN2, CM_ICLKEN3, OMAP24XX_CM_ICLKEN4 OMAP3430_CM_CLKEN_PLL, OMAP3430ES2_CM_CLKEN2 If one of these offsets isn't used, omap2_clk_wait_ready() merely returns without doing anything. So we should use the non-wait clkops version instead and eliminate that conditional. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] omap: eliminate unnecessary conditionals in omap2_clk_wait_readyRussell King2009-02-08
| | | | | | | | | | Rather than employing run-time tests in omap2_clk_wait_ready() to decide whether we need to wait for the clock to become ready, we can set the .ops appropriately. This change deals with the OMAP24xx and OMAP34xx conditionals only. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] omap: add default .ops to all remaining OMAP2 clocksRussell King2009-02-08
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] omap: kill PARENT_CONTROLS_CLOCKRussell King2009-02-08
| | | | | | | | PARENT_CONTROLS_CLOCK just makes enable/disable no-op, and is functionally an alias for ALWAYS_ENABLED. This can be handled in the same way, using clkops_null. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] omap: provide a NULL clock operations structureRussell King2009-02-08
| | | | | | | | ... and use it for clocks which are ALWAYS_ENABLED. These clocks use a non-NULL enable_reg pointer for other purposes (such as selecting clock rates.) Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] omap: introduce clock operations structureRussell King2009-02-02
| | | | | | | Collect up all the common enable/disable clock operation functions into a separate operations structure. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* omap mmc: Add better MMC low-level initTony Lindgren2008-12-10
| | | | | | | | | | | | | | | | | | | | | | This will simplify the MMC low-level init, and make it more flexible to add support for a newer MMC controller in the following patches. The patch rearranges platform data and gets rid of slot vs controller confusion in the old data structures. Also fix device id numbering in the clock code. Some code snippets are based on an earlier patch by Russell King <linux@arm.linux.org.uk>. Cc: Pierre Ossman <drzeus-mmc@drzeus.cx> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP: Enable GPIO debounce clock only when debounce is enabled v3Jouni Hogander2008-12-10
| | | | | | | | | | | | | | | | | | | This patch changes gpio "driver" to enable debounce clock for gpio-bank only when debounce is enabled for some gpio in that bank. Gpio functional clocks are also renamed in clock tree, gpioX_fck -> gpioX_dbck. This patch triggers problem with gpio wake-up and Omap3. Gpios in PER domain aren't capable to generate wake-up if PER domain is in sleep state. For this iopad wake-up should be used and needed pad configuration should be done. Enabling iopad wake-up for gpio pads is left for bootloader or omap mux configuration in kernel. Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP2: Clock: Combine 34xx l3_icks and l4_icksHögander Jouni2008-08-19
| | | | | | | | | | | | | | | E.g dss_l3_ick and dss_l4_ick have same gating control. Having own clock for both of them causes race condition between enable / disable. This patch combines this kind of clocks and names new clock as <module>_ick. Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP2: Clockdomain: Integrate OMAP3 clocks with clockdomain codePaul Walmsley2008-08-19
| | | | | | | | | | | | | | | | | | | | This patch integrates the OMAP3 clock tree with the clockdomain code. This patch: - marks OMAP34xx clocks with their corresponding clockdomain. - adds code to convert the clockdomain name to a clockdomain pointer in the struct clk during clk_register(). - modifies OMAP2 clock usecounting to call into the clockdomain code when clocks are enabled or disabled. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* [ARM] Move include/asm-arm/arch-* to arch/arm/*/include/machRussell King2008-08-07
| | | | | | This just leaves include/asm-arm/plat-* to deal with. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithmPaul Walmsley2008-07-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a new rate rounding algorithm for DPLL clocks on the OMAP2/3 architecture. For a desired DPLL target rate, there may be several multiplier/divider (M, N) values which will generate a sufficiently close rate. Lower N values result in greater power economy. However, lower N values can cause the difference between the rounded rate and the target rate ("rate error") to be larger than it would be with a higher N. This can cause downstream devices to run more slowly than they otherwise would. This DPLL rate rounding algorithm: - attempts to find the lowest possible N (DPLL divider) to reach the target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>, lower N values save more power than higher N values). - allows developers to set an upper bound on the error between the rounded rate and the desired target rate ("rate tolerance"), so an appropriate balance between rate fidelity and power savings can be set. This maximum rate error tolerance is set via omap2_set_dpll_rate_tolerance(). - never returns a rounded rate higher than the target rate. The rate rounding algorithm caches the last rounded M, N, and rate computation to avoid rounding the rate twice for each clk_set_rate() call. (This patch does not yet implement set_rate for DPLLs; that follows in a future patch.) The algorithm trades execution speed for rate accuracy. It will find the (M, N) set that results in the least rate error, within a specified rate tolerance. It does this by evaluating each divider setting - on OMAP3, this involves 128 steps. Another approach to DPLL rate rounding would be to bail out as soon as a valid rate is found within the rate tolerance, which would trade rate accuracy for execution speed. Alternate implementations welcome. This code is not yet used by the OMAP24XX DPLL clock, since it is currently defined as a composite clock, fusing the DPLL M,N and the M2 output divider. This patch also renames the existing OMAP24xx DPLL programming functions to highlight that they program both the DPLL and the DPLL's output multiplier. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP2: Clock: Add OMAP3 DPLL autoidle functionsPaul Walmsley2008-07-03
| | | | | | | | | | | | | | | | This patch adds support for DPLL autoidle control to the OMAP3 clock framework. These functions will be used by the noncore DPLL enable and disable code - this is because, according to the CDP code, the DPLL autoidle status must be saved and restored across DPLL lock/bypass/off transitions. N.B.: the CORE DPLL (DPLL3) has three autoidle mode options, rather than just two. This code currently does not support the third option, low-power bypass autoidle. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP: McBSP: Add support for mcbsp on mach-omap2Eduardo Valentin2008-07-03
| | | | | | | | | This patch adds support for mach-omap2 based on current mcbsp platform driver. Signed-off-by: Eduardo Valentin <eduardo.valentin@indt.org.br> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP: Add PARENT_CONTROLS_CLOCK flag to dpll5_m2_ckHögander Jouni2008-05-09
| | | | | | | | | | | | | This patch removes following message on dpll5_m2_ck enable and disable: clock.c: Enable for dpll5_m2_ck without enable code clock: clk_disable called on independent clock dpll5_m2_ck which has no enable_reg Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP: PRCM fixes to ssi clock handlingJouni Högander2008-05-09
| | | | | | | | ssi_l4_ick should have PARENT_CONTROLS_CLOCK flag. ST_SSI_STDBY bit in idlest register cannot be used in omap2_clk_wait_ready Signed-off-by: Jouni Högander <jouni.hogander@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP: Add fuctional clock enabler for iva2Hiroshi DOYU2008-05-09
| | | | | | | | Add fuctional clock enabler for iva2 Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP: Fix 34xx to use correct shift values for gpio2-6 fclksJouni Högander2008-05-09
| | | | | | | | Wrong shift values were used for gpio2-6 fclks (gpt2-6 shift). Signed-off-by: Jouni Högander <jouni.hogander@nokia.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP2: New DPLL clock frameworkRoman Tereshonkov2008-04-14
| | | | | | | | | | | | | | | | | | | These changes is the result of the discussion with Paul Walmsley. His ideas are included into this patch. Remove DPLL output divider handling from DPLLs and CLKOUTX2 clocks, and place it into specific DPLL output divider clocks (e.g., dpll3_m2_clk). omap2_get_dpll_rate() now returns the correct DPLL rate, as represented by the DPLL's CLKOUT output. Also add MPU and IVA2 subsystem clocks, along with high-frequency bypass support. Add support for DPLLs function in locked and bypass clock modes. Signed-off-by: Roman Tereshonkov <roman.tereshonkov@nokia.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP2: Add 34xx clocksPaul Walmsley2008-04-14
This patch defines 34xx clocks. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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