diff options
author | Jouni Högander <jouni.hogander@nokia.com> | 2008-03-28 08:57:50 -0400 |
---|---|---|
committer | Tony Lindgren <tony@atomide.com> | 2008-05-09 13:25:03 -0400 |
commit | c3aa044aa3c70a24b606b9265cba305717ac131a (patch) | |
tree | 267b777f7ee47a22c66d370c30f38f8e28e3cebe /arch/arm/mach-omap2/clock34xx.h | |
parent | ec44dfa866cc9779b83e9eab9efe6f7d48966eb8 (diff) |
ARM: OMAP: Fix 34xx to use correct shift values for gpio2-6 fclks
Wrong shift values were used for gpio2-6 fclks (gpt2-6 shift).
Signed-off-by: Jouni Högander <jouni.hogander@nokia.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock34xx.h')
-rw-r--r-- | arch/arm/mach-omap2/clock34xx.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index cf4644a94b9b..a7281174c6ed 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h | |||
@@ -2344,7 +2344,7 @@ static struct clk gpio6_fck = { | |||
2344 | .name = "gpio6_fck", | 2344 | .name = "gpio6_fck", |
2345 | .parent = &per_32k_alwon_fck, | 2345 | .parent = &per_32k_alwon_fck, |
2346 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2346 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
2347 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, | 2347 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, |
2348 | .flags = CLOCK_IN_OMAP343X, | 2348 | .flags = CLOCK_IN_OMAP343X, |
2349 | .recalc = &followparent_recalc, | 2349 | .recalc = &followparent_recalc, |
2350 | }; | 2350 | }; |
@@ -2353,7 +2353,7 @@ static struct clk gpio5_fck = { | |||
2353 | .name = "gpio5_fck", | 2353 | .name = "gpio5_fck", |
2354 | .parent = &per_32k_alwon_fck, | 2354 | .parent = &per_32k_alwon_fck, |
2355 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2355 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
2356 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, | 2356 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, |
2357 | .flags = CLOCK_IN_OMAP343X, | 2357 | .flags = CLOCK_IN_OMAP343X, |
2358 | .recalc = &followparent_recalc, | 2358 | .recalc = &followparent_recalc, |
2359 | }; | 2359 | }; |
@@ -2362,7 +2362,7 @@ static struct clk gpio4_fck = { | |||
2362 | .name = "gpio4_fck", | 2362 | .name = "gpio4_fck", |
2363 | .parent = &per_32k_alwon_fck, | 2363 | .parent = &per_32k_alwon_fck, |
2364 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2364 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
2365 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, | 2365 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, |
2366 | .flags = CLOCK_IN_OMAP343X, | 2366 | .flags = CLOCK_IN_OMAP343X, |
2367 | .recalc = &followparent_recalc, | 2367 | .recalc = &followparent_recalc, |
2368 | }; | 2368 | }; |
@@ -2371,7 +2371,7 @@ static struct clk gpio3_fck = { | |||
2371 | .name = "gpio3_fck", | 2371 | .name = "gpio3_fck", |
2372 | .parent = &per_32k_alwon_fck, | 2372 | .parent = &per_32k_alwon_fck, |
2373 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2373 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
2374 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, | 2374 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, |
2375 | .flags = CLOCK_IN_OMAP343X, | 2375 | .flags = CLOCK_IN_OMAP343X, |
2376 | .recalc = &followparent_recalc, | 2376 | .recalc = &followparent_recalc, |
2377 | }; | 2377 | }; |
@@ -2380,7 +2380,7 @@ static struct clk gpio2_fck = { | |||
2380 | .name = "gpio2_fck", | 2380 | .name = "gpio2_fck", |
2381 | .parent = &per_32k_alwon_fck, | 2381 | .parent = &per_32k_alwon_fck, |
2382 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2382 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
2383 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, | 2383 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, |
2384 | .flags = CLOCK_IN_OMAP343X, | 2384 | .flags = CLOCK_IN_OMAP343X, |
2385 | .recalc = &followparent_recalc, | 2385 | .recalc = &followparent_recalc, |
2386 | }; | 2386 | }; |