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authorHögander Jouni <jouni.hogander@nokia.com>2008-08-19 04:08:45 -0400
committerTony Lindgren <tony@atomide.com>2008-08-19 04:08:45 -0400
commit5955902fb5c31f6a784ddb7aa16079a2bec588f5 (patch)
treefcc3ce2cbe010a371ff360549234bd8e5dfee1ad /arch/arm/mach-omap2/clock34xx.h
parent333943ba9e1716a3751af82f2dcc7620b83091ed (diff)
ARM: OMAP2: Clock: Combine 34xx l3_icks and l4_icks
E.g dss_l3_ick and dss_l4_ick have same gating control. Having own clock for both of them causes race condition between enable / disable. This patch combines this kind of clocks and names new clock as <module>_ick. Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock34xx.h')
-rw-r--r--arch/arm/mach-omap2/clock34xx.h62
1 files changed, 24 insertions, 38 deletions
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index bb01e2014818..c38a8a09692f 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -1189,27 +1189,34 @@ static const struct clksel gfx_l3_clksel[] = {
1189 { .parent = NULL } 1189 { .parent = NULL }
1190}; 1190};
1191 1191
1192static struct clk gfx_l3_fck = { 1192/* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1193 .name = "gfx_l3_fck", 1193static struct clk gfx_l3_ck = {
1194 .name = "gfx_l3_ck",
1194 .parent = &l3_ick, 1195 .parent = &l3_ick,
1195 .init = &omap2_init_clksel_parent, 1196 .init = &omap2_init_clksel_parent,
1196 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), 1197 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1197 .enable_bit = OMAP_EN_GFX_SHIFT, 1198 .enable_bit = OMAP_EN_GFX_SHIFT,
1199 .flags = CLOCK_IN_OMAP3430ES1,
1200 .recalc = &followparent_recalc,
1201};
1202
1203static struct clk gfx_l3_fck = {
1204 .name = "gfx_l3_fck",
1205 .parent = &gfx_l3_ck,
1206 .init = &omap2_init_clksel_parent,
1198 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), 1207 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1199 .clksel_mask = OMAP_CLKSEL_GFX_MASK, 1208 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1200 .clksel = gfx_l3_clksel, 1209 .clksel = gfx_l3_clksel,
1201 .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES, 1210 .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
1211 PARENT_CONTROLS_CLOCK,
1202 .clkdm_name = "gfx_3430es1_clkdm", 1212 .clkdm_name = "gfx_3430es1_clkdm",
1203 .recalc = &omap2_clksel_recalc, 1213 .recalc = &omap2_clksel_recalc,
1204}; 1214};
1205 1215
1206static struct clk gfx_l3_ick = { 1216static struct clk gfx_l3_ick = {
1207 .name = "gfx_l3_ick", 1217 .name = "gfx_l3_ick",
1208 .parent = &l3_ick, 1218 .parent = &gfx_l3_ck,
1209 .init = &omap2_init_clk_clkdm, 1219 .flags = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1210 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1211 .enable_bit = OMAP_EN_GFX_SHIFT,
1212 .flags = CLOCK_IN_OMAP3430ES1,
1213 .clkdm_name = "gfx_3430es1_clkdm", 1220 .clkdm_name = "gfx_3430es1_clkdm",
1214 .recalc = &followparent_recalc, 1221 .recalc = &followparent_recalc,
1215}; 1222};
@@ -2153,19 +2160,9 @@ static struct clk cam_mclk = {
2153 .recalc = &omap2_clksel_recalc, 2160 .recalc = &omap2_clksel_recalc,
2154}; 2161};
2155 2162
2156static struct clk cam_l3_ick = { 2163static struct clk cam_ick = {
2157 .name = "cam_l3_ick", 2164 /* Handles both L3 and L4 clocks */
2158 .parent = &l3_ick, 2165 .name = "cam_ick",
2159 .init = &omap2_init_clk_clkdm,
2160 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2161 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2162 .flags = CLOCK_IN_OMAP343X,
2163 .clkdm_name = "cam_clkdm",
2164 .recalc = &followparent_recalc,
2165};
2166
2167static struct clk cam_l4_ick = {
2168 .name = "cam_l4_ick",
2169 .parent = &l4_ick, 2166 .parent = &l4_ick,
2170 .init = &omap2_init_clk_clkdm, 2167 .init = &omap2_init_clk_clkdm,
2171 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), 2168 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
@@ -2199,19 +2196,9 @@ static struct clk usbhost_48m_fck = {
2199 .recalc = &followparent_recalc, 2196 .recalc = &followparent_recalc,
2200}; 2197};
2201 2198
2202static struct clk usbhost_l3_ick = { 2199static struct clk usbhost_ick = {
2203 .name = "usbhost_l3_ick", 2200 /* Handles both L3 and L4 clocks */
2204 .parent = &l3_ick, 2201 .name = "usbhost_ick",
2205 .init = &omap2_init_clk_clkdm,
2206 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2207 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2208 .flags = CLOCK_IN_OMAP3430ES2,
2209 .clkdm_name = "usbhost_clkdm",
2210 .recalc = &followparent_recalc,
2211};
2212
2213static struct clk usbhost_l4_ick = {
2214 .name = "usbhost_l4_ick",
2215 .parent = &l4_ick, 2202 .parent = &l4_ick,
2216 .init = &omap2_init_clk_clkdm, 2203 .init = &omap2_init_clk_clkdm,
2217 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), 2204 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
@@ -3093,6 +3080,7 @@ static struct clk *onchip_34xx_clks[] __initdata = {
3093 &l3_ick, 3080 &l3_ick,
3094 &l4_ick, 3081 &l4_ick,
3095 &rm_ick, 3082 &rm_ick,
3083 &gfx_l3_ck,
3096 &gfx_l3_fck, 3084 &gfx_l3_fck,
3097 &gfx_l3_ick, 3085 &gfx_l3_ick,
3098 &gfx_cg1_ck, 3086 &gfx_cg1_ck,
@@ -3174,12 +3162,10 @@ static struct clk *onchip_34xx_clks[] __initdata = {
3174 &dss2_alwon_fck, 3162 &dss2_alwon_fck,
3175 &dss_ick, 3163 &dss_ick,
3176 &cam_mclk, 3164 &cam_mclk,
3177 &cam_l3_ick, 3165 &cam_ick,
3178 &cam_l4_ick,
3179 &usbhost_120m_fck, 3166 &usbhost_120m_fck,
3180 &usbhost_48m_fck, 3167 &usbhost_48m_fck,
3181 &usbhost_l3_ick, 3168 &usbhost_ick,
3182 &usbhost_l4_ick,
3183 &usbhost_sar_fck, 3169 &usbhost_sar_fck,
3184 &usim_fck, 3170 &usim_fck,
3185 &gpt1_fck, 3171 &gpt1_fck,