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into next/soc
From Shawn Guo:
mxs soc changes for 3.9
- A couple of optimization on timer
- Some updates on mxs_defconfig
* tag 'mxs-soc-3.9' of git://git.linaro.org/people/shawnguo/linux-2.6:
ARM: mxs_defconfig: Select CONFIG_DEVTMPFS_MOUNT
ARM: mxs: decrease mxs_clockevent_device.min_delta_ns to 2 clock cycles
ARM: mxs: use apbx bus clock to drive the timers on timrotv2
ARM: mxs: Update mxs_defconfig
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Newer versions of udev (such as 182) requires CONFIG_DEVTMPFS_MOUNT to be
selected, otherwise we get a stuck console:
Starting udev
Starting Bootlog daemon: bootlogd: cannot deduce real console device
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Signed-off-by: Torben Hohn <torbenh@linutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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timer resolution of ~32us is pretty low.
v2 has 32bits resolution, so we have quite some headroom, and
can use the 24MHz clock.
v1 has only 16bits, so we only increase v2.
So we just exchange the timrot clock in imx28.
On imx23 we have timrotv1 and everything stays the same.
Signed-off-by: Torben Hohn <torbenh@linutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Regenerate the mxs_defconfig to match recent kernel using the following
commands:
make mxs_defconfig
make savedefconfig
cp defconfig arch/arm/configs/mxs_defconfig
Then enable these features:
- MTD block access
- UBI and UBIFS
- JFFS2
- EXT2 and EXT4
- AT24 EEPROM support
- Support for most of the SPI flashes
- Support for ethernet PHYs that are usually used on mxs designs
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Add a couple of fixes sent via email (via Stephen/Hiroshi).
* tegra/t114:
ARM: tegra: sort Kconfig selects for Tegra114
ARM: tegra: enable ARCH_REQUIRE_GPIOLIB for Tegra114
ARM: tegra: Fix build error w/ ARCH_TEGRA_114_SOC w/o ARCH_TEGRA_3x_SOC
Signed-off-by: Olof Johansson <olof@lixom.net>
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The Kconfig options selected by ARCH_TEGRA_*_SOC were recently sorted.
Update the newly added ARCH_TEGRA_114_SOC's select statements to match.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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CONFIG_ARCH_TEGRA_114_SOC doesn't currently enable gpiolib, which causes
numerous build problems building a Tegra kernel with only Tegra114
enabled, and not Tegra20 or Tegra30. Enable ARCH_REQUIRE_GPIOLIB to
solve this. However, all Tegra will use gpiolib, so select this option
from ARCH_TEGRA rather than each individual ARCH_TEGRA_*_SOC, to
prevent this problem for any future chips.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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This patch fixes the build error when ARCH_TEGRA_114_SOC is enabled
and ARCH_TEGRA_3x_SOC is disabled.
This provides Tegra114 with its own tegra114_init_early() instead of
making use of tegra30_init_early() so that T114 build doesn't depend
on T3x anymore.
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
From Simon Horman:
Fourth round of Renesas ARM-based SoC changes for v3.9
Register ARM architected timer.
This is preparatory work by Magnus Damm for SoC(s) that use
the ARM architected timer.
* tag 'renesas-soc4-for-v3.9' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Register ARM architected timer
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Register ARM architected timer by default for all mach-shmobile
systems using late timer.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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into next/soc
From Shawn Guo:
imx soc changes for 3.9
- Sort out imx DEBUG_LL uart port selection
- A couple of imx_v6_v7_defconfig updates
* tag 'imx-soc-3.9' of git://git.linaro.org/people/shawnguo/linux-2.6:
ARM: imx_v6_v7_defconfig: enable anatop regulator and snvs rtc
ARM: imx: support DEBUG_LL uart port selection for all i.MX SoCs
ARM: imx: use separated debug uart symbol for imx31 and imx35
ARM: imx_v6_v7_defconfig: Select IPUV3 driver
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Eanble anatop regulator and snvs rtc support which are very useful
for imx6q build.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Extend imx6q DEBUG_LL uart port selection support to cover all i.MX
SoCs. The 'range' of the Kconfig option gets dropped, as users
looking at the option must know the uart number on his board. The
bottom line is that the build system will report an error if an
invalid port number is picked for given SoC.
The header arch/arm/include/debug/imx-uart.h is created to accommodate
all the uart base addresses. And the header will also be used for
other low-level debug facility later.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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It's improper to use combined symbol DEBUG_IMX31_IMX35_UART for
imx31 and imx35, because imx31 has 5 UARTs while imx35 only has 3.
So later when we add UART port selection for DEBUG_IMX31_IMX35_UART,
we will have problem.
Use separated Kconfig options for imx31 and imx35 debug uart selection.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Let IPUV3 driver be built by default.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
From Tony Lindgren:
OMAP PM related updates via Paul Walmsley <paul@pwsan.com>:
Remove some dead OMAP clock and device integration code and data.
Also, clean up the way that the OMAP device integration code blocks
WFI/WFE to use a consistent mechanism, controlled by a data flag.
Several OMAP2+ power management fixes, optimizations, and cleanup.
This series is a prerequisite for the functional powerdomain
conversion series.
* tag 'omap-for-v3.9/pm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: powerdomain: fix whitespace, improve flag comments
ARM: OMAP2+: clockdomain: convert existing atomic usecounts into spinlock-protected shorts/ints
ARM: OMAP2+: clockdomain: work on wkdep/sleepdep functions
ARM: OMAP2xxx: CM: remove autodep handling
ARM: OMAP2+: powerdomain/clockdomain: add a per-powerdomain spinlock
ARM: OMAP2+: PM/powerdomain: move omap_set_pwrdm_state() to powerdomain code
ARM: OMAP2: PM/powerdomain: drop unnecessary pwrdm_wait_transition()
ARM: OMAP2xxx: PM: clean up some crufty powerstate programming code
ARM: OMAP2+: clockdomain: add pwrdm_state_switch() call to clkdm_sleep()
ARM: OMAP2+: powerdomain: fix powerdomain trace integration
ARM: OMAP4: MPUSS PM: remove unnecessary shim functions for powerdomain control
ARM: OMAP3xxx: CPUIdle: optimize __omap3_enter_idle()
ARM: OMAP2420: hwmod data/PM: use hwmod to block WFI when I2C active
ARM: OMAP2+: hwmod: add support for blocking WFI when a device is active
ARM: OMAP3xxx: CPUIdle: simplify the PER next-state code
ARM: OMAP2xxx: powerdomain: core powerdomain missing logic retention states
ARM: OMAP2xxx: clock data: clean up unused null clocks
ARM: OMAP4: clock/hwmod data: remove MODULEMODE entries in mux + gate combos
ARM: OMAP4: clock/hwmod data: start to remove some IP block control "clocks"
ARM: OMAP2+: omap_device: remove obsolete pm_lats and early_device code
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git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.9/pm
Several OMAP2+ power management fixes, optimizations, and cleanup.
This series is a prerequisite for the functional powerdomain
conversion series.
Basic test logs for this branch are here:
http://www.pwsan.com/omap/testlogs/pm_cleanup_fixes_3.9/20130129150017/
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Fix some whitespace problems introduced by commit
da03ce65b5431245b9cd20db3edaaa6b9f5c8dc1 ("OMAP3: powerdomain data:
add voltage domains"). Also, improve the documentation for the struct
powerdomain.flags field.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
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spinlock-protected shorts/ints
The atomic usecounts seem to be confusing, and are no longer needed
since the operations that they are attached to really should take
place under lock. Replace the atomic counters with simple integers,
protected by the enclosing powerdomain spinlock.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
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Split the clkdm_(add|del)_(wk|sleep)dep() functions into lockless and
locking versions -- this will be needed in a subsequent patch. Also,
while here, remove the leading underscore, since these are not
currently static functions. And for functions that have
kerneldoc-style comment blocks, but which are missing the initial
'/**' tag, fix the tag to indicate that they are kerneldoc.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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There's no need to preserve the autodep handling code in
mach-omap2/cm2xxx.c, since no autodeps are defined for these chips.
Hopefully they'll never be needed, but if in some future case they are,
this code can be added back in.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Add a per-powerdomain spinlock. Use that instead of the clockdomain
spinlock. Add pwrdm_lock()/pwrdm_unlock() functions to allow other
code to acquire or release the powerdomain spinlock without reaching
directly into the struct powerdomain.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Jean Pihet <jean.pihet@newoldbits.com>
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Move omap_set_pwrdm_state() from the PM code to the powerdomain code,
and refactor it to split it up into several functions. A subsequent patch
will rename it to conform with the existing powerdomain function names.
This version includes some additional documentation, based on a
suggestion from Jean Pihet. It also modifies omap_set_pwrdm_state()
to not bail out early unless both the powerdomain current power state
and the next power state are equal. (Previously it would terminate
early if the next power state was equal to the target power state,
which was insufficiently rigorous.)
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Jean Pihet <jean.pihet@newoldbits.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Tero Kristo <t-kristo@ti.com>
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Drop an unnecessary pwrdm_wait_transition() from mach-omap2/pm.c -
it's called by the subsequent pwrdm_state_switch().
Also get rid of pwrdm_wait_transition() in the powerdomain code - there's
no longer any need to export this function.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
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Don't attempt to put clockdomains to sleep; this should be handled by the
clock framework. It should be enough to program the next-power-state,
and then let the code in omap_pm_clkdms_setup() deal with the rest.
Start out by programming the MPU and CORE powerdomains to stay ON.
Then control the MPU and CORE powerdomain states directly in
omap2_enter_full_retention() and omap2_enter_mpu_retention(). Not the
most optimal way to do it, but certainly is the most conservative until
OMAP2xxx PM is working again.
Get rid of the open-coded PM_PWSTCTRL_MPU writes in
omap2_enter_mpu_retention(); use the powerdomain code instead.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
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In clkdm_sleep(), the powerdomain should be eligible to switch power
states right after the call to the low-level clockdomain sleep
function. We should have been tracking that with the
pwrdm_state_switch() code, but we weren't, for whatever reason. Fix that.
This resolves the "pwrdm state mismatch(cam_pwrdm) 3 != 0" that appears
during the OMAP4460 Pandaboard-ES PM test, e.g. here:
http://www.pwsan.com/omap/testlogs/test_v3.8-rc5/20130126003323/pm/4460pandaes/4460pandaes_log.txt
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
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Fix the trace in the case a power domain did not hit the desired
state, as reported by Paul Walmsley.
Reported-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Jean Pihet <j-pihet@ti.com>
[paul@pwsan.com: split this fix off from the patch
"ARM: OMAP2+: PM debug: trace the functional power domains states"]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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The OMAP4 MPU subsystem power management code contains several unnecessary
shim functions for powerdomain control; remove them.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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Avoid programming the MPU and CORE powerdomain next-power-state
registers if those powerdomains will never enter low-power states
(e.g., the state that people refer to as "C1").
To avoid making assumptions about CPUIdle states based on their order
in the list, use a flag to mark CPUIdle states that don't enter
powerdomain low-power states.
Avoid a previous-power-state register read on the MPU powerdomain
unless we know that the MPU was supposed to go OFF during the last
state transition. Previous-power-state register reads can be very
expensive, so it's worth avoiding these when possible.
Since the CORE_L3 clockdomain can't go inactive unless the MPU is active,
there's little point blocking autoidle on the CORE_L3 clockdomain in "C1"
state, since we've programmed the MPU clockdomain to stay active.
Remove the unnecessary code.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
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The OMAP3xxx CPUIdle driver contains some code to place a lower bound
on the PER powerdomain's power state. Convert this code to a data-driven
implementation to remove branches and to improve readability.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
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Add the possible logic retention states for the 24xx CORE powerdomain.
Subsequent patches use this data to avoid returning incorrect data, by
skipping reads from register bitfields that don't actually exist.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.9/pm
Remove some dead OMAP clock and device integration code and data.
Also, clean up the way that the OMAP device integration code blocks
WFI/WFE to use a consistent mechanism, controlled by a data flag.
Basic test logs for this branch are here:
http://www.pwsan.com/omap/testlogs/cleanup_a_3.9/20130126014242/
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Use the HWMOD_BLOCK_WFI flag in the hwmod data to prevent the MPU from
entering WFI when the I2C devices are active. No idea why this is needed;
this could certainly bear further investigation if anyone is interested.
The objective here is to remove some custom code from the OMAP24xx PM
code.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
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Apparently, on some OMAPs, the MPU can't be allowed to enter WFI while
certain peripherals are active. It's not clear why, and it's likely
that there is simply some other bug in the driver or integration code.
But since the likelihood that anyone will have the time to track these
problems down in the future seems quite small, we'll provide a
flag, HWMOD_BLOCK_WFI, to mark these issues in the hwmod data.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Remove some clocks that don't appear to be used by anything
and which are not associated with any hardware registers.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
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Convert all DEFINE_OMAP_MUX_GATE() combinations that list MODULEMODE
registers in their gate arguments to DEFINE_OMAP_MUX(), dropping the
MODULEMODE data. This is possible because the MODULEMODE bits control
IP blocks, not clocks; and the hwmod code takes care of IP block
control. Rename these clocks to reflect the original multiplexer name
as specified in the comments. And convert the hwmod data to use the
multiplexer clock name.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Mike Turquette <mturquette@linaro.org>
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Remove some leaf "clocks" that are actually IP block idle control
points, since these should now be handled by the hwmod code.
There are still a few types of MODULEMODE clocks that need to be
cleaned up:
- those still in use by driver or integration code
- those in DEFINE_CLK_OMAP_MUX_GATE() blocks; the gate portion of
these should be removed
A similar process may also be possible on OMAP2/3.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Mike Turquette <mturquette@linaro.org>
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Remove now-obsolete code from arch/arm/mach-omap2/omap_device.c. This
mostly consists of removing the first attempt at device PM latency
handling. This was never really used, has been replaced by the common
dev_pm_qos code, and needs to go away as part of the DT conversion.
Also, the early platform_device creation code has been removed, as it
appears to be unused.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
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Fix build error in board-dt-tegra114.c(next-20130204)
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reported-by: Sami Liedes<sliedes@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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Based on two separate cleanup branches, it's now empty and can be removed.
Signed-off-by: Olof Johansson <olof@lixom.net>
Cc: Stephen Warren <swarren@wwwdotorg.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc
From Stepen Warren:
ARM: tegra: add Tegra114 SoC support
This pull request adds initial support for the Tegra114 SoC, which
integrates a quad-core ARM Cortex-A15 CPU. I'm proud to observe that we
posted the initial versions of these patches before the final official
announcement of this chip.
These patches are enough to boot with a UART-based console, support the
Dalmore and Pluto reference/evaluation boards, instantiate the GPIO and
pinctrl drivers, and enable a cpuidle state. As yet, no clocks or
storage devices are supported, but patches for those will follow shortly.
This pull request is based on (most of) the previous pull request with
tag tegra-for-3.9-soc-cpuidle, followed by a merge of the previous pull
request with tag tegra-for-3.9-scu-base-rework.
* tag 'tegra-for-3.9-soc-t114' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (24 commits)
ARM: DT: tegra114: add pinmux DT entry
ARM: DT: tegra114: add GPIO DT entry
ARM: tegra114: select PINCTRL for Tegra114 SoC
ARM: tegra: add Tegra114 ARM_CPUIDLE_WFI_STATE support
ARM: tegra: Add SMMU entry to Tegra114 DT
ARM: tegra: add AHB entry to Tegra114 DT
ARM: tegra: Add initial support for Tegra114 SoC.
ARM: dt: tegra114: Add new board, Pluto
ARM: dt: tegra114: Add new board, Dalmore
ARM: dt: tegra114: Add new SoC base, Tegra114 SoC
ARM: tegra: fuse: Add chip ID Tegra114 0x35
ARM: OMAP: Make use of available scu_a9_get_base() interface
ARM: tegra: Skip scu_enable(scu_base) if not Cortex A9
ARM: Add API to detect SCU base address from CP15
ARM: tegra: Use DT /cpu node to detect number of CPU core
ARM: tegra: Add CPU nodes to Tegra30 device tree
ARM: tegra: Add CPU nodes to Tegra20 device tree
ARM: perf: simplify __hw_perf_event_init err handling
ARM: perf: remove unnecessary checks for idx < 0
ARM: perf: handle armpmu_register failing
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Remove/add conflict in arch/arm/mach-tegra/common.c resolved.
Remove/remove conflict in arch/arm/mach-tegra/platsmp.c. Leave the empty
stub function for now since removing it in the merge commit is confusing;
will be cleaned up in a separate commit. # # It looks like you may be
committing a merge. # If this is not correct, please remove the file #
.git/MERGE_HEAD # and try again.
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Add DT entry for pinmux and drive configuration addresses.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Tegra114 has the GPIO controllers with 8 GPIO bank and each bank
supports 32 pins.
Add DT entry for GPIO controller. Tegra114 GPIO controller is
compatible with Tegra30 GPIO controller driver.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Select PINCTRL and PINCTRL_TEGRA114 for enabling Tegra114 pincontrol
driver for Tegra114 SoC.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Adding the generic ARM_CPUIDLE_WFI_STATE support for Tegra114.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Add SMMU entry.
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Add AHB entry.
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Add new Tegra 114 SoC support.
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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