ARM: OMAP4: clock/hwmod data: start to remove some IP block control "clocks"

Remove some leaf "clocks" that are actually IP block idle control
points, since these should now be handled by the hwmod code.

There are still a few types of MODULEMODE clocks that need to be
cleaned up:

- those still in use by driver or integration code

- those in DEFINE_CLK_OMAP_MUX_GATE() blocks; the gate portion of
  these should be removed

A similar process may also be possible on OMAP2/3.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Mike Turquette <mturquette@linaro.org>

2 files changed, 34 insertions, 315 deletions

diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
index a2cc046b47f4..4c3f5a32694c 100644
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -16,6 +16,11 @@
  * XXX Some of the ES1 clocks have been removed/changed; once support
  * is added for discriminating clocks by ES level, these should be added back
  * in.
+ *
+ * XXX All of the CLK_OMAP_MUX_GATE entries with MODULEMODE registers should
+ * be split into separate mux and gate nodes, then the gates should be removed
+ * (handled by hwmod).  Also all of the other remaining MODULEMODE entries
+ * should be removed once the drivers are updated to use pm_runtime.
  */
 
 #include <linux/kernel.h>
@@ -749,10 +754,6 @@ DEFINE_CLK_GATE(aes2_fck, "l3_div_ck", &l3_div_ck, 0x0,
                 OMAP4430_CM_L4SEC_AES2_CLKCTRL,
                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
 
-DEFINE_CLK_GATE(aess_fck, "aess_fclk", &aess_fclk, 0x0,
-                OMAP4430_CM1_ABE_AESS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
-                0x0, NULL);
-
 DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0,
                 OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
                 OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL);
@@ -774,11 +775,6 @@ DEFINE_CLK_GATE(bandgap_ts_fclk, "div_ts_ck", &div_ts_ck, 0x0,
                 OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
                 0x0, NULL);
 
-DEFINE_CLK_GATE(des3des_fck, "l4_div_ck", &l4_div_ck, 0x0,
-                OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT,
-                0x0, NULL);
-
 static const char *dmic_sync_mux_ck_parents[] = {
         "abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk",
 };
@@ -809,10 +805,6 @@ DEFINE_CLK_OMAP_MUX_GATE(dmic_fck, "abe_clkdm", func_dmic_abe_gfclk_sel,
                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
                          dmic_fck_parents, dmic_fck_ops);
 
-DEFINE_CLK_GATE(dsp_fck, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, 0x0,
-                OMAP4430_CM_TESLA_TESLA_CLKCTRL,
-                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
-
 DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0,
                 OMAP4430_CM_DSS_DSS_CLKCTRL,
                 OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, 0x0, NULL);
@@ -833,78 +825,34 @@ DEFINE_CLK_GATE(dss_fck, "l3_div_ck", &l3_div_ck, 0x0,
                 OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
                 0x0, NULL);
 
-DEFINE_CLK_GATE(efuse_ctrl_cust_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
-                OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(emif1_fck, "ddrphy_ck", &ddrphy_ck, 0x0,
-                OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
-                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(emif2_fck, "ddrphy_ck", &ddrphy_ck, 0x0,
-                OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
-                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
-
 DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
                    OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT,
                    OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
 
-DEFINE_CLK_GATE(fpka_fck, "l4_div_ck", &l4_div_ck, 0x0,
-                OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
 DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
                 OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
                 OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
 
-DEFINE_CLK_GATE(gpio1_ick, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, 0x0,
-                OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
-                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
-
 DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
                 OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
                 0x0, NULL);
 
-DEFINE_CLK_GATE(gpio2_ick, "l4_div_ck", &l4_div_ck, 0x0,
-                OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
-                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
-
 DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
                 OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
                 OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
 
-DEFINE_CLK_GATE(gpio3_ick, "l4_div_ck", &l4_div_ck, 0x0,
-                OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
-                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
-
 DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
                 OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
                 0x0, NULL);
 
-DEFINE_CLK_GATE(gpio4_ick, "l4_div_ck", &l4_div_ck, 0x0,
-                OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
-                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
-
 DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
                 OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
                 0x0, NULL);
 
-DEFINE_CLK_GATE(gpio5_ick, "l4_div_ck", &l4_div_ck, 0x0,
-                OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
-                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
-
 DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
                 OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
                 0x0, NULL);
 
-DEFINE_CLK_GATE(gpio6_ick, "l4_div_ck", &l4_div_ck, 0x0,
-                OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
-                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpmc_ick, "l3_div_ck", &l3_div_ck, 0x0,
-                OMAP4430_CM_L3_2_GPMC_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
-                0x0, NULL);
-
 static const struct clksel sgx_clk_mux_sel[] = {
         { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
         { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
@@ -923,87 +871,15 @@ DEFINE_CLK_OMAP_MUX_GATE(gpu_fck, "l3_gfx_clkdm", sgx_clk_mux_sel,
                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
                          gpu_fck_parents, dmic_fck_ops);
 
-DEFINE_CLK_GATE(hdq1w_fck, "func_12m_fclk", &func_12m_fclk, 0x0,
-                OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
 DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0,
                    OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT,
                    OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
                    NULL);
 
-DEFINE_CLK_GATE(i2c1_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
-                OMAP4430_CM_L4PER_I2C1_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(i2c2_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
-                OMAP4430_CM_L4PER_I2C2_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(i2c3_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
-                OMAP4430_CM_L4PER_I2C3_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(i2c4_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
-                OMAP4430_CM_L4PER_I2C4_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(ipu_fck, "ducati_clk_mux_ck", &ducati_clk_mux_ck, 0x0,
-                OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
-                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
-
 DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0,
                 OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
                 0x0, NULL);
 
-DEFINE_CLK_GATE(iss_fck, "ducati_clk_mux_ck", &ducati_clk_mux_ck, 0x0,
-                OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
-                0x0, NULL);
-
-DEFINE_CLK_GATE(iva_fck, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, 0x0,
-                OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
-                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(kbd_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
-                OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-static struct clk l3_instr_ick;
-
-static const char *l3_instr_ick_parent_names[] = {
-        "l3_div_ck",
-};
-
-static const struct clk_ops l3_instr_ick_ops = {
-        .enable         = &omap2_dflt_clk_enable,
-        .disable        = &omap2_dflt_clk_disable,
-        .is_enabled     = &omap2_dflt_clk_is_enabled,
-        .init           = &omap2_init_clk_clkdm,
-};
-
-static struct clk_hw_omap l3_instr_ick_hw = {
-        .hw = {
-                .clk = &l3_instr_ick,
-        },
-        .enable_reg     = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
-        .clkdm_name     = "l3_instr_clkdm",
-};
-
-DEFINE_STRUCT_CLK(l3_instr_ick, l3_instr_ick_parent_names, l3_instr_ick_ops);
-
-static struct clk l3_main_3_ick;
-static struct clk_hw_omap l3_main_3_ick_hw = {
-        .hw = {
-                .clk = &l3_main_3_ick,
-        },
-        .enable_reg     = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
-        .clkdm_name     = "l3_instr_clkdm",
-};
-
-DEFINE_STRUCT_CLK(l3_main_3_ick, l3_instr_ick_parent_names, l3_instr_ick_ops);
-
 DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
                OMAP4430_CM1_ABE_MCASP_CLKCTRL,
                OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
@@ -1127,26 +1003,6 @@ DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "l4_per_clkdm", per_mcbsp4_gfclk_sel,
                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
                          mcbsp4_fck_parents, dmic_fck_ops);
 
-DEFINE_CLK_GATE(mcpdm_fck, "pad_clks_ck", &pad_clks_ck, 0x0,
-                OMAP4430_CM1_ABE_PDM_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
-                0x0, NULL);
-
-DEFINE_CLK_GATE(mcspi1_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
-                OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(mcspi2_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
-                OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(mcspi3_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
-                OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(mcspi4_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
-                OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
 static const struct clksel hsmmc1_fclk_sel[] = {
         { .parent = &func_64m_fclk, .rates = div_1_0_rates },
         { .parent = &func_96m_fclk, .rates = div_1_1_rates },
@@ -1171,51 +1027,10 @@ DEFINE_CLK_OMAP_MUX_GATE(mmc2_fck, "l3_init_clkdm", hsmmc1_fclk_sel,
                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
                          mmc1_fck_parents, dmic_fck_ops);
 
-DEFINE_CLK_GATE(mmc3_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
-                OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(mmc4_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
-                OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(mmc5_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
-                OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0,
-                OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
-                OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(ocp2scp_usb_phy_ick, "l4_div_ck", &l4_div_ck, 0x0,
-                OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
-                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
-
-static struct clk ocp_wp_noc_ick;
-
-static struct clk_hw_omap ocp_wp_noc_ick_hw = {
-        .hw = {
-                .clk = &ocp_wp_noc_ick,
-        },
-        .enable_reg     = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
-        .clkdm_name     = "l3_instr_clkdm",
-};
-
-DEFINE_STRUCT_CLK(ocp_wp_noc_ick, l3_instr_ick_parent_names, l3_instr_ick_ops);
-
-DEFINE_CLK_GATE(rng_ick, "l4_div_ck", &l4_div_ck, 0x0,
-                OMAP4430_CM_L4SEC_RNG_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
-                0x0, NULL);
-
 DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0,
                 OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
 
-DEFINE_CLK_GATE(sl2if_ick, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, 0x0,
-                OMAP4430_CM_IVAHD_SL2_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
-                0x0, NULL);
-
 DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0,
                 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
                 OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL);
@@ -1232,10 +1047,6 @@ DEFINE_CLK_GATE(slimbus1_slimbus_clk, "slimbus_clk", &slimbus_clk, 0x0,
                 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
                 OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL);
 
-DEFINE_CLK_GATE(slimbus1_fck, "ocp_abe_iclk", &ocp_abe_iclk, 0x0,
-                OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
 DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0,
                 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
                 OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL);
@@ -1249,10 +1060,6 @@ DEFINE_CLK_GATE(slimbus2_slimbus_clk, "pad_slimbus_core_clks_ck",
                 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
                 OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL);
 
-DEFINE_CLK_GATE(slimbus2_fck, "l4_div_ck", &l4_div_ck, 0x0,
-                OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
 DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
                 0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
@@ -1364,22 +1171,6 @@ DEFINE_CLK_OMAP_MUX_GATE(timer9_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
                          abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
 
-DEFINE_CLK_GATE(uart1_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
-                OMAP4430_CM_L4PER_UART1_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(uart2_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
-                OMAP4430_CM_L4PER_UART2_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(uart3_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
-                OMAP4430_CM_L4PER_UART3_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(uart4_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
-                OMAP4430_CM_L4PER_UART4_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
 static struct clk usb_host_fs_fck;
 
 static const char *usb_host_fs_fck_parent_names[] = {
@@ -1512,18 +1303,6 @@ DEFINE_CLK_GATE(usim_fclk, "usim_ck", &usim_ck, 0x0,
                 OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT,
                 0x0, NULL);
 
-DEFINE_CLK_GATE(usim_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
-                OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
-                0x0, NULL);
-
-DEFINE_CLK_GATE(wd_timer2_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
-                OMAP4430_CM_WKUP_WDT2_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
-                0x0, NULL);
-
-DEFINE_CLK_GATE(wd_timer3_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
-                OMAP4430_CM1_ABE_WDT3_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
-                0x0, NULL);
-
 /* Remaining optional clocks */
 static const char *pmd_stm_clock_mux_ck_parents[] = {
         "sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck",
@@ -1774,52 +1553,27 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "syc_clk_div_ck",               &syc_clk_div_ck,        CK_443X),
         CLK(NULL,       "aes1_fck",                     &aes1_fck,      CK_443X),
         CLK(NULL,       "aes2_fck",                     &aes2_fck,      CK_443X),
-        CLK(NULL,       "aess_fck",                     &aess_fck,      CK_443X),
         CLK(NULL,       "bandgap_fclk",                 &bandgap_fclk,  CK_443X),
         CLK(NULL,       "div_ts_ck",                    &div_ts_ck,     CK_446X),
         CLK(NULL,       "bandgap_ts_fclk",              &bandgap_ts_fclk,       CK_446X),
-        CLK(NULL,       "des3des_fck",                  &des3des_fck,   CK_443X),
         CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck,      CK_443X),
         CLK(NULL,       "dmic_fck",                     &dmic_fck,      CK_443X),
-        CLK(NULL,       "dsp_fck",                      &dsp_fck,       CK_443X),
         CLK(NULL,       "dss_sys_clk",                  &dss_sys_clk,   CK_443X),
         CLK(NULL,       "dss_tv_clk",                   &dss_tv_clk,    CK_443X),
         CLK(NULL,       "dss_dss_clk",                  &dss_dss_clk,   CK_443X),
         CLK(NULL,       "dss_48mhz_clk",                &dss_48mhz_clk, CK_443X),
         CLK(NULL,       "dss_fck",                      &dss_fck,       CK_443X),
         CLK("omapdss_dss",      "ick",                  &dss_fck,       CK_443X),
-        CLK(NULL,       "efuse_ctrl_cust_fck",          &efuse_ctrl_cust_fck,   CK_443X),
-        CLK(NULL,       "emif1_fck",                    &emif1_fck,     CK_443X),
-        CLK(NULL,       "emif2_fck",                    &emif2_fck,     CK_443X),
         CLK(NULL,       "fdif_fck",                     &fdif_fck,      CK_443X),
-        CLK(NULL,       "fpka_fck",                     &fpka_fck,      CK_443X),
         CLK(NULL,       "gpio1_dbclk",                  &gpio1_dbclk,   CK_443X),
-        CLK(NULL,       "gpio1_ick",                    &gpio1_ick,     CK_443X),
         CLK(NULL,       "gpio2_dbclk",                  &gpio2_dbclk,   CK_443X),
-        CLK(NULL,       "gpio2_ick",                    &gpio2_ick,     CK_443X),
         CLK(NULL,       "gpio3_dbclk",                  &gpio3_dbclk,   CK_443X),
-        CLK(NULL,       "gpio3_ick",                    &gpio3_ick,     CK_443X),
         CLK(NULL,       "gpio4_dbclk",                  &gpio4_dbclk,   CK_443X),
-        CLK(NULL,       "gpio4_ick",                    &gpio4_ick,     CK_443X),
         CLK(NULL,       "gpio5_dbclk",                  &gpio5_dbclk,   CK_443X),
-        CLK(NULL,       "gpio5_ick",                    &gpio5_ick,     CK_443X),
         CLK(NULL,       "gpio6_dbclk",                  &gpio6_dbclk,   CK_443X),
-        CLK(NULL,       "gpio6_ick",                    &gpio6_ick,     CK_443X),
-        CLK(NULL,       "gpmc_ick",                     &gpmc_ick,      CK_443X),
         CLK(NULL,       "gpu_fck",                      &gpu_fck,       CK_443X),
-        CLK(NULL,       "hdq1w_fck",                    &hdq1w_fck,     CK_443X),
         CLK(NULL,       "hsi_fck",                      &hsi_fck,       CK_443X),
-        CLK(NULL,       "i2c1_fck",                     &i2c1_fck,      CK_443X),
-        CLK(NULL,       "i2c2_fck",                     &i2c2_fck,      CK_443X),
-        CLK(NULL,       "i2c3_fck",                     &i2c3_fck,      CK_443X),
-        CLK(NULL,       "i2c4_fck",                     &i2c4_fck,      CK_443X),
-        CLK(NULL,       "ipu_fck",                      &ipu_fck,       CK_443X),
         CLK(NULL,       "iss_ctrlclk",                  &iss_ctrlclk,   CK_443X),
-        CLK(NULL,       "iss_fck",                      &iss_fck,       CK_443X),
-        CLK(NULL,       "iva_fck",                      &iva_fck,       CK_443X),
-        CLK(NULL,       "kbd_fck",                      &kbd_fck,       CK_443X),
-        CLK(NULL,       "l3_instr_ick",                 &l3_instr_ick,  CK_443X),
-        CLK(NULL,       "l3_main_3_ick",                &l3_main_3_ick, CK_443X),
         CLK(NULL,       "mcasp_sync_mux_ck",            &mcasp_sync_mux_ck,     CK_443X),
         CLK(NULL,       "mcasp_fck",                    &mcasp_fck,     CK_443X),
         CLK(NULL,       "mcbsp1_sync_mux_ck",           &mcbsp1_sync_mux_ck,    CK_443X),
@@ -1830,32 +1584,16 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "mcbsp3_fck",                   &mcbsp3_fck,    CK_443X),
         CLK(NULL,       "mcbsp4_sync_mux_ck",           &mcbsp4_sync_mux_ck,    CK_443X),
         CLK(NULL,       "mcbsp4_fck",                   &mcbsp4_fck,    CK_443X),
-        CLK(NULL,       "mcpdm_fck",                    &mcpdm_fck,     CK_443X),
-        CLK(NULL,       "mcspi1_fck",                   &mcspi1_fck,    CK_443X),
-        CLK(NULL,       "mcspi2_fck",                   &mcspi2_fck,    CK_443X),
-        CLK(NULL,       "mcspi3_fck",                   &mcspi3_fck,    CK_443X),
-        CLK(NULL,       "mcspi4_fck",                   &mcspi4_fck,    CK_443X),
         CLK(NULL,       "mmc1_fck",                     &mmc1_fck,      CK_443X),
         CLK(NULL,       "mmc2_fck",                     &mmc2_fck,      CK_443X),
-        CLK(NULL,       "mmc3_fck",                     &mmc3_fck,      CK_443X),
-        CLK(NULL,       "mmc4_fck",                     &mmc4_fck,      CK_443X),
-        CLK(NULL,       "mmc5_fck",                     &mmc5_fck,      CK_443X),
-        CLK(NULL,       "ocp2scp_usb_phy_phy_48m",      &ocp2scp_usb_phy_phy_48m,       CK_443X),
-        CLK(NULL,       "ocp2scp_usb_phy_ick",          &ocp2scp_usb_phy_ick,   CK_443X),
-        CLK(NULL,       "ocp_wp_noc_ick",               &ocp_wp_noc_ick,        CK_443X),
-        CLK(NULL,       "rng_ick",                      &rng_ick,       CK_443X),
-        CLK("omap_rng", "ick",                          &rng_ick,       CK_443X),
         CLK(NULL,       "sha2md5_fck",                  &sha2md5_fck,   CK_443X),
-        CLK(NULL,       "sl2if_ick",                    &sl2if_ick,     CK_443X),
         CLK(NULL,       "slimbus1_fclk_1",              &slimbus1_fclk_1,       CK_443X),
         CLK(NULL,       "slimbus1_fclk_0",              &slimbus1_fclk_0,       CK_443X),
         CLK(NULL,       "slimbus1_fclk_2",              &slimbus1_fclk_2,       CK_443X),
         CLK(NULL,       "slimbus1_slimbus_clk",         &slimbus1_slimbus_clk,  CK_443X),
-        CLK(NULL,       "slimbus1_fck",                 &slimbus1_fck,  CK_443X),
         CLK(NULL,       "slimbus2_fclk_1",              &slimbus2_fclk_1,       CK_443X),
         CLK(NULL,       "slimbus2_fclk_0",              &slimbus2_fclk_0,       CK_443X),
         CLK(NULL,       "slimbus2_slimbus_clk",         &slimbus2_slimbus_clk,  CK_443X),
-        CLK(NULL,       "slimbus2_fck",                 &slimbus2_fck,  CK_443X),
         CLK(NULL,       "smartreflex_core_fck",         &smartreflex_core_fck,  CK_443X),
         CLK(NULL,       "smartreflex_iva_fck",          &smartreflex_iva_fck,   CK_443X),
         CLK(NULL,       "smartreflex_mpu_fck",          &smartreflex_mpu_fck,   CK_443X),
@@ -1870,10 +1608,6 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "timer7_fck",                   &timer7_fck,    CK_443X),
         CLK(NULL,       "timer8_fck",                   &timer8_fck,    CK_443X),
         CLK(NULL,       "timer9_fck",                   &timer9_fck,    CK_443X),
-        CLK(NULL,       "uart1_fck",                    &uart1_fck,     CK_443X),
-        CLK(NULL,       "uart2_fck",                    &uart2_fck,     CK_443X),
-        CLK(NULL,       "uart3_fck",                    &uart3_fck,     CK_443X),
-        CLK(NULL,       "uart4_fck",                    &uart4_fck,     CK_443X),
         CLK(NULL,       "usb_host_fs_fck",              &usb_host_fs_fck,       CK_443X),
         CLK("usbhs_omap",       "fs_fck",               &usb_host_fs_fck,       CK_443X),
         CLK(NULL,       "utmi_p1_gfclk",                &utmi_p1_gfclk, CK_443X),
@@ -1901,9 +1635,6 @@ static struct omap_clk omap44xx_clks[] = {
         CLK("usbhs_tll",        "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
         CLK(NULL,       "usim_ck",                      &usim_ck,       CK_443X),
         CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
-        CLK(NULL,       "usim_fck",                     &usim_fck,      CK_443X),
-        CLK(NULL,       "wd_timer2_fck",                &wd_timer2_fck, CK_443X),
-        CLK(NULL,       "wd_timer3_fck",                &wd_timer3_fck, CK_443X),
         CLK(NULL,       "pmd_stm_clock_mux_ck",         &pmd_stm_clock_mux_ck,  CK_443X),
         CLK(NULL,       "pmd_trace_clk_mux_ck",         &pmd_trace_clk_mux_ck,  CK_443X),
         CLK(NULL,       "stm_clk_div_ck",               &stm_clk_div_ck,        CK_443X),
@@ -1980,15 +1711,6 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "cpufreq_ck",   &dpll_mpu_ck,   CK_443X),
 };
 
-static const char *enable_init_clks[] = {
-        "emif1_fck",
-        "emif2_fck",
-        "gpmc_ick",
-        "l3_instr_ick",
-        "l3_main_3_ick",
-        "ocp_wp_noc_ick",
-};
-
 int __init omap4xxx_clk_init(void)
 {
         u32 cpu_clkflg;
@@ -2019,9 +1741,6 @@ int __init omap4xxx_clk_init(void)
 
         omap2_clk_disable_autoidle_all();
 
-        omap2_clk_enable_init_clocks(enable_init_clks,
-                                     ARRAY_SIZE(enable_init_clks));
-
         /*
          * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
          * state when turning the ABE clock domain. Workaround this by
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 793f54ac7d14..def97aa9a040 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -1161,7 +1161,7 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
         .class          = &omap44xx_gpio_hwmod_class,
         .clkdm_name     = "l4_wkup_clkdm",
         .mpu_irqs       = omap44xx_gpio1_irqs,
-        .main_clk       = "gpio1_ick",
+        .main_clk       = "l4_wkup_clk_mux_ck",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
@@ -1190,7 +1190,7 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
         .clkdm_name     = "l4_per_clkdm",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
         .mpu_irqs       = omap44xx_gpio2_irqs,
-        .main_clk       = "gpio2_ick",
+        .main_clk       = "l4_div_ck",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
@@ -1219,7 +1219,7 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
         .clkdm_name     = "l4_per_clkdm",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
         .mpu_irqs       = omap44xx_gpio3_irqs,
-        .main_clk       = "gpio3_ick",
+        .main_clk       = "l4_div_ck",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
@@ -1248,7 +1248,7 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
         .clkdm_name     = "l4_per_clkdm",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
         .mpu_irqs       = omap44xx_gpio4_irqs,
-        .main_clk       = "gpio4_ick",
+        .main_clk       = "l4_div_ck",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
@@ -1277,7 +1277,7 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
         .clkdm_name     = "l4_per_clkdm",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
         .mpu_irqs       = omap44xx_gpio5_irqs,
-        .main_clk       = "gpio5_ick",
+        .main_clk       = "l4_div_ck",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
@@ -1306,7 +1306,7 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
         .clkdm_name     = "l4_per_clkdm",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
         .mpu_irqs       = omap44xx_gpio6_irqs,
-        .main_clk       = "gpio6_ick",
+        .main_clk       = "l4_div_ck",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
@@ -1446,7 +1446,7 @@ static struct omap_hwmod omap44xx_hdq1w_hwmod = {
         .clkdm_name     = "l4_per_clkdm",
         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
         .mpu_irqs       = omap44xx_hdq1w_irqs,
-        .main_clk       = "hdq1w_fck",
+        .main_clk       = "func_12m_fclk",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
@@ -1550,7 +1550,7 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
         .mpu_irqs       = omap44xx_i2c1_irqs,
         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
-        .main_clk       = "i2c1_fck",
+        .main_clk       = "func_96m_fclk",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
@@ -1580,7 +1580,7 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
         .mpu_irqs       = omap44xx_i2c2_irqs,
         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
-        .main_clk       = "i2c2_fck",
+        .main_clk       = "func_96m_fclk",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
@@ -1610,7 +1610,7 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
         .mpu_irqs       = omap44xx_i2c3_irqs,
         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
-        .main_clk       = "i2c3_fck",
+        .main_clk       = "func_96m_fclk",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
@@ -1640,7 +1640,7 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = {
         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
         .mpu_irqs       = omap44xx_i2c4_irqs,
         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
-        .main_clk       = "i2c4_fck",
+        .main_clk       = "func_96m_fclk",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
@@ -1743,7 +1743,7 @@ static struct omap_hwmod omap44xx_iss_hwmod = {
         .clkdm_name     = "iss_clkdm",
         .mpu_irqs       = omap44xx_iss_irqs,
         .sdma_reqs      = omap44xx_iss_sdma_reqs,
-        .main_clk       = "iss_fck",
+        .main_clk       = "ducati_clk_mux_ck",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
@@ -1785,7 +1785,7 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
         .mpu_irqs       = omap44xx_iva_irqs,
         .rst_lines      = omap44xx_iva_resets,
         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
-        .main_clk       = "iva_fck",
+        .main_clk       = "dpll_iva_m5x2_ck",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
@@ -1829,7 +1829,7 @@ static struct omap_hwmod omap44xx_kbd_hwmod = {
         .class          = &omap44xx_kbd_hwmod_class,
         .clkdm_name     = "l4_wkup_clkdm",
         .mpu_irqs       = omap44xx_kbd_irqs,
-        .main_clk       = "kbd_fck",
+        .main_clk       = "sys_32k_ck",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
@@ -2140,7 +2140,7 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
         .flags          = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
         .mpu_irqs       = omap44xx_mcpdm_irqs,
         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
-        .main_clk       = "mcpdm_fck",
+        .main_clk       = "pad_clks_ck",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
@@ -2201,7 +2201,7 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
         .clkdm_name     = "l4_per_clkdm",
         .mpu_irqs       = omap44xx_mcspi1_irqs,
         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
-        .main_clk       = "mcspi1_fck",
+        .main_clk       = "func_48m_fclk",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
@@ -2237,7 +2237,7 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
         .clkdm_name     = "l4_per_clkdm",
         .mpu_irqs       = omap44xx_mcspi2_irqs,
         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
-        .main_clk       = "mcspi2_fck",
+        .main_clk       = "func_48m_fclk",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
@@ -2273,7 +2273,7 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
         .clkdm_name     = "l4_per_clkdm",
         .mpu_irqs       = omap44xx_mcspi3_irqs,
         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
-        .main_clk       = "mcspi3_fck",
+        .main_clk       = "func_48m_fclk",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
@@ -2307,7 +2307,7 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = {
         .clkdm_name     = "l4_per_clkdm",
         .mpu_irqs       = omap44xx_mcspi4_irqs,
         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
-        .main_clk       = "mcspi4_fck",
+        .main_clk       = "func_48m_fclk",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
@@ -2420,7 +2420,7 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
         .clkdm_name     = "l4_per_clkdm",
         .mpu_irqs       = omap44xx_mmc3_irqs,
         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
-        .main_clk       = "mmc3_fck",
+        .main_clk       = "func_48m_fclk",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
@@ -2448,7 +2448,7 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
         .clkdm_name     = "l4_per_clkdm",
         .mpu_irqs       = omap44xx_mmc4_irqs,
         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
-        .main_clk       = "mmc4_fck",
+        .main_clk       = "func_48m_fclk",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
@@ -2476,7 +2476,7 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = {
         .clkdm_name     = "l4_per_clkdm",
         .mpu_irqs       = omap44xx_mmc5_irqs,
         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
-        .main_clk       = "mmc5_fck",
+        .main_clk       = "func_48m_fclk",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
@@ -2725,7 +2725,7 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
         .name           = "ocp2scp_usb_phy",
         .class          = &omap44xx_ocp2scp_hwmod_class,
         .clkdm_name     = "l3_init_clkdm",
-        .main_clk       = "ocp2scp_usb_phy_phy_48m",
+        .main_clk       = "func_48m_fclk",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
@@ -3433,7 +3433,7 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
         .clkdm_name     = "l4_per_clkdm",
         .mpu_irqs       = omap44xx_uart1_irqs,
         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
-        .main_clk       = "uart1_fck",
+        .main_clk       = "func_48m_fclk",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
@@ -3461,7 +3461,7 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
         .clkdm_name     = "l4_per_clkdm",
         .mpu_irqs       = omap44xx_uart2_irqs,
         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
-        .main_clk       = "uart2_fck",
+        .main_clk       = "func_48m_fclk",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
@@ -3490,7 +3490,7 @@ static struct omap_hwmod omap44xx_uart3_hwmod = {
         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
         .mpu_irqs       = omap44xx_uart3_irqs,
         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
-        .main_clk       = "uart3_fck",
+        .main_clk       = "func_48m_fclk",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
@@ -3518,7 +3518,7 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
         .clkdm_name     = "l4_per_clkdm",
         .mpu_irqs       = omap44xx_uart4_irqs,
         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
-        .main_clk       = "uart4_fck",
+        .main_clk       = "func_48m_fclk",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
@@ -3797,7 +3797,7 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
         .class          = &omap44xx_wd_timer_hwmod_class,
         .clkdm_name     = "l4_wkup_clkdm",
         .mpu_irqs       = omap44xx_wd_timer2_irqs,
-        .main_clk       = "wd_timer2_fck",
+        .main_clk       = "sys_32k_ck",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
@@ -3818,7 +3818,7 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
         .class          = &omap44xx_wd_timer_hwmod_class,
         .clkdm_name     = "abe_clkdm",
         .mpu_irqs       = omap44xx_wd_timer3_irqs,
-        .main_clk       = "wd_timer3_fck",
+        .main_clk       = "sys_32k_ck",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,