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* drm/nouveau/fbcon: use fence for sync, rather than notifierBen Skeggs2012-05-24
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv98/crypt: non-stub implementation of the engine hooksBen Skeggs2012-05-24
| | | | | | fuc is from pscnv driver. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fifo: turn all fifo modules into engine modulesBen Skeggs2012-05-24
| | | | | | | | | | | | | Been tested on each major revision that's relevant here, but I'm sure there are still bugs waiting to be ironed out. This is a *very* invasive change. There's a couple of pieces left that I don't like much (eg. other engines using fifo_priv for the channel count), but that's an artefact of there being a master channel list still. This is changing, slowly. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50/graph: remove ability to do interrupt-driven context switchingBen Skeggs2012-05-24
| | | | | | We never turn this on, no point maintaining the code for it.. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50: remove manual context unload on context destructionBen Skeggs2012-05-24
| | | | | | PFIFO context destruction triggers this automagically now. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50: remove execution engine context saves on suspendBen Skeggs2012-05-24
| | | | | | Now triggered automagically by the GPU on PFIFO takedown. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50/fifo: use hardware channel kickoff functionalityBen Skeggs2012-05-24
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50/gr: make sure NEXT_TO_CURRENT is executed even if nothing doneBen Skeggs2012-05-24
| | | | | | PFIFO channel kickoff will hang sometimes otherwise. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50/fifo: construct playlist from hw context table stateBen Skeggs2012-05-24
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fifo: remove all the "special" engine hooksBen Skeggs2012-05-24
| | | | | | | | | | | All the places this stuff is actually needed tends to be chipset-specific anyway, so we're able to just inline the register bashing instead. The parts of the common code that still directly touch PFIFO temporarily have conditionals, these will be removed in subsequent commits that will refactor the fifo modules into engine modules like graph/mpeg etc. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fence: fix a race where fence->channel can disappearBen Skeggs2012-05-24
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/bios: fix some shadowing issues, particularly acpiBen Skeggs2012-05-24
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: fix engine context destructor orderingBen Skeggs2012-05-24
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fence: convert to exec engine, and improve channel syncBen Skeggs2012-05-24
| | | | | | | | Now have a somewhat simpler semaphore sync implementation for nv17:nv84, and a switched to using semaphores as fences on nv84+ and making use of the hardware's >= acquire operation. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fence: minor api changes for an upcoming reworkBen Skeggs2012-05-24
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fence: make ttm interfaces wrap ours, not the other way aroundBen Skeggs2012-05-24
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: move flip-related channel setup to software engineBen Skeggs2012-05-24
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: create real execution engine for software object classBen Skeggs2012-05-24
| | | | | | | | | | | Just a cleanup more or less, and to remove the need for special handling of software objects. This removes a heap of documentation on dma/graph object formats. The info is very out of date with our current understanding, and is far better documented in rnndb in envytools git. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nvd0/disp: remove unnecessary sync from flip_nextBen Skeggs2012-05-24
| | | | | | | | | | This shouldn't be necessary, I believe this is just a bit of missed debug code that got left over somehow. Causes flips to be always synced to vblank, regardless of swap interval, which we don't want.. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv04/disp: disable vblank interrupts when disabling displayBen Skeggs2012-05-24
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: base fence timeout on time of emissionMarcin Slusarz2012-05-24
| | | | | | | | | Wait loop can be interrupted by signal, so if signals are raised periodically (e.g. SIGALRM) this loop may never finish. Use emission time as a base for fence timeout. Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv40-50/gr: restructure grctx/prog generationBen Skeggs2012-05-24
| | | | | | | | The conditional definition of the generation helper functions apparently confuses some IDEs.... Reported-by: Marcin Slusarz <marcin.slusarz@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50/disp: fixup error paths in crtc object creationBen Skeggs2012-05-24
| | | | | Reported-by: Marcin Slusarz <marcin.slusarz@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: cleanup after display init failureMarcin Slusarz2012-05-24
| | | | | | | | Depending on exact point of failure, not cleaning would lead to BUG_ONs/oopses in various distant places. Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50: fix ramin heap size for kernel channel tooMarcin Slusarz2012-05-24
| | | | | | | | | Port change from "drm/nouveau: Keep RAMIN heap within the channel" to kernel channel, which has its own ramin heap initialisation. Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com> Cc: Younes Manton <younes.m@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nve0/graph: bump hub2gpc buffer sizeBen Skeggs2012-05-24
| | | | | Reported-by: Christoph Bumiller <e0425955@student.tuwien.ac.at> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: use the same packet header macros as userspaceBen Skeggs2012-05-24
| | | | | | Cosmetic cleanup only. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/bios: allow loading alternate vbios image as firmwareBen Skeggs2012-05-24
| | | | | | Useful for debugging different VBIOS versions. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nve0/ttm: implement buffer moves with weirdo pcopy-on-pgraph methodsBen Skeggs2012-05-24
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50-/fbcon: move 2d class to subchannel 3Ben Skeggs2012-05-24
| | | | | | | Kepler GRAPH has (well, sorta) fixed subchannel<->class assignments, make this match up to keep it happy without trapping. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nve0/gr: initial implementationBen Skeggs2012-05-24
| | | | | | | | | This may, perhaps, get re-merged with nvc0_graph.c at some point. It's still unclear as to how great an idea that'd be. Stay tuned... Completely dependent on firmware blobs from NVIDIA binary driver currently. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nve0/fifo: initial implementationBen Skeggs2012-05-24
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: give a slightly larger pci(e)gart aperture on all chipsetsBen Skeggs2012-05-24
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/pm: some more delays for ddr3 reclockingBen Skeggs2012-05-24
| | | | | | | These numbers from the binary driver's daemon scripts, and fix the transition to perflvl 3 on my T510. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nvc0/pm: very initial mclk freq changeBen Skeggs2012-05-24
| | | | | | Loads of magic missing, this will probably blow up if you try it. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nvd9/pm: oops, fix timing calcBen Skeggs2012-05-24
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nvc0/pm: enable mpll src pll, and calc mpll coefficientsBen Skeggs2012-05-24
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nvc0/pm: start filling in memory reclocking stubsBen Skeggs2012-05-24
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* drm/nva3/pm: another few magic regs, and slightly better 0x004018 handlingBen Skeggs2012-05-24
| | | | | | | | | | | Not entirely convinced 0x004018 transitions are correct yet, but, it's an improvement. The 750MHz value comes from fiddling with the binary driver + coolbits on two different DDR3 NVA8 chipsets (T510 NVS3100M, and NVS300), not a clue where this number comes from. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nva3/pm: initial attempt at handling 111100/111104Ben Skeggs2012-05-24
| | | | | | | Probably not quite right, but this is enough now to make NVS300 reclock between all 3 of its perflvls correctly. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nva3/pm: make pll->pll mode workBen Skeggs2012-05-24
| | | | | | | | | | This probably wants a cleanup, but I'm holding off until I know for sure how the rest of the things that need doing fit together. Tested on NVS300 by hacking up perflvl 1 to require PLL mode, and switching between perflvl 3 and 1. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nva3/pm: attempt to bash a few 0x100200 bits correctlyBen Skeggs2012-05-24
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nva3/pm: begin to restructure memory clock changes + another magicBen Skeggs2012-05-24
| | | | | | | | | | | | | | | | | | | | The binary driver appears to do various bits and pieces of the memory clock frequency change at different times, depending on the particular transition that's occuring. I've attempted to replicate this here for div->pll, pll->div and div->div transitions. With some additional (patches upcoming) magic regs being bashed, this allows me to correctly transition between all 3 perflvls on NVS300. pll->pll transitions will *not* work correctly at the moment, pending me tricking the binary driver into doing one and seeing how to correctly handle it. This patch also handles (hopefully) 0x1110e0, which appears to need changing depending on whether in PLL or divider mode.. Maybe. We'll see. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nva3/pm: more random unknown PFB regsBen Skeggs2012-05-24
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nva3/pm: initial attempt at more magic PFB regsBen Skeggs2012-05-24
| | | | | | | The reg calculation may get moved elsewhere at some point, but lets figure out what exactly we need to do first. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nva3/pm: hook up to ram reclocking helperBen Skeggs2012-05-24
| | | | | | This gets us a start on memory timings. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nva3/pm: introduce more paranoiaBen Skeggs2012-05-24
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/radeon: add static const to the dma-buf ops.Dave Airlie2012-05-23
| | | | | Reported-by: wfg@linux.intel.com Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/i915: make some dmabuf things staticDave Airlie2012-05-23
| | | | | | | these functions and the table can all be static/static const. Reported-by: wfg@linux.intel.com Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm: update ast/cirrus/mgag200 for change in TTM apiDave Airlie2012-05-23
| | | | | | | | New drivers merged after changes were done in prime TTM code. Fix build. Signed-off-by: Dave Airlie <airlied@redhat.com>
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