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authorBen Skeggs <bskeggs@redhat.com>2012-05-02 07:00:20 -0400
committerBen Skeggs <bskeggs@redhat.com>2012-05-24 02:56:13 -0400
commitb355096992e2b4d30bb77173927f45e7f2c12570 (patch)
tree69a580dcf707cf19b8e44dc78c8e74da3de40129
parentc420b2dc8dc3cdd507214f4df5c5f96f08812cbe (diff)
drm/nv98/crypt: non-stub implementation of the engine hooks
fuc is from pscnv driver. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat
-rw-r--r--drivers/gpu/drm/nouveau/nv98_crypt.c166
-rw-r--r--drivers/gpu/drm/nouveau/nv98_crypt.fuc698
-rw-r--r--drivers/gpu/drm/nouveau/nv98_crypt.fuc.h584
3 files changed, 1434 insertions, 14 deletions
diff --git a/drivers/gpu/drm/nouveau/nv98_crypt.c b/drivers/gpu/drm/nouveau/nv98_crypt.c
index db94ff0a9fab..e25e13fb894e 100644
--- a/drivers/gpu/drm/nouveau/nv98_crypt.c
+++ b/drivers/gpu/drm/nouveau/nv98_crypt.c
@@ -23,21 +23,93 @@
23 */ 23 */
24 24
25#include "drmP.h" 25#include "drmP.h"
26
26#include "nouveau_drv.h" 27#include "nouveau_drv.h"
27#include "nouveau_util.h" 28#include "nouveau_util.h"
28#include "nouveau_vm.h" 29#include "nouveau_vm.h"
29#include "nouveau_ramht.h" 30#include "nouveau_ramht.h"
30 31
31struct nv98_crypt_engine { 32#include "nv98_crypt.fuc.h"
33
34struct nv98_crypt_priv {
32 struct nouveau_exec_engine base; 35 struct nouveau_exec_engine base;
33}; 36};
34 37
38struct nv98_crypt_chan {
39 struct nouveau_gpuobj *mem;
40};
41
35static int 42static int
36nv98_crypt_fini(struct drm_device *dev, int engine, bool suspend) 43nv98_crypt_context_new(struct nouveau_channel *chan, int engine)
44{
45 struct drm_device *dev = chan->dev;
46 struct drm_nouveau_private *dev_priv = dev->dev_private;
47 struct nv98_crypt_priv *priv = nv_engine(dev, engine);
48 struct nv98_crypt_chan *cctx;
49 int ret;
50
51 cctx = chan->engctx[engine] = kzalloc(sizeof(*cctx), GFP_KERNEL);
52 if (!cctx)
53 return -ENOMEM;
54
55 atomic_inc(&chan->vm->engref[engine]);
56
57 ret = nouveau_gpuobj_new(dev, chan, 256, 0, NVOBJ_FLAG_ZERO_ALLOC |
58 NVOBJ_FLAG_ZERO_FREE, &cctx->mem);
59 if (ret)
60 goto error;
61
62 nv_wo32(chan->ramin, 0xa0, 0x00190000);
63 nv_wo32(chan->ramin, 0xa4, cctx->mem->vinst + cctx->mem->size - 1);
64 nv_wo32(chan->ramin, 0xa8, cctx->mem->vinst);
65 nv_wo32(chan->ramin, 0xac, 0x00000000);
66 nv_wo32(chan->ramin, 0xb0, 0x00000000);
67 nv_wo32(chan->ramin, 0xb4, 0x00000000);
68 dev_priv->engine.instmem.flush(dev);
69
70error:
71 if (ret)
72 priv->base.context_del(chan, engine);
73 return ret;
74}
75
76static void
77nv98_crypt_context_del(struct nouveau_channel *chan, int engine)
78{
79 struct nv98_crypt_chan *cctx = chan->engctx[engine];
80 int i;
81
82 for (i = 0xa0; i < 0xb4; i += 4)
83 nv_wo32(chan->ramin, i, 0x00000000);
84
85 nouveau_gpuobj_ref(NULL, &cctx->mem);
86
87 atomic_dec(&chan->vm->engref[engine]);
88 chan->engctx[engine] = NULL;
89 kfree(cctx);
90}
91
92static int
93nv98_crypt_object_new(struct nouveau_channel *chan, int engine,
94 u32 handle, u16 class)
37{ 95{
38 if (!(nv_rd32(dev, 0x000200) & 0x00004000)) 96 struct nv98_crypt_chan *cctx = chan->engctx[engine];
39 return 0; 97
98 /* fuc engine doesn't need an object, our ramht code does.. */
99 cctx->mem->engine = 5;
100 cctx->mem->class = class;
101 return nouveau_ramht_insert(chan, handle, cctx->mem);
102}
40 103
104static void
105nv98_crypt_tlb_flush(struct drm_device *dev, int engine)
106{
107 nv50_vm_flush_engine(dev, 0x0a);
108}
109
110static int
111nv98_crypt_fini(struct drm_device *dev, int engine, bool suspend)
112{
41 nv_mask(dev, 0x000200, 0x00004000, 0x00000000); 113 nv_mask(dev, 0x000200, 0x00004000, 0x00000000);
42 return 0; 114 return 0;
43} 115}
@@ -45,34 +117,100 @@ nv98_crypt_fini(struct drm_device *dev, int engine, bool suspend)
45static int 117static int
46nv98_crypt_init(struct drm_device *dev, int engine) 118nv98_crypt_init(struct drm_device *dev, int engine)
47{ 119{
120 int i;
121
122 /* reset! */
48 nv_mask(dev, 0x000200, 0x00004000, 0x00000000); 123 nv_mask(dev, 0x000200, 0x00004000, 0x00000000);
49 nv_mask(dev, 0x000200, 0x00004000, 0x00004000); 124 nv_mask(dev, 0x000200, 0x00004000, 0x00004000);
125
126 /* wait for exit interrupt to signal */
127 nv_wait(dev, 0x087008, 0x00000010, 0x00000010);
128 nv_wr32(dev, 0x087004, 0x00000010);
129
130 /* upload microcode code and data segments */
131 nv_wr32(dev, 0x087ff8, 0x00100000);
132 for (i = 0; i < ARRAY_SIZE(nv98_pcrypt_code); i++)
133 nv_wr32(dev, 0x087ff4, nv98_pcrypt_code[i]);
134
135 nv_wr32(dev, 0x087ff8, 0x00000000);
136 for (i = 0; i < ARRAY_SIZE(nv98_pcrypt_data); i++)
137 nv_wr32(dev, 0x087ff4, nv98_pcrypt_data[i]);
138
139 /* start it running */
140 nv_wr32(dev, 0x08710c, 0x00000000);
141 nv_wr32(dev, 0x087104, 0x00000000); /* ENTRY */
142 nv_wr32(dev, 0x087100, 0x00000002); /* TRIGGER */
50 return 0; 143 return 0;
51} 144}
52 145
146static struct nouveau_enum nv98_crypt_isr_error_name[] = {
147 { 0x0000, "ILLEGAL_MTHD" },
148 { 0x0001, "INVALID_BITFIELD" },
149 { 0x0002, "INVALID_ENUM" },
150 { 0x0003, "QUERY" },
151 {}
152};
153
154static void
155nv98_crypt_isr(struct drm_device *dev)
156{
157 u32 disp = nv_rd32(dev, 0x08701c);
158 u32 stat = nv_rd32(dev, 0x087008) & disp & ~(disp >> 16);
159 u32 inst = nv_rd32(dev, 0x087050) & 0x3fffffff;
160 u32 ssta = nv_rd32(dev, 0x087040) & 0x0000ffff;
161 u32 addr = nv_rd32(dev, 0x087040) >> 16;
162 u32 mthd = (addr & 0x07ff) << 2;
163 u32 subc = (addr & 0x3800) >> 11;
164 u32 data = nv_rd32(dev, 0x087044);
165 int chid = nv50_graph_isr_chid(dev, inst);
166
167 if (stat & 0x00000040) {
168 NV_INFO(dev, "PCRYPT: DISPATCH_ERROR [");
169 nouveau_enum_print(nv98_crypt_isr_error_name, ssta);
170 printk("] ch %d [0x%08x] subc %d mthd 0x%04x data 0x%08x\n",
171 chid, inst, subc, mthd, data);
172 nv_wr32(dev, 0x087004, 0x00000040);
173 stat &= ~0x00000040;
174 }
175
176 if (stat) {
177 NV_INFO(dev, "PCRYPT: unhandled intr 0x%08x\n", stat);
178 nv_wr32(dev, 0x087004, stat);
179 }
180
181 nv50_fb_vm_trap(dev, 1);
182}
183
53static void 184static void
54nv98_crypt_destroy(struct drm_device *dev, int engine) 185nv98_crypt_destroy(struct drm_device *dev, int engine)
55{ 186{
56 struct nv98_crypt_engine *pcrypt = nv_engine(dev, engine); 187 struct nv98_crypt_priv *priv = nv_engine(dev, engine);
57 188
189 nouveau_irq_unregister(dev, 14);
58 NVOBJ_ENGINE_DEL(dev, CRYPT); 190 NVOBJ_ENGINE_DEL(dev, CRYPT);
59 191 kfree(priv);
60 kfree(pcrypt);
61} 192}
62 193
63int 194int
64nv98_crypt_create(struct drm_device *dev) 195nv98_crypt_create(struct drm_device *dev)
65{ 196{
66 struct nv98_crypt_engine *pcrypt; 197 struct nv98_crypt_priv *priv;
67 198
68 pcrypt = kzalloc(sizeof(*pcrypt), GFP_KERNEL); 199 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
69 if (!pcrypt) 200 if (!priv)
70 return -ENOMEM; 201 return -ENOMEM;
71 202
72 pcrypt->base.destroy = nv98_crypt_destroy; 203 priv->base.destroy = nv98_crypt_destroy;
73 pcrypt->base.init = nv98_crypt_init; 204 priv->base.init = nv98_crypt_init;
74 pcrypt->base.fini = nv98_crypt_fini; 205 priv->base.fini = nv98_crypt_fini;
206 priv->base.context_new = nv98_crypt_context_new;
207 priv->base.context_del = nv98_crypt_context_del;
208 priv->base.object_new = nv98_crypt_object_new;
209 priv->base.tlb_flush = nv98_crypt_tlb_flush;
210
211 nouveau_irq_register(dev, 14, nv98_crypt_isr);
75 212
76 NVOBJ_ENGINE_ADD(dev, CRYPT, &pcrypt->base); 213 NVOBJ_ENGINE_ADD(dev, CRYPT, &priv->base);
214 NVOBJ_CLASS(dev, 0x88b4, CRYPT);
77 return 0; 215 return 0;
78} 216}
diff --git a/drivers/gpu/drm/nouveau/nv98_crypt.fuc b/drivers/gpu/drm/nouveau/nv98_crypt.fuc
new file mode 100644
index 000000000000..7393813044de
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv98_crypt.fuc
@@ -0,0 +1,698 @@
1/*
2 * fuc microcode for nv98 pcrypt engine
3 * Copyright (C) 2010 Marcin Kościelnicki
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20.section #nv98_pcrypt_data
21
22ctx_dma:
23ctx_dma_query: .b32 0
24ctx_dma_src: .b32 0
25ctx_dma_dst: .b32 0
26.equ #dma_count 3
27ctx_query_address_high: .b32 0
28ctx_query_address_low: .b32 0
29ctx_query_counter: .b32 0
30ctx_cond_address_high: .b32 0
31ctx_cond_address_low: .b32 0
32ctx_cond_off: .b32 0
33ctx_src_address_high: .b32 0
34ctx_src_address_low: .b32 0
35ctx_dst_address_high: .b32 0
36ctx_dst_address_low: .b32 0
37ctx_mode: .b32 0
38.align 16
39ctx_key: .skip 16
40ctx_iv: .skip 16
41
42.align 0x80
43swap:
44.skip 32
45
46.align 8
47common_cmd_dtable:
48.b32 #ctx_query_address_high + 0x20000 ~0xff
49.b32 #ctx_query_address_low + 0x20000 ~0xfffffff0
50.b32 #ctx_query_counter + 0x20000 ~0xffffffff
51.b32 #cmd_query_get + 0x00000 ~1
52.b32 #ctx_cond_address_high + 0x20000 ~0xff
53.b32 #ctx_cond_address_low + 0x20000 ~0xfffffff0
54.b32 #cmd_cond_mode + 0x00000 ~7
55.b32 #cmd_wrcache_flush + 0x00000 ~0
56.equ #common_cmd_max 0x88
57
58
59.align 8
60engine_cmd_dtable:
61.b32 #ctx_key + 0x0 + 0x20000 ~0xffffffff
62.b32 #ctx_key + 0x4 + 0x20000 ~0xffffffff
63.b32 #ctx_key + 0x8 + 0x20000 ~0xffffffff
64.b32 #ctx_key + 0xc + 0x20000 ~0xffffffff
65.b32 #ctx_iv + 0x0 + 0x20000 ~0xffffffff
66.b32 #ctx_iv + 0x4 + 0x20000 ~0xffffffff
67.b32 #ctx_iv + 0x8 + 0x20000 ~0xffffffff
68.b32 #ctx_iv + 0xc + 0x20000 ~0xffffffff
69.b32 #ctx_src_address_high + 0x20000 ~0xff
70.b32 #ctx_src_address_low + 0x20000 ~0xfffffff0
71.b32 #ctx_dst_address_high + 0x20000 ~0xff
72.b32 #ctx_dst_address_low + 0x20000 ~0xfffffff0
73.b32 #crypt_cmd_mode + 0x00000 ~0xf
74.b32 #crypt_cmd_length + 0x10000 ~0x0ffffff0
75.equ #engine_cmd_max 0xce
76
77.align 4
78crypt_dtable:
79.b16 #crypt_copy_prep #crypt_do_inout
80.b16 #crypt_store_prep #crypt_do_out
81.b16 #crypt_ecb_e_prep #crypt_do_inout
82.b16 #crypt_ecb_d_prep #crypt_do_inout
83.b16 #crypt_cbc_e_prep #crypt_do_inout
84.b16 #crypt_cbc_d_prep #crypt_do_inout
85.b16 #crypt_pcbc_e_prep #crypt_do_inout
86.b16 #crypt_pcbc_d_prep #crypt_do_inout
87.b16 #crypt_cfb_e_prep #crypt_do_inout
88.b16 #crypt_cfb_d_prep #crypt_do_inout
89.b16 #crypt_ofb_prep #crypt_do_inout
90.b16 #crypt_ctr_prep #crypt_do_inout
91.b16 #crypt_cbc_mac_prep #crypt_do_in
92.b16 #crypt_cmac_finish_complete_prep #crypt_do_in
93.b16 #crypt_cmac_finish_partial_prep #crypt_do_in
94
95.align 0x100
96
97.section #nv98_pcrypt_code
98
99 // $r0 is always set to 0 in our code - this allows some space savings.
100 clear b32 $r0
101
102 // set up the interrupt handler
103 mov $r1 #ih
104 mov $iv0 $r1
105
106 // init stack pointer
107 mov $sp $r0
108
109 // set interrupt dispatch - route timer, fifo, ctxswitch to i0, others to host
110 movw $r1 0xfff0
111 sethi $r1 0
112 mov $r2 0x400
113 iowr I[$r2 + 0x300] $r1
114
115 // enable the interrupts
116 or $r1 0xc
117 iowr I[$r2] $r1
118
119 // enable fifo access and context switching
120 mov $r1 3
121 mov $r2 0x1200
122 iowr I[$r2] $r1
123
124 // enable i0 delivery
125 bset $flags ie0
126
127 // sleep forver, waking only for interrupts.
128 bset $flags $p0
129 spin:
130 sleep $p0
131 bra #spin
132
133// i0 handler
134ih:
135 // see which interrupts we got
136 iord $r1 I[$r0 + 0x200]
137
138 and $r2 $r1 0x8
139 cmpu b32 $r2 0
140 bra e #noctx
141
142 // context switch... prepare the regs for xfer
143 mov $r2 0x7700
144 mov $xtargets $r2
145 mov $xdbase $r0
146 // 128-byte context.
147 mov $r2 0
148 sethi $r2 0x50000
149
150 // read current channel
151 mov $r3 0x1400
152 iord $r4 I[$r3]
153 // if bit 30 set, it's active, so we have to unload it first.
154 shl b32 $r5 $r4 1
155 cmps b32 $r5 0
156 bra nc #ctxload
157
158 // unload the current channel - save the context
159 xdst $r0 $r2
160 xdwait
161 // and clear bit 30, then write back
162 bclr $r4 0x1e
163 iowr I[$r3] $r4
164 // tell PFIFO we unloaded
165 mov $r4 1
166 iowr I[$r3 + 0x200] $r4
167
168 bra #noctx
169
170 ctxload:
171 // no channel loaded - perhaps we're requested to load one
172 iord $r4 I[$r3 + 0x100]
173 shl b32 $r15 $r4 1
174 cmps b32 $r15 0
175 // if bit 30 of next channel not set, probably PFIFO is just
176 // killing a context. do a faux load, without the active bit.
177 bra nc #dummyload
178
179 // ok, do a real context load.
180 xdld $r0 $r2
181 xdwait
182 mov $r5 #ctx_dma
183 mov $r6 #dma_count - 1
184 ctxload_dma_loop:
185 ld b32 $r7 D[$r5 + $r6 * 4]
186 add b32 $r8 $r6 0x180
187 shl b32 $r8 8
188 iowr I[$r8] $r7
189 sub b32 $r6 1
190 bra nc #ctxload_dma_loop
191
192 dummyload:
193 // tell PFIFO we're done
194 mov $r5 2
195 iowr I[$r3 + 0x200] $r5
196
197 noctx:
198 and $r2 $r1 0x4
199 cmpu b32 $r2 0
200 bra e #nocmd
201
202 // incoming fifo command.
203 mov $r3 0x1900
204 iord $r2 I[$r3 + 0x100]
205 iord $r3 I[$r3]
206 // extract the method
207 and $r4 $r2 0x7ff
208 // shift the addr to proper position if we need to interrupt later
209 shl b32 $r2 0x10
210
211 // mthd 0 and 0x100 [NAME, NOP]: ignore
212 and $r5 $r4 0x7bf
213 cmpu b32 $r5 0
214 bra e #cmddone
215
216 mov $r5 #engine_cmd_dtable - 0xc0 * 8
217 mov $r6 #engine_cmd_max
218 cmpu b32 $r4 0xc0
219 bra nc #dtable_cmd
220 mov $r5 #common_cmd_dtable - 0x80 * 8
221 mov $r6 #common_cmd_max
222 cmpu b32 $r4 0x80
223 bra nc #dtable_cmd
224 cmpu b32 $r4 0x60
225 bra nc #dma_cmd
226 cmpu b32 $r4 0x50
227 bra ne #illegal_mthd
228
229 // mthd 0x140: PM_TRIGGER
230 mov $r2 0x2200
231 clear b32 $r3
232 sethi $r3 0x20000
233 iowr I[$r2] $r3
234 bra #cmddone
235
236 dma_cmd:
237 // mthd 0x180...: DMA_*
238 cmpu b32 $r4 0x60+#dma_count
239 bra nc #illegal_mthd
240 shl b32 $r5 $r4 2
241 add b32 $r5 (#ctx_dma - 0x60 * 4) & 0xffff
242 bset $r3 0x1e
243 st b32 D[$r5] $r3
244 add b32 $r4 0x180 - 0x60
245 shl b32 $r4 8
246 iowr I[$r4] $r3
247 bra #cmddone
248
249 dtable_cmd:
250 cmpu b32 $r4 $r6
251 bra nc #illegal_mthd
252 shl b32 $r4 3
253 add b32 $r4 $r5
254 ld b32 $r5 D[$r4 + 4]
255 and $r5 $r3
256 cmpu b32 $r5 0
257 bra ne #invalid_bitfield
258 ld b16 $r5 D[$r4]
259 ld b16 $r6 D[$r4 + 2]
260 cmpu b32 $r6 2
261 bra e #cmd_setctx
262 ld b32 $r7 D[$r0 + #ctx_cond_off]
263 and $r6 $r7
264 cmpu b32 $r6 1
265 bra e #cmddone
266 call $r5
267 bra $p1 #dispatch_error
268 bra #cmddone
269
270 cmd_setctx:
271 st b32 D[$r5] $r3
272 bra #cmddone
273
274
275 invalid_bitfield:
276 or $r2 1
277 dispatch_error:
278 illegal_mthd:
279 mov $r4 0x1000
280 iowr I[$r4] $r2
281 iowr I[$r4 + 0x100] $r3
282 mov $r4 0x40
283 iowr I[$r0] $r4
284
285 im_loop:
286 iord $r4 I[$r0 + 0x200]
287 and $r4 0x40
288 cmpu b32 $r4 0
289 bra ne #im_loop
290
291 cmddone:
292 // remove the command from FIFO
293 mov $r3 0x1d00
294 mov $r4 1
295 iowr I[$r3] $r4
296
297 nocmd:
298 // ack the processed interrupts
299 and $r1 $r1 0xc
300 iowr I[$r0 + 0x100] $r1
301iret
302
303cmd_query_get:
304 // if bit 0 of param set, trigger interrupt afterwards.
305 setp $p1 $r3
306 or $r2 3
307
308 // read PTIMER, beware of races...
309 mov $r4 0xb00
310 ptimer_retry:
311 iord $r6 I[$r4 + 0x100]
312 iord $r5 I[$r4]
313 iord $r7 I[$r4 + 0x100]
314 cmpu b32 $r6 $r7
315 bra ne #ptimer_retry
316
317 // prepare the query structure
318 ld b32 $r4 D[$r0 + #ctx_query_counter]
319 st b32 D[$r0 + #swap + 0x0] $r4
320 st b32 D[$r0 + #swap + 0x4] $r0
321 st b32 D[$r0 + #swap + 0x8] $r5
322 st b32 D[$r0 + #swap + 0xc] $r6
323
324 // will use target 0, DMA_QUERY.
325 mov $xtargets $r0
326
327 ld b32 $r4 D[$r0 + #ctx_query_address_high]
328 shl b32 $r4 0x18
329 mov $xdbase $r4
330
331 ld b32 $r4 D[$r0 + #ctx_query_address_low]
332 mov $r5 #swap
333 sethi $r5 0x20000
334 xdst $r4 $r5
335 xdwait
336
337 ret
338
339cmd_cond_mode:
340 // if >= 5, INVALID_ENUM
341 bset $flags $p1
342 or $r2 2
343 cmpu b32 $r3 5
344 bra nc #return
345
346 // otherwise, no error.
347 bclr $flags $p1
348
349 // if < 2, no QUERY object is involved
350 cmpu b32 $r3 2
351 bra nc #cmd_cond_mode_queryful
352
353 xor $r3 1
354 st b32 D[$r0 + #ctx_cond_off] $r3
355 return:
356 ret
357
358 cmd_cond_mode_queryful:
359 // ok, will need to pull a QUERY object, prepare offsets
360 ld b32 $r4 D[$r0 + #ctx_cond_address_high]
361 ld b32 $r5 D[$r0 + #ctx_cond_address_low]
362 and $r6 $r5 0xff
363 shr b32 $r5 8
364 shl b32 $r4 0x18
365 or $r4 $r5
366 mov $xdbase $r4
367 mov $xtargets $r0
368
369 // pull the first one
370 mov $r5 #swap
371 sethi $r5 0x20000
372 xdld $r6 $r5
373
374 // if == 2, only a single QUERY is involved...
375 cmpu b32 $r3 2
376 bra ne #cmd_cond_mode_double
377
378 xdwait
379 ld b32 $r4 D[$r0 + #swap + 4]
380 cmpu b32 $r4 0
381 xbit $r4 $flags z
382 st b32 D[$r0 + #ctx_cond_off] $r4
383 ret
384
385 // ok, we'll need to pull second one too
386 cmd_cond_mode_double:
387 add b32 $r6 0x10
388 add b32 $r5 0x10
389 xdld $r6 $r5
390 xdwait
391
392 // compare COUNTERs
393 ld b32 $r5 D[$r0 + #swap + 0x00]
394 ld b32 $r6 D[$r0 + #swap + 0x10]
395 cmpu b32 $r5 $r6
396 xbit $r4 $flags z
397
398 // compare RESen
399 ld b32 $r5 D[$r0 + #swap + 0x04]
400 ld b32 $r6 D[$r0 + #swap + 0x14]
401 cmpu b32 $r5 $r6
402 xbit $r5 $flags z
403 and $r4 $r5
404
405 // and negate or not, depending on mode
406 cmpu b32 $r3 3
407 xbit $r5 $flags z
408 xor $r4 $r5
409 st b32 D[$r0 + #ctx_cond_off] $r4
410 ret
411
412cmd_wrcache_flush:
413 bclr $flags $p1
414 mov $r2 0x2200
415 clear b32 $r3
416 sethi $r3 0x10000
417 iowr I[$r2] $r3
418 ret
419
420crypt_cmd_mode:
421 // if >= 0xf, INVALID_ENUM
422 bset $flags $p1
423 or $r2 2
424 cmpu b32 $r3 0xf
425 bra nc #crypt_cmd_mode_return
426
427 bclr $flags $p1
428 st b32 D[$r0 + #ctx_mode] $r3
429
430 crypt_cmd_mode_return:
431 ret
432
433crypt_cmd_length:
434 // nop if length == 0
435 cmpu b32 $r3 0
436 bra e #crypt_cmd_mode_return
437
438 // init key, IV
439 cxset 3
440 mov $r4 #ctx_key
441 sethi $r4 0x70000
442 xdst $r0 $r4
443 mov $r4 #ctx_iv
444 sethi $r4 0x60000
445 xdst $r0 $r4
446 xdwait
447 ckeyreg $c7
448
449 // prepare the targets
450 mov $r4 0x2100
451 mov $xtargets $r4
452
453 // prepare src address
454 ld b32 $r4 D[$r0 + #ctx_src_address_high]
455 ld b32 $r5 D[$r0 + #ctx_src_address_low]
456 shr b32 $r8 $r5 8
457 shl b32 $r4 0x18
458 or $r4 $r8
459 and $r5 $r5 0xff
460
461 // prepare dst address
462 ld b32 $r6 D[$r0 + #ctx_dst_address_high]
463 ld b32 $r7 D[$r0 + #ctx_dst_address_low]
464 shr b32 $r8 $r7 8
465 shl b32 $r6 0x18
466 or $r6 $r8
467 and $r7 $r7 0xff
468
469 // find the proper prep & do functions
470 ld b32 $r8 D[$r0 + #ctx_mode]
471 shl b32 $r8 2
472
473 // run prep
474 ld b16 $r9 D[$r8 + #crypt_dtable]
475 call $r9
476
477 // do it
478 ld b16 $r9 D[$r8 + #crypt_dtable + 2]
479 call $r9
480 cxset 1
481 xdwait
482 cxset 0x61
483 xdwait
484 xdwait
485
486 // update src address
487 shr b32 $r8 $r4 0x18
488 shl b32 $r9 $r4 8
489 add b32 $r9 $r5
490 adc b32 $r8 0
491 st b32 D[$r0 + #ctx_src_address_high] $r8
492 st b32 D[$r0 + #ctx_src_address_low] $r9
493
494 // update dst address
495 shr b32 $r8 $r6 0x18
496 shl b32 $r9 $r6 8
497 add b32 $r9 $r7
498 adc b32 $r8 0
499 st b32 D[$r0 + #ctx_dst_address_high] $r8
500 st b32 D[$r0 + #ctx_dst_address_low] $r9
501
502 // pull updated IV
503 cxset 2
504 mov $r4 #ctx_iv
505 sethi $r4 0x60000
506 xdld $r0 $r4
507 xdwait
508
509 ret
510
511
512crypt_copy_prep:
513 cs0begin 2
514 cxsin $c0
515 cxsout $c0
516 ret
517
518crypt_store_prep:
519 cs0begin 1
520 cxsout $c6
521 ret
522
523crypt_ecb_e_prep:
524 cs0begin 3
525 cxsin $c0
526 cenc $c0 $c0
527 cxsout $c0
528 ret
529
530crypt_ecb_d_prep:
531 ckexp $c7 $c7
532 cs0begin 3
533 cxsin $c0
534 cdec $c0 $c0
535 cxsout $c0
536 ret
537
538crypt_cbc_e_prep:
539 cs0begin 4
540 cxsin $c0
541 cxor $c6 $c0
542 cenc $c6 $c6
543 cxsout $c6
544 ret
545
546crypt_cbc_d_prep:
547 ckexp $c7 $c7
548 cs0begin 5
549 cmov $c2 $c6
550 cxsin $c6
551 cdec $c0 $c6
552 cxor $c0 $c2
553 cxsout $c0
554 ret
555
556crypt_pcbc_e_prep:
557 cs0begin 5
558 cxsin $c0
559 cxor $c6 $c0
560 cenc $c6 $c6
561 cxsout $c6
562 cxor $c6 $c0
563 ret
564
565crypt_pcbc_d_prep:
566 ckexp $c7 $c7
567 cs0begin 5
568 cxsin $c0
569 cdec $c1 $c0
570 cxor $c6 $c1
571 cxsout $c6
572 cxor $c6 $c0
573 ret
574
575crypt_cfb_e_prep:
576 cs0begin 4
577 cenc $c6 $c6
578 cxsin $c0
579 cxor $c6 $c0
580 cxsout $c6
581 ret
582
583crypt_cfb_d_prep:
584 cs0begin 4
585 cenc $c0 $c6
586 cxsin $c6
587 cxor $c0 $c6
588 cxsout $c0
589 ret
590
591crypt_ofb_prep:
592 cs0begin 4
593 cenc $c6 $c6
594 cxsin $c0
595 cxor $c0 $c6
596 cxsout $c0
597 ret
598
599crypt_ctr_prep:
600 cs0begin 5
601 cenc $c1 $c6
602 cadd $c6 1
603 cxsin $c0
604 cxor $c0 $c1
605 cxsout $c0
606 ret
607
608crypt_cbc_mac_prep:
609 cs0begin 3
610 cxsin $c0
611 cxor $c6 $c0
612 cenc $c6 $c6
613 ret
614
615crypt_cmac_finish_complete_prep:
616 cs0begin 7
617 cxsin $c0
618 cxor $c6 $c0
619 cxor $c0 $c0
620 cenc $c0 $c0
621 cprecmac $c0 $c0
622 cxor $c6 $c0
623 cenc $c6 $c6
624 ret
625
626crypt_cmac_finish_partial_prep:
627 cs0begin 8
628 cxsin $c0
629 cxor $c6 $c0
630 cxor $c0 $c0
631 cenc $c0 $c0
632 cprecmac $c0 $c0
633 cprecmac $c0 $c0
634 cxor $c6 $c0
635 cenc $c6 $c6
636 ret
637
638// TODO
639crypt_do_in:
640 add b32 $r3 $r5
641 mov $xdbase $r4
642 mov $r9 #swap
643 sethi $r9 0x20000
644 crypt_do_in_loop:
645 xdld $r5 $r9
646 xdwait
647 cxset 0x22
648 xdst $r0 $r9
649 cs0exec 1
650 xdwait
651 add b32 $r5 0x10
652 cmpu b32 $r5 $r3
653 bra ne #crypt_do_in_loop
654 cxset 1
655 xdwait
656 ret
657
658crypt_do_out:
659 add b32 $r3 $r7
660 mov $xdbase $r6
661 mov $r9 #swap
662 sethi $r9 0x20000
663 crypt_do_out_loop:
664 cs0exec 1
665 cxset 0x61
666 xdld $r7 $r9
667 xdst $r7 $r9
668 cxset 1
669 xdwait
670 add b32 $r7 0x10
671 cmpu b32 $r7 $r3
672 bra ne #crypt_do_out_loop
673 ret
674
675crypt_do_inout:
676 add b32 $r3 $r5
677 mov $r9 #swap
678 sethi $r9 0x20000
679 crypt_do_inout_loop:
680 mov $xdbase $r4
681 xdld $r5 $r9
682 xdwait
683 cxset 0x21
684 xdst $r0 $r9
685 cs0exec 1
686 cxset 0x61
687 mov $xdbase $r6
688 xdld $r7 $r9
689 xdst $r7 $r9
690 cxset 1
691 xdwait
692 add b32 $r5 0x10
693 add b32 $r7 0x10
694 cmpu b32 $r5 $r3
695 bra ne #crypt_do_inout_loop
696 ret
697
698.align 0x100
diff --git a/drivers/gpu/drm/nouveau/nv98_crypt.fuc.h b/drivers/gpu/drm/nouveau/nv98_crypt.fuc.h
new file mode 100644
index 000000000000..38676c74e6e0
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv98_crypt.fuc.h
@@ -0,0 +1,584 @@
1uint32_t nv98_pcrypt_data[] = {
2/* 0x0000: ctx_dma */
3/* 0x0000: ctx_dma_query */
4 0x00000000,
5/* 0x0004: ctx_dma_src */
6 0x00000000,
7/* 0x0008: ctx_dma_dst */
8 0x00000000,
9/* 0x000c: ctx_query_address_high */
10 0x00000000,
11/* 0x0010: ctx_query_address_low */
12 0x00000000,
13/* 0x0014: ctx_query_counter */
14 0x00000000,
15/* 0x0018: ctx_cond_address_high */
16 0x00000000,
17/* 0x001c: ctx_cond_address_low */
18 0x00000000,
19/* 0x0020: ctx_cond_off */
20 0x00000000,
21/* 0x0024: ctx_src_address_high */
22 0x00000000,
23/* 0x0028: ctx_src_address_low */
24 0x00000000,
25/* 0x002c: ctx_dst_address_high */
26 0x00000000,
27/* 0x0030: ctx_dst_address_low */
28 0x00000000,
29/* 0x0034: ctx_mode */
30 0x00000000,
31 0x00000000,
32 0x00000000,
33/* 0x0040: ctx_key */
34 0x00000000,
35 0x00000000,
36 0x00000000,
37 0x00000000,
38/* 0x0050: ctx_iv */
39 0x00000000,
40 0x00000000,
41 0x00000000,
42 0x00000000,
43 0x00000000,
44 0x00000000,
45 0x00000000,
46 0x00000000,
47 0x00000000,
48 0x00000000,
49 0x00000000,
50 0x00000000,
51/* 0x0080: swap */
52 0x00000000,
53 0x00000000,
54 0x00000000,
55 0x00000000,
56 0x00000000,
57 0x00000000,
58 0x00000000,
59 0x00000000,
60/* 0x00a0: common_cmd_dtable */
61 0x0002000c,
62 0xffffff00,
63 0x00020010,
64 0x0000000f,
65 0x00020014,
66 0x00000000,
67 0x00000192,
68 0xfffffffe,
69 0x00020018,
70 0xffffff00,
71 0x0002001c,
72 0x0000000f,
73 0x000001d7,
74 0xfffffff8,
75 0x00000260,
76 0xffffffff,
77/* 0x00e0: engine_cmd_dtable */
78 0x00020040,
79 0x00000000,
80 0x00020044,
81 0x00000000,
82 0x00020048,
83 0x00000000,
84 0x0002004c,
85 0x00000000,
86 0x00020050,
87 0x00000000,
88 0x00020054,
89 0x00000000,
90 0x00020058,
91 0x00000000,
92 0x0002005c,
93 0x00000000,
94 0x00020024,
95 0xffffff00,
96 0x00020028,
97 0x0000000f,
98 0x0002002c,
99 0xffffff00,
100 0x00020030,
101 0x0000000f,
102 0x00000271,
103 0xfffffff0,
104 0x00010285,
105 0xf000000f,
106/* 0x0150: crypt_dtable */
107 0x04db0321,
108 0x04b1032f,
109 0x04db0339,
110 0x04db034b,
111 0x04db0361,
112 0x04db0377,
113 0x04db0395,
114 0x04db03af,
115 0x04db03cd,
116 0x04db03e3,
117 0x04db03f9,
118 0x04db040f,
119 0x04830429,
120 0x0483043b,
121 0x0483045d,
122 0x00000000,
123 0x00000000,
124 0x00000000,
125 0x00000000,
126 0x00000000,
127 0x00000000,
128 0x00000000,
129 0x00000000,
130 0x00000000,
131 0x00000000,
132 0x00000000,
133 0x00000000,
134 0x00000000,
135 0x00000000,
136 0x00000000,
137 0x00000000,
138 0x00000000,
139 0x00000000,
140 0x00000000,
141 0x00000000,
142 0x00000000,
143 0x00000000,
144 0x00000000,
145 0x00000000,
146 0x00000000,
147 0x00000000,
148 0x00000000,
149 0x00000000,
150 0x00000000,
151};
152
153uint32_t nv98_pcrypt_code[] = {
154 0x17f004bd,
155 0x0010fe35,
156 0xf10004fe,
157 0xf0fff017,
158 0x27f10013,
159 0x21d00400,
160 0x0c15f0c0,
161 0xf00021d0,
162 0x27f10317,
163 0x21d01200,
164 0x1031f400,
165/* 0x002f: spin */
166 0xf40031f4,
167 0x0ef40028,
168/* 0x0035: ih */
169 0x8001cffd,
170 0xb00812c4,
171 0x0bf40024,
172 0x0027f167,
173 0x002bfe77,
174 0xf00007fe,
175 0x23f00027,
176 0x0037f105,
177 0x0034cf14,
178 0xb0014594,
179 0x18f40055,
180 0x0602fa17,
181 0x4af003f8,
182 0x0034d01e,
183 0xd00147f0,
184 0x0ef48034,
185/* 0x0075: ctxload */
186 0x4034cf33,
187 0xb0014f94,
188 0x18f400f5,
189 0x0502fa21,
190 0x57f003f8,
191 0x0267f000,
192/* 0x008c: ctxload_dma_loop */
193 0xa07856bc,
194 0xb6018068,
195 0x87d00884,
196 0x0162b600,
197/* 0x009f: dummyload */
198 0xf0f018f4,
199 0x35d00257,
200/* 0x00a5: noctx */
201 0x0412c480,
202 0xf50024b0,
203 0xf100df0b,
204 0xcf190037,
205 0x33cf4032,
206 0xff24e400,
207 0x1024b607,
208 0x07bf45e4,
209 0xf50054b0,
210 0xf100b90b,
211 0xf1fae057,
212 0xb000ce67,
213 0x18f4c044,
214 0xa057f14d,
215 0x8867f1fc,
216 0x8044b000,
217 0xb03f18f4,
218 0x18f46044,
219 0x5044b019,
220 0xf1741bf4,
221 0xbd220027,
222 0x0233f034,
223 0xf50023d0,
224/* 0x0103: dma_cmd */
225 0xb000810e,
226 0x18f46344,
227 0x0245945e,
228 0xfe8050b7,
229 0x801e39f0,
230 0x40b70053,
231 0x44b60120,
232 0x0043d008,
233/* 0x0123: dtable_cmd */
234 0xb8600ef4,
235 0x18f40446,
236 0x0344b63e,
237 0x980045bb,
238 0x53fd0145,
239 0x0054b004,
240 0x58291bf4,
241 0x46580045,
242 0x0264b001,
243 0x98170bf4,
244 0x67fd0807,
245 0x0164b004,
246 0xf9300bf4,
247 0x0f01f455,
248/* 0x015b: cmd_setctx */
249 0x80280ef4,
250 0x0ef40053,
251/* 0x0161: invalid_bitfield */
252 0x0125f022,
253/* 0x0164: dispatch_error */
254/* 0x0164: illegal_mthd */
255 0x100047f1,
256 0xd00042d0,
257 0x47f04043,
258 0x0004d040,
259/* 0x0174: im_loop */
260 0xf08004cf,
261 0x44b04044,
262 0xf71bf400,
263/* 0x0180: cmddone */
264 0x1d0037f1,
265 0xd00147f0,
266/* 0x018a: nocmd */
267 0x11c40034,
268 0x4001d00c,
269/* 0x0192: cmd_query_get */
270 0x38f201f8,
271 0x0325f001,
272 0x0b0047f1,
273/* 0x019c: ptimer_retry */
274 0xcf4046cf,
275 0x47cf0045,
276 0x0467b840,
277 0x98f41bf4,
278 0x04800504,
279 0x21008020,
280 0x80220580,
281 0x0bfe2306,
282 0x03049800,
283 0xfe1844b6,
284 0x04980047,
285 0x8057f104,
286 0x0253f000,
287 0xf80645fa,
288/* 0x01d7: cmd_cond_mode */
289 0xf400f803,
290 0x25f00131,
291 0x0534b002,
292 0xf41218f4,
293 0x34b00132,
294 0x0b18f402,
295 0x800136f0,
296/* 0x01f2: return */
297 0x00f80803,
298/* 0x01f4: cmd_cond_mode_queryful */
299 0x98060498,
300 0x56c40705,
301 0x0855b6ff,
302 0xfd1844b6,
303 0x47fe0545,
304 0x000bfe00,
305 0x008057f1,
306 0xfa0253f0,
307 0x34b00565,
308 0x131bf402,
309 0x049803f8,
310 0x0044b021,
311 0x800b4cf0,
312 0x00f80804,
313/* 0x022c: cmd_cond_mode_double */
314 0xb61060b6,
315 0x65fa1050,
316 0x9803f805,
317 0x06982005,
318 0x0456b824,
319 0x980b4cf0,
320 0x06982105,
321 0x0456b825,
322 0xfd0b5cf0,
323 0x34b00445,
324 0x0b5cf003,
325 0x800645fd,
326 0x00f80804,
327/* 0x0260: cmd_wrcache_flush */
328 0xf10132f4,
329 0xbd220027,
330 0x0133f034,
331 0xf80023d0,
332/* 0x0271: crypt_cmd_mode */
333 0x0131f400,
334 0xb00225f0,
335 0x18f40f34,
336 0x0132f409,
337/* 0x0283: crypt_cmd_mode_return */
338 0xf80d0380,
339/* 0x0285: crypt_cmd_length */
340 0x0034b000,
341 0xf4fb0bf4,
342 0x47f0033c,
343 0x0743f040,
344 0xf00604fa,
345 0x43f05047,
346 0x0604fa06,
347 0x3cf503f8,
348 0x47f1c407,
349 0x4bfe2100,
350 0x09049800,
351 0x950a0598,
352 0x44b60858,
353 0x0548fd18,
354 0x98ff55c4,
355 0x07980b06,
356 0x0878950c,
357 0xfd1864b6,
358 0x77c40568,
359 0x0d0898ff,
360 0x580284b6,
361 0x95f9a889,
362 0xf9a98958,
363 0x013cf495,
364 0x3cf403f8,
365 0xf803f861,
366 0x18489503,
367 0xbb084994,
368 0x81b60095,
369 0x09088000,
370 0x950a0980,
371 0x69941868,
372 0x0097bb08,
373 0x800081b6,
374 0x09800b08,
375 0x023cf40c,
376 0xf05047f0,
377 0x04fa0643,
378 0xf803f805,
379/* 0x0321: crypt_copy_prep */
380 0x203cf500,
381 0x003cf594,
382 0x003cf588,
383/* 0x032f: crypt_store_prep */
384 0xf500f88c,
385 0xf594103c,
386 0xf88c063c,
387/* 0x0339: crypt_ecb_e_prep */
388 0x303cf500,
389 0x003cf594,
390 0x003cf588,
391 0x003cf5d0,
392/* 0x034b: crypt_ecb_d_prep */
393 0xf500f88c,
394 0xf5c8773c,
395 0xf594303c,
396 0xf588003c,
397 0xf5d4003c,
398 0xf88c003c,
399/* 0x0361: crypt_cbc_e_prep */
400 0x403cf500,
401 0x003cf594,
402 0x063cf588,
403 0x663cf5ac,
404 0x063cf5d0,
405/* 0x0377: crypt_cbc_d_prep */
406 0xf500f88c,
407 0xf5c8773c,
408 0xf594503c,
409 0xf584623c,
410 0xf588063c,
411 0xf5d4603c,
412 0xf5ac203c,
413 0xf88c003c,
414/* 0x0395: crypt_pcbc_e_prep */
415 0x503cf500,
416 0x003cf594,
417 0x063cf588,
418 0x663cf5ac,
419 0x063cf5d0,
420 0x063cf58c,
421/* 0x03af: crypt_pcbc_d_prep */
422 0xf500f8ac,
423 0xf5c8773c,
424 0xf594503c,
425 0xf588003c,
426 0xf5d4013c,
427 0xf5ac163c,
428 0xf58c063c,
429 0xf8ac063c,
430/* 0x03cd: crypt_cfb_e_prep */
431 0x403cf500,
432 0x663cf594,
433 0x003cf5d0,
434 0x063cf588,
435 0x063cf5ac,
436/* 0x03e3: crypt_cfb_d_prep */
437 0xf500f88c,
438 0xf594403c,
439 0xf5d0603c,
440 0xf588063c,
441 0xf5ac603c,
442 0xf88c003c,
443/* 0x03f9: crypt_ofb_prep */
444 0x403cf500,
445 0x663cf594,
446 0x003cf5d0,
447 0x603cf588,
448 0x003cf5ac,
449/* 0x040f: crypt_ctr_prep */
450 0xf500f88c,
451 0xf594503c,
452 0xf5d0613c,
453 0xf5b0163c,
454 0xf588003c,
455 0xf5ac103c,
456 0xf88c003c,
457/* 0x0429: crypt_cbc_mac_prep */
458 0x303cf500,
459 0x003cf594,
460 0x063cf588,
461 0x663cf5ac,
462/* 0x043b: crypt_cmac_finish_complete_prep */
463 0xf500f8d0,
464 0xf594703c,
465 0xf588003c,
466 0xf5ac063c,
467 0xf5ac003c,
468 0xf5d0003c,
469 0xf5bc003c,
470 0xf5ac063c,
471 0xf8d0663c,
472/* 0x045d: crypt_cmac_finish_partial_prep */
473 0x803cf500,
474 0x003cf594,
475 0x063cf588,
476 0x003cf5ac,
477 0x003cf5ac,
478 0x003cf5d0,
479 0x003cf5bc,
480 0x063cf5bc,
481 0x663cf5ac,
482/* 0x0483: crypt_do_in */
483 0xbb00f8d0,
484 0x47fe0035,
485 0x8097f100,
486 0x0293f000,
487/* 0x0490: crypt_do_in_loop */
488 0xf80559fa,
489 0x223cf403,
490 0xf50609fa,
491 0xf898103c,
492 0x1050b603,
493 0xf40453b8,
494 0x3cf4e91b,
495 0xf803f801,
496/* 0x04b1: crypt_do_out */
497 0x0037bb00,
498 0xf10067fe,
499 0xf0008097,
500/* 0x04be: crypt_do_out_loop */
501 0x3cf50293,
502 0x3cf49810,
503 0x0579fa61,
504 0xf40679fa,
505 0x03f8013c,
506 0xb81070b6,
507 0x1bf40473,
508/* 0x04db: crypt_do_inout */
509 0xbb00f8e8,
510 0x97f10035,
511 0x93f00080,
512/* 0x04e5: crypt_do_inout_loop */
513 0x0047fe02,
514 0xf80559fa,
515 0x213cf403,
516 0xf50609fa,
517 0xf498103c,
518 0x67fe613c,
519 0x0579fa00,
520 0xf40679fa,
521 0x03f8013c,
522 0xb61050b6,
523 0x53b81070,
524 0xd41bf404,
525 0x000000f8,
526 0x00000000,
527 0x00000000,
528 0x00000000,
529 0x00000000,
530 0x00000000,
531 0x00000000,
532 0x00000000,
533 0x00000000,
534 0x00000000,
535 0x00000000,
536 0x00000000,
537 0x00000000,
538 0x00000000,
539 0x00000000,
540 0x00000000,
541 0x00000000,
542 0x00000000,
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generated by cgit v1.2.2 (git 2.25.0) at 2025-01-15 09:34:28 -0500