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-rw-r--r--sound/soc/davinci/davinci-mcasp.c1016
1 files changed, 435 insertions, 581 deletions
diff --git a/sound/soc/davinci/davinci-mcasp.c b/sound/soc/davinci/davinci-mcasp.c
index 71e14bb3a8cd..b7858bfa0295 100644
--- a/sound/soc/davinci/davinci-mcasp.c
+++ b/sound/soc/davinci/davinci-mcasp.c
@@ -21,6 +21,7 @@
21#include <linux/slab.h> 21#include <linux/slab.h>
22#include <linux/delay.h> 22#include <linux/delay.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/clk.h>
24#include <linux/pm_runtime.h> 25#include <linux/pm_runtime.h>
25#include <linux/of.h> 26#include <linux/of.h>
26#include <linux/of_platform.h> 27#include <linux/of_platform.h>
@@ -31,351 +32,147 @@
31#include <sound/pcm_params.h> 32#include <sound/pcm_params.h>
32#include <sound/initval.h> 33#include <sound/initval.h>
33#include <sound/soc.h> 34#include <sound/soc.h>
35#include <sound/dmaengine_pcm.h>
34 36
35#include "davinci-pcm.h" 37#include "davinci-pcm.h"
36#include "davinci-mcasp.h" 38#include "davinci-mcasp.h"
37 39
38/* 40struct davinci_mcasp {
39 * McASP register definitions 41 struct davinci_pcm_dma_params dma_params[2];
40 */ 42 struct snd_dmaengine_dai_dma_data dma_data[2];
41#define DAVINCI_MCASP_PID_REG 0x00 43 void __iomem *base;
42#define DAVINCI_MCASP_PWREMUMGT_REG 0x04 44 u32 fifo_base;
43 45 struct device *dev;
44#define DAVINCI_MCASP_PFUNC_REG 0x10
45#define DAVINCI_MCASP_PDIR_REG 0x14
46#define DAVINCI_MCASP_PDOUT_REG 0x18
47#define DAVINCI_MCASP_PDSET_REG 0x1c
48
49#define DAVINCI_MCASP_PDCLR_REG 0x20
50
51#define DAVINCI_MCASP_TLGC_REG 0x30
52#define DAVINCI_MCASP_TLMR_REG 0x34
53
54#define DAVINCI_MCASP_GBLCTL_REG 0x44
55#define DAVINCI_MCASP_AMUTE_REG 0x48
56#define DAVINCI_MCASP_LBCTL_REG 0x4c
57
58#define DAVINCI_MCASP_TXDITCTL_REG 0x50
59
60#define DAVINCI_MCASP_GBLCTLR_REG 0x60
61#define DAVINCI_MCASP_RXMASK_REG 0x64
62#define DAVINCI_MCASP_RXFMT_REG 0x68
63#define DAVINCI_MCASP_RXFMCTL_REG 0x6c
64
65#define DAVINCI_MCASP_ACLKRCTL_REG 0x70
66#define DAVINCI_MCASP_AHCLKRCTL_REG 0x74
67#define DAVINCI_MCASP_RXTDM_REG 0x78
68#define DAVINCI_MCASP_EVTCTLR_REG 0x7c
69
70#define DAVINCI_MCASP_RXSTAT_REG 0x80
71#define DAVINCI_MCASP_RXTDMSLOT_REG 0x84
72#define DAVINCI_MCASP_RXCLKCHK_REG 0x88
73#define DAVINCI_MCASP_REVTCTL_REG 0x8c
74
75#define DAVINCI_MCASP_GBLCTLX_REG 0xa0
76#define DAVINCI_MCASP_TXMASK_REG 0xa4
77#define DAVINCI_MCASP_TXFMT_REG 0xa8
78#define DAVINCI_MCASP_TXFMCTL_REG 0xac
79
80#define DAVINCI_MCASP_ACLKXCTL_REG 0xb0
81#define DAVINCI_MCASP_AHCLKXCTL_REG 0xb4
82#define DAVINCI_MCASP_TXTDM_REG 0xb8
83#define DAVINCI_MCASP_EVTCTLX_REG 0xbc
84
85#define DAVINCI_MCASP_TXSTAT_REG 0xc0
86#define DAVINCI_MCASP_TXTDMSLOT_REG 0xc4
87#define DAVINCI_MCASP_TXCLKCHK_REG 0xc8
88#define DAVINCI_MCASP_XEVTCTL_REG 0xcc
89
90/* Left(even TDM Slot) Channel Status Register File */
91#define DAVINCI_MCASP_DITCSRA_REG 0x100
92/* Right(odd TDM slot) Channel Status Register File */
93#define DAVINCI_MCASP_DITCSRB_REG 0x118
94/* Left(even TDM slot) User Data Register File */
95#define DAVINCI_MCASP_DITUDRA_REG 0x130
96/* Right(odd TDM Slot) User Data Register File */
97#define DAVINCI_MCASP_DITUDRB_REG 0x148
98
99/* Serializer n Control Register */
100#define DAVINCI_MCASP_XRSRCTL_BASE_REG 0x180
101#define DAVINCI_MCASP_XRSRCTL_REG(n) (DAVINCI_MCASP_XRSRCTL_BASE_REG + \
102 (n << 2))
103
104/* Transmit Buffer for Serializer n */
105#define DAVINCI_MCASP_TXBUF_REG 0x200
106/* Receive Buffer for Serializer n */
107#define DAVINCI_MCASP_RXBUF_REG 0x280
108
109/* McASP FIFO Registers */
110#define DAVINCI_MCASP_WFIFOCTL (0x1010)
111#define DAVINCI_MCASP_WFIFOSTS (0x1014)
112#define DAVINCI_MCASP_RFIFOCTL (0x1018)
113#define DAVINCI_MCASP_RFIFOSTS (0x101C)
114#define MCASP_VER3_WFIFOCTL (0x1000)
115#define MCASP_VER3_WFIFOSTS (0x1004)
116#define MCASP_VER3_RFIFOCTL (0x1008)
117#define MCASP_VER3_RFIFOSTS (0x100C)
118
119/*
120 * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management
121 * Register Bits
122 */
123#define MCASP_FREE BIT(0)
124#define MCASP_SOFT BIT(1)
125
126/*
127 * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits
128 */
129#define AXR(n) (1<<n)
130#define PFUNC_AMUTE BIT(25)
131#define ACLKX BIT(26)
132#define AHCLKX BIT(27)
133#define AFSX BIT(28)
134#define ACLKR BIT(29)
135#define AHCLKR BIT(30)
136#define AFSR BIT(31)
137
138/*
139 * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits
140 */
141#define AXR(n) (1<<n)
142#define PDIR_AMUTE BIT(25)
143#define ACLKX BIT(26)
144#define AHCLKX BIT(27)
145#define AFSX BIT(28)
146#define ACLKR BIT(29)
147#define AHCLKR BIT(30)
148#define AFSR BIT(31)
149
150/*
151 * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits
152 */
153#define DITEN BIT(0) /* Transmit DIT mode enable/disable */
154#define VA BIT(2)
155#define VB BIT(3)
156
157/*
158 * DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits
159 */
160#define TXROT(val) (val)
161#define TXSEL BIT(3)
162#define TXSSZ(val) (val<<4)
163#define TXPBIT(val) (val<<8)
164#define TXPAD(val) (val<<13)
165#define TXORD BIT(15)
166#define FSXDLY(val) (val<<16)
167
168/*
169 * DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits
170 */
171#define RXROT(val) (val)
172#define RXSEL BIT(3)
173#define RXSSZ(val) (val<<4)
174#define RXPBIT(val) (val<<8)
175#define RXPAD(val) (val<<13)
176#define RXORD BIT(15)
177#define FSRDLY(val) (val<<16)
178
179/*
180 * DAVINCI_MCASP_TXFMCTL_REG - Transmit Frame Control Register Bits
181 */
182#define FSXPOL BIT(0)
183#define AFSXE BIT(1)
184#define FSXDUR BIT(4)
185#define FSXMOD(val) (val<<7)
186
187/*
188 * DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits
189 */
190#define FSRPOL BIT(0)
191#define AFSRE BIT(1)
192#define FSRDUR BIT(4)
193#define FSRMOD(val) (val<<7)
194
195/*
196 * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits
197 */
198#define ACLKXDIV(val) (val)
199#define ACLKXE BIT(5)
200#define TX_ASYNC BIT(6)
201#define ACLKXPOL BIT(7)
202#define ACLKXDIV_MASK 0x1f
203
204/*
205 * DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits
206 */
207#define ACLKRDIV(val) (val)
208#define ACLKRE BIT(5)
209#define RX_ASYNC BIT(6)
210#define ACLKRPOL BIT(7)
211#define ACLKRDIV_MASK 0x1f
212
213/*
214 * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
215 * Register Bits
216 */
217#define AHCLKXDIV(val) (val)
218#define AHCLKXPOL BIT(14)
219#define AHCLKXE BIT(15)
220#define AHCLKXDIV_MASK 0xfff
221 46
222/* 47 /* McASP specific data */
223 * DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control 48 int tdm_slots;
224 * Register Bits 49 u8 op_mode;
225 */ 50 u8 num_serializer;
226#define AHCLKRDIV(val) (val) 51 u8 *serial_dir;
227#define AHCLKRPOL BIT(14) 52 u8 version;
228#define AHCLKRE BIT(15) 53 u16 bclk_lrclk_ratio;
229#define AHCLKRDIV_MASK 0xfff 54 int streams;
230 55
231/* 56 /* McASP FIFO related */
232 * DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits 57 u8 txnumevt;
233 */ 58 u8 rxnumevt;
234#define MODE(val) (val)
235#define DISMOD (val)(val<<2)
236#define TXSTATE BIT(4)
237#define RXSTATE BIT(5)
238#define SRMOD_MASK 3
239#define SRMOD_INACTIVE 0
240
241/*
242 * DAVINCI_MCASP_LBCTL_REG - Loop Back Control Register Bits
243 */
244#define LBEN BIT(0)
245#define LBORD BIT(1)
246#define LBGENMODE(val) (val<<2)
247 59
248/* 60 bool dat_port;
249 * DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration
250 */
251#define TXTDMS(n) (1<<n)
252
253/*
254 * DAVINCI_MCASP_RXTDMSLOT_REG - Receive TDM Slot Register configuration
255 */
256#define RXTDMS(n) (1<<n)
257
258/*
259 * DAVINCI_MCASP_GBLCTL_REG - Global Control Register Bits
260 */
261#define RXCLKRST BIT(0) /* Receiver Clock Divider Reset */
262#define RXHCLKRST BIT(1) /* Receiver High Frequency Clock Divider */
263#define RXSERCLR BIT(2) /* Receiver Serializer Clear */
264#define RXSMRST BIT(3) /* Receiver State Machine Reset */
265#define RXFSRST BIT(4) /* Frame Sync Generator Reset */
266#define TXCLKRST BIT(8) /* Transmitter Clock Divider Reset */
267#define TXHCLKRST BIT(9) /* Transmitter High Frequency Clock Divider*/
268#define TXSERCLR BIT(10) /* Transmit Serializer Clear */
269#define TXSMRST BIT(11) /* Transmitter State Machine Reset */
270#define TXFSRST BIT(12) /* Frame Sync Generator Reset */
271 61
272/* 62#ifdef CONFIG_PM_SLEEP
273 * DAVINCI_MCASP_AMUTE_REG - Mute Control Register Bits 63 struct {
274 */ 64 u32 txfmtctl;
275#define MUTENA(val) (val) 65 u32 rxfmtctl;
276#define MUTEINPOL BIT(2) 66 u32 txfmt;
277#define MUTEINENA BIT(3) 67 u32 rxfmt;
278#define MUTEIN BIT(4) 68 u32 aclkxctl;
279#define MUTER BIT(5) 69 u32 aclkrctl;
280#define MUTEX BIT(6) 70 u32 pdir;
281#define MUTEFSR BIT(7) 71 } context;
282#define MUTEFSX BIT(8) 72#endif
283#define MUTEBADCLKR BIT(9) 73};
284#define MUTEBADCLKX BIT(10)
285#define MUTERXDMAERR BIT(11)
286#define MUTETXDMAERR BIT(12)
287
288/*
289 * DAVINCI_MCASP_REVTCTL_REG - Receiver DMA Event Control Register bits
290 */
291#define RXDATADMADIS BIT(0)
292
293/*
294 * DAVINCI_MCASP_XEVTCTL_REG - Transmitter DMA Event Control Register bits
295 */
296#define TXDATADMADIS BIT(0)
297
298/*
299 * DAVINCI_MCASP_W[R]FIFOCTL - Write/Read FIFO Control Register bits
300 */
301#define FIFO_ENABLE BIT(16)
302#define NUMEVT_MASK (0xFF << 8)
303#define NUMDMA_MASK (0xFF)
304
305#define DAVINCI_MCASP_NUM_SERIALIZER 16
306 74
307static inline void mcasp_set_bits(void __iomem *reg, u32 val) 75static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
76 u32 val)
308{ 77{
78 void __iomem *reg = mcasp->base + offset;
309 __raw_writel(__raw_readl(reg) | val, reg); 79 __raw_writel(__raw_readl(reg) | val, reg);
310} 80}
311 81
312static inline void mcasp_clr_bits(void __iomem *reg, u32 val) 82static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
83 u32 val)
313{ 84{
85 void __iomem *reg = mcasp->base + offset;
314 __raw_writel((__raw_readl(reg) & ~(val)), reg); 86 __raw_writel((__raw_readl(reg) & ~(val)), reg);
315} 87}
316 88
317static inline void mcasp_mod_bits(void __iomem *reg, u32 val, u32 mask) 89static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
90 u32 val, u32 mask)
318{ 91{
92 void __iomem *reg = mcasp->base + offset;
319 __raw_writel((__raw_readl(reg) & ~mask) | val, reg); 93 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
320} 94}
321 95
322static inline void mcasp_set_reg(void __iomem *reg, u32 val) 96static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
97 u32 val)
323{ 98{
324 __raw_writel(val, reg); 99 __raw_writel(val, mcasp->base + offset);
325} 100}
326 101
327static inline u32 mcasp_get_reg(void __iomem *reg) 102static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
328{ 103{
329 return (unsigned int)__raw_readl(reg); 104 return (u32)__raw_readl(mcasp->base + offset);
330} 105}
331 106
332static inline void mcasp_set_ctl_reg(void __iomem *regs, u32 val) 107static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
333{ 108{
334 int i = 0; 109 int i = 0;
335 110
336 mcasp_set_bits(regs, val); 111 mcasp_set_bits(mcasp, ctl_reg, val);
337 112
338 /* programming GBLCTL needs to read back from GBLCTL and verfiy */ 113 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
339 /* loop count is to avoid the lock-up */ 114 /* loop count is to avoid the lock-up */
340 for (i = 0; i < 1000; i++) { 115 for (i = 0; i < 1000; i++) {
341 if ((mcasp_get_reg(regs) & val) == val) 116 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
342 break; 117 break;
343 } 118 }
344 119
345 if (i == 1000 && ((mcasp_get_reg(regs) & val) != val)) 120 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
346 printk(KERN_ERR "GBLCTL write error\n"); 121 printk(KERN_ERR "GBLCTL write error\n");
347} 122}
348 123
349static void mcasp_start_rx(struct davinci_audio_dev *dev) 124static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
350{ 125{
351 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST); 126 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
352 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST); 127 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
353 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
354 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
355 128
356 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); 129 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
357 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); 130}
358 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
359 131
360 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); 132static void mcasp_start_rx(struct davinci_mcasp *mcasp)
361 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); 133{
134 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
135 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
136
137 /*
138 * When ASYNC == 0 the transmit and receive sections operate
139 * synchronously from the transmit clock and frame sync. We need to make
140 * sure that the TX signlas are enabled when starting reception.
141 */
142 if (mcasp_is_synchronous(mcasp)) {
143 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
144 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
145 }
146
147 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
148 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);
149
150 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
151 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
152 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);
153
154 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
155 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
156
157 if (mcasp_is_synchronous(mcasp))
158 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
362} 159}
363 160
364static void mcasp_start_tx(struct davinci_audio_dev *dev) 161static void mcasp_start_tx(struct davinci_mcasp *mcasp)
365{ 162{
366 u8 offset = 0, i; 163 u8 offset = 0, i;
367 u32 cnt; 164 u32 cnt;
368 165
369 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); 166 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
370 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); 167 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
371 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); 168 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
372 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0); 169 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
373 170
374 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); 171 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
375 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); 172 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
376 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0); 173 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
377 for (i = 0; i < dev->num_serializer; i++) { 174 for (i = 0; i < mcasp->num_serializer; i++) {
378 if (dev->serial_dir[i] == TX_MODE) { 175 if (mcasp->serial_dir[i] == TX_MODE) {
379 offset = i; 176 offset = i;
380 break; 177 break;
381 } 178 }
@@ -383,156 +180,140 @@ static void mcasp_start_tx(struct davinci_audio_dev *dev)
383 180
384 /* wait for TX ready */ 181 /* wait for TX ready */
385 cnt = 0; 182 cnt = 0;
386 while (!(mcasp_get_reg(dev->base + DAVINCI_MCASP_XRSRCTL_REG(offset)) & 183 while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(offset)) &
387 TXSTATE) && (cnt < 100000)) 184 TXSTATE) && (cnt < 100000))
388 cnt++; 185 cnt++;
389 186
390 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0); 187 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
391} 188}
392 189
393static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream) 190static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
394{ 191{
192 u32 reg;
193
194 mcasp->streams++;
195
395 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 196 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
396 if (dev->txnumevt) { /* enable FIFO */ 197 if (mcasp->txnumevt) { /* enable FIFO */
397 switch (dev->version) { 198 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
398 case MCASP_VERSION_3: 199 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
399 mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL, 200 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
400 FIFO_ENABLE);
401 mcasp_set_bits(dev->base + MCASP_VER3_WFIFOCTL,
402 FIFO_ENABLE);
403 break;
404 default:
405 mcasp_clr_bits(dev->base +
406 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
407 mcasp_set_bits(dev->base +
408 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
409 }
410 } 201 }
411 mcasp_start_tx(dev); 202 mcasp_start_tx(mcasp);
412 } else { 203 } else {
413 if (dev->rxnumevt) { /* enable FIFO */ 204 if (mcasp->rxnumevt) { /* enable FIFO */
414 switch (dev->version) { 205 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
415 case MCASP_VERSION_3: 206 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
416 mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL, 207 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
417 FIFO_ENABLE);
418 mcasp_set_bits(dev->base + MCASP_VER3_RFIFOCTL,
419 FIFO_ENABLE);
420 break;
421 default:
422 mcasp_clr_bits(dev->base +
423 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
424 mcasp_set_bits(dev->base +
425 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
426 }
427 } 208 }
428 mcasp_start_rx(dev); 209 mcasp_start_rx(mcasp);
429 } 210 }
430} 211}
431 212
432static void mcasp_stop_rx(struct davinci_audio_dev *dev) 213static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
433{ 214{
434 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, 0); 215 /*
435 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 216 * In synchronous mode stop the TX clocks if no other stream is
217 * running
218 */
219 if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
220 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
221
222 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
223 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
436} 224}
437 225
438static void mcasp_stop_tx(struct davinci_audio_dev *dev) 226static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
439{ 227{
440 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, 0); 228 u32 val = 0;
441 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 229
230 /*
231 * In synchronous mode keep TX clocks running if the capture stream is
232 * still running.
233 */
234 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
235 val = TXHCLKRST | TXCLKRST | TXFSRST;
236
237 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
238 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
442} 239}
443 240
444static void davinci_mcasp_stop(struct davinci_audio_dev *dev, int stream) 241static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
445{ 242{
243 u32 reg;
244
245 mcasp->streams--;
246
446 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 247 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
447 if (dev->txnumevt) { /* disable FIFO */ 248 if (mcasp->txnumevt) { /* disable FIFO */
448 switch (dev->version) { 249 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
449 case MCASP_VERSION_3: 250 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
450 mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
451 FIFO_ENABLE);
452 break;
453 default:
454 mcasp_clr_bits(dev->base +
455 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
456 }
457 } 251 }
458 mcasp_stop_tx(dev); 252 mcasp_stop_tx(mcasp);
459 } else { 253 } else {
460 if (dev->rxnumevt) { /* disable FIFO */ 254 if (mcasp->rxnumevt) { /* disable FIFO */
461 switch (dev->version) { 255 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
462 case MCASP_VERSION_3: 256 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
463 mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL,
464 FIFO_ENABLE);
465 break;
466
467 default:
468 mcasp_clr_bits(dev->base +
469 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
470 }
471 } 257 }
472 mcasp_stop_rx(dev); 258 mcasp_stop_rx(mcasp);
473 } 259 }
474} 260}
475 261
476static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, 262static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
477 unsigned int fmt) 263 unsigned int fmt)
478{ 264{
479 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai); 265 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
480 void __iomem *base = dev->base;
481 266
482 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 267 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
483 case SND_SOC_DAIFMT_DSP_B: 268 case SND_SOC_DAIFMT_DSP_B:
484 case SND_SOC_DAIFMT_AC97: 269 case SND_SOC_DAIFMT_AC97:
485 mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 270 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
486 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 271 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
487 break; 272 break;
488 default: 273 default:
489 /* configure a full-word SYNC pulse (LRCLK) */ 274 /* configure a full-word SYNC pulse (LRCLK) */
490 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 275 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
491 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 276 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
492 277
493 /* make 1st data bit occur one ACLK cycle after the frame sync */ 278 /* make 1st data bit occur one ACLK cycle after the frame sync */
494 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, FSXDLY(1)); 279 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(1));
495 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, FSRDLY(1)); 280 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(1));
496 break; 281 break;
497 } 282 }
498 283
499 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 284 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
500 case SND_SOC_DAIFMT_CBS_CFS: 285 case SND_SOC_DAIFMT_CBS_CFS:
501 /* codec is clock and frame slave */ 286 /* codec is clock and frame slave */
502 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 287 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
503 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 288 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
504 289
505 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 290 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
506 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 291 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
507 292
508 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, 293 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
509 ACLKX | ACLKR); 294 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
510 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
511 AFSX | AFSR);
512 break; 295 break;
513 case SND_SOC_DAIFMT_CBM_CFS: 296 case SND_SOC_DAIFMT_CBM_CFS:
514 /* codec is clock master and frame slave */ 297 /* codec is clock master and frame slave */
515 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 298 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
516 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 299 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
517 300
518 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 301 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
519 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 302 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
520 303
521 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG, 304 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
522 ACLKX | ACLKR); 305 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
523 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
524 AFSX | AFSR);
525 break; 306 break;
526 case SND_SOC_DAIFMT_CBM_CFM: 307 case SND_SOC_DAIFMT_CBM_CFM:
527 /* codec is clock and frame master */ 308 /* codec is clock and frame master */
528 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 309 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
529 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 310 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
530 311
531 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 312 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
532 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 313 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
533 314
534 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG, 315 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
535 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR); 316 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
536 break; 317 break;
537 318
538 default: 319 default:
@@ -541,35 +322,35 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
541 322
542 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 323 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
543 case SND_SOC_DAIFMT_IB_NF: 324 case SND_SOC_DAIFMT_IB_NF:
544 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 325 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
545 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); 326 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
546 327
547 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 328 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
548 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); 329 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
549 break; 330 break;
550 331
551 case SND_SOC_DAIFMT_NB_IF: 332 case SND_SOC_DAIFMT_NB_IF:
552 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 333 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
553 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); 334 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
554 335
555 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 336 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
556 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); 337 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
557 break; 338 break;
558 339
559 case SND_SOC_DAIFMT_IB_IF: 340 case SND_SOC_DAIFMT_IB_IF:
560 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 341 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
561 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); 342 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
562 343
563 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 344 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
564 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); 345 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
565 break; 346 break;
566 347
567 case SND_SOC_DAIFMT_NB_NF: 348 case SND_SOC_DAIFMT_NB_NF:
568 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 349 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
569 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); 350 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
570 351
571 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 352 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
572 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); 353 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
573 break; 354 break;
574 355
575 default: 356 default:
@@ -581,25 +362,25 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
581 362
582static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div) 363static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
583{ 364{
584 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai); 365 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
585 366
586 switch (div_id) { 367 switch (div_id) {
587 case 0: /* MCLK divider */ 368 case 0: /* MCLK divider */
588 mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, 369 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
589 AHCLKXDIV(div - 1), AHCLKXDIV_MASK); 370 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
590 mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, 371 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
591 AHCLKRDIV(div - 1), AHCLKRDIV_MASK); 372 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
592 break; 373 break;
593 374
594 case 1: /* BCLK divider */ 375 case 1: /* BCLK divider */
595 mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, 376 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
596 ACLKXDIV(div - 1), ACLKXDIV_MASK); 377 ACLKXDIV(div - 1), ACLKXDIV_MASK);
597 mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKRCTL_REG, 378 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
598 ACLKRDIV(div - 1), ACLKRDIV_MASK); 379 ACLKRDIV(div - 1), ACLKRDIV_MASK);
599 break; 380 break;
600 381
601 case 2: /* BCLK/LRCLK ratio */ 382 case 2: /* BCLK/LRCLK ratio */
602 dev->bclk_lrclk_ratio = div; 383 mcasp->bclk_lrclk_ratio = div;
603 break; 384 break;
604 385
605 default: 386 default:
@@ -612,22 +393,22 @@ static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div
612static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id, 393static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
613 unsigned int freq, int dir) 394 unsigned int freq, int dir)
614{ 395{
615 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai); 396 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
616 397
617 if (dir == SND_SOC_CLOCK_OUT) { 398 if (dir == SND_SOC_CLOCK_OUT) {
618 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); 399 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
619 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); 400 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
620 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AHCLKX); 401 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
621 } else { 402 } else {
622 mcasp_clr_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); 403 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
623 mcasp_clr_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); 404 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
624 mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AHCLKX); 405 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
625 } 406 }
626 407
627 return 0; 408 return 0;
628} 409}
629 410
630static int davinci_config_channel_size(struct davinci_audio_dev *dev, 411static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
631 int word_length) 412 int word_length)
632{ 413{
633 u32 fmt; 414 u32 fmt;
@@ -644,71 +425,68 @@ static int davinci_config_channel_size(struct davinci_audio_dev *dev,
644 * both left and right channels), so it has to be divided by number of 425 * both left and right channels), so it has to be divided by number of
645 * tdm-slots (for I2S - divided by 2). 426 * tdm-slots (for I2S - divided by 2).
646 */ 427 */
647 if (dev->bclk_lrclk_ratio) 428 if (mcasp->bclk_lrclk_ratio)
648 word_length = dev->bclk_lrclk_ratio / dev->tdm_slots; 429 word_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots;
649 430
650 /* mapping of the XSSZ bit-field as described in the datasheet */ 431 /* mapping of the XSSZ bit-field as described in the datasheet */
651 fmt = (word_length >> 1) - 1; 432 fmt = (word_length >> 1) - 1;
652 433
653 if (dev->op_mode != DAVINCI_MCASP_DIT_MODE) { 434 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
654 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, 435 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
655 RXSSZ(fmt), RXSSZ(0x0F)); 436 RXSSZ(0x0F));
656 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, 437 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
657 TXSSZ(fmt), TXSSZ(0x0F)); 438 TXSSZ(0x0F));
658 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, 439 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
659 TXROT(tx_rotate), TXROT(7)); 440 TXROT(7));
660 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, 441 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
661 RXROT(rx_rotate), RXROT(7)); 442 RXROT(7));
662 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG, 443 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
663 mask);
664 } 444 }
665 445
666 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, mask); 446 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
667 447
668 return 0; 448 return 0;
669} 449}
670 450
671static int davinci_hw_common_param(struct davinci_audio_dev *dev, int stream, 451static int davinci_hw_common_param(struct davinci_mcasp *mcasp, int stream,
672 int channels) 452 int channels)
673{ 453{
674 int i; 454 int i;
675 u8 tx_ser = 0; 455 u8 tx_ser = 0;
676 u8 rx_ser = 0; 456 u8 rx_ser = 0;
677 u8 ser; 457 u8 ser;
678 u8 slots = dev->tdm_slots; 458 u8 slots = mcasp->tdm_slots;
679 u8 max_active_serializers = (channels + slots - 1) / slots; 459 u8 max_active_serializers = (channels + slots - 1) / slots;
460 u32 reg;
680 /* Default configuration */ 461 /* Default configuration */
681 mcasp_set_bits(dev->base + DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT); 462 if (mcasp->version != MCASP_VERSION_4)
463 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
682 464
683 /* All PINS as McASP */ 465 /* All PINS as McASP */
684 mcasp_set_reg(dev->base + DAVINCI_MCASP_PFUNC_REG, 0x00000000); 466 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
685 467
686 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 468 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
687 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 469 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
688 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG, 470 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
689 TXDATADMADIS);
690 } else { 471 } else {
691 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 472 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
692 mcasp_clr_bits(dev->base + DAVINCI_MCASP_REVTCTL_REG, 473 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
693 RXDATADMADIS);
694 } 474 }
695 475
696 for (i = 0; i < dev->num_serializer; i++) { 476 for (i = 0; i < mcasp->num_serializer; i++) {
697 mcasp_set_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i), 477 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
698 dev->serial_dir[i]); 478 mcasp->serial_dir[i]);
699 if (dev->serial_dir[i] == TX_MODE && 479 if (mcasp->serial_dir[i] == TX_MODE &&
700 tx_ser < max_active_serializers) { 480 tx_ser < max_active_serializers) {
701 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, 481 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
702 AXR(i));
703 tx_ser++; 482 tx_ser++;
704 } else if (dev->serial_dir[i] == RX_MODE && 483 } else if (mcasp->serial_dir[i] == RX_MODE &&
705 rx_ser < max_active_serializers) { 484 rx_ser < max_active_serializers) {
706 mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG, 485 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
707 AXR(i));
708 rx_ser++; 486 rx_ser++;
709 } else { 487 } else {
710 mcasp_mod_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i), 488 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
711 SRMOD_INACTIVE, SRMOD_MASK); 489 SRMOD_INACTIVE, SRMOD_MASK);
712 } 490 }
713 } 491 }
714 492
@@ -718,127 +496,113 @@ static int davinci_hw_common_param(struct davinci_audio_dev *dev, int stream,
718 ser = rx_ser; 496 ser = rx_ser;
719 497
720 if (ser < max_active_serializers) { 498 if (ser < max_active_serializers) {
721 dev_warn(dev->dev, "stream has more channels (%d) than are " 499 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
722 "enabled in mcasp (%d)\n", channels, ser * slots); 500 "enabled in mcasp (%d)\n", channels, ser * slots);
723 return -EINVAL; 501 return -EINVAL;
724 } 502 }
725 503
726 if (dev->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) { 504 if (mcasp->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) {
727 if (dev->txnumevt * tx_ser > 64) 505 if (mcasp->txnumevt * tx_ser > 64)
728 dev->txnumevt = 1; 506 mcasp->txnumevt = 1;
729 507
730 switch (dev->version) { 508 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
731 case MCASP_VERSION_3: 509 mcasp_mod_bits(mcasp, reg, tx_ser, NUMDMA_MASK);
732 mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL, tx_ser, 510 mcasp_mod_bits(mcasp, reg, ((mcasp->txnumevt * tx_ser) << 8),
733 NUMDMA_MASK); 511 NUMEVT_MASK);
734 mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL,
735 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
736 break;
737 default:
738 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
739 tx_ser, NUMDMA_MASK);
740 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
741 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
742 }
743 } 512 }
744 513
745 if (dev->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) { 514 if (mcasp->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
746 if (dev->rxnumevt * rx_ser > 64) 515 if (mcasp->rxnumevt * rx_ser > 64)
747 dev->rxnumevt = 1; 516 mcasp->rxnumevt = 1;
748 switch (dev->version) { 517
749 case MCASP_VERSION_3: 518 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
750 mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL, rx_ser, 519 mcasp_mod_bits(mcasp, reg, rx_ser, NUMDMA_MASK);
751 NUMDMA_MASK); 520 mcasp_mod_bits(mcasp, reg, ((mcasp->rxnumevt * rx_ser) << 8),
752 mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL, 521 NUMEVT_MASK);
753 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
754 break;
755 default:
756 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
757 rx_ser, NUMDMA_MASK);
758 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
759 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
760 }
761 } 522 }
762 523
763 return 0; 524 return 0;
764} 525}
765 526
766static void davinci_hw_param(struct davinci_audio_dev *dev, int stream) 527static void davinci_hw_param(struct davinci_mcasp *mcasp, int stream)
767{ 528{
768 int i, active_slots; 529 int i, active_slots;
769 u32 mask = 0; 530 u32 mask = 0;
531 u32 busel = 0;
770 532
771 active_slots = (dev->tdm_slots > 31) ? 32 : dev->tdm_slots; 533 active_slots = (mcasp->tdm_slots > 31) ? 32 : mcasp->tdm_slots;
772 for (i = 0; i < active_slots; i++) 534 for (i = 0; i < active_slots; i++)
773 mask |= (1 << i); 535 mask |= (1 << i);
774 536
775 mcasp_clr_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); 537 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
538
539 if (!mcasp->dat_port)
540 busel = TXSEL;
776 541
777 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 542 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
778 /* bit stream is MSB first with no delay */ 543 /* bit stream is MSB first with no delay */
779 /* DSP_B mode */ 544 /* DSP_B mode */
780 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, mask); 545 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
781 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXORD); 546 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
782 547
783 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32)) 548 if ((mcasp->tdm_slots >= 2) && (mcasp->tdm_slots <= 32))
784 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, 549 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
785 FSXMOD(dev->tdm_slots), FSXMOD(0x1FF)); 550 FSXMOD(mcasp->tdm_slots), FSXMOD(0x1FF));
786 else 551 else
787 printk(KERN_ERR "playback tdm slot %d not supported\n", 552 printk(KERN_ERR "playback tdm slot %d not supported\n",
788 dev->tdm_slots); 553 mcasp->tdm_slots);
789 } else { 554 } else {
790 /* bit stream is MSB first with no delay */ 555 /* bit stream is MSB first with no delay */
791 /* DSP_B mode */ 556 /* DSP_B mode */
792 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXORD); 557 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
793 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXTDM_REG, mask); 558 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
794 559
795 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32)) 560 if ((mcasp->tdm_slots >= 2) && (mcasp->tdm_slots <= 32))
796 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, 561 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
797 FSRMOD(dev->tdm_slots), FSRMOD(0x1FF)); 562 FSRMOD(mcasp->tdm_slots), FSRMOD(0x1FF));
798 else 563 else
799 printk(KERN_ERR "capture tdm slot %d not supported\n", 564 printk(KERN_ERR "capture tdm slot %d not supported\n",
800 dev->tdm_slots); 565 mcasp->tdm_slots);
801 } 566 }
802} 567}
803 568
804/* S/PDIF */ 569/* S/PDIF */
805static void davinci_hw_dit_param(struct davinci_audio_dev *dev) 570static void davinci_hw_dit_param(struct davinci_mcasp *mcasp)
806{ 571{
807 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0 572 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
808 and LSB first */ 573 and LSB first */
809 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, 574 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
810 TXROT(6) | TXSSZ(15));
811 575
812 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */ 576 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
813 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXFMCTL_REG, 577 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
814 AFSXE | FSXMOD(0x180));
815 578
816 /* Set the TX tdm : for all the slots */ 579 /* Set the TX tdm : for all the slots */
817 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF); 580 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
818 581
819 /* Set the TX clock controls : div = 1 and internal */ 582 /* Set the TX clock controls : div = 1 and internal */
820 mcasp_set_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, 583 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
821 ACLKXE | TX_ASYNC);
822 584
823 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); 585 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
824 586
825 /* Only 44100 and 48000 are valid, both have the same setting */ 587 /* Only 44100 and 48000 are valid, both have the same setting */
826 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3)); 588 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
827 589
828 /* Enable the DIT */ 590 /* Enable the DIT */
829 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXDITCTL_REG, DITEN); 591 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
830} 592}
831 593
832static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream, 594static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
833 struct snd_pcm_hw_params *params, 595 struct snd_pcm_hw_params *params,
834 struct snd_soc_dai *cpu_dai) 596 struct snd_soc_dai *cpu_dai)
835{ 597{
836 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai); 598 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
837 struct davinci_pcm_dma_params *dma_params = 599 struct davinci_pcm_dma_params *dma_params =
838 &dev->dma_params[substream->stream]; 600 &mcasp->dma_params[substream->stream];
601 struct snd_dmaengine_dai_dma_data *dma_data =
602 &mcasp->dma_data[substream->stream];
839 int word_length; 603 int word_length;
840 u8 fifo_level; 604 u8 fifo_level;
841 u8 slots = dev->tdm_slots; 605 u8 slots = mcasp->tdm_slots;
842 u8 active_serializers; 606 u8 active_serializers;
843 int channels; 607 int channels;
844 struct snd_interval *pcm_channels = hw_param_interval(params, 608 struct snd_interval *pcm_channels = hw_param_interval(params,
@@ -847,17 +611,17 @@ static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
847 611
848 active_serializers = (channels + slots - 1) / slots; 612 active_serializers = (channels + slots - 1) / slots;
849 613
850 if (davinci_hw_common_param(dev, substream->stream, channels) == -EINVAL) 614 if (davinci_hw_common_param(mcasp, substream->stream, channels) == -EINVAL)
851 return -EINVAL; 615 return -EINVAL;
852 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 616 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
853 fifo_level = dev->txnumevt * active_serializers; 617 fifo_level = mcasp->txnumevt * active_serializers;
854 else 618 else
855 fifo_level = dev->rxnumevt * active_serializers; 619 fifo_level = mcasp->rxnumevt * active_serializers;
856 620
857 if (dev->op_mode == DAVINCI_MCASP_DIT_MODE) 621 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
858 davinci_hw_dit_param(dev); 622 davinci_hw_dit_param(mcasp);
859 else 623 else
860 davinci_hw_param(dev, substream->stream); 624 davinci_hw_param(mcasp, substream->stream);
861 625
862 switch (params_format(params)) { 626 switch (params_format(params)) {
863 case SNDRV_PCM_FORMAT_U8: 627 case SNDRV_PCM_FORMAT_U8:
@@ -891,13 +655,15 @@ static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
891 return -EINVAL; 655 return -EINVAL;
892 } 656 }
893 657
894 if (dev->version == MCASP_VERSION_2 && !fifo_level) 658 if (mcasp->version == MCASP_VERSION_2 && !fifo_level)
895 dma_params->acnt = 4; 659 dma_params->acnt = 4;
896 else 660 else
897 dma_params->acnt = dma_params->data_type; 661 dma_params->acnt = dma_params->data_type;
898 662
899 dma_params->fifo_level = fifo_level; 663 dma_params->fifo_level = fifo_level;
900 davinci_config_channel_size(dev, word_length); 664 dma_data->maxburst = fifo_level;
665
666 davinci_config_channel_size(mcasp, word_length);
901 667
902 return 0; 668 return 0;
903} 669}
@@ -905,29 +671,29 @@ static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
905static int davinci_mcasp_trigger(struct snd_pcm_substream *substream, 671static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
906 int cmd, struct snd_soc_dai *cpu_dai) 672 int cmd, struct snd_soc_dai *cpu_dai)
907{ 673{
908 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai); 674 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
909 int ret = 0; 675 int ret = 0;
910 676
911 switch (cmd) { 677 switch (cmd) {
912 case SNDRV_PCM_TRIGGER_RESUME: 678 case SNDRV_PCM_TRIGGER_RESUME:
913 case SNDRV_PCM_TRIGGER_START: 679 case SNDRV_PCM_TRIGGER_START:
914 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 680 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
915 ret = pm_runtime_get_sync(dev->dev); 681 ret = pm_runtime_get_sync(mcasp->dev);
916 if (IS_ERR_VALUE(ret)) 682 if (IS_ERR_VALUE(ret))
917 dev_err(dev->dev, "pm_runtime_get_sync() failed\n"); 683 dev_err(mcasp->dev, "pm_runtime_get_sync() failed\n");
918 davinci_mcasp_start(dev, substream->stream); 684 davinci_mcasp_start(mcasp, substream->stream);
919 break; 685 break;
920 686
921 case SNDRV_PCM_TRIGGER_SUSPEND: 687 case SNDRV_PCM_TRIGGER_SUSPEND:
922 davinci_mcasp_stop(dev, substream->stream); 688 davinci_mcasp_stop(mcasp, substream->stream);
923 ret = pm_runtime_put_sync(dev->dev); 689 ret = pm_runtime_put_sync(mcasp->dev);
924 if (IS_ERR_VALUE(ret)) 690 if (IS_ERR_VALUE(ret))
925 dev_err(dev->dev, "pm_runtime_put_sync() failed\n"); 691 dev_err(mcasp->dev, "pm_runtime_put_sync() failed\n");
926 break; 692 break;
927 693
928 case SNDRV_PCM_TRIGGER_STOP: 694 case SNDRV_PCM_TRIGGER_STOP:
929 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 695 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
930 davinci_mcasp_stop(dev, substream->stream); 696 davinci_mcasp_stop(mcasp, substream->stream);
931 break; 697 break;
932 698
933 default: 699 default:
@@ -940,9 +706,14 @@ static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
940static int davinci_mcasp_startup(struct snd_pcm_substream *substream, 706static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
941 struct snd_soc_dai *dai) 707 struct snd_soc_dai *dai)
942{ 708{
943 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai); 709 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
710
711 if (mcasp->version == MCASP_VERSION_4)
712 snd_soc_dai_set_dma_data(dai, substream,
713 &mcasp->dma_data[substream->stream]);
714 else
715 snd_soc_dai_set_dma_data(dai, substream, mcasp->dma_params);
944 716
945 snd_soc_dai_set_dma_data(dai, substream, dev->dma_params);
946 return 0; 717 return 0;
947} 718}
948 719
@@ -955,6 +726,8 @@ static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
955 .set_sysclk = davinci_mcasp_set_sysclk, 726 .set_sysclk = davinci_mcasp_set_sysclk,
956}; 727};
957 728
729#define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
730
958#define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \ 731#define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
959 SNDRV_PCM_FMTBIT_U8 | \ 732 SNDRV_PCM_FMTBIT_U8 | \
960 SNDRV_PCM_FMTBIT_S16_LE | \ 733 SNDRV_PCM_FMTBIT_S16_LE | \
@@ -985,7 +758,7 @@ static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
985 758
986 }, 759 },
987 { 760 {
988 "davinci-mcasp.1", 761 .name = "davinci-mcasp.1",
989 .playback = { 762 .playback = {
990 .channels_min = 1, 763 .channels_min = 1,
991 .channels_max = 384, 764 .channels_max = 384,
@@ -1016,13 +789,20 @@ static struct snd_platform_data da830_mcasp_pdata = {
1016 .version = MCASP_VERSION_2, 789 .version = MCASP_VERSION_2,
1017}; 790};
1018 791
1019static struct snd_platform_data omap2_mcasp_pdata = { 792static struct snd_platform_data am33xx_mcasp_pdata = {
1020 .tx_dma_offset = 0, 793 .tx_dma_offset = 0,
1021 .rx_dma_offset = 0, 794 .rx_dma_offset = 0,
1022 .asp_chan_q = EVENTQ_0, 795 .asp_chan_q = EVENTQ_0,
1023 .version = MCASP_VERSION_3, 796 .version = MCASP_VERSION_3,
1024}; 797};
1025 798
799static struct snd_platform_data dra7_mcasp_pdata = {
800 .tx_dma_offset = 0x200,
801 .rx_dma_offset = 0x284,
802 .asp_chan_q = EVENTQ_0,
803 .version = MCASP_VERSION_4,
804};
805
1026static const struct of_device_id mcasp_dt_ids[] = { 806static const struct of_device_id mcasp_dt_ids[] = {
1027 { 807 {
1028 .compatible = "ti,dm646x-mcasp-audio", 808 .compatible = "ti,dm646x-mcasp-audio",
@@ -1034,12 +814,56 @@ static const struct of_device_id mcasp_dt_ids[] = {
1034 }, 814 },
1035 { 815 {
1036 .compatible = "ti,am33xx-mcasp-audio", 816 .compatible = "ti,am33xx-mcasp-audio",
1037 .data = &omap2_mcasp_pdata, 817 .data = &am33xx_mcasp_pdata,
818 },
819 {
820 .compatible = "ti,dra7-mcasp-audio",
821 .data = &dra7_mcasp_pdata,
1038 }, 822 },
1039 { /* sentinel */ } 823 { /* sentinel */ }
1040}; 824};
1041MODULE_DEVICE_TABLE(of, mcasp_dt_ids); 825MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1042 826
827static int mcasp_reparent_fck(struct platform_device *pdev)
828{
829 struct device_node *node = pdev->dev.of_node;
830 struct clk *gfclk, *parent_clk;
831 const char *parent_name;
832 int ret;
833
834 if (!node)
835 return 0;
836
837 parent_name = of_get_property(node, "fck_parent", NULL);
838 if (!parent_name)
839 return 0;
840
841 gfclk = clk_get(&pdev->dev, "fck");
842 if (IS_ERR(gfclk)) {
843 dev_err(&pdev->dev, "failed to get fck\n");
844 return PTR_ERR(gfclk);
845 }
846
847 parent_clk = clk_get(NULL, parent_name);
848 if (IS_ERR(parent_clk)) {
849 dev_err(&pdev->dev, "failed to get parent clock\n");
850 ret = PTR_ERR(parent_clk);
851 goto err1;
852 }
853
854 ret = clk_set_parent(gfclk, parent_clk);
855 if (ret) {
856 dev_err(&pdev->dev, "failed to reparent fck\n");
857 goto err2;
858 }
859
860err2:
861 clk_put(parent_clk);
862err1:
863 clk_put(gfclk);
864 return ret;
865}
866
1043static struct snd_platform_data *davinci_mcasp_set_pdata_from_of( 867static struct snd_platform_data *davinci_mcasp_set_pdata_from_of(
1044 struct platform_device *pdev) 868 struct platform_device *pdev)
1045{ 869{
@@ -1152,7 +976,7 @@ static int davinci_mcasp_probe(struct platform_device *pdev)
1152 struct davinci_pcm_dma_params *dma_data; 976 struct davinci_pcm_dma_params *dma_data;
1153 struct resource *mem, *ioarea, *res, *dat; 977 struct resource *mem, *ioarea, *res, *dat;
1154 struct snd_platform_data *pdata; 978 struct snd_platform_data *pdata;
1155 struct davinci_audio_dev *dev; 979 struct davinci_mcasp *mcasp;
1156 int ret; 980 int ret;
1157 981
1158 if (!pdev->dev.platform_data && !pdev->dev.of_node) { 982 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
@@ -1160,9 +984,9 @@ static int davinci_mcasp_probe(struct platform_device *pdev)
1160 return -EINVAL; 984 return -EINVAL;
1161 } 985 }
1162 986
1163 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_audio_dev), 987 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
1164 GFP_KERNEL); 988 GFP_KERNEL);
1165 if (!dev) 989 if (!mcasp)
1166 return -ENOMEM; 990 return -ENOMEM;
1167 991
1168 pdata = davinci_mcasp_set_pdata_from_of(pdev); 992 pdata = davinci_mcasp_set_pdata_from_of(pdev);
@@ -1173,7 +997,7 @@ static int davinci_mcasp_probe(struct platform_device *pdev)
1173 997
1174 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); 998 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1175 if (!mem) { 999 if (!mem) {
1176 dev_warn(dev->dev, 1000 dev_warn(mcasp->dev,
1177 "\"mpu\" mem resource not found, using index 0\n"); 1001 "\"mpu\" mem resource not found, using index 0\n");
1178 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1002 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1179 if (!mem) { 1003 if (!mem) {
@@ -1197,32 +1021,39 @@ static int davinci_mcasp_probe(struct platform_device *pdev)
1197 return ret; 1021 return ret;
1198 } 1022 }
1199 1023
1200 dev->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem)); 1024 mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
1201 if (!dev->base) { 1025 if (!mcasp->base) {
1202 dev_err(&pdev->dev, "ioremap failed\n"); 1026 dev_err(&pdev->dev, "ioremap failed\n");
1203 ret = -ENOMEM; 1027 ret = -ENOMEM;
1204 goto err_release_clk; 1028 goto err_release_clk;
1205 } 1029 }
1206 1030
1207 dev->op_mode = pdata->op_mode; 1031 mcasp->op_mode = pdata->op_mode;
1208 dev->tdm_slots = pdata->tdm_slots; 1032 mcasp->tdm_slots = pdata->tdm_slots;
1209 dev->num_serializer = pdata->num_serializer; 1033 mcasp->num_serializer = pdata->num_serializer;
1210 dev->serial_dir = pdata->serial_dir; 1034 mcasp->serial_dir = pdata->serial_dir;
1211 dev->version = pdata->version; 1035 mcasp->version = pdata->version;
1212 dev->txnumevt = pdata->txnumevt; 1036 mcasp->txnumevt = pdata->txnumevt;
1213 dev->rxnumevt = pdata->rxnumevt; 1037 mcasp->rxnumevt = pdata->rxnumevt;
1214 dev->dev = &pdev->dev; 1038
1039 mcasp->dev = &pdev->dev;
1215 1040
1216 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); 1041 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
1217 if (!dat) 1042 if (dat)
1218 dat = mem; 1043 mcasp->dat_port = true;
1219 1044
1220 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]; 1045 dma_data = &mcasp->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
1221 dma_data->asp_chan_q = pdata->asp_chan_q; 1046 dma_data->asp_chan_q = pdata->asp_chan_q;
1222 dma_data->ram_chan_q = pdata->ram_chan_q; 1047 dma_data->ram_chan_q = pdata->ram_chan_q;
1223 dma_data->sram_pool = pdata->sram_pool; 1048 dma_data->sram_pool = pdata->sram_pool;
1224 dma_data->sram_size = pdata->sram_size_playback; 1049 dma_data->sram_size = pdata->sram_size_playback;
1225 dma_data->dma_addr = dat->start + pdata->tx_dma_offset; 1050 if (dat)
1051 dma_data->dma_addr = dat->start;
1052 else
1053 dma_data->dma_addr = mem->start + pdata->tx_dma_offset;
1054
1055 /* Unconditional dmaengine stuff */
1056 mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr = dma_data->dma_addr;
1226 1057
1227 res = platform_get_resource(pdev, IORESOURCE_DMA, 0); 1058 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1228 if (res) 1059 if (res)
@@ -1230,12 +1061,26 @@ static int davinci_mcasp_probe(struct platform_device *pdev)
1230 else 1061 else
1231 dma_data->channel = pdata->tx_dma_channel; 1062 dma_data->channel = pdata->tx_dma_channel;
1232 1063
1233 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]; 1064 dma_data = &mcasp->dma_params[SNDRV_PCM_STREAM_CAPTURE];
1234 dma_data->asp_chan_q = pdata->asp_chan_q; 1065 dma_data->asp_chan_q = pdata->asp_chan_q;
1235 dma_data->ram_chan_q = pdata->ram_chan_q; 1066 dma_data->ram_chan_q = pdata->ram_chan_q;
1236 dma_data->sram_pool = pdata->sram_pool; 1067 dma_data->sram_pool = pdata->sram_pool;
1237 dma_data->sram_size = pdata->sram_size_capture; 1068 dma_data->sram_size = pdata->sram_size_capture;
1238 dma_data->dma_addr = dat->start + pdata->rx_dma_offset; 1069 if (dat)
1070 dma_data->dma_addr = dat->start;
1071 else
1072 dma_data->dma_addr = mem->start + pdata->rx_dma_offset;
1073
1074 /* Unconditional dmaengine stuff */
1075 mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr = dma_data->dma_addr;
1076
1077 if (mcasp->version < MCASP_VERSION_3) {
1078 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
1079 /* dma_data->dma_addr is pointing to the data port address */
1080 mcasp->dat_port = true;
1081 } else {
1082 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
1083 }
1239 1084
1240 res = platform_get_resource(pdev, IORESOURCE_DMA, 1); 1085 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1241 if (res) 1086 if (res)
@@ -1243,17 +1088,26 @@ static int davinci_mcasp_probe(struct platform_device *pdev)
1243 else 1088 else
1244 dma_data->channel = pdata->rx_dma_channel; 1089 dma_data->channel = pdata->rx_dma_channel;
1245 1090
1246 dev_set_drvdata(&pdev->dev, dev); 1091 /* Unconditional dmaengine stuff */
1092 mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data = "tx";
1093 mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE].filter_data = "rx";
1094
1095 dev_set_drvdata(&pdev->dev, mcasp);
1096
1097 mcasp_reparent_fck(pdev);
1098
1247 ret = snd_soc_register_component(&pdev->dev, &davinci_mcasp_component, 1099 ret = snd_soc_register_component(&pdev->dev, &davinci_mcasp_component,
1248 &davinci_mcasp_dai[pdata->op_mode], 1); 1100 &davinci_mcasp_dai[pdata->op_mode], 1);
1249 1101
1250 if (ret != 0) 1102 if (ret != 0)
1251 goto err_release_clk; 1103 goto err_release_clk;
1252 1104
1253 ret = davinci_soc_platform_register(&pdev->dev); 1105 if (mcasp->version != MCASP_VERSION_4) {
1254 if (ret) { 1106 ret = davinci_soc_platform_register(&pdev->dev);
1255 dev_err(&pdev->dev, "register PCM failed: %d\n", ret); 1107 if (ret) {
1256 goto err_unregister_component; 1108 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
1109 goto err_unregister_component;
1110 }
1257 } 1111 }
1258 1112
1259 return 0; 1113 return 0;
@@ -1268,9 +1122,11 @@ err_release_clk:
1268 1122
1269static int davinci_mcasp_remove(struct platform_device *pdev) 1123static int davinci_mcasp_remove(struct platform_device *pdev)
1270{ 1124{
1125 struct davinci_mcasp *mcasp = dev_get_drvdata(&pdev->dev);
1271 1126
1272 snd_soc_unregister_component(&pdev->dev); 1127 snd_soc_unregister_component(&pdev->dev);
1273 davinci_soc_platform_unregister(&pdev->dev); 1128 if (mcasp->version != MCASP_VERSION_4)
1129 davinci_soc_platform_unregister(&pdev->dev);
1274 1130
1275 pm_runtime_put_sync(&pdev->dev); 1131 pm_runtime_put_sync(&pdev->dev);
1276 pm_runtime_disable(&pdev->dev); 1132 pm_runtime_disable(&pdev->dev);
@@ -1281,32 +1137,30 @@ static int davinci_mcasp_remove(struct platform_device *pdev)
1281#ifdef CONFIG_PM_SLEEP 1137#ifdef CONFIG_PM_SLEEP
1282static int davinci_mcasp_suspend(struct device *dev) 1138static int davinci_mcasp_suspend(struct device *dev)
1283{ 1139{
1284 struct davinci_audio_dev *a = dev_get_drvdata(dev); 1140 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
1285 void __iomem *base = a->base;
1286 1141
1287 a->context.txfmtctl = mcasp_get_reg(base + DAVINCI_MCASP_TXFMCTL_REG); 1142 mcasp->context.txfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG);
1288 a->context.rxfmtctl = mcasp_get_reg(base + DAVINCI_MCASP_RXFMCTL_REG); 1143 mcasp->context.rxfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
1289 a->context.txfmt = mcasp_get_reg(base + DAVINCI_MCASP_TXFMT_REG); 1144 mcasp->context.txfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMT_REG);
1290 a->context.rxfmt = mcasp_get_reg(base + DAVINCI_MCASP_RXFMT_REG); 1145 mcasp->context.rxfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMT_REG);
1291 a->context.aclkxctl = mcasp_get_reg(base + DAVINCI_MCASP_ACLKXCTL_REG); 1146 mcasp->context.aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
1292 a->context.aclkrctl = mcasp_get_reg(base + DAVINCI_MCASP_ACLKRCTL_REG); 1147 mcasp->context.aclkrctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG);
1293 a->context.pdir = mcasp_get_reg(base + DAVINCI_MCASP_PDIR_REG); 1148 mcasp->context.pdir = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);
1294 1149
1295 return 0; 1150 return 0;
1296} 1151}
1297 1152
1298static int davinci_mcasp_resume(struct device *dev) 1153static int davinci_mcasp_resume(struct device *dev)
1299{ 1154{
1300 struct davinci_audio_dev *a = dev_get_drvdata(dev); 1155 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
1301 void __iomem *base = a->base; 1156
1302 1157 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, mcasp->context.txfmtctl);
1303 mcasp_set_reg(base + DAVINCI_MCASP_TXFMCTL_REG, a->context.txfmtctl); 1158 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG, mcasp->context.rxfmtctl);
1304 mcasp_set_reg(base + DAVINCI_MCASP_RXFMCTL_REG, a->context.rxfmtctl); 1159 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMT_REG, mcasp->context.txfmt);
1305 mcasp_set_reg(base + DAVINCI_MCASP_TXFMT_REG, a->context.txfmt); 1160 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMT_REG, mcasp->context.rxfmt);
1306 mcasp_set_reg(base + DAVINCI_MCASP_RXFMT_REG, a->context.rxfmt); 1161 mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, mcasp->context.aclkxctl);
1307 mcasp_set_reg(base + DAVINCI_MCASP_ACLKXCTL_REG, a->context.aclkxctl); 1162 mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, mcasp->context.aclkrctl);
1308 mcasp_set_reg(base + DAVINCI_MCASP_ACLKRCTL_REG, a->context.aclkrctl); 1163 mcasp_set_reg(mcasp, DAVINCI_MCASP_PDIR_REG, mcasp->context.pdir);
1309 mcasp_set_reg(base + DAVINCI_MCASP_PDIR_REG, a->context.pdir);
1310 1164
1311 return 0; 1165 return 0;
1312} 1166}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-26 14:45:47 -0500