aboutsummaryrefslogtreecommitdiffstats
path: root/include
diff options
context:
space:
mode:
Diffstat (limited to 'include')
-rw-r--r--include/dt-bindings/clock/imx6sl-clock.h148
-rw-r--r--include/dt-bindings/clock/vf610-clock.h163
-rw-r--r--include/linux/arm-cci.h61
-rw-r--r--include/linux/clk/mvebu.h22
-rw-r--r--include/linux/clk/zynq.h8
-rw-r--r--include/linux/dw_apb_timer.h1
-rw-r--r--include/linux/mfd/davinci_voicecodec.h3
-rw-r--r--include/linux/mfd/syscon/clps711x.h94
-rw-r--r--include/linux/platform_data/edma.h183
-rw-r--r--include/linux/platform_data/gpio-rcar.h5
-rw-r--r--include/linux/platform_data/pinctrl-coh901.h22
-rw-r--r--include/linux/platform_data/spi-davinci.h2
-rw-r--r--include/linux/platform_data/usb-rcar-phy.h28
-rw-r--r--include/linux/usb/ehci_pdriver.h4
14 files changed, 694 insertions, 50 deletions
diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h
new file mode 100644
index 000000000000..7fcdf90879f2
--- /dev/null
+++ b/include/dt-bindings/clock/imx6sl-clock.h
@@ -0,0 +1,148 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#ifndef __DT_BINDINGS_CLOCK_IMX6SL_H
11#define __DT_BINDINGS_CLOCK_IMX6SL_H
12
13#define IMX6SL_CLK_DUMMY 0
14#define IMX6SL_CLK_CKIL 1
15#define IMX6SL_CLK_OSC 2
16#define IMX6SL_CLK_PLL1_SYS 3
17#define IMX6SL_CLK_PLL2_BUS 4
18#define IMX6SL_CLK_PLL3_USB_OTG 5
19#define IMX6SL_CLK_PLL4_AUDIO 6
20#define IMX6SL_CLK_PLL5_VIDEO 7
21#define IMX6SL_CLK_PLL6_ENET 8
22#define IMX6SL_CLK_PLL7_USB_HOST 9
23#define IMX6SL_CLK_USBPHY1 10
24#define IMX6SL_CLK_USBPHY2 11
25#define IMX6SL_CLK_USBPHY1_GATE 12
26#define IMX6SL_CLK_USBPHY2_GATE 13
27#define IMX6SL_CLK_PLL4_POST_DIV 14
28#define IMX6SL_CLK_PLL5_POST_DIV 15
29#define IMX6SL_CLK_PLL5_VIDEO_DIV 16
30#define IMX6SL_CLK_ENET_REF 17
31#define IMX6SL_CLK_PLL2_PFD0 18
32#define IMX6SL_CLK_PLL2_PFD1 19
33#define IMX6SL_CLK_PLL2_PFD2 20
34#define IMX6SL_CLK_PLL3_PFD0 21
35#define IMX6SL_CLK_PLL3_PFD1 22
36#define IMX6SL_CLK_PLL3_PFD2 23
37#define IMX6SL_CLK_PLL3_PFD3 24
38#define IMX6SL_CLK_PLL2_198M 25
39#define IMX6SL_CLK_PLL3_120M 26
40#define IMX6SL_CLK_PLL3_80M 27
41#define IMX6SL_CLK_PLL3_60M 28
42#define IMX6SL_CLK_STEP 29
43#define IMX6SL_CLK_PLL1_SW 30
44#define IMX6SL_CLK_OCRAM_ALT_SEL 31
45#define IMX6SL_CLK_OCRAM_SEL 32
46#define IMX6SL_CLK_PRE_PERIPH2_SEL 33
47#define IMX6SL_CLK_PRE_PERIPH_SEL 34
48#define IMX6SL_CLK_PERIPH2_CLK2_SEL 35
49#define IMX6SL_CLK_PERIPH_CLK2_SEL 36
50#define IMX6SL_CLK_CSI_SEL 37
51#define IMX6SL_CLK_LCDIF_AXI_SEL 38
52#define IMX6SL_CLK_USDHC1_SEL 39
53#define IMX6SL_CLK_USDHC2_SEL 40
54#define IMX6SL_CLK_USDHC3_SEL 41
55#define IMX6SL_CLK_USDHC4_SEL 42
56#define IMX6SL_CLK_SSI1_SEL 43
57#define IMX6SL_CLK_SSI2_SEL 44
58#define IMX6SL_CLK_SSI3_SEL 45
59#define IMX6SL_CLK_PERCLK_SEL 46
60#define IMX6SL_CLK_PXP_AXI_SEL 47
61#define IMX6SL_CLK_EPDC_AXI_SEL 48
62#define IMX6SL_CLK_GPU2D_OVG_SEL 49
63#define IMX6SL_CLK_GPU2D_SEL 50
64#define IMX6SL_CLK_LCDIF_PIX_SEL 51
65#define IMX6SL_CLK_EPDC_PIX_SEL 52
66#define IMX6SL_CLK_SPDIF0_SEL 53
67#define IMX6SL_CLK_SPDIF1_SEL 54
68#define IMX6SL_CLK_EXTERN_AUDIO_SEL 55
69#define IMX6SL_CLK_ECSPI_SEL 56
70#define IMX6SL_CLK_UART_SEL 57
71#define IMX6SL_CLK_PERIPH 58
72#define IMX6SL_CLK_PERIPH2 59
73#define IMX6SL_CLK_OCRAM_PODF 60
74#define IMX6SL_CLK_PERIPH_CLK2_PODF 61
75#define IMX6SL_CLK_PERIPH2_CLK2_PODF 62
76#define IMX6SL_CLK_IPG 63
77#define IMX6SL_CLK_CSI_PODF 64
78#define IMX6SL_CLK_LCDIF_AXI_PODF 65
79#define IMX6SL_CLK_USDHC1_PODF 66
80#define IMX6SL_CLK_USDHC2_PODF 67
81#define IMX6SL_CLK_USDHC3_PODF 68
82#define IMX6SL_CLK_USDHC4_PODF 69
83#define IMX6SL_CLK_SSI1_PRED 70
84#define IMX6SL_CLK_SSI1_PODF 71
85#define IMX6SL_CLK_SSI2_PRED 72
86#define IMX6SL_CLK_SSI2_PODF 73
87#define IMX6SL_CLK_SSI3_PRED 74
88#define IMX6SL_CLK_SSI3_PODF 75
89#define IMX6SL_CLK_PERCLK 76
90#define IMX6SL_CLK_PXP_AXI_PODF 77
91#define IMX6SL_CLK_EPDC_AXI_PODF 78
92#define IMX6SL_CLK_GPU2D_OVG_PODF 79
93#define IMX6SL_CLK_GPU2D_PODF 80
94#define IMX6SL_CLK_LCDIF_PIX_PRED 81
95#define IMX6SL_CLK_EPDC_PIX_PRED 82
96#define IMX6SL_CLK_LCDIF_PIX_PODF 83
97#define IMX6SL_CLK_EPDC_PIX_PODF 84
98#define IMX6SL_CLK_SPDIF0_PRED 85
99#define IMX6SL_CLK_SPDIF0_PODF 86
100#define IMX6SL_CLK_SPDIF1_PRED 87
101#define IMX6SL_CLK_SPDIF1_PODF 88
102#define IMX6SL_CLK_EXTERN_AUDIO_PRED 89
103#define IMX6SL_CLK_EXTERN_AUDIO_PODF 90
104#define IMX6SL_CLK_ECSPI_ROOT 91
105#define IMX6SL_CLK_UART_ROOT 92
106#define IMX6SL_CLK_AHB 93
107#define IMX6SL_CLK_MMDC_ROOT 94
108#define IMX6SL_CLK_ARM 95
109#define IMX6SL_CLK_ECSPI1 96
110#define IMX6SL_CLK_ECSPI2 97
111#define IMX6SL_CLK_ECSPI3 98
112#define IMX6SL_CLK_ECSPI4 99
113#define IMX6SL_CLK_EPIT1 100
114#define IMX6SL_CLK_EPIT2 101
115#define IMX6SL_CLK_EXTERN_AUDIO 102
116#define IMX6SL_CLK_GPT 103
117#define IMX6SL_CLK_GPT_SERIAL 104
118#define IMX6SL_CLK_GPU2D_OVG 105
119#define IMX6SL_CLK_I2C1 106
120#define IMX6SL_CLK_I2C2 107
121#define IMX6SL_CLK_I2C3 108
122#define IMX6SL_CLK_OCOTP 109
123#define IMX6SL_CLK_CSI 110
124#define IMX6SL_CLK_PXP_AXI 111
125#define IMX6SL_CLK_EPDC_AXI 112
126#define IMX6SL_CLK_LCDIF_AXI 113
127#define IMX6SL_CLK_LCDIF_PIX 114
128#define IMX6SL_CLK_EPDC_PIX 115
129#define IMX6SL_CLK_OCRAM 116
130#define IMX6SL_CLK_PWM1 117
131#define IMX6SL_CLK_PWM2 118
132#define IMX6SL_CLK_PWM3 119
133#define IMX6SL_CLK_PWM4 120
134#define IMX6SL_CLK_SDMA 121
135#define IMX6SL_CLK_SPDIF 122
136#define IMX6SL_CLK_SSI1 123
137#define IMX6SL_CLK_SSI2 124
138#define IMX6SL_CLK_SSI3 125
139#define IMX6SL_CLK_UART 126
140#define IMX6SL_CLK_UART_SERIAL 127
141#define IMX6SL_CLK_USBOH3 128
142#define IMX6SL_CLK_USDHC1 129
143#define IMX6SL_CLK_USDHC2 130
144#define IMX6SL_CLK_USDHC3 131
145#define IMX6SL_CLK_USDHC4 132
146#define IMX6SL_CLK_CLK_END 133
147
148#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h
new file mode 100644
index 000000000000..15e997fa78f2
--- /dev/null
+++ b/include/dt-bindings/clock/vf610-clock.h
@@ -0,0 +1,163 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#ifndef __DT_BINDINGS_CLOCK_VF610_H
11#define __DT_BINDINGS_CLOCK_VF610_H
12
13#define VF610_CLK_DUMMY 0
14#define VF610_CLK_SIRC_128K 1
15#define VF610_CLK_SIRC_32K 2
16#define VF610_CLK_FIRC 3
17#define VF610_CLK_SXOSC 4
18#define VF610_CLK_FXOSC 5
19#define VF610_CLK_FXOSC_HALF 6
20#define VF610_CLK_SLOW_CLK_SEL 7
21#define VF610_CLK_FASK_CLK_SEL 8
22#define VF610_CLK_AUDIO_EXT 9
23#define VF610_CLK_ENET_EXT 10
24#define VF610_CLK_PLL1_MAIN 11
25#define VF610_CLK_PLL1_PFD1 12
26#define VF610_CLK_PLL1_PFD2 13
27#define VF610_CLK_PLL1_PFD3 14
28#define VF610_CLK_PLL1_PFD4 15
29#define VF610_CLK_PLL2_MAIN 16
30#define VF610_CLK_PLL2_PFD1 17
31#define VF610_CLK_PLL2_PFD2 18
32#define VF610_CLK_PLL2_PFD3 19
33#define VF610_CLK_PLL2_PFD4 20
34#define VF610_CLK_PLL3_MAIN 21
35#define VF610_CLK_PLL3_PFD1 22
36#define VF610_CLK_PLL3_PFD2 23
37#define VF610_CLK_PLL3_PFD3 24
38#define VF610_CLK_PLL3_PFD4 25
39#define VF610_CLK_PLL4_MAIN 26
40#define VF610_CLK_PLL5_MAIN 27
41#define VF610_CLK_PLL6_MAIN 28
42#define VF610_CLK_PLL3_MAIN_DIV 29
43#define VF610_CLK_PLL4_MAIN_DIV 30
44#define VF610_CLK_PLL6_MAIN_DIV 31
45#define VF610_CLK_PLL1_PFD_SEL 32
46#define VF610_CLK_PLL2_PFD_SEL 33
47#define VF610_CLK_SYS_SEL 34
48#define VF610_CLK_DDR_SEL 35
49#define VF610_CLK_SYS_BUS 36
50#define VF610_CLK_PLATFORM_BUS 37
51#define VF610_CLK_IPG_BUS 38
52#define VF610_CLK_UART0 39
53#define VF610_CLK_UART1 40
54#define VF610_CLK_UART2 41
55#define VF610_CLK_UART3 42
56#define VF610_CLK_UART4 43
57#define VF610_CLK_UART5 44
58#define VF610_CLK_PIT 45
59#define VF610_CLK_I2C0 46
60#define VF610_CLK_I2C1 47
61#define VF610_CLK_I2C2 48
62#define VF610_CLK_I2C3 49
63#define VF610_CLK_FTM0_EXT_SEL 50
64#define VF610_CLK_FTM0_FIX_SEL 51
65#define VF610_CLK_FTM0_EXT_FIX_EN 52
66#define VF610_CLK_FTM1_EXT_SEL 53
67#define VF610_CLK_FTM1_FIX_SEL 54
68#define VF610_CLK_FTM1_EXT_FIX_EN 55
69#define VF610_CLK_FTM2_EXT_SEL 56
70#define VF610_CLK_FTM2_FIX_SEL 57
71#define VF610_CLK_FTM2_EXT_FIX_EN 58
72#define VF610_CLK_FTM3_EXT_SEL 59
73#define VF610_CLK_FTM3_FIX_SEL 60
74#define VF610_CLK_FTM3_EXT_FIX_EN 61
75#define VF610_CLK_FTM0 62
76#define VF610_CLK_FTM1 63
77#define VF610_CLK_FTM2 64
78#define VF610_CLK_FTM3 65
79#define VF610_CLK_ENET_50M 66
80#define VF610_CLK_ENET_25M 67
81#define VF610_CLK_ENET_SEL 68
82#define VF610_CLK_ENET 69
83#define VF610_CLK_ENET_TS_SEL 70
84#define VF610_CLK_ENET_TS 71
85#define VF610_CLK_DSPI0 72
86#define VF610_CLK_DSPI1 73
87#define VF610_CLK_DSPI2 74
88#define VF610_CLK_DSPI3 75
89#define VF610_CLK_WDT 76
90#define VF610_CLK_ESDHC0_SEL 77
91#define VF610_CLK_ESDHC0_EN 78
92#define VF610_CLK_ESDHC0_DIV 79
93#define VF610_CLK_ESDHC0 80
94#define VF610_CLK_ESDHC1_SEL 81
95#define VF610_CLK_ESDHC1_EN 82
96#define VF610_CLK_ESDHC1_DIV 83
97#define VF610_CLK_ESDHC1 84
98#define VF610_CLK_DCU0_SEL 85
99#define VF610_CLK_DCU0_EN 86
100#define VF610_CLK_DCU0_DIV 87
101#define VF610_CLK_DCU0 88
102#define VF610_CLK_DCU1_SEL 89
103#define VF610_CLK_DCU1_EN 90
104#define VF610_CLK_DCU1_DIV 91
105#define VF610_CLK_DCU1 92
106#define VF610_CLK_ESAI_SEL 93
107#define VF610_CLK_ESAI_EN 94
108#define VF610_CLK_ESAI_DIV 95
109#define VF610_CLK_ESAI 96
110#define VF610_CLK_SAI0_SEL 97
111#define VF610_CLK_SAI0_EN 98
112#define VF610_CLK_SAI0_DIV 99
113#define VF610_CLK_SAI0 100
114#define VF610_CLK_SAI1_SEL 101
115#define VF610_CLK_SAI1_EN 102
116#define VF610_CLK_SAI1_DIV 103
117#define VF610_CLK_SAI1 104
118#define VF610_CLK_SAI2_SEL 105
119#define VF610_CLK_SAI2_EN 106
120#define VF610_CLK_SAI2_DIV 107
121#define VF610_CLK_SAI2 108
122#define VF610_CLK_SAI3_SEL 109
123#define VF610_CLK_SAI3_EN 110
124#define VF610_CLK_SAI3_DIV 111
125#define VF610_CLK_SAI3 112
126#define VF610_CLK_USBC0 113
127#define VF610_CLK_USBC1 114
128#define VF610_CLK_QSPI0_SEL 115
129#define VF610_CLK_QSPI0_EN 116
130#define VF610_CLK_QSPI0_X4_DIV 117
131#define VF610_CLK_QSPI0_X2_DIV 118
132#define VF610_CLK_QSPI0_X1_DIV 119
133#define VF610_CLK_QSPI1_SEL 120
134#define VF610_CLK_QSPI1_EN 121
135#define VF610_CLK_QSPI1_X4_DIV 122
136#define VF610_CLK_QSPI1_X2_DIV 123
137#define VF610_CLK_QSPI1_X1_DIV 124
138#define VF610_CLK_QSPI0 125
139#define VF610_CLK_QSPI1 126
140#define VF610_CLK_NFC_SEL 127
141#define VF610_CLK_NFC_EN 128
142#define VF610_CLK_NFC_PRE_DIV 129
143#define VF610_CLK_NFC_FRAC_DIV 130
144#define VF610_CLK_NFC_INV 131
145#define VF610_CLK_NFC 132
146#define VF610_CLK_VADC_SEL 133
147#define VF610_CLK_VADC_EN 134
148#define VF610_CLK_VADC_DIV 135
149#define VF610_CLK_VADC_DIV_HALF 136
150#define VF610_CLK_VADC 137
151#define VF610_CLK_ADC0 138
152#define VF610_CLK_ADC1 139
153#define VF610_CLK_DAC0 140
154#define VF610_CLK_DAC1 141
155#define VF610_CLK_FLEXCAN0 142
156#define VF610_CLK_FLEXCAN1 143
157#define VF610_CLK_ASRC 144
158#define VF610_CLK_GPU_SEL 145
159#define VF610_CLK_GPU_EN 146
160#define VF610_CLK_GPU2D 147
161#define VF610_CLK_END 148
162
163#endif /* __DT_BINDINGS_CLOCK_VF610_H */
diff --git a/include/linux/arm-cci.h b/include/linux/arm-cci.h
new file mode 100644
index 000000000000..79d6edf446d5
--- /dev/null
+++ b/include/linux/arm-cci.h
@@ -0,0 +1,61 @@
1/*
2 * CCI cache coherent interconnect support
3 *
4 * Copyright (C) 2013 ARM Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __LINUX_ARM_CCI_H
22#define __LINUX_ARM_CCI_H
23
24#include <linux/errno.h>
25#include <linux/types.h>
26
27struct device_node;
28
29#ifdef CONFIG_ARM_CCI
30extern bool cci_probed(void);
31extern int cci_ace_get_port(struct device_node *dn);
32extern int cci_disable_port_by_cpu(u64 mpidr);
33extern int __cci_control_port_by_device(struct device_node *dn, bool enable);
34extern int __cci_control_port_by_index(u32 port, bool enable);
35#else
36static inline bool cci_probed(void) { return false; }
37static inline int cci_ace_get_port(struct device_node *dn)
38{
39 return -ENODEV;
40}
41static inline int cci_disable_port_by_cpu(u64 mpidr) { return -ENODEV; }
42static inline int __cci_control_port_by_device(struct device_node *dn,
43 bool enable)
44{
45 return -ENODEV;
46}
47static inline int __cci_control_port_by_index(u32 port, bool enable)
48{
49 return -ENODEV;
50}
51#endif
52#define cci_disable_port_by_device(dev) \
53 __cci_control_port_by_device(dev, false)
54#define cci_enable_port_by_device(dev) \
55 __cci_control_port_by_device(dev, true)
56#define cci_disable_port_by_index(dev) \
57 __cci_control_port_by_index(dev, false)
58#define cci_enable_port_by_index(dev) \
59 __cci_control_port_by_index(dev, true)
60
61#endif
diff --git a/include/linux/clk/mvebu.h b/include/linux/clk/mvebu.h
deleted file mode 100644
index 8c4ae713b063..000000000000
--- a/include/linux/clk/mvebu.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
15 */
16
17#ifndef __CLK_MVEBU_H_
18#define __CLK_MVEBU_H_
19
20void __init mvebu_clocks_init(void);
21
22#endif
diff --git a/include/linux/clk/zynq.h b/include/linux/clk/zynq.h
index 56be7cd9aa8b..e062d317ccce 100644
--- a/include/linux/clk/zynq.h
+++ b/include/linux/clk/zynq.h
@@ -1,4 +1,5 @@
1/* 1/*
2 * Copyright (C) 2013 Xilinx Inc.
2 * Copyright (C) 2012 National Instruments 3 * Copyright (C) 2012 National Instruments
3 * 4 *
4 * This program is free software; you can redistribute it and/or modify 5 * This program is free software; you can redistribute it and/or modify
@@ -19,6 +20,11 @@
19#ifndef __LINUX_CLK_ZYNQ_H_ 20#ifndef __LINUX_CLK_ZYNQ_H_
20#define __LINUX_CLK_ZYNQ_H_ 21#define __LINUX_CLK_ZYNQ_H_
21 22
22void __init xilinx_zynq_clocks_init(void __iomem *slcr); 23#include <linux/spinlock.h>
23 24
25void zynq_clock_init(void __iomem *slcr);
26
27struct clk *clk_register_zynq_pll(const char *name, const char *parent,
28 void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index,
29 spinlock_t *lock);
24#endif 30#endif
diff --git a/include/linux/dw_apb_timer.h b/include/linux/dw_apb_timer.h
index dd755ce2a5eb..07261d52a6df 100644
--- a/include/linux/dw_apb_timer.h
+++ b/include/linux/dw_apb_timer.h
@@ -53,5 +53,4 @@ void dw_apb_clocksource_start(struct dw_apb_clocksource *dw_cs);
53cycle_t dw_apb_clocksource_read(struct dw_apb_clocksource *dw_cs); 53cycle_t dw_apb_clocksource_read(struct dw_apb_clocksource *dw_cs);
54void dw_apb_clocksource_unregister(struct dw_apb_clocksource *dw_cs); 54void dw_apb_clocksource_unregister(struct dw_apb_clocksource *dw_cs);
55 55
56extern void dw_apb_timer_init(void);
57#endif /* __DW_APB_TIMER_H__ */ 56#endif /* __DW_APB_TIMER_H__ */
diff --git a/include/linux/mfd/davinci_voicecodec.h b/include/linux/mfd/davinci_voicecodec.h
index 0ab61320ffa8..7dd6524d2aac 100644
--- a/include/linux/mfd/davinci_voicecodec.h
+++ b/include/linux/mfd/davinci_voicecodec.h
@@ -26,8 +26,7 @@
26#include <linux/kernel.h> 26#include <linux/kernel.h>
27#include <linux/platform_device.h> 27#include <linux/platform_device.h>
28#include <linux/mfd/core.h> 28#include <linux/mfd/core.h>
29 29#include <linux/platform_data/edma.h>
30#include <mach/edma.h>
31 30
32/* 31/*
33 * Register values. 32 * Register values.
diff --git a/include/linux/mfd/syscon/clps711x.h b/include/linux/mfd/syscon/clps711x.h
new file mode 100644
index 000000000000..26355abae515
--- /dev/null
+++ b/include/linux/mfd/syscon/clps711x.h
@@ -0,0 +1,94 @@
1/*
2 * CLPS711X system register bits definitions
3 *
4 * Copyright (C) 2013 Alexander Shiyan <shc_work@mail.ru>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#ifndef _LINUX_MFD_SYSCON_CLPS711X_H_
13#define _LINUX_MFD_SYSCON_CLPS711X_H_
14
15#define SYSCON_OFFSET (0x00)
16#define SYSFLG_OFFSET (0x40)
17
18#define SYSCON1_KBDSCAN(x) ((x) & 15)
19#define SYSCON1_KBDSCAN_MASK (15)
20#define SYSCON1_TC1M (1 << 4)
21#define SYSCON1_TC1S (1 << 5)
22#define SYSCON1_TC2M (1 << 6)
23#define SYSCON1_TC2S (1 << 7)
24#define SYSCON1_BZTOG (1 << 9)
25#define SYSCON1_BZMOD (1 << 10)
26#define SYSCON1_DBGEN (1 << 11)
27#define SYSCON1_LCDEN (1 << 12)
28#define SYSCON1_CDENTX (1 << 13)
29#define SYSCON1_CDENRX (1 << 14)
30#define SYSCON1_SIREN (1 << 15)
31#define SYSCON1_ADCKSEL(x) (((x) & 3) << 16)
32#define SYSCON1_ADCKSEL_MASK (3 << 16)
33#define SYSCON1_EXCKEN (1 << 18)
34#define SYSCON1_WAKEDIS (1 << 19)
35#define SYSCON1_IRTXM (1 << 20)
36
37#define SYSCON2_SERSEL (1 << 0)
38#define SYSCON2_KBD6 (1 << 1)
39#define SYSCON2_DRAMZ (1 << 2)
40#define SYSCON2_KBWEN (1 << 3)
41#define SYSCON2_SS2TXEN (1 << 4)
42#define SYSCON2_PCCARD1 (1 << 5)
43#define SYSCON2_PCCARD2 (1 << 6)
44#define SYSCON2_SS2RXEN (1 << 7)
45#define SYSCON2_SS2MAEN (1 << 9)
46#define SYSCON2_OSTB (1 << 12)
47#define SYSCON2_CLKENSL (1 << 13)
48#define SYSCON2_BUZFREQ (1 << 14)
49
50#define SYSCON3_ADCCON (1 << 0)
51#define SYSCON3_CLKCTL0 (1 << 1)
52#define SYSCON3_CLKCTL1 (1 << 2)
53#define SYSCON3_DAISEL (1 << 3)
54#define SYSCON3_ADCCKNSEN (1 << 4)
55#define SYSCON3_VERSN(x) (((x) >> 5) & 7)
56#define SYSCON3_VERSN_MASK (7 << 5)
57#define SYSCON3_FASTWAKE (1 << 8)
58#define SYSCON3_DAIEN (1 << 9)
59#define SYSCON3_128FS SYSCON3_DAIEN
60#define SYSCON3_ENPD67 (1 << 10)
61
62#define SYSCON_UARTEN (1 << 8)
63
64#define SYSFLG1_MCDR (1 << 0)
65#define SYSFLG1_DCDET (1 << 1)
66#define SYSFLG1_WUDR (1 << 2)
67#define SYSFLG1_WUON (1 << 3)
68#define SYSFLG1_CTS (1 << 8)
69#define SYSFLG1_DSR (1 << 9)
70#define SYSFLG1_DCD (1 << 10)
71#define SYSFLG1_NBFLG (1 << 12)
72#define SYSFLG1_RSTFLG (1 << 13)
73#define SYSFLG1_PFFLG (1 << 14)
74#define SYSFLG1_CLDFLG (1 << 15)
75#define SYSFLG1_CRXFE (1 << 24)
76#define SYSFLG1_CTXFF (1 << 25)
77#define SYSFLG1_SSIBUSY (1 << 26)
78#define SYSFLG1_ID (1 << 29)
79#define SYSFLG1_VERID(x) (((x) >> 30) & 3)
80#define SYSFLG1_VERID_MASK (3 << 30)
81
82#define SYSFLG2_SSRXOF (1 << 0)
83#define SYSFLG2_RESVAL (1 << 1)
84#define SYSFLG2_RESFRM (1 << 2)
85#define SYSFLG2_SS2RXFE (1 << 3)
86#define SYSFLG2_SS2TXFF (1 << 4)
87#define SYSFLG2_SS2TXUF (1 << 5)
88#define SYSFLG2_CKMODE (1 << 6)
89
90#define SYSFLG_UBUSY (1 << 11)
91#define SYSFLG_URXFE (1 << 22)
92#define SYSFLG_UTXFF (1 << 23)
93
94#endif
diff --git a/include/linux/platform_data/edma.h b/include/linux/platform_data/edma.h
new file mode 100644
index 000000000000..57300fd7cc03
--- /dev/null
+++ b/include/linux/platform_data/edma.h
@@ -0,0 +1,183 @@
1/*
2 * TI EDMA definitions
3 *
4 * Copyright (C) 2006-2013 Texas Instruments.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/*
13 * This EDMA3 programming framework exposes two basic kinds of resource:
14 *
15 * Channel Triggers transfers, usually from a hardware event but
16 * also manually or by "chaining" from DMA completions.
17 * Each channel is coupled to a Parameter RAM (PaRAM) slot.
18 *
19 * Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM
20 * "set"), source and destination addresses, a link to a
21 * next PaRAM slot (if any), options for the transfer, and
22 * instructions for updating those addresses. There are
23 * more than twice as many slots as event channels.
24 *
25 * Each PaRAM set describes a sequence of transfers, either for one large
26 * buffer or for several discontiguous smaller buffers. An EDMA transfer
27 * is driven only from a channel, which performs the transfers specified
28 * in its PaRAM slot until there are no more transfers. When that last
29 * transfer completes, the "link" field may be used to reload the channel's
30 * PaRAM slot with a new transfer descriptor.
31 *
32 * The EDMA Channel Controller (CC) maps requests from channels into physical
33 * Transfer Controller (TC) requests when the channel triggers (by hardware
34 * or software events, or by chaining). The two physical DMA channels provided
35 * by the TCs are thus shared by many logical channels.
36 *
37 * DaVinci hardware also has a "QDMA" mechanism which is not currently
38 * supported through this interface. (DSP firmware uses it though.)
39 */
40
41#ifndef EDMA_H_
42#define EDMA_H_
43
44/* PaRAM slots are laid out like this */
45struct edmacc_param {
46 unsigned int opt;
47 unsigned int src;
48 unsigned int a_b_cnt;
49 unsigned int dst;
50 unsigned int src_dst_bidx;
51 unsigned int link_bcntrld;
52 unsigned int src_dst_cidx;
53 unsigned int ccnt;
54};
55
56/* fields in edmacc_param.opt */
57#define SAM BIT(0)
58#define DAM BIT(1)
59#define SYNCDIM BIT(2)
60#define STATIC BIT(3)
61#define EDMA_FWID (0x07 << 8)
62#define TCCMODE BIT(11)
63#define EDMA_TCC(t) ((t) << 12)
64#define TCINTEN BIT(20)
65#define ITCINTEN BIT(21)
66#define TCCHEN BIT(22)
67#define ITCCHEN BIT(23)
68
69/*ch_status paramater of callback function possible values*/
70#define DMA_COMPLETE 1
71#define DMA_CC_ERROR 2
72#define DMA_TC1_ERROR 3
73#define DMA_TC2_ERROR 4
74
75enum address_mode {
76 INCR = 0,
77 FIFO = 1
78};
79
80enum fifo_width {
81 W8BIT = 0,
82 W16BIT = 1,
83 W32BIT = 2,
84 W64BIT = 3,
85 W128BIT = 4,
86 W256BIT = 5
87};
88
89enum dma_event_q {
90 EVENTQ_0 = 0,
91 EVENTQ_1 = 1,
92 EVENTQ_2 = 2,
93 EVENTQ_3 = 3,
94 EVENTQ_DEFAULT = -1
95};
96
97enum sync_dimension {
98 ASYNC = 0,
99 ABSYNC = 1
100};
101
102#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan))
103#define EDMA_CTLR(i) ((i) >> 16)
104#define EDMA_CHAN_SLOT(i) ((i) & 0xffff)
105
106#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */
107#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */
108#define EDMA_CONT_PARAMS_ANY 1001
109#define EDMA_CONT_PARAMS_FIXED_EXACT 1002
110#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
111
112#define EDMA_MAX_CC 2
113
114/* alloc/free DMA channels and their dedicated parameter RAM slots */
115int edma_alloc_channel(int channel,
116 void (*callback)(unsigned channel, u16 ch_status, void *data),
117 void *data, enum dma_event_q);
118void edma_free_channel(unsigned channel);
119
120/* alloc/free parameter RAM slots */
121int edma_alloc_slot(unsigned ctlr, int slot);
122void edma_free_slot(unsigned slot);
123
124/* alloc/free a set of contiguous parameter RAM slots */
125int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count);
126int edma_free_cont_slots(unsigned slot, int count);
127
128/* calls that operate on part of a parameter RAM slot */
129void edma_set_src(unsigned slot, dma_addr_t src_port,
130 enum address_mode mode, enum fifo_width);
131void edma_set_dest(unsigned slot, dma_addr_t dest_port,
132 enum address_mode mode, enum fifo_width);
133void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst);
134void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx);
135void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx);
136void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt,
137 u16 bcnt_rld, enum sync_dimension sync_mode);
138void edma_link(unsigned from, unsigned to);
139void edma_unlink(unsigned from);
140
141/* calls that operate on an entire parameter RAM slot */
142void edma_write_slot(unsigned slot, const struct edmacc_param *params);
143void edma_read_slot(unsigned slot, struct edmacc_param *params);
144
145/* channel control operations */
146int edma_start(unsigned channel);
147void edma_stop(unsigned channel);
148void edma_clean_channel(unsigned channel);
149void edma_clear_event(unsigned channel);
150void edma_pause(unsigned channel);
151void edma_resume(unsigned channel);
152
153struct edma_rsv_info {
154
155 const s16 (*rsv_chans)[2];
156 const s16 (*rsv_slots)[2];
157};
158
159/* platform_data for EDMA driver */
160struct edma_soc_info {
161
162 /* how many dma resources of each type */
163 unsigned n_channel;
164 unsigned n_region;
165 unsigned n_slot;
166 unsigned n_tc;
167 unsigned n_cc;
168 /*
169 * Default queue is expected to be a low-priority queue.
170 * This way, long transfers on the default queue started
171 * by the codec engine will not cause audio defects.
172 */
173 enum dma_event_q default_queue;
174
175 /* Resource reservation for other cores */
176 struct edma_rsv_info *rsv;
177
178 s8 (*queue_tc_mapping)[2];
179 s8 (*queue_priority_mapping)[2];
180 const s16 (*xbar_chans)[2];
181};
182
183#endif
diff --git a/include/linux/platform_data/gpio-rcar.h b/include/linux/platform_data/gpio-rcar.h
index b253f77a7ddf..2d8d69432813 100644
--- a/include/linux/platform_data/gpio-rcar.h
+++ b/include/linux/platform_data/gpio-rcar.h
@@ -17,10 +17,13 @@
17#define __GPIO_RCAR_H__ 17#define __GPIO_RCAR_H__
18 18
19struct gpio_rcar_config { 19struct gpio_rcar_config {
20 unsigned int gpio_base; 20 int gpio_base;
21 unsigned int irq_base; 21 unsigned int irq_base;
22 unsigned int number_of_pins; 22 unsigned int number_of_pins;
23 const char *pctl_name; 23 const char *pctl_name;
24 unsigned has_both_edge_trigger:1;
24}; 25};
25 26
27#define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin))
28
26#endif /* __GPIO_RCAR_H__ */ 29#endif /* __GPIO_RCAR_H__ */
diff --git a/include/linux/platform_data/pinctrl-coh901.h b/include/linux/platform_data/pinctrl-coh901.h
deleted file mode 100644
index dfbc65d10484..000000000000
--- a/include/linux/platform_data/pinctrl-coh901.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * Copyright (C) 2007-2012 ST-Ericsson AB
3 * License terms: GNU General Public License (GPL) version 2
4 * GPIO block resgister definitions and inline macros for
5 * U300 GPIO COH 901 335 or COH 901 571/3
6 * Author: Linus Walleij <linus.walleij@stericsson.com>
7 */
8
9#ifndef __MACH_U300_GPIO_U300_H
10#define __MACH_U300_GPIO_U300_H
11
12/**
13 * struct u300_gpio_platform - U300 GPIO platform data
14 * @ports: number of GPIO block ports
15 * @gpio_base: first GPIO number for this block (use a free range)
16 */
17struct u300_gpio_platform {
18 u8 ports;
19 int gpio_base;
20};
21
22#endif /* __MACH_U300_GPIO_U300_H */
diff --git a/include/linux/platform_data/spi-davinci.h b/include/linux/platform_data/spi-davinci.h
index 7af305b37868..8dc2fa47a2aa 100644
--- a/include/linux/platform_data/spi-davinci.h
+++ b/include/linux/platform_data/spi-davinci.h
@@ -19,7 +19,7 @@
19#ifndef __ARCH_ARM_DAVINCI_SPI_H 19#ifndef __ARCH_ARM_DAVINCI_SPI_H
20#define __ARCH_ARM_DAVINCI_SPI_H 20#define __ARCH_ARM_DAVINCI_SPI_H
21 21
22#include <mach/edma.h> 22#include <linux/platform_data/edma.h>
23 23
24#define SPI_INTERN_CS 0xFF 24#define SPI_INTERN_CS 0xFF
25 25
diff --git a/include/linux/platform_data/usb-rcar-phy.h b/include/linux/platform_data/usb-rcar-phy.h
new file mode 100644
index 000000000000..8ec6964a32a5
--- /dev/null
+++ b/include/linux/platform_data/usb-rcar-phy.h
@@ -0,0 +1,28 @@
1/*
2 * Copyright (C) 2013 Renesas Solutions Corp.
3 * Copyright (C) 2013 Cogent Embedded, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#ifndef __USB_RCAR_PHY_H
11#define __USB_RCAR_PHY_H
12
13#include <linux/types.h>
14
15struct rcar_phy_platform_data {
16 bool ferrite_bead:1; /* (R8A7778 only) */
17
18 bool port1_func:1; /* true: port 1 used by function, false: host */
19 unsigned penc1:1; /* Output of the PENC1 pin in function mode */
20 struct { /* Overcurrent pin control for ports 0..2 */
21 bool select_3_3v:1; /* true: USB_OVCn pin, false: OVCn pin */
22 /* Set to false on port 1 in function mode */
23 bool active_high:1; /* true: active high, false: active low */
24 /* Set to true on port 1 in function mode */
25 } ovc_pin[3]; /* (R8A7778 only has 2 ports) */
26};
27
28#endif /* __USB_RCAR_PHY_H */
diff --git a/include/linux/usb/ehci_pdriver.h b/include/linux/usb/ehci_pdriver.h
index 99238b096f7e..7eb4dcd0d386 100644
--- a/include/linux/usb/ehci_pdriver.h
+++ b/include/linux/usb/ehci_pdriver.h
@@ -19,6 +19,9 @@
19#ifndef __USB_CORE_EHCI_PDRIVER_H 19#ifndef __USB_CORE_EHCI_PDRIVER_H
20#define __USB_CORE_EHCI_PDRIVER_H 20#define __USB_CORE_EHCI_PDRIVER_H
21 21
22struct platform_device;
23struct usb_hcd;
24
22/** 25/**
23 * struct usb_ehci_pdata - platform_data for generic ehci driver 26 * struct usb_ehci_pdata - platform_data for generic ehci driver
24 * 27 *
@@ -50,6 +53,7 @@ struct usb_ehci_pdata {
50 /* Turn on only VBUS suspend power and hotplug detection, 53 /* Turn on only VBUS suspend power and hotplug detection,
51 * turn off everything else */ 54 * turn off everything else */
52 void (*power_suspend)(struct platform_device *pdev); 55 void (*power_suspend)(struct platform_device *pdev);
56 int (*pre_setup)(struct usb_hcd *hcd);
53}; 57};
54 58
55#endif /* __USB_CORE_EHCI_PDRIVER_H */ 59#endif /* __USB_CORE_EHCI_PDRIVER_H */
generated by cgit v1.2.2 (git 2.25.0) at 2026-05-17 10:47:03 -0400