aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-ppc
diff options
context:
space:
mode:
Diffstat (limited to 'include/asm-ppc')
-rw-r--r--include/asm-ppc/cache.h84
-rw-r--r--include/asm-ppc/cacheflush.h49
2 files changed, 0 insertions, 133 deletions
diff --git a/include/asm-ppc/cache.h b/include/asm-ppc/cache.h
deleted file mode 100644
index 7a157d0f4b5f..000000000000
--- a/include/asm-ppc/cache.h
+++ /dev/null
@@ -1,84 +0,0 @@
1/*
2 * include/asm-ppc/cache.h
3 */
4#ifdef __KERNEL__
5#ifndef __ARCH_PPC_CACHE_H
6#define __ARCH_PPC_CACHE_H
7
8#include <linux/config.h>
9
10/* bytes per L1 cache line */
11#if defined(CONFIG_8xx) || defined(CONFIG_403GCX)
12#define L1_CACHE_SHIFT 4
13#define MAX_COPY_PREFETCH 1
14#elif defined(CONFIG_PPC64BRIDGE)
15#define L1_CACHE_SHIFT 7
16#define MAX_COPY_PREFETCH 1
17#else
18#define L1_CACHE_SHIFT 5
19#define MAX_COPY_PREFETCH 4
20#endif
21
22#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
23
24#define SMP_CACHE_BYTES L1_CACHE_BYTES
25#define L1_CACHE_SHIFT_MAX 7 /* largest L1 which this arch supports */
26
27#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
28#define L1_CACHE_PAGES 8
29
30#ifndef __ASSEMBLY__
31extern void clean_dcache_range(unsigned long start, unsigned long stop);
32extern void flush_dcache_range(unsigned long start, unsigned long stop);
33extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
34extern void flush_dcache_all(void);
35#endif /* __ASSEMBLY__ */
36
37/* prep registers for L2 */
38#define CACHECRBA 0x80000823 /* Cache configuration register address */
39#define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */
40#define L2CACHE_512KB 0x00 /* 512KB */
41#define L2CACHE_256KB 0x01 /* 256KB */
42#define L2CACHE_1MB 0x02 /* 1MB */
43#define L2CACHE_NONE 0x03 /* NONE */
44#define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */
45
46#ifdef CONFIG_8xx
47/* Cache control on the MPC8xx is provided through some additional
48 * special purpose registers.
49 */
50#define SPRN_IC_CST 560 /* Instruction cache control/status */
51#define SPRN_IC_ADR 561 /* Address needed for some commands */
52#define SPRN_IC_DAT 562 /* Read-only data register */
53#define SPRN_DC_CST 568 /* Data cache control/status */
54#define SPRN_DC_ADR 569 /* Address needed for some commands */
55#define SPRN_DC_DAT 570 /* Read-only data register */
56
57/* Commands. Only the first few are available to the instruction cache.
58*/
59#define IDC_ENABLE 0x02000000 /* Cache enable */
60#define IDC_DISABLE 0x04000000 /* Cache disable */
61#define IDC_LDLCK 0x06000000 /* Load and lock */
62#define IDC_UNLINE 0x08000000 /* Unlock line */
63#define IDC_UNALL 0x0a000000 /* Unlock all */
64#define IDC_INVALL 0x0c000000 /* Invalidate all */
65
66#define DC_FLINE 0x0e000000 /* Flush data cache line */
67#define DC_SFWT 0x01000000 /* Set forced writethrough mode */
68#define DC_CFWT 0x03000000 /* Clear forced writethrough mode */
69#define DC_SLES 0x05000000 /* Set little endian swap mode */
70#define DC_CLES 0x07000000 /* Clear little endian swap mode */
71
72/* Status.
73*/
74#define IDC_ENABLED 0x80000000 /* Cache is enabled */
75#define IDC_CERR1 0x00200000 /* Cache error 1 */
76#define IDC_CERR2 0x00100000 /* Cache error 2 */
77#define IDC_CERR3 0x00080000 /* Cache error 3 */
78
79#define DC_DFWT 0x40000000 /* Data cache is forced write through */
80#define DC_LES 0x20000000 /* Caches are little endian mode */
81#endif /* CONFIG_8xx */
82
83#endif
84#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/cacheflush.h b/include/asm-ppc/cacheflush.h
deleted file mode 100644
index 6a243efb3317..000000000000
--- a/include/asm-ppc/cacheflush.h
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * include/asm-ppc/cacheflush.h
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9#ifdef __KERNEL__
10#ifndef _PPC_CACHEFLUSH_H
11#define _PPC_CACHEFLUSH_H
12
13#include <linux/mm.h>
14
15/*
16 * No cache flushing is required when address mappings are
17 * changed, because the caches on PowerPCs are physically
18 * addressed. -- paulus
19 * Also, when SMP we use the coherency (M) bit of the
20 * BATs and PTEs. -- Cort
21 */
22#define flush_cache_all() do { } while (0)
23#define flush_cache_mm(mm) do { } while (0)
24#define flush_cache_range(vma, a, b) do { } while (0)
25#define flush_cache_page(vma, p, pfn) do { } while (0)
26#define flush_icache_page(vma, page) do { } while (0)
27#define flush_cache_vmap(start, end) do { } while (0)
28#define flush_cache_vunmap(start, end) do { } while (0)
29
30extern void flush_dcache_page(struct page *page);
31#define flush_dcache_mmap_lock(mapping) do { } while (0)
32#define flush_dcache_mmap_unlock(mapping) do { } while (0)
33
34extern void flush_icache_range(unsigned long, unsigned long);
35extern void flush_icache_user_range(struct vm_area_struct *vma,
36 struct page *page, unsigned long addr, int len);
37
38#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
39do { memcpy(dst, src, len); \
40 flush_icache_user_range(vma, page, vaddr, len); \
41} while (0)
42#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
43 memcpy(dst, src, len)
44
45extern void __flush_dcache_icache(void *page_va);
46extern void __flush_dcache_icache_phys(unsigned long physaddr);
47extern void flush_dcache_icache_page(struct page *page);
48#endif /* _PPC_CACHEFLUSH_H */
49#endif /* __KERNEL__ */
generated by cgit v1.2.2 (git 2.25.0) at 2026-07-10 08:16:09 -0400