6 files changed, 85 insertions, 148 deletions

diff --git a/include/asm-powerpc/cache.h b/include/asm-powerpc/cache.h
new file mode 100644
index 000000000000..26ce502e76e8
--- /dev/null
+++ b/include/asm-powerpc/cache.h
@@ -0,0 +1,40 @@
+#ifndef _ASM_POWERPC_CACHE_H
+#define _ASM_POWERPC_CACHE_H
+
+#ifdef __KERNEL__
+
+#include <linux/config.h>
+
+/* bytes per L1 cache line */
+#if defined(CONFIG_8xx) || defined(CONFIG_403GCX)
+#define L1_CACHE_SHIFT          4
+#define MAX_COPY_PREFETCH       1
+#elif defined(CONFIG_PPC32)
+#define L1_CACHE_SHIFT          5
+#define MAX_COPY_PREFETCH       4
+#else /* CONFIG_PPC64 */
+#define L1_CACHE_SHIFT          7
+#endif
+
+#define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
+
+#define SMP_CACHE_BYTES         L1_CACHE_BYTES
+#define L1_CACHE_SHIFT_MAX      7 /* largest L1 which this arch supports */
+
+#if defined(__powerpc64__) && !defined(__ASSEMBLY__)
+struct ppc64_caches {
+        u32     dsize;                  /* L1 d-cache size */
+        u32     dline_size;             /* L1 d-cache line size */
+        u32     log_dline_size;
+        u32     dlines_per_page;
+        u32     isize;                  /* L1 i-cache size */
+        u32     iline_size;             /* L1 i-cache line size */
+        u32     log_iline_size;
+        u32     ilines_per_page;
+};
+
+extern struct ppc64_caches ppc64_caches;
+#endif /* __powerpc64__ && ! __ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_CACHE_H */
diff --git a/include/asm-ppc64/cacheflush.h b/include/asm-powerpc/cacheflush.h
index ffbc08be8e52..8a740c88d93d 100644
--- a/include/asm-ppc64/cacheflush.h
+++ b/include/asm-powerpc/cacheflush.h
@@ -1,13 +1,20 @@
-#ifndef _PPC64_CACHEFLUSH_H
-#define _PPC64_CACHEFLUSH_H
+/*
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version
+ *  2 of the License, or (at your option) any later version.
+ */
+#ifndef _ASM_POWERPC_CACHEFLUSH_H
+#define _ASM_POWERPC_CACHEFLUSH_H
+
+#ifdef __KERNEL__
 
 #include <linux/mm.h>
 #include <asm/cputable.h>
 
 /*
- * No cache flushing is required when address mappings are
- * changed, because the caches on PowerPCs are physically
- * addressed.
+ * No cache flushing is required when address mappings are changed,
+ * because the caches on PowerPCs are physically addressed.
  */
 #define flush_cache_all()                       do { } while (0)
 #define flush_cache_mm(mm)                      do { } while (0)
@@ -22,27 +29,40 @@ extern void flush_dcache_page(struct page *page);
 #define flush_dcache_mmap_unlock(mapping)       do { } while (0)
 
 extern void __flush_icache_range(unsigned long, unsigned long);
+static inline void flush_icache_range(unsigned long start, unsigned long stop)
+{
+        if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
+                __flush_icache_range(start, stop);
+}
+
 extern void flush_icache_user_range(struct vm_area_struct *vma,
                                     struct page *page, unsigned long addr,
                                     int len);
+extern void __flush_dcache_icache(void *page_va);
+extern void flush_dcache_icache_page(struct page *page);
+#if defined(CONFIG_PPC32) && !defined(CONFIG_BOOKE)
+extern void __flush_dcache_icache_phys(unsigned long physaddr);
+#endif /* CONFIG_PPC32 && !CONFIG_BOOKE */
 
 extern void flush_dcache_range(unsigned long start, unsigned long stop);
-extern void flush_dcache_phys_range(unsigned long start, unsigned long stop);
+#ifdef CONFIG_PPC32
+extern void clean_dcache_range(unsigned long start, unsigned long stop);
+extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
+#endif /* CONFIG_PPC32 */
+#ifdef CONFIG_PPC64
 extern void flush_inval_dcache_range(unsigned long start, unsigned long stop);
+extern void flush_dcache_phys_range(unsigned long start, unsigned long stop);
+#endif
 
 #define copy_to_user_page(vma, page, vaddr, dst, src, len) \
-do { memcpy(dst, src, len); \
-     flush_icache_user_range(vma, page, vaddr, len); \
-} while (0)
+        do { \
+                memcpy(dst, src, len); \
+                flush_icache_user_range(vma, page, vaddr, len); \
+        } while (0)
 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
         memcpy(dst, src, len)
 
-extern void __flush_dcache_icache(void *page_va);
 
-static inline void flush_icache_range(unsigned long start, unsigned long stop)
-{
-        if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
-                __flush_icache_range(start, stop);
-}
+#endif /* __KERNEL__ */
 
-#endif /* _PPC64_CACHEFLUSH_H */
+#endif /* _ASM_POWERPC_CACHEFLUSH_H */
diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h
index 489cf4c99c21..ef121f4f0bab 100644
--- a/include/asm-powerpc/reg.h
+++ b/include/asm-powerpc/reg.h
@@ -16,7 +16,11 @@
 /* Pickup Book E specific registers. */
 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
 #include <asm/reg_booke.h>
-#endif
+#endif /* CONFIG_BOOKE || CONFIG_40x */
+
+#ifdef CONFIG_8xx
+#include <asm/reg_8xx.h>
+#endif /* CONFIG_8xx */
 
 #define MSR_SF_LG       63              /* Enable 64 bit mode */
 #define MSR_ISF_LG      61              /* Interrupt 64b mode valid on 630 */
diff --git a/include/asm-ppc/cache.h b/include/asm-powerpc/reg_8xx.h
index 7a157d0f4b5f..e8ea346b21d3 100644
--- a/include/asm-ppc/cache.h
+++ b/include/asm-powerpc/reg_8xx.h
@@ -1,49 +1,9 @@
 /*
- * include/asm-ppc/cache.h
+ * Contains register definitions common to PowerPC 8xx CPUs.  Notice
  */
-#ifdef __KERNEL__
-#ifndef __ARCH_PPC_CACHE_H
-#define __ARCH_PPC_CACHE_H
+#ifndef _ASM_POWERPC_REG_8xx_H
+#define _ASM_POWERPC_REG_8xx_H
 
-#include <linux/config.h>
-
-/* bytes per L1 cache line */
-#if defined(CONFIG_8xx) || defined(CONFIG_403GCX)
-#define L1_CACHE_SHIFT  4
-#define MAX_COPY_PREFETCH       1
-#elif defined(CONFIG_PPC64BRIDGE)
-#define L1_CACHE_SHIFT  7
-#define MAX_COPY_PREFETCH       1
-#else
-#define L1_CACHE_SHIFT  5
-#define MAX_COPY_PREFETCH       4
-#endif
-
-#define L1_CACHE_BYTES  (1 << L1_CACHE_SHIFT)
-
-#define SMP_CACHE_BYTES L1_CACHE_BYTES
-#define L1_CACHE_SHIFT_MAX 7    /* largest L1 which this arch supports */
-
-#define L1_CACHE_ALIGN(x)       (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
-#define L1_CACHE_PAGES          8
-
-#ifndef __ASSEMBLY__
-extern void clean_dcache_range(unsigned long start, unsigned long stop);
-extern void flush_dcache_range(unsigned long start, unsigned long stop);
-extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
-extern void flush_dcache_all(void);
-#endif /* __ASSEMBLY__ */
-
-/* prep registers for L2 */
-#define CACHECRBA       0x80000823      /* Cache configuration register address */