56 files changed, 2178 insertions, 1291 deletions
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
index 964c5eddc21b..0b3ff9c48409 100644
--- a/include/asm-mips/addrspace.h
+++ b/include/asm-mips/addrspace.h
@@ -129,29 +129,12 @@
 #define PHYS_TO_XKPHYS(cm,a)            (_CONST64_(0x8000000000000000) | \
                                         ((cm)<<59) | (a))
-#if defined (CONFIG_CPU_R4300)                                          \
+/*
-    || defined (CONFIG_CPU_R4X00)                                       \
+ * The ultimate limited of the 64-bit MIPS architecture:  2 bits for selecting
-    || defined (CONFIG_CPU_R5000)                                       \
+ * the region, 3 bits for the CCA mode.  This leaves 59 bits of which the
-    || defined (CONFIG_CPU_RM7000)                                      \
+ * R8000 implements most with its 48-bit physical address space.
-    || defined (CONFIG_CPU_RM9000)                                      \
+ */
-    || defined (CONFIG_CPU_NEVADA)                                      \
+#define TO_PHYS_MASK    _CONST64_(0x07ffffffffffffff)   /* 2^^59 - 1 */
-    || defined (CONFIG_CPU_TX49XX)                                      \
-    || defined (CONFIG_CPU_MIPS64)
-#define TO_PHYS_MASK    _CONST64_(0x0000000fffffffff)   /* 2^^36 - 1 */
-#endif
-#if defined (CONFIG_CPU_R8000)
-/* We keep KUSIZE consistent with R4000 for now (2^^40) instead of (2^^48) */
-#define TO_PHYS_MASK    _CONST64_(0x000000ffffffffff)   /* 2^^40 - 1 */
-#endif
-#if defined (CONFIG_CPU_R10000)
-#define TO_PHYS_MASK    _CONST64_(0x000000ffffffffff)   /* 2^^40 - 1 */
-#endif
-#if defined(CONFIG_CPU_SB1) || defined(CONFIG_CPU_SB1A)
-#define TO_PHYS_MASK    _CONST64_(0x00000fffffffffff)   /* 2^^44 - 1 */
-#endif
 #ifndef CONFIG_CPU_R8000
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index b0c329783ac5..087126a5faf9 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -109,18 +109,12 @@
 #define  MACH_COSINE_ORION      0
 /*
- * Valid machtype for group GALILEO
- */
-#define MACH_GROUP_GALILEO     11       /* Galileo Eval Boards          */
-#define  MACH_EV64120A          0       /* EV64120A */
-/*
 * Valid machtype for group MOMENCO
 */
 #define MACH_GROUP_MOMENCO      12      /* Momentum Boards              */
 #define  MACH_MOMENCO_OCELOT    0
 #define  MACH_MOMENCO_OCELOT_G  1       /* no more supported (may 2007) */
-#define  MACH_MOMENCO_OCELOT_C  2
+#define  MACH_MOMENCO_OCELOT_C  2       /* no more supported (jun 2007) */
 #define  MACH_MOMENCO_JAGUAR_ATX 3      /* no more supported (may 2007) */
 #define  MACH_MOMENCO_OCELOT_3  4
@@ -194,13 +188,6 @@
 #define  MACH_HP_LASERJET       1
 /*
- * Valid machtype for group LASAT
- */
-#define MACH_GROUP_LASAT       21
-#define  MACH_LASAT_100         0       /* Masquerade II/SP100/SP50/SP25 */
-#define  MACH_LASAT_200         1       /* Masquerade PRO/SP200 */
-/*
 * Valid machtype for group TITAN
 */
 #define MACH_GROUP_TITAN       22       /* PMC-Sierra Titan             */
@@ -213,6 +200,27 @@
 #define MACH_GROUP_NEC_EMMA2RH 25       /* NEC EMMA2RH (was 23)         */
 #define  MACH_NEC_MARKEINS      0       /* NEC EMMA2RH Mark-eins        */
+/*
+ * Valid machtype for group LEMOTE
+ */
+#define MACH_GROUP_LEMOTE          27
+#define  MACH_LEMOTE_FULONG        0
+/*
+ * Valid machtype for group PMC-MSP
+ */
+#define MACH_GROUP_MSP         26       /* PMC-Sierra MSP boards/CPUs    */
+#define MACH_MSP4200_EVAL       0       /* PMC-Sierra MSP4200 Evaluation */
+#define MACH_MSP4200_GW         1       /* PMC-Sierra MSP4200 Gateway demo */
+#define MACH_MSP4200_FPGA       2       /* PMC-Sierra MSP4200 Emulation */
+#define MACH_MSP7120_EVAL       3       /* PMC-Sierra MSP7120 Evaluation */
+#define MACH_MSP7120_GW         4       /* PMC-Sierra MSP7120 Residential GW */
+#define MACH_MSP7120_FPGA       5       /* PMC-Sierra MSP7120 Emulation */
+#define MACH_MSP_OTHER        255       /* PMC-Sierra unknown board type */
+#define MACH_GROUP_WINDRIVER   28       /* Windriver boards */
+#define MACH_WRPPMC             1
 #define CL_SIZE                 COMMAND_LINE_SIZE
 const char *get_system_type(void);
diff --git a/include/asm-mips/cacheops.h b/include/asm-mips/cacheops.h
index c4a1ec31ff6a..df7f2deb3b56 100644
--- a/include/asm-mips/cacheops.h
+++ b/include/asm-mips/cacheops.h
@@ -20,7 +20,11 @@
 #define Index_Load_Tag_D        0x05
 #define Index_Store_Tag_I       0x08
 #define Index_Store_Tag_D       0x09
+#if defined(CONFIG_CPU_LOONGSON2)
+#define Hit_Invalidate_I        0x00
+#else
 #define Hit_Invalidate_I        0x10
+#endif
 #define Hit_Invalidate_D        0x11
 #define Hit_Writeback_Inv_D     0x15
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h
index 5e4bed123b48..d95a83e3e1d7 100644
--- a/include/asm-mips/cpu-features.h
+++ b/include/asm-mips/cpu-features.h
@@ -150,6 +150,10 @@
 #define cpu_has_mipsmt          (cpu_data[0].ases & MIPS_ASE_MIPSMT)
 #endif
+#ifndef cpu_has_userlocal
+#define cpu_has_userlocal       (cpu_data[0].options & MIPS_CPU_ULRI)
+#endif
 #ifdef CONFIG_32BIT
 # ifndef cpu_has_nofpuex
 # define cpu_has_nofpuex        (cpu_data[0].options & MIPS_CPU_NOFPUEX)
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index 2924069075e0..3857358fb6de 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -89,6 +89,8 @@
 #define PRID_IMP_34K            0x9500
 #define PRID_IMP_24KE           0x9600
 #define PRID_IMP_74K            0x9700
+#define PRID_IMP_LOONGSON1      0x4200
+#define PRID_IMP_LOONGSON2      0x6300
 /*
 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
@@ -107,6 +109,7 @@
 * Definitions for 7:0 on legacy processors
 */
+#define PRID_REV_MASK           0x00ff
 #define PRID_REV_TX4927         0x0022
 #define PRID_REV_TX4937         0x0030
@@ -123,6 +126,7 @@
 #define PRID_REV_VR4122         0x0070
 #define PRID_REV_VR4181A        0x0070  /* Same as VR4122 */
 #define PRID_REV_VR4130         0x0080
+#define PRID_REV_34K_V1_0_2     0x0022
 /*
 * Older processors used to encode processor version and revision in two
@@ -211,7 +215,10 @@
 #define CPU_SB1A                62
 #define CPU_74K                 63
 #define CPU_R14000              64
-#define CPU_LAST                64
+#define CPU_LOONGSON1           65
+#define CPU_LOONGSON2           66
+#define CPU_LAST                66
 /*
 * ISA Level encodings
@@ -257,6 +264,7 @@
 #define MIPS_CPU_PREFETCH       0x00080000 /* CPU has usable prefetch */
 #define MIPS_CPU_VINT           0x00100000 /* CPU supports MIPSR2 vectored interrupts */
 #define MIPS_CPU_VEIC           0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */
+#define MIPS_CPU_ULRI           0x00400000 /* CPU has ULRI feature */
 /*
 * CPU ASE encodings
diff --git a/include/asm-mips/div64.h b/include/asm-mips/div64.h
index 66189f5f6399..716371bd0980 100644
--- a/include/asm-mips/div64.h
+++ b/include/asm-mips/div64.h
@@ -20,7 +20,7 @@
 */
 #define do_div64_32(res, high, low, base) ({ \
-        unsigned long __quot, __mod; \
+        unsigned long __quot32, __mod32; \
        unsigned long __cf, __tmp, __tmp2, __i; \
        \
        __asm__(".set   push\n\t" \
@@ -48,12 +48,13 @@
                "bnez   %4, 0b\n\t" \
                " srl   %5, %1, 0x1f\n\t" \
                ".set   pop" \
-                : "=&r" (__mod), "=&r" (__tmp), "=&r" (__quot), "=&r" (__cf), \
+                : "=&r" (__mod32), "=&r" (__tmp), \
+                  "=&r" (__quot32), "=&r" (__cf), \
                  "=&r" (__i), "=&r" (__tmp2) \
                : "Jr" (base), "0" (high), "1" (low)); \
        \
-        (res) = __quot; \
+        (res) = __quot32; \
-        __mod; })
+        __mod32; })
 #define do_div(n, base) ({ \
        unsigned long long __quot; \
diff --git a/include/asm-mips/gpio.h b/include/asm-mips/gpio.h
new file mode 100644
index 000000000000..06e46faf862d
--- /dev/null
+++ b/include/asm-mips/gpio.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_MIPS_GPIO_H
+#define __ASM_MIPS_GPIO_H
+#include <gpio.h>
+#endif /* __ASM_MIPS_GPIO_H */
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h
index 92ec2618560c..12bcc1f9fba9 100644
--- a/include/asm-mips/io.h
+++ b/include/asm-mips/io.h
@@ -178,6 +178,11 @@ extern void __iounmap(const volatile void __iomem *addr);
 static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
        unsigned long flags)
 {
+        void __iomem *addr = plat_ioremap(offset, size, flags);
+        if (addr)
+                return addr;
 #define __IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL))
        if (cpu_has_64bit_addresses) {
@@ -282,6 +287,9 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
 static inline void iounmap(const volatile void __iomem *addr)
 {
+        if (plat_iounmap(addr))
+                return;
 #define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1)
        if (cpu_has_64bit_addresses ||
diff --git a/include/asm-mips/lasat/ds1603.h b/include/asm-mips/lasat/ds1603.h
deleted file mode 100644
index edcd7544b358..000000000000
--- a/include/asm-mips/lasat/ds1603.h
+++ /dev/null
@@ -1,18 +0,0 @@
-#include <asm/addrspace.h>
-/* Lasat 100    */
-#define DS1603_REG_100          (KSEG1ADDR(0x1c810000))
-#define DS1603_RST_100          (1 << 2)
-#define DS1603_CLK_100          (1 << 0)
-#define DS1603_DATA_SHIFT_100   1
-#define DS1603_DATA_100         (1 << DS1603_DATA_SHIFT_100)
-/* Lasat 200    */
-#define DS1603_REG_200          (KSEG1ADDR(0x11000000))
-#define DS1603_RST_200          (1 << 3)
-#define DS1603_CLK_200          (1 << 4)
-#define DS1603_DATA_200         (1 << 5)
-#define DS1603_DATA_REG_200             (DS1603_REG_200 + 0x10000)
-#define DS1603_DATA_READ_SHIFT_200      9
-#define DS1603_DATA_READ_200    (1 << DS1603_DATA_READ_SHIFT_200)
diff --git a/include/asm-mips/lasat/eeprom.h b/include/asm-mips/lasat/eeprom.h
deleted file mode 100644
index 7b53edd5cd5f..000000000000
--- a/include/asm-mips/lasat/eeprom.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#include <asm/addrspace.h>
-/* lasat 100 */
-#define AT93C_REG_100               KSEG1ADDR(0x1c810000)
-#define AT93C_RDATA_REG_100         AT93C_REG_100
-#define AT93C_RDATA_SHIFT_100       4
-#define AT93C_WDATA_SHIFT_100       4
-#define AT93C_CS_M_100              ( 1 << 5 )
-#define AT93C_CLK_M_100             ( 1 << 3 )
-/* lasat 200 */
-#define AT93C_REG_200           KSEG1ADDR(0x11000000)
-#define AT93C_RDATA_REG_200     (AT93C_REG_200+0x10000)
-#define AT93C_RDATA_SHIFT_200   8
-#define AT93C_WDATA_SHIFT_200   2
-#define AT93C_CS_M_200          ( 1 << 0 )
-#define AT93C_CLK_M_200         ( 1 << 1 )
diff --git a/include/asm-mips/lasat/head.h b/include/asm-mips/lasat/head.h
deleted file mode 100644
index f5589f31a197..000000000000
--- a/include/asm-mips/lasat/head.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Image header stuff
- */
-#ifndef _HEAD_H
-#define _HEAD_H
-#define LASAT_K_MAGIC0_VAL      0xfedeabba
-#define LASAT_K_MAGIC1_VAL      0x00bedead
-#ifndef _LANGUAGE_ASSEMBLY
-#include <linux/types.h>
-struct bootloader_header {
-        u32 magic[2];
-        u32 version;
-        u32 image_start;
-        u32 image_size;
-        u32 kernel_start;
-        u32 kernel_entry;
-};
-#endif
-#endif /* _HEAD_H */
diff --git a/include/asm-mips/lasat/lasat.h b/include/asm-mips/lasat/lasat.h
deleted file mode 100644
index 42077e367a5b..000000000000
--- a/include/asm-mips/lasat/lasat.h
+++ /dev/null
@@ -1,253 +0,0 @@
-/*
- * lasat.h
- *
- * Thomas Horsten <thh@lasat.com>
- * Copyright (C) 2000 LASAT Networks A/S.
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * Configuration for LASAT boards, loads the appropriate include files.
- */
-#ifndef _LASAT_H
-#define _LASAT_H
-#ifndef _LANGUAGE_ASSEMBLY
-extern struct lasat_misc {
-        volatile u32 *reset_reg;
-        volatile u32 *flash_wp_reg;
-        u32 flash_wp_bit;
-} *lasat_misc;
-enum lasat_mtdparts {
-        LASAT_MTD_BOOTLOADER,
-        LASAT_MTD_SERVICE,
-        LASAT_MTD_NORMAL,
-        LASAT_MTD_CONFIG,
-        LASAT_MTD_FS,
-        LASAT_MTD_LAST
-};
-/*
- * The format of the data record in the EEPROM.
- * See Documentation/LASAT/eeprom.txt for a detailed description
- * of the fields in this struct, and the LASAT Hardware Configuration
- * field specification for a detailed description of the config
- * field.
- */
-#include <linux/types.h>
-#define LASAT_EEPROM_VERSION 7
-struct lasat_eeprom_struct {
-        unsigned int  version;
-        unsigned int  cfg[3];
-        unsigned char hwaddr[6];
-        unsigned char print_partno[12];
-        unsigned char term0;
-        unsigned char print_serial[14];
-        unsigned char term1;
-        unsigned char prod_partno[12];
-        unsigned char term2;
-        unsigned char prod_serial[14];
-        unsigned char term3;
-        unsigned char passwd_hash[16];
-        unsigned char pwdnull;
-        unsigned char vendid;
-        unsigned char ts_ref;
-        unsigned char ts_signoff;
-        unsigned char reserved[11];
-        unsigned char debugaccess;
-        unsigned short prid;
-        unsigned int  serviceflag;
-        unsigned int  ipaddr;
-        unsigned int  netmask;
-        unsigned int  crc32;
-};
-struct lasat_eeprom_struct_pre7 {
-        unsigned int  version;
-        unsigned int  flags[3];
-        unsigned char hwaddr0[6];
-        unsigned char hwaddr1[6];
-        unsigned char print_partno[9];
-        unsigned char term0;
-        unsigned char print_serial[14];
-        unsigned char term1;
-        unsigned char prod_partno[9];
-        unsigned char term2;
-        unsigned char prod_serial[14];
-        unsigned char term3;
-        unsigned char passwd_hash[24];
-        unsigned char pwdnull;
-        unsigned char vendor;
-        unsigned char ts_ref;
-        unsigned char ts_signoff;
-        unsigned char reserved[6];
-        unsigned int  writecount;
-        unsigned int  ipaddr;
-        unsigned int  netmask;
-        unsigned int  crc32;
-};
-/* Configuration descriptor encoding - see the doc for details */
-#define LASAT_W0_DSCTYPE(v)             ( ( (v)         ) & 0xf )
-#define LASAT_W0_BMID(v)                ( ( (v) >> 0x04 ) & 0xf )
-#define LASAT_W0_CPUTYPE(v)             ( ( (v) >> 0x08 ) & 0xf )
-#define LASAT_W0_BUSSPEED(v)            ( ( (v) >> 0x0c ) & 0xf )
-#define LASAT_W0_CPUCLK(v)              ( ( (v) >> 0x10 ) & 0xf )
-#define LASAT_W0_SDRAMBANKSZ(v)         ( ( (v) >> 0x14 ) & 0xf )
-#define LASAT_W0_SDRAMBANKS(v)          ( ( (v) >> 0x18 ) & 0xf )
-#define LASAT_W0_L2CACHE(v)             ( ( (v) >> 0x1c ) & 0xf )
-#define LASAT_W1_EDHAC(v)               ( ( (v)         ) & 0xf )
-#define LASAT_W1_HIFN(v)                ( ( (v) >> 0x04 ) & 0x1 )
-#define LASAT_W1_ISDN(v)                ( ( (v) >> 0x05 ) & 0x1 )
-#define LASAT_W1_IDE(v)                 ( ( (v) >> 0x06 ) & 0x1 )
-#define LASAT_W1_HDLC(v)                ( ( (v) >> 0x07 ) & 0x1 )
-#define LASAT_W1_USVERSION(v)           ( ( (v) >> 0x08 ) & 0x1 )
-#define LASAT_W1_4MACS(v)               ( ( (v) >> 0x09 ) & 0x1 )
-#define LASAT_W1_EXTSERIAL(v)           ( ( (v) >> 0x0a ) & 0x1 )
-#define LASAT_W1_FLASHSIZE(v)           ( ( (v) >> 0x0c ) & 0xf )
-#define LASAT_W1_PCISLOTS(v)            ( ( (v) >> 0x10 ) & 0xf )
-#define LASAT_W1_PCI1OPT(v)             ( ( (v) >> 0x14 ) & 0xf )
-#define LASAT_W1_PCI2OPT(v)             ( ( (v) >> 0x18 ) & 0xf )
-#define LASAT_W1_PCI3OPT(v)             ( ( (v) >> 0x1c ) & 0xf )
-/* Routines specific to LASAT boards */
-#define LASAT_BMID_MASQUERADE2          0
-#define LASAT_BMID_MASQUERADEPRO        1
-#define LASAT_BMID_SAFEPIPE25                   2
-#define LASAT_BMID_SAFEPIPE50                   3
-#define LASAT_BMID_SAFEPIPE100          4
-#define LASAT_BMID_SAFEPIPE5000         5
-#define LASAT_BMID_SAFEPIPE7000         6
-#define LASAT_BMID_SAFEPIPE1000         7
-//#define LASAT_BMID_SAFEPIPE30         7
-//#define LASAT_BMID_SAFEPIPE5100       8
-//#define LASAT_BMID_SAFEPIPE7100       9
-#define LASAT_BMID_UNKNOWN                              0xf
-#define LASAT_MAX_BMID_NAMES                    9   // no larger than 15!
-#define LASAT_HAS_EDHAC                 ( 1 << 0 )
-#define LASAT_EDHAC_FAST                ( 1 << 1 )
-#define LASAT_HAS_EADI                  ( 1 << 2 )
-#define LASAT_HAS_HIFN                  ( 1 << 3 )
-#define LASAT_HAS_ISDN                  ( 1 << 4 )
-#define LASAT_HAS_LEASEDLINE_IF         ( 1 << 5 )
-#define LASAT_HAS_HDC                   ( 1 << 6 )
-#define LASAT_PRID_MASQUERADE2          0
-#define LASAT_PRID_MASQUERADEPRO        1
-#define LASAT_PRID_SAFEPIPE25                   2
-#define LASAT_PRID_SAFEPIPE50                   3
-#define LASAT_PRID_SAFEPIPE100          4
-#define LASAT_PRID_SAFEPIPE5000         5
-#define LASAT_PRID_SAFEPIPE7000         6
-#define LASAT_PRID_SAFEPIPE30                   7
-#define LASAT_PRID_SAFEPIPE5100         8
-#define LASAT_PRID_SAFEPIPE7100         9
-#define LASAT_PRID_SAFEPIPE1110         10
-#define LASAT_PRID_SAFEPIPE3020         11
-#define LASAT_PRID_SAFEPIPE3030         12
-#define LASAT_PRID_SAFEPIPE5020         13
-#define LASAT_PRID_SAFEPIPE5030         14
-#define LASAT_PRID_SAFEPIPE1120         15
-#define LASAT_PRID_SAFEPIPE1130         16
-#define LASAT_PRID_SAFEPIPE6010         17
-#define LASAT_PRID_SAFEPIPE6110         18
-#define LASAT_PRID_SAFEPIPE6210         19
-#define LASAT_PRID_SAFEPIPE1020         20
-#define LASAT_PRID_SAFEPIPE1040         21
-#define LASAT_PRID_SAFEPIPE1060         22
-struct lasat_info {
-        unsigned int  li_cpu_hz;
-        unsigned int  li_bus_hz;
-        unsigned int  li_bmid;
-        unsigned int  li_memsize;
-        unsigned int  li_flash_size;
-        unsigned int  li_prid;
-        unsigned char li_bmstr[16];
-        unsigned char li_namestr[32];
-        unsigned char li_typestr[16];
-        /* Info on the Flash layout */
-        unsigned int  li_flash_base;
-        unsigned long li_flashpart_base[LASAT_MTD_LAST];
-        unsigned long li_flashpart_size[LASAT_MTD_LAST];
-        struct lasat_eeprom_struct li_eeprom_info;
-        unsigned int  li_eeprom_upgrade_version;
-        unsigned int  li_debugaccess;
-};
-extern struct lasat_info lasat_board_info;
-static inline unsigned long lasat_flash_partition_start(int partno)
-{
-        if (partno < 0 || partno >= LASAT_MTD_LAST)
-                return 0;
-        return lasat_board_info.li_flashpart_base[partno];
-}
-static inline unsigned long lasat_flash_partition_size(int partno)
-{
-        if (partno < 0 || partno >= LASAT_MTD_LAST)
-                return 0;
-        return lasat_board_info.li_flashpart_size[partno];
-}
-/* Called from setup() to initialize the global board_info struct */
-extern int lasat_init_board_info(void);
-/* Write the modified EEPROM info struct */
-extern void lasat_write_eeprom_info(void);
-#define N_MACHTYPES             2
-/* for calibration of delays */
-/* the lasat_ndelay function is necessary because it is used at an
- * early stage of the boot process where ndelay is not calibrated.
- * It is used for the bit-banging rtc and eeprom drivers */
-#include <asm/delay.h>
-/* calculating with the slowest board with 100 MHz clock */
-#define LASAT_100_DIVIDER 20
-/* All 200's run at 250 MHz clock */
-#define LASAT_200_DIVIDER 8
-extern unsigned int lasat_ndelay_divider;
-static inline void lasat_ndelay(unsigned int ns)
-{
-            __delay(ns / lasat_ndelay_divider);
-}
-#endif /* !defined (_LANGUAGE_ASSEMBLY) */
-#define LASAT_SERVICEMODE_MAGIC_1     0xdeadbeef
-#define LASAT_SERVICEMODE_MAGIC_2     0xfedeabba
-/* Lasat 100 boards */
-#define LASAT_GT_BASE           (KSEG1ADDR(0x14000000))
-/* Lasat 200 boards */
-#define Vrc5074_PHYS_BASE       0x1fa00000
-#define Vrc5074_BASE            (KSEG1ADDR(Vrc5074_PHYS_BASE))
-#define PCI_WINDOW1             0x1a000000
-#endif /* _LASAT_H */
diff --git a/include/asm-mips/lasat/lasatint.h b/include/asm-mips/lasat/lasatint.h
deleted file mode 100644
index 065474feeccc..000000000000
--- a/include/asm-mips/lasat/lasatint.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#define LASATINT_END 16
-/* lasat 100 */
-#define LASAT_INT_STATUS_REG_100        (KSEG1ADDR(0x1c880000))
-#define LASAT_INT_MASK_REG_100          (KSEG1ADDR(0x1c890000))
-#define LASATINT_MASK_SHIFT_100         0
-/* lasat 200 */
-#define LASAT_INT_STATUS_REG_200        (KSEG1ADDR(0x1104003c))
-#define LASAT_INT_MASK_REG_200          (KSEG1ADDR(0x1104003c))
-#define LASATINT_MASK_SHIFT_200         16
diff --git a/include/asm-mips/lasat/picvue.h b/include/asm-mips/lasat/picvue.h
deleted file mode 100644
index 42a492edc40e..000000000000
--- a/include/asm-mips/lasat/picvue.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* Lasat 100 */
-#define PVC_REG_100             KSEG1ADDR(0x1c820000)
-#define PVC_DATA_SHIFT_100      0
-#define PVC_DATA_M_100          0xFF
-#define PVC_E_100               (1 << 8)
-#define PVC_RW_100              (1 << 9)
-#define PVC_RS_100              (1 << 10)
-/* Lasat 200 */
-#define PVC_REG_200             KSEG1ADDR(0x11000000)
-#define PVC_DATA_SHIFT_200      24
-#define PVC_DATA_M_200          (0xFF << PVC_DATA_SHIFT_200)
-#define PVC_E_200               (1 << 16)
-#define PVC_RW_200              (1 << 17)
-#define PVC_RS_200              (1 << 18)
diff --git a/include/asm-mips/lasat/serial.h b/include/asm-mips/lasat/serial.h
deleted file mode 100644
index 9e88c7669c7a..000000000000
--- a/include/asm-mips/lasat/serial.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#include <asm/lasat/lasat.h>
-/* Lasat 100 boards serial configuration */
-#define LASAT_BASE_BAUD_100             ( 7372800 / 16 )
-#define LASAT_UART_REGS_BASE_100        0x1c8b0000
-#define LASAT_UART_REGS_SHIFT_100       2
-#define LASATINT_UART_100               8
-/* * LASAT 200 boards serial configuration */
-#define LASAT_BASE_BAUD_200             (100000000 / 16 / 12)
-#define LASAT_UART_REGS_BASE_200        (Vrc5074_PHYS_BASE + 0x0300)
-#define LASAT_UART_REGS_SHIFT_200       3
-#define LASATINT_UART_200               13
diff --git a/include/asm-mips/mach-au1x00/au1xxx_gpio.h b/include/asm-mips/mach-au1x00/au1xxx_gpio.h
deleted file mode 100644
index 27911e054ffc..000000000000
--- a/include/asm-mips/mach-au1x00/au1xxx_gpio.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef __AU1XXX_GPIO_H
-#define __AU1XXX_GPIO_H
-void au1xxx_gpio1_set_inputs(void);
-void au1xxx_gpio_tristate(int signal);
-void au1xxx_gpio_write(int signal, int value);
-int  au1xxx_gpio_read(int signal);
-typedef volatile struct
-{
-        u32 dir;
-        u32 reserved;
-        u32 output;
-        u32 pinstate;
-        u32 inten;
-        u32 enable;
-} AU1X00_GPIO2;
-#endif //__AU1XXX_GPIO_H
diff --git a/include/asm-mips/mach-au1x00/gpio.h b/include/asm-mips/mach-au1x00/gpio.h
new file mode 100644
index 000000000000..2dc61e009a08
--- /dev/null
+++ b/include/asm-mips/mach-au1x00/gpio.h
@@ -0,0 +1,69 @@
+#ifndef _AU1XXX_GPIO_H_
+#define _AU1XXX_GPIO_H_
+#include <linux/types.h>
+#define AU1XXX_GPIO_BASE        200
+struct au1x00_gpio2 {
+        u32     dir;
+        u32     reserved;
+        u32     output;
+        u32     pinstate;
+        u32     inten;
+        u32     enable;
+};
+extern int au1xxx_gpio_get_value(unsigned gpio);
+extern void au1xxx_gpio_set_value(unsigned gpio, int value);
+extern int au1xxx_gpio_direction_input(unsigned gpio);
+extern int au1xxx_gpio_direction_output(unsigned gpio, int value);
+/* Wrappers for the arch-neutral GPIO API */
+static inline int gpio_request(unsigned gpio, const char *label)
+{
+        /* Not yet implemented */
+        return 0;
+}
+static inline void gpio_free(unsigned gpio)
+{
+        /* Not yet implemented */
+}
+static inline int gpio_direction_input(unsigned gpio)
+{
+        return au1xxx_gpio_direction_input(gpio);
+}
+static inline int gpio_direction_output(unsigned gpio, int value)
+{
+        return au1xxx_gpio_direction_output(gpio, value);
+}
+static inline int gpio_get_value(unsigned gpio)
+{
+        return au1xxx_gpio_get_value(gpio);
+}
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+        au1xxx_gpio_set_value(gpio, value);
+}
+static inline int gpio_to_irq(unsigned gpio)
+{
+        return gpio;
+}
+static inline int irq_to_gpio(unsigned irq)
+{
+        return irq;
+}
+/* For cansleep */
+#include <asm-generic/gpio.h>
+#endif /* _AU1XXX_GPIO_H_ */
diff --git a/include/asm-mips/mach-au1x00/ioremap.h b/include/asm-mips/mach-au1x00/ioremap.h
index 098fca4289bb..364cea2dc71f 100644
--- a/include/asm-mips/mach-au1x00/ioremap.h
+++ b/include/asm-mips/mach-au1x00/ioremap.h
@@ -28,4 +28,15 @@ static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
        return __fixup_bigphys_addr(phys_addr, size);
 }
+static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
+        unsigned long flags)
+{
+        return NULL;
+}
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+        return 0;
+}
 #endif /* __ASM_MACH_AU1X00_IOREMAP_H */
diff --git a/include/asm-mips/mach-cobalt/cobalt.h b/include/asm-mips/mach-cobalt/cobalt.h
index 684a501c04cf..9c9d2b998ca4 100644
--- a/include/asm-mips/mach-cobalt/cobalt.h
+++ b/include/asm-mips/mach-cobalt/cobalt.h
@@ -30,7 +30,6 @@
 #define COBALT_CPU_IRQ          MIPS_CPU_IRQ_BASE
 #define COBALT_GALILEO_IRQ      (COBALT_CPU_IRQ + 2)
-#define COBALT_SCC_IRQ          (COBALT_CPU_IRQ + 3)    /* pre-production has 85C30 */
 #define COBALT_RAQ_SCSI_IRQ     (COBALT_CPU_IRQ + 3)
 #define COBALT_ETH0_IRQ         (COBALT_CPU_IRQ + 3)
 #define COBALT_QUBE1_ETH0_IRQ   (COBALT_CPU_IRQ + 4)
@@ -71,10 +70,6 @@
 extern int cobalt_board_id;
-#define PCI_CFG_SET(devfn,where)                                        \
-        GT_WRITE(GT_PCI0_CFGADDR_OFS, (0x80000000 | (PCI_SLOT (devfn) << 11) |          \
-                (PCI_FUNC (devfn) << 8) | (where)))
 #define COBALT_LED_PORT         (*(volatile unsigned char *) CKSEG1ADDR(0x1c000000))
 # define COBALT_LED_BAR_LEFT    (1 << 0)        /* Qube */
 # define COBALT_LED_BAR_RIGHT   (1 << 1)        /* Qube */
diff --git a/include/asm-mips/mach-ev64120/mach-gt64120.h b/include/asm-mips/mach-ev64120/mach-gt64120.h
deleted file mode 100644
index 7e272ce57ea3..000000000000
--- a/include/asm-mips/mach-ev64120/mach-gt64120.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- *  This is a direct copy of the ev96100.h file, with a global
- * search and replace.  The numbers are the same.
- *
- *  The reason I'm duplicating this is so that the 64120/96100
- * defines won't be confusing in the source code.
- */
-#ifndef __ASM_GALILEO_BOARDS_MIPS_EV64120_H
-#define __ASM_GALILEO_BOARDS_MIPS_EV64120_H
-/*
- *   GT64120 config space base address
- */
-extern unsigned long gt64120_base;
-#define GT64120_BASE    (gt64120_base)
-/*
- *   PCI Bus allocation
- */
-#define GT_PCI_MEM_BASE 0x12000000UL
-#define GT_PCI_MEM_SIZE 0x02000000UL
-#define GT_PCI_IO_BASE  0x10000000UL
-#define GT_PCI_IO_SIZE  0x02000000UL
-#define GT_ISA_IO_BASE  PCI_IO_BASE
-/*
- *   Duart I/O ports.
- */
-#define EV64120_COM1_BASE_ADDR  (0x1d000000 + 0x20)
-#define EV64120_COM2_BASE_ADDR  (0x1d000000 + 0x00)
-/*
- *   EV64120 interrupt controller register base.
- */
-#define EV64120_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000))
-/*
- *   EV64120 UART register base.
- */
-#define EV64120_UART0_REGS_BASE (KSEG1ADDR(EV64120_COM1_BASE_ADDR))
-#define EV64120_UART1_REGS_BASE (KSEG1ADDR(EV64120_COM2_BASE_ADDR))
-#define EV64120_BASE_BAUD ( 3686400 / 16 )
-#define EV64120_UART_IRQ        6
-/*
- * PCI interrupts will come in on either the INTA or INTD interrups lines,
- * which are mapped to the #2 and #5 interrupt pins of the MIPS.  On our
- * boards, they all either come in on IntD or they all come in on IntA, they
- * aren't mixed. There can be numerous PCI interrupts, so we keep a list of the
- * "requested" interrupt numbers and go through the list whenever we get an
- * IntA/D.
- *
- * Interrupts < 8 are directly wired to the processor; PCI INTA is 8 and
- * INTD is 11.
- */
-#define GT_TIMER        4
-#define GT_INTA         2
-#define GT_INTD         5
-#endif /* __ASM_GALILEO_BOARDS_MIPS_EV64120_H */
diff --git a/include/asm-mips/mach-generic/gpio.h b/include/asm-mips/mach-generic/gpio.h
new file mode 100644
index 000000000000..6eaf5efedf3a
--- /dev/null
+++ b/include/asm-mips/mach-generic/gpio.h
@@ -0,0 +1,15 @@
+#ifndef __ASM_MACH_GENERIC_GPIO_H
+#define __ASM_MACH_GENERIC_GPIO_H
+int gpio_request(unsigned gpio, const char *label);
+void gpio_free(unsigned gpio);
+int gpio_direction_input(unsigned gpio);
+int gpio_direction_output(unsigned gpio, int value);
+int gpio_get_value(unsigned gpio);
+void gpio_set_value(unsigned gpio, int value);
+int gpio_to_irq(unsigned gpio);
+int irq_to_gpio(unsigned irq);
+#include <asm-generic/gpio.h>           /* cansleep wrappers */
+#endif /* __ASM_MACH_GENERIC_GPIO_H */
diff --git a/include/asm-mips/mach-generic/ioremap.h b/include/asm-mips/mach-generic/ioremap.h
index 9b64ff6e485d..b379938d47f0 100644
--- a/include/asm-mips/mach-generic/ioremap.h
+++ b/include/asm-mips/mach-generic/ioremap.h
@@ -20,4 +20,15 @@ static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
        return phys_addr;
 }
+static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
+        unsigned long flags)
+{
+        return NULL;
+}
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+        return 0;
+}
 #endif /* __ASM_MACH_GENERIC_IOREMAP_H */
diff --git a/include/asm-mips/mach-generic/spaces.h b/include/asm-mips/mach-generic/spaces.h
index 0ae9997bc9a8..c9fa4b14968d 100644
--- a/include/asm-mips/mach-generic/spaces.h
+++ b/include/asm-mips/mach-generic/spaces.h
@@ -10,38 +10,54 @@
 #ifndef _ASM_MACH_GENERIC_SPACES_H
 #define _ASM_MACH_GENERIC_SPACES_H
+#include <linux/const.h>
+/*
+ * This gives the physical RAM offset.
+ */
+#ifndef PHYS_OFFSET
+#define PHYS_OFFSET             _AC(0, UL)
+#endif
 #ifdef CONFIG_32BIT
-#define CAC_BASE                0x80000000
+#define CAC_BASE                _AC(0x80000000, UL)
-#define IO_BASE                 0xa0000000
+#define IO_BASE                 _AC(0xa0000000, UL)
-#define UNCAC_BASE              0xa0000000
+#define UNCAC_BASE              _AC(0xa0000000, UL)
-#define MAP_BASE                0xc0000000
-/*
+#ifndef MAP_BASE
- * This handles the memory map.
+#define MAP_BASE                _AC(0xc0000000, UL)
- * We handle pages at KSEG0 for kernels with 32 bit address space.
+#endif
- */
-#define PAGE_OFFSET             0x80000000UL
 /*
 * Memory above this physical address will be considered highmem.
 */
 #ifndef HIGHMEM_START
-#define HIGHMEM_START           0x20000000UL
+#define HIGHMEM_START           _AC(0x20000000, UL)
 #endif
 #endif /* CONFIG_32BIT */
 #ifdef CONFIG_64BIT
-/*
+#ifndef CAC_BASE
- * This handles the memory map.
- */
 #ifdef CONFIG_DMA_NONCOHERENT
-#define PAGE_OFFSET     0x9800000000000000UL
+#define CAC_BASE                _AC(0x9800000000000000, UL)
 #else
-#define PAGE_OFFSET     0xa800000000000000UL
+#define CAC_BASE                _AC(0xa800000000000000, UL)
+#endif
+#endif
+#ifndef IO_BASE
+#define IO_BASE                 _AC(0x9000000000000000, UL)
+#endif
+#ifndef UNCAC_BASE
+#define UNCAC_BASE              _AC(0x9000000000000000, UL)
+#endif
+#ifndef MAP_BASE
+#define MAP_BASE                _AC(0xc000000000000000, UL)
 #endif
 /*
@@ -50,22 +66,20 @@
 * in the distant future.  Nobody will care for a few years :-)
 */
 #ifndef HIGHMEM_START
-#define HIGHMEM_START           (1UL << 59UL)
+#define HIGHMEM_START           (_AC(1, UL) << _AC(59, UL))
 #endif
-#ifdef CONFIG_DMA_NONCOHERENT
-#define CAC_BASE                0x9800000000000000UL
-#else
-#define CAC_BASE                0xa800000000000000UL
-#endif
-#define IO_BASE                 0x9000000000000000UL
-#define UNCAC_BASE              0x9000000000000000UL
-#define MAP_BASE                0xc000000000000000UL
 #define TO_PHYS(x)              (             ((x) & TO_PHYS_MASK))
 #define TO_CAC(x)               (CAC_BASE   | ((x) & TO_PHYS_MASK))
 #define TO_UNCAC(x)             (UNCAC_BASE | ((x) & TO_PHYS_MASK))
 #endif /* CONFIG_64BIT */
+/*
+ * This handles the memory map.
+ */
+#ifndef PAGE_OFFSET
+#define PAGE_OFFSET             (CAC_BASE + PHYS_OFFSET)
+#endif
 #endif /* __ASM_MACH_GENERIC_SPACES_H */
diff --git a/include/asm-mips/mach-ip22/spaces.h b/include/asm-mips/mach-ip22/spaces.h
index ab20c026fd19..7f9fa6f66059 100644
--- a/include/asm-mips/mach-ip22/spaces.h
+++ b/include/asm-mips/mach-ip22/spaces.h
@@ -11,44 +11,17 @@
 #define _ASM_MACH_IP22_SPACES_H
-#ifdef CONFIG_32BIT
-#define CAC_BASE                0x80000000
-#define IO_BASE                 0xa0000000
-#define UNCAC_BASE              0xa0000000
-#define MAP_BASE                0xc0000000
-/*
- * This handles the memory map.
- * We handle pages at KSEG0 for kernels with 32 bit address space.
- */
-#define PAGE_OFFSET             0x80000000UL
-/*
- * Memory above this physical address will be considered highmem.
- */
-#ifndef HIGHMEM_START
-#define HIGHMEM_START           0x20000000UL
-#endif
-#endif /* CONFIG_32BIT */
 #ifdef CONFIG_64BIT
-#define PAGE_OFFSET             0xffffffff80000000UL
-#ifndef HIGHMEM_START
+#define PAGE_OFFSET             0xffffffff80000000UL
-#define HIGHMEM_START           (1UL << 59UL)
-#endif
 #define CAC_BASE                0xffffffff80000000
 #define IO_BASE                 0xffffffffa0000000
 #define UNCAC_BASE              0xffffffffa0000000
 #define MAP_BASE                0xc000000000000000
-#define TO_PHYS(x)              (             ((x) & TO_PHYS_MASK))
-#define TO_CAC(x)               (CAC_BASE   | ((x) & TO_PHYS_MASK))
-#define TO_UNCAC(x)             (UNCAC_BASE | ((x) & TO_PHYS_MASK))
 #endif /* CONFIG_64BIT */
+#include <asm/mach-generic/spaces.h>
 #endif /* __ASM_MACH_IP22_SPACES_H */
diff --git a/include/asm-mips/mach-ip27/spaces.h b/include/asm-mips/mach-ip27/spaces.h
index 45e61785ef42..b18802a0b17e 100644
--- a/include/asm-mips/mach-ip27/spaces.h
+++ b/include/asm-mips/mach-ip27/spaces.h
@@ -14,22 +14,17 @@
 * IP27 uses the R10000's uncached attribute feature.  Attribute 3 selects
 * uncached memory addressing.
 */
-#define CAC_BASE                0xa800000000000000
 #define HSPEC_BASE              0x9000000000000000
 #define IO_BASE                 0x9200000000000000
 #define MSPEC_BASE              0x9400000000000000
 #define UNCAC_BASE              0x9600000000000000
-#define MAP_BASE                0xc000000000000000
-#define TO_PHYS(x)              (             ((x) & TO_PHYS_MASK))
-#define TO_CAC(x)               (CAC_BASE   | ((x) & TO_PHYS_MASK))
-#define TO_UNCAC(x)             (UNCAC_BASE | ((x) & TO_PHYS_MASK))
 #define TO_MSPEC(x)             (MSPEC_BASE | ((x) & TO_PHYS_MASK))
 #define TO_HSPEC(x)             (HSPEC_BASE | ((x) & TO_PHYS_MASK))
-#define PAGE_OFFSET             CAC_BASE
 #define HIGHMEM_START           (~0UL)
+#include <asm/mach-generic/spaces.h>
 #endif /* _ASM_MACH_IP27_SPACES_H */
diff --git a/include/asm-mips/mach-ip32/spaces.h b/include/asm-mips/mach-ip32/spaces.h
deleted file mode 100644
index 44abe5c02389..000000000000
--- a/include/asm-mips/mach-ip32/spaces.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994 - 1999, 2000, 03, 04, 05 Ralf Baechle (ralf@linux-mips.org)
- * Copyright (C) 2000, 2002  Maciej W. Rozycki
- * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
- */
-#ifndef _ASM_MACH_IP32_SPACES_H
-#define _ASM_MACH_IP32_SPACES_H
-/*
- * Memory above this physical address will be considered highmem.
- * Fixme: 59 bits is a fictive number and makes assumptions about processors
- * in the distant future.  Nobody will care for a few years :-)
- */
-#ifndef HIGHMEM_START
-#define HIGHMEM_START           (1UL << 59UL)
-#endif
-#define CAC_BASE                0x9800000000000000UL
-#define IO_BASE                 0x9000000000000000UL
-#define UNCAC_BASE              0x9000000000000000UL
-#define MAP_BASE                0xc000000000000000UL
-#define TO_PHYS(x)              (             ((x) & TO_PHYS_MASK))
-#define TO_CAC(x)               (CAC_BASE   | ((x) & TO_PHYS_MASK))
-#define TO_UNCAC(x)             (UNCAC_BASE | ((x) & TO_PHYS_MASK))
-/*
- * This handles the memory map.
- */
-#define PAGE_OFFSET             CAC_BASE
-#endif /* __ASM_MACH_IP32_SPACES_H */
diff --git a/include/asm-mips/mach-jmr3927/ioremap.h b/include/asm-mips/mach-jmr3927/ioremap.h
new file mode 100644
index 000000000000..aa131ad7f717
--- /dev/null
+++ b/include/asm-mips/mach-jmr3927/ioremap.h
@@ -0,0 +1,38 @@
+/*
+ *      include/asm-mips/mach-jmr3927/ioremap.h
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+#ifndef __ASM_MACH_JMR3927_IOREMAP_H
+#define __ASM_MACH_JMR3927_IOREMAP_H
+#include <linux/types.h>
+/*
+ * Allow physical addresses to be fixed up to help peripherals located
+ * outside the low 32-bit range -- generic pass-through version.
+ */
+static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
+{
+        return phys_addr;
+}
+static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
+        unsigned long flags)
+{
+#define TXX9_DIRECTMAP_BASE     0xff000000ul
+        if (offset >= TXX9_DIRECTMAP_BASE &&
+            offset < TXX9_DIRECTMAP_BASE + 0xf0000)
+                return (void __iomem *)offset;
+        return NULL;
+}
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+        return (unsigned long)addr >= TXX9_DIRECTMAP_BASE;
+}
+#endif /* __ASM_MACH_JMR3927_IOREMAP_H */
diff --git a/include/asm-mips/mach-lasat/mach-gt64120.h b/include/asm-mips/mach-lasat/mach-gt64120.h
deleted file mode 100644
index 1a9ad45cc135..000000000000
--- a/include/asm-mips/mach-lasat/mach-gt64120.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- *  This is a direct copy of the ev96100.h file, with a global
- * search and replace.  The numbers are the same.
- *
- *  The reason I'm duplicating this is so that the 64120/96100
- * defines won't be confusing in the source code.
- */
-#ifndef _ASM_GT64120_LASAT_GT64120_DEP_H
-#define _ASM_GT64120_LASAT_GT64120_DEP_H
-/*
- *   GT64120 config space base address on Lasat 100
- */
-#define GT64120_BASE    (KSEG1ADDR(0x14000000))
-/*
- *   PCI Bus allocation
- *
- *   (Guessing ...)
- */
-#define GT_PCI_MEM_BASE 0x12000000UL
-#define GT_PCI_MEM_SIZE 0x02000000UL
-#define GT_PCI_IO_BASE  0x10000000UL
-#define GT_PCI_IO_SIZE  0x02000000UL
-#define GT_ISA_IO_BASE  PCI_IO_BASE
-#endif /* _ASM_GT64120_LASAT_GT64120_DEP_H */
diff --git a/include/asm-mips/mach-lemote/dma-coherence.h b/include/asm-mips/mach-lemote/dma-coherence.h
new file mode 100644
index 000000000000..7e914777ebc4
--- /dev/null
+++ b/include/asm-mips/mach-lemote/dma-coherence.h
@@ -0,0 +1,42 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2006, 07  Ralf Baechle <ralf@linux-mips.org>
+ * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
+ * Author: Fuxin Zhang, zhangfx@lemote.com
+ *
+ */
+#ifndef __ASM_MACH_LEMOTE_DMA_COHERENCE_H
+#define __ASM_MACH_LEMOTE_DMA_COHERENCE_H
+struct device;
+static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
+                                          size_t size)
+{
+        return virt_to_phys(addr) | 0x80000000;
+}
+static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
+                                               struct page *page)
+{
+        return page_to_phys(page) | 0x80000000;
+}
+static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
+{
+        return dma_addr & 0x7fffffff;
+}
+static inline void plat_unmap_dma_mem(dma_addr_t dma_addr)
+{
+}
+static inline int plat_device_is_coherent(struct device *dev)
+{
+        return 0;
+}
+#endif /* __ASM_MACH_LEMOTE_DMA_COHERENCE_H */
diff --git a/include/asm-mips/mach-lemote/mc146818rtc.h b/include/asm-mips/mach-lemote/mc146818rtc.h
new file mode 100644
index 000000000000..ed5147e11085
--- /dev/null
+++ b/include/asm-mips/mach-lemote/mc146818rtc.h
@@ -0,0 +1,36 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998, 2001, 03, 07 by Ralf Baechle (ralf@linux-mips.org)
+ *
+ * RTC routines for PC style attached Dallas chip.
+ */
+#ifndef __ASM_MACH_LEMOTE_MC146818RTC_H
+#define __ASM_MACH_LEMOTE_MC146818RTC_H
+#include <linux/io.h>
+#define RTC_PORT(x)     (0x70 + (x))
+#define RTC_IRQ         8
+static inline unsigned char CMOS_READ(unsigned long addr)
+{
+        outb_p(addr, RTC_PORT(0));
+        return inb_p(RTC_PORT(1));
+}
+static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
+{
+        outb_p(addr, RTC_PORT(0));
+        outb_p(data, RTC_PORT(1));
+}
+#define RTC_ALWAYS_BCD  0
+#ifndef mc146818_decode_year
+#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1970)
+#endif
+#endif /* __ASM_MACH_LEMOTE_MC146818RTC_H */
diff --git a/include/asm-mips/mach-mips/kernel-entry-init.h b/include/asm-mips/mach-mips/kernel-entry-init.h
new file mode 100644
index 000000000000..0b793e7bf67e
--- /dev/null
+++ b/include/asm-mips/mach-mips/kernel-entry-init.h
@@ -0,0 +1,52 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Chris Dearman (chris@mips.com)
+ * Copyright (C) 2007 Mips Technologies, Inc.
+ */
+#ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
+#define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
+        .macro  kernel_entry_setup
+#ifdef CONFIG_MIPS_MT_SMTC
+        mfc0    t0, CP0_CONFIG
+        bgez    t0, 9f
+        mfc0    t0, CP0_CONFIG, 1
+        bgez    t0, 9f
+        mfc0    t0, CP0_CONFIG, 2
+        bgez    t0, 9f
+        mfc0    t0, CP0_CONFIG, 3
+        and     t0, 1<<2
+        bnez    t0, 0f
+9:
+        /* Assume we came from YAMON... */
+        PTR_LA  v0, 0x9fc00534  /* YAMON print */
+        lw      v0, (v0)
+        move    a0, zero
+        PTR_LA  a1, nonmt_processor
+        jal     v0
+        PTR_LA  v0, 0x9fc00520  /* YAMON exit */
+        lw      v0, (v0)
+        li      a0, 1
+        jal     v0
+1:      b       1b
+        __INITDATA
+nonmt_processor:
+        .asciz  "SMTC kernel requires the MT ASE to run\n"
+        __FINIT
+0:
+#endif
+        .endm
+/*
+ * Do SMP slave processor setup necessary before we can safely execute C code.
+ */
+        .macro  smp_slave_setup
+        .endm
+#endif /* __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H */
diff --git a/include/asm-mips/mach-sim/cpu-feature-overrides.h b/include/asm-mips/mach-mipssim/cpu-feature-overrides.h
index 779b02205737..779b02205737 100644
--- a/include/asm-mips/mach-sim/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-mipssim/cpu-feature-overrides.h
diff --git a/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h b/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
deleted file mode 100644
index 57a12ded0613..000000000000
--- a/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2004 MontaVista Software Inc.
- * Author: Manish Lachwani, mlachwani@mvista.com
- * Copyright (C) 2004 Ralf Baechle
- */
-#ifndef __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H
-#define __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H
-/*
- * Momentum Ocelot-3 is based on Rm7900 processor which
- * is based on the E9000 core.
- */
-#define cpu_has_watch           1
-#define cpu_has_mips16          0
-#define cpu_has_divec           0
-#define cpu_has_vce             0
-#define cpu_has_cache_cdex_p    0
-#define cpu_has_cache_cdex_s    0
-#define cpu_has_prefetch        1
-#define cpu_has_mcheck          0
-#define cpu_has_ejtag           0
-#define cpu_has_llsc            1
-#define cpu_has_vtag_icache     0
-#define cpu_has_dc_aliases      0
-#define cpu_has_ic_fills_f_dc   0
-#define cpu_has_dsp             0
-#define cpu_icache_snoops_remote_store  0
-#define cpu_has_nofpuex         0
-#define cpu_has_64bits          1
-#define cpu_has_inclusive_pcaches       0
-#define cpu_dcache_line_size()  32
-#define cpu_icache_line_size()  32
-#define cpu_scache_line_size()  32
-#define cpu_has_mips32r1        0
-#define cpu_has_mips32r2        0
-#define cpu_has_mips64r1        0
-#define cpu_has_mips64r2        0
-#endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-tx49xx/ioremap.h b/include/asm-mips/mach-tx49xx/ioremap.h
new file mode 100644
index 000000000000..88cf546719b8
--- /dev/null
+++ b/include/asm-mips/mach-tx49xx/ioremap.h
@@ -0,0 +1,42 @@
+/*
+ *      include/asm-mips/mach-tx49xx/ioremap.h
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+#ifndef __ASM_MACH_TX49XX_IOREMAP_H
+#define __ASM_MACH_TX49XX_IOREMAP_H
+#include <linux/types.h>
+/*
+ * Allow physical addresses to be fixed up to help peripherals located
+ * outside the low 32-bit range -- generic pass-through version.
+ */
+static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
+{
+        return phys_addr;
+}
+static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
+        unsigned long flags)
+{
+#ifdef CONFIG_64BIT
+#define TXX9_DIRECTMAP_BASE     0xfff000000ul
+#else
+#define TXX9_DIRECTMAP_BASE     0xff000000ul
+#endif
+        if (offset >= TXX9_DIRECTMAP_BASE &&
+            offset < TXX9_DIRECTMAP_BASE + 0x400000)
+                return (void __iomem *)(unsigned long)(int)offset;
+        return NULL;
+}
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+        return (unsigned long)addr >= (unsigned long)(int)TXX9_DIRECTMAP_BASE;
+}
+#endif /* __ASM_MACH_TX49XX_IOREMAP_H */
diff --git a/include/asm-mips/mips-boards/bonito64.h b/include/asm-mips/mips-boards/bonito64.h
index cd7125610100..dc3fc32eedd8 100644
--- a/include/asm-mips/mips-boards/bonito64.h
+++ b/include/asm-mips/mips-boards/bonito64.h
@@ -26,7 +26,12 @@
 /* offsets from base register */
 #define BONITO(x)       (x)
-#else /* !__ASSEMBLY__ */
+#elif defined(CONFIG_LEMOTE_FULONG)
+#define BONITO(x) (*(volatile u32 *)((char *)CKSEG1ADDR(BONITO_REG_BASE) + (x)))
+#define BONITO_IRQ_BASE   32
+#else
 /*
 * Algorithmics Bonito64 system controller register base.
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index 89c81922d47c..706b3691f57e 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -7,7 +7,7 @@
 * Copyright (C) 2000 Silicon Graphics, Inc.
 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 2000, 07 MIPS Technologies, Inc.
 * Copyright (C) 2003, 2004  Maciej W. Rozycki
 */
 #ifndef _ASM_MIPSREGS_H
@@ -15,6 +15,7 @@
 #include <linux/linkage.h>
 #include <asm/hazards.h>
+#include <asm/war.h>
 /*
 * The following macros are especially useful for __asm__
@@ -533,9 +534,13 @@
 #define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
 #define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
 #define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
+#define MIPS_CONF3_ULRI         (_ULCAST_(1) << 13)
 #define MIPS_CONF7_WII          (_ULCAST_(1) << 31)
+#define MIPS_CONF7_RPS          (_ULCAST_(1) << 2)
 /*
 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
 */
@@ -772,6 +777,9 @@ do {									\
 #define read_c0_context()       __read_ulong_c0_register($4, 0)
 #define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
+#define read_c0_userlocal()     __read_ulong_c0_register($4, 2)
+#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
 #define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
 #define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
@@ -1294,10 +1302,39 @@ static inline void tlb_probe(void)
 static inline void tlb_read(void)
 {
+#if MIPS34K_MISSED_ITLB_WAR
+        int res = 0;
+        __asm__ __volatile__(
+        "       .set    push                                    \n"
+        "       .set    noreorder                               \n"
+        "       .set    noat                                    \n"
+        "       .set    mips32r2                                \n"
+        "       .word   0x41610001              # dvpe $1       \n"
+        "       move    %0, $1                                  \n"
+        "       ehb                                             \n"
+        "       .set    pop                                     \n"
+        : "=r" (res));
+        instruction_hazard();
+#endif
        __asm__ __volatile__(
                ".set noreorder\n\t"
                "tlbr\n\t"
                ".set reorder");
+#if MIPS34K_MISSED_ITLB_WAR
+        if ((res & _ULCAST_(1)))
+                __asm__ __volatile__(
+                "       .set    push                            \n"
+                "       .set    noreorder                       \n"
+                "       .set    noat                            \n"
+                "       .set    mips32r2                        \n"
+                "       .word   0x41600021      # evpe          \n"
+                "       ehb                                     \n"
+                "       .set    pop                             \n");
+#endif
 }
 static inline void tlb_write_indexed(void)
diff --git a/include/asm-mips/module.h b/include/asm-mips/module.h
index c5ef324fd69f..de6d09ebbd80 100644
--- a/include/asm-mips/module.h
+++ b/include/asm-mips/module.h
@@ -112,6 +112,8 @@ search_module_dbetables(unsigned long addr)
 #define MODULE_PROC_FAMILY "RM9000 "
 #elif defined CONFIG_CPU_SB1
 #define MODULE_PROC_FAMILY "SB1 "
+#elif defined CONFIG_CPU_LOONGSON2
+#define MODULE_PROC_FAMILY "LOONGSON2 "
 #else
 #error MODULE_PROC_FAMILY undefined for your processor configuration
 #endif
diff --git a/include/asm-mips/nile4.h b/include/asm-mips/nile4.h
deleted file mode 100644
index c3ca959aa4d9..000000000000
--- a/include/asm-mips/nile4.h
+++ /dev/null
@@ -1,310 +0,0 @@
-/*
- *  asm-mips/nile4.h -- NEC Vrc-5074 Nile 4 definitions
- *
- *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
- *                     Sony Software Development Center Europe (SDCE), Brussels
- *
- *  This file is based on the following documentation:
- *
- *      NEC Vrc 5074 System Controller Data Sheet, June 1998
- */
-#ifndef _ASM_NILE4_H
-#define _ASM_NILE4_H
-#define NILE4_BASE              0xbfa00000
-#define NILE4_SIZE              0x00200000              /* 2 MB */
-    /*
-     *  Physical Device Address Registers (PDARs)
-     */
-#define NILE4_SDRAM0    0x0000  /* SDRAM Bank 0 [R/W] */
-#define NILE4_SDRAM1    0x0008  /* SDRAM Bank 1 [R/W] */
-#define NILE4_DCS2      0x0010  /* Device Chip-Select 2 [R/W] */
-#define NILE4_DCS3      0x0018  /* Device Chip-Select 3 [R/W] */
-#define NILE4_DCS4      0x0020  /* Device Chip-Select 4 [R/W] */
-#define NILE4_DCS5      0x0028  /* Device Chip-Select 5 [R/W] */
-#define NILE4_DCS6      0x0030  /* Device Chip-Select 6 [R/W] */
-#define NILE4_DCS7      0x0038  /* Device Chip-Select 7 [R/W] */
-#define NILE4_DCS8      0x0040  /* Device Chip-Select 8 [R/W] */
-#define NILE4_PCIW0     0x0060  /* PCI Address Window 0 [R/W] */
-#define NILE4_PCIW1     0x0068  /* PCI Address Window 1 [R/W] */
-#define NILE4_INTCS     0x0070  /* Controller Internal Registers and Devices */
-                                /* [R/W] */
-#define NILE4_BOOTCS    0x0078  /* Boot ROM Chip-Select [R/W] */
-    /*
-     *  CPU Interface Registers
-     */
-#define NILE4_CPUSTAT   0x0080  /* CPU Status [R/W] */
-#define NILE4_INTCTRL   0x0088  /* Interrupt Control [R/W] */
-#define NILE4_INTSTAT0  0x0090  /* Interrupt Status 0 [R] */
-#define NILE4_INTSTAT1  0x0098  /* Interrupt Status 1 and CPU Interrupt */
-                                /* Enable [R/W] */
-#define NILE4_INTCLR    0x00A0  /* Interrupt Clear [R/W] */
-#define NILE4_INTPPES   0x00A8  /* PCI Interrupt Control [R/W] */
-    /*
-     *  Memory-Interface Registers
-     */
-#define NILE4_MEMCTRL   0x00C0  /* Memory Control */
-#define NILE4_ACSTIME   0x00C8  /* Memory Access Timing [R/W] */
-#define NILE4_CHKERR    0x00D0  /* Memory Check Error Status [R] */
-    /*
-     *  PCI-Bus Registers
-     */
-#define NILE4_PCICTRL   0x00E0  /* PCI Control [R/W] */
-#define NILE4_PCIARB    0x00E8  /* PCI Arbiter [R/W] */
-#define NILE4_PCIINIT0  0x00F0  /* PCI Master (Initiator) 0 [R/W] */
-#define NILE4_PCIINIT1  0x00F8  /* PCI Master (Initiator) 1 [R/W] */
-#define NILE4_PCIERR    0x00B8  /* PCI Error [R/W] */
-    /*
-     *  Local-Bus Registers
-     */
-#define NILE4_LCNFG     0x0100  /* Local Bus Configuration [R/W] */
-#define NILE4_LCST2     0x0110  /* Local Bus Chip-Select Timing 2 [R/W] */
-#define NILE4_LCST3     0x0118  /* Local Bus Chip-Select Timing 3 [R/W] */
-#define NILE4_LCST4     0x0120  /* Local Bus Chip-Select Timing 4 [R/W] */
-#define NILE4_LCST5     0x0128  /* Local Bus Chip-Select Timing 5 [R/W] */
-#define NILE4_LCST6     0x0130  /* Local Bus Chip-Select Timing 6 [R/W] */
-#define NILE4_LCST7     0x0138  /* Local Bus Chip-Select Timing 7 [R/W] */
-#define NILE4_LCST8     0x0140  /* Local Bus Chip-Select Timing 8 [R/W] */
-#define NILE4_DCSFN     0x0150  /* Device Chip-Select Muxing and Output */
-                                /* Enables [R/W] */
-#define NILE4_DCSIO     0x0158  /* Device Chip-Selects As I/O Bits [R/W] */
-#define NILE4_BCST      0x0178  /* Local Boot Chip-Select Timing [R/W] */
-    /*
-     *  DMA Registers
-     */
-#define NILE4_DMACTRL0  0x0180  /* DMA Control 0 [R/W] */
-#define NILE4_DMASRCA0  0x0188  /* DMA Source Address 0 [R/W] */
-#define NILE4_DMADESA0  0x0190  /* DMA Destination Address 0 [R/W] */
-#define NILE4_DMACTRL1  0x0198  /* DMA Control 1 [R/W] */
-#define NILE4_DMASRCA1  0x01A0  /* DMA Source Address 1 [R/W] */
-#define NILE4_DMADESA1  0x01A8  /* DMA Destination Address 1 [R/W] */
-    /*
-     *  Timer Registers
-     */
-#define NILE4_T0CTRL    0x01C0  /* SDRAM Refresh Control [R/W] */
-#define NILE4_T0CNTR    0x01C8  /* SDRAM Refresh Counter [R/W] */
-#define NILE4_T1CTRL    0x01D0  /* CPU-Bus Read Time-Out Control [R/W] */
-#define NILE4_T1CNTR    0x01D8  /* CPU-Bus Read Time-Out Counter [R/W] */
-#define NILE4_T2CTRL    0x01E0  /* General-Purpose Timer Control [R/W] */
-#define NILE4_T2CNTR    0x01E8  /* General-Purpose Timer Counter [R/W] */
-#define NILE4_T3CTRL    0x01F0  /* Watchdog Timer Control [R/W] */
-#define NILE4_T3CNTR    0x01F8  /* Watchdog Timer Counter [R/W] */
-    /*
-     *  PCI Configuration Space Registers
-     */
-#define NILE4_PCI_BASE  0x0200
-#define NILE4_VID       0x0200  /* PCI Vendor ID [R] */
-#define NILE4_DID       0x0202  /* PCI Device ID [R] */
-#define NILE4_PCICMD    0x0204  /* PCI Command [R/W] */
-#define NILE4_PCISTS    0x0206  /* PCI Status [R/W] */
-#define NILE4_REVID     0x0208  /* PCI Revision ID [R] */
-#define NILE4_CLASS     0x0209  /* PCI Class Code [R] */
-#define NILE4_CLSIZ     0x020C  /* PCI Cache Line Size [R/W] */
-#define NILE4_MLTIM     0x020D  /* PCI Latency Timer [R/W] */
-#define NILE4_HTYPE     0x020E  /* PCI Header Type [R] */
-#define NILE4_BIST      0x020F  /* BIST [R] (unimplemented) */
-#define NILE4_BARC      0x0210  /* PCI Base Address Register Control [R/W] */
-#define NILE4_BAR0      0x0218  /* PCI Base Address Register 0 [R/W] */
-#define NILE4_BAR1      0x0220  /* PCI Base Address Register 1 [R/W] */
-#define NILE4_CIS       0x0228  /* PCI Cardbus CIS Pointer [R] */
-                                /* (unimplemented) */
-#define NILE4_SSVID     0x022C  /* PCI Sub-System Vendor ID [R/W] */
-#define NILE4_SSID      0x022E  /* PCI Sub-System ID [R/W] */
-#define NILE4_ROM       0x0230  /* Expansion ROM Base Address [R] */
-                                /* (unimplemented) */
-#define NILE4_INTLIN    0x023C  /* PCI Interrupt Line [R/W] */
-#define NILE4_INTPIN    0x023D  /* PCI Interrupt Pin [R] */
-#define NILE4_MINGNT    0x023E  /* PCI Min_Gnt [R] (unimplemented) */
-#define NILE4_MAXLAT    0x023F  /* PCI Max_Lat [R] (unimplemented) */
-#define NILE4_BAR2      0x0240  /* PCI Base Address Register 2 [R/W] */
-#define NILE4_BAR3      0x0248  /* PCI Base Address Register 3 [R/W] */
-#define NILE4_BAR4      0x0250  /* PCI Base Address Register 4 [R/W] */
-#define NILE4_BAR5      0x0258  /* PCI Base Address Register 5 [R/W] */
-#define NILE4_BAR6      0x0260  /* PCI Base Address Register 6 [R/W] */
-#define NILE4_BAR7      0x0268  /* PCI Base Address Register 7 [R/W] */
-#define NILE4_BAR8      0x0270  /* PCI Base Address Register 8 [R/W] */
-#define NILE4_BARB      0x0278  /* PCI Base Address Register BOOT [R/W] */
-    /*
-     *  Serial-Port Registers
-     */
-#define NILE4_UART_BASE 0x0300
-#define NILE4_UARTRBR   0x0300  /* UART Receiver Data Buffer [R] */
-#define NILE4_UARTTHR   0x0300  /* UART Transmitter Data Holding [W] */
-#define NILE4_UARTIER   0x0308  /* UART Interrupt Enable [R/W] */
-#define NILE4_UARTDLL   0x0300  /* UART Divisor Latch LSB [R/W] */
-#define NILE4_UARTDLM   0x0308  /* UART Divisor Latch MSB [R/W] */
-#define NILE4_UARTIIR   0x0310  /* UART Interrupt ID [R] */
-#define NILE4_UARTFCR   0x0310  /* UART FIFO Control [W] */
-#define NILE4_UARTLCR   0x0318  /* UART Line Control [R/W] */
-#define NILE4_UARTMCR   0x0320  /* UART Modem Control [R/W] */
-#define NILE4_UARTLSR   0x0328  /* UART Line Status [R/W] */
-#define NILE4_UARTMSR   0x0330  /* UART Modem Status [R/W] */
-#define NILE4_UARTSCR   0x0338  /* UART Scratch [R/W] */
-#define NILE4_UART_BASE_BAUD    520833  /* 100 MHz / 12 / 16 */
-    /*
-     *  Interrupt Lines
-     */
-#define NILE4_INT_CPCE  0       /* CPU-Interface Parity-Error Interrupt */
-#define NILE4_INT_CNTD  1       /* CPU No-Target Decode Interrupt */
-#define NILE4_INT_MCE   2       /* Memory-Check Error Interrupt */
-#define NILE4_INT_DMA   3       /* DMA Controller Interrupt */
-#define NILE4_INT_UART  4       /* UART Interrupt */
-#define NILE4_INT_WDOG  5       /* Watchdog Timer Interrupt */
-#define NILE4_INT_GPT   6       /* General-Purpose Timer Interrupt */
-#define NILE4_INT_LBRTD 7       /* Local-Bus Ready Timer Interrupt */
-#define NILE4_INT_INTA  8       /* PCI Interrupt Signal INTA# */
-#define NILE4_INT_INTB  9       /* PCI Interrupt Signal INTB# */
-#define NILE4_INT_INTC  10      /* PCI Interrupt Signal INTC# */
-#define NILE4_INT_INTD  11      /* PCI Interrupt Signal INTD# */
-#define NILE4_INT_INTE  12      /* PCI Interrupt Signal INTE# (ISA cascade) */
-#define NILE4_INT_RESV  13      /* Reserved */
-#define NILE4_INT_PCIS  14      /* PCI SERR# Interrupt */
-#define NILE4_INT_PCIE  15      /* PCI Internal Error Interrupt */
-    /*
-     *  Nile 4 Register Access
-     */
-static inline void nile4_sync(void)
-{
-    volatile u32 *p = (volatile u32 *)0xbfc00000;
-    (void)(*p);
-}
-static inline void nile4_out32(u32 offset, u32 val)
-{
-    *(volatile u32 *)(NILE4_BASE+offset) = val;
-    nile4_sync();
-}
-static inline u32 nile4_in32(u32 offset)
-{
-    u32 val = *(volatile u32 *)(NILE4_BASE+offset);
-    nile4_sync();
-    return val;
-}
-static inline void nile4_out16(u32 offset, u16 val)
-{
-    *(volatile u16 *)(NILE4_BASE+offset) = val;
-    nile4_sync();
-}
-static inline u16 nile4_in16(u32 offset)
-{
-    u16 val = *(volatile u16 *)(NILE4_BASE+offset);
-    nile4_sync();
-    return val;
-}
-static inline void nile4_out8(u32 offset, u8 val)
-{
-    *(volatile u8 *)(NILE4_BASE+offset) = val;
-    nile4_sync();
-}
-static inline u8 nile4_in8(u32 offset)
-{
-    u8 val = *(volatile u8 *)(NILE4_BASE+offset);
-    nile4_sync();
-    return val;
-}
-    /*
-     *  Physical Device Address Registers
-     */
-extern void nile4_set_pdar(u32 pdar, u32 phys, u32 size, int width,
-                           int on_memory_bus, int visible);
-    /*
-     *  PCI Master Registers
-     */
-#define NILE4_PCICMD_IACK       0       /* PCI Interrupt Acknowledge */
-#define NILE4_PCICMD_IO         1       /* PCI I/O Space */
-#define NILE4_PCICMD_MEM        3       /* PCI Memory Space */
-#define NILE4_PCICMD_CFG        5       /* PCI Configuration Space */
-    /*
-     *  PCI Address Spaces
-     *
-     *  Note that these are multiplexed using PCIINIT[01]!
-     */
-#define NILE4_PCI_IO_BASE       0xa6000000
-#define NILE4_PCI_MEM_BASE      0xa8000000
-#define NILE4_PCI_CFG_BASE      NILE4_PCI_MEM_BASE
-#define NILE4_PCI_IACK_BASE     NILE4_PCI_IO_BASE
-extern void nile4_set_pmr(u32 pmr, u32 type, u32 addr);
-    /*
-     *  Interrupt Programming
-     */
-#define NUM_I8259_INTERRUPTS    16
-#define NUM_NILE4_INTERRUPTS    16
-#define IRQ_I8259_CASCADE       NILE4_INT_INTE
-#define is_i8259_irq(irq)       ((irq) < NUM_I8259_INTERRUPTS)
-#define nile4_to_irq(n)         ((n)+NUM_I8259_INTERRUPTS)
-#define irq_to_nile4(n)         ((n)-NUM_I8259_INTERRUPTS)
-extern void nile4_map_irq(int nile4_irq, int cpu_irq);
-extern void nile4_map_irq_all(int cpu_irq);
-extern void nile4_enable_irq(unsigned int nile4_irq);
-extern void nile4_disable_irq(unsigned int nile4_irq);
-extern void nile4_disable_irq_all(void);
-extern u16 nile4_get_irq_stat(int cpu_irq);
-extern void nile4_enable_irq_output(int cpu_irq);
-extern void nile4_disable_irq_output(int cpu_irq);
-extern void nile4_set_pci_irq_polarity(int pci_irq, int high);
-extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level);
-extern void nile4_clear_irq(int nile4_irq);
-extern void nile4_clear_irq_mask(u32 mask);
-extern u8 nile4_i8259_iack(void);
-extern void nile4_dump_irq_status(void);        /* Debug */
-#endif
diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h
index 5c3239dad0f2..b92dd8c760da 100644
--- a/include/asm-mips/page.h
+++ b/include/asm-mips/page.h
@@ -34,12 +34,8 @@
 #ifndef __ASSEMBLY__
-/*
+#include <linux/pfn.h>
- * This gives the physical RAM offset.
+#include <asm/io.h>
- */
-#ifndef PHYS_OFFSET
-#define PHYS_OFFSET             0UL
-#endif
 /*
 * It's normally defined only for FLATMEM config but it's
@@ -48,9 +44,6 @@
 */
 #define ARCH_PFN_OFFSET         PFN_UP(PHYS_OFFSET)
-#include <linux/pfn.h>
-#include <asm/io.h>
 extern void clear_page(void * page);
 extern void copy_page(void * to, void * from);
@@ -150,11 +143,15 @@ typedef struct { unsigned long pgprot; } pgprot_t;
 * __pa()/__va() should be used only during mem init.
 */
 #if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64)
-#define __pa_page_offset(x)     ((unsigned long)(x) < CKSEG0 ? PAGE_OFFSET : CKSEG0)
+#define __pa(x)                                                         \
+({                                                                      \
+    unsigned long __x = (unsigned long)(x);                             \
+    __x < CKSEG0 ? XPHYSADDR(__x) : CPHYSADDR(__x);                     \
+})
 #else
-#define __pa_page_offset(x)     PAGE_OFFSET
+#define __pa(x)                                                         \
+    ((unsigned long)(x) - PAGE_OFFSET + PHYS_OFFSET)
 #endif
-#define __pa(x)         ((unsigned long)(x) - __pa_page_offset(x) + PHYS_OFFSET)
 #define __va(x)         ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET))
 #define __pa_symbol(x)  __pa(RELOC_HIDE((unsigned long)(x),0))
diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h
index 3eea3ba0fca5..a59d54749eef 100644
--- a/include/asm-mips/pci.h
+++ b/include/asm-mips/pci.h
@@ -56,7 +56,7 @@ extern void register_pci_controller(struct pci_controller *hose);
 /*
 * board supplied pci irq fixup routine
 */
-extern int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin);
+extern int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
 /* Can be used to override the logic in pci_scan_bus for skipping
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_cic_int.h b/include/asm-mips/pmc-sierra/msp71xx/msp_cic_int.h
new file mode 100644
index 000000000000..c84bcf9570b1
--- /dev/null
+++ b/include/asm-mips/pmc-sierra/msp71xx/msp_cic_int.h
@@ -0,0 +1,151 @@
+/*
+ * Defines for the MSP interrupt controller.
+ *
+ * Copyright (C) 1999 MIPS Technologies, Inc.  All rights reserved.
+ * Author: Carsten Langgaard, carstenl@mips.com
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ */
+#ifndef _MSP_CIC_INT_H
+#define _MSP_CIC_INT_H
+/*
+ * The PMC-Sierra CIC interrupts are all centrally managed by the
+ * CIC sub-system.
+ * We attempt to keep the interrupt numbers as consistent as possible
+ * across all of the MSP devices, but some differences will creep in ...
+ * The interrupts which are directly forwarded to the MIPS core interrupts
+ * are assigned interrupts in the range 0-7, interrupts cascaded through
+ * the CIC are assigned interrupts 8-39.  The cascade occurs on C_IRQ4
+ * (MSP_INT_CIC).  Currently we don't really distinguish between VPE1
+ * and VPE0 (or thread contexts for that matter).  Will have to fix.
+ * The PER interrupts are assigned interrupts in the range 40-71.
+*/
+/*
+ * IRQs directly forwarded to the CPU
+ */
+#define MSP_MIPS_INTBASE        0
+#define MSP_INT_SW0             0       /* IRQ for swint0,       C_SW0  */
+#define MSP_INT_SW1             1       /* IRQ for swint1,       C_SW1  */
+#define MSP_INT_MAC0            2       /* IRQ for MAC 0,        C_IRQ0 */
+#define MSP_INT_MAC1            3       /* IRQ for MAC 1,        C_IRQ1 */
+#define MSP_INT_USB             4       /* IRQ for USB,          C_IRQ2 */
+#define MSP_INT_SAR             5       /* IRQ for ADSL2+ SAR,   C_IRQ3 */
+#define MSP_INT_CIC             6       /* IRQ for CIC block,    C_IRQ4 */
+#define MSP_INT_SEC             7       /* IRQ for Sec engine,   C_IRQ5 */
+/*
+ * IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4)
+ * These defines should be tied to the register definitions for the CIC
+ * interrupt routine.  For now, just use hard-coded values.
+ */
+#define MSP_CIC_INTBASE         (MSP_MIPS_INTBASE + 8)
+#define MSP_INT_EXT0            (MSP_CIC_INTBASE + 0)
+                                        /* External interrupt 0         */
+#define MSP_INT_EXT1            (MSP_CIC_INTBASE + 1)
+                                        /* External interrupt 1         */
+#define MSP_INT_EXT2            (MSP_CIC_INTBASE + 2)
+                                        /* External interrupt 2         */
+#define MSP_INT_EXT3            (MSP_CIC_INTBASE + 3)
+                                        /* External interrupt 3         */
+#define MSP_INT_CPUIF           (MSP_CIC_INTBASE + 4)
+                                        /* CPU interface interrupt      */
+#define MSP_INT_EXT4            (MSP_CIC_INTBASE + 5)
+                                        /* External interrupt 4         */
+#define MSP_INT_CIC_USB         (MSP_CIC_INTBASE + 6)
+                                        /* Cascaded IRQ for USB         */
+#define MSP_INT_MBOX            (MSP_CIC_INTBASE + 7)
+                                        /* Sec engine mailbox IRQ       */
+#define MSP_INT_EXT5            (MSP_CIC_INTBASE + 8)
+                                        /* External interrupt 5         */
+#define MSP_INT_TDM             (MSP_CIC_INTBASE + 9)
+                                        /* TDM interrupt                */
+#define MSP_INT_CIC_MAC0        (MSP_CIC_INTBASE + 10)
+                                        /* Cascaded IRQ for MAC 0       */
+#define MSP_INT_CIC_MAC1        (MSP_CIC_INTBASE + 11)
+                                        /* Cascaded IRQ for MAC 1       */
+#define MSP_INT_CIC_SEC         (MSP_CIC_INTBASE + 12)
+                                        /* Cascaded IRQ for sec engine  */
+#define MSP_INT_PER             (MSP_CIC_INTBASE + 13)
+                                        /* Peripheral interrupt         */
+#define MSP_INT_TIMER0          (MSP_CIC_INTBASE + 14)
+                                        /* SLP timer 0                  */
+#define MSP_INT_TIMER1          (MSP_CIC_INTBASE + 15)
+                                        /* SLP timer 1                  */
+#define MSP_INT_TIMER2          (MSP_CIC_INTBASE + 16)
+                                        /* SLP timer 2                  */
+#define MSP_INT_VPE0_TIMER      (MSP_CIC_INTBASE + 17)
+                                        /* VPE0 MIPS timer              */
+#define MSP_INT_BLKCP           (MSP_CIC_INTBASE + 18)
+                                        /* Block Copy                   */
+#define MSP_INT_UART0           (MSP_CIC_INTBASE + 19)
+                                        /* UART 0                       */
+#define MSP_INT_PCI             (MSP_CIC_INTBASE + 20)
+                                        /* PCI subsystem                */
+#define MSP_INT_EXT6            (MSP_CIC_INTBASE + 21)
+                                        /* External interrupt 5         */
+#define MSP_INT_PCI_MSI         (MSP_CIC_INTBASE + 22)
+                                        /* PCI Message Signal           */
+#define MSP_INT_CIC_SAR         (MSP_CIC_INTBASE + 23)
+                                        /* Cascaded ADSL2+ SAR IRQ      */
+#define MSP_INT_DSL             (MSP_CIC_INTBASE + 24)
+                                        /* ADSL2+ IRQ                   */
+#define MSP_INT_CIC_ERR         (MSP_CIC_INTBASE + 25)
+                                        /* SLP error condition          */
+#define MSP_INT_VPE1_TIMER      (MSP_CIC_INTBASE + 26)
+                                        /* VPE1 MIPS timer              */
+#define MSP_INT_VPE0_PC         (MSP_CIC_INTBASE + 27)
+                                        /* VPE0 Performance counter     */
+#define MSP_INT_VPE1_PC         (MSP_CIC_INTBASE + 28)
+                                        /* VPE1 Performance counter     */
+#define MSP_INT_EXT7            (MSP_CIC_INTBASE + 29)
+                                        /* External interrupt 5         */
+#define MSP_INT_VPE0_SW         (MSP_CIC_INTBASE + 30)
+                                        /* VPE0 Software interrupt      */
+#define MSP_INT_VPE1_SW         (MSP_CIC_INTBASE + 31)
+                                        /* VPE0 Software interrupt      */
+/*
+ * IRQs cascaded on CIC PER interrupt (MSP_INT_PER)
+ */
+#define MSP_PER_INTBASE         (MSP_CIC_INTBASE + 32)
+/* Reserved                                        0-1                  */
+#define MSP_INT_UART1           (MSP_PER_INTBASE + 2)
+                                        /* UART 1                       */
+/* Reserved                                        3-5                  */
+#define MSP_INT_2WIRE           (MSP_PER_INTBASE + 6)
+                                        /* 2-wire                       */
+#define MSP_INT_TM0             (MSP_PER_INTBASE + 7)
+                                        /* Peripheral timer block out 0 */
+#define MSP_INT_TM1             (MSP_PER_INTBASE + 8)
+                                        /* Peripheral timer block out 1 */
+/* Reserved                                        9                    */
+#define MSP_INT_SPRX            (MSP_PER_INTBASE + 10)
+                                        /* SPI RX complete              */
+#define MSP_INT_SPTX            (MSP_PER_INTBASE + 11)
+                                        /* SPI TX complete              */
+#define MSP_INT_GPIO            (MSP_PER_INTBASE + 12)
+                                        /* GPIO                         */
+#define MSP_INT_PER_ERR         (MSP_PER_INTBASE + 13)
+                                        /* Peripheral error             */
+/* Reserved                                        14-31                */
+#endif /* !_MSP_CIC_INT_H */
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_int.h b/include/asm-mips/pmc-sierra/msp71xx/msp_int.h
new file mode 100644
index 000000000000..1d9f05474820
--- /dev/null
+++ b/include/asm-mips/pmc-sierra/msp71xx/msp_int.h
@@ -0,0 +1,43 @@
+/*
+ * Defines for the MSP interrupt handlers.
+ *
+ * Copyright (C) 2005, PMC-Sierra, Inc.  All rights reserved.
+ * Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ */
+#ifndef _MSP_INT_H
+#define _MSP_INT_H
+/*
+ * The PMC-Sierra MSP product line has at least two different interrupt
+ * controllers, the SLP register based scheme and the CIC interrupt
+ * controller block mechanism.  This file distinguishes between them
+ * so that devices see a uniform interface.
+ */
+#if defined(CONFIG_IRQ_MSP_SLP)
+        #include "msp_slp_int.h"
+#elif defined(CONFIG_IRQ_MSP_CIC)
+        #include "msp_cic_int.h"
+#else
+        #error "What sort of interrupt controller does *your* MSP have?"
+#endif
+#endif /* !_MSP_INT_H */
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_pci.h b/include/asm-mips/pmc-sierra/msp71xx/msp_pci.h
new file mode 100644
index 000000000000..415606903617
--- /dev/null
+++ b/include/asm-mips/pmc-sierra/msp71xx/msp_pci.h
@@ -0,0 +1,205 @@
+/*
+ * Copyright (c) 2000-2006 PMC-Sierra INC.
+ *
+ *     This program is free software; you can redistribute it
+ *     and/or modify it under the terms of the GNU General
+ *     Public License as published by the Free Software
+ *     Foundation; either version 2 of the License, or (at your
+ *     option) any later version.
+ *
+ *     This program is distributed in the hope that it will be
+ *     useful, but WITHOUT ANY WARRANTY; without even the implied
+ *     warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+ *     PURPOSE.  See the GNU General Public License for more
+ *     details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this program; if not, write to the Free
+ *     Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
+ *     02139, USA.
+ *
+ * PMC-SIERRA INC. DISCLAIMS ANY LIABILITY OF ANY KIND
+ * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS
+ * SOFTWARE.
+ */
+#ifndef _MSP_PCI_H_
+#define _MSP_PCI_H_
+#define MSP_HAS_PCI(ID) (((u32)(ID) <= 0x4236) && ((u32)(ID) >= 0x4220))
+/*
+ * It is convenient to program the OATRAN register so that
+ * Athena virtual address space and PCI address space are
+ * the same. This is not a requirement, just a convenience.
+ *
+ * The only hard restrictions on the value of OATRAN is that
+ * OATRAN must not be programmed to allow translated memory
+ * addresses to fall within the lowest 512MB of
+ * PCI address space. This region is hardcoded
+ * for use as Athena PCI Host Controller target
+ * access memory space to the Athena's SDRAM.
+ *
+ * Note that OATRAN applies only to memory accesses, not
+ * to I/O accesses.
+ *
+ * To program OATRAN to make Athena virtual address space
+ * and PCI address space have the same values, OATRAN
+ * is to be programmed to 0xB8000000. The top seven
+ * bits of the value mimic the seven bits clipped off
+ * by the PCI Host controller.
+ *
+ * With OATRAN at the said value, when the CPU does
+ * an access to its virtual address at, say 0xB900_5000,
+ * the address appearing on the PCI bus will be
+ * 0xB900_5000.
+ *    - Michael Penner
+ */
+#define MSP_PCI_OATRAN          0xB8000000UL
+#define MSP_PCI_SPACE_BASE      (MSP_PCI_OATRAN + 0x1002000UL)
+#define MSP_PCI_SPACE_SIZE      (0x3000000UL - 0x2000)
+#define MSP_PCI_SPACE_END \
+                (MSP_PCI_SPACE_BASE + MSP_PCI_SPACE_SIZE - 1)
+#define MSP_PCI_IOSPACE_BASE    (MSP_PCI_OATRAN + 0x1001000UL)
+#define MSP_PCI_IOSPACE_SIZE    0x1000
+#define MSP_PCI_IOSPACE_END  \
+                (MSP_PCI_IOSPACE_BASE + MSP_PCI_IOSPACE_SIZE - 1)
+/* IRQ for PCI status interrupts */
+#define PCI_STAT_IRQ    20
+#define QFLUSH_REG_1    0xB7F40000
+typedef volatile unsigned int pcireg;
+typedef void * volatile ppcireg;
+struct pci_block_copy
+{
+    pcireg   unused1; /* +0x00 */
+    pcireg   unused2; /* +0x04 */
+    ppcireg  unused3; /* +0x08 */
+    ppcireg  unused4; /* +0x0C */
+    pcireg   unused5; /* +0x10 */
+    pcireg   unused6; /* +0x14 */
+    pcireg   unused7; /* +0x18 */
+    ppcireg  unused8; /* +0x1C */
+    ppcireg  unused9; /* +0x20 */
+    pcireg   unusedA; /* +0x24 */
+    ppcireg  unusedB; /* +0x28 */
+    ppcireg  unusedC; /* +0x2C */
+};
+enum
+{
+    config_device_vendor,  /* 0 */
+    config_status_command, /* 1 */
+    config_class_revision, /* 2 */
+    config_BIST_header_latency_cache, /* 3 */
+    config_BAR0,           /* 4 */
+    config_BAR1,           /* 5 */
+    config_BAR2,           /* 6 */
+    config_not_used7,      /* 7 */
+    config_not_used8,      /* 8 */
+    config_not_used9,      /* 9 */
+    config_CIS,            /* 10 */
+    config_subsystem,      /* 11 */
+    config_not_used12,     /* 12 */
+    config_capabilities,   /* 13 */
+    config_not_used14,     /* 14 */
+    config_lat_grant_irq,  /* 15 */
+    config_message_control,/* 16 */
+    config_message_addr,   /* 17 */
+    config_message_data,   /* 18 */
+    config_VPD_addr,       /* 19 */
+    config_VPD_data,       /* 20 */
+    config_maxregs         /* 21 - number of registers */
+};
+struct msp_pci_regs
+{
+    pcireg hop_unused_00; /* +0x00 */
+    pcireg hop_unused_04; /* +0x04 */
+    pcireg hop_unused_08; /* +0x08 */
+    pcireg hop_unused_0C; /* +0x0C */
+    pcireg hop_unused_10; /* +0x10 */
+    pcireg hop_unused_14; /* +0x14 */
+    pcireg hop_unused_18; /* +0x18 */
+    pcireg hop_unused_1C; /* +0x1C */
+    pcireg hop_unused_20; /* +0x20 */
+    pcireg hop_unused_24; /* +0x24 */
+    pcireg hop_unused_28; /* +0x28 */
+    pcireg hop_unused_2C; /* +0x2C */
+    pcireg hop_unused_30; /* +0x30 */
+    pcireg hop_unused_34; /* +0x34 */
+    pcireg if_control;    /* +0x38 */
+    pcireg oatran;        /* +0x3C */
+    pcireg reset_ctl;     /* +0x40 */
+    pcireg config_addr;   /* +0x44 */
+    pcireg hop_unused_48; /* +0x48 */
+    pcireg msg_signaled_int_status; /* +0x4C */
+    pcireg msg_signaled_int_mask;   /* +0x50 */
+    pcireg if_status;     /* +0x54 */
+    pcireg if_mask;       /* +0x58 */
+    pcireg hop_unused_5C; /* +0x5C */
+    pcireg hop_unused_60; /* +0x60 */
+    pcireg hop_unused_64; /* +0x64 */
+    pcireg hop_unused_68; /* +0x68 */
+    pcireg hop_unused_6C; /* +0x6C */
+    pcireg hop_unused_70; /* +0x70 */
+    struct pci_block_copy pci_bc[2] __attribute__((aligned(64)));
+    pcireg error_hdr1; /* +0xE0 */
+    pcireg error_hdr2; /* +0xE4 */
+    pcireg config[config_maxregs] __attribute__((aligned(256)));
+};
+#define BPCI_CFGADDR_BUSNUM_SHF 16
+#define BPCI_CFGADDR_FUNCTNUM_SHF 8
+#define BPCI_CFGADDR_REGNUM_SHF 2
+#define BPCI_CFGADDR_ENABLE (1<<31)
+#define BPCI_IFCONTROL_RTO (1<<20) /* Retry timeout */
+#define BPCI_IFCONTROL_HCE (1<<16) /* Host configuration enable */
+#define BPCI_IFCONTROL_CTO_SHF 12  /* Shift count for CTO bits */
+#define BPCI_IFCONTROL_SE  (1<<5)  /* Enable exceptions on errors */
+#define BPCI_IFCONTROL_BIST (1<<4) /* Use BIST in per. mode */
+#define BPCI_IFCONTROL_CAP (1<<3)  /* Enable capabilities */
+#define BPCI_IFCONTROL_MMC_SHF 0   /* Shift count for MMC bits */
+#define BPCI_IFSTATUS_MGT  (1<<8)  /* Master Grant timeout */
+#define BPCI_IFSTATUS_MTT  (1<<9)  /* Master TRDY timeout */
+#define BPCI_IFSTATUS_MRT  (1<<10) /* Master retry timeout */
+#define BPCI_IFSTATUS_BC0F (1<<13) /* Block copy 0 fault */
+#define BPCI_IFSTATUS_BC1F (1<<14) /* Block copy 1 fault */
+#define BPCI_IFSTATUS_PCIU (1<<15) /* PCI unable to respond */
+#define BPCI_IFSTATUS_BSIZ (1<<16) /* PCI access with illegal size */
+#define BPCI_IFSTATUS_BADD (1<<17) /* PCI access with illegal addr */
+#define BPCI_IFSTATUS_RTO  (1<<18) /* Retry time out */
+#define BPCI_IFSTATUS_SER  (1<<19) /* System error */
+#define BPCI_IFSTATUS_PER  (1<<20) /* Parity error */
+#define BPCI_IFSTATUS_LCA  (1<<21) /* Local CPU abort */
+#define BPCI_IFSTATUS_MEM  (1<<22) /* Memory prot. violation */
+#define BPCI_IFSTATUS_ARB  (1<<23) /* Arbiter timed out */
+#define BPCI_IFSTATUS_STA  (1<<27) /* Signaled target abort */
+#define BPCI_IFSTATUS_TA   (1<<28) /* Target abort */
+#define BPCI_IFSTATUS_MA   (1<<29) /* Master abort */
+#define BPCI_IFSTATUS_PEI  (1<<30) /* Parity error as initiator */
+#define BPCI_IFSTATUS_PET  (1<<31) /* Parity error as target */
+#define BPCI_RESETCTL_PR (1<<0)    /* True if reset asserted */
+#define BPCI_RESETCTL_RT (1<<4)    /* Release time */
+#define BPCI_RESETCTL_CT (1<<8)    /* Config time */
+#define BPCI_RESETCTL_PE (1<<12)   /* PCI enabled */
+#define BPCI_RESETCTL_HM (1<<13)   /* PCI host mode */
+#define BPCI_RESETCTL_RI (1<<14)   /* PCI reset in */
+extern struct msp_pci_regs msp_pci_regs
+                        __attribute__((section(".register")));
+extern unsigned long msp_pci_config_space
+                        __attribute__((section(".register")));
+#endif /* !_MSP_PCI_H_ */
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_prom.h b/include/asm-mips/pmc-sierra/msp71xx/msp_prom.h
new file mode 100644
index 000000000000..14ca7dc382a8
--- /dev/null
+++ b/include/asm-mips/pmc-sierra/msp71xx/msp_prom.h
@@ -0,0 +1,176 @@
+/*
+ * MIPS boards bootprom interface for the Linux kernel.
+ *
+ * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ * Author: Carsten Langgaard, carstenl@mips.com
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ */
+#ifndef _ASM_MSP_PROM_H
+#define _ASM_MSP_PROM_H
+#include <linux/types.h>
+#define DEVICEID                        "deviceid"
+#define FEATURES                        "features"
+#define PROM_ENV                        "prom_env"
+#define PROM_ENV_FILE                   "/proc/"PROM_ENV
+#define PROM_ENV_SIZE                   256
+#define CPU_DEVID_FAMILY                0x0000ff00
+#define CPU_DEVID_REVISION              0x000000ff
+#define FPGA_IS_POLO(revision) \
+                (((revision >= 0xb0) && (revision < 0xd0)))
+#define FPGA_IS_5000(revision) \
+                ((revision >= 0x80) && (revision <= 0x90))
+#define FPGA_IS_ZEUS(revision)          ((revision < 0x7f))
+#define FPGA_IS_DUET(revision) \
+                (((revision >= 0xa0) && (revision < 0xb0)))
+#define FPGA_IS_MSP4200(revision)       ((revision >= 0xd0))
+#define FPGA_IS_MSP7100(revision)       ((revision >= 0xd0))
+#define MACHINE_TYPE_POLO               "POLO"
+#define MACHINE_TYPE_DUET               "DUET"
+#define MACHINE_TYPE_ZEUS               "ZEUS"
+#define MACHINE_TYPE_MSP2000REVB        "MSP2000REVB"
+#define MACHINE_TYPE_MSP5000            "MSP5000"
+#define MACHINE_TYPE_MSP4200            "MSP4200"
+#define MACHINE_TYPE_MSP7120            "MSP7120"
+#define MACHINE_TYPE_MSP7130            "MSP7130"
+#define MACHINE_TYPE_OTHER              "OTHER"
+#define MACHINE_TYPE_POLO_FPGA          "POLO-FPGA"
+#define MACHINE_TYPE_DUET_FPGA          "DUET-FPGA"
+#define MACHINE_TYPE_ZEUS_FPGA          "ZEUS_FPGA"
+#define MACHINE_TYPE_MSP2000REVB_FPGA   "MSP2000REVB-FPGA"
+#define MACHINE_TYPE_MSP5000_FPGA       "MSP5000-FPGA"
+#define MACHINE_TYPE_MSP4200_FPGA       "MSP4200-FPGA"
+#define MACHINE_TYPE_MSP7100_FPGA       "MSP7100-FPGA"
+#define MACHINE_TYPE_OTHER_FPGA         "OTHER-FPGA"
+/* Device Family definitions */
+#define FAMILY_FPGA                     0x0000
+#define FAMILY_ZEUS                     0x1000
+#define FAMILY_POLO                     0x2000
+#define FAMILY_DUET                     0x4000
+#define FAMILY_TRIAD                    0x5000
+#define FAMILY_MSP4200                  0x4200
+#define FAMILY_MSP4200_FPGA             0x4f00
+#define FAMILY_MSP7100                  0x7100
+#define FAMILY_MSP7100_FPGA             0x7f00
+/* Device Type definitions */
+#define TYPE_MSP7120                    0x7120
+#define TYPE_MSP7130                    0x7130
+#define ENET_KEY                'E'
+#define ENETTXD_KEY             'e'
+#define PCI_KEY                 'P'
+#define PCIMUX_KEY              'p'
+#define SEC_KEY                 'S'
+#define SPAD_KEY                'D'
+#define TDM_KEY                 'T'
+#define ZSP_KEY                 'Z'
+#define FEATURE_NOEXIST         '-'
+#define FEATURE_EXIST           '+'
+#define ENET_MII                'M'
+#define ENET_RMII               'R'
+#define ENETTXD_FALLING         'F'
+#define ENETTXD_RISING          'R'
+#define PCI_HOST                'H'
+#define PCI_PERIPHERAL          'P'
+#define PCIMUX_FULL             'F'
+#define PCIMUX_SINGLE           'S'
+#define SEC_DUET                'D'
+#define SEC_POLO                'P'
+#define SEC_SLOW                'S'
+#define SEC_TRIAD               'T'
+#define SPAD_POLO               'P'
+#define TDM_DUET                'D'     /* DUET TDMs might exist */
+#define TDM_POLO                'P'     /* POLO TDMs might exist */
+#define TDM_TRIAD               'T'     /* TRIAD TDMs might exist */
+#define ZSP_DUET                'D'     /* one DUET zsp engine */
+#define ZSP_TRIAD               'T'     /* two TRIAD zsp engines */
+extern char *prom_getcmdline(void);
+extern char *prom_getenv(char *name);
+extern void prom_init_cmdline(void);
+extern void prom_meminit(void);
+extern void prom_fixup_mem_map(unsigned long start_mem,
+                               unsigned long end_mem);
+#ifdef CONFIG_MTD_PMC_MSP_RAMROOT
+extern bool get_ramroot(void **start, unsigned long *size);
+#endif
+extern int get_ethernet_addr(char *ethaddr_name, char *ethernet_addr);
+extern unsigned long get_deviceid(void);
+extern char identify_enet(unsigned long interface_num);
+extern char identify_enetTxD(unsigned long interface_num);
+extern char identify_pci(void);
+extern char identify_sec(void);
+extern char identify_spad(void);
+extern char identify_sec(void);
+extern char identify_tdm(void);
+extern char identify_zsp(void);
+extern unsigned long identify_family(void);
+extern unsigned long identify_revision(void);
+/*
+ * The following macro calls prom_printf and puts the format string
+ * into an init section so it can be reclaimed.
+ */
+#define ppfinit(f, x...) \
+        do { \
+                static char _f[] __initdata = KERN_INFO f; \
+                printk(_f, ## x); \
+        } while (0)
+/* Memory descriptor management. */
+#define PROM_MAX_PMEMBLOCKS    7        /* 6 used */
+enum yamon_memtypes {
+        yamon_dontuse,
+        yamon_prom,
+        yamon_free,
+};
+struct prom_pmemblock {
+        unsigned long base; /* Within KSEG0. */
+        unsigned int size;  /* In bytes. */
+        unsigned int type;  /* free or prom memory */
+};
+extern int prom_argc;
+extern char **prom_argv;
+extern char **prom_envp;
+extern int *prom_vec;
+extern struct prom_pmemblock *prom_getmdesc(void);
+#endif /* !_ASM_MSP_PROM_H */
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_regops.h b/include/asm-mips/pmc-sierra/msp71xx/msp_regops.h
new file mode 100644
index 000000000000..60a5a38dd5b2
--- /dev/null
+++ b/include/asm-mips/pmc-sierra/msp71xx/msp_regops.h
@@ -0,0 +1,236 @@
+/*
+ * SMP/VPE-safe functions to access "registers" (see note).
+ *
+ * NOTES:
+* - These macros use ll/sc instructions, so it is your responsibility to
+ * ensure these are available on your platform before including this file.
+ * - The MIPS32 spec states that ll/sc results are undefined for uncached
+ * accesses. This means they can't be used on HW registers accessed
+ * through kseg1. Code which requires these macros for this purpose must
+ * front-end the registers with cached memory "registers" and have a single
+ * thread update the actual HW registers.
+ * - A maximum of 2k of code can be inserted between ll and sc. Every
+ * memory accesses between the instructions will increase the chance of
+ * sc failing and having to loop.
+ * - When using custom_read_reg32/custom_write_reg32 only perform the
+ * necessary logical operations on the register value in between these
+ * two calls. All other logic should be performed before the first call.
+  * - There is a bug on the R10000 chips which has a workaround. If you
+ * are affected by this bug, make sure to define the symbol 'R10000_LLSC_WAR'
+ * to be non-zero.  If you are using this header from within linux, you may
+ * include <asm/war.h> before including this file to have this defined
+ * appropriately for you.
+ *
+ * Copyright 2005-2007 PMC-Sierra, Inc.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO
+ *  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF USE,
+ *  DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc., 675
+ *  Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __ASM_REGOPS_H__
+#define __ASM_REGOPS_H__
+#include <linux/types.h>
+#include <asm/war.h>
+#ifndef R10000_LLSC_WAR
+#define R10000_LLSC_WAR 0
+#endif
+#if R10000_LLSC_WAR == 1
+#define __beqz  "beqzl  "
+#else
+#define __beqz  "beqz   "
+#endif
+#ifndef _LINUX_TYPES_H
+typedef unsigned int u32;
+#endif
+/*
+ * Sets all the masked bits to the corresponding value bits
+ */
+static inline void set_value_reg32(volatile u32 *const addr,
+                                        u32 const mask,
+                                        u32 const value)
+{
+        u32 temp;
+        __asm__ __volatile__(
+        "       .set    push                            \n"
+        "       .set    mips3                           \n"
+        "1:     ll      %0, %1  # set_value_reg32       \n"
+        "       and     %0, %2                          \n"
+        "       or      %0, %3                          \n"
+        "       sc      %0, %1                          \n"
+        "       "__beqz"%0, 1b                          \n"
+        "       nop                                     \n"
+        "       .set    pop                             \n"
+        : "=&r" (temp), "=m" (*addr)
+        : "ir" (~mask), "ir" (value), "m" (*addr));
+}
+/*
+ * Sets all the masked bits to '1'
+ */
+static inline void set_reg32(volatile u32 *const addr,
+                                u32 const mask)
+{
+        u32 temp;
+        __asm__ __volatile__(
+        "       .set    push                            \n"
+        "       .set    mips3                           \n"
+        "1:     ll      %0, %1          # set_reg32     \n"
+        "       or      %0, %2                          \n"
+        "       sc      %0, %1                          \n"
+        "       "__beqz"%0, 1b                          \n"
+        "       nop                                     \n"
+        "       .set    pop                             \n"
+        : "=&r" (temp), "=m" (*addr)
+        : "ir" (mask), "m" (*addr));
+}
+/*
+ * Sets all the masked bits to '0'
+ */
+static inline void clear_reg32(volatile u32 *const addr,
+                                u32 const mask)
+{
+        u32 temp;
+        __asm__ __volatile__(
+        "       .set    push                            \n"
+        "       .set    mips3                           \n"
+        "1:     ll      %0, %1          # clear_reg32   \n"
+        "       and     %0, %2                          \n"
+        "       sc      %0, %1                          \n"
+        "       "__beqz"%0, 1b                          \n"
+        "       nop                                     \n"
+        "       .set    pop                             \n"
+        : "=&r" (temp), "=m" (*addr)
+        : "ir" (~mask), "m" (*addr));
+}
+/*
+ * Toggles all masked bits from '0' to '1' and '1' to '0'
+ */
+static inline void toggle_reg32(volatile u32 *const addr,
+                                u32 const mask)
+{
+        u32 temp;
+        __asm__ __volatile__(
+        "       .set    push                            \n"
+        "       .set    mips3                           \n"
+        "1:     ll      %0, %1          # toggle_reg32  \n"
+        "       xor     %0, %2                          \n"
+        "       sc      %0, %1                          \n"
+        "       "__beqz"%0, 1b                          \n"
+        "       nop                                     \n"
+        "       .set    pop                             \n"
+        : "=&r" (temp), "=m" (*addr)
+        : "ir" (mask), "m" (*addr));
+}
+/*
+ * Read all masked bits others are returned as '0'
+ */
+static inline u32 read_reg32(volatile u32 *const addr,
+                                u32 const mask)
+{
+        u32 temp;
+        __asm__ __volatile__(
+        "       .set    push                            \n"
+        "       .set    noreorder                       \n"
+        "       lw      %0, %1          # read          \n"
+        "       and     %0, %2          # mask          \n"
+        "       .set    pop                             \n"
+        : "=&r" (temp)
+        : "m" (*addr), "ir" (mask));
+        return temp;
+}
+/*
+ * blocking_read_reg32 - Read address with blocking load
+ *
+ * Uncached writes need to be read back to ensure they reach RAM.
+ * The returned value must be 'used' to prevent from becoming a
+ * non-blocking load.
+ */
+static inline u32 blocking_read_reg32(volatile u32 *const addr)
+{
+        u32 temp;
+        __asm__ __volatile__(
+        "       .set    push                            \n"
+        "       .set    noreorder                       \n"
+        "       lw      %0, %1          # read          \n"
+        "       move    %0, %0          # block         \n"
+        "       .set    pop                             \n"
+        : "=&r" (temp)
+        : "m" (*addr));
+        return temp;
+}
+/*
+ * For special strange cases only:
+ *
+ * If you need custom processing within a ll/sc loop, use the following macros
+ * VERY CAREFULLY:
+ *
+ *   u32 tmp;                           <-- Define a variable to hold the data
+ *
+ *   custom_read_reg32(address, tmp);   <-- Reads the address and put the value
+ *                                              in the 'tmp' variable given
+ *
+ *      From here on out, you are (basicly) atomic, so don't do anything too
+ *      fancy!
+ *      Also, this code may loop if the end of this block fails to write
+ *      everything back safely due do the other CPU, so do NOT do anything
+ *      with side-effects!
+ *
+ *   custom_write_reg32(address, tmp);  <-- Writes back 'tmp' safely.
+ */
+#define custom_read_reg32(address, tmp)                         \
+        __asm__ __volatile__(                                   \
+        "       .set    push                            \n"     \
+        "       .set    mips3                           \n"     \
+        "1:     ll      %0, %1  #custom_read_reg32      \n"     \
+        "       .set    pop                             \n"     \
+        : "=r" (tmp), "=m" (*address)                           \
+        : "m" (*address))
+#define custom_write_reg32(address, tmp)                        \
+        __asm__ __volatile__(                                   \
+        "       .set    push                            \n"     \
+        "       .set    mips3                           \n"     \
+        "       sc      %0, %1  #custom_write_reg32     \n"     \
+        "       "__beqz"%0, 1b                          \n"     \
+        "       nop                                     \n"     \
+        "       .set    pop                             \n"     \
+        : "=&r" (tmp), "=m" (*address)                          \
+        : "0" (tmp), "m" (*address))
+#endif  /* __ASM_REGOPS_H__ */
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_regs.h b/include/asm-mips/pmc-sierra/msp71xx/msp_regs.h
new file mode 100644
index 000000000000..0b56f55206c6
--- /dev/null
+++ b/include/asm-mips/pmc-sierra/msp71xx/msp_regs.h
@@ -0,0 +1,667 @@
+/*
+ * Defines for the address space, registers and register configuration
+ * (bit masks, access macros etc) for the PMC-Sierra line of MSP products.
+ * This file contains addess maps for all the devices in the line of
+ * products but only has register definitions and configuration masks for
+ * registers which aren't definitely associated with any device.  Things
+ * like clock settings, reset access, the ELB etc.  Individual device
+ * drivers will reference the appropriate XXX_BASE value defined here
+ * and have individual registers offset from that.
+ *
+ * Copyright (C) 2005-2007 PMC-Sierra, Inc.  All rights reserved.
+ * Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ */
+#include <asm/addrspace.h>
+#include <linux/types.h>
+#ifndef _ASM_MSP_REGS_H
+#define _ASM_MSP_REGS_H
+/*
+ ########################################################################
+ #  Address space and device base definitions                           #
+ ########################################################################
+ */
+/*
+ ***************************************************************************
+ * System Logic and Peripherals (ELB, UART0, etc) device address space     *
+ ***************************************************************************
+ */
+#define MSP_SLP_BASE            0x1c000000
+                                        /* System Logic and Peripherals */
+#define MSP_RST_BASE            (MSP_SLP_BASE + 0x10)
+                                        /* System reset register base   */
+#define MSP_RST_SIZE            0x0C    /* System reset register space  */
+#define MSP_WTIMER_BASE         (MSP_SLP_BASE + 0x04C)
+                                        /* watchdog timer base          */
+#define MSP_ITIMER_BASE         (MSP_SLP_BASE + 0x054)
+                                        /* internal timer base          */
+#define MSP_UART0_BASE          (MSP_SLP_BASE + 0x100)
+                                        /* UART0 controller base        */
+#define MSP_BCPY_CTRL_BASE      (MSP_SLP_BASE + 0x120)
+                                        /* Block Copy controller base   */
+#define MSP_BCPY_DESC_BASE      (MSP_SLP_BASE + 0x160)
+                                        /* Block Copy descriptor base   */
+/*
+ ***************************************************************************
+ * PCI address space                                                       *
+ ***************************************************************************
+ */
+#define MSP_PCI_BASE            0x19000000
+/*
+ ***************************************************************************
+ * MSbus device address space                                              *
+ ***************************************************************************
+ */
+#define MSP_MSB_BASE            0x18000000
+                                        /* MSbus address start          */
+#define MSP_PER_BASE            (MSP_MSB_BASE + 0x400000)
+                                        /* Peripheral device registers  */
+#define MSP_MAC0_BASE           (MSP_MSB_BASE + 0x600000)
+                                        /* MAC A device registers       */
+#define MSP_MAC1_BASE           (MSP_MSB_BASE + 0x700000)
+                                        /* MAC B device registers       */
+#define MSP_MAC_SIZE            0xE0    /* MAC register space           */
+#define MSP_SEC_BASE            (MSP_MSB_BASE + 0x800000)
+                                        /* Security Engine registers    */
+#define MSP_MAC2_BASE           (MSP_MSB_BASE + 0x900000)
+                                        /* MAC C device registers       */
+#define MSP_ADSL2_BASE          (MSP_MSB_BASE + 0xA80000)
+                                        /* ADSL2 device registers       */
+#define MSP_USB_BASE            (MSP_MSB_BASE + 0xB40000)
+                                        /* USB device registers         */
+#define MSP_USB_BASE_START      (MSP_MSB_BASE + 0xB40100)
+                                        /* USB device registers         */
+#define MSP_USB_BASE_END        (MSP_MSB_BASE + 0xB401FF)
+                                        /* USB device registers         */
+#define MSP_CPUIF_BASE          (MSP_MSB_BASE + 0xC00000)
+                                        /* CPU interface registers      */
+/* Devices within the MSbus peripheral block */
+#define MSP_UART1_BASE          (MSP_PER_BASE + 0x030)
+                                        /* UART1 controller base        */
+#define MSP_SPI_BASE            (MSP_PER_BASE + 0x058)
+                                        /* SPI/MPI control registers    */
+#define MSP_TWI_BASE            (MSP_PER_BASE + 0x090)
+                                        /* Two-wire control registers   */
+#define MSP_PTIMER_BASE         (MSP_PER_BASE + 0x0F0)
+                                        /* Programmable timer control   */
+/*
+ ***************************************************************************
+ * Physical Memory configuration address space                             *
+ ***************************************************************************
+ */
+#define MSP_MEM_CFG_BASE        0x17f00000
+#define MSP_MEM_INDIRECT_CTL_10 0x10
+/*
+ * Notes:
+ *  1) The SPI registers are split into two blocks, one offset from the
+ *     MSP_SPI_BASE by 0x00 and the other offset from the MSP_SPI_BASE by
+ *     0x68.  The SPI driver definitions for the register must be aware
+ *     of this.
+ *  2) The block copy engine register are divided into two regions, one
+ *     for the control/configuration of the engine proper and one for the
+ *     values of the descriptors used in the copy process.  These have
+ *     different base defines (CTRL_BASE vs DESC_BASE)
+ *  3) These constants are for physical addresses which means that they
+ *     work correctly with "ioremap" and friends.  This means that device
+ *     drivers will need to remap these addresses using ioremap and perhaps
+ *     the readw/writew macros.  Or they could use the regptr() macro
+ *     defined below, but the readw/writew calls are the correct thing.
+ *  4) The UARTs have an additional status register offset from the base
+ *     address.  This register isn't used in the standard 8250 driver but
+ *     may be used in other software.  Consult the hardware datasheet for
+ *     offset details.
+ *  5) For some unknown reason the security engine (MSP_SEC_BASE) registers
+ *     start at an offset of 0x84 from the base address but the block of
+ *     registers before this is reserved for the security engine.  The
+ *     driver will have to be aware of this but it makes the register
+ *     definitions line up better with the documentation.
+ */
+/*
+ ########################################################################
+ #  System register definitions.  Not associated with a specific device #
+ ########################################################################
+ */
+/*
+ * This macro maps the physical register number into uncached space
+ * and (for C code) casts it into a u32 pointer so it can be dereferenced
+ * Normally these would be accessed with ioremap and readX/writeX, but
+ * these are convenient for a lot of internal kernel code.
+ */
+#ifdef __ASSEMBLER__
+        #define regptr(addr) (KSEG1ADDR(addr))
+#else
+        #define regptr(addr) ((volatile u32 *const)(KSEG1ADDR(addr)))
+#endif
+/*
+ ***************************************************************************
+ * System Logic and Peripherals (RESET, ELB, etc) registers                *
+ ***************************************************************************
+ */
+/* System Control register definitions */
+#define DEV_ID_REG      regptr(MSP_SLP_BASE + 0x00)
+                                        /* Device-ID                 RO */
+#define FWR_ID_REG      regptr(MSP_SLP_BASE + 0x04)
+                                        /* Firmware-ID Register      RW */
+#define SYS_ID_REG0     regptr(MSP_SLP_BASE + 0x08)
+                                        /* System-ID Register-0      RW */
+#define SYS_ID_REG1     regptr(MSP_SLP_BASE + 0x0C)
+                                        /* System-ID Register-1      RW */
+/* System Reset register definitions */
+#define RST_STS_REG     regptr(MSP_SLP_BASE + 0x10)
+                                        /* System Reset Status       RO */
+#define RST_SET_REG     regptr(MSP_SLP_BASE + 0x14)
+                                        /* System Set Reset          WO */
+#define RST_CLR_REG     regptr(MSP_SLP_BASE + 0x18)
+                                        /* System Clear Reset        WO */
+/* System Clock Registers */
+#define PCI_SLP_REG     regptr(MSP_SLP_BASE + 0x1C)
+                                        /* PCI clock generator       RW */
+#define URT_SLP_REG     regptr(MSP_SLP_BASE + 0x20)
+                                        /* UART clock generator      RW */
+/* reserved                   (MSP_SLP_BASE + 0x24)                     */
+/* reserved                   (MSP_SLP_BASE + 0x28)                     */
+#define PLL1_SLP_REG    regptr(MSP_SLP_BASE + 0x2C)
+                                        /* PLL1 clock generator      RW */
+#define PLL0_SLP_REG    regptr(MSP_SLP_BASE + 0x30)
+                                        /* PLL0 clock generator      RW */
+#define MIPS_SLP_REG    regptr(MSP_SLP_BASE + 0x34)
+                                        /* MIPS clock generator      RW */
+#define VE_SLP_REG      regptr(MSP_SLP_BASE + 0x38)
+                                        /* Voice Eng clock generator RW */
+/* reserved                   (MSP_SLP_BASE + 0x3C)                     */
+#define MSB_SLP_REG     regptr(MSP_SLP_BASE + 0x40)
+                                        /* MS-Bus clock generator    RW */
+#define SMAC_SLP_REG    regptr(MSP_SLP_BASE + 0x44)
+                                        /* Sec & MAC clock generator RW */
+#define PERF_SLP_REG    regptr(MSP_SLP_BASE + 0x48)
+                                        /* Per & TDM clock generator RW */
+/* Interrupt Controller Registers */
+#define SLP_INT_STS_REG regptr(MSP_SLP_BASE + 0x70)
+                                        /* Interrupt status register RW */
+#define SLP_INT_MSK_REG regptr(MSP_SLP_BASE + 0x74)
+                                        /* Interrupt enable/mask     RW */
+#define SE_MBOX_REG     regptr(MSP_SLP_BASE + 0x78)
+                                        /* Security Engine mailbox   RW */
+#define VE_MBOX_REG     regptr(MSP_SLP_BASE + 0x7C)
+                                        /* Voice Engine mailbox      RW */
+/* ELB Controller Registers */
+#define CS0_CNFG_REG    regptr(MSP_SLP_BASE + 0x80)
+                                        /* ELB CS0 Configuration Reg    */
+#define CS0_ADDR_REG    regptr(MSP_SLP_BASE + 0x84)
+                                        /* ELB CS0 Base Address Reg     */
+#define CS0_MASK_REG    regptr(MSP_SLP_BASE + 0x88)
+                                        /* ELB CS0 Mask Register        */
+#define CS0_ACCESS_REG  regptr(MSP_SLP_BASE + 0x8C)
+                                        /* ELB CS0 access register      */
+#define CS1_CNFG_REG    regptr(MSP_SLP_BASE + 0x90)
+                                        /* ELB CS1 Configuration Reg    */
+#define CS1_ADDR_REG    regptr(MSP_SLP_BASE + 0x94)
+                                        /* ELB CS1 Base Address Reg     */
+#define CS1_MASK_REG    regptr(MSP_SLP_BASE + 0x98)
+                                        /* ELB CS1 Mask Register        */
+#define CS1_ACCESS_REG  regptr(MSP_SLP_BASE + 0x9C)
+                                        /* ELB CS1 access register      */
+#define CS2_CNFG_REG    regptr(MSP_SLP_BASE + 0xA0)
+                                        /* ELB CS2 Configuration Reg    */
+#define CS2_ADDR_REG    regptr(MSP_SLP_BASE + 0xA4)
+                                        /* ELB CS2 Base Address Reg     */
+#define CS2_MASK_REG    regptr(MSP_SLP_BASE + 0xA8)
+                                        /* ELB CS2 Mask Register        */
+#define CS2_ACCESS_REG  regptr(MSP_SLP_BASE + 0xAC)
+                                        /* ELB CS2 access register      */
+#define CS3_CNFG_REG    regptr(MSP_SLP_BASE + 0xB0)
+                                        /* ELB CS3 Configuration Reg    */
+#define CS3_ADDR_REG    regptr(MSP_SLP_BASE + 0xB4)
+                                        /* ELB CS3 Base Address Reg     */
+#define CS3_MASK_REG    regptr(MSP_SLP_BASE + 0xB8)
+                                        /* ELB CS3 Mask Register        */
+#define CS3_ACCESS_REG  regptr(MSP_SLP_BASE + 0xBC)
+                                        /* ELB CS3 access register      */
+#define CS4_CNFG_REG    regptr(MSP_SLP_BASE + 0xC0)
+                                        /* ELB CS4 Configuration Reg    */
+#define CS4_ADDR_REG    regptr(MSP_SLP_BASE + 0xC4)
+                                        /* ELB CS4 Base Address Reg     */
+#define CS4_MASK_REG    regptr(MSP_SLP_BASE + 0xC8)
+                                        /* ELB CS4 Mask Register        */
+#define CS4_ACCESS_REG  regptr(MSP_SLP_BASE + 0xCC)
+                                        /* ELB CS4 access register      */
+#define CS5_CNFG_REG    regptr(MSP_SLP_BASE + 0xD0)
+                                        /* ELB CS5 Configuration Reg    */
+#define CS5_ADDR_REG    regptr(MSP_SLP_BASE + 0xD4)
+                                        /* ELB CS5 Base Address Reg     */
+#define CS5_MASK_REG    regptr(MSP_SLP_BASE + 0xD8)
+                                        /* ELB CS5 Mask Register        */
+#define CS5_ACCESS_REG  regptr(MSP_SLP_BASE + 0xDC)
+                                        /* ELB CS5 access register      */
+/* reserved                            0xE0 - 0xE8                      */
+#define ELB_1PC_EN_REG  regptr(MSP_SLP_BASE + 0xEC)
+                                        /* ELB single PC card detect    */
+/* reserved                            0xF0 - 0xF8                      */
+#define ELB_CLK_CFG_REG regptr(MSP_SLP_BASE + 0xFC)
+                                        /* SDRAM read/ELB timing Reg    */
+/* Extended UART status registers */
+#define UART0_STATUS_REG        regptr(MSP_UART0_BASE + 0x0c0)
+                                        /* UART Status Register 0       */
+#define UART1_STATUS_REG        regptr(MSP_UART1_BASE + 0x170)
+                                        /* UART Status Register 1       */
+/* Performance monitoring registers */
+#define PERF_MON_CTRL_REG       regptr(MSP_SLP_BASE + 0x140)
+                                        /* Performance monitor control  */
+#define PERF_MON_CLR_REG        regptr(MSP_SLP_BASE + 0x144)
+                                        /* Performance monitor clear    */
+#define PERF_MON_CNTH_REG       regptr(MSP_SLP_BASE + 0x148)
+                                        /* Perf monitor counter high    */
+#define PERF_MON_CNTL_REG       regptr(MSP_SLP_BASE + 0x14C)
+                                        /* Perf monitor counter low     */
+/* System control registers */
+#define SYS_CTRL_REG            regptr(MSP_SLP_BASE + 0x150)
+                                        /* System control register      */
+#define SYS_ERR1_REG            regptr(MSP_SLP_BASE + 0x154)
+                                        /* System Error status 1        */
+#define SYS_ERR2_REG            regptr(MSP_SLP_BASE + 0x158)
+                                        /* System Error status 2        */
+#define SYS_INT_CFG_REG         regptr(MSP_SLP_BASE + 0x15C)
+                                        /* System Interrupt config      */
+/* Voice Engine Memory configuration */
+#define VE_MEM_REG              regptr(MSP_SLP_BASE + 0x17C)
+                                        /* Voice engine memory config   */
+/* CPU/SLP Error Status registers */
+#define CPU_ERR1_REG            regptr(MSP_SLP_BASE + 0x180)
+                                        /* CPU/SLP Error status 1       */
+#define CPU_ERR2_REG            regptr(MSP_SLP_BASE + 0x184)
+                                        /* CPU/SLP Error status 1       */
+#define EXTENDED_GPIO_REG       regptr(MSP_SLP_BASE + 0x188)
+                                        /* Extended GPIO register       */
+/* System Error registers */
+#define SLP_ERR_STS_REG         regptr(MSP_SLP_BASE + 0x190)
+                                        /* Int status for SLP errors    */
+#define SLP_ERR_MSK_REG         regptr(MSP_SLP_BASE + 0x194)
+                                        /* Int mask for SLP errors      */
+#define SLP_ELB_ERST_REG        regptr(MSP_SLP_BASE + 0x198)
+                                        /* External ELB reset           */
+#define SLP_BOOT_STS_REG        regptr(MSP_SLP_BASE + 0x19C)
+                                        /* Boot Status                  */
+/* Extended ELB addressing */
+#define CS0_EXT_ADDR_REG        regptr(MSP_SLP_BASE + 0x1A0)
+                                        /* CS0 Extended address         */
+#define CS1_EXT_ADDR_REG        regptr(MSP_SLP_BASE + 0x1A4)
+                                        /* CS1 Extended address         */
+#define CS2_EXT_ADDR_REG        regptr(MSP_SLP_BASE + 0x1A8)
+                                        /* CS2 Extended address         */
+#define CS3_EXT_ADDR_REG        regptr(MSP_SLP_BASE + 0x1AC)
+                                        /* CS3 Extended address         */
+/* reserved                                           0x1B0             */
+#define CS5_EXT_ADDR_REG        regptr(MSP_SLP_BASE + 0x1B4)
+                                        /* CS5 Extended address         */
+/* PLL Adjustment registers */
+#define PLL_LOCK_REG            regptr(MSP_SLP_BASE + 0x200)
+                                        /* PLL0 lock status             */
+#define PLL_ARST_REG            regptr(MSP_SLP_BASE + 0x204)
+                                        /* PLL Analog reset status      */
+#define PLL0_ADJ_REG            regptr(MSP_SLP_BASE + 0x208)
+                                        /* PLL0 Adjustment value        */
+#define PLL1_ADJ_REG            regptr(MSP_SLP_BASE + 0x20C)
+                                        /* PLL1 Adjustment value        */
+/*
+ ***************************************************************************
+ * Peripheral Register definitions                                         *
+ ***************************************************************************
+ */
+/* Peripheral status */
+#define PER_CTRL_REG            regptr(MSP_PER_BASE + 0x50)
+                                        /* Peripheral control register  */
+#define PER_STS_REG             regptr(MSP_PER_BASE + 0x54)
+                                        /* Peripheral status register   */
+/* SPI/MPI Registers */
+#define SMPI_TX_SZ_REG          regptr(MSP_PER_BASE + 0x58)
+                                        /* SPI/MPI Tx Size register     */
+#define SMPI_RX_SZ_REG          regptr(MSP_PER_BASE + 0x5C)
+                                        /* SPI/MPI Rx Size register     */
+#define SMPI_CTL_REG            regptr(MSP_PER_BASE + 0x60)
+                                        /* SPI/MPI Control register     */
+#define SMPI_MS_REG             regptr(MSP_PER_BASE + 0x64)
+                                        /* SPI/MPI Chip Select reg      */
+#define SMPI_CORE_DATA_REG      regptr(MSP_PER_BASE + 0xC0)
+                                        /* SPI/MPI Core Data reg        */
+#define SMPI_CORE_CTRL_REG      regptr(MSP_PER_BASE + 0xC4)
+                                        /* SPI/MPI Core Control reg     */
+#define SMPI_CORE_STAT_REG      regptr(MSP_PER_BASE + 0xC8)
+                                        /* SPI/MPI Core Status reg      */
+#define SMPI_CORE_SSEL_REG      regptr(MSP_PER_BASE + 0xCC)
+                                        /* SPI/MPI Core Ssel reg        */
+#define SMPI_FIFO_REG           regptr(MSP_PER_BASE + 0xD0)
+                                        /* SPI/MPI Data FIFO reg        */
+/* Peripheral Block Error Registers           */
+#define PER_ERR_STS_REG         regptr(MSP_PER_BASE + 0x70)
+                                        /* Error Bit Status Register    */
+#define PER_ERR_MSK_REG         regptr(MSP_PER_BASE + 0x74)
+                                        /* Error Bit Mask Register      */
+#define PER_HDR1_REG            regptr(MSP_PER_BASE + 0x78)
+                                        /* Error Header 1 Register      */
+#define PER_HDR2_REG            regptr(MSP_PER_BASE + 0x7C)
+                                        /* Error Header 2 Register      */
+/* Peripheral Block Interrupt Registers       */
+#define PER_INT_STS_REG         regptr(MSP_PER_BASE + 0x80)
+                                        /* Interrupt status register    */
+#define PER_INT_MSK_REG         regptr(MSP_PER_BASE + 0x84)
+                                        /* Interrupt Mask Register      */
+#define GPIO_INT_STS_REG        regptr(MSP_PER_BASE + 0x88)
+                                        /* GPIO interrupt status reg    */
+#define GPIO_INT_MSK_REG        regptr(MSP_PER_BASE + 0x8C)
+                                        /* GPIO interrupt MASK Reg      */
+/* POLO GPIO registers                        */
+#define POLO_GPIO_DAT1_REG      regptr(MSP_PER_BASE + 0x0E0)
+                                        /* Polo GPIO[8:0]  data reg     */
+#define POLO_GPIO_CFG1_REG      regptr(MSP_PER_BASE + 0x0E4)
+                                        /* Polo GPIO[7:0]  config reg   */
+#define POLO_GPIO_CFG2_REG      regptr(MSP_PER_BASE + 0x0E8)
+                                        /* Polo GPIO[15:8] config reg   */
+#define POLO_GPIO_OD1_REG       regptr(MSP_PER_BASE + 0x0EC)
+                                        /* Polo GPIO[31:0] output drive */
+#define POLO_GPIO_CFG3_REG      regptr(MSP_PER_BASE + 0x170)
+                                        /* Polo GPIO[23:16] config reg  */
+#define POLO_GPIO_DAT2_REG      regptr(MSP_PER_BASE + 0x174)
+                                        /* Polo GPIO[15:9]  data reg    */
+#define POLO_GPIO_DAT3_REG      regptr(MSP_PER_BASE + 0x178)
+                                        /* Polo GPIO[23:16]  data reg   */
+#define POLO_GPIO_DAT4_REG      regptr(MSP_PER_BASE + 0x17C)
+                                        /* Polo GPIO[31:24]  data reg   */
+#define POLO_GPIO_DAT5_REG      regptr(MSP_PER_BASE + 0x180)
+                                        /* Polo GPIO[39:32]  data reg   */
+#define POLO_GPIO_DAT6_REG      regptr(MSP_PER_BASE + 0x184)
+                                        /* Polo GPIO[47:40]  data reg   */
+#define POLO_GPIO_DAT7_REG      regptr(MSP_PER_BASE + 0x188)
+                                        /* Polo GPIO[54:48]  data reg   */
+#define POLO_GPIO_CFG4_REG      regptr(MSP_PER_BASE + 0x18C)
+                                        /* Polo GPIO[31:24] config reg  */
+#define POLO_GPIO_CFG5_REG      regptr(MSP_PER_BASE + 0x190)
+                                        /* Polo GPIO[39:32] config reg  */
+#define POLO_GPIO_CFG6_REG      regptr(MSP_PER_BASE + 0x194)
+                                        /* Polo GPIO[47:40] config reg  */
+#define POLO_GPIO_CFG7_REG      regptr(MSP_PER_BASE + 0x198)
+                                        /* Polo GPIO[54:48] config reg  */
+#define POLO_GPIO_OD2_REG       regptr(MSP_PER_BASE + 0x19C)
+                                        /* Polo GPIO[54:32] output drive */
+/* Generic GPIO registers                     */
+#define GPIO_DATA1_REG          regptr(MSP_PER_BASE + 0x170)
+                                        /* GPIO[1:0] data register      */
+#define GPIO_DATA2_REG          regptr(MSP_PER_BASE + 0x174)
+                                        /* GPIO[5:2] data register      */
+#define GPIO_DATA3_REG          regptr(MSP_PER_BASE + 0x178)
+                                        /* GPIO[9:6] data register      */
+#define GPIO_DATA4_REG          regptr(MSP_PER_BASE + 0x17C)
+                                        /* GPIO[15:10] data register    */
+#define GPIO_CFG1_REG           regptr(MSP_PER_BASE + 0x180)
+                                        /* GPIO[1:0] config register    */
+#define GPIO_CFG2_REG           regptr(MSP_PER_BASE + 0x184)
+                                        /* GPIO[5:2] config register    */
+#define GPIO_CFG3_REG           regptr(MSP_PER_BASE + 0x188)
+                                        /* GPIO[9:6] config register    */
+#define GPIO_CFG4_REG           regptr(MSP_PER_BASE + 0x18C)
+                                        /* GPIO[15:10] config register  */
+#define GPIO_OD_REG             regptr(MSP_PER_BASE + 0x190)
+                                        /* GPIO[15:0] output drive      */
+/*
+ ***************************************************************************
+ * CPU Interface register definitions                                      *
+ ***************************************************************************
+ */
+#define PCI_FLUSH_REG           regptr(MSP_CPUIF_BASE + 0x00)
+                                        /* PCI-SDRAM queue flush trigger */
+#define OCP_ERR1_REG            regptr(MSP_CPUIF_BASE + 0x04)
+                                        /* OCP Error Attribute 1        */
+#define OCP_ERR2_REG            regptr(MSP_CPUIF_BASE + 0x08)
+                                        /* OCP Error Attribute 2        */
+#define OCP_STS_REG             regptr(MSP_CPUIF_BASE + 0x0C)
+                                        /* OCP Error Status             */
+#define CPUIF_PM_REG            regptr(MSP_CPUIF_BASE + 0x10)
+                                        /* CPU policy configuration     */
+#define CPUIF_CFG_REG           regptr(MSP_CPUIF_BASE + 0x10)
+                                        /* Misc configuration options   */
+/* Central Interrupt Controller Registers */
+#define MSP_CIC_BASE            (MSP_CPUIF_BASE + 0x8000)
+                                        /* Central Interrupt registers  */
+#define CIC_EXT_CFG_REG         regptr(MSP_CIC_BASE + 0x00)
+                                        /* External interrupt config    */
+#define CIC_STS_REG             regptr(MSP_CIC_BASE + 0x04)
+                                        /* CIC Interrupt Status         */
+#define CIC_VPE0_MSK_REG        regptr(MSP_CIC_BASE + 0x08)
+                                        /* VPE0 Interrupt Mask          */
+#define CIC_VPE1_MSK_REG        regptr(MSP_CIC_BASE + 0x0C)
+                                        /* VPE1 Interrupt Mask          */
+#define CIC_TC0_MSK_REG         regptr(MSP_CIC_BASE + 0x10)
+                                        /* Thread Context 0 Int Mask    */
+#define CIC_TC1_MSK_REG         regptr(MSP_CIC_BASE + 0x14)
+                                        /* Thread Context 1 Int Mask    */
+#define CIC_TC2_MSK_REG         regptr(MSP_CIC_BASE + 0x18)
+                                        /* Thread Context 2 Int Mask    */
+#define CIC_TC3_MSK_REG         regptr(MSP_CIC_BASE + 0x18)
+                                        /* Thread Context 3 Int Mask    */
+#define CIC_TC4_MSK_REG         regptr(MSP_CIC_BASE + 0x18)
+                                        /* Thread Context 4 Int Mask    */
+#define CIC_PCIMSI_STS_REG      regptr(MSP_CIC_BASE + 0x18)
+#define CIC_PCIMSI_MSK_REG      regptr(MSP_CIC_BASE + 0x18)
+#define CIC_PCIFLSH_REG         regptr(MSP_CIC_BASE + 0x18)
+#define CIC_VPE0_SWINT_REG      regptr(MSP_CIC_BASE + 0x08)
+/*
+ ***************************************************************************
+ * Memory controller registers                                             *
+ ***************************************************************************
+ */
+#define MEM_CFG1_REG            regptr(MSP_MEM_CFG_BASE + 0x00)
+#define MEM_SS_ADDR             regptr(MSP_MEM_CFG_BASE + 0x00)
+#define MEM_SS_DATA             regptr(MSP_MEM_CFG_BASE + 0x04)
+#define MEM_SS_WRITE            regptr(MSP_MEM_CFG_BASE + 0x08)
+/*
+ ***************************************************************************
+ * PCI controller registers                                                *
+ ***************************************************************************
+ */
+#define PCI_BASE_REG            regptr(MSP_PCI_BASE + 0x00)
+#define PCI_CONFIG_SPACE_REG    regptr(MSP_PCI_BASE + 0x800)
+#define PCI_JTAG_DEVID_REG      regptr(MSP_SLP_BASE + 0x13c)
+/*
+ ########################################################################
+ #  Register content & macro definitions                                #
+ ########################################################################
+ */
+/*
+ ***************************************************************************
+ * DEV_ID defines                                                          *
+ ***************************************************************************
+ */
+#define DEV_ID_PCI_DIS          (1 << 26)       /* Set if PCI disabled */
+#define DEV_ID_PCI_HOST         (1 << 20)       /* Set if PCI host */
+#define DEV_ID_SINGLE_PC        (1 << 19)       /* Set if single PC Card */
+#define DEV_ID_FAMILY           (0xff << 8)     /* family ID code */
+#define POLO_ZEUS_SUB_FAMILY    (0x7  << 16)    /* sub family for Polo/Zeus */
+#define MSPFPGA_ID              (0x00  << 8)    /* you are on your own here */
+#define MSP5000_ID              (0x50  << 8)
+#define MSP4F00_ID              (0x4f  << 8)    /* FPGA version of MSP4200 */
+#define MSP4E00_ID              (0x4f  << 8)    /* FPGA version of MSP7120 */
+#define MSP4200_ID              (0x42  << 8)
+#define MSP4000_ID              (0x40  << 8)
+#define MSP2XXX_ID              (0x20  << 8)
+#define MSPZEUS_ID              (0x10  << 8)
+#define MSP2004_SUB_ID          (0x0   << 16)
+#define MSP2005_SUB_ID          (0x1   << 16)
+#define MSP2006_SUB_ID          (0x1   << 16)
+#define MSP2007_SUB_ID          (0x2   << 16)
+#define MSP2010_SUB_ID          (0x3   << 16)
+#define MSP2015_SUB_ID          (0x4   << 16)
+#define MSP2020_SUB_ID          (0x5   << 16)
+#define MSP2100_SUB_ID          (0x6   << 16)
+/*
+ ***************************************************************************
+ * RESET defines                                                           *
+ ***************************************************************************
+ */
+#define MSP_GR_RST              (0x01 << 0)     /* Global reset bit     */
+#define MSP_MR_RST              (0x01 << 1)     /* MIPS reset bit       */
+#define MSP_PD_RST              (0x01 << 2)     /* PVC DMA reset bit    */
+#define MSP_PP_RST              (0x01 << 3)     /* PVC reset bit        */
+/* reserved                                                             */
+#define MSP_EA_RST              (0x01 << 6)     /* Mac A reset bit      */
+#define MSP_EB_RST              (0x01 << 7)     /* Mac B reset bit      */
+#define MSP_SE_RST              (0x01 << 8)     /* Security Eng reset bit */
+#define MSP_PB_RST              (0x01 << 9)     /* Per block reset bit  */
+#define MSP_EC_RST              (0x01 << 10)    /* Mac C reset bit      */
+#define MSP_TW_RST              (0x01 << 11)    /* TWI reset bit        */
+#define MSP_SPI_RST             (0x01 << 12)    /* SPI/MPI reset bit    */
+#define MSP_U1_RST              (0x01 << 13)    /* UART1 reset bit      */
+#define MSP_U0_RST              (0x01 << 14)    /* UART0 reset bit      */
+/*
+ ***************************************************************************
+ * UART defines                                                            *
+ ***************************************************************************
+ */
+#ifndef CONFIG_MSP_FPGA
+#define MSP_BASE_BAUD           25000000
+#else
+#define MSP_BASE_BAUD           6000000
+#endif
+#define MSP_UART_REG_LEN        0x20
+/*
+ ***************************************************************************
+ * ELB defines                                                             *
+ ***************************************************************************
+ */
+#define PCCARD_32               0x02    /* Set if is PCCARD 32 (Cardbus) */
+#define SINGLE_PCCARD           0x01    /* Set to enable single PC card */
+/*
+ ***************************************************************************
+ * CIC defines                                                             *
+ ***************************************************************************
+ */
+/* CIC_EXT_CFG_REG */
+#define EXT_INT_POL(eirq)                       (1 << (eirq + 8))
+#define EXT_INT_EDGE(eirq)                      (1 << eirq)
+#define CIC_EXT_SET_TRIGGER_LEVEL(reg, eirq)    (reg &= ~EXT_INT_EDGE(eirq))
+#define CIC_EXT_SET_TRIGGER_EDGE(reg, eirq)     (reg |= EXT_INT_EDGE(eirq))
+#define CIC_EXT_SET_ACTIVE_HI(reg, eirq)        (reg |= EXT_INT_POL(eirq))
+#define CIC_EXT_SET_ACTIVE_LO(reg, eirq)        (reg &= ~EXT_INT_POL(eirq))
+#define CIC_EXT_SET_ACTIVE_RISING               CIC_EXT_SET_ACTIVE_HI
+#define CIC_EXT_SET_ACTIVE_FALLING              CIC_EXT_SET_ACTIVE_LO
+#define CIC_EXT_IS_TRIGGER_LEVEL(reg, eirq) \
+                                ((reg & EXT_INT_EDGE(eirq)) == 0)
+#define CIC_EXT_IS_TRIGGER_EDGE(reg, eirq)      (reg & EXT_INT_EDGE(eirq))
+#define CIC_EXT_IS_ACTIVE_HI(reg, eirq)         (reg & EXT_INT_POL(eirq))
+#define CIC_EXT_IS_ACTIVE_LO(reg, eirq) \
+                                ((reg & EXT_INT_POL(eirq)) == 0)
+#define CIC_EXT_IS_ACTIVE_RISING                CIC_EXT_IS_ACTIVE_HI
+#define CIC_EXT_IS_ACTIVE_FALLING               CIC_EXT_IS_ACTIVE_LO
+/*
+ ***************************************************************************
+ * Memory Controller defines                                               *
+ ***************************************************************************
+ */
+/* Indirect memory controller registers */
+#define DDRC_CFG(n)             (n)
+#define DDRC_DEBUG(n)           (0x04 + n)
+#define DDRC_CTL(n)             (0x40 + n)
+/* Macro to perform DDRC indirect write */
+#define DDRC_INDIRECT_WRITE(reg, mask, value) \
+({ \
+        *MEM_SS_ADDR = (((mask) & 0xf) << 8) | ((reg) & 0xff); \
+        *MEM_SS_DATA = (value); \
+        *MEM_SS_WRITE = 1; \
+})
+/*
+ ***************************************************************************
+ * SPI/MPI Mode                                                            *
+ ***************************************************************************
+ */
+#define SPI_MPI_RX_BUSY         0x00008000      /* SPI/MPI Receive Busy */
+#define SPI_MPI_FIFO_EMPTY      0x00004000      /* SPI/MPI Fifo Empty   */
+#define SPI_MPI_TX_BUSY         0x00002000      /* SPI/MPI Transmit Busy */
+#define SPI_MPI_FIFO_FULL       0x00001000      /* SPI/MPU FIFO full    */
+/*
+ ***************************************************************************
+ * SPI/MPI Control Register                                                *
+ ***************************************************************************
+ */
+#define SPI_MPI_RX_START        0x00000004      /* Start receive command */
+#define SPI_MPI_FLUSH_Q         0x00000002      /* Flush SPI/MPI Queue */
+#define SPI_MPI_TX_START        0x00000001      /* Start Transmit Command */
+#endif /* !_ASM_MSP_REGS_H */
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_slp_int.h b/include/asm-mips/pmc-sierra/msp71xx/msp_slp_int.h
new file mode 100644
index 000000000000..96d4c8ce8c83
--- /dev/null
+++ b/include/asm-mips/pmc-sierra/msp71xx/msp_slp_int.h
@@ -0,0 +1,141 @@
+/*
+ * Defines for the MSP interrupt controller.
+ *
+ * Copyright (C) 1999 MIPS Technologies, Inc.  All rights reserved.
+ * Author: Carsten Langgaard, carstenl@mips.com
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ */
+#ifndef _MSP_SLP_INT_H
+#define _MSP_SLP_INT_H
+/*
+ * The PMC-Sierra SLP interrupts are arranged in a 3 level cascaded
+ * hierarchical system.  The first level are the direct MIPS interrupts
+ * and are assigned the interrupt range 0-7.  The second level is the SLM
+ * interrupt controller and is assigned the range 8-39.  The third level
+ * comprises the Peripherial block, the PCI block, the PCI MSI block and
+ * the SLP.  The PCI interrupts and the SLP errors are handled by the
+ * relevant subsystems so the core interrupt code needs only concern
+ * itself with the Peripheral block.  These are assigned interrupts in
+ * the range 40-71.
+ */
+/*
+ * IRQs directly connected to CPU
+ */
+#define MSP_MIPS_INTBASE        0
+#define MSP_INT_SW0             0  /* IRQ for swint0,         C_SW0  */
+#define MSP_INT_SW1             1  /* IRQ for swint1,         C_SW1  */
+#define MSP_INT_MAC0            2  /* IRQ for MAC 0,          C_IRQ0 */
+#define MSP_INT_MAC1            3  /* IRQ for MAC 1,          C_IRQ1 */
+#define MSP_INT_C_IRQ2          4  /* Wired off,              C_IRQ2 */
+#define MSP_INT_VE              5  /* IRQ for Voice Engine,   C_IRQ3 */
+#define MSP_INT_SLP             6  /* IRQ for SLM block,      C_IRQ4 */
+#define MSP_INT_TIMER           7  /* IRQ for the MIPS timer, C_IRQ5 */
+/*
+ * IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4)
+ * These defines should be tied to the register definition for the SLM
+ * interrupt routine.  For now, just use hard-coded values.
+ */
+#define MSP_SLP_INTBASE         (MSP_MIPS_INTBASE + 8)
+#define MSP_INT_EXT0            (MSP_SLP_INTBASE + 0)
+                                        /* External interrupt 0         */
+#define MSP_INT_EXT1            (MSP_SLP_INTBASE + 1)
+                                        /* External interrupt 1         */
+#define MSP_INT_EXT2            (MSP_SLP_INTBASE + 2)
+                                        /* External interrupt 2         */
+#define MSP_INT_EXT3            (MSP_SLP_INTBASE + 3)
+                                        /* External interrupt 3         */
+/* Reserved                                        4-7                  */
+/*
+ *************************************************************************
+ * DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER *
+ * Some MSP produces have this interrupt labelled as Voice and some are  *
+ * SEC mbox ...                                                          *
+ *************************************************************************
+ */
+#define MSP_INT_SLP_VE          (MSP_SLP_INTBASE + 8)
+                                        /* Cascaded IRQ for Voice Engine*/
+#define MSP_INT_SLP_TDM         (MSP_SLP_INTBASE + 9)
+                                        /* TDM interrupt                */
+#define MSP_INT_SLP_MAC0        (MSP_SLP_INTBASE + 10)
+                                        /* Cascaded IRQ for MAC 0       */
+#define MSP_INT_SLP_MAC1        (MSP_SLP_INTBASE + 11)
+                                        /* Cascaded IRQ for MAC 1       */
+#define MSP_INT_SEC             (MSP_SLP_INTBASE + 12)
+                                        /* IRQ for security engine      */
+#define MSP_INT_PER             (MSP_SLP_INTBASE + 13)
+                                        /* Peripheral interrupt         */
+#define MSP_INT_TIMER0          (MSP_SLP_INTBASE + 14)
+                                        /* SLP timer 0                  */
+#define MSP_INT_TIMER1          (MSP_SLP_INTBASE + 15)
+                                        /* SLP timer 1                  */
+#define MSP_INT_TIMER2          (MSP_SLP_INTBASE + 16)
+                                        /* SLP timer 2                  */
+#define MSP_INT_SLP_TIMER       (MSP_SLP_INTBASE + 17)
+                                        /* Cascaded MIPS timer          */
+#define MSP_INT_BLKCP           (MSP_SLP_INTBASE + 18)
+                                        /* Block Copy                   */
+#define MSP_INT_UART0           (MSP_SLP_INTBASE + 19)
+                                        /* UART 0                       */
+#define MSP_INT_PCI             (MSP_SLP_INTBASE + 20)
+                                        /* PCI subsystem                */
+#define MSP_INT_PCI_DBELL       (MSP_SLP_INTBASE + 21)
+                                        /* PCI doorbell                 */
+#define MSP_INT_PCI_MSI         (MSP_SLP_INTBASE + 22)
+                                        /* PCI Message Signal           */
+#define MSP_INT_PCI_BC0         (MSP_SLP_INTBASE + 23)
+                                        /* PCI Block Copy 0             */
+#define MSP_INT_PCI_BC1         (MSP_SLP_INTBASE + 24)
+                                        /* PCI Block Copy 1             */
+#define MSP_INT_SLP_ERR         (MSP_SLP_INTBASE + 25)
+                                        /* SLP error condition          */
+#define MSP_INT_MAC2            (MSP_SLP_INTBASE + 26)
+                                        /* IRQ for MAC2                 */
+/* Reserved                                        26-31                */
+/*
+ * IRQs cascaded on SLP PER interrupt (MSP_INT_PER)
+ */
+#define MSP_PER_INTBASE         (MSP_SLP_INTBASE + 32)
+/* Reserved                                        0-1                  */
+#define MSP_INT_UART1           (MSP_PER_INTBASE + 2)
+                                        /* UART 1                       */
+/* Reserved                                        3-5                  */
+#define MSP_INT_2WIRE           (MSP_PER_INTBASE + 6)
+                                        /* 2-wire                       */
+#define MSP_INT_TM0             (MSP_PER_INTBASE + 7)
+                                        /* Peripheral timer block out 0 */
+#define MSP_INT_TM1             (MSP_PER_INTBASE + 8)
+                                        /* Peripheral timer block out 1 */
+/* Reserved                                        9                    */
+#define MSP_INT_SPRX            (MSP_PER_INTBASE + 10)
+                                        /* SPI RX complete              */
+#define MSP_INT_SPTX            (MSP_PER_INTBASE + 11)
+                                        /* SPI TX complete              */
+#define MSP_INT_GPIO            (MSP_PER_INTBASE + 12)
+                                        /* GPIO                         */
+#define MSP_INT_PER_ERR         (MSP_PER_INTBASE + 13)
+                                        /* Peripheral error             */
+/* Reserved                                        14-31                */
+#endif /* !_MSP_SLP_INT_H */
diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h
index 5f80ba71ab92..1d8b9a8ae324 100644
--- a/include/asm-mips/processor.h
+++ b/include/asm-mips/processor.h
@@ -82,10 +82,6 @@ struct mips_fpu_struct {
        unsigned int    fcr31;
 };
-#define INIT_FPU { \
-        {0,} \
-}
 #define NUM_DSP_REGS   6
 typedef __u32 dspreg_t;
@@ -95,8 +91,6 @@ struct mips_dsp_state {
        unsigned int    dspcontrol;
 };
-#define INIT_DSP {{0,},}
 #define INIT_CPUMASK { \
        {0,} \
 }
@@ -155,41 +149,63 @@ struct thread_struct {
 #define MF_N64          0
 #ifdef CONFIG_MIPS_MT_FPAFF
-#define FPAFF_INIT 0, INIT_CPUMASK,
+#define FPAFF_INIT                                              \
+        .emulated_fp                    = 0,                    \
+        .user_cpus_allowed              = INIT_CPUMASK,
 #else
 #define FPAFF_INIT
 #endif /* CONFIG_MIPS_MT_FPAFF */
-#define INIT_THREAD  { \
+#define INIT_THREAD  {                                          \
-        /* \
+        /*                                                      \
-         * saved main processor registers \
+         * Saved main processor registers                       \
-         */ \
+         */                                                     \
-        0, 0, 0, 0, 0, 0, 0, 0, \
+        .reg16                  = 0,                            \
-                       0, 0, 0, \
+        .reg17                  = 0,                            \
-        /* \
+        .reg18                  = 0,                            \
-         * saved cp0 stuff \
+        .reg19                  = 0,                            \
-         */ \
+        .reg20                  = 0,                            \
-        0, \
+        .reg21                  = 0,                            \
-        /* \
+        .reg22                  = 0,                            \
-         * saved fpu/fpu emulator stuff \
+        .reg23                  = 0,                            \
-         */ \
+        .reg29                  = 0,                            \
-        INIT_FPU, \
+        .reg30                  = 0,                            \
-        /* \
+        .reg31                  = 0,                            \
-         * fpu affinity state (null if not FPAFF) \
+        /*                                                      \
-         */ \
+         * Saved cp0 stuff                                      \
-        FPAFF_INIT \
+         */                                                     \
-        /* \
+        .cp0_status             = 0,                            \
-         * saved dsp/dsp emulator stuff \
+        /*                                                      \
-         */ \
+         * Saved FPU/FPU emulator stuff                         \
-        INIT_DSP, \
+         */                                                     \
-        /* \
+        .fpu                    = {                             \
-         * Other stuff associated with the process \
+                .fpr            = {0,},                         \
-         */ \
+                .fcr31          = 0,                            \
-        0, 0, 0, 0, \
+        },                                                      \
-        /* \
+        /*                                                      \
-         * For now the default is to fix address errors \
+         * FPU affinity state (null if not FPAFF)               \
-         */ \
+         */                                                     \
-        MF_FIXADE, 0, 0 \
+        FPAFF_INIT                                              \
+        /*                                                      \
+         * Saved DSP stuff                                      \
+         */                                                     \
+        .dsp                    = {                             \
+                .dspr           = {0, },                        \
+                .dspcontrol     = 0,                            \
+        },                                                      \
+        /*                                                      \
+         * Other stuff associated with the process              \
+         */                                                     \
+        .cp0_badvaddr           = 0,                            \
+        .cp0_baduaddr           = 0,                            \
+        .error_code             = 0,                            \
+        .trap_no                = 0,                            \
+        /*                                                      \
+         * For now the default is to fix address errors         \
+         */                                                     \
+        .mflags                 = MF_FIXADE,                    \
+        .irix_trampoline        = 0,                            \
+        .irix_oldctx            = 0,                            \
 }
 struct task_struct;
@@ -237,7 +253,7 @@ unsigned long get_wchan(struct task_struct *p);
 #define ARCH_HAS_PREFETCH
-extern inline void prefetch(const void *addr)
+static inline void prefetch(const void *addr)
 {
        __asm__ __volatile__(
        "       .set    mips4           \n"
diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h
index ce51213d84f9..c07ebd8eb9e7 100644
--- a/include/asm-mips/serial.h
+++ b/include/asm-mips/serial.h
@@ -19,159 +19,4 @@
 */
 #define BASE_BAUD (1843200 / 16)
-/* Standard COM flags (except for COM4, because of the 8514 problem) */
-#ifdef CONFIG_SERIAL_DETECT_IRQ
-#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ)
-#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ)
-#else
-#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
-#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
-#endif
-#ifdef CONFIG_MACH_JAZZ
-#include <asm/jazz.h>
-#ifndef CONFIG_OLIVETTI_M700
-   /* Some Jazz machines seem to have an 8MHz crystal clock but I don't know
-      exactly which ones ... XXX */
-#define JAZZ_BASE_BAUD ( 8000000 / 16 ) /* ( 3072000 / 16) */
-#else
-/* but the M700 isn't such a strange beast */
-#define JAZZ_BASE_BAUD BASE_BAUD
-#endif
-#define _JAZZ_SERIAL_INIT(int, base)                                    \
-        { .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS,      \
-          .iomem_base = (u8 *) base, .iomem_reg_shift = 0,                      \
-          .io_type = SERIAL_IO_MEM }
-#define JAZZ_SERIAL_PORT_DEFNS                                          \
-        _JAZZ_SERIAL_INIT(JAZZ_SERIAL1_IRQ, JAZZ_SERIAL1_BASE),         \
-        _JAZZ_SERIAL_INIT(JAZZ_SERIAL2_IRQ, JAZZ_SERIAL2_BASE),
-#else
-#define JAZZ_SERIAL_PORT_DEFNS
-#endif
-/*
- * Galileo EV64120 evaluation board
- */
-#ifdef CONFIG_MIPS_EV64120
-#include <mach-gt64120.h>
-#define EV64120_SERIAL_PORT_DEFNS                                  \
-    { .baud_base = EV64120_BASE_BAUD, .irq = EV64120_UART_IRQ, \
-      .flags = STD_COM_FLAGS,  \
-      .iomem_base = EV64120_UART0_REGS_BASE, .iomem_reg_shift = 2, \
-      .io_type = SERIAL_IO_MEM }, \
-    { .baud_base = EV64120_BASE_BAUD, .irq = EV64120_UART_IRQ, \
-      .flags = STD_COM_FLAGS, \
-      .iomem_base = EV64120_UART1_REGS_BASE, .iomem_reg_shift = 2, \
-      .io_type = SERIAL_IO_MEM },
-#else
-#define EV64120_SERIAL_PORT_DEFNS
-#endif
-#ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
-#define STD_SERIAL_PORT_DEFNS                   \
-        /* UART CLK   PORT IRQ     FLAGS        */                      \
-        { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS },      /* ttyS0 */     \
-        { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS },      /* ttyS1 */     \
-        { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS },      /* ttyS2 */     \
-        { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS },     /* ttyS3 */
-#else /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
-#define STD_SERIAL_PORT_DEFNS
-#endif /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
-#ifdef CONFIG_MOMENCO_OCELOT_3
-#define OCELOT_3_BASE_BAUD      ( 20000000 / 16 )
-#define OCELOT_3_SERIAL_IRQ     6
-#define OCELOT_3_SERIAL_BASE    (signed)0xfd000020
-#define _OCELOT_3_SERIAL_INIT(int, base)                                \
-        { .baud_base = OCELOT_3_BASE_BAUD, irq: int,                    \
-          .flags = STD_COM_FLAGS,                                               \
-          .iomem_base = (u8 *) base, iomem_reg_shift: 2,                        \
-          io_type: SERIAL_IO_MEM }
-#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS                              \
-        _OCELOT_3_SERIAL_INIT(OCELOT_3_SERIAL_IRQ, OCELOT_3_SERIAL_BASE)
-#else
-#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS
-#endif
-#ifdef CONFIG_MOMENCO_OCELOT
-/* Ordinary NS16552 duart with a 20MHz crystal.  */
-#define OCELOT_BASE_BAUD ( 20000000 / 16 )
-#define OCELOT_SERIAL1_IRQ      4
-#define OCELOT_SERIAL1_BASE     0xe0001020
-#define _OCELOT_SERIAL_INIT(int, base)                                  \
-        { .baud_base = OCELOT_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS,    \
-          .iomem_base = (u8 *) base, .iomem_reg_shift = 2,                      \
-          .io_type = SERIAL_IO_MEM }
-#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS                                \
-        _OCELOT_SERIAL_INIT(OCELOT_SERIAL1_IRQ, OCELOT_SERIAL1_BASE)
-#else
-#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS
-#endif
-#ifdef CONFIG_MOMENCO_OCELOT_C
-/* Ordinary NS16552 duart with a 20MHz crystal.  */
-#define OCELOT_C_BASE_BAUD ( 20000000 / 16 )
-#define OCELOT_C_SERIAL1_IRQ    80
-#define OCELOT_C_SERIAL1_BASE   0xfd000020
-#define OCELOT_C_SERIAL2_IRQ    81
-#define OCELOT_C_SERIAL2_BASE   0xfd000000
-#define _OCELOT_C_SERIAL_INIT(int, base)                                \
-        { .baud_base            = OCELOT_C_BASE_BAUD,                   \
-          .irq                  = (int),                                \
-          .flags                = STD_COM_FLAGS,                        \
-          .iomem_base           = (u8 *) base,                          \
-          .iomem_reg_shift      = 2,                                    \
-          .io_type              = SERIAL_IO_MEM                         \
-         }
-#define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS                              \
-        _OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL1_IRQ, OCELOT_C_SERIAL1_BASE), \
-        _OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL2_IRQ, OCELOT_C_SERIAL2_BASE)
-#else
-#define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS
-#endif
-#ifdef CONFIG_DDB5477
-#include <asm/ddb5xxx/ddb5477.h>
-#define DDB5477_SERIAL_PORT_DEFNS                                       \
-        { .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART0,             \
-          .flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04200,        \
-          .iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM},              \
-        { .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART1,             \
-          .flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04240,        \
-          .iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM},
-#else
-#define DDB5477_SERIAL_PORT_DEFNS
-#endif
-#ifdef CONFIG_SGI_IP32
-/*
- * The IP32 (SGI O2) has standard serial ports (UART 16550A) mapped in memory
- * They are initialized in ip32_setup
- */
-#define IP32_SERIAL_PORT_DEFNS                          \
-        {},{},
-#else
-#define IP32_SERIAL_PORT_DEFNS
-#endif /* CONFIG_SGI_IP32 */
-#define SERIAL_PORT_DFNS                                \
-        DDB5477_SERIAL_PORT_DEFNS                       \
-        EV64120_SERIAL_PORT_DEFNS                       \
-        IP32_SERIAL_PORT_DEFNS                          \
-        JAZZ_SERIAL_PORT_DEFNS                          \
-        STD_SERIAL_PORT_DEFNS                           \
-        MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS              \
-        MOMENCO_OCELOT_SERIAL_PORT_DEFNS                \
-        MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS
 #endif /* _ASM_SERIAL_H */
diff --git a/include/asm-mips/smp.h b/include/asm-mips/smp.h
index 1608fd71d6f7..13aef6af422c 100644
--- a/include/asm-mips/smp.h
+++ b/include/asm-mips/smp.h
@@ -49,13 +49,6 @@ extern struct call_data_struct *call_data;
 extern cpumask_t phys_cpu_present_map;
 #define cpu_possible_map        phys_cpu_present_map
-extern cpumask_t cpu_callout_map;
-/* We don't mark CPUs online until __cpu_up(), so we need another measure */
-static inline int num_booting_cpus(void)
-{
-        return cpus_weight(cpu_callout_map);
-}
 /*
 * These are defined by the board-specific code.
 */
diff --git a/include/asm-mips/sni.h b/include/asm-mips/sni.h
index f257509b914f..ddaf36a1e389 100644
--- a/include/asm-mips/sni.h
+++ b/include/asm-mips/sni.h
@@ -146,9 +146,6 @@ extern unsigned int sni_brd_type;
 #define SNI_A20R_IRQ_BASE       MIPS_CPU_IRQ_BASE
 #define SNI_A20R_IRQ_TIMER      (SNI_A20R_IRQ_BASE+5)
-#define SNI_DS1216_A20R_BASE    0xbc081ffc
-#define SNI_DS1216_RM200_BASE   0xbcd41ffc
 #define SNI_PCIT_INT_REG        0xbfff000c
 #define SNI_PCIT_INT_START      24
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h
index bb0b289dbc9e..46bdb3f566f9 100644
--- a/include/asm-mips/system.h
+++ b/include/asm-mips/system.h
@@ -44,7 +44,7 @@ struct task_struct;
 * different thread.
 */
-#define switch_to(prev,next,last)                                       \
+#define __mips_mt_fpaff_switch_to(prev)                                 \
 do {                                                                    \
        if (cpu_has_fpu &&                                              \
            (prev->thread.mflags & MF_FPUBOUND) &&                      \
@@ -52,24 +52,24 @@ do {									\
                prev->thread.mflags &= ~MF_FPUBOUND;                    \
                prev->cpus_allowed = prev->thread.user_cpus_allowed;    \
        }                                                               \
-        if (cpu_has_dsp)                                                \
-                __save_dsp(prev);                                       \
        next->thread.emulated_fp = 0;                                   \
-        (last) = resume(prev, next, task_thread_info(next));            \
-        if (cpu_has_dsp)                                                \
-                __restore_dsp(current);                                 \
 } while(0)
 #else
+#define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0)
+#endif
 #define switch_to(prev,next,last)                                       \
 do {                                                                    \
+        __mips_mt_fpaff_switch_to(prev);                                \
        if (cpu_has_dsp)                                                \
                __save_dsp(prev);                                       \
        (last) = resume(prev, next, task_thread_info(next));            \
        if (cpu_has_dsp)                                                \
                __restore_dsp(current);                                 \
+        if (cpu_has_userlocal)                                          \
+                write_c0_userlocal(task_thread_info(current)->tp_value);\
 } while(0)
-#endif
 /*
 * On SMP systems, when the scheduler does migration-cost autodetection,
diff --git a/include/asm-mips/tx4938/rbtx4938.h b/include/asm-mips/tx4938/rbtx4938.h
index 0fbedafdcea8..74e7d8061e58 100644
--- a/include/asm-mips/tx4938/rbtx4938.h
+++ b/include/asm-mips/tx4938/rbtx4938.h
@@ -105,12 +105,6 @@
 #define rbtx4938_pcireset_ptr   \
        ((volatile unsigned char *)RBTX4938_PCIRESET_ADDR)
-/* SPI */
-#define RBTX4938_SEEPROM1_CHIPID        0
-#define RBTX4938_SEEPROM2_CHIPID        1
-#define RBTX4938_SEEPROM3_CHIPID        2
-#define RBTX4938_SRTC_CHIPID    3
 /*
 * IRQ mappings
 */
diff --git a/include/asm-mips/tx4938/spi.h b/include/asm-mips/tx4938/spi.h
index 0dbbab820a5a..6a60c83e152b 100644
--- a/include/asm-mips/tx4938/spi.h
+++ b/include/asm-mips/tx4938/spi.h
@@ -14,61 +14,7 @@
 #ifndef __ASM_TX_BOARDS_TX4938_SPI_H
 #define __ASM_TX_BOARDS_TX4938_SPI_H
-/* SPI */
+extern int spi_eeprom_register(int chipid);
-struct spi_dev_desc {
-        unsigned int baud;
-        unsigned short tcss, tcsh, tcsr; /* CS setup/hold/recovery time */
-        unsigned int byteorder:1;       /* 0:LSB-First, 1:MSB-First */
-        unsigned int polarity:1;        /* 0:High-Active */
-        unsigned int phase:1;           /* 0:Sample-Then-Shift */
-};
-extern void txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on)) __init;
-extern void txx9_spi_irqinit(int irc_irq) __init;
-extern int txx9_spi_io(int chipid, struct spi_dev_desc *desc,
-                       unsigned char **inbufs, unsigned int *incounts,
-                       unsigned char **outbufs, unsigned int *outcounts,
-                       int cansleep);
-extern int spi_eeprom_write_enable(int chipid, int enable);
-extern int spi_eeprom_read_status(int chipid);
 extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len);
-extern int spi_eeprom_write(int chipid, int address, unsigned char *buf, int len);
-extern void spi_eeprom_proc_create(struct proc_dir_entry *dir, int chipid) __init;
-#define TXX9_IMCLK     (txx9_gbus_clock / 2)
-/*
-* SPI
-*/
-/* SPMCR : SPI Master Control */
-#define TXx9_SPMCR_OPMODE       0xc0
-#define TXx9_SPMCR_CONFIG       0x40
-#define TXx9_SPMCR_ACTIVE       0x80
-#define TXx9_SPMCR_SPSTP        0x02
-#define TXx9_SPMCR_BCLR 0x01
-/* SPCR0 : SPI Status */
-#define TXx9_SPCR0_TXIFL_MASK   0xc000
-#define TXx9_SPCR0_RXIFL_MASK   0x3000
-#define TXx9_SPCR0_SIDIE        0x0800
-#define TXx9_SPCR0_SOEIE        0x0400
-#define TXx9_SPCR0_RBSIE        0x0200
-#define TXx9_SPCR0_TBSIE        0x0100
-#define TXx9_SPCR0_IFSPSE       0x0010
-#define TXx9_SPCR0_SBOS 0x0004
-#define TXx9_SPCR0_SPHA 0x0002
-#define TXx9_SPCR0_SPOL 0x0001
-/* SPSR : SPI Status */
-#define TXx9_SPSR_TBSI  0x8000
-#define TXx9_SPSR_RBSI  0x4000
-#define TXx9_SPSR_TBS_MASK      0x3800
-#define TXx9_SPSR_RBS_MASK      0x0700
-#define TXx9_SPSR_SPOE  0x0080
-#define TXx9_SPSR_IFSD  0x0008
-#define TXx9_SPSR_SIDLE 0x0004
-#define TXx9_SPSR_STRDY 0x0002
-#define TXx9_SPSR_SRRDY 0x0001
 #endif /* __ASM_TX_BOARDS_TX4938_SPI_H */
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h
index ec0eeebd8802..9de52a5b0f3d 100644
--- a/include/asm-mips/war.h
+++ b/include/asm-mips/war.h
@@ -169,10 +169,9 @@
 /*
 * On the RM9000 there is a problem which makes the CreateDirtyExclusive
- * cache operation unusable on SMP systems.
+ * eache operation unusable on SMP systems.
 */
-#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_PMC_YOSEMITE) || \
+#if defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_BASLER_EXCITE)
-    defined(CONFIG_BASLER_EXCITE)
 #define  RM9000_CDEX_SMP_WAR            1
 #endif
@@ -182,11 +181,10 @@
 * I-cache line worth of instructions being fetched may case spurious
 * exceptions.
 */
-#if defined(CONFIG_BASLER_EXCITE) || defined(CONFIG_MOMENCO_JAGUAR_ATX) || \
+#if defined(CONFIG_BASLER_EXCITE) || defined(CONFIG_MIPS_ATLAS) || \
-    defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA) || \
+    defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MOMENCO_OCELOT) || \
-    defined(CONFIG_MOMENCO_OCELOT) || defined(CONFIG_MOMENCO_OCELOT_3) || \
+    defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_SGI_IP32) || \
-    defined(CONFIG_MOMENCO_OCELOT_C) || defined(CONFIG_PMC_YOSEMITE) || \
+    defined(CONFIG_WR_PPMC)
-    defined(CONFIG_SGI_IP32) || defined(CONFIG_WR_PPMC)
 #define ICACHE_REFILLS_WORKAROUND_WAR   1
 #endif
@@ -200,6 +198,14 @@
 #endif
 /*
+ * 34K core erratum: "Problems Executing the TLBR Instruction"
+ */
+#if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \
+        defined(CONFIG_PMC_MSP7120_FPGA)
+#define MIPS34K_MISSED_ITLB_WAR         1
+#endif
+/*
 * Workarounds default to off
 */
 #ifndef ICACHE_REFILLS_WORKAROUND_WAR
@@ -238,5 +244,8 @@
 #ifndef R10000_LLSC_WAR
 #define R10000_LLSC_WAR                 0
 #endif
+#ifndef MIPS34K_MISSED_ITLB_WAR
+#define MIPS34K_MISSED_ITLB_WAR         0
+#endif
 #endif /* _ASM_WAR_H */
diff --git a/include/asm-mips/watch.h b/include/asm-mips/watch.h
deleted file mode 100644
index 6aa90cae1114..000000000000
--- a/include/asm-mips/watch.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1996, 1997, 1998, 2000, 2001 by Ralf Baechle
- */
-#ifndef _ASM_WATCH_H
-#define _ASM_WATCH_H
-#include <linux/linkage.h>
-/*
- * Types of reference for watch_set()
- */
-enum wref_type {
-        wr_save = 1,
-        wr_load = 2
-};
-extern asmlinkage void __watch_set(unsigned long addr, enum wref_type ref);
-extern asmlinkage void __watch_clear(void);
-extern asmlinkage void __watch_reenable(void);
-#define watch_set(addr, ref)                                    \
-        if (cpu_has_watch)                                      \
-                __watch_set(addr, ref)
-#define watch_clear()                                           \
-        if (cpu_has_watch)                                      \
-                __watch_clear()
-#define watch_reenable()                                        \
-        if (cpu_has_watch)                                      \
-                __watch_reenable()
-#endif /* _ASM_WATCH_H */