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-rw-r--r--drivers/net/wireless/rt2x00/rt2800.h40
-rw-r--r--drivers/net/wireless/rt2x00/rt2800lib.c693
-rw-r--r--drivers/net/wireless/rt2x00/rt2800pci.c14
3 files changed, 378 insertions, 369 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2800.h b/drivers/net/wireless/rt2x00/rt2800.h
index 6f4a2432c021..70b9abbdeb9e 100644
--- a/drivers/net/wireless/rt2x00/rt2800.h
+++ b/drivers/net/wireless/rt2x00/rt2800.h
@@ -66,7 +66,7 @@
66#define RF3320 0x000b 66#define RF3320 0x000b
67#define RF3322 0x000c 67#define RF3322 0x000c
68#define RF3853 0x000d 68#define RF3853 0x000d
69#define RF5390 0x5390 69#define RF5390 0x5390
70 70
71/* 71/*
72 * Chipset revisions. 72 * Chipset revisions.
@@ -79,7 +79,7 @@
79#define REV_RT3071E 0x0211 79#define REV_RT3071E 0x0211
80#define REV_RT3090E 0x0211 80#define REV_RT3090E 0x0211
81#define REV_RT3390E 0x0211 81#define REV_RT3390E 0x0211
82#define REV_RT5390F 0x0502 82#define REV_RT5390F 0x0502
83 83
84/* 84/*
85 * Signal information. 85 * Signal information.
@@ -126,9 +126,9 @@
126/* 126/*
127 * AUX_CTRL: Aux/PCI-E related configuration 127 * AUX_CTRL: Aux/PCI-E related configuration
128 */ 128 */
129#define AUX_CTRL 0x10c 129#define AUX_CTRL 0x10c
130#define AUX_CTRL_WAKE_PCIE_EN FIELD32(0x00000002) 130#define AUX_CTRL_WAKE_PCIE_EN FIELD32(0x00000002)
131#define AUX_CTRL_FORCE_PCIE_CLK FIELD32(0x00000400) 131#define AUX_CTRL_FORCE_PCIE_CLK FIELD32(0x00000400)
132 132
133/* 133/*
134 * OPT_14: Unknown register used by rt3xxx devices. 134 * OPT_14: Unknown register used by rt3xxx devices.
@@ -464,7 +464,7 @@
464 */ 464 */
465#define RF_CSR_CFG 0x0500 465#define RF_CSR_CFG 0x0500
466#define RF_CSR_CFG_DATA FIELD32(0x000000ff) 466#define RF_CSR_CFG_DATA FIELD32(0x000000ff)
467#define RF_CSR_CFG_REGNUM FIELD32(0x00003f00) 467#define RF_CSR_CFG_REGNUM FIELD32(0x00003f00)
468#define RF_CSR_CFG_WRITE FIELD32(0x00010000) 468#define RF_CSR_CFG_WRITE FIELD32(0x00010000)
469#define RF_CSR_CFG_BUSY FIELD32(0x00020000) 469#define RF_CSR_CFG_BUSY FIELD32(0x00020000)
470 470
@@ -1746,13 +1746,13 @@ struct mac_iveiv_entry {
1746 */ 1746 */
1747#define BBP4_TX_BF FIELD8(0x01) 1747#define BBP4_TX_BF FIELD8(0x01)
1748#define BBP4_BANDWIDTH FIELD8(0x18) 1748#define BBP4_BANDWIDTH FIELD8(0x18)
1749#define BBP4_MAC_IF_CTRL FIELD8(0x40) 1749#define BBP4_MAC_IF_CTRL FIELD8(0x40)
1750 1750
1751/* 1751/*
1752 * BBP 109 1752 * BBP 109
1753 */ 1753 */
1754#define BBP109_TX0_POWER FIELD8(0x0f) 1754#define BBP109_TX0_POWER FIELD8(0x0f)
1755#define BBP109_TX1_POWER FIELD8(0xf0) 1755#define BBP109_TX1_POWER FIELD8(0xf0)
1756 1756
1757/* 1757/*
1758 * BBP 138: Unknown 1758 * BBP 138: Unknown
@@ -1765,7 +1765,7 @@ struct mac_iveiv_entry {
1765/* 1765/*
1766 * BBP 152: Rx Ant 1766 * BBP 152: Rx Ant
1767 */ 1767 */
1768#define BBP152_RX_DEFAULT_ANT FIELD8(0x80) 1768#define BBP152_RX_DEFAULT_ANT FIELD8(0x80)
1769 1769
1770/* 1770/*
1771 * RFCSR registers 1771 * RFCSR registers
@@ -1776,7 +1776,7 @@ struct mac_iveiv_entry {
1776 * RFCSR 1: 1776 * RFCSR 1:
1777 */ 1777 */
1778#define RFCSR1_RF_BLOCK_EN FIELD8(0x01) 1778#define RFCSR1_RF_BLOCK_EN FIELD8(0x01)
1779#define RFCSR1_PLL_PD FIELD8(0x02) 1779#define RFCSR1_PLL_PD FIELD8(0x02)
1780#define RFCSR1_RX0_PD FIELD8(0x04) 1780#define RFCSR1_RX0_PD FIELD8(0x04)
1781#define RFCSR1_TX0_PD FIELD8(0x08) 1781#define RFCSR1_TX0_PD FIELD8(0x08)
1782#define RFCSR1_RX1_PD FIELD8(0x10) 1782#define RFCSR1_RX1_PD FIELD8(0x10)
@@ -1785,7 +1785,7 @@ struct mac_iveiv_entry {
1785/* 1785/*
1786 * RFCSR 2: 1786 * RFCSR 2:
1787 */ 1787 */
1788#define RFCSR2_RESCAL_EN FIELD8(0x80) 1788#define RFCSR2_RESCAL_EN FIELD8(0x80)
1789 1789
1790/* 1790/*
1791 * RFCSR 6: 1791 * RFCSR 6:
@@ -1801,7 +1801,7 @@ struct mac_iveiv_entry {
1801/* 1801/*
1802 * RFCSR 11: 1802 * RFCSR 11:
1803 */ 1803 */
1804#define RFCSR11_R FIELD8(0x03) 1804#define RFCSR11_R FIELD8(0x03)
1805 1805
1806/* 1806/*
1807 * RFCSR 12: 1807 * RFCSR 12:
@@ -1857,9 +1857,9 @@ struct mac_iveiv_entry {
1857/* 1857/*
1858 * RFCSR 30: 1858 * RFCSR 30:
1859 */ 1859 */
1860#define RFCSR30_TX_H20M FIELD8(0x02) 1860#define RFCSR30_TX_H20M FIELD8(0x02)
1861#define RFCSR30_RX_H20M FIELD8(0x04) 1861#define RFCSR30_RX_H20M FIELD8(0x04)
1862#define RFCSR30_RX_VCM FIELD8(0x18) 1862#define RFCSR30_RX_VCM FIELD8(0x18)
1863#define RFCSR30_RF_CALIBRATION FIELD8(0x80) 1863#define RFCSR30_RF_CALIBRATION FIELD8(0x80)
1864 1864
1865/* 1865/*
@@ -1871,17 +1871,17 @@ struct mac_iveiv_entry {
1871/* 1871/*
1872 * RFCSR 38: 1872 * RFCSR 38:
1873 */ 1873 */
1874#define RFCSR38_RX_LO1_EN FIELD8(0x20) 1874#define RFCSR38_RX_LO1_EN FIELD8(0x20)
1875 1875
1876/* 1876/*
1877 * RFCSR 39: 1877 * RFCSR 39:
1878 */ 1878 */
1879#define RFCSR39_RX_LO2_EN FIELD8(0x80) 1879#define RFCSR39_RX_LO2_EN FIELD8(0x80)
1880 1880
1881/* 1881/*
1882 * RFCSR 49: 1882 * RFCSR 49:
1883 */ 1883 */
1884#define RFCSR49_TX FIELD8(0x3f) 1884#define RFCSR49_TX FIELD8(0x3f)
1885 1885
1886/* 1886/*
1887 * RF registers 1887 * RF registers
@@ -1918,7 +1918,7 @@ struct mac_iveiv_entry {
1918/* 1918/*
1919 * Chip ID 1919 * Chip ID
1920 */ 1920 */
1921#define EEPROM_CHIP_ID 0x0000 1921#define EEPROM_CHIP_ID 0x0000
1922 1922
1923/* 1923/*
1924 * EEPROM Version 1924 * EEPROM Version
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.c b/drivers/net/wireless/rt2x00/rt2800lib.c
index 3da78bf0ca26..dbee3f12d636 100644
--- a/drivers/net/wireless/rt2x00/rt2800lib.c
+++ b/drivers/net/wireless/rt2x00/rt2800lib.c
@@ -400,15 +400,15 @@ int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
400 if (rt2800_wait_csr_ready(rt2x00dev)) 400 if (rt2800_wait_csr_ready(rt2x00dev))
401 return -EBUSY; 401 return -EBUSY;
402 402
403 if (rt2x00_is_pci(rt2x00dev)) { 403 if (rt2x00_is_pci(rt2x00dev)) {
404 if (rt2x00_rt(rt2x00dev, RT5390)) { 404 if (rt2x00_rt(rt2x00dev, RT5390)) {
405 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg); 405 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
406 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1); 406 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
407 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1); 407 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
408 rt2800_register_write(rt2x00dev, AUX_CTRL, reg); 408 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
409 } 409 }
410 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002); 410 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
411 } 411 }
412 412
413 /* 413 /*
414 * Disable DMA, will be reenabled later when enabling 414 * Disable DMA, will be reenabled later when enabling
@@ -1585,92 +1585,98 @@ static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1585#define RT5390_FREQ_OFFSET_BOUND 0x5f 1585#define RT5390_FREQ_OFFSET_BOUND 0x5f
1586 1586
1587static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev, 1587static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
1588 struct ieee80211_conf *conf, 1588 struct ieee80211_conf *conf,
1589 struct rf_channel *rf, 1589 struct rf_channel *rf,
1590 struct channel_info *info) 1590 struct channel_info *info)
1591{ 1591{
1592 u8 rfcsr; 1592 u8 rfcsr;
1593 u16 eeprom; 1593 u16 eeprom;
1594 1594
1595 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 1595 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
1596 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 1596 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
1597 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr); 1597 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
1598 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2); 1598 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
1599 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 1599 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
1600 1600
1601 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr); 1601 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
1602 if (info->default_power1 > RT5390_POWER_BOUND) 1602 if (info->default_power1 > RT5390_POWER_BOUND)
1603 rt2x00_set_field8(&rfcsr, RFCSR49_TX, RT5390_POWER_BOUND); 1603 rt2x00_set_field8(&rfcsr, RFCSR49_TX, RT5390_POWER_BOUND);
1604 else 1604 else
1605 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 1605 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
1606 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 1606 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
1607 1607
1608 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); 1608 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1609 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 1609 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1610 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 1610 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
1611 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 1611 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1612 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 1612 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1613 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 1613 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1614 1614
1615 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr); 1615 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1616 if (rt2x00dev->freq_offset > RT5390_FREQ_OFFSET_BOUND) 1616 if (rt2x00dev->freq_offset > RT5390_FREQ_OFFSET_BOUND)
1617 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, RT5390_FREQ_OFFSET_BOUND); 1617 rt2x00_set_field8(&rfcsr, RFCSR17_CODE,
1618 else 1618 RT5390_FREQ_OFFSET_BOUND);
1619 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset); 1619 else
1620 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 1620 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
1621 1621 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1622 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom); 1622
1623 if (rf->channel <= 14) { 1623 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
1624 int idx = rf->channel-1; 1624 if (rf->channel <= 14) {
1625 1625 int idx = rf->channel-1;
1626 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) { 1626
1627 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 1627 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) {
1628 /* r55/r59 value array of channel 1~14 */ 1628 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1629 static const char r55_bt_rev[] = {0x83, 0x83, 1629 /* r55/r59 value array of channel 1~14 */
1630 0x83, 0x73, 0x73, 0x63, 0x53, 0x53, 1630 static const char r55_bt_rev[] = {0x83, 0x83,
1631 0x53, 0x43, 0x43, 0x43, 0x43, 0x43}; 1631 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
1632 static const char r59_bt_rev[] = {0x0e, 0x0e, 1632 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
1633 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09, 1633 static const char r59_bt_rev[] = {0x0e, 0x0e,
1634 0x07, 0x07, 0x07, 0x07, 0x07, 0x07}; 1634 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
1635 1635 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
1636 rt2800_rfcsr_write(rt2x00dev, 55, r55_bt_rev[idx]); 1636
1637 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt_rev[idx]); 1637 rt2800_rfcsr_write(rt2x00dev, 55,
1638 } else { 1638 r55_bt_rev[idx]);
1639 static const char r59_bt[] = {0x8b, 0x8b, 0x8b, 1639 rt2800_rfcsr_write(rt2x00dev, 59,
1640 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89, 1640 r59_bt_rev[idx]);
1641 0x88, 0x88, 0x86, 0x85, 0x84}; 1641 } else {
1642 1642 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
1643 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]); 1643 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
1644 } 1644 0x88, 0x88, 0x86, 0x85, 0x84};
1645 } else { 1645
1646 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 1646 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
1647 static const char r55_nonbt_rev[] = {0x23, 0x23, 1647 }
1648 0x23, 0x23, 0x13, 0x13, 0x03, 0x03, 1648 } else {
1649 0x03, 0x03, 0x03, 0x03, 0x03, 0x03}; 1649 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1650 static const char r59_nonbt_rev[] = {0x07, 0x07, 1650 static const char r55_nonbt_rev[] = {0x23, 0x23,
1651 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 1651 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
1652 0x07, 0x07, 0x06, 0x05, 0x04, 0x04}; 1652 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
1653 1653 static const char r59_nonbt_rev[] = {0x07, 0x07,
1654 rt2800_rfcsr_write(rt2x00dev, 55, r55_nonbt_rev[idx]); 1654 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
1655 rt2800_rfcsr_write(rt2x00dev, 59, r59_nonbt_rev[idx]); 1655 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
1656 } else if (rt2x00_rt(rt2x00dev, RT5390)) { 1656
1657 static const char r59_non_bt[] = {0x8f, 0x8f, 1657 rt2800_rfcsr_write(rt2x00dev, 55,
1658 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d, 1658 r55_nonbt_rev[idx]);
1659 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86}; 1659 rt2800_rfcsr_write(rt2x00dev, 59,
1660 1660 r59_nonbt_rev[idx]);
1661 rt2800_rfcsr_write(rt2x00dev, 59, r59_non_bt[idx]); 1661 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
1662 } 1662 static const char r59_non_bt[] = {0x8f, 0x8f,
1663 } 1663 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
1664 } 1664 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
1665 1665
1666 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); 1666 rt2800_rfcsr_write(rt2x00dev, 59,
1667 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0); 1667 r59_non_bt[idx]);
1668 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0); 1668 }
1669 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 1669 }
1670 1670 }
1671 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr); 1671
1672 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1); 1672 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1673 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 1673 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
1674 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
1675 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1676
1677 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1678 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1679 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1674} 1680}
1675 1681
1676static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, 1682static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
@@ -1697,8 +1703,8 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1697 rt2x00_rf(rt2x00dev, RF3052) || 1703 rt2x00_rf(rt2x00dev, RF3052) ||
1698 rt2x00_rf(rt2x00dev, RF3320)) 1704 rt2x00_rf(rt2x00dev, RF3320))
1699 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info); 1705 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
1700 else if (rt2x00_rf(rt2x00dev, RF5390)) 1706 else if (rt2x00_rf(rt2x00dev, RF5390))
1701 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info); 1707 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
1702 else 1708 else
1703 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info); 1709 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
1704 1710
@@ -1711,14 +1717,15 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1711 rt2800_bbp_write(rt2x00dev, 86, 0); 1717 rt2800_bbp_write(rt2x00dev, 86, 0);
1712 1718
1713 if (rf->channel <= 14) { 1719 if (rf->channel <= 14) {
1714 if (!rt2x00_rt(rt2x00dev, RT5390)) { 1720 if (!rt2x00_rt(rt2x00dev, RT5390)) {
1715 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) { 1721 if (test_bit(CONFIG_EXTERNAL_LNA_BG,
1716 rt2800_bbp_write(rt2x00dev, 82, 0x62); 1722 &rt2x00dev->flags)) {
1717 rt2800_bbp_write(rt2x00dev, 75, 0x46); 1723 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1718 } else { 1724 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1719 rt2800_bbp_write(rt2x00dev, 82, 0x84); 1725 } else {
1720 rt2800_bbp_write(rt2x00dev, 75, 0x50); 1726 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1721 } 1727 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1728 }
1722 } 1729 }
1723 } else { 1730 } else {
1724 rt2800_bbp_write(rt2x00dev, 82, 0xf2); 1731 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
@@ -2097,8 +2104,8 @@ static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
2097 if (rt2x00_rt(rt2x00dev, RT3070) || 2104 if (rt2x00_rt(rt2x00dev, RT3070) ||
2098 rt2x00_rt(rt2x00dev, RT3071) || 2105 rt2x00_rt(rt2x00dev, RT3071) ||
2099 rt2x00_rt(rt2x00dev, RT3090) || 2106 rt2x00_rt(rt2x00dev, RT3090) ||
2100 rt2x00_rt(rt2x00dev, RT3390) || 2107 rt2x00_rt(rt2x00dev, RT3390) ||
2101 rt2x00_rt(rt2x00dev, RT5390)) 2108 rt2x00_rt(rt2x00dev, RT5390))
2102 return 0x1c + (2 * rt2x00dev->lna_gain); 2109 return 0x1c + (2 * rt2x00dev->lna_gain);
2103 else 2110 else
2104 return 0x2e + rt2x00dev->lna_gain; 2111 return 0x2e + rt2x00dev->lna_gain;
@@ -2230,10 +2237,10 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
2230 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 2237 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2231 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 2238 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2232 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f); 2239 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
2233 } else if (rt2x00_rt(rt2x00dev, RT5390)) { 2240 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2234 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 2241 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
2235 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 2242 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2236 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 2243 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2237 } else { 2244 } else {
2238 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000); 2245 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
2239 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 2246 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
@@ -2609,31 +2616,31 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
2609 rt2800_wait_bbp_ready(rt2x00dev))) 2616 rt2800_wait_bbp_ready(rt2x00dev)))
2610 return -EACCES; 2617 return -EACCES;
2611 2618
2612 if (rt2x00_rt(rt2x00dev, RT5390)) { 2619 if (rt2x00_rt(rt2x00dev, RT5390)) {
2613 rt2800_bbp_read(rt2x00dev, 4, &value); 2620 rt2800_bbp_read(rt2x00dev, 4, &value);
2614 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1); 2621 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
2615 rt2800_bbp_write(rt2x00dev, 4, value); 2622 rt2800_bbp_write(rt2x00dev, 4, value);
2616 } 2623 }
2617 2624
2618 if (rt2800_is_305x_soc(rt2x00dev) || 2625 if (rt2800_is_305x_soc(rt2x00dev) ||
2619 rt2x00_rt(rt2x00dev, RT5390)) 2626 rt2x00_rt(rt2x00dev, RT5390))
2620 rt2800_bbp_write(rt2x00dev, 31, 0x08); 2627 rt2800_bbp_write(rt2x00dev, 31, 0x08);
2621 2628
2622 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 2629 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
2623 rt2800_bbp_write(rt2x00dev, 66, 0x38); 2630 rt2800_bbp_write(rt2x00dev, 66, 0x38);
2624 2631
2625 if (rt2x00_rt(rt2x00dev, RT5390)) 2632 if (rt2x00_rt(rt2x00dev, RT5390))
2626 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 2633 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2627 2634
2628 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { 2635 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2629 rt2800_bbp_write(rt2x00dev, 69, 0x16); 2636 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2630 rt2800_bbp_write(rt2x00dev, 73, 0x12); 2637 rt2800_bbp_write(rt2x00dev, 73, 0x12);
2631 } else if (rt2x00_rt(rt2x00dev, RT5390)) { 2638 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2632 rt2800_bbp_write(rt2x00dev, 69, 0x12); 2639 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2633 rt2800_bbp_write(rt2x00dev, 73, 0x13); 2640 rt2800_bbp_write(rt2x00dev, 73, 0x13);
2634 rt2800_bbp_write(rt2x00dev, 75, 0x46); 2641 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2635 rt2800_bbp_write(rt2x00dev, 76, 0x28); 2642 rt2800_bbp_write(rt2x00dev, 76, 0x28);
2636 rt2800_bbp_write(rt2x00dev, 77, 0x59); 2643 rt2800_bbp_write(rt2x00dev, 77, 0x59);
2637 } else { 2644 } else {
2638 rt2800_bbp_write(rt2x00dev, 69, 0x12); 2645 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2639 rt2800_bbp_write(rt2x00dev, 73, 0x10); 2646 rt2800_bbp_write(rt2x00dev, 73, 0x10);
@@ -2644,8 +2651,8 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
2644 if (rt2x00_rt(rt2x00dev, RT3070) || 2651 if (rt2x00_rt(rt2x00dev, RT3070) ||
2645 rt2x00_rt(rt2x00dev, RT3071) || 2652 rt2x00_rt(rt2x00dev, RT3071) ||
2646 rt2x00_rt(rt2x00dev, RT3090) || 2653 rt2x00_rt(rt2x00dev, RT3090) ||
2647 rt2x00_rt(rt2x00dev, RT3390) || 2654 rt2x00_rt(rt2x00dev, RT3390) ||
2648 rt2x00_rt(rt2x00dev, RT5390)) { 2655 rt2x00_rt(rt2x00dev, RT5390)) {
2649 rt2800_bbp_write(rt2x00dev, 79, 0x13); 2656 rt2800_bbp_write(rt2x00dev, 79, 0x13);
2650 rt2800_bbp_write(rt2x00dev, 80, 0x05); 2657 rt2800_bbp_write(rt2x00dev, 80, 0x05);
2651 rt2800_bbp_write(rt2x00dev, 81, 0x33); 2658 rt2800_bbp_write(rt2x00dev, 81, 0x33);
@@ -2657,62 +2664,62 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
2657 } 2664 }
2658 2665
2659 rt2800_bbp_write(rt2x00dev, 82, 0x62); 2666 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2660 if (rt2x00_rt(rt2x00dev, RT5390)) 2667 if (rt2x00_rt(rt2x00dev, RT5390))
2661 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 2668 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
2662 else 2669 else
2663 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 2670 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
2664 2671
2665 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D)) 2672 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
2666 rt2800_bbp_write(rt2x00dev, 84, 0x19); 2673 rt2800_bbp_write(rt2x00dev, 84, 0x19);
2667 else if (rt2x00_rt(rt2x00dev, RT5390)) 2674 else if (rt2x00_rt(rt2x00dev, RT5390))
2668 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 2675 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
2669 else 2676 else
2670 rt2800_bbp_write(rt2x00dev, 84, 0x99); 2677 rt2800_bbp_write(rt2x00dev, 84, 0x99);
2671 2678
2672 if (rt2x00_rt(rt2x00dev, RT5390)) 2679 if (rt2x00_rt(rt2x00dev, RT5390))
2673 rt2800_bbp_write(rt2x00dev, 86, 0x38); 2680 rt2800_bbp_write(rt2x00dev, 86, 0x38);
2674 else 2681 else
2675 rt2800_bbp_write(rt2x00dev, 86, 0x00); 2682 rt2800_bbp_write(rt2x00dev, 86, 0x00);
2676 2683
2677 rt2800_bbp_write(rt2x00dev, 91, 0x04); 2684 rt2800_bbp_write(rt2x00dev, 91, 0x04);
2678 2685
2679 if (rt2x00_rt(rt2x00dev, RT5390)) 2686 if (rt2x00_rt(rt2x00dev, RT5390))
2680 rt2800_bbp_write(rt2x00dev, 92, 0x02); 2687 rt2800_bbp_write(rt2x00dev, 92, 0x02);
2681 else 2688 else
2682 rt2800_bbp_write(rt2x00dev, 92, 0x00); 2689 rt2800_bbp_write(rt2x00dev, 92, 0x00);
2683 2690
2684 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) || 2691 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
2685 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) || 2692 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
2686 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) || 2693 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
2687 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) || 2694 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
2688 rt2x00_rt(rt2x00dev, RT5390) || 2695 rt2x00_rt(rt2x00dev, RT5390) ||
2689 rt2800_is_305x_soc(rt2x00dev)) 2696 rt2800_is_305x_soc(rt2x00dev))
2690 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 2697 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
2691 else 2698 else
2692 rt2800_bbp_write(rt2x00dev, 103, 0x00); 2699 rt2800_bbp_write(rt2x00dev, 103, 0x00);
2693 2700
2694 if (rt2x00_rt(rt2x00dev, RT5390)) 2701 if (rt2x00_rt(rt2x00dev, RT5390))
2695 rt2800_bbp_write(rt2x00dev, 104, 0x92); 2702 rt2800_bbp_write(rt2x00dev, 104, 0x92);
2696 2703
2697 if (rt2800_is_305x_soc(rt2x00dev)) 2704 if (rt2800_is_305x_soc(rt2x00dev))
2698 rt2800_bbp_write(rt2x00dev, 105, 0x01); 2705 rt2800_bbp_write(rt2x00dev, 105, 0x01);
2699 else if (rt2x00_rt(rt2x00dev, RT5390)) 2706 else if (rt2x00_rt(rt2x00dev, RT5390))
2700 rt2800_bbp_write(rt2x00dev, 105, 0x3c); 2707 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
2701 else 2708 else
2702 rt2800_bbp_write(rt2x00dev, 105, 0x05); 2709 rt2800_bbp_write(rt2x00dev, 105, 0x05);
2703 2710
2704 if (rt2x00_rt(rt2x00dev, RT5390)) 2711 if (rt2x00_rt(rt2x00dev, RT5390))
2705 rt2800_bbp_write(rt2x00dev, 106, 0x03); 2712 rt2800_bbp_write(rt2x00dev, 106, 0x03);
2706 else 2713 else
2707 rt2800_bbp_write(rt2x00dev, 106, 0x35); 2714 rt2800_bbp_write(rt2x00dev, 106, 0x35);
2708 2715
2709 if (rt2x00_rt(rt2x00dev, RT5390)) 2716 if (rt2x00_rt(rt2x00dev, RT5390))
2710 rt2800_bbp_write(rt2x00dev, 128, 0x12); 2717 rt2800_bbp_write(rt2x00dev, 128, 0x12);
2711 2718
2712 if (rt2x00_rt(rt2x00dev, RT3071) || 2719 if (rt2x00_rt(rt2x00dev, RT3071) ||
2713 rt2x00_rt(rt2x00dev, RT3090) || 2720 rt2x00_rt(rt2x00dev, RT3090) ||
2714 rt2x00_rt(rt2x00dev, RT3390) || 2721 rt2x00_rt(rt2x00dev, RT3390) ||
2715 rt2x00_rt(rt2x00dev, RT5390)) { 2722 rt2x00_rt(rt2x00dev, RT5390)) {
2716 rt2800_bbp_read(rt2x00dev, 138, &value); 2723 rt2800_bbp_read(rt2x00dev, 138, &value);
2717 2724
2718 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); 2725 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
@@ -2724,41 +2731,42 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
2724 rt2800_bbp_write(rt2x00dev, 138, value); 2731 rt2800_bbp_write(rt2x00dev, 138, value);
2725 } 2732 }
2726 2733
2727 if (rt2x00_rt(rt2x00dev, RT5390)) { 2734 if (rt2x00_rt(rt2x00dev, RT5390)) {
2728 int ant, div_mode; 2735 int ant, div_mode;
2729 2736
2730 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom); 2737 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2731 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY); 2738 div_mode = rt2x00_get_field16(eeprom,
2732 ant = (div_mode == 3) ? 1 : 0; 2739 EEPROM_NIC_CONF1_ANT_DIVERSITY);
2733 2740 ant = (div_mode == 3) ? 1 : 0;
2734 /* check if this is a Bluetooth combo card */ 2741
2735 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom); 2742 /* check if this is a Bluetooth combo card */
2736 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) { 2743 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2737 u32 reg; 2744 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) {
2738 2745 u32 reg;
2739 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg); 2746
2740 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0); 2747 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
2741 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT6, 0); 2748 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
2742 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 0); 2749 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT6, 0);
2743 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 0); 2750 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 0);
2744 if (ant == 0) 2751 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 0);
2745 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 1); 2752 if (ant == 0)
2746 else if (ant == 1) 2753 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 1);
2747 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 1); 2754 else if (ant == 1)
2748 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg); 2755 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 1);
2749 } 2756 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
2750 2757 }
2751 rt2800_bbp_read(rt2x00dev, 152, &value); 2758
2752 if (ant == 0) 2759 rt2800_bbp_read(rt2x00dev, 152, &value);
2753 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1); 2760 if (ant == 0)
2754 else 2761 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
2755 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0); 2762 else
2756 rt2800_bbp_write(rt2x00dev, 152, value); 2763 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
2757 2764 rt2800_bbp_write(rt2x00dev, 152, value);
2758 /* Init frequency calibration */ 2765
2759 rt2800_bbp_write(rt2x00dev, 142, 1); 2766 /* Init frequency calibration */
2760 rt2800_bbp_write(rt2x00dev, 143, 57); 2767 rt2800_bbp_write(rt2x00dev, 142, 1);
2761 } 2768 rt2800_bbp_write(rt2x00dev, 143, 57);
2769 }
2762 2770
2763 for (i = 0; i < EEPROM_BBP_SIZE; i++) { 2771 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
2764 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom); 2772 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
@@ -2848,28 +2856,28 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2848 !rt2x00_rt(rt2x00dev, RT3071) && 2856 !rt2x00_rt(rt2x00dev, RT3071) &&
2849 !rt2x00_rt(rt2x00dev, RT3090) && 2857 !rt2x00_rt(rt2x00dev, RT3090) &&
2850 !rt2x00_rt(rt2x00dev, RT3390) && 2858 !rt2x00_rt(rt2x00dev, RT3390) &&
2851 !rt2x00_rt(rt2x00dev, RT5390) && 2859 !rt2x00_rt(rt2x00dev, RT5390) &&
2852 !rt2800_is_305x_soc(rt2x00dev)) 2860 !rt2800_is_305x_soc(rt2x00dev))
2853 return 0; 2861 return 0;
2854 2862
2855 /* 2863 /*
2856 * Init RF calibration. 2864 * Init RF calibration.
2857 */ 2865 */
2858 if (rt2x00_rt(rt2x00dev, RT5390)) { 2866 if (rt2x00_rt(rt2x00dev, RT5390)) {
2859 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr); 2867 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
2860 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1); 2868 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
2861 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 2869 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
2862 msleep(1); 2870 msleep(1);
2863 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0); 2871 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
2864 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 2872 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
2865 } else { 2873 } else {
2866 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); 2874 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2867 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1); 2875 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2868 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2876 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2869 msleep(1); 2877 msleep(1);
2870 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0); 2878 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2871 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2879 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2872 } 2880 }
2873 2881
2874 if (rt2x00_rt(rt2x00dev, RT3070) || 2882 if (rt2x00_rt(rt2x00dev, RT3070) ||
2875 rt2x00_rt(rt2x00dev, RT3071) || 2883 rt2x00_rt(rt2x00dev, RT3071) ||
@@ -2960,87 +2968,87 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2960 rt2800_rfcsr_write(rt2x00dev, 30, 0x00); 2968 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
2961 rt2800_rfcsr_write(rt2x00dev, 31, 0x00); 2969 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
2962 return 0; 2970 return 0;
2963 } else if (rt2x00_rt(rt2x00dev, RT5390)) { 2971 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2964 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); 2972 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
2965 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 2973 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
2966 rt2800_rfcsr_write(rt2x00dev, 3, 0x88); 2974 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
2967 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 2975 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
2968 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 2976 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
2969 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 2977 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
2970 else 2978 else
2971 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); 2979 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
2972 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 2980 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
2973 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 2981 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
2974 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 2982 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
2975 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6); 2983 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
2976 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 2984 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
2977 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 2985 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
2978 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 2986 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
2979 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 2987 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
2980 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 2988 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
2981 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 2989 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
2982 2990
2983 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 2991 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
2984 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 2992 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
2985 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 2993 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
2986 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 2994 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
2987 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 2995 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
2988 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 2996 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
2989 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 2997 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2990 else 2998 else
2991 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0); 2999 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
2992 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 3000 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
2993 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 3001 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
2994 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 3002 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
2995 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 3003 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
2996 3004
2997 rt2800_rfcsr_write(rt2x00dev, 30, 0x00); 3005 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
2998 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 3006 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
2999 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 3007 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3000 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 3008 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3001 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 3009 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3002 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 3010 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3003 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 3011 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3004 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 3012 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3005 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 3013 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3006 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 3014 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3007 3015
3008 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 3016 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3009 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 3017 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3010 else 3018 else
3011 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b); 3019 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
3012 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 3020 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3013 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2); 3021 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
3014 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a); 3022 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
3015 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 3023 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3016 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 3024 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3017 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 3025 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3018 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 3026 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3019 else 3027 else
3020 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b); 3028 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
3021 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 3029 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3022 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 3030 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3023 rt2800_rfcsr_write(rt2x00dev, 49, 0x94); 3031 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
3024 3032
3025 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 3033 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3026 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 3034 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3027 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 3035 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3028 else 3036 else
3029 rt2800_rfcsr_write(rt2x00dev, 53, 0x84); 3037 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
3030 rt2800_rfcsr_write(rt2x00dev, 54, 0x78); 3038 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3031 rt2800_rfcsr_write(rt2x00dev, 55, 0x44); 3039 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
3032 rt2800_rfcsr_write(rt2x00dev, 56, 0x22); 3040 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
3033 rt2800_rfcsr_write(rt2x00dev, 57, 0x80); 3041 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3034 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); 3042 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3035 rt2800_rfcsr_write(rt2x00dev, 59, 0x63); 3043 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
3036 3044
3037 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 3045 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3038 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 3046 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3039 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1); 3047 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
3040 else 3048 else
3041 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd); 3049 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
3042 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 3050 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
3043 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 3051 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
3044 } 3052 }
3045 3053
3046 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { 3054 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
@@ -3094,23 +3102,23 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
3094 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15); 3102 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
3095 } 3103 }
3096 3104
3097 if (!rt2x00_rt(rt2x00dev, RT5390)) { 3105 if (!rt2x00_rt(rt2x00dev, RT5390)) {
3098 /* 3106 /*
3099 * Set back to initial state 3107 * Set back to initial state
3100 */ 3108 */
3101 rt2800_bbp_write(rt2x00dev, 24, 0); 3109 rt2800_bbp_write(rt2x00dev, 24, 0);
3102 3110
3103 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr); 3111 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3104 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0); 3112 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
3105 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 3113 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3106 3114
3107 /* 3115 /*
3108 * Set BBP back to BW20 3116 * Set BBP back to BW20
3109 */ 3117 */
3110 rt2800_bbp_read(rt2x00dev, 4, &bbp); 3118 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3111 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0); 3119 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
3112 rt2800_bbp_write(rt2x00dev, 4, bbp); 3120 rt2800_bbp_write(rt2x00dev, 4, bbp);
3113 } 3121 }
3114 3122
3115 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) || 3123 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
3116 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 3124 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
@@ -3122,23 +3130,24 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
3122 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1); 3130 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
3123 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg); 3131 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
3124 3132
3125 if (!rt2x00_rt(rt2x00dev, RT5390)) { 3133 if (!rt2x00_rt(rt2x00dev, RT5390)) {
3126 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr); 3134 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
3127 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0); 3135 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
3128 if (rt2x00_rt(rt2x00dev, RT3070) || 3136 if (rt2x00_rt(rt2x00dev, RT3070) ||
3129 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 3137 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3130 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 3138 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3131 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { 3139 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3132 if (!test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) 3140 if (!test_bit(CONFIG_EXTERNAL_LNA_BG,
3133 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1); 3141 &rt2x00dev->flags))
3134 } 3142 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
3135 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom); 3143 }
3136 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1) 3144 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
3137 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN, 3145 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
3138 rt2x00_get_field16(eeprom, 3146 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
3139 EEPROM_TXMIXER_GAIN_BG_VAL)); 3147 rt2x00_get_field16(eeprom,
3140 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 3148 EEPROM_TXMIXER_GAIN_BG_VAL));
3141 } 3149 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3150 }
3142 3151
3143 if (rt2x00_rt(rt2x00dev, RT3090)) { 3152 if (rt2x00_rt(rt2x00dev, RT3090)) {
3144 rt2800_bbp_read(rt2x00dev, 138, &bbp); 3153 rt2800_bbp_read(rt2x00dev, 138, &bbp);
@@ -3189,19 +3198,19 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
3189 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr); 3198 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
3190 } 3199 }
3191 3200
3192 if (rt2x00_rt(rt2x00dev, RT5390)) { 3201 if (rt2x00_rt(rt2x00dev, RT5390)) {
3193 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr); 3202 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
3194 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0); 3203 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
3195 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr); 3204 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
3196 3205
3197 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr); 3206 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
3198 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0); 3207 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
3199 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 3208 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3200 3209
3201 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); 3210 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3202 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2); 3211 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
3203 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 3212 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3204 } 3213 }
3205 3214
3206 return 0; 3215 return 0;
3207} 3216}
@@ -3467,15 +3476,15 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
3467 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); 3476 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3468 3477
3469 /* 3478 /*
3470 * Identify RF chipset by EEPROM value 3479 * Identify RF chipset by EEPROM value
3471 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field 3480 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
3472 * RT53xx: defined in "EEPROM_CHIP_ID" field 3481 * RT53xx: defined in "EEPROM_CHIP_ID" field
3473 */ 3482 */
3474 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg); 3483 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
3475 if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390) 3484 if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390)
3476 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value); 3485 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
3477 else 3486 else
3478 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE); 3487 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
3479 3488
3480 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET), 3489 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
3481 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION)); 3490 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
@@ -3487,8 +3496,8 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
3487 !rt2x00_rt(rt2x00dev, RT3071) && 3496 !rt2x00_rt(rt2x00dev, RT3071) &&
3488 !rt2x00_rt(rt2x00dev, RT3090) && 3497 !rt2x00_rt(rt2x00dev, RT3090) &&
3489 !rt2x00_rt(rt2x00dev, RT3390) && 3498 !rt2x00_rt(rt2x00dev, RT3390) &&
3490 !rt2x00_rt(rt2x00dev, RT3572) && 3499 !rt2x00_rt(rt2x00dev, RT3572) &&
3491 !rt2x00_rt(rt2x00dev, RT5390)) { 3500 !rt2x00_rt(rt2x00dev, RT5390)) {
3492 ERROR(rt2x00dev, "Invalid RT chipset detected.\n"); 3501 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
3493 return -ENODEV; 3502 return -ENODEV;
3494 } 3503 }
@@ -3502,8 +3511,8 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
3502 !rt2x00_rf(rt2x00dev, RF3021) && 3511 !rt2x00_rf(rt2x00dev, RF3021) &&
3503 !rt2x00_rf(rt2x00dev, RF3022) && 3512 !rt2x00_rf(rt2x00dev, RF3022) &&
3504 !rt2x00_rf(rt2x00dev, RF3052) && 3513 !rt2x00_rf(rt2x00dev, RF3052) &&
3505 !rt2x00_rf(rt2x00dev, RF3320) && 3514 !rt2x00_rf(rt2x00dev, RF3320) &&
3506 !rt2x00_rf(rt2x00dev, RF5390)) { 3515 !rt2x00_rf(rt2x00dev, RF5390)) {
3507 ERROR(rt2x00dev, "Invalid RF chipset detected.\n"); 3516 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
3508 return -ENODEV; 3517 return -ENODEV;
3509 } 3518 }
@@ -3800,8 +3809,8 @@ int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
3800 rt2x00_rf(rt2x00dev, RF2020) || 3809 rt2x00_rf(rt2x00dev, RF2020) ||
3801 rt2x00_rf(rt2x00dev, RF3021) || 3810 rt2x00_rf(rt2x00dev, RF3021) ||
3802 rt2x00_rf(rt2x00dev, RF3022) || 3811 rt2x00_rf(rt2x00dev, RF3022) ||
3803 rt2x00_rf(rt2x00dev, RF3320) || 3812 rt2x00_rf(rt2x00dev, RF3320) ||
3804 rt2x00_rf(rt2x00dev, RF5390)) { 3813 rt2x00_rf(rt2x00dev, RF5390)) {
3805 spec->num_channels = 14; 3814 spec->num_channels = 14;
3806 spec->channels = rf_vals_3x; 3815 spec->channels = rf_vals_3x;
3807 } else if (rt2x00_rf(rt2x00dev, RF3052)) { 3816 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
diff --git a/drivers/net/wireless/rt2x00/rt2800pci.c b/drivers/net/wireless/rt2x00/rt2800pci.c
index 38605e9fe427..6c634c3a2e01 100644
--- a/drivers/net/wireless/rt2x00/rt2800pci.c
+++ b/drivers/net/wireless/rt2x00/rt2800pci.c
@@ -493,12 +493,12 @@ static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
493 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f); 493 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
494 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00); 494 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
495 495
496 if (rt2x00_rt(rt2x00dev, RT5390)) { 496 if (rt2x00_rt(rt2x00dev, RT5390)) {
497 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg); 497 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
498 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1); 498 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
499 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1); 499 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
500 rt2800_register_write(rt2x00dev, AUX_CTRL, reg); 500 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
501 } 501 }
502 502
503 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); 503 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
504 504
@@ -1135,7 +1135,7 @@ static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
1135 { PCI_DEVICE(0x1814, 0x3593), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1135 { PCI_DEVICE(0x1814, 0x3593), PCI_DEVICE_DATA(&rt2800pci_ops) },
1136#endif 1136#endif
1137#ifdef CONFIG_RT2800PCI_RT53XX 1137#ifdef CONFIG_RT2800PCI_RT53XX
1138 { PCI_DEVICE(0x1814, 0x5390), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1138 { PCI_DEVICE(0x1814, 0x5390), PCI_DEVICE_DATA(&rt2800pci_ops) },
1139#endif 1139#endif
1140 { 0, } 1140 { 0, }
1141}; 1141};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-16 16:10:49 -0500