1 files changed, 21 insertions, 5 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f99993577168..4c9684c54f18 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5119,6 +5119,8 @@ static void ironlake_update_pch_refclk(struct drm_device *dev)
         bool has_cpu_edp = false;
         bool has_pch_edp = false;
         bool has_panel = false;
+        bool has_ck505 = false;
+        bool can_ssc = false;
 
         /* We need to take the global config into account */
         list_for_each_entry(encoder, &mode_config->encoder_list,
@@ -5137,8 +5139,18 @@ static void ironlake_update_pch_refclk(struct drm_device *dev)
                         break;
                 }
         }
-        DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d\n",
-                      has_panel, has_lvds, has_pch_edp, has_cpu_edp);
+
+        if (HAS_PCH_IBX(dev)) {
+                has_ck505 = dev_priv->display_clock_mode;
+                can_ssc = has_ck505;
+        } else {
+                has_ck505 = false;
+                can_ssc = true;
+        }
+
+        DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
+                      has_panel, has_lvds, has_pch_edp, has_cpu_edp,
+                      has_ck505);
 
         /* Ironlake: try to setup display ref clock before DPLL
          * enabling. This is only under driver's control after
@@ -5148,14 +5160,18 @@ static void ironlake_update_pch_refclk(struct drm_device *dev)
         temp = I915_READ(PCH_DREF_CONTROL);
         /* Always enable nonspread source */
         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
-        temp |= DREF_NONSPREAD_SOURCE_ENABLE;
+
+        if (has_ck505)
+                temp |= DREF_NONSPREAD_CK505_ENABLE;
+        else
+                temp |= DREF_NONSPREAD_SOURCE_ENABLE;
 
         if (has_panel) {
                 temp &= ~DREF_SSC_SOURCE_MASK;
                 temp |= DREF_SSC_SOURCE_ENABLE;
 
                 /* SSC must be turned on before enabling the CPU output  */
-                if (intel_panel_use_ssc(dev_priv)) {
+                if (intel_panel_use_ssc(dev_priv) && can_ssc) {
                         DRM_DEBUG_KMS("Using SSC on panel\n");
                         temp |= DREF_SSC1_ENABLE;
                 }
@@ -5169,7 +5185,7 @@ static void ironlake_update_pch_refclk(struct drm_device *dev)
 
                 /* Enable CPU source on CPU attached eDP */
                 if (has_cpu_edp) {
-                        if (intel_panel_use_ssc(dev_priv)) {
+                        if (intel_panel_use_ssc(dev_priv) && can_ssc) {
                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
                         }