diff options
author | Keith Packard <keithp@keithp.com> | 2011-09-26 17:29:12 -0400 |
---|---|---|
committer | Keith Packard <keithp@keithp.com> | 2011-09-28 17:08:06 -0400 |
commit | 99eb6a01e5ac6cf28aadc64e6ff346939874dfd2 (patch) | |
tree | 9d91704f1196bf33b62c0355c4bab61f395eab3f /drivers | |
parent | 199e5d79f1c988a8039fa75b736a3adcdda56abc (diff) |
drm/i915: Use CK505 as non-SSC source where available
When trying to use SSC on Ibex Peak without CK505, any non-SSC outputs
(like VGA or TV) get broken. So, do not use SSC on Ibex Peak unless
there is a CK505 available (as specified by the VBT).
On Cougar Point, all clocking is internal, so SSC can always be used,
and there will never be a CK505 available.
This eliminates VGA shimmer on some Ironlake machines which have a
CK505 clock source.
References: https://bugzilla.kernel.org/show_bug.cgi?id=21742
References: https://bugs.freedesktop.org/show_bug.cgi?id=38750
Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 26 |
1 files changed, 21 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index f99993577168..4c9684c54f18 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -5119,6 +5119,8 @@ static void ironlake_update_pch_refclk(struct drm_device *dev) | |||
5119 | bool has_cpu_edp = false; | 5119 | bool has_cpu_edp = false; |
5120 | bool has_pch_edp = false; | 5120 | bool has_pch_edp = false; |
5121 | bool has_panel = false; | 5121 | bool has_panel = false; |
5122 | bool has_ck505 = false; | ||
5123 | bool can_ssc = false; | ||
5122 | 5124 | ||
5123 | /* We need to take the global config into account */ | 5125 | /* We need to take the global config into account */ |
5124 | list_for_each_entry(encoder, &mode_config->encoder_list, | 5126 | list_for_each_entry(encoder, &mode_config->encoder_list, |
@@ -5137,8 +5139,18 @@ static void ironlake_update_pch_refclk(struct drm_device *dev) | |||
5137 | break; | 5139 | break; |
5138 | } | 5140 | } |
5139 | } | 5141 | } |
5140 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d\n", | 5142 | |
5141 | has_panel, has_lvds, has_pch_edp, has_cpu_edp); | 5143 | if (HAS_PCH_IBX(dev)) { |
5144 | has_ck505 = dev_priv->display_clock_mode; | ||
5145 | can_ssc = has_ck505; | ||
5146 | } else { | ||
5147 | has_ck505 = false; | ||
5148 | can_ssc = true; | ||
5149 | } | ||
5150 | |||
5151 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n", | ||
5152 | has_panel, has_lvds, has_pch_edp, has_cpu_edp, | ||
5153 | has_ck505); | ||
5142 | 5154 | ||
5143 | /* Ironlake: try to setup display ref clock before DPLL | 5155 | /* Ironlake: try to setup display ref clock before DPLL |
5144 | * enabling. This is only under driver's control after | 5156 | * enabling. This is only under driver's control after |
@@ -5148,14 +5160,18 @@ static void ironlake_update_pch_refclk(struct drm_device *dev) | |||
5148 | temp = I915_READ(PCH_DREF_CONTROL); | 5160 | temp = I915_READ(PCH_DREF_CONTROL); |
5149 | /* Always enable nonspread source */ | 5161 | /* Always enable nonspread source */ |
5150 | temp &= ~DREF_NONSPREAD_SOURCE_MASK; | 5162 | temp &= ~DREF_NONSPREAD_SOURCE_MASK; |
5151 | temp |= DREF_NONSPREAD_SOURCE_ENABLE; | 5163 | |
5164 | if (has_ck505) | ||
5165 | temp |= DREF_NONSPREAD_CK505_ENABLE; | ||
5166 | else | ||
5167 | temp |= DREF_NONSPREAD_SOURCE_ENABLE; | ||
5152 | 5168 | ||
5153 | if (has_panel) { | 5169 | if (has_panel) { |
5154 | temp &= ~DREF_SSC_SOURCE_MASK; | 5170 | temp &= ~DREF_SSC_SOURCE_MASK; |
5155 | temp |= DREF_SSC_SOURCE_ENABLE; | 5171 | temp |= DREF_SSC_SOURCE_ENABLE; |
5156 | 5172 | ||
5157 | /* SSC must be turned on before enabling the CPU output */ | 5173 | /* SSC must be turned on before enabling the CPU output */ |
5158 | if (intel_panel_use_ssc(dev_priv)) { | 5174 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
5159 | DRM_DEBUG_KMS("Using SSC on panel\n"); | 5175 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
5160 | temp |= DREF_SSC1_ENABLE; | 5176 | temp |= DREF_SSC1_ENABLE; |
5161 | } | 5177 | } |
@@ -5169,7 +5185,7 @@ static void ironlake_update_pch_refclk(struct drm_device *dev) | |||
5169 | 5185 | ||
5170 | /* Enable CPU source on CPU attached eDP */ | 5186 | /* Enable CPU source on CPU attached eDP */ |
5171 | if (has_cpu_edp) { | 5187 | if (has_cpu_edp) { |
5172 | if (intel_panel_use_ssc(dev_priv)) { | 5188 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
5173 | DRM_DEBUG_KMS("Using SSC on eDP\n"); | 5189 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
5174 | temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | 5190 | temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
5175 | } | 5191 | } |