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path: root/drivers/video/geode
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-rw-r--r--drivers/video/geode/display_gx.c28
-rw-r--r--drivers/video/geode/display_gx.h78
-rw-r--r--drivers/video/geode/gxfb.h222
-rw-r--r--drivers/video/geode/video_gx.c92
-rw-r--r--drivers/video/geode/video_gx.h39
5 files changed, 276 insertions, 183 deletions
diff --git a/drivers/video/geode/display_gx.c b/drivers/video/geode/display_gx.c
index 47f422e19974..acf20bf2d26c 100644
--- a/drivers/video/geode/display_gx.c
+++ b/drivers/video/geode/display_gx.c
@@ -51,20 +51,21 @@ static void gx_set_mode(struct fb_info *info)
51 int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal; 51 int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
52 52
53 /* Unlock the display controller registers. */ 53 /* Unlock the display controller registers. */
54 write_dc(par, DC_UNLOCK, DC_UNLOCK_CODE); 54 write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
55 55
56 gcfg = read_dc(par, DC_GENERAL_CFG); 56 gcfg = read_dc(par, DC_GENERAL_CFG);
57 dcfg = read_dc(par, DC_DISPLAY_CFG); 57 dcfg = read_dc(par, DC_DISPLAY_CFG);
58 58
59 /* Disable the timing generator. */ 59 /* Disable the timing generator. */
60 dcfg &= ~(DC_DCFG_TGEN); 60 dcfg &= ~DC_DISPLAY_CFG_TGEN;
61 write_dc(par, DC_DISPLAY_CFG, dcfg); 61 write_dc(par, DC_DISPLAY_CFG, dcfg);
62 62
63 /* Wait for pending memory requests before disabling the FIFO load. */ 63 /* Wait for pending memory requests before disabling the FIFO load. */
64 udelay(100); 64 udelay(100);
65 65
66 /* Disable FIFO load and compression. */ 66 /* Disable FIFO load and compression. */
67 gcfg &= ~(DC_GCFG_DFLE | DC_GCFG_CMPE | DC_GCFG_DECE); 67 gcfg &= ~(DC_GENERAL_CFG_DFLE | DC_GENERAL_CFG_CMPE |
68 DC_GENERAL_CFG_DECE);
68 write_dc(par, DC_GENERAL_CFG, gcfg); 69 write_dc(par, DC_GENERAL_CFG, gcfg);
69 70
70 /* Setup DCLK and its divisor. */ 71 /* Setup DCLK and its divisor. */
@@ -75,12 +76,13 @@ static void gx_set_mode(struct fb_info *info)
75 */ 76 */
76 77
77 /* Clear all unused feature bits. */ 78 /* Clear all unused feature bits. */
78 gcfg &= DC_GCFG_YUVM | DC_GCFG_VDSE; 79 gcfg &= DC_GENERAL_CFG_YUVM | DC_GENERAL_CFG_VDSE;
79 dcfg = 0; 80 dcfg = 0;
80 81
81 /* Set FIFO priority (default 6/5) and enable. */ 82 /* Set FIFO priority (default 6/5) and enable. */
82 /* FIXME: increase fifo priority for 1280x1024 and higher modes? */ 83 /* FIXME: increase fifo priority for 1280x1024 and higher modes? */
83 gcfg |= (6 << DC_GCFG_DFHPEL_POS) | (5 << DC_GCFG_DFHPSL_POS) | DC_GCFG_DFLE; 84 gcfg |= (6 << DC_GENERAL_CFG_DFHPEL_SHIFT) |
85 (5 << DC_GENERAL_CFG_DFHPSL_SHIFT) | DC_GENERAL_CFG_DFLE;
84 86
85 /* Framebuffer start offset. */ 87 /* Framebuffer start offset. */
86 write_dc(par, DC_FB_ST_OFFSET, 0); 88 write_dc(par, DC_FB_ST_OFFSET, 0);
@@ -92,25 +94,25 @@ static void gx_set_mode(struct fb_info *info)
92 94
93 95
94 /* Enable graphics and video data and unmask address lines. */ 96 /* Enable graphics and video data and unmask address lines. */
95 dcfg |= DC_DCFG_GDEN | DC_DCFG_VDEN | DC_DCFG_A20M | DC_DCFG_A18M; 97 dcfg |= DC_DISPLAY_CFG_GDEN | DC_DISPLAY_CFG_VDEN |
98 DC_DISPLAY_CFG_A20M | DC_DISPLAY_CFG_A18M;
96 99
97 /* Set pixel format. */ 100 /* Set pixel format. */
98 switch (info->var.bits_per_pixel) { 101 switch (info->var.bits_per_pixel) {
99 case 8: 102 case 8:
100 dcfg |= DC_DCFG_DISP_MODE_8BPP; 103 dcfg |= DC_DISPLAY_CFG_DISP_MODE_8BPP;
101 break; 104 break;
102 case 16: 105 case 16:
103 dcfg |= DC_DCFG_DISP_MODE_16BPP; 106 dcfg |= DC_DISPLAY_CFG_DISP_MODE_16BPP;
104 dcfg |= DC_DCFG_16BPP_MODE_565;
105 break; 107 break;
106 case 32: 108 case 32:
107 dcfg |= DC_DCFG_DISP_MODE_24BPP; 109 dcfg |= DC_DISPLAY_CFG_DISP_MODE_24BPP;
108 dcfg |= DC_DCFG_PALB; 110 dcfg |= DC_DISPLAY_CFG_PALB;
109 break; 111 break;
110 } 112 }
111 113
112 /* Enable timing generator. */ 114 /* Enable timing generator. */
113 dcfg |= DC_DCFG_TGEN; 115 dcfg |= DC_DISPLAY_CFG_TGEN;
114 116
115 /* Horizontal and vertical timings. */ 117 /* Horizontal and vertical timings. */
116 hactive = info->var.xres; 118 hactive = info->var.xres;
@@ -148,7 +150,7 @@ static void gx_set_mode(struct fb_info *info)
148 par->vid_ops->configure_display(info); 150 par->vid_ops->configure_display(info);
149 151
150 /* Relock display controller registers */ 152 /* Relock display controller registers */
151 write_dc(par, DC_UNLOCK, 0); 153 write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
152} 154}
153 155
154static void gx_set_hw_palette_reg(struct fb_info *info, unsigned regno, 156static void gx_set_hw_palette_reg(struct fb_info *info, unsigned regno,
diff --git a/drivers/video/geode/display_gx.h b/drivers/video/geode/display_gx.h
index df94e4fc6626..56e9d2ea52c9 100644
--- a/drivers/video/geode/display_gx.h
+++ b/drivers/video/geode/display_gx.h
@@ -19,82 +19,4 @@ extern struct geode_dc_ops gx_dc_ops;
19/* MSR that tells us if a TFT or CRT is attached */ 19/* MSR that tells us if a TFT or CRT is attached */
20#define GLD_MSR_CONFIG_DM_FP 0x40 20#define GLD_MSR_CONFIG_DM_FP 0x40
21 21
22/* Display controller registers */
23
24#define DC_UNLOCK 0x00
25# define DC_UNLOCK_CODE 0x00004758
26
27#define DC_GENERAL_CFG 0x04
28# define DC_GCFG_DFLE 0x00000001
29# define DC_GCFG_CURE 0x00000002
30# define DC_GCFG_ICNE 0x00000004
31# define DC_GCFG_VIDE 0x00000008
32# define DC_GCFG_CMPE 0x00000020
33# define DC_GCFG_DECE 0x00000040
34# define DC_GCFG_VGAE 0x00000080
35# define DC_GCFG_DFHPSL_MASK 0x00000F00
36# define DC_GCFG_DFHPSL_POS 8
37# define DC_GCFG_DFHPEL_MASK 0x0000F000
38# define DC_GCFG_DFHPEL_POS 12
39# define DC_GCFG_STFM 0x00010000
40# define DC_GCFG_FDTY 0x00020000
41# define DC_GCFG_VGAFT 0x00040000
42# define DC_GCFG_VDSE 0x00080000
43# define DC_GCFG_YUVM 0x00100000
44# define DC_GCFG_VFSL 0x00800000
45# define DC_GCFG_SIGE 0x01000000
46# define DC_GCFG_SGRE 0x02000000
47# define DC_GCFG_SGFR 0x04000000
48# define DC_GCFG_CRC_MODE 0x08000000
49# define DC_GCFG_DIAG 0x10000000
50# define DC_GCFG_CFRW 0x20000000
51
52#define DC_DISPLAY_CFG 0x08
53# define DC_DCFG_TGEN 0x00000001
54# define DC_DCFG_GDEN 0x00000008
55# define DC_DCFG_VDEN 0x00000010
56# define DC_DCFG_TRUP 0x00000040
57# define DC_DCFG_DISP_MODE_MASK 0x00000300
58# define DC_DCFG_DISP_MODE_8BPP 0x00000000
59# define DC_DCFG_DISP_MODE_16BPP 0x00000100
60# define DC_DCFG_DISP_MODE_24BPP 0x00000200
61# define DC_DCFG_16BPP_MODE_MASK 0x00000c00
62# define DC_DCFG_16BPP_MODE_565 0x00000000
63# define DC_DCFG_16BPP_MODE_555 0x00000100
64# define DC_DCFG_16BPP_MODE_444 0x00000200
65# define DC_DCFG_DCEN 0x00080000
66# define DC_DCFG_PALB 0x02000000
67# define DC_DCFG_FRLK 0x04000000
68# define DC_DCFG_VISL 0x08000000
69# define DC_DCFG_FRSL 0x20000000
70# define DC_DCFG_A18M 0x40000000
71# define DC_DCFG_A20M 0x80000000
72
73#define DC_FB_ST_OFFSET 0x10
74
75#define DC_LINE_SIZE 0x30
76# define DC_LINE_SIZE_FB_LINE_SIZE_MASK 0x000007ff
77# define DC_LINE_SIZE_FB_LINE_SIZE_POS 0
78# define DC_LINE_SIZE_CB_LINE_SIZE_MASK 0x007f0000
79# define DC_LINE_SIZE_CB_LINE_SIZE_POS 16
80# define DC_LINE_SIZE_VID_LINE_SIZE_MASK 0xff000000
81# define DC_LINE_SIZE_VID_LINE_SIZE_POS 24
82
83#define DC_GFX_PITCH 0x34
84# define DC_GFX_PITCH_FB_PITCH_MASK 0x0000ffff
85# define DC_GFX_PITCH_FB_PITCH_POS 0
86# define DC_GFX_PITCH_CB_PITCH_MASK 0xffff0000
87# define DC_GFX_PITCH_CB_PITCH_POS 16
88
89#define DC_H_ACTIVE_TIMING 0x40
90#define DC_H_BLANK_TIMING 0x44
91#define DC_H_SYNC_TIMING 0x48
92#define DC_V_ACTIVE_TIMING 0x50
93#define DC_V_BLANK_TIMING 0x54
94#define DC_V_SYNC_TIMING 0x58
95
96#define DC_PAL_ADDRESS 0x70
97#define DC_PAL_DATA 0x74
98
99#define DC_GLIU0_MEM_OFFSET 0x84
100#endif /* !__DISPLAY_GX1_H__ */ 22#endif /* !__DISPLAY_GX1_H__ */
diff --git a/drivers/video/geode/gxfb.h b/drivers/video/geode/gxfb.h
index 42fa10db619a..d408ad354d2d 100644
--- a/drivers/video/geode/gxfb.h
+++ b/drivers/video/geode/gxfb.h
@@ -13,35 +13,243 @@
13 13
14#include <linux/io.h> 14#include <linux/io.h>
15 15
16/* Display Controller registers (table 6-38 from the data book) */
17enum dc_registers {
18 DC_UNLOCK = 0,
19 DC_GENERAL_CFG,
20 DC_DISPLAY_CFG,
21 DC_RSVD_0,
22
23 DC_FB_ST_OFFSET,
24 DC_CB_ST_OFFSET,
25 DC_CURS_ST_OFFSET,
26 DC_ICON_ST_OFFSET,
27
28 DC_VID_Y_ST_OFFSET,
29 DC_VID_U_ST_OFFSET,
30 DC_VID_V_ST_OFFSET,
31 DC_RSVD_1,
32
33 DC_LINE_SIZE,
34 DC_GFX_PITCH,
35 DC_VID_YUV_PITCH,
36 DC_RSVD_2,
37
38 DC_H_ACTIVE_TIMING,
39 DC_H_BLANK_TIMING,
40 DC_H_SYNC_TIMING,
41 DC_RSVD_3,
42
43 DC_V_ACTIVE_TIMING,
44 DC_V_BLANK_TIMING,
45 DC_V_SYNC_TIMING,
46 DC_RSVD_4,
47
48 DC_CURSOR_X,
49 DC_CURSOR_Y,
50 DC_ICON_X,
51 DC_LINE_CNT,
52
53 DC_PAL_ADDRESS,
54 DC_PAL_DATA,
55 DC_DFIFO_DIAG,
56 DC_CFIFO_DIAG,
57
58 DC_VID_DS_DELTA,
59 DC_GLIU0_MEM_OFFSET,
60 DC_RSVD_5,
61 DC_DV_ACC, /* 0x8c */
62};
63
64#define DC_UNLOCK_LOCK 0x00000000
65#define DC_UNLOCK_UNLOCK 0x00004758 /* magic value */
66
67#define DC_GENERAL_CFG_YUVM (1 << 20)
68#define DC_GENERAL_CFG_VDSE (1 << 19)
69#define DC_GENERAL_CFG_DFHPEL_SHIFT 12
70#define DC_GENERAL_CFG_DFHPSL_SHIFT 8
71#define DC_GENERAL_CFG_DECE (1 << 6)
72#define DC_GENERAL_CFG_CMPE (1 << 5)
73#define DC_GENERAL_CFG_VIDE (1 << 3)
74#define DC_GENERAL_CFG_ICNE (1 << 2)
75#define DC_GENERAL_CFG_CURE (1 << 1)
76#define DC_GENERAL_CFG_DFLE (1 << 0)
77
78#define DC_DISPLAY_CFG_A20M (1 << 31)
79#define DC_DISPLAY_CFG_A18M (1 << 30)
80#define DC_DISPLAY_CFG_PALB (1 << 25)
81#define DC_DISPLAY_CFG_DISP_MODE_24BPP (1 << 9)
82#define DC_DISPLAY_CFG_DISP_MODE_16BPP (1 << 8)
83#define DC_DISPLAY_CFG_DISP_MODE_8BPP (0)
84#define DC_DISPLAY_CFG_VDEN (1 << 4)
85#define DC_DISPLAY_CFG_GDEN (1 << 3)
86#define DC_DISPLAY_CFG_TGEN (1 << 0)
87
88
89/*
90 * Video Processor registers (table 6-54).
91 * There is space for 64 bit values, but we never use more than the
92 * lower 32 bits. The actual register save/restore code only bothers
93 * to restore those 32 bits.
94 */
95enum vp_registers {
96 VP_VCFG = 0,
97 VP_DCFG,
98
99 VP_VX,
100 VP_VY,
101
102 VP_VS,
103 VP_VCK,
104
105 VP_VCM,
106 VP_GAR,
107
108 VP_GDR,
109 VP_RSVD_0,
110
111 VP_MISC,
112 VP_CCS,
113
114 VP_RSVD_1,
115 VP_RSVD_2,
116
117 VP_RSVD_3,
118 VP_VDC,
119
120 VP_VCO,
121 VP_CRC,
122
123 VP_CRC32,
124 VP_VDE,
125
126 VP_CCK,
127 VP_CCM,
128
129 VP_CC1,
130 VP_CC2,
131
132 VP_A1X,
133 VP_A1Y,
134
135 VP_A1C,
136 VP_A1T,
137
138 VP_A2X,
139 VP_A2Y,
140
141 VP_A2C,
142 VP_A2T,
143
144 VP_A3X,
145 VP_A3Y,
146
147 VP_A3C,
148 VP_A3T,
149
150 VP_VRR,
151 VP_AWT,
152
153 VP_VTM, /* 0x130 */
154};
155
156#define VP_VCFG_VID_EN (1 << 0)
157
158#define VP_DCFG_DAC_VREF (1 << 26)
159#define VP_DCFG_GV_GAM (1 << 21)
160#define VP_DCFG_VG_CK (1 << 20)
161#define VP_DCFG_CRT_SYNC_SKW_DEFAULT (1 << 16)
162#define VP_DCFG_CRT_SYNC_SKW ((1 << 14) | (1 << 15) | (1 << 16))
163#define VP_DCFG_CRT_VSYNC_POL (1 << 9)
164#define VP_DCFG_CRT_HSYNC_POL (1 << 8)
165#define VP_DCFG_FP_DATA_EN (1 << 7) /* undocumented */
166#define VP_DCFG_FP_PWR_EN (1 << 6) /* undocumented */
167#define VP_DCFG_DAC_BL_EN (1 << 3)
168#define VP_DCFG_VSYNC_EN (1 << 2)
169#define VP_DCFG_HSYNC_EN (1 << 1)
170#define VP_DCFG_CRT_EN (1 << 0)
171
172#define VP_MISC_GAM_EN (1 << 0)
173#define VP_MISC_DACPWRDN (1 << 10)
174#define VP_MISC_APWRDN (1 << 11)
175
176
177/*
178 * Flat Panel registers (table 6-55).
179 * Also 64 bit registers; see above note about 32-bit handling.
180 */
181
182/* we're actually in the VP register space, starting at address 0x400 */
183#define VP_FP_START 0x400
184
185enum fp_registers {
186 FP_PT1 = 0,
187 FP_PT2,
188
189 FP_PM,
190 FP_DFC,
191
192 FP_BLFSR,
193 FP_RLFSR,
194
195 FP_FMI,
196 FP_FMD,
197
198 FP_RSVD_0,
199 FP_DCA,
200
201 FP_DMD,
202 FP_CRC,
203
204 FP_FBB, /* 0x460 */
205};
206
207#define FP_PT1_VSIZE_SHIFT 16 /* undocumented? */
208#define FP_PT1_VSIZE_MASK 0x7FF0000 /* undocumented? */
209
210#define FP_PT2_HSP (1 << 22)
211#define FP_PT2_VSP (1 << 23)
212
213#define FP_PM_P (1 << 24) /* panel power on */
214#define FP_PM_PANEL_PWR_UP (1 << 3) /* r/o */
215#define FP_PM_PANEL_PWR_DOWN (1 << 2) /* r/o */
216#define FP_PM_PANEL_OFF (1 << 1) /* r/o */
217#define FP_PM_PANEL_ON (1 << 0) /* r/o */
218
219#define FP_DFC_NFI ((1 << 4) | (1 << 5) | (1 << 6))
220
221
222/* register access functions */
223
16static inline uint32_t read_dc(struct geodefb_par *par, int reg) 224static inline uint32_t read_dc(struct geodefb_par *par, int reg)
17{ 225{
18 return readl(par->dc_regs + reg); 226 return readl(par->dc_regs + 4*reg);
19} 227}
20 228
21static inline void write_dc(struct geodefb_par *par, int reg, uint32_t val) 229static inline void write_dc(struct geodefb_par *par, int reg, uint32_t val)
22{ 230{
23 writel(val, par->dc_regs + reg); 231 writel(val, par->dc_regs + 4*reg);
24
25} 232}
26 233
234
27static inline uint32_t read_vp(struct geodefb_par *par, int reg) 235static inline uint32_t read_vp(struct geodefb_par *par, int reg)
28{ 236{
29 return readl(par->vid_regs + reg); 237 return readl(par->vid_regs + 8*reg);
30} 238}
31 239
32static inline void write_vp(struct geodefb_par *par, int reg, uint32_t val) 240static inline void write_vp(struct geodefb_par *par, int reg, uint32_t val)
33{ 241{
34 writel(val, par->vid_regs + reg); 242 writel(val, par->vid_regs + 8*reg);
35} 243}
36 244
37static inline uint32_t read_fp(struct geodefb_par *par, int reg) 245static inline uint32_t read_fp(struct geodefb_par *par, int reg)
38{ 246{
39 return readl(par->vid_regs + reg); 247 return readl(par->vid_regs + 8*reg + VP_FP_START);
40} 248}
41 249
42static inline void write_fp(struct geodefb_par *par, int reg, uint32_t val) 250static inline void write_fp(struct geodefb_par *par, int reg, uint32_t val)
43{ 251{
44 writel(val, par->vid_regs + reg); 252 writel(val, par->vid_regs + 8*reg + VP_FP_START);
45} 253}
46 254
47#endif 255#endif
diff --git a/drivers/video/geode/video_gx.c b/drivers/video/geode/video_gx.c
index e45d94143da0..1b98b7b4e853 100644
--- a/drivers/video/geode/video_gx.c
+++ b/drivers/video/geode/video_gx.c
@@ -193,16 +193,16 @@ gx_configure_tft(struct fb_info *info)
193 193
194 /* Turn off the panel */ 194 /* Turn off the panel */
195 195
196 fp = read_fp(par, GX_FP_PM); 196 fp = read_fp(par, FP_PM);
197 fp &= ~GX_FP_PM_P; 197 fp &= ~FP_PM_P;
198 write_fp(par, GX_FP_PM, fp); 198 write_fp(par, FP_PM, fp);
199 199
200 /* Set timing 1 */ 200 /* Set timing 1 */
201 201
202 fp = read_fp(par, GX_FP_PT1); 202 fp = read_fp(par, FP_PT1);
203 fp &= GX_FP_PT1_VSIZE_MASK; 203 fp &= FP_PT1_VSIZE_MASK;
204 fp |= info->var.yres << GX_FP_PT1_VSIZE_SHIFT; 204 fp |= info->var.yres << FP_PT1_VSIZE_SHIFT;
205 write_fp(par, GX_FP_PT1, fp); 205 write_fp(par, FP_PT1, fp);
206 206
207 /* Timing 2 */ 207 /* Timing 2 */
208 /* Set bits that are always on for TFT */ 208 /* Set bits that are always on for TFT */
@@ -212,27 +212,27 @@ gx_configure_tft(struct fb_info *info)
212 /* Configure sync polarity */ 212 /* Configure sync polarity */
213 213
214 if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT)) 214 if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
215 fp |= GX_FP_PT2_VSP; 215 fp |= FP_PT2_VSP;
216 216
217 if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT)) 217 if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
218 fp |= GX_FP_PT2_HSP; 218 fp |= FP_PT2_HSP;
219 219
220 write_fp(par, GX_FP_PT2, fp); 220 write_fp(par, FP_PT2, fp);
221 221
222 /* Set the dither control */ 222 /* Set the dither control */
223 write_fp(par, GX_FP_DFC, 0x70); 223 write_fp(par, FP_DFC, FP_DFC_NFI);
224 224
225 /* Enable the FP data and power (in case the BIOS didn't) */ 225 /* Enable the FP data and power (in case the BIOS didn't) */
226 226
227 fp = read_vp(par, GX_DCFG); 227 fp = read_vp(par, VP_DCFG);
228 fp |= GX_DCFG_FP_PWR_EN | GX_DCFG_FP_DATA_EN; 228 fp |= VP_DCFG_FP_PWR_EN | VP_DCFG_FP_DATA_EN;
229 write_vp(par, GX_DCFG, fp); 229 write_vp(par, VP_DCFG, fp);
230 230
231 /* Unblank the panel */ 231 /* Unblank the panel */
232 232
233 fp = read_fp(par, GX_FP_PM); 233 fp = read_fp(par, FP_PM);
234 fp |= GX_FP_PM_P; 234 fp |= FP_PM_P;
235 write_fp(par, GX_FP_PM, fp); 235 write_fp(par, FP_PM, fp);
236} 236}
237 237
238static void gx_configure_display(struct fb_info *info) 238static void gx_configure_display(struct fb_info *info)
@@ -241,55 +241,55 @@ static void gx_configure_display(struct fb_info *info)
241 u32 dcfg, misc; 241 u32 dcfg, misc;
242 242
243 /* Write the display configuration */ 243 /* Write the display configuration */
244 dcfg = read_vp(par, GX_DCFG); 244 dcfg = read_vp(par, VP_DCFG);
245 245
246 /* Disable hsync and vsync */ 246 /* Disable hsync and vsync */
247 dcfg &= ~(GX_DCFG_VSYNC_EN | GX_DCFG_HSYNC_EN); 247 dcfg &= ~(VP_DCFG_VSYNC_EN | VP_DCFG_HSYNC_EN);
248 write_vp(par, GX_DCFG, dcfg); 248 write_vp(par, VP_DCFG, dcfg);
249 249
250 /* Clear bits from existing mode. */ 250 /* Clear bits from existing mode. */
251 dcfg &= ~(GX_DCFG_CRT_SYNC_SKW_MASK 251 dcfg &= ~(VP_DCFG_CRT_SYNC_SKW
252 | GX_DCFG_CRT_HSYNC_POL | GX_DCFG_CRT_VSYNC_POL 252 | VP_DCFG_CRT_HSYNC_POL | VP_DCFG_CRT_VSYNC_POL
253 | GX_DCFG_VSYNC_EN | GX_DCFG_HSYNC_EN); 253 | VP_DCFG_VSYNC_EN | VP_DCFG_HSYNC_EN);
254 254
255 /* Set default sync skew. */ 255 /* Set default sync skew. */
256 dcfg |= GX_DCFG_CRT_SYNC_SKW_DFLT; 256 dcfg |= VP_DCFG_CRT_SYNC_SKW_DEFAULT;
257 257
258 /* Enable hsync and vsync. */ 258 /* Enable hsync and vsync. */
259 dcfg |= GX_DCFG_HSYNC_EN | GX_DCFG_VSYNC_EN; 259 dcfg |= VP_DCFG_HSYNC_EN | VP_DCFG_VSYNC_EN;
260 260
261 misc = read_vp(par, GX_MISC); 261 misc = read_vp(par, VP_MISC);
262 262
263 /* Disable gamma correction */ 263 /* Disable gamma correction */
264 misc |= GX_MISC_GAM_EN; 264 misc |= VP_MISC_GAM_EN;
265 265
266 if (par->enable_crt) { 266 if (par->enable_crt) {
267 267
268 /* Power up the CRT DACs */ 268 /* Power up the CRT DACs */
269 misc &= ~(GX_MISC_A_PWRDN | GX_MISC_DAC_PWRDN); 269 misc &= ~(VP_MISC_APWRDN | VP_MISC_DACPWRDN);
270 write_vp(par, GX_MISC, misc); 270 write_vp(par, VP_MISC, misc);
271 271
272 /* Only change the sync polarities if we are running 272 /* Only change the sync polarities if we are running
273 * in CRT mode. The FP polarities will be handled in 273 * in CRT mode. The FP polarities will be handled in
274 * gxfb_configure_tft */ 274 * gxfb_configure_tft */
275 if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT)) 275 if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
276 dcfg |= GX_DCFG_CRT_HSYNC_POL; 276 dcfg |= VP_DCFG_CRT_HSYNC_POL;
277 if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT)) 277 if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
278 dcfg |= GX_DCFG_CRT_VSYNC_POL; 278 dcfg |= VP_DCFG_CRT_VSYNC_POL;
279 } else { 279 } else {
280 /* Power down the CRT DACs if in FP mode */ 280 /* Power down the CRT DACs if in FP mode */
281 misc |= (GX_MISC_A_PWRDN | GX_MISC_DAC_PWRDN); 281 misc |= (VP_MISC_APWRDN | VP_MISC_DACPWRDN);
282 write_vp(par, GX_MISC, misc); 282 write_vp(par, VP_MISC, misc);
283 } 283 }
284 284
285 /* Enable the display logic */ 285 /* Enable the display logic */
286 /* Set up the DACS to blank normally */ 286 /* Set up the DACS to blank normally */
287 287
288 dcfg |= GX_DCFG_CRT_EN | GX_DCFG_DAC_BL_EN; 288 dcfg |= VP_DCFG_CRT_EN | VP_DCFG_DAC_BL_EN;
289 289
290 /* Enable the external DAC VREF? */ 290 /* Enable the external DAC VREF? */
291 291
292 write_vp(par, GX_DCFG, dcfg); 292 write_vp(par, VP_DCFG, dcfg);
293 293
294 /* Set up the flat panel (if it is enabled) */ 294 /* Set up the flat panel (if it is enabled) */
295 295
@@ -323,26 +323,26 @@ static int gx_blank_display(struct fb_info *info, int blank_mode)
323 default: 323 default:
324 return -EINVAL; 324 return -EINVAL;
325 } 325 }
326 dcfg = read_vp(par, GX_DCFG); 326 dcfg = read_vp(par, VP_DCFG);
327 dcfg &= ~(GX_DCFG_DAC_BL_EN 327 dcfg &= ~(VP_DCFG_DAC_BL_EN
328 | GX_DCFG_HSYNC_EN | GX_DCFG_VSYNC_EN); 328 | VP_DCFG_HSYNC_EN | VP_DCFG_VSYNC_EN);
329 if (!blank) 329 if (!blank)
330 dcfg |= GX_DCFG_DAC_BL_EN; 330 dcfg |= VP_DCFG_DAC_BL_EN;
331 if (hsync) 331 if (hsync)
332 dcfg |= GX_DCFG_HSYNC_EN; 332 dcfg |= VP_DCFG_HSYNC_EN;
333 if (vsync) 333 if (vsync)
334 dcfg |= GX_DCFG_VSYNC_EN; 334 dcfg |= VP_DCFG_VSYNC_EN;
335 write_vp(par, GX_DCFG, dcfg); 335 write_vp(par, VP_DCFG, dcfg);
336 336
337 /* Power on/off flat panel. */ 337 /* Power on/off flat panel. */
338 338
339 if (par->enable_crt == 0) { 339 if (par->enable_crt == 0) {
340 fp_pm = read_fp(par, GX_FP_PM); 340 fp_pm = read_fp(par, FP_PM);
341 if (blank_mode == FB_BLANK_POWERDOWN) 341 if (blank_mode == FB_BLANK_POWERDOWN)
342 fp_pm &= ~GX_FP_PM_P; 342 fp_pm &= ~FP_PM_P;
343 else 343 else
344 fp_pm |= GX_FP_PM_P; 344 fp_pm |= FP_PM_P;
345 write_fp(par, GX_FP_PM, fp_pm); 345 write_fp(par, FP_PM, fp_pm);
346 } 346 }
347 347
348 return 0; 348 return 0;
diff --git a/drivers/video/geode/video_gx.h b/drivers/video/geode/video_gx.h
index d21bca020594..5457bd04ec74 100644
--- a/drivers/video/geode/video_gx.h
+++ b/drivers/video/geode/video_gx.h
@@ -17,45 +17,6 @@ extern struct geode_vid_ops gx_vid_ops;
17#define GX_VP_PAD_SELECT_MASK 0x3FFFFFFF 17#define GX_VP_PAD_SELECT_MASK 0x3FFFFFFF
18#define GX_VP_PAD_SELECT_TFT 0x1FFFFFFF 18#define GX_VP_PAD_SELECT_TFT 0x1FFFFFFF
19 19
20/* Geode GX video processor registers */
21
22#define GX_DCFG 0x0008
23# define GX_DCFG_CRT_EN 0x00000001
24# define GX_DCFG_HSYNC_EN 0x00000002
25# define GX_DCFG_VSYNC_EN 0x00000004
26# define GX_DCFG_DAC_BL_EN 0x00000008
27# define GX_DCFG_FP_PWR_EN 0x00000040
28# define GX_DCFG_FP_DATA_EN 0x00000080
29# define GX_DCFG_CRT_HSYNC_POL 0x00000100
30# define GX_DCFG_CRT_VSYNC_POL 0x00000200
31# define GX_DCFG_CRT_SYNC_SKW_MASK 0x0001C000
32# define GX_DCFG_CRT_SYNC_SKW_DFLT 0x00010000
33# define GX_DCFG_VG_CK 0x00100000
34# define GX_DCFG_GV_GAM 0x00200000
35# define GX_DCFG_DAC_VREF 0x04000000
36
37/* Geode GX MISC video configuration */
38
39#define GX_MISC 0x50
40#define GX_MISC_GAM_EN 0x00000001
41#define GX_MISC_DAC_PWRDN 0x00000400
42#define GX_MISC_A_PWRDN 0x00000800
43
44/* Geode GX flat panel display control registers */
45
46#define GX_FP_PT1 0x0400
47#define GX_FP_PT1_VSIZE_MASK 0x7FF0000
48#define GX_FP_PT1_VSIZE_SHIFT 16
49
50#define GX_FP_PT2 0x408
51#define GX_FP_PT2_VSP (1 << 23)
52#define GX_FP_PT2_HSP (1 << 22)
53
54#define GX_FP_PM 0x410
55# define GX_FP_PM_P 0x01000000
56
57#define GX_FP_DFC 0x418
58
59/* Geode GX clock control MSRs */ 20/* Geode GX clock control MSRs */
60 21
61# define MSR_GLCP_SYS_RSTPLL_DOTPREDIV2 (0x0000000000000002ull) 22# define MSR_GLCP_SYS_RSTPLL_DOTPREDIV2 (0x0000000000000002ull)
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-31 22:26:45 -0400