diff options
Diffstat (limited to 'drivers/video/geode/video_gx.c')
-rw-r--r-- | drivers/video/geode/video_gx.c | 92 |
1 files changed, 46 insertions, 46 deletions
diff --git a/drivers/video/geode/video_gx.c b/drivers/video/geode/video_gx.c index e45d94143da0..1b98b7b4e853 100644 --- a/drivers/video/geode/video_gx.c +++ b/drivers/video/geode/video_gx.c | |||
@@ -193,16 +193,16 @@ gx_configure_tft(struct fb_info *info) | |||
193 | 193 | ||
194 | /* Turn off the panel */ | 194 | /* Turn off the panel */ |
195 | 195 | ||
196 | fp = read_fp(par, GX_FP_PM); | 196 | fp = read_fp(par, FP_PM); |
197 | fp &= ~GX_FP_PM_P; | 197 | fp &= ~FP_PM_P; |
198 | write_fp(par, GX_FP_PM, fp); | 198 | write_fp(par, FP_PM, fp); |
199 | 199 | ||
200 | /* Set timing 1 */ | 200 | /* Set timing 1 */ |
201 | 201 | ||
202 | fp = read_fp(par, GX_FP_PT1); | 202 | fp = read_fp(par, FP_PT1); |
203 | fp &= GX_FP_PT1_VSIZE_MASK; | 203 | fp &= FP_PT1_VSIZE_MASK; |
204 | fp |= info->var.yres << GX_FP_PT1_VSIZE_SHIFT; | 204 | fp |= info->var.yres << FP_PT1_VSIZE_SHIFT; |
205 | write_fp(par, GX_FP_PT1, fp); | 205 | write_fp(par, FP_PT1, fp); |
206 | 206 | ||
207 | /* Timing 2 */ | 207 | /* Timing 2 */ |
208 | /* Set bits that are always on for TFT */ | 208 | /* Set bits that are always on for TFT */ |
@@ -212,27 +212,27 @@ gx_configure_tft(struct fb_info *info) | |||
212 | /* Configure sync polarity */ | 212 | /* Configure sync polarity */ |
213 | 213 | ||
214 | if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT)) | 214 | if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT)) |
215 | fp |= GX_FP_PT2_VSP; | 215 | fp |= FP_PT2_VSP; |
216 | 216 | ||
217 | if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT)) | 217 | if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT)) |
218 | fp |= GX_FP_PT2_HSP; | 218 | fp |= FP_PT2_HSP; |
219 | 219 | ||
220 | write_fp(par, GX_FP_PT2, fp); | 220 | write_fp(par, FP_PT2, fp); |
221 | 221 | ||
222 | /* Set the dither control */ | 222 | /* Set the dither control */ |
223 | write_fp(par, GX_FP_DFC, 0x70); | 223 | write_fp(par, FP_DFC, FP_DFC_NFI); |
224 | 224 | ||
225 | /* Enable the FP data and power (in case the BIOS didn't) */ | 225 | /* Enable the FP data and power (in case the BIOS didn't) */ |
226 | 226 | ||
227 | fp = read_vp(par, GX_DCFG); | 227 | fp = read_vp(par, VP_DCFG); |
228 | fp |= GX_DCFG_FP_PWR_EN | GX_DCFG_FP_DATA_EN; | 228 | fp |= VP_DCFG_FP_PWR_EN | VP_DCFG_FP_DATA_EN; |
229 | write_vp(par, GX_DCFG, fp); | 229 | write_vp(par, VP_DCFG, fp); |
230 | 230 | ||
231 | /* Unblank the panel */ | 231 | /* Unblank the panel */ |
232 | 232 | ||
233 | fp = read_fp(par, GX_FP_PM); | 233 | fp = read_fp(par, FP_PM); |
234 | fp |= GX_FP_PM_P; | 234 | fp |= FP_PM_P; |
235 | write_fp(par, GX_FP_PM, fp); | 235 | write_fp(par, FP_PM, fp); |
236 | } | 236 | } |
237 | 237 | ||
238 | static void gx_configure_display(struct fb_info *info) | 238 | static void gx_configure_display(struct fb_info *info) |
@@ -241,55 +241,55 @@ static void gx_configure_display(struct fb_info *info) | |||
241 | u32 dcfg, misc; | 241 | u32 dcfg, misc; |
242 | 242 | ||
243 | /* Write the display configuration */ | 243 | /* Write the display configuration */ |
244 | dcfg = read_vp(par, GX_DCFG); | 244 | dcfg = read_vp(par, VP_DCFG); |
245 | 245 | ||
246 | /* Disable hsync and vsync */ | 246 | /* Disable hsync and vsync */ |
247 | dcfg &= ~(GX_DCFG_VSYNC_EN | GX_DCFG_HSYNC_EN); | 247 | dcfg &= ~(VP_DCFG_VSYNC_EN | VP_DCFG_HSYNC_EN); |
248 | write_vp(par, GX_DCFG, dcfg); | 248 | write_vp(par, VP_DCFG, dcfg); |
249 | 249 | ||
250 | /* Clear bits from existing mode. */ | 250 | /* Clear bits from existing mode. */ |
251 | dcfg &= ~(GX_DCFG_CRT_SYNC_SKW_MASK | 251 | dcfg &= ~(VP_DCFG_CRT_SYNC_SKW |
252 | | GX_DCFG_CRT_HSYNC_POL | GX_DCFG_CRT_VSYNC_POL | 252 | | VP_DCFG_CRT_HSYNC_POL | VP_DCFG_CRT_VSYNC_POL |
253 | | GX_DCFG_VSYNC_EN | GX_DCFG_HSYNC_EN); | 253 | | VP_DCFG_VSYNC_EN | VP_DCFG_HSYNC_EN); |
254 | 254 | ||
255 | /* Set default sync skew. */ | 255 | /* Set default sync skew. */ |
256 | dcfg |= GX_DCFG_CRT_SYNC_SKW_DFLT; | 256 | dcfg |= VP_DCFG_CRT_SYNC_SKW_DEFAULT; |
257 | 257 | ||
258 | /* Enable hsync and vsync. */ | 258 | /* Enable hsync and vsync. */ |
259 | dcfg |= GX_DCFG_HSYNC_EN | GX_DCFG_VSYNC_EN; | 259 | dcfg |= VP_DCFG_HSYNC_EN | VP_DCFG_VSYNC_EN; |
260 | 260 | ||
261 | misc = read_vp(par, GX_MISC); | 261 | misc = read_vp(par, VP_MISC); |
262 | 262 | ||
263 | /* Disable gamma correction */ | 263 | /* Disable gamma correction */ |
264 | misc |= GX_MISC_GAM_EN; | 264 | misc |= VP_MISC_GAM_EN; |
265 | 265 | ||
266 | if (par->enable_crt) { | 266 | if (par->enable_crt) { |
267 | 267 | ||
268 | /* Power up the CRT DACs */ | 268 | /* Power up the CRT DACs */ |
269 | misc &= ~(GX_MISC_A_PWRDN | GX_MISC_DAC_PWRDN); | 269 | misc &= ~(VP_MISC_APWRDN | VP_MISC_DACPWRDN); |
270 | write_vp(par, GX_MISC, misc); | 270 | write_vp(par, VP_MISC, misc); |
271 | 271 | ||
272 | /* Only change the sync polarities if we are running | 272 | /* Only change the sync polarities if we are running |
273 | * in CRT mode. The FP polarities will be handled in | 273 | * in CRT mode. The FP polarities will be handled in |
274 | * gxfb_configure_tft */ | 274 | * gxfb_configure_tft */ |
275 | if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT)) | 275 | if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT)) |
276 | dcfg |= GX_DCFG_CRT_HSYNC_POL; | 276 | dcfg |= VP_DCFG_CRT_HSYNC_POL; |
277 | if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT)) | 277 | if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT)) |
278 | dcfg |= GX_DCFG_CRT_VSYNC_POL; | 278 | dcfg |= VP_DCFG_CRT_VSYNC_POL; |
279 | } else { | 279 | } else { |
280 | /* Power down the CRT DACs if in FP mode */ | 280 | /* Power down the CRT DACs if in FP mode */ |
281 | misc |= (GX_MISC_A_PWRDN | GX_MISC_DAC_PWRDN); | 281 | misc |= (VP_MISC_APWRDN | VP_MISC_DACPWRDN); |
282 | write_vp(par, GX_MISC, misc); | 282 | write_vp(par, VP_MISC, misc); |
283 | } | 283 | } |
284 | 284 | ||
285 | /* Enable the display logic */ | 285 | /* Enable the display logic */ |
286 | /* Set up the DACS to blank normally */ | 286 | /* Set up the DACS to blank normally */ |
287 | 287 | ||
288 | dcfg |= GX_DCFG_CRT_EN | GX_DCFG_DAC_BL_EN; | 288 | dcfg |= VP_DCFG_CRT_EN | VP_DCFG_DAC_BL_EN; |
289 | 289 | ||
290 | /* Enable the external DAC VREF? */ | 290 | /* Enable the external DAC VREF? */ |
291 | 291 | ||
292 | write_vp(par, GX_DCFG, dcfg); | 292 | write_vp(par, VP_DCFG, dcfg); |
293 | 293 | ||
294 | /* Set up the flat panel (if it is enabled) */ | 294 | /* Set up the flat panel (if it is enabled) */ |
295 | 295 | ||
@@ -323,26 +323,26 @@ static int gx_blank_display(struct fb_info *info, int blank_mode) | |||
323 | default: | 323 | default: |
324 | return -EINVAL; | 324 | return -EINVAL; |
325 | } | 325 | } |
326 | dcfg = read_vp(par, GX_DCFG); | 326 | dcfg = read_vp(par, VP_DCFG); |
327 | dcfg &= ~(GX_DCFG_DAC_BL_EN | 327 | dcfg &= ~(VP_DCFG_DAC_BL_EN |
328 | | GX_DCFG_HSYNC_EN | GX_DCFG_VSYNC_EN); | 328 | | VP_DCFG_HSYNC_EN | VP_DCFG_VSYNC_EN); |
329 | if (!blank) | 329 | if (!blank) |
330 | dcfg |= GX_DCFG_DAC_BL_EN; | 330 | dcfg |= VP_DCFG_DAC_BL_EN; |
331 | if (hsync) | 331 | if (hsync) |
332 | dcfg |= GX_DCFG_HSYNC_EN; | 332 | dcfg |= VP_DCFG_HSYNC_EN; |
333 | if (vsync) | 333 | if (vsync) |
334 | dcfg |= GX_DCFG_VSYNC_EN; | 334 | dcfg |= VP_DCFG_VSYNC_EN; |
335 | write_vp(par, GX_DCFG, dcfg); | 335 | write_vp(par, VP_DCFG, dcfg); |
336 | 336 | ||
337 | /* Power on/off flat panel. */ | 337 | /* Power on/off flat panel. */ |
338 | 338 | ||
339 | if (par->enable_crt == 0) { | 339 | if (par->enable_crt == 0) { |
340 | fp_pm = read_fp(par, GX_FP_PM); | 340 | fp_pm = read_fp(par, FP_PM); |
341 | if (blank_mode == FB_BLANK_POWERDOWN) | 341 | if (blank_mode == FB_BLANK_POWERDOWN) |
342 | fp_pm &= ~GX_FP_PM_P; | 342 | fp_pm &= ~FP_PM_P; |
343 | else | 343 | else |
344 | fp_pm |= GX_FP_PM_P; | 344 | fp_pm |= FP_PM_P; |
345 | write_fp(par, GX_FP_PM, fp_pm); | 345 | write_fp(par, FP_PM, fp_pm); |
346 | } | 346 | } |
347 | 347 | ||
348 | return 0; | 348 | return 0; |