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-rw-r--r--drivers/spi/spi-rspi.c842
1 files changed, 560 insertions, 282 deletions
diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c
index 28987d9fcfe5..1fb0ad213324 100644
--- a/drivers/spi/spi-rspi.c
+++ b/drivers/spi/spi-rspi.c
@@ -1,7 +1,8 @@
1/* 1/*
2 * SH RSPI driver 2 * SH RSPI driver
3 * 3 *
4 * Copyright (C) 2012 Renesas Solutions Corp. 4 * Copyright (C) 2012, 2013 Renesas Solutions Corp.
5 * Copyright (C) 2014 Glider bvba
5 * 6 *
6 * Based on spi-sh.c: 7 * Based on spi-sh.c:
7 * Copyright (C) 2011 Renesas Solutions Corp. 8 * Copyright (C) 2011 Renesas Solutions Corp.
@@ -25,14 +26,14 @@
25#include <linux/kernel.h> 26#include <linux/kernel.h>
26#include <linux/sched.h> 27#include <linux/sched.h>
27#include <linux/errno.h> 28#include <linux/errno.h>
28#include <linux/list.h>
29#include <linux/workqueue.h>
30#include <linux/interrupt.h> 29#include <linux/interrupt.h>
31#include <linux/platform_device.h> 30#include <linux/platform_device.h>
32#include <linux/io.h> 31#include <linux/io.h>
33#include <linux/clk.h> 32#include <linux/clk.h>
34#include <linux/dmaengine.h> 33#include <linux/dmaengine.h>
35#include <linux/dma-mapping.h> 34#include <linux/dma-mapping.h>
35#include <linux/of_device.h>
36#include <linux/pm_runtime.h>
36#include <linux/sh_dma.h> 37#include <linux/sh_dma.h>
37#include <linux/spi/spi.h> 38#include <linux/spi/spi.h>
38#include <linux/spi/rspi.h> 39#include <linux/spi/rspi.h>
@@ -49,7 +50,7 @@
49#define RSPI_SPCKD 0x0c /* Clock Delay Register */ 50#define RSPI_SPCKD 0x0c /* Clock Delay Register */
50#define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */ 51#define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */
51#define RSPI_SPND 0x0e /* Next-Access Delay Register */ 52#define RSPI_SPND 0x0e /* Next-Access Delay Register */
52#define RSPI_SPCR2 0x0f /* Control Register 2 */ 53#define RSPI_SPCR2 0x0f /* Control Register 2 (SH only) */
53#define RSPI_SPCMD0 0x10 /* Command Register 0 */ 54#define RSPI_SPCMD0 0x10 /* Command Register 0 */
54#define RSPI_SPCMD1 0x12 /* Command Register 1 */ 55#define RSPI_SPCMD1 0x12 /* Command Register 1 */
55#define RSPI_SPCMD2 0x14 /* Command Register 2 */ 56#define RSPI_SPCMD2 0x14 /* Command Register 2 */
@@ -58,16 +59,23 @@
58#define RSPI_SPCMD5 0x1a /* Command Register 5 */ 59#define RSPI_SPCMD5 0x1a /* Command Register 5 */
59#define RSPI_SPCMD6 0x1c /* Command Register 6 */ 60#define RSPI_SPCMD6 0x1c /* Command Register 6 */
60#define RSPI_SPCMD7 0x1e /* Command Register 7 */ 61#define RSPI_SPCMD7 0x1e /* Command Register 7 */
62#define RSPI_SPCMD(i) (RSPI_SPCMD0 + (i) * 2)
63#define RSPI_NUM_SPCMD 8
64#define RSPI_RZ_NUM_SPCMD 4
65#define QSPI_NUM_SPCMD 4
66
67/* RSPI on RZ only */
61#define RSPI_SPBFCR 0x20 /* Buffer Control Register */ 68#define RSPI_SPBFCR 0x20 /* Buffer Control Register */
62#define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */ 69#define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */
63 70
64/*qspi only */ 71/* QSPI only */
65#define QSPI_SPBFCR 0x18 /* Buffer Control Register */ 72#define QSPI_SPBFCR 0x18 /* Buffer Control Register */
66#define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */ 73#define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */
67#define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */ 74#define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */
68#define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */ 75#define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */
69#define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */ 76#define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */
70#define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */ 77#define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */
78#define QSPI_SPBMUL(i) (QSPI_SPBMUL0 + (i) * 4)
71 79
72/* SPCR - Control Register */ 80/* SPCR - Control Register */
73#define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */ 81#define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */
@@ -104,7 +112,7 @@
104#define SPSR_PERF 0x08 /* Parity Error Flag */ 112#define SPSR_PERF 0x08 /* Parity Error Flag */
105#define SPSR_MODF 0x04 /* Mode Fault Error Flag */ 113#define SPSR_MODF 0x04 /* Mode Fault Error Flag */
106#define SPSR_IDLNF 0x02 /* RSPI Idle Flag */ 114#define SPSR_IDLNF 0x02 /* RSPI Idle Flag */
107#define SPSR_OVRF 0x01 /* Overrun Error Flag */ 115#define SPSR_OVRF 0x01 /* Overrun Error Flag (RSPI only) */
108 116
109/* SPSCR - Sequence Control Register */ 117/* SPSCR - Sequence Control Register */
110#define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */ 118#define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */
@@ -121,13 +129,13 @@
121#define SPDCR_SPLWORD SPDCR_SPLW1 129#define SPDCR_SPLWORD SPDCR_SPLW1
122#define SPDCR_SPLBYTE SPDCR_SPLW0 130#define SPDCR_SPLBYTE SPDCR_SPLW0
123#define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */ 131#define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */
124#define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select */ 132#define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select (SH) */
125#define SPDCR_SLSEL1 0x08 133#define SPDCR_SLSEL1 0x08
126#define SPDCR_SLSEL0 0x04 134#define SPDCR_SLSEL0 0x04
127#define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select */ 135#define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select (SH) */
128#define SPDCR_SPFC1 0x02 136#define SPDCR_SPFC1 0x02
129#define SPDCR_SPFC0 0x01 137#define SPDCR_SPFC0 0x01
130#define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) */ 138#define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) (SH) */
131 139
132/* SPCKD - Clock Delay Register */ 140/* SPCKD - Clock Delay Register */
133#define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */ 141#define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */
@@ -151,7 +159,7 @@
151#define SPCMD_LSBF 0x1000 /* LSB First */ 159#define SPCMD_LSBF 0x1000 /* LSB First */
152#define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */ 160#define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */
153#define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK) 161#define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK)
154#define SPCMD_SPB_8BIT 0x0000 /* qspi only */ 162#define SPCMD_SPB_8BIT 0x0000 /* QSPI only */
155#define SPCMD_SPB_16BIT 0x0100 163#define SPCMD_SPB_16BIT 0x0100
156#define SPCMD_SPB_20BIT 0x0000 164#define SPCMD_SPB_20BIT 0x0000
157#define SPCMD_SPB_24BIT 0x0100 165#define SPCMD_SPB_24BIT 0x0100
@@ -170,8 +178,8 @@
170#define SPCMD_CPHA 0x0001 /* Clock Phase Setting */ 178#define SPCMD_CPHA 0x0001 /* Clock Phase Setting */
171 179
172/* SPBFCR - Buffer Control Register */ 180/* SPBFCR - Buffer Control Register */
173#define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset (qspi only) */ 181#define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset */
174#define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset (qspi only) */ 182#define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset */
175#define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */ 183#define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */
176#define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */ 184#define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */
177 185
@@ -181,22 +189,21 @@ struct rspi_data {
181 void __iomem *addr; 189 void __iomem *addr;
182 u32 max_speed_hz; 190 u32 max_speed_hz;
183 struct spi_master *master; 191 struct spi_master *master;
184 struct list_head queue;
185 struct work_struct ws;
186 wait_queue_head_t wait; 192 wait_queue_head_t wait;
187 spinlock_t lock;
188 struct clk *clk; 193 struct clk *clk;
189 u8 spsr;
190 u16 spcmd; 194 u16 spcmd;
195 u8 spsr;
196 u8 sppcr;
197 int rx_irq, tx_irq;
191 const struct spi_ops *ops; 198 const struct spi_ops *ops;
192 199
193 /* for dmaengine */ 200 /* for dmaengine */
194 struct dma_chan *chan_tx; 201 struct dma_chan *chan_tx;
195 struct dma_chan *chan_rx; 202 struct dma_chan *chan_rx;
196 int irq;
197 203
198 unsigned dma_width_16bit:1; 204 unsigned dma_width_16bit:1;
199 unsigned dma_callbacked:1; 205 unsigned dma_callbacked:1;
206 unsigned byte_access:1;
200}; 207};
201 208
202static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset) 209static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset)
@@ -224,34 +231,47 @@ static u16 rspi_read16(const struct rspi_data *rspi, u16 offset)
224 return ioread16(rspi->addr + offset); 231 return ioread16(rspi->addr + offset);
225} 232}
226 233
234static void rspi_write_data(const struct rspi_data *rspi, u16 data)
235{
236 if (rspi->byte_access)
237 rspi_write8(rspi, data, RSPI_SPDR);
238 else /* 16 bit */
239 rspi_write16(rspi, data, RSPI_SPDR);
240}
241
242static u16 rspi_read_data(const struct rspi_data *rspi)
243{
244 if (rspi->byte_access)
245 return rspi_read8(rspi, RSPI_SPDR);
246 else /* 16 bit */
247 return rspi_read16(rspi, RSPI_SPDR);
248}
249
227/* optional functions */ 250/* optional functions */
228struct spi_ops { 251struct spi_ops {
229 int (*set_config_register)(const struct rspi_data *rspi, 252 int (*set_config_register)(struct rspi_data *rspi, int access_size);
230 int access_size); 253 int (*transfer_one)(struct spi_master *master, struct spi_device *spi,
231 int (*send_pio)(struct rspi_data *rspi, struct spi_message *mesg, 254 struct spi_transfer *xfer);
232 struct spi_transfer *t); 255 u16 mode_bits;
233 int (*receive_pio)(struct rspi_data *rspi, struct spi_message *mesg,
234 struct spi_transfer *t);
235
236}; 256};
237 257
238/* 258/*
239 * functions for RSPI 259 * functions for RSPI on legacy SH
240 */ 260 */
241static int rspi_set_config_register(const struct rspi_data *rspi, 261static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
242 int access_size)
243{ 262{
244 int spbr; 263 int spbr;
245 264
246 /* Sets output mode(CMOS) and MOSI signal(from previous transfer) */ 265 /* Sets output mode, MOSI signal, and (optionally) loopback */
247 rspi_write8(rspi, 0x00, RSPI_SPPCR); 266 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
248 267
249 /* Sets transfer bit rate */ 268 /* Sets transfer bit rate */
250 spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1; 269 spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1;
251 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); 270 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
252 271
253 /* Sets number of frames to be used: 1 frame */ 272 /* Disable dummy transmission, set 16-bit word access, 1 frame */
254 rspi_write8(rspi, 0x00, RSPI_SPDCR); 273 rspi_write8(rspi, 0, RSPI_SPDCR);
274 rspi->byte_access = 0;
255 275
256 /* Sets RSPCK, SSL, next-access delay value */ 276 /* Sets RSPCK, SSL, next-access delay value */
257 rspi_write8(rspi, 0x00, RSPI_SPCKD); 277 rspi_write8(rspi, 0x00, RSPI_SPCKD);
@@ -262,8 +282,41 @@ static int rspi_set_config_register(const struct rspi_data *rspi,
262 rspi_write8(rspi, 0x00, RSPI_SPCR2); 282 rspi_write8(rspi, 0x00, RSPI_SPCR2);
263 283
264 /* Sets SPCMD */ 284 /* Sets SPCMD */
265 rspi_write16(rspi, SPCMD_SPB_8_TO_16(access_size) | rspi->spcmd, 285 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
266 RSPI_SPCMD0); 286 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
287
288 /* Sets RSPI mode */
289 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
290
291 return 0;
292}
293
294/*
295 * functions for RSPI on RZ
296 */
297static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)
298{
299 int spbr;
300
301 /* Sets output mode, MOSI signal, and (optionally) loopback */
302 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
303
304 /* Sets transfer bit rate */
305 spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1;
306 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
307
308 /* Disable dummy transmission, set byte access */
309 rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR);
310 rspi->byte_access = 1;
311
312 /* Sets RSPCK, SSL, next-access delay value */
313 rspi_write8(rspi, 0x00, RSPI_SPCKD);
314 rspi_write8(rspi, 0x00, RSPI_SSLND);
315 rspi_write8(rspi, 0x00, RSPI_SPND);
316
317 /* Sets SPCMD */
318 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
319 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
267 320
268 /* Sets RSPI mode */ 321 /* Sets RSPI mode */
269 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); 322 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
@@ -274,21 +327,20 @@ static int rspi_set_config_register(const struct rspi_data *rspi,
274/* 327/*
275 * functions for QSPI 328 * functions for QSPI
276 */ 329 */
277static int qspi_set_config_register(const struct rspi_data *rspi, 330static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
278 int access_size)
279{ 331{
280 u16 spcmd;
281 int spbr; 332 int spbr;
282 333
283 /* Sets output mode(CMOS) and MOSI signal(from previous transfer) */ 334 /* Sets output mode, MOSI signal, and (optionally) loopback */
284 rspi_write8(rspi, 0x00, RSPI_SPPCR); 335 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
285 336
286 /* Sets transfer bit rate */ 337 /* Sets transfer bit rate */
287 spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz); 338 spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz);
288 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); 339 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
289 340
290 /* Sets number of frames to be used: 1 frame */ 341 /* Disable dummy transmission, set byte access */
291 rspi_write8(rspi, 0x00, RSPI_SPDCR); 342 rspi_write8(rspi, 0, RSPI_SPDCR);
343 rspi->byte_access = 1;
292 344
293 /* Sets RSPCK, SSL, next-access delay value */ 345 /* Sets RSPCK, SSL, next-access delay value */
294 rspi_write8(rspi, 0x00, RSPI_SPCKD); 346 rspi_write8(rspi, 0x00, RSPI_SPCKD);
@@ -297,13 +349,13 @@ static int qspi_set_config_register(const struct rspi_data *rspi,
297 349
298 /* Data Length Setting */ 350 /* Data Length Setting */
299 if (access_size == 8) 351 if (access_size == 8)
300 spcmd = SPCMD_SPB_8BIT; 352 rspi->spcmd |= SPCMD_SPB_8BIT;
301 else if (access_size == 16) 353 else if (access_size == 16)
302 spcmd = SPCMD_SPB_16BIT; 354 rspi->spcmd |= SPCMD_SPB_16BIT;
303 else 355 else
304 spcmd = SPCMD_SPB_32BIT; 356 rspi->spcmd |= SPCMD_SPB_32BIT;
305 357
306 spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | rspi->spcmd | SPCMD_SPNDEN; 358 rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN;
307 359
308 /* Resets transfer data length */ 360 /* Resets transfer data length */
309 rspi_write32(rspi, 0, QSPI_SPBMUL0); 361 rspi_write32(rspi, 0, QSPI_SPBMUL0);
@@ -314,9 +366,9 @@ static int qspi_set_config_register(const struct rspi_data *rspi,
314 rspi_write8(rspi, 0x00, QSPI_SPBFCR); 366 rspi_write8(rspi, 0x00, QSPI_SPBFCR);
315 367
316 /* Sets SPCMD */ 368 /* Sets SPCMD */
317 rspi_write16(rspi, spcmd, RSPI_SPCMD0); 369 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
318 370
319 /* Enables SPI function in a master mode */ 371 /* Enables SPI function in master mode */
320 rspi_write8(rspi, SPCR_SPE | SPCR_MSTR, RSPI_SPCR); 372 rspi_write8(rspi, SPCR_SPE | SPCR_MSTR, RSPI_SPCR);
321 373
322 return 0; 374 return 0;
@@ -340,6 +392,9 @@ static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
340 int ret; 392 int ret;
341 393
342 rspi->spsr = rspi_read8(rspi, RSPI_SPSR); 394 rspi->spsr = rspi_read8(rspi, RSPI_SPSR);
395 if (rspi->spsr & wait_mask)
396 return 0;
397
343 rspi_enable_irq(rspi, enable_bit); 398 rspi_enable_irq(rspi, enable_bit);
344 ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ); 399 ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ);
345 if (ret == 0 && !(rspi->spsr & wait_mask)) 400 if (ret == 0 && !(rspi->spsr & wait_mask))
@@ -348,78 +403,39 @@ static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
348 return 0; 403 return 0;
349} 404}
350 405
351static void rspi_assert_ssl(const struct rspi_data *rspi) 406static int rspi_data_out(struct rspi_data *rspi, u8 data)
352{
353 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
354}
355
356static void rspi_negate_ssl(const struct rspi_data *rspi)
357{ 407{
358 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR); 408 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
409 dev_err(&rspi->master->dev, "transmit timeout\n");
410 return -ETIMEDOUT;
411 }
412 rspi_write_data(rspi, data);
413 return 0;
359} 414}
360 415
361static int rspi_send_pio(struct rspi_data *rspi, struct spi_message *mesg, 416static int rspi_data_in(struct rspi_data *rspi)
362 struct spi_transfer *t)
363{ 417{
364 int remain = t->len; 418 u8 data;
365 const u8 *data = t->tx_buf;
366 while (remain > 0) {
367 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD,
368 RSPI_SPCR);
369
370 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
371 dev_err(&rspi->master->dev,
372 "%s: tx empty timeout\n", __func__);
373 return -ETIMEDOUT;
374 }
375 419
376 rspi_write16(rspi, *data, RSPI_SPDR); 420 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) {
377 data++; 421 dev_err(&rspi->master->dev, "receive timeout\n");
378 remain--; 422 return -ETIMEDOUT;
379 } 423 }
380 424 data = rspi_read_data(rspi);
381 /* Waiting for the last transmission */ 425 return data;
382 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
383
384 return 0;
385} 426}
386 427
387static int qspi_send_pio(struct rspi_data *rspi, struct spi_message *mesg, 428static int rspi_data_out_in(struct rspi_data *rspi, u8 data)
388 struct spi_transfer *t)
389{ 429{
390 int remain = t->len; 430 int ret;
391 const u8 *data = t->tx_buf;
392
393 rspi_write8(rspi, SPBFCR_TXRST, QSPI_SPBFCR);
394 rspi_write8(rspi, 0x00, QSPI_SPBFCR);
395
396 while (remain > 0) {
397
398 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
399 dev_err(&rspi->master->dev,
400 "%s: tx empty timeout\n", __func__);
401 return -ETIMEDOUT;
402 }
403 rspi_write8(rspi, *data++, RSPI_SPDR);
404
405 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) {
406 dev_err(&rspi->master->dev,
407 "%s: receive timeout\n", __func__);
408 return -ETIMEDOUT;
409 }
410 rspi_read8(rspi, RSPI_SPDR);
411
412 remain--;
413 }
414 431
415 /* Waiting for the last transmission */ 432 ret = rspi_data_out(rspi, data);
416 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); 433 if (ret < 0)
434 return ret;
417 435
418 return 0; 436 return rspi_data_in(rspi);
419} 437}
420 438
421#define send_pio(spi, mesg, t) spi->ops->send_pio(spi, mesg, t)
422
423static void rspi_dma_complete(void *arg) 439static void rspi_dma_complete(void *arg)
424{ 440{
425 struct rspi_data *rspi = arg; 441 struct rspi_data *rspi = arg;
@@ -471,7 +487,7 @@ static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t)
471 struct scatterlist sg; 487 struct scatterlist sg;
472 const void *buf = NULL; 488 const void *buf = NULL;
473 struct dma_async_tx_descriptor *desc; 489 struct dma_async_tx_descriptor *desc;
474 unsigned len; 490 unsigned int len;
475 int ret = 0; 491 int ret = 0;
476 492
477 if (rspi->dma_width_16bit) { 493 if (rspi->dma_width_16bit) {
@@ -509,7 +525,7 @@ static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t)
509 * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be 525 * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be
510 * called. So, this driver disables the IRQ while DMA transfer. 526 * called. So, this driver disables the IRQ while DMA transfer.
511 */ 527 */
512 disable_irq(rspi->irq); 528 disable_irq(rspi->tx_irq);
513 529
514 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD, RSPI_SPCR); 530 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD, RSPI_SPCR);
515 rspi_enable_irq(rspi, SPCR_SPTIE); 531 rspi_enable_irq(rspi, SPCR_SPTIE);
@@ -528,7 +544,7 @@ static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t)
528 ret = -ETIMEDOUT; 544 ret = -ETIMEDOUT;
529 rspi_disable_irq(rspi, SPCR_SPTIE); 545 rspi_disable_irq(rspi, SPCR_SPTIE);
530 546
531 enable_irq(rspi->irq); 547 enable_irq(rspi->tx_irq);
532 548
533end: 549end:
534 rspi_dma_unmap_sg(&sg, rspi->chan_tx, DMA_TO_DEVICE); 550 rspi_dma_unmap_sg(&sg, rspi->chan_tx, DMA_TO_DEVICE);
@@ -545,46 +561,17 @@ static void rspi_receive_init(const struct rspi_data *rspi)
545 561
546 spsr = rspi_read8(rspi, RSPI_SPSR); 562 spsr = rspi_read8(rspi, RSPI_SPSR);
547 if (spsr & SPSR_SPRF) 563 if (spsr & SPSR_SPRF)
548 rspi_read16(rspi, RSPI_SPDR); /* dummy read */ 564 rspi_read_data(rspi); /* dummy read */
549 if (spsr & SPSR_OVRF) 565 if (spsr & SPSR_OVRF)
550 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF, 566 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF,
551 RSPI_SPSR); 567 RSPI_SPSR);
552} 568}
553 569
554static int rspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg, 570static void rspi_rz_receive_init(const struct rspi_data *rspi)
555 struct spi_transfer *t)
556{ 571{
557 int remain = t->len;
558 u8 *data;
559
560 rspi_receive_init(rspi); 572 rspi_receive_init(rspi);
561 573 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR);
562 data = t->rx_buf; 574 rspi_write8(rspi, 0, RSPI_SPBFCR);
563 while (remain > 0) {
564 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD,
565 RSPI_SPCR);
566
567 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
568 dev_err(&rspi->master->dev,
569 "%s: tx empty timeout\n", __func__);
570 return -ETIMEDOUT;
571 }
572 /* dummy write for generate clock */
573 rspi_write16(rspi, DUMMY_DATA, RSPI_SPDR);
574
575 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) {
576 dev_err(&rspi->master->dev,
577 "%s: receive timeout\n", __func__);
578 return -ETIMEDOUT;
579 }
580 /* SPDR allows 16 or 32-bit access only */
581 *data = (u8)rspi_read16(rspi, RSPI_SPDR);
582
583 data++;
584 remain--;
585 }
586
587 return 0;
588} 575}
589 576
590static void qspi_receive_init(const struct rspi_data *rspi) 577static void qspi_receive_init(const struct rspi_data *rspi)
@@ -593,51 +580,17 @@ static void qspi_receive_init(const struct rspi_data *rspi)
593 580
594 spsr = rspi_read8(rspi, RSPI_SPSR); 581 spsr = rspi_read8(rspi, RSPI_SPSR);
595 if (spsr & SPSR_SPRF) 582 if (spsr & SPSR_SPRF)
596 rspi_read8(rspi, RSPI_SPDR); /* dummy read */ 583 rspi_read_data(rspi); /* dummy read */
597 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); 584 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
598 rspi_write8(rspi, 0x00, QSPI_SPBFCR); 585 rspi_write8(rspi, 0, QSPI_SPBFCR);
599} 586}
600 587
601static int qspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg,
602 struct spi_transfer *t)
603{
604 int remain = t->len;
605 u8 *data;
606
607 qspi_receive_init(rspi);
608
609 data = t->rx_buf;
610 while (remain > 0) {
611
612 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
613 dev_err(&rspi->master->dev,
614 "%s: tx empty timeout\n", __func__);
615 return -ETIMEDOUT;
616 }
617 /* dummy write for generate clock */
618 rspi_write8(rspi, DUMMY_DATA, RSPI_SPDR);
619
620 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) {
621 dev_err(&rspi->master->dev,
622 "%s: receive timeout\n", __func__);
623 return -ETIMEDOUT;
624 }
625 /* SPDR allows 8, 16 or 32-bit access */
626 *data++ = rspi_read8(rspi, RSPI_SPDR);
627 remain--;
628 }
629
630 return 0;
631}
632
633#define receive_pio(spi, mesg, t) spi->ops->receive_pio(spi, mesg, t)
634
635static int rspi_receive_dma(struct rspi_data *rspi, struct spi_transfer *t) 588static int rspi_receive_dma(struct rspi_data *rspi, struct spi_transfer *t)
636{ 589{
637 struct scatterlist sg, sg_dummy; 590 struct scatterlist sg, sg_dummy;
638 void *dummy = NULL, *rx_buf = NULL; 591 void *dummy = NULL, *rx_buf = NULL;
639 struct dma_async_tx_descriptor *desc, *desc_dummy; 592 struct dma_async_tx_descriptor *desc, *desc_dummy;
640 unsigned len; 593 unsigned int len;
641 int ret = 0; 594 int ret = 0;
642 595
643 if (rspi->dma_width_16bit) { 596 if (rspi->dma_width_16bit) {
@@ -695,7 +648,9 @@ static int rspi_receive_dma(struct rspi_data *rspi, struct spi_transfer *t)
695 * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be 648 * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be
696 * called. So, this driver disables the IRQ while DMA transfer. 649 * called. So, this driver disables the IRQ while DMA transfer.
697 */ 650 */
698 disable_irq(rspi->irq); 651 disable_irq(rspi->tx_irq);
652 if (rspi->rx_irq != rspi->tx_irq)
653 disable_irq(rspi->rx_irq);
699 654
700 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD, RSPI_SPCR); 655 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD, RSPI_SPCR);
701 rspi_enable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE); 656 rspi_enable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE);
@@ -718,7 +673,9 @@ static int rspi_receive_dma(struct rspi_data *rspi, struct spi_transfer *t)
718 ret = -ETIMEDOUT; 673 ret = -ETIMEDOUT;
719 rspi_disable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE); 674 rspi_disable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE);
720 675
721 enable_irq(rspi->irq); 676 enable_irq(rspi->tx_irq);
677 if (rspi->rx_irq != rspi->tx_irq)
678 enable_irq(rspi->rx_irq);
722 679
723end: 680end:
724 rspi_dma_unmap_sg(&sg, rspi->chan_rx, DMA_FROM_DEVICE); 681 rspi_dma_unmap_sg(&sg, rspi->chan_rx, DMA_FROM_DEVICE);
@@ -746,56 +703,175 @@ static int rspi_is_dma(const struct rspi_data *rspi, struct spi_transfer *t)
746 return 0; 703 return 0;
747} 704}
748 705
749static void rspi_work(struct work_struct *work) 706static int rspi_transfer_out_in(struct rspi_data *rspi,
707 struct spi_transfer *xfer)
750{ 708{
751 struct rspi_data *rspi = container_of(work, struct rspi_data, ws); 709 int remain = xfer->len, ret;
752 struct spi_message *mesg; 710 const u8 *tx_buf = xfer->tx_buf;
753 struct spi_transfer *t; 711 u8 *rx_buf = xfer->rx_buf;
754 unsigned long flags; 712 u8 spcr, data;
755 int ret;
756 713
757 while (1) { 714 rspi_receive_init(rspi);
758 spin_lock_irqsave(&rspi->lock, flags); 715
759 if (list_empty(&rspi->queue)) { 716 spcr = rspi_read8(rspi, RSPI_SPCR);
760 spin_unlock_irqrestore(&rspi->lock, flags); 717 if (rx_buf)
761 break; 718 spcr &= ~SPCR_TXMD;
762 } 719 else
763 mesg = list_entry(rspi->queue.next, struct spi_message, queue); 720 spcr |= SPCR_TXMD;
764 list_del_init(&mesg->queue); 721 rspi_write8(rspi, spcr, RSPI_SPCR);
765 spin_unlock_irqrestore(&rspi->lock, flags); 722
766 723 while (remain > 0) {
767 rspi_assert_ssl(rspi); 724 data = tx_buf ? *tx_buf++ : DUMMY_DATA;
768 725 ret = rspi_data_out(rspi, data);
769 list_for_each_entry(t, &mesg->transfers, transfer_list) { 726 if (ret < 0)
770 if (t->tx_buf) { 727 return ret;
771 if (rspi_is_dma(rspi, t)) 728 if (rx_buf) {
772 ret = rspi_send_dma(rspi, t); 729 ret = rspi_data_in(rspi);
773 else 730 if (ret < 0)
774 ret = send_pio(rspi, mesg, t); 731 return ret;
775 if (ret < 0) 732 *rx_buf++ = ret;
776 goto error;
777 }
778 if (t->rx_buf) {
779 if (rspi_is_dma(rspi, t))
780 ret = rspi_receive_dma(rspi, t);
781 else
782 ret = receive_pio(rspi, mesg, t);
783 if (ret < 0)
784 goto error;
785 }
786 mesg->actual_length += t->len;
787 } 733 }
788 rspi_negate_ssl(rspi); 734 remain--;
735 }
736
737 /* Wait for the last transmission */
738 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
739
740 return 0;
741}
742
743static int rspi_transfer_one(struct spi_master *master, struct spi_device *spi,
744 struct spi_transfer *xfer)
745{
746 struct rspi_data *rspi = spi_master_get_devdata(master);
747 int ret;
748
749 if (!rspi_is_dma(rspi, xfer))
750 return rspi_transfer_out_in(rspi, xfer);
751
752 if (xfer->tx_buf) {
753 ret = rspi_send_dma(rspi, xfer);
754 if (ret < 0)
755 return ret;
756 }
757 if (xfer->rx_buf)
758 return rspi_receive_dma(rspi, xfer);
759
760 return 0;
761}
762
763static int rspi_rz_transfer_out_in(struct rspi_data *rspi,
764 struct spi_transfer *xfer)
765{
766 int remain = xfer->len, ret;
767 const u8 *tx_buf = xfer->tx_buf;
768 u8 *rx_buf = xfer->rx_buf;
769 u8 data;
770
771 rspi_rz_receive_init(rspi);
772
773 while (remain > 0) {
774 data = tx_buf ? *tx_buf++ : DUMMY_DATA;
775 ret = rspi_data_out_in(rspi, data);
776 if (ret < 0)
777 return ret;
778 if (rx_buf)
779 *rx_buf++ = ret;
780 remain--;
781 }
782
783 /* Wait for the last transmission */
784 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
785
786 return 0;
787}
788
789static int rspi_rz_transfer_one(struct spi_master *master,
790 struct spi_device *spi,
791 struct spi_transfer *xfer)
792{
793 struct rspi_data *rspi = spi_master_get_devdata(master);
794
795 return rspi_rz_transfer_out_in(rspi, xfer);
796}
797
798static int qspi_transfer_out_in(struct rspi_data *rspi,
799 struct spi_transfer *xfer)
800{
801 int remain = xfer->len, ret;
802 const u8 *tx_buf = xfer->tx_buf;
803 u8 *rx_buf = xfer->rx_buf;
804 u8 data;
789 805
790 mesg->status = 0; 806 qspi_receive_init(rspi);
791 mesg->complete(mesg->context); 807
808 while (remain > 0) {
809 data = tx_buf ? *tx_buf++ : DUMMY_DATA;
810 ret = rspi_data_out_in(rspi, data);
811 if (ret < 0)
812 return ret;
813 if (rx_buf)
814 *rx_buf++ = ret;
815 remain--;
816 }
817
818 /* Wait for the last transmission */
819 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
820
821 return 0;
822}
823
824static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer)
825{
826 const u8 *buf = xfer->tx_buf;
827 unsigned int i;
828 int ret;
829
830 for (i = 0; i < xfer->len; i++) {
831 ret = rspi_data_out(rspi, *buf++);
832 if (ret < 0)
833 return ret;
792 } 834 }
793 835
794 return; 836 /* Wait for the last transmission */
837 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
795 838
796error: 839 return 0;
797 mesg->status = ret; 840}
798 mesg->complete(mesg->context); 841
842static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer)
843{
844 u8 *buf = xfer->rx_buf;
845 unsigned int i;
846 int ret;
847
848 for (i = 0; i < xfer->len; i++) {
849 ret = rspi_data_in(rspi);
850 if (ret < 0)
851 return ret;
852 *buf++ = ret;
853 }
854
855 return 0;
856}
857
858static int qspi_transfer_one(struct spi_master *master, struct spi_device *spi,
859 struct spi_transfer *xfer)
860{
861 struct rspi_data *rspi = spi_master_get_devdata(master);
862
863 if (spi->mode & SPI_LOOP) {
864 return qspi_transfer_out_in(rspi, xfer);
865 } else if (xfer->tx_buf && xfer->tx_nbits > SPI_NBITS_SINGLE) {
866 /* Quad or Dual SPI Write */
867 return qspi_transfer_out(rspi, xfer);
868 } else if (xfer->rx_buf && xfer->rx_nbits > SPI_NBITS_SINGLE) {
869 /* Quad or Dual SPI Read */
870 return qspi_transfer_in(rspi, xfer);
871 } else {
872 /* Single SPI Transfer */
873 return qspi_transfer_out_in(rspi, xfer);
874 }
799} 875}
800 876
801static int rspi_setup(struct spi_device *spi) 877static int rspi_setup(struct spi_device *spi)
@@ -810,32 +886,115 @@ static int rspi_setup(struct spi_device *spi)
810 if (spi->mode & SPI_CPHA) 886 if (spi->mode & SPI_CPHA)
811 rspi->spcmd |= SPCMD_CPHA; 887 rspi->spcmd |= SPCMD_CPHA;
812 888
889 /* CMOS output mode and MOSI signal from previous transfer */
890 rspi->sppcr = 0;
891 if (spi->mode & SPI_LOOP)
892 rspi->sppcr |= SPPCR_SPLP;
893
813 set_config_register(rspi, 8); 894 set_config_register(rspi, 8);
814 895
815 return 0; 896 return 0;
816} 897}
817 898
818static int rspi_transfer(struct spi_device *spi, struct spi_message *mesg) 899static u16 qspi_transfer_mode(const struct spi_transfer *xfer)
819{ 900{
820 struct rspi_data *rspi = spi_master_get_devdata(spi->master); 901 if (xfer->tx_buf)
821 unsigned long flags; 902 switch (xfer->tx_nbits) {
903 case SPI_NBITS_QUAD:
904 return SPCMD_SPIMOD_QUAD;
905 case SPI_NBITS_DUAL:
906 return SPCMD_SPIMOD_DUAL;
907 default:
908 return 0;
909 }
910 if (xfer->rx_buf)
911 switch (xfer->rx_nbits) {
912 case SPI_NBITS_QUAD:
913 return SPCMD_SPIMOD_QUAD | SPCMD_SPRW;
914 case SPI_NBITS_DUAL:
915 return SPCMD_SPIMOD_DUAL | SPCMD_SPRW;
916 default:
917 return 0;
918 }
919
920 return 0;
921}
822 922
823 mesg->actual_length = 0; 923static int qspi_setup_sequencer(struct rspi_data *rspi,
824 mesg->status = -EINPROGRESS; 924 const struct spi_message *msg)
925{
926 const struct spi_transfer *xfer;
927 unsigned int i = 0, len = 0;
928 u16 current_mode = 0xffff, mode;
929
930 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
931 mode = qspi_transfer_mode(xfer);
932 if (mode == current_mode) {
933 len += xfer->len;
934 continue;
935 }
936
937 /* Transfer mode change */
938 if (i) {
939 /* Set transfer data length of previous transfer */
940 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
941 }
825 942
826 spin_lock_irqsave(&rspi->lock, flags); 943 if (i >= QSPI_NUM_SPCMD) {
827 list_add_tail(&mesg->queue, &rspi->queue); 944 dev_err(&msg->spi->dev,
828 schedule_work(&rspi->ws); 945 "Too many different transfer modes");
829 spin_unlock_irqrestore(&rspi->lock, flags); 946 return -EINVAL;
947 }
948
949 /* Program transfer mode for this transfer */
950 rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i));
951 current_mode = mode;
952 len = xfer->len;
953 i++;
954 }
955 if (i) {
956 /* Set final transfer data length and sequence length */
957 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
958 rspi_write8(rspi, i - 1, RSPI_SPSCR);
959 }
830 960
831 return 0; 961 return 0;
832} 962}
833 963
834static void rspi_cleanup(struct spi_device *spi) 964static int rspi_prepare_message(struct spi_master *master,
965 struct spi_message *msg)
835{ 966{
967 struct rspi_data *rspi = spi_master_get_devdata(master);
968 int ret;
969
970 if (msg->spi->mode &
971 (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) {
972 /* Setup sequencer for messages with multiple transfer modes */
973 ret = qspi_setup_sequencer(rspi, msg);
974 if (ret < 0)
975 return ret;
976 }
977
978 /* Enable SPI function in master mode */
979 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
980 return 0;
836} 981}
837 982
838static irqreturn_t rspi_irq(int irq, void *_sr) 983static int rspi_unprepare_message(struct spi_master *master,
984 struct spi_message *msg)
985{
986 struct rspi_data *rspi = spi_master_get_devdata(master);
987
988 /* Disable SPI function */
989 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
990
991 /* Reset sequencer for Single SPI Transfers */
992 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
993 rspi_write8(rspi, 0, RSPI_SPSCR);
994 return 0;
995}
996
997static irqreturn_t rspi_irq_mux(int irq, void *_sr)
839{ 998{
840 struct rspi_data *rspi = _sr; 999 struct rspi_data *rspi = _sr;
841 u8 spsr; 1000 u8 spsr;
@@ -857,6 +1016,36 @@ static irqreturn_t rspi_irq(int irq, void *_sr)
857 return ret; 1016 return ret;
858} 1017}
859 1018
1019static irqreturn_t rspi_irq_rx(int irq, void *_sr)
1020{
1021 struct rspi_data *rspi = _sr;
1022 u8 spsr;
1023
1024 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1025 if (spsr & SPSR_SPRF) {
1026 rspi_disable_irq(rspi, SPCR_SPRIE);
1027 wake_up(&rspi->wait);
1028 return IRQ_HANDLED;
1029 }
1030
1031 return 0;
1032}
1033
1034static irqreturn_t rspi_irq_tx(int irq, void *_sr)
1035{
1036 struct rspi_data *rspi = _sr;
1037 u8 spsr;
1038
1039 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1040 if (spsr & SPSR_SPTEF) {
1041 rspi_disable_irq(rspi, SPCR_SPTIE);
1042 wake_up(&rspi->wait);
1043 return IRQ_HANDLED;
1044 }
1045
1046 return 0;
1047}
1048
860static int rspi_request_dma(struct rspi_data *rspi, 1049static int rspi_request_dma(struct rspi_data *rspi,
861 struct platform_device *pdev) 1050 struct platform_device *pdev)
862{ 1051{
@@ -923,34 +1112,89 @@ static int rspi_remove(struct platform_device *pdev)
923 struct rspi_data *rspi = platform_get_drvdata(pdev); 1112 struct rspi_data *rspi = platform_get_drvdata(pdev);
924 1113
925 rspi_release_dma(rspi); 1114 rspi_release_dma(rspi);
926 clk_disable(rspi->clk); 1115 pm_runtime_disable(&pdev->dev);
927 1116
928 return 0; 1117 return 0;
929} 1118}
930 1119
1120static const struct spi_ops rspi_ops = {
1121 .set_config_register = rspi_set_config_register,
1122 .transfer_one = rspi_transfer_one,
1123 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP,
1124};
1125
1126static const struct spi_ops rspi_rz_ops = {
1127 .set_config_register = rspi_rz_set_config_register,
1128 .transfer_one = rspi_rz_transfer_one,
1129 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP,
1130};
1131
1132static const struct spi_ops qspi_ops = {
1133 .set_config_register = qspi_set_config_register,
1134 .transfer_one = qspi_transfer_one,
1135 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP |
1136 SPI_TX_DUAL | SPI_TX_QUAD |
1137 SPI_RX_DUAL | SPI_RX_QUAD,
1138};
1139
1140#ifdef CONFIG_OF
1141static const struct of_device_id rspi_of_match[] = {
1142 /* RSPI on legacy SH */
1143 { .compatible = "renesas,rspi", .data = &rspi_ops },
1144 /* RSPI on RZ/A1H */
1145 { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops },
1146 /* QSPI on R-Car Gen2 */
1147 { .compatible = "renesas,qspi", .data = &qspi_ops },
1148 { /* sentinel */ }
1149};
1150
1151MODULE_DEVICE_TABLE(of, rspi_of_match);
1152
1153static int rspi_parse_dt(struct device *dev, struct spi_master *master)
1154{
1155 u32 num_cs;
1156 int error;
1157
1158 /* Parse DT properties */
1159 error = of_property_read_u32(dev->of_node, "num-cs", &num_cs);
1160 if (error) {
1161 dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error);
1162 return error;
1163 }
1164
1165 master->num_chipselect = num_cs;
1166 return 0;
1167}
1168#else
1169#define rspi_of_match NULL
1170static inline int rspi_parse_dt(struct device *dev, struct spi_master *master)
1171{
1172 return -EINVAL;
1173}
1174#endif /* CONFIG_OF */
1175
1176static int rspi_request_irq(struct device *dev, unsigned int irq,
1177 irq_handler_t handler, const char *suffix,
1178 void *dev_id)
1179{
1180 const char *base = dev_name(dev);
1181 size_t len = strlen(base) + strlen(suffix) + 2;
1182 char *name = devm_kzalloc(dev, len, GFP_KERNEL);
1183 if (!name)
1184 return -ENOMEM;
1185 snprintf(name, len, "%s:%s", base, suffix);
1186 return devm_request_irq(dev, irq, handler, 0, name, dev_id);
1187}
1188
931static int rspi_probe(struct platform_device *pdev) 1189static int rspi_probe(struct platform_device *pdev)
932{ 1190{
933 struct resource *res; 1191 struct resource *res;
934 struct spi_master *master; 1192 struct spi_master *master;
935 struct rspi_data *rspi; 1193 struct rspi_data *rspi;
936 int ret, irq; 1194 int ret;
937 char clk_name[16]; 1195 const struct of_device_id *of_id;
938 const struct rspi_plat_data *rspi_pd = dev_get_platdata(&pdev->dev); 1196 const struct rspi_plat_data *rspi_pd;
939 const struct spi_ops *ops; 1197 const struct spi_ops *ops;
940 const struct platform_device_id *id_entry = pdev->id_entry;
941
942 ops = (struct spi_ops *)id_entry->driver_data;
943 /* ops parameter check */
944 if (!ops->set_config_register) {
945 dev_err(&pdev->dev, "there is no set_config_register\n");
946 return -ENODEV;
947 }
948
949 irq = platform_get_irq(pdev, 0);
950 if (irq < 0) {
951 dev_err(&pdev->dev, "platform_get_irq error\n");
952 return -ENODEV;
953 }
954 1198
955 master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data)); 1199 master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data));
956 if (master == NULL) { 1200 if (master == NULL) {
@@ -958,6 +1202,28 @@ static int rspi_probe(struct platform_device *pdev)
958 return -ENOMEM; 1202 return -ENOMEM;
959 } 1203 }
960 1204
1205 of_id = of_match_device(rspi_of_match, &pdev->dev);
1206 if (of_id) {
1207 ops = of_id->data;
1208 ret = rspi_parse_dt(&pdev->dev, master);
1209 if (ret)
1210 goto error1;
1211 } else {
1212 ops = (struct spi_ops *)pdev->id_entry->driver_data;
1213 rspi_pd = dev_get_platdata(&pdev->dev);
1214 if (rspi_pd && rspi_pd->num_chipselect)
1215 master->num_chipselect = rspi_pd->num_chipselect;
1216 else
1217 master->num_chipselect = 2; /* default */
1218 };
1219
1220 /* ops parameter check */
1221 if (!ops->set_config_register) {
1222 dev_err(&pdev->dev, "there is no set_config_register\n");
1223 ret = -ENODEV;
1224 goto error1;
1225 }
1226
961 rspi = spi_master_get_devdata(master); 1227 rspi = spi_master_get_devdata(master);
962 platform_set_drvdata(pdev, rspi); 1228 platform_set_drvdata(pdev, rspi);
963 rspi->ops = ops; 1229 rspi->ops = ops;
@@ -970,39 +1236,61 @@ static int rspi_probe(struct platform_device *pdev)
970 goto error1; 1236 goto error1;
971 } 1237 }
972 1238
973 snprintf(clk_name, sizeof(clk_name), "%s%d", id_entry->name, pdev->id); 1239 rspi->clk = devm_clk_get(&pdev->dev, NULL);
974 rspi->clk = devm_clk_get(&pdev->dev, clk_name);
975 if (IS_ERR(rspi->clk)) { 1240 if (IS_ERR(rspi->clk)) {
976 dev_err(&pdev->dev, "cannot get clock\n"); 1241 dev_err(&pdev->dev, "cannot get clock\n");
977 ret = PTR_ERR(rspi->clk); 1242 ret = PTR_ERR(rspi->clk);
978 goto error1; 1243 goto error1;
979 } 1244 }
980 clk_enable(rspi->clk);
981 1245
982 INIT_LIST_HEAD(&rspi->queue); 1246 pm_runtime_enable(&pdev->dev);
983 spin_lock_init(&rspi->lock);
984 INIT_WORK(&rspi->ws, rspi_work);
985 init_waitqueue_head(&rspi->wait);
986 1247
987 if (rspi_pd && rspi_pd->num_chipselect) 1248 init_waitqueue_head(&rspi->wait);
988 master->num_chipselect = rspi_pd->num_chipselect;
989 else
990 master->num_chipselect = 2; /* default */
991 1249
992 master->bus_num = pdev->id; 1250 master->bus_num = pdev->id;
993 master->setup = rspi_setup; 1251 master->setup = rspi_setup;
994 master->transfer = rspi_transfer; 1252 master->auto_runtime_pm = true;
995 master->cleanup = rspi_cleanup; 1253 master->transfer_one = ops->transfer_one;
996 master->mode_bits = SPI_CPHA | SPI_CPOL; 1254 master->prepare_message = rspi_prepare_message;
1255 master->unprepare_message = rspi_unprepare_message;
1256 master->mode_bits = ops->mode_bits;
1257 master->dev.of_node = pdev->dev.of_node;
1258
1259 ret = platform_get_irq_byname(pdev, "rx");
1260 if (ret < 0) {
1261 ret = platform_get_irq_byname(pdev, "mux");
1262 if (ret < 0)
1263 ret = platform_get_irq(pdev, 0);
1264 if (ret >= 0)
1265 rspi->rx_irq = rspi->tx_irq = ret;
1266 } else {
1267 rspi->rx_irq = ret;
1268 ret = platform_get_irq_byname(pdev, "tx");
1269 if (ret >= 0)
1270 rspi->tx_irq = ret;
1271 }
1272 if (ret < 0) {
1273 dev_err(&pdev->dev, "platform_get_irq error\n");
1274 goto error2;
1275 }
997 1276
998 ret = devm_request_irq(&pdev->dev, irq, rspi_irq, 0, 1277 if (rspi->rx_irq == rspi->tx_irq) {
999 dev_name(&pdev->dev), rspi); 1278 /* Single multiplexed interrupt */
1279 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux,
1280 "mux", rspi);
1281 } else {
1282 /* Multi-interrupt mode, only SPRI and SPTI are used */
1283 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx,
1284 "rx", rspi);
1285 if (!ret)
1286 ret = rspi_request_irq(&pdev->dev, rspi->tx_irq,
1287 rspi_irq_tx, "tx", rspi);
1288 }
1000 if (ret < 0) { 1289 if (ret < 0) {
1001 dev_err(&pdev->dev, "request_irq error\n"); 1290 dev_err(&pdev->dev, "request_irq error\n");
1002 goto error2; 1291 goto error2;
1003 } 1292 }
1004 1293
1005 rspi->irq = irq;
1006 ret = rspi_request_dma(rspi, pdev); 1294 ret = rspi_request_dma(rspi, pdev);
1007 if (ret < 0) { 1295 if (ret < 0) {
1008 dev_err(&pdev->dev, "rspi_request_dma failed.\n"); 1296 dev_err(&pdev->dev, "rspi_request_dma failed.\n");
@@ -1022,27 +1310,16 @@ static int rspi_probe(struct platform_device *pdev)
1022error3: 1310error3:
1023 rspi_release_dma(rspi); 1311 rspi_release_dma(rspi);
1024error2: 1312error2:
1025 clk_disable(rspi->clk); 1313 pm_runtime_disable(&pdev->dev);
1026error1: 1314error1:
1027 spi_master_put(master); 1315 spi_master_put(master);
1028 1316
1029 return ret; 1317 return ret;
1030} 1318}
1031 1319
1032static struct spi_ops rspi_ops = {
1033 .set_config_register = rspi_set_config_register,
1034 .send_pio = rspi_send_pio,
1035 .receive_pio = rspi_receive_pio,
1036};
1037
1038static struct spi_ops qspi_ops = {
1039 .set_config_register = qspi_set_config_register,
1040 .send_pio = qspi_send_pio,
1041 .receive_pio = qspi_receive_pio,
1042};
1043
1044static struct platform_device_id spi_driver_ids[] = { 1320static struct platform_device_id spi_driver_ids[] = {
1045 { "rspi", (kernel_ulong_t)&rspi_ops }, 1321 { "rspi", (kernel_ulong_t)&rspi_ops },
1322 { "rspi-rz", (kernel_ulong_t)&rspi_rz_ops },
1046 { "qspi", (kernel_ulong_t)&qspi_ops }, 1323 { "qspi", (kernel_ulong_t)&qspi_ops },
1047 {}, 1324 {},
1048}; 1325};
@@ -1056,6 +1333,7 @@ static struct platform_driver rspi_driver = {
1056 .driver = { 1333 .driver = {
1057 .name = "renesas_spi", 1334 .name = "renesas_spi",
1058 .owner = THIS_MODULE, 1335 .owner = THIS_MODULE,
1336 .of_match_table = of_match_ptr(rspi_of_match),
1059 }, 1337 },
1060}; 1338};
1061module_platform_driver(rspi_driver); 1339module_platform_driver(rspi_driver);
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-26 12:39:55 -0400