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-rw-r--r--Documentation/devicetree/bindings/spi/qcom,spi-qup.txt85
-rw-r--r--Documentation/devicetree/bindings/spi/spi-rspi.txt61
-rw-r--r--drivers/base/power/Makefile3
-rw-r--r--drivers/base/power/runtime.c162
-rw-r--r--drivers/spi/Kconfig15
-rw-r--r--drivers/spi/Makefile1
-rw-r--r--drivers/spi/spi-omap-100k.c52
-rw-r--r--drivers/spi/spi-omap-uwire.c23
-rw-r--r--drivers/spi/spi-omap2-mcspi.c64
-rw-r--r--drivers/spi/spi-orion.c79
-rw-r--r--drivers/spi/spi-pl022.c75
-rw-r--r--drivers/spi/spi-qup.c779
-rw-r--r--drivers/spi/spi-rspi.c842
-rw-r--r--drivers/spi/spi-s3c24xx.c18
-rw-r--r--include/linux/pm_runtime.h4
15 files changed, 1735 insertions, 528 deletions
diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
new file mode 100644
index 000000000000..b82a268f1bd4
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
@@ -0,0 +1,85 @@
1Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
2
3The QUP core is an AHB slave that provides a common data path (an output FIFO
4and an input FIFO) for serial peripheral interface (SPI) mini-core.
5
6SPI in master mode supports up to 50MHz, up to four chip selects, programmable
7data path from 4 bits to 32 bits and numerous protocol variants.
8
9Required properties:
10- compatible: Should contain "qcom,spi-qup-v2.1.1" or "qcom,spi-qup-v2.2.1"
11- reg: Should contain base register location and length
12- interrupts: Interrupt number used by this controller
13
14- clocks: Should contain the core clock and the AHB clock.
15- clock-names: Should be "core" for the core clock and "iface" for the
16 AHB clock.
17
18- #address-cells: Number of cells required to define a chip select
19 address on the SPI bus. Should be set to 1.
20- #size-cells: Should be zero.
21
22Optional properties:
23- spi-max-frequency: Specifies maximum SPI clock frequency,
24 Units - Hz. Definition as per
25 Documentation/devicetree/bindings/spi/spi-bus.txt
26
27SPI slave nodes must be children of the SPI master node and can contain
28properties described in Documentation/devicetree/bindings/spi/spi-bus.txt
29
30Example:
31
32 spi_8: spi@f9964000 { /* BLSP2 QUP2 */
33
34 compatible = "qcom,spi-qup-v2";
35 #address-cells = <1>;
36 #size-cells = <0>;
37 reg = <0xf9964000 0x1000>;
38 interrupts = <0 102 0>;
39 spi-max-frequency = <19200000>;
40
41 clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
42 clock-names = "core", "iface";
43
44 pinctrl-names = "default";
45 pinctrl-0 = <&spi8_default>;
46
47 device@0 {
48 compatible = "arm,pl022-dummy";
49 #address-cells = <1>;
50 #size-cells = <1>;
51 reg = <0>; /* Chip select 0 */
52 spi-max-frequency = <19200000>;
53 spi-cpol;
54 };
55
56 device@1 {
57 compatible = "arm,pl022-dummy";
58 #address-cells = <1>;
59 #size-cells = <1>;
60 reg = <1>; /* Chip select 1 */
61 spi-max-frequency = <9600000>;
62 spi-cpha;
63 };
64
65 device@2 {
66 compatible = "arm,pl022-dummy";
67 #address-cells = <1>;
68 #size-cells = <1>;
69 reg = <2>; /* Chip select 2 */
70 spi-max-frequency = <19200000>;
71 spi-cpol;
72 spi-cpha;
73 };
74
75 device@3 {
76 compatible = "arm,pl022-dummy";
77 #address-cells = <1>;
78 #size-cells = <1>;
79 reg = <3>; /* Chip select 3 */
80 spi-max-frequency = <19200000>;
81 spi-cpol;
82 spi-cpha;
83 spi-cs-high;
84 };
85 };
diff --git a/Documentation/devicetree/bindings/spi/spi-rspi.txt b/Documentation/devicetree/bindings/spi/spi-rspi.txt
new file mode 100644
index 000000000000..d57d82a74054
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-rspi.txt
@@ -0,0 +1,61 @@
1Device tree configuration for Renesas RSPI/QSPI driver
2
3Required properties:
4- compatible : For Renesas Serial Peripheral Interface on legacy SH:
5 "renesas,rspi-<soctype>", "renesas,rspi" as fallback.
6 For Renesas Serial Peripheral Interface on RZ/A1H:
7 "renesas,rspi-<soctype>", "renesas,rspi-rz" as fallback.
8 For Quad Serial Peripheral Interface on R-Car Gen2:
9 "renesas,qspi-<soctype>", "renesas,qspi" as fallback.
10 Examples with soctypes are:
11 - "renesas,rspi-sh7757" (SH)
12 - "renesas,rspi-r7s72100" (RZ/A1H)
13 - "renesas,qspi-r8a7790" (R-Car H2)
14 - "renesas,qspi-r8a7791" (R-Car M2)
15- reg : Address start and address range size of the device
16- interrupts : A list of interrupt-specifiers, one for each entry in
17 interrupt-names.
18 If interrupt-names is not present, an interrupt specifier
19 for a single muxed interrupt.
20- interrupt-names : A list of interrupt names. Should contain (if present):
21 - "error" for SPEI,
22 - "rx" for SPRI,
23 - "tx" to SPTI,
24 - "mux" for a single muxed interrupt.
25- interrupt-parent : The phandle for the interrupt controller that
26 services interrupts for this device.
27- num-cs : Number of chip selects. Some RSPI cores have more than 1.
28- #address-cells : Must be <1>
29- #size-cells : Must be <0>
30
31Optional properties:
32- clocks : Must contain a reference to the functional clock.
33
34Pinctrl properties might be needed, too. See
35Documentation/devicetree/bindings/pinctrl/renesas,*.
36
37Examples:
38
39 spi0: spi@e800c800 {
40 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
41 reg = <0xe800c800 0x24>;
42 interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>,
43 <0 239 IRQ_TYPE_LEVEL_HIGH>,
44 <0 240 IRQ_TYPE_LEVEL_HIGH>;
45 interrupt-names = "error", "rx", "tx";
46 interrupt-parent = <&gic>;
47 num-cs = <1>;
48 #address-cells = <1>;
49 #size-cells = <0>;
50 };
51
52 spi: spi@e6b10000 {
53 compatible = "renesas,qspi-r8a7791", "renesas,qspi";
54 reg = <0 0xe6b10000 0 0x2c>;
55 interrupt-parent = <&gic>;
56 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
57 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
58 num-cs = <1>;
59 #address-cells = <1>;
60 #size-cells = <0>;
61 };
diff --git a/drivers/base/power/Makefile b/drivers/base/power/Makefile
index 2e58ebb1f6c0..1cb8544598d5 100644
--- a/drivers/base/power/Makefile
+++ b/drivers/base/power/Makefile
@@ -1,6 +1,5 @@
1obj-$(CONFIG_PM) += sysfs.o generic_ops.o common.o qos.o 1obj-$(CONFIG_PM) += sysfs.o generic_ops.o common.o qos.o runtime.o
2obj-$(CONFIG_PM_SLEEP) += main.o wakeup.o 2obj-$(CONFIG_PM_SLEEP) += main.o wakeup.o
3obj-$(CONFIG_PM_RUNTIME) += runtime.o
4obj-$(CONFIG_PM_TRACE_RTC) += trace.o 3obj-$(CONFIG_PM_TRACE_RTC) += trace.o
5obj-$(CONFIG_PM_OPP) += opp.o 4obj-$(CONFIG_PM_OPP) += opp.o
6obj-$(CONFIG_PM_GENERIC_DOMAINS) += domain.o domain_governor.o 5obj-$(CONFIG_PM_GENERIC_DOMAINS) += domain.o domain_governor.o
diff --git a/drivers/base/power/runtime.c b/drivers/base/power/runtime.c
index 72e00e66ecc5..4776cf528d08 100644
--- a/drivers/base/power/runtime.c
+++ b/drivers/base/power/runtime.c
@@ -13,6 +13,43 @@
13#include <trace/events/rpm.h> 13#include <trace/events/rpm.h>
14#include "power.h" 14#include "power.h"
15 15
16#define RPM_GET_CALLBACK(dev, cb) \
17({ \
18 int (*__rpm_cb)(struct device *__d); \
19 \
20 if (dev->pm_domain) \
21 __rpm_cb = dev->pm_domain->ops.cb; \
22 else if (dev->type && dev->type->pm) \
23 __rpm_cb = dev->type->pm->cb; \
24 else if (dev->class && dev->class->pm) \
25 __rpm_cb = dev->class->pm->cb; \
26 else if (dev->bus && dev->bus->pm) \
27 __rpm_cb = dev->bus->pm->cb; \
28 else \
29 __rpm_cb = NULL; \
30 \
31 if (!__rpm_cb && dev->driver && dev->driver->pm) \
32 __rpm_cb = dev->driver->pm->cb; \
33 \
34 __rpm_cb; \
35})
36
37static int (*rpm_get_suspend_cb(struct device *dev))(struct device *)
38{
39 return RPM_GET_CALLBACK(dev, runtime_suspend);
40}
41
42static int (*rpm_get_resume_cb(struct device *dev))(struct device *)
43{
44 return RPM_GET_CALLBACK(dev, runtime_resume);
45}
46
47#ifdef CONFIG_PM_RUNTIME
48static int (*rpm_get_idle_cb(struct device *dev))(struct device *)
49{
50 return RPM_GET_CALLBACK(dev, runtime_idle);
51}
52
16static int rpm_resume(struct device *dev, int rpmflags); 53static int rpm_resume(struct device *dev, int rpmflags);
17static int rpm_suspend(struct device *dev, int rpmflags); 54static int rpm_suspend(struct device *dev, int rpmflags);
18 55
@@ -310,19 +347,7 @@ static int rpm_idle(struct device *dev, int rpmflags)
310 347
311 dev->power.idle_notification = true; 348 dev->power.idle_notification = true;
312 349
313 if (dev->pm_domain) 350 callback = rpm_get_idle_cb(dev);
314 callback = dev->pm_domain->ops.runtime_idle;
315 else if (dev->type && dev->type->pm)
316 callback = dev->type->pm->runtime_idle;
317 else if (dev->class && dev->class->pm)
318 callback = dev->class->pm->runtime_idle;
319 else if (dev->bus && dev->bus->pm)
320 callback = dev->bus->pm->runtime_idle;
321 else
322 callback = NULL;
323
324 if (!callback && dev->driver && dev->driver->pm)
325 callback = dev->driver->pm->runtime_idle;
326 351
327 if (callback) 352 if (callback)
328 retval = __rpm_callback(callback, dev); 353 retval = __rpm_callback(callback, dev);
@@ -492,19 +517,7 @@ static int rpm_suspend(struct device *dev, int rpmflags)
492 517
493 __update_runtime_status(dev, RPM_SUSPENDING); 518 __update_runtime_status(dev, RPM_SUSPENDING);
494 519
495 if (dev->pm_domain) 520 callback = rpm_get_suspend_cb(dev);
496 callback = dev->pm_domain->ops.runtime_suspend;
497 else if (dev->type && dev->type->pm)
498 callback = dev->type->pm->runtime_suspend;
499 else if (dev->class && dev->class->pm)
500 callback = dev->class->pm->runtime_suspend;
501 else if (dev->bus && dev->bus->pm)
502 callback = dev->bus->pm->runtime_suspend;
503 else
504 callback = NULL;
505
506 if (!callback && dev->driver && dev->driver->pm)
507 callback = dev->driver->pm->runtime_suspend;
508 521
509 retval = rpm_callback(callback, dev); 522 retval = rpm_callback(callback, dev);
510 if (retval) 523 if (retval)
@@ -724,19 +737,7 @@ static int rpm_resume(struct device *dev, int rpmflags)
724 737
725 __update_runtime_status(dev, RPM_RESUMING); 738 __update_runtime_status(dev, RPM_RESUMING);
726 739
727 if (dev->pm_domain) 740 callback = rpm_get_resume_cb(dev);
728 callback = dev->pm_domain->ops.runtime_resume;
729 else if (dev->type && dev->type->pm)
730 callback = dev->type->pm->runtime_resume;
731 else if (dev->class && dev->class->pm)
732 callback = dev->class->pm->runtime_resume;
733 else if (dev->bus && dev->bus->pm)
734 callback = dev->bus->pm->runtime_resume;
735 else
736 callback = NULL;
737
738 if (!callback && dev->driver && dev->driver->pm)
739 callback = dev->driver->pm->runtime_resume;
740 741
741 retval = rpm_callback(callback, dev); 742 retval = rpm_callback(callback, dev);
742 if (retval) { 743 if (retval) {
@@ -1401,3 +1402,86 @@ void pm_runtime_remove(struct device *dev)
1401 if (dev->power.irq_safe && dev->parent) 1402 if (dev->power.irq_safe && dev->parent)
1402 pm_runtime_put(dev->parent); 1403 pm_runtime_put(dev->parent);
1403} 1404}
1405#endif
1406
1407/**
1408 * pm_runtime_force_suspend - Force a device into suspend state if needed.
1409 * @dev: Device to suspend.
1410 *
1411 * Disable runtime PM so we safely can check the device's runtime PM status and
1412 * if it is active, invoke it's .runtime_suspend callback to bring it into
1413 * suspend state. Keep runtime PM disabled to preserve the state unless we
1414 * encounter errors.
1415 *
1416 * Typically this function may be invoked from a system suspend callback to make
1417 * sure the device is put into low power state.
1418 */
1419int pm_runtime_force_suspend(struct device *dev)
1420{
1421 int (*callback)(struct device *);
1422 int ret = 0;
1423
1424 pm_runtime_disable(dev);
1425
1426 /*
1427 * Note that pm_runtime_status_suspended() returns false while
1428 * !CONFIG_PM_RUNTIME, which means the device will be put into low
1429 * power state.
1430 */
1431 if (pm_runtime_status_suspended(dev))
1432 return 0;
1433
1434 callback = rpm_get_suspend_cb(dev);
1435
1436 if (!callback) {
1437 ret = -ENOSYS;
1438 goto err;
1439 }
1440
1441 ret = callback(dev);
1442 if (ret)
1443 goto err;
1444
1445 pm_runtime_set_suspended(dev);
1446 return 0;
1447err:
1448 pm_runtime_enable(dev);
1449 return ret;
1450}
1451EXPORT_SYMBOL_GPL(pm_runtime_force_suspend);
1452
1453/**
1454 * pm_runtime_force_resume - Force a device into resume state.
1455 * @dev: Device to resume.
1456 *
1457 * Prior invoking this function we expect the user to have brought the device
1458 * into low power state by a call to pm_runtime_force_suspend(). Here we reverse
1459 * those actions and brings the device into full power. We update the runtime PM
1460 * status and re-enables runtime PM.
1461 *
1462 * Typically this function may be invoked from a system resume callback to make
1463 * sure the device is put into full power state.
1464 */
1465int pm_runtime_force_resume(struct device *dev)
1466{
1467 int (*callback)(struct device *);
1468 int ret = 0;
1469
1470 callback = rpm_get_resume_cb(dev);
1471
1472 if (!callback) {
1473 ret = -ENOSYS;
1474 goto out;
1475 }
1476
1477 ret = callback(dev);
1478 if (ret)
1479 goto out;
1480
1481 pm_runtime_set_active(dev);
1482 pm_runtime_mark_last_busy(dev);
1483out:
1484 pm_runtime_enable(dev);
1485 return ret;
1486}
1487EXPORT_SYMBOL_GPL(pm_runtime_force_resume);
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 5bf7a4f100d2..5dea67c798d5 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -307,7 +307,7 @@ config SPI_OMAP_UWIRE
307 307
308config SPI_OMAP24XX 308config SPI_OMAP24XX
309 tristate "McSPI driver for OMAP" 309 tristate "McSPI driver for OMAP"
310 depends on ARM || ARM64 || AVR32 || HEXAGON || MIPS || SH 310 depends on ARM || ARM64 || AVR32 || HEXAGON || MIPS || SUPERH
311 depends on ARCH_OMAP2PLUS || COMPILE_TEST 311 depends on ARCH_OMAP2PLUS || COMPILE_TEST
312 help 312 help
313 SPI master controller for OMAP24XX and later Multichannel SPI 313 SPI master controller for OMAP24XX and later Multichannel SPI
@@ -381,6 +381,19 @@ config SPI_RSPI
381 help 381 help
382 SPI driver for Renesas RSPI and QSPI blocks. 382 SPI driver for Renesas RSPI and QSPI blocks.
383 383
384config SPI_QUP
385 tristate "Qualcomm SPI controller with QUP interface"
386 depends on ARCH_MSM_DT || (ARM && COMPILE_TEST)
387 help
388 Qualcomm Universal Peripheral (QUP) core is an AHB slave that
389 provides a common data path (an output FIFO and an input FIFO)
390 for serial peripheral interface (SPI) mini-core. SPI in master
391 mode supports up to 50MHz, up to four chip selects, programmable
392 data path from 4 bits to 32 bits and numerous protocol variants.
393
394 This driver can also be built as a module. If so, the module
395 will be called spi_qup.
396
384config SPI_S3C24XX 397config SPI_S3C24XX
385 tristate "Samsung S3C24XX series SPI" 398 tristate "Samsung S3C24XX series SPI"
386 depends on ARCH_S3C24XX 399 depends on ARCH_S3C24XX
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 95af48d2d360..e598147b06ef 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -59,6 +59,7 @@ spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_PXADMA) += spi-pxa2xx-pxadma.o
59spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_DMA) += spi-pxa2xx-dma.o 59spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_DMA) += spi-pxa2xx-dma.o
60obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx-platform.o 60obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx-platform.o
61obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o 61obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o
62obj-$(CONFIG_SPI_QUP) += spi-qup.o
62obj-$(CONFIG_SPI_RSPI) += spi-rspi.o 63obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
63obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o 64obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o
64spi-s3c24xx-hw-y := spi-s3c24xx.o 65spi-s3c24xx-hw-y := spi-s3c24xx.o
diff --git a/drivers/spi/spi-omap-100k.c b/drivers/spi/spi-omap-100k.c
index 0d32054bfc0d..e7ffcded4e14 100644
--- a/drivers/spi/spi-omap-100k.c
+++ b/drivers/spi/spi-omap-100k.c
@@ -83,15 +83,11 @@
83#define SPI_SHUTDOWN 1 83#define SPI_SHUTDOWN 1
84 84
85struct omap1_spi100k { 85struct omap1_spi100k {
86 struct spi_master *master;
87 struct clk *ick; 86 struct clk *ick;
88 struct clk *fck; 87 struct clk *fck;
89 88
90 /* Virtual base address of the controller */ 89 /* Virtual base address of the controller */
91 void __iomem *base; 90 void __iomem *base;
92
93 /* State of the SPI */
94 unsigned int state;
95}; 91};
96 92
97struct omap1_spi100k_cs { 93struct omap1_spi100k_cs {
@@ -99,13 +95,6 @@ struct omap1_spi100k_cs {
99 int word_len; 95 int word_len;
100}; 96};
101 97
102#define MOD_REG_BIT(val, mask, set) do { \
103 if (set) \
104 val |= mask; \
105 else \
106 val &= ~mask; \
107} while (0)
108
109static void spi100k_enable_clock(struct spi_master *master) 98static void spi100k_enable_clock(struct spi_master *master)
110{ 99{
111 unsigned int val; 100 unsigned int val;
@@ -139,7 +128,7 @@ static void spi100k_write_data(struct spi_master *master, int len, int data)
139 } 128 }
140 129
141 spi100k_enable_clock(master); 130 spi100k_enable_clock(master);
142 writew( data , spi100k->base + SPI_TX_MSB); 131 writew(data , spi100k->base + SPI_TX_MSB);
143 132
144 writew(SPI_CTRL_SEN(0) | 133 writew(SPI_CTRL_SEN(0) |
145 SPI_CTRL_WORD_SIZE(len) | 134 SPI_CTRL_WORD_SIZE(len) |
@@ -147,7 +136,8 @@ static void spi100k_write_data(struct spi_master *master, int len, int data)
147 spi100k->base + SPI_CTRL); 136 spi100k->base + SPI_CTRL);
148 137
149 /* Wait for bit ack send change */ 138 /* Wait for bit ack send change */
150 while((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_WE) != SPI_STATUS_WE); 139 while ((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_WE) != SPI_STATUS_WE)
140 ;
151 udelay(1000); 141 udelay(1000);
152 142
153 spi100k_disable_clock(master); 143 spi100k_disable_clock(master);
@@ -155,7 +145,7 @@ static void spi100k_write_data(struct spi_master *master, int len, int data)
155 145
156static int spi100k_read_data(struct spi_master *master, int len) 146static int spi100k_read_data(struct spi_master *master, int len)
157{ 147{
158 int dataH,dataL; 148 int dataH, dataL;
159 struct omap1_spi100k *spi100k = spi_master_get_devdata(master); 149 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
160 150
161 /* Always do at least 16 bits */ 151 /* Always do at least 16 bits */
@@ -168,7 +158,8 @@ static int spi100k_read_data(struct spi_master *master, int len)
168 SPI_CTRL_RD, 158 SPI_CTRL_RD,
169 spi100k->base + SPI_CTRL); 159 spi100k->base + SPI_CTRL);
170 160
171 while((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_RD) != SPI_STATUS_RD); 161 while ((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_RD) != SPI_STATUS_RD)
162 ;
172 udelay(1000); 163 udelay(1000);
173 164
174 dataL = readw(spi100k->base + SPI_RX_LSB); 165 dataL = readw(spi100k->base + SPI_RX_LSB);
@@ -204,12 +195,10 @@ static void omap1_spi100k_force_cs(struct omap1_spi100k *spi100k, int enable)
204static unsigned 195static unsigned
205omap1_spi100k_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) 196omap1_spi100k_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
206{ 197{
207 struct omap1_spi100k *spi100k;
208 struct omap1_spi100k_cs *cs = spi->controller_state; 198 struct omap1_spi100k_cs *cs = spi->controller_state;
209 unsigned int count, c; 199 unsigned int count, c;
210 int word_len; 200 int word_len;
211 201
212 spi100k = spi_master_get_devdata(spi->master);
213 count = xfer->len; 202 count = xfer->len;
214 c = count; 203 c = count;
215 word_len = cs->word_len; 204 word_len = cs->word_len;
@@ -221,12 +210,12 @@ omap1_spi100k_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
221 rx = xfer->rx_buf; 210 rx = xfer->rx_buf;
222 tx = xfer->tx_buf; 211 tx = xfer->tx_buf;
223 do { 212 do {
224 c-=1; 213 c -= 1;
225 if (xfer->tx_buf != NULL) 214 if (xfer->tx_buf != NULL)
226 spi100k_write_data(spi->master, word_len, *tx++); 215 spi100k_write_data(spi->master, word_len, *tx++);
227 if (xfer->rx_buf != NULL) 216 if (xfer->rx_buf != NULL)
228 *rx++ = spi100k_read_data(spi->master, word_len); 217 *rx++ = spi100k_read_data(spi->master, word_len);
229 } while(c); 218 } while (c);
230 } else if (word_len <= 16) { 219 } else if (word_len <= 16) {
231 u16 *rx; 220 u16 *rx;
232 const u16 *tx; 221 const u16 *tx;
@@ -234,12 +223,12 @@ omap1_spi100k_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
234 rx = xfer->rx_buf; 223 rx = xfer->rx_buf;
235 tx = xfer->tx_buf; 224 tx = xfer->tx_buf;
236 do { 225 do {
237 c-=2; 226 c -= 2;
238 if (xfer->tx_buf != NULL) 227 if (xfer->tx_buf != NULL)
239 spi100k_write_data(spi->master,word_len, *tx++); 228 spi100k_write_data(spi->master, word_len, *tx++);
240 if (xfer->rx_buf != NULL) 229 if (xfer->rx_buf != NULL)
241 *rx++ = spi100k_read_data(spi->master,word_len); 230 *rx++ = spi100k_read_data(spi->master, word_len);
242 } while(c); 231 } while (c);
243 } else if (word_len <= 32) { 232 } else if (word_len <= 32) {
244 u32 *rx; 233 u32 *rx;
245 const u32 *tx; 234 const u32 *tx;
@@ -247,12 +236,12 @@ omap1_spi100k_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
247 rx = xfer->rx_buf; 236 rx = xfer->rx_buf;
248 tx = xfer->tx_buf; 237 tx = xfer->tx_buf;
249 do { 238 do {
250 c-=4; 239 c -= 4;
251 if (xfer->tx_buf != NULL) 240 if (xfer->tx_buf != NULL)
252 spi100k_write_data(spi->master,word_len, *tx); 241 spi100k_write_data(spi->master, word_len, *tx);
253 if (xfer->rx_buf != NULL) 242 if (xfer->rx_buf != NULL)
254 *rx = spi100k_read_data(spi->master,word_len); 243 *rx = spi100k_read_data(spi->master, word_len);
255 } while(c); 244 } while (c);
256 } 245 }
257 return count - c; 246 return count - c;
258} 247}
@@ -294,7 +283,7 @@ static int omap1_spi100k_setup(struct spi_device *spi)
294 spi100k = spi_master_get_devdata(spi->master); 283 spi100k = spi_master_get_devdata(spi->master);
295 284
296 if (!cs) { 285 if (!cs) {
297 cs = kzalloc(sizeof *cs, GFP_KERNEL); 286 cs = devm_kzalloc(&spi->dev, sizeof(*cs), GFP_KERNEL);
298 if (!cs) 287 if (!cs)
299 return -ENOMEM; 288 return -ENOMEM;
300 cs->base = spi100k->base + spi->chip_select * 0x14; 289 cs->base = spi100k->base + spi->chip_select * 0x14;
@@ -411,14 +400,14 @@ static int omap1_spi100k_probe(struct platform_device *pdev)
411 if (!pdev->id) 400 if (!pdev->id)
412 return -EINVAL; 401 return -EINVAL;
413 402
414 master = spi_alloc_master(&pdev->dev, sizeof *spi100k); 403 master = spi_alloc_master(&pdev->dev, sizeof(*spi100k));
415 if (master == NULL) { 404 if (master == NULL) {
416 dev_dbg(&pdev->dev, "master allocation failed\n"); 405 dev_dbg(&pdev->dev, "master allocation failed\n");
417 return -ENOMEM; 406 return -ENOMEM;
418 } 407 }
419 408
420 if (pdev->id != -1) 409 if (pdev->id != -1)
421 master->bus_num = pdev->id; 410 master->bus_num = pdev->id;
422 411
423 master->setup = omap1_spi100k_setup; 412 master->setup = omap1_spi100k_setup;
424 master->transfer_one_message = omap1_spi100k_transfer_one_message; 413 master->transfer_one_message = omap1_spi100k_transfer_one_message;
@@ -434,7 +423,6 @@ static int omap1_spi100k_probe(struct platform_device *pdev)
434 platform_set_drvdata(pdev, master); 423 platform_set_drvdata(pdev, master);
435 424
436 spi100k = spi_master_get_devdata(master); 425 spi100k = spi_master_get_devdata(master);
437 spi100k->master = master;
438 426
439 /* 427 /*
440 * The memory region base address is taken as the platform_data. 428 * The memory region base address is taken as the platform_data.
@@ -461,8 +449,6 @@ static int omap1_spi100k_probe(struct platform_device *pdev)
461 if (status < 0) 449 if (status < 0)
462 goto err; 450 goto err;
463 451
464 spi100k->state = SPI_RUNNING;
465
466 return status; 452 return status;
467 453
468err: 454err:
diff --git a/drivers/spi/spi-omap-uwire.c b/drivers/spi/spi-omap-uwire.c
index 8062909b9f5e..be2a2e108e2f 100644
--- a/drivers/spi/spi-omap-uwire.c
+++ b/drivers/spi/spi-omap-uwire.c
@@ -99,7 +99,6 @@ struct uwire_spi {
99}; 99};
100 100
101struct uwire_state { 101struct uwire_state {
102 unsigned bits_per_word;
103 unsigned div1_idx; 102 unsigned div1_idx;
104}; 103};
105 104
@@ -210,9 +209,8 @@ static void uwire_chipselect(struct spi_device *spi, int value)
210 209
211static int uwire_txrx(struct spi_device *spi, struct spi_transfer *t) 210static int uwire_txrx(struct spi_device *spi, struct spi_transfer *t)
212{ 211{
213 struct uwire_state *ust = spi->controller_state;
214 unsigned len = t->len; 212 unsigned len = t->len;
215 unsigned bits = ust->bits_per_word; 213 unsigned bits = t->bits_per_word ? : spi->bits_per_word;
216 unsigned bytes; 214 unsigned bytes;
217 u16 val, w; 215 u16 val, w;
218 int status = 0; 216 int status = 0;
@@ -220,10 +218,6 @@ static int uwire_txrx(struct spi_device *spi, struct spi_transfer *t)
220 if (!t->tx_buf && !t->rx_buf) 218 if (!t->tx_buf && !t->rx_buf)
221 return 0; 219 return 0;
222 220
223 /* Microwire doesn't read and write concurrently */
224 if (t->tx_buf && t->rx_buf)
225 return -EPERM;
226
227 w = spi->chip_select << 10; 221 w = spi->chip_select << 10;
228 w |= CS_CMD; 222 w |= CS_CMD;
229 223
@@ -322,7 +316,6 @@ static int uwire_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
322 struct uwire_state *ust = spi->controller_state; 316 struct uwire_state *ust = spi->controller_state;
323 struct uwire_spi *uwire; 317 struct uwire_spi *uwire;
324 unsigned flags = 0; 318 unsigned flags = 0;
325 unsigned bits;
326 unsigned hz; 319 unsigned hz;
327 unsigned long rate; 320 unsigned long rate;
328 int div1_idx; 321 int div1_idx;
@@ -332,17 +325,6 @@ static int uwire_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
332 325
333 uwire = spi_master_get_devdata(spi->master); 326 uwire = spi_master_get_devdata(spi->master);
334 327
335 bits = spi->bits_per_word;
336 if (t != NULL && t->bits_per_word)
337 bits = t->bits_per_word;
338
339 if (bits > 16) {
340 pr_debug("%s: wordsize %d?\n", dev_name(&spi->dev), bits);
341 status = -ENODEV;
342 goto done;
343 }
344 ust->bits_per_word = bits;
345
346 /* mode 0..3, clock inverted separately; 328 /* mode 0..3, clock inverted separately;
347 * standard nCS signaling; 329 * standard nCS signaling;
348 * don't treat DI=high as "not ready" 330 * don't treat DI=high as "not ready"
@@ -496,6 +478,7 @@ static int uwire_probe(struct platform_device *pdev)
496 status = PTR_ERR(uwire->ck); 478 status = PTR_ERR(uwire->ck);
497 dev_dbg(&pdev->dev, "no functional clock?\n"); 479 dev_dbg(&pdev->dev, "no functional clock?\n");
498 spi_master_put(master); 480 spi_master_put(master);
481 iounmap(uwire_base);
499 return status; 482 return status;
500 } 483 }
501 clk_enable(uwire->ck); 484 clk_enable(uwire->ck);
@@ -509,7 +492,7 @@ static int uwire_probe(struct platform_device *pdev)
509 492
510 /* the spi->mode bits understood by this driver: */ 493 /* the spi->mode bits understood by this driver: */
511 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 494 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
512 495 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 16);
513 master->flags = SPI_MASTER_HALF_DUPLEX; 496 master->flags = SPI_MASTER_HALF_DUPLEX;
514 497
515 master->bus_num = 2; /* "official" */ 498 master->bus_num = 2; /* "official" */
diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c
index 94f133cb2770..2941c5b96ebc 100644
--- a/drivers/spi/spi-omap2-mcspi.c
+++ b/drivers/spi/spi-omap2-mcspi.c
@@ -44,6 +44,7 @@
44#include <linux/platform_data/spi-omap2-mcspi.h> 44#include <linux/platform_data/spi-omap2-mcspi.h>
45 45
46#define OMAP2_MCSPI_MAX_FREQ 48000000 46#define OMAP2_MCSPI_MAX_FREQ 48000000
47#define OMAP2_MCSPI_MAX_DIVIDER 4096
47#define OMAP2_MCSPI_MAX_FIFODEPTH 64 48#define OMAP2_MCSPI_MAX_FIFODEPTH 64
48#define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF 49#define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF
49#define SPI_AUTOSUSPEND_TIMEOUT 2000 50#define SPI_AUTOSUSPEND_TIMEOUT 2000
@@ -88,6 +89,7 @@
88#define OMAP2_MCSPI_CHCONF_FORCE BIT(20) 89#define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
89#define OMAP2_MCSPI_CHCONF_FFET BIT(27) 90#define OMAP2_MCSPI_CHCONF_FFET BIT(27)
90#define OMAP2_MCSPI_CHCONF_FFER BIT(28) 91#define OMAP2_MCSPI_CHCONF_FFER BIT(28)
92#define OMAP2_MCSPI_CHCONF_CLKG BIT(29)
91 93
92#define OMAP2_MCSPI_CHSTAT_RXS BIT(0) 94#define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
93#define OMAP2_MCSPI_CHSTAT_TXS BIT(1) 95#define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
@@ -95,6 +97,7 @@
95#define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3) 97#define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3)
96 98
97#define OMAP2_MCSPI_CHCTRL_EN BIT(0) 99#define OMAP2_MCSPI_CHCTRL_EN BIT(0)
100#define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK (0xff << 8)
98 101
99#define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0) 102#define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
100 103
@@ -148,7 +151,7 @@ struct omap2_mcspi_cs {
148 int word_len; 151 int word_len;
149 struct list_head node; 152 struct list_head node;
150 /* Context save and restore shadow register */ 153 /* Context save and restore shadow register */
151 u32 chconf0; 154 u32 chconf0, chctrl0;
152}; 155};
153 156
154static inline void mcspi_write_reg(struct spi_master *master, 157static inline void mcspi_write_reg(struct spi_master *master,
@@ -229,10 +232,16 @@ static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
229 232
230static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) 233static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
231{ 234{
235 struct omap2_mcspi_cs *cs = spi->controller_state;
232 u32 l; 236 u32 l;
233 237
234 l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0; 238 l = cs->chctrl0;
235 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l); 239 if (enable)
240 l |= OMAP2_MCSPI_CHCTRL_EN;
241 else
242 l &= ~OMAP2_MCSPI_CHCTRL_EN;
243 cs->chctrl0 = l;
244 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
236 /* Flash post-writes */ 245 /* Flash post-writes */
237 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0); 246 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
238} 247}
@@ -839,7 +848,7 @@ static int omap2_mcspi_setup_transfer(struct spi_device *spi,
839 struct omap2_mcspi_cs *cs = spi->controller_state; 848 struct omap2_mcspi_cs *cs = spi->controller_state;
840 struct omap2_mcspi *mcspi; 849 struct omap2_mcspi *mcspi;
841 struct spi_master *spi_cntrl; 850 struct spi_master *spi_cntrl;
842 u32 l = 0, div = 0; 851 u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0;
843 u8 word_len = spi->bits_per_word; 852 u8 word_len = spi->bits_per_word;
844 u32 speed_hz = spi->max_speed_hz; 853 u32 speed_hz = spi->max_speed_hz;
845 854
@@ -855,7 +864,17 @@ static int omap2_mcspi_setup_transfer(struct spi_device *spi,
855 speed_hz = t->speed_hz; 864 speed_hz = t->speed_hz;
856 865
857 speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ); 866 speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
858 div = omap2_mcspi_calc_divisor(speed_hz); 867 if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) {
868 clkd = omap2_mcspi_calc_divisor(speed_hz);
869 speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd;
870 clkg = 0;
871 } else {
872 div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz;
873 speed_hz = OMAP2_MCSPI_MAX_FREQ / div;
874 clkd = (div - 1) & 0xf;
875 extclk = (div - 1) >> 4;
876 clkg = OMAP2_MCSPI_CHCONF_CLKG;
877 }
859 878
860 l = mcspi_cached_chconf0(spi); 879 l = mcspi_cached_chconf0(spi);
861 880
@@ -884,7 +903,16 @@ static int omap2_mcspi_setup_transfer(struct spi_device *spi,
884 903
885 /* set clock divisor */ 904 /* set clock divisor */
886 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK; 905 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
887 l |= div << 2; 906 l |= clkd << 2;
907
908 /* set clock granularity */
909 l &= ~OMAP2_MCSPI_CHCONF_CLKG;
910 l |= clkg;
911 if (clkg) {
912 cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK;
913 cs->chctrl0 |= extclk << 8;
914 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
915 }
888 916
889 /* set SPI mode 0..3 */ 917 /* set SPI mode 0..3 */
890 if (spi->mode & SPI_CPOL) 918 if (spi->mode & SPI_CPOL)
@@ -899,7 +927,7 @@ static int omap2_mcspi_setup_transfer(struct spi_device *spi,
899 mcspi_write_chconf0(spi, l); 927 mcspi_write_chconf0(spi, l);
900 928
901 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", 929 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
902 OMAP2_MCSPI_MAX_FREQ >> div, 930 speed_hz,
903 (spi->mode & SPI_CPHA) ? "trailing" : "leading", 931 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
904 (spi->mode & SPI_CPOL) ? "inverted" : "normal"); 932 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
905 933
@@ -971,6 +999,7 @@ static int omap2_mcspi_setup(struct spi_device *spi)
971 cs->base = mcspi->base + spi->chip_select * 0x14; 999 cs->base = mcspi->base + spi->chip_select * 0x14;
972 cs->phys = mcspi->phys + spi->chip_select * 0x14; 1000 cs->phys = mcspi->phys + spi->chip_select * 0x14;
973 cs->chconf0 = 0; 1001 cs->chconf0 = 0;
1002 cs->chctrl0 = 0;
974 spi->controller_state = cs; 1003 spi->controller_state = cs;
975 /* Link this to context save list */ 1004 /* Link this to context save list */
976 list_add_tail(&cs->node, &ctx->cs); 1005 list_add_tail(&cs->node, &ctx->cs);
@@ -1056,12 +1085,15 @@ static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
1056 status = -EINVAL; 1085 status = -EINVAL;
1057 break; 1086 break;
1058 } 1087 }
1059 if (par_override || t->speed_hz || t->bits_per_word) { 1088 if (par_override ||
1089 (t->speed_hz != spi->max_speed_hz) ||
1090 (t->bits_per_word != spi->bits_per_word)) {
1060 par_override = 1; 1091 par_override = 1;
1061 status = omap2_mcspi_setup_transfer(spi, t); 1092 status = omap2_mcspi_setup_transfer(spi, t);
1062 if (status < 0) 1093 if (status < 0)
1063 break; 1094 break;
1064 if (!t->speed_hz && !t->bits_per_word) 1095 if (t->speed_hz == spi->max_speed_hz &&
1096 t->bits_per_word == spi->bits_per_word)
1065 par_override = 0; 1097 par_override = 0;
1066 } 1098 }
1067 if (cd && cd->cs_per_word) { 1099 if (cd && cd->cs_per_word) {
@@ -1175,16 +1207,12 @@ static int omap2_mcspi_transfer_one_message(struct spi_master *master,
1175 m->actual_length = 0; 1207 m->actual_length = 0;
1176 m->status = 0; 1208 m->status = 0;
1177 1209
1178 /* reject invalid messages and transfers */
1179 if (list_empty(&m->transfers))
1180 return -EINVAL;
1181 list_for_each_entry(t, &m->transfers, transfer_list) { 1210 list_for_each_entry(t, &m->transfers, transfer_list) {
1182 const void *tx_buf = t->tx_buf; 1211 const void *tx_buf = t->tx_buf;
1183 void *rx_buf = t->rx_buf; 1212 void *rx_buf = t->rx_buf;
1184 unsigned len = t->len; 1213 unsigned len = t->len;
1185 1214
1186 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ 1215 if ((len && !(rx_buf || tx_buf))) {
1187 || (len && !(rx_buf || tx_buf))) {
1188 dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n", 1216 dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
1189 t->speed_hz, 1217 t->speed_hz,
1190 len, 1218 len,
@@ -1193,12 +1221,6 @@ static int omap2_mcspi_transfer_one_message(struct spi_master *master,
1193 t->bits_per_word); 1221 t->bits_per_word);
1194 return -EINVAL; 1222 return -EINVAL;
1195 } 1223 }
1196 if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) {
1197 dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n",
1198 t->speed_hz,
1199 OMAP2_MCSPI_MAX_FREQ >> 15);
1200 return -EINVAL;
1201 }
1202 1224
1203 if (m->is_dma_mapped || len < DMA_MIN_BYTES) 1225 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
1204 continue; 1226 continue;
@@ -1310,6 +1332,8 @@ static int omap2_mcspi_probe(struct platform_device *pdev)
1310 master->transfer_one_message = omap2_mcspi_transfer_one_message; 1332 master->transfer_one_message = omap2_mcspi_transfer_one_message;
1311 master->cleanup = omap2_mcspi_cleanup; 1333 master->cleanup = omap2_mcspi_cleanup;
1312 master->dev.of_node = node; 1334 master->dev.of_node = node;
1335 master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ;
1336 master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15;
1313 1337
1314 platform_set_drvdata(pdev, master); 1338 platform_set_drvdata(pdev, master);
1315 1339
diff --git a/drivers/spi/spi-orion.c b/drivers/spi/spi-orion.c
index a362425400ea..d018a4aac3a1 100644
--- a/drivers/spi/spi-orion.c
+++ b/drivers/spi/spi-orion.c
@@ -42,8 +42,6 @@
42struct orion_spi { 42struct orion_spi {
43 struct spi_master *master; 43 struct spi_master *master;
44 void __iomem *base; 44 void __iomem *base;
45 unsigned int max_speed;
46 unsigned int min_speed;
47 struct clk *clk; 45 struct clk *clk;
48}; 46};
49 47
@@ -74,23 +72,6 @@ orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
74 writel(val, reg_addr); 72 writel(val, reg_addr);
75} 73}
76 74
77static int orion_spi_set_transfer_size(struct orion_spi *orion_spi, int size)
78{
79 if (size == 16) {
80 orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
81 ORION_SPI_IF_8_16_BIT_MODE);
82 } else if (size == 8) {
83 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
84 ORION_SPI_IF_8_16_BIT_MODE);
85 } else {
86 pr_debug("Bad bits per word value %d (only 8 or 16 are allowed).\n",
87 size);
88 return -EINVAL;
89 }
90
91 return 0;
92}
93
94static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed) 75static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
95{ 76{
96 u32 tclk_hz; 77 u32 tclk_hz;
@@ -169,7 +150,14 @@ orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
169 if (rc) 150 if (rc)
170 return rc; 151 return rc;
171 152
172 return orion_spi_set_transfer_size(orion_spi, bits_per_word); 153 if (bits_per_word == 16)
154 orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
155 ORION_SPI_IF_8_16_BIT_MODE);
156 else
157 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
158 ORION_SPI_IF_8_16_BIT_MODE);
159
160 return 0;
173} 161}
174 162
175static void orion_spi_set_cs(struct orion_spi *orion_spi, int enable) 163static void orion_spi_set_cs(struct orion_spi *orion_spi, int enable)
@@ -259,11 +247,9 @@ orion_spi_write_read_16bit(struct spi_device *spi,
259static unsigned int 247static unsigned int
260orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer) 248orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
261{ 249{
262 struct orion_spi *orion_spi;
263 unsigned int count; 250 unsigned int count;
264 int word_len; 251 int word_len;
265 252
266 orion_spi = spi_master_get_devdata(spi->master);
267 word_len = spi->bits_per_word; 253 word_len = spi->bits_per_word;
268 count = xfer->len; 254 count = xfer->len;
269 255
@@ -309,27 +295,6 @@ static int orion_spi_transfer_one_message(struct spi_master *master,
309 goto msg_done; 295 goto msg_done;
310 296
311 list_for_each_entry(t, &m->transfers, transfer_list) { 297 list_for_each_entry(t, &m->transfers, transfer_list) {
312 /* make sure buffer length is even when working in 16
313 * bit mode*/
314 if ((t->bits_per_word == 16) && (t->len & 1)) {
315 dev_err(&spi->dev,
316 "message rejected : "
317 "odd data length %d while in 16 bit mode\n",
318 t->len);
319 status = -EIO;
320 goto msg_done;
321 }
322
323 if (t->speed_hz && t->speed_hz < orion_spi->min_speed) {
324 dev_err(&spi->dev,
325 "message rejected : "
326 "device min speed (%d Hz) exceeds "
327 "required transfer speed (%d Hz)\n",
328 orion_spi->min_speed, t->speed_hz);
329 status = -EIO;
330 goto msg_done;
331 }
332
333 if (par_override || t->speed_hz || t->bits_per_word) { 298 if (par_override || t->speed_hz || t->bits_per_word) {
334 par_override = 1; 299 par_override = 1;
335 status = orion_spi_setup_transfer(spi, t); 300 status = orion_spi_setup_transfer(spi, t);
@@ -374,28 +339,6 @@ static int orion_spi_reset(struct orion_spi *orion_spi)
374 return 0; 339 return 0;
375} 340}
376 341
377static int orion_spi_setup(struct spi_device *spi)
378{
379 struct orion_spi *orion_spi;
380
381 orion_spi = spi_master_get_devdata(spi->master);
382
383 if ((spi->max_speed_hz == 0)
384 || (spi->max_speed_hz > orion_spi->max_speed))
385 spi->max_speed_hz = orion_spi->max_speed;
386
387 if (spi->max_speed_hz < orion_spi->min_speed) {
388 dev_err(&spi->dev, "setup: requested speed too low %d Hz\n",
389 spi->max_speed_hz);
390 return -EINVAL;
391 }
392
393 /*
394 * baudrate & width will be set orion_spi_setup_transfer
395 */
396 return 0;
397}
398
399static int orion_spi_probe(struct platform_device *pdev) 342static int orion_spi_probe(struct platform_device *pdev)
400{ 343{
401 struct spi_master *master; 344 struct spi_master *master;
@@ -424,9 +367,9 @@ static int orion_spi_probe(struct platform_device *pdev)
424 /* we support only mode 0, and no options */ 367 /* we support only mode 0, and no options */
425 master->mode_bits = SPI_CPHA | SPI_CPOL; 368 master->mode_bits = SPI_CPHA | SPI_CPOL;
426 369
427 master->setup = orion_spi_setup;
428 master->transfer_one_message = orion_spi_transfer_one_message; 370 master->transfer_one_message = orion_spi_transfer_one_message;
429 master->num_chipselect = ORION_NUM_CHIPSELECTS; 371 master->num_chipselect = ORION_NUM_CHIPSELECTS;
372 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
430 373
431 platform_set_drvdata(pdev, master); 374 platform_set_drvdata(pdev, master);
432 375
@@ -442,8 +385,8 @@ static int orion_spi_probe(struct platform_device *pdev)
442 clk_prepare(spi->clk); 385 clk_prepare(spi->clk);
443 clk_enable(spi->clk); 386 clk_enable(spi->clk);
444 tclk_hz = clk_get_rate(spi->clk); 387 tclk_hz = clk_get_rate(spi->clk);
445 spi->max_speed = DIV_ROUND_UP(tclk_hz, 4); 388 master->max_speed_hz = DIV_ROUND_UP(tclk_hz, 4);
446 spi->min_speed = DIV_ROUND_UP(tclk_hz, 30); 389 master->min_speed_hz = DIV_ROUND_UP(tclk_hz, 30);
447 390
448 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 391 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
449 spi->base = devm_ioremap_resource(&pdev->dev, r); 392 spi->base = devm_ioremap_resource(&pdev->dev, r);
diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c
index 3c5b90559bec..51d99779682f 100644
--- a/drivers/spi/spi-pl022.c
+++ b/drivers/spi/spi-pl022.c
@@ -2108,8 +2108,6 @@ static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
2108 pl022->chipselects = devm_kzalloc(dev, num_cs * sizeof(int), 2108 pl022->chipselects = devm_kzalloc(dev, num_cs * sizeof(int),
2109 GFP_KERNEL); 2109 GFP_KERNEL);
2110 2110
2111 pinctrl_pm_select_default_state(dev);
2112
2113 /* 2111 /*
2114 * Bus Number Which has been Assigned to this SSP controller 2112 * Bus Number Which has been Assigned to this SSP controller
2115 * on this board 2113 * on this board
@@ -2182,13 +2180,7 @@ static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
2182 goto err_no_clk; 2180 goto err_no_clk;
2183 } 2181 }
2184 2182
2185 status = clk_prepare(pl022->clk); 2183 status = clk_prepare_enable(pl022->clk);
2186 if (status) {
2187 dev_err(&adev->dev, "could not prepare SSP/SPI bus clock\n");
2188 goto err_clk_prep;
2189 }
2190
2191 status = clk_enable(pl022->clk);
2192 if (status) { 2184 if (status) {
2193 dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n"); 2185 dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n");
2194 goto err_no_clk_en; 2186 goto err_no_clk_en;
@@ -2249,10 +2241,8 @@ static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
2249 if (platform_info->enable_dma) 2241 if (platform_info->enable_dma)
2250 pl022_dma_remove(pl022); 2242 pl022_dma_remove(pl022);
2251 err_no_irq: 2243 err_no_irq:
2252 clk_disable(pl022->clk); 2244 clk_disable_unprepare(pl022->clk);
2253 err_no_clk_en: 2245 err_no_clk_en:
2254 clk_unprepare(pl022->clk);
2255 err_clk_prep:
2256 err_no_clk: 2246 err_no_clk:
2257 err_no_ioremap: 2247 err_no_ioremap:
2258 amba_release_regions(adev); 2248 amba_release_regions(adev);
@@ -2280,42 +2270,13 @@ pl022_remove(struct amba_device *adev)
2280 if (pl022->master_info->enable_dma) 2270 if (pl022->master_info->enable_dma)
2281 pl022_dma_remove(pl022); 2271 pl022_dma_remove(pl022);
2282 2272
2283 clk_disable(pl022->clk); 2273 clk_disable_unprepare(pl022->clk);
2284 clk_unprepare(pl022->clk);
2285 amba_release_regions(adev); 2274 amba_release_regions(adev);
2286 tasklet_disable(&pl022->pump_transfers); 2275 tasklet_disable(&pl022->pump_transfers);
2287 return 0; 2276 return 0;
2288} 2277}
2289 2278
2290#if defined(CONFIG_SUSPEND) || defined(CONFIG_PM_RUNTIME) 2279#ifdef CONFIG_PM_SLEEP
2291/*
2292 * These two functions are used from both suspend/resume and
2293 * the runtime counterparts to handle external resources like
2294 * clocks, pins and regulators when going to sleep.
2295 */
2296static void pl022_suspend_resources(struct pl022 *pl022, bool runtime)
2297{
2298 clk_disable(pl022->clk);
2299
2300 if (runtime)
2301 pinctrl_pm_select_idle_state(&pl022->adev->dev);
2302 else
2303 pinctrl_pm_select_sleep_state(&pl022->adev->dev);
2304}
2305
2306static void pl022_resume_resources(struct pl022 *pl022, bool runtime)
2307{
2308 /* First go to the default state */
2309 pinctrl_pm_select_default_state(&pl022->adev->dev);
2310 if (!runtime)
2311 /* Then let's idle the pins until the next transfer happens */
2312 pinctrl_pm_select_idle_state(&pl022->adev->dev);
2313
2314 clk_enable(pl022->clk);
2315}
2316#endif
2317
2318#ifdef CONFIG_SUSPEND
2319static int pl022_suspend(struct device *dev) 2280static int pl022_suspend(struct device *dev)
2320{ 2281{
2321 struct pl022 *pl022 = dev_get_drvdata(dev); 2282 struct pl022 *pl022 = dev_get_drvdata(dev);
@@ -2327,8 +2288,13 @@ static int pl022_suspend(struct device *dev)
2327 return ret; 2288 return ret;
2328 } 2289 }
2329 2290
2330 pm_runtime_get_sync(dev); 2291 ret = pm_runtime_force_suspend(dev);
2331 pl022_suspend_resources(pl022, false); 2292 if (ret) {
2293 spi_master_resume(pl022->master);
2294 return ret;
2295 }
2296
2297 pinctrl_pm_select_sleep_state(dev);
2332 2298
2333 dev_dbg(dev, "suspended\n"); 2299 dev_dbg(dev, "suspended\n");
2334 return 0; 2300 return 0;
@@ -2339,8 +2305,9 @@ static int pl022_resume(struct device *dev)
2339 struct pl022 *pl022 = dev_get_drvdata(dev); 2305 struct pl022 *pl022 = dev_get_drvdata(dev);
2340 int ret; 2306 int ret;
2341 2307
2342 pl022_resume_resources(pl022, false); 2308 ret = pm_runtime_force_resume(dev);
2343 pm_runtime_put(dev); 2309 if (ret)
2310 dev_err(dev, "problem resuming\n");
2344 2311
2345 /* Start the queue running */ 2312 /* Start the queue running */
2346 ret = spi_master_resume(pl022->master); 2313 ret = spi_master_resume(pl022->master);
@@ -2351,14 +2318,16 @@ static int pl022_resume(struct device *dev)
2351 2318
2352 return ret; 2319 return ret;
2353} 2320}
2354#endif /* CONFIG_PM */ 2321#endif
2355 2322
2356#ifdef CONFIG_PM_RUNTIME 2323#ifdef CONFIG_PM
2357static int pl022_runtime_suspend(struct device *dev) 2324static int pl022_runtime_suspend(struct device *dev)
2358{ 2325{
2359 struct pl022 *pl022 = dev_get_drvdata(dev); 2326 struct pl022 *pl022 = dev_get_drvdata(dev);
2360 2327
2361 pl022_suspend_resources(pl022, true); 2328 clk_disable_unprepare(pl022->clk);
2329 pinctrl_pm_select_idle_state(dev);
2330
2362 return 0; 2331 return 0;
2363} 2332}
2364 2333
@@ -2366,14 +2335,16 @@ static int pl022_runtime_resume(struct device *dev)
2366{ 2335{
2367 struct pl022 *pl022 = dev_get_drvdata(dev); 2336 struct pl022 *pl022 = dev_get_drvdata(dev);
2368 2337
2369 pl022_resume_resources(pl022, true); 2338 pinctrl_pm_select_default_state(dev);
2339 clk_prepare_enable(pl022->clk);
2340
2370 return 0; 2341 return 0;
2371} 2342}
2372#endif 2343#endif
2373 2344
2374static const struct dev_pm_ops pl022_dev_pm_ops = { 2345static const struct dev_pm_ops pl022_dev_pm_ops = {
2375 SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume) 2346 SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume)
2376 SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL) 2347 SET_PM_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL)
2377}; 2348};
2378 2349
2379static struct vendor_data vendor_arm = { 2350static struct vendor_data vendor_arm = {
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
new file mode 100644
index 000000000000..b032e8885e24
--- /dev/null
+++ b/drivers/spi/spi-qup.c
@@ -0,0 +1,779 @@
1/*
2 * Copyright (c) 2008-2014, The Linux foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License rev 2 and
6 * only rev 2 as published by the free Software foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/clk.h>
15#include <linux/delay.h>
16#include <linux/err.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/list.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/platform_device.h>
23#include <linux/pm_runtime.h>
24#include <linux/spi/spi.h>
25
26#define QUP_CONFIG 0x0000
27#define QUP_STATE 0x0004
28#define QUP_IO_M_MODES 0x0008
29#define QUP_SW_RESET 0x000c
30#define QUP_OPERATIONAL 0x0018
31#define QUP_ERROR_FLAGS 0x001c
32#define QUP_ERROR_FLAGS_EN 0x0020
33#define QUP_OPERATIONAL_MASK 0x0028
34#define QUP_HW_VERSION 0x0030
35#define QUP_MX_OUTPUT_CNT 0x0100
36#define QUP_OUTPUT_FIFO 0x0110
37#define QUP_MX_WRITE_CNT 0x0150
38#define QUP_MX_INPUT_CNT 0x0200
39#define QUP_MX_READ_CNT 0x0208
40#define QUP_INPUT_FIFO 0x0218
41
42#define SPI_CONFIG 0x0300
43#define SPI_IO_CONTROL 0x0304
44#define SPI_ERROR_FLAGS 0x0308
45#define SPI_ERROR_FLAGS_EN 0x030c
46
47/* QUP_CONFIG fields */
48#define QUP_CONFIG_SPI_MODE (1 << 8)
49#define QUP_CONFIG_CLOCK_AUTO_GATE BIT(13)
50#define QUP_CONFIG_NO_INPUT BIT(7)
51#define QUP_CONFIG_NO_OUTPUT BIT(6)
52#define QUP_CONFIG_N 0x001f
53
54/* QUP_STATE fields */
55#define QUP_STATE_VALID BIT(2)
56#define QUP_STATE_RESET 0
57#define QUP_STATE_RUN 1
58#define QUP_STATE_PAUSE 3
59#define QUP_STATE_MASK 3
60#define QUP_STATE_CLEAR 2
61
62#define QUP_HW_VERSION_2_1_1 0x20010001
63
64/* QUP_IO_M_MODES fields */
65#define QUP_IO_M_PACK_EN BIT(15)
66#define QUP_IO_M_UNPACK_EN BIT(14)
67#define QUP_IO_M_INPUT_MODE_MASK_SHIFT 12
68#define QUP_IO_M_OUTPUT_MODE_MASK_SHIFT 10
69#define QUP_IO_M_INPUT_MODE_MASK (3 << QUP_IO_M_INPUT_MODE_MASK_SHIFT)
70#define QUP_IO_M_OUTPUT_MODE_MASK (3 << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT)
71
72#define QUP_IO_M_OUTPUT_BLOCK_SIZE(x) (((x) & (0x03 << 0)) >> 0)
73#define QUP_IO_M_OUTPUT_FIFO_SIZE(x) (((x) & (0x07 << 2)) >> 2)
74#define QUP_IO_M_INPUT_BLOCK_SIZE(x) (((x) & (0x03 << 5)) >> 5)
75#define QUP_IO_M_INPUT_FIFO_SIZE(x) (((x) & (0x07 << 7)) >> 7)
76
77#define QUP_IO_M_MODE_FIFO 0
78#define QUP_IO_M_MODE_BLOCK 1
79#define QUP_IO_M_MODE_DMOV 2
80#define QUP_IO_M_MODE_BAM 3
81
82/* QUP_OPERATIONAL fields */
83#define QUP_OP_MAX_INPUT_DONE_FLAG BIT(11)
84#define QUP_OP_MAX_OUTPUT_DONE_FLAG BIT(10)
85#define QUP_OP_IN_SERVICE_FLAG BIT(9)
86#define QUP_OP_OUT_SERVICE_FLAG BIT(8)
87#define QUP_OP_IN_FIFO_FULL BIT(7)
88#define QUP_OP_OUT_FIFO_FULL BIT(6)
89#define QUP_OP_IN_FIFO_NOT_EMPTY BIT(5)
90#define QUP_OP_OUT_FIFO_NOT_EMPTY BIT(4)
91
92/* QUP_ERROR_FLAGS and QUP_ERROR_FLAGS_EN fields */
93#define QUP_ERROR_OUTPUT_OVER_RUN BIT(5)
94#define QUP_ERROR_INPUT_UNDER_RUN BIT(4)
95#define QUP_ERROR_OUTPUT_UNDER_RUN BIT(3)
96#define QUP_ERROR_INPUT_OVER_RUN BIT(2)
97
98/* SPI_CONFIG fields */
99#define SPI_CONFIG_HS_MODE BIT(10)
100#define SPI_CONFIG_INPUT_FIRST BIT(9)
101#define SPI_CONFIG_LOOPBACK BIT(8)
102
103/* SPI_IO_CONTROL fields */
104#define SPI_IO_C_FORCE_CS BIT(11)
105#define SPI_IO_C_CLK_IDLE_HIGH BIT(10)
106#define SPI_IO_C_MX_CS_MODE BIT(8)
107#define SPI_IO_C_CS_N_POLARITY_0 BIT(4)
108#define SPI_IO_C_CS_SELECT(x) (((x) & 3) << 2)
109#define SPI_IO_C_CS_SELECT_MASK 0x000c
110#define SPI_IO_C_TRISTATE_CS BIT(1)
111#define SPI_IO_C_NO_TRI_STATE BIT(0)
112
113/* SPI_ERROR_FLAGS and SPI_ERROR_FLAGS_EN fields */
114#define SPI_ERROR_CLK_OVER_RUN BIT(1)
115#define SPI_ERROR_CLK_UNDER_RUN BIT(0)
116
117#define SPI_NUM_CHIPSELECTS 4
118
119/* high speed mode is when bus rate is greater then 26MHz */
120#define SPI_HS_MIN_RATE 26000000
121#define SPI_MAX_RATE 50000000
122
123#define SPI_DELAY_THRESHOLD 1
124#define SPI_DELAY_RETRY 10
125
126struct spi_qup {
127 void __iomem *base;
128 struct device *dev;
129 struct clk *cclk; /* core clock */
130 struct clk *iclk; /* interface clock */
131 int irq;
132 spinlock_t lock;
133
134 int in_fifo_sz;
135 int out_fifo_sz;
136 int in_blk_sz;
137 int out_blk_sz;
138
139 struct spi_transfer *xfer;
140 struct completion done;
141 int error;
142 int w_size; /* bytes per SPI word */
143 int tx_bytes;
144 int rx_bytes;
145};
146
147
148static inline bool spi_qup_is_valid_state(struct spi_qup *controller)
149{
150 u32 opstate = readl_relaxed(controller->base + QUP_STATE);
151
152 return opstate & QUP_STATE_VALID;
153}
154
155static int spi_qup_set_state(struct spi_qup *controller, u32 state)
156{
157 unsigned long loop;
158 u32 cur_state;
159
160 loop = 0;
161 while (!spi_qup_is_valid_state(controller)) {
162
163 usleep_range(SPI_DELAY_THRESHOLD, SPI_DELAY_THRESHOLD * 2);
164
165 if (++loop > SPI_DELAY_RETRY)
166 return -EIO;
167 }
168
169 if (loop)
170 dev_dbg(controller->dev, "invalid state for %ld,us %d\n",
171 loop, state);
172
173 cur_state = readl_relaxed(controller->base + QUP_STATE);
174 /*
175 * Per spec: for PAUSE_STATE to RESET_STATE, two writes
176 * of (b10) are required
177 */
178 if (((cur_state & QUP_STATE_MASK) == QUP_STATE_PAUSE) &&
179 (state == QUP_STATE_RESET)) {
180 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE);
181 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE);
182 } else {
183 cur_state &= ~QUP_STATE_MASK;
184 cur_state |= state;
185 writel_relaxed(cur_state, controller->base + QUP_STATE);
186 }
187
188 loop = 0;
189 while (!spi_qup_is_valid_state(controller)) {
190
191 usleep_range(SPI_DELAY_THRESHOLD, SPI_DELAY_THRESHOLD * 2);
192
193 if (++loop > SPI_DELAY_RETRY)
194 return -EIO;
195 }
196
197 return 0;
198}
199
200
201static void spi_qup_fifo_read(struct spi_qup *controller,
202 struct spi_transfer *xfer)
203{
204 u8 *rx_buf = xfer->rx_buf;
205 u32 word, state;
206 int idx, shift, w_size;
207
208 w_size = controller->w_size;
209
210 while (controller->rx_bytes < xfer->len) {
211
212 state = readl_relaxed(controller->base + QUP_OPERATIONAL);
213 if (0 == (state & QUP_OP_IN_FIFO_NOT_EMPTY))
214 break;
215
216 word = readl_relaxed(controller->base + QUP_INPUT_FIFO);
217
218 if (!rx_buf) {
219 controller->rx_bytes += w_size;
220 continue;
221 }
222
223 for (idx = 0; idx < w_size; idx++, controller->rx_bytes++) {
224 /*
225 * The data format depends on bytes per SPI word:
226 * 4 bytes: 0x12345678
227 * 2 bytes: 0x00001234
228 * 1 byte : 0x00000012
229 */
230 shift = BITS_PER_BYTE;
231 shift *= (w_size - idx - 1);
232 rx_buf[controller->rx_bytes] = word >> shift;
233 }
234 }
235}
236
237static void spi_qup_fifo_write(struct spi_qup *controller,
238 struct spi_transfer *xfer)
239{
240 const u8 *tx_buf = xfer->tx_buf;
241 u32 word, state, data;
242 int idx, w_size;
243
244 w_size = controller->w_size;
245
246 while (controller->tx_bytes < xfer->len) {
247
248 state = readl_relaxed(controller->base + QUP_OPERATIONAL);
249 if (state & QUP_OP_OUT_FIFO_FULL)
250 break;
251
252 word = 0;
253 for (idx = 0; idx < w_size; idx++, controller->tx_bytes++) {
254
255 if (!tx_buf) {
256 controller->tx_bytes += w_size;
257 break;
258 }
259
260 data = tx_buf[controller->tx_bytes];
261 word |= data << (BITS_PER_BYTE * (3 - idx));
262 }
263
264 writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO);
265 }
266}
267
268static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id)
269{
270 struct spi_qup *controller = dev_id;
271 struct spi_transfer *xfer;
272 u32 opflags, qup_err, spi_err;
273 unsigned long flags;
274 int error = 0;
275
276 spin_lock_irqsave(&controller->lock, flags);
277 xfer = controller->xfer;
278 controller->xfer = NULL;
279 spin_unlock_irqrestore(&controller->lock, flags);
280
281 qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS);
282 spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS);
283 opflags = readl_relaxed(controller->base + QUP_OPERATIONAL);
284
285 writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS);
286 writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS);
287 writel_relaxed(opflags, controller->base + QUP_OPERATIONAL);
288
289 if (!xfer) {
290 dev_err_ratelimited(controller->dev, "unexpected irq %x08 %x08 %x08\n",
291 qup_err, spi_err, opflags);
292 return IRQ_HANDLED;
293 }
294
295 if (qup_err) {
296 if (qup_err & QUP_ERROR_OUTPUT_OVER_RUN)
297 dev_warn(controller->dev, "OUTPUT_OVER_RUN\n");
298 if (qup_err & QUP_ERROR_INPUT_UNDER_RUN)
299 dev_warn(controller->dev, "INPUT_UNDER_RUN\n");
300 if (qup_err & QUP_ERROR_OUTPUT_UNDER_RUN)
301 dev_warn(controller->dev, "OUTPUT_UNDER_RUN\n");
302 if (qup_err & QUP_ERROR_INPUT_OVER_RUN)
303 dev_warn(controller->dev, "INPUT_OVER_RUN\n");
304
305 error = -EIO;
306 }
307
308 if (spi_err) {
309 if (spi_err & SPI_ERROR_CLK_OVER_RUN)
310 dev_warn(controller->dev, "CLK_OVER_RUN\n");
311 if (spi_err & SPI_ERROR_CLK_UNDER_RUN)
312 dev_warn(controller->dev, "CLK_UNDER_RUN\n");
313
314 error = -EIO;
315 }
316
317 if (opflags & QUP_OP_IN_SERVICE_FLAG)
318 spi_qup_fifo_read(controller, xfer);
319
320 if (opflags & QUP_OP_OUT_SERVICE_FLAG)
321 spi_qup_fifo_write(controller, xfer);
322
323 spin_lock_irqsave(&controller->lock, flags);
324 controller->error = error;
325 controller->xfer = xfer;
326 spin_unlock_irqrestore(&controller->lock, flags);
327
328 if (controller->rx_bytes == xfer->len || error)
329 complete(&controller->done);
330
331 return IRQ_HANDLED;
332}
333
334
335/* set clock freq ... bits per word */
336static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
337{
338 struct spi_qup *controller = spi_master_get_devdata(spi->master);
339 u32 config, iomode, mode;
340 int ret, n_words, w_size;
341
342 if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) {
343 dev_err(controller->dev, "too big size for loopback %d > %d\n",
344 xfer->len, controller->in_fifo_sz);
345 return -EIO;
346 }
347
348 ret = clk_set_rate(controller->cclk, xfer->speed_hz);
349 if (ret) {
350 dev_err(controller->dev, "fail to set frequency %d",
351 xfer->speed_hz);
352 return -EIO;
353 }
354
355 if (spi_qup_set_state(controller, QUP_STATE_RESET)) {
356 dev_err(controller->dev, "cannot set RESET state\n");
357 return -EIO;
358 }
359
360 w_size = 4;
361 if (xfer->bits_per_word <= 8)
362 w_size = 1;
363 else if (xfer->bits_per_word <= 16)
364 w_size = 2;
365
366 n_words = xfer->len / w_size;
367 controller->w_size = w_size;
368
369 if (n_words <= controller->in_fifo_sz) {
370 mode = QUP_IO_M_MODE_FIFO;
371 writel_relaxed(n_words, controller->base + QUP_MX_READ_CNT);
372 writel_relaxed(n_words, controller->base + QUP_MX_WRITE_CNT);
373 /* must be zero for FIFO */
374 writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
375 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
376 } else {
377 mode = QUP_IO_M_MODE_BLOCK;
378 writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT);
379 writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT);
380 /* must be zero for BLOCK and BAM */
381 writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
382 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
383 }
384
385 iomode = readl_relaxed(controller->base + QUP_IO_M_MODES);
386 /* Set input and output transfer mode */
387 iomode &= ~(QUP_IO_M_INPUT_MODE_MASK | QUP_IO_M_OUTPUT_MODE_MASK);
388 iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN);
389 iomode |= (mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT);
390 iomode |= (mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT);
391
392 writel_relaxed(iomode, controller->base + QUP_IO_M_MODES);
393
394 config = readl_relaxed(controller->base + SPI_CONFIG);
395
396 if (spi->mode & SPI_LOOP)
397 config |= SPI_CONFIG_LOOPBACK;
398 else
399 config &= ~SPI_CONFIG_LOOPBACK;
400
401 if (spi->mode & SPI_CPHA)
402 config &= ~SPI_CONFIG_INPUT_FIRST;
403 else
404 config |= SPI_CONFIG_INPUT_FIRST;
405
406 /*
407 * HS_MODE improves signal stability for spi-clk high rates,
408 * but is invalid in loop back mode.
409 */
410 if ((xfer->speed_hz >= SPI_HS_MIN_RATE) && !(spi->mode & SPI_LOOP))
411 config |= SPI_CONFIG_HS_MODE;
412 else
413 config &= ~SPI_CONFIG_HS_MODE;
414
415 writel_relaxed(config, controller->base + SPI_CONFIG);
416
417 config = readl_relaxed(controller->base + QUP_CONFIG);
418 config &= ~(QUP_CONFIG_NO_INPUT | QUP_CONFIG_NO_OUTPUT | QUP_CONFIG_N);
419 config |= xfer->bits_per_word - 1;
420 config |= QUP_CONFIG_SPI_MODE;
421 writel_relaxed(config, controller->base + QUP_CONFIG);
422
423 writel_relaxed(0, controller->base + QUP_OPERATIONAL_MASK);
424 return 0;
425}
426
427static void spi_qup_set_cs(struct spi_device *spi, bool enable)
428{
429 struct spi_qup *controller = spi_master_get_devdata(spi->master);
430
431 u32 iocontol, mask;
432
433 iocontol = readl_relaxed(controller->base + SPI_IO_CONTROL);
434
435 /* Disable auto CS toggle and use manual */
436 iocontol &= ~SPI_IO_C_MX_CS_MODE;
437 iocontol |= SPI_IO_C_FORCE_CS;
438
439 iocontol &= ~SPI_IO_C_CS_SELECT_MASK;
440 iocontol |= SPI_IO_C_CS_SELECT(spi->chip_select);
441
442 mask = SPI_IO_C_CS_N_POLARITY_0 << spi->chip_select;
443
444 if (enable)
445 iocontol |= mask;
446 else
447 iocontol &= ~mask;
448
449 writel_relaxed(iocontol, controller->base + SPI_IO_CONTROL);
450}
451
452static int spi_qup_transfer_one(struct spi_master *master,
453 struct spi_device *spi,
454 struct spi_transfer *xfer)
455{
456 struct spi_qup *controller = spi_master_get_devdata(master);
457 unsigned long timeout, flags;
458 int ret = -EIO;
459
460 ret = spi_qup_io_config(spi, xfer);
461 if (ret)
462 return ret;
463
464 timeout = DIV_ROUND_UP(xfer->speed_hz, MSEC_PER_SEC);
465 timeout = DIV_ROUND_UP(xfer->len * 8, timeout);
466 timeout = 100 * msecs_to_jiffies(timeout);
467
468 reinit_completion(&controller->done);
469
470 spin_lock_irqsave(&controller->lock, flags);
471 controller->xfer = xfer;
472 controller->error = 0;
473 controller->rx_bytes = 0;
474 controller->tx_bytes = 0;
475 spin_unlock_irqrestore(&controller->lock, flags);
476
477 if (spi_qup_set_state(controller, QUP_STATE_RUN)) {
478 dev_warn(controller->dev, "cannot set RUN state\n");
479 goto exit;
480 }
481
482 if (spi_qup_set_state(controller, QUP_STATE_PAUSE)) {
483 dev_warn(controller->dev, "cannot set PAUSE state\n");
484 goto exit;
485 }
486
487 spi_qup_fifo_write(controller, xfer);
488
489 if (spi_qup_set_state(controller, QUP_STATE_RUN)) {
490 dev_warn(controller->dev, "cannot set EXECUTE state\n");
491 goto exit;
492 }
493
494 if (!wait_for_completion_timeout(&controller->done, timeout))
495 ret = -ETIMEDOUT;
496exit:
497 spi_qup_set_state(controller, QUP_STATE_RESET);
498 spin_lock_irqsave(&controller->lock, flags);
499 controller->xfer = NULL;
500 if (!ret)
501 ret = controller->error;
502 spin_unlock_irqrestore(&controller->lock, flags);
503 return ret;
504}
505
506static int spi_qup_probe(struct platform_device *pdev)
507{
508 struct spi_master *master;
509 struct clk *iclk, *cclk;
510 struct spi_qup *controller;
511 struct resource *res;
512 struct device *dev;
513 void __iomem *base;
514 u32 data, max_freq, iomode;
515 int ret, irq, size;
516
517 dev = &pdev->dev;
518 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
519 base = devm_ioremap_resource(dev, res);
520 if (IS_ERR(base))
521 return PTR_ERR(base);
522
523 irq = platform_get_irq(pdev, 0);
524 if (irq < 0)
525 return irq;
526
527 cclk = devm_clk_get(dev, "core");
528 if (IS_ERR(cclk))
529 return PTR_ERR(cclk);
530
531 iclk = devm_clk_get(dev, "iface");
532 if (IS_ERR(iclk))
533 return PTR_ERR(iclk);
534
535 /* This is optional parameter */
536 if (of_property_read_u32(dev->of_node, "spi-max-frequency", &max_freq))
537 max_freq = SPI_MAX_RATE;
538
539 if (!max_freq || max_freq > SPI_MAX_RATE) {
540 dev_err(dev, "invalid clock frequency %d\n", max_freq);
541 return -ENXIO;
542 }
543
544 ret = clk_prepare_enable(cclk);
545 if (ret) {
546 dev_err(dev, "cannot enable core clock\n");
547 return ret;
548 }
549
550 ret = clk_prepare_enable(iclk);
551 if (ret) {
552 clk_disable_unprepare(cclk);
553 dev_err(dev, "cannot enable iface clock\n");
554 return ret;
555 }
556
557 data = readl_relaxed(base + QUP_HW_VERSION);
558
559 if (data < QUP_HW_VERSION_2_1_1) {
560 clk_disable_unprepare(cclk);
561 clk_disable_unprepare(iclk);
562 dev_err(dev, "v.%08x is not supported\n", data);
563 return -ENXIO;
564 }
565
566 master = spi_alloc_master(dev, sizeof(struct spi_qup));
567 if (!master) {
568 clk_disable_unprepare(cclk);
569 clk_disable_unprepare(iclk);
570 dev_err(dev, "cannot allocate master\n");
571 return -ENOMEM;
572 }
573
574 master->bus_num = pdev->id;
575 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
576 master->num_chipselect = SPI_NUM_CHIPSELECTS;
577 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
578 master->max_speed_hz = max_freq;
579 master->set_cs = spi_qup_set_cs;
580 master->transfer_one = spi_qup_transfer_one;
581 master->dev.of_node = pdev->dev.of_node;
582 master->auto_runtime_pm = true;
583
584 platform_set_drvdata(pdev, master);
585
586 controller = spi_master_get_devdata(master);
587
588 controller->dev = dev;
589 controller->base = base;
590 controller->iclk = iclk;
591 controller->cclk = cclk;
592 controller->irq = irq;
593
594 spin_lock_init(&controller->lock);
595 init_completion(&controller->done);
596
597 iomode = readl_relaxed(base + QUP_IO_M_MODES);
598
599 size = QUP_IO_M_OUTPUT_BLOCK_SIZE(iomode);
600 if (size)
601 controller->out_blk_sz = size * 16;
602 else
603 controller->out_blk_sz = 4;
604
605 size = QUP_IO_M_INPUT_BLOCK_SIZE(iomode);
606 if (size)
607 controller->in_blk_sz = size * 16;
608 else
609 controller->in_blk_sz = 4;
610
611 size = QUP_IO_M_OUTPUT_FIFO_SIZE(iomode);
612 controller->out_fifo_sz = controller->out_blk_sz * (2 << size);
613
614 size = QUP_IO_M_INPUT_FIFO_SIZE(iomode);
615 controller->in_fifo_sz = controller->in_blk_sz * (2 << size);
616
617 dev_info(dev, "v.%08x IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
618 data, controller->in_blk_sz, controller->in_fifo_sz,
619 controller->out_blk_sz, controller->out_fifo_sz);
620
621 writel_relaxed(1, base + QUP_SW_RESET);
622
623 ret = spi_qup_set_state(controller, QUP_STATE_RESET);
624 if (ret) {
625 dev_err(dev, "cannot set RESET state\n");
626 goto error;
627 }
628
629 writel_relaxed(0, base + QUP_OPERATIONAL);
630 writel_relaxed(0, base + QUP_IO_M_MODES);
631 writel_relaxed(0, base + QUP_OPERATIONAL_MASK);
632 writel_relaxed(SPI_ERROR_CLK_UNDER_RUN | SPI_ERROR_CLK_OVER_RUN,
633 base + SPI_ERROR_FLAGS_EN);
634
635 writel_relaxed(0, base + SPI_CONFIG);
636 writel_relaxed(SPI_IO_C_NO_TRI_STATE, base + SPI_IO_CONTROL);
637
638 ret = devm_request_irq(dev, irq, spi_qup_qup_irq,
639 IRQF_TRIGGER_HIGH, pdev->name, controller);
640 if (ret)
641 goto error;
642
643 ret = devm_spi_register_master(dev, master);
644 if (ret)
645 goto error;
646
647 pm_runtime_set_autosuspend_delay(dev, MSEC_PER_SEC);
648 pm_runtime_use_autosuspend(dev);
649 pm_runtime_set_active(dev);
650 pm_runtime_enable(dev);
651 return 0;
652
653error:
654 clk_disable_unprepare(cclk);
655 clk_disable_unprepare(iclk);
656 spi_master_put(master);
657 return ret;
658}
659
660#ifdef CONFIG_PM_RUNTIME
661static int spi_qup_pm_suspend_runtime(struct device *device)
662{
663 struct spi_master *master = dev_get_drvdata(device);
664 struct spi_qup *controller = spi_master_get_devdata(master);
665 u32 config;
666
667 /* Enable clocks auto gaiting */
668 config = readl(controller->base + QUP_CONFIG);
669 config |= QUP_CONFIG_CLOCK_AUTO_GATE;
670 writel_relaxed(config, controller->base + QUP_CONFIG);
671 return 0;
672}
673
674static int spi_qup_pm_resume_runtime(struct device *device)
675{
676 struct spi_master *master = dev_get_drvdata(device);
677 struct spi_qup *controller = spi_master_get_devdata(master);
678 u32 config;
679
680 /* Disable clocks auto gaiting */
681 config = readl_relaxed(controller->base + QUP_CONFIG);
682 config &= ~QUP_CONFIG_CLOCK_AUTO_GATE;
683 writel_relaxed(config, controller->base + QUP_CONFIG);
684 return 0;
685}
686#endif /* CONFIG_PM_RUNTIME */
687
688#ifdef CONFIG_PM_SLEEP
689static int spi_qup_suspend(struct device *device)
690{
691 struct spi_master *master = dev_get_drvdata(device);
692 struct spi_qup *controller = spi_master_get_devdata(master);
693 int ret;
694
695 ret = spi_master_suspend(master);
696 if (ret)
697 return ret;
698
699 ret = spi_qup_set_state(controller, QUP_STATE_RESET);
700 if (ret)
701 return ret;
702
703 clk_disable_unprepare(controller->cclk);
704 clk_disable_unprepare(controller->iclk);
705 return 0;
706}
707
708static int spi_qup_resume(struct device *device)
709{
710 struct spi_master *master = dev_get_drvdata(device);
711 struct spi_qup *controller = spi_master_get_devdata(master);
712 int ret;
713
714 ret = clk_prepare_enable(controller->iclk);
715 if (ret)
716 return ret;
717
718 ret = clk_prepare_enable(controller->cclk);
719 if (ret)
720 return ret;
721
722 ret = spi_qup_set_state(controller, QUP_STATE_RESET);
723 if (ret)
724 return ret;
725
726 return spi_master_resume(master);
727}
728#endif /* CONFIG_PM_SLEEP */
729
730static int spi_qup_remove(struct platform_device *pdev)
731{
732 struct spi_master *master = dev_get_drvdata(&pdev->dev);
733 struct spi_qup *controller = spi_master_get_devdata(master);
734 int ret;
735
736 ret = pm_runtime_get_sync(&pdev->dev);
737 if (ret)
738 return ret;
739
740 ret = spi_qup_set_state(controller, QUP_STATE_RESET);
741 if (ret)
742 return ret;
743
744 clk_disable_unprepare(controller->cclk);
745 clk_disable_unprepare(controller->iclk);
746
747 pm_runtime_put_noidle(&pdev->dev);
748 pm_runtime_disable(&pdev->dev);
749 return 0;
750}
751
752static struct of_device_id spi_qup_dt_match[] = {
753 { .compatible = "qcom,spi-qup-v2.1.1", },
754 { .compatible = "qcom,spi-qup-v2.2.1", },
755 { }
756};
757MODULE_DEVICE_TABLE(of, spi_qup_dt_match);
758
759static const struct dev_pm_ops spi_qup_dev_pm_ops = {
760 SET_SYSTEM_SLEEP_PM_OPS(spi_qup_suspend, spi_qup_resume)
761 SET_RUNTIME_PM_OPS(spi_qup_pm_suspend_runtime,
762 spi_qup_pm_resume_runtime,
763 NULL)
764};
765
766static struct platform_driver spi_qup_driver = {
767 .driver = {
768 .name = "spi_qup",
769 .owner = THIS_MODULE,
770 .pm = &spi_qup_dev_pm_ops,
771 .of_match_table = spi_qup_dt_match,
772 },
773 .probe = spi_qup_probe,
774 .remove = spi_qup_remove,
775};
776module_platform_driver(spi_qup_driver);
777
778MODULE_LICENSE("GPL v2");
779MODULE_ALIAS("platform:spi_qup");
diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c
index 28987d9fcfe5..1fb0ad213324 100644
--- a/drivers/spi/spi-rspi.c
+++ b/drivers/spi/spi-rspi.c
@@ -1,7 +1,8 @@
1/* 1/*
2 * SH RSPI driver 2 * SH RSPI driver
3 * 3 *
4 * Copyright (C) 2012 Renesas Solutions Corp. 4 * Copyright (C) 2012, 2013 Renesas Solutions Corp.
5 * Copyright (C) 2014 Glider bvba
5 * 6 *
6 * Based on spi-sh.c: 7 * Based on spi-sh.c:
7 * Copyright (C) 2011 Renesas Solutions Corp. 8 * Copyright (C) 2011 Renesas Solutions Corp.
@@ -25,14 +26,14 @@
25#include <linux/kernel.h> 26#include <linux/kernel.h>
26#include <linux/sched.h> 27#include <linux/sched.h>
27#include <linux/errno.h> 28#include <linux/errno.h>
28#include <linux/list.h>
29#include <linux/workqueue.h>
30#include <linux/interrupt.h> 29#include <linux/interrupt.h>
31#include <linux/platform_device.h> 30#include <linux/platform_device.h>
32#include <linux/io.h> 31#include <linux/io.h>
33#include <linux/clk.h> 32#include <linux/clk.h>
34#include <linux/dmaengine.h> 33#include <linux/dmaengine.h>
35#include <linux/dma-mapping.h> 34#include <linux/dma-mapping.h>
35#include <linux/of_device.h>
36#include <linux/pm_runtime.h>
36#include <linux/sh_dma.h> 37#include <linux/sh_dma.h>
37#include <linux/spi/spi.h> 38#include <linux/spi/spi.h>
38#include <linux/spi/rspi.h> 39#include <linux/spi/rspi.h>
@@ -49,7 +50,7 @@
49#define RSPI_SPCKD 0x0c /* Clock Delay Register */ 50#define RSPI_SPCKD 0x0c /* Clock Delay Register */
50#define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */ 51#define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */
51#define RSPI_SPND 0x0e /* Next-Access Delay Register */ 52#define RSPI_SPND 0x0e /* Next-Access Delay Register */
52#define RSPI_SPCR2 0x0f /* Control Register 2 */ 53#define RSPI_SPCR2 0x0f /* Control Register 2 (SH only) */
53#define RSPI_SPCMD0 0x10 /* Command Register 0 */ 54#define RSPI_SPCMD0 0x10 /* Command Register 0 */
54#define RSPI_SPCMD1 0x12 /* Command Register 1 */ 55#define RSPI_SPCMD1 0x12 /* Command Register 1 */
55#define RSPI_SPCMD2 0x14 /* Command Register 2 */ 56#define RSPI_SPCMD2 0x14 /* Command Register 2 */
@@ -58,16 +59,23 @@
58#define RSPI_SPCMD5 0x1a /* Command Register 5 */ 59#define RSPI_SPCMD5 0x1a /* Command Register 5 */
59#define RSPI_SPCMD6 0x1c /* Command Register 6 */ 60#define RSPI_SPCMD6 0x1c /* Command Register 6 */
60#define RSPI_SPCMD7 0x1e /* Command Register 7 */ 61#define RSPI_SPCMD7 0x1e /* Command Register 7 */
62#define RSPI_SPCMD(i) (RSPI_SPCMD0 + (i) * 2)
63#define RSPI_NUM_SPCMD 8
64#define RSPI_RZ_NUM_SPCMD 4
65#define QSPI_NUM_SPCMD 4
66
67/* RSPI on RZ only */
61#define RSPI_SPBFCR 0x20 /* Buffer Control Register */ 68#define RSPI_SPBFCR 0x20 /* Buffer Control Register */
62#define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */ 69#define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */
63 70
64/*qspi only */ 71/* QSPI only */
65#define QSPI_SPBFCR 0x18 /* Buffer Control Register */ 72#define QSPI_SPBFCR 0x18 /* Buffer Control Register */
66#define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */ 73#define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */
67#define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */ 74#define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */
68#define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */ 75#define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */
69#define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */ 76#define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */
70#define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */ 77#define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */
78#define QSPI_SPBMUL(i) (QSPI_SPBMUL0 + (i) * 4)
71 79
72/* SPCR - Control Register */ 80/* SPCR - Control Register */
73#define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */ 81#define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */
@@ -104,7 +112,7 @@
104#define SPSR_PERF 0x08 /* Parity Error Flag */ 112#define SPSR_PERF 0x08 /* Parity Error Flag */
105#define SPSR_MODF 0x04 /* Mode Fault Error Flag */ 113#define SPSR_MODF 0x04 /* Mode Fault Error Flag */
106#define SPSR_IDLNF 0x02 /* RSPI Idle Flag */ 114#define SPSR_IDLNF 0x02 /* RSPI Idle Flag */
107#define SPSR_OVRF 0x01 /* Overrun Error Flag */ 115#define SPSR_OVRF 0x01 /* Overrun Error Flag (RSPI only) */
108 116
109/* SPSCR - Sequence Control Register */ 117/* SPSCR - Sequence Control Register */
110#define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */ 118#define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */
@@ -121,13 +129,13 @@
121#define SPDCR_SPLWORD SPDCR_SPLW1 129#define SPDCR_SPLWORD SPDCR_SPLW1
122#define SPDCR_SPLBYTE SPDCR_SPLW0 130#define SPDCR_SPLBYTE SPDCR_SPLW0
123#define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */ 131#define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */
124#define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select */ 132#define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select (SH) */
125#define SPDCR_SLSEL1 0x08 133#define SPDCR_SLSEL1 0x08
126#define SPDCR_SLSEL0 0x04 134#define SPDCR_SLSEL0 0x04
127#define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select */ 135#define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select (SH) */
128#define SPDCR_SPFC1 0x02 136#define SPDCR_SPFC1 0x02
129#define SPDCR_SPFC0 0x01 137#define SPDCR_SPFC0 0x01
130#define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) */ 138#define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) (SH) */
131 139
132/* SPCKD - Clock Delay Register */ 140/* SPCKD - Clock Delay Register */
133#define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */ 141#define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */
@@ -151,7 +159,7 @@
151#define SPCMD_LSBF 0x1000 /* LSB First */ 159#define SPCMD_LSBF 0x1000 /* LSB First */
152#define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */ 160#define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */
153#define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK) 161#define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK)
154#define SPCMD_SPB_8BIT 0x0000 /* qspi only */ 162#define SPCMD_SPB_8BIT 0x0000 /* QSPI only */
155#define SPCMD_SPB_16BIT 0x0100 163#define SPCMD_SPB_16BIT 0x0100
156#define SPCMD_SPB_20BIT 0x0000 164#define SPCMD_SPB_20BIT 0x0000
157#define SPCMD_SPB_24BIT 0x0100 165#define SPCMD_SPB_24BIT 0x0100
@@ -170,8 +178,8 @@
170#define SPCMD_CPHA 0x0001 /* Clock Phase Setting */ 178#define SPCMD_CPHA 0x0001 /* Clock Phase Setting */
171 179
172/* SPBFCR - Buffer Control Register */ 180/* SPBFCR - Buffer Control Register */
173#define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset (qspi only) */ 181#define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset */
174#define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset (qspi only) */ 182#define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset */
175#define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */ 183#define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */
176#define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */ 184#define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */
177 185
@@ -181,22 +189,21 @@ struct rspi_data {
181 void __iomem *addr; 189 void __iomem *addr;
182 u32 max_speed_hz; 190 u32 max_speed_hz;
183 struct spi_master *master; 191 struct spi_master *master;
184 struct list_head queue;
185 struct work_struct ws;
186 wait_queue_head_t wait; 192 wait_queue_head_t wait;
187 spinlock_t lock;
188 struct clk *clk; 193 struct clk *clk;
189 u8 spsr;
190 u16 spcmd; 194 u16 spcmd;
195 u8 spsr;
196 u8 sppcr;
197 int rx_irq, tx_irq;
191 const struct spi_ops *ops; 198 const struct spi_ops *ops;
192 199
193 /* for dmaengine */ 200 /* for dmaengine */
194 struct dma_chan *chan_tx; 201 struct dma_chan *chan_tx;
195 struct dma_chan *chan_rx; 202 struct dma_chan *chan_rx;
196 int irq;
197 203
198 unsigned dma_width_16bit:1; 204 unsigned dma_width_16bit:1;
199 unsigned dma_callbacked:1; 205 unsigned dma_callbacked:1;
206 unsigned byte_access:1;
200}; 207};
201 208
202static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset) 209static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset)
@@ -224,34 +231,47 @@ static u16 rspi_read16(const struct rspi_data *rspi, u16 offset)
224 return ioread16(rspi->addr + offset); 231 return ioread16(rspi->addr + offset);
225} 232}
226 233
234static void rspi_write_data(const struct rspi_data *rspi, u16 data)
235{
236 if (rspi->byte_access)
237 rspi_write8(rspi, data, RSPI_SPDR);
238 else /* 16 bit */
239 rspi_write16(rspi, data, RSPI_SPDR);
240}
241
242static u16 rspi_read_data(const struct rspi_data *rspi)
243{
244 if (rspi->byte_access)
245 return rspi_read8(rspi, RSPI_SPDR);
246 else /* 16 bit */
247 return rspi_read16(rspi, RSPI_SPDR);
248}
249
227/* optional functions */ 250/* optional functions */
228struct spi_ops { 251struct spi_ops {
229 int (*set_config_register)(const struct rspi_data *rspi, 252 int (*set_config_register)(struct rspi_data *rspi, int access_size);
230 int access_size); 253 int (*transfer_one)(struct spi_master *master, struct spi_device *spi,
231 int (*send_pio)(struct rspi_data *rspi, struct spi_message *mesg, 254 struct spi_transfer *xfer);
232 struct spi_transfer *t); 255 u16 mode_bits;
233 int (*receive_pio)(struct rspi_data *rspi, struct spi_message *mesg,
234 struct spi_transfer *t);
235
236}; 256};
237 257
238/* 258/*
239 * functions for RSPI 259 * functions for RSPI on legacy SH
240 */ 260 */
241static int rspi_set_config_register(const struct rspi_data *rspi, 261static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
242 int access_size)
243{ 262{
244 int spbr; 263 int spbr;
245 264
246 /* Sets output mode(CMOS) and MOSI signal(from previous transfer) */ 265 /* Sets output mode, MOSI signal, and (optionally) loopback */
247 rspi_write8(rspi, 0x00, RSPI_SPPCR); 266 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
248 267
249 /* Sets transfer bit rate */ 268 /* Sets transfer bit rate */
250 spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1; 269 spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1;
251 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); 270 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
252 271
253 /* Sets number of frames to be used: 1 frame */ 272 /* Disable dummy transmission, set 16-bit word access, 1 frame */
254 rspi_write8(rspi, 0x00, RSPI_SPDCR); 273 rspi_write8(rspi, 0, RSPI_SPDCR);
274 rspi->byte_access = 0;
255 275
256 /* Sets RSPCK, SSL, next-access delay value */ 276 /* Sets RSPCK, SSL, next-access delay value */
257 rspi_write8(rspi, 0x00, RSPI_SPCKD); 277 rspi_write8(rspi, 0x00, RSPI_SPCKD);
@@ -262,8 +282,41 @@ static int rspi_set_config_register(const struct rspi_data *rspi,
262 rspi_write8(rspi, 0x00, RSPI_SPCR2); 282 rspi_write8(rspi, 0x00, RSPI_SPCR2);
263 283
264 /* Sets SPCMD */ 284 /* Sets SPCMD */
265 rspi_write16(rspi, SPCMD_SPB_8_TO_16(access_size) | rspi->spcmd, 285 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
266 RSPI_SPCMD0); 286 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
287
288 /* Sets RSPI mode */
289 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
290
291 return 0;
292}
293
294/*
295 * functions for RSPI on RZ
296 */
297static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)
298{
299 int spbr;
300
301 /* Sets output mode, MOSI signal, and (optionally) loopback */
302 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
303
304 /* Sets transfer bit rate */
305 spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1;
306 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
307
308 /* Disable dummy transmission, set byte access */
309 rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR);
310 rspi->byte_access = 1;
311
312 /* Sets RSPCK, SSL, next-access delay value */
313 rspi_write8(rspi, 0x00, RSPI_SPCKD);
314 rspi_write8(rspi, 0x00, RSPI_SSLND);
315 rspi_write8(rspi, 0x00, RSPI_SPND);
316
317 /* Sets SPCMD */
318 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
319 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
267 320
268 /* Sets RSPI mode */ 321 /* Sets RSPI mode */
269 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); 322 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
@@ -274,21 +327,20 @@ static int rspi_set_config_register(const struct rspi_data *rspi,
274/* 327/*
275 * functions for QSPI 328 * functions for QSPI
276 */ 329 */
277static int qspi_set_config_register(const struct rspi_data *rspi, 330static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
278 int access_size)
279{ 331{
280 u16 spcmd;
281 int spbr; 332 int spbr;
282 333
283 /* Sets output mode(CMOS) and MOSI signal(from previous transfer) */ 334 /* Sets output mode, MOSI signal, and (optionally) loopback */
284 rspi_write8(rspi, 0x00, RSPI_SPPCR); 335 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
285 336
286 /* Sets transfer bit rate */ 337 /* Sets transfer bit rate */
287 spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz); 338 spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz);
288 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); 339 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
289 340
290 /* Sets number of frames to be used: 1 frame */ 341 /* Disable dummy transmission, set byte access */
291 rspi_write8(rspi, 0x00, RSPI_SPDCR); 342 rspi_write8(rspi, 0, RSPI_SPDCR);
343 rspi->byte_access = 1;
292 344
293 /* Sets RSPCK, SSL, next-access delay value */ 345 /* Sets RSPCK, SSL, next-access delay value */
294 rspi_write8(rspi, 0x00, RSPI_SPCKD); 346 rspi_write8(rspi, 0x00, RSPI_SPCKD);
@@ -297,13 +349,13 @@ static int qspi_set_config_register(const struct rspi_data *rspi,
297 349
298 /* Data Length Setting */ 350 /* Data Length Setting */
299 if (access_size == 8) 351 if (access_size == 8)
300 spcmd = SPCMD_SPB_8BIT; 352 rspi->spcmd |= SPCMD_SPB_8BIT;
301 else if (access_size == 16) 353 else if (access_size == 16)
302 spcmd = SPCMD_SPB_16BIT; 354 rspi->spcmd |= SPCMD_SPB_16BIT;
303 else 355 else
304 spcmd = SPCMD_SPB_32BIT; 356 rspi->spcmd |= SPCMD_SPB_32BIT;
305 357
306 spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | rspi->spcmd | SPCMD_SPNDEN; 358 rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN;
307 359
308 /* Resets transfer data length */ 360 /* Resets transfer data length */
309 rspi_write32(rspi, 0, QSPI_SPBMUL0); 361 rspi_write32(rspi, 0, QSPI_SPBMUL0);
@@ -314,9 +366,9 @@ static int qspi_set_config_register(const struct rspi_data *rspi,
314 rspi_write8(rspi, 0x00, QSPI_SPBFCR); 366 rspi_write8(rspi, 0x00, QSPI_SPBFCR);
315 367
316 /* Sets SPCMD */ 368 /* Sets SPCMD */
317 rspi_write16(rspi, spcmd, RSPI_SPCMD0); 369 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
318 370
319 /* Enables SPI function in a master mode */ 371 /* Enables SPI function in master mode */
320 rspi_write8(rspi, SPCR_SPE | SPCR_MSTR, RSPI_SPCR); 372 rspi_write8(rspi, SPCR_SPE | SPCR_MSTR, RSPI_SPCR);
321 373
322 return 0; 374 return 0;
@@ -340,6 +392,9 @@ static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
340 int ret; 392 int ret;
341 393
342 rspi->spsr = rspi_read8(rspi, RSPI_SPSR); 394 rspi->spsr = rspi_read8(rspi, RSPI_SPSR);
395 if (rspi->spsr & wait_mask)
396 return 0;
397
343 rspi_enable_irq(rspi, enable_bit); 398 rspi_enable_irq(rspi, enable_bit);
344 ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ); 399 ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ);
345 if (ret == 0 && !(rspi->spsr & wait_mask)) 400 if (ret == 0 && !(rspi->spsr & wait_mask))
@@ -348,78 +403,39 @@ static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
348 return 0; 403 return 0;
349} 404}
350 405
351static void rspi_assert_ssl(const struct rspi_data *rspi) 406static int rspi_data_out(struct rspi_data *rspi, u8 data)
352{
353 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
354}
355
356static void rspi_negate_ssl(const struct rspi_data *rspi)
357{ 407{
358 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR); 408 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
409 dev_err(&rspi->master->dev, "transmit timeout\n");
410 return -ETIMEDOUT;
411 }
412 rspi_write_data(rspi, data);
413 return 0;
359} 414}
360 415
361static int rspi_send_pio(struct rspi_data *rspi, struct spi_message *mesg, 416static int rspi_data_in(struct rspi_data *rspi)
362 struct spi_transfer *t)
363{ 417{
364 int remain = t->len; 418 u8 data;
365 const u8 *data = t->tx_buf;
366 while (remain > 0) {
367 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD,
368 RSPI_SPCR);
369
370 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
371 dev_err(&rspi->master->dev,
372 "%s: tx empty timeout\n", __func__);
373 return -ETIMEDOUT;
374 }
375 419
376 rspi_write16(rspi, *data, RSPI_SPDR); 420 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) {
377 data++; 421 dev_err(&rspi->master->dev, "receive timeout\n");
378 remain--; 422 return -ETIMEDOUT;
379 } 423 }
380 424 data = rspi_read_data(rspi);
381 /* Waiting for the last transmission */ 425 return data;
382 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
383
384 return 0;
385} 426}
386 427
387static int qspi_send_pio(struct rspi_data *rspi, struct spi_message *mesg, 428static int rspi_data_out_in(struct rspi_data *rspi, u8 data)
388 struct spi_transfer *t)
389{ 429{
390 int remain = t->len; 430 int ret;
391 const u8 *data = t->tx_buf;
392
393 rspi_write8(rspi, SPBFCR_TXRST, QSPI_SPBFCR);
394 rspi_write8(rspi, 0x00, QSPI_SPBFCR);
395
396 while (remain > 0) {
397
398 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
399 dev_err(&rspi->master->dev,
400 "%s: tx empty timeout\n", __func__);
401 return -ETIMEDOUT;
402 }
403 rspi_write8(rspi, *data++, RSPI_SPDR);
404
405 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) {
406 dev_err(&rspi->master->dev,
407 "%s: receive timeout\n", __func__);
408 return -ETIMEDOUT;
409 }
410 rspi_read8(rspi, RSPI_SPDR);
411
412 remain--;
413 }
414 431
415 /* Waiting for the last transmission */ 432 ret = rspi_data_out(rspi, data);
416 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); 433 if (ret < 0)
434 return ret;
417 435
418 return 0; 436 return rspi_data_in(rspi);
419} 437}
420 438
421#define send_pio(spi, mesg, t) spi->ops->send_pio(spi, mesg, t)
422
423static void rspi_dma_complete(void *arg) 439static void rspi_dma_complete(void *arg)
424{ 440{
425 struct rspi_data *rspi = arg; 441 struct rspi_data *rspi = arg;
@@ -471,7 +487,7 @@ static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t)
471 struct scatterlist sg; 487 struct scatterlist sg;
472 const void *buf = NULL; 488 const void *buf = NULL;
473 struct dma_async_tx_descriptor *desc; 489 struct dma_async_tx_descriptor *desc;
474 unsigned len; 490 unsigned int len;
475 int ret = 0; 491 int ret = 0;
476 492
477 if (rspi->dma_width_16bit) { 493 if (rspi->dma_width_16bit) {
@@ -509,7 +525,7 @@ static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t)
509 * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be 525 * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be
510 * called. So, this driver disables the IRQ while DMA transfer. 526 * called. So, this driver disables the IRQ while DMA transfer.
511 */ 527 */
512 disable_irq(rspi->irq); 528 disable_irq(rspi->tx_irq);
513 529
514 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD, RSPI_SPCR); 530 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD, RSPI_SPCR);
515 rspi_enable_irq(rspi, SPCR_SPTIE); 531 rspi_enable_irq(rspi, SPCR_SPTIE);
@@ -528,7 +544,7 @@ static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t)
528 ret = -ETIMEDOUT; 544 ret = -ETIMEDOUT;
529 rspi_disable_irq(rspi, SPCR_SPTIE); 545 rspi_disable_irq(rspi, SPCR_SPTIE);
530 546
531 enable_irq(rspi->irq); 547 enable_irq(rspi->tx_irq);
532 548
533end: 549end:
534 rspi_dma_unmap_sg(&sg, rspi->chan_tx, DMA_TO_DEVICE); 550 rspi_dma_unmap_sg(&sg, rspi->chan_tx, DMA_TO_DEVICE);
@@ -545,46 +561,17 @@ static void rspi_receive_init(const struct rspi_data *rspi)
545 561
546 spsr = rspi_read8(rspi, RSPI_SPSR); 562 spsr = rspi_read8(rspi, RSPI_SPSR);
547 if (spsr & SPSR_SPRF) 563 if (spsr & SPSR_SPRF)
548 rspi_read16(rspi, RSPI_SPDR); /* dummy read */ 564 rspi_read_data(rspi); /* dummy read */
549 if (spsr & SPSR_OVRF) 565 if (spsr & SPSR_OVRF)
550 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF, 566 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF,
551 RSPI_SPSR); 567 RSPI_SPSR);
552} 568}
553 569
554static int rspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg, 570static void rspi_rz_receive_init(const struct rspi_data *rspi)
555 struct spi_transfer *t)
556{ 571{
557 int remain = t->len;
558 u8 *data;
559
560 rspi_receive_init(rspi); 572 rspi_receive_init(rspi);
561 573 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR);
562 data = t->rx_buf; 574 rspi_write8(rspi, 0, RSPI_SPBFCR);
563 while (remain > 0) {
564 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD,
565 RSPI_SPCR);
566
567 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
568 dev_err(&rspi->master->dev,
569 "%s: tx empty timeout\n", __func__);
570 return -ETIMEDOUT;
571 }
572 /* dummy write for generate clock */
573 rspi_write16(rspi, DUMMY_DATA, RSPI_SPDR);
574
575 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) {
576 dev_err(&rspi->master->dev,
577 "%s: receive timeout\n", __func__);
578 return -ETIMEDOUT;
579 }
580 /* SPDR allows 16 or 32-bit access only */
581 *data = (u8)rspi_read16(rspi, RSPI_SPDR);
582
583 data++;
584 remain--;
585 }
586
587 return 0;
588} 575}
589 576
590static void qspi_receive_init(const struct rspi_data *rspi) 577static void qspi_receive_init(const struct rspi_data *rspi)
@@ -593,51 +580,17 @@ static void qspi_receive_init(const struct rspi_data *rspi)
593 580
594 spsr = rspi_read8(rspi, RSPI_SPSR); 581 spsr = rspi_read8(rspi, RSPI_SPSR);
595 if (spsr & SPSR_SPRF) 582 if (spsr & SPSR_SPRF)
596 rspi_read8(rspi, RSPI_SPDR); /* dummy read */ 583 rspi_read_data(rspi); /* dummy read */
597 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); 584 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
598 rspi_write8(rspi, 0x00, QSPI_SPBFCR); 585 rspi_write8(rspi, 0, QSPI_SPBFCR);
599} 586}
600 587
601static int qspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg,
602 struct spi_transfer *t)
603{
604 int remain = t->len;
605 u8 *data;
606
607 qspi_receive_init(rspi);
608
609 data = t->rx_buf;
610 while (remain > 0) {
611
612 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
613 dev_err(&rspi->master->dev,
614 "%s: tx empty timeout\n", __func__);
615 return -ETIMEDOUT;
616 }
617 /* dummy write for generate clock */
618 rspi_write8(rspi, DUMMY_DATA, RSPI_SPDR);
619
620 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) {
621 dev_err(&rspi->master->dev,
622 "%s: receive timeout\n", __func__);
623 return -ETIMEDOUT;
624 }
625 /* SPDR allows 8, 16 or 32-bit access */
626 *data++ = rspi_read8(rspi, RSPI_SPDR);
627 remain--;
628 }
629
630 return 0;
631}
632
633#define receive_pio(spi, mesg, t) spi->ops->receive_pio(spi, mesg, t)
634
635static int rspi_receive_dma(struct rspi_data *rspi, struct spi_transfer *t) 588static int rspi_receive_dma(struct rspi_data *rspi, struct spi_transfer *t)
636{ 589{
637 struct scatterlist sg, sg_dummy; 590 struct scatterlist sg, sg_dummy;
638 void *dummy = NULL, *rx_buf = NULL; 591 void *dummy = NULL, *rx_buf = NULL;
639 struct dma_async_tx_descriptor *desc, *desc_dummy; 592 struct dma_async_tx_descriptor *desc, *desc_dummy;
640 unsigned len; 593 unsigned int len;
641 int ret = 0; 594 int ret = 0;
642 595
643 if (rspi->dma_width_16bit) { 596 if (rspi->dma_width_16bit) {
@@ -695,7 +648,9 @@ static int rspi_receive_dma(struct rspi_data *rspi, struct spi_transfer *t)
695 * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be 648 * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be
696 * called. So, this driver disables the IRQ while DMA transfer. 649 * called. So, this driver disables the IRQ while DMA transfer.
697 */ 650 */
698 disable_irq(rspi->irq); 651 disable_irq(rspi->tx_irq);
652 if (rspi->rx_irq != rspi->tx_irq)
653 disable_irq(rspi->rx_irq);
699 654
700 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD, RSPI_SPCR); 655 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD, RSPI_SPCR);
701 rspi_enable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE); 656 rspi_enable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE);
@@ -718,7 +673,9 @@ static int rspi_receive_dma(struct rspi_data *rspi, struct spi_transfer *t)
718 ret = -ETIMEDOUT; 673 ret = -ETIMEDOUT;
719 rspi_disable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE); 674 rspi_disable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE);
720 675
721 enable_irq(rspi->irq); 676 enable_irq(rspi->tx_irq);
677 if (rspi->rx_irq != rspi->tx_irq)
678 enable_irq(rspi->rx_irq);
722 679
723end: 680end:
724 rspi_dma_unmap_sg(&sg, rspi->chan_rx, DMA_FROM_DEVICE); 681 rspi_dma_unmap_sg(&sg, rspi->chan_rx, DMA_FROM_DEVICE);
@@ -746,56 +703,175 @@ static int rspi_is_dma(const struct rspi_data *rspi, struct spi_transfer *t)
746 return 0; 703 return 0;
747} 704}
748 705
749static void rspi_work(struct work_struct *work) 706static int rspi_transfer_out_in(struct rspi_data *rspi,
707 struct spi_transfer *xfer)
750{ 708{
751 struct rspi_data *rspi = container_of(work, struct rspi_data, ws); 709 int remain = xfer->len, ret;
752 struct spi_message *mesg; 710 const u8 *tx_buf = xfer->tx_buf;
753 struct spi_transfer *t; 711 u8 *rx_buf = xfer->rx_buf;
754 unsigned long flags; 712 u8 spcr, data;
755 int ret;
756 713
757 while (1) { 714 rspi_receive_init(rspi);
758 spin_lock_irqsave(&rspi->lock, flags); 715
759 if (list_empty(&rspi->queue)) { 716 spcr = rspi_read8(rspi, RSPI_SPCR);
760 spin_unlock_irqrestore(&rspi->lock, flags); 717 if (rx_buf)
761 break; 718 spcr &= ~SPCR_TXMD;
762 } 719 else
763 mesg = list_entry(rspi->queue.next, struct spi_message, queue); 720 spcr |= SPCR_TXMD;
764 list_del_init(&mesg->queue); 721 rspi_write8(rspi, spcr, RSPI_SPCR);
765 spin_unlock_irqrestore(&rspi->lock, flags); 722
766 723 while (remain > 0) {
767 rspi_assert_ssl(rspi); 724 data = tx_buf ? *tx_buf++ : DUMMY_DATA;
768 725 ret = rspi_data_out(rspi, data);
769 list_for_each_entry(t, &mesg->transfers, transfer_list) { 726 if (ret < 0)
770 if (t->tx_buf) { 727 return ret;
771 if (rspi_is_dma(rspi, t)) 728 if (rx_buf) {
772 ret = rspi_send_dma(rspi, t); 729 ret = rspi_data_in(rspi);
773 else 730 if (ret < 0)
774 ret = send_pio(rspi, mesg, t); 731 return ret;
775 if (ret < 0) 732 *rx_buf++ = ret;
776 goto error;
777 }
778 if (t->rx_buf) {
779 if (rspi_is_dma(rspi, t))
780 ret = rspi_receive_dma(rspi, t);
781 else
782 ret = receive_pio(rspi, mesg, t);
783 if (ret < 0)
784 goto error;
785 }
786 mesg->actual_length += t->len;
787 } 733 }
788 rspi_negate_ssl(rspi); 734 remain--;
735 }
736
737 /* Wait for the last transmission */
738 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
739
740 return 0;
741}
742
743static int rspi_transfer_one(struct spi_master *master, struct spi_device *spi,
744 struct spi_transfer *xfer)
745{
746 struct rspi_data *rspi = spi_master_get_devdata(master);
747 int ret;
748
749 if (!rspi_is_dma(rspi, xfer))
750 return rspi_transfer_out_in(rspi, xfer);
751
752 if (xfer->tx_buf) {
753 ret = rspi_send_dma(rspi, xfer);
754 if (ret < 0)
755 return ret;
756 }
757 if (xfer->rx_buf)
758 return rspi_receive_dma(rspi, xfer);
759
760 return 0;
761}
762
763static int rspi_rz_transfer_out_in(struct rspi_data *rspi,
764 struct spi_transfer *xfer)
765{
766 int remain = xfer->len, ret;
767 const u8 *tx_buf = xfer->tx_buf;
768 u8 *rx_buf = xfer->rx_buf;
769 u8 data;
770
771 rspi_rz_receive_init(rspi);
772
773 while (remain > 0) {
774 data = tx_buf ? *tx_buf++ : DUMMY_DATA;
775 ret = rspi_data_out_in(rspi, data);
776 if (ret < 0)
777 return ret;
778 if (rx_buf)
779 *rx_buf++ = ret;
780 remain--;
781 }
782
783 /* Wait for the last transmission */
784 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
785
786 return 0;
787}
788
789static int rspi_rz_transfer_one(struct spi_master *master,
790 struct spi_device *spi,
791 struct spi_transfer *xfer)
792{
793 struct rspi_data *rspi = spi_master_get_devdata(master);
794
795 return rspi_rz_transfer_out_in(rspi, xfer);
796}
797
798static int qspi_transfer_out_in(struct rspi_data *rspi,
799 struct spi_transfer *xfer)
800{
801 int remain = xfer->len, ret;
802 const u8 *tx_buf = xfer->tx_buf;
803 u8 *rx_buf = xfer->rx_buf;
804 u8 data;
789 805
790 mesg->status = 0; 806 qspi_receive_init(rspi);
791 mesg->complete(mesg->context); 807
808 while (remain > 0) {
809 data = tx_buf ? *tx_buf++ : DUMMY_DATA;
810 ret = rspi_data_out_in(rspi, data);
811 if (ret < 0)
812 return ret;
813 if (rx_buf)
814 *rx_buf++ = ret;
815 remain--;
816 }
817
818 /* Wait for the last transmission */
819 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
820
821 return 0;
822}
823
824static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer)
825{
826 const u8 *buf = xfer->tx_buf;
827 unsigned int i;
828 int ret;
829
830 for (i = 0; i < xfer->len; i++) {
831 ret = rspi_data_out(rspi, *buf++);
832 if (ret < 0)
833 return ret;
792 } 834 }
793 835
794 return; 836 /* Wait for the last transmission */
837 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
795 838
796error: 839 return 0;
797 mesg->status = ret; 840}
798 mesg->complete(mesg->context); 841
842static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer)
843{
844 u8 *buf = xfer->rx_buf;
845 unsigned int i;
846 int ret;
847
848 for (i = 0; i < xfer->len; i++) {
849 ret = rspi_data_in(rspi);
850 if (ret < 0)
851 return ret;
852 *buf++ = ret;
853 }
854
855 return 0;
856}
857
858static int qspi_transfer_one(struct spi_master *master, struct spi_device *spi,
859 struct spi_transfer *xfer)
860{
861 struct rspi_data *rspi = spi_master_get_devdata(master);
862
863 if (spi->mode & SPI_LOOP) {
864 return qspi_transfer_out_in(rspi, xfer);
865 } else if (xfer->tx_buf && xfer->tx_nbits > SPI_NBITS_SINGLE) {
866 /* Quad or Dual SPI Write */
867 return qspi_transfer_out(rspi, xfer);
868 } else if (xfer->rx_buf && xfer->rx_nbits > SPI_NBITS_SINGLE) {
869 /* Quad or Dual SPI Read */
870 return qspi_transfer_in(rspi, xfer);
871 } else {
872 /* Single SPI Transfer */
873 return qspi_transfer_out_in(rspi, xfer);
874 }
799} 875}
800 876
801static int rspi_setup(struct spi_device *spi) 877static int rspi_setup(struct spi_device *spi)
@@ -810,32 +886,115 @@ static int rspi_setup(struct spi_device *spi)
810 if (spi->mode & SPI_CPHA) 886 if (spi->mode & SPI_CPHA)
811 rspi->spcmd |= SPCMD_CPHA; 887 rspi->spcmd |= SPCMD_CPHA;
812 888
889 /* CMOS output mode and MOSI signal from previous transfer */
890 rspi->sppcr = 0;
891 if (spi->mode & SPI_LOOP)
892 rspi->sppcr |= SPPCR_SPLP;
893
813 set_config_register(rspi, 8); 894 set_config_register(rspi, 8);
814 895
815 return 0; 896 return 0;
816} 897}
817 898
818static int rspi_transfer(struct spi_device *spi, struct spi_message *mesg) 899static u16 qspi_transfer_mode(const struct spi_transfer *xfer)
819{ 900{
820 struct rspi_data *rspi = spi_master_get_devdata(spi->master); 901 if (xfer->tx_buf)
821 unsigned long flags; 902 switch (xfer->tx_nbits) {
903 case SPI_NBITS_QUAD:
904 return SPCMD_SPIMOD_QUAD;
905 case SPI_NBITS_DUAL:
906 return SPCMD_SPIMOD_DUAL;
907 default:
908 return 0;
909 }
910 if (xfer->rx_buf)
911 switch (xfer->rx_nbits) {
912 case SPI_NBITS_QUAD:
913 return SPCMD_SPIMOD_QUAD | SPCMD_SPRW;
914 case SPI_NBITS_DUAL:
915 return SPCMD_SPIMOD_DUAL | SPCMD_SPRW;
916 default:
917 return 0;
918 }
919
920 return 0;
921}
822 922
823 mesg->actual_length = 0; 923static int qspi_setup_sequencer(struct rspi_data *rspi,
824 mesg->status = -EINPROGRESS; 924 const struct spi_message *msg)
925{
926 const struct spi_transfer *xfer;
927 unsigned int i = 0, len = 0;
928 u16 current_mode = 0xffff, mode;
929
930 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
931 mode = qspi_transfer_mode(xfer);
932 if (mode == current_mode) {
933 len += xfer->len;
934 continue;
935 }
936
937 /* Transfer mode change */
938 if (i) {
939 /* Set transfer data length of previous transfer */
940 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
941 }
825 942
826 spin_lock_irqsave(&rspi->lock, flags); 943 if (i >= QSPI_NUM_SPCMD) {
827 list_add_tail(&mesg->queue, &rspi->queue); 944 dev_err(&msg->spi->dev,
828 schedule_work(&rspi->ws); 945 "Too many different transfer modes");
829 spin_unlock_irqrestore(&rspi->lock, flags); 946 return -EINVAL;
947 }
948
949 /* Program transfer mode for this transfer */
950 rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i));
951 current_mode = mode;
952 len = xfer->len;
953 i++;
954 }
955 if (i) {
956 /* Set final transfer data length and sequence length */
957 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
958 rspi_write8(rspi, i - 1, RSPI_SPSCR);
959 }
830 960
831 return 0; 961 return 0;
832} 962}
833 963
834static void rspi_cleanup(struct spi_device *spi) 964static int rspi_prepare_message(struct spi_master *master,
965 struct spi_message *msg)
835{ 966{
967 struct rspi_data *rspi = spi_master_get_devdata(master);
968 int ret;
969
970 if (msg->spi->mode &
971 (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) {
972 /* Setup sequencer for messages with multiple transfer modes */
973 ret = qspi_setup_sequencer(rspi, msg);
974 if (ret < 0)
975 return ret;
976 }
977
978 /* Enable SPI function in master mode */
979 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
980 return 0;
836} 981}
837 982
838static irqreturn_t rspi_irq(int irq, void *_sr) 983static int rspi_unprepare_message(struct spi_master *master,
984 struct spi_message *msg)
985{
986 struct rspi_data *rspi = spi_master_get_devdata(master);
987
988 /* Disable SPI function */
989 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
990
991 /* Reset sequencer for Single SPI Transfers */
992 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
993 rspi_write8(rspi, 0, RSPI_SPSCR);
994 return 0;
995}
996
997static irqreturn_t rspi_irq_mux(int irq, void *_sr)
839{ 998{
840 struct rspi_data *rspi = _sr; 999 struct rspi_data *rspi = _sr;
841 u8 spsr; 1000 u8 spsr;
@@ -857,6 +1016,36 @@ static irqreturn_t rspi_irq(int irq, void *_sr)
857 return ret; 1016 return ret;
858} 1017}
859 1018
1019static irqreturn_t rspi_irq_rx(int irq, void *_sr)
1020{
1021 struct rspi_data *rspi = _sr;
1022 u8 spsr;
1023
1024 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1025 if (spsr & SPSR_SPRF) {
1026 rspi_disable_irq(rspi, SPCR_SPRIE);
1027 wake_up(&rspi->wait);
1028 return IRQ_HANDLED;
1029 }
1030
1031 return 0;
1032}
1033
1034static irqreturn_t rspi_irq_tx(int irq, void *_sr)
1035{
1036 struct rspi_data *rspi = _sr;
1037 u8 spsr;
1038
1039 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1040 if (spsr & SPSR_SPTEF) {
1041 rspi_disable_irq(rspi, SPCR_SPTIE);
1042 wake_up(&rspi->wait);
1043 return IRQ_HANDLED;
1044 }
1045
1046 return 0;
1047}
1048
860static int rspi_request_dma(struct rspi_data *rspi, 1049static int rspi_request_dma(struct rspi_data *rspi,
861 struct platform_device *pdev) 1050 struct platform_device *pdev)
862{ 1051{
@@ -923,34 +1112,89 @@ static int rspi_remove(struct platform_device *pdev)
923 struct rspi_data *rspi = platform_get_drvdata(pdev); 1112 struct rspi_data *rspi = platform_get_drvdata(pdev);
924 1113
925 rspi_release_dma(rspi); 1114 rspi_release_dma(rspi);
926 clk_disable(rspi->clk); 1115 pm_runtime_disable(&pdev->dev);
927 1116
928 return 0; 1117 return 0;
929} 1118}
930 1119
1120static const struct spi_ops rspi_ops = {
1121 .set_config_register = rspi_set_config_register,
1122 .transfer_one = rspi_transfer_one,
1123 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP,
1124};
1125
1126static const struct spi_ops rspi_rz_ops = {
1127 .set_config_register = rspi_rz_set_config_register,
1128 .transfer_one = rspi_rz_transfer_one,
1129 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP,
1130};
1131
1132static const struct spi_ops qspi_ops = {
1133 .set_config_register = qspi_set_config_register,
1134 .transfer_one = qspi_transfer_one,
1135 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP |
1136 SPI_TX_DUAL | SPI_TX_QUAD |
1137 SPI_RX_DUAL | SPI_RX_QUAD,
1138};
1139
1140#ifdef CONFIG_OF
1141static const struct of_device_id rspi_of_match[] = {
1142 /* RSPI on legacy SH */
1143 { .compatible = "renesas,rspi", .data = &rspi_ops },
1144 /* RSPI on RZ/A1H */
1145 { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops },
1146 /* QSPI on R-Car Gen2 */
1147 { .compatible = "renesas,qspi", .data = &qspi_ops },
1148 { /* sentinel */ }
1149};
1150
1151MODULE_DEVICE_TABLE(of, rspi_of_match);
1152
1153static int rspi_parse_dt(struct device *dev, struct spi_master *master)
1154{
1155 u32 num_cs;
1156 int error;
1157
1158 /* Parse DT properties */
1159 error = of_property_read_u32(dev->of_node, "num-cs", &num_cs);
1160 if (error) {
1161 dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error);
1162 return error;
1163 }
1164
1165 master->num_chipselect = num_cs;
1166 return 0;
1167}
1168#else
1169#define rspi_of_match NULL
1170static inline int rspi_parse_dt(struct device *dev, struct spi_master *master)
1171{
1172 return -EINVAL;
1173}
1174#endif /* CONFIG_OF */
1175
1176static int rspi_request_irq(struct device *dev, unsigned int irq,
1177 irq_handler_t handler, const char *suffix,
1178 void *dev_id)
1179{
1180 const char *base = dev_name(dev);
1181 size_t len = strlen(base) + strlen(suffix) + 2;
1182 char *name = devm_kzalloc(dev, len, GFP_KERNEL);
1183 if (!name)
1184 return -ENOMEM;
1185 snprintf(name, len, "%s:%s", base, suffix);
1186 return devm_request_irq(dev, irq, handler, 0, name, dev_id);
1187}
1188
931static int rspi_probe(struct platform_device *pdev) 1189static int rspi_probe(struct platform_device *pdev)
932{ 1190{
933 struct resource *res; 1191 struct resource *res;
934 struct spi_master *master; 1192 struct spi_master *master;
935 struct rspi_data *rspi; 1193 struct rspi_data *rspi;
936 int ret, irq; 1194 int ret;
937 char clk_name[16]; 1195 const struct of_device_id *of_id;
938 const struct rspi_plat_data *rspi_pd = dev_get_platdata(&pdev->dev); 1196 const struct rspi_plat_data *rspi_pd;
939 const struct spi_ops *ops; 1197 const struct spi_ops *ops;
940 const struct platform_device_id *id_entry = pdev->id_entry;
941
942 ops = (struct spi_ops *)id_entry->driver_data;
943 /* ops parameter check */
944 if (!ops->set_config_register) {
945 dev_err(&pdev->dev, "there is no set_config_register\n");
946 return -ENODEV;
947 }
948
949 irq = platform_get_irq(pdev, 0);
950 if (irq < 0) {
951 dev_err(&pdev->dev, "platform_get_irq error\n");
952 return -ENODEV;
953 }
954 1198
955 master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data)); 1199 master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data));
956 if (master == NULL) { 1200 if (master == NULL) {
@@ -958,6 +1202,28 @@ static int rspi_probe(struct platform_device *pdev)
958 return -ENOMEM; 1202 return -ENOMEM;
959 } 1203 }
960 1204
1205 of_id = of_match_device(rspi_of_match, &pdev->dev);
1206 if (of_id) {
1207 ops = of_id->data;
1208 ret = rspi_parse_dt(&pdev->dev, master);
1209 if (ret)
1210 goto error1;
1211 } else {
1212 ops = (struct spi_ops *)pdev->id_entry->driver_data;
1213 rspi_pd = dev_get_platdata(&pdev->dev);
1214 if (rspi_pd && rspi_pd->num_chipselect)
1215 master->num_chipselect = rspi_pd->num_chipselect;
1216 else
1217 master->num_chipselect = 2; /* default */
1218 };
1219
1220 /* ops parameter check */
1221 if (!ops->set_config_register) {
1222 dev_err(&pdev->dev, "there is no set_config_register\n");
1223 ret = -ENODEV;
1224 goto error1;
1225 }
1226
961 rspi = spi_master_get_devdata(master); 1227 rspi = spi_master_get_devdata(master);
962 platform_set_drvdata(pdev, rspi); 1228 platform_set_drvdata(pdev, rspi);
963 rspi->ops = ops; 1229 rspi->ops = ops;
@@ -970,39 +1236,61 @@ static int rspi_probe(struct platform_device *pdev)
970 goto error1; 1236 goto error1;
971 } 1237 }
972 1238
973 snprintf(clk_name, sizeof(clk_name), "%s%d", id_entry->name, pdev->id); 1239 rspi->clk = devm_clk_get(&pdev->dev, NULL);
974 rspi->clk = devm_clk_get(&pdev->dev, clk_name);
975 if (IS_ERR(rspi->clk)) { 1240 if (IS_ERR(rspi->clk)) {
976 dev_err(&pdev->dev, "cannot get clock\n"); 1241 dev_err(&pdev->dev, "cannot get clock\n");
977 ret = PTR_ERR(rspi->clk); 1242 ret = PTR_ERR(rspi->clk);
978 goto error1; 1243 goto error1;
979 } 1244 }
980 clk_enable(rspi->clk);
981 1245
982 INIT_LIST_HEAD(&rspi->queue); 1246 pm_runtime_enable(&pdev->dev);
983 spin_lock_init(&rspi->lock);
984 INIT_WORK(&rspi->ws, rspi_work);
985 init_waitqueue_head(&rspi->wait);
986 1247
987 if (rspi_pd && rspi_pd->num_chipselect) 1248 init_waitqueue_head(&rspi->wait);
988 master->num_chipselect = rspi_pd->num_chipselect;
989 else
990 master->num_chipselect = 2; /* default */
991 1249
992 master->bus_num = pdev->id; 1250 master->bus_num = pdev->id;
993 master->setup = rspi_setup; 1251 master->setup = rspi_setup;
994 master->transfer = rspi_transfer; 1252 master->auto_runtime_pm = true;
995 master->cleanup = rspi_cleanup; 1253 master->transfer_one = ops->transfer_one;
996 master->mode_bits = SPI_CPHA | SPI_CPOL; 1254 master->prepare_message = rspi_prepare_message;
1255 master->unprepare_message = rspi_unprepare_message;
1256 master->mode_bits = ops->mode_bits;
1257 master->dev.of_node = pdev->dev.of_node;
1258
1259 ret = platform_get_irq_byname(pdev, "rx");
1260 if (ret < 0) {
1261 ret = platform_get_irq_byname(pdev, "mux");
1262 if (ret < 0)
1263 ret = platform_get_irq(pdev, 0);
1264 if (ret >= 0)
1265 rspi->rx_irq = rspi->tx_irq = ret;
1266 } else {
1267 rspi->rx_irq = ret;
1268 ret = platform_get_irq_byname(pdev, "tx");
1269 if (ret >= 0)
1270 rspi->tx_irq = ret;
1271 }
1272 if (ret < 0) {
1273 dev_err(&pdev->dev, "platform_get_irq error\n");
1274 goto error2;
1275 }
997 1276
998 ret = devm_request_irq(&pdev->dev, irq, rspi_irq, 0, 1277 if (rspi->rx_irq == rspi->tx_irq) {
999 dev_name(&pdev->dev), rspi); 1278 /* Single multiplexed interrupt */
1279 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux,
1280 "mux", rspi);
1281 } else {
1282 /* Multi-interrupt mode, only SPRI and SPTI are used */
1283 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx,
1284 "rx", rspi);
1285 if (!ret)
1286 ret = rspi_request_irq(&pdev->dev, rspi->tx_irq,
1287 rspi_irq_tx, "tx", rspi);
1288 }
1000 if (ret < 0) { 1289 if (ret < 0) {
1001 dev_err(&pdev->dev, "request_irq error\n"); 1290 dev_err(&pdev->dev, "request_irq error\n");
1002 goto error2; 1291 goto error2;
1003 } 1292 }
1004 1293
1005 rspi->irq = irq;
1006 ret = rspi_request_dma(rspi, pdev); 1294 ret = rspi_request_dma(rspi, pdev);
1007 if (ret < 0) { 1295 if (ret < 0) {
1008 dev_err(&pdev->dev, "rspi_request_dma failed.\n"); 1296 dev_err(&pdev->dev, "rspi_request_dma failed.\n");
@@ -1022,27 +1310,16 @@ static int rspi_probe(struct platform_device *pdev)
1022error3: 1310error3:
1023 rspi_release_dma(rspi); 1311 rspi_release_dma(rspi);
1024error2: 1312error2:
1025 clk_disable(rspi->clk); 1313 pm_runtime_disable(&pdev->dev);
1026error1: 1314error1:
1027 spi_master_put(master); 1315 spi_master_put(master);
1028 1316
1029 return ret; 1317 return ret;
1030} 1318}
1031 1319
1032static struct spi_ops rspi_ops = {
1033 .set_config_register = rspi_set_config_register,
1034 .send_pio = rspi_send_pio,
1035 .receive_pio = rspi_receive_pio,
1036};
1037
1038static struct spi_ops qspi_ops = {
1039 .set_config_register = qspi_set_config_register,
1040 .send_pio = qspi_send_pio,
1041 .receive_pio = qspi_receive_pio,
1042};
1043
1044static struct platform_device_id spi_driver_ids[] = { 1320static struct platform_device_id spi_driver_ids[] = {
1045 { "rspi", (kernel_ulong_t)&rspi_ops }, 1321 { "rspi", (kernel_ulong_t)&rspi_ops },
1322 { "rspi-rz", (kernel_ulong_t)&rspi_rz_ops },
1046 { "qspi", (kernel_ulong_t)&qspi_ops }, 1323 { "qspi", (kernel_ulong_t)&qspi_ops },
1047 {}, 1324 {},
1048}; 1325};
@@ -1056,6 +1333,7 @@ static struct platform_driver rspi_driver = {
1056 .driver = { 1333 .driver = {
1057 .name = "renesas_spi", 1334 .name = "renesas_spi",
1058 .owner = THIS_MODULE, 1335 .owner = THIS_MODULE,
1336 .of_match_table = of_match_ptr(rspi_of_match),
1059 }, 1337 },
1060}; 1338};
1061module_platform_driver(rspi_driver); 1339module_platform_driver(rspi_driver);
diff --git a/drivers/spi/spi-s3c24xx.c b/drivers/spi/spi-s3c24xx.c
index c20df45204e2..bed23384dfab 100644
--- a/drivers/spi/spi-s3c24xx.c
+++ b/drivers/spi/spi-s3c24xx.c
@@ -122,25 +122,15 @@ static int s3c24xx_spi_update_state(struct spi_device *spi,
122{ 122{
123 struct s3c24xx_spi *hw = to_hw(spi); 123 struct s3c24xx_spi *hw = to_hw(spi);
124 struct s3c24xx_spi_devstate *cs = spi->controller_state; 124 struct s3c24xx_spi_devstate *cs = spi->controller_state;
125 unsigned int bpw;
126 unsigned int hz; 125 unsigned int hz;
127 unsigned int div; 126 unsigned int div;
128 unsigned long clk; 127 unsigned long clk;
129 128
130 bpw = t ? t->bits_per_word : spi->bits_per_word;
131 hz = t ? t->speed_hz : spi->max_speed_hz; 129 hz = t ? t->speed_hz : spi->max_speed_hz;
132 130
133 if (!bpw)
134 bpw = 8;
135
136 if (!hz) 131 if (!hz)
137 hz = spi->max_speed_hz; 132 hz = spi->max_speed_hz;
138 133
139 if (bpw != 8) {
140 dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw);
141 return -EINVAL;
142 }
143
144 if (spi->mode != cs->mode) { 134 if (spi->mode != cs->mode) {
145 u8 spcon = SPCON_DEFAULT | S3C2410_SPCON_ENSCK; 135 u8 spcon = SPCON_DEFAULT | S3C2410_SPCON_ENSCK;
146 136
@@ -543,6 +533,7 @@ static int s3c24xx_spi_probe(struct platform_device *pdev)
543 533
544 master->num_chipselect = hw->pdata->num_cs; 534 master->num_chipselect = hw->pdata->num_cs;
545 master->bus_num = pdata->bus_num; 535 master->bus_num = pdata->bus_num;
536 master->bits_per_word_mask = SPI_BPW_MASK(8);
546 537
547 /* setup the state for the bitbang driver */ 538 /* setup the state for the bitbang driver */
548 539
@@ -642,6 +633,11 @@ static int s3c24xx_spi_remove(struct platform_device *dev)
642static int s3c24xx_spi_suspend(struct device *dev) 633static int s3c24xx_spi_suspend(struct device *dev)
643{ 634{
644 struct s3c24xx_spi *hw = dev_get_drvdata(dev); 635 struct s3c24xx_spi *hw = dev_get_drvdata(dev);
636 int ret;
637
638 ret = spi_master_suspend(hw->master);
639 if (ret)
640 return ret;
645 641
646 if (hw->pdata && hw->pdata->gpio_setup) 642 if (hw->pdata && hw->pdata->gpio_setup)
647 hw->pdata->gpio_setup(hw->pdata, 0); 643 hw->pdata->gpio_setup(hw->pdata, 0);
@@ -655,7 +651,7 @@ static int s3c24xx_spi_resume(struct device *dev)
655 struct s3c24xx_spi *hw = dev_get_drvdata(dev); 651 struct s3c24xx_spi *hw = dev_get_drvdata(dev);
656 652
657 s3c24xx_spi_initialsetup(hw); 653 s3c24xx_spi_initialsetup(hw);
658 return 0; 654 return spi_master_resume(hw->master);
659} 655}
660 656
661static const struct dev_pm_ops s3c24xx_spi_pmops = { 657static const struct dev_pm_ops s3c24xx_spi_pmops = {
diff --git a/include/linux/pm_runtime.h b/include/linux/pm_runtime.h
index 16c9a62fa1c0..2a5897a4afbc 100644
--- a/include/linux/pm_runtime.h
+++ b/include/linux/pm_runtime.h
@@ -26,9 +26,13 @@
26#ifdef CONFIG_PM 26#ifdef CONFIG_PM
27extern int pm_generic_runtime_suspend(struct device *dev); 27extern int pm_generic_runtime_suspend(struct device *dev);
28extern int pm_generic_runtime_resume(struct device *dev); 28extern int pm_generic_runtime_resume(struct device *dev);
29extern int pm_runtime_force_suspend(struct device *dev);
30extern int pm_runtime_force_resume(struct device *dev);
29#else 31#else
30static inline int pm_generic_runtime_suspend(struct device *dev) { return 0; } 32static inline int pm_generic_runtime_suspend(struct device *dev) { return 0; }
31static inline int pm_generic_runtime_resume(struct device *dev) { return 0; } 33static inline int pm_generic_runtime_resume(struct device *dev) { return 0; }
34static inline int pm_runtime_force_suspend(struct device *dev) { return 0; }
35static inline int pm_runtime_force_resume(struct device *dev) { return 0; }
32#endif 36#endif
33 37
34#ifdef CONFIG_PM_RUNTIME 38#ifdef CONFIG_PM_RUNTIME
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-26 07:11:57 -0400