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-rw-r--r--drivers/serial/21285.c513
-rw-r--r--drivers/serial/68328serial.c1472
-rw-r--r--drivers/serial/68328serial.h193
-rw-r--r--drivers/serial/68360serial.c2979
-rw-r--r--drivers/serial/8250.c3309
-rw-r--r--drivers/serial/8250.h80
-rw-r--r--drivers/serial/8250_accent.c47
-rw-r--r--drivers/serial/8250_acorn.c141
-rw-r--r--drivers/serial/8250_boca.c61
-rw-r--r--drivers/serial/8250_early.c287
-rw-r--r--drivers/serial/8250_exar_st16c554.c52
-rw-r--r--drivers/serial/8250_fourport.c53
-rw-r--r--drivers/serial/8250_gsc.c122
-rw-r--r--drivers/serial/8250_hp300.c327
-rw-r--r--drivers/serial/8250_hub6.c58
-rw-r--r--drivers/serial/8250_mca.c63
-rw-r--r--drivers/serial/8250_pci.c3809
-rw-r--r--drivers/serial/8250_pnp.c523
-rw-r--r--drivers/serial/Kconfig1614
-rw-r--r--drivers/serial/Makefile90
-rw-r--r--drivers/serial/altera_jtaguart.c504
-rw-r--r--drivers/serial/altera_uart.c552
-rw-r--r--drivers/serial/amba-pl010.c825
-rw-r--r--drivers/serial/amba-pl011.c989
-rw-r--r--drivers/serial/apbuart.c710
-rw-r--r--drivers/serial/apbuart.h64
-rw-r--r--drivers/serial/atmel_serial.c1808
-rw-r--r--drivers/serial/bcm63xx_uart.c891
-rw-r--r--drivers/serial/bfin_5xx.c1459
-rw-r--r--drivers/serial/bfin_sport_uart.c930
-rw-r--r--drivers/serial/bfin_sport_uart.h86
-rw-r--r--drivers/serial/clps711x.c579
-rw-r--r--drivers/serial/cpm_uart/Makefile11
-rw-r--r--drivers/serial/cpm_uart/cpm_uart.h153
-rw-r--r--drivers/serial/cpm_uart/cpm_uart_core.c1424
-rw-r--r--drivers/serial/cpm_uart/cpm_uart_cpm1.c138
-rw-r--r--drivers/serial/cpm_uart/cpm_uart_cpm1.h34
-rw-r--r--drivers/serial/cpm_uart/cpm_uart_cpm2.c174
-rw-r--r--drivers/serial/cpm_uart/cpm_uart_cpm2.h34
-rw-r--r--drivers/serial/crisv10.c4567
-rw-r--r--drivers/serial/crisv10.h147
-rw-r--r--drivers/serial/dz.c955
-rw-r--r--drivers/serial/dz.h129
-rw-r--r--drivers/serial/icom.c1658
-rw-r--r--drivers/serial/icom.h287
-rw-r--r--drivers/serial/imx.c1381
-rw-r--r--drivers/serial/ioc3_serial.c2195
-rw-r--r--drivers/serial/ioc4_serial.c2953
-rw-r--r--drivers/serial/ip22zilog.c1221
-rw-r--r--drivers/serial/ip22zilog.h281
-rw-r--r--drivers/serial/jsm/Makefile8
-rw-r--r--drivers/serial/jsm/jsm.h388
-rw-r--r--drivers/serial/jsm/jsm_driver.c295
-rw-r--r--drivers/serial/jsm/jsm_neo.c1412
-rw-r--r--drivers/serial/jsm/jsm_tty.c910
-rw-r--r--drivers/serial/kgdboc.c268
-rw-r--r--drivers/serial/m32r_sio.c1192
-rw-r--r--drivers/serial/m32r_sio.h48
-rw-r--r--drivers/serial/m32r_sio_reg.h152
-rw-r--r--drivers/serial/max3100.c926
-rw-r--r--drivers/serial/max3107-aava.c344
-rw-r--r--drivers/serial/max3107.c1197
-rw-r--r--drivers/serial/max3107.h441
-rw-r--r--drivers/serial/mcf.c662
-rw-r--r--drivers/serial/mfd.c1500
-rw-r--r--drivers/serial/mpc52xx_uart.c1523
-rw-r--r--drivers/serial/mpsc.c2159
-rw-r--r--drivers/serial/mrst_max3110.c845
-rw-r--r--drivers/serial/mrst_max3110.h59
-rw-r--r--drivers/serial/msm_serial.c758
-rw-r--r--drivers/serial/msm_serial.h173
-rw-r--r--drivers/serial/mux.c633
-rw-r--r--drivers/serial/netx-serial.c750
-rw-r--r--drivers/serial/nwpserial.c477
-rw-r--r--drivers/serial/of_serial.c200
-rw-r--r--drivers/serial/pmac_zilog.c2208
-rw-r--r--drivers/serial/pmac_zilog.h396
-rw-r--r--drivers/serial/pnx8xxx_uart.c854
-rw-r--r--drivers/serial/pxa.c879
-rw-r--r--drivers/serial/s3c2400.c106
-rw-r--r--drivers/serial/s3c2410.c118
-rw-r--r--drivers/serial/s3c2412.c152
-rw-r--r--drivers/serial/s3c2440.c181
-rw-r--r--drivers/serial/s3c24a0.c118
-rw-r--r--drivers/serial/s3c6400.c152
-rw-r--r--drivers/serial/s5pv210.c162
-rw-r--r--drivers/serial/sa1100.c918
-rw-r--r--drivers/serial/samsung.c1487
-rw-r--r--drivers/serial/samsung.h120
-rw-r--r--drivers/serial/sb1250-duart.c976
-rw-r--r--drivers/serial/sc26xx.c757
-rw-r--r--drivers/serial/serial_core.c2564
-rw-r--r--drivers/serial/serial_cs.c920
-rw-r--r--drivers/serial/serial_ks8695.c705
-rw-r--r--drivers/serial/serial_lh7a40x.c682
-rw-r--r--drivers/serial/serial_txx9.c1344
-rw-r--r--drivers/serial/sh-sci.c2027
-rw-r--r--drivers/serial/sh-sci.h644
-rw-r--r--drivers/serial/sn_console.c1085
-rw-r--r--drivers/serial/suncore.c247
-rw-r--r--drivers/serial/suncore.h33
-rw-r--r--drivers/serial/sunhv.c661
-rw-r--r--drivers/serial/sunsab.c1152
-rw-r--r--drivers/serial/sunsab.h322
-rw-r--r--drivers/serial/sunsu.c1608
-rw-r--r--drivers/serial/sunzilog.c1655
-rw-r--r--drivers/serial/sunzilog.h289
-rw-r--r--drivers/serial/timbuart.c531
-rw-r--r--drivers/serial/timbuart.h58
-rw-r--r--drivers/serial/uartlite.c685
-rw-r--r--drivers/serial/ucc_uart.c1537
-rw-r--r--drivers/serial/vr41xx_siu.c978
-rw-r--r--drivers/serial/zs.c1304
-rw-r--r--drivers/serial/zs.h284
114 files changed, 0 insertions, 91151 deletions
diff --git a/drivers/serial/21285.c b/drivers/serial/21285.c
deleted file mode 100644
index d89aa38c5cf0..000000000000
--- a/drivers/serial/21285.c
+++ /dev/null
@@ -1,513 +0,0 @@
1/*
2 * linux/drivers/serial/21285.c
3 *
4 * Driver for the serial port on the 21285 StrongArm-110 core logic chip.
5 *
6 * Based on drivers/char/serial.c
7 */
8#include <linux/module.h>
9#include <linux/tty.h>
10#include <linux/ioport.h>
11#include <linux/init.h>
12#include <linux/console.h>
13#include <linux/device.h>
14#include <linux/tty_flip.h>
15#include <linux/serial_core.h>
16#include <linux/serial.h>
17#include <linux/io.h>
18
19#include <asm/irq.h>
20#include <asm/mach-types.h>
21#include <asm/hardware/dec21285.h>
22#include <mach/hardware.h>
23
24#define BAUD_BASE (mem_fclk_21285/64)
25
26#define SERIAL_21285_NAME "ttyFB"
27#define SERIAL_21285_MAJOR 204
28#define SERIAL_21285_MINOR 4
29
30#define RXSTAT_DUMMY_READ 0x80000000
31#define RXSTAT_FRAME (1 << 0)
32#define RXSTAT_PARITY (1 << 1)
33#define RXSTAT_OVERRUN (1 << 2)
34#define RXSTAT_ANYERR (RXSTAT_FRAME|RXSTAT_PARITY|RXSTAT_OVERRUN)
35
36#define H_UBRLCR_BREAK (1 << 0)
37#define H_UBRLCR_PARENB (1 << 1)
38#define H_UBRLCR_PAREVN (1 << 2)
39#define H_UBRLCR_STOPB (1 << 3)
40#define H_UBRLCR_FIFO (1 << 4)
41
42static const char serial21285_name[] = "Footbridge UART";
43
44#define tx_enabled(port) ((port)->unused[0])
45#define rx_enabled(port) ((port)->unused[1])
46
47/*
48 * The documented expression for selecting the divisor is:
49 * BAUD_BASE / baud - 1
50 * However, typically BAUD_BASE is not divisible by baud, so
51 * we want to select the divisor that gives us the minimum
52 * error. Therefore, we want:
53 * int(BAUD_BASE / baud - 0.5) ->
54 * int(BAUD_BASE / baud - (baud >> 1) / baud) ->
55 * int((BAUD_BASE - (baud >> 1)) / baud)
56 */
57
58static void serial21285_stop_tx(struct uart_port *port)
59{
60 if (tx_enabled(port)) {
61 disable_irq_nosync(IRQ_CONTX);
62 tx_enabled(port) = 0;
63 }
64}
65
66static void serial21285_start_tx(struct uart_port *port)
67{
68 if (!tx_enabled(port)) {
69 enable_irq(IRQ_CONTX);
70 tx_enabled(port) = 1;
71 }
72}
73
74static void serial21285_stop_rx(struct uart_port *port)
75{
76 if (rx_enabled(port)) {
77 disable_irq_nosync(IRQ_CONRX);
78 rx_enabled(port) = 0;
79 }
80}
81
82static void serial21285_enable_ms(struct uart_port *port)
83{
84}
85
86static irqreturn_t serial21285_rx_chars(int irq, void *dev_id)
87{
88 struct uart_port *port = dev_id;
89 struct tty_struct *tty = port->state->port.tty;
90 unsigned int status, ch, flag, rxs, max_count = 256;
91
92 status = *CSR_UARTFLG;
93 while (!(status & 0x10) && max_count--) {
94 ch = *CSR_UARTDR;
95 flag = TTY_NORMAL;
96 port->icount.rx++;
97
98 rxs = *CSR_RXSTAT | RXSTAT_DUMMY_READ;
99 if (unlikely(rxs & RXSTAT_ANYERR)) {
100 if (rxs & RXSTAT_PARITY)
101 port->icount.parity++;
102 else if (rxs & RXSTAT_FRAME)
103 port->icount.frame++;
104 if (rxs & RXSTAT_OVERRUN)
105 port->icount.overrun++;
106
107 rxs &= port->read_status_mask;
108
109 if (rxs & RXSTAT_PARITY)
110 flag = TTY_PARITY;
111 else if (rxs & RXSTAT_FRAME)
112 flag = TTY_FRAME;
113 }
114
115 uart_insert_char(port, rxs, RXSTAT_OVERRUN, ch, flag);
116
117 status = *CSR_UARTFLG;
118 }
119 tty_flip_buffer_push(tty);
120
121 return IRQ_HANDLED;
122}
123
124static irqreturn_t serial21285_tx_chars(int irq, void *dev_id)
125{
126 struct uart_port *port = dev_id;
127 struct circ_buf *xmit = &port->state->xmit;
128 int count = 256;
129
130 if (port->x_char) {
131 *CSR_UARTDR = port->x_char;
132 port->icount.tx++;
133 port->x_char = 0;
134 goto out;
135 }
136 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
137 serial21285_stop_tx(port);
138 goto out;
139 }
140
141 do {
142 *CSR_UARTDR = xmit->buf[xmit->tail];
143 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
144 port->icount.tx++;
145 if (uart_circ_empty(xmit))
146 break;
147 } while (--count > 0 && !(*CSR_UARTFLG & 0x20));
148
149 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
150 uart_write_wakeup(port);
151
152 if (uart_circ_empty(xmit))
153 serial21285_stop_tx(port);
154
155 out:
156 return IRQ_HANDLED;
157}
158
159static unsigned int serial21285_tx_empty(struct uart_port *port)
160{
161 return (*CSR_UARTFLG & 8) ? 0 : TIOCSER_TEMT;
162}
163
164/* no modem control lines */
165static unsigned int serial21285_get_mctrl(struct uart_port *port)
166{
167 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
168}
169
170static void serial21285_set_mctrl(struct uart_port *port, unsigned int mctrl)
171{
172}
173
174static void serial21285_break_ctl(struct uart_port *port, int break_state)
175{
176 unsigned long flags;
177 unsigned int h_lcr;
178
179 spin_lock_irqsave(&port->lock, flags);
180 h_lcr = *CSR_H_UBRLCR;
181 if (break_state)
182 h_lcr |= H_UBRLCR_BREAK;
183 else
184 h_lcr &= ~H_UBRLCR_BREAK;
185 *CSR_H_UBRLCR = h_lcr;
186 spin_unlock_irqrestore(&port->lock, flags);
187}
188
189static int serial21285_startup(struct uart_port *port)
190{
191 int ret;
192
193 tx_enabled(port) = 1;
194 rx_enabled(port) = 1;
195
196 ret = request_irq(IRQ_CONRX, serial21285_rx_chars, 0,
197 serial21285_name, port);
198 if (ret == 0) {
199 ret = request_irq(IRQ_CONTX, serial21285_tx_chars, 0,
200 serial21285_name, port);
201 if (ret)
202 free_irq(IRQ_CONRX, port);
203 }
204
205 return ret;
206}
207
208static void serial21285_shutdown(struct uart_port *port)
209{
210 free_irq(IRQ_CONTX, port);
211 free_irq(IRQ_CONRX, port);
212}
213
214static void
215serial21285_set_termios(struct uart_port *port, struct ktermios *termios,
216 struct ktermios *old)
217{
218 unsigned long flags;
219 unsigned int baud, quot, h_lcr, b;
220
221 /*
222 * We don't support modem control lines.
223 */
224 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
225 termios->c_cflag |= CLOCAL;
226
227 /*
228 * We don't support BREAK character recognition.
229 */
230 termios->c_iflag &= ~(IGNBRK | BRKINT);
231
232 /*
233 * Ask the core to calculate the divisor for us.
234 */
235 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
236 quot = uart_get_divisor(port, baud);
237 b = port->uartclk / (16 * quot);
238 tty_termios_encode_baud_rate(termios, b, b);
239
240 switch (termios->c_cflag & CSIZE) {
241 case CS5:
242 h_lcr = 0x00;
243 break;
244 case CS6:
245 h_lcr = 0x20;
246 break;
247 case CS7:
248 h_lcr = 0x40;
249 break;
250 default: /* CS8 */
251 h_lcr = 0x60;
252 break;
253 }
254
255 if (termios->c_cflag & CSTOPB)
256 h_lcr |= H_UBRLCR_STOPB;
257 if (termios->c_cflag & PARENB) {
258 h_lcr |= H_UBRLCR_PARENB;
259 if (!(termios->c_cflag & PARODD))
260 h_lcr |= H_UBRLCR_PAREVN;
261 }
262
263 if (port->fifosize)
264 h_lcr |= H_UBRLCR_FIFO;
265
266 spin_lock_irqsave(&port->lock, flags);
267
268 /*
269 * Update the per-port timeout.
270 */
271 uart_update_timeout(port, termios->c_cflag, baud);
272
273 /*
274 * Which character status flags are we interested in?
275 */
276 port->read_status_mask = RXSTAT_OVERRUN;
277 if (termios->c_iflag & INPCK)
278 port->read_status_mask |= RXSTAT_FRAME | RXSTAT_PARITY;
279
280 /*
281 * Which character status flags should we ignore?
282 */
283 port->ignore_status_mask = 0;
284 if (termios->c_iflag & IGNPAR)
285 port->ignore_status_mask |= RXSTAT_FRAME | RXSTAT_PARITY;
286 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
287 port->ignore_status_mask |= RXSTAT_OVERRUN;
288
289 /*
290 * Ignore all characters if CREAD is not set.
291 */
292 if ((termios->c_cflag & CREAD) == 0)
293 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
294
295 quot -= 1;
296
297 *CSR_UARTCON = 0;
298 *CSR_L_UBRLCR = quot & 0xff;
299 *CSR_M_UBRLCR = (quot >> 8) & 0x0f;
300 *CSR_H_UBRLCR = h_lcr;
301 *CSR_UARTCON = 1;
302
303 spin_unlock_irqrestore(&port->lock, flags);
304}
305
306static const char *serial21285_type(struct uart_port *port)
307{
308 return port->type == PORT_21285 ? "DC21285" : NULL;
309}
310
311static void serial21285_release_port(struct uart_port *port)
312{
313 release_mem_region(port->mapbase, 32);
314}
315
316static int serial21285_request_port(struct uart_port *port)
317{
318 return request_mem_region(port->mapbase, 32, serial21285_name)
319 != NULL ? 0 : -EBUSY;
320}
321
322static void serial21285_config_port(struct uart_port *port, int flags)
323{
324 if (flags & UART_CONFIG_TYPE && serial21285_request_port(port) == 0)
325 port->type = PORT_21285;
326}
327
328/*
329 * verify the new serial_struct (for TIOCSSERIAL).
330 */
331static int serial21285_verify_port(struct uart_port *port, struct serial_struct *ser)
332{
333 int ret = 0;
334 if (ser->type != PORT_UNKNOWN && ser->type != PORT_21285)
335 ret = -EINVAL;
336 if (ser->irq != NO_IRQ)
337 ret = -EINVAL;
338 if (ser->baud_base != port->uartclk / 16)
339 ret = -EINVAL;
340 return ret;
341}
342
343static struct uart_ops serial21285_ops = {
344 .tx_empty = serial21285_tx_empty,
345 .get_mctrl = serial21285_get_mctrl,
346 .set_mctrl = serial21285_set_mctrl,
347 .stop_tx = serial21285_stop_tx,
348 .start_tx = serial21285_start_tx,
349 .stop_rx = serial21285_stop_rx,
350 .enable_ms = serial21285_enable_ms,
351 .break_ctl = serial21285_break_ctl,
352 .startup = serial21285_startup,
353 .shutdown = serial21285_shutdown,
354 .set_termios = serial21285_set_termios,
355 .type = serial21285_type,
356 .release_port = serial21285_release_port,
357 .request_port = serial21285_request_port,
358 .config_port = serial21285_config_port,
359 .verify_port = serial21285_verify_port,
360};
361
362static struct uart_port serial21285_port = {
363 .mapbase = 0x42000160,
364 .iotype = UPIO_MEM,
365 .irq = NO_IRQ,
366 .fifosize = 16,
367 .ops = &serial21285_ops,
368 .flags = UPF_BOOT_AUTOCONF,
369};
370
371static void serial21285_setup_ports(void)
372{
373 serial21285_port.uartclk = mem_fclk_21285 / 4;
374}
375
376#ifdef CONFIG_SERIAL_21285_CONSOLE
377static void serial21285_console_putchar(struct uart_port *port, int ch)
378{
379 while (*CSR_UARTFLG & 0x20)
380 barrier();
381 *CSR_UARTDR = ch;
382}
383
384static void
385serial21285_console_write(struct console *co, const char *s,
386 unsigned int count)
387{
388 uart_console_write(&serial21285_port, s, count, serial21285_console_putchar);
389}
390
391static void __init
392serial21285_get_options(struct uart_port *port, int *baud,
393 int *parity, int *bits)
394{
395 if (*CSR_UARTCON == 1) {
396 unsigned int tmp;
397
398 tmp = *CSR_H_UBRLCR;
399 switch (tmp & 0x60) {
400 case 0x00:
401 *bits = 5;
402 break;
403 case 0x20:
404 *bits = 6;
405 break;
406 case 0x40:
407 *bits = 7;
408 break;
409 default:
410 case 0x60:
411 *bits = 8;
412 break;
413 }
414
415 if (tmp & H_UBRLCR_PARENB) {
416 *parity = 'o';
417 if (tmp & H_UBRLCR_PAREVN)
418 *parity = 'e';
419 }
420
421 tmp = *CSR_L_UBRLCR | (*CSR_M_UBRLCR << 8);
422
423 *baud = port->uartclk / (16 * (tmp + 1));
424 }
425}
426
427static int __init serial21285_console_setup(struct console *co, char *options)
428{
429 struct uart_port *port = &serial21285_port;
430 int baud = 9600;
431 int bits = 8;
432 int parity = 'n';
433 int flow = 'n';
434
435 if (machine_is_personal_server())
436 baud = 57600;
437
438 /*
439 * Check whether an invalid uart number has been specified, and
440 * if so, search for the first available port that does have
441 * console support.
442 */
443 if (options)
444 uart_parse_options(options, &baud, &parity, &bits, &flow);
445 else
446 serial21285_get_options(port, &baud, &parity, &bits);
447
448 return uart_set_options(port, co, baud, parity, bits, flow);
449}
450
451static struct uart_driver serial21285_reg;
452
453static struct console serial21285_console =
454{
455 .name = SERIAL_21285_NAME,
456 .write = serial21285_console_write,
457 .device = uart_console_device,
458 .setup = serial21285_console_setup,
459 .flags = CON_PRINTBUFFER,
460 .index = -1,
461 .data = &serial21285_reg,
462};
463
464static int __init rs285_console_init(void)
465{
466 serial21285_setup_ports();
467 register_console(&serial21285_console);
468 return 0;
469}
470console_initcall(rs285_console_init);
471
472#define SERIAL_21285_CONSOLE &serial21285_console
473#else
474#define SERIAL_21285_CONSOLE NULL
475#endif
476
477static struct uart_driver serial21285_reg = {
478 .owner = THIS_MODULE,
479 .driver_name = "ttyFB",
480 .dev_name = "ttyFB",
481 .major = SERIAL_21285_MAJOR,
482 .minor = SERIAL_21285_MINOR,
483 .nr = 1,
484 .cons = SERIAL_21285_CONSOLE,
485};
486
487static int __init serial21285_init(void)
488{
489 int ret;
490
491 printk(KERN_INFO "Serial: 21285 driver\n");
492
493 serial21285_setup_ports();
494
495 ret = uart_register_driver(&serial21285_reg);
496 if (ret == 0)
497 uart_add_one_port(&serial21285_reg, &serial21285_port);
498
499 return ret;
500}
501
502static void __exit serial21285_exit(void)
503{
504 uart_remove_one_port(&serial21285_reg, &serial21285_port);
505 uart_unregister_driver(&serial21285_reg);
506}
507
508module_init(serial21285_init);
509module_exit(serial21285_exit);
510
511MODULE_LICENSE("GPL");
512MODULE_DESCRIPTION("Intel Footbridge (21285) serial driver");
513MODULE_ALIAS_CHARDEV(SERIAL_21285_MAJOR, SERIAL_21285_MINOR);
diff --git a/drivers/serial/68328serial.c b/drivers/serial/68328serial.c
deleted file mode 100644
index be0ebce36e54..000000000000
--- a/drivers/serial/68328serial.c
+++ /dev/null
@@ -1,1472 +0,0 @@
1/* 68328serial.c: Serial port driver for 68328 microcontroller
2 *
3 * Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu>
4 * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>
5 * Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org>
6 * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
7 * Copyright (C) 2002-2003 David McCullough <davidm@snapgear.com>
8 * Copyright (C) 2002 Greg Ungerer <gerg@snapgear.com>
9 *
10 * VZ Support/Fixes Evan Stawnyczy <e@lineo.ca>
11 * Multiple UART support Daniel Potts <danielp@cse.unsw.edu.au>
12 * Power management support Daniel Potts <danielp@cse.unsw.edu.au>
13 * VZ Second Serial Port enable Phil Wilshire
14 * 2.4/2.5 port David McCullough
15 */
16
17#include <asm/dbg.h>
18#include <linux/module.h>
19#include <linux/errno.h>
20#include <linux/signal.h>
21#include <linux/sched.h>
22#include <linux/timer.h>
23#include <linux/interrupt.h>
24#include <linux/tty.h>
25#include <linux/tty_flip.h>
26#include <linux/major.h>
27#include <linux/string.h>
28#include <linux/fcntl.h>
29#include <linux/mm.h>
30#include <linux/kernel.h>
31#include <linux/console.h>
32#include <linux/reboot.h>
33#include <linux/keyboard.h>
34#include <linux/init.h>
35#include <linux/pm.h>
36#include <linux/bitops.h>
37#include <linux/delay.h>
38#include <linux/gfp.h>
39
40#include <asm/io.h>
41#include <asm/irq.h>
42#include <asm/system.h>
43#include <asm/delay.h>
44#include <asm/uaccess.h>
45
46/* (es) */
47/* note: perhaps we can murge these files, so that you can just
48 * define 1 of them, and they can sort that out for themselves
49 */
50#if defined(CONFIG_M68EZ328)
51#include <asm/MC68EZ328.h>
52#else
53#if defined(CONFIG_M68VZ328)
54#include <asm/MC68VZ328.h>
55#else
56#include <asm/MC68328.h>
57#endif /* CONFIG_M68VZ328 */
58#endif /* CONFIG_M68EZ328 */
59
60#include "68328serial.h"
61
62/* Turn off usage of real serial interrupt code, to "support" Copilot */
63#ifdef CONFIG_XCOPILOT_BUGS
64#undef USE_INTS
65#else
66#define USE_INTS
67#endif
68
69static struct m68k_serial m68k_soft[NR_PORTS];
70
71static unsigned int uart_irqs[NR_PORTS] = UART_IRQ_DEFNS;
72
73/* multiple ports are contiguous in memory */
74m68328_uart *uart_addr = (m68328_uart *)USTCNT_ADDR;
75
76struct tty_struct m68k_ttys;
77struct m68k_serial *m68k_consinfo = 0;
78
79#define M68K_CLOCK (16667000) /* FIXME: 16MHz is likely wrong */
80
81struct tty_driver *serial_driver;
82
83/* number of characters left in xmit buffer before we ask for more */
84#define WAKEUP_CHARS 256
85
86/* Debugging... DEBUG_INTR is bad to use when one of the zs
87 * lines is your console ;(
88 */
89#undef SERIAL_DEBUG_INTR
90#undef SERIAL_DEBUG_OPEN
91#undef SERIAL_DEBUG_FLOW
92
93#define RS_ISR_PASS_LIMIT 256
94
95static void change_speed(struct m68k_serial *info);
96
97/*
98 * Setup for console. Argument comes from the boot command line.
99 */
100
101/* note: this is messy, but it works, again, perhaps defined somewhere else?*/
102#ifdef CONFIG_M68VZ328
103#define CONSOLE_BAUD_RATE 19200
104#define DEFAULT_CBAUD B19200
105#endif
106
107
108#ifndef CONSOLE_BAUD_RATE
109#define CONSOLE_BAUD_RATE 9600
110#define DEFAULT_CBAUD B9600
111#endif
112
113
114static int m68328_console_initted = 0;
115static int m68328_console_baud = CONSOLE_BAUD_RATE;
116static int m68328_console_cbaud = DEFAULT_CBAUD;
117
118
119static inline int serial_paranoia_check(struct m68k_serial *info,
120 char *name, const char *routine)
121{
122#ifdef SERIAL_PARANOIA_CHECK
123 static const char *badmagic =
124 "Warning: bad magic number for serial struct %s in %s\n";
125 static const char *badinfo =
126 "Warning: null m68k_serial for %s in %s\n";
127
128 if (!info) {
129 printk(badinfo, name, routine);
130 return 1;
131 }
132 if (info->magic != SERIAL_MAGIC) {
133 printk(badmagic, name, routine);
134 return 1;
135 }
136#endif
137 return 0;
138}
139
140/*
141 * This is used to figure out the divisor speeds and the timeouts
142 */
143static int baud_table[] = {
144 0, 50, 75, 110, 134, 150, 200, 300, 600, 1200, 1800, 2400, 4800,
145 9600, 19200, 38400, 57600, 115200, 0 };
146
147/* Sets or clears DTR/RTS on the requested line */
148static inline void m68k_rtsdtr(struct m68k_serial *ss, int set)
149{
150 if (set) {
151 /* set the RTS/CTS line */
152 } else {
153 /* clear it */
154 }
155 return;
156}
157
158/* Utility routines */
159static inline int get_baud(struct m68k_serial *ss)
160{
161 unsigned long result = 115200;
162 unsigned short int baud = uart_addr[ss->line].ubaud;
163 if (GET_FIELD(baud, UBAUD_PRESCALER) == 0x38) result = 38400;
164 result >>= GET_FIELD(baud, UBAUD_DIVIDE);
165
166 return result;
167}
168
169/*
170 * ------------------------------------------------------------
171 * rs_stop() and rs_start()
172 *
173 * This routines are called before setting or resetting tty->stopped.
174 * They enable or disable transmitter interrupts, as necessary.
175 * ------------------------------------------------------------
176 */
177static void rs_stop(struct tty_struct *tty)
178{
179 struct m68k_serial *info = (struct m68k_serial *)tty->driver_data;
180 m68328_uart *uart = &uart_addr[info->line];
181 unsigned long flags;
182
183 if (serial_paranoia_check(info, tty->name, "rs_stop"))
184 return;
185
186 local_irq_save(flags);
187 uart->ustcnt &= ~USTCNT_TXEN;
188 local_irq_restore(flags);
189}
190
191static int rs_put_char(char ch)
192{
193 int flags, loops = 0;
194
195 local_irq_save(flags);
196
197 while (!(UTX & UTX_TX_AVAIL) && (loops < 1000)) {
198 loops++;
199 udelay(5);
200 }
201
202 UTX_TXDATA = ch;
203 udelay(5);
204 local_irq_restore(flags);
205 return 1;
206}
207
208static void rs_start(struct tty_struct *tty)
209{
210 struct m68k_serial *info = (struct m68k_serial *)tty->driver_data;
211 m68328_uart *uart = &uart_addr[info->line];
212 unsigned long flags;
213
214 if (serial_paranoia_check(info, tty->name, "rs_start"))
215 return;
216
217 local_irq_save(flags);
218 if (info->xmit_cnt && info->xmit_buf && !(uart->ustcnt & USTCNT_TXEN)) {
219#ifdef USE_INTS
220 uart->ustcnt |= USTCNT_TXEN | USTCNT_TX_INTR_MASK;
221#else
222 uart->ustcnt |= USTCNT_TXEN;
223#endif
224 }
225 local_irq_restore(flags);
226}
227
228/* Drop into either the boot monitor or kadb upon receiving a break
229 * from keyboard/console input.
230 */
231static void batten_down_hatches(void)
232{
233 /* Drop into the debugger */
234}
235
236static void status_handle(struct m68k_serial *info, unsigned short status)
237{
238#if 0
239 if(status & DCD) {
240 if((info->port.tty->termios->c_cflag & CRTSCTS) &&
241 ((info->curregs[3] & AUTO_ENAB)==0)) {
242 info->curregs[3] |= AUTO_ENAB;
243 info->pendregs[3] |= AUTO_ENAB;
244 write_zsreg(info->m68k_channel, 3, info->curregs[3]);
245 }
246 } else {
247 if((info->curregs[3] & AUTO_ENAB)) {
248 info->curregs[3] &= ~AUTO_ENAB;
249 info->pendregs[3] &= ~AUTO_ENAB;
250 write_zsreg(info->m68k_channel, 3, info->curregs[3]);
251 }
252 }
253#endif
254 /* If this is console input and this is a
255 * 'break asserted' status change interrupt
256 * see if we can drop into the debugger
257 */
258 if((status & URX_BREAK) && info->break_abort)
259 batten_down_hatches();
260 return;
261}
262
263static void receive_chars(struct m68k_serial *info, unsigned short rx)
264{
265 struct tty_struct *tty = info->port.tty;
266 m68328_uart *uart = &uart_addr[info->line];
267 unsigned char ch, flag;
268
269 /*
270 * This do { } while() loop will get ALL chars out of Rx FIFO
271 */
272#ifndef CONFIG_XCOPILOT_BUGS
273 do {
274#endif
275 ch = GET_FIELD(rx, URX_RXDATA);
276
277 if(info->is_cons) {
278 if(URX_BREAK & rx) { /* whee, break received */
279 status_handle(info, rx);
280 return;
281#ifdef CONFIG_MAGIC_SYSRQ
282 } else if (ch == 0x10) { /* ^P */
283 show_state();
284 show_free_areas();
285 show_buffers();
286/* show_net_buffers(); */
287 return;
288 } else if (ch == 0x12) { /* ^R */
289 emergency_restart();
290 return;
291#endif /* CONFIG_MAGIC_SYSRQ */
292 }
293 }
294
295 if(!tty)
296 goto clear_and_exit;
297
298 flag = TTY_NORMAL;
299
300 if(rx & URX_PARITY_ERROR) {
301 flag = TTY_PARITY;
302 status_handle(info, rx);
303 } else if(rx & URX_OVRUN) {
304 flag = TTY_OVERRUN;
305 status_handle(info, rx);
306 } else if(rx & URX_FRAME_ERROR) {
307 flag = TTY_FRAME;
308 status_handle(info, rx);
309 }
310 tty_insert_flip_char(tty, ch, flag);
311#ifndef CONFIG_XCOPILOT_BUGS
312 } while((rx = uart->urx.w) & URX_DATA_READY);
313#endif
314
315 tty_schedule_flip(tty);
316
317clear_and_exit:
318 return;
319}
320
321static void transmit_chars(struct m68k_serial *info)
322{
323 m68328_uart *uart = &uart_addr[info->line];
324
325 if (info->x_char) {
326 /* Send next char */
327 uart->utx.b.txdata = info->x_char;
328 info->x_char = 0;
329 goto clear_and_return;
330 }
331
332 if((info->xmit_cnt <= 0) || info->port.tty->stopped) {
333 /* That's peculiar... TX ints off */
334 uart->ustcnt &= ~USTCNT_TX_INTR_MASK;
335 goto clear_and_return;
336 }
337
338 /* Send char */
339 uart->utx.b.txdata = info->xmit_buf[info->xmit_tail++];
340 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
341 info->xmit_cnt--;
342
343 if (info->xmit_cnt < WAKEUP_CHARS)
344 schedule_work(&info->tqueue);
345
346 if(info->xmit_cnt <= 0) {
347 /* All done for now... TX ints off */
348 uart->ustcnt &= ~USTCNT_TX_INTR_MASK;
349 goto clear_and_return;
350 }
351
352clear_and_return:
353 /* Clear interrupt (should be auto)*/
354 return;
355}
356
357/*
358 * This is the serial driver's generic interrupt routine
359 */
360irqreturn_t rs_interrupt(int irq, void *dev_id)
361{
362 struct m68k_serial *info = dev_id;
363 m68328_uart *uart;
364 unsigned short rx;
365 unsigned short tx;
366
367 uart = &uart_addr[info->line];
368 rx = uart->urx.w;
369
370#ifdef USE_INTS
371 tx = uart->utx.w;
372
373 if (rx & URX_DATA_READY) receive_chars(info, rx);
374 if (tx & UTX_TX_AVAIL) transmit_chars(info);
375#else
376 receive_chars(info, rx);
377#endif
378 return IRQ_HANDLED;
379}
380
381static void do_softint(struct work_struct *work)
382{
383 struct m68k_serial *info = container_of(work, struct m68k_serial, tqueue);
384 struct tty_struct *tty;
385
386 tty = info->port.tty;
387 if (!tty)
388 return;
389#if 0
390 if (clear_bit(RS_EVENT_WRITE_WAKEUP, &info->event)) {
391 tty_wakeup(tty);
392 }
393#endif
394}
395
396/*
397 * This routine is called from the scheduler tqueue when the interrupt
398 * routine has signalled that a hangup has occurred. The path of
399 * hangup processing is:
400 *
401 * serial interrupt routine -> (scheduler tqueue) ->
402 * do_serial_hangup() -> tty->hangup() -> rs_hangup()
403 *
404 */
405static void do_serial_hangup(struct work_struct *work)
406{
407 struct m68k_serial *info = container_of(work, struct m68k_serial, tqueue_hangup);
408 struct tty_struct *tty;
409
410 tty = info->port.tty;
411 if (!tty)
412 return;
413
414 tty_hangup(tty);
415}
416
417
418static int startup(struct m68k_serial * info)
419{
420 m68328_uart *uart = &uart_addr[info->line];
421 unsigned long flags;
422
423 if (info->flags & S_INITIALIZED)
424 return 0;
425
426 if (!info->xmit_buf) {
427 info->xmit_buf = (unsigned char *) __get_free_page(GFP_KERNEL);
428 if (!info->xmit_buf)
429 return -ENOMEM;
430 }
431
432 local_irq_save(flags);
433
434 /*
435 * Clear the FIFO buffers and disable them
436 * (they will be reenabled in change_speed())
437 */
438
439 uart->ustcnt = USTCNT_UEN;
440 info->xmit_fifo_size = 1;
441 uart->ustcnt = USTCNT_UEN | USTCNT_RXEN | USTCNT_TXEN;
442 (void)uart->urx.w;
443
444 /*
445 * Finally, enable sequencing and interrupts
446 */
447#ifdef USE_INTS
448 uart->ustcnt = USTCNT_UEN | USTCNT_RXEN |
449 USTCNT_RX_INTR_MASK | USTCNT_TX_INTR_MASK;
450#else
451 uart->ustcnt = USTCNT_UEN | USTCNT_RXEN | USTCNT_RX_INTR_MASK;
452#endif
453
454 if (info->port.tty)
455 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
456 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
457
458 /*
459 * and set the speed of the serial port
460 */
461
462 change_speed(info);
463
464 info->flags |= S_INITIALIZED;
465 local_irq_restore(flags);
466 return 0;
467}
468
469/*
470 * This routine will shutdown a serial port; interrupts are disabled, and
471 * DTR is dropped if the hangup on close termio flag is on.
472 */
473static void shutdown(struct m68k_serial * info)
474{
475 m68328_uart *uart = &uart_addr[info->line];
476 unsigned long flags;
477
478 uart->ustcnt = 0; /* All off! */
479 if (!(info->flags & S_INITIALIZED))
480 return;
481
482 local_irq_save(flags);
483
484 if (info->xmit_buf) {
485 free_page((unsigned long) info->xmit_buf);
486 info->xmit_buf = 0;
487 }
488
489 if (info->port.tty)
490 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
491
492 info->flags &= ~S_INITIALIZED;
493 local_irq_restore(flags);
494}
495
496struct {
497 int divisor, prescale;
498}
499#ifndef CONFIG_M68VZ328
500 hw_baud_table[18] = {
501 {0,0}, /* 0 */
502 {0,0}, /* 50 */
503 {0,0}, /* 75 */
504 {0,0}, /* 110 */
505 {0,0}, /* 134 */
506 {0,0}, /* 150 */
507 {0,0}, /* 200 */
508 {7,0x26}, /* 300 */
509 {6,0x26}, /* 600 */
510 {5,0x26}, /* 1200 */
511 {0,0}, /* 1800 */
512 {4,0x26}, /* 2400 */
513 {3,0x26}, /* 4800 */
514 {2,0x26}, /* 9600 */
515 {1,0x26}, /* 19200 */
516 {0,0x26}, /* 38400 */
517 {1,0x38}, /* 57600 */
518 {0,0x38}, /* 115200 */
519};
520#else
521 hw_baud_table[18] = {
522 {0,0}, /* 0 */
523 {0,0}, /* 50 */
524 {0,0}, /* 75 */
525 {0,0}, /* 110 */
526 {0,0}, /* 134 */
527 {0,0}, /* 150 */
528 {0,0}, /* 200 */
529 {0,0}, /* 300 */
530 {7,0x26}, /* 600 */
531 {6,0x26}, /* 1200 */
532 {0,0}, /* 1800 */
533 {5,0x26}, /* 2400 */
534 {4,0x26}, /* 4800 */
535 {3,0x26}, /* 9600 */
536 {2,0x26}, /* 19200 */
537 {1,0x26}, /* 38400 */
538 {0,0x26}, /* 57600 */
539 {1,0x38}, /* 115200 */
540};
541#endif
542/* rate = 1036800 / ((65 - prescale) * (1<<divider)) */
543
544/*
545 * This routine is called to set the UART divisor registers to match
546 * the specified baud rate for a serial port.
547 */
548static void change_speed(struct m68k_serial *info)
549{
550 m68328_uart *uart = &uart_addr[info->line];
551 unsigned short port;
552 unsigned short ustcnt;
553 unsigned cflag;
554 int i;
555
556 if (!info->port.tty || !info->port.tty->termios)
557 return;
558 cflag = info->port.tty->termios->c_cflag;
559 if (!(port = info->port))
560 return;
561
562 ustcnt = uart->ustcnt;
563 uart->ustcnt = ustcnt & ~USTCNT_TXEN;
564
565 i = cflag & CBAUD;
566 if (i & CBAUDEX) {
567 i = (i & ~CBAUDEX) + B38400;
568 }
569
570 info->baud = baud_table[i];
571 uart->ubaud = PUT_FIELD(UBAUD_DIVIDE, hw_baud_table[i].divisor) |
572 PUT_FIELD(UBAUD_PRESCALER, hw_baud_table[i].prescale);
573
574 ustcnt &= ~(USTCNT_PARITYEN | USTCNT_ODD_EVEN | USTCNT_STOP | USTCNT_8_7);
575
576 if ((cflag & CSIZE) == CS8)
577 ustcnt |= USTCNT_8_7;
578
579 if (cflag & CSTOPB)
580 ustcnt |= USTCNT_STOP;
581
582 if (cflag & PARENB)
583 ustcnt |= USTCNT_PARITYEN;
584 if (cflag & PARODD)
585 ustcnt |= USTCNT_ODD_EVEN;
586
587#ifdef CONFIG_SERIAL_68328_RTS_CTS
588 if (cflag & CRTSCTS) {
589 uart->utx.w &= ~ UTX_NOCTS;
590 } else {
591 uart->utx.w |= UTX_NOCTS;
592 }
593#endif
594
595 ustcnt |= USTCNT_TXEN;
596
597 uart->ustcnt = ustcnt;
598 return;
599}
600
601/*
602 * Fair output driver allows a process to speak.
603 */
604static void rs_fair_output(void)
605{
606 int left; /* Output no more than that */
607 unsigned long flags;
608 struct m68k_serial *info = &m68k_soft[0];
609 char c;
610
611 if (info == 0) return;
612 if (info->xmit_buf == 0) return;
613
614 local_irq_save(flags);
615 left = info->xmit_cnt;
616 while (left != 0) {
617 c = info->xmit_buf[info->xmit_tail];
618 info->xmit_tail = (info->xmit_tail+1) & (SERIAL_XMIT_SIZE-1);
619 info->xmit_cnt--;
620 local_irq_restore(flags);
621
622 rs_put_char(c);
623
624 local_irq_save(flags);
625 left = min(info->xmit_cnt, left-1);
626 }
627
628 /* Last character is being transmitted now (hopefully). */
629 udelay(5);
630
631 local_irq_restore(flags);
632 return;
633}
634
635/*
636 * m68k_console_print is registered for printk.
637 */
638void console_print_68328(const char *p)
639{
640 char c;
641
642 while((c=*(p++)) != 0) {
643 if(c == '\n')
644 rs_put_char('\r');
645 rs_put_char(c);
646 }
647
648 /* Comment this if you want to have a strict interrupt-driven output */
649 rs_fair_output();
650
651 return;
652}
653
654static void rs_set_ldisc(struct tty_struct *tty)
655{
656 struct m68k_serial *info = (struct m68k_serial *)tty->driver_data;
657
658 if (serial_paranoia_check(info, tty->name, "rs_set_ldisc"))
659 return;
660
661 info->is_cons = (tty->termios->c_line == N_TTY);
662
663 printk("ttyS%d console mode %s\n", info->line, info->is_cons ? "on" : "off");
664}
665
666static void rs_flush_chars(struct tty_struct *tty)
667{
668 struct m68k_serial *info = (struct m68k_serial *)tty->driver_data;
669 m68328_uart *uart = &uart_addr[info->line];
670 unsigned long flags;
671
672 if (serial_paranoia_check(info, tty->name, "rs_flush_chars"))
673 return;
674#ifndef USE_INTS
675 for(;;) {
676#endif
677
678 /* Enable transmitter */
679 local_irq_save(flags);
680
681 if (info->xmit_cnt <= 0 || tty->stopped || tty->hw_stopped ||
682 !info->xmit_buf) {
683 local_irq_restore(flags);
684 return;
685 }
686
687#ifdef USE_INTS
688 uart->ustcnt |= USTCNT_TXEN | USTCNT_TX_INTR_MASK;
689#else
690 uart->ustcnt |= USTCNT_TXEN;
691#endif
692
693#ifdef USE_INTS
694 if (uart->utx.w & UTX_TX_AVAIL) {
695#else
696 if (1) {
697#endif
698 /* Send char */
699 uart->utx.b.txdata = info->xmit_buf[info->xmit_tail++];
700 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
701 info->xmit_cnt--;
702 }
703
704#ifndef USE_INTS
705 while (!(uart->utx.w & UTX_TX_AVAIL)) udelay(5);
706 }
707#endif
708 local_irq_restore(flags);
709}
710
711extern void console_printn(const char * b, int count);
712
713static int rs_write(struct tty_struct * tty,
714 const unsigned char *buf, int count)
715{
716 int c, total = 0;
717 struct m68k_serial *info = (struct m68k_serial *)tty->driver_data;
718 m68328_uart *uart = &uart_addr[info->line];
719 unsigned long flags;
720
721 if (serial_paranoia_check(info, tty->name, "rs_write"))
722 return 0;
723
724 if (!tty || !info->xmit_buf)
725 return 0;
726
727 local_save_flags(flags);
728 while (1) {
729 local_irq_disable();
730 c = min_t(int, count, min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
731 SERIAL_XMIT_SIZE - info->xmit_head));
732 local_irq_restore(flags);
733
734 if (c <= 0)
735 break;
736
737 memcpy(info->xmit_buf + info->xmit_head, buf, c);
738
739 local_irq_disable();
740 info->xmit_head = (info->xmit_head + c) & (SERIAL_XMIT_SIZE-1);
741 info->xmit_cnt += c;
742 local_irq_restore(flags);
743 buf += c;
744 count -= c;
745 total += c;
746 }
747
748 if (info->xmit_cnt && !tty->stopped && !tty->hw_stopped) {
749 /* Enable transmitter */
750 local_irq_disable();
751#ifndef USE_INTS
752 while(info->xmit_cnt) {
753#endif
754
755 uart->ustcnt |= USTCNT_TXEN;
756#ifdef USE_INTS
757 uart->ustcnt |= USTCNT_TX_INTR_MASK;
758#else
759 while (!(uart->utx.w & UTX_TX_AVAIL)) udelay(5);
760#endif
761 if (uart->utx.w & UTX_TX_AVAIL) {
762 uart->utx.b.txdata = info->xmit_buf[info->xmit_tail++];
763 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
764 info->xmit_cnt--;
765 }
766
767#ifndef USE_INTS
768 }
769#endif
770 local_irq_restore(flags);
771 }
772
773 return total;
774}
775
776static int rs_write_room(struct tty_struct *tty)
777{
778 struct m68k_serial *info = (struct m68k_serial *)tty->driver_data;
779 int ret;
780
781 if (serial_paranoia_check(info, tty->name, "rs_write_room"))
782 return 0;
783 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
784 if (ret < 0)
785 ret = 0;
786 return ret;
787}
788
789static int rs_chars_in_buffer(struct tty_struct *tty)
790{
791 struct m68k_serial *info = (struct m68k_serial *)tty->driver_data;
792
793 if (serial_paranoia_check(info, tty->name, "rs_chars_in_buffer"))
794 return 0;
795 return info->xmit_cnt;
796}
797
798static void rs_flush_buffer(struct tty_struct *tty)
799{
800 struct m68k_serial *info = (struct m68k_serial *)tty->driver_data;
801 unsigned long flags;
802
803 if (serial_paranoia_check(info, tty->name, "rs_flush_buffer"))
804 return;
805 local_irq_save(flags);
806 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
807 local_irq_restore(flags);
808 tty_wakeup(tty);
809}
810
811/*
812 * ------------------------------------------------------------
813 * rs_throttle()
814 *
815 * This routine is called by the upper-layer tty layer to signal that
816 * incoming characters should be throttled.
817 * ------------------------------------------------------------
818 */
819static void rs_throttle(struct tty_struct * tty)
820{
821 struct m68k_serial *info = (struct m68k_serial *)tty->driver_data;
822
823 if (serial_paranoia_check(info, tty->name, "rs_throttle"))
824 return;
825
826 if (I_IXOFF(tty))
827 info->x_char = STOP_CHAR(tty);
828
829 /* Turn off RTS line (do this atomic) */
830}
831
832static void rs_unthrottle(struct tty_struct * tty)
833{
834 struct m68k_serial *info = (struct m68k_serial *)tty->driver_data;
835
836 if (serial_paranoia_check(info, tty->name, "rs_unthrottle"))
837 return;
838
839 if (I_IXOFF(tty)) {
840 if (info->x_char)
841 info->x_char = 0;
842 else
843 info->x_char = START_CHAR(tty);
844 }
845
846 /* Assert RTS line (do this atomic) */
847}
848
849/*
850 * ------------------------------------------------------------
851 * rs_ioctl() and friends
852 * ------------------------------------------------------------
853 */
854
855static int get_serial_info(struct m68k_serial * info,
856 struct serial_struct * retinfo)
857{
858 struct serial_struct tmp;
859
860 if (!retinfo)
861 return -EFAULT;
862 memset(&tmp, 0, sizeof(tmp));
863 tmp.type = info->type;
864 tmp.line = info->line;
865 tmp.port = info->port;
866 tmp.irq = info->irq;
867 tmp.flags = info->flags;
868 tmp.baud_base = info->baud_base;
869 tmp.close_delay = info->close_delay;
870 tmp.closing_wait = info->closing_wait;
871 tmp.custom_divisor = info->custom_divisor;
872 if (copy_to_user(retinfo, &tmp, sizeof(*retinfo)))
873 return -EFAULT;
874
875 return 0;
876}
877
878static int set_serial_info(struct m68k_serial * info,
879 struct serial_struct * new_info)
880{
881 struct serial_struct new_serial;
882 struct m68k_serial old_info;
883 int retval = 0;
884
885 if (!new_info)
886 return -EFAULT;
887 if (copy_from_user(&new_serial, new_info, sizeof(new_serial)))
888 return -EFAULT;
889 old_info = *info;
890
891 if (!capable(CAP_SYS_ADMIN)) {
892 if ((new_serial.baud_base != info->baud_base) ||
893 (new_serial.type != info->type) ||
894 (new_serial.close_delay != info->close_delay) ||
895 ((new_serial.flags & ~S_USR_MASK) !=
896 (info->flags & ~S_USR_MASK)))
897 return -EPERM;
898 info->flags = ((info->flags & ~S_USR_MASK) |
899 (new_serial.flags & S_USR_MASK));
900 info->custom_divisor = new_serial.custom_divisor;
901 goto check_and_exit;
902 }
903
904 if (info->count > 1)
905 return -EBUSY;
906
907 /*
908 * OK, past this point, all the error checking has been done.
909 * At this point, we start making changes.....
910 */
911
912 info->baud_base = new_serial.baud_base;
913 info->flags = ((info->flags & ~S_FLAGS) |
914 (new_serial.flags & S_FLAGS));
915 info->type = new_serial.type;
916 info->close_delay = new_serial.close_delay;
917 info->closing_wait = new_serial.closing_wait;
918
919check_and_exit:
920 retval = startup(info);
921 return retval;
922}
923
924/*
925 * get_lsr_info - get line status register info
926 *
927 * Purpose: Let user call ioctl() to get info when the UART physically
928 * is emptied. On bus types like RS485, the transmitter must
929 * release the bus after transmitting. This must be done when
930 * the transmit shift register is empty, not be done when the
931 * transmit holding register is empty. This functionality
932 * allows an RS485 driver to be written in user space.
933 */
934static int get_lsr_info(struct m68k_serial * info, unsigned int *value)
935{
936#ifdef CONFIG_SERIAL_68328_RTS_CTS
937 m68328_uart *uart = &uart_addr[info->line];
938#endif
939 unsigned char status;
940 unsigned long flags;
941
942 local_irq_save(flags);
943#ifdef CONFIG_SERIAL_68328_RTS_CTS
944 status = (uart->utx.w & UTX_CTS_STAT) ? 1 : 0;
945#else
946 status = 0;
947#endif
948 local_irq_restore(flags);
949 return put_user(status, value);
950}
951
952/*
953 * This routine sends a break character out the serial port.
954 */
955static void send_break(struct m68k_serial * info, unsigned int duration)
956{
957 m68328_uart *uart = &uart_addr[info->line];
958 unsigned long flags;
959 if (!info->port)
960 return;
961 local_irq_save(flags);
962#ifdef USE_INTS
963 uart->utx.w |= UTX_SEND_BREAK;
964 msleep_interruptible(duration);
965 uart->utx.w &= ~UTX_SEND_BREAK;
966#endif
967 local_irq_restore(flags);
968}
969
970static int rs_ioctl(struct tty_struct *tty, struct file * file,
971 unsigned int cmd, unsigned long arg)
972{
973 int error;
974 struct m68k_serial * info = (struct m68k_serial *)tty->driver_data;
975 int retval;
976
977 if (serial_paranoia_check(info, tty->name, "rs_ioctl"))
978 return -ENODEV;
979
980 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
981 (cmd != TIOCSERCONFIG) && (cmd != TIOCSERGWILD) &&
982 (cmd != TIOCSERSWILD) && (cmd != TIOCSERGSTRUCT)) {
983 if (tty->flags & (1 << TTY_IO_ERROR))
984 return -EIO;
985 }
986
987 switch (cmd) {
988 case TCSBRK: /* SVID version: non-zero arg --> no break */
989 retval = tty_check_change(tty);
990 if (retval)
991 return retval;
992 tty_wait_until_sent(tty, 0);
993 if (!arg)
994 send_break(info, 250); /* 1/4 second */
995 return 0;
996 case TCSBRKP: /* support for POSIX tcsendbreak() */
997 retval = tty_check_change(tty);
998 if (retval)
999 return retval;
1000 tty_wait_until_sent(tty, 0);
1001 send_break(info, arg ? arg*(100) : 250);
1002 return 0;
1003 case TIOCGSERIAL:
1004 return get_serial_info(info,
1005 (struct serial_struct *) arg);
1006 case TIOCSSERIAL:
1007 return set_serial_info(info,
1008 (struct serial_struct *) arg);
1009 case TIOCSERGETLSR: /* Get line status register */
1010 return get_lsr_info(info, (unsigned int *) arg);
1011 case TIOCSERGSTRUCT:
1012 if (copy_to_user((struct m68k_serial *) arg,
1013 info, sizeof(struct m68k_serial)))
1014 return -EFAULT;
1015 return 0;
1016 default:
1017 return -ENOIOCTLCMD;
1018 }
1019 return 0;
1020}
1021
1022static void rs_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
1023{
1024 struct m68k_serial *info = (struct m68k_serial *)tty->driver_data;
1025
1026 change_speed(info);
1027
1028 if ((old_termios->c_cflag & CRTSCTS) &&
1029 !(tty->termios->c_cflag & CRTSCTS)) {
1030 tty->hw_stopped = 0;
1031 rs_start(tty);
1032 }
1033
1034}
1035
1036/*
1037 * ------------------------------------------------------------
1038 * rs_close()
1039 *
1040 * This routine is called when the serial port gets closed. First, we
1041 * wait for the last remaining data to be sent. Then, we unlink its
1042 * S structure from the interrupt chain if necessary, and we free
1043 * that IRQ if nothing is left in the chain.
1044 * ------------------------------------------------------------
1045 */
1046static void rs_close(struct tty_struct *tty, struct file * filp)
1047{
1048 struct m68k_serial * info = (struct m68k_serial *)tty->driver_data;
1049 m68328_uart *uart = &uart_addr[info->line];
1050 unsigned long flags;
1051
1052 if (!info || serial_paranoia_check(info, tty->name, "rs_close"))
1053 return;
1054
1055 local_irq_save(flags);
1056
1057 if (tty_hung_up_p(filp)) {
1058 local_irq_restore(flags);
1059 return;
1060 }
1061
1062 if ((tty->count == 1) && (info->count != 1)) {
1063 /*
1064 * Uh, oh. tty->count is 1, which means that the tty
1065 * structure will be freed. Info->count should always
1066 * be one in these conditions. If it's greater than
1067 * one, we've got real problems, since it means the
1068 * serial port won't be shutdown.
1069 */
1070 printk("rs_close: bad serial port count; tty->count is 1, "
1071 "info->count is %d\n", info->count);
1072 info->count = 1;
1073 }
1074 if (--info->count < 0) {
1075 printk("rs_close: bad serial port count for ttyS%d: %d\n",
1076 info->line, info->count);
1077 info->count = 0;
1078 }
1079 if (info->count) {
1080 local_irq_restore(flags);
1081 return;
1082 }
1083 info->flags |= S_CLOSING;
1084 /*
1085 * Now we wait for the transmit buffer to clear; and we notify
1086 * the line discipline to only process XON/XOFF characters.
1087 */
1088 tty->closing = 1;
1089 if (info->closing_wait != S_CLOSING_WAIT_NONE)
1090 tty_wait_until_sent(tty, info->closing_wait);
1091 /*
1092 * At this point we stop accepting input. To do this, we
1093 * disable the receive line status interrupts, and tell the
1094 * interrupt driver to stop checking the data ready bit in the
1095 * line status register.
1096 */
1097
1098 uart->ustcnt &= ~USTCNT_RXEN;
1099 uart->ustcnt &= ~(USTCNT_RXEN | USTCNT_RX_INTR_MASK);
1100
1101 shutdown(info);
1102 rs_flush_buffer(tty);
1103
1104 tty_ldisc_flush(tty);
1105 tty->closing = 0;
1106 info->event = 0;
1107 info->port.tty = NULL;
1108#warning "This is not and has never been valid so fix it"
1109#if 0
1110 if (tty->ldisc.num != ldiscs[N_TTY].num) {
1111 if (tty->ldisc.close)
1112 (tty->ldisc.close)(tty);
1113 tty->ldisc = ldiscs[N_TTY];
1114 tty->termios->c_line = N_TTY;
1115 if (tty->ldisc.open)
1116 (tty->ldisc.open)(tty);
1117 }
1118#endif
1119 if (info->blocked_open) {
1120 if (info->close_delay) {
1121 msleep_interruptible(jiffies_to_msecs(info->close_delay));
1122 }
1123 wake_up_interruptible(&info->open_wait);
1124 }
1125 info->flags &= ~(S_NORMAL_ACTIVE|S_CLOSING);
1126 wake_up_interruptible(&info->close_wait);
1127 local_irq_restore(flags);
1128}
1129
1130/*
1131 * rs_hangup() --- called by tty_hangup() when a hangup is signaled.
1132 */
1133void rs_hangup(struct tty_struct *tty)
1134{
1135 struct m68k_serial * info = (struct m68k_serial *)tty->driver_data;
1136
1137 if (serial_paranoia_check(info, tty->name, "rs_hangup"))
1138 return;
1139
1140 rs_flush_buffer(tty);
1141 shutdown(info);
1142 info->event = 0;
1143 info->count = 0;
1144 info->flags &= ~S_NORMAL_ACTIVE;
1145 info->port.tty = NULL;
1146 wake_up_interruptible(&info->open_wait);
1147}
1148
1149/*
1150 * ------------------------------------------------------------
1151 * rs_open() and friends
1152 * ------------------------------------------------------------
1153 */
1154static int block_til_ready(struct tty_struct *tty, struct file * filp,
1155 struct m68k_serial *info)
1156{
1157 DECLARE_WAITQUEUE(wait, current);
1158 int retval;
1159 int do_clocal = 0;
1160
1161 /*
1162 * If the device is in the middle of being closed, then block
1163 * until it's done, and then try again.
1164 */
1165 if (info->flags & S_CLOSING) {
1166 interruptible_sleep_on(&info->close_wait);
1167#ifdef SERIAL_DO_RESTART
1168 if (info->flags & S_HUP_NOTIFY)
1169 return -EAGAIN;
1170 else
1171 return -ERESTARTSYS;
1172#else
1173 return -EAGAIN;
1174#endif
1175 }
1176
1177 /*
1178 * If non-blocking mode is set, or the port is not enabled,
1179 * then make the check up front and then exit.
1180 */
1181 if ((filp->f_flags & O_NONBLOCK) ||
1182 (tty->flags & (1 << TTY_IO_ERROR))) {
1183 info->flags |= S_NORMAL_ACTIVE;
1184 return 0;
1185 }
1186
1187 if (tty->termios->c_cflag & CLOCAL)
1188 do_clocal = 1;
1189
1190 /*
1191 * Block waiting for the carrier detect and the line to become
1192 * free (i.e., not in use by the callout). While we are in
1193 * this loop, info->count is dropped by one, so that
1194 * rs_close() knows when to free things. We restore it upon
1195 * exit, either normal or abnormal.
1196 */
1197 retval = 0;
1198 add_wait_queue(&info->open_wait, &wait);
1199
1200 info->count--;
1201 info->blocked_open++;
1202 while (1) {
1203 local_irq_disable();
1204 m68k_rtsdtr(info, 1);
1205 local_irq_enable();
1206 current->state = TASK_INTERRUPTIBLE;
1207 if (tty_hung_up_p(filp) ||
1208 !(info->flags & S_INITIALIZED)) {
1209#ifdef SERIAL_DO_RESTART
1210 if (info->flags & S_HUP_NOTIFY)
1211 retval = -EAGAIN;
1212 else
1213 retval = -ERESTARTSYS;
1214#else
1215 retval = -EAGAIN;
1216#endif
1217 break;
1218 }
1219 if (!(info->flags & S_CLOSING) && do_clocal)
1220 break;
1221 if (signal_pending(current)) {
1222 retval = -ERESTARTSYS;
1223 break;
1224 }
1225 tty_unlock();
1226 schedule();
1227 tty_lock();
1228 }
1229 current->state = TASK_RUNNING;
1230 remove_wait_queue(&info->open_wait, &wait);
1231 if (!tty_hung_up_p(filp))
1232 info->count++;
1233 info->blocked_open--;
1234
1235 if (retval)
1236 return retval;
1237 info->flags |= S_NORMAL_ACTIVE;
1238 return 0;
1239}
1240
1241/*
1242 * This routine is called whenever a serial port is opened. It
1243 * enables interrupts for a serial port, linking in its S structure into
1244 * the IRQ chain. It also performs the serial-specific
1245 * initialization for the tty structure.
1246 */
1247int rs_open(struct tty_struct *tty, struct file * filp)
1248{
1249 struct m68k_serial *info;
1250 int retval, line;
1251
1252 line = tty->index;
1253
1254 if (line >= NR_PORTS || line < 0) /* we have exactly one */
1255 return -ENODEV;
1256
1257 info = &m68k_soft[line];
1258
1259 if (serial_paranoia_check(info, tty->name, "rs_open"))
1260 return -ENODEV;
1261
1262 info->count++;
1263 tty->driver_data = info;
1264 info->port.tty = tty;
1265
1266 /*
1267 * Start up serial port
1268 */
1269 retval = startup(info);
1270 if (retval)
1271 return retval;
1272
1273 return block_til_ready(tty, filp, info);
1274}
1275
1276/* Finally, routines used to initialize the serial driver. */
1277
1278static void show_serial_version(void)
1279{
1280 printk("MC68328 serial driver version 1.00\n");
1281}
1282
1283static const struct tty_operations rs_ops = {
1284 .open = rs_open,
1285 .close = rs_close,
1286 .write = rs_write,
1287 .flush_chars = rs_flush_chars,
1288 .write_room = rs_write_room,
1289 .chars_in_buffer = rs_chars_in_buffer,
1290 .flush_buffer = rs_flush_buffer,
1291 .ioctl = rs_ioctl,
1292 .throttle = rs_throttle,
1293 .unthrottle = rs_unthrottle,
1294 .set_termios = rs_set_termios,
1295 .stop = rs_stop,
1296 .start = rs_start,
1297 .hangup = rs_hangup,
1298 .set_ldisc = rs_set_ldisc,
1299};
1300
1301/* rs_init inits the driver */
1302static int __init
1303rs68328_init(void)
1304{
1305 int flags, i;
1306 struct m68k_serial *info;
1307
1308 serial_driver = alloc_tty_driver(NR_PORTS);
1309 if (!serial_driver)
1310 return -ENOMEM;
1311
1312 show_serial_version();
1313
1314 /* Initialize the tty_driver structure */
1315 /* SPARC: Not all of this is exactly right for us. */
1316
1317 serial_driver->name = "ttyS";
1318 serial_driver->major = TTY_MAJOR;
1319 serial_driver->minor_start = 64;
1320 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
1321 serial_driver->subtype = SERIAL_TYPE_NORMAL;
1322 serial_driver->init_termios = tty_std_termios;
1323 serial_driver->init_termios.c_cflag =
1324 m68328_console_cbaud | CS8 | CREAD | HUPCL | CLOCAL;
1325 serial_driver->flags = TTY_DRIVER_REAL_RAW;
1326 tty_set_operations(serial_driver, &rs_ops);
1327
1328 if (tty_register_driver(serial_driver)) {
1329 put_tty_driver(serial_driver);
1330 printk(KERN_ERR "Couldn't register serial driver\n");
1331 return -ENOMEM;
1332 }
1333
1334 local_irq_save(flags);
1335
1336 for(i=0;i<NR_PORTS;i++) {
1337
1338 info = &m68k_soft[i];
1339 info->magic = SERIAL_MAGIC;
1340 info->port = (int) &uart_addr[i];
1341 info->port.tty = NULL;
1342 info->irq = uart_irqs[i];
1343 info->custom_divisor = 16;
1344 info->close_delay = 50;
1345 info->closing_wait = 3000;
1346 info->x_char = 0;
1347 info->event = 0;
1348 info->count = 0;
1349 info->blocked_open = 0;
1350 INIT_WORK(&info->tqueue, do_softint);
1351 INIT_WORK(&info->tqueue_hangup, do_serial_hangup);
1352 init_waitqueue_head(&info->open_wait);
1353 init_waitqueue_head(&info->close_wait);
1354 info->line = i;
1355 info->is_cons = 1; /* Means shortcuts work */
1356
1357 printk("%s%d at 0x%08x (irq = %d)", serial_driver->name, info->line,
1358 info->port, info->irq);
1359 printk(" is a builtin MC68328 UART\n");
1360
1361#ifdef CONFIG_M68VZ328
1362 if (i > 0 )
1363 PJSEL &= 0xCF; /* PSW enable second port output */
1364#endif
1365
1366 if (request_irq(uart_irqs[i],
1367 rs_interrupt,
1368 IRQF_DISABLED,
1369 "M68328_UART", info))
1370 panic("Unable to attach 68328 serial interrupt\n");
1371 }
1372 local_irq_restore(flags);
1373 return 0;
1374}
1375
1376module_init(rs68328_init);
1377
1378
1379
1380static void m68328_set_baud(void)
1381{
1382 unsigned short ustcnt;
1383 int i;
1384
1385 ustcnt = USTCNT;
1386 USTCNT = ustcnt & ~USTCNT_TXEN;
1387
1388again:
1389 for (i = 0; i < ARRAY_SIZE(baud_table); i++)
1390 if (baud_table[i] == m68328_console_baud)
1391 break;
1392 if (i >= ARRAY_SIZE(baud_table)) {
1393 m68328_console_baud = 9600;
1394 goto again;
1395 }
1396
1397 UBAUD = PUT_FIELD(UBAUD_DIVIDE, hw_baud_table[i].divisor) |
1398 PUT_FIELD(UBAUD_PRESCALER, hw_baud_table[i].prescale);
1399 ustcnt &= ~(USTCNT_PARITYEN | USTCNT_ODD_EVEN | USTCNT_STOP | USTCNT_8_7);
1400 ustcnt |= USTCNT_8_7;
1401 ustcnt |= USTCNT_TXEN;
1402 USTCNT = ustcnt;
1403 m68328_console_initted = 1;
1404 return;
1405}
1406
1407
1408int m68328_console_setup(struct console *cp, char *arg)
1409{
1410 int i, n = CONSOLE_BAUD_RATE;
1411
1412 if (!cp)
1413 return(-1);
1414
1415 if (arg)
1416 n = simple_strtoul(arg,NULL,0);
1417
1418 for (i = 0; i < ARRAY_SIZE(baud_table); i++)
1419 if (baud_table[i] == n)
1420 break;
1421 if (i < ARRAY_SIZE(baud_table)) {
1422 m68328_console_baud = n;
1423 m68328_console_cbaud = 0;
1424 if (i > 15) {
1425 m68328_console_cbaud |= CBAUDEX;
1426 i -= 15;
1427 }
1428 m68328_console_cbaud |= i;
1429 }
1430
1431 m68328_set_baud(); /* make sure baud rate changes */
1432 return(0);
1433}
1434
1435
1436static struct tty_driver *m68328_console_device(struct console *c, int *index)
1437{
1438 *index = c->index;
1439 return serial_driver;
1440}
1441
1442
1443void m68328_console_write (struct console *co, const char *str,
1444 unsigned int count)
1445{
1446 if (!m68328_console_initted)
1447 m68328_set_baud();
1448 while (count--) {
1449 if (*str == '\n')
1450 rs_put_char('\r');
1451 rs_put_char( *str++ );
1452 }
1453}
1454
1455
1456static struct console m68328_driver = {
1457 .name = "ttyS",
1458 .write = m68328_console_write,
1459 .device = m68328_console_device,
1460 .setup = m68328_console_setup,
1461 .flags = CON_PRINTBUFFER,
1462 .index = -1,
1463};
1464
1465
1466static int __init m68328_console_init(void)
1467{
1468 register_console(&m68328_driver);
1469 return 0;
1470}
1471
1472console_initcall(m68328_console_init);
diff --git a/drivers/serial/68328serial.h b/drivers/serial/68328serial.h
deleted file mode 100644
index 58aa2154655b..000000000000
--- a/drivers/serial/68328serial.h
+++ /dev/null
@@ -1,193 +0,0 @@
1/* 68328serial.h: Definitions for the mc68328 serial driver.
2 *
3 * Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu>
4 * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>
5 * Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org>
6 * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
7 *
8 * VZ Support/Fixes Evan Stawnyczy <e@lineo.ca>
9 */
10
11#ifndef _MC683XX_SERIAL_H
12#define _MC683XX_SERIAL_H
13
14
15struct serial_struct {
16 int type;
17 int line;
18 int port;
19 int irq;
20 int flags;
21 int xmit_fifo_size;
22 int custom_divisor;
23 int baud_base;
24 unsigned short close_delay;
25 char reserved_char[2];
26 int hub6; /* FIXME: We don't have AT&T Hub6 boards! */
27 unsigned short closing_wait; /* time to wait before closing */
28 unsigned short closing_wait2; /* no longer used... */
29 int reserved[4];
30};
31
32/*
33 * For the close wait times, 0 means wait forever for serial port to
34 * flush its output. 65535 means don't wait at all.
35 */
36#define S_CLOSING_WAIT_INF 0
37#define S_CLOSING_WAIT_NONE 65535
38
39/*
40 * Definitions for S_struct (and serial_struct) flags field
41 */
42#define S_HUP_NOTIFY 0x0001 /* Notify getty on hangups and closes
43 on the callout port */
44#define S_FOURPORT 0x0002 /* Set OU1, OUT2 per AST Fourport settings */
45#define S_SAK 0x0004 /* Secure Attention Key (Orange book) */
46#define S_SPLIT_TERMIOS 0x0008 /* Separate termios for dialin/callout */
47
48#define S_SPD_MASK 0x0030
49#define S_SPD_HI 0x0010 /* Use 56000 instead of 38400 bps */
50
51#define S_SPD_VHI 0x0020 /* Use 115200 instead of 38400 bps */
52#define S_SPD_CUST 0x0030 /* Use user-specified divisor */
53
54#define S_SKIP_TEST 0x0040 /* Skip UART test during autoconfiguration */
55#define S_AUTO_IRQ 0x0080 /* Do automatic IRQ during autoconfiguration */
56#define S_SESSION_LOCKOUT 0x0100 /* Lock out cua opens based on session */
57#define S_PGRP_LOCKOUT 0x0200 /* Lock out cua opens based on pgrp */
58#define S_CALLOUT_NOHUP 0x0400 /* Don't do hangups for cua device */
59
60#define S_FLAGS 0x0FFF /* Possible legal S flags */
61#define S_USR_MASK 0x0430 /* Legal flags that non-privileged
62 * users can set or reset */
63
64/* Internal flags used only by kernel/chr_drv/serial.c */
65#define S_INITIALIZED 0x80000000 /* Serial port was initialized */
66#define S_CALLOUT_ACTIVE 0x40000000 /* Call out device is active */
67#define S_NORMAL_ACTIVE 0x20000000 /* Normal device is active */
68#define S_BOOT_AUTOCONF 0x10000000 /* Autoconfigure port on bootup */
69#define S_CLOSING 0x08000000 /* Serial port is closing */
70#define S_CTS_FLOW 0x04000000 /* Do CTS flow control */
71#define S_CHECK_CD 0x02000000 /* i.e., CLOCAL */
72
73/* Software state per channel */
74
75#ifdef __KERNEL__
76
77/*
78 * I believe this is the optimal setting that reduces the number of interrupts.
79 * At high speeds the output might become a little "bursted" (use USTCNT_TXHE
80 * if that bothers you), but in most cases it will not, since we try to
81 * transmit characters every time rs_interrupt is called. Thus, quite often
82 * you'll see that a receive interrupt occures before the transmit one.
83 * -- Vladimir Gurevich
84 */
85#define USTCNT_TX_INTR_MASK (USTCNT_TXEE)
86
87/*
88 * 68328 and 68EZ328 UARTS are a little bit different. EZ328 has special
89 * "Old data interrupt" which occures whenever the data stay in the FIFO
90 * longer than 30 bits time. This allows us to use FIFO without compromising
91 * latency. '328 does not have this feature and without the real 328-based
92 * board I would assume that RXRE is the safest setting.
93 *
94 * For EZ328 I use RXHE (Half empty) interrupt to reduce the number of
95 * interrupts. RXFE (receive queue full) causes the system to lose data
96 * at least at 115200 baud
97 *
98 * If your board is busy doing other stuff, you might consider to use
99 * RXRE (data ready intrrupt) instead.
100 *
101 * The other option is to make these INTR masks run-time configurable, so
102 * that people can dynamically adapt them according to the current usage.
103 * -- Vladimir Gurevich
104 */
105
106/* (es) */
107#if defined(CONFIG_M68EZ328) || defined(CONFIG_M68VZ328)
108#define USTCNT_RX_INTR_MASK (USTCNT_RXHE | USTCNT_ODEN)
109#elif defined(CONFIG_M68328)
110#define USTCNT_RX_INTR_MASK (USTCNT_RXRE)
111#else
112#error Please, define the Rx interrupt events for your CPU
113#endif
114/* (/es) */
115
116/*
117 * This is our internal structure for each serial port's state.
118 *
119 * Many fields are paralleled by the structure used by the serial_struct
120 * structure.
121 *
122 * For definitions of the flags field, see tty.h
123 */
124
125struct m68k_serial {
126 char soft_carrier; /* Use soft carrier on this channel */
127 char break_abort; /* Is serial console in, so process brk/abrt */
128 char is_cons; /* Is this our console. */
129
130 /* We need to know the current clock divisor
131 * to read the bps rate the chip has currently
132 * loaded.
133 */
134 unsigned char clk_divisor; /* May be 1, 16, 32, or 64 */
135 int baud;
136 int magic;
137 int baud_base;
138 int port;
139 int irq;
140 int flags; /* defined in tty.h */
141 int type; /* UART type */
142 struct tty_struct *tty;
143 int read_status_mask;
144 int ignore_status_mask;
145 int timeout;
146 int xmit_fifo_size;
147 int custom_divisor;
148 int x_char; /* xon/xoff character */
149 int close_delay;
150 unsigned short closing_wait;
151 unsigned short closing_wait2;
152 unsigned long event;
153 unsigned long last_active;
154 int line;
155 int count; /* # of fd on device */
156 int blocked_open; /* # of blocked opens */
157 unsigned char *xmit_buf;
158 int xmit_head;
159 int xmit_tail;
160 int xmit_cnt;
161 struct work_struct tqueue;
162 struct work_struct tqueue_hangup;
163 wait_queue_head_t open_wait;
164 wait_queue_head_t close_wait;
165};
166
167
168#define SERIAL_MAGIC 0x5301
169
170/*
171 * The size of the serial xmit buffer is 1 page, or 4096 bytes
172 */
173#define SERIAL_XMIT_SIZE 4096
174
175/*
176 * Events are used to schedule things to happen at timer-interrupt
177 * time, instead of at rs interrupt time.
178 */
179#define RS_EVENT_WRITE_WAKEUP 0
180
181/*
182 * Define the number of ports supported and their irqs.
183 */
184#ifndef CONFIG_68328_SERIAL_UART2
185#define NR_PORTS 1
186#define UART_IRQ_DEFNS {UART_IRQ_NUM}
187#else
188#define NR_PORTS 2
189#define UART_IRQ_DEFNS {UART1_IRQ_NUM, UART2_IRQ_NUM}
190#endif
191
192#endif /* __KERNEL__ */
193#endif /* !(_MC683XX_SERIAL_H) */
diff --git a/drivers/serial/68360serial.c b/drivers/serial/68360serial.c
deleted file mode 100644
index 0dff3bbddc8b..000000000000
--- a/drivers/serial/68360serial.c
+++ /dev/null
@@ -1,2979 +0,0 @@
1/*
2 * UART driver for 68360 CPM SCC or SMC
3 * Copyright (c) 2000 D. Jeff Dionne <jeff@uclinux.org>,
4 * Copyright (c) 2000 Michael Leslie <mleslie@lineo.ca>
5 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
6 *
7 * I used the serial.c driver as the framework for this driver.
8 * Give credit to those guys.
9 * The original code was written for the MBX860 board. I tried to make
10 * it generic, but there may be some assumptions in the structures that
11 * have to be fixed later.
12 * To save porting time, I did not bother to change any object names
13 * that are not accessed outside of this file.
14 * It still needs lots of work........When it was easy, I included code
15 * to support the SCCs, but this has never been tested, nor is it complete.
16 * Only the SCCs support modem control, so that is not complete either.
17 *
18 * This module exports the following rs232 io functions:
19 *
20 * int rs_360_init(void);
21 */
22
23#include <linux/module.h>
24#include <linux/errno.h>
25#include <linux/signal.h>
26#include <linux/sched.h>
27#include <linux/timer.h>
28#include <linux/interrupt.h>
29#include <linux/tty.h>
30#include <linux/tty_flip.h>
31#include <linux/serial.h>
32#include <linux/serialP.h>
33#include <linux/major.h>
34#include <linux/string.h>
35#include <linux/fcntl.h>
36#include <linux/ptrace.h>
37#include <linux/mm.h>
38#include <linux/init.h>
39#include <linux/delay.h>
40#include <asm/irq.h>
41#include <asm/m68360.h>
42#include <asm/commproc.h>
43
44
45#ifdef CONFIG_KGDB
46extern void breakpoint(void);
47extern void set_debug_traps(void);
48extern int kgdb_output_string (const char* s, unsigned int count);
49#endif
50
51
52/* #ifdef CONFIG_SERIAL_CONSOLE */ /* This seems to be a post 2.0 thing - mles */
53#include <linux/console.h>
54#include <linux/jiffies.h>
55
56/* this defines the index into rs_table for the port to use
57 */
58#ifndef CONFIG_SERIAL_CONSOLE_PORT
59#define CONFIG_SERIAL_CONSOLE_PORT 1 /* ie SMC2 - note USE_SMC2 must be defined */
60#endif
61/* #endif */
62
63#if 0
64/* SCC2 for console
65 */
66#undef CONFIG_SERIAL_CONSOLE_PORT
67#define CONFIG_SERIAL_CONSOLE_PORT 2
68#endif
69
70
71#define TX_WAKEUP ASYNC_SHARE_IRQ
72
73static char *serial_name = "CPM UART driver";
74static char *serial_version = "0.03";
75
76static struct tty_driver *serial_driver;
77int serial_console_setup(struct console *co, char *options);
78
79/*
80 * Serial driver configuration section. Here are the various options:
81 */
82#define SERIAL_PARANOIA_CHECK
83#define CONFIG_SERIAL_NOPAUSE_IO
84#define SERIAL_DO_RESTART
85
86/* Set of debugging defines */
87
88#undef SERIAL_DEBUG_INTR
89#undef SERIAL_DEBUG_OPEN
90#undef SERIAL_DEBUG_FLOW
91#undef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
92
93#define _INLINE_ inline
94
95#define DBG_CNT(s)
96
97/* We overload some of the items in the data structure to meet our
98 * needs. For example, the port address is the CPM parameter ram
99 * offset for the SCC or SMC. The maximum number of ports is 4 SCCs and
100 * 2 SMCs. The "hub6" field is used to indicate the channel number, with
101 * a flag indicating SCC or SMC, and the number is used as an index into
102 * the CPM parameter area for this device.
103 * The "type" field is currently set to 0, for PORT_UNKNOWN. It is
104 * not currently used. I should probably use it to indicate the port
105 * type of SMC or SCC.
106 * The SMCs do not support any modem control signals.
107 */
108#define smc_scc_num hub6
109#define NUM_IS_SCC ((int)0x00010000)
110#define PORT_NUM(P) ((P) & 0x0000ffff)
111
112
113#if defined (CONFIG_UCQUICC)
114
115volatile extern void *_periph_base;
116/* sipex transceiver
117 * mode bits for are on pins
118 *
119 * SCC2 d16..19
120 * SCC3 d20..23
121 * SCC4 d24..27
122 */
123#define SIPEX_MODE(n,m) ((m & 0x0f)<<(16+4*(n-1)))
124
125static uint sipex_mode_bits = 0x00000000;
126
127#endif
128
129/* There is no `serial_state' defined back here in 2.0.
130 * Try to get by with serial_struct
131 */
132/* #define serial_state serial_struct */
133
134/* 2.4 -> 2.0 portability problem: async_icount in 2.4 has a few
135 * extras: */
136
137#if 0
138struct async_icount_24 {
139 __u32 cts, dsr, rng, dcd, tx, rx;
140 __u32 frame, parity, overrun, brk;
141 __u32 buf_overrun;
142} icount;
143#endif
144
145#if 0
146
147struct serial_state {
148 int magic;
149 int baud_base;
150 unsigned long port;
151 int irq;
152 int flags;
153 int hub6;
154 int type;
155 int line;
156 int revision; /* Chip revision (950) */
157 int xmit_fifo_size;
158 int custom_divisor;
159 int count;
160 u8 *iomem_base;
161 u16 iomem_reg_shift;
162 unsigned short close_delay;
163 unsigned short closing_wait; /* time to wait before closing */
164 struct async_icount_24 icount;
165 int io_type;
166 struct async_struct *info;
167};
168#endif
169
170#define SSTATE_MAGIC 0x5302
171
172
173
174/* SMC2 is sometimes used for low performance TDM interfaces. Define
175 * this as 1 if you want SMC2 as a serial port UART managed by this driver.
176 * Define this as 0 if you wish to use SMC2 for something else.
177 */
178#define USE_SMC2 1
179
180#if 0
181/* Define SCC to ttySx mapping. */
182#define SCC_NUM_BASE (USE_SMC2 + 1) /* SCC base tty "number" */
183
184/* Define which SCC is the first one to use for a serial port. These
185 * are 0-based numbers, i.e. this assumes the first SCC (SCC1) is used
186 * for Ethernet, and the first available SCC for serial UART is SCC2.
187 * NOTE: IF YOU CHANGE THIS, you have to change the PROFF_xxx and
188 * interrupt vectors in the table below to match.
189 */
190#define SCC_IDX_BASE 1 /* table index */
191#endif
192
193
194/* Processors other than the 860 only get SMCs configured by default.
195 * Either they don't have SCCs or they are allocated somewhere else.
196 * Of course, there are now 860s without some SCCs, so we will need to
197 * address that someday.
198 * The Embedded Planet Multimedia I/O cards use TDM interfaces to the
199 * stereo codec parts, and we use SMC2 to help support that.
200 */
201static struct serial_state rs_table[] = {
202/* type line PORT IRQ FLAGS smc_scc_num (F.K.A. hub6) */
203 { 0, 0, PRSLOT_SMC1, CPMVEC_SMC1, 0, 0 } /* SMC1 ttyS0 */
204#if USE_SMC2
205 ,{ 0, 0, PRSLOT_SMC2, CPMVEC_SMC2, 0, 1 } /* SMC2 ttyS1 */
206#endif
207
208#if defined(CONFIG_SERIAL_68360_SCC)
209 ,{ 0, 0, PRSLOT_SCC2, CPMVEC_SCC2, 0, (NUM_IS_SCC | 1) } /* SCC2 ttyS2 */
210 ,{ 0, 0, PRSLOT_SCC3, CPMVEC_SCC3, 0, (NUM_IS_SCC | 2) } /* SCC3 ttyS3 */
211 ,{ 0, 0, PRSLOT_SCC4, CPMVEC_SCC4, 0, (NUM_IS_SCC | 3) } /* SCC4 ttyS4 */
212#endif
213};
214
215#define NR_PORTS (sizeof(rs_table)/sizeof(struct serial_state))
216
217/* The number of buffer descriptors and their sizes.
218 */
219#define RX_NUM_FIFO 4
220#define RX_BUF_SIZE 32
221#define TX_NUM_FIFO 4
222#define TX_BUF_SIZE 32
223
224#define CONSOLE_NUM_FIFO 2
225#define CONSOLE_BUF_SIZE 4
226
227char *console_fifos[CONSOLE_NUM_FIFO * CONSOLE_BUF_SIZE];
228
229/* The async_struct in serial.h does not really give us what we
230 * need, so define our own here.
231 */
232typedef struct serial_info {
233 int magic;
234 int flags;
235
236 struct serial_state *state;
237 /* struct serial_struct *state; */
238 /* struct async_struct *state; */
239
240 struct tty_struct *tty;
241 int read_status_mask;
242 int ignore_status_mask;
243 int timeout;
244 int line;
245 int x_char; /* xon/xoff character */
246 int close_delay;
247 unsigned short closing_wait;
248 unsigned short closing_wait2;
249 unsigned long event;
250 unsigned long last_active;
251 int blocked_open; /* # of blocked opens */
252 struct work_struct tqueue;
253 struct work_struct tqueue_hangup;
254 wait_queue_head_t open_wait;
255 wait_queue_head_t close_wait;
256
257
258/* CPM Buffer Descriptor pointers.
259 */
260 QUICC_BD *rx_bd_base;
261 QUICC_BD *rx_cur;
262 QUICC_BD *tx_bd_base;
263 QUICC_BD *tx_cur;
264} ser_info_t;
265
266
267/* since kmalloc_init() does not get called until much after this initialization: */
268static ser_info_t quicc_ser_info[NR_PORTS];
269static char rx_buf_pool[NR_PORTS * RX_NUM_FIFO * RX_BUF_SIZE];
270static char tx_buf_pool[NR_PORTS * TX_NUM_FIFO * TX_BUF_SIZE];
271
272static void change_speed(ser_info_t *info);
273static void rs_360_wait_until_sent(struct tty_struct *tty, int timeout);
274
275static inline int serial_paranoia_check(ser_info_t *info,
276 char *name, const char *routine)
277{
278#ifdef SERIAL_PARANOIA_CHECK
279 static const char *badmagic =
280 "Warning: bad magic number for serial struct (%s) in %s\n";
281 static const char *badinfo =
282 "Warning: null async_struct for (%s) in %s\n";
283
284 if (!info) {
285 printk(badinfo, name, routine);
286 return 1;
287 }
288 if (info->magic != SERIAL_MAGIC) {
289 printk(badmagic, name, routine);
290 return 1;
291 }
292#endif
293 return 0;
294}
295
296/*
297 * This is used to figure out the divisor speeds and the timeouts,
298 * indexed by the termio value. The generic CPM functions are responsible
299 * for setting and assigning baud rate generators for us.
300 */
301static int baud_table[] = {
302 0, 50, 75, 110, 134, 150, 200, 300, 600, 1200, 1800, 2400, 4800,
303 9600, 19200, 38400, 57600, 115200, 230400, 460800, 0 };
304
305/* This sucks. There is a better way: */
306#if defined(CONFIG_CONSOLE_9600)
307 #define CONSOLE_BAUDRATE 9600
308#elif defined(CONFIG_CONSOLE_19200)
309 #define CONSOLE_BAUDRATE 19200
310#elif defined(CONFIG_CONSOLE_115200)
311 #define CONSOLE_BAUDRATE 115200
312#else
313 #warning "console baud rate undefined"
314 #define CONSOLE_BAUDRATE 9600
315#endif
316
317/*
318 * ------------------------------------------------------------
319 * rs_stop() and rs_start()
320 *
321 * This routines are called before setting or resetting tty->stopped.
322 * They enable or disable transmitter interrupts, as necessary.
323 * ------------------------------------------------------------
324 */
325static void rs_360_stop(struct tty_struct *tty)
326{
327 ser_info_t *info = (ser_info_t *)tty->driver_data;
328 int idx;
329 unsigned long flags;
330 volatile struct scc_regs *sccp;
331 volatile struct smc_regs *smcp;
332
333 if (serial_paranoia_check(info, tty->name, "rs_stop"))
334 return;
335
336 local_irq_save(flags);
337 idx = PORT_NUM(info->state->smc_scc_num);
338 if (info->state->smc_scc_num & NUM_IS_SCC) {
339 sccp = &pquicc->scc_regs[idx];
340 sccp->scc_sccm &= ~UART_SCCM_TX;
341 } else {
342 /* smcp = &cpmp->cp_smc[idx]; */
343 smcp = &pquicc->smc_regs[idx];
344 smcp->smc_smcm &= ~SMCM_TX;
345 }
346 local_irq_restore(flags);
347}
348
349
350static void rs_360_start(struct tty_struct *tty)
351{
352 ser_info_t *info = (ser_info_t *)tty->driver_data;
353 int idx;
354 unsigned long flags;
355 volatile struct scc_regs *sccp;
356 volatile struct smc_regs *smcp;
357
358 if (serial_paranoia_check(info, tty->name, "rs_stop"))
359 return;
360
361 local_irq_save(flags);
362 idx = PORT_NUM(info->state->smc_scc_num);
363 if (info->state->smc_scc_num & NUM_IS_SCC) {
364 sccp = &pquicc->scc_regs[idx];
365 sccp->scc_sccm |= UART_SCCM_TX;
366 } else {
367 smcp = &pquicc->smc_regs[idx];
368 smcp->smc_smcm |= SMCM_TX;
369 }
370 local_irq_restore(flags);
371}
372
373/*
374 * ----------------------------------------------------------------------
375 *
376 * Here starts the interrupt handling routines. All of the following
377 * subroutines are declared as inline and are folded into
378 * rs_interrupt(). They were separated out for readability's sake.
379 *
380 * Note: rs_interrupt() is a "fast" interrupt, which means that it
381 * runs with interrupts turned off. People who may want to modify
382 * rs_interrupt() should try to keep the interrupt handler as fast as
383 * possible. After you are done making modifications, it is not a bad
384 * idea to do:
385 *
386 * gcc -S -DKERNEL -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer serial.c
387 *
388 * and look at the resulting assemble code in serial.s.
389 *
390 * - Ted Ts'o (tytso@mit.edu), 7-Mar-93
391 * -----------------------------------------------------------------------
392 */
393
394static _INLINE_ void receive_chars(ser_info_t *info)
395{
396 struct tty_struct *tty = info->port.tty;
397 unsigned char ch, flag, *cp;
398 /*int ignored = 0;*/
399 int i;
400 ushort status;
401 struct async_icount *icount;
402 /* struct async_icount_24 *icount; */
403 volatile QUICC_BD *bdp;
404
405 icount = &info->state->icount;
406
407 /* Just loop through the closed BDs and copy the characters into
408 * the buffer.
409 */
410 bdp = info->rx_cur;
411 for (;;) {
412 if (bdp->status & BD_SC_EMPTY) /* If this one is empty */
413 break; /* we are all done */
414
415 /* The read status mask tell us what we should do with
416 * incoming characters, especially if errors occur.
417 * One special case is the use of BD_SC_EMPTY. If
418 * this is not set, we are supposed to be ignoring
419 * inputs. In this case, just mark the buffer empty and
420 * continue.
421 */
422 if (!(info->read_status_mask & BD_SC_EMPTY)) {
423 bdp->status |= BD_SC_EMPTY;
424 bdp->status &=
425 ~(BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV);
426
427 if (bdp->status & BD_SC_WRAP)
428 bdp = info->rx_bd_base;
429 else
430 bdp++;
431 continue;
432 }
433
434 /* Get the number of characters and the buffer pointer.
435 */
436 i = bdp->length;
437 /* cp = (unsigned char *)__va(bdp->buf); */
438 cp = (char *)bdp->buf;
439 status = bdp->status;
440
441 while (i-- > 0) {
442 ch = *cp++;
443 icount->rx++;
444
445#ifdef SERIAL_DEBUG_INTR
446 printk("DR%02x:%02x...", ch, status);
447#endif
448 flag = TTY_NORMAL;
449
450 if (status & (BD_SC_BR | BD_SC_FR |
451 BD_SC_PR | BD_SC_OV)) {
452 /*
453 * For statistics only
454 */
455 if (status & BD_SC_BR)
456 icount->brk++;
457 else if (status & BD_SC_PR)
458 icount->parity++;
459 else if (status & BD_SC_FR)
460 icount->frame++;
461 if (status & BD_SC_OV)
462 icount->overrun++;
463
464 /*
465 * Now check to see if character should be
466 * ignored, and mask off conditions which
467 * should be ignored.
468 if (status & info->ignore_status_mask) {
469 if (++ignored > 100)
470 break;
471 continue;
472 }
473 */
474 status &= info->read_status_mask;
475
476 if (status & (BD_SC_BR)) {
477#ifdef SERIAL_DEBUG_INTR
478 printk("handling break....");
479#endif
480 *tty->flip.flag_buf_ptr = TTY_BREAK;
481 if (info->flags & ASYNC_SAK)
482 do_SAK(tty);
483 } else if (status & BD_SC_PR)
484 flag = TTY_PARITY;
485 else if (status & BD_SC_FR)
486 flag = TTY_FRAME;
487 }
488 tty_insert_flip_char(tty, ch, flag);
489 if (status & BD_SC_OV)
490 /*
491 * Overrun is special, since it's
492 * reported immediately, and doesn't
493 * affect the current character
494 */
495 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
496 }
497
498 /* This BD is ready to be used again. Clear status.
499 * Get next BD.
500 */
501 bdp->status |= BD_SC_EMPTY;
502 bdp->status &= ~(BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV);
503
504 if (bdp->status & BD_SC_WRAP)
505 bdp = info->rx_bd_base;
506 else
507 bdp++;
508 }
509
510 info->rx_cur = (QUICC_BD *)bdp;
511
512 tty_schedule_flip(tty);
513}
514
515static _INLINE_ void receive_break(ser_info_t *info)
516{
517 struct tty_struct *tty = info->port.tty;
518
519 info->state->icount.brk++;
520 /* Check to see if there is room in the tty buffer for
521 * the break. If not, we exit now, losing the break. FIXME
522 */
523 tty_insert_flip_char(tty, 0, TTY_BREAK);
524 tty_schedule_flip(tty);
525}
526
527static _INLINE_ void transmit_chars(ser_info_t *info)
528{
529
530 if ((info->flags & TX_WAKEUP) ||
531 (info->port.tty->flags & (1 << TTY_DO_WRITE_WAKEUP))) {
532 schedule_work(&info->tqueue);
533 }
534
535#ifdef SERIAL_DEBUG_INTR
536 printk("THRE...");
537#endif
538}
539
540#ifdef notdef
541 /* I need to do this for the SCCs, so it is left as a reminder.
542 */
543static _INLINE_ void check_modem_status(struct async_struct *info)
544{
545 int status;
546 /* struct async_icount *icount; */
547 struct async_icount_24 *icount;
548
549 status = serial_in(info, UART_MSR);
550
551 if (status & UART_MSR_ANY_DELTA) {
552 icount = &info->state->icount;
553 /* update input line counters */
554 if (status & UART_MSR_TERI)
555 icount->rng++;
556 if (status & UART_MSR_DDSR)
557 icount->dsr++;
558 if (status & UART_MSR_DDCD) {
559 icount->dcd++;
560#ifdef CONFIG_HARD_PPS
561 if ((info->flags & ASYNC_HARDPPS_CD) &&
562 (status & UART_MSR_DCD))
563 hardpps();
564#endif
565 }
566 if (status & UART_MSR_DCTS)
567 icount->cts++;
568 wake_up_interruptible(&info->delta_msr_wait);
569 }
570
571 if ((info->flags & ASYNC_CHECK_CD) && (status & UART_MSR_DDCD)) {
572#if (defined(SERIAL_DEBUG_OPEN) || defined(SERIAL_DEBUG_INTR))
573 printk("ttys%d CD now %s...", info->line,
574 (status & UART_MSR_DCD) ? "on" : "off");
575#endif
576 if (status & UART_MSR_DCD)
577 wake_up_interruptible(&info->open_wait);
578 else {
579#ifdef SERIAL_DEBUG_OPEN
580 printk("scheduling hangup...");
581#endif
582 queue_task(&info->tqueue_hangup,
583 &tq_scheduler);
584 }
585 }
586 if (info->flags & ASYNC_CTS_FLOW) {
587 if (info->port.tty->hw_stopped) {
588 if (status & UART_MSR_CTS) {
589#if (defined(SERIAL_DEBUG_INTR) || defined(SERIAL_DEBUG_FLOW))
590 printk("CTS tx start...");
591#endif
592 info->port.tty->hw_stopped = 0;
593 info->IER |= UART_IER_THRI;
594 serial_out(info, UART_IER, info->IER);
595 rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
596 return;
597 }
598 } else {
599 if (!(status & UART_MSR_CTS)) {
600#if (defined(SERIAL_DEBUG_INTR) || defined(SERIAL_DEBUG_FLOW))
601 printk("CTS tx stop...");
602#endif
603 info->port.tty->hw_stopped = 1;
604 info->IER &= ~UART_IER_THRI;
605 serial_out(info, UART_IER, info->IER);
606 }
607 }
608 }
609}
610#endif
611
612/*
613 * This is the serial driver's interrupt routine for a single port
614 */
615/* static void rs_360_interrupt(void *dev_id) */ /* until and if we start servicing irqs here */
616static void rs_360_interrupt(int vec, void *dev_id)
617{
618 u_char events;
619 int idx;
620 ser_info_t *info;
621 volatile struct smc_regs *smcp;
622 volatile struct scc_regs *sccp;
623
624 info = dev_id;
625
626 idx = PORT_NUM(info->state->smc_scc_num);
627 if (info->state->smc_scc_num & NUM_IS_SCC) {
628 sccp = &pquicc->scc_regs[idx];
629 events = sccp->scc_scce;
630 if (events & SCCM_RX)
631 receive_chars(info);
632 if (events & SCCM_TX)
633 transmit_chars(info);
634 sccp->scc_scce = events;
635 } else {
636 smcp = &pquicc->smc_regs[idx];
637 events = smcp->smc_smce;
638 if (events & SMCM_BRKE)
639 receive_break(info);
640 if (events & SMCM_RX)
641 receive_chars(info);
642 if (events & SMCM_TX)
643 transmit_chars(info);
644 smcp->smc_smce = events;
645 }
646
647#ifdef SERIAL_DEBUG_INTR
648 printk("rs_interrupt_single(%d, %x)...",
649 info->state->smc_scc_num, events);
650#endif
651#ifdef modem_control
652 check_modem_status(info);
653#endif
654 info->last_active = jiffies;
655#ifdef SERIAL_DEBUG_INTR
656 printk("end.\n");
657#endif
658}
659
660
661/*
662 * -------------------------------------------------------------------
663 * Here ends the serial interrupt routines.
664 * -------------------------------------------------------------------
665 */
666
667
668static void do_softint(void *private_)
669{
670 ser_info_t *info = (ser_info_t *) private_;
671 struct tty_struct *tty;
672
673 tty = info->port.tty;
674 if (!tty)
675 return;
676
677 if (test_and_clear_bit(RS_EVENT_WRITE_WAKEUP, &info->event))
678 tty_wakeup(tty);
679}
680
681
682/*
683 * This routine is called from the scheduler tqueue when the interrupt
684 * routine has signalled that a hangup has occurred. The path of
685 * hangup processing is:
686 *
687 * serial interrupt routine -> (scheduler tqueue) ->
688 * do_serial_hangup() -> tty->hangup() -> rs_hangup()
689 *
690 */
691static void do_serial_hangup(void *private_)
692{
693 struct async_struct *info = (struct async_struct *) private_;
694 struct tty_struct *tty;
695
696 tty = info->port.tty;
697 if (!tty)
698 return;
699
700 tty_hangup(tty);
701}
702
703
704static int startup(ser_info_t *info)
705{
706 unsigned long flags;
707 int retval=0;
708 int idx;
709 /*struct serial_state *state = info->state;*/
710 volatile struct smc_regs *smcp;
711 volatile struct scc_regs *sccp;
712 volatile struct smc_uart_pram *up;
713 volatile struct uart_pram *scup;
714
715
716 local_irq_save(flags);
717
718 if (info->flags & ASYNC_INITIALIZED) {
719 goto errout;
720 }
721
722#ifdef maybe
723 if (!state->port || !state->type) {
724 if (info->port.tty)
725 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
726 goto errout;
727 }
728#endif
729
730#ifdef SERIAL_DEBUG_OPEN
731 printk("starting up ttys%d (irq %d)...", info->line, state->irq);
732#endif
733
734
735#ifdef modem_control
736 info->MCR = 0;
737 if (info->port.tty->termios->c_cflag & CBAUD)
738 info->MCR = UART_MCR_DTR | UART_MCR_RTS;
739#endif
740
741 if (info->port.tty)
742 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
743
744 /*
745 * and set the speed of the serial port
746 */
747 change_speed(info);
748
749 idx = PORT_NUM(info->state->smc_scc_num);
750 if (info->state->smc_scc_num & NUM_IS_SCC) {
751 sccp = &pquicc->scc_regs[idx];
752 scup = &pquicc->pram[info->state->port].scc.pscc.u;
753
754 scup->mrblr = RX_BUF_SIZE;
755 scup->max_idl = RX_BUF_SIZE;
756
757 sccp->scc_sccm |= (UART_SCCM_TX | UART_SCCM_RX);
758 sccp->scc_gsmr.w.low |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
759
760 } else {
761 smcp = &pquicc->smc_regs[idx];
762
763 /* Enable interrupts and I/O.
764 */
765 smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
766 smcp->smc_smcmr |= (SMCMR_REN | SMCMR_TEN);
767
768 /* We can tune the buffer length and idle characters
769 * to take advantage of the entire incoming buffer size.
770 * If mrblr is something other than 1, maxidl has to be
771 * non-zero or we never get an interrupt. The maxidl
772 * is the number of character times we wait after reception
773 * of the last character before we decide no more characters
774 * are coming.
775 */
776 /* up = (smc_uart_t *)&pquicc->cp_dparam[state->port]; */
777 /* holy unionized structures, Batman: */
778 up = &pquicc->pram[info->state->port].scc.pothers.idma_smc.psmc.u;
779
780 up->mrblr = RX_BUF_SIZE;
781 up->max_idl = RX_BUF_SIZE;
782
783 up->brkcr = 1; /* number of break chars */
784 }
785
786 info->flags |= ASYNC_INITIALIZED;
787 local_irq_restore(flags);
788 return 0;
789
790errout:
791 local_irq_restore(flags);
792 return retval;
793}
794
795/*
796 * This routine will shutdown a serial port; interrupts are disabled, and
797 * DTR is dropped if the hangup on close termio flag is on.
798 */
799static void shutdown(ser_info_t *info)
800{
801 unsigned long flags;
802 struct serial_state *state;
803 int idx;
804 volatile struct smc_regs *smcp;
805 volatile struct scc_regs *sccp;
806
807 if (!(info->flags & ASYNC_INITIALIZED))
808 return;
809
810 state = info->state;
811
812#ifdef SERIAL_DEBUG_OPEN
813 printk("Shutting down serial port %d (irq %d)....", info->line,
814 state->irq);
815#endif
816
817 local_irq_save(flags);
818
819 idx = PORT_NUM(state->smc_scc_num);
820 if (state->smc_scc_num & NUM_IS_SCC) {
821 sccp = &pquicc->scc_regs[idx];
822 sccp->scc_gsmr.w.low &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
823#ifdef CONFIG_SERIAL_CONSOLE
824 /* We can't disable the transmitter if this is the
825 * system console.
826 */
827 if ((state - rs_table) != CONFIG_SERIAL_CONSOLE_PORT)
828#endif
829 sccp->scc_sccm &= ~(UART_SCCM_TX | UART_SCCM_RX);
830 } else {
831 smcp = &pquicc->smc_regs[idx];
832
833 /* Disable interrupts and I/O.
834 */
835 smcp->smc_smcm &= ~(SMCM_RX | SMCM_TX);
836#ifdef CONFIG_SERIAL_CONSOLE
837 /* We can't disable the transmitter if this is the
838 * system console.
839 */
840 if ((state - rs_table) != CONFIG_SERIAL_CONSOLE_PORT)
841#endif
842 smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
843 }
844
845 if (info->port.tty)
846 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
847
848 info->flags &= ~ASYNC_INITIALIZED;
849 local_irq_restore(flags);
850}
851
852/*
853 * This routine is called to set the UART divisor registers to match
854 * the specified baud rate for a serial port.
855 */
856static void change_speed(ser_info_t *info)
857{
858 int baud_rate;
859 unsigned cflag, cval, scval, prev_mode;
860 int i, bits, sbits, idx;
861 unsigned long flags;
862 struct serial_state *state;
863 volatile struct smc_regs *smcp;
864 volatile struct scc_regs *sccp;
865
866 if (!info->port.tty || !info->port.tty->termios)
867 return;
868 cflag = info->port.tty->termios->c_cflag;
869
870 state = info->state;
871
872 /* Character length programmed into the mode register is the
873 * sum of: 1 start bit, number of data bits, 0 or 1 parity bit,
874 * 1 or 2 stop bits, minus 1.
875 * The value 'bits' counts this for us.
876 */
877 cval = 0;
878 scval = 0;
879
880 /* byte size and parity */
881 switch (cflag & CSIZE) {
882 case CS5: bits = 5; break;
883 case CS6: bits = 6; break;
884 case CS7: bits = 7; break;
885 case CS8: bits = 8; break;
886 /* Never happens, but GCC is too dumb to figure it out */
887 default: bits = 8; break;
888 }
889 sbits = bits - 5;
890
891 if (cflag & CSTOPB) {
892 cval |= SMCMR_SL; /* Two stops */
893 scval |= SCU_PMSR_SL;
894 bits++;
895 }
896 if (cflag & PARENB) {
897 cval |= SMCMR_PEN;
898 scval |= SCU_PMSR_PEN;
899 bits++;
900 }
901 if (!(cflag & PARODD)) {
902 cval |= SMCMR_PM_EVEN;
903 scval |= (SCU_PMSR_REVP | SCU_PMSR_TEVP);
904 }
905
906 /* Determine divisor based on baud rate */
907 i = cflag & CBAUD;
908 if (i >= (sizeof(baud_table)/sizeof(int)))
909 baud_rate = 9600;
910 else
911 baud_rate = baud_table[i];
912
913 info->timeout = (TX_BUF_SIZE*HZ*bits);
914 info->timeout += HZ/50; /* Add .02 seconds of slop */
915
916#ifdef modem_control
917 /* CTS flow control flag and modem status interrupts */
918 info->IER &= ~UART_IER_MSI;
919 if (info->flags & ASYNC_HARDPPS_CD)
920 info->IER |= UART_IER_MSI;
921 if (cflag & CRTSCTS) {
922 info->flags |= ASYNC_CTS_FLOW;
923 info->IER |= UART_IER_MSI;
924 } else
925 info->flags &= ~ASYNC_CTS_FLOW;
926 if (cflag & CLOCAL)
927 info->flags &= ~ASYNC_CHECK_CD;
928 else {
929 info->flags |= ASYNC_CHECK_CD;
930 info->IER |= UART_IER_MSI;
931 }
932 serial_out(info, UART_IER, info->IER);
933#endif
934
935 /*
936 * Set up parity check flag
937 */
938 info->read_status_mask = (BD_SC_EMPTY | BD_SC_OV);
939 if (I_INPCK(info->port.tty))
940 info->read_status_mask |= BD_SC_FR | BD_SC_PR;
941 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
942 info->read_status_mask |= BD_SC_BR;
943
944 /*
945 * Characters to ignore
946 */
947 info->ignore_status_mask = 0;
948 if (I_IGNPAR(info->port.tty))
949 info->ignore_status_mask |= BD_SC_PR | BD_SC_FR;
950 if (I_IGNBRK(info->port.tty)) {
951 info->ignore_status_mask |= BD_SC_BR;
952 /*
953 * If we're ignore parity and break indicators, ignore
954 * overruns too. (For real raw support).
955 */
956 if (I_IGNPAR(info->port.tty))
957 info->ignore_status_mask |= BD_SC_OV;
958 }
959 /*
960 * !!! ignore all characters if CREAD is not set
961 */
962 if ((cflag & CREAD) == 0)
963 info->read_status_mask &= ~BD_SC_EMPTY;
964 local_irq_save(flags);
965
966 /* Start bit has not been added (so don't, because we would just
967 * subtract it later), and we need to add one for the number of
968 * stops bits (there is always at least one).
969 */
970 bits++;
971 idx = PORT_NUM(state->smc_scc_num);
972 if (state->smc_scc_num & NUM_IS_SCC) {
973 sccp = &pquicc->scc_regs[idx];
974 sccp->scc_psmr = (sbits << 12) | scval;
975 } else {
976 smcp = &pquicc->smc_regs[idx];
977
978 /* Set the mode register. We want to keep a copy of the
979 * enables, because we want to put them back if they were
980 * present.
981 */
982 prev_mode = smcp->smc_smcmr;
983 smcp->smc_smcmr = smcr_mk_clen(bits) | cval | SMCMR_SM_UART;
984 smcp->smc_smcmr |= (prev_mode & (SMCMR_REN | SMCMR_TEN));
985 }
986
987 m360_cpm_setbrg((state - rs_table), baud_rate);
988
989 local_irq_restore(flags);
990}
991
992static void rs_360_put_char(struct tty_struct *tty, unsigned char ch)
993{
994 ser_info_t *info = (ser_info_t *)tty->driver_data;
995 volatile QUICC_BD *bdp;
996
997 if (serial_paranoia_check(info, tty->name, "rs_put_char"))
998 return 0;
999
1000 if (!tty)
1001 return 0;
1002
1003 bdp = info->tx_cur;
1004 while (bdp->status & BD_SC_READY);
1005
1006 /* *((char *)__va(bdp->buf)) = ch; */
1007 *((char *)bdp->buf) = ch;
1008 bdp->length = 1;
1009 bdp->status |= BD_SC_READY;
1010
1011 /* Get next BD.
1012 */
1013 if (bdp->status & BD_SC_WRAP)
1014 bdp = info->tx_bd_base;
1015 else
1016 bdp++;
1017
1018 info->tx_cur = (QUICC_BD *)bdp;
1019 return 1;
1020
1021}
1022
1023static int rs_360_write(struct tty_struct * tty,
1024 const unsigned char *buf, int count)
1025{
1026 int c, ret = 0;
1027 ser_info_t *info = (ser_info_t *)tty->driver_data;
1028 volatile QUICC_BD *bdp;
1029
1030#ifdef CONFIG_KGDB
1031 /* Try to let stub handle output. Returns true if it did. */
1032 if (kgdb_output_string(buf, count))
1033 return ret;
1034#endif
1035
1036 if (serial_paranoia_check(info, tty->name, "rs_write"))
1037 return 0;
1038
1039 if (!tty)
1040 return 0;
1041
1042 bdp = info->tx_cur;
1043
1044 while (1) {
1045 c = min(count, TX_BUF_SIZE);
1046
1047 if (c <= 0)
1048 break;
1049
1050 if (bdp->status & BD_SC_READY) {
1051 info->flags |= TX_WAKEUP;
1052 break;
1053 }
1054
1055 /* memcpy(__va(bdp->buf), buf, c); */
1056 memcpy((void *)bdp->buf, buf, c);
1057
1058 bdp->length = c;
1059 bdp->status |= BD_SC_READY;
1060
1061 buf += c;
1062 count -= c;
1063 ret += c;
1064
1065 /* Get next BD.
1066 */
1067 if (bdp->status & BD_SC_WRAP)
1068 bdp = info->tx_bd_base;
1069 else
1070 bdp++;
1071 info->tx_cur = (QUICC_BD *)bdp;
1072 }
1073 return ret;
1074}
1075
1076static int rs_360_write_room(struct tty_struct *tty)
1077{
1078 ser_info_t *info = (ser_info_t *)tty->driver_data;
1079 int ret;
1080
1081 if (serial_paranoia_check(info, tty->name, "rs_write_room"))
1082 return 0;
1083
1084 if ((info->tx_cur->status & BD_SC_READY) == 0) {
1085 info->flags &= ~TX_WAKEUP;
1086 ret = TX_BUF_SIZE;
1087 }
1088 else {
1089 info->flags |= TX_WAKEUP;
1090 ret = 0;
1091 }
1092 return ret;
1093}
1094
1095/* I could track this with transmit counters....maybe later.
1096*/
1097static int rs_360_chars_in_buffer(struct tty_struct *tty)
1098{
1099 ser_info_t *info = (ser_info_t *)tty->driver_data;
1100
1101 if (serial_paranoia_check(info, tty->name, "rs_chars_in_buffer"))
1102 return 0;
1103 return 0;
1104}
1105
1106static void rs_360_flush_buffer(struct tty_struct *tty)
1107{
1108 ser_info_t *info = (ser_info_t *)tty->driver_data;
1109
1110 if (serial_paranoia_check(info, tty->name, "rs_flush_buffer"))
1111 return;
1112
1113 /* There is nothing to "flush", whatever we gave the CPM
1114 * is on its way out.
1115 */
1116 tty_wakeup(tty);
1117 info->flags &= ~TX_WAKEUP;
1118}
1119
1120/*
1121 * This function is used to send a high-priority XON/XOFF character to
1122 * the device
1123 */
1124static void rs_360_send_xchar(struct tty_struct *tty, char ch)
1125{
1126 volatile QUICC_BD *bdp;
1127
1128 ser_info_t *info = (ser_info_t *)tty->driver_data;
1129
1130 if (serial_paranoia_check(info, tty->name, "rs_send_char"))
1131 return;
1132
1133 bdp = info->tx_cur;
1134 while (bdp->status & BD_SC_READY);
1135
1136 /* *((char *)__va(bdp->buf)) = ch; */
1137 *((char *)bdp->buf) = ch;
1138 bdp->length = 1;
1139 bdp->status |= BD_SC_READY;
1140
1141 /* Get next BD.
1142 */
1143 if (bdp->status & BD_SC_WRAP)
1144 bdp = info->tx_bd_base;
1145 else
1146 bdp++;
1147
1148 info->tx_cur = (QUICC_BD *)bdp;
1149}
1150
1151/*
1152 * ------------------------------------------------------------
1153 * rs_throttle()
1154 *
1155 * This routine is called by the upper-layer tty layer to signal that
1156 * incoming characters should be throttled.
1157 * ------------------------------------------------------------
1158 */
1159static void rs_360_throttle(struct tty_struct * tty)
1160{
1161 ser_info_t *info = (ser_info_t *)tty->driver_data;
1162#ifdef SERIAL_DEBUG_THROTTLE
1163 char buf[64];
1164
1165 printk("throttle %s: %d....\n", _tty_name(tty, buf),
1166 tty->ldisc.chars_in_buffer(tty));
1167#endif
1168
1169 if (serial_paranoia_check(info, tty->name, "rs_throttle"))
1170 return;
1171
1172 if (I_IXOFF(tty))
1173 rs_360_send_xchar(tty, STOP_CHAR(tty));
1174
1175#ifdef modem_control
1176 if (tty->termios->c_cflag & CRTSCTS)
1177 info->MCR &= ~UART_MCR_RTS;
1178
1179 local_irq_disable();
1180 serial_out(info, UART_MCR, info->MCR);
1181 local_irq_enable();
1182#endif
1183}
1184
1185static void rs_360_unthrottle(struct tty_struct * tty)
1186{
1187 ser_info_t *info = (ser_info_t *)tty->driver_data;
1188#ifdef SERIAL_DEBUG_THROTTLE
1189 char buf[64];
1190
1191 printk("unthrottle %s: %d....\n", _tty_name(tty, buf),
1192 tty->ldisc.chars_in_buffer(tty));
1193#endif
1194
1195 if (serial_paranoia_check(info, tty->name, "rs_unthrottle"))
1196 return;
1197
1198 if (I_IXOFF(tty)) {
1199 if (info->x_char)
1200 info->x_char = 0;
1201 else
1202 rs_360_send_xchar(tty, START_CHAR(tty));
1203 }
1204#ifdef modem_control
1205 if (tty->termios->c_cflag & CRTSCTS)
1206 info->MCR |= UART_MCR_RTS;
1207 local_irq_disable();
1208 serial_out(info, UART_MCR, info->MCR);
1209 local_irq_enable();
1210#endif
1211}
1212
1213/*
1214 * ------------------------------------------------------------
1215 * rs_ioctl() and friends
1216 * ------------------------------------------------------------
1217 */
1218
1219#ifdef maybe
1220/*
1221 * get_lsr_info - get line status register info
1222 *
1223 * Purpose: Let user call ioctl() to get info when the UART physically
1224 * is emptied. On bus types like RS485, the transmitter must
1225 * release the bus after transmitting. This must be done when
1226 * the transmit shift register is empty, not be done when the
1227 * transmit holding register is empty. This functionality
1228 * allows an RS485 driver to be written in user space.
1229 */
1230static int get_lsr_info(struct async_struct * info, unsigned int *value)
1231{
1232 unsigned char status;
1233 unsigned int result;
1234
1235 local_irq_disable();
1236 status = serial_in(info, UART_LSR);
1237 local_irq_enable();
1238 result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0);
1239 return put_user(result,value);
1240}
1241#endif
1242
1243static int rs_360_tiocmget(struct tty_struct *tty, struct file *file)
1244{
1245 ser_info_t *info = (ser_info_t *)tty->driver_data;
1246 unsigned int result = 0;
1247#ifdef modem_control
1248 unsigned char control, status;
1249
1250 if (serial_paranoia_check(info, tty->name, __func__))
1251 return -ENODEV;
1252
1253 if (tty->flags & (1 << TTY_IO_ERROR))
1254 return -EIO;
1255
1256 control = info->MCR;
1257 local_irq_disable();
1258 status = serial_in(info, UART_MSR);
1259 local_irq_enable();
1260 result = ((control & UART_MCR_RTS) ? TIOCM_RTS : 0)
1261 | ((control & UART_MCR_DTR) ? TIOCM_DTR : 0)
1262#ifdef TIOCM_OUT1
1263 | ((control & UART_MCR_OUT1) ? TIOCM_OUT1 : 0)
1264 | ((control & UART_MCR_OUT2) ? TIOCM_OUT2 : 0)
1265#endif
1266 | ((status & UART_MSR_DCD) ? TIOCM_CAR : 0)
1267 | ((status & UART_MSR_RI) ? TIOCM_RNG : 0)
1268 | ((status & UART_MSR_DSR) ? TIOCM_DSR : 0)
1269 | ((status & UART_MSR_CTS) ? TIOCM_CTS : 0);
1270#endif
1271 return result;
1272}
1273
1274static int rs_360_tiocmset(struct tty_struct *tty, struct file *file,
1275 unsigned int set, unsigned int clear)
1276{
1277#ifdef modem_control
1278 ser_info_t *info = (ser_info_t *)tty->driver_data;
1279 unsigned int arg;
1280
1281 if (serial_paranoia_check(info, tty->name, __func__))
1282 return -ENODEV;
1283
1284 if (tty->flags & (1 << TTY_IO_ERROR))
1285 return -EIO;
1286 /* FIXME: locking on info->mcr */
1287 if (set & TIOCM_RTS)
1288 info->mcr |= UART_MCR_RTS;
1289 if (set & TIOCM_DTR)
1290 info->mcr |= UART_MCR_DTR;
1291 if (clear & TIOCM_RTS)
1292 info->MCR &= ~UART_MCR_RTS;
1293 if (clear & TIOCM_DTR)
1294 info->MCR &= ~UART_MCR_DTR;
1295
1296#ifdef TIOCM_OUT1
1297 if (set & TIOCM_OUT1)
1298 info->MCR |= UART_MCR_OUT1;
1299 if (set & TIOCM_OUT2)
1300 info->MCR |= UART_MCR_OUT2;
1301 if (clear & TIOCM_OUT1)
1302 info->MCR &= ~UART_MCR_OUT1;
1303 if (clear & TIOCM_OUT2)
1304 info->MCR &= ~UART_MCR_OUT2;
1305#endif
1306
1307 local_irq_disable();
1308 serial_out(info, UART_MCR, info->MCR);
1309 local_irq_enable();
1310#endif
1311 return 0;
1312}
1313
1314/* Sending a break is a two step process on the SMC/SCC. It is accomplished
1315 * by sending a STOP TRANSMIT command followed by a RESTART TRANSMIT
1316 * command. We take advantage of the begin/end functions to make this
1317 * happen.
1318 */
1319static ushort smc_chan_map[] = {
1320 CPM_CR_CH_SMC1,
1321 CPM_CR_CH_SMC2
1322};
1323
1324static ushort scc_chan_map[] = {
1325 CPM_CR_CH_SCC1,
1326 CPM_CR_CH_SCC2,
1327 CPM_CR_CH_SCC3,
1328 CPM_CR_CH_SCC4
1329};
1330
1331static void begin_break(ser_info_t *info)
1332{
1333 volatile QUICC *cp;
1334 ushort chan;
1335 int idx;
1336
1337 cp = pquicc;
1338
1339 idx = PORT_NUM(info->state->smc_scc_num);
1340 if (info->state->smc_scc_num & NUM_IS_SCC)
1341 chan = scc_chan_map[idx];
1342 else
1343 chan = smc_chan_map[idx];
1344
1345 cp->cp_cr = mk_cr_cmd(chan, CPM_CR_STOP_TX) | CPM_CR_FLG;
1346 while (cp->cp_cr & CPM_CR_FLG);
1347}
1348
1349static void end_break(ser_info_t *info)
1350{
1351 volatile QUICC *cp;
1352 ushort chan;
1353 int idx;
1354
1355 cp = pquicc;
1356
1357 idx = PORT_NUM(info->state->smc_scc_num);
1358 if (info->state->smc_scc_num & NUM_IS_SCC)
1359 chan = scc_chan_map[idx];
1360 else
1361 chan = smc_chan_map[idx];
1362
1363 cp->cp_cr = mk_cr_cmd(chan, CPM_CR_RESTART_TX) | CPM_CR_FLG;
1364 while (cp->cp_cr & CPM_CR_FLG);
1365}
1366
1367/*
1368 * This routine sends a break character out the serial port.
1369 */
1370static void send_break(ser_info_t *info, unsigned int duration)
1371{
1372#ifdef SERIAL_DEBUG_SEND_BREAK
1373 printk("rs_send_break(%d) jiff=%lu...", duration, jiffies);
1374#endif
1375 begin_break(info);
1376 msleep_interruptible(duration);
1377 end_break(info);
1378#ifdef SERIAL_DEBUG_SEND_BREAK
1379 printk("done jiffies=%lu\n", jiffies);
1380#endif
1381}
1382
1383
1384static int rs_360_ioctl(struct tty_struct *tty, struct file * file,
1385 unsigned int cmd, unsigned long arg)
1386{
1387 int error;
1388 ser_info_t *info = (ser_info_t *)tty->driver_data;
1389 int retval;
1390 struct async_icount cnow;
1391 /* struct async_icount_24 cnow;*/ /* kernel counter temps */
1392 struct serial_icounter_struct *p_cuser; /* user space */
1393
1394 if (serial_paranoia_check(info, tty->name, "rs_ioctl"))
1395 return -ENODEV;
1396
1397 if ((cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1398 if (tty->flags & (1 << TTY_IO_ERROR))
1399 return -EIO;
1400 }
1401
1402 switch (cmd) {
1403 case TCSBRK: /* SVID version: non-zero arg --> no break */
1404 retval = tty_check_change(tty);
1405 if (retval)
1406 return retval;
1407 tty_wait_until_sent(tty, 0);
1408 if (signal_pending(current))
1409 return -EINTR;
1410 if (!arg) {
1411 send_break(info, 250); /* 1/4 second */
1412 if (signal_pending(current))
1413 return -EINTR;
1414 }
1415 return 0;
1416 case TCSBRKP: /* support for POSIX tcsendbreak() */
1417 retval = tty_check_change(tty);
1418 if (retval)
1419 return retval;
1420 tty_wait_until_sent(tty, 0);
1421 if (signal_pending(current))
1422 return -EINTR;
1423 send_break(info, arg ? arg*100 : 250);
1424 if (signal_pending(current))
1425 return -EINTR;
1426 return 0;
1427 case TIOCSBRK:
1428 retval = tty_check_change(tty);
1429 if (retval)
1430 return retval;
1431 tty_wait_until_sent(tty, 0);
1432 begin_break(info);
1433 return 0;
1434 case TIOCCBRK:
1435 retval = tty_check_change(tty);
1436 if (retval)
1437 return retval;
1438 end_break(info);
1439 return 0;
1440#ifdef maybe
1441 case TIOCSERGETLSR: /* Get line status register */
1442 return get_lsr_info(info, (unsigned int *) arg);
1443#endif
1444 /*
1445 * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change
1446 * - mask passed in arg for lines of interest
1447 * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking)
1448 * Caller should use TIOCGICOUNT to see which one it was
1449 */
1450 case TIOCMIWAIT:
1451#ifdef modem_control
1452 local_irq_disable();
1453 /* note the counters on entry */
1454 cprev = info->state->icount;
1455 local_irq_enable();
1456 while (1) {
1457 interruptible_sleep_on(&info->delta_msr_wait);
1458 /* see if a signal did it */
1459 if (signal_pending(current))
1460 return -ERESTARTSYS;
1461 local_irq_disable();
1462 cnow = info->state->icount; /* atomic copy */
1463 local_irq_enable();
1464 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
1465 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts)
1466 return -EIO; /* no change => error */
1467 if ( ((arg & TIOCM_RNG) && (cnow.rng != cprev.rng)) ||
1468 ((arg & TIOCM_DSR) && (cnow.dsr != cprev.dsr)) ||
1469 ((arg & TIOCM_CD) && (cnow.dcd != cprev.dcd)) ||
1470 ((arg & TIOCM_CTS) && (cnow.cts != cprev.cts)) ) {
1471 return 0;
1472 }
1473 cprev = cnow;
1474 }
1475 /* NOTREACHED */
1476#else
1477 return 0;
1478#endif
1479
1480 /*
1481 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1482 * Return: write counters to the user passed counter struct
1483 * NB: both 1->0 and 0->1 transitions are counted except for
1484 * RI where only 0->1 is counted.
1485 */
1486 case TIOCGICOUNT:
1487 local_irq_disable();
1488 cnow = info->state->icount;
1489 local_irq_enable();
1490 p_cuser = (struct serial_icounter_struct *) arg;
1491/* error = put_user(cnow.cts, &p_cuser->cts); */
1492/* if (error) return error; */
1493/* error = put_user(cnow.dsr, &p_cuser->dsr); */
1494/* if (error) return error; */
1495/* error = put_user(cnow.rng, &p_cuser->rng); */
1496/* if (error) return error; */
1497/* error = put_user(cnow.dcd, &p_cuser->dcd); */
1498/* if (error) return error; */
1499
1500 put_user(cnow.cts, &p_cuser->cts);
1501 put_user(cnow.dsr, &p_cuser->dsr);
1502 put_user(cnow.rng, &p_cuser->rng);
1503 put_user(cnow.dcd, &p_cuser->dcd);
1504 return 0;
1505
1506 default:
1507 return -ENOIOCTLCMD;
1508 }
1509 return 0;
1510}
1511
1512/* FIX UP modem control here someday......
1513*/
1514static void rs_360_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
1515{
1516 ser_info_t *info = (ser_info_t *)tty->driver_data;
1517
1518 change_speed(info);
1519
1520#ifdef modem_control
1521 /* Handle transition to B0 status */
1522 if ((old_termios->c_cflag & CBAUD) &&
1523 !(tty->termios->c_cflag & CBAUD)) {
1524 info->MCR &= ~(UART_MCR_DTR|UART_MCR_RTS);
1525 local_irq_disable();
1526 serial_out(info, UART_MCR, info->MCR);
1527 local_irq_enable();
1528 }
1529
1530 /* Handle transition away from B0 status */
1531 if (!(old_termios->c_cflag & CBAUD) &&
1532 (tty->termios->c_cflag & CBAUD)) {
1533 info->MCR |= UART_MCR_DTR;
1534 if (!tty->hw_stopped ||
1535 !(tty->termios->c_cflag & CRTSCTS)) {
1536 info->MCR |= UART_MCR_RTS;
1537 }
1538 local_irq_disable();
1539 serial_out(info, UART_MCR, info->MCR);
1540 local_irq_enable();
1541 }
1542
1543 /* Handle turning off CRTSCTS */
1544 if ((old_termios->c_cflag & CRTSCTS) &&
1545 !(tty->termios->c_cflag & CRTSCTS)) {
1546 tty->hw_stopped = 0;
1547 rs_360_start(tty);
1548 }
1549#endif
1550
1551#if 0
1552 /*
1553 * No need to wake up processes in open wait, since they
1554 * sample the CLOCAL flag once, and don't recheck it.
1555 * XXX It's not clear whether the current behavior is correct
1556 * or not. Hence, this may change.....
1557 */
1558 if (!(old_termios->c_cflag & CLOCAL) &&
1559 (tty->termios->c_cflag & CLOCAL))
1560 wake_up_interruptible(&info->open_wait);
1561#endif
1562}
1563
1564/*
1565 * ------------------------------------------------------------
1566 * rs_close()
1567 *
1568 * This routine is called when the serial port gets closed. First, we
1569 * wait for the last remaining data to be sent. Then, we unlink its
1570 * async structure from the interrupt chain if necessary, and we free
1571 * that IRQ if nothing is left in the chain.
1572 * ------------------------------------------------------------
1573 */
1574static void rs_360_close(struct tty_struct *tty, struct file * filp)
1575{
1576 ser_info_t *info = (ser_info_t *)tty->driver_data;
1577 /* struct async_state *state; */
1578 struct serial_state *state;
1579 unsigned long flags;
1580 int idx;
1581 volatile struct smc_regs *smcp;
1582 volatile struct scc_regs *sccp;
1583
1584 if (!info || serial_paranoia_check(info, tty->name, "rs_close"))
1585 return;
1586
1587 state = info->state;
1588
1589 local_irq_save(flags);
1590
1591 if (tty_hung_up_p(filp)) {
1592 DBG_CNT("before DEC-hung");
1593 local_irq_restore(flags);
1594 return;
1595 }
1596
1597#ifdef SERIAL_DEBUG_OPEN
1598 printk("rs_close ttys%d, count = %d\n", info->line, state->count);
1599#endif
1600 if ((tty->count == 1) && (state->count != 1)) {
1601 /*
1602 * Uh, oh. tty->count is 1, which means that the tty
1603 * structure will be freed. state->count should always
1604 * be one in these conditions. If it's greater than
1605 * one, we've got real problems, since it means the
1606 * serial port won't be shutdown.
1607 */
1608 printk("rs_close: bad serial port count; tty->count is 1, "
1609 "state->count is %d\n", state->count);
1610 state->count = 1;
1611 }
1612 if (--state->count < 0) {
1613 printk("rs_close: bad serial port count for ttys%d: %d\n",
1614 info->line, state->count);
1615 state->count = 0;
1616 }
1617 if (state->count) {
1618 DBG_CNT("before DEC-2");
1619 local_irq_restore(flags);
1620 return;
1621 }
1622 info->flags |= ASYNC_CLOSING;
1623 /*
1624 * Now we wait for the transmit buffer to clear; and we notify
1625 * the line discipline to only process XON/XOFF characters.
1626 */
1627 tty->closing = 1;
1628 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE)
1629 tty_wait_until_sent(tty, info->closing_wait);
1630 /*
1631 * At this point we stop accepting input. To do this, we
1632 * disable the receive line status interrupts, and tell the
1633 * interrupt driver to stop checking the data ready bit in the
1634 * line status register.
1635 */
1636 info->read_status_mask &= ~BD_SC_EMPTY;
1637 if (info->flags & ASYNC_INITIALIZED) {
1638
1639 idx = PORT_NUM(info->state->smc_scc_num);
1640 if (info->state->smc_scc_num & NUM_IS_SCC) {
1641 sccp = &pquicc->scc_regs[idx];
1642 sccp->scc_sccm &= ~UART_SCCM_RX;
1643 sccp->scc_gsmr.w.low &= ~SCC_GSMRL_ENR;
1644 } else {
1645 smcp = &pquicc->smc_regs[idx];
1646 smcp->smc_smcm &= ~SMCM_RX;
1647 smcp->smc_smcmr &= ~SMCMR_REN;
1648 }
1649 /*
1650 * Before we drop DTR, make sure the UART transmitter
1651 * has completely drained; this is especially
1652 * important if there is a transmit FIFO!
1653 */
1654 rs_360_wait_until_sent(tty, info->timeout);
1655 }
1656 shutdown(info);
1657 rs_360_flush_buffer(tty);
1658 tty_ldisc_flush(tty);
1659 tty->closing = 0;
1660 info->event = 0;
1661 info->port.tty = NULL;
1662 if (info->blocked_open) {
1663 if (info->close_delay) {
1664 msleep_interruptible(jiffies_to_msecs(info->close_delay));
1665 }
1666 wake_up_interruptible(&info->open_wait);
1667 }
1668 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
1669 wake_up_interruptible(&info->close_wait);
1670 local_irq_restore(flags);
1671}
1672
1673/*
1674 * rs_wait_until_sent() --- wait until the transmitter is empty
1675 */
1676static void rs_360_wait_until_sent(struct tty_struct *tty, int timeout)
1677{
1678 ser_info_t *info = (ser_info_t *)tty->driver_data;
1679 unsigned long orig_jiffies, char_time;
1680 /*int lsr;*/
1681 volatile QUICC_BD *bdp;
1682
1683 if (serial_paranoia_check(info, tty->name, "rs_wait_until_sent"))
1684 return;
1685
1686#ifdef maybe
1687 if (info->state->type == PORT_UNKNOWN)
1688 return;
1689#endif
1690
1691 orig_jiffies = jiffies;
1692 /*
1693 * Set the check interval to be 1/5 of the estimated time to
1694 * send a single character, and make it at least 1. The check
1695 * interval should also be less than the timeout.
1696 *
1697 * Note: we have to use pretty tight timings here to satisfy
1698 * the NIST-PCTS.
1699 */
1700 char_time = 1;
1701 if (timeout)
1702 char_time = min(char_time, (unsigned long)timeout);
1703#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
1704 printk("In rs_wait_until_sent(%d) check=%lu...", timeout, char_time);
1705 printk("jiff=%lu...", jiffies);
1706#endif
1707
1708 /* We go through the loop at least once because we can't tell
1709 * exactly when the last character exits the shifter. There can
1710 * be at least two characters waiting to be sent after the buffers
1711 * are empty.
1712 */
1713 do {
1714#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
1715 printk("lsr = %d (jiff=%lu)...", lsr, jiffies);
1716#endif
1717/* current->counter = 0; make us low-priority */
1718 msleep_interruptible(jiffies_to_msecs(char_time));
1719 if (signal_pending(current))
1720 break;
1721 if (timeout && (time_after(jiffies, orig_jiffies + timeout)))
1722 break;
1723 /* The 'tx_cur' is really the next buffer to send. We
1724 * have to back up to the previous BD and wait for it
1725 * to go. This isn't perfect, because all this indicates
1726 * is the buffer is available. There are still characters
1727 * in the CPM FIFO.
1728 */
1729 bdp = info->tx_cur;
1730 if (bdp == info->tx_bd_base)
1731 bdp += (TX_NUM_FIFO-1);
1732 else
1733 bdp--;
1734 } while (bdp->status & BD_SC_READY);
1735 current->state = TASK_RUNNING;
1736#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
1737 printk("lsr = %d (jiff=%lu)...done\n", lsr, jiffies);
1738#endif
1739}
1740
1741/*
1742 * rs_hangup() --- called by tty_hangup() when a hangup is signaled.
1743 */
1744static void rs_360_hangup(struct tty_struct *tty)
1745{
1746 ser_info_t *info = (ser_info_t *)tty->driver_data;
1747 struct serial_state *state = info->state;
1748
1749 if (serial_paranoia_check(info, tty->name, "rs_hangup"))
1750 return;
1751
1752 state = info->state;
1753
1754 rs_360_flush_buffer(tty);
1755 shutdown(info);
1756 info->event = 0;
1757 state->count = 0;
1758 info->flags &= ~ASYNC_NORMAL_ACTIVE;
1759 info->port.tty = NULL;
1760 wake_up_interruptible(&info->open_wait);
1761}
1762
1763/*
1764 * ------------------------------------------------------------
1765 * rs_open() and friends
1766 * ------------------------------------------------------------
1767 */
1768static int block_til_ready(struct tty_struct *tty, struct file * filp,
1769 ser_info_t *info)
1770{
1771#ifdef DO_THIS_LATER
1772 DECLARE_WAITQUEUE(wait, current);
1773#endif
1774 struct serial_state *state = info->state;
1775 int retval;
1776 int do_clocal = 0;
1777
1778 /*
1779 * If the device is in the middle of being closed, then block
1780 * until it's done, and then try again.
1781 */
1782 if (tty_hung_up_p(filp) ||
1783 (info->flags & ASYNC_CLOSING)) {
1784 if (info->flags & ASYNC_CLOSING)
1785 interruptible_sleep_on(&info->close_wait);
1786#ifdef SERIAL_DO_RESTART
1787 if (info->flags & ASYNC_HUP_NOTIFY)
1788 return -EAGAIN;
1789 else
1790 return -ERESTARTSYS;
1791#else
1792 return -EAGAIN;
1793#endif
1794 }
1795
1796 /*
1797 * If non-blocking mode is set, or the port is not enabled,
1798 * then make the check up front and then exit.
1799 * If this is an SMC port, we don't have modem control to wait
1800 * for, so just get out here.
1801 */
1802 if ((filp->f_flags & O_NONBLOCK) ||
1803 (tty->flags & (1 << TTY_IO_ERROR)) ||
1804 !(info->state->smc_scc_num & NUM_IS_SCC)) {
1805 info->flags |= ASYNC_NORMAL_ACTIVE;
1806 return 0;
1807 }
1808
1809 if (tty->termios->c_cflag & CLOCAL)
1810 do_clocal = 1;
1811
1812 /*
1813 * Block waiting for the carrier detect and the line to become
1814 * free (i.e., not in use by the callout). While we are in
1815 * this loop, state->count is dropped by one, so that
1816 * rs_close() knows when to free things. We restore it upon
1817 * exit, either normal or abnormal.
1818 */
1819 retval = 0;
1820#ifdef DO_THIS_LATER
1821 add_wait_queue(&info->open_wait, &wait);
1822#ifdef SERIAL_DEBUG_OPEN
1823 printk("block_til_ready before block: ttys%d, count = %d\n",
1824 state->line, state->count);
1825#endif
1826 local_irq_disable();
1827 if (!tty_hung_up_p(filp))
1828 state->count--;
1829 local_irq_enable();
1830 info->blocked_open++;
1831 while (1) {
1832 local_irq_disable();
1833 if (tty->termios->c_cflag & CBAUD)
1834 serial_out(info, UART_MCR,
1835 serial_inp(info, UART_MCR) |
1836 (UART_MCR_DTR | UART_MCR_RTS));
1837 local_irq_enable();
1838 set_current_state(TASK_INTERRUPTIBLE);
1839 if (tty_hung_up_p(filp) ||
1840 !(info->flags & ASYNC_INITIALIZED)) {
1841#ifdef SERIAL_DO_RESTART
1842 if (info->flags & ASYNC_HUP_NOTIFY)
1843 retval = -EAGAIN;
1844 else
1845 retval = -ERESTARTSYS;
1846#else
1847 retval = -EAGAIN;
1848#endif
1849 break;
1850 }
1851 if (!(info->flags & ASYNC_CLOSING) &&
1852 (do_clocal || (serial_in(info, UART_MSR) &
1853 UART_MSR_DCD)))
1854 break;
1855 if (signal_pending(current)) {
1856 retval = -ERESTARTSYS;
1857 break;
1858 }
1859#ifdef SERIAL_DEBUG_OPEN
1860 printk("block_til_ready blocking: ttys%d, count = %d\n",
1861 info->line, state->count);
1862#endif
1863 tty_unlock();
1864 schedule();
1865 tty_lock();
1866 }
1867 current->state = TASK_RUNNING;
1868 remove_wait_queue(&info->open_wait, &wait);
1869 if (!tty_hung_up_p(filp))
1870 state->count++;
1871 info->blocked_open--;
1872#ifdef SERIAL_DEBUG_OPEN
1873 printk("block_til_ready after blocking: ttys%d, count = %d\n",
1874 info->line, state->count);
1875#endif
1876#endif /* DO_THIS_LATER */
1877 if (retval)
1878 return retval;
1879 info->flags |= ASYNC_NORMAL_ACTIVE;
1880 return 0;
1881}
1882
1883static int get_async_struct(int line, ser_info_t **ret_info)
1884{
1885 struct serial_state *sstate;
1886
1887 sstate = rs_table + line;
1888 if (sstate->info) {
1889 sstate->count++;
1890 *ret_info = (ser_info_t *)sstate->info;
1891 return 0;
1892 }
1893 else {
1894 return -ENOMEM;
1895 }
1896}
1897
1898/*
1899 * This routine is called whenever a serial port is opened. It
1900 * enables interrupts for a serial port, linking in its async structure into
1901 * the IRQ chain. It also performs the serial-specific
1902 * initialization for the tty structure.
1903 */
1904static int rs_360_open(struct tty_struct *tty, struct file * filp)
1905{
1906 ser_info_t *info;
1907 int retval, line;
1908
1909 line = tty->index;
1910 if ((line < 0) || (line >= NR_PORTS))
1911 return -ENODEV;
1912 retval = get_async_struct(line, &info);
1913 if (retval)
1914 return retval;
1915 if (serial_paranoia_check(info, tty->name, "rs_open"))
1916 return -ENODEV;
1917
1918#ifdef SERIAL_DEBUG_OPEN
1919 printk("rs_open %s, count = %d\n", tty->name, info->state->count);
1920#endif
1921 tty->driver_data = info;
1922 info->port.tty = tty;
1923
1924 /*
1925 * Start up serial port
1926 */
1927 retval = startup(info);
1928 if (retval)
1929 return retval;
1930
1931 retval = block_til_ready(tty, filp, info);
1932 if (retval) {
1933#ifdef SERIAL_DEBUG_OPEN
1934 printk("rs_open returning after block_til_ready with %d\n",
1935 retval);
1936#endif
1937 return retval;
1938 }
1939
1940#ifdef SERIAL_DEBUG_OPEN
1941 printk("rs_open %s successful...", tty->name);
1942#endif
1943 return 0;
1944}
1945
1946/*
1947 * /proc fs routines....
1948 */
1949
1950static inline int line_info(char *buf, struct serial_state *state)
1951{
1952#ifdef notdef
1953 struct async_struct *info = state->info, scr_info;
1954 char stat_buf[30], control, status;
1955#endif
1956 int ret;
1957
1958 ret = sprintf(buf, "%d: uart:%s port:%X irq:%d",
1959 state->line,
1960 (state->smc_scc_num & NUM_IS_SCC) ? "SCC" : "SMC",
1961 (unsigned int)(state->port), state->irq);
1962
1963 if (!state->port || (state->type == PORT_UNKNOWN)) {
1964 ret += sprintf(buf+ret, "\n");
1965 return ret;
1966 }
1967
1968#ifdef notdef
1969 /*
1970 * Figure out the current RS-232 lines
1971 */
1972 if (!info) {
1973 info = &scr_info; /* This is just for serial_{in,out} */
1974
1975 info->magic = SERIAL_MAGIC;
1976 info->port = state->port;
1977 info->flags = state->flags;
1978 info->quot = 0;
1979 info->port.tty = NULL;
1980 }
1981 local_irq_disable();
1982 status = serial_in(info, UART_MSR);
1983 control = info ? info->MCR : serial_in(info, UART_MCR);
1984 local_irq_enable();
1985
1986 stat_buf[0] = 0;
1987 stat_buf[1] = 0;
1988 if (control & UART_MCR_RTS)
1989 strcat(stat_buf, "|RTS");
1990 if (status & UART_MSR_CTS)
1991 strcat(stat_buf, "|CTS");
1992 if (control & UART_MCR_DTR)
1993 strcat(stat_buf, "|DTR");
1994 if (status & UART_MSR_DSR)
1995 strcat(stat_buf, "|DSR");
1996 if (status & UART_MSR_DCD)
1997 strcat(stat_buf, "|CD");
1998 if (status & UART_MSR_RI)
1999 strcat(stat_buf, "|RI");
2000
2001 if (info->quot) {
2002 ret += sprintf(buf+ret, " baud:%d",
2003 state->baud_base / info->quot);
2004 }
2005
2006 ret += sprintf(buf+ret, " tx:%d rx:%d",
2007 state->icount.tx, state->icount.rx);
2008
2009 if (state->icount.frame)
2010 ret += sprintf(buf+ret, " fe:%d", state->icount.frame);
2011
2012 if (state->icount.parity)
2013 ret += sprintf(buf+ret, " pe:%d", state->icount.parity);
2014
2015 if (state->icount.brk)
2016 ret += sprintf(buf+ret, " brk:%d", state->icount.brk);
2017
2018 if (state->icount.overrun)
2019 ret += sprintf(buf+ret, " oe:%d", state->icount.overrun);
2020
2021 /*
2022 * Last thing is the RS-232 status lines
2023 */
2024 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
2025#endif
2026 return ret;
2027}
2028
2029int rs_360_read_proc(char *page, char **start, off_t off, int count,
2030 int *eof, void *data)
2031{
2032 int i, len = 0;
2033 off_t begin = 0;
2034
2035 len += sprintf(page, "serinfo:1.0 driver:%s\n", serial_version);
2036 for (i = 0; i < NR_PORTS && len < 4000; i++) {
2037 len += line_info(page + len, &rs_table[i]);
2038 if (len+begin > off+count)
2039 goto done;
2040 if (len+begin < off) {
2041 begin += len;
2042 len = 0;
2043 }
2044 }
2045 *eof = 1;
2046done:
2047 if (off >= len+begin)
2048 return 0;
2049 *start = page + (begin-off);
2050 return ((count < begin+len-off) ? count : begin+len-off);
2051}
2052
2053/*
2054 * ---------------------------------------------------------------------
2055 * rs_init() and friends
2056 *
2057 * rs_init() is called at boot-time to initialize the serial driver.
2058 * ---------------------------------------------------------------------
2059 */
2060
2061/*
2062 * This routine prints out the appropriate serial driver version
2063 * number, and identifies which options were configured into this
2064 * driver.
2065 */
2066static _INLINE_ void show_serial_version(void)
2067{
2068 printk(KERN_INFO "%s version %s\n", serial_name, serial_version);
2069}
2070
2071
2072/*
2073 * The serial console driver used during boot. Note that these names
2074 * clash with those found in "serial.c", so we currently can't support
2075 * the 16xxx uarts and these at the same time. I will fix this to become
2076 * an indirect function call from tty_io.c (or something).
2077 */
2078
2079#ifdef CONFIG_SERIAL_CONSOLE
2080
2081/*
2082 * Print a string to the serial port trying not to disturb any possible
2083 * real use of the port...
2084 */
2085static void my_console_write(int idx, const char *s,
2086 unsigned count)
2087{
2088 struct serial_state *ser;
2089 ser_info_t *info;
2090 unsigned i;
2091 QUICC_BD *bdp, *bdbase;
2092 volatile struct smc_uart_pram *up;
2093 volatile u_char *cp;
2094
2095 ser = rs_table + idx;
2096
2097
2098 /* If the port has been initialized for general use, we have
2099 * to use the buffer descriptors allocated there. Otherwise,
2100 * we simply use the single buffer allocated.
2101 */
2102 if ((info = (ser_info_t *)ser->info) != NULL) {
2103 bdp = info->tx_cur;
2104 bdbase = info->tx_bd_base;
2105 }
2106 else {
2107 /* Pointer to UART in parameter ram.
2108 */
2109 /* up = (smc_uart_t *)&cpmp->cp_dparam[ser->port]; */
2110 up = &pquicc->pram[ser->port].scc.pothers.idma_smc.psmc.u;
2111
2112 /* Get the address of the host memory buffer.
2113 */
2114 bdp = bdbase = (QUICC_BD *)((uint)pquicc + (uint)up->tbase);
2115 }
2116
2117 /*
2118 * We need to gracefully shut down the transmitter, disable
2119 * interrupts, then send our bytes out.
2120 */
2121
2122 /*
2123 * Now, do each character. This is not as bad as it looks
2124 * since this is a holding FIFO and not a transmitting FIFO.
2125 * We could add the complexity of filling the entire transmit
2126 * buffer, but we would just wait longer between accesses......
2127 */
2128 for (i = 0; i < count; i++, s++) {
2129 /* Wait for transmitter fifo to empty.
2130 * Ready indicates output is ready, and xmt is doing
2131 * that, not that it is ready for us to send.
2132 */
2133 while (bdp->status & BD_SC_READY);
2134
2135 /* Send the character out.
2136 */
2137 cp = bdp->buf;
2138 *cp = *s;
2139
2140 bdp->length = 1;
2141 bdp->status |= BD_SC_READY;
2142
2143 if (bdp->status & BD_SC_WRAP)
2144 bdp = bdbase;
2145 else
2146 bdp++;
2147
2148 /* if a LF, also do CR... */
2149 if (*s == 10) {
2150 while (bdp->status & BD_SC_READY);
2151 /* cp = __va(bdp->buf); */
2152 cp = bdp->buf;
2153 *cp = 13;
2154 bdp->length = 1;
2155 bdp->status |= BD_SC_READY;
2156
2157 if (bdp->status & BD_SC_WRAP) {
2158 bdp = bdbase;
2159 }
2160 else {
2161 bdp++;
2162 }
2163 }
2164 }
2165
2166 /*
2167 * Finally, Wait for transmitter & holding register to empty
2168 * and restore the IER
2169 */
2170 while (bdp->status & BD_SC_READY);
2171
2172 if (info)
2173 info->tx_cur = (QUICC_BD *)bdp;
2174}
2175
2176static void serial_console_write(struct console *c, const char *s,
2177 unsigned count)
2178{
2179#ifdef CONFIG_KGDB
2180 /* Try to let stub handle output. Returns true if it did. */
2181 if (kgdb_output_string(s, count))
2182 return;
2183#endif
2184 my_console_write(c->index, s, count);
2185}
2186
2187
2188
2189/*void console_print_68360(const char *p)
2190{
2191 const char *cp = p;
2192 int i;
2193
2194 for (i=0;cp[i]!=0;i++);
2195
2196 serial_console_write (p, i);
2197
2198 //Comment this if you want to have a strict interrupt-driven output
2199 //rs_fair_output();
2200
2201 return;
2202}*/
2203
2204
2205
2206
2207
2208
2209#ifdef CONFIG_XMON
2210int
2211xmon_360_write(const char *s, unsigned count)
2212{
2213 my_console_write(0, s, count);
2214 return(count);
2215}
2216#endif
2217
2218#ifdef CONFIG_KGDB
2219void
2220putDebugChar(char ch)
2221{
2222 my_console_write(0, &ch, 1);
2223}
2224#endif
2225
2226/*
2227 * Receive character from the serial port. This only works well
2228 * before the port is initialized for real use.
2229 */
2230static int my_console_wait_key(int idx, int xmon, char *obuf)
2231{
2232 struct serial_state *ser;
2233 u_char c, *cp;
2234 ser_info_t *info;
2235 QUICC_BD *bdp;
2236 volatile struct smc_uart_pram *up;
2237 int i;
2238
2239 ser = rs_table + idx;
2240
2241 /* Get the address of the host memory buffer.
2242 * If the port has been initialized for general use, we must
2243 * use information from the port structure.
2244 */
2245 if ((info = (ser_info_t *)ser->info))
2246 bdp = info->rx_cur;
2247 else
2248 /* bdp = (QUICC_BD *)&cpmp->cp_dpmem[up->smc_rbase]; */
2249 bdp = (QUICC_BD *)((uint)pquicc + (uint)up->tbase);
2250
2251 /* Pointer to UART in parameter ram.
2252 */
2253 /* up = (smc_uart_t *)&cpmp->cp_dparam[ser->port]; */
2254 up = &pquicc->pram[info->state->port].scc.pothers.idma_smc.psmc.u;
2255
2256 /*
2257 * We need to gracefully shut down the receiver, disable
2258 * interrupts, then read the input.
2259 * XMON just wants a poll. If no character, return -1, else
2260 * return the character.
2261 */
2262 if (!xmon) {
2263 while (bdp->status & BD_SC_EMPTY);
2264 }
2265 else {
2266 if (bdp->status & BD_SC_EMPTY)
2267 return -1;
2268 }
2269
2270 cp = (char *)bdp->buf;
2271
2272 if (obuf) {
2273 i = c = bdp->length;
2274 while (i-- > 0)
2275 *obuf++ = *cp++;
2276 }
2277 else {
2278 c = *cp;
2279 }
2280 bdp->status |= BD_SC_EMPTY;
2281
2282 if (info) {
2283 if (bdp->status & BD_SC_WRAP) {
2284 bdp = info->rx_bd_base;
2285 }
2286 else {
2287 bdp++;
2288 }
2289 info->rx_cur = (QUICC_BD *)bdp;
2290 }
2291
2292 return((int)c);
2293}
2294
2295static int serial_console_wait_key(struct console *co)
2296{
2297 return(my_console_wait_key(co->index, 0, NULL));
2298}
2299
2300#ifdef CONFIG_XMON
2301int
2302xmon_360_read_poll(void)
2303{
2304 return(my_console_wait_key(0, 1, NULL));
2305}
2306
2307int
2308xmon_360_read_char(void)
2309{
2310 return(my_console_wait_key(0, 0, NULL));
2311}
2312#endif
2313
2314#ifdef CONFIG_KGDB
2315static char kgdb_buf[RX_BUF_SIZE], *kgdp;
2316static int kgdb_chars;
2317
2318unsigned char
2319getDebugChar(void)
2320{
2321 if (kgdb_chars <= 0) {
2322 kgdb_chars = my_console_wait_key(0, 0, kgdb_buf);
2323 kgdp = kgdb_buf;
2324 }
2325 kgdb_chars--;
2326
2327 return(*kgdp++);
2328}
2329
2330void kgdb_interruptible(int state)
2331{
2332}
2333void kgdb_map_scc(void)
2334{
2335 struct serial_state *ser;
2336 uint mem_addr;
2337 volatile QUICC_BD *bdp;
2338 volatile smc_uart_t *up;
2339
2340 cpmp = (cpm360_t *)&(((immap_t *)IMAP_ADDR)->im_cpm);
2341
2342 /* To avoid data cache CPM DMA coherency problems, allocate a
2343 * buffer in the CPM DPRAM. This will work until the CPM and
2344 * serial ports are initialized. At that time a memory buffer
2345 * will be allocated.
2346 * The port is already initialized from the boot procedure, all
2347 * we do here is give it a different buffer and make it a FIFO.
2348 */
2349
2350 ser = rs_table;
2351
2352 /* Right now, assume we are using SMCs.
2353 */
2354 up = (smc_uart_t *)&cpmp->cp_dparam[ser->port];
2355
2356 /* Allocate space for an input FIFO, plus a few bytes for output.
2357 * Allocate bytes to maintain word alignment.
2358 */
2359 mem_addr = (uint)(&cpmp->cp_dpmem[0x1000]);
2360
2361 /* Set the physical address of the host memory buffers in
2362 * the buffer descriptors.
2363 */
2364 bdp = (QUICC_BD *)&cpmp->cp_dpmem[up->smc_rbase];
2365 bdp->buf = mem_addr;
2366
2367 bdp = (QUICC_BD *)&cpmp->cp_dpmem[up->smc_tbase];
2368 bdp->buf = mem_addr+RX_BUF_SIZE;
2369
2370 up->smc_mrblr = RX_BUF_SIZE; /* receive buffer length */
2371 up->smc_maxidl = RX_BUF_SIZE;
2372}
2373#endif
2374
2375static struct tty_struct *serial_console_device(struct console *c, int *index)
2376{
2377 *index = c->index;
2378 return serial_driver;
2379}
2380
2381
2382struct console sercons = {
2383 .name = "ttyS",
2384 .write = serial_console_write,
2385 .device = serial_console_device,
2386 .wait_key = serial_console_wait_key,
2387 .setup = serial_console_setup,
2388 .flags = CON_PRINTBUFFER,
2389 .index = CONFIG_SERIAL_CONSOLE_PORT,
2390};
2391
2392
2393
2394/*
2395 * Register console.
2396 */
2397long console_360_init(long kmem_start, long kmem_end)
2398{
2399 register_console(&sercons);
2400 /*register_console (console_print_68360); - 2.0.38 only required a write
2401 function pointer. */
2402 return kmem_start;
2403}
2404
2405#endif
2406
2407/* Index in baud rate table of the default console baud rate.
2408*/
2409static int baud_idx;
2410
2411static const struct tty_operations rs_360_ops = {
2412 .owner = THIS_MODULE,
2413 .open = rs_360_open,
2414 .close = rs_360_close,
2415 .write = rs_360_write,
2416 .put_char = rs_360_put_char,
2417 .write_room = rs_360_write_room,
2418 .chars_in_buffer = rs_360_chars_in_buffer,
2419 .flush_buffer = rs_360_flush_buffer,
2420 .ioctl = rs_360_ioctl,
2421 .throttle = rs_360_throttle,
2422 .unthrottle = rs_360_unthrottle,
2423 /* .send_xchar = rs_360_send_xchar, */
2424 .set_termios = rs_360_set_termios,
2425 .stop = rs_360_stop,
2426 .start = rs_360_start,
2427 .hangup = rs_360_hangup,
2428 /* .wait_until_sent = rs_360_wait_until_sent, */
2429 /* .read_proc = rs_360_read_proc, */
2430 .tiocmget = rs_360_tiocmget,
2431 .tiocmset = rs_360_tiocmset,
2432};
2433
2434static int __init rs_360_init(void)
2435{
2436 struct serial_state * state;
2437 ser_info_t *info;
2438 void *mem_addr;
2439 uint dp_addr, iobits;
2440 int i, j, idx;
2441 ushort chan;
2442 QUICC_BD *bdp;
2443 volatile QUICC *cp;
2444 volatile struct smc_regs *sp;
2445 volatile struct smc_uart_pram *up;
2446 volatile struct scc_regs *scp;
2447 volatile struct uart_pram *sup;
2448 /* volatile immap_t *immap; */
2449
2450 serial_driver = alloc_tty_driver(NR_PORTS);
2451 if (!serial_driver)
2452 return -1;
2453
2454 show_serial_version();
2455
2456 serial_driver->name = "ttyS";
2457 serial_driver->major = TTY_MAJOR;
2458 serial_driver->minor_start = 64;
2459 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
2460 serial_driver->subtype = SERIAL_TYPE_NORMAL;
2461 serial_driver->init_termios = tty_std_termios;
2462 serial_driver->init_termios.c_cflag =
2463 baud_idx | CS8 | CREAD | HUPCL | CLOCAL;
2464 serial_driver->flags = TTY_DRIVER_REAL_RAW;
2465 tty_set_operations(serial_driver, &rs_360_ops);
2466
2467 if (tty_register_driver(serial_driver))
2468 panic("Couldn't register serial driver\n");
2469
2470 cp = pquicc; /* Get pointer to Communication Processor */
2471 /* immap = (immap_t *)IMAP_ADDR; */ /* and to internal registers */
2472
2473
2474 /* Configure SCC2, SCC3, and SCC4 instead of port A parallel I/O.
2475 */
2476 /* The "standard" configuration through the 860.
2477 */
2478/* immap->im_ioport.iop_papar |= 0x00fc; */
2479/* immap->im_ioport.iop_padir &= ~0x00fc; */
2480/* immap->im_ioport.iop_paodr &= ~0x00fc; */
2481 cp->pio_papar |= 0x00fc;
2482 cp->pio_padir &= ~0x00fc;
2483 /* cp->pio_paodr &= ~0x00fc; */
2484
2485
2486 /* Since we don't yet do modem control, connect the port C pins
2487 * as general purpose I/O. This will assert CTS and CD for the
2488 * SCC ports.
2489 */
2490 /* FIXME: see 360um p.7-365 and 860um p.34-12
2491 * I can't make sense of these bits - mleslie*/
2492/* immap->im_ioport.iop_pcdir |= 0x03c6; */
2493/* immap->im_ioport.iop_pcpar &= ~0x03c6; */
2494
2495/* cp->pio_pcdir |= 0x03c6; */
2496/* cp->pio_pcpar &= ~0x03c6; */
2497
2498
2499
2500 /* Connect SCC2 and SCC3 to NMSI. Connect BRG3 to SCC2 and
2501 * BRG4 to SCC3.
2502 */
2503 cp->si_sicr &= ~0x00ffff00;
2504 cp->si_sicr |= 0x001b1200;
2505
2506#ifdef CONFIG_PP04
2507 /* Frequentis PP04 forced to RS-232 until we know better.
2508 * Port C 12 and 13 low enables RS-232 on SCC3 and SCC4.
2509 */
2510 immap->im_ioport.iop_pcdir |= 0x000c;
2511 immap->im_ioport.iop_pcpar &= ~0x000c;
2512 immap->im_ioport.iop_pcdat &= ~0x000c;
2513
2514 /* This enables the TX driver.
2515 */
2516 cp->cp_pbpar &= ~0x6000;
2517 cp->cp_pbdat &= ~0x6000;
2518#endif
2519
2520 for (i = 0, state = rs_table; i < NR_PORTS; i++,state++) {
2521 state->magic = SSTATE_MAGIC;
2522 state->line = i;
2523 state->type = PORT_UNKNOWN;
2524 state->custom_divisor = 0;
2525 state->close_delay = 5*HZ/10;
2526 state->closing_wait = 30*HZ;
2527 state->icount.cts = state->icount.dsr =
2528 state->icount.rng = state->icount.dcd = 0;
2529 state->icount.rx = state->icount.tx = 0;
2530 state->icount.frame = state->icount.parity = 0;
2531 state->icount.overrun = state->icount.brk = 0;
2532 printk(KERN_INFO "ttyS%d at irq 0x%02x is an %s\n",
2533 i, (unsigned int)(state->irq),
2534 (state->smc_scc_num & NUM_IS_SCC) ? "SCC" : "SMC");
2535
2536#ifdef CONFIG_SERIAL_CONSOLE
2537 /* If we just printed the message on the console port, and
2538 * we are about to initialize it for general use, we have
2539 * to wait a couple of character times for the CR/NL to
2540 * make it out of the transmit buffer.
2541 */
2542 if (i == CONFIG_SERIAL_CONSOLE_PORT)
2543 mdelay(8);
2544
2545
2546/* idx = PORT_NUM(info->state->smc_scc_num); */
2547/* if (info->state->smc_scc_num & NUM_IS_SCC) */
2548/* chan = scc_chan_map[idx]; */
2549/* else */
2550/* chan = smc_chan_map[idx]; */
2551
2552/* cp->cp_cr = mk_cr_cmd(chan, CPM_CR_STOP_TX) | CPM_CR_FLG; */
2553/* while (cp->cp_cr & CPM_CR_FLG); */
2554
2555#endif
2556 /* info = kmalloc(sizeof(ser_info_t), GFP_KERNEL); */
2557 info = &quicc_ser_info[i];
2558 if (info) {
2559 memset (info, 0, sizeof(ser_info_t));
2560 info->magic = SERIAL_MAGIC;
2561 info->line = i;
2562 info->flags = state->flags;
2563 INIT_WORK(&info->tqueue, do_softint, info);
2564 INIT_WORK(&info->tqueue_hangup, do_serial_hangup, info);
2565 init_waitqueue_head(&info->open_wait);
2566 init_waitqueue_head(&info->close_wait);
2567 info->state = state;
2568 state->info = (struct async_struct *)info;
2569
2570 /* We need to allocate a transmit and receive buffer
2571 * descriptors from dual port ram, and a character
2572 * buffer area from host mem.
2573 */
2574 dp_addr = m360_cpm_dpalloc(sizeof(QUICC_BD) * RX_NUM_FIFO);
2575
2576 /* Allocate space for FIFOs in the host memory.
2577 * (for now this is from a static array of buffers :(
2578 */
2579 /* mem_addr = m360_cpm_hostalloc(RX_NUM_FIFO * RX_BUF_SIZE); */
2580 /* mem_addr = kmalloc (RX_NUM_FIFO * RX_BUF_SIZE, GFP_BUFFER); */
2581 mem_addr = &rx_buf_pool[i * RX_NUM_FIFO * RX_BUF_SIZE];
2582
2583 /* Set the physical address of the host memory
2584 * buffers in the buffer descriptors, and the
2585 * virtual address for us to work with.
2586 */
2587 bdp = (QUICC_BD *)((uint)pquicc + dp_addr);
2588 info->rx_cur = info->rx_bd_base = bdp;
2589
2590 /* initialize rx buffer descriptors */
2591 for (j=0; j<(RX_NUM_FIFO-1); j++) {
2592 bdp->buf = &rx_buf_pool[(i * RX_NUM_FIFO + j ) * RX_BUF_SIZE];
2593 bdp->status = BD_SC_EMPTY | BD_SC_INTRPT;
2594 mem_addr += RX_BUF_SIZE;
2595 bdp++;
2596 }
2597 bdp->buf = &rx_buf_pool[(i * RX_NUM_FIFO + j ) * RX_BUF_SIZE];
2598 bdp->status = BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT;
2599
2600
2601 idx = PORT_NUM(info->state->smc_scc_num);
2602 if (info->state->smc_scc_num & NUM_IS_SCC) {
2603
2604#if defined (CONFIG_UCQUICC) && 1
2605 /* set the transceiver mode to RS232 */
2606 sipex_mode_bits &= ~(uint)SIPEX_MODE(idx,0x0f); /* clear current mode */
2607 sipex_mode_bits |= (uint)SIPEX_MODE(idx,0x02);
2608 *(uint *)_periph_base = sipex_mode_bits;
2609 /* printk ("sipex bits = 0x%08x\n", sipex_mode_bits); */
2610#endif
2611 }
2612
2613 dp_addr = m360_cpm_dpalloc(sizeof(QUICC_BD) * TX_NUM_FIFO);
2614
2615 /* Allocate space for FIFOs in the host memory.
2616 */
2617 /* mem_addr = m360_cpm_hostalloc(TX_NUM_FIFO * TX_BUF_SIZE); */
2618 /* mem_addr = kmalloc (TX_NUM_FIFO * TX_BUF_SIZE, GFP_BUFFER); */
2619 mem_addr = &tx_buf_pool[i * TX_NUM_FIFO * TX_BUF_SIZE];
2620
2621 /* Set the physical address of the host memory
2622 * buffers in the buffer descriptors, and the
2623 * virtual address for us to work with.
2624 */
2625 /* bdp = (QUICC_BD *)&cp->cp_dpmem[dp_addr]; */
2626 bdp = (QUICC_BD *)((uint)pquicc + dp_addr);
2627 info->tx_cur = info->tx_bd_base = (QUICC_BD *)bdp;
2628
2629 /* initialize tx buffer descriptors */
2630 for (j=0; j<(TX_NUM_FIFO-1); j++) {
2631 bdp->buf = &tx_buf_pool[(i * TX_NUM_FIFO + j ) * TX_BUF_SIZE];
2632 bdp->status = BD_SC_INTRPT;
2633 mem_addr += TX_BUF_SIZE;
2634 bdp++;
2635 }
2636 bdp->buf = &tx_buf_pool[(i * TX_NUM_FIFO + j ) * TX_BUF_SIZE];
2637 bdp->status = (BD_SC_WRAP | BD_SC_INTRPT);
2638
2639 if (info->state->smc_scc_num & NUM_IS_SCC) {
2640 scp = &pquicc->scc_regs[idx];
2641 sup = &pquicc->pram[info->state->port].scc.pscc.u;
2642 sup->rbase = dp_addr;
2643 sup->tbase = dp_addr;
2644
2645 /* Set up the uart parameters in the
2646 * parameter ram.
2647 */
2648 sup->rfcr = SMC_EB;
2649 sup->tfcr = SMC_EB;
2650
2651 /* Set this to 1 for now, so we get single
2652 * character interrupts. Using idle character
2653 * time requires some additional tuning.
2654 */
2655 sup->mrblr = 1;
2656 sup->max_idl = 0;
2657 sup->brkcr = 1;
2658 sup->parec = 0;
2659 sup->frmer = 0;
2660 sup->nosec = 0;
2661 sup->brkec = 0;
2662 sup->uaddr1 = 0;
2663 sup->uaddr2 = 0;
2664 sup->toseq = 0;
2665 {
2666 int i;
2667 for (i=0;i<8;i++)
2668 sup->cc[i] = 0x8000;
2669 }
2670 sup->rccm = 0xc0ff;
2671
2672 /* Send the CPM an initialize command.
2673 */
2674 chan = scc_chan_map[idx];
2675
2676 /* execute the INIT RX & TX PARAMS command for this channel. */
2677 cp->cp_cr = mk_cr_cmd(chan, CPM_CR_INIT_TRX) | CPM_CR_FLG;
2678 while (cp->cp_cr & CPM_CR_FLG);
2679
2680 /* Set UART mode, 8 bit, no parity, one stop.
2681 * Enable receive and transmit.
2682 */
2683 scp->scc_gsmr.w.high = 0;
2684 scp->scc_gsmr.w.low =
2685 (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
2686
2687 /* Disable all interrupts and clear all pending
2688 * events.
2689 */
2690 scp->scc_sccm = 0;
2691 scp->scc_scce = 0xffff;
2692 scp->scc_dsr = 0x7e7e;
2693 scp->scc_psmr = 0x3000;
2694
2695 /* If the port is the console, enable Rx and Tx.
2696 */
2697#ifdef CONFIG_SERIAL_CONSOLE
2698 if (i == CONFIG_SERIAL_CONSOLE_PORT)
2699 scp->scc_gsmr.w.low |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
2700#endif
2701 }
2702 else {
2703 /* Configure SMCs Tx/Rx instead of port B
2704 * parallel I/O.
2705 */
2706 up = &pquicc->pram[info->state->port].scc.pothers.idma_smc.psmc.u;
2707 up->rbase = dp_addr;
2708
2709 iobits = 0xc0 << (idx * 4);
2710 cp->pip_pbpar |= iobits;
2711 cp->pip_pbdir &= ~iobits;
2712 cp->pip_pbodr &= ~iobits;
2713
2714
2715 /* Connect the baud rate generator to the
2716 * SMC based upon index in rs_table. Also
2717 * make sure it is connected to NMSI.
2718 */
2719 cp->si_simode &= ~(0xffff << (idx * 16));
2720 cp->si_simode |= (i << ((idx * 16) + 12));
2721
2722 up->tbase = dp_addr;
2723
2724 /* Set up the uart parameters in the
2725 * parameter ram.
2726 */
2727 up->rfcr = SMC_EB;
2728 up->tfcr = SMC_EB;
2729
2730 /* Set this to 1 for now, so we get single
2731 * character interrupts. Using idle character
2732 * time requires some additional tuning.
2733 */
2734 up->mrblr = 1;
2735 up->max_idl = 0;
2736 up->brkcr = 1;
2737
2738 /* Send the CPM an initialize command.
2739 */
2740 chan = smc_chan_map[idx];
2741
2742 cp->cp_cr = mk_cr_cmd(chan,
2743 CPM_CR_INIT_TRX) | CPM_CR_FLG;
2744#ifdef CONFIG_SERIAL_CONSOLE
2745 if (i == CONFIG_SERIAL_CONSOLE_PORT)
2746 printk("");
2747#endif
2748 while (cp->cp_cr & CPM_CR_FLG);
2749
2750 /* Set UART mode, 8 bit, no parity, one stop.
2751 * Enable receive and transmit.
2752 */
2753 sp = &cp->smc_regs[idx];
2754 sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
2755
2756 /* Disable all interrupts and clear all pending
2757 * events.
2758 */
2759 sp->smc_smcm = 0;
2760 sp->smc_smce = 0xff;
2761
2762 /* If the port is the console, enable Rx and Tx.
2763 */
2764#ifdef CONFIG_SERIAL_CONSOLE
2765 if (i == CONFIG_SERIAL_CONSOLE_PORT)
2766 sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
2767#endif
2768 }
2769
2770 /* Install interrupt handler.
2771 */
2772 /* cpm_install_handler(IRQ_MACHSPEC | state->irq, rs_360_interrupt, info); */
2773 /*request_irq(IRQ_MACHSPEC | state->irq, rs_360_interrupt, */
2774 request_irq(state->irq, rs_360_interrupt,
2775 IRQ_FLG_LOCK, "ttyS", (void *)info);
2776
2777 /* Set up the baud rate generator.
2778 */
2779 m360_cpm_setbrg(i, baud_table[baud_idx]);
2780
2781 }
2782 }
2783
2784 return 0;
2785}
2786module_init(rs_360_init);
2787
2788/* This must always be called before the rs_360_init() function, otherwise
2789 * it blows away the port control information.
2790 */
2791//static int __init serial_console_setup( struct console *co, char *options)
2792int serial_console_setup( struct console *co, char *options)
2793{
2794 struct serial_state *ser;
2795 uint mem_addr, dp_addr, bidx, idx, iobits;
2796 ushort chan;
2797 QUICC_BD *bdp;
2798 volatile QUICC *cp;
2799 volatile struct smc_regs *sp;
2800 volatile struct scc_regs *scp;
2801 volatile struct smc_uart_pram *up;
2802 volatile struct uart_pram *sup;
2803
2804/* mleslie TODO:
2805 * add something to the 68k bootloader to store a desired initial console baud rate */
2806
2807/* bd_t *bd; */ /* a board info struct used by EPPC-bug */
2808/* bd = (bd_t *)__res; */
2809
2810 for (bidx = 0; bidx < (sizeof(baud_table) / sizeof(int)); bidx++)
2811 /* if (bd->bi_baudrate == baud_table[bidx]) */
2812 if (CONSOLE_BAUDRATE == baud_table[bidx])
2813 break;
2814
2815 /* co->cflag = CREAD|CLOCAL|bidx|CS8; */
2816 baud_idx = bidx;
2817
2818 ser = rs_table + CONFIG_SERIAL_CONSOLE_PORT;
2819
2820 cp = pquicc; /* Get pointer to Communication Processor */
2821
2822 idx = PORT_NUM(ser->smc_scc_num);
2823 if (ser->smc_scc_num & NUM_IS_SCC) {
2824
2825 /* TODO: need to set up SCC pin assignment etc. here */
2826
2827 }
2828 else {
2829 iobits = 0xc0 << (idx * 4);
2830 cp->pip_pbpar |= iobits;
2831 cp->pip_pbdir &= ~iobits;
2832 cp->pip_pbodr &= ~iobits;
2833
2834 /* Connect the baud rate generator to the
2835 * SMC based upon index in rs_table. Also
2836 * make sure it is connected to NMSI.
2837 */
2838 cp->si_simode &= ~(0xffff << (idx * 16));
2839 cp->si_simode |= (idx << ((idx * 16) + 12));
2840 }
2841
2842 /* When we get here, the CPM has been reset, so we need
2843 * to configure the port.
2844 * We need to allocate a transmit and receive buffer descriptor
2845 * from dual port ram, and a character buffer area from host mem.
2846 */
2847
2848 /* Allocate space for two buffer descriptors in the DP ram.
2849 */
2850 dp_addr = m360_cpm_dpalloc(sizeof(QUICC_BD) * CONSOLE_NUM_FIFO);
2851
2852 /* Allocate space for two 2 byte FIFOs in the host memory.
2853 */
2854 /* mem_addr = m360_cpm_hostalloc(8); */
2855 mem_addr = (uint)console_fifos;
2856
2857
2858 /* Set the physical address of the host memory buffers in
2859 * the buffer descriptors.
2860 */
2861 /* bdp = (QUICC_BD *)&cp->cp_dpmem[dp_addr]; */
2862 bdp = (QUICC_BD *)((uint)pquicc + dp_addr);
2863 bdp->buf = (char *)mem_addr;
2864 (bdp+1)->buf = (char *)(mem_addr+4);
2865
2866 /* For the receive, set empty and wrap.
2867 * For transmit, set wrap.
2868 */
2869 bdp->status = BD_SC_EMPTY | BD_SC_WRAP;
2870 (bdp+1)->status = BD_SC_WRAP;
2871
2872 /* Set up the uart parameters in the parameter ram.
2873 */
2874 if (ser->smc_scc_num & NUM_IS_SCC) {
2875 scp = &cp->scc_regs[idx];
2876 /* sup = (scc_uart_t *)&cp->cp_dparam[ser->port]; */
2877 sup = &pquicc->pram[ser->port].scc.pscc.u;
2878
2879 sup->rbase = dp_addr;
2880 sup->tbase = dp_addr + sizeof(QUICC_BD);
2881
2882 /* Set up the uart parameters in the
2883 * parameter ram.
2884 */
2885 sup->rfcr = SMC_EB;
2886 sup->tfcr = SMC_EB;
2887
2888 /* Set this to 1 for now, so we get single
2889 * character interrupts. Using idle character
2890 * time requires some additional tuning.
2891 */
2892 sup->mrblr = 1;
2893 sup->max_idl = 0;
2894 sup->brkcr = 1;
2895 sup->parec = 0;
2896 sup->frmer = 0;
2897 sup->nosec = 0;
2898 sup->brkec = 0;
2899 sup->uaddr1 = 0;
2900 sup->uaddr2 = 0;
2901 sup->toseq = 0;
2902 {
2903 int i;
2904 for (i=0;i<8;i++)
2905 sup->cc[i] = 0x8000;
2906 }
2907 sup->rccm = 0xc0ff;
2908
2909 /* Send the CPM an initialize command.
2910 */
2911 chan = scc_chan_map[idx];
2912
2913 cp->cp_cr = mk_cr_cmd(chan, CPM_CR_INIT_TRX) | CPM_CR_FLG;
2914 while (cp->cp_cr & CPM_CR_FLG);
2915
2916 /* Set UART mode, 8 bit, no parity, one stop.
2917 * Enable receive and transmit.
2918 */
2919 scp->scc_gsmr.w.high = 0;
2920 scp->scc_gsmr.w.low =
2921 (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
2922
2923 /* Disable all interrupts and clear all pending
2924 * events.
2925 */
2926 scp->scc_sccm = 0;
2927 scp->scc_scce = 0xffff;
2928 scp->scc_dsr = 0x7e7e;
2929 scp->scc_psmr = 0x3000;
2930
2931 scp->scc_gsmr.w.low |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
2932
2933 }
2934 else {
2935 /* up = (smc_uart_t *)&cp->cp_dparam[ser->port]; */
2936 up = &pquicc->pram[ser->port].scc.pothers.idma_smc.psmc.u;
2937
2938 up->rbase = dp_addr; /* Base of receive buffer desc. */
2939 up->tbase = dp_addr+sizeof(QUICC_BD); /* Base of xmt buffer desc. */
2940 up->rfcr = SMC_EB;
2941 up->tfcr = SMC_EB;
2942
2943 /* Set this to 1 for now, so we get single character interrupts.
2944 */
2945 up->mrblr = 1; /* receive buffer length */
2946 up->max_idl = 0; /* wait forever for next char */
2947
2948 /* Send the CPM an initialize command.
2949 */
2950 chan = smc_chan_map[idx];
2951 cp->cp_cr = mk_cr_cmd(chan, CPM_CR_INIT_TRX) | CPM_CR_FLG;
2952 while (cp->cp_cr & CPM_CR_FLG);
2953
2954 /* Set UART mode, 8 bit, no parity, one stop.
2955 * Enable receive and transmit.
2956 */
2957 sp = &cp->smc_regs[idx];
2958 sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
2959
2960 /* And finally, enable Rx and Tx.
2961 */
2962 sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
2963 }
2964
2965 /* Set up the baud rate generator.
2966 */
2967 /* m360_cpm_setbrg((ser - rs_table), bd->bi_baudrate); */
2968 m360_cpm_setbrg((ser - rs_table), CONSOLE_BAUDRATE);
2969
2970 return 0;
2971}
2972
2973/*
2974 * Local variables:
2975 * c-indent-level: 4
2976 * c-basic-offset: 4
2977 * tab-width: 4
2978 * End:
2979 */
diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c
deleted file mode 100644
index 24110f6f61e0..000000000000
--- a/drivers/serial/8250.c
+++ /dev/null
@@ -1,3309 +0,0 @@
1/*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * A note about mapbase / membase
16 *
17 * mapbase is the physical address of the IO port.
18 * membase is an 'ioremapped' cookie.
19 */
20
21#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22#define SUPPORT_SYSRQ
23#endif
24
25#include <linux/module.h>
26#include <linux/moduleparam.h>
27#include <linux/ioport.h>
28#include <linux/init.h>
29#include <linux/console.h>
30#include <linux/sysrq.h>
31#include <linux/delay.h>
32#include <linux/platform_device.h>
33#include <linux/tty.h>
34#include <linux/tty_flip.h>
35#include <linux/serial_reg.h>
36#include <linux/serial_core.h>
37#include <linux/serial.h>
38#include <linux/serial_8250.h>
39#include <linux/nmi.h>
40#include <linux/mutex.h>
41#include <linux/slab.h>
42
43#include <asm/io.h>
44#include <asm/irq.h>
45
46#include "8250.h"
47
48#ifdef CONFIG_SPARC
49#include "suncore.h"
50#endif
51
52/*
53 * Configuration:
54 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
55 * is unsafe when used on edge-triggered interrupts.
56 */
57static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
58
59static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
60
61static struct uart_driver serial8250_reg;
62
63static int serial_index(struct uart_port *port)
64{
65 return (serial8250_reg.minor - 64) + port->line;
66}
67
68static unsigned int skip_txen_test; /* force skip of txen test at init time */
69
70/*
71 * Debugging.
72 */
73#if 0
74#define DEBUG_AUTOCONF(fmt...) printk(fmt)
75#else
76#define DEBUG_AUTOCONF(fmt...) do { } while (0)
77#endif
78
79#if 0
80#define DEBUG_INTR(fmt...) printk(fmt)
81#else
82#define DEBUG_INTR(fmt...) do { } while (0)
83#endif
84
85#define PASS_LIMIT 256
86
87#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
88
89
90/*
91 * We default to IRQ0 for the "no irq" hack. Some
92 * machine types want others as well - they're free
93 * to redefine this in their header file.
94 */
95#define is_real_interrupt(irq) ((irq) != 0)
96
97#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
98#define CONFIG_SERIAL_DETECT_IRQ 1
99#endif
100#ifdef CONFIG_SERIAL_8250_MANY_PORTS
101#define CONFIG_SERIAL_MANY_PORTS 1
102#endif
103
104/*
105 * HUB6 is always on. This will be removed once the header
106 * files have been cleaned.
107 */
108#define CONFIG_HUB6 1
109
110#include <asm/serial.h>
111/*
112 * SERIAL_PORT_DFNS tells us about built-in ports that have no
113 * standard enumeration mechanism. Platforms that can find all
114 * serial ports via mechanisms like ACPI or PCI need not supply it.
115 */
116#ifndef SERIAL_PORT_DFNS
117#define SERIAL_PORT_DFNS
118#endif
119
120static const struct old_serial_port old_serial_port[] = {
121 SERIAL_PORT_DFNS /* defined in asm/serial.h */
122};
123
124#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
125
126#ifdef CONFIG_SERIAL_8250_RSA
127
128#define PORT_RSA_MAX 4
129static unsigned long probe_rsa[PORT_RSA_MAX];
130static unsigned int probe_rsa_count;
131#endif /* CONFIG_SERIAL_8250_RSA */
132
133struct uart_8250_port {
134 struct uart_port port;
135 struct timer_list timer; /* "no irq" timer */
136 struct list_head list; /* ports on this IRQ */
137 unsigned short capabilities; /* port capabilities */
138 unsigned short bugs; /* port bugs */
139 unsigned int tx_loadsz; /* transmit fifo load size */
140 unsigned char acr;
141 unsigned char ier;
142 unsigned char lcr;
143 unsigned char mcr;
144 unsigned char mcr_mask; /* mask of user bits */
145 unsigned char mcr_force; /* mask of forced bits */
146 unsigned char cur_iotype; /* Running I/O type */
147
148 /*
149 * Some bits in registers are cleared on a read, so they must
150 * be saved whenever the register is read but the bits will not
151 * be immediately processed.
152 */
153#define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
154 unsigned char lsr_saved_flags;
155#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
156 unsigned char msr_saved_flags;
157
158 /*
159 * We provide a per-port pm hook.
160 */
161 void (*pm)(struct uart_port *port,
162 unsigned int state, unsigned int old);
163};
164
165struct irq_info {
166 struct hlist_node node;
167 int irq;
168 spinlock_t lock; /* Protects list not the hash */
169 struct list_head *head;
170};
171
172#define NR_IRQ_HASH 32 /* Can be adjusted later */
173static struct hlist_head irq_lists[NR_IRQ_HASH];
174static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
175
176/*
177 * Here we define the default xmit fifo size used for each type of UART.
178 */
179static const struct serial8250_config uart_config[] = {
180 [PORT_UNKNOWN] = {
181 .name = "unknown",
182 .fifo_size = 1,
183 .tx_loadsz = 1,
184 },
185 [PORT_8250] = {
186 .name = "8250",
187 .fifo_size = 1,
188 .tx_loadsz = 1,
189 },
190 [PORT_16450] = {
191 .name = "16450",
192 .fifo_size = 1,
193 .tx_loadsz = 1,
194 },
195 [PORT_16550] = {
196 .name = "16550",
197 .fifo_size = 1,
198 .tx_loadsz = 1,
199 },
200 [PORT_16550A] = {
201 .name = "16550A",
202 .fifo_size = 16,
203 .tx_loadsz = 16,
204 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
205 .flags = UART_CAP_FIFO,
206 },
207 [PORT_CIRRUS] = {
208 .name = "Cirrus",
209 .fifo_size = 1,
210 .tx_loadsz = 1,
211 },
212 [PORT_16650] = {
213 .name = "ST16650",
214 .fifo_size = 1,
215 .tx_loadsz = 1,
216 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
217 },
218 [PORT_16650V2] = {
219 .name = "ST16650V2",
220 .fifo_size = 32,
221 .tx_loadsz = 16,
222 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
223 UART_FCR_T_TRIG_00,
224 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
225 },
226 [PORT_16750] = {
227 .name = "TI16750",
228 .fifo_size = 64,
229 .tx_loadsz = 64,
230 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
231 UART_FCR7_64BYTE,
232 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
233 },
234 [PORT_STARTECH] = {
235 .name = "Startech",
236 .fifo_size = 1,
237 .tx_loadsz = 1,
238 },
239 [PORT_16C950] = {
240 .name = "16C950/954",
241 .fifo_size = 128,
242 .tx_loadsz = 128,
243 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
244 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
245 },
246 [PORT_16654] = {
247 .name = "ST16654",
248 .fifo_size = 64,
249 .tx_loadsz = 32,
250 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
251 UART_FCR_T_TRIG_10,
252 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
253 },
254 [PORT_16850] = {
255 .name = "XR16850",
256 .fifo_size = 128,
257 .tx_loadsz = 128,
258 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
259 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
260 },
261 [PORT_RSA] = {
262 .name = "RSA",
263 .fifo_size = 2048,
264 .tx_loadsz = 2048,
265 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
266 .flags = UART_CAP_FIFO,
267 },
268 [PORT_NS16550A] = {
269 .name = "NS16550A",
270 .fifo_size = 16,
271 .tx_loadsz = 16,
272 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
273 .flags = UART_CAP_FIFO | UART_NATSEMI,
274 },
275 [PORT_XSCALE] = {
276 .name = "XScale",
277 .fifo_size = 32,
278 .tx_loadsz = 32,
279 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
280 .flags = UART_CAP_FIFO | UART_CAP_UUE,
281 },
282 [PORT_RM9000] = {
283 .name = "RM9000",
284 .fifo_size = 16,
285 .tx_loadsz = 16,
286 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
287 .flags = UART_CAP_FIFO,
288 },
289 [PORT_OCTEON] = {
290 .name = "OCTEON",
291 .fifo_size = 64,
292 .tx_loadsz = 64,
293 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
294 .flags = UART_CAP_FIFO,
295 },
296 [PORT_AR7] = {
297 .name = "AR7",
298 .fifo_size = 16,
299 .tx_loadsz = 16,
300 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
301 .flags = UART_CAP_FIFO | UART_CAP_AFE,
302 },
303 [PORT_U6_16550A] = {
304 .name = "U6_16550A",
305 .fifo_size = 64,
306 .tx_loadsz = 64,
307 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
308 .flags = UART_CAP_FIFO | UART_CAP_AFE,
309 },
310};
311
312#if defined(CONFIG_MIPS_ALCHEMY)
313
314/* Au1x00 UART hardware has a weird register layout */
315static const u8 au_io_in_map[] = {
316 [UART_RX] = 0,
317 [UART_IER] = 2,
318 [UART_IIR] = 3,
319 [UART_LCR] = 5,
320 [UART_MCR] = 6,
321 [UART_LSR] = 7,
322 [UART_MSR] = 8,
323};
324
325static const u8 au_io_out_map[] = {
326 [UART_TX] = 1,
327 [UART_IER] = 2,
328 [UART_FCR] = 4,
329 [UART_LCR] = 5,
330 [UART_MCR] = 6,
331};
332
333/* sane hardware needs no mapping */
334static inline int map_8250_in_reg(struct uart_port *p, int offset)
335{
336 if (p->iotype != UPIO_AU)
337 return offset;
338 return au_io_in_map[offset];
339}
340
341static inline int map_8250_out_reg(struct uart_port *p, int offset)
342{
343 if (p->iotype != UPIO_AU)
344 return offset;
345 return au_io_out_map[offset];
346}
347
348#elif defined(CONFIG_SERIAL_8250_RM9K)
349
350static const u8
351 regmap_in[8] = {
352 [UART_RX] = 0x00,
353 [UART_IER] = 0x0c,
354 [UART_IIR] = 0x14,
355 [UART_LCR] = 0x1c,
356 [UART_MCR] = 0x20,
357 [UART_LSR] = 0x24,
358 [UART_MSR] = 0x28,
359 [UART_SCR] = 0x2c
360 },
361 regmap_out[8] = {
362 [UART_TX] = 0x04,
363 [UART_IER] = 0x0c,
364 [UART_FCR] = 0x18,
365 [UART_LCR] = 0x1c,
366 [UART_MCR] = 0x20,
367 [UART_LSR] = 0x24,
368 [UART_MSR] = 0x28,
369 [UART_SCR] = 0x2c
370 };
371
372static inline int map_8250_in_reg(struct uart_port *p, int offset)
373{
374 if (p->iotype != UPIO_RM9000)
375 return offset;
376 return regmap_in[offset];
377}
378
379static inline int map_8250_out_reg(struct uart_port *p, int offset)
380{
381 if (p->iotype != UPIO_RM9000)
382 return offset;
383 return regmap_out[offset];
384}
385
386#else
387
388/* sane hardware needs no mapping */
389#define map_8250_in_reg(up, offset) (offset)
390#define map_8250_out_reg(up, offset) (offset)
391
392#endif
393
394static unsigned int hub6_serial_in(struct uart_port *p, int offset)
395{
396 offset = map_8250_in_reg(p, offset) << p->regshift;
397 outb(p->hub6 - 1 + offset, p->iobase);
398 return inb(p->iobase + 1);
399}
400
401static void hub6_serial_out(struct uart_port *p, int offset, int value)
402{
403 offset = map_8250_out_reg(p, offset) << p->regshift;
404 outb(p->hub6 - 1 + offset, p->iobase);
405 outb(value, p->iobase + 1);
406}
407
408static unsigned int mem_serial_in(struct uart_port *p, int offset)
409{
410 offset = map_8250_in_reg(p, offset) << p->regshift;
411 return readb(p->membase + offset);
412}
413
414static void mem_serial_out(struct uart_port *p, int offset, int value)
415{
416 offset = map_8250_out_reg(p, offset) << p->regshift;
417 writeb(value, p->membase + offset);
418}
419
420static void mem32_serial_out(struct uart_port *p, int offset, int value)
421{
422 offset = map_8250_out_reg(p, offset) << p->regshift;
423 writel(value, p->membase + offset);
424}
425
426static unsigned int mem32_serial_in(struct uart_port *p, int offset)
427{
428 offset = map_8250_in_reg(p, offset) << p->regshift;
429 return readl(p->membase + offset);
430}
431
432static unsigned int au_serial_in(struct uart_port *p, int offset)
433{
434 offset = map_8250_in_reg(p, offset) << p->regshift;
435 return __raw_readl(p->membase + offset);
436}
437
438static void au_serial_out(struct uart_port *p, int offset, int value)
439{
440 offset = map_8250_out_reg(p, offset) << p->regshift;
441 __raw_writel(value, p->membase + offset);
442}
443
444static unsigned int tsi_serial_in(struct uart_port *p, int offset)
445{
446 unsigned int tmp;
447 offset = map_8250_in_reg(p, offset) << p->regshift;
448 if (offset == UART_IIR) {
449 tmp = readl(p->membase + (UART_IIR & ~3));
450 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
451 } else
452 return readb(p->membase + offset);
453}
454
455static void tsi_serial_out(struct uart_port *p, int offset, int value)
456{
457 offset = map_8250_out_reg(p, offset) << p->regshift;
458 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
459 writeb(value, p->membase + offset);
460}
461
462static void dwapb_serial_out(struct uart_port *p, int offset, int value)
463{
464 int save_offset = offset;
465 offset = map_8250_out_reg(p, offset) << p->regshift;
466 /* Save the LCR value so it can be re-written when a
467 * Busy Detect interrupt occurs. */
468 if (save_offset == UART_LCR) {
469 struct uart_8250_port *up = (struct uart_8250_port *)p;
470 up->lcr = value;
471 }
472 writeb(value, p->membase + offset);
473 /* Read the IER to ensure any interrupt is cleared before
474 * returning from ISR. */
475 if (save_offset == UART_TX || save_offset == UART_IER)
476 value = p->serial_in(p, UART_IER);
477}
478
479static unsigned int io_serial_in(struct uart_port *p, int offset)
480{
481 offset = map_8250_in_reg(p, offset) << p->regshift;
482 return inb(p->iobase + offset);
483}
484
485static void io_serial_out(struct uart_port *p, int offset, int value)
486{
487 offset = map_8250_out_reg(p, offset) << p->regshift;
488 outb(value, p->iobase + offset);
489}
490
491static void set_io_from_upio(struct uart_port *p)
492{
493 struct uart_8250_port *up = (struct uart_8250_port *)p;
494 switch (p->iotype) {
495 case UPIO_HUB6:
496 p->serial_in = hub6_serial_in;
497 p->serial_out = hub6_serial_out;
498 break;
499
500 case UPIO_MEM:
501 p->serial_in = mem_serial_in;
502 p->serial_out = mem_serial_out;
503 break;
504
505 case UPIO_RM9000:
506 case UPIO_MEM32:
507 p->serial_in = mem32_serial_in;
508 p->serial_out = mem32_serial_out;
509 break;
510
511 case UPIO_AU:
512 p->serial_in = au_serial_in;
513 p->serial_out = au_serial_out;
514 break;
515
516 case UPIO_TSI:
517 p->serial_in = tsi_serial_in;
518 p->serial_out = tsi_serial_out;
519 break;
520
521 case UPIO_DWAPB:
522 p->serial_in = mem_serial_in;
523 p->serial_out = dwapb_serial_out;
524 break;
525
526 default:
527 p->serial_in = io_serial_in;
528 p->serial_out = io_serial_out;
529 break;
530 }
531 /* Remember loaded iotype */
532 up->cur_iotype = p->iotype;
533}
534
535static void
536serial_out_sync(struct uart_8250_port *up, int offset, int value)
537{
538 struct uart_port *p = &up->port;
539 switch (p->iotype) {
540 case UPIO_MEM:
541 case UPIO_MEM32:
542 case UPIO_AU:
543 case UPIO_DWAPB:
544 p->serial_out(p, offset, value);
545 p->serial_in(p, UART_LCR); /* safe, no side-effects */
546 break;
547 default:
548 p->serial_out(p, offset, value);
549 }
550}
551
552#define serial_in(up, offset) \
553 (up->port.serial_in(&(up)->port, (offset)))
554#define serial_out(up, offset, value) \
555 (up->port.serial_out(&(up)->port, (offset), (value)))
556/*
557 * We used to support using pause I/O for certain machines. We
558 * haven't supported this for a while, but just in case it's badly
559 * needed for certain old 386 machines, I've left these #define's
560 * in....
561 */
562#define serial_inp(up, offset) serial_in(up, offset)
563#define serial_outp(up, offset, value) serial_out(up, offset, value)
564
565/* Uart divisor latch read */
566static inline int _serial_dl_read(struct uart_8250_port *up)
567{
568 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
569}
570
571/* Uart divisor latch write */
572static inline void _serial_dl_write(struct uart_8250_port *up, int value)
573{
574 serial_outp(up, UART_DLL, value & 0xff);
575 serial_outp(up, UART_DLM, value >> 8 & 0xff);
576}
577
578#if defined(CONFIG_MIPS_ALCHEMY)
579/* Au1x00 haven't got a standard divisor latch */
580static int serial_dl_read(struct uart_8250_port *up)
581{
582 if (up->port.iotype == UPIO_AU)
583 return __raw_readl(up->port.membase + 0x28);
584 else
585 return _serial_dl_read(up);
586}
587
588static void serial_dl_write(struct uart_8250_port *up, int value)
589{
590 if (up->port.iotype == UPIO_AU)
591 __raw_writel(value, up->port.membase + 0x28);
592 else
593 _serial_dl_write(up, value);
594}
595#elif defined(CONFIG_SERIAL_8250_RM9K)
596static int serial_dl_read(struct uart_8250_port *up)
597{
598 return (up->port.iotype == UPIO_RM9000) ?
599 (((__raw_readl(up->port.membase + 0x10) << 8) |
600 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
601 _serial_dl_read(up);
602}
603
604static void serial_dl_write(struct uart_8250_port *up, int value)
605{
606 if (up->port.iotype == UPIO_RM9000) {
607 __raw_writel(value, up->port.membase + 0x08);
608 __raw_writel(value >> 8, up->port.membase + 0x10);
609 } else {
610 _serial_dl_write(up, value);
611 }
612}
613#else
614#define serial_dl_read(up) _serial_dl_read(up)
615#define serial_dl_write(up, value) _serial_dl_write(up, value)
616#endif
617
618/*
619 * For the 16C950
620 */
621static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
622{
623 serial_out(up, UART_SCR, offset);
624 serial_out(up, UART_ICR, value);
625}
626
627static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
628{
629 unsigned int value;
630
631 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
632 serial_out(up, UART_SCR, offset);
633 value = serial_in(up, UART_ICR);
634 serial_icr_write(up, UART_ACR, up->acr);
635
636 return value;
637}
638
639/*
640 * FIFO support.
641 */
642static void serial8250_clear_fifos(struct uart_8250_port *p)
643{
644 if (p->capabilities & UART_CAP_FIFO) {
645 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
646 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
647 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
648 serial_outp(p, UART_FCR, 0);
649 }
650}
651
652/*
653 * IER sleep support. UARTs which have EFRs need the "extended
654 * capability" bit enabled. Note that on XR16C850s, we need to
655 * reset LCR to write to IER.
656 */
657static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
658{
659 if (p->capabilities & UART_CAP_SLEEP) {
660 if (p->capabilities & UART_CAP_EFR) {
661 serial_outp(p, UART_LCR, 0xBF);
662 serial_outp(p, UART_EFR, UART_EFR_ECB);
663 serial_outp(p, UART_LCR, 0);
664 }
665 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
666 if (p->capabilities & UART_CAP_EFR) {
667 serial_outp(p, UART_LCR, 0xBF);
668 serial_outp(p, UART_EFR, 0);
669 serial_outp(p, UART_LCR, 0);
670 }
671 }
672}
673
674#ifdef CONFIG_SERIAL_8250_RSA
675/*
676 * Attempts to turn on the RSA FIFO. Returns zero on failure.
677 * We set the port uart clock rate if we succeed.
678 */
679static int __enable_rsa(struct uart_8250_port *up)
680{
681 unsigned char mode;
682 int result;
683
684 mode = serial_inp(up, UART_RSA_MSR);
685 result = mode & UART_RSA_MSR_FIFO;
686
687 if (!result) {
688 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
689 mode = serial_inp(up, UART_RSA_MSR);
690 result = mode & UART_RSA_MSR_FIFO;
691 }
692
693 if (result)
694 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
695
696 return result;
697}
698
699static void enable_rsa(struct uart_8250_port *up)
700{
701 if (up->port.type == PORT_RSA) {
702 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
703 spin_lock_irq(&up->port.lock);
704 __enable_rsa(up);
705 spin_unlock_irq(&up->port.lock);
706 }
707 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
708 serial_outp(up, UART_RSA_FRR, 0);
709 }
710}
711
712/*
713 * Attempts to turn off the RSA FIFO. Returns zero on failure.
714 * It is unknown why interrupts were disabled in here. However,
715 * the caller is expected to preserve this behaviour by grabbing
716 * the spinlock before calling this function.
717 */
718static void disable_rsa(struct uart_8250_port *up)
719{
720 unsigned char mode;
721 int result;
722
723 if (up->port.type == PORT_RSA &&
724 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
725 spin_lock_irq(&up->port.lock);
726
727 mode = serial_inp(up, UART_RSA_MSR);
728 result = !(mode & UART_RSA_MSR_FIFO);
729
730 if (!result) {
731 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
732 mode = serial_inp(up, UART_RSA_MSR);
733 result = !(mode & UART_RSA_MSR_FIFO);
734 }
735
736 if (result)
737 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
738 spin_unlock_irq(&up->port.lock);
739 }
740}
741#endif /* CONFIG_SERIAL_8250_RSA */
742
743/*
744 * This is a quickie test to see how big the FIFO is.
745 * It doesn't work at all the time, more's the pity.
746 */
747static int size_fifo(struct uart_8250_port *up)
748{
749 unsigned char old_fcr, old_mcr, old_lcr;
750 unsigned short old_dl;
751 int count;
752
753 old_lcr = serial_inp(up, UART_LCR);
754 serial_outp(up, UART_LCR, 0);
755 old_fcr = serial_inp(up, UART_FCR);
756 old_mcr = serial_inp(up, UART_MCR);
757 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
758 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
759 serial_outp(up, UART_MCR, UART_MCR_LOOP);
760 serial_outp(up, UART_LCR, UART_LCR_DLAB);
761 old_dl = serial_dl_read(up);
762 serial_dl_write(up, 0x0001);
763 serial_outp(up, UART_LCR, 0x03);
764 for (count = 0; count < 256; count++)
765 serial_outp(up, UART_TX, count);
766 mdelay(20);/* FIXME - schedule_timeout */
767 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
768 (count < 256); count++)
769 serial_inp(up, UART_RX);
770 serial_outp(up, UART_FCR, old_fcr);
771 serial_outp(up, UART_MCR, old_mcr);
772 serial_outp(up, UART_LCR, UART_LCR_DLAB);
773 serial_dl_write(up, old_dl);
774 serial_outp(up, UART_LCR, old_lcr);
775
776 return count;
777}
778
779/*
780 * Read UART ID using the divisor method - set DLL and DLM to zero
781 * and the revision will be in DLL and device type in DLM. We
782 * preserve the device state across this.
783 */
784static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
785{
786 unsigned char old_dll, old_dlm, old_lcr;
787 unsigned int id;
788
789 old_lcr = serial_inp(p, UART_LCR);
790 serial_outp(p, UART_LCR, UART_LCR_DLAB);
791
792 old_dll = serial_inp(p, UART_DLL);
793 old_dlm = serial_inp(p, UART_DLM);
794
795 serial_outp(p, UART_DLL, 0);
796 serial_outp(p, UART_DLM, 0);
797
798 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
799
800 serial_outp(p, UART_DLL, old_dll);
801 serial_outp(p, UART_DLM, old_dlm);
802 serial_outp(p, UART_LCR, old_lcr);
803
804 return id;
805}
806
807/*
808 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
809 * When this function is called we know it is at least a StarTech
810 * 16650 V2, but it might be one of several StarTech UARTs, or one of
811 * its clones. (We treat the broken original StarTech 16650 V1 as a
812 * 16550, and why not? Startech doesn't seem to even acknowledge its
813 * existence.)
814 *
815 * What evil have men's minds wrought...
816 */
817static void autoconfig_has_efr(struct uart_8250_port *up)
818{
819 unsigned int id1, id2, id3, rev;
820
821 /*
822 * Everything with an EFR has SLEEP
823 */
824 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
825
826 /*
827 * First we check to see if it's an Oxford Semiconductor UART.
828 *
829 * If we have to do this here because some non-National
830 * Semiconductor clone chips lock up if you try writing to the
831 * LSR register (which serial_icr_read does)
832 */
833
834 /*
835 * Check for Oxford Semiconductor 16C950.
836 *
837 * EFR [4] must be set else this test fails.
838 *
839 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
840 * claims that it's needed for 952 dual UART's (which are not
841 * recommended for new designs).
842 */
843 up->acr = 0;
844 serial_out(up, UART_LCR, 0xBF);
845 serial_out(up, UART_EFR, UART_EFR_ECB);
846 serial_out(up, UART_LCR, 0x00);
847 id1 = serial_icr_read(up, UART_ID1);
848 id2 = serial_icr_read(up, UART_ID2);
849 id3 = serial_icr_read(up, UART_ID3);
850 rev = serial_icr_read(up, UART_REV);
851
852 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
853
854 if (id1 == 0x16 && id2 == 0xC9 &&
855 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
856 up->port.type = PORT_16C950;
857
858 /*
859 * Enable work around for the Oxford Semiconductor 952 rev B
860 * chip which causes it to seriously miscalculate baud rates
861 * when DLL is 0.
862 */
863 if (id3 == 0x52 && rev == 0x01)
864 up->bugs |= UART_BUG_QUOT;
865 return;
866 }
867
868 /*
869 * We check for a XR16C850 by setting DLL and DLM to 0, and then
870 * reading back DLL and DLM. The chip type depends on the DLM
871 * value read back:
872 * 0x10 - XR16C850 and the DLL contains the chip revision.
873 * 0x12 - XR16C2850.
874 * 0x14 - XR16C854.
875 */
876 id1 = autoconfig_read_divisor_id(up);
877 DEBUG_AUTOCONF("850id=%04x ", id1);
878
879 id2 = id1 >> 8;
880 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
881 up->port.type = PORT_16850;
882 return;
883 }
884
885 /*
886 * It wasn't an XR16C850.
887 *
888 * We distinguish between the '654 and the '650 by counting
889 * how many bytes are in the FIFO. I'm using this for now,
890 * since that's the technique that was sent to me in the
891 * serial driver update, but I'm not convinced this works.
892 * I've had problems doing this in the past. -TYT
893 */
894 if (size_fifo(up) == 64)
895 up->port.type = PORT_16654;
896 else
897 up->port.type = PORT_16650V2;
898}
899
900/*
901 * We detected a chip without a FIFO. Only two fall into
902 * this category - the original 8250 and the 16450. The
903 * 16450 has a scratch register (accessible with LCR=0)
904 */
905static void autoconfig_8250(struct uart_8250_port *up)
906{
907 unsigned char scratch, status1, status2;
908
909 up->port.type = PORT_8250;
910
911 scratch = serial_in(up, UART_SCR);
912 serial_outp(up, UART_SCR, 0xa5);
913 status1 = serial_in(up, UART_SCR);
914 serial_outp(up, UART_SCR, 0x5a);
915 status2 = serial_in(up, UART_SCR);
916 serial_outp(up, UART_SCR, scratch);
917
918 if (status1 == 0xa5 && status2 == 0x5a)
919 up->port.type = PORT_16450;
920}
921
922static int broken_efr(struct uart_8250_port *up)
923{
924 /*
925 * Exar ST16C2550 "A2" devices incorrectly detect as
926 * having an EFR, and report an ID of 0x0201. See
927 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
928 */
929 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
930 return 1;
931
932 return 0;
933}
934
935/*
936 * We know that the chip has FIFOs. Does it have an EFR? The
937 * EFR is located in the same register position as the IIR and
938 * we know the top two bits of the IIR are currently set. The
939 * EFR should contain zero. Try to read the EFR.
940 */
941static void autoconfig_16550a(struct uart_8250_port *up)
942{
943 unsigned char status1, status2;
944 unsigned int iersave;
945
946 up->port.type = PORT_16550A;
947 up->capabilities |= UART_CAP_FIFO;
948
949 /*
950 * Check for presence of the EFR when DLAB is set.
951 * Only ST16C650V1 UARTs pass this test.
952 */
953 serial_outp(up, UART_LCR, UART_LCR_DLAB);
954 if (serial_in(up, UART_EFR) == 0) {
955 serial_outp(up, UART_EFR, 0xA8);
956 if (serial_in(up, UART_EFR) != 0) {
957 DEBUG_AUTOCONF("EFRv1 ");
958 up->port.type = PORT_16650;
959 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
960 } else {
961 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
962 }
963 serial_outp(up, UART_EFR, 0);
964 return;
965 }
966
967 /*
968 * Maybe it requires 0xbf to be written to the LCR.
969 * (other ST16C650V2 UARTs, TI16C752A, etc)
970 */
971 serial_outp(up, UART_LCR, 0xBF);
972 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
973 DEBUG_AUTOCONF("EFRv2 ");
974 autoconfig_has_efr(up);
975 return;
976 }
977
978 /*
979 * Check for a National Semiconductor SuperIO chip.
980 * Attempt to switch to bank 2, read the value of the LOOP bit
981 * from EXCR1. Switch back to bank 0, change it in MCR. Then
982 * switch back to bank 2, read it from EXCR1 again and check
983 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
984 */
985 serial_outp(up, UART_LCR, 0);
986 status1 = serial_in(up, UART_MCR);
987 serial_outp(up, UART_LCR, 0xE0);
988 status2 = serial_in(up, 0x02); /* EXCR1 */
989
990 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
991 serial_outp(up, UART_LCR, 0);
992 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
993 serial_outp(up, UART_LCR, 0xE0);
994 status2 = serial_in(up, 0x02); /* EXCR1 */
995 serial_outp(up, UART_LCR, 0);
996 serial_outp(up, UART_MCR, status1);
997
998 if ((status2 ^ status1) & UART_MCR_LOOP) {
999 unsigned short quot;
1000
1001 serial_outp(up, UART_LCR, 0xE0);
1002
1003 quot = serial_dl_read(up);
1004 quot <<= 3;
1005
1006 status1 = serial_in(up, 0x04); /* EXCR2 */
1007 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
1008 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
1009 serial_outp(up, 0x04, status1);
1010
1011 serial_dl_write(up, quot);
1012
1013 serial_outp(up, UART_LCR, 0);
1014
1015 up->port.uartclk = 921600*16;
1016 up->port.type = PORT_NS16550A;
1017 up->capabilities |= UART_NATSEMI;
1018 return;
1019 }
1020 }
1021
1022 /*
1023 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1024 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1025 * Try setting it with and without DLAB set. Cheap clones
1026 * set bit 5 without DLAB set.
1027 */
1028 serial_outp(up, UART_LCR, 0);
1029 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1030 status1 = serial_in(up, UART_IIR) >> 5;
1031 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1032 serial_outp(up, UART_LCR, UART_LCR_DLAB);
1033 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1034 status2 = serial_in(up, UART_IIR) >> 5;
1035 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1036 serial_outp(up, UART_LCR, 0);
1037
1038 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1039
1040 if (status1 == 6 && status2 == 7) {
1041 up->port.type = PORT_16750;
1042 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1043 return;
1044 }
1045
1046 /*
1047 * Try writing and reading the UART_IER_UUE bit (b6).
1048 * If it works, this is probably one of the Xscale platform's
1049 * internal UARTs.
1050 * We're going to explicitly set the UUE bit to 0 before
1051 * trying to write and read a 1 just to make sure it's not
1052 * already a 1 and maybe locked there before we even start start.
1053 */
1054 iersave = serial_in(up, UART_IER);
1055 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1056 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1057 /*
1058 * OK it's in a known zero state, try writing and reading
1059 * without disturbing the current state of the other bits.
1060 */
1061 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1062 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1063 /*
1064 * It's an Xscale.
1065 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1066 */
1067 DEBUG_AUTOCONF("Xscale ");
1068 up->port.type = PORT_XSCALE;
1069 up->capabilities |= UART_CAP_UUE;
1070 return;
1071 }
1072 } else {
1073 /*
1074 * If we got here we couldn't force the IER_UUE bit to 0.
1075 * Log it and continue.
1076 */
1077 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1078 }
1079 serial_outp(up, UART_IER, iersave);
1080
1081 /*
1082 * We distinguish between 16550A and U6 16550A by counting
1083 * how many bytes are in the FIFO.
1084 */
1085 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1086 up->port.type = PORT_U6_16550A;
1087 up->capabilities |= UART_CAP_AFE;
1088 }
1089}
1090
1091/*
1092 * This routine is called by rs_init() to initialize a specific serial
1093 * port. It determines what type of UART chip this serial port is
1094 * using: 8250, 16450, 16550, 16550A. The important question is
1095 * whether or not this UART is a 16550A or not, since this will
1096 * determine whether or not we can use its FIFO features or not.
1097 */
1098static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1099{
1100 unsigned char status1, scratch, scratch2, scratch3;
1101 unsigned char save_lcr, save_mcr;
1102 unsigned long flags;
1103
1104 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1105 return;
1106
1107 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1108 serial_index(&up->port), up->port.iobase, up->port.membase);
1109
1110 /*
1111 * We really do need global IRQs disabled here - we're going to
1112 * be frobbing the chips IRQ enable register to see if it exists.
1113 */
1114 spin_lock_irqsave(&up->port.lock, flags);
1115
1116 up->capabilities = 0;
1117 up->bugs = 0;
1118
1119 if (!(up->port.flags & UPF_BUGGY_UART)) {
1120 /*
1121 * Do a simple existence test first; if we fail this,
1122 * there's no point trying anything else.
1123 *
1124 * 0x80 is used as a nonsense port to prevent against
1125 * false positives due to ISA bus float. The
1126 * assumption is that 0x80 is a non-existent port;
1127 * which should be safe since include/asm/io.h also
1128 * makes this assumption.
1129 *
1130 * Note: this is safe as long as MCR bit 4 is clear
1131 * and the device is in "PC" mode.
1132 */
1133 scratch = serial_inp(up, UART_IER);
1134 serial_outp(up, UART_IER, 0);
1135#ifdef __i386__
1136 outb(0xff, 0x080);
1137#endif
1138 /*
1139 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1140 * 16C754B) allow only to modify them if an EFR bit is set.
1141 */
1142 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1143 serial_outp(up, UART_IER, 0x0F);
1144#ifdef __i386__
1145 outb(0, 0x080);
1146#endif
1147 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1148 serial_outp(up, UART_IER, scratch);
1149 if (scratch2 != 0 || scratch3 != 0x0F) {
1150 /*
1151 * We failed; there's nothing here
1152 */
1153 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1154 scratch2, scratch3);
1155 goto out;
1156 }
1157 }
1158
1159 save_mcr = serial_in(up, UART_MCR);
1160 save_lcr = serial_in(up, UART_LCR);
1161
1162 /*
1163 * Check to see if a UART is really there. Certain broken
1164 * internal modems based on the Rockwell chipset fail this
1165 * test, because they apparently don't implement the loopback
1166 * test mode. So this test is skipped on the COM 1 through
1167 * COM 4 ports. This *should* be safe, since no board
1168 * manufacturer would be stupid enough to design a board
1169 * that conflicts with COM 1-4 --- we hope!
1170 */
1171 if (!(up->port.flags & UPF_SKIP_TEST)) {
1172 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1173 status1 = serial_inp(up, UART_MSR) & 0xF0;
1174 serial_outp(up, UART_MCR, save_mcr);
1175 if (status1 != 0x90) {
1176 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1177 status1);
1178 goto out;
1179 }
1180 }
1181
1182 /*
1183 * We're pretty sure there's a port here. Lets find out what
1184 * type of port it is. The IIR top two bits allows us to find
1185 * out if it's 8250 or 16450, 16550, 16550A or later. This
1186 * determines what we test for next.
1187 *
1188 * We also initialise the EFR (if any) to zero for later. The
1189 * EFR occupies the same register location as the FCR and IIR.
1190 */
1191 serial_outp(up, UART_LCR, 0xBF);
1192 serial_outp(up, UART_EFR, 0);
1193 serial_outp(up, UART_LCR, 0);
1194
1195 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1196 scratch = serial_in(up, UART_IIR) >> 6;
1197
1198 DEBUG_AUTOCONF("iir=%d ", scratch);
1199
1200 switch (scratch) {
1201 case 0:
1202 autoconfig_8250(up);
1203 break;
1204 case 1:
1205 up->port.type = PORT_UNKNOWN;
1206 break;
1207 case 2:
1208 up->port.type = PORT_16550;
1209 break;
1210 case 3:
1211 autoconfig_16550a(up);
1212 break;
1213 }
1214
1215#ifdef CONFIG_SERIAL_8250_RSA
1216 /*
1217 * Only probe for RSA ports if we got the region.
1218 */
1219 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1220 int i;
1221
1222 for (i = 0 ; i < probe_rsa_count; ++i) {
1223 if (probe_rsa[i] == up->port.iobase &&
1224 __enable_rsa(up)) {
1225 up->port.type = PORT_RSA;
1226 break;
1227 }
1228 }
1229 }
1230#endif
1231
1232 serial_outp(up, UART_LCR, save_lcr);
1233
1234 if (up->capabilities != uart_config[up->port.type].flags) {
1235 printk(KERN_WARNING
1236 "ttyS%d: detected caps %08x should be %08x\n",
1237 serial_index(&up->port), up->capabilities,
1238 uart_config[up->port.type].flags);
1239 }
1240
1241 up->port.fifosize = uart_config[up->port.type].fifo_size;
1242 up->capabilities = uart_config[up->port.type].flags;
1243 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1244
1245 if (up->port.type == PORT_UNKNOWN)
1246 goto out;
1247
1248 /*
1249 * Reset the UART.
1250 */
1251#ifdef CONFIG_SERIAL_8250_RSA
1252 if (up->port.type == PORT_RSA)
1253 serial_outp(up, UART_RSA_FRR, 0);
1254#endif
1255 serial_outp(up, UART_MCR, save_mcr);
1256 serial8250_clear_fifos(up);
1257 serial_in(up, UART_RX);
1258 if (up->capabilities & UART_CAP_UUE)
1259 serial_outp(up, UART_IER, UART_IER_UUE);
1260 else
1261 serial_outp(up, UART_IER, 0);
1262
1263 out:
1264 spin_unlock_irqrestore(&up->port.lock, flags);
1265 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1266}
1267
1268static void autoconfig_irq(struct uart_8250_port *up)
1269{
1270 unsigned char save_mcr, save_ier;
1271 unsigned char save_ICP = 0;
1272 unsigned int ICP = 0;
1273 unsigned long irqs;
1274 int irq;
1275
1276 if (up->port.flags & UPF_FOURPORT) {
1277 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1278 save_ICP = inb_p(ICP);
1279 outb_p(0x80, ICP);
1280 (void) inb_p(ICP);
1281 }
1282
1283 /* forget possible initially masked and pending IRQ */
1284 probe_irq_off(probe_irq_on());
1285 save_mcr = serial_inp(up, UART_MCR);
1286 save_ier = serial_inp(up, UART_IER);
1287 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1288
1289 irqs = probe_irq_on();
1290 serial_outp(up, UART_MCR, 0);
1291 udelay(10);
1292 if (up->port.flags & UPF_FOURPORT) {
1293 serial_outp(up, UART_MCR,
1294 UART_MCR_DTR | UART_MCR_RTS);
1295 } else {
1296 serial_outp(up, UART_MCR,
1297 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1298 }
1299 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1300 (void)serial_inp(up, UART_LSR);
1301 (void)serial_inp(up, UART_RX);
1302 (void)serial_inp(up, UART_IIR);
1303 (void)serial_inp(up, UART_MSR);
1304 serial_outp(up, UART_TX, 0xFF);
1305 udelay(20);
1306 irq = probe_irq_off(irqs);
1307
1308 serial_outp(up, UART_MCR, save_mcr);
1309 serial_outp(up, UART_IER, save_ier);
1310
1311 if (up->port.flags & UPF_FOURPORT)
1312 outb_p(save_ICP, ICP);
1313
1314 up->port.irq = (irq > 0) ? irq : 0;
1315}
1316
1317static inline void __stop_tx(struct uart_8250_port *p)
1318{
1319 if (p->ier & UART_IER_THRI) {
1320 p->ier &= ~UART_IER_THRI;
1321 serial_out(p, UART_IER, p->ier);
1322 }
1323}
1324
1325static void serial8250_stop_tx(struct uart_port *port)
1326{
1327 struct uart_8250_port *up = (struct uart_8250_port *)port;
1328
1329 __stop_tx(up);
1330
1331 /*
1332 * We really want to stop the transmitter from sending.
1333 */
1334 if (up->port.type == PORT_16C950) {
1335 up->acr |= UART_ACR_TXDIS;
1336 serial_icr_write(up, UART_ACR, up->acr);
1337 }
1338}
1339
1340static void transmit_chars(struct uart_8250_port *up);
1341
1342static void serial8250_start_tx(struct uart_port *port)
1343{
1344 struct uart_8250_port *up = (struct uart_8250_port *)port;
1345
1346 if (!(up->ier & UART_IER_THRI)) {
1347 up->ier |= UART_IER_THRI;
1348 serial_out(up, UART_IER, up->ier);
1349
1350 if (up->bugs & UART_BUG_TXEN) {
1351 unsigned char lsr;
1352 lsr = serial_in(up, UART_LSR);
1353 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1354 if ((up->port.type == PORT_RM9000) ?
1355 (lsr & UART_LSR_THRE) :
1356 (lsr & UART_LSR_TEMT))
1357 transmit_chars(up);
1358 }
1359 }
1360
1361 /*
1362 * Re-enable the transmitter if we disabled it.
1363 */
1364 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1365 up->acr &= ~UART_ACR_TXDIS;
1366 serial_icr_write(up, UART_ACR, up->acr);
1367 }
1368}
1369
1370static void serial8250_stop_rx(struct uart_port *port)
1371{
1372 struct uart_8250_port *up = (struct uart_8250_port *)port;
1373
1374 up->ier &= ~UART_IER_RLSI;
1375 up->port.read_status_mask &= ~UART_LSR_DR;
1376 serial_out(up, UART_IER, up->ier);
1377}
1378
1379static void serial8250_enable_ms(struct uart_port *port)
1380{
1381 struct uart_8250_port *up = (struct uart_8250_port *)port;
1382
1383 /* no MSR capabilities */
1384 if (up->bugs & UART_BUG_NOMSR)
1385 return;
1386
1387 up->ier |= UART_IER_MSI;
1388 serial_out(up, UART_IER, up->ier);
1389}
1390
1391static void
1392receive_chars(struct uart_8250_port *up, unsigned int *status)
1393{
1394 struct tty_struct *tty = up->port.state->port.tty;
1395 unsigned char ch, lsr = *status;
1396 int max_count = 256;
1397 char flag;
1398
1399 do {
1400 if (likely(lsr & UART_LSR_DR))
1401 ch = serial_inp(up, UART_RX);
1402 else
1403 /*
1404 * Intel 82571 has a Serial Over Lan device that will
1405 * set UART_LSR_BI without setting UART_LSR_DR when
1406 * it receives a break. To avoid reading from the
1407 * receive buffer without UART_LSR_DR bit set, we
1408 * just force the read character to be 0
1409 */
1410 ch = 0;
1411
1412 flag = TTY_NORMAL;
1413 up->port.icount.rx++;
1414
1415 lsr |= up->lsr_saved_flags;
1416 up->lsr_saved_flags = 0;
1417
1418 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1419 /*
1420 * For statistics only
1421 */
1422 if (lsr & UART_LSR_BI) {
1423 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1424 up->port.icount.brk++;
1425 /*
1426 * We do the SysRQ and SAK checking
1427 * here because otherwise the break
1428 * may get masked by ignore_status_mask
1429 * or read_status_mask.
1430 */
1431 if (uart_handle_break(&up->port))
1432 goto ignore_char;
1433 } else if (lsr & UART_LSR_PE)
1434 up->port.icount.parity++;
1435 else if (lsr & UART_LSR_FE)
1436 up->port.icount.frame++;
1437 if (lsr & UART_LSR_OE)
1438 up->port.icount.overrun++;
1439
1440 /*
1441 * Mask off conditions which should be ignored.
1442 */
1443 lsr &= up->port.read_status_mask;
1444
1445 if (lsr & UART_LSR_BI) {
1446 DEBUG_INTR("handling break....");
1447 flag = TTY_BREAK;
1448 } else if (lsr & UART_LSR_PE)
1449 flag = TTY_PARITY;
1450 else if (lsr & UART_LSR_FE)
1451 flag = TTY_FRAME;
1452 }
1453 if (uart_handle_sysrq_char(&up->port, ch))
1454 goto ignore_char;
1455
1456 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1457
1458ignore_char:
1459 lsr = serial_inp(up, UART_LSR);
1460 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1461 spin_unlock(&up->port.lock);
1462 tty_flip_buffer_push(tty);
1463 spin_lock(&up->port.lock);
1464 *status = lsr;
1465}
1466
1467static void transmit_chars(struct uart_8250_port *up)
1468{
1469 struct circ_buf *xmit = &up->port.state->xmit;
1470 int count;
1471
1472 if (up->port.x_char) {
1473 serial_outp(up, UART_TX, up->port.x_char);
1474 up->port.icount.tx++;
1475 up->port.x_char = 0;
1476 return;
1477 }
1478 if (uart_tx_stopped(&up->port)) {
1479 serial8250_stop_tx(&up->port);
1480 return;
1481 }
1482 if (uart_circ_empty(xmit)) {
1483 __stop_tx(up);
1484 return;
1485 }
1486
1487 count = up->tx_loadsz;
1488 do {
1489 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1490 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1491 up->port.icount.tx++;
1492 if (uart_circ_empty(xmit))
1493 break;
1494 } while (--count > 0);
1495
1496 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1497 uart_write_wakeup(&up->port);
1498
1499 DEBUG_INTR("THRE...");
1500
1501 if (uart_circ_empty(xmit))
1502 __stop_tx(up);
1503}
1504
1505static unsigned int check_modem_status(struct uart_8250_port *up)
1506{
1507 unsigned int status = serial_in(up, UART_MSR);
1508
1509 status |= up->msr_saved_flags;
1510 up->msr_saved_flags = 0;
1511 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1512 up->port.state != NULL) {
1513 if (status & UART_MSR_TERI)
1514 up->port.icount.rng++;
1515 if (status & UART_MSR_DDSR)
1516 up->port.icount.dsr++;
1517 if (status & UART_MSR_DDCD)
1518 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1519 if (status & UART_MSR_DCTS)
1520 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1521
1522 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
1523 }
1524
1525 return status;
1526}
1527
1528/*
1529 * This handles the interrupt from one port.
1530 */
1531static void serial8250_handle_port(struct uart_8250_port *up)
1532{
1533 unsigned int status;
1534 unsigned long flags;
1535
1536 spin_lock_irqsave(&up->port.lock, flags);
1537
1538 status = serial_inp(up, UART_LSR);
1539
1540 DEBUG_INTR("status = %x...", status);
1541
1542 if (status & (UART_LSR_DR | UART_LSR_BI))
1543 receive_chars(up, &status);
1544 check_modem_status(up);
1545 if (status & UART_LSR_THRE)
1546 transmit_chars(up);
1547
1548 spin_unlock_irqrestore(&up->port.lock, flags);
1549}
1550
1551/*
1552 * This is the serial driver's interrupt routine.
1553 *
1554 * Arjan thinks the old way was overly complex, so it got simplified.
1555 * Alan disagrees, saying that need the complexity to handle the weird
1556 * nature of ISA shared interrupts. (This is a special exception.)
1557 *
1558 * In order to handle ISA shared interrupts properly, we need to check
1559 * that all ports have been serviced, and therefore the ISA interrupt
1560 * line has been de-asserted.
1561 *
1562 * This means we need to loop through all ports. checking that they
1563 * don't have an interrupt pending.
1564 */
1565static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1566{
1567 struct irq_info *i = dev_id;
1568 struct list_head *l, *end = NULL;
1569 int pass_counter = 0, handled = 0;
1570
1571 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1572
1573 spin_lock(&i->lock);
1574
1575 l = i->head;
1576 do {
1577 struct uart_8250_port *up;
1578 unsigned int iir;
1579
1580 up = list_entry(l, struct uart_8250_port, list);
1581
1582 iir = serial_in(up, UART_IIR);
1583 if (!(iir & UART_IIR_NO_INT)) {
1584 serial8250_handle_port(up);
1585
1586 handled = 1;
1587
1588 end = NULL;
1589 } else if (up->port.iotype == UPIO_DWAPB &&
1590 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1591 /* The DesignWare APB UART has an Busy Detect (0x07)
1592 * interrupt meaning an LCR write attempt occured while the
1593 * UART was busy. The interrupt must be cleared by reading
1594 * the UART status register (USR) and the LCR re-written. */
1595 unsigned int status;
1596 status = *(volatile u32 *)up->port.private_data;
1597 serial_out(up, UART_LCR, up->lcr);
1598
1599 handled = 1;
1600
1601 end = NULL;
1602 } else if (end == NULL)
1603 end = l;
1604
1605 l = l->next;
1606
1607 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1608 /* If we hit this, we're dead. */
1609 printk(KERN_ERR "serial8250: too much work for "
1610 "irq%d\n", irq);
1611 break;
1612 }
1613 } while (l != end);
1614
1615 spin_unlock(&i->lock);
1616
1617 DEBUG_INTR("end.\n");
1618
1619 return IRQ_RETVAL(handled);
1620}
1621
1622/*
1623 * To support ISA shared interrupts, we need to have one interrupt
1624 * handler that ensures that the IRQ line has been deasserted
1625 * before returning. Failing to do this will result in the IRQ
1626 * line being stuck active, and, since ISA irqs are edge triggered,
1627 * no more IRQs will be seen.
1628 */
1629static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1630{
1631 spin_lock_irq(&i->lock);
1632
1633 if (!list_empty(i->head)) {
1634 if (i->head == &up->list)
1635 i->head = i->head->next;
1636 list_del(&up->list);
1637 } else {
1638 BUG_ON(i->head != &up->list);
1639 i->head = NULL;
1640 }
1641 spin_unlock_irq(&i->lock);
1642 /* List empty so throw away the hash node */
1643 if (i->head == NULL) {
1644 hlist_del(&i->node);
1645 kfree(i);
1646 }
1647}
1648
1649static int serial_link_irq_chain(struct uart_8250_port *up)
1650{
1651 struct hlist_head *h;
1652 struct hlist_node *n;
1653 struct irq_info *i;
1654 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1655
1656 mutex_lock(&hash_mutex);
1657
1658 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1659
1660 hlist_for_each(n, h) {
1661 i = hlist_entry(n, struct irq_info, node);
1662 if (i->irq == up->port.irq)
1663 break;
1664 }
1665
1666 if (n == NULL) {
1667 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1668 if (i == NULL) {
1669 mutex_unlock(&hash_mutex);
1670 return -ENOMEM;
1671 }
1672 spin_lock_init(&i->lock);
1673 i->irq = up->port.irq;
1674 hlist_add_head(&i->node, h);
1675 }
1676 mutex_unlock(&hash_mutex);
1677
1678 spin_lock_irq(&i->lock);
1679
1680 if (i->head) {
1681 list_add(&up->list, i->head);
1682 spin_unlock_irq(&i->lock);
1683
1684 ret = 0;
1685 } else {
1686 INIT_LIST_HEAD(&up->list);
1687 i->head = &up->list;
1688 spin_unlock_irq(&i->lock);
1689 irq_flags |= up->port.irqflags;
1690 ret = request_irq(up->port.irq, serial8250_interrupt,
1691 irq_flags, "serial", i);
1692 if (ret < 0)
1693 serial_do_unlink(i, up);
1694 }
1695
1696 return ret;
1697}
1698
1699static void serial_unlink_irq_chain(struct uart_8250_port *up)
1700{
1701 struct irq_info *i;
1702 struct hlist_node *n;
1703 struct hlist_head *h;
1704
1705 mutex_lock(&hash_mutex);
1706
1707 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1708
1709 hlist_for_each(n, h) {
1710 i = hlist_entry(n, struct irq_info, node);
1711 if (i->irq == up->port.irq)
1712 break;
1713 }
1714
1715 BUG_ON(n == NULL);
1716 BUG_ON(i->head == NULL);
1717
1718 if (list_empty(i->head))
1719 free_irq(up->port.irq, i);
1720
1721 serial_do_unlink(i, up);
1722 mutex_unlock(&hash_mutex);
1723}
1724
1725/* Base timer interval for polling */
1726static inline int poll_timeout(int timeout)
1727{
1728 return timeout > 6 ? (timeout / 2 - 2) : 1;
1729}
1730
1731/*
1732 * This function is used to handle ports that do not have an
1733 * interrupt. This doesn't work very well for 16450's, but gives
1734 * barely passable results for a 16550A. (Although at the expense
1735 * of much CPU overhead).
1736 */
1737static void serial8250_timeout(unsigned long data)
1738{
1739 struct uart_8250_port *up = (struct uart_8250_port *)data;
1740 unsigned int iir;
1741
1742 iir = serial_in(up, UART_IIR);
1743 if (!(iir & UART_IIR_NO_INT))
1744 serial8250_handle_port(up);
1745 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1746}
1747
1748static void serial8250_backup_timeout(unsigned long data)
1749{
1750 struct uart_8250_port *up = (struct uart_8250_port *)data;
1751 unsigned int iir, ier = 0, lsr;
1752 unsigned long flags;
1753
1754 /*
1755 * Must disable interrupts or else we risk racing with the interrupt
1756 * based handler.
1757 */
1758 if (is_real_interrupt(up->port.irq)) {
1759 ier = serial_in(up, UART_IER);
1760 serial_out(up, UART_IER, 0);
1761 }
1762
1763 iir = serial_in(up, UART_IIR);
1764
1765 /*
1766 * This should be a safe test for anyone who doesn't trust the
1767 * IIR bits on their UART, but it's specifically designed for
1768 * the "Diva" UART used on the management processor on many HP
1769 * ia64 and parisc boxes.
1770 */
1771 spin_lock_irqsave(&up->port.lock, flags);
1772 lsr = serial_in(up, UART_LSR);
1773 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1774 spin_unlock_irqrestore(&up->port.lock, flags);
1775 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1776 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1777 (lsr & UART_LSR_THRE)) {
1778 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1779 iir |= UART_IIR_THRI;
1780 }
1781
1782 if (!(iir & UART_IIR_NO_INT))
1783 serial8250_handle_port(up);
1784
1785 if (is_real_interrupt(up->port.irq))
1786 serial_out(up, UART_IER, ier);
1787
1788 /* Standard timer interval plus 0.2s to keep the port running */
1789 mod_timer(&up->timer,
1790 jiffies + poll_timeout(up->port.timeout) + HZ / 5);
1791}
1792
1793static unsigned int serial8250_tx_empty(struct uart_port *port)
1794{
1795 struct uart_8250_port *up = (struct uart_8250_port *)port;
1796 unsigned long flags;
1797 unsigned int lsr;
1798
1799 spin_lock_irqsave(&up->port.lock, flags);
1800 lsr = serial_in(up, UART_LSR);
1801 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1802 spin_unlock_irqrestore(&up->port.lock, flags);
1803
1804 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1805}
1806
1807static unsigned int serial8250_get_mctrl(struct uart_port *port)
1808{
1809 struct uart_8250_port *up = (struct uart_8250_port *)port;
1810 unsigned int status;
1811 unsigned int ret;
1812
1813 status = check_modem_status(up);
1814
1815 ret = 0;
1816 if (status & UART_MSR_DCD)
1817 ret |= TIOCM_CAR;
1818 if (status & UART_MSR_RI)
1819 ret |= TIOCM_RNG;
1820 if (status & UART_MSR_DSR)
1821 ret |= TIOCM_DSR;
1822 if (status & UART_MSR_CTS)
1823 ret |= TIOCM_CTS;
1824 return ret;
1825}
1826
1827static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1828{
1829 struct uart_8250_port *up = (struct uart_8250_port *)port;
1830 unsigned char mcr = 0;
1831
1832 if (mctrl & TIOCM_RTS)
1833 mcr |= UART_MCR_RTS;
1834 if (mctrl & TIOCM_DTR)
1835 mcr |= UART_MCR_DTR;
1836 if (mctrl & TIOCM_OUT1)
1837 mcr |= UART_MCR_OUT1;
1838 if (mctrl & TIOCM_OUT2)
1839 mcr |= UART_MCR_OUT2;
1840 if (mctrl & TIOCM_LOOP)
1841 mcr |= UART_MCR_LOOP;
1842
1843 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1844
1845 serial_out(up, UART_MCR, mcr);
1846}
1847
1848static void serial8250_break_ctl(struct uart_port *port, int break_state)
1849{
1850 struct uart_8250_port *up = (struct uart_8250_port *)port;
1851 unsigned long flags;
1852
1853 spin_lock_irqsave(&up->port.lock, flags);
1854 if (break_state == -1)
1855 up->lcr |= UART_LCR_SBC;
1856 else
1857 up->lcr &= ~UART_LCR_SBC;
1858 serial_out(up, UART_LCR, up->lcr);
1859 spin_unlock_irqrestore(&up->port.lock, flags);
1860}
1861
1862/*
1863 * Wait for transmitter & holding register to empty
1864 */
1865static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1866{
1867 unsigned int status, tmout = 10000;
1868
1869 /* Wait up to 10ms for the character(s) to be sent. */
1870 do {
1871 status = serial_in(up, UART_LSR);
1872
1873 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1874
1875 if (--tmout == 0)
1876 break;
1877 udelay(1);
1878 } while ((status & bits) != bits);
1879
1880 /* Wait up to 1s for flow control if necessary */
1881 if (up->port.flags & UPF_CONS_FLOW) {
1882 unsigned int tmout;
1883 for (tmout = 1000000; tmout; tmout--) {
1884 unsigned int msr = serial_in(up, UART_MSR);
1885 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1886 if (msr & UART_MSR_CTS)
1887 break;
1888 udelay(1);
1889 touch_nmi_watchdog();
1890 }
1891 }
1892}
1893
1894#ifdef CONFIG_CONSOLE_POLL
1895/*
1896 * Console polling routines for writing and reading from the uart while
1897 * in an interrupt or debug context.
1898 */
1899
1900static int serial8250_get_poll_char(struct uart_port *port)
1901{
1902 struct uart_8250_port *up = (struct uart_8250_port *)port;
1903 unsigned char lsr = serial_inp(up, UART_LSR);
1904
1905 if (!(lsr & UART_LSR_DR))
1906 return NO_POLL_CHAR;
1907
1908 return serial_inp(up, UART_RX);
1909}
1910
1911
1912static void serial8250_put_poll_char(struct uart_port *port,
1913 unsigned char c)
1914{
1915 unsigned int ier;
1916 struct uart_8250_port *up = (struct uart_8250_port *)port;
1917
1918 /*
1919 * First save the IER then disable the interrupts
1920 */
1921 ier = serial_in(up, UART_IER);
1922 if (up->capabilities & UART_CAP_UUE)
1923 serial_out(up, UART_IER, UART_IER_UUE);
1924 else
1925 serial_out(up, UART_IER, 0);
1926
1927 wait_for_xmitr(up, BOTH_EMPTY);
1928 /*
1929 * Send the character out.
1930 * If a LF, also do CR...
1931 */
1932 serial_out(up, UART_TX, c);
1933 if (c == 10) {
1934 wait_for_xmitr(up, BOTH_EMPTY);
1935 serial_out(up, UART_TX, 13);
1936 }
1937
1938 /*
1939 * Finally, wait for transmitter to become empty
1940 * and restore the IER
1941 */
1942 wait_for_xmitr(up, BOTH_EMPTY);
1943 serial_out(up, UART_IER, ier);
1944}
1945
1946#endif /* CONFIG_CONSOLE_POLL */
1947
1948static int serial8250_startup(struct uart_port *port)
1949{
1950 struct uart_8250_port *up = (struct uart_8250_port *)port;
1951 unsigned long flags;
1952 unsigned char lsr, iir;
1953 int retval;
1954
1955 up->capabilities = uart_config[up->port.type].flags;
1956 up->mcr = 0;
1957
1958 if (up->port.iotype != up->cur_iotype)
1959 set_io_from_upio(port);
1960
1961 if (up->port.type == PORT_16C950) {
1962 /* Wake up and initialize UART */
1963 up->acr = 0;
1964 serial_outp(up, UART_LCR, 0xBF);
1965 serial_outp(up, UART_EFR, UART_EFR_ECB);
1966 serial_outp(up, UART_IER, 0);
1967 serial_outp(up, UART_LCR, 0);
1968 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1969 serial_outp(up, UART_LCR, 0xBF);
1970 serial_outp(up, UART_EFR, UART_EFR_ECB);
1971 serial_outp(up, UART_LCR, 0);
1972 }
1973
1974#ifdef CONFIG_SERIAL_8250_RSA
1975 /*
1976 * If this is an RSA port, see if we can kick it up to the
1977 * higher speed clock.
1978 */
1979 enable_rsa(up);
1980#endif
1981
1982 /*
1983 * Clear the FIFO buffers and disable them.
1984 * (they will be reenabled in set_termios())
1985 */
1986 serial8250_clear_fifos(up);
1987
1988 /*
1989 * Clear the interrupt registers.
1990 */
1991 (void) serial_inp(up, UART_LSR);
1992 (void) serial_inp(up, UART_RX);
1993 (void) serial_inp(up, UART_IIR);
1994 (void) serial_inp(up, UART_MSR);
1995
1996 /*
1997 * At this point, there's no way the LSR could still be 0xff;
1998 * if it is, then bail out, because there's likely no UART
1999 * here.
2000 */
2001 if (!(up->port.flags & UPF_BUGGY_UART) &&
2002 (serial_inp(up, UART_LSR) == 0xff)) {
2003 printk(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2004 serial_index(&up->port));
2005 return -ENODEV;
2006 }
2007
2008 /*
2009 * For a XR16C850, we need to set the trigger levels
2010 */
2011 if (up->port.type == PORT_16850) {
2012 unsigned char fctr;
2013
2014 serial_outp(up, UART_LCR, 0xbf);
2015
2016 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2017 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2018 serial_outp(up, UART_TRG, UART_TRG_96);
2019 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2020 serial_outp(up, UART_TRG, UART_TRG_96);
2021
2022 serial_outp(up, UART_LCR, 0);
2023 }
2024
2025 if (is_real_interrupt(up->port.irq)) {
2026 unsigned char iir1;
2027 /*
2028 * Test for UARTs that do not reassert THRE when the
2029 * transmitter is idle and the interrupt has already
2030 * been cleared. Real 16550s should always reassert
2031 * this interrupt whenever the transmitter is idle and
2032 * the interrupt is enabled. Delays are necessary to
2033 * allow register changes to become visible.
2034 */
2035 spin_lock_irqsave(&up->port.lock, flags);
2036 if (up->port.irqflags & IRQF_SHARED)
2037 disable_irq_nosync(up->port.irq);
2038
2039 wait_for_xmitr(up, UART_LSR_THRE);
2040 serial_out_sync(up, UART_IER, UART_IER_THRI);
2041 udelay(1); /* allow THRE to set */
2042 iir1 = serial_in(up, UART_IIR);
2043 serial_out(up, UART_IER, 0);
2044 serial_out_sync(up, UART_IER, UART_IER_THRI);
2045 udelay(1); /* allow a working UART time to re-assert THRE */
2046 iir = serial_in(up, UART_IIR);
2047 serial_out(up, UART_IER, 0);
2048
2049 if (up->port.irqflags & IRQF_SHARED)
2050 enable_irq(up->port.irq);
2051 spin_unlock_irqrestore(&up->port.lock, flags);
2052
2053 /*
2054 * If the interrupt is not reasserted, setup a timer to
2055 * kick the UART on a regular basis.
2056 */
2057 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
2058 up->bugs |= UART_BUG_THRE;
2059 pr_debug("ttyS%d - using backup timer\n",
2060 serial_index(port));
2061 }
2062 }
2063
2064 /*
2065 * The above check will only give an accurate result the first time
2066 * the port is opened so this value needs to be preserved.
2067 */
2068 if (up->bugs & UART_BUG_THRE) {
2069 up->timer.function = serial8250_backup_timeout;
2070 up->timer.data = (unsigned long)up;
2071 mod_timer(&up->timer, jiffies +
2072 poll_timeout(up->port.timeout) + HZ / 5);
2073 }
2074
2075 /*
2076 * If the "interrupt" for this port doesn't correspond with any
2077 * hardware interrupt, we use a timer-based system. The original
2078 * driver used to do this with IRQ0.
2079 */
2080 if (!is_real_interrupt(up->port.irq)) {
2081 up->timer.data = (unsigned long)up;
2082 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
2083 } else {
2084 retval = serial_link_irq_chain(up);
2085 if (retval)
2086 return retval;
2087 }
2088
2089 /*
2090 * Now, initialize the UART
2091 */
2092 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2093
2094 spin_lock_irqsave(&up->port.lock, flags);
2095 if (up->port.flags & UPF_FOURPORT) {
2096 if (!is_real_interrupt(up->port.irq))
2097 up->port.mctrl |= TIOCM_OUT1;
2098 } else
2099 /*
2100 * Most PC uarts need OUT2 raised to enable interrupts.
2101 */
2102 if (is_real_interrupt(up->port.irq))
2103 up->port.mctrl |= TIOCM_OUT2;
2104
2105 serial8250_set_mctrl(&up->port, up->port.mctrl);
2106
2107 /* Serial over Lan (SoL) hack:
2108 Intel 8257x Gigabit ethernet chips have a
2109 16550 emulation, to be used for Serial Over Lan.
2110 Those chips take a longer time than a normal
2111 serial device to signalize that a transmission
2112 data was queued. Due to that, the above test generally
2113 fails. One solution would be to delay the reading of
2114 iir. However, this is not reliable, since the timeout
2115 is variable. So, let's just don't test if we receive
2116 TX irq. This way, we'll never enable UART_BUG_TXEN.
2117 */
2118 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2119 goto dont_test_tx_en;
2120
2121 /*
2122 * Do a quick test to see if we receive an
2123 * interrupt when we enable the TX irq.
2124 */
2125 serial_outp(up, UART_IER, UART_IER_THRI);
2126 lsr = serial_in(up, UART_LSR);
2127 iir = serial_in(up, UART_IIR);
2128 serial_outp(up, UART_IER, 0);
2129
2130 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2131 if (!(up->bugs & UART_BUG_TXEN)) {
2132 up->bugs |= UART_BUG_TXEN;
2133 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2134 serial_index(port));
2135 }
2136 } else {
2137 up->bugs &= ~UART_BUG_TXEN;
2138 }
2139
2140dont_test_tx_en:
2141 spin_unlock_irqrestore(&up->port.lock, flags);
2142
2143 /*
2144 * Clear the interrupt registers again for luck, and clear the
2145 * saved flags to avoid getting false values from polling
2146 * routines or the previous session.
2147 */
2148 serial_inp(up, UART_LSR);
2149 serial_inp(up, UART_RX);
2150 serial_inp(up, UART_IIR);
2151 serial_inp(up, UART_MSR);
2152 up->lsr_saved_flags = 0;
2153 up->msr_saved_flags = 0;
2154
2155 /*
2156 * Finally, enable interrupts. Note: Modem status interrupts
2157 * are set via set_termios(), which will be occurring imminently
2158 * anyway, so we don't enable them here.
2159 */
2160 up->ier = UART_IER_RLSI | UART_IER_RDI;
2161 serial_outp(up, UART_IER, up->ier);
2162
2163 if (up->port.flags & UPF_FOURPORT) {
2164 unsigned int icp;
2165 /*
2166 * Enable interrupts on the AST Fourport board
2167 */
2168 icp = (up->port.iobase & 0xfe0) | 0x01f;
2169 outb_p(0x80, icp);
2170 (void) inb_p(icp);
2171 }
2172
2173 return 0;
2174}
2175
2176static void serial8250_shutdown(struct uart_port *port)
2177{
2178 struct uart_8250_port *up = (struct uart_8250_port *)port;
2179 unsigned long flags;
2180
2181 /*
2182 * Disable interrupts from this port
2183 */
2184 up->ier = 0;
2185 serial_outp(up, UART_IER, 0);
2186
2187 spin_lock_irqsave(&up->port.lock, flags);
2188 if (up->port.flags & UPF_FOURPORT) {
2189 /* reset interrupts on the AST Fourport board */
2190 inb((up->port.iobase & 0xfe0) | 0x1f);
2191 up->port.mctrl |= TIOCM_OUT1;
2192 } else
2193 up->port.mctrl &= ~TIOCM_OUT2;
2194
2195 serial8250_set_mctrl(&up->port, up->port.mctrl);
2196 spin_unlock_irqrestore(&up->port.lock, flags);
2197
2198 /*
2199 * Disable break condition and FIFOs
2200 */
2201 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2202 serial8250_clear_fifos(up);
2203
2204#ifdef CONFIG_SERIAL_8250_RSA
2205 /*
2206 * Reset the RSA board back to 115kbps compat mode.
2207 */
2208 disable_rsa(up);
2209#endif
2210
2211 /*
2212 * Read data port to reset things, and then unlink from
2213 * the IRQ chain.
2214 */
2215 (void) serial_in(up, UART_RX);
2216
2217 del_timer_sync(&up->timer);
2218 up->timer.function = serial8250_timeout;
2219 if (is_real_interrupt(up->port.irq))
2220 serial_unlink_irq_chain(up);
2221}
2222
2223static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2224{
2225 unsigned int quot;
2226
2227 /*
2228 * Handle magic divisors for baud rates above baud_base on
2229 * SMSC SuperIO chips.
2230 */
2231 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2232 baud == (port->uartclk/4))
2233 quot = 0x8001;
2234 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2235 baud == (port->uartclk/8))
2236 quot = 0x8002;
2237 else
2238 quot = uart_get_divisor(port, baud);
2239
2240 return quot;
2241}
2242
2243void
2244serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2245 struct ktermios *old)
2246{
2247 struct uart_8250_port *up = (struct uart_8250_port *)port;
2248 unsigned char cval, fcr = 0;
2249 unsigned long flags;
2250 unsigned int baud, quot;
2251
2252 switch (termios->c_cflag & CSIZE) {
2253 case CS5:
2254 cval = UART_LCR_WLEN5;
2255 break;
2256 case CS6:
2257 cval = UART_LCR_WLEN6;
2258 break;
2259 case CS7:
2260 cval = UART_LCR_WLEN7;
2261 break;
2262 default:
2263 case CS8:
2264 cval = UART_LCR_WLEN8;
2265 break;
2266 }
2267
2268 if (termios->c_cflag & CSTOPB)
2269 cval |= UART_LCR_STOP;
2270 if (termios->c_cflag & PARENB)
2271 cval |= UART_LCR_PARITY;
2272 if (!(termios->c_cflag & PARODD))
2273 cval |= UART_LCR_EPAR;
2274#ifdef CMSPAR
2275 if (termios->c_cflag & CMSPAR)
2276 cval |= UART_LCR_SPAR;
2277#endif
2278
2279 /*
2280 * Ask the core to calculate the divisor for us.
2281 */
2282 baud = uart_get_baud_rate(port, termios, old,
2283 port->uartclk / 16 / 0xffff,
2284 port->uartclk / 16);
2285 quot = serial8250_get_divisor(port, baud);
2286
2287 /*
2288 * Oxford Semi 952 rev B workaround
2289 */
2290 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2291 quot++;
2292
2293 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2294 if (baud < 2400)
2295 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2296 else
2297 fcr = uart_config[up->port.type].fcr;
2298 }
2299
2300 /*
2301 * MCR-based auto flow control. When AFE is enabled, RTS will be
2302 * deasserted when the receive FIFO contains more characters than
2303 * the trigger, or the MCR RTS bit is cleared. In the case where
2304 * the remote UART is not using CTS auto flow control, we must
2305 * have sufficient FIFO entries for the latency of the remote
2306 * UART to respond. IOW, at least 32 bytes of FIFO.
2307 */
2308 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2309 up->mcr &= ~UART_MCR_AFE;
2310 if (termios->c_cflag & CRTSCTS)
2311 up->mcr |= UART_MCR_AFE;
2312 }
2313
2314 /*
2315 * Ok, we're now changing the port state. Do it with
2316 * interrupts disabled.
2317 */
2318 spin_lock_irqsave(&up->port.lock, flags);
2319
2320 /*
2321 * Update the per-port timeout.
2322 */
2323 uart_update_timeout(port, termios->c_cflag, baud);
2324
2325 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2326 if (termios->c_iflag & INPCK)
2327 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2328 if (termios->c_iflag & (BRKINT | PARMRK))
2329 up->port.read_status_mask |= UART_LSR_BI;
2330
2331 /*
2332 * Characteres to ignore
2333 */
2334 up->port.ignore_status_mask = 0;
2335 if (termios->c_iflag & IGNPAR)
2336 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2337 if (termios->c_iflag & IGNBRK) {
2338 up->port.ignore_status_mask |= UART_LSR_BI;
2339 /*
2340 * If we're ignoring parity and break indicators,
2341 * ignore overruns too (for real raw support).
2342 */
2343 if (termios->c_iflag & IGNPAR)
2344 up->port.ignore_status_mask |= UART_LSR_OE;
2345 }
2346
2347 /*
2348 * ignore all characters if CREAD is not set
2349 */
2350 if ((termios->c_cflag & CREAD) == 0)
2351 up->port.ignore_status_mask |= UART_LSR_DR;
2352
2353 /*
2354 * CTS flow control flag and modem status interrupts
2355 */
2356 up->ier &= ~UART_IER_MSI;
2357 if (!(up->bugs & UART_BUG_NOMSR) &&
2358 UART_ENABLE_MS(&up->port, termios->c_cflag))
2359 up->ier |= UART_IER_MSI;
2360 if (up->capabilities & UART_CAP_UUE)
2361 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
2362
2363 serial_out(up, UART_IER, up->ier);
2364
2365 if (up->capabilities & UART_CAP_EFR) {
2366 unsigned char efr = 0;
2367 /*
2368 * TI16C752/Startech hardware flow control. FIXME:
2369 * - TI16C752 requires control thresholds to be set.
2370 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2371 */
2372 if (termios->c_cflag & CRTSCTS)
2373 efr |= UART_EFR_CTS;
2374
2375 serial_outp(up, UART_LCR, 0xBF);
2376 serial_outp(up, UART_EFR, efr);
2377 }
2378
2379#ifdef CONFIG_ARCH_OMAP
2380 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2381 if (cpu_is_omap1510() && is_omap_port(up)) {
2382 if (baud == 115200) {
2383 quot = 1;
2384 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2385 } else
2386 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2387 }
2388#endif
2389
2390 if (up->capabilities & UART_NATSEMI) {
2391 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2392 serial_outp(up, UART_LCR, 0xe0);
2393 } else {
2394 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2395 }
2396
2397 serial_dl_write(up, quot);
2398
2399 /*
2400 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2401 * is written without DLAB set, this mode will be disabled.
2402 */
2403 if (up->port.type == PORT_16750)
2404 serial_outp(up, UART_FCR, fcr);
2405
2406 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2407 up->lcr = cval; /* Save LCR */
2408 if (up->port.type != PORT_16750) {
2409 if (fcr & UART_FCR_ENABLE_FIFO) {
2410 /* emulated UARTs (Lucent Venus 167x) need two steps */
2411 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2412 }
2413 serial_outp(up, UART_FCR, fcr); /* set fcr */
2414 }
2415 serial8250_set_mctrl(&up->port, up->port.mctrl);
2416 spin_unlock_irqrestore(&up->port.lock, flags);
2417 /* Don't rewrite B0 */
2418 if (tty_termios_baud_rate(termios))
2419 tty_termios_encode_baud_rate(termios, baud, baud);
2420}
2421EXPORT_SYMBOL(serial8250_do_set_termios);
2422
2423static void
2424serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2425 struct ktermios *old)
2426{
2427 if (port->set_termios)
2428 port->set_termios(port, termios, old);
2429 else
2430 serial8250_do_set_termios(port, termios, old);
2431}
2432
2433static void
2434serial8250_set_ldisc(struct uart_port *port, int new)
2435{
2436 if (new == N_PPS) {
2437 port->flags |= UPF_HARDPPS_CD;
2438 serial8250_enable_ms(port);
2439 } else
2440 port->flags &= ~UPF_HARDPPS_CD;
2441}
2442
2443static void
2444serial8250_pm(struct uart_port *port, unsigned int state,
2445 unsigned int oldstate)
2446{
2447 struct uart_8250_port *p = (struct uart_8250_port *)port;
2448
2449 serial8250_set_sleep(p, state != 0);
2450
2451 if (p->pm)
2452 p->pm(port, state, oldstate);
2453}
2454
2455static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2456{
2457 if (pt->port.iotype == UPIO_AU)
2458 return 0x1000;
2459#ifdef CONFIG_ARCH_OMAP
2460 if (is_omap_port(pt))
2461 return 0x16 << pt->port.regshift;
2462#endif
2463 return 8 << pt->port.regshift;
2464}
2465
2466/*
2467 * Resource handling.
2468 */
2469static int serial8250_request_std_resource(struct uart_8250_port *up)
2470{
2471 unsigned int size = serial8250_port_size(up);
2472 int ret = 0;
2473
2474 switch (up->port.iotype) {
2475 case UPIO_AU:
2476 case UPIO_TSI:
2477 case UPIO_MEM32:
2478 case UPIO_MEM:
2479 case UPIO_DWAPB:
2480 if (!up->port.mapbase)
2481 break;
2482
2483 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2484 ret = -EBUSY;
2485 break;
2486 }
2487
2488 if (up->port.flags & UPF_IOREMAP) {
2489 up->port.membase = ioremap_nocache(up->port.mapbase,
2490 size);
2491 if (!up->port.membase) {
2492 release_mem_region(up->port.mapbase, size);
2493 ret = -ENOMEM;
2494 }
2495 }
2496 break;
2497
2498 case UPIO_HUB6:
2499 case UPIO_PORT:
2500 if (!request_region(up->port.iobase, size, "serial"))
2501 ret = -EBUSY;
2502 break;
2503 }
2504 return ret;
2505}
2506
2507static void serial8250_release_std_resource(struct uart_8250_port *up)
2508{
2509 unsigned int size = serial8250_port_size(up);
2510
2511 switch (up->port.iotype) {
2512 case UPIO_AU:
2513 case UPIO_TSI:
2514 case UPIO_MEM32:
2515 case UPIO_MEM:
2516 case UPIO_DWAPB:
2517 if (!up->port.mapbase)
2518 break;
2519
2520 if (up->port.flags & UPF_IOREMAP) {
2521 iounmap(up->port.membase);
2522 up->port.membase = NULL;
2523 }
2524
2525 release_mem_region(up->port.mapbase, size);
2526 break;
2527
2528 case UPIO_HUB6:
2529 case UPIO_PORT:
2530 release_region(up->port.iobase, size);
2531 break;
2532 }
2533}
2534
2535static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2536{
2537 unsigned long start = UART_RSA_BASE << up->port.regshift;
2538 unsigned int size = 8 << up->port.regshift;
2539 int ret = -EINVAL;
2540
2541 switch (up->port.iotype) {
2542 case UPIO_HUB6:
2543 case UPIO_PORT:
2544 start += up->port.iobase;
2545 if (request_region(start, size, "serial-rsa"))
2546 ret = 0;
2547 else
2548 ret = -EBUSY;
2549 break;
2550 }
2551
2552 return ret;
2553}
2554
2555static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2556{
2557 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2558 unsigned int size = 8 << up->port.regshift;
2559
2560 switch (up->port.iotype) {
2561 case UPIO_HUB6:
2562 case UPIO_PORT:
2563 release_region(up->port.iobase + offset, size);
2564 break;
2565 }
2566}
2567
2568static void serial8250_release_port(struct uart_port *port)
2569{
2570 struct uart_8250_port *up = (struct uart_8250_port *)port;
2571
2572 serial8250_release_std_resource(up);
2573 if (up->port.type == PORT_RSA)
2574 serial8250_release_rsa_resource(up);
2575}
2576
2577static int serial8250_request_port(struct uart_port *port)
2578{
2579 struct uart_8250_port *up = (struct uart_8250_port *)port;
2580 int ret = 0;
2581
2582 ret = serial8250_request_std_resource(up);
2583 if (ret == 0 && up->port.type == PORT_RSA) {
2584 ret = serial8250_request_rsa_resource(up);
2585 if (ret < 0)
2586 serial8250_release_std_resource(up);
2587 }
2588
2589 return ret;
2590}
2591
2592static void serial8250_config_port(struct uart_port *port, int flags)
2593{
2594 struct uart_8250_port *up = (struct uart_8250_port *)port;
2595 int probeflags = PROBE_ANY;
2596 int ret;
2597
2598 /*
2599 * Find the region that we can probe for. This in turn
2600 * tells us whether we can probe for the type of port.
2601 */
2602 ret = serial8250_request_std_resource(up);
2603 if (ret < 0)
2604 return;
2605
2606 ret = serial8250_request_rsa_resource(up);
2607 if (ret < 0)
2608 probeflags &= ~PROBE_RSA;
2609
2610 if (up->port.iotype != up->cur_iotype)
2611 set_io_from_upio(port);
2612
2613 if (flags & UART_CONFIG_TYPE)
2614 autoconfig(up, probeflags);
2615
2616 /* if access method is AU, it is a 16550 with a quirk */
2617 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
2618 up->bugs |= UART_BUG_NOMSR;
2619
2620 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2621 autoconfig_irq(up);
2622
2623 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2624 serial8250_release_rsa_resource(up);
2625 if (up->port.type == PORT_UNKNOWN)
2626 serial8250_release_std_resource(up);
2627}
2628
2629static int
2630serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2631{
2632 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2633 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2634 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2635 ser->type == PORT_STARTECH)
2636 return -EINVAL;
2637 return 0;
2638}
2639
2640static const char *
2641serial8250_type(struct uart_port *port)
2642{
2643 int type = port->type;
2644
2645 if (type >= ARRAY_SIZE(uart_config))
2646 type = 0;
2647 return uart_config[type].name;
2648}
2649
2650static struct uart_ops serial8250_pops = {
2651 .tx_empty = serial8250_tx_empty,
2652 .set_mctrl = serial8250_set_mctrl,
2653 .get_mctrl = serial8250_get_mctrl,
2654 .stop_tx = serial8250_stop_tx,
2655 .start_tx = serial8250_start_tx,
2656 .stop_rx = serial8250_stop_rx,
2657 .enable_ms = serial8250_enable_ms,
2658 .break_ctl = serial8250_break_ctl,
2659 .startup = serial8250_startup,
2660 .shutdown = serial8250_shutdown,
2661 .set_termios = serial8250_set_termios,
2662 .set_ldisc = serial8250_set_ldisc,
2663 .pm = serial8250_pm,
2664 .type = serial8250_type,
2665 .release_port = serial8250_release_port,
2666 .request_port = serial8250_request_port,
2667 .config_port = serial8250_config_port,
2668 .verify_port = serial8250_verify_port,
2669#ifdef CONFIG_CONSOLE_POLL
2670 .poll_get_char = serial8250_get_poll_char,
2671 .poll_put_char = serial8250_put_poll_char,
2672#endif
2673};
2674
2675static struct uart_8250_port serial8250_ports[UART_NR];
2676
2677static void __init serial8250_isa_init_ports(void)
2678{
2679 struct uart_8250_port *up;
2680 static int first = 1;
2681 int i, irqflag = 0;
2682
2683 if (!first)
2684 return;
2685 first = 0;
2686
2687 for (i = 0; i < nr_uarts; i++) {
2688 struct uart_8250_port *up = &serial8250_ports[i];
2689
2690 up->port.line = i;
2691 spin_lock_init(&up->port.lock);
2692
2693 init_timer(&up->timer);
2694 up->timer.function = serial8250_timeout;
2695
2696 /*
2697 * ALPHA_KLUDGE_MCR needs to be killed.
2698 */
2699 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2700 up->mcr_force = ALPHA_KLUDGE_MCR;
2701
2702 up->port.ops = &serial8250_pops;
2703 }
2704
2705 if (share_irqs)
2706 irqflag = IRQF_SHARED;
2707
2708 for (i = 0, up = serial8250_ports;
2709 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2710 i++, up++) {
2711 up->port.iobase = old_serial_port[i].port;
2712 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2713 up->port.irqflags = old_serial_port[i].irqflags;
2714 up->port.uartclk = old_serial_port[i].baud_base * 16;
2715 up->port.flags = old_serial_port[i].flags;
2716 up->port.hub6 = old_serial_port[i].hub6;
2717 up->port.membase = old_serial_port[i].iomem_base;
2718 up->port.iotype = old_serial_port[i].io_type;
2719 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2720 set_io_from_upio(&up->port);
2721 up->port.irqflags |= irqflag;
2722 }
2723}
2724
2725static void
2726serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2727{
2728 up->port.type = type;
2729 up->port.fifosize = uart_config[type].fifo_size;
2730 up->capabilities = uart_config[type].flags;
2731 up->tx_loadsz = uart_config[type].tx_loadsz;
2732}
2733
2734static void __init
2735serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2736{
2737 int i;
2738
2739 for (i = 0; i < nr_uarts; i++) {
2740 struct uart_8250_port *up = &serial8250_ports[i];
2741 up->cur_iotype = 0xFF;
2742 }
2743
2744 serial8250_isa_init_ports();
2745
2746 for (i = 0; i < nr_uarts; i++) {
2747 struct uart_8250_port *up = &serial8250_ports[i];
2748
2749 up->port.dev = dev;
2750
2751 if (up->port.flags & UPF_FIXED_TYPE)
2752 serial8250_init_fixed_type_port(up, up->port.type);
2753
2754 uart_add_one_port(drv, &up->port);
2755 }
2756}
2757
2758#ifdef CONFIG_SERIAL_8250_CONSOLE
2759
2760static void serial8250_console_putchar(struct uart_port *port, int ch)
2761{
2762 struct uart_8250_port *up = (struct uart_8250_port *)port;
2763
2764 wait_for_xmitr(up, UART_LSR_THRE);
2765 serial_out(up, UART_TX, ch);
2766}
2767
2768/*
2769 * Print a string to the serial port trying not to disturb
2770 * any possible real use of the port...
2771 *
2772 * The console_lock must be held when we get here.
2773 */
2774static void
2775serial8250_console_write(struct console *co, const char *s, unsigned int count)
2776{
2777 struct uart_8250_port *up = &serial8250_ports[co->index];
2778 unsigned long flags;
2779 unsigned int ier;
2780 int locked = 1;
2781
2782 touch_nmi_watchdog();
2783
2784 local_irq_save(flags);
2785 if (up->port.sysrq) {
2786 /* serial8250_handle_port() already took the lock */
2787 locked = 0;
2788 } else if (oops_in_progress) {
2789 locked = spin_trylock(&up->port.lock);
2790 } else
2791 spin_lock(&up->port.lock);
2792
2793 /*
2794 * First save the IER then disable the interrupts
2795 */
2796 ier = serial_in(up, UART_IER);
2797
2798 if (up->capabilities & UART_CAP_UUE)
2799 serial_out(up, UART_IER, UART_IER_UUE);
2800 else
2801 serial_out(up, UART_IER, 0);
2802
2803 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2804
2805 /*
2806 * Finally, wait for transmitter to become empty
2807 * and restore the IER
2808 */
2809 wait_for_xmitr(up, BOTH_EMPTY);
2810 serial_out(up, UART_IER, ier);
2811
2812 /*
2813 * The receive handling will happen properly because the
2814 * receive ready bit will still be set; it is not cleared
2815 * on read. However, modem control will not, we must
2816 * call it if we have saved something in the saved flags
2817 * while processing with interrupts off.
2818 */
2819 if (up->msr_saved_flags)
2820 check_modem_status(up);
2821
2822 if (locked)
2823 spin_unlock(&up->port.lock);
2824 local_irq_restore(flags);
2825}
2826
2827static int __init serial8250_console_setup(struct console *co, char *options)
2828{
2829 struct uart_port *port;
2830 int baud = 9600;
2831 int bits = 8;
2832 int parity = 'n';
2833 int flow = 'n';
2834
2835 /*
2836 * Check whether an invalid uart number has been specified, and
2837 * if so, search for the first available port that does have
2838 * console support.
2839 */
2840 if (co->index >= nr_uarts)
2841 co->index = 0;
2842 port = &serial8250_ports[co->index].port;
2843 if (!port->iobase && !port->membase)
2844 return -ENODEV;
2845
2846 if (options)
2847 uart_parse_options(options, &baud, &parity, &bits, &flow);
2848
2849 return uart_set_options(port, co, baud, parity, bits, flow);
2850}
2851
2852static int serial8250_console_early_setup(void)
2853{
2854 return serial8250_find_port_for_earlycon();
2855}
2856
2857static struct console serial8250_console = {
2858 .name = "ttyS",
2859 .write = serial8250_console_write,
2860 .device = uart_console_device,
2861 .setup = serial8250_console_setup,
2862 .early_setup = serial8250_console_early_setup,
2863 .flags = CON_PRINTBUFFER,
2864 .index = -1,
2865 .data = &serial8250_reg,
2866};
2867
2868static int __init serial8250_console_init(void)
2869{
2870 if (nr_uarts > UART_NR)
2871 nr_uarts = UART_NR;
2872
2873 serial8250_isa_init_ports();
2874 register_console(&serial8250_console);
2875 return 0;
2876}
2877console_initcall(serial8250_console_init);
2878
2879int serial8250_find_port(struct uart_port *p)
2880{
2881 int line;
2882 struct uart_port *port;
2883
2884 for (line = 0; line < nr_uarts; line++) {
2885 port = &serial8250_ports[line].port;
2886 if (uart_match_port(p, port))
2887 return line;
2888 }
2889 return -ENODEV;
2890}
2891
2892#define SERIAL8250_CONSOLE &serial8250_console
2893#else
2894#define SERIAL8250_CONSOLE NULL
2895#endif
2896
2897static struct uart_driver serial8250_reg = {
2898 .owner = THIS_MODULE,
2899 .driver_name = "serial",
2900 .dev_name = "ttyS",
2901 .major = TTY_MAJOR,
2902 .minor = 64,
2903 .cons = SERIAL8250_CONSOLE,
2904};
2905
2906/*
2907 * early_serial_setup - early registration for 8250 ports
2908 *
2909 * Setup an 8250 port structure prior to console initialisation. Use
2910 * after console initialisation will cause undefined behaviour.
2911 */
2912int __init early_serial_setup(struct uart_port *port)
2913{
2914 struct uart_port *p;
2915
2916 if (port->line >= ARRAY_SIZE(serial8250_ports))
2917 return -ENODEV;
2918
2919 serial8250_isa_init_ports();
2920 p = &serial8250_ports[port->line].port;
2921 p->iobase = port->iobase;
2922 p->membase = port->membase;
2923 p->irq = port->irq;
2924 p->irqflags = port->irqflags;
2925 p->uartclk = port->uartclk;
2926 p->fifosize = port->fifosize;
2927 p->regshift = port->regshift;
2928 p->iotype = port->iotype;
2929 p->flags = port->flags;
2930 p->mapbase = port->mapbase;
2931 p->private_data = port->private_data;
2932 p->type = port->type;
2933 p->line = port->line;
2934
2935 set_io_from_upio(p);
2936 if (port->serial_in)
2937 p->serial_in = port->serial_in;
2938 if (port->serial_out)
2939 p->serial_out = port->serial_out;
2940
2941 return 0;
2942}
2943
2944/**
2945 * serial8250_suspend_port - suspend one serial port
2946 * @line: serial line number
2947 *
2948 * Suspend one serial port.
2949 */
2950void serial8250_suspend_port(int line)
2951{
2952 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2953}
2954
2955/**
2956 * serial8250_resume_port - resume one serial port
2957 * @line: serial line number
2958 *
2959 * Resume one serial port.
2960 */
2961void serial8250_resume_port(int line)
2962{
2963 struct uart_8250_port *up = &serial8250_ports[line];
2964
2965 if (up->capabilities & UART_NATSEMI) {
2966 unsigned char tmp;
2967
2968 /* Ensure it's still in high speed mode */
2969 serial_outp(up, UART_LCR, 0xE0);
2970
2971 tmp = serial_in(up, 0x04); /* EXCR2 */
2972 tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
2973 tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
2974 serial_outp(up, 0x04, tmp);
2975
2976 serial_outp(up, UART_LCR, 0);
2977 }
2978 uart_resume_port(&serial8250_reg, &up->port);
2979}
2980
2981/*
2982 * Register a set of serial devices attached to a platform device. The
2983 * list is terminated with a zero flags entry, which means we expect
2984 * all entries to have at least UPF_BOOT_AUTOCONF set.
2985 */
2986static int __devinit serial8250_probe(struct platform_device *dev)
2987{
2988 struct plat_serial8250_port *p = dev->dev.platform_data;
2989 struct uart_port port;
2990 int ret, i, irqflag = 0;
2991
2992 memset(&port, 0, sizeof(struct uart_port));
2993
2994 if (share_irqs)
2995 irqflag = IRQF_SHARED;
2996
2997 for (i = 0; p && p->flags != 0; p++, i++) {
2998 port.iobase = p->iobase;
2999 port.membase = p->membase;
3000 port.irq = p->irq;
3001 port.irqflags = p->irqflags;
3002 port.uartclk = p->uartclk;
3003 port.regshift = p->regshift;
3004 port.iotype = p->iotype;
3005 port.flags = p->flags;
3006 port.mapbase = p->mapbase;
3007 port.hub6 = p->hub6;
3008 port.private_data = p->private_data;
3009 port.type = p->type;
3010 port.serial_in = p->serial_in;
3011 port.serial_out = p->serial_out;
3012 port.set_termios = p->set_termios;
3013 port.dev = &dev->dev;
3014 port.irqflags |= irqflag;
3015 ret = serial8250_register_port(&port);
3016 if (ret < 0) {
3017 dev_err(&dev->dev, "unable to register port at index %d "
3018 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3019 p->iobase, (unsigned long long)p->mapbase,
3020 p->irq, ret);
3021 }
3022 }
3023 return 0;
3024}
3025
3026/*
3027 * Remove serial ports registered against a platform device.
3028 */
3029static int __devexit serial8250_remove(struct platform_device *dev)
3030{
3031 int i;
3032
3033 for (i = 0; i < nr_uarts; i++) {
3034 struct uart_8250_port *up = &serial8250_ports[i];
3035
3036 if (up->port.dev == &dev->dev)
3037 serial8250_unregister_port(i);
3038 }
3039 return 0;
3040}
3041
3042static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3043{
3044 int i;
3045
3046 for (i = 0; i < UART_NR; i++) {
3047 struct uart_8250_port *up = &serial8250_ports[i];
3048
3049 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3050 uart_suspend_port(&serial8250_reg, &up->port);
3051 }
3052
3053 return 0;
3054}
3055
3056static int serial8250_resume(struct platform_device *dev)
3057{
3058 int i;
3059
3060 for (i = 0; i < UART_NR; i++) {
3061 struct uart_8250_port *up = &serial8250_ports[i];
3062
3063 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3064 serial8250_resume_port(i);
3065 }
3066
3067 return 0;
3068}
3069
3070static struct platform_driver serial8250_isa_driver = {
3071 .probe = serial8250_probe,
3072 .remove = __devexit_p(serial8250_remove),
3073 .suspend = serial8250_suspend,
3074 .resume = serial8250_resume,
3075 .driver = {
3076 .name = "serial8250",
3077 .owner = THIS_MODULE,
3078 },
3079};
3080
3081/*
3082 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3083 * in the table in include/asm/serial.h
3084 */
3085static struct platform_device *serial8250_isa_devs;
3086
3087/*
3088 * serial8250_register_port and serial8250_unregister_port allows for
3089 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3090 * modems and PCI multiport cards.
3091 */
3092static DEFINE_MUTEX(serial_mutex);
3093
3094static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3095{
3096 int i;
3097
3098 /*
3099 * First, find a port entry which matches.
3100 */
3101 for (i = 0; i < nr_uarts; i++)
3102 if (uart_match_port(&serial8250_ports[i].port, port))
3103 return &serial8250_ports[i];
3104
3105 /*
3106 * We didn't find a matching entry, so look for the first
3107 * free entry. We look for one which hasn't been previously
3108 * used (indicated by zero iobase).
3109 */
3110 for (i = 0; i < nr_uarts; i++)
3111 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3112 serial8250_ports[i].port.iobase == 0)
3113 return &serial8250_ports[i];
3114
3115 /*
3116 * That also failed. Last resort is to find any entry which
3117 * doesn't have a real port associated with it.
3118 */
3119 for (i = 0; i < nr_uarts; i++)
3120 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3121 return &serial8250_ports[i];
3122
3123 return NULL;
3124}
3125
3126/**
3127 * serial8250_register_port - register a serial port
3128 * @port: serial port template
3129 *
3130 * Configure the serial port specified by the request. If the
3131 * port exists and is in use, it is hung up and unregistered
3132 * first.
3133 *
3134 * The port is then probed and if necessary the IRQ is autodetected
3135 * If this fails an error is returned.
3136 *
3137 * On success the port is ready to use and the line number is returned.
3138 */
3139int serial8250_register_port(struct uart_port *port)
3140{
3141 struct uart_8250_port *uart;
3142 int ret = -ENOSPC;
3143
3144 if (port->uartclk == 0)
3145 return -EINVAL;
3146
3147 mutex_lock(&serial_mutex);
3148
3149 uart = serial8250_find_match_or_unused(port);
3150 if (uart) {
3151 uart_remove_one_port(&serial8250_reg, &uart->port);
3152
3153 uart->port.iobase = port->iobase;
3154 uart->port.membase = port->membase;
3155 uart->port.irq = port->irq;
3156 uart->port.irqflags = port->irqflags;
3157 uart->port.uartclk = port->uartclk;
3158 uart->port.fifosize = port->fifosize;
3159 uart->port.regshift = port->regshift;
3160 uart->port.iotype = port->iotype;
3161 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3162 uart->port.mapbase = port->mapbase;
3163 uart->port.private_data = port->private_data;
3164 if (port->dev)
3165 uart->port.dev = port->dev;
3166
3167 if (port->flags & UPF_FIXED_TYPE)
3168 serial8250_init_fixed_type_port(uart, port->type);
3169
3170 set_io_from_upio(&uart->port);
3171 /* Possibly override default I/O functions. */
3172 if (port->serial_in)
3173 uart->port.serial_in = port->serial_in;
3174 if (port->serial_out)
3175 uart->port.serial_out = port->serial_out;
3176 /* Possibly override set_termios call */
3177 if (port->set_termios)
3178 uart->port.set_termios = port->set_termios;
3179
3180 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3181 if (ret == 0)
3182 ret = uart->port.line;
3183 }
3184 mutex_unlock(&serial_mutex);
3185
3186 return ret;
3187}
3188EXPORT_SYMBOL(serial8250_register_port);
3189
3190/**
3191 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3192 * @line: serial line number
3193 *
3194 * Remove one serial port. This may not be called from interrupt
3195 * context. We hand the port back to the our control.
3196 */
3197void serial8250_unregister_port(int line)
3198{
3199 struct uart_8250_port *uart = &serial8250_ports[line];
3200
3201 mutex_lock(&serial_mutex);
3202 uart_remove_one_port(&serial8250_reg, &uart->port);
3203 if (serial8250_isa_devs) {
3204 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3205 uart->port.type = PORT_UNKNOWN;
3206 uart->port.dev = &serial8250_isa_devs->dev;
3207 uart_add_one_port(&serial8250_reg, &uart->port);
3208 } else {
3209 uart->port.dev = NULL;
3210 }
3211 mutex_unlock(&serial_mutex);
3212}
3213EXPORT_SYMBOL(serial8250_unregister_port);
3214
3215static int __init serial8250_init(void)
3216{
3217 int ret;
3218
3219 if (nr_uarts > UART_NR)
3220 nr_uarts = UART_NR;
3221
3222 printk(KERN_INFO "Serial: 8250/16550 driver, "
3223 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3224 share_irqs ? "en" : "dis");
3225
3226#ifdef CONFIG_SPARC
3227 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3228#else
3229 serial8250_reg.nr = UART_NR;
3230 ret = uart_register_driver(&serial8250_reg);
3231#endif
3232 if (ret)
3233 goto out;
3234
3235 serial8250_isa_devs = platform_device_alloc("serial8250",
3236 PLAT8250_DEV_LEGACY);
3237 if (!serial8250_isa_devs) {
3238 ret = -ENOMEM;
3239 goto unreg_uart_drv;
3240 }
3241
3242 ret = platform_device_add(serial8250_isa_devs);
3243 if (ret)
3244 goto put_dev;
3245
3246 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3247
3248 ret = platform_driver_register(&serial8250_isa_driver);
3249 if (ret == 0)
3250 goto out;
3251
3252 platform_device_del(serial8250_isa_devs);
3253put_dev:
3254 platform_device_put(serial8250_isa_devs);
3255unreg_uart_drv:
3256#ifdef CONFIG_SPARC
3257 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3258#else
3259 uart_unregister_driver(&serial8250_reg);
3260#endif
3261out:
3262 return ret;
3263}
3264
3265static void __exit serial8250_exit(void)
3266{
3267 struct platform_device *isa_dev = serial8250_isa_devs;
3268
3269 /*
3270 * This tells serial8250_unregister_port() not to re-register
3271 * the ports (thereby making serial8250_isa_driver permanently
3272 * in use.)
3273 */
3274 serial8250_isa_devs = NULL;
3275
3276 platform_driver_unregister(&serial8250_isa_driver);
3277 platform_device_unregister(isa_dev);
3278
3279#ifdef CONFIG_SPARC
3280 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3281#else
3282 uart_unregister_driver(&serial8250_reg);
3283#endif
3284}
3285
3286module_init(serial8250_init);
3287module_exit(serial8250_exit);
3288
3289EXPORT_SYMBOL(serial8250_suspend_port);
3290EXPORT_SYMBOL(serial8250_resume_port);
3291
3292MODULE_LICENSE("GPL");
3293MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3294
3295module_param(share_irqs, uint, 0644);
3296MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3297 " (unsafe)");
3298
3299module_param(nr_uarts, uint, 0644);
3300MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3301
3302module_param(skip_txen_test, uint, 0644);
3303MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3304
3305#ifdef CONFIG_SERIAL_8250_RSA
3306module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3307MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3308#endif
3309MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
diff --git a/drivers/serial/8250.h b/drivers/serial/8250.h
deleted file mode 100644
index 6e19ea3e48d5..000000000000
--- a/drivers/serial/8250.h
+++ /dev/null
@@ -1,80 +0,0 @@
1/*
2 * linux/drivers/char/8250.h
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#include <linux/serial_8250.h>
17
18struct old_serial_port {
19 unsigned int uart;
20 unsigned int baud_base;
21 unsigned int port;
22 unsigned int irq;
23 unsigned int flags;
24 unsigned char hub6;
25 unsigned char io_type;
26 unsigned char *iomem_base;
27 unsigned short iomem_reg_shift;
28 unsigned long irqflags;
29};
30
31/*
32 * This replaces serial_uart_config in include/linux/serial.h
33 */
34struct serial8250_config {
35 const char *name;
36 unsigned short fifo_size;
37 unsigned short tx_loadsz;
38 unsigned char fcr;
39 unsigned int flags;
40};
41
42#define UART_CAP_FIFO (1 << 8) /* UART has FIFO */
43#define UART_CAP_EFR (1 << 9) /* UART has EFR */
44#define UART_CAP_SLEEP (1 << 10) /* UART has IER sleep */
45#define UART_CAP_AFE (1 << 11) /* MCR-based hw flow control */
46#define UART_CAP_UUE (1 << 12) /* UART needs IER bit 6 set (Xscale) */
47
48#define UART_BUG_QUOT (1 << 0) /* UART has buggy quot LSB */
49#define UART_BUG_TXEN (1 << 1) /* UART has buggy TX IIR status */
50#define UART_BUG_NOMSR (1 << 2) /* UART has buggy MSR status bits (Au1x00) */
51#define UART_BUG_THRE (1 << 3) /* UART has buggy THRE reassertion */
52
53#define PROBE_RSA (1 << 0)
54#define PROBE_ANY (~0)
55
56#define HIGH_BITS_OFFSET ((sizeof(long)-sizeof(int))*8)
57
58#ifdef CONFIG_SERIAL_8250_SHARE_IRQ
59#define SERIAL8250_SHARE_IRQS 1
60#else
61#define SERIAL8250_SHARE_IRQS 0
62#endif
63
64#if defined(__alpha__) && !defined(CONFIG_PCI)
65/*
66 * Digital did something really horribly wrong with the OUT1 and OUT2
67 * lines on at least some ALPHA's. The failure mode is that if either
68 * is cleared, the machine locks up with endless interrupts.
69 */
70#define ALPHA_KLUDGE_MCR (UART_MCR_OUT2 | UART_MCR_OUT1)
71#elif defined(CONFIG_SBC8560)
72/*
73 * WindRiver did something similarly broken on their SBC8560 board. The
74 * UART tristates its IRQ output while OUT2 is clear, but they pulled
75 * the interrupt line _up_ instead of down, so if we register the IRQ
76 * while the UART is in that state, we die in an IRQ storm. */
77#define ALPHA_KLUDGE_MCR (UART_MCR_OUT2)
78#else
79#define ALPHA_KLUDGE_MCR 0
80#endif
diff --git a/drivers/serial/8250_accent.c b/drivers/serial/8250_accent.c
deleted file mode 100644
index 9c10262f2469..000000000000
--- a/drivers/serial/8250_accent.c
+++ /dev/null
@@ -1,47 +0,0 @@
1/*
2 * linux/drivers/serial/8250_accent.c
3 *
4 * Copyright (C) 2005 Russell King.
5 * Data taken from include/asm-i386/serial.h
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/module.h>
12#include <linux/init.h>
13#include <linux/serial_8250.h>
14
15#define PORT(_base,_irq) \
16 { \
17 .iobase = _base, \
18 .irq = _irq, \
19 .uartclk = 1843200, \
20 .iotype = UPIO_PORT, \
21 .flags = UPF_BOOT_AUTOCONF, \
22 }
23
24static struct plat_serial8250_port accent_data[] = {
25 PORT(0x330, 4),
26 PORT(0x338, 4),
27 { },
28};
29
30static struct platform_device accent_device = {
31 .name = "serial8250",
32 .id = PLAT8250_DEV_ACCENT,
33 .dev = {
34 .platform_data = accent_data,
35 },
36};
37
38static int __init accent_init(void)
39{
40 return platform_device_register(&accent_device);
41}
42
43module_init(accent_init);
44
45MODULE_AUTHOR("Russell King");
46MODULE_DESCRIPTION("8250 serial probe module for Accent Async cards");
47MODULE_LICENSE("GPL");
diff --git a/drivers/serial/8250_acorn.c b/drivers/serial/8250_acorn.c
deleted file mode 100644
index b0ce8c56f1a4..000000000000
--- a/drivers/serial/8250_acorn.c
+++ /dev/null
@@ -1,141 +0,0 @@
1/*
2 * linux/drivers/serial/acorn.c
3 *
4 * Copyright (C) 1996-2003 Russell King.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/module.h>
11#include <linux/types.h>
12#include <linux/tty.h>
13#include <linux/serial_core.h>
14#include <linux/errno.h>
15#include <linux/ioport.h>
16#include <linux/slab.h>
17#include <linux/device.h>
18#include <linux/init.h>
19
20#include <asm/io.h>
21#include <asm/ecard.h>
22#include <asm/string.h>
23
24#include "8250.h"
25
26#define MAX_PORTS 3
27
28struct serial_card_type {
29 unsigned int num_ports;
30 unsigned int uartclk;
31 unsigned int type;
32 unsigned int offset[MAX_PORTS];
33};
34
35struct serial_card_info {
36 unsigned int num_ports;
37 int ports[MAX_PORTS];
38 void __iomem *vaddr;
39};
40
41static int __devinit
42serial_card_probe(struct expansion_card *ec, const struct ecard_id *id)
43{
44 struct serial_card_info *info;
45 struct serial_card_type *type = id->data;
46 struct uart_port port;
47 unsigned long bus_addr;
48 unsigned int i;
49
50 info = kzalloc(sizeof(struct serial_card_info), GFP_KERNEL);
51 if (!info)
52 return -ENOMEM;
53
54 info->num_ports = type->num_ports;
55
56 bus_addr = ecard_resource_start(ec, type->type);
57 info->vaddr = ecardm_iomap(ec, type->type, 0, 0);
58 if (!info->vaddr) {
59 kfree(info);
60 return -ENOMEM;
61 }
62
63 ecard_set_drvdata(ec, info);
64
65 memset(&port, 0, sizeof(struct uart_port));
66 port.irq = ec->irq;
67 port.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
68 port.uartclk = type->uartclk;
69 port.iotype = UPIO_MEM;
70 port.regshift = 2;
71 port.dev = &ec->dev;
72
73 for (i = 0; i < info->num_ports; i ++) {
74 port.membase = info->vaddr + type->offset[i];
75 port.mapbase = bus_addr + type->offset[i];
76
77 info->ports[i] = serial8250_register_port(&port);
78 }
79
80 return 0;
81}
82
83static void __devexit serial_card_remove(struct expansion_card *ec)
84{
85 struct serial_card_info *info = ecard_get_drvdata(ec);
86 int i;
87
88 ecard_set_drvdata(ec, NULL);
89
90 for (i = 0; i < info->num_ports; i++)
91 if (info->ports[i] > 0)
92 serial8250_unregister_port(info->ports[i]);
93
94 kfree(info);
95}
96
97static struct serial_card_type atomwide_type = {
98 .num_ports = 3,
99 .uartclk = 7372800,
100 .type = ECARD_RES_IOCSLOW,
101 .offset = { 0x2800, 0x2400, 0x2000 },
102};
103
104static struct serial_card_type serport_type = {
105 .num_ports = 2,
106 .uartclk = 3686400,
107 .type = ECARD_RES_IOCSLOW,
108 .offset = { 0x2000, 0x2020 },
109};
110
111static const struct ecard_id serial_cids[] = {
112 { MANU_ATOMWIDE, PROD_ATOMWIDE_3PSERIAL, &atomwide_type },
113 { MANU_SERPORT, PROD_SERPORT_DSPORT, &serport_type },
114 { 0xffff, 0xffff }
115};
116
117static struct ecard_driver serial_card_driver = {
118 .probe = serial_card_probe,
119 .remove = __devexit_p(serial_card_remove),
120 .id_table = serial_cids,
121 .drv = {
122 .name = "8250_acorn",
123 },
124};
125
126static int __init serial_card_init(void)
127{
128 return ecard_register_driver(&serial_card_driver);
129}
130
131static void __exit serial_card_exit(void)
132{
133 ecard_remove_driver(&serial_card_driver);
134}
135
136MODULE_AUTHOR("Russell King");
137MODULE_DESCRIPTION("Acorn 8250-compatible serial port expansion card driver");
138MODULE_LICENSE("GPL");
139
140module_init(serial_card_init);
141module_exit(serial_card_exit);
diff --git a/drivers/serial/8250_boca.c b/drivers/serial/8250_boca.c
deleted file mode 100644
index 3bfe0f7b26fb..000000000000
--- a/drivers/serial/8250_boca.c
+++ /dev/null
@@ -1,61 +0,0 @@
1/*
2 * linux/drivers/serial/8250_boca.c
3 *
4 * Copyright (C) 2005 Russell King.
5 * Data taken from include/asm-i386/serial.h
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/module.h>
12#include <linux/init.h>
13#include <linux/serial_8250.h>
14
15#define PORT(_base,_irq) \
16 { \
17 .iobase = _base, \
18 .irq = _irq, \
19 .uartclk = 1843200, \
20 .iotype = UPIO_PORT, \
21 .flags = UPF_BOOT_AUTOCONF, \
22 }
23
24static struct plat_serial8250_port boca_data[] = {
25 PORT(0x100, 12),
26 PORT(0x108, 12),
27 PORT(0x110, 12),
28 PORT(0x118, 12),
29 PORT(0x120, 12),
30 PORT(0x128, 12),
31 PORT(0x130, 12),
32 PORT(0x138, 12),
33 PORT(0x140, 12),
34 PORT(0x148, 12),
35 PORT(0x150, 12),
36 PORT(0x158, 12),
37 PORT(0x160, 12),
38 PORT(0x168, 12),
39 PORT(0x170, 12),
40 PORT(0x178, 12),
41 { },
42};
43
44static struct platform_device boca_device = {
45 .name = "serial8250",
46 .id = PLAT8250_DEV_BOCA,
47 .dev = {
48 .platform_data = boca_data,
49 },
50};
51
52static int __init boca_init(void)
53{
54 return platform_device_register(&boca_device);
55}
56
57module_init(boca_init);
58
59MODULE_AUTHOR("Russell King");
60MODULE_DESCRIPTION("8250 serial probe module for Boca cards");
61MODULE_LICENSE("GPL");
diff --git a/drivers/serial/8250_early.c b/drivers/serial/8250_early.c
deleted file mode 100644
index eaafb98debed..000000000000
--- a/drivers/serial/8250_early.c
+++ /dev/null
@@ -1,287 +0,0 @@
1/*
2 * Early serial console for 8250/16550 devices
3 *
4 * (c) Copyright 2004 Hewlett-Packard Development Company, L.P.
5 * Bjorn Helgaas <bjorn.helgaas@hp.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Based on the 8250.c serial driver, Copyright (C) 2001 Russell King,
12 * and on early_printk.c by Andi Kleen.
13 *
14 * This is for use before the serial driver has initialized, in
15 * particular, before the UARTs have been discovered and named.
16 * Instead of specifying the console device as, e.g., "ttyS0",
17 * we locate the device directly by its MMIO or I/O port address.
18 *
19 * The user can specify the device directly, e.g.,
20 * earlycon=uart8250,io,0x3f8,9600n8
21 * earlycon=uart8250,mmio,0xff5e0000,115200n8
22 * earlycon=uart8250,mmio32,0xff5e0000,115200n8
23 * or
24 * console=uart8250,io,0x3f8,9600n8
25 * console=uart8250,mmio,0xff5e0000,115200n8
26 * console=uart8250,mmio32,0xff5e0000,115200n8
27 */
28
29#include <linux/tty.h>
30#include <linux/init.h>
31#include <linux/console.h>
32#include <linux/serial_core.h>
33#include <linux/serial_reg.h>
34#include <linux/serial.h>
35#include <linux/serial_8250.h>
36#include <asm/io.h>
37#include <asm/serial.h>
38#ifdef CONFIG_FIX_EARLYCON_MEM
39#include <asm/pgtable.h>
40#include <asm/fixmap.h>
41#endif
42
43struct early_serial8250_device {
44 struct uart_port port;
45 char options[16]; /* e.g., 115200n8 */
46 unsigned int baud;
47};
48
49static struct early_serial8250_device early_device;
50
51static unsigned int __init serial_in(struct uart_port *port, int offset)
52{
53 switch (port->iotype) {
54 case UPIO_MEM:
55 return readb(port->membase + offset);
56 case UPIO_MEM32:
57 return readl(port->membase + (offset << 2));
58 case UPIO_PORT:
59 return inb(port->iobase + offset);
60 default:
61 return 0;
62 }
63}
64
65static void __init serial_out(struct uart_port *port, int offset, int value)
66{
67 switch (port->iotype) {
68 case UPIO_MEM:
69 writeb(value, port->membase + offset);
70 break;
71 case UPIO_MEM32:
72 writel(value, port->membase + (offset << 2));
73 break;
74 case UPIO_PORT:
75 outb(value, port->iobase + offset);
76 break;
77 }
78}
79
80#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
81
82static void __init wait_for_xmitr(struct uart_port *port)
83{
84 unsigned int status;
85
86 for (;;) {
87 status = serial_in(port, UART_LSR);
88 if ((status & BOTH_EMPTY) == BOTH_EMPTY)
89 return;
90 cpu_relax();
91 }
92}
93
94static void __init serial_putc(struct uart_port *port, int c)
95{
96 wait_for_xmitr(port);
97 serial_out(port, UART_TX, c);
98}
99
100static void __init early_serial8250_write(struct console *console,
101 const char *s, unsigned int count)
102{
103 struct uart_port *port = &early_device.port;
104 unsigned int ier;
105
106 /* Save the IER and disable interrupts */
107 ier = serial_in(port, UART_IER);
108 serial_out(port, UART_IER, 0);
109
110 uart_console_write(port, s, count, serial_putc);
111
112 /* Wait for transmitter to become empty and restore the IER */
113 wait_for_xmitr(port);
114 serial_out(port, UART_IER, ier);
115}
116
117static unsigned int __init probe_baud(struct uart_port *port)
118{
119 unsigned char lcr, dll, dlm;
120 unsigned int quot;
121
122 lcr = serial_in(port, UART_LCR);
123 serial_out(port, UART_LCR, lcr | UART_LCR_DLAB);
124 dll = serial_in(port, UART_DLL);
125 dlm = serial_in(port, UART_DLM);
126 serial_out(port, UART_LCR, lcr);
127
128 quot = (dlm << 8) | dll;
129 return (port->uartclk / 16) / quot;
130}
131
132static void __init init_port(struct early_serial8250_device *device)
133{
134 struct uart_port *port = &device->port;
135 unsigned int divisor;
136 unsigned char c;
137
138 serial_out(port, UART_LCR, 0x3); /* 8n1 */
139 serial_out(port, UART_IER, 0); /* no interrupt */
140 serial_out(port, UART_FCR, 0); /* no fifo */
141 serial_out(port, UART_MCR, 0x3); /* DTR + RTS */
142
143 divisor = port->uartclk / (16 * device->baud);
144 c = serial_in(port, UART_LCR);
145 serial_out(port, UART_LCR, c | UART_LCR_DLAB);
146 serial_out(port, UART_DLL, divisor & 0xff);
147 serial_out(port, UART_DLM, (divisor >> 8) & 0xff);
148 serial_out(port, UART_LCR, c & ~UART_LCR_DLAB);
149}
150
151static int __init parse_options(struct early_serial8250_device *device,
152 char *options)
153{
154 struct uart_port *port = &device->port;
155 int mmio, mmio32, length;
156
157 if (!options)
158 return -ENODEV;
159
160 port->uartclk = BASE_BAUD * 16;
161
162 mmio = !strncmp(options, "mmio,", 5);
163 mmio32 = !strncmp(options, "mmio32,", 7);
164 if (mmio || mmio32) {
165 port->iotype = (mmio ? UPIO_MEM : UPIO_MEM32);
166 port->mapbase = simple_strtoul(options + (mmio ? 5 : 7),
167 &options, 0);
168 if (mmio32)
169 port->regshift = 2;
170#ifdef CONFIG_FIX_EARLYCON_MEM
171 set_fixmap_nocache(FIX_EARLYCON_MEM_BASE,
172 port->mapbase & PAGE_MASK);
173 port->membase =
174 (void __iomem *)__fix_to_virt(FIX_EARLYCON_MEM_BASE);
175 port->membase += port->mapbase & ~PAGE_MASK;
176#else
177 port->membase = ioremap_nocache(port->mapbase, 64);
178 if (!port->membase) {
179 printk(KERN_ERR "%s: Couldn't ioremap 0x%llx\n",
180 __func__,
181 (unsigned long long) port->mapbase);
182 return -ENOMEM;
183 }
184#endif
185 } else if (!strncmp(options, "io,", 3)) {
186 port->iotype = UPIO_PORT;
187 port->iobase = simple_strtoul(options + 3, &options, 0);
188 mmio = 0;
189 } else
190 return -EINVAL;
191
192 options = strchr(options, ',');
193 if (options) {
194 options++;
195 device->baud = simple_strtoul(options, NULL, 0);
196 length = min(strcspn(options, " "), sizeof(device->options));
197 strncpy(device->options, options, length);
198 } else {
199 device->baud = probe_baud(port);
200 snprintf(device->options, sizeof(device->options), "%u",
201 device->baud);
202 }
203
204 if (mmio || mmio32)
205 printk(KERN_INFO
206 "Early serial console at MMIO%s 0x%llx (options '%s')\n",
207 mmio32 ? "32" : "",
208 (unsigned long long)port->mapbase,
209 device->options);
210 else
211 printk(KERN_INFO
212 "Early serial console at I/O port 0x%lx (options '%s')\n",
213 port->iobase,
214 device->options);
215
216 return 0;
217}
218
219static struct console early_serial8250_console __initdata = {
220 .name = "uart",
221 .write = early_serial8250_write,
222 .flags = CON_PRINTBUFFER | CON_BOOT,
223 .index = -1,
224};
225
226static int __init early_serial8250_setup(char *options)
227{
228 struct early_serial8250_device *device = &early_device;
229 int err;
230
231 if (device->port.membase || device->port.iobase)
232 return 0;
233
234 err = parse_options(device, options);
235 if (err < 0)
236 return err;
237
238 init_port(device);
239 return 0;
240}
241
242int __init setup_early_serial8250_console(char *cmdline)
243{
244 char *options;
245 int err;
246
247 options = strstr(cmdline, "uart8250,");
248 if (!options) {
249 options = strstr(cmdline, "uart,");
250 if (!options)
251 return 0;
252 }
253
254 options = strchr(cmdline, ',') + 1;
255 err = early_serial8250_setup(options);
256 if (err < 0)
257 return err;
258
259 register_console(&early_serial8250_console);
260
261 return 0;
262}
263
264int serial8250_find_port_for_earlycon(void)
265{
266 struct early_serial8250_device *device = &early_device;
267 struct uart_port *port = &device->port;
268 int line;
269 int ret;
270
271 if (!device->port.membase && !device->port.iobase)
272 return -ENODEV;
273
274 line = serial8250_find_port(port);
275 if (line < 0)
276 return -ENODEV;
277
278 ret = update_console_cmdline("uart", 8250,
279 "ttyS", line, device->options);
280 if (ret < 0)
281 ret = update_console_cmdline("uart", 0,
282 "ttyS", line, device->options);
283
284 return ret;
285}
286
287early_param("earlycon", setup_early_serial8250_console);
diff --git a/drivers/serial/8250_exar_st16c554.c b/drivers/serial/8250_exar_st16c554.c
deleted file mode 100644
index 567143ace159..000000000000
--- a/drivers/serial/8250_exar_st16c554.c
+++ /dev/null
@@ -1,52 +0,0 @@
1/*
2 * linux/drivers/serial/8250_exar.c
3 *
4 * Written by Paul B Schroeder < pschroeder "at" uplogix "dot" com >
5 * Based on 8250_boca.
6 *
7 * Copyright (C) 2005 Russell King.
8 * Data taken from include/asm-i386/serial.h
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/serial_8250.h>
17
18#define PORT(_base,_irq) \
19 { \
20 .iobase = _base, \
21 .irq = _irq, \
22 .uartclk = 1843200, \
23 .iotype = UPIO_PORT, \
24 .flags = UPF_BOOT_AUTOCONF, \
25 }
26
27static struct plat_serial8250_port exar_data[] = {
28 PORT(0x100, 5),
29 PORT(0x108, 5),
30 PORT(0x110, 5),
31 PORT(0x118, 5),
32 { },
33};
34
35static struct platform_device exar_device = {
36 .name = "serial8250",
37 .id = PLAT8250_DEV_EXAR_ST16C554,
38 .dev = {
39 .platform_data = exar_data,
40 },
41};
42
43static int __init exar_init(void)
44{
45 return platform_device_register(&exar_device);
46}
47
48module_init(exar_init);
49
50MODULE_AUTHOR("Paul B Schroeder");
51MODULE_DESCRIPTION("8250 serial probe module for Exar cards");
52MODULE_LICENSE("GPL");
diff --git a/drivers/serial/8250_fourport.c b/drivers/serial/8250_fourport.c
deleted file mode 100644
index 6375d68b7913..000000000000
--- a/drivers/serial/8250_fourport.c
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 * linux/drivers/serial/8250_fourport.c
3 *
4 * Copyright (C) 2005 Russell King.
5 * Data taken from include/asm-i386/serial.h
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/module.h>
12#include <linux/init.h>
13#include <linux/serial_8250.h>
14
15#define PORT(_base,_irq) \
16 { \
17 .iobase = _base, \
18 .irq = _irq, \
19 .uartclk = 1843200, \
20 .iotype = UPIO_PORT, \
21 .flags = UPF_BOOT_AUTOCONF | UPF_FOURPORT, \
22 }
23
24static struct plat_serial8250_port fourport_data[] = {
25 PORT(0x1a0, 9),
26 PORT(0x1a8, 9),
27 PORT(0x1b0, 9),
28 PORT(0x1b8, 9),
29 PORT(0x2a0, 5),
30 PORT(0x2a8, 5),
31 PORT(0x2b0, 5),
32 PORT(0x2b8, 5),
33 { },
34};
35
36static struct platform_device fourport_device = {
37 .name = "serial8250",
38 .id = PLAT8250_DEV_FOURPORT,
39 .dev = {
40 .platform_data = fourport_data,
41 },
42};
43
44static int __init fourport_init(void)
45{
46 return platform_device_register(&fourport_device);
47}
48
49module_init(fourport_init);
50
51MODULE_AUTHOR("Russell King");
52MODULE_DESCRIPTION("8250 serial probe module for AST Fourport cards");
53MODULE_LICENSE("GPL");
diff --git a/drivers/serial/8250_gsc.c b/drivers/serial/8250_gsc.c
deleted file mode 100644
index d8c0ffbfa6e3..000000000000
--- a/drivers/serial/8250_gsc.c
+++ /dev/null
@@ -1,122 +0,0 @@
1/*
2 * Serial Device Initialisation for Lasi/Asp/Wax/Dino
3 *
4 * (c) Copyright Matthew Wilcox <willy@debian.org> 2001-2002
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/errno.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/ioport.h>
16#include <linux/module.h>
17#include <linux/serial_core.h>
18#include <linux/signal.h>
19#include <linux/types.h>
20
21#include <asm/hardware.h>
22#include <asm/parisc-device.h>
23#include <asm/io.h>
24
25#include "8250.h"
26
27static int __init serial_init_chip(struct parisc_device *dev)
28{
29 struct uart_port port;
30 unsigned long address;
31 int err;
32
33 if (!dev->irq) {
34 /* We find some unattached serial ports by walking native
35 * busses. These should be silently ignored. Otherwise,
36 * what we have here is a missing parent device, so tell
37 * the user what they're missing.
38 */
39 if (parisc_parent(dev)->id.hw_type != HPHW_IOA)
40 printk(KERN_INFO
41 "Serial: device 0x%llx not configured.\n"
42 "Enable support for Wax, Lasi, Asp or Dino.\n",
43 (unsigned long long)dev->hpa.start);
44 return -ENODEV;
45 }
46
47 address = dev->hpa.start;
48 if (dev->id.sversion != 0x8d)
49 address += 0x800;
50
51 memset(&port, 0, sizeof(port));
52 port.iotype = UPIO_MEM;
53 /* 7.272727MHz on Lasi. Assumed the same for Dino, Wax and Timi. */
54 port.uartclk = 7272727;
55 port.mapbase = address;
56 port.membase = ioremap_nocache(address, 16);
57 port.irq = dev->irq;
58 port.flags = UPF_BOOT_AUTOCONF;
59 port.dev = &dev->dev;
60
61 err = serial8250_register_port(&port);
62 if (err < 0) {
63 printk(KERN_WARNING
64 "serial8250_register_port returned error %d\n", err);
65 iounmap(port.membase);
66 return err;
67 }
68
69 return 0;
70}
71
72static struct parisc_device_id serial_tbl[] = {
73 { HPHW_FIO, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00075 },
74 { HPHW_FIO, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x0008c },
75 { HPHW_FIO, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x0008d },
76 { 0 }
77};
78
79/* Hack. Some machines have SERIAL_0 attached to Lasi and SERIAL_1
80 * attached to Dino. Unfortunately, Dino appears before Lasi in the device
81 * tree. To ensure that ttyS0 == SERIAL_0, we register two drivers; one
82 * which only knows about Lasi and then a second which will find all the
83 * other serial ports. HPUX ignores this problem.
84 */
85static struct parisc_device_id lasi_tbl[] = {
86 { HPHW_FIO, HVERSION_REV_ANY_ID, 0x03B, 0x0008C }, /* C1xx/C1xxL */
87 { HPHW_FIO, HVERSION_REV_ANY_ID, 0x03C, 0x0008C }, /* B132L */
88 { HPHW_FIO, HVERSION_REV_ANY_ID, 0x03D, 0x0008C }, /* B160L */
89 { HPHW_FIO, HVERSION_REV_ANY_ID, 0x03E, 0x0008C }, /* B132L+ */
90 { HPHW_FIO, HVERSION_REV_ANY_ID, 0x03F, 0x0008C }, /* B180L+ */
91 { HPHW_FIO, HVERSION_REV_ANY_ID, 0x046, 0x0008C }, /* Rocky2 120 */
92 { HPHW_FIO, HVERSION_REV_ANY_ID, 0x047, 0x0008C }, /* Rocky2 150 */
93 { HPHW_FIO, HVERSION_REV_ANY_ID, 0x04E, 0x0008C }, /* Kiji L2 132 */
94 { HPHW_FIO, HVERSION_REV_ANY_ID, 0x056, 0x0008C }, /* Raven+ */
95 { 0 }
96};
97
98
99MODULE_DEVICE_TABLE(parisc, serial_tbl);
100
101static struct parisc_driver lasi_driver = {
102 .name = "serial_1",
103 .id_table = lasi_tbl,
104 .probe = serial_init_chip,
105};
106
107static struct parisc_driver serial_driver = {
108 .name = "serial",
109 .id_table = serial_tbl,
110 .probe = serial_init_chip,
111};
112
113static int __init probe_serial_gsc(void)
114{
115 register_parisc_driver(&lasi_driver);
116 register_parisc_driver(&serial_driver);
117 return 0;
118}
119
120module_init(probe_serial_gsc);
121
122MODULE_LICENSE("GPL");
diff --git a/drivers/serial/8250_hp300.c b/drivers/serial/8250_hp300.c
deleted file mode 100644
index c13438c93012..000000000000
--- a/drivers/serial/8250_hp300.c
+++ /dev/null
@@ -1,327 +0,0 @@
1/*
2 * Driver for the 98626/98644/internal serial interface on hp300/hp400
3 * (based on the National Semiconductor INS8250/NS16550AF/WD16C552 UARTs)
4 *
5 * Ported from 2.2 and modified to use the normal 8250 driver
6 * by Kars de Jong <jongk@linux-m68k.org>, May 2004.
7 */
8#include <linux/module.h>
9#include <linux/init.h>
10#include <linux/string.h>
11#include <linux/kernel.h>
12#include <linux/serial.h>
13#include <linux/serial_core.h>
14#include <linux/serial_8250.h>
15#include <linux/delay.h>
16#include <linux/dio.h>
17#include <linux/console.h>
18#include <linux/slab.h>
19#include <asm/io.h>
20
21#include "8250.h"
22
23#if !defined(CONFIG_HPDCA) && !defined(CONFIG_HPAPCI)
24#warning CONFIG_8250 defined but neither CONFIG_HPDCA nor CONFIG_HPAPCI defined, are you sure?
25#endif
26
27#ifdef CONFIG_HPAPCI
28struct hp300_port
29{
30 struct hp300_port *next; /* next port */
31 int line; /* line (tty) number */
32};
33
34static struct hp300_port *hp300_ports;
35#endif
36
37#ifdef CONFIG_HPDCA
38
39static int __devinit hpdca_init_one(struct dio_dev *d,
40 const struct dio_device_id *ent);
41static void __devexit hpdca_remove_one(struct dio_dev *d);
42
43static struct dio_device_id hpdca_dio_tbl[] = {
44 { DIO_ID_DCA0 },
45 { DIO_ID_DCA0REM },
46 { DIO_ID_DCA1 },
47 { DIO_ID_DCA1REM },
48 { 0 }
49};
50
51static struct dio_driver hpdca_driver = {
52 .name = "hpdca",
53 .id_table = hpdca_dio_tbl,
54 .probe = hpdca_init_one,
55 .remove = __devexit_p(hpdca_remove_one),
56};
57
58#endif
59
60static unsigned int num_ports;
61
62extern int hp300_uart_scode;
63
64/* Offset to UART registers from base of DCA */
65#define UART_OFFSET 17
66
67#define DCA_ID 0x01 /* ID (read), reset (write) */
68#define DCA_IC 0x03 /* Interrupt control */
69
70/* Interrupt control */
71#define DCA_IC_IE 0x80 /* Master interrupt enable */
72
73#define HPDCA_BAUD_BASE 153600
74
75/* Base address of the Frodo part */
76#define FRODO_BASE (0x41c000)
77
78/*
79 * Where we find the 8250-like APCI ports, and how far apart they are.
80 */
81#define FRODO_APCIBASE 0x0
82#define FRODO_APCISPACE 0x20
83#define FRODO_APCI_OFFSET(x) (FRODO_APCIBASE + ((x) * FRODO_APCISPACE))
84
85#define HPAPCI_BAUD_BASE 500400
86
87#ifdef CONFIG_SERIAL_8250_CONSOLE
88/*
89 * Parse the bootinfo to find descriptions for headless console and
90 * debug serial ports and register them with the 8250 driver.
91 * This function should be called before serial_console_init() is called
92 * to make sure the serial console will be available for use. IA-64 kernel
93 * calls this function from setup_arch() after the EFI and ACPI tables have
94 * been parsed.
95 */
96int __init hp300_setup_serial_console(void)
97{
98 int scode;
99 struct uart_port port;
100
101 memset(&port, 0, sizeof(port));
102
103 if (hp300_uart_scode < 0 || hp300_uart_scode > DIO_SCMAX)
104 return 0;
105
106 if (DIO_SCINHOLE(hp300_uart_scode))
107 return 0;
108
109 scode = hp300_uart_scode;
110
111 /* Memory mapped I/O */
112 port.iotype = UPIO_MEM;
113 port.flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF;
114 port.type = PORT_UNKNOWN;
115
116 /* Check for APCI console */
117 if (scode == 256) {
118#ifdef CONFIG_HPAPCI
119 printk(KERN_INFO "Serial console is HP APCI 1\n");
120
121 port.uartclk = HPAPCI_BAUD_BASE * 16;
122 port.mapbase = (FRODO_BASE + FRODO_APCI_OFFSET(1));
123 port.membase = (char *)(port.mapbase + DIO_VIRADDRBASE);
124 port.regshift = 2;
125 add_preferred_console("ttyS", port.line, "9600n8");
126#else
127 printk(KERN_WARNING "Serial console is APCI but support is disabled (CONFIG_HPAPCI)!\n");
128 return 0;
129#endif
130 } else {
131#ifdef CONFIG_HPDCA
132 unsigned long pa = dio_scodetophysaddr(scode);
133 if (!pa)
134 return 0;
135
136 printk(KERN_INFO "Serial console is HP DCA at select code %d\n", scode);
137
138 port.uartclk = HPDCA_BAUD_BASE * 16;
139 port.mapbase = (pa + UART_OFFSET);
140 port.membase = (char *)(port.mapbase + DIO_VIRADDRBASE);
141 port.regshift = 1;
142 port.irq = DIO_IPL(pa + DIO_VIRADDRBASE);
143
144 /* Enable board-interrupts */
145 out_8(pa + DIO_VIRADDRBASE + DCA_IC, DCA_IC_IE);
146
147 if (DIO_ID(pa + DIO_VIRADDRBASE) & 0x80)
148 add_preferred_console("ttyS", port.line, "9600n8");
149#else
150 printk(KERN_WARNING "Serial console is DCA but support is disabled (CONFIG_HPDCA)!\n");
151 return 0;
152#endif
153 }
154
155 if (early_serial_setup(&port) < 0)
156 printk(KERN_WARNING "hp300_setup_serial_console(): early_serial_setup() failed.\n");
157 return 0;
158}
159#endif /* CONFIG_SERIAL_8250_CONSOLE */
160
161#ifdef CONFIG_HPDCA
162static int __devinit hpdca_init_one(struct dio_dev *d,
163 const struct dio_device_id *ent)
164{
165 struct uart_port port;
166 int line;
167
168#ifdef CONFIG_SERIAL_8250_CONSOLE
169 if (hp300_uart_scode == d->scode) {
170 /* Already got it. */
171 return 0;
172 }
173#endif
174 memset(&port, 0, sizeof(struct uart_port));
175
176 /* Memory mapped I/O */
177 port.iotype = UPIO_MEM;
178 port.flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF;
179 port.irq = d->ipl;
180 port.uartclk = HPDCA_BAUD_BASE * 16;
181 port.mapbase = (d->resource.start + UART_OFFSET);
182 port.membase = (char *)(port.mapbase + DIO_VIRADDRBASE);
183 port.regshift = 1;
184 port.dev = &d->dev;
185 line = serial8250_register_port(&port);
186
187 if (line < 0) {
188 printk(KERN_NOTICE "8250_hp300: register_serial() DCA scode %d"
189 " irq %d failed\n", d->scode, port.irq);
190 return -ENOMEM;
191 }
192
193 /* Enable board-interrupts */
194 out_8(d->resource.start + DIO_VIRADDRBASE + DCA_IC, DCA_IC_IE);
195 dio_set_drvdata(d, (void *)line);
196
197 /* Reset the DCA */
198 out_8(d->resource.start + DIO_VIRADDRBASE + DCA_ID, 0xff);
199 udelay(100);
200
201 num_ports++;
202
203 return 0;
204}
205#endif
206
207static int __init hp300_8250_init(void)
208{
209 static int called;
210#ifdef CONFIG_HPAPCI
211 int line;
212 unsigned long base;
213 struct uart_port uport;
214 struct hp300_port *port;
215 int i;
216#endif
217 if (called)
218 return -ENODEV;
219 called = 1;
220
221 if (!MACH_IS_HP300)
222 return -ENODEV;
223
224#ifdef CONFIG_HPDCA
225 dio_register_driver(&hpdca_driver);
226#endif
227#ifdef CONFIG_HPAPCI
228 if (hp300_model < HP_400) {
229 if (!num_ports)
230 return -ENODEV;
231 return 0;
232 }
233 /* These models have the Frodo chip.
234 * Port 0 is reserved for the Apollo Domain keyboard.
235 * Port 1 is either the console or the DCA.
236 */
237 for (i = 1; i < 4; i++) {
238 /* Port 1 is the console on a 425e, on other machines it's
239 * mapped to DCA.
240 */
241#ifdef CONFIG_SERIAL_8250_CONSOLE
242 if (i == 1)
243 continue;
244#endif
245
246 /* Create new serial device */
247 port = kmalloc(sizeof(struct hp300_port), GFP_KERNEL);
248 if (!port)
249 return -ENOMEM;
250
251 memset(&uport, 0, sizeof(struct uart_port));
252
253 base = (FRODO_BASE + FRODO_APCI_OFFSET(i));
254
255 /* Memory mapped I/O */
256 uport.iotype = UPIO_MEM;
257 uport.flags = UPF_SKIP_TEST | UPF_SHARE_IRQ \
258 | UPF_BOOT_AUTOCONF;
259 /* XXX - no interrupt support yet */
260 uport.irq = 0;
261 uport.uartclk = HPAPCI_BAUD_BASE * 16;
262 uport.mapbase = base;
263 uport.membase = (char *)(base + DIO_VIRADDRBASE);
264 uport.regshift = 2;
265
266 line = serial8250_register_port(&uport);
267
268 if (line < 0) {
269 printk(KERN_NOTICE "8250_hp300: register_serial() APCI"
270 " %d irq %d failed\n", i, uport.irq);
271 kfree(port);
272 continue;
273 }
274
275 port->line = line;
276 port->next = hp300_ports;
277 hp300_ports = port;
278
279 num_ports++;
280 }
281#endif
282
283 /* Any boards found? */
284 if (!num_ports)
285 return -ENODEV;
286
287 return 0;
288}
289
290#ifdef CONFIG_HPDCA
291static void __devexit hpdca_remove_one(struct dio_dev *d)
292{
293 int line;
294
295 line = (int) dio_get_drvdata(d);
296 if (d->resource.start) {
297 /* Disable board-interrupts */
298 out_8(d->resource.start + DIO_VIRADDRBASE + DCA_IC, 0);
299 }
300 serial8250_unregister_port(line);
301}
302#endif
303
304static void __exit hp300_8250_exit(void)
305{
306#ifdef CONFIG_HPAPCI
307 struct hp300_port *port, *to_free;
308
309 for (port = hp300_ports; port; ) {
310 serial8250_unregister_port(port->line);
311 to_free = port;
312 port = port->next;
313 kfree(to_free);
314 }
315
316 hp300_ports = NULL;
317#endif
318#ifdef CONFIG_HPDCA
319 dio_unregister_driver(&hpdca_driver);
320#endif
321}
322
323module_init(hp300_8250_init);
324module_exit(hp300_8250_exit);
325MODULE_DESCRIPTION("HP DCA/APCI serial driver");
326MODULE_AUTHOR("Kars de Jong <jongk@linux-m68k.org>");
327MODULE_LICENSE("GPL");
diff --git a/drivers/serial/8250_hub6.c b/drivers/serial/8250_hub6.c
deleted file mode 100644
index 7609150e7d5e..000000000000
--- a/drivers/serial/8250_hub6.c
+++ /dev/null
@@ -1,58 +0,0 @@
1/*
2 * linux/drivers/serial/8250_hub6.c
3 *
4 * Copyright (C) 2005 Russell King.
5 * Data taken from include/asm-i386/serial.h
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/module.h>
12#include <linux/init.h>
13#include <linux/serial_8250.h>
14
15#define HUB6(card,port) \
16 { \
17 .iobase = 0x302, \
18 .irq = 3, \
19 .uartclk = 1843200, \
20 .iotype = UPIO_HUB6, \
21 .flags = UPF_BOOT_AUTOCONF, \
22 .hub6 = (card) << 6 | (port) << 3 | 1, \
23 }
24
25static struct plat_serial8250_port hub6_data[] = {
26 HUB6(0, 0),
27 HUB6(0, 1),
28 HUB6(0, 2),
29 HUB6(0, 3),
30 HUB6(0, 4),
31 HUB6(0, 5),
32 HUB6(1, 0),
33 HUB6(1, 1),
34 HUB6(1, 2),
35 HUB6(1, 3),
36 HUB6(1, 4),
37 HUB6(1, 5),
38 { },
39};
40
41static struct platform_device hub6_device = {
42 .name = "serial8250",
43 .id = PLAT8250_DEV_HUB6,
44 .dev = {
45 .platform_data = hub6_data,
46 },
47};
48
49static int __init hub6_init(void)
50{
51 return platform_device_register(&hub6_device);
52}
53
54module_init(hub6_init);
55
56MODULE_AUTHOR("Russell King");
57MODULE_DESCRIPTION("8250 serial probe module for Hub6 cards");
58MODULE_LICENSE("GPL");
diff --git a/drivers/serial/8250_mca.c b/drivers/serial/8250_mca.c
deleted file mode 100644
index d10be944ad44..000000000000
--- a/drivers/serial/8250_mca.c
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * linux/drivers/serial/8250_mca.c
3 *
4 * Copyright (C) 2005 Russell King.
5 * Data taken from include/asm-i386/serial.h
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/module.h>
12#include <linux/init.h>
13#include <linux/mca.h>
14#include <linux/serial_8250.h>
15
16/*
17 * FIXME: Should we be doing AUTO_IRQ here?
18 */
19#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
20#define MCA_FLAGS UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ
21#else
22#define MCA_FLAGS UPF_BOOT_AUTOCONF | UPF_SKIP_TEST
23#endif
24
25#define PORT(_base,_irq) \
26 { \
27 .iobase = _base, \
28 .irq = _irq, \
29 .uartclk = 1843200, \
30 .iotype = UPIO_PORT, \
31 .flags = MCA_FLAGS, \
32 }
33
34static struct plat_serial8250_port mca_data[] = {
35 PORT(0x3220, 3),
36 PORT(0x3228, 3),
37 PORT(0x4220, 3),
38 PORT(0x4228, 3),
39 PORT(0x5220, 3),
40 PORT(0x5228, 3),
41 { },
42};
43
44static struct platform_device mca_device = {
45 .name = "serial8250",
46 .id = PLAT8250_DEV_MCA,
47 .dev = {
48 .platform_data = mca_data,
49 },
50};
51
52static int __init mca_init(void)
53{
54 if (!MCA_bus)
55 return -ENODEV;
56 return platform_device_register(&mca_device);
57}
58
59module_init(mca_init);
60
61MODULE_AUTHOR("Russell King");
62MODULE_DESCRIPTION("8250 serial probe module for MCA ports");
63MODULE_LICENSE("GPL");
diff --git a/drivers/serial/8250_pci.c b/drivers/serial/8250_pci.c
deleted file mode 100644
index 53be4d35a0aa..000000000000
--- a/drivers/serial/8250_pci.c
+++ /dev/null
@@ -1,3809 +0,0 @@
1/*
2 * linux/drivers/char/8250_pci.c
3 *
4 * Probe module for 8250/16550-type PCI serial ports.
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 */
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/pci.h>
17#include <linux/string.h>
18#include <linux/kernel.h>
19#include <linux/slab.h>
20#include <linux/delay.h>
21#include <linux/tty.h>
22#include <linux/serial_core.h>
23#include <linux/8250_pci.h>
24#include <linux/bitops.h>
25
26#include <asm/byteorder.h>
27#include <asm/io.h>
28
29#include "8250.h"
30
31#undef SERIAL_DEBUG_PCI
32
33/*
34 * init function returns:
35 * > 0 - number of ports
36 * = 0 - use board->num_ports
37 * < 0 - error
38 */
39struct pci_serial_quirk {
40 u32 vendor;
41 u32 device;
42 u32 subvendor;
43 u32 subdevice;
44 int (*init)(struct pci_dev *dev);
45 int (*setup)(struct serial_private *,
46 const struct pciserial_board *,
47 struct uart_port *, int);
48 void (*exit)(struct pci_dev *dev);
49};
50
51#define PCI_NUM_BAR_RESOURCES 6
52
53struct serial_private {
54 struct pci_dev *dev;
55 unsigned int nr;
56 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
57 struct pci_serial_quirk *quirk;
58 int line[0];
59};
60
61static void moan_device(const char *str, struct pci_dev *dev)
62{
63 printk(KERN_WARNING
64 "%s: %s\n"
65 "Please send the output of lspci -vv, this\n"
66 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
67 "manufacturer and name of serial board or\n"
68 "modem board to rmk+serial@arm.linux.org.uk.\n",
69 pci_name(dev), str, dev->vendor, dev->device,
70 dev->subsystem_vendor, dev->subsystem_device);
71}
72
73static int
74setup_port(struct serial_private *priv, struct uart_port *port,
75 int bar, int offset, int regshift)
76{
77 struct pci_dev *dev = priv->dev;
78 unsigned long base, len;
79
80 if (bar >= PCI_NUM_BAR_RESOURCES)
81 return -EINVAL;
82
83 base = pci_resource_start(dev, bar);
84
85 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
86 len = pci_resource_len(dev, bar);
87
88 if (!priv->remapped_bar[bar])
89 priv->remapped_bar[bar] = ioremap_nocache(base, len);
90 if (!priv->remapped_bar[bar])
91 return -ENOMEM;
92
93 port->iotype = UPIO_MEM;
94 port->iobase = 0;
95 port->mapbase = base + offset;
96 port->membase = priv->remapped_bar[bar] + offset;
97 port->regshift = regshift;
98 } else {
99 port->iotype = UPIO_PORT;
100 port->iobase = base + offset;
101 port->mapbase = 0;
102 port->membase = NULL;
103 port->regshift = 0;
104 }
105 return 0;
106}
107
108/*
109 * ADDI-DATA GmbH communication cards <info@addi-data.com>
110 */
111static int addidata_apci7800_setup(struct serial_private *priv,
112 const struct pciserial_board *board,
113 struct uart_port *port, int idx)
114{
115 unsigned int bar = 0, offset = board->first_offset;
116 bar = FL_GET_BASE(board->flags);
117
118 if (idx < 2) {
119 offset += idx * board->uart_offset;
120 } else if ((idx >= 2) && (idx < 4)) {
121 bar += 1;
122 offset += ((idx - 2) * board->uart_offset);
123 } else if ((idx >= 4) && (idx < 6)) {
124 bar += 2;
125 offset += ((idx - 4) * board->uart_offset);
126 } else if (idx >= 6) {
127 bar += 3;
128 offset += ((idx - 6) * board->uart_offset);
129 }
130
131 return setup_port(priv, port, bar, offset, board->reg_shift);
132}
133
134/*
135 * AFAVLAB uses a different mixture of BARs and offsets
136 * Not that ugly ;) -- HW
137 */
138static int
139afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
140 struct uart_port *port, int idx)
141{
142 unsigned int bar, offset = board->first_offset;
143
144 bar = FL_GET_BASE(board->flags);
145 if (idx < 4)
146 bar += idx;
147 else {
148 bar = 4;
149 offset += (idx - 4) * board->uart_offset;
150 }
151
152 return setup_port(priv, port, bar, offset, board->reg_shift);
153}
154
155/*
156 * HP's Remote Management Console. The Diva chip came in several
157 * different versions. N-class, L2000 and A500 have two Diva chips, each
158 * with 3 UARTs (the third UART on the second chip is unused). Superdome
159 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
160 * one Diva chip, but it has been expanded to 5 UARTs.
161 */
162static int pci_hp_diva_init(struct pci_dev *dev)
163{
164 int rc = 0;
165
166 switch (dev->subsystem_device) {
167 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
168 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
169 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
170 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
171 rc = 3;
172 break;
173 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
174 rc = 2;
175 break;
176 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
177 rc = 4;
178 break;
179 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
180 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
181 rc = 1;
182 break;
183 }
184
185 return rc;
186}
187
188/*
189 * HP's Diva chip puts the 4th/5th serial port further out, and
190 * some serial ports are supposed to be hidden on certain models.
191 */
192static int
193pci_hp_diva_setup(struct serial_private *priv,
194 const struct pciserial_board *board,
195 struct uart_port *port, int idx)
196{
197 unsigned int offset = board->first_offset;
198 unsigned int bar = FL_GET_BASE(board->flags);
199
200 switch (priv->dev->subsystem_device) {
201 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
202 if (idx == 3)
203 idx++;
204 break;
205 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
206 if (idx > 0)
207 idx++;
208 if (idx > 2)
209 idx++;
210 break;
211 }
212 if (idx > 2)
213 offset = 0x18;
214
215 offset += idx * board->uart_offset;
216
217 return setup_port(priv, port, bar, offset, board->reg_shift);
218}
219
220/*
221 * Added for EKF Intel i960 serial boards
222 */
223static int pci_inteli960ni_init(struct pci_dev *dev)
224{
225 unsigned long oldval;
226
227 if (!(dev->subsystem_device & 0x1000))
228 return -ENODEV;
229
230 /* is firmware started? */
231 pci_read_config_dword(dev, 0x44, (void *)&oldval);
232 if (oldval == 0x00001000L) { /* RESET value */
233 printk(KERN_DEBUG "Local i960 firmware missing");
234 return -ENODEV;
235 }
236 return 0;
237}
238
239/*
240 * Some PCI serial cards using the PLX 9050 PCI interface chip require
241 * that the card interrupt be explicitly enabled or disabled. This
242 * seems to be mainly needed on card using the PLX which also use I/O
243 * mapped memory.
244 */
245static int pci_plx9050_init(struct pci_dev *dev)
246{
247 u8 irq_config;
248 void __iomem *p;
249
250 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
251 moan_device("no memory in bar 0", dev);
252 return 0;
253 }
254
255 irq_config = 0x41;
256 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
257 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
258 irq_config = 0x43;
259
260 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
261 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
262 /*
263 * As the megawolf cards have the int pins active
264 * high, and have 2 UART chips, both ints must be
265 * enabled on the 9050. Also, the UARTS are set in
266 * 16450 mode by default, so we have to enable the
267 * 16C950 'enhanced' mode so that we can use the
268 * deep FIFOs
269 */
270 irq_config = 0x5b;
271 /*
272 * enable/disable interrupts
273 */
274 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
275 if (p == NULL)
276 return -ENOMEM;
277 writel(irq_config, p + 0x4c);
278
279 /*
280 * Read the register back to ensure that it took effect.
281 */
282 readl(p + 0x4c);
283 iounmap(p);
284
285 return 0;
286}
287
288static void __devexit pci_plx9050_exit(struct pci_dev *dev)
289{
290 u8 __iomem *p;
291
292 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
293 return;
294
295 /*
296 * disable interrupts
297 */
298 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
299 if (p != NULL) {
300 writel(0, p + 0x4c);
301
302 /*
303 * Read the register back to ensure that it took effect.
304 */
305 readl(p + 0x4c);
306 iounmap(p);
307 }
308}
309
310#define NI8420_INT_ENABLE_REG 0x38
311#define NI8420_INT_ENABLE_BIT 0x2000
312
313static void __devexit pci_ni8420_exit(struct pci_dev *dev)
314{
315 void __iomem *p;
316 unsigned long base, len;
317 unsigned int bar = 0;
318
319 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
320 moan_device("no memory in bar", dev);
321 return;
322 }
323
324 base = pci_resource_start(dev, bar);
325 len = pci_resource_len(dev, bar);
326 p = ioremap_nocache(base, len);
327 if (p == NULL)
328 return;
329
330 /* Disable the CPU Interrupt */
331 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
332 p + NI8420_INT_ENABLE_REG);
333 iounmap(p);
334}
335
336
337/* MITE registers */
338#define MITE_IOWBSR1 0xc4
339#define MITE_IOWCR1 0xf4
340#define MITE_LCIMR1 0x08
341#define MITE_LCIMR2 0x10
342
343#define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
344
345static void __devexit pci_ni8430_exit(struct pci_dev *dev)
346{
347 void __iomem *p;
348 unsigned long base, len;
349 unsigned int bar = 0;
350
351 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
352 moan_device("no memory in bar", dev);
353 return;
354 }
355
356 base = pci_resource_start(dev, bar);
357 len = pci_resource_len(dev, bar);
358 p = ioremap_nocache(base, len);
359 if (p == NULL)
360 return;
361
362 /* Disable the CPU Interrupt */
363 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
364 iounmap(p);
365}
366
367/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
368static int
369sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
370 struct uart_port *port, int idx)
371{
372 unsigned int bar, offset = board->first_offset;
373
374 bar = 0;
375
376 if (idx < 4) {
377 /* first four channels map to 0, 0x100, 0x200, 0x300 */
378 offset += idx * board->uart_offset;
379 } else if (idx < 8) {
380 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
381 offset += idx * board->uart_offset + 0xC00;
382 } else /* we have only 8 ports on PMC-OCTALPRO */
383 return 1;
384
385 return setup_port(priv, port, bar, offset, board->reg_shift);
386}
387
388/*
389* This does initialization for PMC OCTALPRO cards:
390* maps the device memory, resets the UARTs (needed, bc
391* if the module is removed and inserted again, the card
392* is in the sleep mode) and enables global interrupt.
393*/
394
395/* global control register offset for SBS PMC-OctalPro */
396#define OCT_REG_CR_OFF 0x500
397
398static int sbs_init(struct pci_dev *dev)
399{
400 u8 __iomem *p;
401
402 p = pci_ioremap_bar(dev, 0);
403
404 if (p == NULL)
405 return -ENOMEM;
406 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
407 writeb(0x10, p + OCT_REG_CR_OFF);
408 udelay(50);
409 writeb(0x0, p + OCT_REG_CR_OFF);
410
411 /* Set bit-2 (INTENABLE) of Control Register */
412 writeb(0x4, p + OCT_REG_CR_OFF);
413 iounmap(p);
414
415 return 0;
416}
417
418/*
419 * Disables the global interrupt of PMC-OctalPro
420 */
421
422static void __devexit sbs_exit(struct pci_dev *dev)
423{
424 u8 __iomem *p;
425
426 p = pci_ioremap_bar(dev, 0);
427 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
428 if (p != NULL)
429 writeb(0, p + OCT_REG_CR_OFF);
430 iounmap(p);
431}
432
433/*
434 * SIIG serial cards have an PCI interface chip which also controls
435 * the UART clocking frequency. Each UART can be clocked independently
436 * (except cards equiped with 4 UARTs) and initial clocking settings
437 * are stored in the EEPROM chip. It can cause problems because this
438 * version of serial driver doesn't support differently clocked UART's
439 * on single PCI card. To prevent this, initialization functions set
440 * high frequency clocking for all UART's on given card. It is safe (I
441 * hope) because it doesn't touch EEPROM settings to prevent conflicts
442 * with other OSes (like M$ DOS).
443 *
444 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
445 *
446 * There is two family of SIIG serial cards with different PCI
447 * interface chip and different configuration methods:
448 * - 10x cards have control registers in IO and/or memory space;
449 * - 20x cards have control registers in standard PCI configuration space.
450 *
451 * Note: all 10x cards have PCI device ids 0x10..
452 * all 20x cards have PCI device ids 0x20..
453 *
454 * There are also Quartet Serial cards which use Oxford Semiconductor
455 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
456 *
457 * Note: some SIIG cards are probed by the parport_serial object.
458 */
459
460#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
461#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
462
463static int pci_siig10x_init(struct pci_dev *dev)
464{
465 u16 data;
466 void __iomem *p;
467
468 switch (dev->device & 0xfff8) {
469 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
470 data = 0xffdf;
471 break;
472 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
473 data = 0xf7ff;
474 break;
475 default: /* 1S1P, 4S */
476 data = 0xfffb;
477 break;
478 }
479
480 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
481 if (p == NULL)
482 return -ENOMEM;
483
484 writew(readw(p + 0x28) & data, p + 0x28);
485 readw(p + 0x28);
486 iounmap(p);
487 return 0;
488}
489
490#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
491#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
492
493static int pci_siig20x_init(struct pci_dev *dev)
494{
495 u8 data;
496
497 /* Change clock frequency for the first UART. */
498 pci_read_config_byte(dev, 0x6f, &data);
499 pci_write_config_byte(dev, 0x6f, data & 0xef);
500
501 /* If this card has 2 UART, we have to do the same with second UART. */
502 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
503 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
504 pci_read_config_byte(dev, 0x73, &data);
505 pci_write_config_byte(dev, 0x73, data & 0xef);
506 }
507 return 0;
508}
509
510static int pci_siig_init(struct pci_dev *dev)
511{
512 unsigned int type = dev->device & 0xff00;
513
514 if (type == 0x1000)
515 return pci_siig10x_init(dev);
516 else if (type == 0x2000)
517 return pci_siig20x_init(dev);
518
519 moan_device("Unknown SIIG card", dev);
520 return -ENODEV;
521}
522
523static int pci_siig_setup(struct serial_private *priv,
524 const struct pciserial_board *board,
525 struct uart_port *port, int idx)
526{
527 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
528
529 if (idx > 3) {
530 bar = 4;
531 offset = (idx - 4) * 8;
532 }
533
534 return setup_port(priv, port, bar, offset, 0);
535}
536
537/*
538 * Timedia has an explosion of boards, and to avoid the PCI table from
539 * growing *huge*, we use this function to collapse some 70 entries
540 * in the PCI table into one, for sanity's and compactness's sake.
541 */
542static const unsigned short timedia_single_port[] = {
543 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
544};
545
546static const unsigned short timedia_dual_port[] = {
547 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
548 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
549 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
550 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
551 0xD079, 0
552};
553
554static const unsigned short timedia_quad_port[] = {
555 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
556 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
557 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
558 0xB157, 0
559};
560
561static const unsigned short timedia_eight_port[] = {
562 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
563 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
564};
565
566static const struct timedia_struct {
567 int num;
568 const unsigned short *ids;
569} timedia_data[] = {
570 { 1, timedia_single_port },
571 { 2, timedia_dual_port },
572 { 4, timedia_quad_port },
573 { 8, timedia_eight_port }
574};
575
576static int pci_timedia_init(struct pci_dev *dev)
577{
578 const unsigned short *ids;
579 int i, j;
580
581 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
582 ids = timedia_data[i].ids;
583 for (j = 0; ids[j]; j++)
584 if (dev->subsystem_device == ids[j])
585 return timedia_data[i].num;
586 }
587 return 0;
588}
589
590/*
591 * Timedia/SUNIX uses a mixture of BARs and offsets
592 * Ugh, this is ugly as all hell --- TYT
593 */
594static int
595pci_timedia_setup(struct serial_private *priv,
596 const struct pciserial_board *board,
597 struct uart_port *port, int idx)
598{
599 unsigned int bar = 0, offset = board->first_offset;
600
601 switch (idx) {
602 case 0:
603 bar = 0;
604 break;
605 case 1:
606 offset = board->uart_offset;
607 bar = 0;
608 break;
609 case 2:
610 bar = 1;
611 break;
612 case 3:
613 offset = board->uart_offset;
614 /* FALLTHROUGH */
615 case 4: /* BAR 2 */
616 case 5: /* BAR 3 */
617 case 6: /* BAR 4 */
618 case 7: /* BAR 5 */
619 bar = idx - 2;
620 }
621
622 return setup_port(priv, port, bar, offset, board->reg_shift);
623}
624
625/*
626 * Some Titan cards are also a little weird
627 */
628static int
629titan_400l_800l_setup(struct serial_private *priv,
630 const struct pciserial_board *board,
631 struct uart_port *port, int idx)
632{
633 unsigned int bar, offset = board->first_offset;
634
635 switch (idx) {
636 case 0:
637 bar = 1;
638 break;
639 case 1:
640 bar = 2;
641 break;
642 default:
643 bar = 4;
644 offset = (idx - 2) * board->uart_offset;
645 }
646
647 return setup_port(priv, port, bar, offset, board->reg_shift);
648}
649
650static int pci_xircom_init(struct pci_dev *dev)
651{
652 msleep(100);
653 return 0;
654}
655
656static int pci_ni8420_init(struct pci_dev *dev)
657{
658 void __iomem *p;
659 unsigned long base, len;
660 unsigned int bar = 0;
661
662 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
663 moan_device("no memory in bar", dev);
664 return 0;
665 }
666
667 base = pci_resource_start(dev, bar);
668 len = pci_resource_len(dev, bar);
669 p = ioremap_nocache(base, len);
670 if (p == NULL)
671 return -ENOMEM;
672
673 /* Enable CPU Interrupt */
674 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
675 p + NI8420_INT_ENABLE_REG);
676
677 iounmap(p);
678 return 0;
679}
680
681#define MITE_IOWBSR1_WSIZE 0xa
682#define MITE_IOWBSR1_WIN_OFFSET 0x800
683#define MITE_IOWBSR1_WENAB (1 << 7)
684#define MITE_LCIMR1_IO_IE_0 (1 << 24)
685#define MITE_LCIMR2_SET_CPU_IE (1 << 31)
686#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
687
688static int pci_ni8430_init(struct pci_dev *dev)
689{
690 void __iomem *p;
691 unsigned long base, len;
692 u32 device_window;
693 unsigned int bar = 0;
694
695 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
696 moan_device("no memory in bar", dev);
697 return 0;
698 }
699
700 base = pci_resource_start(dev, bar);
701 len = pci_resource_len(dev, bar);
702 p = ioremap_nocache(base, len);
703 if (p == NULL)
704 return -ENOMEM;
705
706 /* Set device window address and size in BAR0 */
707 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
708 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
709 writel(device_window, p + MITE_IOWBSR1);
710
711 /* Set window access to go to RAMSEL IO address space */
712 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
713 p + MITE_IOWCR1);
714
715 /* Enable IO Bus Interrupt 0 */
716 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
717
718 /* Enable CPU Interrupt */
719 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
720
721 iounmap(p);
722 return 0;
723}
724
725/* UART Port Control Register */
726#define NI8430_PORTCON 0x0f
727#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
728
729static int
730pci_ni8430_setup(struct serial_private *priv,
731 const struct pciserial_board *board,
732 struct uart_port *port, int idx)
733{
734 void __iomem *p;
735 unsigned long base, len;
736 unsigned int bar, offset = board->first_offset;
737
738 if (idx >= board->num_ports)
739 return 1;
740
741 bar = FL_GET_BASE(board->flags);
742 offset += idx * board->uart_offset;
743
744 base = pci_resource_start(priv->dev, bar);
745 len = pci_resource_len(priv->dev, bar);
746 p = ioremap_nocache(base, len);
747
748 /* enable the transciever */
749 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
750 p + offset + NI8430_PORTCON);
751
752 iounmap(p);
753
754 return setup_port(priv, port, bar, offset, board->reg_shift);
755}
756
757
758static int pci_netmos_init(struct pci_dev *dev)
759{
760 /* subdevice 0x00PS means <P> parallel, <S> serial */
761 unsigned int num_serial = dev->subsystem_device & 0xf;
762
763 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
764 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
765 return 0;
766 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
767 dev->subsystem_device == 0x0299)
768 return 0;
769
770 if (num_serial == 0)
771 return -ENODEV;
772 return num_serial;
773}
774
775/*
776 * These chips are available with optionally one parallel port and up to
777 * two serial ports. Unfortunately they all have the same product id.
778 *
779 * Basic configuration is done over a region of 32 I/O ports. The base
780 * ioport is called INTA or INTC, depending on docs/other drivers.
781 *
782 * The region of the 32 I/O ports is configured in POSIO0R...
783 */
784
785/* registers */
786#define ITE_887x_MISCR 0x9c
787#define ITE_887x_INTCBAR 0x78
788#define ITE_887x_UARTBAR 0x7c
789#define ITE_887x_PS0BAR 0x10
790#define ITE_887x_POSIO0 0x60
791
792/* I/O space size */
793#define ITE_887x_IOSIZE 32
794/* I/O space size (bits 26-24; 8 bytes = 011b) */
795#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
796/* I/O space size (bits 26-24; 32 bytes = 101b) */
797#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
798/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
799#define ITE_887x_POSIO_SPEED (3 << 29)
800/* enable IO_Space bit */
801#define ITE_887x_POSIO_ENABLE (1 << 31)
802
803static int pci_ite887x_init(struct pci_dev *dev)
804{
805 /* inta_addr are the configuration addresses of the ITE */
806 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
807 0x200, 0x280, 0 };
808 int ret, i, type;
809 struct resource *iobase = NULL;
810 u32 miscr, uartbar, ioport;
811
812 /* search for the base-ioport */
813 i = 0;
814 while (inta_addr[i] && iobase == NULL) {
815 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
816 "ite887x");
817 if (iobase != NULL) {
818 /* write POSIO0R - speed | size | ioport */
819 pci_write_config_dword(dev, ITE_887x_POSIO0,
820 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
821 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
822 /* write INTCBAR - ioport */
823 pci_write_config_dword(dev, ITE_887x_INTCBAR,
824 inta_addr[i]);
825 ret = inb(inta_addr[i]);
826 if (ret != 0xff) {
827 /* ioport connected */
828 break;
829 }
830 release_region(iobase->start, ITE_887x_IOSIZE);
831 iobase = NULL;
832 }
833 i++;
834 }
835
836 if (!inta_addr[i]) {
837 printk(KERN_ERR "ite887x: could not find iobase\n");
838 return -ENODEV;
839 }
840
841 /* start of undocumented type checking (see parport_pc.c) */
842 type = inb(iobase->start + 0x18) & 0x0f;
843
844 switch (type) {
845 case 0x2: /* ITE8871 (1P) */
846 case 0xa: /* ITE8875 (1P) */
847 ret = 0;
848 break;
849 case 0xe: /* ITE8872 (2S1P) */
850 ret = 2;
851 break;
852 case 0x6: /* ITE8873 (1S) */
853 ret = 1;
854 break;
855 case 0x8: /* ITE8874 (2S) */
856 ret = 2;
857 break;
858 default:
859 moan_device("Unknown ITE887x", dev);
860 ret = -ENODEV;
861 }
862
863 /* configure all serial ports */
864 for (i = 0; i < ret; i++) {
865 /* read the I/O port from the device */
866 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
867 &ioport);
868 ioport &= 0x0000FF00; /* the actual base address */
869 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
870 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
871 ITE_887x_POSIO_IOSIZE_8 | ioport);
872
873 /* write the ioport to the UARTBAR */
874 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
875 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
876 uartbar |= (ioport << (16 * i)); /* set the ioport */
877 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
878
879 /* get current config */
880 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
881 /* disable interrupts (UARTx_Routing[3:0]) */
882 miscr &= ~(0xf << (12 - 4 * i));
883 /* activate the UART (UARTx_En) */
884 miscr |= 1 << (23 - i);
885 /* write new config with activated UART */
886 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
887 }
888
889 if (ret <= 0) {
890 /* the device has no UARTs if we get here */
891 release_region(iobase->start, ITE_887x_IOSIZE);
892 }
893
894 return ret;
895}
896
897static void __devexit pci_ite887x_exit(struct pci_dev *dev)
898{
899 u32 ioport;
900 /* the ioport is bit 0-15 in POSIO0R */
901 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
902 ioport &= 0xffff;
903 release_region(ioport, ITE_887x_IOSIZE);
904}
905
906/*
907 * Oxford Semiconductor Inc.
908 * Check that device is part of the Tornado range of devices, then determine
909 * the number of ports available on the device.
910 */
911static int pci_oxsemi_tornado_init(struct pci_dev *dev)
912{
913 u8 __iomem *p;
914 unsigned long deviceID;
915 unsigned int number_uarts = 0;
916
917 /* OxSemi Tornado devices are all 0xCxxx */
918 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
919 (dev->device & 0xF000) != 0xC000)
920 return 0;
921
922 p = pci_iomap(dev, 0, 5);
923 if (p == NULL)
924 return -ENOMEM;
925
926 deviceID = ioread32(p);
927 /* Tornado device */
928 if (deviceID == 0x07000200) {
929 number_uarts = ioread8(p + 4);
930 printk(KERN_DEBUG
931 "%d ports detected on Oxford PCI Express device\n",
932 number_uarts);
933 }
934 pci_iounmap(dev, p);
935 return number_uarts;
936}
937
938static int
939pci_default_setup(struct serial_private *priv,
940 const struct pciserial_board *board,
941 struct uart_port *port, int idx)
942{
943 unsigned int bar, offset = board->first_offset, maxnr;
944
945 bar = FL_GET_BASE(board->flags);
946 if (board->flags & FL_BASE_BARS)
947 bar += idx;
948 else
949 offset += idx * board->uart_offset;
950
951 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
952 (board->reg_shift + 3);
953
954 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
955 return 1;
956
957 return setup_port(priv, port, bar, offset, board->reg_shift);
958}
959
960static int skip_tx_en_setup(struct serial_private *priv,
961 const struct pciserial_board *board,
962 struct uart_port *port, int idx)
963{
964 port->flags |= UPF_NO_TXEN_TEST;
965 printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
966 "[%04x:%04x] subsystem [%04x:%04x]\n",
967 priv->dev->vendor,
968 priv->dev->device,
969 priv->dev->subsystem_vendor,
970 priv->dev->subsystem_device);
971
972 return pci_default_setup(priv, board, port, idx);
973}
974
975/* This should be in linux/pci_ids.h */
976#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
977#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
978#define PCI_DEVICE_ID_OCTPRO 0x0001
979#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
980#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
981#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
982#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
983#define PCI_VENDOR_ID_ADVANTECH 0x13fe
984#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
985#define PCI_DEVICE_ID_TITAN_200I 0x8028
986#define PCI_DEVICE_ID_TITAN_400I 0x8048
987#define PCI_DEVICE_ID_TITAN_800I 0x8088
988#define PCI_DEVICE_ID_TITAN_800EH 0xA007
989#define PCI_DEVICE_ID_TITAN_800EHB 0xA008
990#define PCI_DEVICE_ID_TITAN_400EH 0xA009
991#define PCI_DEVICE_ID_TITAN_100E 0xA010
992#define PCI_DEVICE_ID_TITAN_200E 0xA012
993#define PCI_DEVICE_ID_TITAN_400E 0xA013
994#define PCI_DEVICE_ID_TITAN_800E 0xA014
995#define PCI_DEVICE_ID_TITAN_200EI 0xA016
996#define PCI_DEVICE_ID_TITAN_200EISI 0xA017
997#define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
998
999/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1000#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1001
1002/*
1003 * Master list of serial port init/setup/exit quirks.
1004 * This does not describe the general nature of the port.
1005 * (ie, baud base, number and location of ports, etc)
1006 *
1007 * This list is ordered alphabetically by vendor then device.
1008 * Specific entries must come before more generic entries.
1009 */
1010static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1011 /*
1012 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1013 */
1014 {
1015 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
1016 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1017 .subvendor = PCI_ANY_ID,
1018 .subdevice = PCI_ANY_ID,
1019 .setup = addidata_apci7800_setup,
1020 },
1021 /*
1022 * AFAVLAB cards - these may be called via parport_serial
1023 * It is not clear whether this applies to all products.
1024 */
1025 {
1026 .vendor = PCI_VENDOR_ID_AFAVLAB,
1027 .device = PCI_ANY_ID,
1028 .subvendor = PCI_ANY_ID,
1029 .subdevice = PCI_ANY_ID,
1030 .setup = afavlab_setup,
1031 },
1032 /*
1033 * HP Diva
1034 */
1035 {
1036 .vendor = PCI_VENDOR_ID_HP,
1037 .device = PCI_DEVICE_ID_HP_DIVA,
1038 .subvendor = PCI_ANY_ID,
1039 .subdevice = PCI_ANY_ID,
1040 .init = pci_hp_diva_init,
1041 .setup = pci_hp_diva_setup,
1042 },
1043 /*
1044 * Intel
1045 */
1046 {
1047 .vendor = PCI_VENDOR_ID_INTEL,
1048 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1049 .subvendor = 0xe4bf,
1050 .subdevice = PCI_ANY_ID,
1051 .init = pci_inteli960ni_init,
1052 .setup = pci_default_setup,
1053 },
1054 {
1055 .vendor = PCI_VENDOR_ID_INTEL,
1056 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1057 .subvendor = PCI_ANY_ID,
1058 .subdevice = PCI_ANY_ID,
1059 .setup = skip_tx_en_setup,
1060 },
1061 {
1062 .vendor = PCI_VENDOR_ID_INTEL,
1063 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1064 .subvendor = PCI_ANY_ID,
1065 .subdevice = PCI_ANY_ID,
1066 .setup = skip_tx_en_setup,
1067 },
1068 {
1069 .vendor = PCI_VENDOR_ID_INTEL,
1070 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1071 .subvendor = PCI_ANY_ID,
1072 .subdevice = PCI_ANY_ID,
1073 .setup = skip_tx_en_setup,
1074 },
1075 /*
1076 * ITE
1077 */
1078 {
1079 .vendor = PCI_VENDOR_ID_ITE,
1080 .device = PCI_DEVICE_ID_ITE_8872,
1081 .subvendor = PCI_ANY_ID,
1082 .subdevice = PCI_ANY_ID,
1083 .init = pci_ite887x_init,
1084 .setup = pci_default_setup,
1085 .exit = __devexit_p(pci_ite887x_exit),
1086 },
1087 /*
1088 * National Instruments
1089 */
1090 {
1091 .vendor = PCI_VENDOR_ID_NI,
1092 .device = PCI_DEVICE_ID_NI_PCI23216,
1093 .subvendor = PCI_ANY_ID,
1094 .subdevice = PCI_ANY_ID,
1095 .init = pci_ni8420_init,
1096 .setup = pci_default_setup,
1097 .exit = __devexit_p(pci_ni8420_exit),
1098 },
1099 {
1100 .vendor = PCI_VENDOR_ID_NI,
1101 .device = PCI_DEVICE_ID_NI_PCI2328,
1102 .subvendor = PCI_ANY_ID,
1103 .subdevice = PCI_ANY_ID,
1104 .init = pci_ni8420_init,
1105 .setup = pci_default_setup,
1106 .exit = __devexit_p(pci_ni8420_exit),
1107 },
1108 {
1109 .vendor = PCI_VENDOR_ID_NI,
1110 .device = PCI_DEVICE_ID_NI_PCI2324,
1111 .subvendor = PCI_ANY_ID,
1112 .subdevice = PCI_ANY_ID,
1113 .init = pci_ni8420_init,
1114 .setup = pci_default_setup,
1115 .exit = __devexit_p(pci_ni8420_exit),
1116 },
1117 {
1118 .vendor = PCI_VENDOR_ID_NI,
1119 .device = PCI_DEVICE_ID_NI_PCI2322,
1120 .subvendor = PCI_ANY_ID,
1121 .subdevice = PCI_ANY_ID,
1122 .init = pci_ni8420_init,
1123 .setup = pci_default_setup,
1124 .exit = __devexit_p(pci_ni8420_exit),
1125 },
1126 {
1127 .vendor = PCI_VENDOR_ID_NI,
1128 .device = PCI_DEVICE_ID_NI_PCI2324I,
1129 .subvendor = PCI_ANY_ID,
1130 .subdevice = PCI_ANY_ID,
1131 .init = pci_ni8420_init,
1132 .setup = pci_default_setup,
1133 .exit = __devexit_p(pci_ni8420_exit),
1134 },
1135 {
1136 .vendor = PCI_VENDOR_ID_NI,
1137 .device = PCI_DEVICE_ID_NI_PCI2322I,
1138 .subvendor = PCI_ANY_ID,
1139 .subdevice = PCI_ANY_ID,
1140 .init = pci_ni8420_init,
1141 .setup = pci_default_setup,
1142 .exit = __devexit_p(pci_ni8420_exit),
1143 },
1144 {
1145 .vendor = PCI_VENDOR_ID_NI,
1146 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1147 .subvendor = PCI_ANY_ID,
1148 .subdevice = PCI_ANY_ID,
1149 .init = pci_ni8420_init,
1150 .setup = pci_default_setup,
1151 .exit = __devexit_p(pci_ni8420_exit),
1152 },
1153 {
1154 .vendor = PCI_VENDOR_ID_NI,
1155 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1156 .subvendor = PCI_ANY_ID,
1157 .subdevice = PCI_ANY_ID,
1158 .init = pci_ni8420_init,
1159 .setup = pci_default_setup,
1160 .exit = __devexit_p(pci_ni8420_exit),
1161 },
1162 {
1163 .vendor = PCI_VENDOR_ID_NI,
1164 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1165 .subvendor = PCI_ANY_ID,
1166 .subdevice = PCI_ANY_ID,
1167 .init = pci_ni8420_init,
1168 .setup = pci_default_setup,
1169 .exit = __devexit_p(pci_ni8420_exit),
1170 },
1171 {
1172 .vendor = PCI_VENDOR_ID_NI,
1173 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1174 .subvendor = PCI_ANY_ID,
1175 .subdevice = PCI_ANY_ID,
1176 .init = pci_ni8420_init,
1177 .setup = pci_default_setup,
1178 .exit = __devexit_p(pci_ni8420_exit),
1179 },
1180 {
1181 .vendor = PCI_VENDOR_ID_NI,
1182 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1183 .subvendor = PCI_ANY_ID,
1184 .subdevice = PCI_ANY_ID,
1185 .init = pci_ni8420_init,
1186 .setup = pci_default_setup,
1187 .exit = __devexit_p(pci_ni8420_exit),
1188 },
1189 {
1190 .vendor = PCI_VENDOR_ID_NI,
1191 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1192 .subvendor = PCI_ANY_ID,
1193 .subdevice = PCI_ANY_ID,
1194 .init = pci_ni8420_init,
1195 .setup = pci_default_setup,
1196 .exit = __devexit_p(pci_ni8420_exit),
1197 },
1198 {
1199 .vendor = PCI_VENDOR_ID_NI,
1200 .device = PCI_ANY_ID,
1201 .subvendor = PCI_ANY_ID,
1202 .subdevice = PCI_ANY_ID,
1203 .init = pci_ni8430_init,
1204 .setup = pci_ni8430_setup,
1205 .exit = __devexit_p(pci_ni8430_exit),
1206 },
1207 /*
1208 * Panacom
1209 */
1210 {
1211 .vendor = PCI_VENDOR_ID_PANACOM,
1212 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1213 .subvendor = PCI_ANY_ID,
1214 .subdevice = PCI_ANY_ID,
1215 .init = pci_plx9050_init,
1216 .setup = pci_default_setup,
1217 .exit = __devexit_p(pci_plx9050_exit),
1218 },
1219 {
1220 .vendor = PCI_VENDOR_ID_PANACOM,
1221 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1222 .subvendor = PCI_ANY_ID,
1223 .subdevice = PCI_ANY_ID,
1224 .init = pci_plx9050_init,
1225 .setup = pci_default_setup,
1226 .exit = __devexit_p(pci_plx9050_exit),
1227 },
1228 /*
1229 * PLX
1230 */
1231 {
1232 .vendor = PCI_VENDOR_ID_PLX,
1233 .device = PCI_DEVICE_ID_PLX_9030,
1234 .subvendor = PCI_SUBVENDOR_ID_PERLE,
1235 .subdevice = PCI_ANY_ID,
1236 .setup = pci_default_setup,
1237 },
1238 {
1239 .vendor = PCI_VENDOR_ID_PLX,
1240 .device = PCI_DEVICE_ID_PLX_9050,
1241 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
1242 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
1243 .init = pci_plx9050_init,
1244 .setup = pci_default_setup,
1245 .exit = __devexit_p(pci_plx9050_exit),
1246 },
1247 {
1248 .vendor = PCI_VENDOR_ID_PLX,
1249 .device = PCI_DEVICE_ID_PLX_9050,
1250 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
1251 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1252 .init = pci_plx9050_init,
1253 .setup = pci_default_setup,
1254 .exit = __devexit_p(pci_plx9050_exit),
1255 },
1256 {
1257 .vendor = PCI_VENDOR_ID_PLX,
1258 .device = PCI_DEVICE_ID_PLX_9050,
1259 .subvendor = PCI_VENDOR_ID_PLX,
1260 .subdevice = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1261 .init = pci_plx9050_init,
1262 .setup = pci_default_setup,
1263 .exit = __devexit_p(pci_plx9050_exit),
1264 },
1265 {
1266 .vendor = PCI_VENDOR_ID_PLX,
1267 .device = PCI_DEVICE_ID_PLX_ROMULUS,
1268 .subvendor = PCI_VENDOR_ID_PLX,
1269 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
1270 .init = pci_plx9050_init,
1271 .setup = pci_default_setup,
1272 .exit = __devexit_p(pci_plx9050_exit),
1273 },
1274 /*
1275 * SBS Technologies, Inc., PMC-OCTALPRO 232
1276 */
1277 {
1278 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1279 .device = PCI_DEVICE_ID_OCTPRO,
1280 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1281 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
1282 .init = sbs_init,
1283 .setup = sbs_setup,
1284 .exit = __devexit_p(sbs_exit),
1285 },
1286 /*
1287 * SBS Technologies, Inc., PMC-OCTALPRO 422
1288 */
1289 {
1290 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1291 .device = PCI_DEVICE_ID_OCTPRO,
1292 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1293 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
1294 .init = sbs_init,
1295 .setup = sbs_setup,
1296 .exit = __devexit_p(sbs_exit),
1297 },
1298 /*
1299 * SBS Technologies, Inc., P-Octal 232
1300 */
1301 {
1302 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1303 .device = PCI_DEVICE_ID_OCTPRO,
1304 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1305 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
1306 .init = sbs_init,
1307 .setup = sbs_setup,
1308 .exit = __devexit_p(sbs_exit),
1309 },
1310 /*
1311 * SBS Technologies, Inc., P-Octal 422
1312 */
1313 {
1314 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1315 .device = PCI_DEVICE_ID_OCTPRO,
1316 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1317 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
1318 .init = sbs_init,
1319 .setup = sbs_setup,
1320 .exit = __devexit_p(sbs_exit),
1321 },
1322 /*
1323 * SIIG cards - these may be called via parport_serial
1324 */
1325 {
1326 .vendor = PCI_VENDOR_ID_SIIG,
1327 .device = PCI_ANY_ID,
1328 .subvendor = PCI_ANY_ID,
1329 .subdevice = PCI_ANY_ID,
1330 .init = pci_siig_init,
1331 .setup = pci_siig_setup,
1332 },
1333 /*
1334 * Titan cards
1335 */
1336 {
1337 .vendor = PCI_VENDOR_ID_TITAN,
1338 .device = PCI_DEVICE_ID_TITAN_400L,
1339 .subvendor = PCI_ANY_ID,
1340 .subdevice = PCI_ANY_ID,
1341 .setup = titan_400l_800l_setup,
1342 },
1343 {
1344 .vendor = PCI_VENDOR_ID_TITAN,
1345 .device = PCI_DEVICE_ID_TITAN_800L,
1346 .subvendor = PCI_ANY_ID,
1347 .subdevice = PCI_ANY_ID,
1348 .setup = titan_400l_800l_setup,
1349 },
1350 /*
1351 * Timedia cards
1352 */
1353 {
1354 .vendor = PCI_VENDOR_ID_TIMEDIA,
1355 .device = PCI_DEVICE_ID_TIMEDIA_1889,
1356 .subvendor = PCI_VENDOR_ID_TIMEDIA,
1357 .subdevice = PCI_ANY_ID,
1358 .init = pci_timedia_init,
1359 .setup = pci_timedia_setup,
1360 },
1361 {
1362 .vendor = PCI_VENDOR_ID_TIMEDIA,
1363 .device = PCI_ANY_ID,
1364 .subvendor = PCI_ANY_ID,
1365 .subdevice = PCI_ANY_ID,
1366 .setup = pci_timedia_setup,
1367 },
1368 /*
1369 * Xircom cards
1370 */
1371 {
1372 .vendor = PCI_VENDOR_ID_XIRCOM,
1373 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1374 .subvendor = PCI_ANY_ID,
1375 .subdevice = PCI_ANY_ID,
1376 .init = pci_xircom_init,
1377 .setup = pci_default_setup,
1378 },
1379 /*
1380 * Netmos cards - these may be called via parport_serial
1381 */
1382 {
1383 .vendor = PCI_VENDOR_ID_NETMOS,
1384 .device = PCI_ANY_ID,
1385 .subvendor = PCI_ANY_ID,
1386 .subdevice = PCI_ANY_ID,
1387 .init = pci_netmos_init,
1388 .setup = pci_default_setup,
1389 },
1390 /*
1391 * For Oxford Semiconductor and Mainpine
1392 */
1393 {
1394 .vendor = PCI_VENDOR_ID_OXSEMI,
1395 .device = PCI_ANY_ID,
1396 .subvendor = PCI_ANY_ID,
1397 .subdevice = PCI_ANY_ID,
1398 .init = pci_oxsemi_tornado_init,
1399 .setup = pci_default_setup,
1400 },
1401 {
1402 .vendor = PCI_VENDOR_ID_MAINPINE,
1403 .device = PCI_ANY_ID,
1404 .subvendor = PCI_ANY_ID,
1405 .subdevice = PCI_ANY_ID,
1406 .init = pci_oxsemi_tornado_init,
1407 .setup = pci_default_setup,
1408 },
1409 /*
1410 * Default "match everything" terminator entry
1411 */
1412 {
1413 .vendor = PCI_ANY_ID,
1414 .device = PCI_ANY_ID,
1415 .subvendor = PCI_ANY_ID,
1416 .subdevice = PCI_ANY_ID,
1417 .setup = pci_default_setup,
1418 }
1419};
1420
1421static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1422{
1423 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1424}
1425
1426static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1427{
1428 struct pci_serial_quirk *quirk;
1429
1430 for (quirk = pci_serial_quirks; ; quirk++)
1431 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1432 quirk_id_matches(quirk->device, dev->device) &&
1433 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1434 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1435 break;
1436 return quirk;
1437}
1438
1439static inline int get_pci_irq(struct pci_dev *dev,
1440 const struct pciserial_board *board)
1441{
1442 if (board->flags & FL_NOIRQ)
1443 return 0;
1444 else
1445 return dev->irq;
1446}
1447
1448/*
1449 * This is the configuration table for all of the PCI serial boards
1450 * which we support. It is directly indexed by the pci_board_num_t enum
1451 * value, which is encoded in the pci_device_id PCI probe table's
1452 * driver_data member.
1453 *
1454 * The makeup of these names are:
1455 * pbn_bn{_bt}_n_baud{_offsetinhex}
1456 *
1457 * bn = PCI BAR number
1458 * bt = Index using PCI BARs
1459 * n = number of serial ports
1460 * baud = baud rate
1461 * offsetinhex = offset for each sequential port (in hex)
1462 *
1463 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1464 *
1465 * Please note: in theory if n = 1, _bt infix should make no difference.
1466 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1467 */
1468enum pci_board_num_t {
1469 pbn_default = 0,
1470
1471 pbn_b0_1_115200,
1472 pbn_b0_2_115200,
1473 pbn_b0_4_115200,
1474 pbn_b0_5_115200,
1475 pbn_b0_8_115200,
1476
1477 pbn_b0_1_921600,
1478 pbn_b0_2_921600,
1479 pbn_b0_4_921600,
1480
1481 pbn_b0_2_1130000,
1482
1483 pbn_b0_4_1152000,
1484
1485 pbn_b0_2_1843200,
1486 pbn_b0_4_1843200,
1487
1488 pbn_b0_2_1843200_200,
1489 pbn_b0_4_1843200_200,
1490 pbn_b0_8_1843200_200,
1491
1492 pbn_b0_1_4000000,
1493
1494 pbn_b0_bt_1_115200,
1495 pbn_b0_bt_2_115200,
1496 pbn_b0_bt_4_115200,
1497 pbn_b0_bt_8_115200,
1498
1499 pbn_b0_bt_1_460800,
1500 pbn_b0_bt_2_460800,
1501 pbn_b0_bt_4_460800,
1502
1503 pbn_b0_bt_1_921600,
1504 pbn_b0_bt_2_921600,
1505 pbn_b0_bt_4_921600,
1506 pbn_b0_bt_8_921600,
1507
1508 pbn_b1_1_115200,
1509 pbn_b1_2_115200,
1510 pbn_b1_4_115200,
1511 pbn_b1_8_115200,
1512 pbn_b1_16_115200,
1513
1514 pbn_b1_1_921600,
1515 pbn_b1_2_921600,
1516 pbn_b1_4_921600,
1517 pbn_b1_8_921600,
1518
1519 pbn_b1_2_1250000,
1520
1521 pbn_b1_bt_1_115200,
1522 pbn_b1_bt_2_115200,
1523 pbn_b1_bt_4_115200,
1524
1525 pbn_b1_bt_2_921600,
1526
1527 pbn_b1_1_1382400,
1528 pbn_b1_2_1382400,
1529 pbn_b1_4_1382400,
1530 pbn_b1_8_1382400,
1531
1532 pbn_b2_1_115200,
1533 pbn_b2_2_115200,
1534 pbn_b2_4_115200,
1535 pbn_b2_8_115200,
1536
1537 pbn_b2_1_460800,
1538 pbn_b2_4_460800,
1539 pbn_b2_8_460800,
1540 pbn_b2_16_460800,
1541
1542 pbn_b2_1_921600,
1543 pbn_b2_4_921600,
1544 pbn_b2_8_921600,
1545
1546 pbn_b2_8_1152000,
1547
1548 pbn_b2_bt_1_115200,
1549 pbn_b2_bt_2_115200,
1550 pbn_b2_bt_4_115200,
1551
1552 pbn_b2_bt_2_921600,
1553 pbn_b2_bt_4_921600,
1554
1555 pbn_b3_2_115200,
1556 pbn_b3_4_115200,
1557 pbn_b3_8_115200,
1558
1559 pbn_b4_bt_2_921600,
1560 pbn_b4_bt_4_921600,
1561 pbn_b4_bt_8_921600,
1562
1563 /*
1564 * Board-specific versions.
1565 */
1566 pbn_panacom,
1567 pbn_panacom2,
1568 pbn_panacom4,
1569 pbn_exsys_4055,
1570 pbn_plx_romulus,
1571 pbn_oxsemi,
1572 pbn_oxsemi_1_4000000,
1573 pbn_oxsemi_2_4000000,
1574 pbn_oxsemi_4_4000000,
1575 pbn_oxsemi_8_4000000,
1576 pbn_intel_i960,
1577 pbn_sgi_ioc3,
1578 pbn_computone_4,
1579 pbn_computone_6,
1580 pbn_computone_8,
1581 pbn_sbsxrsio,
1582 pbn_exar_XR17C152,
1583 pbn_exar_XR17C154,
1584 pbn_exar_XR17C158,
1585 pbn_exar_ibm_saturn,
1586 pbn_pasemi_1682M,
1587 pbn_ni8430_2,
1588 pbn_ni8430_4,
1589 pbn_ni8430_8,
1590 pbn_ni8430_16,
1591 pbn_ADDIDATA_PCIe_1_3906250,
1592 pbn_ADDIDATA_PCIe_2_3906250,
1593 pbn_ADDIDATA_PCIe_4_3906250,
1594 pbn_ADDIDATA_PCIe_8_3906250,
1595};
1596
1597/*
1598 * uart_offset - the space between channels
1599 * reg_shift - describes how the UART registers are mapped
1600 * to PCI memory by the card.
1601 * For example IER register on SBS, Inc. PMC-OctPro is located at
1602 * offset 0x10 from the UART base, while UART_IER is defined as 1
1603 * in include/linux/serial_reg.h,
1604 * see first lines of serial_in() and serial_out() in 8250.c
1605*/
1606
1607static struct pciserial_board pci_boards[] __devinitdata = {
1608 [pbn_default] = {
1609 .flags = FL_BASE0,
1610 .num_ports = 1,
1611 .base_baud = 115200,
1612 .uart_offset = 8,
1613 },
1614 [pbn_b0_1_115200] = {
1615 .flags = FL_BASE0,
1616 .num_ports = 1,
1617 .base_baud = 115200,
1618 .uart_offset = 8,
1619 },
1620 [pbn_b0_2_115200] = {
1621 .flags = FL_BASE0,
1622 .num_ports = 2,
1623 .base_baud = 115200,
1624 .uart_offset = 8,
1625 },
1626 [pbn_b0_4_115200] = {
1627 .flags = FL_BASE0,
1628 .num_ports = 4,
1629 .base_baud = 115200,
1630 .uart_offset = 8,
1631 },
1632 [pbn_b0_5_115200] = {
1633 .flags = FL_BASE0,
1634 .num_ports = 5,
1635 .base_baud = 115200,
1636 .uart_offset = 8,
1637 },
1638 [pbn_b0_8_115200] = {
1639 .flags = FL_BASE0,
1640 .num_ports = 8,
1641 .base_baud = 115200,
1642 .uart_offset = 8,
1643 },
1644 [pbn_b0_1_921600] = {
1645 .flags = FL_BASE0,
1646 .num_ports = 1,
1647 .base_baud = 921600,
1648 .uart_offset = 8,
1649 },
1650 [pbn_b0_2_921600] = {
1651 .flags = FL_BASE0,
1652 .num_ports = 2,
1653 .base_baud = 921600,
1654 .uart_offset = 8,
1655 },
1656 [pbn_b0_4_921600] = {
1657 .flags = FL_BASE0,
1658 .num_ports = 4,
1659 .base_baud = 921600,
1660 .uart_offset = 8,
1661 },
1662
1663 [pbn_b0_2_1130000] = {
1664 .flags = FL_BASE0,
1665 .num_ports = 2,
1666 .base_baud = 1130000,
1667 .uart_offset = 8,
1668 },
1669
1670 [pbn_b0_4_1152000] = {
1671 .flags = FL_BASE0,
1672 .num_ports = 4,
1673 .base_baud = 1152000,
1674 .uart_offset = 8,
1675 },
1676
1677 [pbn_b0_2_1843200] = {
1678 .flags = FL_BASE0,
1679 .num_ports = 2,
1680 .base_baud = 1843200,
1681 .uart_offset = 8,
1682 },
1683 [pbn_b0_4_1843200] = {
1684 .flags = FL_BASE0,
1685 .num_ports = 4,
1686 .base_baud = 1843200,
1687 .uart_offset = 8,
1688 },
1689
1690 [pbn_b0_2_1843200_200] = {
1691 .flags = FL_BASE0,
1692 .num_ports = 2,
1693 .base_baud = 1843200,
1694 .uart_offset = 0x200,
1695 },
1696 [pbn_b0_4_1843200_200] = {
1697 .flags = FL_BASE0,
1698 .num_ports = 4,
1699 .base_baud = 1843200,
1700 .uart_offset = 0x200,
1701 },
1702 [pbn_b0_8_1843200_200] = {
1703 .flags = FL_BASE0,
1704 .num_ports = 8,
1705 .base_baud = 1843200,
1706 .uart_offset = 0x200,
1707 },
1708 [pbn_b0_1_4000000] = {
1709 .flags = FL_BASE0,
1710 .num_ports = 1,
1711 .base_baud = 4000000,
1712 .uart_offset = 8,
1713 },
1714
1715 [pbn_b0_bt_1_115200] = {
1716 .flags = FL_BASE0|FL_BASE_BARS,
1717 .num_ports = 1,
1718 .base_baud = 115200,
1719 .uart_offset = 8,
1720 },
1721 [pbn_b0_bt_2_115200] = {
1722 .flags = FL_BASE0|FL_BASE_BARS,
1723 .num_ports = 2,
1724 .base_baud = 115200,
1725 .uart_offset = 8,
1726 },
1727 [pbn_b0_bt_4_115200] = {
1728 .flags = FL_BASE0|FL_BASE_BARS,
1729 .num_ports = 4,
1730 .base_baud = 115200,
1731 .uart_offset = 8,
1732 },
1733 [pbn_b0_bt_8_115200] = {
1734 .flags = FL_BASE0|FL_BASE_BARS,
1735 .num_ports = 8,
1736 .base_baud = 115200,
1737 .uart_offset = 8,
1738 },
1739
1740 [pbn_b0_bt_1_460800] = {
1741 .flags = FL_BASE0|FL_BASE_BARS,
1742 .num_ports = 1,
1743 .base_baud = 460800,
1744 .uart_offset = 8,
1745 },
1746 [pbn_b0_bt_2_460800] = {
1747 .flags = FL_BASE0|FL_BASE_BARS,
1748 .num_ports = 2,
1749 .base_baud = 460800,
1750 .uart_offset = 8,
1751 },
1752 [pbn_b0_bt_4_460800] = {
1753 .flags = FL_BASE0|FL_BASE_BARS,
1754 .num_ports = 4,
1755 .base_baud = 460800,
1756 .uart_offset = 8,
1757 },
1758
1759 [pbn_b0_bt_1_921600] = {
1760 .flags = FL_BASE0|FL_BASE_BARS,
1761 .num_ports = 1,
1762 .base_baud = 921600,
1763 .uart_offset = 8,
1764 },
1765 [pbn_b0_bt_2_921600] = {
1766 .flags = FL_BASE0|FL_BASE_BARS,
1767 .num_ports = 2,
1768 .base_baud = 921600,
1769 .uart_offset = 8,
1770 },
1771 [pbn_b0_bt_4_921600] = {
1772 .flags = FL_BASE0|FL_BASE_BARS,
1773 .num_ports = 4,
1774 .base_baud = 921600,
1775 .uart_offset = 8,
1776 },
1777 [pbn_b0_bt_8_921600] = {
1778 .flags = FL_BASE0|FL_BASE_BARS,
1779 .num_ports = 8,
1780 .base_baud = 921600,
1781 .uart_offset = 8,
1782 },
1783
1784 [pbn_b1_1_115200] = {
1785 .flags = FL_BASE1,
1786 .num_ports = 1,
1787 .base_baud = 115200,
1788 .uart_offset = 8,
1789 },
1790 [pbn_b1_2_115200] = {
1791 .flags = FL_BASE1,
1792 .num_ports = 2,
1793 .base_baud = 115200,
1794 .uart_offset = 8,
1795 },
1796 [pbn_b1_4_115200] = {
1797 .flags = FL_BASE1,
1798 .num_ports = 4,
1799 .base_baud = 115200,
1800 .uart_offset = 8,
1801 },
1802 [pbn_b1_8_115200] = {
1803 .flags = FL_BASE1,
1804 .num_ports = 8,
1805 .base_baud = 115200,
1806 .uart_offset = 8,
1807 },
1808 [pbn_b1_16_115200] = {
1809 .flags = FL_BASE1,
1810 .num_ports = 16,
1811 .base_baud = 115200,
1812 .uart_offset = 8,
1813 },
1814
1815 [pbn_b1_1_921600] = {
1816 .flags = FL_BASE1,
1817 .num_ports = 1,
1818 .base_baud = 921600,
1819 .uart_offset = 8,
1820 },
1821 [pbn_b1_2_921600] = {
1822 .flags = FL_BASE1,
1823 .num_ports = 2,
1824 .base_baud = 921600,
1825 .uart_offset = 8,
1826 },
1827 [pbn_b1_4_921600] = {
1828 .flags = FL_BASE1,
1829 .num_ports = 4,
1830 .base_baud = 921600,
1831 .uart_offset = 8,
1832 },
1833 [pbn_b1_8_921600] = {
1834 .flags = FL_BASE1,
1835 .num_ports = 8,
1836 .base_baud = 921600,
1837 .uart_offset = 8,
1838 },
1839 [pbn_b1_2_1250000] = {
1840 .flags = FL_BASE1,
1841 .num_ports = 2,
1842 .base_baud = 1250000,
1843 .uart_offset = 8,
1844 },
1845
1846 [pbn_b1_bt_1_115200] = {
1847 .flags = FL_BASE1|FL_BASE_BARS,
1848 .num_ports = 1,
1849 .base_baud = 115200,
1850 .uart_offset = 8,
1851 },
1852 [pbn_b1_bt_2_115200] = {
1853 .flags = FL_BASE1|FL_BASE_BARS,
1854 .num_ports = 2,
1855 .base_baud = 115200,
1856 .uart_offset = 8,
1857 },
1858 [pbn_b1_bt_4_115200] = {
1859 .flags = FL_BASE1|FL_BASE_BARS,
1860 .num_ports = 4,
1861 .base_baud = 115200,
1862 .uart_offset = 8,
1863 },
1864
1865 [pbn_b1_bt_2_921600] = {
1866 .flags = FL_BASE1|FL_BASE_BARS,
1867 .num_ports = 2,
1868 .base_baud = 921600,
1869 .uart_offset = 8,
1870 },
1871
1872 [pbn_b1_1_1382400] = {
1873 .flags = FL_BASE1,
1874 .num_ports = 1,
1875 .base_baud = 1382400,
1876 .uart_offset = 8,
1877 },
1878 [pbn_b1_2_1382400] = {
1879 .flags = FL_BASE1,
1880 .num_ports = 2,
1881 .base_baud = 1382400,
1882 .uart_offset = 8,
1883 },
1884 [pbn_b1_4_1382400] = {
1885 .flags = FL_BASE1,
1886 .num_ports = 4,
1887 .base_baud = 1382400,
1888 .uart_offset = 8,
1889 },
1890 [pbn_b1_8_1382400] = {
1891 .flags = FL_BASE1,
1892 .num_ports = 8,
1893 .base_baud = 1382400,
1894 .uart_offset = 8,
1895 },
1896
1897 [pbn_b2_1_115200] = {
1898 .flags = FL_BASE2,
1899 .num_ports = 1,
1900 .base_baud = 115200,
1901 .uart_offset = 8,
1902 },
1903 [pbn_b2_2_115200] = {
1904 .flags = FL_BASE2,
1905 .num_ports = 2,
1906 .base_baud = 115200,
1907 .uart_offset = 8,
1908 },
1909 [pbn_b2_4_115200] = {
1910 .flags = FL_BASE2,
1911 .num_ports = 4,
1912 .base_baud = 115200,
1913 .uart_offset = 8,
1914 },
1915 [pbn_b2_8_115200] = {
1916 .flags = FL_BASE2,
1917 .num_ports = 8,
1918 .base_baud = 115200,
1919 .uart_offset = 8,
1920 },
1921
1922 [pbn_b2_1_460800] = {
1923 .flags = FL_BASE2,
1924 .num_ports = 1,
1925 .base_baud = 460800,
1926 .uart_offset = 8,
1927 },
1928 [pbn_b2_4_460800] = {
1929 .flags = FL_BASE2,
1930 .num_ports = 4,
1931 .base_baud = 460800,
1932 .uart_offset = 8,
1933 },
1934 [pbn_b2_8_460800] = {
1935 .flags = FL_BASE2,
1936 .num_ports = 8,
1937 .base_baud = 460800,
1938 .uart_offset = 8,
1939 },
1940 [pbn_b2_16_460800] = {
1941 .flags = FL_BASE2,
1942 .num_ports = 16,
1943 .base_baud = 460800,
1944 .uart_offset = 8,
1945 },
1946
1947 [pbn_b2_1_921600] = {
1948 .flags = FL_BASE2,
1949 .num_ports = 1,
1950 .base_baud = 921600,
1951 .uart_offset = 8,
1952 },
1953 [pbn_b2_4_921600] = {
1954 .flags = FL_BASE2,
1955 .num_ports = 4,
1956 .base_baud = 921600,
1957 .uart_offset = 8,
1958 },
1959 [pbn_b2_8_921600] = {
1960 .flags = FL_BASE2,
1961 .num_ports = 8,
1962 .base_baud = 921600,
1963 .uart_offset = 8,
1964 },
1965
1966 [pbn_b2_8_1152000] = {
1967 .flags = FL_BASE2,
1968 .num_ports = 8,
1969 .base_baud = 1152000,
1970 .uart_offset = 8,
1971 },
1972
1973 [pbn_b2_bt_1_115200] = {
1974 .flags = FL_BASE2|FL_BASE_BARS,
1975 .num_ports = 1,
1976 .base_baud = 115200,
1977 .uart_offset = 8,
1978 },
1979 [pbn_b2_bt_2_115200] = {
1980 .flags = FL_BASE2|FL_BASE_BARS,
1981 .num_ports = 2,
1982 .base_baud = 115200,
1983 .uart_offset = 8,
1984 },
1985 [pbn_b2_bt_4_115200] = {
1986 .flags = FL_BASE2|FL_BASE_BARS,
1987 .num_ports = 4,
1988 .base_baud = 115200,
1989 .uart_offset = 8,
1990 },
1991
1992 [pbn_b2_bt_2_921600] = {
1993 .flags = FL_BASE2|FL_BASE_BARS,
1994 .num_ports = 2,
1995 .base_baud = 921600,
1996 .uart_offset = 8,
1997 },
1998 [pbn_b2_bt_4_921600] = {
1999 .flags = FL_BASE2|FL_BASE_BARS,
2000 .num_ports = 4,
2001 .base_baud = 921600,
2002 .uart_offset = 8,
2003 },
2004
2005 [pbn_b3_2_115200] = {
2006 .flags = FL_BASE3,
2007 .num_ports = 2,
2008 .base_baud = 115200,
2009 .uart_offset = 8,
2010 },
2011 [pbn_b3_4_115200] = {
2012 .flags = FL_BASE3,
2013 .num_ports = 4,
2014 .base_baud = 115200,
2015 .uart_offset = 8,
2016 },
2017 [pbn_b3_8_115200] = {
2018 .flags = FL_BASE3,
2019 .num_ports = 8,
2020 .base_baud = 115200,
2021 .uart_offset = 8,
2022 },
2023
2024 [pbn_b4_bt_2_921600] = {
2025 .flags = FL_BASE4,
2026 .num_ports = 2,
2027 .base_baud = 921600,
2028 .uart_offset = 8,
2029 },
2030 [pbn_b4_bt_4_921600] = {
2031 .flags = FL_BASE4,
2032 .num_ports = 4,
2033 .base_baud = 921600,
2034 .uart_offset = 8,
2035 },
2036 [pbn_b4_bt_8_921600] = {
2037 .flags = FL_BASE4,
2038 .num_ports = 8,
2039 .base_baud = 921600,
2040 .uart_offset = 8,
2041 },
2042
2043 /*
2044 * Entries following this are board-specific.
2045 */
2046
2047 /*
2048 * Panacom - IOMEM
2049 */
2050 [pbn_panacom] = {
2051 .flags = FL_BASE2,
2052 .num_ports = 2,
2053 .base_baud = 921600,
2054 .uart_offset = 0x400,
2055 .reg_shift = 7,
2056 },
2057 [pbn_panacom2] = {
2058 .flags = FL_BASE2|FL_BASE_BARS,
2059 .num_ports = 2,
2060 .base_baud = 921600,
2061 .uart_offset = 0x400,
2062 .reg_shift = 7,
2063 },
2064 [pbn_panacom4] = {
2065 .flags = FL_BASE2|FL_BASE_BARS,
2066 .num_ports = 4,
2067 .base_baud = 921600,
2068 .uart_offset = 0x400,
2069 .reg_shift = 7,
2070 },
2071
2072 [pbn_exsys_4055] = {
2073 .flags = FL_BASE2,
2074 .num_ports = 4,
2075 .base_baud = 115200,
2076 .uart_offset = 8,
2077 },
2078
2079 /* I think this entry is broken - the first_offset looks wrong --rmk */
2080 [pbn_plx_romulus] = {
2081 .flags = FL_BASE2,
2082 .num_ports = 4,
2083 .base_baud = 921600,
2084 .uart_offset = 8 << 2,
2085 .reg_shift = 2,
2086 .first_offset = 0x03,
2087 },
2088
2089 /*
2090 * This board uses the size of PCI Base region 0 to
2091 * signal now many ports are available
2092 */
2093 [pbn_oxsemi] = {
2094 .flags = FL_BASE0|FL_REGION_SZ_CAP,
2095 .num_ports = 32,
2096 .base_baud = 115200,
2097 .uart_offset = 8,
2098 },
2099 [pbn_oxsemi_1_4000000] = {
2100 .flags = FL_BASE0,
2101 .num_ports = 1,
2102 .base_baud = 4000000,
2103 .uart_offset = 0x200,
2104 .first_offset = 0x1000,
2105 },
2106 [pbn_oxsemi_2_4000000] = {
2107 .flags = FL_BASE0,
2108 .num_ports = 2,
2109 .base_baud = 4000000,
2110 .uart_offset = 0x200,
2111 .first_offset = 0x1000,
2112 },
2113 [pbn_oxsemi_4_4000000] = {
2114 .flags = FL_BASE0,
2115 .num_ports = 4,
2116 .base_baud = 4000000,
2117 .uart_offset = 0x200,
2118 .first_offset = 0x1000,
2119 },
2120 [pbn_oxsemi_8_4000000] = {
2121 .flags = FL_BASE0,
2122 .num_ports = 8,
2123 .base_baud = 4000000,
2124 .uart_offset = 0x200,
2125 .first_offset = 0x1000,
2126 },
2127
2128
2129 /*
2130 * EKF addition for i960 Boards form EKF with serial port.
2131 * Max 256 ports.
2132 */
2133 [pbn_intel_i960] = {
2134 .flags = FL_BASE0,
2135 .num_ports = 32,
2136 .base_baud = 921600,
2137 .uart_offset = 8 << 2,
2138 .reg_shift = 2,
2139 .first_offset = 0x10000,
2140 },
2141 [pbn_sgi_ioc3] = {
2142 .flags = FL_BASE0|FL_NOIRQ,
2143 .num_ports = 1,
2144 .base_baud = 458333,
2145 .uart_offset = 8,
2146 .reg_shift = 0,
2147 .first_offset = 0x20178,
2148 },
2149
2150 /*
2151 * Computone - uses IOMEM.
2152 */
2153 [pbn_computone_4] = {
2154 .flags = FL_BASE0,
2155 .num_ports = 4,
2156 .base_baud = 921600,
2157 .uart_offset = 0x40,
2158 .reg_shift = 2,
2159 .first_offset = 0x200,
2160 },
2161 [pbn_computone_6] = {
2162 .flags = FL_BASE0,
2163 .num_ports = 6,
2164 .base_baud = 921600,
2165 .uart_offset = 0x40,
2166 .reg_shift = 2,
2167 .first_offset = 0x200,
2168 },
2169 [pbn_computone_8] = {
2170 .flags = FL_BASE0,
2171 .num_ports = 8,
2172 .base_baud = 921600,
2173 .uart_offset = 0x40,
2174 .reg_shift = 2,
2175 .first_offset = 0x200,
2176 },
2177 [pbn_sbsxrsio] = {
2178 .flags = FL_BASE0,
2179 .num_ports = 8,
2180 .base_baud = 460800,
2181 .uart_offset = 256,
2182 .reg_shift = 4,
2183 },
2184 /*
2185 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2186 * Only basic 16550A support.
2187 * XR17C15[24] are not tested, but they should work.
2188 */
2189 [pbn_exar_XR17C152] = {
2190 .flags = FL_BASE0,
2191 .num_ports = 2,
2192 .base_baud = 921600,
2193 .uart_offset = 0x200,
2194 },
2195 [pbn_exar_XR17C154] = {
2196 .flags = FL_BASE0,
2197 .num_ports = 4,
2198 .base_baud = 921600,
2199 .uart_offset = 0x200,
2200 },
2201 [pbn_exar_XR17C158] = {
2202 .flags = FL_BASE0,
2203 .num_ports = 8,
2204 .base_baud = 921600,
2205 .uart_offset = 0x200,
2206 },
2207 [pbn_exar_ibm_saturn] = {
2208 .flags = FL_BASE0,
2209 .num_ports = 1,
2210 .base_baud = 921600,
2211 .uart_offset = 0x200,
2212 },
2213
2214 /*
2215 * PA Semi PWRficient PA6T-1682M on-chip UART
2216 */
2217 [pbn_pasemi_1682M] = {
2218 .flags = FL_BASE0,
2219 .num_ports = 1,
2220 .base_baud = 8333333,
2221 },
2222 /*
2223 * National Instruments 843x
2224 */
2225 [pbn_ni8430_16] = {
2226 .flags = FL_BASE0,
2227 .num_ports = 16,
2228 .base_baud = 3686400,
2229 .uart_offset = 0x10,
2230 .first_offset = 0x800,
2231 },
2232 [pbn_ni8430_8] = {
2233 .flags = FL_BASE0,
2234 .num_ports = 8,
2235 .base_baud = 3686400,
2236 .uart_offset = 0x10,
2237 .first_offset = 0x800,
2238 },
2239 [pbn_ni8430_4] = {
2240 .flags = FL_BASE0,
2241 .num_ports = 4,
2242 .base_baud = 3686400,
2243 .uart_offset = 0x10,
2244 .first_offset = 0x800,
2245 },
2246 [pbn_ni8430_2] = {
2247 .flags = FL_BASE0,
2248 .num_ports = 2,
2249 .base_baud = 3686400,
2250 .uart_offset = 0x10,
2251 .first_offset = 0x800,
2252 },
2253 /*
2254 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2255 */
2256 [pbn_ADDIDATA_PCIe_1_3906250] = {
2257 .flags = FL_BASE0,
2258 .num_ports = 1,
2259 .base_baud = 3906250,
2260 .uart_offset = 0x200,
2261 .first_offset = 0x1000,
2262 },
2263 [pbn_ADDIDATA_PCIe_2_3906250] = {
2264 .flags = FL_BASE0,
2265 .num_ports = 2,
2266 .base_baud = 3906250,
2267 .uart_offset = 0x200,
2268 .first_offset = 0x1000,
2269 },
2270 [pbn_ADDIDATA_PCIe_4_3906250] = {
2271 .flags = FL_BASE0,
2272 .num_ports = 4,
2273 .base_baud = 3906250,
2274 .uart_offset = 0x200,
2275 .first_offset = 0x1000,
2276 },
2277 [pbn_ADDIDATA_PCIe_8_3906250] = {
2278 .flags = FL_BASE0,
2279 .num_ports = 8,
2280 .base_baud = 3906250,
2281 .uart_offset = 0x200,
2282 .first_offset = 0x1000,
2283 },
2284};
2285
2286static const struct pci_device_id softmodem_blacklist[] = {
2287 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
2288};
2289
2290/*
2291 * Given a complete unknown PCI device, try to use some heuristics to
2292 * guess what the configuration might be, based on the pitiful PCI
2293 * serial specs. Returns 0 on success, 1 on failure.
2294 */
2295static int __devinit
2296serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
2297{
2298 const struct pci_device_id *blacklist;
2299 int num_iomem, num_port, first_port = -1, i;
2300
2301 /*
2302 * If it is not a communications device or the programming
2303 * interface is greater than 6, give up.
2304 *
2305 * (Should we try to make guesses for multiport serial devices
2306 * later?)
2307 */
2308 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2309 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2310 (dev->class & 0xff) > 6)
2311 return -ENODEV;
2312
2313 /*
2314 * Do not access blacklisted devices that are known not to
2315 * feature serial ports.
2316 */
2317 for (blacklist = softmodem_blacklist;
2318 blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2319 blacklist++) {
2320 if (dev->vendor == blacklist->vendor &&
2321 dev->device == blacklist->device)
2322 return -ENODEV;
2323 }
2324
2325 num_iomem = num_port = 0;
2326 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2327 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2328 num_port++;
2329 if (first_port == -1)
2330 first_port = i;
2331 }
2332 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2333 num_iomem++;
2334 }
2335
2336 /*
2337 * If there is 1 or 0 iomem regions, and exactly one port,
2338 * use it. We guess the number of ports based on the IO
2339 * region size.
2340 */
2341 if (num_iomem <= 1 && num_port == 1) {
2342 board->flags = first_port;
2343 board->num_ports = pci_resource_len(dev, first_port) / 8;
2344 return 0;
2345 }
2346
2347 /*
2348 * Now guess if we've got a board which indexes by BARs.
2349 * Each IO BAR should be 8 bytes, and they should follow
2350 * consecutively.
2351 */
2352 first_port = -1;
2353 num_port = 0;
2354 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2355 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2356 pci_resource_len(dev, i) == 8 &&
2357 (first_port == -1 || (first_port + num_port) == i)) {
2358 num_port++;
2359 if (first_port == -1)
2360 first_port = i;
2361 }
2362 }
2363
2364 if (num_port > 1) {
2365 board->flags = first_port | FL_BASE_BARS;
2366 board->num_ports = num_port;
2367 return 0;
2368 }
2369
2370 return -ENODEV;
2371}
2372
2373static inline int
2374serial_pci_matches(const struct pciserial_board *board,
2375 const struct pciserial_board *guessed)
2376{
2377 return
2378 board->num_ports == guessed->num_ports &&
2379 board->base_baud == guessed->base_baud &&
2380 board->uart_offset == guessed->uart_offset &&
2381 board->reg_shift == guessed->reg_shift &&
2382 board->first_offset == guessed->first_offset;
2383}
2384
2385struct serial_private *
2386pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
2387{
2388 struct uart_port serial_port;
2389 struct serial_private *priv;
2390 struct pci_serial_quirk *quirk;
2391 int rc, nr_ports, i;
2392
2393 nr_ports = board->num_ports;
2394
2395 /*
2396 * Find an init and setup quirks.
2397 */
2398 quirk = find_quirk(dev);
2399
2400 /*
2401 * Run the new-style initialization function.
2402 * The initialization function returns:
2403 * <0 - error
2404 * 0 - use board->num_ports
2405 * >0 - number of ports
2406 */
2407 if (quirk->init) {
2408 rc = quirk->init(dev);
2409 if (rc < 0) {
2410 priv = ERR_PTR(rc);
2411 goto err_out;
2412 }
2413 if (rc)
2414 nr_ports = rc;
2415 }
2416
2417 priv = kzalloc(sizeof(struct serial_private) +
2418 sizeof(unsigned int) * nr_ports,
2419 GFP_KERNEL);
2420 if (!priv) {
2421 priv = ERR_PTR(-ENOMEM);
2422 goto err_deinit;
2423 }
2424
2425 priv->dev = dev;
2426 priv->quirk = quirk;
2427
2428 memset(&serial_port, 0, sizeof(struct uart_port));
2429 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2430 serial_port.uartclk = board->base_baud * 16;
2431 serial_port.irq = get_pci_irq(dev, board);
2432 serial_port.dev = &dev->dev;
2433
2434 for (i = 0; i < nr_ports; i++) {
2435 if (quirk->setup(priv, board, &serial_port, i))
2436 break;
2437
2438#ifdef SERIAL_DEBUG_PCI
2439 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
2440 serial_port.iobase, serial_port.irq, serial_port.iotype);
2441#endif
2442
2443 priv->line[i] = serial8250_register_port(&serial_port);
2444 if (priv->line[i] < 0) {
2445 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2446 break;
2447 }
2448 }
2449 priv->nr = i;
2450 return priv;
2451
2452err_deinit:
2453 if (quirk->exit)
2454 quirk->exit(dev);
2455err_out:
2456 return priv;
2457}
2458EXPORT_SYMBOL_GPL(pciserial_init_ports);
2459
2460void pciserial_remove_ports(struct serial_private *priv)
2461{
2462 struct pci_serial_quirk *quirk;
2463 int i;
2464
2465 for (i = 0; i < priv->nr; i++)
2466 serial8250_unregister_port(priv->line[i]);
2467
2468 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2469 if (priv->remapped_bar[i])
2470 iounmap(priv->remapped_bar[i]);
2471 priv->remapped_bar[i] = NULL;
2472 }
2473
2474 /*
2475 * Find the exit quirks.
2476 */
2477 quirk = find_quirk(priv->dev);
2478 if (quirk->exit)
2479 quirk->exit(priv->dev);
2480
2481 kfree(priv);
2482}
2483EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2484
2485void pciserial_suspend_ports(struct serial_private *priv)
2486{
2487 int i;
2488
2489 for (i = 0; i < priv->nr; i++)
2490 if (priv->line[i] >= 0)
2491 serial8250_suspend_port(priv->line[i]);
2492}
2493EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2494
2495void pciserial_resume_ports(struct serial_private *priv)
2496{
2497 int i;
2498
2499 /*
2500 * Ensure that the board is correctly configured.
2501 */
2502 if (priv->quirk->init)
2503 priv->quirk->init(priv->dev);
2504
2505 for (i = 0; i < priv->nr; i++)
2506 if (priv->line[i] >= 0)
2507 serial8250_resume_port(priv->line[i]);
2508}
2509EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2510
2511/*
2512 * Probe one serial board. Unfortunately, there is no rhyme nor reason
2513 * to the arrangement of serial ports on a PCI card.
2514 */
2515static int __devinit
2516pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2517{
2518 struct serial_private *priv;
2519 const struct pciserial_board *board;
2520 struct pciserial_board tmp;
2521 int rc;
2522
2523 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2524 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2525 ent->driver_data);
2526 return -EINVAL;
2527 }
2528
2529 board = &pci_boards[ent->driver_data];
2530
2531 rc = pci_enable_device(dev);
2532 if (rc)
2533 return rc;
2534
2535 if (ent->driver_data == pbn_default) {
2536 /*
2537 * Use a copy of the pci_board entry for this;
2538 * avoid changing entries in the table.
2539 */
2540 memcpy(&tmp, board, sizeof(struct pciserial_board));
2541 board = &tmp;
2542
2543 /*
2544 * We matched one of our class entries. Try to
2545 * determine the parameters of this board.
2546 */
2547 rc = serial_pci_guess_board(dev, &tmp);
2548 if (rc)
2549 goto disable;
2550 } else {
2551 /*
2552 * We matched an explicit entry. If we are able to
2553 * detect this boards settings with our heuristic,
2554 * then we no longer need this entry.
2555 */
2556 memcpy(&tmp, &pci_boards[pbn_default],
2557 sizeof(struct pciserial_board));
2558 rc = serial_pci_guess_board(dev, &tmp);
2559 if (rc == 0 && serial_pci_matches(board, &tmp))
2560 moan_device("Redundant entry in serial pci_table.",
2561 dev);
2562 }
2563
2564 priv = pciserial_init_ports(dev, board);
2565 if (!IS_ERR(priv)) {
2566 pci_set_drvdata(dev, priv);
2567 return 0;
2568 }
2569
2570 rc = PTR_ERR(priv);
2571
2572 disable:
2573 pci_disable_device(dev);
2574 return rc;
2575}
2576
2577static void __devexit pciserial_remove_one(struct pci_dev *dev)
2578{
2579 struct serial_private *priv = pci_get_drvdata(dev);
2580
2581 pci_set_drvdata(dev, NULL);
2582
2583 pciserial_remove_ports(priv);
2584
2585 pci_disable_device(dev);
2586}
2587
2588#ifdef CONFIG_PM
2589static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2590{
2591 struct serial_private *priv = pci_get_drvdata(dev);
2592
2593 if (priv)
2594 pciserial_suspend_ports(priv);
2595
2596 pci_save_state(dev);
2597 pci_set_power_state(dev, pci_choose_state(dev, state));
2598 return 0;
2599}
2600
2601static int pciserial_resume_one(struct pci_dev *dev)
2602{
2603 int err;
2604 struct serial_private *priv = pci_get_drvdata(dev);
2605
2606 pci_set_power_state(dev, PCI_D0);
2607 pci_restore_state(dev);
2608
2609 if (priv) {
2610 /*
2611 * The device may have been disabled. Re-enable it.
2612 */
2613 err = pci_enable_device(dev);
2614 /* FIXME: We cannot simply error out here */
2615 if (err)
2616 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
2617 pciserial_resume_ports(priv);
2618 }
2619 return 0;
2620}
2621#endif
2622
2623static struct pci_device_id serial_pci_tbl[] = {
2624 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2625 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2626 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2627 pbn_b2_8_921600 },
2628 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2629 PCI_SUBVENDOR_ID_CONNECT_TECH,
2630 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2631 pbn_b1_8_1382400 },
2632 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2633 PCI_SUBVENDOR_ID_CONNECT_TECH,
2634 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2635 pbn_b1_4_1382400 },
2636 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2637 PCI_SUBVENDOR_ID_CONNECT_TECH,
2638 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2639 pbn_b1_2_1382400 },
2640 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2641 PCI_SUBVENDOR_ID_CONNECT_TECH,
2642 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2643 pbn_b1_8_1382400 },
2644 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2645 PCI_SUBVENDOR_ID_CONNECT_TECH,
2646 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2647 pbn_b1_4_1382400 },
2648 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2649 PCI_SUBVENDOR_ID_CONNECT_TECH,
2650 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2651 pbn_b1_2_1382400 },
2652 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2653 PCI_SUBVENDOR_ID_CONNECT_TECH,
2654 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2655 pbn_b1_8_921600 },
2656 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2657 PCI_SUBVENDOR_ID_CONNECT_TECH,
2658 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2659 pbn_b1_8_921600 },
2660 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2661 PCI_SUBVENDOR_ID_CONNECT_TECH,
2662 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2663 pbn_b1_4_921600 },
2664 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2665 PCI_SUBVENDOR_ID_CONNECT_TECH,
2666 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2667 pbn_b1_4_921600 },
2668 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2669 PCI_SUBVENDOR_ID_CONNECT_TECH,
2670 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2671 pbn_b1_2_921600 },
2672 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2673 PCI_SUBVENDOR_ID_CONNECT_TECH,
2674 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2675 pbn_b1_8_921600 },
2676 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2677 PCI_SUBVENDOR_ID_CONNECT_TECH,
2678 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2679 pbn_b1_8_921600 },
2680 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2681 PCI_SUBVENDOR_ID_CONNECT_TECH,
2682 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2683 pbn_b1_4_921600 },
2684 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2685 PCI_SUBVENDOR_ID_CONNECT_TECH,
2686 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2687 pbn_b1_2_1250000 },
2688 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2689 PCI_SUBVENDOR_ID_CONNECT_TECH,
2690 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2691 pbn_b0_2_1843200 },
2692 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2693 PCI_SUBVENDOR_ID_CONNECT_TECH,
2694 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2695 pbn_b0_4_1843200 },
2696 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2697 PCI_VENDOR_ID_AFAVLAB,
2698 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2699 pbn_b0_4_1152000 },
2700 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2701 PCI_SUBVENDOR_ID_CONNECT_TECH,
2702 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2703 pbn_b0_2_1843200_200 },
2704 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2705 PCI_SUBVENDOR_ID_CONNECT_TECH,
2706 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2707 pbn_b0_4_1843200_200 },
2708 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2709 PCI_SUBVENDOR_ID_CONNECT_TECH,
2710 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2711 pbn_b0_8_1843200_200 },
2712 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2713 PCI_SUBVENDOR_ID_CONNECT_TECH,
2714 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2715 pbn_b0_2_1843200_200 },
2716 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2717 PCI_SUBVENDOR_ID_CONNECT_TECH,
2718 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2719 pbn_b0_4_1843200_200 },
2720 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2721 PCI_SUBVENDOR_ID_CONNECT_TECH,
2722 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2723 pbn_b0_8_1843200_200 },
2724 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2725 PCI_SUBVENDOR_ID_CONNECT_TECH,
2726 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
2727 pbn_b0_2_1843200_200 },
2728 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2729 PCI_SUBVENDOR_ID_CONNECT_TECH,
2730 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
2731 pbn_b0_4_1843200_200 },
2732 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2733 PCI_SUBVENDOR_ID_CONNECT_TECH,
2734 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
2735 pbn_b0_8_1843200_200 },
2736 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2737 PCI_SUBVENDOR_ID_CONNECT_TECH,
2738 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
2739 pbn_b0_2_1843200_200 },
2740 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2741 PCI_SUBVENDOR_ID_CONNECT_TECH,
2742 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
2743 pbn_b0_4_1843200_200 },
2744 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2745 PCI_SUBVENDOR_ID_CONNECT_TECH,
2746 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
2747 pbn_b0_8_1843200_200 },
2748 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2749 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
2750 0, 0, pbn_exar_ibm_saturn },
2751
2752 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
2753 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2754 pbn_b2_bt_1_115200 },
2755 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
2756 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2757 pbn_b2_bt_2_115200 },
2758 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
2759 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2760 pbn_b2_bt_4_115200 },
2761 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
2762 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2763 pbn_b2_bt_2_115200 },
2764 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
2765 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2766 pbn_b2_bt_4_115200 },
2767 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
2768 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2769 pbn_b2_8_115200 },
2770 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
2771 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2772 pbn_b2_8_460800 },
2773 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
2774 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2775 pbn_b2_8_115200 },
2776
2777 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
2778 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2779 pbn_b2_bt_2_115200 },
2780 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
2781 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2782 pbn_b2_bt_2_921600 },
2783 /*
2784 * VScom SPCOM800, from sl@s.pl
2785 */
2786 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
2787 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2788 pbn_b2_8_921600 },
2789 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
2790 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2791 pbn_b2_4_921600 },
2792 /* Unknown card - subdevice 0x1584 */
2793 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2794 PCI_VENDOR_ID_PLX,
2795 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
2796 pbn_b0_4_115200 },
2797 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2798 PCI_SUBVENDOR_ID_KEYSPAN,
2799 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
2800 pbn_panacom },
2801 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
2802 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2803 pbn_panacom4 },
2804 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
2805 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2806 pbn_panacom2 },
2807 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2808 PCI_VENDOR_ID_ESDGMBH,
2809 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
2810 pbn_b2_4_115200 },
2811 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2812 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2813 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
2814 pbn_b2_4_460800 },
2815 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2816 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2817 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
2818 pbn_b2_8_460800 },
2819 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2820 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2821 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
2822 pbn_b2_16_460800 },
2823 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2824 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2825 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
2826 pbn_b2_16_460800 },
2827 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2828 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2829 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
2830 pbn_b2_4_460800 },
2831 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2832 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2833 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
2834 pbn_b2_8_460800 },
2835 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2836 PCI_SUBVENDOR_ID_EXSYS,
2837 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2838 pbn_exsys_4055 },
2839 /*
2840 * Megawolf Romulus PCI Serial Card, from Mike Hudson
2841 * (Exoray@isys.ca)
2842 */
2843 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2844 0x10b5, 0x106a, 0, 0,
2845 pbn_plx_romulus },
2846 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2847 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2848 pbn_b1_4_115200 },
2849 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2850 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2851 pbn_b1_2_115200 },
2852 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2853 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2854 pbn_b1_8_115200 },
2855 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2856 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2857 pbn_b1_8_115200 },
2858 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
2859 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
2860 0, 0,
2861 pbn_b0_4_921600 },
2862 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2863 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
2864 0, 0,
2865 pbn_b0_4_1152000 },
2866
2867 /*
2868 * The below card is a little controversial since it is the
2869 * subject of a PCI vendor/device ID clash. (See
2870 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2871 * For now just used the hex ID 0x950a.
2872 */
2873 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2874 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
2875 pbn_b0_2_115200 },
2876 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2877 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2878 pbn_b0_2_1130000 },
2879 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
2880 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
2881 pbn_b0_1_921600 },
2882 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2883 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2884 pbn_b0_4_115200 },
2885 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2886 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2887 pbn_b0_bt_2_921600 },
2888 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
2889 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
2890 pbn_b2_8_1152000 },
2891
2892 /*
2893 * Oxford Semiconductor Inc. Tornado PCI express device range.
2894 */
2895 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
2896 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2897 pbn_b0_1_4000000 },
2898 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
2899 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2900 pbn_b0_1_4000000 },
2901 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
2902 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2903 pbn_oxsemi_1_4000000 },
2904 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
2905 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2906 pbn_oxsemi_1_4000000 },
2907 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
2908 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2909 pbn_b0_1_4000000 },
2910 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
2911 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2912 pbn_b0_1_4000000 },
2913 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
2914 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2915 pbn_oxsemi_1_4000000 },
2916 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
2917 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2918 pbn_oxsemi_1_4000000 },
2919 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
2920 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2921 pbn_b0_1_4000000 },
2922 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
2923 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2924 pbn_b0_1_4000000 },
2925 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
2926 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2927 pbn_b0_1_4000000 },
2928 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
2929 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2930 pbn_b0_1_4000000 },
2931 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
2932 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2933 pbn_oxsemi_2_4000000 },
2934 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
2935 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2936 pbn_oxsemi_2_4000000 },
2937 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
2938 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2939 pbn_oxsemi_4_4000000 },
2940 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
2941 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2942 pbn_oxsemi_4_4000000 },
2943 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
2944 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2945 pbn_oxsemi_8_4000000 },
2946 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
2947 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2948 pbn_oxsemi_8_4000000 },
2949 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
2950 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2951 pbn_oxsemi_1_4000000 },
2952 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
2953 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2954 pbn_oxsemi_1_4000000 },
2955 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
2956 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2957 pbn_oxsemi_1_4000000 },
2958 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
2959 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2960 pbn_oxsemi_1_4000000 },
2961 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
2962 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2963 pbn_oxsemi_1_4000000 },
2964 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
2965 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2966 pbn_oxsemi_1_4000000 },
2967 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
2968 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2969 pbn_oxsemi_1_4000000 },
2970 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
2971 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2972 pbn_oxsemi_1_4000000 },
2973 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
2974 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2975 pbn_oxsemi_1_4000000 },
2976 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
2977 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2978 pbn_oxsemi_1_4000000 },
2979 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
2980 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2981 pbn_oxsemi_1_4000000 },
2982 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
2983 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2984 pbn_oxsemi_1_4000000 },
2985 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
2986 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2987 pbn_oxsemi_1_4000000 },
2988 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
2989 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2990 pbn_oxsemi_1_4000000 },
2991 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
2992 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2993 pbn_oxsemi_1_4000000 },
2994 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
2995 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2996 pbn_oxsemi_1_4000000 },
2997 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
2998 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2999 pbn_oxsemi_1_4000000 },
3000 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
3001 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3002 pbn_oxsemi_1_4000000 },
3003 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
3004 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3005 pbn_oxsemi_1_4000000 },
3006 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
3007 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3008 pbn_oxsemi_1_4000000 },
3009 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
3010 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3011 pbn_oxsemi_1_4000000 },
3012 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
3013 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3014 pbn_oxsemi_1_4000000 },
3015 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
3016 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3017 pbn_oxsemi_1_4000000 },
3018 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
3019 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3020 pbn_oxsemi_1_4000000 },
3021 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
3022 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3023 pbn_oxsemi_1_4000000 },
3024 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
3025 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3026 pbn_oxsemi_1_4000000 },
3027 /*
3028 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
3029 */
3030 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
3031 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
3032 pbn_oxsemi_1_4000000 },
3033 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
3034 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
3035 pbn_oxsemi_2_4000000 },
3036 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
3037 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
3038 pbn_oxsemi_4_4000000 },
3039 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
3040 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
3041 pbn_oxsemi_8_4000000 },
3042 /*
3043 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
3044 * from skokodyn@yahoo.com
3045 */
3046 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3047 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
3048 pbn_sbsxrsio },
3049 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3050 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
3051 pbn_sbsxrsio },
3052 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3053 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
3054 pbn_sbsxrsio },
3055 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3056 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3057 pbn_sbsxrsio },
3058
3059 /*
3060 * Digitan DS560-558, from jimd@esoft.com
3061 */
3062 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
3063 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3064 pbn_b1_1_115200 },
3065
3066 /*
3067 * Titan Electronic cards
3068 * The 400L and 800L have a custom setup quirk.
3069 */
3070 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
3071 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3072 pbn_b0_1_921600 },
3073 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
3074 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3075 pbn_b0_2_921600 },
3076 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
3077 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3078 pbn_b0_4_921600 },
3079 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
3080 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3081 pbn_b0_4_921600 },
3082 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3083 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3084 pbn_b1_1_921600 },
3085 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3086 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3087 pbn_b1_bt_2_921600 },
3088 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3089 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3090 pbn_b0_bt_4_921600 },
3091 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3092 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3093 pbn_b0_bt_8_921600 },
3094 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
3095 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3096 pbn_b4_bt_2_921600 },
3097 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
3098 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3099 pbn_b4_bt_4_921600 },
3100 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
3101 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3102 pbn_b4_bt_8_921600 },
3103 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
3104 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3105 pbn_b0_4_921600 },
3106 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
3107 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3108 pbn_b0_4_921600 },
3109 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
3110 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3111 pbn_b0_4_921600 },
3112 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
3113 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3114 pbn_oxsemi_1_4000000 },
3115 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
3116 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3117 pbn_oxsemi_2_4000000 },
3118 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
3119 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3120 pbn_oxsemi_4_4000000 },
3121 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
3122 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3123 pbn_oxsemi_8_4000000 },
3124 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
3125 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3126 pbn_oxsemi_2_4000000 },
3127 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
3128 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3129 pbn_oxsemi_2_4000000 },
3130
3131 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3132 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3133 pbn_b2_1_460800 },
3134 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3135 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3136 pbn_b2_1_460800 },
3137 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3138 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3139 pbn_b2_1_460800 },
3140 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3141 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3142 pbn_b2_bt_2_921600 },
3143 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3144 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3145 pbn_b2_bt_2_921600 },
3146 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3147 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3148 pbn_b2_bt_2_921600 },
3149 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3150 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3151 pbn_b2_bt_4_921600 },
3152 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3153 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3154 pbn_b2_bt_4_921600 },
3155 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3156 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3157 pbn_b2_bt_4_921600 },
3158 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3159 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3160 pbn_b0_1_921600 },
3161 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3162 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3163 pbn_b0_1_921600 },
3164 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3165 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3166 pbn_b0_1_921600 },
3167 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3168 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3169 pbn_b0_bt_2_921600 },
3170 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3171 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3172 pbn_b0_bt_2_921600 },
3173 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3174 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3175 pbn_b0_bt_2_921600 },
3176 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3177 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3178 pbn_b0_bt_4_921600 },
3179 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3180 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3181 pbn_b0_bt_4_921600 },
3182 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3183 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3184 pbn_b0_bt_4_921600 },
3185 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3186 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3187 pbn_b0_bt_8_921600 },
3188 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3189 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3190 pbn_b0_bt_8_921600 },
3191 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3192 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3193 pbn_b0_bt_8_921600 },
3194
3195 /*
3196 * Computone devices submitted by Doug McNash dmcnash@computone.com
3197 */
3198 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3199 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3200 0, 0, pbn_computone_4 },
3201 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3202 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3203 0, 0, pbn_computone_8 },
3204 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3205 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3206 0, 0, pbn_computone_6 },
3207
3208 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3209 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3210 pbn_oxsemi },
3211 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3212 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3213 pbn_b0_bt_1_921600 },
3214
3215 /*
3216 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3217 */
3218 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3219 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3220 pbn_b0_bt_8_115200 },
3221 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3222 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3223 pbn_b0_bt_8_115200 },
3224
3225 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3226 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3227 pbn_b0_bt_2_115200 },
3228 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3229 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3230 pbn_b0_bt_2_115200 },
3231 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3232 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3233 pbn_b0_bt_2_115200 },
3234 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
3235 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3236 pbn_b0_bt_2_115200 },
3237 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
3238 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3239 pbn_b0_bt_2_115200 },
3240 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3241 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3242 pbn_b0_bt_4_460800 },
3243 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3244 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3245 pbn_b0_bt_4_460800 },
3246 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3247 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3248 pbn_b0_bt_2_460800 },
3249 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3250 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3251 pbn_b0_bt_2_460800 },
3252 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3253 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3254 pbn_b0_bt_2_460800 },
3255 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3256 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3257 pbn_b0_bt_1_115200 },
3258 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3259 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3260 pbn_b0_bt_1_460800 },
3261
3262 /*
3263 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3264 * Cards are identified by their subsystem vendor IDs, which
3265 * (in hex) match the model number.
3266 *
3267 * Note that JC140x are RS422/485 cards which require ox950
3268 * ACR = 0x10, and as such are not currently fully supported.
3269 */
3270 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3271 0x1204, 0x0004, 0, 0,
3272 pbn_b0_4_921600 },
3273 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3274 0x1208, 0x0004, 0, 0,
3275 pbn_b0_4_921600 },
3276/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3277 0x1402, 0x0002, 0, 0,
3278 pbn_b0_2_921600 }, */
3279/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3280 0x1404, 0x0004, 0, 0,
3281 pbn_b0_4_921600 }, */
3282 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3283 0x1208, 0x0004, 0, 0,
3284 pbn_b0_4_921600 },
3285
3286 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3287 0x1204, 0x0004, 0, 0,
3288 pbn_b0_4_921600 },
3289 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3290 0x1208, 0x0004, 0, 0,
3291 pbn_b0_4_921600 },
3292 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
3293 0x1208, 0x0004, 0, 0,
3294 pbn_b0_4_921600 },
3295 /*
3296 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3297 */
3298 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3299 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3300 pbn_b1_1_1382400 },
3301
3302 /*
3303 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3304 */
3305 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3306 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3307 pbn_b1_1_1382400 },
3308
3309 /*
3310 * RAStel 2 port modem, gerg@moreton.com.au
3311 */
3312 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3313 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3314 pbn_b2_bt_2_115200 },
3315
3316 /*
3317 * EKF addition for i960 Boards form EKF with serial port
3318 */
3319 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3320 0xE4BF, PCI_ANY_ID, 0, 0,
3321 pbn_intel_i960 },
3322
3323 /*
3324 * Xircom Cardbus/Ethernet combos
3325 */
3326 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3327 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3328 pbn_b0_1_115200 },
3329 /*
3330 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3331 */
3332 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3333 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3334 pbn_b0_1_115200 },
3335
3336 /*
3337 * Untested PCI modems, sent in from various folks...
3338 */
3339
3340 /*
3341 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3342 */
3343 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
3344 0x1048, 0x1500, 0, 0,
3345 pbn_b1_1_115200 },
3346
3347 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3348 0xFF00, 0, 0, 0,
3349 pbn_sgi_ioc3 },
3350
3351 /*
3352 * HP Diva card
3353 */
3354 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3355 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3356 pbn_b1_1_115200 },
3357 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3358 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3359 pbn_b0_5_115200 },
3360 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3361 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3362 pbn_b2_1_115200 },
3363
3364 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3365 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3366 pbn_b3_2_115200 },
3367 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3368 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3369 pbn_b3_4_115200 },
3370 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3371 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3372 pbn_b3_8_115200 },
3373
3374 /*
3375 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3376 */
3377 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3378 PCI_ANY_ID, PCI_ANY_ID,
3379 0,
3380 0, pbn_exar_XR17C152 },
3381 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3382 PCI_ANY_ID, PCI_ANY_ID,
3383 0,
3384 0, pbn_exar_XR17C154 },
3385 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3386 PCI_ANY_ID, PCI_ANY_ID,
3387 0,
3388 0, pbn_exar_XR17C158 },
3389
3390 /*
3391 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3392 */
3393 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3394 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3395 pbn_b0_1_115200 },
3396 /*
3397 * ITE
3398 */
3399 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3400 PCI_ANY_ID, PCI_ANY_ID,
3401 0, 0,
3402 pbn_b1_bt_1_115200 },
3403
3404 /*
3405 * IntaShield IS-200
3406 */
3407 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3408 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
3409 pbn_b2_2_115200 },
3410 /*
3411 * IntaShield IS-400
3412 */
3413 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3414 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
3415 pbn_b2_4_115200 },
3416 /*
3417 * Perle PCI-RAS cards
3418 */
3419 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3420 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3421 0, 0, pbn_b2_4_921600 },
3422 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3423 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3424 0, 0, pbn_b2_8_921600 },
3425
3426 /*
3427 * Mainpine series cards: Fairly standard layout but fools
3428 * parts of the autodetect in some cases and uses otherwise
3429 * unmatched communications subclasses in the PCI Express case
3430 */
3431
3432 { /* RockForceDUO */
3433 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3434 PCI_VENDOR_ID_MAINPINE, 0x0200,
3435 0, 0, pbn_b0_2_115200 },
3436 { /* RockForceQUATRO */
3437 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3438 PCI_VENDOR_ID_MAINPINE, 0x0300,
3439 0, 0, pbn_b0_4_115200 },
3440 { /* RockForceDUO+ */
3441 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3442 PCI_VENDOR_ID_MAINPINE, 0x0400,
3443 0, 0, pbn_b0_2_115200 },
3444 { /* RockForceQUATRO+ */
3445 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3446 PCI_VENDOR_ID_MAINPINE, 0x0500,
3447 0, 0, pbn_b0_4_115200 },
3448 { /* RockForce+ */
3449 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3450 PCI_VENDOR_ID_MAINPINE, 0x0600,
3451 0, 0, pbn_b0_2_115200 },
3452 { /* RockForce+ */
3453 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3454 PCI_VENDOR_ID_MAINPINE, 0x0700,
3455 0, 0, pbn_b0_4_115200 },
3456 { /* RockForceOCTO+ */
3457 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3458 PCI_VENDOR_ID_MAINPINE, 0x0800,
3459 0, 0, pbn_b0_8_115200 },
3460 { /* RockForceDUO+ */
3461 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3462 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3463 0, 0, pbn_b0_2_115200 },
3464 { /* RockForceQUARTRO+ */
3465 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3466 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3467 0, 0, pbn_b0_4_115200 },
3468 { /* RockForceOCTO+ */
3469 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3470 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3471 0, 0, pbn_b0_8_115200 },
3472 { /* RockForceD1 */
3473 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3474 PCI_VENDOR_ID_MAINPINE, 0x2000,
3475 0, 0, pbn_b0_1_115200 },
3476 { /* RockForceF1 */
3477 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3478 PCI_VENDOR_ID_MAINPINE, 0x2100,
3479 0, 0, pbn_b0_1_115200 },
3480 { /* RockForceD2 */
3481 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3482 PCI_VENDOR_ID_MAINPINE, 0x2200,
3483 0, 0, pbn_b0_2_115200 },
3484 { /* RockForceF2 */
3485 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3486 PCI_VENDOR_ID_MAINPINE, 0x2300,
3487 0, 0, pbn_b0_2_115200 },
3488 { /* RockForceD4 */
3489 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3490 PCI_VENDOR_ID_MAINPINE, 0x2400,
3491 0, 0, pbn_b0_4_115200 },
3492 { /* RockForceF4 */
3493 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3494 PCI_VENDOR_ID_MAINPINE, 0x2500,
3495 0, 0, pbn_b0_4_115200 },
3496 { /* RockForceD8 */
3497 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3498 PCI_VENDOR_ID_MAINPINE, 0x2600,
3499 0, 0, pbn_b0_8_115200 },
3500 { /* RockForceF8 */
3501 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3502 PCI_VENDOR_ID_MAINPINE, 0x2700,
3503 0, 0, pbn_b0_8_115200 },
3504 { /* IQ Express D1 */
3505 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3506 PCI_VENDOR_ID_MAINPINE, 0x3000,
3507 0, 0, pbn_b0_1_115200 },
3508 { /* IQ Express F1 */
3509 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3510 PCI_VENDOR_ID_MAINPINE, 0x3100,
3511 0, 0, pbn_b0_1_115200 },
3512 { /* IQ Express D2 */
3513 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3514 PCI_VENDOR_ID_MAINPINE, 0x3200,
3515 0, 0, pbn_b0_2_115200 },
3516 { /* IQ Express F2 */
3517 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3518 PCI_VENDOR_ID_MAINPINE, 0x3300,
3519 0, 0, pbn_b0_2_115200 },
3520 { /* IQ Express D4 */
3521 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3522 PCI_VENDOR_ID_MAINPINE, 0x3400,
3523 0, 0, pbn_b0_4_115200 },
3524 { /* IQ Express F4 */
3525 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3526 PCI_VENDOR_ID_MAINPINE, 0x3500,
3527 0, 0, pbn_b0_4_115200 },
3528 { /* IQ Express D8 */
3529 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3530 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3531 0, 0, pbn_b0_8_115200 },
3532 { /* IQ Express F8 */
3533 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3534 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3535 0, 0, pbn_b0_8_115200 },
3536
3537
3538 /*
3539 * PA Semi PA6T-1682M on-chip UART
3540 */
3541 { PCI_VENDOR_ID_PASEMI, 0xa004,
3542 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3543 pbn_pasemi_1682M },
3544
3545 /*
3546 * National Instruments
3547 */
3548 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3549 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3550 pbn_b1_16_115200 },
3551 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3552 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3553 pbn_b1_8_115200 },
3554 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3555 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3556 pbn_b1_bt_4_115200 },
3557 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3558 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3559 pbn_b1_bt_2_115200 },
3560 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3561 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3562 pbn_b1_bt_4_115200 },
3563 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3564 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3565 pbn_b1_bt_2_115200 },
3566 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3567 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3568 pbn_b1_16_115200 },
3569 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3570 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3571 pbn_b1_8_115200 },
3572 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3573 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3574 pbn_b1_bt_4_115200 },
3575 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3576 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3577 pbn_b1_bt_2_115200 },
3578 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3579 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3580 pbn_b1_bt_4_115200 },
3581 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3582 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3583 pbn_b1_bt_2_115200 },
3584 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3585 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3586 pbn_ni8430_2 },
3587 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3588 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3589 pbn_ni8430_2 },
3590 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3591 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3592 pbn_ni8430_4 },
3593 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3594 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3595 pbn_ni8430_4 },
3596 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3597 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3598 pbn_ni8430_8 },
3599 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3600 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3601 pbn_ni8430_8 },
3602 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3603 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3604 pbn_ni8430_16 },
3605 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3606 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3607 pbn_ni8430_16 },
3608 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3609 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3610 pbn_ni8430_2 },
3611 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3612 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3613 pbn_ni8430_2 },
3614 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3615 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3616 pbn_ni8430_4 },
3617 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3618 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3619 pbn_ni8430_4 },
3620
3621 /*
3622 * ADDI-DATA GmbH communication cards <info@addi-data.com>
3623 */
3624 { PCI_VENDOR_ID_ADDIDATA,
3625 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3626 PCI_ANY_ID,
3627 PCI_ANY_ID,
3628 0,
3629 0,
3630 pbn_b0_4_115200 },
3631
3632 { PCI_VENDOR_ID_ADDIDATA,
3633 PCI_DEVICE_ID_ADDIDATA_APCI7420,
3634 PCI_ANY_ID,
3635 PCI_ANY_ID,
3636 0,
3637 0,
3638 pbn_b0_2_115200 },
3639
3640 { PCI_VENDOR_ID_ADDIDATA,
3641 PCI_DEVICE_ID_ADDIDATA_APCI7300,
3642 PCI_ANY_ID,
3643 PCI_ANY_ID,
3644 0,
3645 0,
3646 pbn_b0_1_115200 },
3647
3648 { PCI_VENDOR_ID_ADDIDATA_OLD,
3649 PCI_DEVICE_ID_ADDIDATA_APCI7800,
3650 PCI_ANY_ID,
3651 PCI_ANY_ID,
3652 0,
3653 0,
3654 pbn_b1_8_115200 },
3655
3656 { PCI_VENDOR_ID_ADDIDATA,
3657 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3658 PCI_ANY_ID,
3659 PCI_ANY_ID,
3660 0,
3661 0,
3662 pbn_b0_4_115200 },
3663
3664 { PCI_VENDOR_ID_ADDIDATA,
3665 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
3666 PCI_ANY_ID,
3667 PCI_ANY_ID,
3668 0,
3669 0,
3670 pbn_b0_2_115200 },
3671
3672 { PCI_VENDOR_ID_ADDIDATA,
3673 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
3674 PCI_ANY_ID,
3675 PCI_ANY_ID,
3676 0,
3677 0,
3678 pbn_b0_1_115200 },
3679
3680 { PCI_VENDOR_ID_ADDIDATA,
3681 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
3682 PCI_ANY_ID,
3683 PCI_ANY_ID,
3684 0,
3685 0,
3686 pbn_b0_4_115200 },
3687
3688 { PCI_VENDOR_ID_ADDIDATA,
3689 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
3690 PCI_ANY_ID,
3691 PCI_ANY_ID,
3692 0,
3693 0,
3694 pbn_b0_2_115200 },
3695
3696 { PCI_VENDOR_ID_ADDIDATA,
3697 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
3698 PCI_ANY_ID,
3699 PCI_ANY_ID,
3700 0,
3701 0,
3702 pbn_b0_1_115200 },
3703
3704 { PCI_VENDOR_ID_ADDIDATA,
3705 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
3706 PCI_ANY_ID,
3707 PCI_ANY_ID,
3708 0,
3709 0,
3710 pbn_b0_8_115200 },
3711
3712 { PCI_VENDOR_ID_ADDIDATA,
3713 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
3714 PCI_ANY_ID,
3715 PCI_ANY_ID,
3716 0,
3717 0,
3718 pbn_ADDIDATA_PCIe_4_3906250 },
3719
3720 { PCI_VENDOR_ID_ADDIDATA,
3721 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
3722 PCI_ANY_ID,
3723 PCI_ANY_ID,
3724 0,
3725 0,
3726 pbn_ADDIDATA_PCIe_2_3906250 },
3727
3728 { PCI_VENDOR_ID_ADDIDATA,
3729 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
3730 PCI_ANY_ID,
3731 PCI_ANY_ID,
3732 0,
3733 0,
3734 pbn_ADDIDATA_PCIe_1_3906250 },
3735
3736 { PCI_VENDOR_ID_ADDIDATA,
3737 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
3738 PCI_ANY_ID,
3739 PCI_ANY_ID,
3740 0,
3741 0,
3742 pbn_ADDIDATA_PCIe_8_3906250 },
3743
3744 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
3745 PCI_VENDOR_ID_IBM, 0x0299,
3746 0, 0, pbn_b0_bt_2_115200 },
3747
3748 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
3749 0xA000, 0x1000,
3750 0, 0, pbn_b0_1_115200 },
3751
3752 /*
3753 * Best Connectivity PCI Multi I/O cards
3754 */
3755
3756 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
3757 0xA000, 0x1000,
3758 0, 0, pbn_b0_1_115200 },
3759
3760 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
3761 0xA000, 0x3004,
3762 0, 0, pbn_b0_bt_4_115200 },
3763
3764 /*
3765 * These entries match devices with class COMMUNICATION_SERIAL,
3766 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
3767 */
3768 { PCI_ANY_ID, PCI_ANY_ID,
3769 PCI_ANY_ID, PCI_ANY_ID,
3770 PCI_CLASS_COMMUNICATION_SERIAL << 8,
3771 0xffff00, pbn_default },
3772 { PCI_ANY_ID, PCI_ANY_ID,
3773 PCI_ANY_ID, PCI_ANY_ID,
3774 PCI_CLASS_COMMUNICATION_MODEM << 8,
3775 0xffff00, pbn_default },
3776 { PCI_ANY_ID, PCI_ANY_ID,
3777 PCI_ANY_ID, PCI_ANY_ID,
3778 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
3779 0xffff00, pbn_default },
3780 { 0, }
3781};
3782
3783static struct pci_driver serial_pci_driver = {
3784 .name = "serial",
3785 .probe = pciserial_init_one,
3786 .remove = __devexit_p(pciserial_remove_one),
3787#ifdef CONFIG_PM
3788 .suspend = pciserial_suspend_one,
3789 .resume = pciserial_resume_one,
3790#endif
3791 .id_table = serial_pci_tbl,
3792};
3793
3794static int __init serial8250_pci_init(void)
3795{
3796 return pci_register_driver(&serial_pci_driver);
3797}
3798
3799static void __exit serial8250_pci_exit(void)
3800{
3801 pci_unregister_driver(&serial_pci_driver);
3802}
3803
3804module_init(serial8250_pci_init);
3805module_exit(serial8250_pci_exit);
3806
3807MODULE_LICENSE("GPL");
3808MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
3809MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
diff --git a/drivers/serial/8250_pnp.c b/drivers/serial/8250_pnp.c
deleted file mode 100644
index 4822cb50cd0f..000000000000
--- a/drivers/serial/8250_pnp.c
+++ /dev/null
@@ -1,523 +0,0 @@
1/*
2 * linux/drivers/char/8250_pnp.c
3 *
4 * Probe module for 8250/16550-type ISAPNP serial ports.
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
9 *
10 * Ported to the Linux PnP Layer - (C) Adam Belay.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License.
15 */
16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/pci.h>
19#include <linux/pnp.h>
20#include <linux/string.h>
21#include <linux/kernel.h>
22#include <linux/serial_core.h>
23#include <linux/bitops.h>
24
25#include <asm/byteorder.h>
26
27#include "8250.h"
28
29#define UNKNOWN_DEV 0x3000
30
31
32static const struct pnp_device_id pnp_dev_table[] = {
33 /* Archtek America Corp. */
34 /* Archtek SmartLink Modem 3334BT Plug & Play */
35 { "AAC000F", 0 },
36 /* Anchor Datacomm BV */
37 /* SXPro 144 External Data Fax Modem Plug & Play */
38 { "ADC0001", 0 },
39 /* SXPro 288 External Data Fax Modem Plug & Play */
40 { "ADC0002", 0 },
41 /* PROLiNK 1456VH ISA PnP K56flex Fax Modem */
42 { "AEI0250", 0 },
43 /* Actiontec ISA PNP 56K X2 Fax Modem */
44 { "AEI1240", 0 },
45 /* Rockwell 56K ACF II Fax+Data+Voice Modem */
46 { "AKY1021", 0 /*SPCI_FL_NO_SHIRQ*/ },
47 /* AZT3005 PnP SOUND DEVICE */
48 { "AZT4001", 0 },
49 /* Best Data Products Inc. Smart One 336F PnP Modem */
50 { "BDP3336", 0 },
51 /* Boca Research */
52 /* Boca Complete Ofc Communicator 14.4 Data-FAX */
53 { "BRI0A49", 0 },
54 /* Boca Research 33,600 ACF Modem */
55 { "BRI1400", 0 },
56 /* Boca 33.6 Kbps Internal FD34FSVD */
57 { "BRI3400", 0 },
58 /* Boca 33.6 Kbps Internal FD34FSVD */
59 { "BRI0A49", 0 },
60 /* Best Data Products Inc. Smart One 336F PnP Modem */
61 { "BDP3336", 0 },
62 /* Computer Peripherals Inc */
63 /* EuroViVa CommCenter-33.6 SP PnP */
64 { "CPI4050", 0 },
65 /* Creative Labs */
66 /* Creative Labs Phone Blaster 28.8 DSVD PnP Voice */
67 { "CTL3001", 0 },
68 /* Creative Labs Modem Blaster 28.8 DSVD PnP Voice */
69 { "CTL3011", 0 },
70 /* Davicom ISA 33.6K Modem */
71 { "DAV0336", 0 },
72 /* Creative */
73 /* Creative Modem Blaster Flash56 DI5601-1 */
74 { "DMB1032", 0 },
75 /* Creative Modem Blaster V.90 DI5660 */
76 { "DMB2001", 0 },
77 /* E-Tech */
78 /* E-Tech CyberBULLET PC56RVP */
79 { "ETT0002", 0 },
80 /* FUJITSU */
81 /* Fujitsu 33600 PnP-I2 R Plug & Play */
82 { "FUJ0202", 0 },
83 /* Fujitsu FMV-FX431 Plug & Play */
84 { "FUJ0205", 0 },
85 /* Fujitsu 33600 PnP-I4 R Plug & Play */
86 { "FUJ0206", 0 },
87 /* Fujitsu Fax Voice 33600 PNP-I5 R Plug & Play */
88 { "FUJ0209", 0 },
89 /* Archtek America Corp. */
90 /* Archtek SmartLink Modem 3334BT Plug & Play */
91 { "GVC000F", 0 },
92 /* Archtek SmartLink Modem 3334BRV 33.6K Data Fax Voice */
93 { "GVC0303", 0 },
94 /* Hayes */
95 /* Hayes Optima 288 V.34-V.FC + FAX + Voice Plug & Play */
96 { "HAY0001", 0 },
97 /* Hayes Optima 336 V.34 + FAX + Voice PnP */
98 { "HAY000C", 0 },
99 /* Hayes Optima 336B V.34 + FAX + Voice PnP */
100 { "HAY000D", 0 },
101 /* Hayes Accura 56K Ext Fax Modem PnP */
102 { "HAY5670", 0 },
103 /* Hayes Accura 56K Ext Fax Modem PnP */
104 { "HAY5674", 0 },
105 /* Hayes Accura 56K Fax Modem PnP */
106 { "HAY5675", 0 },
107 /* Hayes 288, V.34 + FAX */
108 { "HAYF000", 0 },
109 /* Hayes Optima 288 V.34 + FAX + Voice, Plug & Play */
110 { "HAYF001", 0 },
111 /* IBM */
112 /* IBM Thinkpad 701 Internal Modem Voice */
113 { "IBM0033", 0 },
114 /* Intertex */
115 /* Intertex 28k8 33k6 Voice EXT PnP */
116 { "IXDC801", 0 },
117 /* Intertex 33k6 56k Voice EXT PnP */
118 { "IXDC901", 0 },
119 /* Intertex 28k8 33k6 Voice SP EXT PnP */
120 { "IXDD801", 0 },
121 /* Intertex 33k6 56k Voice SP EXT PnP */
122 { "IXDD901", 0 },
123 /* Intertex 28k8 33k6 Voice SP INT PnP */
124 { "IXDF401", 0 },
125 /* Intertex 28k8 33k6 Voice SP EXT PnP */
126 { "IXDF801", 0 },
127 /* Intertex 33k6 56k Voice SP EXT PnP */
128 { "IXDF901", 0 },
129 /* Kortex International */
130 /* KORTEX 28800 Externe PnP */
131 { "KOR4522", 0 },
132 /* KXPro 33.6 Vocal ASVD PnP */
133 { "KORF661", 0 },
134 /* Lasat */
135 /* LASAT Internet 33600 PnP */
136 { "LAS4040", 0 },
137 /* Lasat Safire 560 PnP */
138 { "LAS4540", 0 },
139 /* Lasat Safire 336 PnP */
140 { "LAS5440", 0 },
141 /* Microcom, Inc. */
142 /* Microcom TravelPorte FAST V.34 Plug & Play */
143 { "MNP0281", 0 },
144 /* Microcom DeskPorte V.34 FAST or FAST+ Plug & Play */
145 { "MNP0336", 0 },
146 /* Microcom DeskPorte FAST EP 28.8 Plug & Play */
147 { "MNP0339", 0 },
148 /* Microcom DeskPorte 28.8P Plug & Play */
149 { "MNP0342", 0 },
150 /* Microcom DeskPorte FAST ES 28.8 Plug & Play */
151 { "MNP0500", 0 },
152 /* Microcom DeskPorte FAST ES 28.8 Plug & Play */
153 { "MNP0501", 0 },
154 /* Microcom DeskPorte 28.8S Internal Plug & Play */
155 { "MNP0502", 0 },
156 /* Motorola */
157 /* Motorola BitSURFR Plug & Play */
158 { "MOT1105", 0 },
159 /* Motorola TA210 Plug & Play */
160 { "MOT1111", 0 },
161 /* Motorola HMTA 200 (ISDN) Plug & Play */
162 { "MOT1114", 0 },
163 /* Motorola BitSURFR Plug & Play */
164 { "MOT1115", 0 },
165 /* Motorola Lifestyle 28.8 Internal */
166 { "MOT1190", 0 },
167 /* Motorola V.3400 Plug & Play */
168 { "MOT1501", 0 },
169 /* Motorola Lifestyle 28.8 V.34 Plug & Play */
170 { "MOT1502", 0 },
171 /* Motorola Power 28.8 V.34 Plug & Play */
172 { "MOT1505", 0 },
173 /* Motorola ModemSURFR External 28.8 Plug & Play */
174 { "MOT1509", 0 },
175 /* Motorola Premier 33.6 Desktop Plug & Play */
176 { "MOT150A", 0 },
177 /* Motorola VoiceSURFR 56K External PnP */
178 { "MOT150F", 0 },
179 /* Motorola ModemSURFR 56K External PnP */
180 { "MOT1510", 0 },
181 /* Motorola ModemSURFR 56K Internal PnP */
182 { "MOT1550", 0 },
183 /* Motorola ModemSURFR Internal 28.8 Plug & Play */
184 { "MOT1560", 0 },
185 /* Motorola Premier 33.6 Internal Plug & Play */
186 { "MOT1580", 0 },
187 /* Motorola OnlineSURFR 28.8 Internal Plug & Play */
188 { "MOT15B0", 0 },
189 /* Motorola VoiceSURFR 56K Internal PnP */
190 { "MOT15F0", 0 },
191 /* Com 1 */
192 /* Deskline K56 Phone System PnP */
193 { "MVX00A1", 0 },
194 /* PC Rider K56 Phone System PnP */
195 { "MVX00F2", 0 },
196 /* NEC 98NOTE SPEAKER PHONE FAX MODEM(33600bps) */
197 { "nEC8241", 0 },
198 /* Pace 56 Voice Internal Plug & Play Modem */
199 { "PMC2430", 0 },
200 /* Generic */
201 /* Generic standard PC COM port */
202 { "PNP0500", 0 },
203 /* Generic 16550A-compatible COM port */
204 { "PNP0501", 0 },
205 /* Compaq 14400 Modem */
206 { "PNPC000", 0 },
207 /* Compaq 2400/9600 Modem */
208 { "PNPC001", 0 },
209 /* Dial-Up Networking Serial Cable between 2 PCs */
210 { "PNPC031", 0 },
211 /* Dial-Up Networking Parallel Cable between 2 PCs */
212 { "PNPC032", 0 },
213 /* Standard 9600 bps Modem */
214 { "PNPC100", 0 },
215 /* Standard 14400 bps Modem */
216 { "PNPC101", 0 },
217 /* Standard 28800 bps Modem*/
218 { "PNPC102", 0 },
219 /* Standard Modem*/
220 { "PNPC103", 0 },
221 /* Standard 9600 bps Modem*/
222 { "PNPC104", 0 },
223 /* Standard 14400 bps Modem*/
224 { "PNPC105", 0 },
225 /* Standard 28800 bps Modem*/
226 { "PNPC106", 0 },
227 /* Standard Modem */
228 { "PNPC107", 0 },
229 /* Standard 9600 bps Modem */
230 { "PNPC108", 0 },
231 /* Standard 14400 bps Modem */
232 { "PNPC109", 0 },
233 /* Standard 28800 bps Modem */
234 { "PNPC10A", 0 },
235 /* Standard Modem */
236 { "PNPC10B", 0 },
237 /* Standard 9600 bps Modem */
238 { "PNPC10C", 0 },
239 /* Standard 14400 bps Modem */
240 { "PNPC10D", 0 },
241 /* Standard 28800 bps Modem */
242 { "PNPC10E", 0 },
243 /* Standard Modem */
244 { "PNPC10F", 0 },
245 /* Standard PCMCIA Card Modem */
246 { "PNP2000", 0 },
247 /* Rockwell */
248 /* Modular Technology */
249 /* Rockwell 33.6 DPF Internal PnP */
250 /* Modular Technology 33.6 Internal PnP */
251 { "ROK0030", 0 },
252 /* Kortex International */
253 /* KORTEX 14400 Externe PnP */
254 { "ROK0100", 0 },
255 /* Rockwell 28.8 */
256 { "ROK4120", 0 },
257 /* Viking Components, Inc */
258 /* Viking 28.8 INTERNAL Fax+Data+Voice PnP */
259 { "ROK4920", 0 },
260 /* Rockwell */
261 /* British Telecom */
262 /* Modular Technology */
263 /* Rockwell 33.6 DPF External PnP */
264 /* BT Prologue 33.6 External PnP */
265 /* Modular Technology 33.6 External PnP */
266 { "RSS00A0", 0 },
267 /* Viking 56K FAX INT */
268 { "RSS0262", 0 },
269 /* K56 par,VV,Voice,Speakphone,AudioSpan,PnP */
270 { "RSS0250", 0 },
271 /* SupraExpress 28.8 Data/Fax PnP modem */
272 { "SUP1310", 0 },
273 /* SupraExpress 336i PnP Voice Modem */
274 { "SUP1381", 0 },
275 /* SupraExpress 33.6 Data/Fax PnP modem */
276 { "SUP1421", 0 },
277 /* SupraExpress 33.6 Data/Fax PnP modem */
278 { "SUP1590", 0 },
279 /* SupraExpress 336i Sp ASVD */
280 { "SUP1620", 0 },
281 /* SupraExpress 33.6 Data/Fax PnP modem */
282 { "SUP1760", 0 },
283 /* SupraExpress 56i Sp Intl */
284 { "SUP2171", 0 },
285 /* Phoebe Micro */
286 /* Phoebe Micro 33.6 Data Fax 1433VQH Plug & Play */
287 { "TEX0011", 0 },
288 /* Archtek America Corp. */
289 /* Archtek SmartLink Modem 3334BT Plug & Play */
290 { "UAC000F", 0 },
291 /* 3Com Corp. */
292 /* Gateway Telepath IIvi 33.6 */
293 { "USR0000", 0 },
294 /* U.S. Robotics Sporster 33.6K Fax INT PnP */
295 { "USR0002", 0 },
296 /* Sportster Vi 14.4 PnP FAX Voicemail */
297 { "USR0004", 0 },
298 /* U.S. Robotics 33.6K Voice INT PnP */
299 { "USR0006", 0 },
300 /* U.S. Robotics 33.6K Voice EXT PnP */
301 { "USR0007", 0 },
302 /* U.S. Robotics Courier V.Everything INT PnP */
303 { "USR0009", 0 },
304 /* U.S. Robotics 33.6K Voice INT PnP */
305 { "USR2002", 0 },
306 /* U.S. Robotics 56K Voice INT PnP */
307 { "USR2070", 0 },
308 /* U.S. Robotics 56K Voice EXT PnP */
309 { "USR2080", 0 },
310 /* U.S. Robotics 56K FAX INT */
311 { "USR3031", 0 },
312 /* U.S. Robotics 56K FAX INT */
313 { "USR3050", 0 },
314 /* U.S. Robotics 56K Voice INT PnP */
315 { "USR3070", 0 },
316 /* U.S. Robotics 56K Voice EXT PnP */
317 { "USR3080", 0 },
318 /* U.S. Robotics 56K Voice INT PnP */
319 { "USR3090", 0 },
320 /* U.S. Robotics 56K Message */
321 { "USR9100", 0 },
322 /* U.S. Robotics 56K FAX EXT PnP*/
323 { "USR9160", 0 },
324 /* U.S. Robotics 56K FAX INT PnP*/
325 { "USR9170", 0 },
326 /* U.S. Robotics 56K Voice EXT PnP*/
327 { "USR9180", 0 },
328 /* U.S. Robotics 56K Voice INT PnP*/
329 { "USR9190", 0 },
330 /* Wacom tablets */
331 { "WACFXXX", 0 },
332 /* Compaq touchscreen */
333 { "FPI2002", 0 },
334 /* Fujitsu Stylistic touchscreens */
335 { "FUJ02B2", 0 },
336 { "FUJ02B3", 0 },
337 /* Fujitsu Stylistic LT touchscreens */
338 { "FUJ02B4", 0 },
339 /* Passive Fujitsu Stylistic touchscreens */
340 { "FUJ02B6", 0 },
341 { "FUJ02B7", 0 },
342 { "FUJ02B8", 0 },
343 { "FUJ02B9", 0 },
344 { "FUJ02BC", 0 },
345 /* Fujitsu Wacom Tablet PC device */
346 { "FUJ02E5", 0 },
347 /* Fujitsu P-series tablet PC device */
348 { "FUJ02E6", 0 },
349 /* Fujitsu Wacom 2FGT Tablet PC device */
350 { "FUJ02E7", 0 },
351 /* Fujitsu Wacom 1FGT Tablet PC device */
352 { "FUJ02E9", 0 },
353 /*
354 * LG C1 EXPRESS DUAL (C1-PB11A3) touch screen (actually a FUJ02E6 in
355 * disguise)
356 */
357 { "LTS0001", 0 },
358 /* Rockwell's (PORALiNK) 33600 INT PNP */
359 { "WCI0003", 0 },
360 /* Unknown PnP modems */
361 { "PNPCXXX", UNKNOWN_DEV },
362 /* More unknown PnP modems */
363 { "PNPDXXX", UNKNOWN_DEV },
364 { "", 0 }
365};
366
367MODULE_DEVICE_TABLE(pnp, pnp_dev_table);
368
369static char *modem_names[] __devinitdata = {
370 "MODEM", "Modem", "modem", "FAX", "Fax", "fax",
371 "56K", "56k", "K56", "33.6", "28.8", "14.4",
372 "33,600", "28,800", "14,400", "33.600", "28.800", "14.400",
373 "33600", "28800", "14400", "V.90", "V.34", "V.32", NULL
374};
375
376static int __devinit check_name(char *name)
377{
378 char **tmp;
379
380 for (tmp = modem_names; *tmp; tmp++)
381 if (strstr(name, *tmp))
382 return 1;
383
384 return 0;
385}
386
387static int __devinit check_resources(struct pnp_dev *dev)
388{
389 resource_size_t base[] = {0x2f8, 0x3f8, 0x2e8, 0x3e8};
390 int i;
391
392 for (i = 0; i < ARRAY_SIZE(base); i++) {
393 if (pnp_possible_config(dev, IORESOURCE_IO, base[i], 8))
394 return 1;
395 }
396
397 return 0;
398}
399
400/*
401 * Given a complete unknown PnP device, try to use some heuristics to
402 * detect modems. Currently use such heuristic set:
403 * - dev->name or dev->bus->name must contain "modem" substring;
404 * - device must have only one IO region (8 byte long) with base address
405 * 0x2e8, 0x3e8, 0x2f8 or 0x3f8.
406 *
407 * Such detection looks very ugly, but can detect at least some of numerous
408 * PnP modems, alternatively we must hardcode all modems in pnp_devices[]
409 * table.
410 */
411static int __devinit serial_pnp_guess_board(struct pnp_dev *dev, int *flags)
412{
413 if (!(check_name(pnp_dev_name(dev)) ||
414 (dev->card && check_name(dev->card->name))))
415 return -ENODEV;
416
417 if (check_resources(dev))
418 return 0;
419
420 return -ENODEV;
421}
422
423static int __devinit
424serial_pnp_probe(struct pnp_dev *dev, const struct pnp_device_id *dev_id)
425{
426 struct uart_port port;
427 int ret, line, flags = dev_id->driver_data;
428
429 if (flags & UNKNOWN_DEV) {
430 ret = serial_pnp_guess_board(dev, &flags);
431 if (ret < 0)
432 return ret;
433 }
434
435 memset(&port, 0, sizeof(struct uart_port));
436 if (pnp_irq_valid(dev, 0))
437 port.irq = pnp_irq(dev, 0);
438 if (pnp_port_valid(dev, 0)) {
439 port.iobase = pnp_port_start(dev, 0);
440 port.iotype = UPIO_PORT;
441 } else if (pnp_mem_valid(dev, 0)) {
442 port.mapbase = pnp_mem_start(dev, 0);
443 port.iotype = UPIO_MEM;
444 port.flags = UPF_IOREMAP;
445 } else
446 return -ENODEV;
447
448#ifdef SERIAL_DEBUG_PNP
449 printk(KERN_DEBUG
450 "Setup PNP port: port %x, mem 0x%lx, irq %d, type %d\n",
451 port.iobase, port.mapbase, port.irq, port.iotype);
452#endif
453
454 port.flags |= UPF_SKIP_TEST | UPF_BOOT_AUTOCONF;
455 if (pnp_irq_flags(dev, 0) & IORESOURCE_IRQ_SHAREABLE)
456 port.flags |= UPF_SHARE_IRQ;
457 port.uartclk = 1843200;
458 port.dev = &dev->dev;
459
460 line = serial8250_register_port(&port);
461 if (line < 0)
462 return -ENODEV;
463
464 pnp_set_drvdata(dev, (void *)((long)line + 1));
465 return 0;
466}
467
468static void __devexit serial_pnp_remove(struct pnp_dev *dev)
469{
470 long line = (long)pnp_get_drvdata(dev);
471 if (line)
472 serial8250_unregister_port(line - 1);
473}
474
475#ifdef CONFIG_PM
476static int serial_pnp_suspend(struct pnp_dev *dev, pm_message_t state)
477{
478 long line = (long)pnp_get_drvdata(dev);
479
480 if (!line)
481 return -ENODEV;
482 serial8250_suspend_port(line - 1);
483 return 0;
484}
485
486static int serial_pnp_resume(struct pnp_dev *dev)
487{
488 long line = (long)pnp_get_drvdata(dev);
489
490 if (!line)
491 return -ENODEV;
492 serial8250_resume_port(line - 1);
493 return 0;
494}
495#else
496#define serial_pnp_suspend NULL
497#define serial_pnp_resume NULL
498#endif /* CONFIG_PM */
499
500static struct pnp_driver serial_pnp_driver = {
501 .name = "serial",
502 .probe = serial_pnp_probe,
503 .remove = __devexit_p(serial_pnp_remove),
504 .suspend = serial_pnp_suspend,
505 .resume = serial_pnp_resume,
506 .id_table = pnp_dev_table,
507};
508
509static int __init serial8250_pnp_init(void)
510{
511 return pnp_register_driver(&serial_pnp_driver);
512}
513
514static void __exit serial8250_pnp_exit(void)
515{
516 pnp_unregister_driver(&serial_pnp_driver);
517}
518
519module_init(serial8250_pnp_init);
520module_exit(serial8250_pnp_exit);
521
522MODULE_LICENSE("GPL");
523MODULE_DESCRIPTION("Generic 8250/16x50 PnP serial driver");
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
deleted file mode 100644
index 12900f7083b0..000000000000
--- a/drivers/serial/Kconfig
+++ /dev/null
@@ -1,1614 +0,0 @@
1#
2# Serial device configuration
3#
4
5menu "Serial drivers"
6 depends on HAS_IOMEM
7
8#
9# The new 8250/16550 serial drivers
10config SERIAL_8250
11 tristate "8250/16550 and compatible serial support"
12 select SERIAL_CORE
13 ---help---
14 This selects whether you want to include the driver for the standard
15 serial ports. The standard answer is Y. People who might say N
16 here are those that are setting up dedicated Ethernet WWW/FTP
17 servers, or users that have one of the various bus mice instead of a
18 serial mouse and don't intend to use their machine's standard serial
19 port for anything. (Note that the Cyclades and Stallion multi
20 serial port drivers do not need this driver built in for them to
21 work.)
22
23 To compile this driver as a module, choose M here: the
24 module will be called 8250.
25 [WARNING: Do not compile this driver as a module if you are using
26 non-standard serial ports, since the configuration information will
27 be lost when the driver is unloaded. This limitation may be lifted
28 in the future.]
29
30 BTW1: If you have a mouseman serial mouse which is not recognized by
31 the X window system, try running gpm first.
32
33 BTW2: If you intend to use a software modem (also called Winmodem)
34 under Linux, forget it. These modems are crippled and require
35 proprietary drivers which are only available under Windows.
36
37 Most people will say Y or M here, so that they can use serial mice,
38 modems and similar devices connecting to the standard serial ports.
39
40config SERIAL_8250_CONSOLE
41 bool "Console on 8250/16550 and compatible serial port"
42 depends on SERIAL_8250=y
43 select SERIAL_CORE_CONSOLE
44 ---help---
45 If you say Y here, it will be possible to use a serial port as the
46 system console (the system console is the device which receives all
47 kernel messages and warnings and which allows logins in single user
48 mode). This could be useful if some terminal or printer is connected
49 to that serial port.
50
51 Even if you say Y here, the currently visible virtual console
52 (/dev/tty0) will still be used as the system console by default, but
53 you can alter that using a kernel command line option such as
54 "console=ttyS1". (Try "man bootparam" or see the documentation of
55 your boot loader (grub or lilo or loadlin) about how to pass options
56 to the kernel at boot time.)
57
58 If you don't have a VGA card installed and you say Y here, the
59 kernel will automatically use the first serial line, /dev/ttyS0, as
60 system console.
61
62 You can set that using a kernel command line option such as
63 "console=uart8250,io,0x3f8,9600n8"
64 "console=uart8250,mmio,0xff5e0000,115200n8".
65 and it will switch to normal serial console when the corresponding
66 port is ready.
67 "earlycon=uart8250,io,0x3f8,9600n8"
68 "earlycon=uart8250,mmio,0xff5e0000,115200n8".
69 it will not only setup early console.
70
71 If unsure, say N.
72
73config FIX_EARLYCON_MEM
74 bool
75 depends on X86
76 default y
77
78config SERIAL_8250_GSC
79 tristate
80 depends on SERIAL_8250 && GSC
81 default SERIAL_8250
82
83config SERIAL_8250_PCI
84 tristate "8250/16550 PCI device support" if EMBEDDED
85 depends on SERIAL_8250 && PCI
86 default SERIAL_8250
87 help
88 This builds standard PCI serial support. You may be able to
89 disable this feature if you only need legacy serial support.
90 Saves about 9K.
91
92config SERIAL_8250_PNP
93 tristate "8250/16550 PNP device support" if EMBEDDED
94 depends on SERIAL_8250 && PNP
95 default SERIAL_8250
96 help
97 This builds standard PNP serial support. You may be able to
98 disable this feature if you only need legacy serial support.
99
100config SERIAL_8250_HP300
101 tristate
102 depends on SERIAL_8250 && HP300
103 default SERIAL_8250
104
105config SERIAL_8250_CS
106 tristate "8250/16550 PCMCIA device support"
107 depends on PCMCIA && SERIAL_8250
108 ---help---
109 Say Y here to enable support for 16-bit PCMCIA serial devices,
110 including serial port cards, modems, and the modem functions of
111 multi-function Ethernet/modem cards. (PCMCIA- or PC-cards are
112 credit-card size devices often used with laptops.)
113
114 To compile this driver as a module, choose M here: the
115 module will be called serial_cs.
116
117 If unsure, say N.
118
119config SERIAL_8250_NR_UARTS
120 int "Maximum number of 8250/16550 serial ports"
121 depends on SERIAL_8250
122 default "4"
123 help
124 Set this to the number of serial ports you want the driver
125 to support. This includes any ports discovered via ACPI or
126 PCI enumeration and any ports that may be added at run-time
127 via hot-plug, or any ISA multi-port serial cards.
128
129config SERIAL_8250_RUNTIME_UARTS
130 int "Number of 8250/16550 serial ports to register at runtime"
131 depends on SERIAL_8250
132 range 0 SERIAL_8250_NR_UARTS
133 default "4"
134 help
135 Set this to the maximum number of serial ports you want
136 the kernel to register at boot time. This can be overridden
137 with the module parameter "nr_uarts", or boot-time parameter
138 8250.nr_uarts
139
140config SERIAL_8250_EXTENDED
141 bool "Extended 8250/16550 serial driver options"
142 depends on SERIAL_8250
143 help
144 If you wish to use any non-standard features of the standard "dumb"
145 driver, say Y here. This includes HUB6 support, shared serial
146 interrupts, special multiport support, support for more than the
147 four COM 1/2/3/4 boards, etc.
148
149 Note that the answer to this question won't directly affect the
150 kernel: saying N will just cause the configurator to skip all
151 the questions about serial driver options. If unsure, say N.
152
153config SERIAL_8250_MANY_PORTS
154 bool "Support more than 4 legacy serial ports"
155 depends on SERIAL_8250_EXTENDED && !IA64
156 help
157 Say Y here if you have dumb serial boards other than the four
158 standard COM 1/2/3/4 ports. This may happen if you have an AST
159 FourPort, Accent Async, Boca (read the Boca mini-HOWTO, available
160 from <http://www.tldp.org/docs.html#howto>), or other custom
161 serial port hardware which acts similar to standard serial port
162 hardware. If you only use the standard COM 1/2/3/4 ports, you can
163 say N here to save some memory. You can also say Y if you have an
164 "intelligent" multiport card such as Cyclades, Digiboards, etc.
165
166#
167# Multi-port serial cards
168#
169
170config SERIAL_8250_FOURPORT
171 tristate "Support Fourport cards"
172 depends on SERIAL_8250 != n && ISA && SERIAL_8250_MANY_PORTS
173 help
174 Say Y here if you have an AST FourPort serial board.
175
176 To compile this driver as a module, choose M here: the module
177 will be called 8250_fourport.
178
179config SERIAL_8250_ACCENT
180 tristate "Support Accent cards"
181 depends on SERIAL_8250 != n && ISA && SERIAL_8250_MANY_PORTS
182 help
183 Say Y here if you have an Accent Async serial board.
184
185 To compile this driver as a module, choose M here: the module
186 will be called 8250_accent.
187
188config SERIAL_8250_BOCA
189 tristate "Support Boca cards"
190 depends on SERIAL_8250 != n && ISA && SERIAL_8250_MANY_PORTS
191 help
192 Say Y here if you have a Boca serial board. Please read the Boca
193 mini-HOWTO, available from <http://www.tldp.org/docs.html#howto>
194
195 To compile this driver as a module, choose M here: the module
196 will be called 8250_boca.
197
198config SERIAL_8250_EXAR_ST16C554
199 tristate "Support Exar ST16C554/554D Quad UART"
200 depends on SERIAL_8250 != n && ISA && SERIAL_8250_MANY_PORTS
201 help
202 The Uplogix Envoy TU301 uses this Exar Quad UART. If you are
203 tinkering with your Envoy TU301, or have a machine with this UART,
204 say Y here.
205
206 To compile this driver as a module, choose M here: the module
207 will be called 8250_exar_st16c554.
208
209config SERIAL_8250_HUB6
210 tristate "Support Hub6 cards"
211 depends on SERIAL_8250 != n && ISA && SERIAL_8250_MANY_PORTS
212 help
213 Say Y here if you have a HUB6 serial board.
214
215 To compile this driver as a module, choose M here: the module
216 will be called 8250_hub6.
217
218config SERIAL_8250_SHARE_IRQ
219 bool "Support for sharing serial interrupts"
220 depends on SERIAL_8250_EXTENDED
221 help
222 Some serial boards have hardware support which allows multiple dumb
223 serial ports on the same board to share a single IRQ. To enable
224 support for this in the serial driver, say Y here.
225
226config SERIAL_8250_DETECT_IRQ
227 bool "Autodetect IRQ on standard ports (unsafe)"
228 depends on SERIAL_8250_EXTENDED
229 help
230 Say Y here if you want the kernel to try to guess which IRQ
231 to use for your serial port.
232
233 This is considered unsafe; it is far better to configure the IRQ in
234 a boot script using the setserial command.
235
236 If unsure, say N.
237
238config SERIAL_8250_RSA
239 bool "Support RSA serial ports"
240 depends on SERIAL_8250_EXTENDED
241 help
242 ::: To be written :::
243
244config SERIAL_8250_MCA
245 tristate "Support 8250-type ports on MCA buses"
246 depends on SERIAL_8250 != n && MCA
247 help
248 Say Y here if you have a MCA serial ports.
249
250 To compile this driver as a module, choose M here: the module
251 will be called 8250_mca.
252
253config SERIAL_8250_ACORN
254 tristate "Acorn expansion card serial port support"
255 depends on ARCH_ACORN && SERIAL_8250
256 help
257 If you have an Atomwide Serial card or Serial Port card for an Acorn
258 system, say Y to this option. The driver can handle 1, 2, or 3 port
259 cards. If unsure, say N.
260
261config SERIAL_8250_RM9K
262 bool "Support for MIPS RM9xxx integrated serial port"
263 depends on SERIAL_8250 != n && SERIAL_RM9000
264 select SERIAL_8250_SHARE_IRQ
265 help
266 Selecting this option will add support for the integrated serial
267 port hardware found on MIPS RM9122 and similar processors.
268 If unsure, say N.
269
270comment "Non-8250 serial port support"
271
272config SERIAL_AMBA_PL010
273 tristate "ARM AMBA PL010 serial port support"
274 depends on ARM_AMBA && (BROKEN || !ARCH_VERSATILE)
275 select SERIAL_CORE
276 help
277 This selects the ARM(R) AMBA(R) PrimeCell PL010 UART. If you have
278 an Integrator/AP or Integrator/PP2 platform, or if you have a
279 Cirrus Logic EP93xx CPU, say Y or M here.
280
281 If unsure, say N.
282
283config SERIAL_AMBA_PL010_CONSOLE
284 bool "Support for console on AMBA serial port"
285 depends on SERIAL_AMBA_PL010=y
286 select SERIAL_CORE_CONSOLE
287 ---help---
288 Say Y here if you wish to use an AMBA PrimeCell UART as the system
289 console (the system console is the device which receives all kernel
290 messages and warnings and which allows logins in single user mode).
291
292 Even if you say Y here, the currently visible framebuffer console
293 (/dev/tty0) will still be used as the system console by default, but
294 you can alter that using a kernel command line option such as
295 "console=ttyAM0". (Try "man bootparam" or see the documentation of
296 your boot loader (lilo or loadlin) about how to pass options to the
297 kernel at boot time.)
298
299config SERIAL_AMBA_PL011
300 tristate "ARM AMBA PL011 serial port support"
301 depends on ARM_AMBA
302 select SERIAL_CORE
303 help
304 This selects the ARM(R) AMBA(R) PrimeCell PL011 UART. If you have
305 an Integrator/PP2, Integrator/CP or Versatile platform, say Y or M
306 here.
307
308 If unsure, say N.
309
310config SERIAL_AMBA_PL011_CONSOLE
311 bool "Support for console on AMBA serial port"
312 depends on SERIAL_AMBA_PL011=y
313 select SERIAL_CORE_CONSOLE
314 ---help---
315 Say Y here if you wish to use an AMBA PrimeCell UART as the system
316 console (the system console is the device which receives all kernel
317 messages and warnings and which allows logins in single user mode).
318
319 Even if you say Y here, the currently visible framebuffer console
320 (/dev/tty0) will still be used as the system console by default, but
321 you can alter that using a kernel command line option such as
322 "console=ttyAMA0". (Try "man bootparam" or see the documentation of
323 your boot loader (lilo or loadlin) about how to pass options to the
324 kernel at boot time.)
325
326config SERIAL_SB1250_DUART
327 tristate "BCM1xxx on-chip DUART serial support"
328 depends on SIBYTE_SB1xxx_SOC=y
329 select SERIAL_CORE
330 default y
331 ---help---
332 Support for the asynchronous serial interface (DUART) included in
333 the BCM1250 and derived System-On-a-Chip (SOC) devices. Note that
334 the letter D in DUART stands for "dual", which is how the device
335 is implemented. Depending on the SOC configuration there may be
336 one or more DUARTs available of which all are handled.
337
338 If unsure, say Y. To compile this driver as a module, choose M here:
339 the module will be called sb1250-duart.
340
341config SERIAL_SB1250_DUART_CONSOLE
342 bool "Support for console on a BCM1xxx DUART serial port"
343 depends on SERIAL_SB1250_DUART=y
344 select SERIAL_CORE_CONSOLE
345 default y
346 ---help---
347 If you say Y here, it will be possible to use a serial port as the
348 system console (the system console is the device which receives all
349 kernel messages and warnings and which allows logins in single user
350 mode).
351
352 If unsure, say Y.
353
354config SERIAL_ATMEL
355 bool "AT91 / AT32 on-chip serial port support"
356 depends on (ARM && ARCH_AT91) || AVR32
357 select SERIAL_CORE
358 help
359 This enables the driver for the on-chip UARTs of the Atmel
360 AT91 and AT32 processors.
361
362config SERIAL_ATMEL_CONSOLE
363 bool "Support for console on AT91 / AT32 serial port"
364 depends on SERIAL_ATMEL=y
365 select SERIAL_CORE_CONSOLE
366 help
367 Say Y here if you wish to use an on-chip UART on a Atmel
368 AT91 or AT32 processor as the system console (the system
369 console is the device which receives all kernel messages and
370 warnings and which allows logins in single user mode).
371
372config SERIAL_ATMEL_PDC
373 bool "Support DMA transfers on AT91 / AT32 serial port"
374 depends on SERIAL_ATMEL
375 default y
376 help
377 Say Y here if you wish to use the PDC to do DMA transfers to
378 and from the Atmel AT91 / AT32 serial port. In order to
379 actually use DMA transfers, make sure that the use_dma_tx
380 and use_dma_rx members in the atmel_uart_data struct is set
381 appropriately for each port.
382
383 Note that break and error handling currently doesn't work
384 properly when DMA is enabled. Make sure that ports where
385 this matters don't use DMA.
386
387config SERIAL_ATMEL_TTYAT
388 bool "Install as device ttyATn instead of ttySn"
389 depends on SERIAL_ATMEL=y
390 help
391 Say Y here if you wish to have the internal AT91 / AT32 UARTs
392 appear as /dev/ttyATn (major 204, minor starting at 154)
393 instead of the normal /dev/ttySn (major 4, minor starting at
394 64). This is necessary if you also want other UARTs, such as
395 external 8250/16C550 compatible UARTs.
396 The ttySn nodes are legally reserved for the 8250 serial driver
397 but are often misused by other serial drivers.
398
399 To use this, you should create suitable ttyATn device nodes in
400 /dev/, and pass "console=ttyATn" to the kernel.
401
402 Say Y if you have an external 8250/16C550 UART. If unsure, say N.
403
404config SERIAL_KS8695
405 bool "Micrel KS8695 (Centaur) serial port support"
406 depends on ARCH_KS8695
407 select SERIAL_CORE
408 help
409 This selects the Micrel Centaur KS8695 UART. Say Y here.
410
411config SERIAL_KS8695_CONSOLE
412 bool "Support for console on KS8695 (Centaur) serial port"
413 depends on SERIAL_KS8695=y
414 select SERIAL_CORE_CONSOLE
415 help
416 Say Y here if you wish to use a KS8695 (Centaur) UART as the
417 system console (the system console is the device which
418 receives all kernel messages and warnings and which allows
419 logins in single user mode).
420
421config SERIAL_CLPS711X
422 tristate "CLPS711X serial port support"
423 depends on ARM && ARCH_CLPS711X
424 select SERIAL_CORE
425 help
426 ::: To be written :::
427
428config SERIAL_CLPS711X_CONSOLE
429 bool "Support for console on CLPS711X serial port"
430 depends on SERIAL_CLPS711X=y
431 select SERIAL_CORE_CONSOLE
432 help
433 Even if you say Y here, the currently visible virtual console
434 (/dev/tty0) will still be used as the system console by default, but
435 you can alter that using a kernel command line option such as
436 "console=ttyCL1". (Try "man bootparam" or see the documentation of
437 your boot loader (lilo or loadlin) about how to pass options to the
438 kernel at boot time.)
439
440config SERIAL_SAMSUNG
441 tristate "Samsung SoC serial support"
442 depends on ARM && PLAT_SAMSUNG
443 select SERIAL_CORE
444 help
445 Support for the on-chip UARTs on the Samsung S3C24XX series CPUs,
446 providing /dev/ttySAC0, 1 and 2 (note, some machines may not
447 provide all of these ports, depending on how the serial port
448 pins are configured.
449
450config SERIAL_SAMSUNG_UARTS_4
451 bool
452 depends on ARM && PLAT_SAMSUNG
453 default y if CPU_S3C2443
454 help
455 Internal node for the common case of 4 Samsung compatible UARTs
456
457config SERIAL_SAMSUNG_UARTS
458 int
459 depends on ARM && PLAT_SAMSUNG
460 default 2 if ARCH_S3C2400
461 default 4 if SERIAL_SAMSUNG_UARTS_4
462 default 3
463 help
464 Select the number of available UART ports for the Samsung S3C
465 serial driver
466
467config SERIAL_SAMSUNG_DEBUG
468 bool "Samsung SoC serial debug"
469 depends on SERIAL_SAMSUNG && DEBUG_LL
470 help
471 Add support for debugging the serial driver. Since this is
472 generally being used as a console, we use our own output
473 routines that go via the low-level debug printascii()
474 function.
475
476config SERIAL_SAMSUNG_CONSOLE
477 bool "Support for console on Samsung SoC serial port"
478 depends on SERIAL_SAMSUNG=y
479 select SERIAL_CORE_CONSOLE
480 help
481 Allow selection of the S3C24XX on-board serial ports for use as
482 an virtual console.
483
484 Even if you say Y here, the currently visible virtual console
485 (/dev/tty0) will still be used as the system console by default, but
486 you can alter that using a kernel command line option such as
487 "console=ttySACx". (Try "man bootparam" or see the documentation of
488 your boot loader about how to pass options to the kernel at
489 boot time.)
490
491config SERIAL_S3C2400
492 tristate "Samsung S3C2410 Serial port support"
493 depends on ARM && SERIAL_SAMSUNG && CPU_S3C2400
494 default y if CPU_S3C2400
495 help
496 Serial port support for the Samsung S3C2400 SoC
497
498config SERIAL_S3C2410
499 tristate "Samsung S3C2410 Serial port support"
500 depends on SERIAL_SAMSUNG && CPU_S3C2410
501 default y if CPU_S3C2410
502 help
503 Serial port support for the Samsung S3C2410 SoC
504
505config SERIAL_S3C2412
506 tristate "Samsung S3C2412/S3C2413 Serial port support"
507 depends on SERIAL_SAMSUNG && CPU_S3C2412
508 default y if CPU_S3C2412
509 help
510 Serial port support for the Samsung S3C2412 and S3C2413 SoC
511
512config SERIAL_S3C2440
513 tristate "Samsung S3C2440/S3C2442/S3C2416 Serial port support"
514 depends on SERIAL_SAMSUNG && (CPU_S3C2440 || CPU_S3C2442 || CPU_S3C2416)
515 default y if CPU_S3C2440
516 default y if CPU_S3C2442
517 select SERIAL_SAMSUNG_UARTS_4 if CPU_S3C2416
518 help
519 Serial port support for the Samsung S3C2440, S3C2416 and S3C2442 SoC
520
521config SERIAL_S3C24A0
522 tristate "Samsung S3C24A0 Serial port support"
523 depends on SERIAL_SAMSUNG && CPU_S3C24A0
524 default y if CPU_S3C24A0
525 help
526 Serial port support for the Samsung S3C24A0 SoC
527
528config SERIAL_S3C6400
529 tristate "Samsung S3C6400/S3C6410/S5P6440/S5PC100 Serial port support"
530 depends on SERIAL_SAMSUNG && (CPU_S3C6400 || CPU_S3C6410 || CPU_S5P6440 || CPU_S5PC100)
531 select SERIAL_SAMSUNG_UARTS_4
532 default y
533 help
534 Serial port support for the Samsung S3C6400, S3C6410, S5P6440
535 and S5PC100 SoCs
536
537config SERIAL_S5PV210
538 tristate "Samsung S5PV210 Serial port support"
539 depends on SERIAL_SAMSUNG && (CPU_S5PV210 || CPU_S5P6442 || CPU_S5PV310)
540 select SERIAL_SAMSUNG_UARTS_4 if (CPU_S5PV210 || CPU_S5PV310)
541 default y
542 help
543 Serial port support for Samsung's S5P Family of SoC's
544
545
546config SERIAL_MAX3100
547 tristate "MAX3100 support"
548 depends on SPI
549 select SERIAL_CORE
550 help
551 MAX3100 chip support
552
553config SERIAL_MAX3107
554 tristate "MAX3107 support"
555 depends on SPI
556 select SERIAL_CORE
557 help
558 MAX3107 chip support
559
560config SERIAL_MAX3107_AAVA
561 tristate "MAX3107 AAVA platform support"
562 depends on X86_MRST && SERIAL_MAX3107 && GPIOLIB
563 select SERIAL_CORE
564 help
565 Support for the MAX3107 chip configuration found on the AAVA
566 platform. Includes the extra initialisation and GPIO support
567 neded for this device.
568
569config SERIAL_DZ
570 bool "DECstation DZ serial driver"
571 depends on MACH_DECSTATION && 32BIT
572 select SERIAL_CORE
573 default y
574 ---help---
575 DZ11-family serial controllers for DECstations and VAXstations,
576 including the DC7085, M7814, and M7819.
577
578config SERIAL_DZ_CONSOLE
579 bool "Support console on DECstation DZ serial driver"
580 depends on SERIAL_DZ=y
581 select SERIAL_CORE_CONSOLE
582 default y
583 ---help---
584 If you say Y here, it will be possible to use a serial port as the
585 system console (the system console is the device which receives all
586 kernel messages and warnings and which allows logins in single user
587 mode).
588
589 Note that the firmware uses ttyS3 as the serial console on
590 DECstations that use this driver.
591
592 If unsure, say Y.
593
594config SERIAL_ZS
595 tristate "DECstation Z85C30 serial support"
596 depends on MACH_DECSTATION
597 select SERIAL_CORE
598 default y
599 ---help---
600 Support for the Zilog 85C350 serial communications controller used
601 for serial ports in newer DECstation systems. These include the
602 DECsystem 5900 and all models of the DECstation and DECsystem 5000
603 systems except from model 200.
604
605 If unsure, say Y. To compile this driver as a module, choose M here:
606 the module will be called zs.
607
608config SERIAL_ZS_CONSOLE
609 bool "Support for console on a DECstation Z85C30 serial port"
610 depends on SERIAL_ZS=y
611 select SERIAL_CORE_CONSOLE
612 default y
613 ---help---
614 If you say Y here, it will be possible to use a serial port as the
615 system console (the system console is the device which receives all
616 kernel messages and warnings and which allows logins in single user
617 mode).
618
619 Note that the firmware uses ttyS1 as the serial console on the
620 Maxine and ttyS3 on the others using this driver.
621
622 If unsure, say Y.
623
624config SERIAL_21285
625 tristate "DC21285 serial port support"
626 depends on ARM && FOOTBRIDGE
627 select SERIAL_CORE
628 help
629 If you have a machine based on a 21285 (Footbridge) StrongARM(R)/
630 PCI bridge you can enable its onboard serial port by enabling this
631 option.
632
633config SERIAL_21285_CONSOLE
634 bool "Console on DC21285 serial port"
635 depends on SERIAL_21285=y
636 select SERIAL_CORE_CONSOLE
637 help
638 If you have enabled the serial port on the 21285 footbridge you can
639 make it the console by answering Y to this option.
640
641 Even if you say Y here, the currently visible virtual console
642 (/dev/tty0) will still be used as the system console by default, but
643 you can alter that using a kernel command line option such as
644 "console=ttyFB". (Try "man bootparam" or see the documentation of
645 your boot loader (lilo or loadlin) about how to pass options to the
646 kernel at boot time.)
647
648config SERIAL_MPSC
649 bool "Marvell MPSC serial port support"
650 depends on PPC32 && MV64X60
651 select SERIAL_CORE
652 help
653 Say Y here if you want to use the Marvell MPSC serial controller.
654
655config SERIAL_MPSC_CONSOLE
656 bool "Support for console on Marvell MPSC serial port"
657 depends on SERIAL_MPSC
658 select SERIAL_CORE_CONSOLE
659 help
660 Say Y here if you want to support a serial console on a Marvell MPSC.
661
662config SERIAL_PXA
663 bool "PXA serial port support"
664 depends on ARCH_PXA || ARCH_MMP
665 select SERIAL_CORE
666 help
667 If you have a machine based on an Intel XScale PXA2xx CPU you
668 can enable its onboard serial ports by enabling this option.
669
670config SERIAL_PXA_CONSOLE
671 bool "Console on PXA serial port"
672 depends on SERIAL_PXA
673 select SERIAL_CORE_CONSOLE
674 help
675 If you have enabled the serial port on the Intel XScale PXA
676 CPU you can make it the console by answering Y to this option.
677
678 Even if you say Y here, the currently visible virtual console
679 (/dev/tty0) will still be used as the system console by default, but
680 you can alter that using a kernel command line option such as
681 "console=ttySA0". (Try "man bootparam" or see the documentation of
682 your boot loader (lilo or loadlin) about how to pass options to the
683 kernel at boot time.)
684
685config SERIAL_SA1100
686 bool "SA1100 serial port support"
687 depends on ARM && ARCH_SA1100
688 select SERIAL_CORE
689 help
690 If you have a machine based on a SA1100/SA1110 StrongARM(R) CPU you
691 can enable its onboard serial port by enabling this option.
692 Please read <file:Documentation/arm/SA1100/serial_UART> for further
693 info.
694
695config SERIAL_SA1100_CONSOLE
696 bool "Console on SA1100 serial port"
697 depends on SERIAL_SA1100
698 select SERIAL_CORE_CONSOLE
699 help
700 If you have enabled the serial port on the SA1100/SA1110 StrongARM
701 CPU you can make it the console by answering Y to this option.
702
703 Even if you say Y here, the currently visible virtual console
704 (/dev/tty0) will still be used as the system console by default, but
705 you can alter that using a kernel command line option such as
706 "console=ttySA0". (Try "man bootparam" or see the documentation of
707 your boot loader (lilo or loadlin) about how to pass options to the
708 kernel at boot time.)
709
710config SERIAL_MRST_MAX3110
711 tristate "SPI UART driver for Max3110"
712 depends on SPI_DW_PCI
713 select SERIAL_CORE
714 select SERIAL_CORE_CONSOLE
715 help
716 This is the UART protocol driver for the MAX3110 device on
717 the Intel Moorestown platform. On other systems use the max3100
718 driver.
719
720config MRST_MAX3110_IRQ
721 boolean "Enable GPIO IRQ for Max3110 over Moorestown"
722 default n
723 depends on SERIAL_MRST_MAX3110 && GPIO_LANGWELL
724 help
725 This has to be enabled after Moorestown GPIO driver is loaded
726
727config SERIAL_MFD_HSU
728 tristate "Medfield High Speed UART support"
729 depends on PCI
730 select SERIAL_CORE
731
732config SERIAL_MFD_HSU_CONSOLE
733 boolean "Medfile HSU serial console support"
734 depends on SERIAL_MFD_HSU=y
735 select SERIAL_CORE_CONSOLE
736
737config SERIAL_BFIN
738 tristate "Blackfin serial port support"
739 depends on BLACKFIN
740 select SERIAL_CORE
741 select SERIAL_BFIN_UART0 if (BF531 || BF532 || BF533 || BF561)
742 help
743 Add support for the built-in UARTs on the Blackfin.
744
745 To compile this driver as a module, choose M here: the
746 module will be called bfin_5xx.
747
748config SERIAL_BFIN_CONSOLE
749 bool "Console on Blackfin serial port"
750 depends on SERIAL_BFIN=y
751 select SERIAL_CORE_CONSOLE
752
753choice
754 prompt "UART Mode"
755 depends on SERIAL_BFIN
756 default SERIAL_BFIN_DMA
757 help
758 This driver supports the built-in serial ports of the Blackfin family
759 of CPUs
760
761config SERIAL_BFIN_DMA
762 bool "DMA mode"
763 depends on !DMA_UNCACHED_NONE && KGDB_SERIAL_CONSOLE=n
764 help
765 This driver works under DMA mode. If this option is selected, the
766 blackfin simple dma driver is also enabled.
767
768config SERIAL_BFIN_PIO
769 bool "PIO mode"
770 help
771 This driver works under PIO mode.
772
773endchoice
774
775config SERIAL_BFIN_UART0
776 bool "Enable UART0"
777 depends on SERIAL_BFIN
778 help
779 Enable UART0
780
781config BFIN_UART0_CTSRTS
782 bool "Enable UART0 hardware flow control"
783 depends on SERIAL_BFIN_UART0
784 help
785 Enable hardware flow control in the driver. Using GPIO emulate the CTS/RTS
786 signal.
787
788config UART0_CTS_PIN
789 int "UART0 CTS pin"
790 depends on BFIN_UART0_CTSRTS && !BF548
791 default 23
792 help
793 The default pin is GPIO_GP7.
794 Refer to arch/blackfin/mach-*/include/mach/gpio.h to see the GPIO map.
795
796config UART0_RTS_PIN
797 int "UART0 RTS pin"
798 depends on BFIN_UART0_CTSRTS && !BF548
799 default 22
800 help
801 The default pin is GPIO_GP6.
802 Refer to arch/blackfin/mach-*/include/mach/gpio.h to see the GPIO map.
803
804config SERIAL_BFIN_UART1
805 bool "Enable UART1"
806 depends on SERIAL_BFIN && (!BF531 && !BF532 && !BF533 && !BF561)
807 help
808 Enable UART1
809
810config BFIN_UART1_CTSRTS
811 bool "Enable UART1 hardware flow control"
812 depends on SERIAL_BFIN_UART1
813 help
814 Enable hardware flow control in the driver. Using GPIO emulate the CTS/RTS
815 signal.
816
817config UART1_CTS_PIN
818 int "UART1 CTS pin"
819 depends on BFIN_UART1_CTSRTS && !BF548
820 default -1
821 help
822 Refer to arch/blackfin/mach-*/include/mach/gpio.h to see the GPIO map.
823
824config UART1_RTS_PIN
825 int "UART1 RTS pin"
826 depends on BFIN_UART1_CTSRTS && !BF548
827 default -1
828 help
829 Refer to arch/blackfin/mach-*/include/mach/gpio.h to see the GPIO map.
830
831config SERIAL_BFIN_UART2
832 bool "Enable UART2"
833 depends on SERIAL_BFIN && (BF54x || BF538 || BF539)
834 help
835 Enable UART2
836
837config BFIN_UART2_CTSRTS
838 bool "Enable UART2 hardware flow control"
839 depends on SERIAL_BFIN_UART2
840 help
841 Enable hardware flow control in the driver. Using GPIO emulate the CTS/RTS
842 signal.
843
844config UART2_CTS_PIN
845 int "UART2 CTS pin"
846 depends on BFIN_UART2_CTSRTS && !BF548
847 default -1
848 help
849 Refer to arch/blackfin/mach-*/include/mach/gpio.h to see the GPIO map.
850
851config UART2_RTS_PIN
852 int "UART2 RTS pin"
853 depends on BFIN_UART2_CTSRTS && !BF548
854 default -1
855 help
856 Refer to arch/blackfin/mach-*/include/mach/gpio.h to see the GPIO map.
857
858config SERIAL_BFIN_UART3
859 bool "Enable UART3"
860 depends on SERIAL_BFIN && (BF54x)
861 help
862 Enable UART3
863
864config BFIN_UART3_CTSRTS
865 bool "Enable UART3 hardware flow control"
866 depends on SERIAL_BFIN_UART3
867 help
868 Enable hardware flow control in the driver. Using GPIO emulate the CTS/RTS
869 signal.
870
871config UART3_CTS_PIN
872 int "UART3 CTS pin"
873 depends on BFIN_UART3_CTSRTS && !BF548
874 default -1
875 help
876 Refer to arch/blackfin/mach-*/include/mach/gpio.h to see the GPIO map.
877
878config UART3_RTS_PIN
879 int "UART3 RTS pin"
880 depends on BFIN_UART3_CTSRTS && !BF548
881 default -1
882 help
883 Refer to arch/blackfin/mach-*/include/mach/gpio.h to see the GPIO map.
884
885config SERIAL_IMX
886 bool "IMX serial port support"
887 depends on ARM && (ARCH_IMX || ARCH_MXC)
888 select SERIAL_CORE
889 select RATIONAL
890 help
891 If you have a machine based on a Motorola IMX CPU you
892 can enable its onboard serial port by enabling this option.
893
894config SERIAL_IMX_CONSOLE
895 bool "Console on IMX serial port"
896 depends on SERIAL_IMX
897 select SERIAL_CORE_CONSOLE
898 help
899 If you have enabled the serial port on the Motorola IMX
900 CPU you can make it the console by answering Y to this option.
901
902 Even if you say Y here, the currently visible virtual console
903 (/dev/tty0) will still be used as the system console by default, but
904 you can alter that using a kernel command line option such as
905 "console=ttySA0". (Try "man bootparam" or see the documentation of
906 your boot loader (lilo or loadlin) about how to pass options to the
907 kernel at boot time.)
908
909config SERIAL_UARTLITE
910 tristate "Xilinx uartlite serial port support"
911 depends on PPC32 || MICROBLAZE || MFD_TIMBERDALE
912 select SERIAL_CORE
913 help
914 Say Y here if you want to use the Xilinx uartlite serial controller.
915
916 To compile this driver as a module, choose M here: the
917 module will be called uartlite.
918
919config SERIAL_UARTLITE_CONSOLE
920 bool "Support for console on Xilinx uartlite serial port"
921 depends on SERIAL_UARTLITE=y
922 select SERIAL_CORE_CONSOLE
923 help
924 Say Y here if you wish to use a Xilinx uartlite as the system
925 console (the system console is the device which receives all kernel
926 messages and warnings and which allows logins in single user mode).
927
928config SERIAL_SUNCORE
929 bool
930 depends on SPARC
931 select SERIAL_CORE
932 select SERIAL_CORE_CONSOLE
933 default y
934
935config SERIAL_SUNZILOG
936 tristate "Sun Zilog8530 serial support"
937 depends on SPARC
938 help
939 This driver supports the Zilog8530 serial ports found on many Sparc
940 systems. Say Y or M if you want to be able to these serial ports.
941
942config SERIAL_SUNZILOG_CONSOLE
943 bool "Console on Sun Zilog8530 serial port"
944 depends on SERIAL_SUNZILOG=y
945 help
946 If you would like to be able to use the Zilog8530 serial port
947 on your Sparc system as the console, you can do so by answering
948 Y to this option.
949
950config SERIAL_SUNSU
951 tristate "Sun SU serial support"
952 depends on SPARC && PCI
953 help
954 This driver supports the 8250 serial ports that run the keyboard and
955 mouse on (PCI) UltraSPARC systems. Say Y or M if you want to be able
956 to these serial ports.
957
958config SERIAL_SUNSU_CONSOLE
959 bool "Console on Sun SU serial port"
960 depends on SERIAL_SUNSU=y
961 help
962 If you would like to be able to use the SU serial port
963 on your Sparc system as the console, you can do so by answering
964 Y to this option.
965
966config SERIAL_MUX
967 tristate "Serial MUX support"
968 depends on GSC
969 select SERIAL_CORE
970 default y
971 ---help---
972 Saying Y here will enable the hardware MUX serial driver for
973 the Nova, K class systems and D class with a 'remote control card'.
974 The hardware MUX is not 8250/16550 compatible therefore the
975 /dev/ttyB0 device is shared between the Serial MUX and the PDC
976 software console. The following steps need to be completed to use
977 the Serial MUX:
978
979 1. create the device entry (mknod /dev/ttyB0 c 11 0)
980 2. Edit the /etc/inittab to start a getty listening on /dev/ttyB0
981 3. Add device ttyB0 to /etc/securetty (if you want to log on as
982 root on this console.)
983 4. Change the kernel command console parameter to: console=ttyB0
984
985config SERIAL_MUX_CONSOLE
986 bool "Support for console on serial MUX"
987 depends on SERIAL_MUX=y
988 select SERIAL_CORE_CONSOLE
989 default y
990
991config PDC_CONSOLE
992 bool "PDC software console support"
993 depends on PARISC && !SERIAL_MUX && VT
994 default n
995 help
996 Saying Y here will enable the software based PDC console to be
997 used as the system console. This is useful for machines in
998 which the hardware based console has not been written yet. The
999 following steps must be competed to use the PDC console:
1000
1001 1. create the device entry (mknod /dev/ttyB0 c 11 0)
1002 2. Edit the /etc/inittab to start a getty listening on /dev/ttyB0
1003 3. Add device ttyB0 to /etc/securetty (if you want to log on as
1004 root on this console.)
1005 4. Change the kernel command console parameter to: console=ttyB0
1006
1007config SERIAL_SUNSAB
1008 tristate "Sun Siemens SAB82532 serial support"
1009 depends on SPARC && PCI
1010 help
1011 This driver supports the Siemens SAB82532 DUSCC serial ports on newer
1012 (PCI) UltraSPARC systems. Say Y or M if you want to be able to these
1013 serial ports.
1014
1015config SERIAL_SUNSAB_CONSOLE
1016 bool "Console on Sun Siemens SAB82532 serial port"
1017 depends on SERIAL_SUNSAB=y
1018 help
1019 If you would like to be able to use the SAB82532 serial port
1020 on your Sparc system as the console, you can do so by answering
1021 Y to this option.
1022
1023config SERIAL_SUNHV
1024 bool "Sun4v Hypervisor Console support"
1025 depends on SPARC64
1026 help
1027 This driver supports the console device found on SUN4V Sparc
1028 systems. Say Y if you want to be able to use this device.
1029
1030config SERIAL_IP22_ZILOG
1031 tristate "SGI Zilog8530 serial support"
1032 depends on SGI_HAS_ZILOG
1033 select SERIAL_CORE
1034 help
1035 This driver supports the Zilog8530 serial ports found on SGI
1036 systems. Say Y or M if you want to be able to these serial ports.
1037
1038config SERIAL_IP22_ZILOG_CONSOLE
1039 bool "Console on SGI Zilog8530 serial port"
1040 depends on SERIAL_IP22_ZILOG=y
1041 select SERIAL_CORE_CONSOLE
1042
1043config SERIAL_SH_SCI
1044 tristate "SuperH SCI(F) serial port support"
1045 depends on HAVE_CLK && (SUPERH || H8300 || ARCH_SHMOBILE)
1046 select SERIAL_CORE
1047
1048config SERIAL_SH_SCI_NR_UARTS
1049 int "Maximum number of SCI(F) serial ports"
1050 depends on SERIAL_SH_SCI
1051 default "2"
1052
1053config SERIAL_SH_SCI_CONSOLE
1054 bool "Support for console on SuperH SCI(F)"
1055 depends on SERIAL_SH_SCI=y
1056 select SERIAL_CORE_CONSOLE
1057
1058config SERIAL_SH_SCI_DMA
1059 bool "DMA support"
1060 depends on SERIAL_SH_SCI && SH_DMAE && EXPERIMENTAL
1061
1062config SERIAL_PNX8XXX
1063 bool "Enable PNX8XXX SoCs' UART Support"
1064 depends on MIPS && (SOC_PNX8550 || SOC_PNX833X)
1065 select SERIAL_CORE
1066 help
1067 If you have a MIPS-based Philips SoC such as PNX8550 or PNX8330
1068 and you want to use serial ports, say Y. Otherwise, say N.
1069
1070config SERIAL_PNX8XXX_CONSOLE
1071 bool "Enable PNX8XX0 serial console"
1072 depends on SERIAL_PNX8XXX
1073 select SERIAL_CORE_CONSOLE
1074 help
1075 If you have a MIPS-based Philips SoC such as PNX8550 or PNX8330
1076 and you want to use serial console, say Y. Otherwise, say N.
1077
1078config SERIAL_CORE
1079 tristate
1080
1081config SERIAL_CORE_CONSOLE
1082 bool
1083
1084config CONSOLE_POLL
1085 bool
1086
1087config SERIAL_68328
1088 bool "68328 serial support"
1089 depends on M68328 || M68EZ328 || M68VZ328
1090 help
1091 This driver supports the built-in serial port of the Motorola 68328
1092 (standard, EZ and VZ varieties).
1093
1094config SERIAL_68328_RTS_CTS
1095 bool "Support RTS/CTS on 68328 serial port"
1096 depends on SERIAL_68328
1097
1098config SERIAL_MCF
1099 bool "Coldfire serial support"
1100 depends on COLDFIRE
1101 select SERIAL_CORE
1102 help
1103 This serial driver supports the Freescale Coldfire serial ports.
1104
1105config SERIAL_MCF_BAUDRATE
1106 int "Default baudrate for Coldfire serial ports"
1107 depends on SERIAL_MCF
1108 default 19200
1109 help
1110 This setting lets you define what the default baudrate is for the
1111 ColdFire serial ports. The usual default varies from board to board,
1112 and this setting is a way of catering for that.
1113
1114config SERIAL_MCF_CONSOLE
1115 bool "Coldfire serial console support"
1116 depends on SERIAL_MCF
1117 select SERIAL_CORE_CONSOLE
1118 help
1119 Enable a ColdFire internal serial port to be the system console.
1120
1121config SERIAL_68360_SMC
1122 bool "68360 SMC uart support"
1123 depends on M68360
1124 help
1125 This driver supports the SMC serial ports of the Motorola 68360 CPU.
1126
1127config SERIAL_68360_SCC
1128 bool "68360 SCC uart support"
1129 depends on M68360
1130 help
1131 This driver supports the SCC serial ports of the Motorola 68360 CPU.
1132
1133config SERIAL_68360
1134 bool
1135 depends on SERIAL_68360_SMC || SERIAL_68360_SCC
1136 default y
1137
1138config SERIAL_PMACZILOG
1139 tristate "Mac or PowerMac z85c30 ESCC support"
1140 depends on (M68K && MAC) || (PPC_OF && PPC_PMAC)
1141 select SERIAL_CORE
1142 help
1143 This driver supports the Zilog z85C30 serial ports found on
1144 (Power)Mac machines.
1145 Say Y or M if you want to be able to these serial ports.
1146
1147config SERIAL_PMACZILOG_TTYS
1148 bool "Use ttySn device nodes for Zilog z85c30"
1149 depends on SERIAL_PMACZILOG
1150 help
1151 The pmac_zilog driver for the z85C30 chip on many powermacs
1152 historically used the device numbers for /dev/ttySn. The
1153 8250 serial port driver also uses these numbers, which means
1154 the two drivers being unable to coexist; you could not use
1155 both z85C30 and 8250 type ports at the same time.
1156
1157 If this option is not selected, the pmac_zilog driver will
1158 use the device numbers allocated for /dev/ttyPZn. This allows
1159 the pmac_zilog and 8250 drivers to co-exist, but may cause
1160 existing userspace setups to break. Programs that need to
1161 access the built-in serial ports on powermacs will need to
1162 be reconfigured to use /dev/ttyPZn instead of /dev/ttySn.
1163
1164 If you enable this option, any z85c30 ports in the system will
1165 be registered as ttyS0 onwards as in the past, and you will be
1166 unable to use the 8250 module for PCMCIA or other 16C550-style
1167 UARTs.
1168
1169 Say N unless you need the z85c30 ports on your (Power)Mac
1170 to appear as /dev/ttySn.
1171
1172config SERIAL_PMACZILOG_CONSOLE
1173 bool "Console on Mac or PowerMac z85c30 serial port"
1174 depends on SERIAL_PMACZILOG=y
1175 select SERIAL_CORE_CONSOLE
1176 help
1177 If you would like to be able to use the z85c30 serial port
1178 on your (Power)Mac as the console, you can do so by answering
1179 Y to this option.
1180
1181config SERIAL_LH7A40X
1182 tristate "Sharp LH7A40X embedded UART support"
1183 depends on ARM && ARCH_LH7A40X
1184 select SERIAL_CORE
1185 help
1186 This enables support for the three on-board UARTs of the
1187 Sharp LH7A40X series CPUs. Choose Y or M.
1188
1189config SERIAL_LH7A40X_CONSOLE
1190 bool "Support for console on Sharp LH7A40X serial port"
1191 depends on SERIAL_LH7A40X=y
1192 select SERIAL_CORE_CONSOLE
1193 help
1194 Say Y here if you wish to use one of the serial ports as the
1195 system console--the system console is the device which
1196 receives all kernel messages and warnings and which allows
1197 logins in single user mode.
1198
1199 Even if you say Y here, the currently visible framebuffer console
1200 (/dev/tty0) will still be used as the default system console, but
1201 you can alter that using a kernel command line, for example
1202 "console=ttyAM1".
1203
1204config SERIAL_CPM
1205 tristate "CPM SCC/SMC serial port support"
1206 depends on CPM2 || 8xx
1207 select SERIAL_CORE
1208 help
1209 This driver supports the SCC and SMC serial ports on Motorola
1210 embedded PowerPC that contain a CPM1 (8xx) or CPM2 (8xxx)
1211
1212config SERIAL_CPM_CONSOLE
1213 bool "Support for console on CPM SCC/SMC serial port"
1214 depends on SERIAL_CPM=y
1215 select SERIAL_CORE_CONSOLE
1216 help
1217 Say Y here if you wish to use a SCC or SMC CPM UART as the system
1218 console (the system console is the device which receives all kernel
1219 messages and warnings and which allows logins in single user mode).
1220
1221 Even if you say Y here, the currently visible framebuffer console
1222 (/dev/tty0) will still be used as the system console by default, but
1223 you can alter that using a kernel command line option such as
1224 "console=ttyCPM0". (Try "man bootparam" or see the documentation of
1225 your boot loader (lilo or loadlin) about how to pass options to the
1226 kernel at boot time.)
1227
1228config SERIAL_SGI_L1_CONSOLE
1229 bool "SGI Altix L1 serial console support"
1230 depends on IA64_GENERIC || IA64_SGI_SN2
1231 select SERIAL_CORE
1232 select SERIAL_CORE_CONSOLE
1233 help
1234 If you have an SGI Altix and you would like to use the system
1235 controller serial port as your console (you want this!),
1236 say Y. Otherwise, say N.
1237
1238config SERIAL_MPC52xx
1239 tristate "Freescale MPC52xx/MPC512x family PSC serial support"
1240 depends on PPC_MPC52xx || PPC_MPC512x
1241 select SERIAL_CORE
1242 help
1243 This driver supports MPC52xx and MPC512x PSC serial ports. If you would
1244 like to use them, you must answer Y or M to this option. Note that
1245 for use as console, it must be included in kernel and not as a
1246 module.
1247
1248config SERIAL_MPC52xx_CONSOLE
1249 bool "Console on a Freescale MPC52xx/MPC512x family PSC serial port"
1250 depends on SERIAL_MPC52xx=y
1251 select SERIAL_CORE_CONSOLE
1252 help
1253 Select this options if you'd like to use one of the PSC serial port
1254 of the Freescale MPC52xx family as a console.
1255
1256config SERIAL_MPC52xx_CONSOLE_BAUD
1257 int "Freescale MPC52xx/MPC512x family PSC serial port baud"
1258 depends on SERIAL_MPC52xx_CONSOLE=y
1259 default "9600"
1260 help
1261 Select the MPC52xx console baud rate.
1262 This value is only used if the bootloader doesn't pass in the
1263 console baudrate
1264
1265config SERIAL_ICOM
1266 tristate "IBM Multiport Serial Adapter"
1267 depends on PCI && (PPC_ISERIES || PPC_PSERIES)
1268 select SERIAL_CORE
1269 select FW_LOADER
1270 help
1271 This driver is for a family of multiport serial adapters
1272 including 2 port RVX, 2 port internal modem, 4 port internal
1273 modem and a split 1 port RVX and 1 port internal modem.
1274
1275 This driver can also be built as a module. If so, the module
1276 will be called icom.
1277
1278config SERIAL_M32R_SIO
1279 bool "M32R SIO I/F"
1280 depends on M32R
1281 default y
1282 select SERIAL_CORE
1283 help
1284 Say Y here if you want to use the M32R serial controller.
1285
1286config SERIAL_M32R_SIO_CONSOLE
1287 bool "use SIO console"
1288 depends on SERIAL_M32R_SIO=y
1289 select SERIAL_CORE_CONSOLE
1290 help
1291 Say Y here if you want to support a serial console.
1292
1293 If you use an M3T-M32700UT or an OPSPUT platform,
1294 please say also y for SERIAL_M32R_PLDSIO.
1295
1296config SERIAL_M32R_PLDSIO
1297 bool "M32R SIO I/F on a PLD"
1298 depends on SERIAL_M32R_SIO=y && (PLAT_OPSPUT || PLAT_USRV || PLAT_M32700UT)
1299 default n
1300 help
1301 Say Y here if you want to use the M32R serial controller
1302 on a PLD (Programmable Logic Device).
1303
1304 If you use an M3T-M32700UT or an OPSPUT platform,
1305 please say Y.
1306
1307config SERIAL_TXX9
1308 bool "TMPTX39XX/49XX SIO support"
1309 depends on HAS_TXX9_SERIAL
1310 select SERIAL_CORE
1311 default y
1312
1313config HAS_TXX9_SERIAL
1314 bool
1315
1316config SERIAL_TXX9_NR_UARTS
1317 int "Maximum number of TMPTX39XX/49XX SIO ports"
1318 depends on SERIAL_TXX9
1319 default "6"
1320
1321config SERIAL_TXX9_CONSOLE
1322 bool "TMPTX39XX/49XX SIO Console support"
1323 depends on SERIAL_TXX9=y
1324 select SERIAL_CORE_CONSOLE
1325
1326config SERIAL_TXX9_STDSERIAL
1327 bool "TX39XX/49XX SIO act as standard serial"
1328 depends on !SERIAL_8250 && SERIAL_TXX9
1329
1330config SERIAL_VR41XX
1331 tristate "NEC VR4100 series Serial Interface Unit support"
1332 depends on CPU_VR41XX
1333 select SERIAL_CORE
1334 help
1335 If you have a NEC VR4100 series processor and you want to use
1336 Serial Interface Unit(SIU) or Debug Serial Interface Unit(DSIU)
1337 (not include VR4111/VR4121 DSIU), say Y. Otherwise, say N.
1338
1339config SERIAL_VR41XX_CONSOLE
1340 bool "Enable NEC VR4100 series Serial Interface Unit console"
1341 depends on SERIAL_VR41XX=y
1342 select SERIAL_CORE_CONSOLE
1343 help
1344 If you have a NEC VR4100 series processor and you want to use
1345 a console on a serial port, say Y. Otherwise, say N.
1346
1347config SERIAL_JSM
1348 tristate "Digi International NEO PCI Support"
1349 depends on PCI
1350 select SERIAL_CORE
1351 help
1352 This is a driver for Digi International's Neo series
1353 of cards which provide multiple serial ports. You would need
1354 something like this to connect more than two modems to your Linux
1355 box, for instance in order to become a dial-in server. This driver
1356 supports PCI boards only.
1357
1358 If you have a card like this, say Y here, otherwise say N.
1359
1360 To compile this driver as a module, choose M here: the
1361 module will be called jsm.
1362
1363config SERIAL_SGI_IOC4
1364 tristate "SGI IOC4 controller serial support"
1365 depends on (IA64_GENERIC || IA64_SGI_SN2) && SGI_IOC4
1366 select SERIAL_CORE
1367 help
1368 If you have an SGI Altix with an IOC4 based Base IO card
1369 and wish to use the serial ports on this card, say Y.
1370 Otherwise, say N.
1371
1372config SERIAL_SGI_IOC3
1373 tristate "SGI Altix IOC3 serial support"
1374 depends on (IA64_GENERIC || IA64_SGI_SN2) && SGI_IOC3
1375 select SERIAL_CORE
1376 help
1377 If you have an SGI Altix with an IOC3 serial card,
1378 say Y or M. Otherwise, say N.
1379
1380config SERIAL_MSM
1381 bool "MSM on-chip serial port support"
1382 depends on ARM && ARCH_MSM
1383 select SERIAL_CORE
1384
1385config SERIAL_MSM_CONSOLE
1386 bool "MSM serial console support"
1387 depends on SERIAL_MSM=y
1388 select SERIAL_CORE_CONSOLE
1389
1390config SERIAL_NETX
1391 tristate "NetX serial port support"
1392 depends on ARM && ARCH_NETX
1393 select SERIAL_CORE
1394 help
1395 If you have a machine based on a Hilscher NetX SoC you
1396 can enable its onboard serial port by enabling this option.
1397
1398 To compile this driver as a module, choose M here: the
1399 module will be called netx-serial.
1400
1401config SERIAL_NETX_CONSOLE
1402 bool "Console on NetX serial port"
1403 depends on SERIAL_NETX=y
1404 select SERIAL_CORE_CONSOLE
1405 help
1406 If you have enabled the serial port on the Hilscher NetX SoC
1407 you can make it the console by answering Y to this option.
1408
1409config SERIAL_OF_PLATFORM
1410 tristate "Serial port on Open Firmware platform bus"
1411 depends on PPC_OF || MICROBLAZE
1412 depends on SERIAL_8250 || SERIAL_OF_PLATFORM_NWPSERIAL
1413 help
1414 If you have a PowerPC based system that has serial ports
1415 on a platform specific bus, you should enable this option.
1416 Currently, only 8250 compatible ports are supported, but
1417 others can easily be added.
1418
1419config SERIAL_OF_PLATFORM_NWPSERIAL
1420 tristate "NWP serial port driver"
1421 depends on PPC_OF && PPC_DCR
1422 select SERIAL_OF_PLATFORM
1423 select SERIAL_CORE_CONSOLE
1424 select SERIAL_CORE
1425 help
1426 This driver supports the cell network processor nwp serial
1427 device.
1428
1429config SERIAL_OF_PLATFORM_NWPSERIAL_CONSOLE
1430 bool "Console on NWP serial port"
1431 depends on SERIAL_OF_PLATFORM_NWPSERIAL=y
1432 select SERIAL_CORE_CONSOLE
1433 help
1434 Support for Console on the NWP serial ports.
1435
1436config SERIAL_QE
1437 tristate "Freescale QUICC Engine serial port support"
1438 depends on QUICC_ENGINE
1439 select SERIAL_CORE
1440 select FW_LOADER
1441 default n
1442 help
1443 This driver supports the QE serial ports on Freescale embedded
1444 PowerPC that contain a QUICC Engine.
1445
1446config SERIAL_SC26XX
1447 tristate "SC2681/SC2692 serial port support"
1448 depends on SNI_RM
1449 select SERIAL_CORE
1450 help
1451 This is a driver for the onboard serial ports of
1452 older RM400 machines.
1453
1454config SERIAL_SC26XX_CONSOLE
1455 bool "Console on SC2681/SC2692 serial port"
1456 depends on SERIAL_SC26XX
1457 select SERIAL_CORE_CONSOLE
1458 help
1459 Support for Console on SC2681/SC2692 serial ports.
1460
1461config SERIAL_BFIN_SPORT
1462 tristate "Blackfin SPORT emulate UART"
1463 depends on BLACKFIN
1464 select SERIAL_CORE
1465 help
1466 Enable SPORT emulate UART on Blackfin series.
1467
1468 To compile this driver as a module, choose M here: the
1469 module will be called bfin_sport_uart.
1470
1471config SERIAL_BFIN_SPORT_CONSOLE
1472 bool "Console on Blackfin sport emulated uart"
1473 depends on SERIAL_BFIN_SPORT=y
1474 select SERIAL_CORE_CONSOLE
1475
1476config SERIAL_BFIN_SPORT0_UART
1477 bool "Enable UART over SPORT0"
1478 depends on SERIAL_BFIN_SPORT && !(BF542 || BF544)
1479 help
1480 Enable UART over SPORT0
1481
1482config SERIAL_BFIN_SPORT0_UART_CTSRTS
1483 bool "Enable UART over SPORT0 hardware flow control"
1484 depends on SERIAL_BFIN_SPORT0_UART
1485 help
1486 Enable hardware flow control in the driver.
1487
1488config SERIAL_BFIN_SPORT1_UART
1489 bool "Enable UART over SPORT1"
1490 depends on SERIAL_BFIN_SPORT
1491 help
1492 Enable UART over SPORT1
1493
1494config SERIAL_BFIN_SPORT1_UART_CTSRTS
1495 bool "Enable UART over SPORT1 hardware flow control"
1496 depends on SERIAL_BFIN_SPORT1_UART
1497 help
1498 Enable hardware flow control in the driver.
1499
1500config SERIAL_BFIN_SPORT2_UART
1501 bool "Enable UART over SPORT2"
1502 depends on SERIAL_BFIN_SPORT && (BF54x || BF538 || BF539)
1503 help
1504 Enable UART over SPORT2
1505
1506config SERIAL_BFIN_SPORT2_UART_CTSRTS
1507 bool "Enable UART over SPORT2 hardware flow control"
1508 depends on SERIAL_BFIN_SPORT2_UART
1509 help
1510 Enable hardware flow control in the driver.
1511
1512config SERIAL_BFIN_SPORT3_UART
1513 bool "Enable UART over SPORT3"
1514 depends on SERIAL_BFIN_SPORT && (BF54x || BF538 || BF539)
1515 help
1516 Enable UART over SPORT3
1517
1518config SERIAL_BFIN_SPORT3_UART_CTSRTS
1519 bool "Enable UART over SPORT3 hardware flow control"
1520 depends on SERIAL_BFIN_SPORT3_UART
1521 help
1522 Enable hardware flow control in the driver.
1523
1524config SERIAL_TIMBERDALE
1525 tristate "Support for timberdale UART"
1526 select SERIAL_CORE
1527 ---help---
1528 Add support for UART controller on timberdale.
1529
1530config SERIAL_BCM63XX
1531 tristate "bcm63xx serial port support"
1532 select SERIAL_CORE
1533 depends on BCM63XX
1534 help
1535 If you have a bcm63xx CPU, you can enable its onboard
1536 serial port by enabling this options.
1537
1538 To compile this driver as a module, choose M here: the
1539 module will be called bcm963xx_uart.
1540
1541config SERIAL_BCM63XX_CONSOLE
1542 bool "Console on bcm63xx serial port"
1543 depends on SERIAL_BCM63XX=y
1544 select SERIAL_CORE_CONSOLE
1545 help
1546 If you have enabled the serial port on the bcm63xx CPU
1547 you can make it the console by answering Y to this option.
1548
1549config SERIAL_GRLIB_GAISLER_APBUART
1550 tristate "GRLIB APBUART serial support"
1551 depends on OF
1552 ---help---
1553 Add support for the GRLIB APBUART serial port.
1554
1555config SERIAL_GRLIB_GAISLER_APBUART_CONSOLE
1556 bool "Console on GRLIB APBUART serial port"
1557 depends on SERIAL_GRLIB_GAISLER_APBUART=y
1558 select SERIAL_CORE_CONSOLE
1559 help
1560 Support for running a console on the GRLIB APBUART
1561
1562config SERIAL_ALTERA_JTAGUART
1563 tristate "Altera JTAG UART support"
1564 select SERIAL_CORE
1565 help
1566 This driver supports the Altera JTAG UART port.
1567
1568config SERIAL_ALTERA_JTAGUART_CONSOLE
1569 bool "Altera JTAG UART console support"
1570 depends on SERIAL_ALTERA_JTAGUART=y
1571 select SERIAL_CORE_CONSOLE
1572 help
1573 Enable a Altera JTAG UART port to be the system console.
1574
1575config SERIAL_ALTERA_JTAGUART_CONSOLE_BYPASS
1576 bool "Bypass output when no connection"
1577 depends on SERIAL_ALTERA_JTAGUART_CONSOLE
1578 select SERIAL_CORE_CONSOLE
1579 help
1580 Bypass console output and keep going even if there is no
1581 JTAG terminal connection with the host.
1582
1583config SERIAL_ALTERA_UART
1584 tristate "Altera UART support"
1585 select SERIAL_CORE
1586 help
1587 This driver supports the Altera softcore UART port.
1588
1589config SERIAL_ALTERA_UART_MAXPORTS
1590 int "Maximum number of Altera UART ports"
1591 depends on SERIAL_ALTERA_UART
1592 default 4
1593 help
1594 This setting lets you define the maximum number of the Altera
1595 UART ports. The usual default varies from board to board, and
1596 this setting is a way of catering for that.
1597
1598config SERIAL_ALTERA_UART_BAUDRATE
1599 int "Default baudrate for Altera UART ports"
1600 depends on SERIAL_ALTERA_UART
1601 default 115200
1602 help
1603 This setting lets you define what the default baudrate is for the
1604 Altera UART ports. The usual default varies from board to board,
1605 and this setting is a way of catering for that.
1606
1607config SERIAL_ALTERA_UART_CONSOLE
1608 bool "Altera UART console support"
1609 depends on SERIAL_ALTERA_UART=y
1610 select SERIAL_CORE_CONSOLE
1611 help
1612 Enable a Altera UART port to be the system console.
1613
1614endmenu
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
deleted file mode 100644
index 1ca4fd599ffe..000000000000
--- a/drivers/serial/Makefile
+++ /dev/null
@@ -1,90 +0,0 @@
1#
2# Makefile for the kernel serial device drivers.
3#
4
5obj-$(CONFIG_SERIAL_CORE) += serial_core.o
6obj-$(CONFIG_SERIAL_21285) += 21285.o
7
8# These Sparc drivers have to appear before others such as 8250
9# which share ttySx minor node space. Otherwise console device
10# names change and other unplesantries.
11obj-$(CONFIG_SERIAL_SUNCORE) += suncore.o
12obj-$(CONFIG_SERIAL_SUNHV) += sunhv.o
13obj-$(CONFIG_SERIAL_SUNZILOG) += sunzilog.o
14obj-$(CONFIG_SERIAL_SUNSU) += sunsu.o
15obj-$(CONFIG_SERIAL_SUNSAB) += sunsab.o
16
17obj-$(CONFIG_SERIAL_8250) += 8250.o
18obj-$(CONFIG_SERIAL_8250_PNP) += 8250_pnp.o
19obj-$(CONFIG_SERIAL_8250_GSC) += 8250_gsc.o
20obj-$(CONFIG_SERIAL_8250_PCI) += 8250_pci.o
21obj-$(CONFIG_SERIAL_8250_HP300) += 8250_hp300.o
22obj-$(CONFIG_SERIAL_8250_CS) += serial_cs.o
23obj-$(CONFIG_SERIAL_8250_ACORN) += 8250_acorn.o
24obj-$(CONFIG_SERIAL_8250_CONSOLE) += 8250_early.o
25obj-$(CONFIG_SERIAL_8250_FOURPORT) += 8250_fourport.o
26obj-$(CONFIG_SERIAL_8250_ACCENT) += 8250_accent.o
27obj-$(CONFIG_SERIAL_8250_BOCA) += 8250_boca.o
28obj-$(CONFIG_SERIAL_8250_EXAR_ST16C554) += 8250_exar_st16c554.o
29obj-$(CONFIG_SERIAL_8250_HUB6) += 8250_hub6.o
30obj-$(CONFIG_SERIAL_8250_MCA) += 8250_mca.o
31obj-$(CONFIG_SERIAL_AMBA_PL010) += amba-pl010.o
32obj-$(CONFIG_SERIAL_AMBA_PL011) += amba-pl011.o
33obj-$(CONFIG_SERIAL_CLPS711X) += clps711x.o
34obj-$(CONFIG_SERIAL_PXA) += pxa.o
35obj-$(CONFIG_SERIAL_PNX8XXX) += pnx8xxx_uart.o
36obj-$(CONFIG_SERIAL_SA1100) += sa1100.o
37obj-$(CONFIG_SERIAL_BCM63XX) += bcm63xx_uart.o
38obj-$(CONFIG_SERIAL_BFIN) += bfin_5xx.o
39obj-$(CONFIG_SERIAL_BFIN_SPORT) += bfin_sport_uart.o
40obj-$(CONFIG_SERIAL_SAMSUNG) += samsung.o
41obj-$(CONFIG_SERIAL_S3C2400) += s3c2400.o
42obj-$(CONFIG_SERIAL_S3C2410) += s3c2410.o
43obj-$(CONFIG_SERIAL_S3C2412) += s3c2412.o
44obj-$(CONFIG_SERIAL_S3C2440) += s3c2440.o
45obj-$(CONFIG_SERIAL_S3C24A0) += s3c24a0.o
46obj-$(CONFIG_SERIAL_S3C6400) += s3c6400.o
47obj-$(CONFIG_SERIAL_S5PV210) += s5pv210.o
48obj-$(CONFIG_SERIAL_MAX3100) += max3100.o
49obj-$(CONFIG_SERIAL_MAX3107) += max3107.o
50obj-$(CONFIG_SERIAL_MAX3107_AAVA) += max3107-aava.o
51obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o
52obj-$(CONFIG_SERIAL_MUX) += mux.o
53obj-$(CONFIG_SERIAL_68328) += 68328serial.o
54obj-$(CONFIG_SERIAL_68360) += 68360serial.o
55obj-$(CONFIG_SERIAL_MCF) += mcf.o
56obj-$(CONFIG_SERIAL_PMACZILOG) += pmac_zilog.o
57obj-$(CONFIG_SERIAL_LH7A40X) += serial_lh7a40x.o
58obj-$(CONFIG_SERIAL_DZ) += dz.o
59obj-$(CONFIG_SERIAL_ZS) += zs.o
60obj-$(CONFIG_SERIAL_SH_SCI) += sh-sci.o
61obj-$(CONFIG_SERIAL_SGI_L1_CONSOLE) += sn_console.o
62obj-$(CONFIG_SERIAL_CPM) += cpm_uart/
63obj-$(CONFIG_SERIAL_IMX) += imx.o
64obj-$(CONFIG_SERIAL_MPC52xx) += mpc52xx_uart.o
65obj-$(CONFIG_SERIAL_ICOM) += icom.o
66obj-$(CONFIG_SERIAL_M32R_SIO) += m32r_sio.o
67obj-$(CONFIG_SERIAL_MPSC) += mpsc.o
68obj-$(CONFIG_SERIAL_SB1250_DUART) += sb1250-duart.o
69obj-$(CONFIG_ETRAX_SERIAL) += crisv10.o
70obj-$(CONFIG_SERIAL_SC26XX) += sc26xx.o
71obj-$(CONFIG_SERIAL_JSM) += jsm/
72obj-$(CONFIG_SERIAL_TXX9) += serial_txx9.o
73obj-$(CONFIG_SERIAL_VR41XX) += vr41xx_siu.o
74obj-$(CONFIG_SERIAL_SGI_IOC4) += ioc4_serial.o
75obj-$(CONFIG_SERIAL_SGI_IOC3) += ioc3_serial.o
76obj-$(CONFIG_SERIAL_ATMEL) += atmel_serial.o
77obj-$(CONFIG_SERIAL_UARTLITE) += uartlite.o
78obj-$(CONFIG_SERIAL_MSM) += msm_serial.o
79obj-$(CONFIG_SERIAL_NETX) += netx-serial.o
80obj-$(CONFIG_SERIAL_OF_PLATFORM) += of_serial.o
81obj-$(CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL) += nwpserial.o
82obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o
83obj-$(CONFIG_KGDB_SERIAL_CONSOLE) += kgdboc.o
84obj-$(CONFIG_SERIAL_QE) += ucc_uart.o
85obj-$(CONFIG_SERIAL_TIMBERDALE) += timbuart.o
86obj-$(CONFIG_SERIAL_GRLIB_GAISLER_APBUART) += apbuart.o
87obj-$(CONFIG_SERIAL_ALTERA_JTAGUART) += altera_jtaguart.o
88obj-$(CONFIG_SERIAL_ALTERA_UART) += altera_uart.o
89obj-$(CONFIG_SERIAL_MRST_MAX3110) += mrst_max3110.o
90obj-$(CONFIG_SERIAL_MFD_HSU) += mfd.o
diff --git a/drivers/serial/altera_jtaguart.c b/drivers/serial/altera_jtaguart.c
deleted file mode 100644
index f9b49b5ff5e1..000000000000
--- a/drivers/serial/altera_jtaguart.c
+++ /dev/null
@@ -1,504 +0,0 @@
1/*
2 * altera_jtaguart.c -- Altera JTAG UART driver
3 *
4 * Based on mcf.c -- Freescale ColdFire UART driver
5 *
6 * (C) Copyright 2003-2007, Greg Ungerer <gerg@snapgear.com>
7 * (C) Copyright 2008, Thomas Chou <thomas@wytron.com.tw>
8 * (C) Copyright 2010, Tobias Klauser <tklauser@distanz.ch>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/interrupt.h>
19#include <linux/module.h>
20#include <linux/console.h>
21#include <linux/tty.h>
22#include <linux/tty_flip.h>
23#include <linux/serial.h>
24#include <linux/serial_core.h>
25#include <linux/platform_device.h>
26#include <linux/io.h>
27#include <linux/altera_jtaguart.h>
28
29#define DRV_NAME "altera_jtaguart"
30
31/*
32 * Altera JTAG UART register definitions according to the Altera JTAG UART
33 * datasheet: http://www.altera.com/literature/hb/nios2/n2cpu_nii51009.pdf
34 */
35
36#define ALTERA_JTAGUART_SIZE 8
37
38#define ALTERA_JTAGUART_DATA_REG 0
39
40#define ALTERA_JTAGUART_DATA_DATA_MSK 0x000000FF
41#define ALTERA_JTAGUART_DATA_RVALID_MSK 0x00008000
42#define ALTERA_JTAGUART_DATA_RAVAIL_MSK 0xFFFF0000
43#define ALTERA_JTAGUART_DATA_RAVAIL_OFF 16
44
45#define ALTERA_JTAGUART_CONTROL_REG 4
46
47#define ALTERA_JTAGUART_CONTROL_RE_MSK 0x00000001
48#define ALTERA_JTAGUART_CONTROL_WE_MSK 0x00000002
49#define ALTERA_JTAGUART_CONTROL_RI_MSK 0x00000100
50#define ALTERA_JTAGUART_CONTROL_RI_OFF 8
51#define ALTERA_JTAGUART_CONTROL_WI_MSK 0x00000200
52#define ALTERA_JTAGUART_CONTROL_AC_MSK 0x00000400
53#define ALTERA_JTAGUART_CONTROL_WSPACE_MSK 0xFFFF0000
54#define ALTERA_JTAGUART_CONTROL_WSPACE_OFF 16
55
56/*
57 * Local per-uart structure.
58 */
59struct altera_jtaguart {
60 struct uart_port port;
61 unsigned int sigs; /* Local copy of line sigs */
62 unsigned long imr; /* Local IMR mirror */
63};
64
65static unsigned int altera_jtaguart_tx_empty(struct uart_port *port)
66{
67 return (readl(port->membase + ALTERA_JTAGUART_CONTROL_REG) &
68 ALTERA_JTAGUART_CONTROL_WSPACE_MSK) ? TIOCSER_TEMT : 0;
69}
70
71static unsigned int altera_jtaguart_get_mctrl(struct uart_port *port)
72{
73 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
74}
75
76static void altera_jtaguart_set_mctrl(struct uart_port *port, unsigned int sigs)
77{
78}
79
80static void altera_jtaguart_start_tx(struct uart_port *port)
81{
82 struct altera_jtaguart *pp =
83 container_of(port, struct altera_jtaguart, port);
84
85 pp->imr |= ALTERA_JTAGUART_CONTROL_WE_MSK;
86 writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG);
87}
88
89static void altera_jtaguart_stop_tx(struct uart_port *port)
90{
91 struct altera_jtaguart *pp =
92 container_of(port, struct altera_jtaguart, port);
93
94 pp->imr &= ~ALTERA_JTAGUART_CONTROL_WE_MSK;
95 writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG);
96}
97
98static void altera_jtaguart_stop_rx(struct uart_port *port)
99{
100 struct altera_jtaguart *pp =
101 container_of(port, struct altera_jtaguart, port);
102
103 pp->imr &= ~ALTERA_JTAGUART_CONTROL_RE_MSK;
104 writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG);
105}
106
107static void altera_jtaguart_break_ctl(struct uart_port *port, int break_state)
108{
109}
110
111static void altera_jtaguart_enable_ms(struct uart_port *port)
112{
113}
114
115static void altera_jtaguart_set_termios(struct uart_port *port,
116 struct ktermios *termios,
117 struct ktermios *old)
118{
119 /* Just copy the old termios settings back */
120 if (old)
121 tty_termios_copy_hw(termios, old);
122}
123
124static void altera_jtaguart_rx_chars(struct altera_jtaguart *pp)
125{
126 struct uart_port *port = &pp->port;
127 unsigned char ch, flag;
128 unsigned long status;
129
130 while ((status = readl(port->membase + ALTERA_JTAGUART_DATA_REG)) &
131 ALTERA_JTAGUART_DATA_RVALID_MSK) {
132 ch = status & ALTERA_JTAGUART_DATA_DATA_MSK;
133 flag = TTY_NORMAL;
134 port->icount.rx++;
135
136 if (uart_handle_sysrq_char(port, ch))
137 continue;
138 uart_insert_char(port, 0, 0, ch, flag);
139 }
140
141 tty_flip_buffer_push(port->state->port.tty);
142}
143
144static void altera_jtaguart_tx_chars(struct altera_jtaguart *pp)
145{
146 struct uart_port *port = &pp->port;
147 struct circ_buf *xmit = &port->state->xmit;
148 unsigned int pending, count;
149
150 if (port->x_char) {
151 /* Send special char - probably flow control */
152 writel(port->x_char, port->membase + ALTERA_JTAGUART_DATA_REG);
153 port->x_char = 0;
154 port->icount.tx++;
155 return;
156 }
157
158 pending = uart_circ_chars_pending(xmit);
159 if (pending > 0) {
160 count = (readl(port->membase + ALTERA_JTAGUART_CONTROL_REG) &
161 ALTERA_JTAGUART_CONTROL_WSPACE_MSK) >>
162 ALTERA_JTAGUART_CONTROL_WSPACE_OFF;
163 if (count > pending)
164 count = pending;
165 if (count > 0) {
166 pending -= count;
167 while (count--) {
168 writel(xmit->buf[xmit->tail],
169 port->membase + ALTERA_JTAGUART_DATA_REG);
170 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
171 port->icount.tx++;
172 }
173 if (pending < WAKEUP_CHARS)
174 uart_write_wakeup(port);
175 }
176 }
177
178 if (pending == 0) {
179 pp->imr &= ~ALTERA_JTAGUART_CONTROL_WE_MSK;
180 writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG);
181 }
182}
183
184static irqreturn_t altera_jtaguart_interrupt(int irq, void *data)
185{
186 struct uart_port *port = data;
187 struct altera_jtaguart *pp =
188 container_of(port, struct altera_jtaguart, port);
189 unsigned int isr;
190
191 isr = (readl(port->membase + ALTERA_JTAGUART_CONTROL_REG) >>
192 ALTERA_JTAGUART_CONTROL_RI_OFF) & pp->imr;
193
194 spin_lock(&port->lock);
195
196 if (isr & ALTERA_JTAGUART_CONTROL_RE_MSK)
197 altera_jtaguart_rx_chars(pp);
198 if (isr & ALTERA_JTAGUART_CONTROL_WE_MSK)
199 altera_jtaguart_tx_chars(pp);
200
201 spin_unlock(&port->lock);
202
203 return IRQ_RETVAL(isr);
204}
205
206static void altera_jtaguart_config_port(struct uart_port *port, int flags)
207{
208 port->type = PORT_ALTERA_JTAGUART;
209
210 /* Clear mask, so no surprise interrupts. */
211 writel(0, port->membase + ALTERA_JTAGUART_CONTROL_REG);
212}
213
214static int altera_jtaguart_startup(struct uart_port *port)
215{
216 struct altera_jtaguart *pp =
217 container_of(port, struct altera_jtaguart, port);
218 unsigned long flags;
219 int ret;
220
221 ret = request_irq(port->irq, altera_jtaguart_interrupt, IRQF_DISABLED,
222 DRV_NAME, port);
223 if (ret) {
224 pr_err(DRV_NAME ": unable to attach Altera JTAG UART %d "
225 "interrupt vector=%d\n", port->line, port->irq);
226 return ret;
227 }
228
229 spin_lock_irqsave(&port->lock, flags);
230
231 /* Enable RX interrupts now */
232 pp->imr = ALTERA_JTAGUART_CONTROL_RE_MSK;
233 writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG);
234
235 spin_unlock_irqrestore(&port->lock, flags);
236
237 return 0;
238}
239
240static void altera_jtaguart_shutdown(struct uart_port *port)
241{
242 struct altera_jtaguart *pp =
243 container_of(port, struct altera_jtaguart, port);
244 unsigned long flags;
245
246 spin_lock_irqsave(&port->lock, flags);
247
248 /* Disable all interrupts now */
249 pp->imr = 0;
250 writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG);
251
252 spin_unlock_irqrestore(&port->lock, flags);
253
254 free_irq(port->irq, port);
255}
256
257static const char *altera_jtaguart_type(struct uart_port *port)
258{
259 return (port->type == PORT_ALTERA_JTAGUART) ? "Altera JTAG UART" : NULL;
260}
261
262static int altera_jtaguart_request_port(struct uart_port *port)
263{
264 /* UARTs always present */
265 return 0;
266}
267
268static void altera_jtaguart_release_port(struct uart_port *port)
269{
270 /* Nothing to release... */
271}
272
273static int altera_jtaguart_verify_port(struct uart_port *port,
274 struct serial_struct *ser)
275{
276 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ALTERA_JTAGUART)
277 return -EINVAL;
278 return 0;
279}
280
281/*
282 * Define the basic serial functions we support.
283 */
284static struct uart_ops altera_jtaguart_ops = {
285 .tx_empty = altera_jtaguart_tx_empty,
286 .get_mctrl = altera_jtaguart_get_mctrl,
287 .set_mctrl = altera_jtaguart_set_mctrl,
288 .start_tx = altera_jtaguart_start_tx,
289 .stop_tx = altera_jtaguart_stop_tx,
290 .stop_rx = altera_jtaguart_stop_rx,
291 .enable_ms = altera_jtaguart_enable_ms,
292 .break_ctl = altera_jtaguart_break_ctl,
293 .startup = altera_jtaguart_startup,
294 .shutdown = altera_jtaguart_shutdown,
295 .set_termios = altera_jtaguart_set_termios,
296 .type = altera_jtaguart_type,
297 .request_port = altera_jtaguart_request_port,
298 .release_port = altera_jtaguart_release_port,
299 .config_port = altera_jtaguart_config_port,
300 .verify_port = altera_jtaguart_verify_port,
301};
302
303#define ALTERA_JTAGUART_MAXPORTS 1
304static struct altera_jtaguart altera_jtaguart_ports[ALTERA_JTAGUART_MAXPORTS];
305
306#if defined(CONFIG_SERIAL_ALTERA_JTAGUART_CONSOLE)
307
308int __init early_altera_jtaguart_setup(struct altera_jtaguart_platform_uart
309 *platp)
310{
311 struct uart_port *port;
312 int i;
313
314 for (i = 0; i < ALTERA_JTAGUART_MAXPORTS && platp[i].mapbase; i++) {
315 port = &altera_jtaguart_ports[i].port;
316
317 port->line = i;
318 port->type = PORT_ALTERA_JTAGUART;
319 port->mapbase = platp[i].mapbase;
320 port->membase = ioremap(port->mapbase, ALTERA_JTAGUART_SIZE);
321 port->iotype = SERIAL_IO_MEM;
322 port->irq = platp[i].irq;
323 port->flags = ASYNC_BOOT_AUTOCONF;
324 port->ops = &altera_jtaguart_ops;
325 }
326
327 return 0;
328}
329
330#if defined(CONFIG_SERIAL_ALTERA_JTAGUART_CONSOLE_BYPASS)
331static void altera_jtaguart_console_putc(struct console *co, const char c)
332{
333 struct uart_port *port = &(altera_jtaguart_ports + co->index)->port;
334 unsigned long status;
335 unsigned long flags;
336
337 spin_lock_irqsave(&port->lock, flags);
338 while (((status = readl(port->membase + ALTERA_JTAGUART_CONTROL_REG)) &
339 ALTERA_JTAGUART_CONTROL_WSPACE_MSK) == 0) {
340 if ((status & ALTERA_JTAGUART_CONTROL_AC_MSK) == 0) {
341 spin_unlock_irqrestore(&port->lock, flags);
342 return; /* no connection activity */
343 }
344 spin_unlock_irqrestore(&port->lock, flags);
345 cpu_relax();
346 spin_lock_irqsave(&port->lock, flags);
347 }
348 writel(c, port->membase + ALTERA_JTAGUART_DATA_REG);
349 spin_unlock_irqrestore(&port->lock, flags);
350}
351#else
352static void altera_jtaguart_console_putc(struct console *co, const char c)
353{
354 struct uart_port *port = &(altera_jtaguart_ports + co->index)->port;
355 unsigned long flags;
356
357 spin_lock_irqsave(&port->lock, flags);
358 while ((readl(port->membase + ALTERA_JTAGUART_CONTROL_REG) &
359 ALTERA_JTAGUART_CONTROL_WSPACE_MSK) == 0) {
360 spin_unlock_irqrestore(&port->lock, flags);
361 cpu_relax();
362 spin_lock_irqsave(&port->lock, flags);
363 }
364 writel(c, port->membase + ALTERA_JTAGUART_DATA_REG);
365 spin_unlock_irqrestore(&port->lock, flags);
366}
367#endif
368
369static void altera_jtaguart_console_write(struct console *co, const char *s,
370 unsigned int count)
371{
372 for (; count; count--, s++) {
373 altera_jtaguart_console_putc(co, *s);
374 if (*s == '\n')
375 altera_jtaguart_console_putc(co, '\r');
376 }
377}
378
379static int __init altera_jtaguart_console_setup(struct console *co,
380 char *options)
381{
382 struct uart_port *port;
383
384 if (co->index < 0 || co->index >= ALTERA_JTAGUART_MAXPORTS)
385 return -EINVAL;
386 port = &altera_jtaguart_ports[co->index].port;
387 if (port->membase == 0)
388 return -ENODEV;
389 return 0;
390}
391
392static struct uart_driver altera_jtaguart_driver;
393
394static struct console altera_jtaguart_console = {
395 .name = "ttyJ",
396 .write = altera_jtaguart_console_write,
397 .device = uart_console_device,
398 .setup = altera_jtaguart_console_setup,
399 .flags = CON_PRINTBUFFER,
400 .index = -1,
401 .data = &altera_jtaguart_driver,
402};
403
404static int __init altera_jtaguart_console_init(void)
405{
406 register_console(&altera_jtaguart_console);
407 return 0;
408}
409
410console_initcall(altera_jtaguart_console_init);
411
412#define ALTERA_JTAGUART_CONSOLE (&altera_jtaguart_console)
413
414#else
415
416#define ALTERA_JTAGUART_CONSOLE NULL
417
418#endif /* CONFIG_ALTERA_JTAGUART_CONSOLE */
419
420static struct uart_driver altera_jtaguart_driver = {
421 .owner = THIS_MODULE,
422 .driver_name = "altera_jtaguart",
423 .dev_name = "ttyJ",
424 .major = ALTERA_JTAGUART_MAJOR,
425 .minor = ALTERA_JTAGUART_MINOR,
426 .nr = ALTERA_JTAGUART_MAXPORTS,
427 .cons = ALTERA_JTAGUART_CONSOLE,
428};
429
430static int __devinit altera_jtaguart_probe(struct platform_device *pdev)
431{
432 struct altera_jtaguart_platform_uart *platp = pdev->dev.platform_data;
433 struct uart_port *port;
434 int i;
435
436 for (i = 0; i < ALTERA_JTAGUART_MAXPORTS && platp[i].mapbase; i++) {
437 port = &altera_jtaguart_ports[i].port;
438
439 port->line = i;
440 port->type = PORT_ALTERA_JTAGUART;
441 port->mapbase = platp[i].mapbase;
442 port->membase = ioremap(port->mapbase, ALTERA_JTAGUART_SIZE);
443 port->iotype = SERIAL_IO_MEM;
444 port->irq = platp[i].irq;
445 port->ops = &altera_jtaguart_ops;
446 port->flags = ASYNC_BOOT_AUTOCONF;
447
448 uart_add_one_port(&altera_jtaguart_driver, port);
449 }
450
451 return 0;
452}
453
454static int __devexit altera_jtaguart_remove(struct platform_device *pdev)
455{
456 struct uart_port *port;
457 int i;
458
459 for (i = 0; i < ALTERA_JTAGUART_MAXPORTS; i++) {
460 port = &altera_jtaguart_ports[i].port;
461 if (port)
462 uart_remove_one_port(&altera_jtaguart_driver, port);
463 }
464
465 return 0;
466}
467
468static struct platform_driver altera_jtaguart_platform_driver = {
469 .probe = altera_jtaguart_probe,
470 .remove = __devexit_p(altera_jtaguart_remove),
471 .driver = {
472 .name = DRV_NAME,
473 .owner = THIS_MODULE,
474 },
475};
476
477static int __init altera_jtaguart_init(void)
478{
479 int rc;
480
481 rc = uart_register_driver(&altera_jtaguart_driver);
482 if (rc)
483 return rc;
484 rc = platform_driver_register(&altera_jtaguart_platform_driver);
485 if (rc) {
486 uart_unregister_driver(&altera_jtaguart_driver);
487 return rc;
488 }
489 return 0;
490}
491
492static void __exit altera_jtaguart_exit(void)
493{
494 platform_driver_unregister(&altera_jtaguart_platform_driver);
495 uart_unregister_driver(&altera_jtaguart_driver);
496}
497
498module_init(altera_jtaguart_init);
499module_exit(altera_jtaguart_exit);
500
501MODULE_DESCRIPTION("Altera JTAG UART driver");
502MODULE_AUTHOR("Thomas Chou <thomas@wytron.com.tw>");
503MODULE_LICENSE("GPL");
504MODULE_ALIAS("platform:" DRV_NAME);
diff --git a/drivers/serial/altera_uart.c b/drivers/serial/altera_uart.c
deleted file mode 100644
index f8d8a00554da..000000000000
--- a/drivers/serial/altera_uart.c
+++ /dev/null
@@ -1,552 +0,0 @@
1/*
2 * altera_uart.c -- Altera UART driver
3 *
4 * Based on mcf.c -- Freescale ColdFire UART driver
5 *
6 * (C) Copyright 2003-2007, Greg Ungerer <gerg@snapgear.com>
7 * (C) Copyright 2008, Thomas Chou <thomas@wytron.com.tw>
8 * (C) Copyright 2010, Tobias Klauser <tklauser@distanz.ch>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/interrupt.h>
19#include <linux/module.h>
20#include <linux/console.h>
21#include <linux/tty.h>
22#include <linux/tty_flip.h>
23#include <linux/serial.h>
24#include <linux/serial_core.h>
25#include <linux/platform_device.h>
26#include <linux/io.h>
27#include <linux/altera_uart.h>
28
29#define DRV_NAME "altera_uart"
30
31/*
32 * Altera UART register definitions according to the Nios UART datasheet:
33 * http://www.altera.com/literature/ds/ds_nios_uart.pdf
34 */
35
36#define ALTERA_UART_SIZE 32
37
38#define ALTERA_UART_RXDATA_REG 0
39#define ALTERA_UART_TXDATA_REG 4
40#define ALTERA_UART_STATUS_REG 8
41#define ALTERA_UART_CONTROL_REG 12
42#define ALTERA_UART_DIVISOR_REG 16
43#define ALTERA_UART_EOP_REG 20
44
45#define ALTERA_UART_STATUS_PE_MSK 0x0001 /* parity error */
46#define ALTERA_UART_STATUS_FE_MSK 0x0002 /* framing error */
47#define ALTERA_UART_STATUS_BRK_MSK 0x0004 /* break */
48#define ALTERA_UART_STATUS_ROE_MSK 0x0008 /* RX overrun error */
49#define ALTERA_UART_STATUS_TOE_MSK 0x0010 /* TX overrun error */
50#define ALTERA_UART_STATUS_TMT_MSK 0x0020 /* TX shift register state */
51#define ALTERA_UART_STATUS_TRDY_MSK 0x0040 /* TX ready */
52#define ALTERA_UART_STATUS_RRDY_MSK 0x0080 /* RX ready */
53#define ALTERA_UART_STATUS_E_MSK 0x0100 /* exception condition */
54#define ALTERA_UART_STATUS_DCTS_MSK 0x0400 /* CTS logic-level change */
55#define ALTERA_UART_STATUS_CTS_MSK 0x0800 /* CTS logic state */
56#define ALTERA_UART_STATUS_EOP_MSK 0x1000 /* EOP written/read */
57
58 /* Enable interrupt on... */
59#define ALTERA_UART_CONTROL_PE_MSK 0x0001 /* ...parity error */
60#define ALTERA_UART_CONTROL_FE_MSK 0x0002 /* ...framing error */
61#define ALTERA_UART_CONTROL_BRK_MSK 0x0004 /* ...break */
62#define ALTERA_UART_CONTROL_ROE_MSK 0x0008 /* ...RX overrun */
63#define ALTERA_UART_CONTROL_TOE_MSK 0x0010 /* ...TX overrun */
64#define ALTERA_UART_CONTROL_TMT_MSK 0x0020 /* ...TX shift register empty */
65#define ALTERA_UART_CONTROL_TRDY_MSK 0x0040 /* ...TX ready */
66#define ALTERA_UART_CONTROL_RRDY_MSK 0x0080 /* ...RX ready */
67#define ALTERA_UART_CONTROL_E_MSK 0x0100 /* ...exception*/
68
69#define ALTERA_UART_CONTROL_TRBK_MSK 0x0200 /* TX break */
70#define ALTERA_UART_CONTROL_DCTS_MSK 0x0400 /* Interrupt on CTS change */
71#define ALTERA_UART_CONTROL_RTS_MSK 0x0800 /* RTS signal */
72#define ALTERA_UART_CONTROL_EOP_MSK 0x1000 /* Interrupt on EOP */
73
74/*
75 * Local per-uart structure.
76 */
77struct altera_uart {
78 struct uart_port port;
79 unsigned int sigs; /* Local copy of line sigs */
80 unsigned short imr; /* Local IMR mirror */
81};
82
83static unsigned int altera_uart_tx_empty(struct uart_port *port)
84{
85 return (readl(port->membase + ALTERA_UART_STATUS_REG) &
86 ALTERA_UART_STATUS_TMT_MSK) ? TIOCSER_TEMT : 0;
87}
88
89static unsigned int altera_uart_get_mctrl(struct uart_port *port)
90{
91 struct altera_uart *pp = container_of(port, struct altera_uart, port);
92 unsigned int sigs;
93
94 sigs =
95 (readl(port->membase + ALTERA_UART_STATUS_REG) &
96 ALTERA_UART_STATUS_CTS_MSK) ? TIOCM_CTS : 0;
97 sigs |= (pp->sigs & TIOCM_RTS);
98
99 return sigs;
100}
101
102static void altera_uart_set_mctrl(struct uart_port *port, unsigned int sigs)
103{
104 struct altera_uart *pp = container_of(port, struct altera_uart, port);
105
106 pp->sigs = sigs;
107 if (sigs & TIOCM_RTS)
108 pp->imr |= ALTERA_UART_CONTROL_RTS_MSK;
109 else
110 pp->imr &= ~ALTERA_UART_CONTROL_RTS_MSK;
111 writel(pp->imr, port->membase + ALTERA_UART_CONTROL_REG);
112}
113
114static void altera_uart_start_tx(struct uart_port *port)
115{
116 struct altera_uart *pp = container_of(port, struct altera_uart, port);
117
118 pp->imr |= ALTERA_UART_CONTROL_TRDY_MSK;
119 writel(pp->imr, port->membase + ALTERA_UART_CONTROL_REG);
120}
121
122static void altera_uart_stop_tx(struct uart_port *port)
123{
124 struct altera_uart *pp = container_of(port, struct altera_uart, port);
125
126 pp->imr &= ~ALTERA_UART_CONTROL_TRDY_MSK;
127 writel(pp->imr, port->membase + ALTERA_UART_CONTROL_REG);
128}
129
130static void altera_uart_stop_rx(struct uart_port *port)
131{
132 struct altera_uart *pp = container_of(port, struct altera_uart, port);
133
134 pp->imr &= ~ALTERA_UART_CONTROL_RRDY_MSK;
135 writel(pp->imr, port->membase + ALTERA_UART_CONTROL_REG);
136}
137
138static void altera_uart_break_ctl(struct uart_port *port, int break_state)
139{
140 struct altera_uart *pp = container_of(port, struct altera_uart, port);
141 unsigned long flags;
142
143 spin_lock_irqsave(&port->lock, flags);
144 if (break_state == -1)
145 pp->imr |= ALTERA_UART_CONTROL_TRBK_MSK;
146 else
147 pp->imr &= ~ALTERA_UART_CONTROL_TRBK_MSK;
148 writel(pp->imr, port->membase + ALTERA_UART_CONTROL_REG);
149 spin_unlock_irqrestore(&port->lock, flags);
150}
151
152static void altera_uart_enable_ms(struct uart_port *port)
153{
154}
155
156static void altera_uart_set_termios(struct uart_port *port,
157 struct ktermios *termios,
158 struct ktermios *old)
159{
160 unsigned long flags;
161 unsigned int baud, baudclk;
162
163 baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
164 baudclk = port->uartclk / baud;
165
166 if (old)
167 tty_termios_copy_hw(termios, old);
168 tty_termios_encode_baud_rate(termios, baud, baud);
169
170 spin_lock_irqsave(&port->lock, flags);
171 writel(baudclk, port->membase + ALTERA_UART_DIVISOR_REG);
172 spin_unlock_irqrestore(&port->lock, flags);
173}
174
175static void altera_uart_rx_chars(struct altera_uart *pp)
176{
177 struct uart_port *port = &pp->port;
178 unsigned char ch, flag;
179 unsigned short status;
180
181 while ((status = readl(port->membase + ALTERA_UART_STATUS_REG)) &
182 ALTERA_UART_STATUS_RRDY_MSK) {
183 ch = readl(port->membase + ALTERA_UART_RXDATA_REG);
184 flag = TTY_NORMAL;
185 port->icount.rx++;
186
187 if (status & ALTERA_UART_STATUS_E_MSK) {
188 writel(status, port->membase + ALTERA_UART_STATUS_REG);
189
190 if (status & ALTERA_UART_STATUS_BRK_MSK) {
191 port->icount.brk++;
192 if (uart_handle_break(port))
193 continue;
194 } else if (status & ALTERA_UART_STATUS_PE_MSK) {
195 port->icount.parity++;
196 } else if (status & ALTERA_UART_STATUS_ROE_MSK) {
197 port->icount.overrun++;
198 } else if (status & ALTERA_UART_STATUS_FE_MSK) {
199 port->icount.frame++;
200 }
201
202 status &= port->read_status_mask;
203
204 if (status & ALTERA_UART_STATUS_BRK_MSK)
205 flag = TTY_BREAK;
206 else if (status & ALTERA_UART_STATUS_PE_MSK)
207 flag = TTY_PARITY;
208 else if (status & ALTERA_UART_STATUS_FE_MSK)
209 flag = TTY_FRAME;
210 }
211
212 if (uart_handle_sysrq_char(port, ch))
213 continue;
214 uart_insert_char(port, status, ALTERA_UART_STATUS_ROE_MSK, ch,
215 flag);
216 }
217
218 tty_flip_buffer_push(port->state->port.tty);
219}
220
221static void altera_uart_tx_chars(struct altera_uart *pp)
222{
223 struct uart_port *port = &pp->port;
224 struct circ_buf *xmit = &port->state->xmit;
225
226 if (port->x_char) {
227 /* Send special char - probably flow control */
228 writel(port->x_char, port->membase + ALTERA_UART_TXDATA_REG);
229 port->x_char = 0;
230 port->icount.tx++;
231 return;
232 }
233
234 while (readl(port->membase + ALTERA_UART_STATUS_REG) &
235 ALTERA_UART_STATUS_TRDY_MSK) {
236 if (xmit->head == xmit->tail)
237 break;
238 writel(xmit->buf[xmit->tail],
239 port->membase + ALTERA_UART_TXDATA_REG);
240 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
241 port->icount.tx++;
242 }
243
244 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
245 uart_write_wakeup(port);
246
247 if (xmit->head == xmit->tail) {
248 pp->imr &= ~ALTERA_UART_CONTROL_TRDY_MSK;
249 writel(pp->imr, port->membase + ALTERA_UART_CONTROL_REG);
250 }
251}
252
253static irqreturn_t altera_uart_interrupt(int irq, void *data)
254{
255 struct uart_port *port = data;
256 struct altera_uart *pp = container_of(port, struct altera_uart, port);
257 unsigned int isr;
258
259 isr = readl(port->membase + ALTERA_UART_STATUS_REG) & pp->imr;
260
261 spin_lock(&port->lock);
262 if (isr & ALTERA_UART_STATUS_RRDY_MSK)
263 altera_uart_rx_chars(pp);
264 if (isr & ALTERA_UART_STATUS_TRDY_MSK)
265 altera_uart_tx_chars(pp);
266 spin_unlock(&port->lock);
267
268 return IRQ_RETVAL(isr);
269}
270
271static void altera_uart_config_port(struct uart_port *port, int flags)
272{
273 port->type = PORT_ALTERA_UART;
274
275 /* Clear mask, so no surprise interrupts. */
276 writel(0, port->membase + ALTERA_UART_CONTROL_REG);
277 /* Clear status register */
278 writel(0, port->membase + ALTERA_UART_STATUS_REG);
279}
280
281static int altera_uart_startup(struct uart_port *port)
282{
283 struct altera_uart *pp = container_of(port, struct altera_uart, port);
284 unsigned long flags;
285 int ret;
286
287 ret = request_irq(port->irq, altera_uart_interrupt, IRQF_DISABLED,
288 DRV_NAME, port);
289 if (ret) {
290 pr_err(DRV_NAME ": unable to attach Altera UART %d "
291 "interrupt vector=%d\n", port->line, port->irq);
292 return ret;
293 }
294
295 spin_lock_irqsave(&port->lock, flags);
296
297 /* Enable RX interrupts now */
298 pp->imr = ALTERA_UART_CONTROL_RRDY_MSK;
299 writel(pp->imr, port->membase + ALTERA_UART_CONTROL_REG);
300
301 spin_unlock_irqrestore(&port->lock, flags);
302
303 return 0;
304}
305
306static void altera_uart_shutdown(struct uart_port *port)
307{
308 struct altera_uart *pp = container_of(port, struct altera_uart, port);
309 unsigned long flags;
310
311 spin_lock_irqsave(&port->lock, flags);
312
313 /* Disable all interrupts now */
314 pp->imr = 0;
315 writel(pp->imr, port->membase + ALTERA_UART_CONTROL_REG);
316
317 spin_unlock_irqrestore(&port->lock, flags);
318
319 free_irq(port->irq, port);
320}
321
322static const char *altera_uart_type(struct uart_port *port)
323{
324 return (port->type == PORT_ALTERA_UART) ? "Altera UART" : NULL;
325}
326
327static int altera_uart_request_port(struct uart_port *port)
328{
329 /* UARTs always present */
330 return 0;
331}
332
333static void altera_uart_release_port(struct uart_port *port)
334{
335 /* Nothing to release... */
336}
337
338static int altera_uart_verify_port(struct uart_port *port,
339 struct serial_struct *ser)
340{
341 if ((ser->type != PORT_UNKNOWN) && (ser->type != PORT_ALTERA_UART))
342 return -EINVAL;
343 return 0;
344}
345
346/*
347 * Define the basic serial functions we support.
348 */
349static struct uart_ops altera_uart_ops = {
350 .tx_empty = altera_uart_tx_empty,
351 .get_mctrl = altera_uart_get_mctrl,
352 .set_mctrl = altera_uart_set_mctrl,
353 .start_tx = altera_uart_start_tx,
354 .stop_tx = altera_uart_stop_tx,
355 .stop_rx = altera_uart_stop_rx,
356 .enable_ms = altera_uart_enable_ms,
357 .break_ctl = altera_uart_break_ctl,
358 .startup = altera_uart_startup,
359 .shutdown = altera_uart_shutdown,
360 .set_termios = altera_uart_set_termios,
361 .type = altera_uart_type,
362 .request_port = altera_uart_request_port,
363 .release_port = altera_uart_release_port,
364 .config_port = altera_uart_config_port,
365 .verify_port = altera_uart_verify_port,
366};
367
368static struct altera_uart altera_uart_ports[CONFIG_SERIAL_ALTERA_UART_MAXPORTS];
369
370#if defined(CONFIG_SERIAL_ALTERA_UART_CONSOLE)
371
372int __init early_altera_uart_setup(struct altera_uart_platform_uart *platp)
373{
374 struct uart_port *port;
375 int i;
376
377 for (i = 0; i < CONFIG_SERIAL_ALTERA_UART_MAXPORTS && platp[i].mapbase; i++) {
378 port = &altera_uart_ports[i].port;
379
380 port->line = i;
381 port->type = PORT_ALTERA_UART;
382 port->mapbase = platp[i].mapbase;
383 port->membase = ioremap(port->mapbase, ALTERA_UART_SIZE);
384 port->iotype = SERIAL_IO_MEM;
385 port->irq = platp[i].irq;
386 port->uartclk = platp[i].uartclk;
387 port->flags = ASYNC_BOOT_AUTOCONF;
388 port->ops = &altera_uart_ops;
389 }
390
391 return 0;
392}
393
394static void altera_uart_console_putc(struct uart_port *port, const char c)
395{
396 while (!(readl(port->membase + ALTERA_UART_STATUS_REG) &
397 ALTERA_UART_STATUS_TRDY_MSK))
398 cpu_relax();
399
400 writel(c, port->membase + ALTERA_UART_TXDATA_REG);
401}
402
403static void altera_uart_console_write(struct console *co, const char *s,
404 unsigned int count)
405{
406 struct uart_port *port = &(altera_uart_ports + co->index)->port;
407
408 for (; count; count--, s++) {
409 altera_uart_console_putc(port, *s);
410 if (*s == '\n')
411 altera_uart_console_putc(port, '\r');
412 }
413}
414
415static int __init altera_uart_console_setup(struct console *co, char *options)
416{
417 struct uart_port *port;
418 int baud = CONFIG_SERIAL_ALTERA_UART_BAUDRATE;
419 int bits = 8;
420 int parity = 'n';
421 int flow = 'n';
422
423 if (co->index < 0 || co->index >= CONFIG_SERIAL_ALTERA_UART_MAXPORTS)
424 return -EINVAL;
425 port = &altera_uart_ports[co->index].port;
426 if (port->membase == 0)
427 return -ENODEV;
428
429 if (options)
430 uart_parse_options(options, &baud, &parity, &bits, &flow);
431
432 return uart_set_options(port, co, baud, parity, bits, flow);
433}
434
435static struct uart_driver altera_uart_driver;
436
437static struct console altera_uart_console = {
438 .name = "ttyS",
439 .write = altera_uart_console_write,
440 .device = uart_console_device,
441 .setup = altera_uart_console_setup,
442 .flags = CON_PRINTBUFFER,
443 .index = -1,
444 .data = &altera_uart_driver,
445};
446
447static int __init altera_uart_console_init(void)
448{
449 register_console(&altera_uart_console);
450 return 0;
451}
452
453console_initcall(altera_uart_console_init);
454
455#define ALTERA_UART_CONSOLE (&altera_uart_console)
456
457#else
458
459#define ALTERA_UART_CONSOLE NULL
460
461#endif /* CONFIG_ALTERA_UART_CONSOLE */
462
463/*
464 * Define the altera_uart UART driver structure.
465 */
466static struct uart_driver altera_uart_driver = {
467 .owner = THIS_MODULE,
468 .driver_name = DRV_NAME,
469 .dev_name = "ttyS",
470 .major = TTY_MAJOR,
471 .minor = 64,
472 .nr = CONFIG_SERIAL_ALTERA_UART_MAXPORTS,
473 .cons = ALTERA_UART_CONSOLE,
474};
475
476static int __devinit altera_uart_probe(struct platform_device *pdev)
477{
478 struct altera_uart_platform_uart *platp = pdev->dev.platform_data;
479 struct uart_port *port;
480 int i;
481
482 for (i = 0; i < CONFIG_SERIAL_ALTERA_UART_MAXPORTS && platp[i].mapbase; i++) {
483 port = &altera_uart_ports[i].port;
484
485 port->line = i;
486 port->type = PORT_ALTERA_UART;
487 port->mapbase = platp[i].mapbase;
488 port->membase = ioremap(port->mapbase, ALTERA_UART_SIZE);
489 port->iotype = SERIAL_IO_MEM;
490 port->irq = platp[i].irq;
491 port->uartclk = platp[i].uartclk;
492 port->ops = &altera_uart_ops;
493 port->flags = ASYNC_BOOT_AUTOCONF;
494
495 uart_add_one_port(&altera_uart_driver, port);
496 }
497
498 return 0;
499}
500
501static int __devexit altera_uart_remove(struct platform_device *pdev)
502{
503 struct uart_port *port;
504 int i;
505
506 for (i = 0; i < CONFIG_SERIAL_ALTERA_UART_MAXPORTS; i++) {
507 port = &altera_uart_ports[i].port;
508 if (port)
509 uart_remove_one_port(&altera_uart_driver, port);
510 }
511
512 return 0;
513}
514
515static struct platform_driver altera_uart_platform_driver = {
516 .probe = altera_uart_probe,
517 .remove = __devexit_p(altera_uart_remove),
518 .driver = {
519 .name = DRV_NAME,
520 .owner = THIS_MODULE,
521 .pm = NULL,
522 },
523};
524
525static int __init altera_uart_init(void)
526{
527 int rc;
528
529 rc = uart_register_driver(&altera_uart_driver);
530 if (rc)
531 return rc;
532 rc = platform_driver_register(&altera_uart_platform_driver);
533 if (rc) {
534 uart_unregister_driver(&altera_uart_driver);
535 return rc;
536 }
537 return 0;
538}
539
540static void __exit altera_uart_exit(void)
541{
542 platform_driver_unregister(&altera_uart_platform_driver);
543 uart_unregister_driver(&altera_uart_driver);
544}
545
546module_init(altera_uart_init);
547module_exit(altera_uart_exit);
548
549MODULE_DESCRIPTION("Altera UART driver");
550MODULE_AUTHOR("Thomas Chou <thomas@wytron.com.tw>");
551MODULE_LICENSE("GPL");
552MODULE_ALIAS("platform:" DRV_NAME);
diff --git a/drivers/serial/amba-pl010.c b/drivers/serial/amba-pl010.c
deleted file mode 100644
index 2904aa044126..000000000000
--- a/drivers/serial/amba-pl010.c
+++ /dev/null
@@ -1,825 +0,0 @@
1/*
2 * linux/drivers/char/amba.c
3 *
4 * Driver for AMBA serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright 1999 ARM Limited
9 * Copyright (C) 2000 Deep Blue Solutions Ltd.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 * This is a generic driver for ARM AMBA-type serial ports. They
26 * have a lot of 16550-like features, but are not register compatible.
27 * Note that although they do have CTS, DCD and DSR inputs, they do
28 * not have an RI input, nor do they have DTR or RTS outputs. If
29 * required, these have to be supplied via some other means (eg, GPIO)
30 * and hooked into this driver.
31 */
32
33#if defined(CONFIG_SERIAL_AMBA_PL010_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
34#define SUPPORT_SYSRQ
35#endif
36
37#include <linux/module.h>
38#include <linux/ioport.h>
39#include <linux/init.h>
40#include <linux/console.h>
41#include <linux/sysrq.h>
42#include <linux/device.h>
43#include <linux/tty.h>
44#include <linux/tty_flip.h>
45#include <linux/serial_core.h>
46#include <linux/serial.h>
47#include <linux/amba/bus.h>
48#include <linux/amba/serial.h>
49#include <linux/clk.h>
50#include <linux/slab.h>
51
52#include <asm/io.h>
53
54#define UART_NR 8
55
56#define SERIAL_AMBA_MAJOR 204
57#define SERIAL_AMBA_MINOR 16
58#define SERIAL_AMBA_NR UART_NR
59
60#define AMBA_ISR_PASS_LIMIT 256
61
62#define UART_RX_DATA(s) (((s) & UART01x_FR_RXFE) == 0)
63#define UART_TX_READY(s) (((s) & UART01x_FR_TXFF) == 0)
64
65#define UART_DUMMY_RSR_RX 256
66#define UART_PORT_SIZE 64
67
68/*
69 * We wrap our port structure around the generic uart_port.
70 */
71struct uart_amba_port {
72 struct uart_port port;
73 struct clk *clk;
74 struct amba_device *dev;
75 struct amba_pl010_data *data;
76 unsigned int old_status;
77};
78
79static void pl010_stop_tx(struct uart_port *port)
80{
81 struct uart_amba_port *uap = (struct uart_amba_port *)port;
82 unsigned int cr;
83
84 cr = readb(uap->port.membase + UART010_CR);
85 cr &= ~UART010_CR_TIE;
86 writel(cr, uap->port.membase + UART010_CR);
87}
88
89static void pl010_start_tx(struct uart_port *port)
90{
91 struct uart_amba_port *uap = (struct uart_amba_port *)port;
92 unsigned int cr;
93
94 cr = readb(uap->port.membase + UART010_CR);
95 cr |= UART010_CR_TIE;
96 writel(cr, uap->port.membase + UART010_CR);
97}
98
99static void pl010_stop_rx(struct uart_port *port)
100{
101 struct uart_amba_port *uap = (struct uart_amba_port *)port;
102 unsigned int cr;
103
104 cr = readb(uap->port.membase + UART010_CR);
105 cr &= ~(UART010_CR_RIE | UART010_CR_RTIE);
106 writel(cr, uap->port.membase + UART010_CR);
107}
108
109static void pl010_enable_ms(struct uart_port *port)
110{
111 struct uart_amba_port *uap = (struct uart_amba_port *)port;
112 unsigned int cr;
113
114 cr = readb(uap->port.membase + UART010_CR);
115 cr |= UART010_CR_MSIE;
116 writel(cr, uap->port.membase + UART010_CR);
117}
118
119static void pl010_rx_chars(struct uart_amba_port *uap)
120{
121 struct tty_struct *tty = uap->port.state->port.tty;
122 unsigned int status, ch, flag, rsr, max_count = 256;
123
124 status = readb(uap->port.membase + UART01x_FR);
125 while (UART_RX_DATA(status) && max_count--) {
126 ch = readb(uap->port.membase + UART01x_DR);
127 flag = TTY_NORMAL;
128
129 uap->port.icount.rx++;
130
131 /*
132 * Note that the error handling code is
133 * out of the main execution path
134 */
135 rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
136 if (unlikely(rsr & UART01x_RSR_ANY)) {
137 writel(0, uap->port.membase + UART01x_ECR);
138
139 if (rsr & UART01x_RSR_BE) {
140 rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE);
141 uap->port.icount.brk++;
142 if (uart_handle_break(&uap->port))
143 goto ignore_char;
144 } else if (rsr & UART01x_RSR_PE)
145 uap->port.icount.parity++;
146 else if (rsr & UART01x_RSR_FE)
147 uap->port.icount.frame++;
148 if (rsr & UART01x_RSR_OE)
149 uap->port.icount.overrun++;
150
151 rsr &= uap->port.read_status_mask;
152
153 if (rsr & UART01x_RSR_BE)
154 flag = TTY_BREAK;
155 else if (rsr & UART01x_RSR_PE)
156 flag = TTY_PARITY;
157 else if (rsr & UART01x_RSR_FE)
158 flag = TTY_FRAME;
159 }
160
161 if (uart_handle_sysrq_char(&uap->port, ch))
162 goto ignore_char;
163
164 uart_insert_char(&uap->port, rsr, UART01x_RSR_OE, ch, flag);
165
166 ignore_char:
167 status = readb(uap->port.membase + UART01x_FR);
168 }
169 spin_unlock(&uap->port.lock);
170 tty_flip_buffer_push(tty);
171 spin_lock(&uap->port.lock);
172}
173
174static void pl010_tx_chars(struct uart_amba_port *uap)
175{
176 struct circ_buf *xmit = &uap->port.state->xmit;
177 int count;
178
179 if (uap->port.x_char) {
180 writel(uap->port.x_char, uap->port.membase + UART01x_DR);
181 uap->port.icount.tx++;
182 uap->port.x_char = 0;
183 return;
184 }
185 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
186 pl010_stop_tx(&uap->port);
187 return;
188 }
189
190 count = uap->port.fifosize >> 1;
191 do {
192 writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
193 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
194 uap->port.icount.tx++;
195 if (uart_circ_empty(xmit))
196 break;
197 } while (--count > 0);
198
199 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
200 uart_write_wakeup(&uap->port);
201
202 if (uart_circ_empty(xmit))
203 pl010_stop_tx(&uap->port);
204}
205
206static void pl010_modem_status(struct uart_amba_port *uap)
207{
208 unsigned int status, delta;
209
210 writel(0, uap->port.membase + UART010_ICR);
211
212 status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
213
214 delta = status ^ uap->old_status;
215 uap->old_status = status;
216
217 if (!delta)
218 return;
219
220 if (delta & UART01x_FR_DCD)
221 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
222
223 if (delta & UART01x_FR_DSR)
224 uap->port.icount.dsr++;
225
226 if (delta & UART01x_FR_CTS)
227 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
228
229 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
230}
231
232static irqreturn_t pl010_int(int irq, void *dev_id)
233{
234 struct uart_amba_port *uap = dev_id;
235 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
236 int handled = 0;
237
238 spin_lock(&uap->port.lock);
239
240 status = readb(uap->port.membase + UART010_IIR);
241 if (status) {
242 do {
243 if (status & (UART010_IIR_RTIS | UART010_IIR_RIS))
244 pl010_rx_chars(uap);
245 if (status & UART010_IIR_MIS)
246 pl010_modem_status(uap);
247 if (status & UART010_IIR_TIS)
248 pl010_tx_chars(uap);
249
250 if (pass_counter-- == 0)
251 break;
252
253 status = readb(uap->port.membase + UART010_IIR);
254 } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS |
255 UART010_IIR_TIS));
256 handled = 1;
257 }
258
259 spin_unlock(&uap->port.lock);
260
261 return IRQ_RETVAL(handled);
262}
263
264static unsigned int pl010_tx_empty(struct uart_port *port)
265{
266 struct uart_amba_port *uap = (struct uart_amba_port *)port;
267 unsigned int status = readb(uap->port.membase + UART01x_FR);
268 return status & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT;
269}
270
271static unsigned int pl010_get_mctrl(struct uart_port *port)
272{
273 struct uart_amba_port *uap = (struct uart_amba_port *)port;
274 unsigned int result = 0;
275 unsigned int status;
276
277 status = readb(uap->port.membase + UART01x_FR);
278 if (status & UART01x_FR_DCD)
279 result |= TIOCM_CAR;
280 if (status & UART01x_FR_DSR)
281 result |= TIOCM_DSR;
282 if (status & UART01x_FR_CTS)
283 result |= TIOCM_CTS;
284
285 return result;
286}
287
288static void pl010_set_mctrl(struct uart_port *port, unsigned int mctrl)
289{
290 struct uart_amba_port *uap = (struct uart_amba_port *)port;
291
292 if (uap->data)
293 uap->data->set_mctrl(uap->dev, uap->port.membase, mctrl);
294}
295
296static void pl010_break_ctl(struct uart_port *port, int break_state)
297{
298 struct uart_amba_port *uap = (struct uart_amba_port *)port;
299 unsigned long flags;
300 unsigned int lcr_h;
301
302 spin_lock_irqsave(&uap->port.lock, flags);
303 lcr_h = readb(uap->port.membase + UART010_LCRH);
304 if (break_state == -1)
305 lcr_h |= UART01x_LCRH_BRK;
306 else
307 lcr_h &= ~UART01x_LCRH_BRK;
308 writel(lcr_h, uap->port.membase + UART010_LCRH);
309 spin_unlock_irqrestore(&uap->port.lock, flags);
310}
311
312static int pl010_startup(struct uart_port *port)
313{
314 struct uart_amba_port *uap = (struct uart_amba_port *)port;
315 int retval;
316
317 /*
318 * Try to enable the clock producer.
319 */
320 retval = clk_enable(uap->clk);
321 if (retval)
322 goto out;
323
324 uap->port.uartclk = clk_get_rate(uap->clk);
325
326 /*
327 * Allocate the IRQ
328 */
329 retval = request_irq(uap->port.irq, pl010_int, 0, "uart-pl010", uap);
330 if (retval)
331 goto clk_dis;
332
333 /*
334 * initialise the old status of the modem signals
335 */
336 uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
337
338 /*
339 * Finally, enable interrupts
340 */
341 writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE,
342 uap->port.membase + UART010_CR);
343
344 return 0;
345
346 clk_dis:
347 clk_disable(uap->clk);
348 out:
349 return retval;
350}
351
352static void pl010_shutdown(struct uart_port *port)
353{
354 struct uart_amba_port *uap = (struct uart_amba_port *)port;
355
356 /*
357 * Free the interrupt
358 */
359 free_irq(uap->port.irq, uap);
360
361 /*
362 * disable all interrupts, disable the port
363 */
364 writel(0, uap->port.membase + UART010_CR);
365
366 /* disable break condition and fifos */
367 writel(readb(uap->port.membase + UART010_LCRH) &
368 ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN),
369 uap->port.membase + UART010_LCRH);
370
371 /*
372 * Shut down the clock producer
373 */
374 clk_disable(uap->clk);
375}
376
377static void
378pl010_set_termios(struct uart_port *port, struct ktermios *termios,
379 struct ktermios *old)
380{
381 struct uart_amba_port *uap = (struct uart_amba_port *)port;
382 unsigned int lcr_h, old_cr;
383 unsigned long flags;
384 unsigned int baud, quot;
385
386 /*
387 * Ask the core to calculate the divisor for us.
388 */
389 baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16);
390 quot = uart_get_divisor(port, baud);
391
392 switch (termios->c_cflag & CSIZE) {
393 case CS5:
394 lcr_h = UART01x_LCRH_WLEN_5;
395 break;
396 case CS6:
397 lcr_h = UART01x_LCRH_WLEN_6;
398 break;
399 case CS7:
400 lcr_h = UART01x_LCRH_WLEN_7;
401 break;
402 default: // CS8
403 lcr_h = UART01x_LCRH_WLEN_8;
404 break;
405 }
406 if (termios->c_cflag & CSTOPB)
407 lcr_h |= UART01x_LCRH_STP2;
408 if (termios->c_cflag & PARENB) {
409 lcr_h |= UART01x_LCRH_PEN;
410 if (!(termios->c_cflag & PARODD))
411 lcr_h |= UART01x_LCRH_EPS;
412 }
413 if (uap->port.fifosize > 1)
414 lcr_h |= UART01x_LCRH_FEN;
415
416 spin_lock_irqsave(&uap->port.lock, flags);
417
418 /*
419 * Update the per-port timeout.
420 */
421 uart_update_timeout(port, termios->c_cflag, baud);
422
423 uap->port.read_status_mask = UART01x_RSR_OE;
424 if (termios->c_iflag & INPCK)
425 uap->port.read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
426 if (termios->c_iflag & (BRKINT | PARMRK))
427 uap->port.read_status_mask |= UART01x_RSR_BE;
428
429 /*
430 * Characters to ignore
431 */
432 uap->port.ignore_status_mask = 0;
433 if (termios->c_iflag & IGNPAR)
434 uap->port.ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
435 if (termios->c_iflag & IGNBRK) {
436 uap->port.ignore_status_mask |= UART01x_RSR_BE;
437 /*
438 * If we're ignoring parity and break indicators,
439 * ignore overruns too (for real raw support).
440 */
441 if (termios->c_iflag & IGNPAR)
442 uap->port.ignore_status_mask |= UART01x_RSR_OE;
443 }
444
445 /*
446 * Ignore all characters if CREAD is not set.
447 */
448 if ((termios->c_cflag & CREAD) == 0)
449 uap->port.ignore_status_mask |= UART_DUMMY_RSR_RX;
450
451 /* first, disable everything */
452 old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE;
453
454 if (UART_ENABLE_MS(port, termios->c_cflag))
455 old_cr |= UART010_CR_MSIE;
456
457 writel(0, uap->port.membase + UART010_CR);
458
459 /* Set baud rate */
460 quot -= 1;
461 writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM);
462 writel(quot & 0xff, uap->port.membase + UART010_LCRL);
463
464 /*
465 * ----------v----------v----------v----------v-----
466 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
467 * ----------^----------^----------^----------^-----
468 */
469 writel(lcr_h, uap->port.membase + UART010_LCRH);
470 writel(old_cr, uap->port.membase + UART010_CR);
471
472 spin_unlock_irqrestore(&uap->port.lock, flags);
473}
474
475static void pl010_set_ldisc(struct uart_port *port, int new)
476{
477 if (new == N_PPS) {
478 port->flags |= UPF_HARDPPS_CD;
479 pl010_enable_ms(port);
480 } else
481 port->flags &= ~UPF_HARDPPS_CD;
482}
483
484static const char *pl010_type(struct uart_port *port)
485{
486 return port->type == PORT_AMBA ? "AMBA" : NULL;
487}
488
489/*
490 * Release the memory region(s) being used by 'port'
491 */
492static void pl010_release_port(struct uart_port *port)
493{
494 release_mem_region(port->mapbase, UART_PORT_SIZE);
495}
496
497/*
498 * Request the memory region(s) being used by 'port'
499 */
500static int pl010_request_port(struct uart_port *port)
501{
502 return request_mem_region(port->mapbase, UART_PORT_SIZE, "uart-pl010")
503 != NULL ? 0 : -EBUSY;
504}
505
506/*
507 * Configure/autoconfigure the port.
508 */
509static void pl010_config_port(struct uart_port *port, int flags)
510{
511 if (flags & UART_CONFIG_TYPE) {
512 port->type = PORT_AMBA;
513 pl010_request_port(port);
514 }
515}
516
517/*
518 * verify the new serial_struct (for TIOCSSERIAL).
519 */
520static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser)
521{
522 int ret = 0;
523 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
524 ret = -EINVAL;
525 if (ser->irq < 0 || ser->irq >= nr_irqs)
526 ret = -EINVAL;
527 if (ser->baud_base < 9600)
528 ret = -EINVAL;
529 return ret;
530}
531
532static struct uart_ops amba_pl010_pops = {
533 .tx_empty = pl010_tx_empty,
534 .set_mctrl = pl010_set_mctrl,
535 .get_mctrl = pl010_get_mctrl,
536 .stop_tx = pl010_stop_tx,
537 .start_tx = pl010_start_tx,
538 .stop_rx = pl010_stop_rx,
539 .enable_ms = pl010_enable_ms,
540 .break_ctl = pl010_break_ctl,
541 .startup = pl010_startup,
542 .shutdown = pl010_shutdown,
543 .set_termios = pl010_set_termios,
544 .set_ldisc = pl010_set_ldisc,
545 .type = pl010_type,
546 .release_port = pl010_release_port,
547 .request_port = pl010_request_port,
548 .config_port = pl010_config_port,
549 .verify_port = pl010_verify_port,
550};
551
552static struct uart_amba_port *amba_ports[UART_NR];
553
554#ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE
555
556static void pl010_console_putchar(struct uart_port *port, int ch)
557{
558 struct uart_amba_port *uap = (struct uart_amba_port *)port;
559 unsigned int status;
560
561 do {
562 status = readb(uap->port.membase + UART01x_FR);
563 barrier();
564 } while (!UART_TX_READY(status));
565 writel(ch, uap->port.membase + UART01x_DR);
566}
567
568static void
569pl010_console_write(struct console *co, const char *s, unsigned int count)
570{
571 struct uart_amba_port *uap = amba_ports[co->index];
572 unsigned int status, old_cr;
573
574 clk_enable(uap->clk);
575
576 /*
577 * First save the CR then disable the interrupts
578 */
579 old_cr = readb(uap->port.membase + UART010_CR);
580 writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR);
581
582 uart_console_write(&uap->port, s, count, pl010_console_putchar);
583
584 /*
585 * Finally, wait for transmitter to become empty
586 * and restore the TCR
587 */
588 do {
589 status = readb(uap->port.membase + UART01x_FR);
590 barrier();
591 } while (status & UART01x_FR_BUSY);
592 writel(old_cr, uap->port.membase + UART010_CR);
593
594 clk_disable(uap->clk);
595}
596
597static void __init
598pl010_console_get_options(struct uart_amba_port *uap, int *baud,
599 int *parity, int *bits)
600{
601 if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {
602 unsigned int lcr_h, quot;
603 lcr_h = readb(uap->port.membase + UART010_LCRH);
604
605 *parity = 'n';
606 if (lcr_h & UART01x_LCRH_PEN) {
607 if (lcr_h & UART01x_LCRH_EPS)
608 *parity = 'e';
609 else
610 *parity = 'o';
611 }
612
613 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
614 *bits = 7;
615 else
616 *bits = 8;
617
618 quot = readb(uap->port.membase + UART010_LCRL) |
619 readb(uap->port.membase + UART010_LCRM) << 8;
620 *baud = uap->port.uartclk / (16 * (quot + 1));
621 }
622}
623
624static int __init pl010_console_setup(struct console *co, char *options)
625{
626 struct uart_amba_port *uap;
627 int baud = 38400;
628 int bits = 8;
629 int parity = 'n';
630 int flow = 'n';
631
632 /*
633 * Check whether an invalid uart number has been specified, and
634 * if so, search for the first available port that does have
635 * console support.
636 */
637 if (co->index >= UART_NR)
638 co->index = 0;
639 uap = amba_ports[co->index];
640 if (!uap)
641 return -ENODEV;
642
643 uap->port.uartclk = clk_get_rate(uap->clk);
644
645 if (options)
646 uart_parse_options(options, &baud, &parity, &bits, &flow);
647 else
648 pl010_console_get_options(uap, &baud, &parity, &bits);
649
650 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
651}
652
653static struct uart_driver amba_reg;
654static struct console amba_console = {
655 .name = "ttyAM",
656 .write = pl010_console_write,
657 .device = uart_console_device,
658 .setup = pl010_console_setup,
659 .flags = CON_PRINTBUFFER,
660 .index = -1,
661 .data = &amba_reg,
662};
663
664#define AMBA_CONSOLE &amba_console
665#else
666#define AMBA_CONSOLE NULL
667#endif
668
669static struct uart_driver amba_reg = {
670 .owner = THIS_MODULE,
671 .driver_name = "ttyAM",
672 .dev_name = "ttyAM",
673 .major = SERIAL_AMBA_MAJOR,
674 .minor = SERIAL_AMBA_MINOR,
675 .nr = UART_NR,
676 .cons = AMBA_CONSOLE,
677};
678
679static int pl010_probe(struct amba_device *dev, struct amba_id *id)
680{
681 struct uart_amba_port *uap;
682 void __iomem *base;
683 int i, ret;
684
685 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
686 if (amba_ports[i] == NULL)
687 break;
688
689 if (i == ARRAY_SIZE(amba_ports)) {
690 ret = -EBUSY;
691 goto out;
692 }
693
694 uap = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL);
695 if (!uap) {
696 ret = -ENOMEM;
697 goto out;
698 }
699
700 base = ioremap(dev->res.start, resource_size(&dev->res));
701 if (!base) {
702 ret = -ENOMEM;
703 goto free;
704 }
705
706 uap->clk = clk_get(&dev->dev, NULL);
707 if (IS_ERR(uap->clk)) {
708 ret = PTR_ERR(uap->clk);
709 goto unmap;
710 }
711
712 uap->port.dev = &dev->dev;
713 uap->port.mapbase = dev->res.start;
714 uap->port.membase = base;
715 uap->port.iotype = UPIO_MEM;
716 uap->port.irq = dev->irq[0];
717 uap->port.fifosize = 16;
718 uap->port.ops = &amba_pl010_pops;
719 uap->port.flags = UPF_BOOT_AUTOCONF;
720 uap->port.line = i;
721 uap->dev = dev;
722 uap->data = dev->dev.platform_data;
723
724 amba_ports[i] = uap;
725
726 amba_set_drvdata(dev, uap);
727 ret = uart_add_one_port(&amba_reg, &uap->port);
728 if (ret) {
729 amba_set_drvdata(dev, NULL);
730 amba_ports[i] = NULL;
731 clk_put(uap->clk);
732 unmap:
733 iounmap(base);
734 free:
735 kfree(uap);
736 }
737 out:
738 return ret;
739}
740
741static int pl010_remove(struct amba_device *dev)
742{
743 struct uart_amba_port *uap = amba_get_drvdata(dev);
744 int i;
745
746 amba_set_drvdata(dev, NULL);
747
748 uart_remove_one_port(&amba_reg, &uap->port);
749
750 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
751 if (amba_ports[i] == uap)
752 amba_ports[i] = NULL;
753
754 iounmap(uap->port.membase);
755 clk_put(uap->clk);
756 kfree(uap);
757 return 0;
758}
759
760static int pl010_suspend(struct amba_device *dev, pm_message_t state)
761{
762 struct uart_amba_port *uap = amba_get_drvdata(dev);
763
764 if (uap)
765 uart_suspend_port(&amba_reg, &uap->port);
766
767 return 0;
768}
769
770static int pl010_resume(struct amba_device *dev)
771{
772 struct uart_amba_port *uap = amba_get_drvdata(dev);
773
774 if (uap)
775 uart_resume_port(&amba_reg, &uap->port);
776
777 return 0;
778}
779
780static struct amba_id pl010_ids[] = {
781 {
782 .id = 0x00041010,
783 .mask = 0x000fffff,
784 },
785 { 0, 0 },
786};
787
788static struct amba_driver pl010_driver = {
789 .drv = {
790 .name = "uart-pl010",
791 },
792 .id_table = pl010_ids,
793 .probe = pl010_probe,
794 .remove = pl010_remove,
795 .suspend = pl010_suspend,
796 .resume = pl010_resume,
797};
798
799static int __init pl010_init(void)
800{
801 int ret;
802
803 printk(KERN_INFO "Serial: AMBA driver\n");
804
805 ret = uart_register_driver(&amba_reg);
806 if (ret == 0) {
807 ret = amba_driver_register(&pl010_driver);
808 if (ret)
809 uart_unregister_driver(&amba_reg);
810 }
811 return ret;
812}
813
814static void __exit pl010_exit(void)
815{
816 amba_driver_unregister(&pl010_driver);
817 uart_unregister_driver(&amba_reg);
818}
819
820module_init(pl010_init);
821module_exit(pl010_exit);
822
823MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
824MODULE_DESCRIPTION("ARM AMBA serial port driver");
825MODULE_LICENSE("GPL");
diff --git a/drivers/serial/amba-pl011.c b/drivers/serial/amba-pl011.c
deleted file mode 100644
index 6ca7a44f29c2..000000000000
--- a/drivers/serial/amba-pl011.c
+++ /dev/null
@@ -1,989 +0,0 @@
1/*
2 * linux/drivers/char/amba.c
3 *
4 * Driver for AMBA serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright 1999 ARM Limited
9 * Copyright (C) 2000 Deep Blue Solutions Ltd.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 * This is a generic driver for ARM AMBA-type serial ports. They
26 * have a lot of 16550-like features, but are not register compatible.
27 * Note that although they do have CTS, DCD and DSR inputs, they do
28 * not have an RI input, nor do they have DTR or RTS outputs. If
29 * required, these have to be supplied via some other means (eg, GPIO)
30 * and hooked into this driver.
31 */
32
33#if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
34#define SUPPORT_SYSRQ
35#endif
36
37#include <linux/module.h>
38#include <linux/ioport.h>
39#include <linux/init.h>
40#include <linux/console.h>
41#include <linux/sysrq.h>
42#include <linux/device.h>
43#include <linux/tty.h>
44#include <linux/tty_flip.h>
45#include <linux/serial_core.h>
46#include <linux/serial.h>
47#include <linux/amba/bus.h>
48#include <linux/amba/serial.h>
49#include <linux/clk.h>
50#include <linux/slab.h>
51
52#include <asm/io.h>
53#include <asm/sizes.h>
54
55#define UART_NR 14
56
57#define SERIAL_AMBA_MAJOR 204
58#define SERIAL_AMBA_MINOR 64
59#define SERIAL_AMBA_NR UART_NR
60
61#define AMBA_ISR_PASS_LIMIT 256
62
63#define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
64#define UART_DUMMY_DR_RX (1 << 16)
65
66/*
67 * We wrap our port structure around the generic uart_port.
68 */
69struct uart_amba_port {
70 struct uart_port port;
71 struct clk *clk;
72 unsigned int im; /* interrupt mask */
73 unsigned int old_status;
74 unsigned int ifls; /* vendor-specific */
75 unsigned int lcrh_tx; /* vendor-specific */
76 unsigned int lcrh_rx; /* vendor-specific */
77 bool oversampling; /* vendor-specific */
78 bool autorts;
79};
80
81/* There is by now at least one vendor with differing details, so handle it */
82struct vendor_data {
83 unsigned int ifls;
84 unsigned int fifosize;
85 unsigned int lcrh_tx;
86 unsigned int lcrh_rx;
87 bool oversampling;
88};
89
90static struct vendor_data vendor_arm = {
91 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
92 .fifosize = 16,
93 .lcrh_tx = UART011_LCRH,
94 .lcrh_rx = UART011_LCRH,
95 .oversampling = false,
96};
97
98static struct vendor_data vendor_st = {
99 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
100 .fifosize = 64,
101 .lcrh_tx = ST_UART011_LCRH_TX,
102 .lcrh_rx = ST_UART011_LCRH_RX,
103 .oversampling = true,
104};
105
106static void pl011_stop_tx(struct uart_port *port)
107{
108 struct uart_amba_port *uap = (struct uart_amba_port *)port;
109
110 uap->im &= ~UART011_TXIM;
111 writew(uap->im, uap->port.membase + UART011_IMSC);
112}
113
114static void pl011_start_tx(struct uart_port *port)
115{
116 struct uart_amba_port *uap = (struct uart_amba_port *)port;
117
118 uap->im |= UART011_TXIM;
119 writew(uap->im, uap->port.membase + UART011_IMSC);
120}
121
122static void pl011_stop_rx(struct uart_port *port)
123{
124 struct uart_amba_port *uap = (struct uart_amba_port *)port;
125
126 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
127 UART011_PEIM|UART011_BEIM|UART011_OEIM);
128 writew(uap->im, uap->port.membase + UART011_IMSC);
129}
130
131static void pl011_enable_ms(struct uart_port *port)
132{
133 struct uart_amba_port *uap = (struct uart_amba_port *)port;
134
135 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
136 writew(uap->im, uap->port.membase + UART011_IMSC);
137}
138
139static void pl011_rx_chars(struct uart_amba_port *uap)
140{
141 struct tty_struct *tty = uap->port.state->port.tty;
142 unsigned int status, ch, flag, max_count = 256;
143
144 status = readw(uap->port.membase + UART01x_FR);
145 while ((status & UART01x_FR_RXFE) == 0 && max_count--) {
146 ch = readw(uap->port.membase + UART01x_DR) | UART_DUMMY_DR_RX;
147 flag = TTY_NORMAL;
148 uap->port.icount.rx++;
149
150 /*
151 * Note that the error handling code is
152 * out of the main execution path
153 */
154 if (unlikely(ch & UART_DR_ERROR)) {
155 if (ch & UART011_DR_BE) {
156 ch &= ~(UART011_DR_FE | UART011_DR_PE);
157 uap->port.icount.brk++;
158 if (uart_handle_break(&uap->port))
159 goto ignore_char;
160 } else if (ch & UART011_DR_PE)
161 uap->port.icount.parity++;
162 else if (ch & UART011_DR_FE)
163 uap->port.icount.frame++;
164 if (ch & UART011_DR_OE)
165 uap->port.icount.overrun++;
166
167 ch &= uap->port.read_status_mask;
168
169 if (ch & UART011_DR_BE)
170 flag = TTY_BREAK;
171 else if (ch & UART011_DR_PE)
172 flag = TTY_PARITY;
173 else if (ch & UART011_DR_FE)
174 flag = TTY_FRAME;
175 }
176
177 if (uart_handle_sysrq_char(&uap->port, ch & 255))
178 goto ignore_char;
179
180 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
181
182 ignore_char:
183 status = readw(uap->port.membase + UART01x_FR);
184 }
185 spin_unlock(&uap->port.lock);
186 tty_flip_buffer_push(tty);
187 spin_lock(&uap->port.lock);
188}
189
190static void pl011_tx_chars(struct uart_amba_port *uap)
191{
192 struct circ_buf *xmit = &uap->port.state->xmit;
193 int count;
194
195 if (uap->port.x_char) {
196 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
197 uap->port.icount.tx++;
198 uap->port.x_char = 0;
199 return;
200 }
201 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
202 pl011_stop_tx(&uap->port);
203 return;
204 }
205
206 count = uap->port.fifosize >> 1;
207 do {
208 writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
209 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
210 uap->port.icount.tx++;
211 if (uart_circ_empty(xmit))
212 break;
213 } while (--count > 0);
214
215 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
216 uart_write_wakeup(&uap->port);
217
218 if (uart_circ_empty(xmit))
219 pl011_stop_tx(&uap->port);
220}
221
222static void pl011_modem_status(struct uart_amba_port *uap)
223{
224 unsigned int status, delta;
225
226 status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
227
228 delta = status ^ uap->old_status;
229 uap->old_status = status;
230
231 if (!delta)
232 return;
233
234 if (delta & UART01x_FR_DCD)
235 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
236
237 if (delta & UART01x_FR_DSR)
238 uap->port.icount.dsr++;
239
240 if (delta & UART01x_FR_CTS)
241 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
242
243 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
244}
245
246static irqreturn_t pl011_int(int irq, void *dev_id)
247{
248 struct uart_amba_port *uap = dev_id;
249 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
250 int handled = 0;
251
252 spin_lock(&uap->port.lock);
253
254 status = readw(uap->port.membase + UART011_MIS);
255 if (status) {
256 do {
257 writew(status & ~(UART011_TXIS|UART011_RTIS|
258 UART011_RXIS),
259 uap->port.membase + UART011_ICR);
260
261 if (status & (UART011_RTIS|UART011_RXIS))
262 pl011_rx_chars(uap);
263 if (status & (UART011_DSRMIS|UART011_DCDMIS|
264 UART011_CTSMIS|UART011_RIMIS))
265 pl011_modem_status(uap);
266 if (status & UART011_TXIS)
267 pl011_tx_chars(uap);
268
269 if (pass_counter-- == 0)
270 break;
271
272 status = readw(uap->port.membase + UART011_MIS);
273 } while (status != 0);
274 handled = 1;
275 }
276
277 spin_unlock(&uap->port.lock);
278
279 return IRQ_RETVAL(handled);
280}
281
282static unsigned int pl01x_tx_empty(struct uart_port *port)
283{
284 struct uart_amba_port *uap = (struct uart_amba_port *)port;
285 unsigned int status = readw(uap->port.membase + UART01x_FR);
286 return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
287}
288
289static unsigned int pl01x_get_mctrl(struct uart_port *port)
290{
291 struct uart_amba_port *uap = (struct uart_amba_port *)port;
292 unsigned int result = 0;
293 unsigned int status = readw(uap->port.membase + UART01x_FR);
294
295#define TIOCMBIT(uartbit, tiocmbit) \
296 if (status & uartbit) \
297 result |= tiocmbit
298
299 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
300 TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR);
301 TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS);
302 TIOCMBIT(UART011_FR_RI, TIOCM_RNG);
303#undef TIOCMBIT
304 return result;
305}
306
307static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
308{
309 struct uart_amba_port *uap = (struct uart_amba_port *)port;
310 unsigned int cr;
311
312 cr = readw(uap->port.membase + UART011_CR);
313
314#define TIOCMBIT(tiocmbit, uartbit) \
315 if (mctrl & tiocmbit) \
316 cr |= uartbit; \
317 else \
318 cr &= ~uartbit
319
320 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
321 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
322 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
323 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
324 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
325
326 if (uap->autorts) {
327 /* We need to disable auto-RTS if we want to turn RTS off */
328 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
329 }
330#undef TIOCMBIT
331
332 writew(cr, uap->port.membase + UART011_CR);
333}
334
335static void pl011_break_ctl(struct uart_port *port, int break_state)
336{
337 struct uart_amba_port *uap = (struct uart_amba_port *)port;
338 unsigned long flags;
339 unsigned int lcr_h;
340
341 spin_lock_irqsave(&uap->port.lock, flags);
342 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
343 if (break_state == -1)
344 lcr_h |= UART01x_LCRH_BRK;
345 else
346 lcr_h &= ~UART01x_LCRH_BRK;
347 writew(lcr_h, uap->port.membase + uap->lcrh_tx);
348 spin_unlock_irqrestore(&uap->port.lock, flags);
349}
350
351#ifdef CONFIG_CONSOLE_POLL
352static int pl010_get_poll_char(struct uart_port *port)
353{
354 struct uart_amba_port *uap = (struct uart_amba_port *)port;
355 unsigned int status;
356
357 status = readw(uap->port.membase + UART01x_FR);
358 if (status & UART01x_FR_RXFE)
359 return NO_POLL_CHAR;
360
361 return readw(uap->port.membase + UART01x_DR);
362}
363
364static void pl010_put_poll_char(struct uart_port *port,
365 unsigned char ch)
366{
367 struct uart_amba_port *uap = (struct uart_amba_port *)port;
368
369 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
370 barrier();
371
372 writew(ch, uap->port.membase + UART01x_DR);
373}
374
375#endif /* CONFIG_CONSOLE_POLL */
376
377static int pl011_startup(struct uart_port *port)
378{
379 struct uart_amba_port *uap = (struct uart_amba_port *)port;
380 unsigned int cr;
381 int retval;
382
383 /*
384 * Try to enable the clock producer.
385 */
386 retval = clk_enable(uap->clk);
387 if (retval)
388 goto out;
389
390 uap->port.uartclk = clk_get_rate(uap->clk);
391
392 /*
393 * Allocate the IRQ
394 */
395 retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
396 if (retval)
397 goto clk_dis;
398
399 writew(uap->ifls, uap->port.membase + UART011_IFLS);
400
401 /*
402 * Provoke TX FIFO interrupt into asserting.
403 */
404 cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE;
405 writew(cr, uap->port.membase + UART011_CR);
406 writew(0, uap->port.membase + UART011_FBRD);
407 writew(1, uap->port.membase + UART011_IBRD);
408 writew(0, uap->port.membase + uap->lcrh_rx);
409 if (uap->lcrh_tx != uap->lcrh_rx) {
410 int i;
411 /*
412 * Wait 10 PCLKs before writing LCRH_TX register,
413 * to get this delay write read only register 10 times
414 */
415 for (i = 0; i < 10; ++i)
416 writew(0xff, uap->port.membase + UART011_MIS);
417 writew(0, uap->port.membase + uap->lcrh_tx);
418 }
419 writew(0, uap->port.membase + UART01x_DR);
420 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
421 barrier();
422
423 cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
424 writew(cr, uap->port.membase + UART011_CR);
425
426 /*
427 * initialise the old status of the modem signals
428 */
429 uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
430
431 /*
432 * Finally, enable interrupts
433 */
434 spin_lock_irq(&uap->port.lock);
435 uap->im = UART011_RXIM | UART011_RTIM;
436 writew(uap->im, uap->port.membase + UART011_IMSC);
437 spin_unlock_irq(&uap->port.lock);
438
439 return 0;
440
441 clk_dis:
442 clk_disable(uap->clk);
443 out:
444 return retval;
445}
446
447static void pl011_shutdown_channel(struct uart_amba_port *uap,
448 unsigned int lcrh)
449{
450 unsigned long val;
451
452 val = readw(uap->port.membase + lcrh);
453 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
454 writew(val, uap->port.membase + lcrh);
455}
456
457static void pl011_shutdown(struct uart_port *port)
458{
459 struct uart_amba_port *uap = (struct uart_amba_port *)port;
460
461 /*
462 * disable all interrupts
463 */
464 spin_lock_irq(&uap->port.lock);
465 uap->im = 0;
466 writew(uap->im, uap->port.membase + UART011_IMSC);
467 writew(0xffff, uap->port.membase + UART011_ICR);
468 spin_unlock_irq(&uap->port.lock);
469
470 /*
471 * Free the interrupt
472 */
473 free_irq(uap->port.irq, uap);
474
475 /*
476 * disable the port
477 */
478 uap->autorts = false;
479 writew(UART01x_CR_UARTEN | UART011_CR_TXE, uap->port.membase + UART011_CR);
480
481 /*
482 * disable break condition and fifos
483 */
484 pl011_shutdown_channel(uap, uap->lcrh_rx);
485 if (uap->lcrh_rx != uap->lcrh_tx)
486 pl011_shutdown_channel(uap, uap->lcrh_tx);
487
488 /*
489 * Shut down the clock producer
490 */
491 clk_disable(uap->clk);
492}
493
494static void
495pl011_set_termios(struct uart_port *port, struct ktermios *termios,
496 struct ktermios *old)
497{
498 struct uart_amba_port *uap = (struct uart_amba_port *)port;
499 unsigned int lcr_h, old_cr;
500 unsigned long flags;
501 unsigned int baud, quot;
502
503 /*
504 * Ask the core to calculate the divisor for us.
505 */
506 baud = uart_get_baud_rate(port, termios, old, 0,
507 port->uartclk/(uap->oversampling ? 8 : 16));
508
509 if (baud > port->uartclk/16)
510 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
511 else
512 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
513
514 switch (termios->c_cflag & CSIZE) {
515 case CS5:
516 lcr_h = UART01x_LCRH_WLEN_5;
517 break;
518 case CS6:
519 lcr_h = UART01x_LCRH_WLEN_6;
520 break;
521 case CS7:
522 lcr_h = UART01x_LCRH_WLEN_7;
523 break;
524 default: // CS8
525 lcr_h = UART01x_LCRH_WLEN_8;
526 break;
527 }
528 if (termios->c_cflag & CSTOPB)
529 lcr_h |= UART01x_LCRH_STP2;
530 if (termios->c_cflag & PARENB) {
531 lcr_h |= UART01x_LCRH_PEN;
532 if (!(termios->c_cflag & PARODD))
533 lcr_h |= UART01x_LCRH_EPS;
534 }
535 if (port->fifosize > 1)
536 lcr_h |= UART01x_LCRH_FEN;
537
538 spin_lock_irqsave(&port->lock, flags);
539
540 /*
541 * Update the per-port timeout.
542 */
543 uart_update_timeout(port, termios->c_cflag, baud);
544
545 port->read_status_mask = UART011_DR_OE | 255;
546 if (termios->c_iflag & INPCK)
547 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
548 if (termios->c_iflag & (BRKINT | PARMRK))
549 port->read_status_mask |= UART011_DR_BE;
550
551 /*
552 * Characters to ignore
553 */
554 port->ignore_status_mask = 0;
555 if (termios->c_iflag & IGNPAR)
556 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
557 if (termios->c_iflag & IGNBRK) {
558 port->ignore_status_mask |= UART011_DR_BE;
559 /*
560 * If we're ignoring parity and break indicators,
561 * ignore overruns too (for real raw support).
562 */
563 if (termios->c_iflag & IGNPAR)
564 port->ignore_status_mask |= UART011_DR_OE;
565 }
566
567 /*
568 * Ignore all characters if CREAD is not set.
569 */
570 if ((termios->c_cflag & CREAD) == 0)
571 port->ignore_status_mask |= UART_DUMMY_DR_RX;
572
573 if (UART_ENABLE_MS(port, termios->c_cflag))
574 pl011_enable_ms(port);
575
576 /* first, disable everything */
577 old_cr = readw(port->membase + UART011_CR);
578 writew(0, port->membase + UART011_CR);
579
580 if (termios->c_cflag & CRTSCTS) {
581 if (old_cr & UART011_CR_RTS)
582 old_cr |= UART011_CR_RTSEN;
583
584 old_cr |= UART011_CR_CTSEN;
585 uap->autorts = true;
586 } else {
587 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
588 uap->autorts = false;
589 }
590
591 if (uap->oversampling) {
592 if (baud > port->uartclk/16)
593 old_cr |= ST_UART011_CR_OVSFACT;
594 else
595 old_cr &= ~ST_UART011_CR_OVSFACT;
596 }
597
598 /* Set baud rate */
599 writew(quot & 0x3f, port->membase + UART011_FBRD);
600 writew(quot >> 6, port->membase + UART011_IBRD);
601
602 /*
603 * ----------v----------v----------v----------v-----
604 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
605 * ----------^----------^----------^----------^-----
606 */
607 writew(lcr_h, port->membase + uap->lcrh_rx);
608 if (uap->lcrh_rx != uap->lcrh_tx) {
609 int i;
610 /*
611 * Wait 10 PCLKs before writing LCRH_TX register,
612 * to get this delay write read only register 10 times
613 */
614 for (i = 0; i < 10; ++i)
615 writew(0xff, uap->port.membase + UART011_MIS);
616 writew(lcr_h, port->membase + uap->lcrh_tx);
617 }
618 writew(old_cr, port->membase + UART011_CR);
619
620 spin_unlock_irqrestore(&port->lock, flags);
621}
622
623static const char *pl011_type(struct uart_port *port)
624{
625 return port->type == PORT_AMBA ? "AMBA/PL011" : NULL;
626}
627
628/*
629 * Release the memory region(s) being used by 'port'
630 */
631static void pl010_release_port(struct uart_port *port)
632{
633 release_mem_region(port->mapbase, SZ_4K);
634}
635
636/*
637 * Request the memory region(s) being used by 'port'
638 */
639static int pl010_request_port(struct uart_port *port)
640{
641 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
642 != NULL ? 0 : -EBUSY;
643}
644
645/*
646 * Configure/autoconfigure the port.
647 */
648static void pl010_config_port(struct uart_port *port, int flags)
649{
650 if (flags & UART_CONFIG_TYPE) {
651 port->type = PORT_AMBA;
652 pl010_request_port(port);
653 }
654}
655
656/*
657 * verify the new serial_struct (for TIOCSSERIAL).
658 */
659static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser)
660{
661 int ret = 0;
662 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
663 ret = -EINVAL;
664 if (ser->irq < 0 || ser->irq >= nr_irqs)
665 ret = -EINVAL;
666 if (ser->baud_base < 9600)
667 ret = -EINVAL;
668 return ret;
669}
670
671static struct uart_ops amba_pl011_pops = {
672 .tx_empty = pl01x_tx_empty,
673 .set_mctrl = pl011_set_mctrl,
674 .get_mctrl = pl01x_get_mctrl,
675 .stop_tx = pl011_stop_tx,
676 .start_tx = pl011_start_tx,
677 .stop_rx = pl011_stop_rx,
678 .enable_ms = pl011_enable_ms,
679 .break_ctl = pl011_break_ctl,
680 .startup = pl011_startup,
681 .shutdown = pl011_shutdown,
682 .set_termios = pl011_set_termios,
683 .type = pl011_type,
684 .release_port = pl010_release_port,
685 .request_port = pl010_request_port,
686 .config_port = pl010_config_port,
687 .verify_port = pl010_verify_port,
688#ifdef CONFIG_CONSOLE_POLL
689 .poll_get_char = pl010_get_poll_char,
690 .poll_put_char = pl010_put_poll_char,
691#endif
692};
693
694static struct uart_amba_port *amba_ports[UART_NR];
695
696#ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
697
698static void pl011_console_putchar(struct uart_port *port, int ch)
699{
700 struct uart_amba_port *uap = (struct uart_amba_port *)port;
701
702 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
703 barrier();
704 writew(ch, uap->port.membase + UART01x_DR);
705}
706
707static void
708pl011_console_write(struct console *co, const char *s, unsigned int count)
709{
710 struct uart_amba_port *uap = amba_ports[co->index];
711 unsigned int status, old_cr, new_cr;
712
713 clk_enable(uap->clk);
714
715 /*
716 * First save the CR then disable the interrupts
717 */
718 old_cr = readw(uap->port.membase + UART011_CR);
719 new_cr = old_cr & ~UART011_CR_CTSEN;
720 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
721 writew(new_cr, uap->port.membase + UART011_CR);
722
723 uart_console_write(&uap->port, s, count, pl011_console_putchar);
724
725 /*
726 * Finally, wait for transmitter to become empty
727 * and restore the TCR
728 */
729 do {
730 status = readw(uap->port.membase + UART01x_FR);
731 } while (status & UART01x_FR_BUSY);
732 writew(old_cr, uap->port.membase + UART011_CR);
733
734 clk_disable(uap->clk);
735}
736
737static void __init
738pl011_console_get_options(struct uart_amba_port *uap, int *baud,
739 int *parity, int *bits)
740{
741 if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {
742 unsigned int lcr_h, ibrd, fbrd;
743
744 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
745
746 *parity = 'n';
747 if (lcr_h & UART01x_LCRH_PEN) {
748 if (lcr_h & UART01x_LCRH_EPS)
749 *parity = 'e';
750 else
751 *parity = 'o';
752 }
753
754 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
755 *bits = 7;
756 else
757 *bits = 8;
758
759 ibrd = readw(uap->port.membase + UART011_IBRD);
760 fbrd = readw(uap->port.membase + UART011_FBRD);
761
762 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
763
764 if (uap->oversampling) {
765 if (readw(uap->port.membase + UART011_CR)
766 & ST_UART011_CR_OVSFACT)
767 *baud *= 2;
768 }
769 }
770}
771
772static int __init pl011_console_setup(struct console *co, char *options)
773{
774 struct uart_amba_port *uap;
775 int baud = 38400;
776 int bits = 8;
777 int parity = 'n';
778 int flow = 'n';
779
780 /*
781 * Check whether an invalid uart number has been specified, and
782 * if so, search for the first available port that does have
783 * console support.
784 */
785 if (co->index >= UART_NR)
786 co->index = 0;
787 uap = amba_ports[co->index];
788 if (!uap)
789 return -ENODEV;
790
791 uap->port.uartclk = clk_get_rate(uap->clk);
792
793 if (options)
794 uart_parse_options(options, &baud, &parity, &bits, &flow);
795 else
796 pl011_console_get_options(uap, &baud, &parity, &bits);
797
798 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
799}
800
801static struct uart_driver amba_reg;
802static struct console amba_console = {
803 .name = "ttyAMA",
804 .write = pl011_console_write,
805 .device = uart_console_device,
806 .setup = pl011_console_setup,
807 .flags = CON_PRINTBUFFER,
808 .index = -1,
809 .data = &amba_reg,
810};
811
812#define AMBA_CONSOLE (&amba_console)
813#else
814#define AMBA_CONSOLE NULL
815#endif
816
817static struct uart_driver amba_reg = {
818 .owner = THIS_MODULE,
819 .driver_name = "ttyAMA",
820 .dev_name = "ttyAMA",
821 .major = SERIAL_AMBA_MAJOR,
822 .minor = SERIAL_AMBA_MINOR,
823 .nr = UART_NR,
824 .cons = AMBA_CONSOLE,
825};
826
827static int pl011_probe(struct amba_device *dev, struct amba_id *id)
828{
829 struct uart_amba_port *uap;
830 struct vendor_data *vendor = id->data;
831 void __iomem *base;
832 int i, ret;
833
834 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
835 if (amba_ports[i] == NULL)
836 break;
837
838 if (i == ARRAY_SIZE(amba_ports)) {
839 ret = -EBUSY;
840 goto out;
841 }
842
843 uap = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL);
844 if (uap == NULL) {
845 ret = -ENOMEM;
846 goto out;
847 }
848
849 base = ioremap(dev->res.start, resource_size(&dev->res));
850 if (!base) {
851 ret = -ENOMEM;
852 goto free;
853 }
854
855 uap->clk = clk_get(&dev->dev, NULL);
856 if (IS_ERR(uap->clk)) {
857 ret = PTR_ERR(uap->clk);
858 goto unmap;
859 }
860
861 uap->ifls = vendor->ifls;
862 uap->lcrh_rx = vendor->lcrh_rx;
863 uap->lcrh_tx = vendor->lcrh_tx;
864 uap->oversampling = vendor->oversampling;
865 uap->port.dev = &dev->dev;
866 uap->port.mapbase = dev->res.start;
867 uap->port.membase = base;
868 uap->port.iotype = UPIO_MEM;
869 uap->port.irq = dev->irq[0];
870 uap->port.fifosize = vendor->fifosize;
871 uap->port.ops = &amba_pl011_pops;
872 uap->port.flags = UPF_BOOT_AUTOCONF;
873 uap->port.line = i;
874
875 amba_ports[i] = uap;
876
877 amba_set_drvdata(dev, uap);
878 ret = uart_add_one_port(&amba_reg, &uap->port);
879 if (ret) {
880 amba_set_drvdata(dev, NULL);
881 amba_ports[i] = NULL;
882 clk_put(uap->clk);
883 unmap:
884 iounmap(base);
885 free:
886 kfree(uap);
887 }
888 out:
889 return ret;
890}
891
892static int pl011_remove(struct amba_device *dev)
893{
894 struct uart_amba_port *uap = amba_get_drvdata(dev);
895 int i;
896
897 amba_set_drvdata(dev, NULL);
898
899 uart_remove_one_port(&amba_reg, &uap->port);
900
901 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
902 if (amba_ports[i] == uap)
903 amba_ports[i] = NULL;
904
905 iounmap(uap->port.membase);
906 clk_put(uap->clk);
907 kfree(uap);
908 return 0;
909}
910
911#ifdef CONFIG_PM
912static int pl011_suspend(struct amba_device *dev, pm_message_t state)
913{
914 struct uart_amba_port *uap = amba_get_drvdata(dev);
915
916 if (!uap)
917 return -EINVAL;
918
919 return uart_suspend_port(&amba_reg, &uap->port);
920}
921
922static int pl011_resume(struct amba_device *dev)
923{
924 struct uart_amba_port *uap = amba_get_drvdata(dev);
925
926 if (!uap)
927 return -EINVAL;
928
929 return uart_resume_port(&amba_reg, &uap->port);
930}
931#endif
932
933static struct amba_id pl011_ids[] = {
934 {
935 .id = 0x00041011,
936 .mask = 0x000fffff,
937 .data = &vendor_arm,
938 },
939 {
940 .id = 0x00380802,
941 .mask = 0x00ffffff,
942 .data = &vendor_st,
943 },
944 { 0, 0 },
945};
946
947static struct amba_driver pl011_driver = {
948 .drv = {
949 .name = "uart-pl011",
950 },
951 .id_table = pl011_ids,
952 .probe = pl011_probe,
953 .remove = pl011_remove,
954#ifdef CONFIG_PM
955 .suspend = pl011_suspend,
956 .resume = pl011_resume,
957#endif
958};
959
960static int __init pl011_init(void)
961{
962 int ret;
963 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
964
965 ret = uart_register_driver(&amba_reg);
966 if (ret == 0) {
967 ret = amba_driver_register(&pl011_driver);
968 if (ret)
969 uart_unregister_driver(&amba_reg);
970 }
971 return ret;
972}
973
974static void __exit pl011_exit(void)
975{
976 amba_driver_unregister(&pl011_driver);
977 uart_unregister_driver(&amba_reg);
978}
979
980/*
981 * While this can be a module, if builtin it's most likely the console
982 * So let's leave module_exit but move module_init to an earlier place
983 */
984arch_initcall(pl011_init);
985module_exit(pl011_exit);
986
987MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
988MODULE_DESCRIPTION("ARM AMBA serial port driver");
989MODULE_LICENSE("GPL");
diff --git a/drivers/serial/apbuart.c b/drivers/serial/apbuart.c
deleted file mode 100644
index cc01c650a144..000000000000
--- a/drivers/serial/apbuart.c
+++ /dev/null
@@ -1,710 +0,0 @@
1/*
2 * Driver for GRLIB serial ports (APBUART)
3 *
4 * Based on linux/drivers/serial/amba.c
5 *
6 * Copyright (C) 2000 Deep Blue Solutions Ltd.
7 * Copyright (C) 2003 Konrad Eisele <eiselekd@web.de>
8 * Copyright (C) 2006 Daniel Hellstrom <daniel@gaisler.com>, Aeroflex Gaisler AB
9 * Copyright (C) 2008 Gilead Kutnick <kutnickg@zin-tech.com>
10 * Copyright (C) 2009 Kristoffer Glembo <kristoffer@gaisler.com>, Aeroflex Gaisler AB
11 */
12
13#if defined(CONFIG_SERIAL_GRLIB_GAISLER_APBUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
14#define SUPPORT_SYSRQ
15#endif
16
17#include <linux/module.h>
18#include <linux/tty.h>
19#include <linux/ioport.h>
20#include <linux/init.h>
21#include <linux/serial.h>
22#include <linux/console.h>
23#include <linux/sysrq.h>
24#include <linux/kthread.h>
25#include <linux/device.h>
26#include <linux/of.h>
27#include <linux/of_device.h>
28#include <linux/of_platform.h>
29#include <linux/platform_device.h>
30#include <linux/io.h>
31#include <linux/serial_core.h>
32#include <asm/irq.h>
33
34#include "apbuart.h"
35
36#define SERIAL_APBUART_MAJOR TTY_MAJOR
37#define SERIAL_APBUART_MINOR 64
38#define UART_DUMMY_RSR_RX 0x8000 /* for ignore all read */
39
40static void apbuart_tx_chars(struct uart_port *port);
41
42static void apbuart_stop_tx(struct uart_port *port)
43{
44 unsigned int cr;
45
46 cr = UART_GET_CTRL(port);
47 cr &= ~UART_CTRL_TI;
48 UART_PUT_CTRL(port, cr);
49}
50
51static void apbuart_start_tx(struct uart_port *port)
52{
53 unsigned int cr;
54
55 cr = UART_GET_CTRL(port);
56 cr |= UART_CTRL_TI;
57 UART_PUT_CTRL(port, cr);
58
59 if (UART_GET_STATUS(port) & UART_STATUS_THE)
60 apbuart_tx_chars(port);
61}
62
63static void apbuart_stop_rx(struct uart_port *port)
64{
65 unsigned int cr;
66
67 cr = UART_GET_CTRL(port);
68 cr &= ~(UART_CTRL_RI);
69 UART_PUT_CTRL(port, cr);
70}
71
72static void apbuart_enable_ms(struct uart_port *port)
73{
74 /* No modem status change interrupts for APBUART */
75}
76
77static void apbuart_rx_chars(struct uart_port *port)
78{
79 struct tty_struct *tty = port->state->port.tty;
80 unsigned int status, ch, rsr, flag;
81 unsigned int max_chars = port->fifosize;
82
83 status = UART_GET_STATUS(port);
84
85 while (UART_RX_DATA(status) && (max_chars--)) {
86
87 ch = UART_GET_CHAR(port);
88 flag = TTY_NORMAL;
89
90 port->icount.rx++;
91
92 rsr = UART_GET_STATUS(port) | UART_DUMMY_RSR_RX;
93 UART_PUT_STATUS(port, 0);
94 if (rsr & UART_STATUS_ERR) {
95
96 if (rsr & UART_STATUS_BR) {
97 rsr &= ~(UART_STATUS_FE | UART_STATUS_PE);
98 port->icount.brk++;
99 if (uart_handle_break(port))
100 goto ignore_char;
101 } else if (rsr & UART_STATUS_PE) {
102 port->icount.parity++;
103 } else if (rsr & UART_STATUS_FE) {
104 port->icount.frame++;
105 }
106 if (rsr & UART_STATUS_OE)
107 port->icount.overrun++;
108
109 rsr &= port->read_status_mask;
110
111 if (rsr & UART_STATUS_PE)
112 flag = TTY_PARITY;
113 else if (rsr & UART_STATUS_FE)
114 flag = TTY_FRAME;
115 }
116
117 if (uart_handle_sysrq_char(port, ch))
118 goto ignore_char;
119
120 uart_insert_char(port, rsr, UART_STATUS_OE, ch, flag);
121
122
123 ignore_char:
124 status = UART_GET_STATUS(port);
125 }
126
127 tty_flip_buffer_push(tty);
128}
129
130static void apbuart_tx_chars(struct uart_port *port)
131{
132 struct circ_buf *xmit = &port->state->xmit;
133 int count;
134
135 if (port->x_char) {
136 UART_PUT_CHAR(port, port->x_char);
137 port->icount.tx++;
138 port->x_char = 0;
139 return;
140 }
141
142 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
143 apbuart_stop_tx(port);
144 return;
145 }
146
147 /* amba: fill FIFO */
148 count = port->fifosize >> 1;
149 do {
150 UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
151 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
152 port->icount.tx++;
153 if (uart_circ_empty(xmit))
154 break;
155 } while (--count > 0);
156
157 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
158 uart_write_wakeup(port);
159
160 if (uart_circ_empty(xmit))
161 apbuart_stop_tx(port);
162}
163
164static irqreturn_t apbuart_int(int irq, void *dev_id)
165{
166 struct uart_port *port = dev_id;
167 unsigned int status;
168
169 spin_lock(&port->lock);
170
171 status = UART_GET_STATUS(port);
172 if (status & UART_STATUS_DR)
173 apbuart_rx_chars(port);
174 if (status & UART_STATUS_THE)
175 apbuart_tx_chars(port);
176
177 spin_unlock(&port->lock);
178
179 return IRQ_HANDLED;
180}
181
182static unsigned int apbuart_tx_empty(struct uart_port *port)
183{
184 unsigned int status = UART_GET_STATUS(port);
185 return status & UART_STATUS_THE ? TIOCSER_TEMT : 0;
186}
187
188static unsigned int apbuart_get_mctrl(struct uart_port *port)
189{
190 /* The GRLIB APBUART handles flow control in hardware */
191 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
192}
193
194static void apbuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
195{
196 /* The GRLIB APBUART handles flow control in hardware */
197}
198
199static void apbuart_break_ctl(struct uart_port *port, int break_state)
200{
201 /* We don't support sending break */
202}
203
204static int apbuart_startup(struct uart_port *port)
205{
206 int retval;
207 unsigned int cr;
208
209 /* Allocate the IRQ */
210 retval = request_irq(port->irq, apbuart_int, 0, "apbuart", port);
211 if (retval)
212 return retval;
213
214 /* Finally, enable interrupts */
215 cr = UART_GET_CTRL(port);
216 UART_PUT_CTRL(port,
217 cr | UART_CTRL_RE | UART_CTRL_TE |
218 UART_CTRL_RI | UART_CTRL_TI);
219
220 return 0;
221}
222
223static void apbuart_shutdown(struct uart_port *port)
224{
225 unsigned int cr;
226
227 /* disable all interrupts, disable the port */
228 cr = UART_GET_CTRL(port);
229 UART_PUT_CTRL(port,
230 cr & ~(UART_CTRL_RE | UART_CTRL_TE |
231 UART_CTRL_RI | UART_CTRL_TI));
232
233 /* Free the interrupt */
234 free_irq(port->irq, port);
235}
236
237static void apbuart_set_termios(struct uart_port *port,
238 struct ktermios *termios, struct ktermios *old)
239{
240 unsigned int cr;
241 unsigned long flags;
242 unsigned int baud, quot;
243
244 /* Ask the core to calculate the divisor for us. */
245 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
246 if (baud == 0)
247 panic("invalid baudrate %i\n", port->uartclk / 16);
248
249 /* uart_get_divisor calc a *16 uart freq, apbuart is *8 */
250 quot = (uart_get_divisor(port, baud)) * 2;
251 cr = UART_GET_CTRL(port);
252 cr &= ~(UART_CTRL_PE | UART_CTRL_PS);
253
254 if (termios->c_cflag & PARENB) {
255 cr |= UART_CTRL_PE;
256 if ((termios->c_cflag & PARODD))
257 cr |= UART_CTRL_PS;
258 }
259
260 /* Enable flow control. */
261 if (termios->c_cflag & CRTSCTS)
262 cr |= UART_CTRL_FL;
263
264 spin_lock_irqsave(&port->lock, flags);
265
266 /* Update the per-port timeout. */
267 uart_update_timeout(port, termios->c_cflag, baud);
268
269 port->read_status_mask = UART_STATUS_OE;
270 if (termios->c_iflag & INPCK)
271 port->read_status_mask |= UART_STATUS_FE | UART_STATUS_PE;
272
273 /* Characters to ignore */
274 port->ignore_status_mask = 0;
275 if (termios->c_iflag & IGNPAR)
276 port->ignore_status_mask |= UART_STATUS_FE | UART_STATUS_PE;
277
278 /* Ignore all characters if CREAD is not set. */
279 if ((termios->c_cflag & CREAD) == 0)
280 port->ignore_status_mask |= UART_DUMMY_RSR_RX;
281
282 /* Set baud rate */
283 quot -= 1;
284 UART_PUT_SCAL(port, quot);
285 UART_PUT_CTRL(port, cr);
286
287 spin_unlock_irqrestore(&port->lock, flags);
288}
289
290static const char *apbuart_type(struct uart_port *port)
291{
292 return port->type == PORT_APBUART ? "GRLIB/APBUART" : NULL;
293}
294
295static void apbuart_release_port(struct uart_port *port)
296{
297 release_mem_region(port->mapbase, 0x100);
298}
299
300static int apbuart_request_port(struct uart_port *port)
301{
302 return request_mem_region(port->mapbase, 0x100, "grlib-apbuart")
303 != NULL ? 0 : -EBUSY;
304 return 0;
305}
306
307/* Configure/autoconfigure the port */
308static void apbuart_config_port(struct uart_port *port, int flags)
309{
310 if (flags & UART_CONFIG_TYPE) {
311 port->type = PORT_APBUART;
312 apbuart_request_port(port);
313 }
314}
315
316/* Verify the new serial_struct (for TIOCSSERIAL) */
317static int apbuart_verify_port(struct uart_port *port,
318 struct serial_struct *ser)
319{
320 int ret = 0;
321 if (ser->type != PORT_UNKNOWN && ser->type != PORT_APBUART)
322 ret = -EINVAL;
323 if (ser->irq < 0 || ser->irq >= NR_IRQS)
324 ret = -EINVAL;
325 if (ser->baud_base < 9600)
326 ret = -EINVAL;
327 return ret;
328}
329
330static struct uart_ops grlib_apbuart_ops = {
331 .tx_empty = apbuart_tx_empty,
332 .set_mctrl = apbuart_set_mctrl,
333 .get_mctrl = apbuart_get_mctrl,
334 .stop_tx = apbuart_stop_tx,
335 .start_tx = apbuart_start_tx,
336 .stop_rx = apbuart_stop_rx,
337 .enable_ms = apbuart_enable_ms,
338 .break_ctl = apbuart_break_ctl,
339 .startup = apbuart_startup,
340 .shutdown = apbuart_shutdown,
341 .set_termios = apbuart_set_termios,
342 .type = apbuart_type,
343 .release_port = apbuart_release_port,
344 .request_port = apbuart_request_port,
345 .config_port = apbuart_config_port,
346 .verify_port = apbuart_verify_port,
347};
348
349static struct uart_port grlib_apbuart_ports[UART_NR];
350static struct device_node *grlib_apbuart_nodes[UART_NR];
351
352static int apbuart_scan_fifo_size(struct uart_port *port, int portnumber)
353{
354 int ctrl, loop = 0;
355 int status;
356 int fifosize;
357 unsigned long flags;
358
359 ctrl = UART_GET_CTRL(port);
360
361 /*
362 * Enable the transceiver and wait for it to be ready to send data.
363 * Clear interrupts so that this process will not be externally
364 * interrupted in the middle (which can cause the transceiver to
365 * drain prematurely).
366 */
367
368 local_irq_save(flags);
369
370 UART_PUT_CTRL(port, ctrl | UART_CTRL_TE);
371
372 while (!UART_TX_READY(UART_GET_STATUS(port)))
373 loop++;
374
375 /*
376 * Disable the transceiver so data isn't actually sent during the
377 * actual test.
378 */
379
380 UART_PUT_CTRL(port, ctrl & ~(UART_CTRL_TE));
381
382 fifosize = 1;
383 UART_PUT_CHAR(port, 0);
384
385 /*
386 * So long as transmitting a character increments the tranceivier FIFO
387 * length the FIFO must be at least that big. These bytes will
388 * automatically drain off of the FIFO.
389 */
390
391 status = UART_GET_STATUS(port);
392 while (((status >> 20) & 0x3F) == fifosize) {
393 fifosize++;
394 UART_PUT_CHAR(port, 0);
395 status = UART_GET_STATUS(port);
396 }
397
398 fifosize--;
399
400 UART_PUT_CTRL(port, ctrl);
401 local_irq_restore(flags);
402
403 if (fifosize == 0)
404 fifosize = 1;
405
406 return fifosize;
407}
408
409static void apbuart_flush_fifo(struct uart_port *port)
410{
411 int i;
412
413 for (i = 0; i < port->fifosize; i++)
414 UART_GET_CHAR(port);
415}
416
417
418/* ======================================================================== */
419/* Console driver, if enabled */
420/* ======================================================================== */
421
422#ifdef CONFIG_SERIAL_GRLIB_GAISLER_APBUART_CONSOLE
423
424static void apbuart_console_putchar(struct uart_port *port, int ch)
425{
426 unsigned int status;
427 do {
428 status = UART_GET_STATUS(port);
429 } while (!UART_TX_READY(status));
430 UART_PUT_CHAR(port, ch);
431}
432
433static void
434apbuart_console_write(struct console *co, const char *s, unsigned int count)
435{
436 struct uart_port *port = &grlib_apbuart_ports[co->index];
437 unsigned int status, old_cr, new_cr;
438
439 /* First save the CR then disable the interrupts */
440 old_cr = UART_GET_CTRL(port);
441 new_cr = old_cr & ~(UART_CTRL_RI | UART_CTRL_TI);
442 UART_PUT_CTRL(port, new_cr);
443
444 uart_console_write(port, s, count, apbuart_console_putchar);
445
446 /*
447 * Finally, wait for transmitter to become empty
448 * and restore the TCR
449 */
450 do {
451 status = UART_GET_STATUS(port);
452 } while (!UART_TX_READY(status));
453 UART_PUT_CTRL(port, old_cr);
454}
455
456static void __init
457apbuart_console_get_options(struct uart_port *port, int *baud,
458 int *parity, int *bits)
459{
460 if (UART_GET_CTRL(port) & (UART_CTRL_RE | UART_CTRL_TE)) {
461
462 unsigned int quot, status;
463 status = UART_GET_STATUS(port);
464
465 *parity = 'n';
466 if (status & UART_CTRL_PE) {
467 if ((status & UART_CTRL_PS) == 0)
468 *parity = 'e';
469 else
470 *parity = 'o';
471 }
472
473 *bits = 8;
474 quot = UART_GET_SCAL(port) / 8;
475 *baud = port->uartclk / (16 * (quot + 1));
476 }
477}
478
479static int __init apbuart_console_setup(struct console *co, char *options)
480{
481 struct uart_port *port;
482 int baud = 38400;
483 int bits = 8;
484 int parity = 'n';
485 int flow = 'n';
486
487 pr_debug("apbuart_console_setup co=%p, co->index=%i, options=%s\n",
488 co, co->index, options);
489
490 /*
491 * Check whether an invalid uart number has been specified, and
492 * if so, search for the first available port that does have
493 * console support.
494 */
495 if (co->index >= grlib_apbuart_port_nr)
496 co->index = 0;
497
498 port = &grlib_apbuart_ports[co->index];
499
500 spin_lock_init(&port->lock);
501
502 if (options)
503 uart_parse_options(options, &baud, &parity, &bits, &flow);
504 else
505 apbuart_console_get_options(port, &baud, &parity, &bits);
506
507 return uart_set_options(port, co, baud, parity, bits, flow);
508}
509
510static struct uart_driver grlib_apbuart_driver;
511
512static struct console grlib_apbuart_console = {
513 .name = "ttyS",
514 .write = apbuart_console_write,
515 .device = uart_console_device,
516 .setup = apbuart_console_setup,
517 .flags = CON_PRINTBUFFER,
518 .index = -1,
519 .data = &grlib_apbuart_driver,
520};
521
522
523static void grlib_apbuart_configure(void);
524
525static int __init apbuart_console_init(void)
526{
527 grlib_apbuart_configure();
528 register_console(&grlib_apbuart_console);
529 return 0;
530}
531
532console_initcall(apbuart_console_init);
533
534#define APBUART_CONSOLE (&grlib_apbuart_console)
535#else
536#define APBUART_CONSOLE NULL
537#endif
538
539static struct uart_driver grlib_apbuart_driver = {
540 .owner = THIS_MODULE,
541 .driver_name = "serial",
542 .dev_name = "ttyS",
543 .major = SERIAL_APBUART_MAJOR,
544 .minor = SERIAL_APBUART_MINOR,
545 .nr = UART_NR,
546 .cons = APBUART_CONSOLE,
547};
548
549
550/* ======================================================================== */
551/* OF Platform Driver */
552/* ======================================================================== */
553
554static int __devinit apbuart_probe(struct platform_device *op,
555 const struct of_device_id *match)
556{
557 int i = -1;
558 struct uart_port *port = NULL;
559
560 i = 0;
561 for (i = 0; i < grlib_apbuart_port_nr; i++) {
562 if (op->dev.of_node == grlib_apbuart_nodes[i])
563 break;
564 }
565
566 port = &grlib_apbuart_ports[i];
567 port->dev = &op->dev;
568
569 uart_add_one_port(&grlib_apbuart_driver, (struct uart_port *) port);
570
571 apbuart_flush_fifo((struct uart_port *) port);
572
573 printk(KERN_INFO "grlib-apbuart at 0x%llx, irq %d\n",
574 (unsigned long long) port->mapbase, port->irq);
575 return 0;
576
577}
578
579static struct of_device_id __initdata apbuart_match[] = {
580 {
581 .name = "GAISLER_APBUART",
582 },
583 {},
584};
585
586static struct of_platform_driver grlib_apbuart_of_driver = {
587 .probe = apbuart_probe,
588 .driver = {
589 .owner = THIS_MODULE,
590 .name = "grlib-apbuart",
591 .of_match_table = apbuart_match,
592 },
593};
594
595
596static void grlib_apbuart_configure(void)
597{
598 static int enum_done;
599 struct device_node *np, *rp;
600 struct uart_port *port = NULL;
601 const u32 *prop;
602 int freq_khz;
603 int v = 0, d = 0;
604 unsigned int addr;
605 int irq, line;
606 struct amba_prom_registers *regs;
607
608 if (enum_done)
609 return;
610
611 /* Get bus frequency */
612 rp = of_find_node_by_path("/");
613 rp = of_get_next_child(rp, NULL);
614 prop = of_get_property(rp, "clock-frequency", NULL);
615 freq_khz = *prop;
616
617 line = 0;
618 for_each_matching_node(np, apbuart_match) {
619
620 int *vendor = (int *) of_get_property(np, "vendor", NULL);
621 int *device = (int *) of_get_property(np, "device", NULL);
622 int *irqs = (int *) of_get_property(np, "interrupts", NULL);
623 regs = (struct amba_prom_registers *)
624 of_get_property(np, "reg", NULL);
625
626 if (vendor)
627 v = *vendor;
628 if (device)
629 d = *device;
630
631 if (!irqs || !regs)
632 return;
633
634 grlib_apbuart_nodes[line] = np;
635
636 addr = regs->phys_addr;
637 irq = *irqs;
638
639 port = &grlib_apbuart_ports[line];
640
641 port->mapbase = addr;
642 port->membase = ioremap(addr, sizeof(struct grlib_apbuart_regs_map));
643 port->irq = irq;
644 port->iotype = UPIO_MEM;
645 port->ops = &grlib_apbuart_ops;
646 port->flags = UPF_BOOT_AUTOCONF;
647 port->line = line;
648 port->uartclk = freq_khz * 1000;
649 port->fifosize = apbuart_scan_fifo_size((struct uart_port *) port, line);
650 line++;
651
652 /* We support maximum UART_NR uarts ... */
653 if (line == UART_NR)
654 break;
655
656 }
657
658 enum_done = 1;
659
660 grlib_apbuart_driver.nr = grlib_apbuart_port_nr = line;
661}
662
663static int __init grlib_apbuart_init(void)
664{
665 int ret;
666
667 /* Find all APBUARTS in device the tree and initialize their ports */
668 grlib_apbuart_configure();
669
670 printk(KERN_INFO "Serial: GRLIB APBUART driver\n");
671
672 ret = uart_register_driver(&grlib_apbuart_driver);
673
674 if (ret) {
675 printk(KERN_ERR "%s: uart_register_driver failed (%i)\n",
676 __FILE__, ret);
677 return ret;
678 }
679
680 ret = of_register_platform_driver(&grlib_apbuart_of_driver);
681 if (ret) {
682 printk(KERN_ERR
683 "%s: of_register_platform_driver failed (%i)\n",
684 __FILE__, ret);
685 uart_unregister_driver(&grlib_apbuart_driver);
686 return ret;
687 }
688
689 return ret;
690}
691
692static void __exit grlib_apbuart_exit(void)
693{
694 int i;
695
696 for (i = 0; i < grlib_apbuart_port_nr; i++)
697 uart_remove_one_port(&grlib_apbuart_driver,
698 &grlib_apbuart_ports[i]);
699
700 uart_unregister_driver(&grlib_apbuart_driver);
701 of_unregister_platform_driver(&grlib_apbuart_of_driver);
702}
703
704module_init(grlib_apbuart_init);
705module_exit(grlib_apbuart_exit);
706
707MODULE_AUTHOR("Aeroflex Gaisler AB");
708MODULE_DESCRIPTION("GRLIB APBUART serial driver");
709MODULE_VERSION("2.1");
710MODULE_LICENSE("GPL");
diff --git a/drivers/serial/apbuart.h b/drivers/serial/apbuart.h
deleted file mode 100644
index 5faf87c8d2bc..000000000000
--- a/drivers/serial/apbuart.h
+++ /dev/null
@@ -1,64 +0,0 @@
1#ifndef __GRLIB_APBUART_H__
2#define __GRLIB_APBUART_H__
3
4#include <asm/io.h>
5
6#define UART_NR 8
7static int grlib_apbuart_port_nr;
8
9struct grlib_apbuart_regs_map {
10 u32 data;
11 u32 status;
12 u32 ctrl;
13 u32 scaler;
14};
15
16struct amba_prom_registers {
17 unsigned int phys_addr;
18 unsigned int reg_size;
19};
20
21/*
22 * The following defines the bits in the APBUART Status Registers.
23 */
24#define UART_STATUS_DR 0x00000001 /* Data Ready */
25#define UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */
26#define UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */
27#define UART_STATUS_BR 0x00000008 /* Break Error */
28#define UART_STATUS_OE 0x00000010 /* RX Overrun Error */
29#define UART_STATUS_PE 0x00000020 /* RX Parity Error */
30#define UART_STATUS_FE 0x00000040 /* RX Framing Error */
31#define UART_STATUS_ERR 0x00000078 /* Error Mask */
32
33/*
34 * The following defines the bits in the APBUART Ctrl Registers.
35 */
36#define UART_CTRL_RE 0x00000001 /* Receiver enable */
37#define UART_CTRL_TE 0x00000002 /* Transmitter enable */
38#define UART_CTRL_RI 0x00000004 /* Receiver interrupt enable */
39#define UART_CTRL_TI 0x00000008 /* Transmitter irq */
40#define UART_CTRL_PS 0x00000010 /* Parity select */
41#define UART_CTRL_PE 0x00000020 /* Parity enable */
42#define UART_CTRL_FL 0x00000040 /* Flow control enable */
43#define UART_CTRL_LB 0x00000080 /* Loopback enable */
44
45#define APBBASE(port) ((struct grlib_apbuart_regs_map *)((port)->membase))
46
47#define APBBASE_DATA_P(port) (&(APBBASE(port)->data))
48#define APBBASE_STATUS_P(port) (&(APBBASE(port)->status))
49#define APBBASE_CTRL_P(port) (&(APBBASE(port)->ctrl))
50#define APBBASE_SCALAR_P(port) (&(APBBASE(port)->scaler))
51
52#define UART_GET_CHAR(port) (__raw_readl(APBBASE_DATA_P(port)))
53#define UART_PUT_CHAR(port, v) (__raw_writel(v, APBBASE_DATA_P(port)))
54#define UART_GET_STATUS(port) (__raw_readl(APBBASE_STATUS_P(port)))
55#define UART_PUT_STATUS(port, v)(__raw_writel(v, APBBASE_STATUS_P(port)))
56#define UART_GET_CTRL(port) (__raw_readl(APBBASE_CTRL_P(port)))
57#define UART_PUT_CTRL(port, v) (__raw_writel(v, APBBASE_CTRL_P(port)))
58#define UART_GET_SCAL(port) (__raw_readl(APBBASE_SCALAR_P(port)))
59#define UART_PUT_SCAL(port, v) (__raw_writel(v, APBBASE_SCALAR_P(port)))
60
61#define UART_RX_DATA(s) (((s) & UART_STATUS_DR) != 0)
62#define UART_TX_READY(s) (((s) & UART_STATUS_THE) != 0)
63
64#endif /* __GRLIB_APBUART_H__ */
diff --git a/drivers/serial/atmel_serial.c b/drivers/serial/atmel_serial.c
deleted file mode 100644
index 3892666b5fbd..000000000000
--- a/drivers/serial/atmel_serial.c
+++ /dev/null
@@ -1,1808 +0,0 @@
1/*
2 * linux/drivers/char/atmel_serial.c
3 *
4 * Driver for Atmel AT91 / AT32 Serial ports
5 * Copyright (C) 2003 Rick Bronson
6 *
7 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
8 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
9 *
10 * DMA support added by Chip Coldwell.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 */
27#include <linux/module.h>
28#include <linux/tty.h>
29#include <linux/ioport.h>
30#include <linux/slab.h>
31#include <linux/init.h>
32#include <linux/serial.h>
33#include <linux/clk.h>
34#include <linux/console.h>
35#include <linux/sysrq.h>
36#include <linux/tty_flip.h>
37#include <linux/platform_device.h>
38#include <linux/dma-mapping.h>
39#include <linux/atmel_pdc.h>
40#include <linux/atmel_serial.h>
41#include <linux/uaccess.h>
42
43#include <asm/io.h>
44#include <asm/ioctls.h>
45
46#include <asm/mach/serial_at91.h>
47#include <mach/board.h>
48
49#ifdef CONFIG_ARM
50#include <mach/cpu.h>
51#include <mach/gpio.h>
52#endif
53
54#define PDC_BUFFER_SIZE 512
55/* Revisit: We should calculate this based on the actual port settings */
56#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
57
58#if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
59#define SUPPORT_SYSRQ
60#endif
61
62#include <linux/serial_core.h>
63
64static void atmel_start_rx(struct uart_port *port);
65static void atmel_stop_rx(struct uart_port *port);
66
67#ifdef CONFIG_SERIAL_ATMEL_TTYAT
68
69/* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
70 * should coexist with the 8250 driver, such as if we have an external 16C550
71 * UART. */
72#define SERIAL_ATMEL_MAJOR 204
73#define MINOR_START 154
74#define ATMEL_DEVICENAME "ttyAT"
75
76#else
77
78/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
79 * name, but it is legally reserved for the 8250 driver. */
80#define SERIAL_ATMEL_MAJOR TTY_MAJOR
81#define MINOR_START 64
82#define ATMEL_DEVICENAME "ttyS"
83
84#endif
85
86#define ATMEL_ISR_PASS_LIMIT 256
87
88/* UART registers. CR is write-only, hence no GET macro */
89#define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR)
90#define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR)
91#define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR)
92#define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER)
93#define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR)
94#define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR)
95#define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR)
96#define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR)
97#define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR)
98#define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR)
99#define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR)
100#define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR)
101#define UART_PUT_TTGR(port, v) __raw_writel(v, (port)->membase + ATMEL_US_TTGR)
102
103 /* PDC registers */
104#define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR)
105#define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR)
106
107#define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR)
108#define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR)
109#define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR)
110#define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR)
111#define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR)
112
113#define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR)
114#define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR)
115#define UART_GET_TCR(port) __raw_readl((port)->membase + ATMEL_PDC_TCR)
116
117static int (*atmel_open_hook)(struct uart_port *);
118static void (*atmel_close_hook)(struct uart_port *);
119
120struct atmel_dma_buffer {
121 unsigned char *buf;
122 dma_addr_t dma_addr;
123 unsigned int dma_size;
124 unsigned int ofs;
125};
126
127struct atmel_uart_char {
128 u16 status;
129 u16 ch;
130};
131
132#define ATMEL_SERIAL_RINGSIZE 1024
133
134/*
135 * We wrap our port structure around the generic uart_port.
136 */
137struct atmel_uart_port {
138 struct uart_port uart; /* uart */
139 struct clk *clk; /* uart clock */
140 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
141 u32 backup_imr; /* IMR saved during suspend */
142 int break_active; /* break being received */
143
144 short use_dma_rx; /* enable PDC receiver */
145 short pdc_rx_idx; /* current PDC RX buffer */
146 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
147
148 short use_dma_tx; /* enable PDC transmitter */
149 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
150
151 struct tasklet_struct tasklet;
152 unsigned int irq_status;
153 unsigned int irq_status_prev;
154
155 struct circ_buf rx_ring;
156
157 struct serial_rs485 rs485; /* rs485 settings */
158 unsigned int tx_done_mask;
159};
160
161static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
162
163#ifdef SUPPORT_SYSRQ
164static struct console atmel_console;
165#endif
166
167static inline struct atmel_uart_port *
168to_atmel_uart_port(struct uart_port *uart)
169{
170 return container_of(uart, struct atmel_uart_port, uart);
171}
172
173#ifdef CONFIG_SERIAL_ATMEL_PDC
174static bool atmel_use_dma_rx(struct uart_port *port)
175{
176 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
177
178 return atmel_port->use_dma_rx;
179}
180
181static bool atmel_use_dma_tx(struct uart_port *port)
182{
183 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
184
185 return atmel_port->use_dma_tx;
186}
187#else
188static bool atmel_use_dma_rx(struct uart_port *port)
189{
190 return false;
191}
192
193static bool atmel_use_dma_tx(struct uart_port *port)
194{
195 return false;
196}
197#endif
198
199/* Enable or disable the rs485 support */
200void atmel_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf)
201{
202 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
203 unsigned int mode;
204
205 spin_lock(&port->lock);
206
207 /* Disable interrupts */
208 UART_PUT_IDR(port, atmel_port->tx_done_mask);
209
210 mode = UART_GET_MR(port);
211
212 /* Resetting serial mode to RS232 (0x0) */
213 mode &= ~ATMEL_US_USMODE;
214
215 atmel_port->rs485 = *rs485conf;
216
217 if (rs485conf->flags & SER_RS485_ENABLED) {
218 dev_dbg(port->dev, "Setting UART to RS485\n");
219 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
220 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
221 UART_PUT_TTGR(port, rs485conf->delay_rts_after_send);
222 mode |= ATMEL_US_USMODE_RS485;
223 } else {
224 dev_dbg(port->dev, "Setting UART to RS232\n");
225 if (atmel_use_dma_tx(port))
226 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
227 ATMEL_US_TXBUFE;
228 else
229 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
230 }
231 UART_PUT_MR(port, mode);
232
233 /* Enable interrupts */
234 UART_PUT_IER(port, atmel_port->tx_done_mask);
235
236 spin_unlock(&port->lock);
237
238}
239
240/*
241 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
242 */
243static u_int atmel_tx_empty(struct uart_port *port)
244{
245 return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0;
246}
247
248/*
249 * Set state of the modem control output lines
250 */
251static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
252{
253 unsigned int control = 0;
254 unsigned int mode;
255 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
256
257#ifdef CONFIG_ARCH_AT91RM9200
258 if (cpu_is_at91rm9200()) {
259 /*
260 * AT91RM9200 Errata #39: RTS0 is not internally connected
261 * to PA21. We need to drive the pin manually.
262 */
263 if (port->mapbase == AT91RM9200_BASE_US0) {
264 if (mctrl & TIOCM_RTS)
265 at91_set_gpio_value(AT91_PIN_PA21, 0);
266 else
267 at91_set_gpio_value(AT91_PIN_PA21, 1);
268 }
269 }
270#endif
271
272 if (mctrl & TIOCM_RTS)
273 control |= ATMEL_US_RTSEN;
274 else
275 control |= ATMEL_US_RTSDIS;
276
277 if (mctrl & TIOCM_DTR)
278 control |= ATMEL_US_DTREN;
279 else
280 control |= ATMEL_US_DTRDIS;
281
282 UART_PUT_CR(port, control);
283
284 /* Local loopback mode? */
285 mode = UART_GET_MR(port) & ~ATMEL_US_CHMODE;
286 if (mctrl & TIOCM_LOOP)
287 mode |= ATMEL_US_CHMODE_LOC_LOOP;
288 else
289 mode |= ATMEL_US_CHMODE_NORMAL;
290
291 /* Resetting serial mode to RS232 (0x0) */
292 mode &= ~ATMEL_US_USMODE;
293
294 if (atmel_port->rs485.flags & SER_RS485_ENABLED) {
295 dev_dbg(port->dev, "Setting UART to RS485\n");
296 if (atmel_port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
297 UART_PUT_TTGR(port,
298 atmel_port->rs485.delay_rts_after_send);
299 mode |= ATMEL_US_USMODE_RS485;
300 } else {
301 dev_dbg(port->dev, "Setting UART to RS232\n");
302 }
303 UART_PUT_MR(port, mode);
304}
305
306/*
307 * Get state of the modem control input lines
308 */
309static u_int atmel_get_mctrl(struct uart_port *port)
310{
311 unsigned int status, ret = 0;
312
313 status = UART_GET_CSR(port);
314
315 /*
316 * The control signals are active low.
317 */
318 if (!(status & ATMEL_US_DCD))
319 ret |= TIOCM_CD;
320 if (!(status & ATMEL_US_CTS))
321 ret |= TIOCM_CTS;
322 if (!(status & ATMEL_US_DSR))
323 ret |= TIOCM_DSR;
324 if (!(status & ATMEL_US_RI))
325 ret |= TIOCM_RI;
326
327 return ret;
328}
329
330/*
331 * Stop transmitting.
332 */
333static void atmel_stop_tx(struct uart_port *port)
334{
335 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
336
337 if (atmel_use_dma_tx(port)) {
338 /* disable PDC transmit */
339 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
340 }
341 /* Disable interrupts */
342 UART_PUT_IDR(port, atmel_port->tx_done_mask);
343
344 if (atmel_port->rs485.flags & SER_RS485_ENABLED)
345 atmel_start_rx(port);
346}
347
348/*
349 * Start transmitting.
350 */
351static void atmel_start_tx(struct uart_port *port)
352{
353 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
354
355 if (atmel_use_dma_tx(port)) {
356 if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN)
357 /* The transmitter is already running. Yes, we
358 really need this.*/
359 return;
360
361 if (atmel_port->rs485.flags & SER_RS485_ENABLED)
362 atmel_stop_rx(port);
363
364 /* re-enable PDC transmit */
365 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
366 }
367 /* Enable interrupts */
368 UART_PUT_IER(port, atmel_port->tx_done_mask);
369}
370
371/*
372 * start receiving - port is in process of being opened.
373 */
374static void atmel_start_rx(struct uart_port *port)
375{
376 UART_PUT_CR(port, ATMEL_US_RSTSTA); /* reset status and receiver */
377
378 if (atmel_use_dma_rx(port)) {
379 /* enable PDC controller */
380 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
381 port->read_status_mask);
382 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
383 } else {
384 UART_PUT_IER(port, ATMEL_US_RXRDY);
385 }
386}
387
388/*
389 * Stop receiving - port is in process of being closed.
390 */
391static void atmel_stop_rx(struct uart_port *port)
392{
393 if (atmel_use_dma_rx(port)) {
394 /* disable PDC receive */
395 UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS);
396 UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
397 port->read_status_mask);
398 } else {
399 UART_PUT_IDR(port, ATMEL_US_RXRDY);
400 }
401}
402
403/*
404 * Enable modem status interrupts
405 */
406static void atmel_enable_ms(struct uart_port *port)
407{
408 UART_PUT_IER(port, ATMEL_US_RIIC | ATMEL_US_DSRIC
409 | ATMEL_US_DCDIC | ATMEL_US_CTSIC);
410}
411
412/*
413 * Control the transmission of a break signal
414 */
415static void atmel_break_ctl(struct uart_port *port, int break_state)
416{
417 if (break_state != 0)
418 UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */
419 else
420 UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */
421}
422
423/*
424 * Stores the incoming character in the ring buffer
425 */
426static void
427atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
428 unsigned int ch)
429{
430 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
431 struct circ_buf *ring = &atmel_port->rx_ring;
432 struct atmel_uart_char *c;
433
434 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
435 /* Buffer overflow, ignore char */
436 return;
437
438 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
439 c->status = status;
440 c->ch = ch;
441
442 /* Make sure the character is stored before we update head. */
443 smp_wmb();
444
445 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
446}
447
448/*
449 * Deal with parity, framing and overrun errors.
450 */
451static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
452{
453 /* clear error */
454 UART_PUT_CR(port, ATMEL_US_RSTSTA);
455
456 if (status & ATMEL_US_RXBRK) {
457 /* ignore side-effect */
458 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
459 port->icount.brk++;
460 }
461 if (status & ATMEL_US_PARE)
462 port->icount.parity++;
463 if (status & ATMEL_US_FRAME)
464 port->icount.frame++;
465 if (status & ATMEL_US_OVRE)
466 port->icount.overrun++;
467}
468
469/*
470 * Characters received (called from interrupt handler)
471 */
472static void atmel_rx_chars(struct uart_port *port)
473{
474 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
475 unsigned int status, ch;
476
477 status = UART_GET_CSR(port);
478 while (status & ATMEL_US_RXRDY) {
479 ch = UART_GET_CHAR(port);
480
481 /*
482 * note that the error handling code is
483 * out of the main execution path
484 */
485 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
486 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
487 || atmel_port->break_active)) {
488
489 /* clear error */
490 UART_PUT_CR(port, ATMEL_US_RSTSTA);
491
492 if (status & ATMEL_US_RXBRK
493 && !atmel_port->break_active) {
494 atmel_port->break_active = 1;
495 UART_PUT_IER(port, ATMEL_US_RXBRK);
496 } else {
497 /*
498 * This is either the end-of-break
499 * condition or we've received at
500 * least one character without RXBRK
501 * being set. In both cases, the next
502 * RXBRK will indicate start-of-break.
503 */
504 UART_PUT_IDR(port, ATMEL_US_RXBRK);
505 status &= ~ATMEL_US_RXBRK;
506 atmel_port->break_active = 0;
507 }
508 }
509
510 atmel_buffer_rx_char(port, status, ch);
511 status = UART_GET_CSR(port);
512 }
513
514 tasklet_schedule(&atmel_port->tasklet);
515}
516
517/*
518 * Transmit characters (called from tasklet with TXRDY interrupt
519 * disabled)
520 */
521static void atmel_tx_chars(struct uart_port *port)
522{
523 struct circ_buf *xmit = &port->state->xmit;
524 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
525
526 if (port->x_char && UART_GET_CSR(port) & atmel_port->tx_done_mask) {
527 UART_PUT_CHAR(port, port->x_char);
528 port->icount.tx++;
529 port->x_char = 0;
530 }
531 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
532 return;
533
534 while (UART_GET_CSR(port) & atmel_port->tx_done_mask) {
535 UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
536 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
537 port->icount.tx++;
538 if (uart_circ_empty(xmit))
539 break;
540 }
541
542 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
543 uart_write_wakeup(port);
544
545 if (!uart_circ_empty(xmit))
546 /* Enable interrupts */
547 UART_PUT_IER(port, atmel_port->tx_done_mask);
548}
549
550/*
551 * receive interrupt handler.
552 */
553static void
554atmel_handle_receive(struct uart_port *port, unsigned int pending)
555{
556 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
557
558 if (atmel_use_dma_rx(port)) {
559 /*
560 * PDC receive. Just schedule the tasklet and let it
561 * figure out the details.
562 *
563 * TODO: We're not handling error flags correctly at
564 * the moment.
565 */
566 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
567 UART_PUT_IDR(port, (ATMEL_US_ENDRX
568 | ATMEL_US_TIMEOUT));
569 tasklet_schedule(&atmel_port->tasklet);
570 }
571
572 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
573 ATMEL_US_FRAME | ATMEL_US_PARE))
574 atmel_pdc_rxerr(port, pending);
575 }
576
577 /* Interrupt receive */
578 if (pending & ATMEL_US_RXRDY)
579 atmel_rx_chars(port);
580 else if (pending & ATMEL_US_RXBRK) {
581 /*
582 * End of break detected. If it came along with a
583 * character, atmel_rx_chars will handle it.
584 */
585 UART_PUT_CR(port, ATMEL_US_RSTSTA);
586 UART_PUT_IDR(port, ATMEL_US_RXBRK);
587 atmel_port->break_active = 0;
588 }
589}
590
591/*
592 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
593 */
594static void
595atmel_handle_transmit(struct uart_port *port, unsigned int pending)
596{
597 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
598
599 if (pending & atmel_port->tx_done_mask) {
600 /* Either PDC or interrupt transmission */
601 UART_PUT_IDR(port, atmel_port->tx_done_mask);
602 tasklet_schedule(&atmel_port->tasklet);
603 }
604}
605
606/*
607 * status flags interrupt handler.
608 */
609static void
610atmel_handle_status(struct uart_port *port, unsigned int pending,
611 unsigned int status)
612{
613 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
614
615 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
616 | ATMEL_US_CTSIC)) {
617 atmel_port->irq_status = status;
618 tasklet_schedule(&atmel_port->tasklet);
619 }
620}
621
622/*
623 * Interrupt handler
624 */
625static irqreturn_t atmel_interrupt(int irq, void *dev_id)
626{
627 struct uart_port *port = dev_id;
628 unsigned int status, pending, pass_counter = 0;
629
630 do {
631 status = UART_GET_CSR(port);
632 pending = status & UART_GET_IMR(port);
633 if (!pending)
634 break;
635
636 atmel_handle_receive(port, pending);
637 atmel_handle_status(port, pending, status);
638 atmel_handle_transmit(port, pending);
639 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
640
641 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
642}
643
644/*
645 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
646 */
647static void atmel_tx_dma(struct uart_port *port)
648{
649 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
650 struct circ_buf *xmit = &port->state->xmit;
651 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
652 int count;
653
654 /* nothing left to transmit? */
655 if (UART_GET_TCR(port))
656 return;
657
658 xmit->tail += pdc->ofs;
659 xmit->tail &= UART_XMIT_SIZE - 1;
660
661 port->icount.tx += pdc->ofs;
662 pdc->ofs = 0;
663
664 /* more to transmit - setup next transfer */
665
666 /* disable PDC transmit */
667 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
668
669 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
670 dma_sync_single_for_device(port->dev,
671 pdc->dma_addr,
672 pdc->dma_size,
673 DMA_TO_DEVICE);
674
675 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
676 pdc->ofs = count;
677
678 UART_PUT_TPR(port, pdc->dma_addr + xmit->tail);
679 UART_PUT_TCR(port, count);
680 /* re-enable PDC transmit */
681 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
682 /* Enable interrupts */
683 UART_PUT_IER(port, atmel_port->tx_done_mask);
684 } else {
685 if (atmel_port->rs485.flags & SER_RS485_ENABLED) {
686 /* DMA done, stop TX, start RX for RS485 */
687 atmel_start_rx(port);
688 }
689 }
690
691 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
692 uart_write_wakeup(port);
693}
694
695static void atmel_rx_from_ring(struct uart_port *port)
696{
697 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
698 struct circ_buf *ring = &atmel_port->rx_ring;
699 unsigned int flg;
700 unsigned int status;
701
702 while (ring->head != ring->tail) {
703 struct atmel_uart_char c;
704
705 /* Make sure c is loaded after head. */
706 smp_rmb();
707
708 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
709
710 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
711
712 port->icount.rx++;
713 status = c.status;
714 flg = TTY_NORMAL;
715
716 /*
717 * note that the error handling code is
718 * out of the main execution path
719 */
720 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
721 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
722 if (status & ATMEL_US_RXBRK) {
723 /* ignore side-effect */
724 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
725
726 port->icount.brk++;
727 if (uart_handle_break(port))
728 continue;
729 }
730 if (status & ATMEL_US_PARE)
731 port->icount.parity++;
732 if (status & ATMEL_US_FRAME)
733 port->icount.frame++;
734 if (status & ATMEL_US_OVRE)
735 port->icount.overrun++;
736
737 status &= port->read_status_mask;
738
739 if (status & ATMEL_US_RXBRK)
740 flg = TTY_BREAK;
741 else if (status & ATMEL_US_PARE)
742 flg = TTY_PARITY;
743 else if (status & ATMEL_US_FRAME)
744 flg = TTY_FRAME;
745 }
746
747
748 if (uart_handle_sysrq_char(port, c.ch))
749 continue;
750
751 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
752 }
753
754 /*
755 * Drop the lock here since it might end up calling
756 * uart_start(), which takes the lock.
757 */
758 spin_unlock(&port->lock);
759 tty_flip_buffer_push(port->state->port.tty);
760 spin_lock(&port->lock);
761}
762
763static void atmel_rx_from_dma(struct uart_port *port)
764{
765 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
766 struct tty_struct *tty = port->state->port.tty;
767 struct atmel_dma_buffer *pdc;
768 int rx_idx = atmel_port->pdc_rx_idx;
769 unsigned int head;
770 unsigned int tail;
771 unsigned int count;
772
773 do {
774 /* Reset the UART timeout early so that we don't miss one */
775 UART_PUT_CR(port, ATMEL_US_STTTO);
776
777 pdc = &atmel_port->pdc_rx[rx_idx];
778 head = UART_GET_RPR(port) - pdc->dma_addr;
779 tail = pdc->ofs;
780
781 /* If the PDC has switched buffers, RPR won't contain
782 * any address within the current buffer. Since head
783 * is unsigned, we just need a one-way comparison to
784 * find out.
785 *
786 * In this case, we just need to consume the entire
787 * buffer and resubmit it for DMA. This will clear the
788 * ENDRX bit as well, so that we can safely re-enable
789 * all interrupts below.
790 */
791 head = min(head, pdc->dma_size);
792
793 if (likely(head != tail)) {
794 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
795 pdc->dma_size, DMA_FROM_DEVICE);
796
797 /*
798 * head will only wrap around when we recycle
799 * the DMA buffer, and when that happens, we
800 * explicitly set tail to 0. So head will
801 * always be greater than tail.
802 */
803 count = head - tail;
804
805 tty_insert_flip_string(tty, pdc->buf + pdc->ofs, count);
806
807 dma_sync_single_for_device(port->dev, pdc->dma_addr,
808 pdc->dma_size, DMA_FROM_DEVICE);
809
810 port->icount.rx += count;
811 pdc->ofs = head;
812 }
813
814 /*
815 * If the current buffer is full, we need to check if
816 * the next one contains any additional data.
817 */
818 if (head >= pdc->dma_size) {
819 pdc->ofs = 0;
820 UART_PUT_RNPR(port, pdc->dma_addr);
821 UART_PUT_RNCR(port, pdc->dma_size);
822
823 rx_idx = !rx_idx;
824 atmel_port->pdc_rx_idx = rx_idx;
825 }
826 } while (head >= pdc->dma_size);
827
828 /*
829 * Drop the lock here since it might end up calling
830 * uart_start(), which takes the lock.
831 */
832 spin_unlock(&port->lock);
833 tty_flip_buffer_push(tty);
834 spin_lock(&port->lock);
835
836 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
837}
838
839/*
840 * tasklet handling tty stuff outside the interrupt handler.
841 */
842static void atmel_tasklet_func(unsigned long data)
843{
844 struct uart_port *port = (struct uart_port *)data;
845 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
846 unsigned int status;
847 unsigned int status_change;
848
849 /* The interrupt handler does not take the lock */
850 spin_lock(&port->lock);
851
852 if (atmel_use_dma_tx(port))
853 atmel_tx_dma(port);
854 else
855 atmel_tx_chars(port);
856
857 status = atmel_port->irq_status;
858 status_change = status ^ atmel_port->irq_status_prev;
859
860 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
861 | ATMEL_US_DCD | ATMEL_US_CTS)) {
862 /* TODO: All reads to CSR will clear these interrupts! */
863 if (status_change & ATMEL_US_RI)
864 port->icount.rng++;
865 if (status_change & ATMEL_US_DSR)
866 port->icount.dsr++;
867 if (status_change & ATMEL_US_DCD)
868 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
869 if (status_change & ATMEL_US_CTS)
870 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
871
872 wake_up_interruptible(&port->state->port.delta_msr_wait);
873
874 atmel_port->irq_status_prev = status;
875 }
876
877 if (atmel_use_dma_rx(port))
878 atmel_rx_from_dma(port);
879 else
880 atmel_rx_from_ring(port);
881
882 spin_unlock(&port->lock);
883}
884
885/*
886 * Perform initialization and enable port for reception
887 */
888static int atmel_startup(struct uart_port *port)
889{
890 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
891 struct tty_struct *tty = port->state->port.tty;
892 int retval;
893
894 /*
895 * Ensure that no interrupts are enabled otherwise when
896 * request_irq() is called we could get stuck trying to
897 * handle an unexpected interrupt
898 */
899 UART_PUT_IDR(port, -1);
900
901 /*
902 * Allocate the IRQ
903 */
904 retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED,
905 tty ? tty->name : "atmel_serial", port);
906 if (retval) {
907 printk("atmel_serial: atmel_startup - Can't get irq\n");
908 return retval;
909 }
910
911 /*
912 * Initialize DMA (if necessary)
913 */
914 if (atmel_use_dma_rx(port)) {
915 int i;
916
917 for (i = 0; i < 2; i++) {
918 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
919
920 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
921 if (pdc->buf == NULL) {
922 if (i != 0) {
923 dma_unmap_single(port->dev,
924 atmel_port->pdc_rx[0].dma_addr,
925 PDC_BUFFER_SIZE,
926 DMA_FROM_DEVICE);
927 kfree(atmel_port->pdc_rx[0].buf);
928 }
929 free_irq(port->irq, port);
930 return -ENOMEM;
931 }
932 pdc->dma_addr = dma_map_single(port->dev,
933 pdc->buf,
934 PDC_BUFFER_SIZE,
935 DMA_FROM_DEVICE);
936 pdc->dma_size = PDC_BUFFER_SIZE;
937 pdc->ofs = 0;
938 }
939
940 atmel_port->pdc_rx_idx = 0;
941
942 UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr);
943 UART_PUT_RCR(port, PDC_BUFFER_SIZE);
944
945 UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr);
946 UART_PUT_RNCR(port, PDC_BUFFER_SIZE);
947 }
948 if (atmel_use_dma_tx(port)) {
949 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
950 struct circ_buf *xmit = &port->state->xmit;
951
952 pdc->buf = xmit->buf;
953 pdc->dma_addr = dma_map_single(port->dev,
954 pdc->buf,
955 UART_XMIT_SIZE,
956 DMA_TO_DEVICE);
957 pdc->dma_size = UART_XMIT_SIZE;
958 pdc->ofs = 0;
959 }
960
961 /*
962 * If there is a specific "open" function (to register
963 * control line interrupts)
964 */
965 if (atmel_open_hook) {
966 retval = atmel_open_hook(port);
967 if (retval) {
968 free_irq(port->irq, port);
969 return retval;
970 }
971 }
972
973 /* Save current CSR for comparison in atmel_tasklet_func() */
974 atmel_port->irq_status_prev = UART_GET_CSR(port);
975 atmel_port->irq_status = atmel_port->irq_status_prev;
976
977 /*
978 * Finally, enable the serial port
979 */
980 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
981 /* enable xmit & rcvr */
982 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
983
984 if (atmel_use_dma_rx(port)) {
985 /* set UART timeout */
986 UART_PUT_RTOR(port, PDC_RX_TIMEOUT);
987 UART_PUT_CR(port, ATMEL_US_STTTO);
988
989 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
990 /* enable PDC controller */
991 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
992 } else {
993 /* enable receive only */
994 UART_PUT_IER(port, ATMEL_US_RXRDY);
995 }
996
997 return 0;
998}
999
1000/*
1001 * Disable the port
1002 */
1003static void atmel_shutdown(struct uart_port *port)
1004{
1005 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1006 /*
1007 * Ensure everything is stopped.
1008 */
1009 atmel_stop_rx(port);
1010 atmel_stop_tx(port);
1011
1012 /*
1013 * Shut-down the DMA.
1014 */
1015 if (atmel_use_dma_rx(port)) {
1016 int i;
1017
1018 for (i = 0; i < 2; i++) {
1019 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1020
1021 dma_unmap_single(port->dev,
1022 pdc->dma_addr,
1023 pdc->dma_size,
1024 DMA_FROM_DEVICE);
1025 kfree(pdc->buf);
1026 }
1027 }
1028 if (atmel_use_dma_tx(port)) {
1029 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1030
1031 dma_unmap_single(port->dev,
1032 pdc->dma_addr,
1033 pdc->dma_size,
1034 DMA_TO_DEVICE);
1035 }
1036
1037 /*
1038 * Disable all interrupts, port and break condition.
1039 */
1040 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1041 UART_PUT_IDR(port, -1);
1042
1043 /*
1044 * Free the interrupt
1045 */
1046 free_irq(port->irq, port);
1047
1048 /*
1049 * If there is a specific "close" function (to unregister
1050 * control line interrupts)
1051 */
1052 if (atmel_close_hook)
1053 atmel_close_hook(port);
1054}
1055
1056/*
1057 * Flush any TX data submitted for DMA. Called when the TX circular
1058 * buffer is reset.
1059 */
1060static void atmel_flush_buffer(struct uart_port *port)
1061{
1062 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1063
1064 if (atmel_use_dma_tx(port)) {
1065 UART_PUT_TCR(port, 0);
1066 atmel_port->pdc_tx.ofs = 0;
1067 }
1068}
1069
1070/*
1071 * Power / Clock management.
1072 */
1073static void atmel_serial_pm(struct uart_port *port, unsigned int state,
1074 unsigned int oldstate)
1075{
1076 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1077
1078 switch (state) {
1079 case 0:
1080 /*
1081 * Enable the peripheral clock for this serial port.
1082 * This is called on uart_open() or a resume event.
1083 */
1084 clk_enable(atmel_port->clk);
1085
1086 /* re-enable interrupts if we disabled some on suspend */
1087 UART_PUT_IER(port, atmel_port->backup_imr);
1088 break;
1089 case 3:
1090 /* Back up the interrupt mask and disable all interrupts */
1091 atmel_port->backup_imr = UART_GET_IMR(port);
1092 UART_PUT_IDR(port, -1);
1093
1094 /*
1095 * Disable the peripheral clock for this serial port.
1096 * This is called on uart_close() or a suspend event.
1097 */
1098 clk_disable(atmel_port->clk);
1099 break;
1100 default:
1101 printk(KERN_ERR "atmel_serial: unknown pm %d\n", state);
1102 }
1103}
1104
1105/*
1106 * Change the port parameters
1107 */
1108static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
1109 struct ktermios *old)
1110{
1111 unsigned long flags;
1112 unsigned int mode, imr, quot, baud;
1113 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1114
1115 /* Get current mode register */
1116 mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL
1117 | ATMEL_US_NBSTOP | ATMEL_US_PAR
1118 | ATMEL_US_USMODE);
1119
1120 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1121 quot = uart_get_divisor(port, baud);
1122
1123 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */
1124 quot /= 8;
1125 mode |= ATMEL_US_USCLKS_MCK_DIV8;
1126 }
1127
1128 /* byte size */
1129 switch (termios->c_cflag & CSIZE) {
1130 case CS5:
1131 mode |= ATMEL_US_CHRL_5;
1132 break;
1133 case CS6:
1134 mode |= ATMEL_US_CHRL_6;
1135 break;
1136 case CS7:
1137 mode |= ATMEL_US_CHRL_7;
1138 break;
1139 default:
1140 mode |= ATMEL_US_CHRL_8;
1141 break;
1142 }
1143
1144 /* stop bits */
1145 if (termios->c_cflag & CSTOPB)
1146 mode |= ATMEL_US_NBSTOP_2;
1147
1148 /* parity */
1149 if (termios->c_cflag & PARENB) {
1150 /* Mark or Space parity */
1151 if (termios->c_cflag & CMSPAR) {
1152 if (termios->c_cflag & PARODD)
1153 mode |= ATMEL_US_PAR_MARK;
1154 else
1155 mode |= ATMEL_US_PAR_SPACE;
1156 } else if (termios->c_cflag & PARODD)
1157 mode |= ATMEL_US_PAR_ODD;
1158 else
1159 mode |= ATMEL_US_PAR_EVEN;
1160 } else
1161 mode |= ATMEL_US_PAR_NONE;
1162
1163 /* hardware handshake (RTS/CTS) */
1164 if (termios->c_cflag & CRTSCTS)
1165 mode |= ATMEL_US_USMODE_HWHS;
1166 else
1167 mode |= ATMEL_US_USMODE_NORMAL;
1168
1169 spin_lock_irqsave(&port->lock, flags);
1170
1171 port->read_status_mask = ATMEL_US_OVRE;
1172 if (termios->c_iflag & INPCK)
1173 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1174 if (termios->c_iflag & (BRKINT | PARMRK))
1175 port->read_status_mask |= ATMEL_US_RXBRK;
1176
1177 if (atmel_use_dma_rx(port))
1178 /* need to enable error interrupts */
1179 UART_PUT_IER(port, port->read_status_mask);
1180
1181 /*
1182 * Characters to ignore
1183 */
1184 port->ignore_status_mask = 0;
1185 if (termios->c_iflag & IGNPAR)
1186 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1187 if (termios->c_iflag & IGNBRK) {
1188 port->ignore_status_mask |= ATMEL_US_RXBRK;
1189 /*
1190 * If we're ignoring parity and break indicators,
1191 * ignore overruns too (for real raw support).
1192 */
1193 if (termios->c_iflag & IGNPAR)
1194 port->ignore_status_mask |= ATMEL_US_OVRE;
1195 }
1196 /* TODO: Ignore all characters if CREAD is set.*/
1197
1198 /* update the per-port timeout */
1199 uart_update_timeout(port, termios->c_cflag, baud);
1200
1201 /*
1202 * save/disable interrupts. The tty layer will ensure that the
1203 * transmitter is empty if requested by the caller, so there's
1204 * no need to wait for it here.
1205 */
1206 imr = UART_GET_IMR(port);
1207 UART_PUT_IDR(port, -1);
1208
1209 /* disable receiver and transmitter */
1210 UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
1211
1212 /* Resetting serial mode to RS232 (0x0) */
1213 mode &= ~ATMEL_US_USMODE;
1214
1215 if (atmel_port->rs485.flags & SER_RS485_ENABLED) {
1216 dev_dbg(port->dev, "Setting UART to RS485\n");
1217 if (atmel_port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1218 UART_PUT_TTGR(port,
1219 atmel_port->rs485.delay_rts_after_send);
1220 mode |= ATMEL_US_USMODE_RS485;
1221 } else {
1222 dev_dbg(port->dev, "Setting UART to RS232\n");
1223 }
1224
1225 /* set the parity, stop bits and data size */
1226 UART_PUT_MR(port, mode);
1227
1228 /* set the baud rate */
1229 UART_PUT_BRGR(port, quot);
1230 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1231 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1232
1233 /* restore interrupts */
1234 UART_PUT_IER(port, imr);
1235
1236 /* CTS flow-control and modem-status interrupts */
1237 if (UART_ENABLE_MS(port, termios->c_cflag))
1238 port->ops->enable_ms(port);
1239
1240 spin_unlock_irqrestore(&port->lock, flags);
1241}
1242
1243/*
1244 * Return string describing the specified port
1245 */
1246static const char *atmel_type(struct uart_port *port)
1247{
1248 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
1249}
1250
1251/*
1252 * Release the memory region(s) being used by 'port'.
1253 */
1254static void atmel_release_port(struct uart_port *port)
1255{
1256 struct platform_device *pdev = to_platform_device(port->dev);
1257 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
1258
1259 release_mem_region(port->mapbase, size);
1260
1261 if (port->flags & UPF_IOREMAP) {
1262 iounmap(port->membase);
1263 port->membase = NULL;
1264 }
1265}
1266
1267/*
1268 * Request the memory region(s) being used by 'port'.
1269 */
1270static int atmel_request_port(struct uart_port *port)
1271{
1272 struct platform_device *pdev = to_platform_device(port->dev);
1273 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
1274
1275 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
1276 return -EBUSY;
1277
1278 if (port->flags & UPF_IOREMAP) {
1279 port->membase = ioremap(port->mapbase, size);
1280 if (port->membase == NULL) {
1281 release_mem_region(port->mapbase, size);
1282 return -ENOMEM;
1283 }
1284 }
1285
1286 return 0;
1287}
1288
1289/*
1290 * Configure/autoconfigure the port.
1291 */
1292static void atmel_config_port(struct uart_port *port, int flags)
1293{
1294 if (flags & UART_CONFIG_TYPE) {
1295 port->type = PORT_ATMEL;
1296 atmel_request_port(port);
1297 }
1298}
1299
1300/*
1301 * Verify the new serial_struct (for TIOCSSERIAL).
1302 */
1303static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
1304{
1305 int ret = 0;
1306 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
1307 ret = -EINVAL;
1308 if (port->irq != ser->irq)
1309 ret = -EINVAL;
1310 if (ser->io_type != SERIAL_IO_MEM)
1311 ret = -EINVAL;
1312 if (port->uartclk / 16 != ser->baud_base)
1313 ret = -EINVAL;
1314 if ((void *)port->mapbase != ser->iomem_base)
1315 ret = -EINVAL;
1316 if (port->iobase != ser->port)
1317 ret = -EINVAL;
1318 if (ser->hub6 != 0)
1319 ret = -EINVAL;
1320 return ret;
1321}
1322
1323#ifdef CONFIG_CONSOLE_POLL
1324static int atmel_poll_get_char(struct uart_port *port)
1325{
1326 while (!(UART_GET_CSR(port) & ATMEL_US_RXRDY))
1327 cpu_relax();
1328
1329 return UART_GET_CHAR(port);
1330}
1331
1332static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
1333{
1334 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY))
1335 cpu_relax();
1336
1337 UART_PUT_CHAR(port, ch);
1338}
1339#endif
1340
1341static int
1342atmel_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg)
1343{
1344 struct serial_rs485 rs485conf;
1345
1346 switch (cmd) {
1347 case TIOCSRS485:
1348 if (copy_from_user(&rs485conf, (struct serial_rs485 *) arg,
1349 sizeof(rs485conf)))
1350 return -EFAULT;
1351
1352 atmel_config_rs485(port, &rs485conf);
1353 break;
1354
1355 case TIOCGRS485:
1356 if (copy_to_user((struct serial_rs485 *) arg,
1357 &(to_atmel_uart_port(port)->rs485),
1358 sizeof(rs485conf)))
1359 return -EFAULT;
1360 break;
1361
1362 default:
1363 return -ENOIOCTLCMD;
1364 }
1365 return 0;
1366}
1367
1368
1369
1370static struct uart_ops atmel_pops = {
1371 .tx_empty = atmel_tx_empty,
1372 .set_mctrl = atmel_set_mctrl,
1373 .get_mctrl = atmel_get_mctrl,
1374 .stop_tx = atmel_stop_tx,
1375 .start_tx = atmel_start_tx,
1376 .stop_rx = atmel_stop_rx,
1377 .enable_ms = atmel_enable_ms,
1378 .break_ctl = atmel_break_ctl,
1379 .startup = atmel_startup,
1380 .shutdown = atmel_shutdown,
1381 .flush_buffer = atmel_flush_buffer,
1382 .set_termios = atmel_set_termios,
1383 .type = atmel_type,
1384 .release_port = atmel_release_port,
1385 .request_port = atmel_request_port,
1386 .config_port = atmel_config_port,
1387 .verify_port = atmel_verify_port,
1388 .pm = atmel_serial_pm,
1389 .ioctl = atmel_ioctl,
1390#ifdef CONFIG_CONSOLE_POLL
1391 .poll_get_char = atmel_poll_get_char,
1392 .poll_put_char = atmel_poll_put_char,
1393#endif
1394};
1395
1396/*
1397 * Configure the port from the platform device resource info.
1398 */
1399static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port,
1400 struct platform_device *pdev)
1401{
1402 struct uart_port *port = &atmel_port->uart;
1403 struct atmel_uart_data *data = pdev->dev.platform_data;
1404
1405 port->iotype = UPIO_MEM;
1406 port->flags = UPF_BOOT_AUTOCONF;
1407 port->ops = &atmel_pops;
1408 port->fifosize = 1;
1409 port->line = pdev->id;
1410 port->dev = &pdev->dev;
1411 port->mapbase = pdev->resource[0].start;
1412 port->irq = pdev->resource[1].start;
1413
1414 tasklet_init(&atmel_port->tasklet, atmel_tasklet_func,
1415 (unsigned long)port);
1416
1417 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
1418
1419 if (data->regs)
1420 /* Already mapped by setup code */
1421 port->membase = data->regs;
1422 else {
1423 port->flags |= UPF_IOREMAP;
1424 port->membase = NULL;
1425 }
1426
1427 /* for console, the clock could already be configured */
1428 if (!atmel_port->clk) {
1429 atmel_port->clk = clk_get(&pdev->dev, "usart");
1430 clk_enable(atmel_port->clk);
1431 port->uartclk = clk_get_rate(atmel_port->clk);
1432 clk_disable(atmel_port->clk);
1433 /* only enable clock when USART is in use */
1434 }
1435
1436 atmel_port->use_dma_rx = data->use_dma_rx;
1437 atmel_port->use_dma_tx = data->use_dma_tx;
1438 atmel_port->rs485 = data->rs485;
1439 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
1440 if (atmel_port->rs485.flags & SER_RS485_ENABLED)
1441 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
1442 else if (atmel_use_dma_tx(port)) {
1443 port->fifosize = PDC_BUFFER_SIZE;
1444 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
1445 } else {
1446 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
1447 }
1448}
1449
1450/*
1451 * Register board-specific modem-control line handlers.
1452 */
1453void __init atmel_register_uart_fns(struct atmel_port_fns *fns)
1454{
1455 if (fns->enable_ms)
1456 atmel_pops.enable_ms = fns->enable_ms;
1457 if (fns->get_mctrl)
1458 atmel_pops.get_mctrl = fns->get_mctrl;
1459 if (fns->set_mctrl)
1460 atmel_pops.set_mctrl = fns->set_mctrl;
1461 atmel_open_hook = fns->open;
1462 atmel_close_hook = fns->close;
1463 atmel_pops.pm = fns->pm;
1464 atmel_pops.set_wake = fns->set_wake;
1465}
1466
1467#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
1468static void atmel_console_putchar(struct uart_port *port, int ch)
1469{
1470 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY))
1471 cpu_relax();
1472 UART_PUT_CHAR(port, ch);
1473}
1474
1475/*
1476 * Interrupts are disabled on entering
1477 */
1478static void atmel_console_write(struct console *co, const char *s, u_int count)
1479{
1480 struct uart_port *port = &atmel_ports[co->index].uart;
1481 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1482 unsigned int status, imr;
1483 unsigned int pdc_tx;
1484
1485 /*
1486 * First, save IMR and then disable interrupts
1487 */
1488 imr = UART_GET_IMR(port);
1489 UART_PUT_IDR(port, ATMEL_US_RXRDY | atmel_port->tx_done_mask);
1490
1491 /* Store PDC transmit status and disable it */
1492 pdc_tx = UART_GET_PTSR(port) & ATMEL_PDC_TXTEN;
1493 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
1494
1495 uart_console_write(port, s, count, atmel_console_putchar);
1496
1497 /*
1498 * Finally, wait for transmitter to become empty
1499 * and restore IMR
1500 */
1501 do {
1502 status = UART_GET_CSR(port);
1503 } while (!(status & ATMEL_US_TXRDY));
1504
1505 /* Restore PDC transmit status */
1506 if (pdc_tx)
1507 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
1508
1509 /* set interrupts back the way they were */
1510 UART_PUT_IER(port, imr);
1511}
1512
1513/*
1514 * If the port was already initialised (eg, by a boot loader),
1515 * try to determine the current setup.
1516 */
1517static void __init atmel_console_get_options(struct uart_port *port, int *baud,
1518 int *parity, int *bits)
1519{
1520 unsigned int mr, quot;
1521
1522 /*
1523 * If the baud rate generator isn't running, the port wasn't
1524 * initialized by the boot loader.
1525 */
1526 quot = UART_GET_BRGR(port) & ATMEL_US_CD;
1527 if (!quot)
1528 return;
1529
1530 mr = UART_GET_MR(port) & ATMEL_US_CHRL;
1531 if (mr == ATMEL_US_CHRL_8)
1532 *bits = 8;
1533 else
1534 *bits = 7;
1535
1536 mr = UART_GET_MR(port) & ATMEL_US_PAR;
1537 if (mr == ATMEL_US_PAR_EVEN)
1538 *parity = 'e';
1539 else if (mr == ATMEL_US_PAR_ODD)
1540 *parity = 'o';
1541
1542 /*
1543 * The serial core only rounds down when matching this to a
1544 * supported baud rate. Make sure we don't end up slightly
1545 * lower than one of those, as it would make us fall through
1546 * to a much lower baud rate than we really want.
1547 */
1548 *baud = port->uartclk / (16 * (quot - 1));
1549}
1550
1551static int __init atmel_console_setup(struct console *co, char *options)
1552{
1553 struct uart_port *port = &atmel_ports[co->index].uart;
1554 int baud = 115200;
1555 int bits = 8;
1556 int parity = 'n';
1557 int flow = 'n';
1558
1559 if (port->membase == NULL) {
1560 /* Port not initialized yet - delay setup */
1561 return -ENODEV;
1562 }
1563
1564 clk_enable(atmel_ports[co->index].clk);
1565
1566 UART_PUT_IDR(port, -1);
1567 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1568 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1569
1570 if (options)
1571 uart_parse_options(options, &baud, &parity, &bits, &flow);
1572 else
1573 atmel_console_get_options(port, &baud, &parity, &bits);
1574
1575 return uart_set_options(port, co, baud, parity, bits, flow);
1576}
1577
1578static struct uart_driver atmel_uart;
1579
1580static struct console atmel_console = {
1581 .name = ATMEL_DEVICENAME,
1582 .write = atmel_console_write,
1583 .device = uart_console_device,
1584 .setup = atmel_console_setup,
1585 .flags = CON_PRINTBUFFER,
1586 .index = -1,
1587 .data = &atmel_uart,
1588};
1589
1590#define ATMEL_CONSOLE_DEVICE (&atmel_console)
1591
1592/*
1593 * Early console initialization (before VM subsystem initialized).
1594 */
1595static int __init atmel_console_init(void)
1596{
1597 if (atmel_default_console_device) {
1598 add_preferred_console(ATMEL_DEVICENAME,
1599 atmel_default_console_device->id, NULL);
1600 atmel_init_port(&atmel_ports[atmel_default_console_device->id],
1601 atmel_default_console_device);
1602 register_console(&atmel_console);
1603 }
1604
1605 return 0;
1606}
1607
1608console_initcall(atmel_console_init);
1609
1610/*
1611 * Late console initialization.
1612 */
1613static int __init atmel_late_console_init(void)
1614{
1615 if (atmel_default_console_device
1616 && !(atmel_console.flags & CON_ENABLED))
1617 register_console(&atmel_console);
1618
1619 return 0;
1620}
1621
1622core_initcall(atmel_late_console_init);
1623
1624static inline bool atmel_is_console_port(struct uart_port *port)
1625{
1626 return port->cons && port->cons->index == port->line;
1627}
1628
1629#else
1630#define ATMEL_CONSOLE_DEVICE NULL
1631
1632static inline bool atmel_is_console_port(struct uart_port *port)
1633{
1634 return false;
1635}
1636#endif
1637
1638static struct uart_driver atmel_uart = {
1639 .owner = THIS_MODULE,
1640 .driver_name = "atmel_serial",
1641 .dev_name = ATMEL_DEVICENAME,
1642 .major = SERIAL_ATMEL_MAJOR,
1643 .minor = MINOR_START,
1644 .nr = ATMEL_MAX_UART,
1645 .cons = ATMEL_CONSOLE_DEVICE,
1646};
1647
1648#ifdef CONFIG_PM
1649static bool atmel_serial_clk_will_stop(void)
1650{
1651#ifdef CONFIG_ARCH_AT91
1652 return at91_suspend_entering_slow_clock();
1653#else
1654 return false;
1655#endif
1656}
1657
1658static int atmel_serial_suspend(struct platform_device *pdev,
1659 pm_message_t state)
1660{
1661 struct uart_port *port = platform_get_drvdata(pdev);
1662 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1663
1664 if (atmel_is_console_port(port) && console_suspend_enabled) {
1665 /* Drain the TX shifter */
1666 while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY))
1667 cpu_relax();
1668 }
1669
1670 /* we can not wake up if we're running on slow clock */
1671 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
1672 if (atmel_serial_clk_will_stop())
1673 device_set_wakeup_enable(&pdev->dev, 0);
1674
1675 uart_suspend_port(&atmel_uart, port);
1676
1677 return 0;
1678}
1679
1680static int atmel_serial_resume(struct platform_device *pdev)
1681{
1682 struct uart_port *port = platform_get_drvdata(pdev);
1683 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1684
1685 uart_resume_port(&atmel_uart, port);
1686 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
1687
1688 return 0;
1689}
1690#else
1691#define atmel_serial_suspend NULL
1692#define atmel_serial_resume NULL
1693#endif
1694
1695static int __devinit atmel_serial_probe(struct platform_device *pdev)
1696{
1697 struct atmel_uart_port *port;
1698 void *data;
1699 int ret;
1700
1701 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
1702
1703 port = &atmel_ports[pdev->id];
1704 port->backup_imr = 0;
1705
1706 atmel_init_port(port, pdev);
1707
1708 if (!atmel_use_dma_rx(&port->uart)) {
1709 ret = -ENOMEM;
1710 data = kmalloc(sizeof(struct atmel_uart_char)
1711 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
1712 if (!data)
1713 goto err_alloc_ring;
1714 port->rx_ring.buf = data;
1715 }
1716
1717 ret = uart_add_one_port(&atmel_uart, &port->uart);
1718 if (ret)
1719 goto err_add_port;
1720
1721#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
1722 if (atmel_is_console_port(&port->uart)
1723 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
1724 /*
1725 * The serial core enabled the clock for us, so undo
1726 * the clk_enable() in atmel_console_setup()
1727 */
1728 clk_disable(port->clk);
1729 }
1730#endif
1731
1732 device_init_wakeup(&pdev->dev, 1);
1733 platform_set_drvdata(pdev, port);
1734
1735 return 0;
1736
1737err_add_port:
1738 kfree(port->rx_ring.buf);
1739 port->rx_ring.buf = NULL;
1740err_alloc_ring:
1741 if (!atmel_is_console_port(&port->uart)) {
1742 clk_put(port->clk);
1743 port->clk = NULL;
1744 }
1745
1746 return ret;
1747}
1748
1749static int __devexit atmel_serial_remove(struct platform_device *pdev)
1750{
1751 struct uart_port *port = platform_get_drvdata(pdev);
1752 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1753 int ret = 0;
1754
1755 device_init_wakeup(&pdev->dev, 0);
1756 platform_set_drvdata(pdev, NULL);
1757
1758 ret = uart_remove_one_port(&atmel_uart, port);
1759
1760 tasklet_kill(&atmel_port->tasklet);
1761 kfree(atmel_port->rx_ring.buf);
1762
1763 /* "port" is allocated statically, so we shouldn't free it */
1764
1765 clk_put(atmel_port->clk);
1766
1767 return ret;
1768}
1769
1770static struct platform_driver atmel_serial_driver = {
1771 .probe = atmel_serial_probe,
1772 .remove = __devexit_p(atmel_serial_remove),
1773 .suspend = atmel_serial_suspend,
1774 .resume = atmel_serial_resume,
1775 .driver = {
1776 .name = "atmel_usart",
1777 .owner = THIS_MODULE,
1778 },
1779};
1780
1781static int __init atmel_serial_init(void)
1782{
1783 int ret;
1784
1785 ret = uart_register_driver(&atmel_uart);
1786 if (ret)
1787 return ret;
1788
1789 ret = platform_driver_register(&atmel_serial_driver);
1790 if (ret)
1791 uart_unregister_driver(&atmel_uart);
1792
1793 return ret;
1794}
1795
1796static void __exit atmel_serial_exit(void)
1797{
1798 platform_driver_unregister(&atmel_serial_driver);
1799 uart_unregister_driver(&atmel_uart);
1800}
1801
1802module_init(atmel_serial_init);
1803module_exit(atmel_serial_exit);
1804
1805MODULE_AUTHOR("Rick Bronson");
1806MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver");
1807MODULE_LICENSE("GPL");
1808MODULE_ALIAS("platform:atmel_usart");
diff --git a/drivers/serial/bcm63xx_uart.c b/drivers/serial/bcm63xx_uart.c
deleted file mode 100644
index a1a0e55d0807..000000000000
--- a/drivers/serial/bcm63xx_uart.c
+++ /dev/null
@@ -1,891 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Derived from many drivers using generic_serial interface.
7 *
8 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
9 *
10 * Serial driver for BCM63xx integrated UART.
11 *
12 * Hardware flow control was _not_ tested since I only have RX/TX on
13 * my board.
14 */
15
16#if defined(CONFIG_SERIAL_BCM63XX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
17#define SUPPORT_SYSRQ
18#endif
19
20#include <linux/kernel.h>
21#include <linux/platform_device.h>
22#include <linux/init.h>
23#include <linux/delay.h>
24#include <linux/module.h>
25#include <linux/console.h>
26#include <linux/clk.h>
27#include <linux/tty.h>
28#include <linux/tty_flip.h>
29#include <linux/sysrq.h>
30#include <linux/serial.h>
31#include <linux/serial_core.h>
32
33#include <bcm63xx_clk.h>
34#include <bcm63xx_irq.h>
35#include <bcm63xx_regs.h>
36#include <bcm63xx_io.h>
37
38#define BCM63XX_NR_UARTS 2
39
40static struct uart_port ports[BCM63XX_NR_UARTS];
41
42/*
43 * rx interrupt mask / stat
44 *
45 * mask:
46 * - rx fifo full
47 * - rx fifo above threshold
48 * - rx fifo not empty for too long
49 */
50#define UART_RX_INT_MASK (UART_IR_MASK(UART_IR_RXOVER) | \
51 UART_IR_MASK(UART_IR_RXTHRESH) | \
52 UART_IR_MASK(UART_IR_RXTIMEOUT))
53
54#define UART_RX_INT_STAT (UART_IR_STAT(UART_IR_RXOVER) | \
55 UART_IR_STAT(UART_IR_RXTHRESH) | \
56 UART_IR_STAT(UART_IR_RXTIMEOUT))
57
58/*
59 * tx interrupt mask / stat
60 *
61 * mask:
62 * - tx fifo empty
63 * - tx fifo below threshold
64 */
65#define UART_TX_INT_MASK (UART_IR_MASK(UART_IR_TXEMPTY) | \
66 UART_IR_MASK(UART_IR_TXTRESH))
67
68#define UART_TX_INT_STAT (UART_IR_STAT(UART_IR_TXEMPTY) | \
69 UART_IR_STAT(UART_IR_TXTRESH))
70
71/*
72 * external input interrupt
73 *
74 * mask: any edge on CTS, DCD
75 */
76#define UART_EXTINP_INT_MASK (UART_EXTINP_IRMASK(UART_EXTINP_IR_CTS) | \
77 UART_EXTINP_IRMASK(UART_EXTINP_IR_DCD))
78
79/*
80 * handy uart register accessor
81 */
82static inline unsigned int bcm_uart_readl(struct uart_port *port,
83 unsigned int offset)
84{
85 return bcm_readl(port->membase + offset);
86}
87
88static inline void bcm_uart_writel(struct uart_port *port,
89 unsigned int value, unsigned int offset)
90{
91 bcm_writel(value, port->membase + offset);
92}
93
94/*
95 * serial core request to check if uart tx fifo is empty
96 */
97static unsigned int bcm_uart_tx_empty(struct uart_port *port)
98{
99 unsigned int val;
100
101 val = bcm_uart_readl(port, UART_IR_REG);
102 return (val & UART_IR_STAT(UART_IR_TXEMPTY)) ? 1 : 0;
103}
104
105/*
106 * serial core request to set RTS and DTR pin state and loopback mode
107 */
108static void bcm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
109{
110 unsigned int val;
111
112 val = bcm_uart_readl(port, UART_MCTL_REG);
113 val &= ~(UART_MCTL_DTR_MASK | UART_MCTL_RTS_MASK);
114 /* invert of written value is reflected on the pin */
115 if (!(mctrl & TIOCM_DTR))
116 val |= UART_MCTL_DTR_MASK;
117 if (!(mctrl & TIOCM_RTS))
118 val |= UART_MCTL_RTS_MASK;
119 bcm_uart_writel(port, val, UART_MCTL_REG);
120
121 val = bcm_uart_readl(port, UART_CTL_REG);
122 if (mctrl & TIOCM_LOOP)
123 val |= UART_CTL_LOOPBACK_MASK;
124 else
125 val &= ~UART_CTL_LOOPBACK_MASK;
126 bcm_uart_writel(port, val, UART_CTL_REG);
127}
128
129/*
130 * serial core request to return RI, CTS, DCD and DSR pin state
131 */
132static unsigned int bcm_uart_get_mctrl(struct uart_port *port)
133{
134 unsigned int val, mctrl;
135
136 mctrl = 0;
137 val = bcm_uart_readl(port, UART_EXTINP_REG);
138 if (val & UART_EXTINP_RI_MASK)
139 mctrl |= TIOCM_RI;
140 if (val & UART_EXTINP_CTS_MASK)
141 mctrl |= TIOCM_CTS;
142 if (val & UART_EXTINP_DCD_MASK)
143 mctrl |= TIOCM_CD;
144 if (val & UART_EXTINP_DSR_MASK)
145 mctrl |= TIOCM_DSR;
146 return mctrl;
147}
148
149/*
150 * serial core request to disable tx ASAP (used for flow control)
151 */
152static void bcm_uart_stop_tx(struct uart_port *port)
153{
154 unsigned int val;
155
156 val = bcm_uart_readl(port, UART_CTL_REG);
157 val &= ~(UART_CTL_TXEN_MASK);
158 bcm_uart_writel(port, val, UART_CTL_REG);
159
160 val = bcm_uart_readl(port, UART_IR_REG);
161 val &= ~UART_TX_INT_MASK;
162 bcm_uart_writel(port, val, UART_IR_REG);
163}
164
165/*
166 * serial core request to (re)enable tx
167 */
168static void bcm_uart_start_tx(struct uart_port *port)
169{
170 unsigned int val;
171
172 val = bcm_uart_readl(port, UART_IR_REG);
173 val |= UART_TX_INT_MASK;
174 bcm_uart_writel(port, val, UART_IR_REG);
175
176 val = bcm_uart_readl(port, UART_CTL_REG);
177 val |= UART_CTL_TXEN_MASK;
178 bcm_uart_writel(port, val, UART_CTL_REG);
179}
180
181/*
182 * serial core request to stop rx, called before port shutdown
183 */
184static void bcm_uart_stop_rx(struct uart_port *port)
185{
186 unsigned int val;
187
188 val = bcm_uart_readl(port, UART_IR_REG);
189 val &= ~UART_RX_INT_MASK;
190 bcm_uart_writel(port, val, UART_IR_REG);
191}
192
193/*
194 * serial core request to enable modem status interrupt reporting
195 */
196static void bcm_uart_enable_ms(struct uart_port *port)
197{
198 unsigned int val;
199
200 val = bcm_uart_readl(port, UART_IR_REG);
201 val |= UART_IR_MASK(UART_IR_EXTIP);
202 bcm_uart_writel(port, val, UART_IR_REG);
203}
204
205/*
206 * serial core request to start/stop emitting break char
207 */
208static void bcm_uart_break_ctl(struct uart_port *port, int ctl)
209{
210 unsigned long flags;
211 unsigned int val;
212
213 spin_lock_irqsave(&port->lock, flags);
214
215 val = bcm_uart_readl(port, UART_CTL_REG);
216 if (ctl)
217 val |= UART_CTL_XMITBRK_MASK;
218 else
219 val &= ~UART_CTL_XMITBRK_MASK;
220 bcm_uart_writel(port, val, UART_CTL_REG);
221
222 spin_unlock_irqrestore(&port->lock, flags);
223}
224
225/*
226 * return port type in string format
227 */
228static const char *bcm_uart_type(struct uart_port *port)
229{
230 return (port->type == PORT_BCM63XX) ? "bcm63xx_uart" : NULL;
231}
232
233/*
234 * read all chars in rx fifo and send them to core
235 */
236static void bcm_uart_do_rx(struct uart_port *port)
237{
238 struct tty_struct *tty;
239 unsigned int max_count;
240
241 /* limit number of char read in interrupt, should not be
242 * higher than fifo size anyway since we're much faster than
243 * serial port */
244 max_count = 32;
245 tty = port->state->port.tty;
246 do {
247 unsigned int iestat, c, cstat;
248 char flag;
249
250 /* get overrun/fifo empty information from ier
251 * register */
252 iestat = bcm_uart_readl(port, UART_IR_REG);
253 if (!(iestat & UART_IR_STAT(UART_IR_RXNOTEMPTY)))
254 break;
255
256 cstat = c = bcm_uart_readl(port, UART_FIFO_REG);
257 port->icount.rx++;
258 flag = TTY_NORMAL;
259 c &= 0xff;
260
261 if (unlikely((cstat & UART_FIFO_ANYERR_MASK))) {
262 /* do stats first */
263 if (cstat & UART_FIFO_BRKDET_MASK) {
264 port->icount.brk++;
265 if (uart_handle_break(port))
266 continue;
267 }
268
269 if (cstat & UART_FIFO_PARERR_MASK)
270 port->icount.parity++;
271 if (cstat & UART_FIFO_FRAMEERR_MASK)
272 port->icount.frame++;
273
274 /* update flag wrt read_status_mask */
275 cstat &= port->read_status_mask;
276 if (cstat & UART_FIFO_BRKDET_MASK)
277 flag = TTY_BREAK;
278 if (cstat & UART_FIFO_FRAMEERR_MASK)
279 flag = TTY_FRAME;
280 if (cstat & UART_FIFO_PARERR_MASK)
281 flag = TTY_PARITY;
282 }
283
284 if (uart_handle_sysrq_char(port, c))
285 continue;
286
287 if (unlikely(iestat & UART_IR_STAT(UART_IR_RXOVER))) {
288 port->icount.overrun++;
289 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
290 }
291
292 if ((cstat & port->ignore_status_mask) == 0)
293 tty_insert_flip_char(tty, c, flag);
294
295 } while (--max_count);
296
297 tty_flip_buffer_push(tty);
298}
299
300/*
301 * fill tx fifo with chars to send, stop when fifo is about to be full
302 * or when all chars have been sent.
303 */
304static void bcm_uart_do_tx(struct uart_port *port)
305{
306 struct circ_buf *xmit;
307 unsigned int val, max_count;
308
309 if (port->x_char) {
310 bcm_uart_writel(port, port->x_char, UART_FIFO_REG);
311 port->icount.tx++;
312 port->x_char = 0;
313 return;
314 }
315
316 if (uart_tx_stopped(port)) {
317 bcm_uart_stop_tx(port);
318 return;
319 }
320
321 xmit = &port->state->xmit;
322 if (uart_circ_empty(xmit))
323 goto txq_empty;
324
325 val = bcm_uart_readl(port, UART_MCTL_REG);
326 val = (val & UART_MCTL_TXFIFOFILL_MASK) >> UART_MCTL_TXFIFOFILL_SHIFT;
327 max_count = port->fifosize - val;
328
329 while (max_count--) {
330 unsigned int c;
331
332 c = xmit->buf[xmit->tail];
333 bcm_uart_writel(port, c, UART_FIFO_REG);
334 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
335 port->icount.tx++;
336 if (uart_circ_empty(xmit))
337 break;
338 }
339
340 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
341 uart_write_wakeup(port);
342
343 if (uart_circ_empty(xmit))
344 goto txq_empty;
345 return;
346
347txq_empty:
348 /* nothing to send, disable transmit interrupt */
349 val = bcm_uart_readl(port, UART_IR_REG);
350 val &= ~UART_TX_INT_MASK;
351 bcm_uart_writel(port, val, UART_IR_REG);
352 return;
353}
354
355/*
356 * process uart interrupt
357 */
358static irqreturn_t bcm_uart_interrupt(int irq, void *dev_id)
359{
360 struct uart_port *port;
361 unsigned int irqstat;
362
363 port = dev_id;
364 spin_lock(&port->lock);
365
366 irqstat = bcm_uart_readl(port, UART_IR_REG);
367 if (irqstat & UART_RX_INT_STAT)
368 bcm_uart_do_rx(port);
369
370 if (irqstat & UART_TX_INT_STAT)
371 bcm_uart_do_tx(port);
372
373 if (irqstat & UART_IR_MASK(UART_IR_EXTIP)) {
374 unsigned int estat;
375
376 estat = bcm_uart_readl(port, UART_EXTINP_REG);
377 if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_CTS))
378 uart_handle_cts_change(port,
379 estat & UART_EXTINP_CTS_MASK);
380 if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_DCD))
381 uart_handle_dcd_change(port,
382 estat & UART_EXTINP_DCD_MASK);
383 }
384
385 spin_unlock(&port->lock);
386 return IRQ_HANDLED;
387}
388
389/*
390 * enable rx & tx operation on uart
391 */
392static void bcm_uart_enable(struct uart_port *port)
393{
394 unsigned int val;
395
396 val = bcm_uart_readl(port, UART_CTL_REG);
397 val |= (UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
398 bcm_uart_writel(port, val, UART_CTL_REG);
399}
400
401/*
402 * disable rx & tx operation on uart
403 */
404static void bcm_uart_disable(struct uart_port *port)
405{
406 unsigned int val;
407
408 val = bcm_uart_readl(port, UART_CTL_REG);
409 val &= ~(UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK |
410 UART_CTL_RXEN_MASK);
411 bcm_uart_writel(port, val, UART_CTL_REG);
412}
413
414/*
415 * clear all unread data in rx fifo and unsent data in tx fifo
416 */
417static void bcm_uart_flush(struct uart_port *port)
418{
419 unsigned int val;
420
421 /* empty rx and tx fifo */
422 val = bcm_uart_readl(port, UART_CTL_REG);
423 val |= UART_CTL_RSTRXFIFO_MASK | UART_CTL_RSTTXFIFO_MASK;
424 bcm_uart_writel(port, val, UART_CTL_REG);
425
426 /* read any pending char to make sure all irq status are
427 * cleared */
428 (void)bcm_uart_readl(port, UART_FIFO_REG);
429}
430
431/*
432 * serial core request to initialize uart and start rx operation
433 */
434static int bcm_uart_startup(struct uart_port *port)
435{
436 unsigned int val;
437 int ret;
438
439 /* mask all irq and flush port */
440 bcm_uart_disable(port);
441 bcm_uart_writel(port, 0, UART_IR_REG);
442 bcm_uart_flush(port);
443
444 /* clear any pending external input interrupt */
445 (void)bcm_uart_readl(port, UART_EXTINP_REG);
446
447 /* set rx/tx fifo thresh to fifo half size */
448 val = bcm_uart_readl(port, UART_MCTL_REG);
449 val &= ~(UART_MCTL_RXFIFOTHRESH_MASK | UART_MCTL_TXFIFOTHRESH_MASK);
450 val |= (port->fifosize / 2) << UART_MCTL_RXFIFOTHRESH_SHIFT;
451 val |= (port->fifosize / 2) << UART_MCTL_TXFIFOTHRESH_SHIFT;
452 bcm_uart_writel(port, val, UART_MCTL_REG);
453
454 /* set rx fifo timeout to 1 char time */
455 val = bcm_uart_readl(port, UART_CTL_REG);
456 val &= ~UART_CTL_RXTMOUTCNT_MASK;
457 val |= 1 << UART_CTL_RXTMOUTCNT_SHIFT;
458 bcm_uart_writel(port, val, UART_CTL_REG);
459
460 /* report any edge on dcd and cts */
461 val = UART_EXTINP_INT_MASK;
462 val |= UART_EXTINP_DCD_NOSENSE_MASK;
463 val |= UART_EXTINP_CTS_NOSENSE_MASK;
464 bcm_uart_writel(port, val, UART_EXTINP_REG);
465
466 /* register irq and enable rx interrupts */
467 ret = request_irq(port->irq, bcm_uart_interrupt, 0,
468 bcm_uart_type(port), port);
469 if (ret)
470 return ret;
471 bcm_uart_writel(port, UART_RX_INT_MASK, UART_IR_REG);
472 bcm_uart_enable(port);
473 return 0;
474}
475
476/*
477 * serial core request to flush & disable uart
478 */
479static void bcm_uart_shutdown(struct uart_port *port)
480{
481 unsigned long flags;
482
483 spin_lock_irqsave(&port->lock, flags);
484 bcm_uart_writel(port, 0, UART_IR_REG);
485 spin_unlock_irqrestore(&port->lock, flags);
486
487 bcm_uart_disable(port);
488 bcm_uart_flush(port);
489 free_irq(port->irq, port);
490}
491
492/*
493 * serial core request to change current uart setting
494 */
495static void bcm_uart_set_termios(struct uart_port *port,
496 struct ktermios *new,
497 struct ktermios *old)
498{
499 unsigned int ctl, baud, quot, ier;
500 unsigned long flags;
501
502 spin_lock_irqsave(&port->lock, flags);
503
504 /* disable uart while changing speed */
505 bcm_uart_disable(port);
506 bcm_uart_flush(port);
507
508 /* update Control register */
509 ctl = bcm_uart_readl(port, UART_CTL_REG);
510 ctl &= ~UART_CTL_BITSPERSYM_MASK;
511
512 switch (new->c_cflag & CSIZE) {
513 case CS5:
514 ctl |= (0 << UART_CTL_BITSPERSYM_SHIFT);
515 break;
516 case CS6:
517 ctl |= (1 << UART_CTL_BITSPERSYM_SHIFT);
518 break;
519 case CS7:
520 ctl |= (2 << UART_CTL_BITSPERSYM_SHIFT);
521 break;
522 default:
523 ctl |= (3 << UART_CTL_BITSPERSYM_SHIFT);
524 break;
525 }
526
527 ctl &= ~UART_CTL_STOPBITS_MASK;
528 if (new->c_cflag & CSTOPB)
529 ctl |= UART_CTL_STOPBITS_2;
530 else
531 ctl |= UART_CTL_STOPBITS_1;
532
533 ctl &= ~(UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK);
534 if (new->c_cflag & PARENB)
535 ctl |= (UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK);
536 ctl &= ~(UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK);
537 if (new->c_cflag & PARODD)
538 ctl |= (UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK);
539 bcm_uart_writel(port, ctl, UART_CTL_REG);
540
541 /* update Baudword register */
542 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
543 quot = uart_get_divisor(port, baud) - 1;
544 bcm_uart_writel(port, quot, UART_BAUD_REG);
545
546 /* update Interrupt register */
547 ier = bcm_uart_readl(port, UART_IR_REG);
548
549 ier &= ~UART_IR_MASK(UART_IR_EXTIP);
550 if (UART_ENABLE_MS(port, new->c_cflag))
551 ier |= UART_IR_MASK(UART_IR_EXTIP);
552
553 bcm_uart_writel(port, ier, UART_IR_REG);
554
555 /* update read/ignore mask */
556 port->read_status_mask = UART_FIFO_VALID_MASK;
557 if (new->c_iflag & INPCK) {
558 port->read_status_mask |= UART_FIFO_FRAMEERR_MASK;
559 port->read_status_mask |= UART_FIFO_PARERR_MASK;
560 }
561 if (new->c_iflag & (BRKINT))
562 port->read_status_mask |= UART_FIFO_BRKDET_MASK;
563
564 port->ignore_status_mask = 0;
565 if (new->c_iflag & IGNPAR)
566 port->ignore_status_mask |= UART_FIFO_PARERR_MASK;
567 if (new->c_iflag & IGNBRK)
568 port->ignore_status_mask |= UART_FIFO_BRKDET_MASK;
569 if (!(new->c_cflag & CREAD))
570 port->ignore_status_mask |= UART_FIFO_VALID_MASK;
571
572 uart_update_timeout(port, new->c_cflag, baud);
573 bcm_uart_enable(port);
574 spin_unlock_irqrestore(&port->lock, flags);
575}
576
577/*
578 * serial core request to claim uart iomem
579 */
580static int bcm_uart_request_port(struct uart_port *port)
581{
582 unsigned int size;
583
584 size = RSET_UART_SIZE;
585 if (!request_mem_region(port->mapbase, size, "bcm63xx")) {
586 dev_err(port->dev, "Memory region busy\n");
587 return -EBUSY;
588 }
589
590 port->membase = ioremap(port->mapbase, size);
591 if (!port->membase) {
592 dev_err(port->dev, "Unable to map registers\n");
593 release_mem_region(port->mapbase, size);
594 return -EBUSY;
595 }
596 return 0;
597}
598
599/*
600 * serial core request to release uart iomem
601 */
602static void bcm_uart_release_port(struct uart_port *port)
603{
604 release_mem_region(port->mapbase, RSET_UART_SIZE);
605 iounmap(port->membase);
606}
607
608/*
609 * serial core request to do any port required autoconfiguration
610 */
611static void bcm_uart_config_port(struct uart_port *port, int flags)
612{
613 if (flags & UART_CONFIG_TYPE) {
614 if (bcm_uart_request_port(port))
615 return;
616 port->type = PORT_BCM63XX;
617 }
618}
619
620/*
621 * serial core request to check that port information in serinfo are
622 * suitable
623 */
624static int bcm_uart_verify_port(struct uart_port *port,
625 struct serial_struct *serinfo)
626{
627 if (port->type != PORT_BCM63XX)
628 return -EINVAL;
629 if (port->irq != serinfo->irq)
630 return -EINVAL;
631 if (port->iotype != serinfo->io_type)
632 return -EINVAL;
633 if (port->mapbase != (unsigned long)serinfo->iomem_base)
634 return -EINVAL;
635 return 0;
636}
637
638/* serial core callbacks */
639static struct uart_ops bcm_uart_ops = {
640 .tx_empty = bcm_uart_tx_empty,
641 .get_mctrl = bcm_uart_get_mctrl,
642 .set_mctrl = bcm_uart_set_mctrl,
643 .start_tx = bcm_uart_start_tx,
644 .stop_tx = bcm_uart_stop_tx,
645 .stop_rx = bcm_uart_stop_rx,
646 .enable_ms = bcm_uart_enable_ms,
647 .break_ctl = bcm_uart_break_ctl,
648 .startup = bcm_uart_startup,
649 .shutdown = bcm_uart_shutdown,
650 .set_termios = bcm_uart_set_termios,
651 .type = bcm_uart_type,
652 .release_port = bcm_uart_release_port,
653 .request_port = bcm_uart_request_port,
654 .config_port = bcm_uart_config_port,
655 .verify_port = bcm_uart_verify_port,
656};
657
658
659
660#ifdef CONFIG_SERIAL_BCM63XX_CONSOLE
661static inline void wait_for_xmitr(struct uart_port *port)
662{
663 unsigned int tmout;
664
665 /* Wait up to 10ms for the character(s) to be sent. */
666 tmout = 10000;
667 while (--tmout) {
668 unsigned int val;
669
670 val = bcm_uart_readl(port, UART_IR_REG);
671 if (val & UART_IR_STAT(UART_IR_TXEMPTY))
672 break;
673 udelay(1);
674 }
675
676 /* Wait up to 1s for flow control if necessary */
677 if (port->flags & UPF_CONS_FLOW) {
678 tmout = 1000000;
679 while (--tmout) {
680 unsigned int val;
681
682 val = bcm_uart_readl(port, UART_EXTINP_REG);
683 if (val & UART_EXTINP_CTS_MASK)
684 break;
685 udelay(1);
686 }
687 }
688}
689
690/*
691 * output given char
692 */
693static void bcm_console_putchar(struct uart_port *port, int ch)
694{
695 wait_for_xmitr(port);
696 bcm_uart_writel(port, ch, UART_FIFO_REG);
697}
698
699/*
700 * console core request to output given string
701 */
702static void bcm_console_write(struct console *co, const char *s,
703 unsigned int count)
704{
705 struct uart_port *port;
706 unsigned long flags;
707 int locked;
708
709 port = &ports[co->index];
710
711 local_irq_save(flags);
712 if (port->sysrq) {
713 /* bcm_uart_interrupt() already took the lock */
714 locked = 0;
715 } else if (oops_in_progress) {
716 locked = spin_trylock(&port->lock);
717 } else {
718 spin_lock(&port->lock);
719 locked = 1;
720 }
721
722 /* call helper to deal with \r\n */
723 uart_console_write(port, s, count, bcm_console_putchar);
724
725 /* and wait for char to be transmitted */
726 wait_for_xmitr(port);
727
728 if (locked)
729 spin_unlock(&port->lock);
730 local_irq_restore(flags);
731}
732
733/*
734 * console core request to setup given console, find matching uart
735 * port and setup it.
736 */
737static int bcm_console_setup(struct console *co, char *options)
738{
739 struct uart_port *port;
740 int baud = 9600;
741 int bits = 8;
742 int parity = 'n';
743 int flow = 'n';
744
745 if (co->index < 0 || co->index >= BCM63XX_NR_UARTS)
746 return -EINVAL;
747 port = &ports[co->index];
748 if (!port->membase)
749 return -ENODEV;
750 if (options)
751 uart_parse_options(options, &baud, &parity, &bits, &flow);
752
753 return uart_set_options(port, co, baud, parity, bits, flow);
754}
755
756static struct uart_driver bcm_uart_driver;
757
758static struct console bcm63xx_console = {
759 .name = "ttyS",
760 .write = bcm_console_write,
761 .device = uart_console_device,
762 .setup = bcm_console_setup,
763 .flags = CON_PRINTBUFFER,
764 .index = -1,
765 .data = &bcm_uart_driver,
766};
767
768static int __init bcm63xx_console_init(void)
769{
770 register_console(&bcm63xx_console);
771 return 0;
772}
773
774console_initcall(bcm63xx_console_init);
775
776#define BCM63XX_CONSOLE (&bcm63xx_console)
777#else
778#define BCM63XX_CONSOLE NULL
779#endif /* CONFIG_SERIAL_BCM63XX_CONSOLE */
780
781static struct uart_driver bcm_uart_driver = {
782 .owner = THIS_MODULE,
783 .driver_name = "bcm63xx_uart",
784 .dev_name = "ttyS",
785 .major = TTY_MAJOR,
786 .minor = 64,
787 .nr = BCM63XX_NR_UARTS,
788 .cons = BCM63XX_CONSOLE,
789};
790
791/*
792 * platform driver probe/remove callback
793 */
794static int __devinit bcm_uart_probe(struct platform_device *pdev)
795{
796 struct resource *res_mem, *res_irq;
797 struct uart_port *port;
798 struct clk *clk;
799 int ret;
800
801 if (pdev->id < 0 || pdev->id >= BCM63XX_NR_UARTS)
802 return -EINVAL;
803
804 if (ports[pdev->id].membase)
805 return -EBUSY;
806
807 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
808 if (!res_mem)
809 return -ENODEV;
810
811 res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
812 if (!res_irq)
813 return -ENODEV;
814
815 clk = clk_get(&pdev->dev, "periph");
816 if (IS_ERR(clk))
817 return -ENODEV;
818
819 port = &ports[pdev->id];
820 memset(port, 0, sizeof(*port));
821 port->iotype = UPIO_MEM;
822 port->mapbase = res_mem->start;
823 port->irq = res_irq->start;
824 port->ops = &bcm_uart_ops;
825 port->flags = UPF_BOOT_AUTOCONF;
826 port->dev = &pdev->dev;
827 port->fifosize = 16;
828 port->uartclk = clk_get_rate(clk) / 2;
829 port->line = pdev->id;
830 clk_put(clk);
831
832 ret = uart_add_one_port(&bcm_uart_driver, port);
833 if (ret) {
834 ports[pdev->id].membase = 0;
835 return ret;
836 }
837 platform_set_drvdata(pdev, port);
838 return 0;
839}
840
841static int __devexit bcm_uart_remove(struct platform_device *pdev)
842{
843 struct uart_port *port;
844
845 port = platform_get_drvdata(pdev);
846 uart_remove_one_port(&bcm_uart_driver, port);
847 platform_set_drvdata(pdev, NULL);
848 /* mark port as free */
849 ports[pdev->id].membase = 0;
850 return 0;
851}
852
853/*
854 * platform driver stuff
855 */
856static struct platform_driver bcm_uart_platform_driver = {
857 .probe = bcm_uart_probe,
858 .remove = __devexit_p(bcm_uart_remove),
859 .driver = {
860 .owner = THIS_MODULE,
861 .name = "bcm63xx_uart",
862 },
863};
864
865static int __init bcm_uart_init(void)
866{
867 int ret;
868
869 ret = uart_register_driver(&bcm_uart_driver);
870 if (ret)
871 return ret;
872
873 ret = platform_driver_register(&bcm_uart_platform_driver);
874 if (ret)
875 uart_unregister_driver(&bcm_uart_driver);
876
877 return ret;
878}
879
880static void __exit bcm_uart_exit(void)
881{
882 platform_driver_unregister(&bcm_uart_platform_driver);
883 uart_unregister_driver(&bcm_uart_driver);
884}
885
886module_init(bcm_uart_init);
887module_exit(bcm_uart_exit);
888
889MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
890MODULE_DESCRIPTION("Broadcom 63<xx integrated uart driver");
891MODULE_LICENSE("GPL");
diff --git a/drivers/serial/bfin_5xx.c b/drivers/serial/bfin_5xx.c
deleted file mode 100644
index a9eff2b18eab..000000000000
--- a/drivers/serial/bfin_5xx.c
+++ /dev/null
@@ -1,1459 +0,0 @@
1/*
2 * Blackfin On-Chip Serial Driver
3 *
4 * Copyright 2006-2008 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11#if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
12#define SUPPORT_SYSRQ
13#endif
14
15#include <linux/module.h>
16#include <linux/ioport.h>
17#include <linux/gfp.h>
18#include <linux/io.h>
19#include <linux/init.h>
20#include <linux/console.h>
21#include <linux/sysrq.h>
22#include <linux/platform_device.h>
23#include <linux/tty.h>
24#include <linux/tty_flip.h>
25#include <linux/serial_core.h>
26
27#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
28 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
29#include <linux/kgdb.h>
30#include <asm/irq_regs.h>
31#endif
32
33#include <asm/gpio.h>
34#include <mach/bfin_serial_5xx.h>
35
36#ifdef CONFIG_SERIAL_BFIN_DMA
37#include <linux/dma-mapping.h>
38#include <asm/io.h>
39#include <asm/irq.h>
40#include <asm/cacheflush.h>
41#endif
42
43#ifdef CONFIG_SERIAL_BFIN_MODULE
44# undef CONFIG_EARLY_PRINTK
45#endif
46
47#ifdef CONFIG_SERIAL_BFIN_MODULE
48# undef CONFIG_EARLY_PRINTK
49#endif
50
51/* UART name and device definitions */
52#define BFIN_SERIAL_NAME "ttyBF"
53#define BFIN_SERIAL_MAJOR 204
54#define BFIN_SERIAL_MINOR 64
55
56static struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
57static int nr_active_ports = ARRAY_SIZE(bfin_serial_resource);
58
59#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
60 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
61
62# ifndef CONFIG_SERIAL_BFIN_PIO
63# error KGDB only support UART in PIO mode.
64# endif
65
66static int kgdboc_port_line;
67static int kgdboc_break_enabled;
68#endif
69/*
70 * Setup for console. Argument comes from the menuconfig
71 */
72#define DMA_RX_XCOUNT 512
73#define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT)
74
75#define DMA_RX_FLUSH_JIFFIES (HZ / 50)
76
77#ifdef CONFIG_SERIAL_BFIN_DMA
78static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart);
79#else
80static void bfin_serial_tx_chars(struct bfin_serial_port *uart);
81#endif
82
83static void bfin_serial_reset_irda(struct uart_port *port);
84
85#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
86 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
87static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
88{
89 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
90 if (uart->cts_pin < 0)
91 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
92
93 /* CTS PIN is negative assertive. */
94 if (UART_GET_CTS(uart))
95 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
96 else
97 return TIOCM_DSR | TIOCM_CAR;
98}
99
100static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
101{
102 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
103 if (uart->rts_pin < 0)
104 return;
105
106 /* RTS PIN is negative assertive. */
107 if (mctrl & TIOCM_RTS)
108 UART_ENABLE_RTS(uart);
109 else
110 UART_DISABLE_RTS(uart);
111}
112
113/*
114 * Handle any change of modem status signal.
115 */
116static irqreturn_t bfin_serial_mctrl_cts_int(int irq, void *dev_id)
117{
118 struct bfin_serial_port *uart = dev_id;
119 unsigned int status;
120
121 status = bfin_serial_get_mctrl(&uart->port);
122 uart_handle_cts_change(&uart->port, status & TIOCM_CTS);
123#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
124 uart->scts = 1;
125 UART_CLEAR_SCTS(uart);
126 UART_CLEAR_IER(uart, EDSSI);
127#endif
128
129 return IRQ_HANDLED;
130}
131#else
132static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
133{
134 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
135}
136
137static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
138{
139}
140#endif
141
142/*
143 * interrupts are disabled on entry
144 */
145static void bfin_serial_stop_tx(struct uart_port *port)
146{
147 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
148#ifdef CONFIG_SERIAL_BFIN_DMA
149 struct circ_buf *xmit = &uart->port.state->xmit;
150#endif
151
152 while (!(UART_GET_LSR(uart) & TEMT))
153 cpu_relax();
154
155#ifdef CONFIG_SERIAL_BFIN_DMA
156 disable_dma(uart->tx_dma_channel);
157 xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
158 uart->port.icount.tx += uart->tx_count;
159 uart->tx_count = 0;
160 uart->tx_done = 1;
161#else
162#ifdef CONFIG_BF54x
163 /* Clear TFI bit */
164 UART_PUT_LSR(uart, TFI);
165#endif
166 UART_CLEAR_IER(uart, ETBEI);
167#endif
168}
169
170/*
171 * port is locked and interrupts are disabled
172 */
173static void bfin_serial_start_tx(struct uart_port *port)
174{
175 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
176 struct tty_struct *tty = uart->port.state->port.tty;
177
178#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
179 if (uart->scts && !(bfin_serial_get_mctrl(&uart->port) & TIOCM_CTS)) {
180 uart->scts = 0;
181 uart_handle_cts_change(&uart->port, uart->scts);
182 }
183#endif
184
185 /*
186 * To avoid losting RX interrupt, we reset IR function
187 * before sending data.
188 */
189 if (tty->termios->c_line == N_IRDA)
190 bfin_serial_reset_irda(port);
191
192#ifdef CONFIG_SERIAL_BFIN_DMA
193 if (uart->tx_done)
194 bfin_serial_dma_tx_chars(uart);
195#else
196 UART_SET_IER(uart, ETBEI);
197 bfin_serial_tx_chars(uart);
198#endif
199}
200
201/*
202 * Interrupts are enabled
203 */
204static void bfin_serial_stop_rx(struct uart_port *port)
205{
206 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
207
208 UART_CLEAR_IER(uart, ERBFI);
209}
210
211/*
212 * Set the modem control timer to fire immediately.
213 */
214static void bfin_serial_enable_ms(struct uart_port *port)
215{
216}
217
218
219#if ANOMALY_05000363 && defined(CONFIG_SERIAL_BFIN_PIO)
220# define UART_GET_ANOMALY_THRESHOLD(uart) ((uart)->anomaly_threshold)
221# define UART_SET_ANOMALY_THRESHOLD(uart, v) ((uart)->anomaly_threshold = (v))
222#else
223# define UART_GET_ANOMALY_THRESHOLD(uart) 0
224# define UART_SET_ANOMALY_THRESHOLD(uart, v)
225#endif
226
227#ifdef CONFIG_SERIAL_BFIN_PIO
228static void bfin_serial_rx_chars(struct bfin_serial_port *uart)
229{
230 struct tty_struct *tty = NULL;
231 unsigned int status, ch, flg;
232 static struct timeval anomaly_start = { .tv_sec = 0 };
233
234 status = UART_GET_LSR(uart);
235 UART_CLEAR_LSR(uart);
236
237 ch = UART_GET_CHAR(uart);
238 uart->port.icount.rx++;
239
240#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
241 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
242 if (kgdb_connected && kgdboc_port_line == uart->port.line
243 && kgdboc_break_enabled)
244 if (ch == 0x3) {/* Ctrl + C */
245 kgdb_breakpoint();
246 return;
247 }
248
249 if (!uart->port.state || !uart->port.state->port.tty)
250 return;
251#endif
252 tty = uart->port.state->port.tty;
253
254 if (ANOMALY_05000363) {
255 /* The BF533 (and BF561) family of processors have a nice anomaly
256 * where they continuously generate characters for a "single" break.
257 * We have to basically ignore this flood until the "next" valid
258 * character comes across. Due to the nature of the flood, it is
259 * not possible to reliably catch bytes that are sent too quickly
260 * after this break. So application code talking to the Blackfin
261 * which sends a break signal must allow at least 1.5 character
262 * times after the end of the break for things to stabilize. This
263 * timeout was picked as it must absolutely be larger than 1
264 * character time +/- some percent. So 1.5 sounds good. All other
265 * Blackfin families operate properly. Woo.
266 */
267 if (anomaly_start.tv_sec) {
268 struct timeval curr;
269 suseconds_t usecs;
270
271 if ((~ch & (~ch + 1)) & 0xff)
272 goto known_good_char;
273
274 do_gettimeofday(&curr);
275 if (curr.tv_sec - anomaly_start.tv_sec > 1)
276 goto known_good_char;
277
278 usecs = 0;
279 if (curr.tv_sec != anomaly_start.tv_sec)
280 usecs += USEC_PER_SEC;
281 usecs += curr.tv_usec - anomaly_start.tv_usec;
282
283 if (usecs > UART_GET_ANOMALY_THRESHOLD(uart))
284 goto known_good_char;
285
286 if (ch)
287 anomaly_start.tv_sec = 0;
288 else
289 anomaly_start = curr;
290
291 return;
292
293 known_good_char:
294 status &= ~BI;
295 anomaly_start.tv_sec = 0;
296 }
297 }
298
299 if (status & BI) {
300 if (ANOMALY_05000363)
301 if (bfin_revid() < 5)
302 do_gettimeofday(&anomaly_start);
303 uart->port.icount.brk++;
304 if (uart_handle_break(&uart->port))
305 goto ignore_char;
306 status &= ~(PE | FE);
307 }
308 if (status & PE)
309 uart->port.icount.parity++;
310 if (status & OE)
311 uart->port.icount.overrun++;
312 if (status & FE)
313 uart->port.icount.frame++;
314
315 status &= uart->port.read_status_mask;
316
317 if (status & BI)
318 flg = TTY_BREAK;
319 else if (status & PE)
320 flg = TTY_PARITY;
321 else if (status & FE)
322 flg = TTY_FRAME;
323 else
324 flg = TTY_NORMAL;
325
326 if (uart_handle_sysrq_char(&uart->port, ch))
327 goto ignore_char;
328
329 uart_insert_char(&uart->port, status, OE, ch, flg);
330
331 ignore_char:
332 tty_flip_buffer_push(tty);
333}
334
335static void bfin_serial_tx_chars(struct bfin_serial_port *uart)
336{
337 struct circ_buf *xmit = &uart->port.state->xmit;
338
339 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
340#ifdef CONFIG_BF54x
341 /* Clear TFI bit */
342 UART_PUT_LSR(uart, TFI);
343#endif
344 /* Anomaly notes:
345 * 05000215 - we always clear ETBEI within last UART TX
346 * interrupt to end a string. It is always set
347 * when start a new tx.
348 */
349 UART_CLEAR_IER(uart, ETBEI);
350 return;
351 }
352
353 if (uart->port.x_char) {
354 UART_PUT_CHAR(uart, uart->port.x_char);
355 uart->port.icount.tx++;
356 uart->port.x_char = 0;
357 }
358
359 while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) {
360 UART_PUT_CHAR(uart, xmit->buf[xmit->tail]);
361 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
362 uart->port.icount.tx++;
363 SSYNC();
364 }
365
366 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
367 uart_write_wakeup(&uart->port);
368}
369
370static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id)
371{
372 struct bfin_serial_port *uart = dev_id;
373
374 spin_lock(&uart->port.lock);
375 while (UART_GET_LSR(uart) & DR)
376 bfin_serial_rx_chars(uart);
377 spin_unlock(&uart->port.lock);
378
379 return IRQ_HANDLED;
380}
381
382static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id)
383{
384 struct bfin_serial_port *uart = dev_id;
385
386#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
387 if (uart->scts && !(bfin_serial_get_mctrl(&uart->port) & TIOCM_CTS)) {
388 uart->scts = 0;
389 uart_handle_cts_change(&uart->port, uart->scts);
390 }
391#endif
392 spin_lock(&uart->port.lock);
393 if (UART_GET_LSR(uart) & THRE)
394 bfin_serial_tx_chars(uart);
395 spin_unlock(&uart->port.lock);
396
397 return IRQ_HANDLED;
398}
399#endif
400
401#ifdef CONFIG_SERIAL_BFIN_DMA
402static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
403{
404 struct circ_buf *xmit = &uart->port.state->xmit;
405
406 uart->tx_done = 0;
407
408 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
409 uart->tx_count = 0;
410 uart->tx_done = 1;
411 return;
412 }
413
414 if (uart->port.x_char) {
415 UART_PUT_CHAR(uart, uart->port.x_char);
416 uart->port.icount.tx++;
417 uart->port.x_char = 0;
418 }
419
420 uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE);
421 if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail))
422 uart->tx_count = UART_XMIT_SIZE - xmit->tail;
423 blackfin_dcache_flush_range((unsigned long)(xmit->buf+xmit->tail),
424 (unsigned long)(xmit->buf+xmit->tail+uart->tx_count));
425 set_dma_config(uart->tx_dma_channel,
426 set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP,
427 INTR_ON_BUF,
428 DIMENSION_LINEAR,
429 DATA_SIZE_8,
430 DMA_SYNC_RESTART));
431 set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail));
432 set_dma_x_count(uart->tx_dma_channel, uart->tx_count);
433 set_dma_x_modify(uart->tx_dma_channel, 1);
434 SSYNC();
435 enable_dma(uart->tx_dma_channel);
436
437 UART_SET_IER(uart, ETBEI);
438}
439
440static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart)
441{
442 struct tty_struct *tty = uart->port.state->port.tty;
443 int i, flg, status;
444
445 status = UART_GET_LSR(uart);
446 UART_CLEAR_LSR(uart);
447
448 uart->port.icount.rx +=
449 CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail,
450 UART_XMIT_SIZE);
451
452 if (status & BI) {
453 uart->port.icount.brk++;
454 if (uart_handle_break(&uart->port))
455 goto dma_ignore_char;
456 status &= ~(PE | FE);
457 }
458 if (status & PE)
459 uart->port.icount.parity++;
460 if (status & OE)
461 uart->port.icount.overrun++;
462 if (status & FE)
463 uart->port.icount.frame++;
464
465 status &= uart->port.read_status_mask;
466
467 if (status & BI)
468 flg = TTY_BREAK;
469 else if (status & PE)
470 flg = TTY_PARITY;
471 else if (status & FE)
472 flg = TTY_FRAME;
473 else
474 flg = TTY_NORMAL;
475
476 for (i = uart->rx_dma_buf.tail; ; i++) {
477 if (i >= UART_XMIT_SIZE)
478 i = 0;
479 if (i == uart->rx_dma_buf.head)
480 break;
481 if (!uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i]))
482 uart_insert_char(&uart->port, status, OE,
483 uart->rx_dma_buf.buf[i], flg);
484 }
485
486 dma_ignore_char:
487 tty_flip_buffer_push(tty);
488}
489
490void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart)
491{
492 int x_pos, pos;
493
494 dma_disable_irq(uart->tx_dma_channel);
495 dma_disable_irq(uart->rx_dma_channel);
496 spin_lock_bh(&uart->port.lock);
497
498 /* 2D DMA RX buffer ring is used. Because curr_y_count and
499 * curr_x_count can't be read as an atomic operation,
500 * curr_y_count should be read before curr_x_count. When
501 * curr_x_count is read, curr_y_count may already indicate
502 * next buffer line. But, the position calculated here is
503 * still indicate the old line. The wrong position data may
504 * be smaller than current buffer tail, which cause garbages
505 * are received if it is not prohibit.
506 */
507 uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
508 x_pos = get_dma_curr_xcount(uart->rx_dma_channel);
509 uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
510 if (uart->rx_dma_nrows == DMA_RX_YCOUNT || x_pos == 0)
511 uart->rx_dma_nrows = 0;
512 x_pos = DMA_RX_XCOUNT - x_pos;
513 if (x_pos == DMA_RX_XCOUNT)
514 x_pos = 0;
515
516 pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos;
517 /* Ignore receiving data if new position is in the same line of
518 * current buffer tail and small.
519 */
520 if (pos > uart->rx_dma_buf.tail ||
521 uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) {
522 uart->rx_dma_buf.head = pos;
523 bfin_serial_dma_rx_chars(uart);
524 uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
525 }
526
527 spin_unlock_bh(&uart->port.lock);
528 dma_enable_irq(uart->tx_dma_channel);
529 dma_enable_irq(uart->rx_dma_channel);
530
531 mod_timer(&(uart->rx_dma_timer), jiffies + DMA_RX_FLUSH_JIFFIES);
532}
533
534static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id)
535{
536 struct bfin_serial_port *uart = dev_id;
537 struct circ_buf *xmit = &uart->port.state->xmit;
538
539#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
540 if (uart->scts && !(bfin_serial_get_mctrl(&uart->port)&TIOCM_CTS)) {
541 uart->scts = 0;
542 uart_handle_cts_change(&uart->port, uart->scts);
543 }
544#endif
545
546 spin_lock(&uart->port.lock);
547 if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) {
548 disable_dma(uart->tx_dma_channel);
549 clear_dma_irqstat(uart->tx_dma_channel);
550 /* Anomaly notes:
551 * 05000215 - we always clear ETBEI within last UART TX
552 * interrupt to end a string. It is always set
553 * when start a new tx.
554 */
555 UART_CLEAR_IER(uart, ETBEI);
556 xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
557 uart->port.icount.tx += uart->tx_count;
558
559 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
560 uart_write_wakeup(&uart->port);
561
562 bfin_serial_dma_tx_chars(uart);
563 }
564
565 spin_unlock(&uart->port.lock);
566 return IRQ_HANDLED;
567}
568
569static irqreturn_t bfin_serial_dma_rx_int(int irq, void *dev_id)
570{
571 struct bfin_serial_port *uart = dev_id;
572 unsigned short irqstat;
573 int x_pos, pos;
574
575 spin_lock(&uart->port.lock);
576 irqstat = get_dma_curr_irqstat(uart->rx_dma_channel);
577 clear_dma_irqstat(uart->rx_dma_channel);
578
579 uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
580 x_pos = get_dma_curr_xcount(uart->rx_dma_channel);
581 uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
582 if (uart->rx_dma_nrows == DMA_RX_YCOUNT || x_pos == 0)
583 uart->rx_dma_nrows = 0;
584
585 pos = uart->rx_dma_nrows * DMA_RX_XCOUNT;
586 if (pos > uart->rx_dma_buf.tail ||
587 uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) {
588 uart->rx_dma_buf.head = pos;
589 bfin_serial_dma_rx_chars(uart);
590 uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
591 }
592
593 spin_unlock(&uart->port.lock);
594
595 return IRQ_HANDLED;
596}
597#endif
598
599/*
600 * Return TIOCSER_TEMT when transmitter is not busy.
601 */
602static unsigned int bfin_serial_tx_empty(struct uart_port *port)
603{
604 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
605 unsigned short lsr;
606
607 lsr = UART_GET_LSR(uart);
608 if (lsr & TEMT)
609 return TIOCSER_TEMT;
610 else
611 return 0;
612}
613
614static void bfin_serial_break_ctl(struct uart_port *port, int break_state)
615{
616 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
617 u16 lcr = UART_GET_LCR(uart);
618 if (break_state)
619 lcr |= SB;
620 else
621 lcr &= ~SB;
622 UART_PUT_LCR(uart, lcr);
623 SSYNC();
624}
625
626static int bfin_serial_startup(struct uart_port *port)
627{
628 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
629
630#ifdef CONFIG_SERIAL_BFIN_DMA
631 dma_addr_t dma_handle;
632
633 if (request_dma(uart->rx_dma_channel, "BFIN_UART_RX") < 0) {
634 printk(KERN_NOTICE "Unable to attach Blackfin UART RX DMA channel\n");
635 return -EBUSY;
636 }
637
638 if (request_dma(uart->tx_dma_channel, "BFIN_UART_TX") < 0) {
639 printk(KERN_NOTICE "Unable to attach Blackfin UART TX DMA channel\n");
640 free_dma(uart->rx_dma_channel);
641 return -EBUSY;
642 }
643
644 set_dma_callback(uart->rx_dma_channel, bfin_serial_dma_rx_int, uart);
645 set_dma_callback(uart->tx_dma_channel, bfin_serial_dma_tx_int, uart);
646
647 uart->rx_dma_buf.buf = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE, &dma_handle, GFP_DMA);
648 uart->rx_dma_buf.head = 0;
649 uart->rx_dma_buf.tail = 0;
650 uart->rx_dma_nrows = 0;
651
652 set_dma_config(uart->rx_dma_channel,
653 set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO,
654 INTR_ON_ROW, DIMENSION_2D,
655 DATA_SIZE_8,
656 DMA_SYNC_RESTART));
657 set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT);
658 set_dma_x_modify(uart->rx_dma_channel, 1);
659 set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT);
660 set_dma_y_modify(uart->rx_dma_channel, 1);
661 set_dma_start_addr(uart->rx_dma_channel, (unsigned long)uart->rx_dma_buf.buf);
662 enable_dma(uart->rx_dma_channel);
663
664 uart->rx_dma_timer.data = (unsigned long)(uart);
665 uart->rx_dma_timer.function = (void *)bfin_serial_rx_dma_timeout;
666 uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES;
667 add_timer(&(uart->rx_dma_timer));
668#else
669# if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
670 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
671 if (kgdboc_port_line == uart->port.line && kgdboc_break_enabled)
672 kgdboc_break_enabled = 0;
673 else {
674# endif
675 if (request_irq(uart->port.irq, bfin_serial_rx_int, IRQF_DISABLED,
676 "BFIN_UART_RX", uart)) {
677 printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n");
678 return -EBUSY;
679 }
680
681 if (request_irq
682 (uart->port.irq+1, bfin_serial_tx_int, IRQF_DISABLED,
683 "BFIN_UART_TX", uart)) {
684 printk(KERN_NOTICE "Unable to attach BlackFin UART TX interrupt\n");
685 free_irq(uart->port.irq, uart);
686 return -EBUSY;
687 }
688
689# ifdef CONFIG_BF54x
690 {
691 unsigned uart_dma_ch_rx, uart_dma_ch_tx;
692
693 switch (uart->port.irq) {
694 case IRQ_UART3_RX:
695 uart_dma_ch_rx = CH_UART3_RX;
696 uart_dma_ch_tx = CH_UART3_TX;
697 break;
698 case IRQ_UART2_RX:
699 uart_dma_ch_rx = CH_UART2_RX;
700 uart_dma_ch_tx = CH_UART2_TX;
701 break;
702 default:
703 uart_dma_ch_rx = uart_dma_ch_tx = 0;
704 break;
705 };
706
707 if (uart_dma_ch_rx &&
708 request_dma(uart_dma_ch_rx, "BFIN_UART_RX") < 0) {
709 printk(KERN_NOTICE"Fail to attach UART interrupt\n");
710 free_irq(uart->port.irq, uart);
711 free_irq(uart->port.irq + 1, uart);
712 return -EBUSY;
713 }
714 if (uart_dma_ch_tx &&
715 request_dma(uart_dma_ch_tx, "BFIN_UART_TX") < 0) {
716 printk(KERN_NOTICE "Fail to attach UART interrupt\n");
717 free_dma(uart_dma_ch_rx);
718 free_irq(uart->port.irq, uart);
719 free_irq(uart->port.irq + 1, uart);
720 return -EBUSY;
721 }
722 }
723# endif
724# if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
725 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
726 }
727# endif
728#endif
729
730#ifdef CONFIG_SERIAL_BFIN_CTSRTS
731 if (uart->cts_pin >= 0) {
732 if (request_irq(gpio_to_irq(uart->cts_pin),
733 bfin_serial_mctrl_cts_int,
734 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
735 IRQF_DISABLED, "BFIN_UART_CTS", uart)) {
736 uart->cts_pin = -1;
737 pr_info("Unable to attach BlackFin UART CTS interrupt.\
738 So, disable it.\n");
739 }
740 }
741 if (uart->rts_pin >= 0) {
742 gpio_request(uart->rts_pin, DRIVER_NAME);
743 gpio_direction_output(uart->rts_pin, 0);
744 }
745#endif
746#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
747 if (request_irq(uart->status_irq,
748 bfin_serial_mctrl_cts_int,
749 IRQF_DISABLED, "BFIN_UART_MODEM_STATUS", uart)) {
750 pr_info("Unable to attach BlackFin UART Modem \
751 Status interrupt.\n");
752 }
753
754 /* CTS RTS PINs are negative assertive. */
755 UART_PUT_MCR(uart, ACTS);
756 UART_SET_IER(uart, EDSSI);
757#endif
758
759 UART_SET_IER(uart, ERBFI);
760 return 0;
761}
762
763static void bfin_serial_shutdown(struct uart_port *port)
764{
765 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
766
767#ifdef CONFIG_SERIAL_BFIN_DMA
768 disable_dma(uart->tx_dma_channel);
769 free_dma(uart->tx_dma_channel);
770 disable_dma(uart->rx_dma_channel);
771 free_dma(uart->rx_dma_channel);
772 del_timer(&(uart->rx_dma_timer));
773 dma_free_coherent(NULL, PAGE_SIZE, uart->rx_dma_buf.buf, 0);
774#else
775#ifdef CONFIG_BF54x
776 switch (uart->port.irq) {
777 case IRQ_UART3_RX:
778 free_dma(CH_UART3_RX);
779 free_dma(CH_UART3_TX);
780 break;
781 case IRQ_UART2_RX:
782 free_dma(CH_UART2_RX);
783 free_dma(CH_UART2_TX);
784 break;
785 default:
786 break;
787 };
788#endif
789 free_irq(uart->port.irq, uart);
790 free_irq(uart->port.irq+1, uart);
791#endif
792
793#ifdef CONFIG_SERIAL_BFIN_CTSRTS
794 if (uart->cts_pin >= 0)
795 free_irq(gpio_to_irq(uart->cts_pin), uart);
796 if (uart->rts_pin >= 0)
797 gpio_free(uart->rts_pin);
798#endif
799#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
800 if (UART_GET_IER(uart) & EDSSI)
801 free_irq(uart->status_irq, uart);
802#endif
803}
804
805static void
806bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios,
807 struct ktermios *old)
808{
809 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
810 unsigned long flags;
811 unsigned int baud, quot;
812 unsigned short val, ier, lcr = 0;
813
814 switch (termios->c_cflag & CSIZE) {
815 case CS8:
816 lcr = WLS(8);
817 break;
818 case CS7:
819 lcr = WLS(7);
820 break;
821 case CS6:
822 lcr = WLS(6);
823 break;
824 case CS5:
825 lcr = WLS(5);
826 break;
827 default:
828 printk(KERN_ERR "%s: word lengh not supported\n",
829 __func__);
830 }
831
832 /* Anomaly notes:
833 * 05000231 - STOP bit is always set to 1 whatever the user is set.
834 */
835 if (termios->c_cflag & CSTOPB) {
836 if (ANOMALY_05000231)
837 printk(KERN_WARNING "STOP bits other than 1 is not "
838 "supported in case of anomaly 05000231.\n");
839 else
840 lcr |= STB;
841 }
842 if (termios->c_cflag & PARENB)
843 lcr |= PEN;
844 if (!(termios->c_cflag & PARODD))
845 lcr |= EPS;
846 if (termios->c_cflag & CMSPAR)
847 lcr |= STP;
848
849 port->read_status_mask = OE;
850 if (termios->c_iflag & INPCK)
851 port->read_status_mask |= (FE | PE);
852 if (termios->c_iflag & (BRKINT | PARMRK))
853 port->read_status_mask |= BI;
854
855 /*
856 * Characters to ignore
857 */
858 port->ignore_status_mask = 0;
859 if (termios->c_iflag & IGNPAR)
860 port->ignore_status_mask |= FE | PE;
861 if (termios->c_iflag & IGNBRK) {
862 port->ignore_status_mask |= BI;
863 /*
864 * If we're ignoring parity and break indicators,
865 * ignore overruns too (for real raw support).
866 */
867 if (termios->c_iflag & IGNPAR)
868 port->ignore_status_mask |= OE;
869 }
870
871 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
872 quot = uart_get_divisor(port, baud);
873
874 /* If discipline is not IRDA, apply ANOMALY_05000230 */
875 if (termios->c_line != N_IRDA)
876 quot -= ANOMALY_05000230;
877
878 spin_lock_irqsave(&uart->port.lock, flags);
879
880 UART_SET_ANOMALY_THRESHOLD(uart, USEC_PER_SEC / baud * 15);
881
882 /* Disable UART */
883 ier = UART_GET_IER(uart);
884 UART_DISABLE_INTS(uart);
885
886 /* Set DLAB in LCR to Access DLL and DLH */
887 UART_SET_DLAB(uart);
888
889 UART_PUT_DLL(uart, quot & 0xFF);
890 UART_PUT_DLH(uart, (quot >> 8) & 0xFF);
891 SSYNC();
892
893 /* Clear DLAB in LCR to Access THR RBR IER */
894 UART_CLEAR_DLAB(uart);
895
896 UART_PUT_LCR(uart, lcr);
897
898 /* Enable UART */
899 UART_ENABLE_INTS(uart, ier);
900
901 val = UART_GET_GCTL(uart);
902 val |= UCEN;
903 UART_PUT_GCTL(uart, val);
904
905 /* Port speed changed, update the per-port timeout. */
906 uart_update_timeout(port, termios->c_cflag, baud);
907
908 spin_unlock_irqrestore(&uart->port.lock, flags);
909}
910
911static const char *bfin_serial_type(struct uart_port *port)
912{
913 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
914
915 return uart->port.type == PORT_BFIN ? "BFIN-UART" : NULL;
916}
917
918/*
919 * Release the memory region(s) being used by 'port'.
920 */
921static void bfin_serial_release_port(struct uart_port *port)
922{
923}
924
925/*
926 * Request the memory region(s) being used by 'port'.
927 */
928static int bfin_serial_request_port(struct uart_port *port)
929{
930 return 0;
931}
932
933/*
934 * Configure/autoconfigure the port.
935 */
936static void bfin_serial_config_port(struct uart_port *port, int flags)
937{
938 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
939
940 if (flags & UART_CONFIG_TYPE &&
941 bfin_serial_request_port(&uart->port) == 0)
942 uart->port.type = PORT_BFIN;
943}
944
945/*
946 * Verify the new serial_struct (for TIOCSSERIAL).
947 * The only change we allow are to the flags and type, and
948 * even then only between PORT_BFIN and PORT_UNKNOWN
949 */
950static int
951bfin_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
952{
953 return 0;
954}
955
956/*
957 * Enable the IrDA function if tty->ldisc.num is N_IRDA.
958 * In other cases, disable IrDA function.
959 */
960static void bfin_serial_set_ldisc(struct uart_port *port, int ld)
961{
962 int line = port->line;
963 unsigned short val;
964
965 switch (ld) {
966 case N_IRDA:
967 val = UART_GET_GCTL(&bfin_serial_ports[line]);
968 val |= (IREN | RPOLC);
969 UART_PUT_GCTL(&bfin_serial_ports[line], val);
970 break;
971 default:
972 val = UART_GET_GCTL(&bfin_serial_ports[line]);
973 val &= ~(IREN | RPOLC);
974 UART_PUT_GCTL(&bfin_serial_ports[line], val);
975 }
976}
977
978static void bfin_serial_reset_irda(struct uart_port *port)
979{
980 int line = port->line;
981 unsigned short val;
982
983 val = UART_GET_GCTL(&bfin_serial_ports[line]);
984 val &= ~(IREN | RPOLC);
985 UART_PUT_GCTL(&bfin_serial_ports[line], val);
986 SSYNC();
987 val |= (IREN | RPOLC);
988 UART_PUT_GCTL(&bfin_serial_ports[line], val);
989 SSYNC();
990}
991
992#ifdef CONFIG_CONSOLE_POLL
993/* Anomaly notes:
994 * 05000099 - Because we only use THRE in poll_put and DR in poll_get,
995 * losing other bits of UART_LSR is not a problem here.
996 */
997static void bfin_serial_poll_put_char(struct uart_port *port, unsigned char chr)
998{
999 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1000
1001 while (!(UART_GET_LSR(uart) & THRE))
1002 cpu_relax();
1003
1004 UART_CLEAR_DLAB(uart);
1005 UART_PUT_CHAR(uart, (unsigned char)chr);
1006}
1007
1008static int bfin_serial_poll_get_char(struct uart_port *port)
1009{
1010 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1011 unsigned char chr;
1012
1013 while (!(UART_GET_LSR(uart) & DR))
1014 cpu_relax();
1015
1016 UART_CLEAR_DLAB(uart);
1017 chr = UART_GET_CHAR(uart);
1018
1019 return chr;
1020}
1021#endif
1022
1023#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
1024 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
1025static void bfin_kgdboc_port_shutdown(struct uart_port *port)
1026{
1027 if (kgdboc_break_enabled) {
1028 kgdboc_break_enabled = 0;
1029 bfin_serial_shutdown(port);
1030 }
1031}
1032
1033static int bfin_kgdboc_port_startup(struct uart_port *port)
1034{
1035 kgdboc_port_line = port->line;
1036 kgdboc_break_enabled = !bfin_serial_startup(port);
1037 return 0;
1038}
1039#endif
1040
1041static struct uart_ops bfin_serial_pops = {
1042 .tx_empty = bfin_serial_tx_empty,
1043 .set_mctrl = bfin_serial_set_mctrl,
1044 .get_mctrl = bfin_serial_get_mctrl,
1045 .stop_tx = bfin_serial_stop_tx,
1046 .start_tx = bfin_serial_start_tx,
1047 .stop_rx = bfin_serial_stop_rx,
1048 .enable_ms = bfin_serial_enable_ms,
1049 .break_ctl = bfin_serial_break_ctl,
1050 .startup = bfin_serial_startup,
1051 .shutdown = bfin_serial_shutdown,
1052 .set_termios = bfin_serial_set_termios,
1053 .set_ldisc = bfin_serial_set_ldisc,
1054 .type = bfin_serial_type,
1055 .release_port = bfin_serial_release_port,
1056 .request_port = bfin_serial_request_port,
1057 .config_port = bfin_serial_config_port,
1058 .verify_port = bfin_serial_verify_port,
1059#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
1060 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
1061 .kgdboc_port_startup = bfin_kgdboc_port_startup,
1062 .kgdboc_port_shutdown = bfin_kgdboc_port_shutdown,
1063#endif
1064#ifdef CONFIG_CONSOLE_POLL
1065 .poll_put_char = bfin_serial_poll_put_char,
1066 .poll_get_char = bfin_serial_poll_get_char,
1067#endif
1068};
1069
1070static void __init bfin_serial_hw_init(void)
1071{
1072#ifdef CONFIG_SERIAL_BFIN_UART0
1073 peripheral_request(P_UART0_TX, DRIVER_NAME);
1074 peripheral_request(P_UART0_RX, DRIVER_NAME);
1075#endif
1076
1077#ifdef CONFIG_SERIAL_BFIN_UART1
1078 peripheral_request(P_UART1_TX, DRIVER_NAME);
1079 peripheral_request(P_UART1_RX, DRIVER_NAME);
1080
1081# if defined(CONFIG_BFIN_UART1_CTSRTS) && defined(CONFIG_BF54x)
1082 peripheral_request(P_UART1_RTS, DRIVER_NAME);
1083 peripheral_request(P_UART1_CTS, DRIVER_NAME);
1084# endif
1085#endif
1086
1087#ifdef CONFIG_SERIAL_BFIN_UART2
1088 peripheral_request(P_UART2_TX, DRIVER_NAME);
1089 peripheral_request(P_UART2_RX, DRIVER_NAME);
1090#endif
1091
1092#ifdef CONFIG_SERIAL_BFIN_UART3
1093 peripheral_request(P_UART3_TX, DRIVER_NAME);
1094 peripheral_request(P_UART3_RX, DRIVER_NAME);
1095
1096# if defined(CONFIG_BFIN_UART3_CTSRTS) && defined(CONFIG_BF54x)
1097 peripheral_request(P_UART3_RTS, DRIVER_NAME);
1098 peripheral_request(P_UART3_CTS, DRIVER_NAME);
1099# endif
1100#endif
1101}
1102
1103static void __init bfin_serial_init_ports(void)
1104{
1105 static int first = 1;
1106 int i;
1107
1108 if (!first)
1109 return;
1110 first = 0;
1111
1112 bfin_serial_hw_init();
1113
1114 for (i = 0; i < nr_active_ports; i++) {
1115 spin_lock_init(&bfin_serial_ports[i].port.lock);
1116 bfin_serial_ports[i].port.uartclk = get_sclk();
1117 bfin_serial_ports[i].port.fifosize = BFIN_UART_TX_FIFO_SIZE;
1118 bfin_serial_ports[i].port.ops = &bfin_serial_pops;
1119 bfin_serial_ports[i].port.line = i;
1120 bfin_serial_ports[i].port.iotype = UPIO_MEM;
1121 bfin_serial_ports[i].port.membase =
1122 (void __iomem *)bfin_serial_resource[i].uart_base_addr;
1123 bfin_serial_ports[i].port.mapbase =
1124 bfin_serial_resource[i].uart_base_addr;
1125 bfin_serial_ports[i].port.irq =
1126 bfin_serial_resource[i].uart_irq;
1127 bfin_serial_ports[i].status_irq =
1128 bfin_serial_resource[i].uart_status_irq;
1129 bfin_serial_ports[i].port.flags = UPF_BOOT_AUTOCONF;
1130#ifdef CONFIG_SERIAL_BFIN_DMA
1131 bfin_serial_ports[i].tx_done = 1;
1132 bfin_serial_ports[i].tx_count = 0;
1133 bfin_serial_ports[i].tx_dma_channel =
1134 bfin_serial_resource[i].uart_tx_dma_channel;
1135 bfin_serial_ports[i].rx_dma_channel =
1136 bfin_serial_resource[i].uart_rx_dma_channel;
1137 init_timer(&(bfin_serial_ports[i].rx_dma_timer));
1138#endif
1139#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
1140 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
1141 bfin_serial_ports[i].cts_pin =
1142 bfin_serial_resource[i].uart_cts_pin;
1143 bfin_serial_ports[i].rts_pin =
1144 bfin_serial_resource[i].uart_rts_pin;
1145#endif
1146 }
1147}
1148
1149#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
1150/*
1151 * If the port was already initialised (eg, by a boot loader),
1152 * try to determine the current setup.
1153 */
1154static void __init
1155bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud,
1156 int *parity, int *bits)
1157{
1158 unsigned short status;
1159
1160 status = UART_GET_IER(uart) & (ERBFI | ETBEI);
1161 if (status == (ERBFI | ETBEI)) {
1162 /* ok, the port was enabled */
1163 u16 lcr, dlh, dll;
1164
1165 lcr = UART_GET_LCR(uart);
1166
1167 *parity = 'n';
1168 if (lcr & PEN) {
1169 if (lcr & EPS)
1170 *parity = 'e';
1171 else
1172 *parity = 'o';
1173 }
1174 switch (lcr & 0x03) {
1175 case 0: *bits = 5; break;
1176 case 1: *bits = 6; break;
1177 case 2: *bits = 7; break;
1178 case 3: *bits = 8; break;
1179 }
1180 /* Set DLAB in LCR to Access DLL and DLH */
1181 UART_SET_DLAB(uart);
1182
1183 dll = UART_GET_DLL(uart);
1184 dlh = UART_GET_DLH(uart);
1185
1186 /* Clear DLAB in LCR to Access THR RBR IER */
1187 UART_CLEAR_DLAB(uart);
1188
1189 *baud = get_sclk() / (16*(dll | dlh << 8));
1190 }
1191 pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __func__, *baud, *parity, *bits);
1192}
1193
1194static struct uart_driver bfin_serial_reg;
1195
1196static int __init
1197bfin_serial_console_setup(struct console *co, char *options)
1198{
1199 struct bfin_serial_port *uart;
1200 int baud = 57600;
1201 int bits = 8;
1202 int parity = 'n';
1203# if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
1204 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
1205 int flow = 'r';
1206# else
1207 int flow = 'n';
1208# endif
1209
1210 /*
1211 * Check whether an invalid uart number has been specified, and
1212 * if so, search for the first available port that does have
1213 * console support.
1214 */
1215 if (co->index == -1 || co->index >= nr_active_ports)
1216 co->index = 0;
1217 uart = &bfin_serial_ports[co->index];
1218
1219 if (options)
1220 uart_parse_options(options, &baud, &parity, &bits, &flow);
1221 else
1222 bfin_serial_console_get_options(uart, &baud, &parity, &bits);
1223
1224 return uart_set_options(&uart->port, co, baud, parity, bits, flow);
1225}
1226#endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) ||
1227 defined (CONFIG_EARLY_PRINTK) */
1228
1229#ifdef CONFIG_SERIAL_BFIN_CONSOLE
1230static void bfin_serial_console_putchar(struct uart_port *port, int ch)
1231{
1232 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1233 while (!(UART_GET_LSR(uart) & THRE))
1234 barrier();
1235 UART_PUT_CHAR(uart, ch);
1236 SSYNC();
1237}
1238
1239/*
1240 * Interrupts are disabled on entering
1241 */
1242static void
1243bfin_serial_console_write(struct console *co, const char *s, unsigned int count)
1244{
1245 struct bfin_serial_port *uart = &bfin_serial_ports[co->index];
1246 unsigned long flags;
1247
1248 spin_lock_irqsave(&uart->port.lock, flags);
1249 uart_console_write(&uart->port, s, count, bfin_serial_console_putchar);
1250 spin_unlock_irqrestore(&uart->port.lock, flags);
1251
1252}
1253
1254static struct console bfin_serial_console = {
1255 .name = BFIN_SERIAL_NAME,
1256 .write = bfin_serial_console_write,
1257 .device = uart_console_device,
1258 .setup = bfin_serial_console_setup,
1259 .flags = CON_PRINTBUFFER,
1260 .index = -1,
1261 .data = &bfin_serial_reg,
1262};
1263
1264static int __init bfin_serial_rs_console_init(void)
1265{
1266 bfin_serial_init_ports();
1267 register_console(&bfin_serial_console);
1268
1269 return 0;
1270}
1271console_initcall(bfin_serial_rs_console_init);
1272
1273#define BFIN_SERIAL_CONSOLE &bfin_serial_console
1274#else
1275#define BFIN_SERIAL_CONSOLE NULL
1276#endif /* CONFIG_SERIAL_BFIN_CONSOLE */
1277
1278
1279#ifdef CONFIG_EARLY_PRINTK
1280static __init void early_serial_putc(struct uart_port *port, int ch)
1281{
1282 unsigned timeout = 0xffff;
1283 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1284
1285 while ((!(UART_GET_LSR(uart) & THRE)) && --timeout)
1286 cpu_relax();
1287 UART_PUT_CHAR(uart, ch);
1288}
1289
1290static __init void early_serial_write(struct console *con, const char *s,
1291 unsigned int n)
1292{
1293 struct bfin_serial_port *uart = &bfin_serial_ports[con->index];
1294 unsigned int i;
1295
1296 for (i = 0; i < n; i++, s++) {
1297 if (*s == '\n')
1298 early_serial_putc(&uart->port, '\r');
1299 early_serial_putc(&uart->port, *s);
1300 }
1301}
1302
1303/*
1304 * This should have a .setup or .early_setup in it, but then things get called
1305 * without the command line options, and the baud rate gets messed up - so
1306 * don't let the common infrastructure play with things. (see calls to setup
1307 * & earlysetup in ./kernel/printk.c:register_console()
1308 */
1309static struct __initdata console bfin_early_serial_console = {
1310 .name = "early_BFuart",
1311 .write = early_serial_write,
1312 .device = uart_console_device,
1313 .flags = CON_PRINTBUFFER,
1314 .index = -1,
1315 .data = &bfin_serial_reg,
1316};
1317
1318struct console __init *bfin_earlyserial_init(unsigned int port,
1319 unsigned int cflag)
1320{
1321 struct bfin_serial_port *uart;
1322 struct ktermios t;
1323
1324 if (port == -1 || port >= nr_active_ports)
1325 port = 0;
1326 bfin_serial_init_ports();
1327 bfin_early_serial_console.index = port;
1328 uart = &bfin_serial_ports[port];
1329 t.c_cflag = cflag;
1330 t.c_iflag = 0;
1331 t.c_oflag = 0;
1332 t.c_lflag = ICANON;
1333 t.c_line = port;
1334 bfin_serial_set_termios(&uart->port, &t, &t);
1335 return &bfin_early_serial_console;
1336}
1337
1338#endif /* CONFIG_EARLY_PRINTK */
1339
1340static struct uart_driver bfin_serial_reg = {
1341 .owner = THIS_MODULE,
1342 .driver_name = "bfin-uart",
1343 .dev_name = BFIN_SERIAL_NAME,
1344 .major = BFIN_SERIAL_MAJOR,
1345 .minor = BFIN_SERIAL_MINOR,
1346 .nr = BFIN_UART_NR_PORTS,
1347 .cons = BFIN_SERIAL_CONSOLE,
1348};
1349
1350static int bfin_serial_suspend(struct platform_device *dev, pm_message_t state)
1351{
1352 int i;
1353
1354 for (i = 0; i < nr_active_ports; i++) {
1355 if (bfin_serial_ports[i].port.dev != &dev->dev)
1356 continue;
1357 uart_suspend_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1358 }
1359
1360 return 0;
1361}
1362
1363static int bfin_serial_resume(struct platform_device *dev)
1364{
1365 int i;
1366
1367 for (i = 0; i < nr_active_ports; i++) {
1368 if (bfin_serial_ports[i].port.dev != &dev->dev)
1369 continue;
1370 uart_resume_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1371 }
1372
1373 return 0;
1374}
1375
1376static int bfin_serial_probe(struct platform_device *dev)
1377{
1378 struct resource *res = dev->resource;
1379 int i;
1380
1381 for (i = 0; i < dev->num_resources; i++, res++)
1382 if (res->flags & IORESOURCE_MEM)
1383 break;
1384
1385 if (i < dev->num_resources) {
1386 for (i = 0; i < nr_active_ports; i++, res++) {
1387 if (bfin_serial_ports[i].port.mapbase != res->start)
1388 continue;
1389 bfin_serial_ports[i].port.dev = &dev->dev;
1390 uart_add_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1391 }
1392 }
1393
1394 return 0;
1395}
1396
1397static int bfin_serial_remove(struct platform_device *dev)
1398{
1399 int i;
1400
1401 for (i = 0; i < nr_active_ports; i++) {
1402 if (bfin_serial_ports[i].port.dev != &dev->dev)
1403 continue;
1404 uart_remove_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1405 bfin_serial_ports[i].port.dev = NULL;
1406#if defined(CONFIG_SERIAL_BFIN_CTSRTS)
1407 gpio_free(bfin_serial_ports[i].cts_pin);
1408 gpio_free(bfin_serial_ports[i].rts_pin);
1409#endif
1410 }
1411
1412 return 0;
1413}
1414
1415static struct platform_driver bfin_serial_driver = {
1416 .probe = bfin_serial_probe,
1417 .remove = bfin_serial_remove,
1418 .suspend = bfin_serial_suspend,
1419 .resume = bfin_serial_resume,
1420 .driver = {
1421 .name = "bfin-uart",
1422 .owner = THIS_MODULE,
1423 },
1424};
1425
1426static int __init bfin_serial_init(void)
1427{
1428 int ret;
1429
1430 pr_info("Serial: Blackfin serial driver\n");
1431
1432 bfin_serial_init_ports();
1433
1434 ret = uart_register_driver(&bfin_serial_reg);
1435 if (ret == 0) {
1436 ret = platform_driver_register(&bfin_serial_driver);
1437 if (ret) {
1438 pr_debug("uart register failed\n");
1439 uart_unregister_driver(&bfin_serial_reg);
1440 }
1441 }
1442 return ret;
1443}
1444
1445static void __exit bfin_serial_exit(void)
1446{
1447 platform_driver_unregister(&bfin_serial_driver);
1448 uart_unregister_driver(&bfin_serial_reg);
1449}
1450
1451
1452module_init(bfin_serial_init);
1453module_exit(bfin_serial_exit);
1454
1455MODULE_AUTHOR("Aubrey.Li <aubrey.li@analog.com>");
1456MODULE_DESCRIPTION("Blackfin generic serial port driver");
1457MODULE_LICENSE("GPL");
1458MODULE_ALIAS_CHARDEV_MAJOR(BFIN_SERIAL_MAJOR);
1459MODULE_ALIAS("platform:bfin-uart");
diff --git a/drivers/serial/bfin_sport_uart.c b/drivers/serial/bfin_sport_uart.c
deleted file mode 100644
index 5318dd3774ae..000000000000
--- a/drivers/serial/bfin_sport_uart.c
+++ /dev/null
@@ -1,930 +0,0 @@
1/*
2 * Blackfin On-Chip Sport Emulated UART Driver
3 *
4 * Copyright 2006-2009 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11/*
12 * This driver and the hardware supported are in term of EE-191 of ADI.
13 * http://www.analog.com/UploadedFiles/Application_Notes/399447663EE191.pdf
14 * This application note describe how to implement a UART on a Sharc DSP,
15 * but this driver is implemented on Blackfin Processor.
16 * Transmit Frame Sync is not used by this driver to transfer data out.
17 */
18
19/* #define DEBUG */
20
21#define DRV_NAME "bfin-sport-uart"
22#define DEVICE_NAME "ttySS"
23#define pr_fmt(fmt) DRV_NAME ": " fmt
24
25#include <linux/module.h>
26#include <linux/ioport.h>
27#include <linux/io.h>
28#include <linux/init.h>
29#include <linux/console.h>
30#include <linux/sysrq.h>
31#include <linux/slab.h>
32#include <linux/platform_device.h>
33#include <linux/tty.h>
34#include <linux/tty_flip.h>
35#include <linux/serial_core.h>
36
37#include <asm/bfin_sport.h>
38#include <asm/delay.h>
39#include <asm/portmux.h>
40
41#include "bfin_sport_uart.h"
42
43struct sport_uart_port {
44 struct uart_port port;
45 int err_irq;
46 unsigned short csize;
47 unsigned short rxmask;
48 unsigned short txmask1;
49 unsigned short txmask2;
50 unsigned char stopb;
51/* unsigned char parib; */
52#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
53 int cts_pin;
54 int rts_pin;
55#endif
56};
57
58static int sport_uart_tx_chars(struct sport_uart_port *up);
59static void sport_stop_tx(struct uart_port *port);
60
61static inline void tx_one_byte(struct sport_uart_port *up, unsigned int value)
62{
63 pr_debug("%s value:%x, mask1=0x%x, mask2=0x%x\n", __func__, value,
64 up->txmask1, up->txmask2);
65
66 /* Place Start and Stop bits */
67 __asm__ __volatile__ (
68 "%[val] <<= 1;"
69 "%[val] = %[val] & %[mask1];"
70 "%[val] = %[val] | %[mask2];"
71 : [val]"+d"(value)
72 : [mask1]"d"(up->txmask1), [mask2]"d"(up->txmask2)
73 : "ASTAT"
74 );
75 pr_debug("%s value:%x\n", __func__, value);
76
77 SPORT_PUT_TX(up, value);
78}
79
80static inline unsigned char rx_one_byte(struct sport_uart_port *up)
81{
82 unsigned int value;
83 unsigned char extract;
84 u32 tmp_mask1, tmp_mask2, tmp_shift, tmp;
85
86 if ((up->csize + up->stopb) > 7)
87 value = SPORT_GET_RX32(up);
88 else
89 value = SPORT_GET_RX(up);
90
91 pr_debug("%s value:%x, cs=%d, mask=0x%x\n", __func__, value,
92 up->csize, up->rxmask);
93
94 /* Extract data */
95 __asm__ __volatile__ (
96 "%[extr] = 0;"
97 "%[mask1] = %[rxmask];"
98 "%[mask2] = 0x0200(Z);"
99 "%[shift] = 0;"
100 "LSETUP(.Lloop_s, .Lloop_e) LC0 = %[lc];"
101 ".Lloop_s:"
102 "%[tmp] = extract(%[val], %[mask1].L)(Z);"
103 "%[tmp] <<= %[shift];"
104 "%[extr] = %[extr] | %[tmp];"
105 "%[mask1] = %[mask1] - %[mask2];"
106 ".Lloop_e:"
107 "%[shift] += 1;"
108 : [extr]"=&d"(extract), [shift]"=&d"(tmp_shift), [tmp]"=&d"(tmp),
109 [mask1]"=&d"(tmp_mask1), [mask2]"=&d"(tmp_mask2)
110 : [val]"d"(value), [rxmask]"d"(up->rxmask), [lc]"a"(up->csize)
111 : "ASTAT", "LB0", "LC0", "LT0"
112 );
113
114 pr_debug(" extract:%x\n", extract);
115 return extract;
116}
117
118static int sport_uart_setup(struct sport_uart_port *up, int size, int baud_rate)
119{
120 int tclkdiv, rclkdiv;
121 unsigned int sclk = get_sclk();
122
123 /* Set TCR1 and TCR2, TFSR is not enabled for uart */
124 SPORT_PUT_TCR1(up, (LATFS | ITFS | TFSR | TLSBIT | ITCLK));
125 SPORT_PUT_TCR2(up, size + 1);
126 pr_debug("%s TCR1:%x, TCR2:%x\n", __func__, SPORT_GET_TCR1(up), SPORT_GET_TCR2(up));
127
128 /* Set RCR1 and RCR2 */
129 SPORT_PUT_RCR1(up, (RCKFE | LARFS | LRFS | RFSR | IRCLK));
130 SPORT_PUT_RCR2(up, (size + 1) * 2 - 1);
131 pr_debug("%s RCR1:%x, RCR2:%x\n", __func__, SPORT_GET_RCR1(up), SPORT_GET_RCR2(up));
132
133 tclkdiv = sclk / (2 * baud_rate) - 1;
134 rclkdiv = sclk / (2 * baud_rate * 2) - 1;
135 SPORT_PUT_TCLKDIV(up, tclkdiv);
136 SPORT_PUT_RCLKDIV(up, rclkdiv);
137 SSYNC();
138 pr_debug("%s sclk:%d, baud_rate:%d, tclkdiv:%d, rclkdiv:%d\n",
139 __func__, sclk, baud_rate, tclkdiv, rclkdiv);
140
141 return 0;
142}
143
144static irqreturn_t sport_uart_rx_irq(int irq, void *dev_id)
145{
146 struct sport_uart_port *up = dev_id;
147 struct tty_struct *tty = up->port.state->port.tty;
148 unsigned int ch;
149
150 spin_lock(&up->port.lock);
151
152 while (SPORT_GET_STAT(up) & RXNE) {
153 ch = rx_one_byte(up);
154 up->port.icount.rx++;
155
156 if (!uart_handle_sysrq_char(&up->port, ch))
157 tty_insert_flip_char(tty, ch, TTY_NORMAL);
158 }
159 tty_flip_buffer_push(tty);
160
161 spin_unlock(&up->port.lock);
162
163 return IRQ_HANDLED;
164}
165
166static irqreturn_t sport_uart_tx_irq(int irq, void *dev_id)
167{
168 struct sport_uart_port *up = dev_id;
169
170 spin_lock(&up->port.lock);
171 sport_uart_tx_chars(up);
172 spin_unlock(&up->port.lock);
173
174 return IRQ_HANDLED;
175}
176
177static irqreturn_t sport_uart_err_irq(int irq, void *dev_id)
178{
179 struct sport_uart_port *up = dev_id;
180 struct tty_struct *tty = up->port.state->port.tty;
181 unsigned int stat = SPORT_GET_STAT(up);
182
183 spin_lock(&up->port.lock);
184
185 /* Overflow in RX FIFO */
186 if (stat & ROVF) {
187 up->port.icount.overrun++;
188 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
189 SPORT_PUT_STAT(up, ROVF); /* Clear ROVF bit */
190 }
191 /* These should not happen */
192 if (stat & (TOVF | TUVF | RUVF)) {
193 pr_err("SPORT Error:%s %s %s\n",
194 (stat & TOVF) ? "TX overflow" : "",
195 (stat & TUVF) ? "TX underflow" : "",
196 (stat & RUVF) ? "RX underflow" : "");
197 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
198 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
199 }
200 SSYNC();
201
202 spin_unlock(&up->port.lock);
203 return IRQ_HANDLED;
204}
205
206#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
207static unsigned int sport_get_mctrl(struct uart_port *port)
208{
209 struct sport_uart_port *up = (struct sport_uart_port *)port;
210 if (up->cts_pin < 0)
211 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
212
213 /* CTS PIN is negative assertive. */
214 if (SPORT_UART_GET_CTS(up))
215 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
216 else
217 return TIOCM_DSR | TIOCM_CAR;
218}
219
220static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl)
221{
222 struct sport_uart_port *up = (struct sport_uart_port *)port;
223 if (up->rts_pin < 0)
224 return;
225
226 /* RTS PIN is negative assertive. */
227 if (mctrl & TIOCM_RTS)
228 SPORT_UART_ENABLE_RTS(up);
229 else
230 SPORT_UART_DISABLE_RTS(up);
231}
232
233/*
234 * Handle any change of modem status signal.
235 */
236static irqreturn_t sport_mctrl_cts_int(int irq, void *dev_id)
237{
238 struct sport_uart_port *up = (struct sport_uart_port *)dev_id;
239 unsigned int status;
240
241 status = sport_get_mctrl(&up->port);
242 uart_handle_cts_change(&up->port, status & TIOCM_CTS);
243
244 return IRQ_HANDLED;
245}
246#else
247static unsigned int sport_get_mctrl(struct uart_port *port)
248{
249 pr_debug("%s enter\n", __func__);
250 return TIOCM_CTS | TIOCM_CD | TIOCM_DSR;
251}
252
253static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl)
254{
255 pr_debug("%s enter\n", __func__);
256}
257#endif
258
259/* Reqeust IRQ, Setup clock */
260static int sport_startup(struct uart_port *port)
261{
262 struct sport_uart_port *up = (struct sport_uart_port *)port;
263 int ret;
264
265 pr_debug("%s enter\n", __func__);
266 ret = request_irq(up->port.irq, sport_uart_rx_irq, 0,
267 "SPORT_UART_RX", up);
268 if (ret) {
269 dev_err(port->dev, "unable to request SPORT RX interrupt\n");
270 return ret;
271 }
272
273 ret = request_irq(up->port.irq+1, sport_uart_tx_irq, 0,
274 "SPORT_UART_TX", up);
275 if (ret) {
276 dev_err(port->dev, "unable to request SPORT TX interrupt\n");
277 goto fail1;
278 }
279
280 ret = request_irq(up->err_irq, sport_uart_err_irq, 0,
281 "SPORT_UART_STATUS", up);
282 if (ret) {
283 dev_err(port->dev, "unable to request SPORT status interrupt\n");
284 goto fail2;
285 }
286
287#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
288 if (up->cts_pin >= 0) {
289 if (request_irq(gpio_to_irq(up->cts_pin),
290 sport_mctrl_cts_int,
291 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
292 IRQF_DISABLED, "BFIN_SPORT_UART_CTS", up)) {
293 up->cts_pin = -1;
294 dev_info(port->dev, "Unable to attach BlackFin UART \
295 over SPORT CTS interrupt. So, disable it.\n");
296 }
297 }
298 if (up->rts_pin >= 0)
299 gpio_direction_output(up->rts_pin, 0);
300#endif
301
302 return 0;
303 fail2:
304 free_irq(up->port.irq+1, up);
305 fail1:
306 free_irq(up->port.irq, up);
307
308 return ret;
309}
310
311/*
312 * sport_uart_tx_chars
313 *
314 * ret 1 means need to enable sport.
315 * ret 0 means do nothing.
316 */
317static int sport_uart_tx_chars(struct sport_uart_port *up)
318{
319 struct circ_buf *xmit = &up->port.state->xmit;
320
321 if (SPORT_GET_STAT(up) & TXF)
322 return 0;
323
324 if (up->port.x_char) {
325 tx_one_byte(up, up->port.x_char);
326 up->port.icount.tx++;
327 up->port.x_char = 0;
328 return 1;
329 }
330
331 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
332 /* The waiting loop to stop SPORT TX from TX interrupt is
333 * too long. This may block SPORT RX interrupts and cause
334 * RX FIFO overflow. So, do stop sport TX only after the last
335 * char in TX FIFO is moved into the shift register.
336 */
337 if (SPORT_GET_STAT(up) & TXHRE)
338 sport_stop_tx(&up->port);
339 return 0;
340 }
341
342 while(!(SPORT_GET_STAT(up) & TXF) && !uart_circ_empty(xmit)) {
343 tx_one_byte(up, xmit->buf[xmit->tail]);
344 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1);
345 up->port.icount.tx++;
346 }
347
348 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
349 uart_write_wakeup(&up->port);
350
351 return 1;
352}
353
354static unsigned int sport_tx_empty(struct uart_port *port)
355{
356 struct sport_uart_port *up = (struct sport_uart_port *)port;
357 unsigned int stat;
358
359 stat = SPORT_GET_STAT(up);
360 pr_debug("%s stat:%04x\n", __func__, stat);
361 if (stat & TXHRE) {
362 return TIOCSER_TEMT;
363 } else
364 return 0;
365}
366
367static void sport_stop_tx(struct uart_port *port)
368{
369 struct sport_uart_port *up = (struct sport_uart_port *)port;
370
371 pr_debug("%s enter\n", __func__);
372
373 if (!(SPORT_GET_TCR1(up) & TSPEN))
374 return;
375
376 /* Although the hold register is empty, last byte is still in shift
377 * register and not sent out yet. So, put a dummy data into TX FIFO.
378 * Then, sport tx stops when last byte is shift out and the dummy
379 * data is moved into the shift register.
380 */
381 SPORT_PUT_TX(up, 0xffff);
382 while (!(SPORT_GET_STAT(up) & TXHRE))
383 cpu_relax();
384
385 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
386 SSYNC();
387
388 return;
389}
390
391static void sport_start_tx(struct uart_port *port)
392{
393 struct sport_uart_port *up = (struct sport_uart_port *)port;
394
395 pr_debug("%s enter\n", __func__);
396
397 /* Write data into SPORT FIFO before enable SPROT to transmit */
398 if (sport_uart_tx_chars(up)) {
399 /* Enable transmit, then an interrupt will generated */
400 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
401 SSYNC();
402 }
403
404 pr_debug("%s exit\n", __func__);
405}
406
407static void sport_stop_rx(struct uart_port *port)
408{
409 struct sport_uart_port *up = (struct sport_uart_port *)port;
410
411 pr_debug("%s enter\n", __func__);
412 /* Disable sport to stop rx */
413 SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
414 SSYNC();
415}
416
417static void sport_enable_ms(struct uart_port *port)
418{
419 pr_debug("%s enter\n", __func__);
420}
421
422static void sport_break_ctl(struct uart_port *port, int break_state)
423{
424 pr_debug("%s enter\n", __func__);
425}
426
427static void sport_shutdown(struct uart_port *port)
428{
429 struct sport_uart_port *up = (struct sport_uart_port *)port;
430
431 dev_dbg(port->dev, "%s enter\n", __func__);
432
433 /* Disable sport */
434 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
435 SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
436 SSYNC();
437
438 free_irq(up->port.irq, up);
439 free_irq(up->port.irq+1, up);
440 free_irq(up->err_irq, up);
441#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
442 if (up->cts_pin >= 0)
443 free_irq(gpio_to_irq(up->cts_pin), up);
444#endif
445}
446
447static const char *sport_type(struct uart_port *port)
448{
449 struct sport_uart_port *up = (struct sport_uart_port *)port;
450
451 pr_debug("%s enter\n", __func__);
452 return up->port.type == PORT_BFIN_SPORT ? "BFIN-SPORT-UART" : NULL;
453}
454
455static void sport_release_port(struct uart_port *port)
456{
457 pr_debug("%s enter\n", __func__);
458}
459
460static int sport_request_port(struct uart_port *port)
461{
462 pr_debug("%s enter\n", __func__);
463 return 0;
464}
465
466static void sport_config_port(struct uart_port *port, int flags)
467{
468 struct sport_uart_port *up = (struct sport_uart_port *)port;
469
470 pr_debug("%s enter\n", __func__);
471 up->port.type = PORT_BFIN_SPORT;
472}
473
474static int sport_verify_port(struct uart_port *port, struct serial_struct *ser)
475{
476 pr_debug("%s enter\n", __func__);
477 return 0;
478}
479
480static void sport_set_termios(struct uart_port *port,
481 struct ktermios *termios, struct ktermios *old)
482{
483 struct sport_uart_port *up = (struct sport_uart_port *)port;
484 unsigned long flags;
485 int i;
486
487 pr_debug("%s enter, c_cflag:%08x\n", __func__, termios->c_cflag);
488
489 switch (termios->c_cflag & CSIZE) {
490 case CS8:
491 up->csize = 8;
492 break;
493 case CS7:
494 up->csize = 7;
495 break;
496 case CS6:
497 up->csize = 6;
498 break;
499 case CS5:
500 up->csize = 5;
501 break;
502 default:
503 pr_warning("requested word length not supported\n");
504 }
505
506 if (termios->c_cflag & CSTOPB) {
507 up->stopb = 1;
508 }
509 if (termios->c_cflag & PARENB) {
510 pr_warning("PAREN bits is not supported yet\n");
511 /* up->parib = 1; */
512 }
513
514 spin_lock_irqsave(&up->port.lock, flags);
515
516 port->read_status_mask = 0;
517
518 /*
519 * Characters to ignore
520 */
521 port->ignore_status_mask = 0;
522
523 /* RX extract mask */
524 up->rxmask = 0x01 | (((up->csize + up->stopb) * 2 - 1) << 0x8);
525 /* TX masks, 8 bit data and 1 bit stop for example:
526 * mask1 = b#0111111110
527 * mask2 = b#1000000000
528 */
529 for (i = 0, up->txmask1 = 0; i < up->csize; i++)
530 up->txmask1 |= (1<<i);
531 up->txmask2 = (1<<i);
532 if (up->stopb) {
533 ++i;
534 up->txmask2 |= (1<<i);
535 }
536 up->txmask1 <<= 1;
537 up->txmask2 <<= 1;
538 /* uart baud rate */
539 port->uartclk = uart_get_baud_rate(port, termios, old, 0, get_sclk()/16);
540
541 /* Disable UART */
542 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
543 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
544
545 sport_uart_setup(up, up->csize + up->stopb, port->uartclk);
546
547 /* driver TX line high after config, one dummy data is
548 * necessary to stop sport after shift one byte
549 */
550 SPORT_PUT_TX(up, 0xffff);
551 SPORT_PUT_TX(up, 0xffff);
552 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
553 SSYNC();
554 while (!(SPORT_GET_STAT(up) & TXHRE))
555 cpu_relax();
556 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
557 SSYNC();
558
559 /* Port speed changed, update the per-port timeout. */
560 uart_update_timeout(port, termios->c_cflag, port->uartclk);
561
562 /* Enable sport rx */
563 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) | RSPEN);
564 SSYNC();
565
566 spin_unlock_irqrestore(&up->port.lock, flags);
567}
568
569struct uart_ops sport_uart_ops = {
570 .tx_empty = sport_tx_empty,
571 .set_mctrl = sport_set_mctrl,
572 .get_mctrl = sport_get_mctrl,
573 .stop_tx = sport_stop_tx,
574 .start_tx = sport_start_tx,
575 .stop_rx = sport_stop_rx,
576 .enable_ms = sport_enable_ms,
577 .break_ctl = sport_break_ctl,
578 .startup = sport_startup,
579 .shutdown = sport_shutdown,
580 .set_termios = sport_set_termios,
581 .type = sport_type,
582 .release_port = sport_release_port,
583 .request_port = sport_request_port,
584 .config_port = sport_config_port,
585 .verify_port = sport_verify_port,
586};
587
588#define BFIN_SPORT_UART_MAX_PORTS 4
589
590static struct sport_uart_port *bfin_sport_uart_ports[BFIN_SPORT_UART_MAX_PORTS];
591
592#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
593#define CLASS_BFIN_SPORT_CONSOLE "bfin-sport-console"
594
595static int __init
596sport_uart_console_setup(struct console *co, char *options)
597{
598 struct sport_uart_port *up;
599 int baud = 57600;
600 int bits = 8;
601 int parity = 'n';
602# ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
603 int flow = 'r';
604# else
605 int flow = 'n';
606# endif
607
608 /* Check whether an invalid uart number has been specified */
609 if (co->index < 0 || co->index >= BFIN_SPORT_UART_MAX_PORTS)
610 return -ENODEV;
611
612 up = bfin_sport_uart_ports[co->index];
613 if (!up)
614 return -ENODEV;
615
616 if (options)
617 uart_parse_options(options, &baud, &parity, &bits, &flow);
618
619 return uart_set_options(&up->port, co, baud, parity, bits, flow);
620}
621
622static void sport_uart_console_putchar(struct uart_port *port, int ch)
623{
624 struct sport_uart_port *up = (struct sport_uart_port *)port;
625
626 while (SPORT_GET_STAT(up) & TXF)
627 barrier();
628
629 tx_one_byte(up, ch);
630}
631
632/*
633 * Interrupts are disabled on entering
634 */
635static void
636sport_uart_console_write(struct console *co, const char *s, unsigned int count)
637{
638 struct sport_uart_port *up = bfin_sport_uart_ports[co->index];
639 unsigned long flags;
640
641 spin_lock_irqsave(&up->port.lock, flags);
642
643 if (SPORT_GET_TCR1(up) & TSPEN)
644 uart_console_write(&up->port, s, count, sport_uart_console_putchar);
645 else {
646 /* dummy data to start sport */
647 while (SPORT_GET_STAT(up) & TXF)
648 barrier();
649 SPORT_PUT_TX(up, 0xffff);
650 /* Enable transmit, then an interrupt will generated */
651 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
652 SSYNC();
653
654 uart_console_write(&up->port, s, count, sport_uart_console_putchar);
655
656 /* Although the hold register is empty, last byte is still in shift
657 * register and not sent out yet. So, put a dummy data into TX FIFO.
658 * Then, sport tx stops when last byte is shift out and the dummy
659 * data is moved into the shift register.
660 */
661 while (SPORT_GET_STAT(up) & TXF)
662 barrier();
663 SPORT_PUT_TX(up, 0xffff);
664 while (!(SPORT_GET_STAT(up) & TXHRE))
665 barrier();
666
667 /* Stop sport tx transfer */
668 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
669 SSYNC();
670 }
671
672 spin_unlock_irqrestore(&up->port.lock, flags);
673}
674
675static struct uart_driver sport_uart_reg;
676
677static struct console sport_uart_console = {
678 .name = DEVICE_NAME,
679 .write = sport_uart_console_write,
680 .device = uart_console_device,
681 .setup = sport_uart_console_setup,
682 .flags = CON_PRINTBUFFER,
683 .index = -1,
684 .data = &sport_uart_reg,
685};
686
687#define SPORT_UART_CONSOLE (&sport_uart_console)
688#else
689#define SPORT_UART_CONSOLE NULL
690#endif /* CONFIG_SERIAL_BFIN_SPORT_CONSOLE */
691
692
693static struct uart_driver sport_uart_reg = {
694 .owner = THIS_MODULE,
695 .driver_name = DRV_NAME,
696 .dev_name = DEVICE_NAME,
697 .major = 204,
698 .minor = 84,
699 .nr = BFIN_SPORT_UART_MAX_PORTS,
700 .cons = SPORT_UART_CONSOLE,
701};
702
703#ifdef CONFIG_PM
704static int sport_uart_suspend(struct device *dev)
705{
706 struct sport_uart_port *sport = dev_get_drvdata(dev);
707
708 dev_dbg(dev, "%s enter\n", __func__);
709 if (sport)
710 uart_suspend_port(&sport_uart_reg, &sport->port);
711
712 return 0;
713}
714
715static int sport_uart_resume(struct device *dev)
716{
717 struct sport_uart_port *sport = dev_get_drvdata(dev);
718
719 dev_dbg(dev, "%s enter\n", __func__);
720 if (sport)
721 uart_resume_port(&sport_uart_reg, &sport->port);
722
723 return 0;
724}
725
726static struct dev_pm_ops bfin_sport_uart_dev_pm_ops = {
727 .suspend = sport_uart_suspend,
728 .resume = sport_uart_resume,
729};
730#endif
731
732static int __devinit sport_uart_probe(struct platform_device *pdev)
733{
734 struct resource *res;
735 struct sport_uart_port *sport;
736 int ret = 0;
737
738 dev_dbg(&pdev->dev, "%s enter\n", __func__);
739
740 if (pdev->id < 0 || pdev->id >= BFIN_SPORT_UART_MAX_PORTS) {
741 dev_err(&pdev->dev, "Wrong sport uart platform device id.\n");
742 return -ENOENT;
743 }
744
745 if (bfin_sport_uart_ports[pdev->id] == NULL) {
746 bfin_sport_uart_ports[pdev->id] =
747 kzalloc(sizeof(struct sport_uart_port), GFP_KERNEL);
748 sport = bfin_sport_uart_ports[pdev->id];
749 if (!sport) {
750 dev_err(&pdev->dev,
751 "Fail to malloc sport_uart_port\n");
752 return -ENOMEM;
753 }
754
755 ret = peripheral_request_list(
756 (unsigned short *)pdev->dev.platform_data, DRV_NAME);
757 if (ret) {
758 dev_err(&pdev->dev,
759 "Fail to request SPORT peripherals\n");
760 goto out_error_free_mem;
761 }
762
763 spin_lock_init(&sport->port.lock);
764 sport->port.fifosize = SPORT_TX_FIFO_SIZE,
765 sport->port.ops = &sport_uart_ops;
766 sport->port.line = pdev->id;
767 sport->port.iotype = UPIO_MEM;
768 sport->port.flags = UPF_BOOT_AUTOCONF;
769
770 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
771 if (res == NULL) {
772 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
773 ret = -ENOENT;
774 goto out_error_free_peripherals;
775 }
776
777 sport->port.membase = ioremap(res->start, resource_size(res));
778 if (!sport->port.membase) {
779 dev_err(&pdev->dev, "Cannot map sport IO\n");
780 ret = -ENXIO;
781 goto out_error_free_peripherals;
782 }
783 sport->port.mapbase = res->start;
784
785 sport->port.irq = platform_get_irq(pdev, 0);
786 if (sport->port.irq < 0) {
787 dev_err(&pdev->dev, "No sport RX/TX IRQ specified\n");
788 ret = -ENOENT;
789 goto out_error_unmap;
790 }
791
792 sport->err_irq = platform_get_irq(pdev, 1);
793 if (sport->err_irq < 0) {
794 dev_err(&pdev->dev, "No sport status IRQ specified\n");
795 ret = -ENOENT;
796 goto out_error_unmap;
797 }
798#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
799 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
800 if (res == NULL)
801 sport->cts_pin = -1;
802 else
803 sport->cts_pin = res->start;
804
805 res = platform_get_resource(pdev, IORESOURCE_IO, 1);
806 if (res == NULL)
807 sport->rts_pin = -1;
808 else
809 sport->rts_pin = res->start;
810
811 if (sport->rts_pin >= 0)
812 gpio_request(sport->rts_pin, DRV_NAME);
813#endif
814 }
815
816#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
817 if (!is_early_platform_device(pdev)) {
818#endif
819 sport = bfin_sport_uart_ports[pdev->id];
820 sport->port.dev = &pdev->dev;
821 dev_set_drvdata(&pdev->dev, sport);
822 ret = uart_add_one_port(&sport_uart_reg, &sport->port);
823#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
824 }
825#endif
826 if (!ret)
827 return 0;
828
829 if (sport) {
830out_error_unmap:
831 iounmap(sport->port.membase);
832out_error_free_peripherals:
833 peripheral_free_list(
834 (unsigned short *)pdev->dev.platform_data);
835out_error_free_mem:
836 kfree(sport);
837 bfin_sport_uart_ports[pdev->id] = NULL;
838 }
839
840 return ret;
841}
842
843static int __devexit sport_uart_remove(struct platform_device *pdev)
844{
845 struct sport_uart_port *sport = platform_get_drvdata(pdev);
846
847 dev_dbg(&pdev->dev, "%s enter\n", __func__);
848 dev_set_drvdata(&pdev->dev, NULL);
849
850 if (sport) {
851 uart_remove_one_port(&sport_uart_reg, &sport->port);
852#ifdef CONFIG_SERIAL_BFIN_CTSRTS
853 if (sport->rts_pin >= 0)
854 gpio_free(sport->rts_pin);
855#endif
856 iounmap(sport->port.membase);
857 peripheral_free_list(
858 (unsigned short *)pdev->dev.platform_data);
859 kfree(sport);
860 bfin_sport_uart_ports[pdev->id] = NULL;
861 }
862
863 return 0;
864}
865
866static struct platform_driver sport_uart_driver = {
867 .probe = sport_uart_probe,
868 .remove = __devexit_p(sport_uart_remove),
869 .driver = {
870 .name = DRV_NAME,
871#ifdef CONFIG_PM
872 .pm = &bfin_sport_uart_dev_pm_ops,
873#endif
874 },
875};
876
877#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
878static __initdata struct early_platform_driver early_sport_uart_driver = {
879 .class_str = CLASS_BFIN_SPORT_CONSOLE,
880 .pdrv = &sport_uart_driver,
881 .requested_id = EARLY_PLATFORM_ID_UNSET,
882};
883
884static int __init sport_uart_rs_console_init(void)
885{
886 early_platform_driver_register(&early_sport_uart_driver, DRV_NAME);
887
888 early_platform_driver_probe(CLASS_BFIN_SPORT_CONSOLE,
889 BFIN_SPORT_UART_MAX_PORTS, 0);
890
891 register_console(&sport_uart_console);
892
893 return 0;
894}
895console_initcall(sport_uart_rs_console_init);
896#endif
897
898static int __init sport_uart_init(void)
899{
900 int ret;
901
902 pr_info("Blackfin uart over sport driver\n");
903
904 ret = uart_register_driver(&sport_uart_reg);
905 if (ret) {
906 pr_err("failed to register %s:%d\n",
907 sport_uart_reg.driver_name, ret);
908 return ret;
909 }
910
911 ret = platform_driver_register(&sport_uart_driver);
912 if (ret) {
913 pr_err("failed to register sport uart driver:%d\n", ret);
914 uart_unregister_driver(&sport_uart_reg);
915 }
916
917 return ret;
918}
919module_init(sport_uart_init);
920
921static void __exit sport_uart_exit(void)
922{
923 platform_driver_unregister(&sport_uart_driver);
924 uart_unregister_driver(&sport_uart_reg);
925}
926module_exit(sport_uart_exit);
927
928MODULE_AUTHOR("Sonic Zhang, Roy Huang");
929MODULE_DESCRIPTION("Blackfin serial over SPORT driver");
930MODULE_LICENSE("GPL");
diff --git a/drivers/serial/bfin_sport_uart.h b/drivers/serial/bfin_sport_uart.h
deleted file mode 100644
index 9ce253e381d2..000000000000
--- a/drivers/serial/bfin_sport_uart.h
+++ /dev/null
@@ -1,86 +0,0 @@
1/*
2 * Blackfin On-Chip Sport Emulated UART Driver
3 *
4 * Copyright 2006-2008 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11/*
12 * This driver and the hardware supported are in term of EE-191 of ADI.
13 * http://www.analog.com/UploadedFiles/Application_Notes/399447663EE191.pdf
14 * This application note describe how to implement a UART on a Sharc DSP,
15 * but this driver is implemented on Blackfin Processor.
16 * Transmit Frame Sync is not used by this driver to transfer data out.
17 */
18
19#ifndef _BFIN_SPORT_UART_H
20#define _BFIN_SPORT_UART_H
21
22#define OFFSET_TCR1 0x00 /* Transmit Configuration 1 Register */
23#define OFFSET_TCR2 0x04 /* Transmit Configuration 2 Register */
24#define OFFSET_TCLKDIV 0x08 /* Transmit Serial Clock Divider Register */
25#define OFFSET_TFSDIV 0x0C /* Transmit Frame Sync Divider Register */
26#define OFFSET_TX 0x10 /* Transmit Data Register */
27#define OFFSET_RX 0x18 /* Receive Data Register */
28#define OFFSET_RCR1 0x20 /* Receive Configuration 1 Register */
29#define OFFSET_RCR2 0x24 /* Receive Configuration 2 Register */
30#define OFFSET_RCLKDIV 0x28 /* Receive Serial Clock Divider Register */
31#define OFFSET_RFSDIV 0x2c /* Receive Frame Sync Divider Register */
32#define OFFSET_STAT 0x30 /* Status Register */
33
34#define SPORT_GET_TCR1(sport) bfin_read16(((sport)->port.membase + OFFSET_TCR1))
35#define SPORT_GET_TCR2(sport) bfin_read16(((sport)->port.membase + OFFSET_TCR2))
36#define SPORT_GET_TCLKDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_TCLKDIV))
37#define SPORT_GET_TFSDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_TFSDIV))
38#define SPORT_GET_TX(sport) bfin_read16(((sport)->port.membase + OFFSET_TX))
39#define SPORT_GET_RX(sport) bfin_read16(((sport)->port.membase + OFFSET_RX))
40/*
41 * If another interrupt fires while doing a 32-bit read from RX FIFO,
42 * a fake RX underflow error will be generated. So disable interrupts
43 * to prevent interruption while reading the FIFO.
44 */
45#define SPORT_GET_RX32(sport) \
46({ \
47 unsigned int __ret; \
48 if (ANOMALY_05000473) \
49 local_irq_disable(); \
50 __ret = bfin_read32((sport)->port.membase + OFFSET_RX); \
51 if (ANOMALY_05000473) \
52 local_irq_enable(); \
53 __ret; \
54})
55#define SPORT_GET_RCR1(sport) bfin_read16(((sport)->port.membase + OFFSET_RCR1))
56#define SPORT_GET_RCR2(sport) bfin_read16(((sport)->port.membase + OFFSET_RCR2))
57#define SPORT_GET_RCLKDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_RCLKDIV))
58#define SPORT_GET_RFSDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_RFSDIV))
59#define SPORT_GET_STAT(sport) bfin_read16(((sport)->port.membase + OFFSET_STAT))
60
61#define SPORT_PUT_TCR1(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCR1), v)
62#define SPORT_PUT_TCR2(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCR2), v)
63#define SPORT_PUT_TCLKDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCLKDIV), v)
64#define SPORT_PUT_TFSDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TFSDIV), v)
65#define SPORT_PUT_TX(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TX), v)
66#define SPORT_PUT_RX(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RX), v)
67#define SPORT_PUT_RCR1(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCR1), v)
68#define SPORT_PUT_RCR2(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCR2), v)
69#define SPORT_PUT_RCLKDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCLKDIV), v)
70#define SPORT_PUT_RFSDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RFSDIV), v)
71#define SPORT_PUT_STAT(sport, v) bfin_write16(((sport)->port.membase + OFFSET_STAT), v)
72
73#define SPORT_TX_FIFO_SIZE 8
74
75#define SPORT_UART_GET_CTS(x) gpio_get_value(x->cts_pin)
76#define SPORT_UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
77#define SPORT_UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
78
79#if defined(CONFIG_SERIAL_BFIN_SPORT0_UART_CTSRTS) \
80 || defined(CONFIG_SERIAL_BFIN_SPORT1_UART_CTSRTS) \
81 || defined(CONFIG_SERIAL_BFIN_SPORT2_UART_CTSRTS) \
82 || defined(CONFIG_SERIAL_BFIN_SPORT3_UART_CTSRTS)
83# define CONFIG_SERIAL_BFIN_SPORT_CTSRTS
84#endif
85
86#endif /* _BFIN_SPORT_UART_H */
diff --git a/drivers/serial/clps711x.c b/drivers/serial/clps711x.c
deleted file mode 100644
index b6acd19b458e..000000000000
--- a/drivers/serial/clps711x.c
+++ /dev/null
@@ -1,579 +0,0 @@
1/*
2 * linux/drivers/char/clps711x.c
3 *
4 * Driver for CLPS711x serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright 1999 ARM Limited
9 * Copyright (C) 2000 Deep Blue Solutions Ltd.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25
26#if defined(CONFIG_SERIAL_CLPS711X_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
27#define SUPPORT_SYSRQ
28#endif
29
30#include <linux/module.h>
31#include <linux/ioport.h>
32#include <linux/init.h>
33#include <linux/console.h>
34#include <linux/sysrq.h>
35#include <linux/spinlock.h>
36#include <linux/device.h>
37#include <linux/tty.h>
38#include <linux/tty_flip.h>
39#include <linux/serial_core.h>
40#include <linux/serial.h>
41#include <linux/io.h>
42
43#include <mach/hardware.h>
44#include <asm/irq.h>
45#include <asm/hardware/clps7111.h>
46
47#define UART_NR 2
48
49#define SERIAL_CLPS711X_MAJOR 204
50#define SERIAL_CLPS711X_MINOR 40
51#define SERIAL_CLPS711X_NR UART_NR
52
53/*
54 * We use the relevant SYSCON register as a base address for these ports.
55 */
56#define UBRLCR(port) ((port)->iobase + UBRLCR1 - SYSCON1)
57#define UARTDR(port) ((port)->iobase + UARTDR1 - SYSCON1)
58#define SYSFLG(port) ((port)->iobase + SYSFLG1 - SYSCON1)
59#define SYSCON(port) ((port)->iobase + SYSCON1 - SYSCON1)
60
61#define TX_IRQ(port) ((port)->irq)
62#define RX_IRQ(port) ((port)->irq + 1)
63
64#define UART_ANY_ERR (UARTDR_FRMERR | UARTDR_PARERR | UARTDR_OVERR)
65
66#define tx_enabled(port) ((port)->unused[0])
67
68static void clps711xuart_stop_tx(struct uart_port *port)
69{
70 if (tx_enabled(port)) {
71 disable_irq(TX_IRQ(port));
72 tx_enabled(port) = 0;
73 }
74}
75
76static void clps711xuart_start_tx(struct uart_port *port)
77{
78 if (!tx_enabled(port)) {
79 enable_irq(TX_IRQ(port));
80 tx_enabled(port) = 1;
81 }
82}
83
84static void clps711xuart_stop_rx(struct uart_port *port)
85{
86 disable_irq(RX_IRQ(port));
87}
88
89static void clps711xuart_enable_ms(struct uart_port *port)
90{
91}
92
93static irqreturn_t clps711xuart_int_rx(int irq, void *dev_id)
94{
95 struct uart_port *port = dev_id;
96 struct tty_struct *tty = port->state->port.tty;
97 unsigned int status, ch, flg;
98
99 status = clps_readl(SYSFLG(port));
100 while (!(status & SYSFLG_URXFE)) {
101 ch = clps_readl(UARTDR(port));
102
103 port->icount.rx++;
104
105 flg = TTY_NORMAL;
106
107 /*
108 * Note that the error handling code is
109 * out of the main execution path
110 */
111 if (unlikely(ch & UART_ANY_ERR)) {
112 if (ch & UARTDR_PARERR)
113 port->icount.parity++;
114 else if (ch & UARTDR_FRMERR)
115 port->icount.frame++;
116 if (ch & UARTDR_OVERR)
117 port->icount.overrun++;
118
119 ch &= port->read_status_mask;
120
121 if (ch & UARTDR_PARERR)
122 flg = TTY_PARITY;
123 else if (ch & UARTDR_FRMERR)
124 flg = TTY_FRAME;
125
126#ifdef SUPPORT_SYSRQ
127 port->sysrq = 0;
128#endif
129 }
130
131 if (uart_handle_sysrq_char(port, ch))
132 goto ignore_char;
133
134 /*
135 * CHECK: does overrun affect the current character?
136 * ASSUMPTION: it does not.
137 */
138 uart_insert_char(port, ch, UARTDR_OVERR, ch, flg);
139
140 ignore_char:
141 status = clps_readl(SYSFLG(port));
142 }
143 tty_flip_buffer_push(tty);
144 return IRQ_HANDLED;
145}
146
147static irqreturn_t clps711xuart_int_tx(int irq, void *dev_id)
148{
149 struct uart_port *port = dev_id;
150 struct circ_buf *xmit = &port->state->xmit;
151 int count;
152
153 if (port->x_char) {
154 clps_writel(port->x_char, UARTDR(port));
155 port->icount.tx++;
156 port->x_char = 0;
157 return IRQ_HANDLED;
158 }
159 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
160 clps711xuart_stop_tx(port);
161 return IRQ_HANDLED;
162 }
163
164 count = port->fifosize >> 1;
165 do {
166 clps_writel(xmit->buf[xmit->tail], UARTDR(port));
167 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
168 port->icount.tx++;
169 if (uart_circ_empty(xmit))
170 break;
171 } while (--count > 0);
172
173 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
174 uart_write_wakeup(port);
175
176 if (uart_circ_empty(xmit))
177 clps711xuart_stop_tx(port);
178
179 return IRQ_HANDLED;
180}
181
182static unsigned int clps711xuart_tx_empty(struct uart_port *port)
183{
184 unsigned int status = clps_readl(SYSFLG(port));
185 return status & SYSFLG_UBUSY ? 0 : TIOCSER_TEMT;
186}
187
188static unsigned int clps711xuart_get_mctrl(struct uart_port *port)
189{
190 unsigned int port_addr;
191 unsigned int result = 0;
192 unsigned int status;
193
194 port_addr = SYSFLG(port);
195 if (port_addr == SYSFLG1) {
196 status = clps_readl(SYSFLG1);
197 if (status & SYSFLG1_DCD)
198 result |= TIOCM_CAR;
199 if (status & SYSFLG1_DSR)
200 result |= TIOCM_DSR;
201 if (status & SYSFLG1_CTS)
202 result |= TIOCM_CTS;
203 }
204
205 return result;
206}
207
208static void
209clps711xuart_set_mctrl_null(struct uart_port *port, unsigned int mctrl)
210{
211}
212
213static void clps711xuart_break_ctl(struct uart_port *port, int break_state)
214{
215 unsigned long flags;
216 unsigned int ubrlcr;
217
218 spin_lock_irqsave(&port->lock, flags);
219 ubrlcr = clps_readl(UBRLCR(port));
220 if (break_state == -1)
221 ubrlcr |= UBRLCR_BREAK;
222 else
223 ubrlcr &= ~UBRLCR_BREAK;
224 clps_writel(ubrlcr, UBRLCR(port));
225 spin_unlock_irqrestore(&port->lock, flags);
226}
227
228static int clps711xuart_startup(struct uart_port *port)
229{
230 unsigned int syscon;
231 int retval;
232
233 tx_enabled(port) = 1;
234
235 /*
236 * Allocate the IRQs
237 */
238 retval = request_irq(TX_IRQ(port), clps711xuart_int_tx, 0,
239 "clps711xuart_tx", port);
240 if (retval)
241 return retval;
242
243 retval = request_irq(RX_IRQ(port), clps711xuart_int_rx, 0,
244 "clps711xuart_rx", port);
245 if (retval) {
246 free_irq(TX_IRQ(port), port);
247 return retval;
248 }
249
250 /*
251 * enable the port
252 */
253 syscon = clps_readl(SYSCON(port));
254 syscon |= SYSCON_UARTEN;
255 clps_writel(syscon, SYSCON(port));
256
257 return 0;
258}
259
260static void clps711xuart_shutdown(struct uart_port *port)
261{
262 unsigned int ubrlcr, syscon;
263
264 /*
265 * Free the interrupt
266 */
267 free_irq(TX_IRQ(port), port); /* TX interrupt */
268 free_irq(RX_IRQ(port), port); /* RX interrupt */
269
270 /*
271 * disable the port
272 */
273 syscon = clps_readl(SYSCON(port));
274 syscon &= ~SYSCON_UARTEN;
275 clps_writel(syscon, SYSCON(port));
276
277 /*
278 * disable break condition and fifos
279 */
280 ubrlcr = clps_readl(UBRLCR(port));
281 ubrlcr &= ~(UBRLCR_FIFOEN | UBRLCR_BREAK);
282 clps_writel(ubrlcr, UBRLCR(port));
283}
284
285static void
286clps711xuart_set_termios(struct uart_port *port, struct ktermios *termios,
287 struct ktermios *old)
288{
289 unsigned int ubrlcr, baud, quot;
290 unsigned long flags;
291
292 /*
293 * We don't implement CREAD.
294 */
295 termios->c_cflag |= CREAD;
296
297 /*
298 * Ask the core to calculate the divisor for us.
299 */
300 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
301 quot = uart_get_divisor(port, baud);
302
303 switch (termios->c_cflag & CSIZE) {
304 case CS5:
305 ubrlcr = UBRLCR_WRDLEN5;
306 break;
307 case CS6:
308 ubrlcr = UBRLCR_WRDLEN6;
309 break;
310 case CS7:
311 ubrlcr = UBRLCR_WRDLEN7;
312 break;
313 default: // CS8
314 ubrlcr = UBRLCR_WRDLEN8;
315 break;
316 }
317 if (termios->c_cflag & CSTOPB)
318 ubrlcr |= UBRLCR_XSTOP;
319 if (termios->c_cflag & PARENB) {
320 ubrlcr |= UBRLCR_PRTEN;
321 if (!(termios->c_cflag & PARODD))
322 ubrlcr |= UBRLCR_EVENPRT;
323 }
324 if (port->fifosize > 1)
325 ubrlcr |= UBRLCR_FIFOEN;
326
327 spin_lock_irqsave(&port->lock, flags);
328
329 /*
330 * Update the per-port timeout.
331 */
332 uart_update_timeout(port, termios->c_cflag, baud);
333
334 port->read_status_mask = UARTDR_OVERR;
335 if (termios->c_iflag & INPCK)
336 port->read_status_mask |= UARTDR_PARERR | UARTDR_FRMERR;
337
338 /*
339 * Characters to ignore
340 */
341 port->ignore_status_mask = 0;
342 if (termios->c_iflag & IGNPAR)
343 port->ignore_status_mask |= UARTDR_FRMERR | UARTDR_PARERR;
344 if (termios->c_iflag & IGNBRK) {
345 /*
346 * If we're ignoring parity and break indicators,
347 * ignore overruns to (for real raw support).
348 */
349 if (termios->c_iflag & IGNPAR)
350 port->ignore_status_mask |= UARTDR_OVERR;
351 }
352
353 quot -= 1;
354
355 clps_writel(ubrlcr | quot, UBRLCR(port));
356
357 spin_unlock_irqrestore(&port->lock, flags);
358}
359
360static const char *clps711xuart_type(struct uart_port *port)
361{
362 return port->type == PORT_CLPS711X ? "CLPS711x" : NULL;
363}
364
365/*
366 * Configure/autoconfigure the port.
367 */
368static void clps711xuart_config_port(struct uart_port *port, int flags)
369{
370 if (flags & UART_CONFIG_TYPE)
371 port->type = PORT_CLPS711X;
372}
373
374static void clps711xuart_release_port(struct uart_port *port)
375{
376}
377
378static int clps711xuart_request_port(struct uart_port *port)
379{
380 return 0;
381}
382
383static struct uart_ops clps711x_pops = {
384 .tx_empty = clps711xuart_tx_empty,
385 .set_mctrl = clps711xuart_set_mctrl_null,
386 .get_mctrl = clps711xuart_get_mctrl,
387 .stop_tx = clps711xuart_stop_tx,
388 .start_tx = clps711xuart_start_tx,
389 .stop_rx = clps711xuart_stop_rx,
390 .enable_ms = clps711xuart_enable_ms,
391 .break_ctl = clps711xuart_break_ctl,
392 .startup = clps711xuart_startup,
393 .shutdown = clps711xuart_shutdown,
394 .set_termios = clps711xuart_set_termios,
395 .type = clps711xuart_type,
396 .config_port = clps711xuart_config_port,
397 .release_port = clps711xuart_release_port,
398 .request_port = clps711xuart_request_port,
399};
400
401static struct uart_port clps711x_ports[UART_NR] = {
402 {
403 .iobase = SYSCON1,
404 .irq = IRQ_UTXINT1, /* IRQ_URXINT1, IRQ_UMSINT */
405 .uartclk = 3686400,
406 .fifosize = 16,
407 .ops = &clps711x_pops,
408 .line = 0,
409 .flags = UPF_BOOT_AUTOCONF,
410 },
411 {
412 .iobase = SYSCON2,
413 .irq = IRQ_UTXINT2, /* IRQ_URXINT2 */
414 .uartclk = 3686400,
415 .fifosize = 16,
416 .ops = &clps711x_pops,
417 .line = 1,
418 .flags = UPF_BOOT_AUTOCONF,
419 }
420};
421
422#ifdef CONFIG_SERIAL_CLPS711X_CONSOLE
423static void clps711xuart_console_putchar(struct uart_port *port, int ch)
424{
425 while (clps_readl(SYSFLG(port)) & SYSFLG_UTXFF)
426 barrier();
427 clps_writel(ch, UARTDR(port));
428}
429
430/*
431 * Print a string to the serial port trying not to disturb
432 * any possible real use of the port...
433 *
434 * The console_lock must be held when we get here.
435 *
436 * Note that this is called with interrupts already disabled
437 */
438static void
439clps711xuart_console_write(struct console *co, const char *s,
440 unsigned int count)
441{
442 struct uart_port *port = clps711x_ports + co->index;
443 unsigned int status, syscon;
444
445 /*
446 * Ensure that the port is enabled.
447 */
448 syscon = clps_readl(SYSCON(port));
449 clps_writel(syscon | SYSCON_UARTEN, SYSCON(port));
450
451 uart_console_write(port, s, count, clps711xuart_console_putchar);
452
453 /*
454 * Finally, wait for transmitter to become empty
455 * and restore the uart state.
456 */
457 do {
458 status = clps_readl(SYSFLG(port));
459 } while (status & SYSFLG_UBUSY);
460
461 clps_writel(syscon, SYSCON(port));
462}
463
464static void __init
465clps711xuart_console_get_options(struct uart_port *port, int *baud,
466 int *parity, int *bits)
467{
468 if (clps_readl(SYSCON(port)) & SYSCON_UARTEN) {
469 unsigned int ubrlcr, quot;
470
471 ubrlcr = clps_readl(UBRLCR(port));
472
473 *parity = 'n';
474 if (ubrlcr & UBRLCR_PRTEN) {
475 if (ubrlcr & UBRLCR_EVENPRT)
476 *parity = 'e';
477 else
478 *parity = 'o';
479 }
480
481 if ((ubrlcr & UBRLCR_WRDLEN_MASK) == UBRLCR_WRDLEN7)
482 *bits = 7;
483 else
484 *bits = 8;
485
486 quot = ubrlcr & UBRLCR_BAUD_MASK;
487 *baud = port->uartclk / (16 * (quot + 1));
488 }
489}
490
491static int __init clps711xuart_console_setup(struct console *co, char *options)
492{
493 struct uart_port *port;
494 int baud = 38400;
495 int bits = 8;
496 int parity = 'n';
497 int flow = 'n';
498
499 /*
500 * Check whether an invalid uart number has been specified, and
501 * if so, search for the first available port that does have
502 * console support.
503 */
504 port = uart_get_console(clps711x_ports, UART_NR, co);
505
506 if (options)
507 uart_parse_options(options, &baud, &parity, &bits, &flow);
508 else
509 clps711xuart_console_get_options(port, &baud, &parity, &bits);
510
511 return uart_set_options(port, co, baud, parity, bits, flow);
512}
513
514static struct uart_driver clps711x_reg;
515static struct console clps711x_console = {
516 .name = "ttyCL",
517 .write = clps711xuart_console_write,
518 .device = uart_console_device,
519 .setup = clps711xuart_console_setup,
520 .flags = CON_PRINTBUFFER,
521 .index = -1,
522 .data = &clps711x_reg,
523};
524
525static int __init clps711xuart_console_init(void)
526{
527 register_console(&clps711x_console);
528 return 0;
529}
530console_initcall(clps711xuart_console_init);
531
532#define CLPS711X_CONSOLE &clps711x_console
533#else
534#define CLPS711X_CONSOLE NULL
535#endif
536
537static struct uart_driver clps711x_reg = {
538 .driver_name = "ttyCL",
539 .dev_name = "ttyCL",
540 .major = SERIAL_CLPS711X_MAJOR,
541 .minor = SERIAL_CLPS711X_MINOR,
542 .nr = UART_NR,
543
544 .cons = CLPS711X_CONSOLE,
545};
546
547static int __init clps711xuart_init(void)
548{
549 int ret, i;
550
551 printk(KERN_INFO "Serial: CLPS711x driver\n");
552
553 ret = uart_register_driver(&clps711x_reg);
554 if (ret)
555 return ret;
556
557 for (i = 0; i < UART_NR; i++)
558 uart_add_one_port(&clps711x_reg, &clps711x_ports[i]);
559
560 return 0;
561}
562
563static void __exit clps711xuart_exit(void)
564{
565 int i;
566
567 for (i = 0; i < UART_NR; i++)
568 uart_remove_one_port(&clps711x_reg, &clps711x_ports[i]);
569
570 uart_unregister_driver(&clps711x_reg);
571}
572
573module_init(clps711xuart_init);
574module_exit(clps711xuart_exit);
575
576MODULE_AUTHOR("Deep Blue Solutions Ltd");
577MODULE_DESCRIPTION("CLPS-711x generic serial driver");
578MODULE_LICENSE("GPL");
579MODULE_ALIAS_CHARDEV(SERIAL_CLPS711X_MAJOR, SERIAL_CLPS711X_MINOR);
diff --git a/drivers/serial/cpm_uart/Makefile b/drivers/serial/cpm_uart/Makefile
deleted file mode 100644
index e072724ea754..000000000000
--- a/drivers/serial/cpm_uart/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
1#
2# Makefile for the Motorola 8xx FEC ethernet controller
3#
4
5obj-$(CONFIG_SERIAL_CPM) += cpm_uart.o
6
7# Select the correct platform objects.
8cpm_uart-objs-$(CONFIG_CPM2) += cpm_uart_cpm2.o
9cpm_uart-objs-$(CONFIG_8xx) += cpm_uart_cpm1.o
10
11cpm_uart-objs := cpm_uart_core.o $(cpm_uart-objs-y)
diff --git a/drivers/serial/cpm_uart/cpm_uart.h b/drivers/serial/cpm_uart/cpm_uart.h
deleted file mode 100644
index 7274b527a3c1..000000000000
--- a/drivers/serial/cpm_uart/cpm_uart.h
+++ /dev/null
@@ -1,153 +0,0 @@
1/*
2 * linux/drivers/serial/cpm_uart.h
3 *
4 * Driver for CPM (SCC/SMC) serial ports
5 *
6 * Copyright (C) 2004 Freescale Semiconductor, Inc.
7 *
8 * 2006 (c) MontaVista Software, Inc.
9 * Vitaly Bordug <vbordug@ru.mvista.com>
10 *
11 * This file is licensed under the terms of the GNU General Public License
12 * version 2. This program is licensed "as is" without any warranty of any
13 * kind, whether express or implied.
14 *
15 */
16#ifndef CPM_UART_H
17#define CPM_UART_H
18
19#include <linux/platform_device.h>
20#include <linux/fs_uart_pd.h>
21
22#if defined(CONFIG_CPM2)
23#include "cpm_uart_cpm2.h"
24#elif defined(CONFIG_8xx)
25#include "cpm_uart_cpm1.h"
26#endif
27
28#define SERIAL_CPM_MAJOR 204
29#define SERIAL_CPM_MINOR 46
30
31#define IS_SMC(pinfo) (pinfo->flags & FLAG_SMC)
32#define IS_DISCARDING(pinfo) (pinfo->flags & FLAG_DISCARDING)
33#define FLAG_DISCARDING 0x00000004 /* when set, don't discard */
34#define FLAG_SMC 0x00000002
35#define FLAG_CONSOLE 0x00000001
36
37#define UART_SMC1 fsid_smc1_uart
38#define UART_SMC2 fsid_smc2_uart
39#define UART_SCC1 fsid_scc1_uart
40#define UART_SCC2 fsid_scc2_uart
41#define UART_SCC3 fsid_scc3_uart
42#define UART_SCC4 fsid_scc4_uart
43
44#define UART_NR fs_uart_nr
45
46#define RX_NUM_FIFO 4
47#define RX_BUF_SIZE 32
48#define TX_NUM_FIFO 4
49#define TX_BUF_SIZE 32
50
51#define SCC_WAIT_CLOSING 100
52
53#define GPIO_CTS 0
54#define GPIO_RTS 1
55#define GPIO_DCD 2
56#define GPIO_DSR 3
57#define GPIO_DTR 4
58#define GPIO_RI 5
59
60#define NUM_GPIOS (GPIO_RI+1)
61
62struct uart_cpm_port {
63 struct uart_port port;
64 u16 rx_nrfifos;
65 u16 rx_fifosize;
66 u16 tx_nrfifos;
67 u16 tx_fifosize;
68 smc_t __iomem *smcp;
69 smc_uart_t __iomem *smcup;
70 scc_t __iomem *sccp;
71 scc_uart_t __iomem *sccup;
72 cbd_t __iomem *rx_bd_base;
73 cbd_t __iomem *rx_cur;
74 cbd_t __iomem *tx_bd_base;
75 cbd_t __iomem *tx_cur;
76 unsigned char *tx_buf;
77 unsigned char *rx_buf;
78 u32 flags;
79 void (*set_lineif)(struct uart_cpm_port *);
80 struct clk *clk;
81 u8 brg;
82 uint dp_addr;
83 void *mem_addr;
84 dma_addr_t dma_addr;
85 u32 mem_size;
86 /* helpers */
87 int baud;
88 int bits;
89 /* Keep track of 'odd' SMC2 wirings */
90 int is_portb;
91 /* wait on close if needed */
92 int wait_closing;
93 /* value to combine with opcode to form cpm command */
94 u32 command;
95 int gpios[NUM_GPIOS];
96};
97
98extern int cpm_uart_nr;
99extern struct uart_cpm_port cpm_uart_ports[UART_NR];
100
101/* these are located in their respective files */
102void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd);
103void __iomem *cpm_uart_map_pram(struct uart_cpm_port *port,
104 struct device_node *np);
105void cpm_uart_unmap_pram(struct uart_cpm_port *port, void __iomem *pram);
106int cpm_uart_init_portdesc(void);
107int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con);
108void cpm_uart_freebuf(struct uart_cpm_port *pinfo);
109
110void smc1_lineif(struct uart_cpm_port *pinfo);
111void smc2_lineif(struct uart_cpm_port *pinfo);
112void scc1_lineif(struct uart_cpm_port *pinfo);
113void scc2_lineif(struct uart_cpm_port *pinfo);
114void scc3_lineif(struct uart_cpm_port *pinfo);
115void scc4_lineif(struct uart_cpm_port *pinfo);
116
117/*
118 virtual to phys transtalion
119*/
120static inline unsigned long cpu2cpm_addr(void *addr,
121 struct uart_cpm_port *pinfo)
122{
123 int offset;
124 u32 val = (u32)addr;
125 u32 mem = (u32)pinfo->mem_addr;
126 /* sane check */
127 if (likely(val >= mem && val < mem + pinfo->mem_size)) {
128 offset = val - mem;
129 return pinfo->dma_addr + offset;
130 }
131 /* something nasty happened */
132 BUG();
133 return 0;
134}
135
136static inline void *cpm2cpu_addr(unsigned long addr,
137 struct uart_cpm_port *pinfo)
138{
139 int offset;
140 u32 val = addr;
141 u32 dma = (u32)pinfo->dma_addr;
142 /* sane check */
143 if (likely(val >= dma && val < dma + pinfo->mem_size)) {
144 offset = val - dma;
145 return pinfo->mem_addr + offset;
146 }
147 /* something nasty happened */
148 BUG();
149 return NULL;
150}
151
152
153#endif /* CPM_UART_H */
diff --git a/drivers/serial/cpm_uart/cpm_uart_core.c b/drivers/serial/cpm_uart/cpm_uart_core.c
deleted file mode 100644
index f2b8adcc6c92..000000000000
--- a/drivers/serial/cpm_uart/cpm_uart_core.c
+++ /dev/null
@@ -1,1424 +0,0 @@
1/*
2 * linux/drivers/serial/cpm_uart.c
3 *
4 * Driver for CPM (SCC/SMC) serial ports; core driver
5 *
6 * Based on arch/ppc/cpm2_io/uart.c by Dan Malek
7 * Based on ppc8xx.c by Thomas Gleixner
8 * Based on drivers/serial/amba.c by Russell King
9 *
10 * Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2)
11 * Pantelis Antoniou (panto@intracom.gr) (CPM1)
12 *
13 * Copyright (C) 2004, 2007 Freescale Semiconductor, Inc.
14 * (C) 2004 Intracom, S.A.
15 * (C) 2005-2006 MontaVista Software, Inc.
16 * Vitaly Bordug <vbordug@ru.mvista.com>
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 *
32 */
33
34#include <linux/module.h>
35#include <linux/tty.h>
36#include <linux/ioport.h>
37#include <linux/init.h>
38#include <linux/serial.h>
39#include <linux/console.h>
40#include <linux/sysrq.h>
41#include <linux/device.h>
42#include <linux/bootmem.h>
43#include <linux/dma-mapping.h>
44#include <linux/fs_uart_pd.h>
45#include <linux/of_platform.h>
46#include <linux/gpio.h>
47#include <linux/of_gpio.h>
48#include <linux/clk.h>
49
50#include <asm/io.h>
51#include <asm/irq.h>
52#include <asm/delay.h>
53#include <asm/fs_pd.h>
54#include <asm/udbg.h>
55
56#if defined(CONFIG_SERIAL_CPM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
57#define SUPPORT_SYSRQ
58#endif
59
60#include <linux/serial_core.h>
61#include <linux/kernel.h>
62
63#include "cpm_uart.h"
64
65
66/**************************************************************/
67
68static int cpm_uart_tx_pump(struct uart_port *port);
69static void cpm_uart_init_smc(struct uart_cpm_port *pinfo);
70static void cpm_uart_init_scc(struct uart_cpm_port *pinfo);
71static void cpm_uart_initbd(struct uart_cpm_port *pinfo);
72
73/**************************************************************/
74
75/*
76 * Check, if transmit buffers are processed
77*/
78static unsigned int cpm_uart_tx_empty(struct uart_port *port)
79{
80 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
81 cbd_t __iomem *bdp = pinfo->tx_bd_base;
82 int ret = 0;
83
84 while (1) {
85 if (in_be16(&bdp->cbd_sc) & BD_SC_READY)
86 break;
87
88 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) {
89 ret = TIOCSER_TEMT;
90 break;
91 }
92 bdp++;
93 }
94
95 pr_debug("CPM uart[%d]:tx_empty: %d\n", port->line, ret);
96
97 return ret;
98}
99
100static void cpm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
101{
102 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
103
104 if (pinfo->gpios[GPIO_RTS] >= 0)
105 gpio_set_value(pinfo->gpios[GPIO_RTS], !(mctrl & TIOCM_RTS));
106
107 if (pinfo->gpios[GPIO_DTR] >= 0)
108 gpio_set_value(pinfo->gpios[GPIO_DTR], !(mctrl & TIOCM_DTR));
109}
110
111static unsigned int cpm_uart_get_mctrl(struct uart_port *port)
112{
113 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
114 unsigned int mctrl = TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
115
116 if (pinfo->gpios[GPIO_CTS] >= 0) {
117 if (gpio_get_value(pinfo->gpios[GPIO_CTS]))
118 mctrl &= ~TIOCM_CTS;
119 }
120
121 if (pinfo->gpios[GPIO_DSR] >= 0) {
122 if (gpio_get_value(pinfo->gpios[GPIO_DSR]))
123 mctrl &= ~TIOCM_DSR;
124 }
125
126 if (pinfo->gpios[GPIO_DCD] >= 0) {
127 if (gpio_get_value(pinfo->gpios[GPIO_DCD]))
128 mctrl &= ~TIOCM_CAR;
129 }
130
131 if (pinfo->gpios[GPIO_RI] >= 0) {
132 if (!gpio_get_value(pinfo->gpios[GPIO_RI]))
133 mctrl |= TIOCM_RNG;
134 }
135
136 return mctrl;
137}
138
139/*
140 * Stop transmitter
141 */
142static void cpm_uart_stop_tx(struct uart_port *port)
143{
144 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
145 smc_t __iomem *smcp = pinfo->smcp;
146 scc_t __iomem *sccp = pinfo->sccp;
147
148 pr_debug("CPM uart[%d]:stop tx\n", port->line);
149
150 if (IS_SMC(pinfo))
151 clrbits8(&smcp->smc_smcm, SMCM_TX);
152 else
153 clrbits16(&sccp->scc_sccm, UART_SCCM_TX);
154}
155
156/*
157 * Start transmitter
158 */
159static void cpm_uart_start_tx(struct uart_port *port)
160{
161 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
162 smc_t __iomem *smcp = pinfo->smcp;
163 scc_t __iomem *sccp = pinfo->sccp;
164
165 pr_debug("CPM uart[%d]:start tx\n", port->line);
166
167 if (IS_SMC(pinfo)) {
168 if (in_8(&smcp->smc_smcm) & SMCM_TX)
169 return;
170 } else {
171 if (in_be16(&sccp->scc_sccm) & UART_SCCM_TX)
172 return;
173 }
174
175 if (cpm_uart_tx_pump(port) != 0) {
176 if (IS_SMC(pinfo)) {
177 setbits8(&smcp->smc_smcm, SMCM_TX);
178 } else {
179 setbits16(&sccp->scc_sccm, UART_SCCM_TX);
180 }
181 }
182}
183
184/*
185 * Stop receiver
186 */
187static void cpm_uart_stop_rx(struct uart_port *port)
188{
189 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
190 smc_t __iomem *smcp = pinfo->smcp;
191 scc_t __iomem *sccp = pinfo->sccp;
192
193 pr_debug("CPM uart[%d]:stop rx\n", port->line);
194
195 if (IS_SMC(pinfo))
196 clrbits8(&smcp->smc_smcm, SMCM_RX);
197 else
198 clrbits16(&sccp->scc_sccm, UART_SCCM_RX);
199}
200
201/*
202 * Enable Modem status interrupts
203 */
204static void cpm_uart_enable_ms(struct uart_port *port)
205{
206 pr_debug("CPM uart[%d]:enable ms\n", port->line);
207}
208
209/*
210 * Generate a break.
211 */
212static void cpm_uart_break_ctl(struct uart_port *port, int break_state)
213{
214 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
215
216 pr_debug("CPM uart[%d]:break ctrl, break_state: %d\n", port->line,
217 break_state);
218
219 if (break_state)
220 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
221 else
222 cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX);
223}
224
225/*
226 * Transmit characters, refill buffer descriptor, if possible
227 */
228static void cpm_uart_int_tx(struct uart_port *port)
229{
230 pr_debug("CPM uart[%d]:TX INT\n", port->line);
231
232 cpm_uart_tx_pump(port);
233}
234
235#ifdef CONFIG_CONSOLE_POLL
236static int serial_polled;
237#endif
238
239/*
240 * Receive characters
241 */
242static void cpm_uart_int_rx(struct uart_port *port)
243{
244 int i;
245 unsigned char ch;
246 u8 *cp;
247 struct tty_struct *tty = port->state->port.tty;
248 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
249 cbd_t __iomem *bdp;
250 u16 status;
251 unsigned int flg;
252
253 pr_debug("CPM uart[%d]:RX INT\n", port->line);
254
255 /* Just loop through the closed BDs and copy the characters into
256 * the buffer.
257 */
258 bdp = pinfo->rx_cur;
259 for (;;) {
260#ifdef CONFIG_CONSOLE_POLL
261 if (unlikely(serial_polled)) {
262 serial_polled = 0;
263 return;
264 }
265#endif
266 /* get status */
267 status = in_be16(&bdp->cbd_sc);
268 /* If this one is empty, return happy */
269 if (status & BD_SC_EMPTY)
270 break;
271
272 /* get number of characters, and check spce in flip-buffer */
273 i = in_be16(&bdp->cbd_datlen);
274
275 /* If we have not enough room in tty flip buffer, then we try
276 * later, which will be the next rx-interrupt or a timeout
277 */
278 if(tty_buffer_request_room(tty, i) < i) {
279 printk(KERN_WARNING "No room in flip buffer\n");
280 return;
281 }
282
283 /* get pointer */
284 cp = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
285
286 /* loop through the buffer */
287 while (i-- > 0) {
288 ch = *cp++;
289 port->icount.rx++;
290 flg = TTY_NORMAL;
291
292 if (status &
293 (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV))
294 goto handle_error;
295 if (uart_handle_sysrq_char(port, ch))
296 continue;
297#ifdef CONFIG_CONSOLE_POLL
298 if (unlikely(serial_polled)) {
299 serial_polled = 0;
300 return;
301 }
302#endif
303 error_return:
304 tty_insert_flip_char(tty, ch, flg);
305
306 } /* End while (i--) */
307
308 /* This BD is ready to be used again. Clear status. get next */
309 clrbits16(&bdp->cbd_sc, BD_SC_BR | BD_SC_FR | BD_SC_PR |
310 BD_SC_OV | BD_SC_ID);
311 setbits16(&bdp->cbd_sc, BD_SC_EMPTY);
312
313 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
314 bdp = pinfo->rx_bd_base;
315 else
316 bdp++;
317
318 } /* End for (;;) */
319
320 /* Write back buffer pointer */
321 pinfo->rx_cur = bdp;
322
323 /* activate BH processing */
324 tty_flip_buffer_push(tty);
325
326 return;
327
328 /* Error processing */
329
330 handle_error:
331 /* Statistics */
332 if (status & BD_SC_BR)
333 port->icount.brk++;
334 if (status & BD_SC_PR)
335 port->icount.parity++;
336 if (status & BD_SC_FR)
337 port->icount.frame++;
338 if (status & BD_SC_OV)
339 port->icount.overrun++;
340
341 /* Mask out ignored conditions */
342 status &= port->read_status_mask;
343
344 /* Handle the remaining ones */
345 if (status & BD_SC_BR)
346 flg = TTY_BREAK;
347 else if (status & BD_SC_PR)
348 flg = TTY_PARITY;
349 else if (status & BD_SC_FR)
350 flg = TTY_FRAME;
351
352 /* overrun does not affect the current character ! */
353 if (status & BD_SC_OV) {
354 ch = 0;
355 flg = TTY_OVERRUN;
356 /* We skip this buffer */
357 /* CHECK: Is really nothing senseful there */
358 /* ASSUMPTION: it contains nothing valid */
359 i = 0;
360 }
361#ifdef SUPPORT_SYSRQ
362 port->sysrq = 0;
363#endif
364 goto error_return;
365}
366
367/*
368 * Asynchron mode interrupt handler
369 */
370static irqreturn_t cpm_uart_int(int irq, void *data)
371{
372 u8 events;
373 struct uart_port *port = data;
374 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
375 smc_t __iomem *smcp = pinfo->smcp;
376 scc_t __iomem *sccp = pinfo->sccp;
377
378 pr_debug("CPM uart[%d]:IRQ\n", port->line);
379
380 if (IS_SMC(pinfo)) {
381 events = in_8(&smcp->smc_smce);
382 out_8(&smcp->smc_smce, events);
383 if (events & SMCM_BRKE)
384 uart_handle_break(port);
385 if (events & SMCM_RX)
386 cpm_uart_int_rx(port);
387 if (events & SMCM_TX)
388 cpm_uart_int_tx(port);
389 } else {
390 events = in_be16(&sccp->scc_scce);
391 out_be16(&sccp->scc_scce, events);
392 if (events & UART_SCCM_BRKE)
393 uart_handle_break(port);
394 if (events & UART_SCCM_RX)
395 cpm_uart_int_rx(port);
396 if (events & UART_SCCM_TX)
397 cpm_uart_int_tx(port);
398 }
399 return (events) ? IRQ_HANDLED : IRQ_NONE;
400}
401
402static int cpm_uart_startup(struct uart_port *port)
403{
404 int retval;
405 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
406
407 pr_debug("CPM uart[%d]:startup\n", port->line);
408
409 /* If the port is not the console, make sure rx is disabled. */
410 if (!(pinfo->flags & FLAG_CONSOLE)) {
411 /* Disable UART rx */
412 if (IS_SMC(pinfo)) {
413 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN);
414 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX);
415 } else {
416 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR);
417 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX);
418 }
419 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
420 }
421 /* Install interrupt handler. */
422 retval = request_irq(port->irq, cpm_uart_int, 0, "cpm_uart", port);
423 if (retval)
424 return retval;
425
426 /* Startup rx-int */
427 if (IS_SMC(pinfo)) {
428 setbits8(&pinfo->smcp->smc_smcm, SMCM_RX);
429 setbits16(&pinfo->smcp->smc_smcmr, (SMCMR_REN | SMCMR_TEN));
430 } else {
431 setbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX);
432 setbits32(&pinfo->sccp->scc_gsmrl, (SCC_GSMRL_ENR | SCC_GSMRL_ENT));
433 }
434
435 return 0;
436}
437
438inline void cpm_uart_wait_until_send(struct uart_cpm_port *pinfo)
439{
440 set_current_state(TASK_UNINTERRUPTIBLE);
441 schedule_timeout(pinfo->wait_closing);
442}
443
444/*
445 * Shutdown the uart
446 */
447static void cpm_uart_shutdown(struct uart_port *port)
448{
449 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
450
451 pr_debug("CPM uart[%d]:shutdown\n", port->line);
452
453 /* free interrupt handler */
454 free_irq(port->irq, port);
455
456 /* If the port is not the console, disable Rx and Tx. */
457 if (!(pinfo->flags & FLAG_CONSOLE)) {
458 /* Wait for all the BDs marked sent */
459 while(!cpm_uart_tx_empty(port)) {
460 set_current_state(TASK_UNINTERRUPTIBLE);
461 schedule_timeout(2);
462 }
463
464 if (pinfo->wait_closing)
465 cpm_uart_wait_until_send(pinfo);
466
467 /* Stop uarts */
468 if (IS_SMC(pinfo)) {
469 smc_t __iomem *smcp = pinfo->smcp;
470 clrbits16(&smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
471 clrbits8(&smcp->smc_smcm, SMCM_RX | SMCM_TX);
472 } else {
473 scc_t __iomem *sccp = pinfo->sccp;
474 clrbits32(&sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
475 clrbits16(&sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
476 }
477
478 /* Shut them really down and reinit buffer descriptors */
479 if (IS_SMC(pinfo)) {
480 out_be16(&pinfo->smcup->smc_brkcr, 0);
481 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
482 } else {
483 out_be16(&pinfo->sccup->scc_brkcr, 0);
484 cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX);
485 }
486
487 cpm_uart_initbd(pinfo);
488 }
489}
490
491static void cpm_uart_set_termios(struct uart_port *port,
492 struct ktermios *termios,
493 struct ktermios *old)
494{
495 int baud;
496 unsigned long flags;
497 u16 cval, scval, prev_mode;
498 int bits, sbits;
499 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
500 smc_t __iomem *smcp = pinfo->smcp;
501 scc_t __iomem *sccp = pinfo->sccp;
502
503 pr_debug("CPM uart[%d]:set_termios\n", port->line);
504
505 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
506
507 /* Character length programmed into the mode register is the
508 * sum of: 1 start bit, number of data bits, 0 or 1 parity bit,
509 * 1 or 2 stop bits, minus 1.
510 * The value 'bits' counts this for us.
511 */
512 cval = 0;
513 scval = 0;
514
515 /* byte size */
516 switch (termios->c_cflag & CSIZE) {
517 case CS5:
518 bits = 5;
519 break;
520 case CS6:
521 bits = 6;
522 break;
523 case CS7:
524 bits = 7;
525 break;
526 case CS8:
527 bits = 8;
528 break;
529 /* Never happens, but GCC is too dumb to figure it out */
530 default:
531 bits = 8;
532 break;
533 }
534 sbits = bits - 5;
535
536 if (termios->c_cflag & CSTOPB) {
537 cval |= SMCMR_SL; /* Two stops */
538 scval |= SCU_PSMR_SL;
539 bits++;
540 }
541
542 if (termios->c_cflag & PARENB) {
543 cval |= SMCMR_PEN;
544 scval |= SCU_PSMR_PEN;
545 bits++;
546 if (!(termios->c_cflag & PARODD)) {
547 cval |= SMCMR_PM_EVEN;
548 scval |= (SCU_PSMR_REVP | SCU_PSMR_TEVP);
549 }
550 }
551
552 /*
553 * Update the timeout
554 */
555 uart_update_timeout(port, termios->c_cflag, baud);
556
557 /*
558 * Set up parity check flag
559 */
560#define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
561
562 port->read_status_mask = (BD_SC_EMPTY | BD_SC_OV);
563 if (termios->c_iflag & INPCK)
564 port->read_status_mask |= BD_SC_FR | BD_SC_PR;
565 if ((termios->c_iflag & BRKINT) || (termios->c_iflag & PARMRK))
566 port->read_status_mask |= BD_SC_BR;
567
568 /*
569 * Characters to ignore
570 */
571 port->ignore_status_mask = 0;
572 if (termios->c_iflag & IGNPAR)
573 port->ignore_status_mask |= BD_SC_PR | BD_SC_FR;
574 if (termios->c_iflag & IGNBRK) {
575 port->ignore_status_mask |= BD_SC_BR;
576 /*
577 * If we're ignore parity and break indicators, ignore
578 * overruns too. (For real raw support).
579 */
580 if (termios->c_iflag & IGNPAR)
581 port->ignore_status_mask |= BD_SC_OV;
582 }
583 /*
584 * !!! ignore all characters if CREAD is not set
585 */
586 if ((termios->c_cflag & CREAD) == 0)
587 port->read_status_mask &= ~BD_SC_EMPTY;
588
589 spin_lock_irqsave(&port->lock, flags);
590
591 /* Start bit has not been added (so don't, because we would just
592 * subtract it later), and we need to add one for the number of
593 * stops bits (there is always at least one).
594 */
595 bits++;
596 if (IS_SMC(pinfo)) {
597 /* Set the mode register. We want to keep a copy of the
598 * enables, because we want to put them back if they were
599 * present.
600 */
601 prev_mode = in_be16(&smcp->smc_smcmr) & (SMCMR_REN | SMCMR_TEN);
602 /* Output in *one* operation, so we don't interrupt RX/TX if they
603 * were already enabled. */
604 out_be16(&smcp->smc_smcmr, smcr_mk_clen(bits) | cval |
605 SMCMR_SM_UART | prev_mode);
606 } else {
607 out_be16(&sccp->scc_psmr, (sbits << 12) | scval);
608 }
609
610 if (pinfo->clk)
611 clk_set_rate(pinfo->clk, baud);
612 else
613 cpm_set_brg(pinfo->brg - 1, baud);
614 spin_unlock_irqrestore(&port->lock, flags);
615}
616
617static const char *cpm_uart_type(struct uart_port *port)
618{
619 pr_debug("CPM uart[%d]:uart_type\n", port->line);
620
621 return port->type == PORT_CPM ? "CPM UART" : NULL;
622}
623
624/*
625 * verify the new serial_struct (for TIOCSSERIAL).
626 */
627static int cpm_uart_verify_port(struct uart_port *port,
628 struct serial_struct *ser)
629{
630 int ret = 0;
631
632 pr_debug("CPM uart[%d]:verify_port\n", port->line);
633
634 if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM)
635 ret = -EINVAL;
636 if (ser->irq < 0 || ser->irq >= nr_irqs)
637 ret = -EINVAL;
638 if (ser->baud_base < 9600)
639 ret = -EINVAL;
640 return ret;
641}
642
643/*
644 * Transmit characters, refill buffer descriptor, if possible
645 */
646static int cpm_uart_tx_pump(struct uart_port *port)
647{
648 cbd_t __iomem *bdp;
649 u8 *p;
650 int count;
651 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
652 struct circ_buf *xmit = &port->state->xmit;
653
654 /* Handle xon/xoff */
655 if (port->x_char) {
656 /* Pick next descriptor and fill from buffer */
657 bdp = pinfo->tx_cur;
658
659 p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
660
661 *p++ = port->x_char;
662
663 out_be16(&bdp->cbd_datlen, 1);
664 setbits16(&bdp->cbd_sc, BD_SC_READY);
665 /* Get next BD. */
666 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
667 bdp = pinfo->tx_bd_base;
668 else
669 bdp++;
670 pinfo->tx_cur = bdp;
671
672 port->icount.tx++;
673 port->x_char = 0;
674 return 1;
675 }
676
677 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
678 cpm_uart_stop_tx(port);
679 return 0;
680 }
681
682 /* Pick next descriptor and fill from buffer */
683 bdp = pinfo->tx_cur;
684
685 while (!(in_be16(&bdp->cbd_sc) & BD_SC_READY) &&
686 xmit->tail != xmit->head) {
687 count = 0;
688 p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
689 while (count < pinfo->tx_fifosize) {
690 *p++ = xmit->buf[xmit->tail];
691 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
692 port->icount.tx++;
693 count++;
694 if (xmit->head == xmit->tail)
695 break;
696 }
697 out_be16(&bdp->cbd_datlen, count);
698 setbits16(&bdp->cbd_sc, BD_SC_READY);
699 /* Get next BD. */
700 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
701 bdp = pinfo->tx_bd_base;
702 else
703 bdp++;
704 }
705 pinfo->tx_cur = bdp;
706
707 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
708 uart_write_wakeup(port);
709
710 if (uart_circ_empty(xmit)) {
711 cpm_uart_stop_tx(port);
712 return 0;
713 }
714
715 return 1;
716}
717
718/*
719 * init buffer descriptors
720 */
721static void cpm_uart_initbd(struct uart_cpm_port *pinfo)
722{
723 int i;
724 u8 *mem_addr;
725 cbd_t __iomem *bdp;
726
727 pr_debug("CPM uart[%d]:initbd\n", pinfo->port.line);
728
729 /* Set the physical address of the host memory
730 * buffers in the buffer descriptors, and the
731 * virtual address for us to work with.
732 */
733 mem_addr = pinfo->mem_addr;
734 bdp = pinfo->rx_cur = pinfo->rx_bd_base;
735 for (i = 0; i < (pinfo->rx_nrfifos - 1); i++, bdp++) {
736 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
737 out_be16(&bdp->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT);
738 mem_addr += pinfo->rx_fifosize;
739 }
740
741 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
742 out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT);
743
744 /* Set the physical address of the host memory
745 * buffers in the buffer descriptors, and the
746 * virtual address for us to work with.
747 */
748 mem_addr = pinfo->mem_addr + L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize);
749 bdp = pinfo->tx_cur = pinfo->tx_bd_base;
750 for (i = 0; i < (pinfo->tx_nrfifos - 1); i++, bdp++) {
751 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
752 out_be16(&bdp->cbd_sc, BD_SC_INTRPT);
753 mem_addr += pinfo->tx_fifosize;
754 }
755
756 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
757 out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_INTRPT);
758}
759
760static void cpm_uart_init_scc(struct uart_cpm_port *pinfo)
761{
762 scc_t __iomem *scp;
763 scc_uart_t __iomem *sup;
764
765 pr_debug("CPM uart[%d]:init_scc\n", pinfo->port.line);
766
767 scp = pinfo->sccp;
768 sup = pinfo->sccup;
769
770 /* Store address */
771 out_be16(&pinfo->sccup->scc_genscc.scc_rbase,
772 (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE);
773 out_be16(&pinfo->sccup->scc_genscc.scc_tbase,
774 (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE);
775
776 /* Set up the uart parameters in the
777 * parameter ram.
778 */
779
780 cpm_set_scc_fcr(sup);
781
782 out_be16(&sup->scc_genscc.scc_mrblr, pinfo->rx_fifosize);
783 out_be16(&sup->scc_maxidl, pinfo->rx_fifosize);
784 out_be16(&sup->scc_brkcr, 1);
785 out_be16(&sup->scc_parec, 0);
786 out_be16(&sup->scc_frmec, 0);
787 out_be16(&sup->scc_nosec, 0);
788 out_be16(&sup->scc_brkec, 0);
789 out_be16(&sup->scc_uaddr1, 0);
790 out_be16(&sup->scc_uaddr2, 0);
791 out_be16(&sup->scc_toseq, 0);
792 out_be16(&sup->scc_char1, 0x8000);
793 out_be16(&sup->scc_char2, 0x8000);
794 out_be16(&sup->scc_char3, 0x8000);
795 out_be16(&sup->scc_char4, 0x8000);
796 out_be16(&sup->scc_char5, 0x8000);
797 out_be16(&sup->scc_char6, 0x8000);
798 out_be16(&sup->scc_char7, 0x8000);
799 out_be16(&sup->scc_char8, 0x8000);
800 out_be16(&sup->scc_rccm, 0xc0ff);
801
802 /* Send the CPM an initialize command.
803 */
804 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
805
806 /* Set UART mode, 8 bit, no parity, one stop.
807 * Enable receive and transmit.
808 */
809 out_be32(&scp->scc_gsmrh, 0);
810 out_be32(&scp->scc_gsmrl,
811 SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
812
813 /* Enable rx interrupts and clear all pending events. */
814 out_be16(&scp->scc_sccm, 0);
815 out_be16(&scp->scc_scce, 0xffff);
816 out_be16(&scp->scc_dsr, 0x7e7e);
817 out_be16(&scp->scc_psmr, 0x3000);
818
819 setbits32(&scp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
820}
821
822static void cpm_uart_init_smc(struct uart_cpm_port *pinfo)
823{
824 smc_t __iomem *sp;
825 smc_uart_t __iomem *up;
826
827 pr_debug("CPM uart[%d]:init_smc\n", pinfo->port.line);
828
829 sp = pinfo->smcp;
830 up = pinfo->smcup;
831
832 /* Store address */
833 out_be16(&pinfo->smcup->smc_rbase,
834 (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE);
835 out_be16(&pinfo->smcup->smc_tbase,
836 (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE);
837
838/*
839 * In case SMC1 is being relocated...
840 */
841#if defined (CONFIG_I2C_SPI_SMC1_UCODE_PATCH)
842 out_be16(&up->smc_rbptr, in_be16(&pinfo->smcup->smc_rbase));
843 out_be16(&up->smc_tbptr, in_be16(&pinfo->smcup->smc_tbase));
844 out_be32(&up->smc_rstate, 0);
845 out_be32(&up->smc_tstate, 0);
846 out_be16(&up->smc_brkcr, 1); /* number of break chars */
847 out_be16(&up->smc_brkec, 0);
848#endif
849
850 /* Set up the uart parameters in the
851 * parameter ram.
852 */
853 cpm_set_smc_fcr(up);
854
855 /* Using idle character time requires some additional tuning. */
856 out_be16(&up->smc_mrblr, pinfo->rx_fifosize);
857 out_be16(&up->smc_maxidl, pinfo->rx_fifosize);
858 out_be16(&up->smc_brklen, 0);
859 out_be16(&up->smc_brkec, 0);
860 out_be16(&up->smc_brkcr, 1);
861
862 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
863
864 /* Set UART mode, 8 bit, no parity, one stop.
865 * Enable receive and transmit.
866 */
867 out_be16(&sp->smc_smcmr, smcr_mk_clen(9) | SMCMR_SM_UART);
868
869 /* Enable only rx interrupts clear all pending events. */
870 out_8(&sp->smc_smcm, 0);
871 out_8(&sp->smc_smce, 0xff);
872
873 setbits16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
874}
875
876/*
877 * Initialize port. This is called from early_console stuff
878 * so we have to be careful here !
879 */
880static int cpm_uart_request_port(struct uart_port *port)
881{
882 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
883 int ret;
884
885 pr_debug("CPM uart[%d]:request port\n", port->line);
886
887 if (pinfo->flags & FLAG_CONSOLE)
888 return 0;
889
890 if (IS_SMC(pinfo)) {
891 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX);
892 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
893 } else {
894 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
895 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
896 }
897
898 ret = cpm_uart_allocbuf(pinfo, 0);
899
900 if (ret)
901 return ret;
902
903 cpm_uart_initbd(pinfo);
904 if (IS_SMC(pinfo))
905 cpm_uart_init_smc(pinfo);
906 else
907 cpm_uart_init_scc(pinfo);
908
909 return 0;
910}
911
912static void cpm_uart_release_port(struct uart_port *port)
913{
914 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
915
916 if (!(pinfo->flags & FLAG_CONSOLE))
917 cpm_uart_freebuf(pinfo);
918}
919
920/*
921 * Configure/autoconfigure the port.
922 */
923static void cpm_uart_config_port(struct uart_port *port, int flags)
924{
925 pr_debug("CPM uart[%d]:config_port\n", port->line);
926
927 if (flags & UART_CONFIG_TYPE) {
928 port->type = PORT_CPM;
929 cpm_uart_request_port(port);
930 }
931}
932
933#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_CPM_CONSOLE)
934/*
935 * Write a string to the serial port
936 * Note that this is called with interrupts already disabled
937 */
938static void cpm_uart_early_write(struct uart_cpm_port *pinfo,
939 const char *string, u_int count)
940{
941 unsigned int i;
942 cbd_t __iomem *bdp, *bdbase;
943 unsigned char *cpm_outp_addr;
944
945 /* Get the address of the host memory buffer.
946 */
947 bdp = pinfo->tx_cur;
948 bdbase = pinfo->tx_bd_base;
949
950 /*
951 * Now, do each character. This is not as bad as it looks
952 * since this is a holding FIFO and not a transmitting FIFO.
953 * We could add the complexity of filling the entire transmit
954 * buffer, but we would just wait longer between accesses......
955 */
956 for (i = 0; i < count; i++, string++) {
957 /* Wait for transmitter fifo to empty.
958 * Ready indicates output is ready, and xmt is doing
959 * that, not that it is ready for us to send.
960 */
961 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
962 ;
963
964 /* Send the character out.
965 * If the buffer address is in the CPM DPRAM, don't
966 * convert it.
967 */
968 cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr),
969 pinfo);
970 *cpm_outp_addr = *string;
971
972 out_be16(&bdp->cbd_datlen, 1);
973 setbits16(&bdp->cbd_sc, BD_SC_READY);
974
975 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
976 bdp = bdbase;
977 else
978 bdp++;
979
980 /* if a LF, also do CR... */
981 if (*string == 10) {
982 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
983 ;
984
985 cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr),
986 pinfo);
987 *cpm_outp_addr = 13;
988
989 out_be16(&bdp->cbd_datlen, 1);
990 setbits16(&bdp->cbd_sc, BD_SC_READY);
991
992 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
993 bdp = bdbase;
994 else
995 bdp++;
996 }
997 }
998
999 /*
1000 * Finally, Wait for transmitter & holding register to empty
1001 * and restore the IER
1002 */
1003 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
1004 ;
1005
1006 pinfo->tx_cur = bdp;
1007}
1008#endif
1009
1010#ifdef CONFIG_CONSOLE_POLL
1011/* Serial polling routines for writing and reading from the uart while
1012 * in an interrupt or debug context.
1013 */
1014
1015#define GDB_BUF_SIZE 512 /* power of 2, please */
1016
1017static char poll_buf[GDB_BUF_SIZE];
1018static char *pollp;
1019static int poll_chars;
1020
1021static int poll_wait_key(char *obuf, struct uart_cpm_port *pinfo)
1022{
1023 u_char c, *cp;
1024 volatile cbd_t *bdp;
1025 int i;
1026
1027 /* Get the address of the host memory buffer.
1028 */
1029 bdp = pinfo->rx_cur;
1030 while (bdp->cbd_sc & BD_SC_EMPTY)
1031 ;
1032
1033 /* If the buffer address is in the CPM DPRAM, don't
1034 * convert it.
1035 */
1036 cp = cpm2cpu_addr(bdp->cbd_bufaddr, pinfo);
1037
1038 if (obuf) {
1039 i = c = bdp->cbd_datlen;
1040 while (i-- > 0)
1041 *obuf++ = *cp++;
1042 } else
1043 c = *cp;
1044 bdp->cbd_sc &= ~(BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID);
1045 bdp->cbd_sc |= BD_SC_EMPTY;
1046
1047 if (bdp->cbd_sc & BD_SC_WRAP)
1048 bdp = pinfo->rx_bd_base;
1049 else
1050 bdp++;
1051 pinfo->rx_cur = (cbd_t *)bdp;
1052
1053 return (int)c;
1054}
1055
1056static int cpm_get_poll_char(struct uart_port *port)
1057{
1058 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
1059
1060 if (!serial_polled) {
1061 serial_polled = 1;
1062 poll_chars = 0;
1063 }
1064 if (poll_chars <= 0) {
1065 poll_chars = poll_wait_key(poll_buf, pinfo);
1066 pollp = poll_buf;
1067 }
1068 poll_chars--;
1069 return *pollp++;
1070}
1071
1072static void cpm_put_poll_char(struct uart_port *port,
1073 unsigned char c)
1074{
1075 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
1076 static char ch[2];
1077
1078 ch[0] = (char)c;
1079 cpm_uart_early_write(pinfo, ch, 1);
1080}
1081#endif /* CONFIG_CONSOLE_POLL */
1082
1083static struct uart_ops cpm_uart_pops = {
1084 .tx_empty = cpm_uart_tx_empty,
1085 .set_mctrl = cpm_uart_set_mctrl,
1086 .get_mctrl = cpm_uart_get_mctrl,
1087 .stop_tx = cpm_uart_stop_tx,
1088 .start_tx = cpm_uart_start_tx,
1089 .stop_rx = cpm_uart_stop_rx,
1090 .enable_ms = cpm_uart_enable_ms,
1091 .break_ctl = cpm_uart_break_ctl,
1092 .startup = cpm_uart_startup,
1093 .shutdown = cpm_uart_shutdown,
1094 .set_termios = cpm_uart_set_termios,
1095 .type = cpm_uart_type,
1096 .release_port = cpm_uart_release_port,
1097 .request_port = cpm_uart_request_port,
1098 .config_port = cpm_uart_config_port,
1099 .verify_port = cpm_uart_verify_port,
1100#ifdef CONFIG_CONSOLE_POLL
1101 .poll_get_char = cpm_get_poll_char,
1102 .poll_put_char = cpm_put_poll_char,
1103#endif
1104};
1105
1106struct uart_cpm_port cpm_uart_ports[UART_NR];
1107
1108static int cpm_uart_init_port(struct device_node *np,
1109 struct uart_cpm_port *pinfo)
1110{
1111 const u32 *data;
1112 void __iomem *mem, *pram;
1113 int len;
1114 int ret;
1115 int i;
1116
1117 data = of_get_property(np, "clock", NULL);
1118 if (data) {
1119 struct clk *clk = clk_get(NULL, (const char*)data);
1120 if (!IS_ERR(clk))
1121 pinfo->clk = clk;
1122 }
1123 if (!pinfo->clk) {
1124 data = of_get_property(np, "fsl,cpm-brg", &len);
1125 if (!data || len != 4) {
1126 printk(KERN_ERR "CPM UART %s has no/invalid "
1127 "fsl,cpm-brg property.\n", np->name);
1128 return -EINVAL;
1129 }
1130 pinfo->brg = *data;
1131 }
1132
1133 data = of_get_property(np, "fsl,cpm-command", &len);
1134 if (!data || len != 4) {
1135 printk(KERN_ERR "CPM UART %s has no/invalid "
1136 "fsl,cpm-command property.\n", np->name);
1137 return -EINVAL;
1138 }
1139 pinfo->command = *data;
1140
1141 mem = of_iomap(np, 0);
1142 if (!mem)
1143 return -ENOMEM;
1144
1145 if (of_device_is_compatible(np, "fsl,cpm1-scc-uart") ||
1146 of_device_is_compatible(np, "fsl,cpm2-scc-uart")) {
1147 pinfo->sccp = mem;
1148 pinfo->sccup = pram = cpm_uart_map_pram(pinfo, np);
1149 } else if (of_device_is_compatible(np, "fsl,cpm1-smc-uart") ||
1150 of_device_is_compatible(np, "fsl,cpm2-smc-uart")) {
1151 pinfo->flags |= FLAG_SMC;
1152 pinfo->smcp = mem;
1153 pinfo->smcup = pram = cpm_uart_map_pram(pinfo, np);
1154 } else {
1155 ret = -ENODEV;
1156 goto out_mem;
1157 }
1158
1159 if (!pram) {
1160 ret = -ENOMEM;
1161 goto out_mem;
1162 }
1163
1164 pinfo->tx_nrfifos = TX_NUM_FIFO;
1165 pinfo->tx_fifosize = TX_BUF_SIZE;
1166 pinfo->rx_nrfifos = RX_NUM_FIFO;
1167 pinfo->rx_fifosize = RX_BUF_SIZE;
1168
1169 pinfo->port.uartclk = ppc_proc_freq;
1170 pinfo->port.mapbase = (unsigned long)mem;
1171 pinfo->port.type = PORT_CPM;
1172 pinfo->port.ops = &cpm_uart_pops,
1173 pinfo->port.iotype = UPIO_MEM;
1174 pinfo->port.fifosize = pinfo->tx_nrfifos * pinfo->tx_fifosize;
1175 spin_lock_init(&pinfo->port.lock);
1176
1177 pinfo->port.irq = of_irq_to_resource(np, 0, NULL);
1178 if (pinfo->port.irq == NO_IRQ) {
1179 ret = -EINVAL;
1180 goto out_pram;
1181 }
1182
1183 for (i = 0; i < NUM_GPIOS; i++)
1184 pinfo->gpios[i] = of_get_gpio(np, i);
1185
1186#ifdef CONFIG_PPC_EARLY_DEBUG_CPM
1187 udbg_putc = NULL;
1188#endif
1189
1190 return cpm_uart_request_port(&pinfo->port);
1191
1192out_pram:
1193 cpm_uart_unmap_pram(pinfo, pram);
1194out_mem:
1195 iounmap(mem);
1196 return ret;
1197}
1198
1199#ifdef CONFIG_SERIAL_CPM_CONSOLE
1200/*
1201 * Print a string to the serial port trying not to disturb
1202 * any possible real use of the port...
1203 *
1204 * Note that this is called with interrupts already disabled
1205 */
1206static void cpm_uart_console_write(struct console *co, const char *s,
1207 u_int count)
1208{
1209 struct uart_cpm_port *pinfo = &cpm_uart_ports[co->index];
1210 unsigned long flags;
1211 int nolock = oops_in_progress;
1212
1213 if (unlikely(nolock)) {
1214 local_irq_save(flags);
1215 } else {
1216 spin_lock_irqsave(&pinfo->port.lock, flags);
1217 }
1218
1219 cpm_uart_early_write(pinfo, s, count);
1220
1221 if (unlikely(nolock)) {
1222 local_irq_restore(flags);
1223 } else {
1224 spin_unlock_irqrestore(&pinfo->port.lock, flags);
1225 }
1226}
1227
1228
1229static int __init cpm_uart_console_setup(struct console *co, char *options)
1230{
1231 int baud = 38400;
1232 int bits = 8;
1233 int parity = 'n';
1234 int flow = 'n';
1235 int ret;
1236 struct uart_cpm_port *pinfo;
1237 struct uart_port *port;
1238
1239 struct device_node *np = NULL;
1240 int i = 0;
1241
1242 if (co->index >= UART_NR) {
1243 printk(KERN_ERR "cpm_uart: console index %d too high\n",
1244 co->index);
1245 return -ENODEV;
1246 }
1247
1248 do {
1249 np = of_find_node_by_type(np, "serial");
1250 if (!np)
1251 return -ENODEV;
1252
1253 if (!of_device_is_compatible(np, "fsl,cpm1-smc-uart") &&
1254 !of_device_is_compatible(np, "fsl,cpm1-scc-uart") &&
1255 !of_device_is_compatible(np, "fsl,cpm2-smc-uart") &&
1256 !of_device_is_compatible(np, "fsl,cpm2-scc-uart"))
1257 i--;
1258 } while (i++ != co->index);
1259
1260 pinfo = &cpm_uart_ports[co->index];
1261
1262 pinfo->flags |= FLAG_CONSOLE;
1263 port = &pinfo->port;
1264
1265 ret = cpm_uart_init_port(np, pinfo);
1266 of_node_put(np);
1267 if (ret)
1268 return ret;
1269
1270 if (options) {
1271 uart_parse_options(options, &baud, &parity, &bits, &flow);
1272 } else {
1273 if ((baud = uart_baudrate()) == -1)
1274 baud = 9600;
1275 }
1276
1277 if (IS_SMC(pinfo)) {
1278 out_be16(&pinfo->smcup->smc_brkcr, 0);
1279 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
1280 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX);
1281 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
1282 } else {
1283 out_be16(&pinfo->sccup->scc_brkcr, 0);
1284 cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX);
1285 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
1286 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
1287 }
1288
1289 ret = cpm_uart_allocbuf(pinfo, 1);
1290
1291 if (ret)
1292 return ret;
1293
1294 cpm_uart_initbd(pinfo);
1295
1296 if (IS_SMC(pinfo))
1297 cpm_uart_init_smc(pinfo);
1298 else
1299 cpm_uart_init_scc(pinfo);
1300
1301 uart_set_options(port, co, baud, parity, bits, flow);
1302 cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX);
1303
1304 return 0;
1305}
1306
1307static struct uart_driver cpm_reg;
1308static struct console cpm_scc_uart_console = {
1309 .name = "ttyCPM",
1310 .write = cpm_uart_console_write,
1311 .device = uart_console_device,
1312 .setup = cpm_uart_console_setup,
1313 .flags = CON_PRINTBUFFER,
1314 .index = -1,
1315 .data = &cpm_reg,
1316};
1317
1318static int __init cpm_uart_console_init(void)
1319{
1320 register_console(&cpm_scc_uart_console);
1321 return 0;
1322}
1323
1324console_initcall(cpm_uart_console_init);
1325
1326#define CPM_UART_CONSOLE &cpm_scc_uart_console
1327#else
1328#define CPM_UART_CONSOLE NULL
1329#endif
1330
1331static struct uart_driver cpm_reg = {
1332 .owner = THIS_MODULE,
1333 .driver_name = "ttyCPM",
1334 .dev_name = "ttyCPM",
1335 .major = SERIAL_CPM_MAJOR,
1336 .minor = SERIAL_CPM_MINOR,
1337 .cons = CPM_UART_CONSOLE,
1338 .nr = UART_NR,
1339};
1340
1341static int probe_index;
1342
1343static int __devinit cpm_uart_probe(struct platform_device *ofdev,
1344 const struct of_device_id *match)
1345{
1346 int index = probe_index++;
1347 struct uart_cpm_port *pinfo = &cpm_uart_ports[index];
1348 int ret;
1349
1350 pinfo->port.line = index;
1351
1352 if (index >= UART_NR)
1353 return -ENODEV;
1354
1355 dev_set_drvdata(&ofdev->dev, pinfo);
1356
1357 /* initialize the device pointer for the port */
1358 pinfo->port.dev = &ofdev->dev;
1359
1360 ret = cpm_uart_init_port(ofdev->dev.of_node, pinfo);
1361 if (ret)
1362 return ret;
1363
1364 return uart_add_one_port(&cpm_reg, &pinfo->port);
1365}
1366
1367static int __devexit cpm_uart_remove(struct platform_device *ofdev)
1368{
1369 struct uart_cpm_port *pinfo = dev_get_drvdata(&ofdev->dev);
1370 return uart_remove_one_port(&cpm_reg, &pinfo->port);
1371}
1372
1373static struct of_device_id cpm_uart_match[] = {
1374 {
1375 .compatible = "fsl,cpm1-smc-uart",
1376 },
1377 {
1378 .compatible = "fsl,cpm1-scc-uart",
1379 },
1380 {
1381 .compatible = "fsl,cpm2-smc-uart",
1382 },
1383 {
1384 .compatible = "fsl,cpm2-scc-uart",
1385 },
1386 {}
1387};
1388
1389static struct of_platform_driver cpm_uart_driver = {
1390 .driver = {
1391 .name = "cpm_uart",
1392 .owner = THIS_MODULE,
1393 .of_match_table = cpm_uart_match,
1394 },
1395 .probe = cpm_uart_probe,
1396 .remove = cpm_uart_remove,
1397 };
1398
1399static int __init cpm_uart_init(void)
1400{
1401 int ret = uart_register_driver(&cpm_reg);
1402 if (ret)
1403 return ret;
1404
1405 ret = of_register_platform_driver(&cpm_uart_driver);
1406 if (ret)
1407 uart_unregister_driver(&cpm_reg);
1408
1409 return ret;
1410}
1411
1412static void __exit cpm_uart_exit(void)
1413{
1414 of_unregister_platform_driver(&cpm_uart_driver);
1415 uart_unregister_driver(&cpm_reg);
1416}
1417
1418module_init(cpm_uart_init);
1419module_exit(cpm_uart_exit);
1420
1421MODULE_AUTHOR("Kumar Gala/Antoniou Pantelis");
1422MODULE_DESCRIPTION("CPM SCC/SMC port driver $Revision: 0.01 $");
1423MODULE_LICENSE("GPL");
1424MODULE_ALIAS_CHARDEV(SERIAL_CPM_MAJOR, SERIAL_CPM_MINOR);
diff --git a/drivers/serial/cpm_uart/cpm_uart_cpm1.c b/drivers/serial/cpm_uart/cpm_uart_cpm1.c
deleted file mode 100644
index 3fc1d66e32c6..000000000000
--- a/drivers/serial/cpm_uart/cpm_uart_cpm1.c
+++ /dev/null
@@ -1,138 +0,0 @@
1/*
2 * linux/drivers/serial/cpm_uart.c
3 *
4 * Driver for CPM (SCC/SMC) serial ports; CPM1 definitions
5 *
6 * Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2)
7 * Pantelis Antoniou (panto@intracom.gr) (CPM1)
8 *
9 * Copyright (C) 2004 Freescale Semiconductor, Inc.
10 * (C) 2004 Intracom, S.A.
11 * (C) 2006 MontaVista Software, Inc.
12 * Vitaly Bordug <vbordug@ru.mvista.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 *
28 */
29
30#include <linux/module.h>
31#include <linux/tty.h>
32#include <linux/gfp.h>
33#include <linux/ioport.h>
34#include <linux/init.h>
35#include <linux/serial.h>
36#include <linux/console.h>
37#include <linux/sysrq.h>
38#include <linux/device.h>
39#include <linux/bootmem.h>
40#include <linux/dma-mapping.h>
41
42#include <asm/io.h>
43#include <asm/irq.h>
44#include <asm/fs_pd.h>
45
46#include <linux/serial_core.h>
47#include <linux/kernel.h>
48
49#include <linux/of.h>
50
51#include "cpm_uart.h"
52
53/**************************************************************/
54
55void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd)
56{
57 cpm_command(port->command, cmd);
58}
59
60void __iomem *cpm_uart_map_pram(struct uart_cpm_port *port,
61 struct device_node *np)
62{
63 return of_iomap(np, 1);
64}
65
66void cpm_uart_unmap_pram(struct uart_cpm_port *port, void __iomem *pram)
67{
68 iounmap(pram);
69}
70
71/*
72 * Allocate DP-Ram and memory buffers. We need to allocate a transmit and
73 * receive buffer descriptors from dual port ram, and a character
74 * buffer area from host mem. If we are allocating for the console we need
75 * to do it from bootmem
76 */
77int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con)
78{
79 int dpmemsz, memsz;
80 u8 *dp_mem;
81 unsigned long dp_offset;
82 u8 *mem_addr;
83 dma_addr_t dma_addr = 0;
84
85 pr_debug("CPM uart[%d]:allocbuf\n", pinfo->port.line);
86
87 dpmemsz = sizeof(cbd_t) * (pinfo->rx_nrfifos + pinfo->tx_nrfifos);
88 dp_offset = cpm_dpalloc(dpmemsz, 8);
89 if (IS_ERR_VALUE(dp_offset)) {
90 printk(KERN_ERR
91 "cpm_uart_cpm1.c: could not allocate buffer descriptors\n");
92 return -ENOMEM;
93 }
94 dp_mem = cpm_dpram_addr(dp_offset);
95
96 memsz = L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize) +
97 L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize);
98 if (is_con) {
99 /* was hostalloc but changed cause it blows away the */
100 /* large tlb mapping when pinning the kernel area */
101 mem_addr = (u8 *) cpm_dpram_addr(cpm_dpalloc(memsz, 8));
102 dma_addr = (u32)cpm_dpram_phys(mem_addr);
103 } else
104 mem_addr = dma_alloc_coherent(pinfo->port.dev, memsz, &dma_addr,
105 GFP_KERNEL);
106
107 if (mem_addr == NULL) {
108 cpm_dpfree(dp_offset);
109 printk(KERN_ERR
110 "cpm_uart_cpm1.c: could not allocate coherent memory\n");
111 return -ENOMEM;
112 }
113
114 pinfo->dp_addr = dp_offset;
115 pinfo->mem_addr = mem_addr; /* virtual address*/
116 pinfo->dma_addr = dma_addr; /* physical address*/
117 pinfo->mem_size = memsz;
118
119 pinfo->rx_buf = mem_addr;
120 pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos
121 * pinfo->rx_fifosize);
122
123 pinfo->rx_bd_base = (cbd_t __iomem __force *)dp_mem;
124 pinfo->tx_bd_base = pinfo->rx_bd_base + pinfo->rx_nrfifos;
125
126 return 0;
127}
128
129void cpm_uart_freebuf(struct uart_cpm_port *pinfo)
130{
131 dma_free_coherent(pinfo->port.dev, L1_CACHE_ALIGN(pinfo->rx_nrfifos *
132 pinfo->rx_fifosize) +
133 L1_CACHE_ALIGN(pinfo->tx_nrfifos *
134 pinfo->tx_fifosize), pinfo->mem_addr,
135 pinfo->dma_addr);
136
137 cpm_dpfree(pinfo->dp_addr);
138}
diff --git a/drivers/serial/cpm_uart/cpm_uart_cpm1.h b/drivers/serial/cpm_uart/cpm_uart_cpm1.h
deleted file mode 100644
index 10eecd6af6d4..000000000000
--- a/drivers/serial/cpm_uart/cpm_uart_cpm1.h
+++ /dev/null
@@ -1,34 +0,0 @@
1/*
2 * linux/drivers/serial/cpm_uart/cpm_uart_cpm1.h
3 *
4 * Driver for CPM (SCC/SMC) serial ports
5 *
6 * definitions for cpm1
7 *
8 */
9
10#ifndef CPM_UART_CPM1_H
11#define CPM_UART_CPM1_H
12
13#include <asm/cpm1.h>
14
15static inline void cpm_set_brg(int brg, int baud)
16{
17 cpm_setbrg(brg, baud);
18}
19
20static inline void cpm_set_scc_fcr(scc_uart_t __iomem * sup)
21{
22 out_8(&sup->scc_genscc.scc_rfcr, SMC_EB);
23 out_8(&sup->scc_genscc.scc_tfcr, SMC_EB);
24}
25
26static inline void cpm_set_smc_fcr(smc_uart_t __iomem * up)
27{
28 out_8(&up->smc_rfcr, SMC_EB);
29 out_8(&up->smc_tfcr, SMC_EB);
30}
31
32#define DPRAM_BASE ((u8 __iomem __force *)cpm_dpram_addr(0))
33
34#endif
diff --git a/drivers/serial/cpm_uart/cpm_uart_cpm2.c b/drivers/serial/cpm_uart/cpm_uart_cpm2.c
deleted file mode 100644
index 814ac006393f..000000000000
--- a/drivers/serial/cpm_uart/cpm_uart_cpm2.c
+++ /dev/null
@@ -1,174 +0,0 @@
1/*
2 * linux/drivers/serial/cpm_uart_cpm2.c
3 *
4 * Driver for CPM (SCC/SMC) serial ports; CPM2 definitions
5 *
6 * Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2)
7 * Pantelis Antoniou (panto@intracom.gr) (CPM1)
8 *
9 * Copyright (C) 2004 Freescale Semiconductor, Inc.
10 * (C) 2004 Intracom, S.A.
11 * (C) 2006 MontaVista Software, Inc.
12 * Vitaly Bordug <vbordug@ru.mvista.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 *
28 */
29
30#include <linux/module.h>
31#include <linux/tty.h>
32#include <linux/ioport.h>
33#include <linux/slab.h>
34#include <linux/init.h>
35#include <linux/serial.h>
36#include <linux/console.h>
37#include <linux/sysrq.h>
38#include <linux/device.h>
39#include <linux/bootmem.h>
40#include <linux/dma-mapping.h>
41
42#include <asm/io.h>
43#include <asm/irq.h>
44#include <asm/fs_pd.h>
45#include <asm/prom.h>
46
47#include <linux/serial_core.h>
48#include <linux/kernel.h>
49
50#include "cpm_uart.h"
51
52/**************************************************************/
53
54void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd)
55{
56 cpm_command(port->command, cmd);
57}
58
59void __iomem *cpm_uart_map_pram(struct uart_cpm_port *port,
60 struct device_node *np)
61{
62 void __iomem *pram;
63 unsigned long offset;
64 struct resource res;
65 resource_size_t len;
66
67 /* Don't remap parameter RAM if it has already been initialized
68 * during console setup.
69 */
70 if (IS_SMC(port) && port->smcup)
71 return port->smcup;
72 else if (!IS_SMC(port) && port->sccup)
73 return port->sccup;
74
75 if (of_address_to_resource(np, 1, &res))
76 return NULL;
77
78 len = resource_size(&res);
79 pram = ioremap(res.start, len);
80 if (!pram)
81 return NULL;
82
83 if (!IS_SMC(port))
84 return pram;
85
86 if (len != 2) {
87 printk(KERN_WARNING "cpm_uart[%d]: device tree references "
88 "SMC pram, using boot loader/wrapper pram mapping. "
89 "Please fix your device tree to reference the pram "
90 "base register instead.\n",
91 port->port.line);
92 return pram;
93 }
94
95 offset = cpm_dpalloc(PROFF_SMC_SIZE, 64);
96 out_be16(pram, offset);
97 iounmap(pram);
98 return cpm_muram_addr(offset);
99}
100
101void cpm_uart_unmap_pram(struct uart_cpm_port *port, void __iomem *pram)
102{
103 if (!IS_SMC(port))
104 iounmap(pram);
105}
106
107/*
108 * Allocate DP-Ram and memory buffers. We need to allocate a transmit and
109 * receive buffer descriptors from dual port ram, and a character
110 * buffer area from host mem. If we are allocating for the console we need
111 * to do it from bootmem
112 */
113int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con)
114{
115 int dpmemsz, memsz;
116 u8 __iomem *dp_mem;
117 unsigned long dp_offset;
118 u8 *mem_addr;
119 dma_addr_t dma_addr = 0;
120
121 pr_debug("CPM uart[%d]:allocbuf\n", pinfo->port.line);
122
123 dpmemsz = sizeof(cbd_t) * (pinfo->rx_nrfifos + pinfo->tx_nrfifos);
124 dp_offset = cpm_dpalloc(dpmemsz, 8);
125 if (IS_ERR_VALUE(dp_offset)) {
126 printk(KERN_ERR
127 "cpm_uart_cpm.c: could not allocate buffer descriptors\n");
128 return -ENOMEM;
129 }
130
131 dp_mem = cpm_dpram_addr(dp_offset);
132
133 memsz = L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize) +
134 L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize);
135 if (is_con) {
136 mem_addr = kzalloc(memsz, GFP_NOWAIT);
137 dma_addr = virt_to_bus(mem_addr);
138 }
139 else
140 mem_addr = dma_alloc_coherent(pinfo->port.dev, memsz, &dma_addr,
141 GFP_KERNEL);
142
143 if (mem_addr == NULL) {
144 cpm_dpfree(dp_offset);
145 printk(KERN_ERR
146 "cpm_uart_cpm.c: could not allocate coherent memory\n");
147 return -ENOMEM;
148 }
149
150 pinfo->dp_addr = dp_offset;
151 pinfo->mem_addr = mem_addr;
152 pinfo->dma_addr = dma_addr;
153 pinfo->mem_size = memsz;
154
155 pinfo->rx_buf = mem_addr;
156 pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos
157 * pinfo->rx_fifosize);
158
159 pinfo->rx_bd_base = (cbd_t __iomem *)dp_mem;
160 pinfo->tx_bd_base = pinfo->rx_bd_base + pinfo->rx_nrfifos;
161
162 return 0;
163}
164
165void cpm_uart_freebuf(struct uart_cpm_port *pinfo)
166{
167 dma_free_coherent(pinfo->port.dev, L1_CACHE_ALIGN(pinfo->rx_nrfifos *
168 pinfo->rx_fifosize) +
169 L1_CACHE_ALIGN(pinfo->tx_nrfifos *
170 pinfo->tx_fifosize), (void __force *)pinfo->mem_addr,
171 pinfo->dma_addr);
172
173 cpm_dpfree(pinfo->dp_addr);
174}
diff --git a/drivers/serial/cpm_uart/cpm_uart_cpm2.h b/drivers/serial/cpm_uart/cpm_uart_cpm2.h
deleted file mode 100644
index 7194c63dcf5f..000000000000
--- a/drivers/serial/cpm_uart/cpm_uart_cpm2.h
+++ /dev/null
@@ -1,34 +0,0 @@
1/*
2 * linux/drivers/serial/cpm_uart/cpm_uart_cpm2.h
3 *
4 * Driver for CPM (SCC/SMC) serial ports
5 *
6 * definitions for cpm2
7 *
8 */
9
10#ifndef CPM_UART_CPM2_H
11#define CPM_UART_CPM2_H
12
13#include <asm/cpm2.h>
14
15static inline void cpm_set_brg(int brg, int baud)
16{
17 cpm_setbrg(brg, baud);
18}
19
20static inline void cpm_set_scc_fcr(scc_uart_t __iomem *sup)
21{
22 out_8(&sup->scc_genscc.scc_rfcr, CPMFCR_GBL | CPMFCR_EB);
23 out_8(&sup->scc_genscc.scc_tfcr, CPMFCR_GBL | CPMFCR_EB);
24}
25
26static inline void cpm_set_smc_fcr(smc_uart_t __iomem *up)
27{
28 out_8(&up->smc_rfcr, CPMFCR_GBL | CPMFCR_EB);
29 out_8(&up->smc_tfcr, CPMFCR_GBL | CPMFCR_EB);
30}
31
32#define DPRAM_BASE ((u8 __iomem __force *)cpm_dpram_addr(0))
33
34#endif
diff --git a/drivers/serial/crisv10.c b/drivers/serial/crisv10.c
deleted file mode 100644
index c856905bb3bd..000000000000
--- a/drivers/serial/crisv10.c
+++ /dev/null
@@ -1,4567 +0,0 @@
1/*
2 * Serial port driver for the ETRAX 100LX chip
3 *
4 * Copyright (C) 1998-2007 Axis Communications AB
5 *
6 * Many, many authors. Based once upon a time on serial.c for 16x50.
7 *
8 */
9
10static char *serial_version = "$Revision: 1.25 $";
11
12#include <linux/types.h>
13#include <linux/errno.h>
14#include <linux/signal.h>
15#include <linux/sched.h>
16#include <linux/timer.h>
17#include <linux/interrupt.h>
18#include <linux/tty.h>
19#include <linux/tty_flip.h>
20#include <linux/major.h>
21#include <linux/smp_lock.h>
22#include <linux/string.h>
23#include <linux/fcntl.h>
24#include <linux/mm.h>
25#include <linux/slab.h>
26#include <linux/init.h>
27#include <linux/kernel.h>
28#include <linux/mutex.h>
29#include <linux/bitops.h>
30#include <linux/seq_file.h>
31#include <linux/delay.h>
32#include <linux/module.h>
33#include <linux/uaccess.h>
34#include <linux/io.h>
35
36#include <asm/irq.h>
37#include <asm/dma.h>
38#include <asm/system.h>
39
40#include <arch/svinto.h>
41
42/* non-arch dependent serial structures are in linux/serial.h */
43#include <linux/serial.h>
44/* while we keep our own stuff (struct e100_serial) in a local .h file */
45#include "crisv10.h"
46#include <asm/fasttimer.h>
47#include <arch/io_interface_mux.h>
48
49#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
50#ifndef CONFIG_ETRAX_FAST_TIMER
51#error "Enable FAST_TIMER to use SERIAL_FAST_TIMER"
52#endif
53#endif
54
55#if defined(CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS) && \
56 (CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS == 0)
57#error "RX_TIMEOUT_TICKS == 0 not allowed, use 1"
58#endif
59
60#if defined(CONFIG_ETRAX_RS485_ON_PA) && defined(CONFIG_ETRAX_RS485_ON_PORT_G)
61#error "Disable either CONFIG_ETRAX_RS485_ON_PA or CONFIG_ETRAX_RS485_ON_PORT_G"
62#endif
63
64/*
65 * All of the compatibilty code so we can compile serial.c against
66 * older kernels is hidden in serial_compat.h
67 */
68#if defined(LOCAL_HEADERS)
69#include "serial_compat.h"
70#endif
71
72struct tty_driver *serial_driver;
73
74/* number of characters left in xmit buffer before we ask for more */
75#define WAKEUP_CHARS 256
76
77//#define SERIAL_DEBUG_INTR
78//#define SERIAL_DEBUG_OPEN
79//#define SERIAL_DEBUG_FLOW
80//#define SERIAL_DEBUG_DATA
81//#define SERIAL_DEBUG_THROTTLE
82//#define SERIAL_DEBUG_IO /* Debug for Extra control and status pins */
83//#define SERIAL_DEBUG_LINE 0 /* What serport we want to debug */
84
85/* Enable this to use serial interrupts to handle when you
86 expect the first received event on the serial port to
87 be an error, break or similar. Used to be able to flash IRMA
88 from eLinux */
89#define SERIAL_HANDLE_EARLY_ERRORS
90
91/* Currently 16 descriptors x 128 bytes = 2048 bytes */
92#define SERIAL_DESCR_BUF_SIZE 256
93
94#define SERIAL_PRESCALE_BASE 3125000 /* 3.125MHz */
95#define DEF_BAUD_BASE SERIAL_PRESCALE_BASE
96
97/* We don't want to load the system with massive fast timer interrupt
98 * on high baudrates so limit it to 250 us (4kHz) */
99#define MIN_FLUSH_TIME_USEC 250
100
101/* Add an x here to log a lot of timer stuff */
102#define TIMERD(x)
103/* Debug details of interrupt handling */
104#define DINTR1(x) /* irq on/off, errors */
105#define DINTR2(x) /* tx and rx */
106/* Debug flip buffer stuff */
107#define DFLIP(x)
108/* Debug flow control and overview of data flow */
109#define DFLOW(x)
110#define DBAUD(x)
111#define DLOG_INT_TRIG(x)
112
113//#define DEBUG_LOG_INCLUDED
114#ifndef DEBUG_LOG_INCLUDED
115#define DEBUG_LOG(line, string, value)
116#else
117struct debug_log_info
118{
119 unsigned long time;
120 unsigned long timer_data;
121// int line;
122 const char *string;
123 int value;
124};
125#define DEBUG_LOG_SIZE 4096
126
127struct debug_log_info debug_log[DEBUG_LOG_SIZE];
128int debug_log_pos = 0;
129
130#define DEBUG_LOG(_line, _string, _value) do { \
131 if ((_line) == SERIAL_DEBUG_LINE) {\
132 debug_log_func(_line, _string, _value); \
133 }\
134}while(0)
135
136void debug_log_func(int line, const char *string, int value)
137{
138 if (debug_log_pos < DEBUG_LOG_SIZE) {
139 debug_log[debug_log_pos].time = jiffies;
140 debug_log[debug_log_pos].timer_data = *R_TIMER_DATA;
141// debug_log[debug_log_pos].line = line;
142 debug_log[debug_log_pos].string = string;
143 debug_log[debug_log_pos].value = value;
144 debug_log_pos++;
145 }
146 /*printk(string, value);*/
147}
148#endif
149
150#ifndef CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS
151/* Default number of timer ticks before flushing rx fifo
152 * When using "little data, low latency applications: use 0
153 * When using "much data applications (PPP)" use ~5
154 */
155#define CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS 5
156#endif
157
158unsigned long timer_data_to_ns(unsigned long timer_data);
159
160static void change_speed(struct e100_serial *info);
161static void rs_throttle(struct tty_struct * tty);
162static void rs_wait_until_sent(struct tty_struct *tty, int timeout);
163static int rs_write(struct tty_struct *tty,
164 const unsigned char *buf, int count);
165#ifdef CONFIG_ETRAX_RS485
166static int e100_write_rs485(struct tty_struct *tty,
167 const unsigned char *buf, int count);
168#endif
169static int get_lsr_info(struct e100_serial *info, unsigned int *value);
170
171
172#define DEF_BAUD 115200 /* 115.2 kbit/s */
173#define STD_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
174#define DEF_RX 0x20 /* or SERIAL_CTRL_W >> 8 */
175/* Default value of tx_ctrl register: has txd(bit 7)=1 (idle) as default */
176#define DEF_TX 0x80 /* or SERIAL_CTRL_B */
177
178/* offsets from R_SERIALx_CTRL */
179
180#define REG_DATA 0
181#define REG_DATA_STATUS32 0 /* this is the 32 bit register R_SERIALx_READ */
182#define REG_TR_DATA 0
183#define REG_STATUS 1
184#define REG_TR_CTRL 1
185#define REG_REC_CTRL 2
186#define REG_BAUD 3
187#define REG_XOFF 4 /* this is a 32 bit register */
188
189/* The bitfields are the same for all serial ports */
190#define SER_RXD_MASK IO_MASK(R_SERIAL0_STATUS, rxd)
191#define SER_DATA_AVAIL_MASK IO_MASK(R_SERIAL0_STATUS, data_avail)
192#define SER_FRAMING_ERR_MASK IO_MASK(R_SERIAL0_STATUS, framing_err)
193#define SER_PAR_ERR_MASK IO_MASK(R_SERIAL0_STATUS, par_err)
194#define SER_OVERRUN_MASK IO_MASK(R_SERIAL0_STATUS, overrun)
195
196#define SER_ERROR_MASK (SER_OVERRUN_MASK | SER_PAR_ERR_MASK | SER_FRAMING_ERR_MASK)
197
198/* Values for info->errorcode */
199#define ERRCODE_SET_BREAK (TTY_BREAK)
200#define ERRCODE_INSERT 0x100
201#define ERRCODE_INSERT_BREAK (ERRCODE_INSERT | TTY_BREAK)
202
203#define FORCE_EOP(info) *R_SET_EOP = 1U << info->iseteop;
204
205/*
206 * General note regarding the use of IO_* macros in this file:
207 *
208 * We will use the bits defined for DMA channel 6 when using various
209 * IO_* macros (e.g. IO_STATE, IO_MASK, IO_EXTRACT) and _assume_ they are
210 * the same for all channels (which of course they are).
211 *
212 * We will also use the bits defined for serial port 0 when writing commands
213 * to the different ports, as these bits too are the same for all ports.
214 */
215
216
217/* Mask for the irqs possibly enabled in R_IRQ_MASK1_RD etc. */
218static const unsigned long e100_ser_int_mask = 0
219#ifdef CONFIG_ETRAX_SERIAL_PORT0
220| IO_MASK(R_IRQ_MASK1_RD, ser0_data) | IO_MASK(R_IRQ_MASK1_RD, ser0_ready)
221#endif
222#ifdef CONFIG_ETRAX_SERIAL_PORT1
223| IO_MASK(R_IRQ_MASK1_RD, ser1_data) | IO_MASK(R_IRQ_MASK1_RD, ser1_ready)
224#endif
225#ifdef CONFIG_ETRAX_SERIAL_PORT2
226| IO_MASK(R_IRQ_MASK1_RD, ser2_data) | IO_MASK(R_IRQ_MASK1_RD, ser2_ready)
227#endif
228#ifdef CONFIG_ETRAX_SERIAL_PORT3
229| IO_MASK(R_IRQ_MASK1_RD, ser3_data) | IO_MASK(R_IRQ_MASK1_RD, ser3_ready)
230#endif
231;
232unsigned long r_alt_ser_baudrate_shadow = 0;
233
234/* this is the data for the four serial ports in the etrax100 */
235/* DMA2(ser2), DMA4(ser3), DMA6(ser0) or DMA8(ser1) */
236/* R_DMA_CHx_CLR_INTR, R_DMA_CHx_FIRST, R_DMA_CHx_CMD */
237
238static struct e100_serial rs_table[] = {
239 { .baud = DEF_BAUD,
240 .ioport = (unsigned char *)R_SERIAL0_CTRL,
241 .irq = 1U << 12, /* uses DMA 6 and 7 */
242 .oclrintradr = R_DMA_CH6_CLR_INTR,
243 .ofirstadr = R_DMA_CH6_FIRST,
244 .ocmdadr = R_DMA_CH6_CMD,
245 .ostatusadr = R_DMA_CH6_STATUS,
246 .iclrintradr = R_DMA_CH7_CLR_INTR,
247 .ifirstadr = R_DMA_CH7_FIRST,
248 .icmdadr = R_DMA_CH7_CMD,
249 .idescradr = R_DMA_CH7_DESCR,
250 .flags = STD_FLAGS,
251 .rx_ctrl = DEF_RX,
252 .tx_ctrl = DEF_TX,
253 .iseteop = 2,
254 .dma_owner = dma_ser0,
255 .io_if = if_serial_0,
256#ifdef CONFIG_ETRAX_SERIAL_PORT0
257 .enabled = 1,
258#ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA6_OUT
259 .dma_out_enabled = 1,
260 .dma_out_nbr = SER0_TX_DMA_NBR,
261 .dma_out_irq_nbr = SER0_DMA_TX_IRQ_NBR,
262 .dma_out_irq_flags = IRQF_DISABLED,
263 .dma_out_irq_description = "serial 0 dma tr",
264#else
265 .dma_out_enabled = 0,
266 .dma_out_nbr = UINT_MAX,
267 .dma_out_irq_nbr = 0,
268 .dma_out_irq_flags = 0,
269 .dma_out_irq_description = NULL,
270#endif
271#ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA7_IN
272 .dma_in_enabled = 1,
273 .dma_in_nbr = SER0_RX_DMA_NBR,
274 .dma_in_irq_nbr = SER0_DMA_RX_IRQ_NBR,
275 .dma_in_irq_flags = IRQF_DISABLED,
276 .dma_in_irq_description = "serial 0 dma rec",
277#else
278 .dma_in_enabled = 0,
279 .dma_in_nbr = UINT_MAX,
280 .dma_in_irq_nbr = 0,
281 .dma_in_irq_flags = 0,
282 .dma_in_irq_description = NULL,
283#endif
284#else
285 .enabled = 0,
286 .io_if_description = NULL,
287 .dma_out_enabled = 0,
288 .dma_in_enabled = 0
289#endif
290
291}, /* ttyS0 */
292#ifndef CONFIG_SVINTO_SIM
293 { .baud = DEF_BAUD,
294 .ioport = (unsigned char *)R_SERIAL1_CTRL,
295 .irq = 1U << 16, /* uses DMA 8 and 9 */
296 .oclrintradr = R_DMA_CH8_CLR_INTR,
297 .ofirstadr = R_DMA_CH8_FIRST,
298 .ocmdadr = R_DMA_CH8_CMD,
299 .ostatusadr = R_DMA_CH8_STATUS,
300 .iclrintradr = R_DMA_CH9_CLR_INTR,
301 .ifirstadr = R_DMA_CH9_FIRST,
302 .icmdadr = R_DMA_CH9_CMD,
303 .idescradr = R_DMA_CH9_DESCR,
304 .flags = STD_FLAGS,
305 .rx_ctrl = DEF_RX,
306 .tx_ctrl = DEF_TX,
307 .iseteop = 3,
308 .dma_owner = dma_ser1,
309 .io_if = if_serial_1,
310#ifdef CONFIG_ETRAX_SERIAL_PORT1
311 .enabled = 1,
312 .io_if_description = "ser1",
313#ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA8_OUT
314 .dma_out_enabled = 1,
315 .dma_out_nbr = SER1_TX_DMA_NBR,
316 .dma_out_irq_nbr = SER1_DMA_TX_IRQ_NBR,
317 .dma_out_irq_flags = IRQF_DISABLED,
318 .dma_out_irq_description = "serial 1 dma tr",
319#else
320 .dma_out_enabled = 0,
321 .dma_out_nbr = UINT_MAX,
322 .dma_out_irq_nbr = 0,
323 .dma_out_irq_flags = 0,
324 .dma_out_irq_description = NULL,
325#endif
326#ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA9_IN
327 .dma_in_enabled = 1,
328 .dma_in_nbr = SER1_RX_DMA_NBR,
329 .dma_in_irq_nbr = SER1_DMA_RX_IRQ_NBR,
330 .dma_in_irq_flags = IRQF_DISABLED,
331 .dma_in_irq_description = "serial 1 dma rec",
332#else
333 .dma_in_enabled = 0,
334 .dma_in_enabled = 0,
335 .dma_in_nbr = UINT_MAX,
336 .dma_in_irq_nbr = 0,
337 .dma_in_irq_flags = 0,
338 .dma_in_irq_description = NULL,
339#endif
340#else
341 .enabled = 0,
342 .io_if_description = NULL,
343 .dma_in_irq_nbr = 0,
344 .dma_out_enabled = 0,
345 .dma_in_enabled = 0
346#endif
347}, /* ttyS1 */
348
349 { .baud = DEF_BAUD,
350 .ioport = (unsigned char *)R_SERIAL2_CTRL,
351 .irq = 1U << 4, /* uses DMA 2 and 3 */
352 .oclrintradr = R_DMA_CH2_CLR_INTR,
353 .ofirstadr = R_DMA_CH2_FIRST,
354 .ocmdadr = R_DMA_CH2_CMD,
355 .ostatusadr = R_DMA_CH2_STATUS,
356 .iclrintradr = R_DMA_CH3_CLR_INTR,
357 .ifirstadr = R_DMA_CH3_FIRST,
358 .icmdadr = R_DMA_CH3_CMD,
359 .idescradr = R_DMA_CH3_DESCR,
360 .flags = STD_FLAGS,
361 .rx_ctrl = DEF_RX,
362 .tx_ctrl = DEF_TX,
363 .iseteop = 0,
364 .dma_owner = dma_ser2,
365 .io_if = if_serial_2,
366#ifdef CONFIG_ETRAX_SERIAL_PORT2
367 .enabled = 1,
368 .io_if_description = "ser2",
369#ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA2_OUT
370 .dma_out_enabled = 1,
371 .dma_out_nbr = SER2_TX_DMA_NBR,
372 .dma_out_irq_nbr = SER2_DMA_TX_IRQ_NBR,
373 .dma_out_irq_flags = IRQF_DISABLED,
374 .dma_out_irq_description = "serial 2 dma tr",
375#else
376 .dma_out_enabled = 0,
377 .dma_out_nbr = UINT_MAX,
378 .dma_out_irq_nbr = 0,
379 .dma_out_irq_flags = 0,
380 .dma_out_irq_description = NULL,
381#endif
382#ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA3_IN
383 .dma_in_enabled = 1,
384 .dma_in_nbr = SER2_RX_DMA_NBR,
385 .dma_in_irq_nbr = SER2_DMA_RX_IRQ_NBR,
386 .dma_in_irq_flags = IRQF_DISABLED,
387 .dma_in_irq_description = "serial 2 dma rec",
388#else
389 .dma_in_enabled = 0,
390 .dma_in_nbr = UINT_MAX,
391 .dma_in_irq_nbr = 0,
392 .dma_in_irq_flags = 0,
393 .dma_in_irq_description = NULL,
394#endif
395#else
396 .enabled = 0,
397 .io_if_description = NULL,
398 .dma_out_enabled = 0,
399 .dma_in_enabled = 0
400#endif
401 }, /* ttyS2 */
402
403 { .baud = DEF_BAUD,
404 .ioport = (unsigned char *)R_SERIAL3_CTRL,
405 .irq = 1U << 8, /* uses DMA 4 and 5 */
406 .oclrintradr = R_DMA_CH4_CLR_INTR,
407 .ofirstadr = R_DMA_CH4_FIRST,
408 .ocmdadr = R_DMA_CH4_CMD,
409 .ostatusadr = R_DMA_CH4_STATUS,
410 .iclrintradr = R_DMA_CH5_CLR_INTR,
411 .ifirstadr = R_DMA_CH5_FIRST,
412 .icmdadr = R_DMA_CH5_CMD,
413 .idescradr = R_DMA_CH5_DESCR,
414 .flags = STD_FLAGS,
415 .rx_ctrl = DEF_RX,
416 .tx_ctrl = DEF_TX,
417 .iseteop = 1,
418 .dma_owner = dma_ser3,
419 .io_if = if_serial_3,
420#ifdef CONFIG_ETRAX_SERIAL_PORT3
421 .enabled = 1,
422 .io_if_description = "ser3",
423#ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA4_OUT
424 .dma_out_enabled = 1,
425 .dma_out_nbr = SER3_TX_DMA_NBR,
426 .dma_out_irq_nbr = SER3_DMA_TX_IRQ_NBR,
427 .dma_out_irq_flags = IRQF_DISABLED,
428 .dma_out_irq_description = "serial 3 dma tr",
429#else
430 .dma_out_enabled = 0,
431 .dma_out_nbr = UINT_MAX,
432 .dma_out_irq_nbr = 0,
433 .dma_out_irq_flags = 0,
434 .dma_out_irq_description = NULL,
435#endif
436#ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA5_IN
437 .dma_in_enabled = 1,
438 .dma_in_nbr = SER3_RX_DMA_NBR,
439 .dma_in_irq_nbr = SER3_DMA_RX_IRQ_NBR,
440 .dma_in_irq_flags = IRQF_DISABLED,
441 .dma_in_irq_description = "serial 3 dma rec",
442#else
443 .dma_in_enabled = 0,
444 .dma_in_nbr = UINT_MAX,
445 .dma_in_irq_nbr = 0,
446 .dma_in_irq_flags = 0,
447 .dma_in_irq_description = NULL
448#endif
449#else
450 .enabled = 0,
451 .io_if_description = NULL,
452 .dma_out_enabled = 0,
453 .dma_in_enabled = 0
454#endif
455 } /* ttyS3 */
456#endif
457};
458
459
460#define NR_PORTS (sizeof(rs_table)/sizeof(struct e100_serial))
461
462#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
463static struct fast_timer fast_timers[NR_PORTS];
464#endif
465
466#ifdef CONFIG_ETRAX_SERIAL_PROC_ENTRY
467#define PROCSTAT(x) x
468struct ser_statistics_type {
469 int overrun_cnt;
470 int early_errors_cnt;
471 int ser_ints_ok_cnt;
472 int errors_cnt;
473 unsigned long int processing_flip;
474 unsigned long processing_flip_still_room;
475 unsigned long int timeout_flush_cnt;
476 int rx_dma_ints;
477 int tx_dma_ints;
478 int rx_tot;
479 int tx_tot;
480};
481
482static struct ser_statistics_type ser_stat[NR_PORTS];
483
484#else
485
486#define PROCSTAT(x)
487
488#endif /* CONFIG_ETRAX_SERIAL_PROC_ENTRY */
489
490/* RS-485 */
491#if defined(CONFIG_ETRAX_RS485)
492#ifdef CONFIG_ETRAX_FAST_TIMER
493static struct fast_timer fast_timers_rs485[NR_PORTS];
494#endif
495#if defined(CONFIG_ETRAX_RS485_ON_PA)
496static int rs485_pa_bit = CONFIG_ETRAX_RS485_ON_PA_BIT;
497#endif
498#if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
499static int rs485_port_g_bit = CONFIG_ETRAX_RS485_ON_PORT_G_BIT;
500#endif
501#endif
502
503/* Info and macros needed for each ports extra control/status signals. */
504#define E100_STRUCT_PORT(line, pinname) \
505 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
506 (R_PORT_PA_DATA): ( \
507 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
508 (R_PORT_PB_DATA):&dummy_ser[line]))
509
510#define E100_STRUCT_SHADOW(line, pinname) \
511 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
512 (&port_pa_data_shadow): ( \
513 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
514 (&port_pb_data_shadow):&dummy_ser[line]))
515#define E100_STRUCT_MASK(line, pinname) \
516 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
517 (1<<CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT): ( \
518 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
519 (1<<CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT):DUMMY_##pinname##_MASK))
520
521#define DUMMY_DTR_MASK 1
522#define DUMMY_RI_MASK 2
523#define DUMMY_DSR_MASK 4
524#define DUMMY_CD_MASK 8
525static unsigned char dummy_ser[NR_PORTS] = {0xFF, 0xFF, 0xFF,0xFF};
526
527/* If not all status pins are used or disabled, use mixed mode */
528#ifdef CONFIG_ETRAX_SERIAL_PORT0
529
530#define SER0_PA_BITSUM (CONFIG_ETRAX_SER0_DTR_ON_PA_BIT+CONFIG_ETRAX_SER0_RI_ON_PA_BIT+CONFIG_ETRAX_SER0_DSR_ON_PA_BIT+CONFIG_ETRAX_SER0_CD_ON_PA_BIT)
531
532#if SER0_PA_BITSUM != -4
533# if CONFIG_ETRAX_SER0_DTR_ON_PA_BIT == -1
534# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
535# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
536# endif
537# endif
538# if CONFIG_ETRAX_SER0_RI_ON_PA_BIT == -1
539# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
540# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
541# endif
542# endif
543# if CONFIG_ETRAX_SER0_DSR_ON_PA_BIT == -1
544# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
545# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
546# endif
547# endif
548# if CONFIG_ETRAX_SER0_CD_ON_PA_BIT == -1
549# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
550# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
551# endif
552# endif
553#endif
554
555#define SER0_PB_BITSUM (CONFIG_ETRAX_SER0_DTR_ON_PB_BIT+CONFIG_ETRAX_SER0_RI_ON_PB_BIT+CONFIG_ETRAX_SER0_DSR_ON_PB_BIT+CONFIG_ETRAX_SER0_CD_ON_PB_BIT)
556
557#if SER0_PB_BITSUM != -4
558# if CONFIG_ETRAX_SER0_DTR_ON_PB_BIT == -1
559# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
560# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
561# endif
562# endif
563# if CONFIG_ETRAX_SER0_RI_ON_PB_BIT == -1
564# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
565# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
566# endif
567# endif
568# if CONFIG_ETRAX_SER0_DSR_ON_PB_BIT == -1
569# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
570# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
571# endif
572# endif
573# if CONFIG_ETRAX_SER0_CD_ON_PB_BIT == -1
574# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
575# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
576# endif
577# endif
578#endif
579
580#endif /* PORT0 */
581
582
583#ifdef CONFIG_ETRAX_SERIAL_PORT1
584
585#define SER1_PA_BITSUM (CONFIG_ETRAX_SER1_DTR_ON_PA_BIT+CONFIG_ETRAX_SER1_RI_ON_PA_BIT+CONFIG_ETRAX_SER1_DSR_ON_PA_BIT+CONFIG_ETRAX_SER1_CD_ON_PA_BIT)
586
587#if SER1_PA_BITSUM != -4
588# if CONFIG_ETRAX_SER1_DTR_ON_PA_BIT == -1
589# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
590# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
591# endif
592# endif
593# if CONFIG_ETRAX_SER1_RI_ON_PA_BIT == -1
594# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
595# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
596# endif
597# endif
598# if CONFIG_ETRAX_SER1_DSR_ON_PA_BIT == -1
599# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
600# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
601# endif
602# endif
603# if CONFIG_ETRAX_SER1_CD_ON_PA_BIT == -1
604# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
605# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
606# endif
607# endif
608#endif
609
610#define SER1_PB_BITSUM (CONFIG_ETRAX_SER1_DTR_ON_PB_BIT+CONFIG_ETRAX_SER1_RI_ON_PB_BIT+CONFIG_ETRAX_SER1_DSR_ON_PB_BIT+CONFIG_ETRAX_SER1_CD_ON_PB_BIT)
611
612#if SER1_PB_BITSUM != -4
613# if CONFIG_ETRAX_SER1_DTR_ON_PB_BIT == -1
614# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
615# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
616# endif
617# endif
618# if CONFIG_ETRAX_SER1_RI_ON_PB_BIT == -1
619# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
620# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
621# endif
622# endif
623# if CONFIG_ETRAX_SER1_DSR_ON_PB_BIT == -1
624# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
625# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
626# endif
627# endif
628# if CONFIG_ETRAX_SER1_CD_ON_PB_BIT == -1
629# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
630# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
631# endif
632# endif
633#endif
634
635#endif /* PORT1 */
636
637#ifdef CONFIG_ETRAX_SERIAL_PORT2
638
639#define SER2_PA_BITSUM (CONFIG_ETRAX_SER2_DTR_ON_PA_BIT+CONFIG_ETRAX_SER2_RI_ON_PA_BIT+CONFIG_ETRAX_SER2_DSR_ON_PA_BIT+CONFIG_ETRAX_SER2_CD_ON_PA_BIT)
640
641#if SER2_PA_BITSUM != -4
642# if CONFIG_ETRAX_SER2_DTR_ON_PA_BIT == -1
643# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
644# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
645# endif
646# endif
647# if CONFIG_ETRAX_SER2_RI_ON_PA_BIT == -1
648# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
649# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
650# endif
651# endif
652# if CONFIG_ETRAX_SER2_DSR_ON_PA_BIT == -1
653# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
654# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
655# endif
656# endif
657# if CONFIG_ETRAX_SER2_CD_ON_PA_BIT == -1
658# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
659# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
660# endif
661# endif
662#endif
663
664#define SER2_PB_BITSUM (CONFIG_ETRAX_SER2_DTR_ON_PB_BIT+CONFIG_ETRAX_SER2_RI_ON_PB_BIT+CONFIG_ETRAX_SER2_DSR_ON_PB_BIT+CONFIG_ETRAX_SER2_CD_ON_PB_BIT)
665
666#if SER2_PB_BITSUM != -4
667# if CONFIG_ETRAX_SER2_DTR_ON_PB_BIT == -1
668# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
669# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
670# endif
671# endif
672# if CONFIG_ETRAX_SER2_RI_ON_PB_BIT == -1
673# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
674# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
675# endif
676# endif
677# if CONFIG_ETRAX_SER2_DSR_ON_PB_BIT == -1
678# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
679# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
680# endif
681# endif
682# if CONFIG_ETRAX_SER2_CD_ON_PB_BIT == -1
683# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
684# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
685# endif
686# endif
687#endif
688
689#endif /* PORT2 */
690
691#ifdef CONFIG_ETRAX_SERIAL_PORT3
692
693#define SER3_PA_BITSUM (CONFIG_ETRAX_SER3_DTR_ON_PA_BIT+CONFIG_ETRAX_SER3_RI_ON_PA_BIT+CONFIG_ETRAX_SER3_DSR_ON_PA_BIT+CONFIG_ETRAX_SER3_CD_ON_PA_BIT)
694
695#if SER3_PA_BITSUM != -4
696# if CONFIG_ETRAX_SER3_DTR_ON_PA_BIT == -1
697# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
698# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
699# endif
700# endif
701# if CONFIG_ETRAX_SER3_RI_ON_PA_BIT == -1
702# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
703# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
704# endif
705# endif
706# if CONFIG_ETRAX_SER3_DSR_ON_PA_BIT == -1
707# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
708# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
709# endif
710# endif
711# if CONFIG_ETRAX_SER3_CD_ON_PA_BIT == -1
712# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
713# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
714# endif
715# endif
716#endif
717
718#define SER3_PB_BITSUM (CONFIG_ETRAX_SER3_DTR_ON_PB_BIT+CONFIG_ETRAX_SER3_RI_ON_PB_BIT+CONFIG_ETRAX_SER3_DSR_ON_PB_BIT+CONFIG_ETRAX_SER3_CD_ON_PB_BIT)
719
720#if SER3_PB_BITSUM != -4
721# if CONFIG_ETRAX_SER3_DTR_ON_PB_BIT == -1
722# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
723# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
724# endif
725# endif
726# if CONFIG_ETRAX_SER3_RI_ON_PB_BIT == -1
727# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
728# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
729# endif
730# endif
731# if CONFIG_ETRAX_SER3_DSR_ON_PB_BIT == -1
732# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
733# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
734# endif
735# endif
736# if CONFIG_ETRAX_SER3_CD_ON_PB_BIT == -1
737# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
738# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
739# endif
740# endif
741#endif
742
743#endif /* PORT3 */
744
745
746#if defined(CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED) || \
747 defined(CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED) || \
748 defined(CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED) || \
749 defined(CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED)
750#define CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED
751#endif
752
753#ifdef CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED
754/* The pins can be mixed on PA and PB */
755#define CONTROL_PINS_PORT_NOT_USED(line) \
756 &dummy_ser[line], &dummy_ser[line], \
757 &dummy_ser[line], &dummy_ser[line], \
758 &dummy_ser[line], &dummy_ser[line], \
759 &dummy_ser[line], &dummy_ser[line], \
760 DUMMY_DTR_MASK, DUMMY_RI_MASK, DUMMY_DSR_MASK, DUMMY_CD_MASK
761
762
763struct control_pins
764{
765 volatile unsigned char *dtr_port;
766 unsigned char *dtr_shadow;
767 volatile unsigned char *ri_port;
768 unsigned char *ri_shadow;
769 volatile unsigned char *dsr_port;
770 unsigned char *dsr_shadow;
771 volatile unsigned char *cd_port;
772 unsigned char *cd_shadow;
773
774 unsigned char dtr_mask;
775 unsigned char ri_mask;
776 unsigned char dsr_mask;
777 unsigned char cd_mask;
778};
779
780static const struct control_pins e100_modem_pins[NR_PORTS] =
781{
782 /* Ser 0 */
783 {
784#ifdef CONFIG_ETRAX_SERIAL_PORT0
785 E100_STRUCT_PORT(0,DTR), E100_STRUCT_SHADOW(0,DTR),
786 E100_STRUCT_PORT(0,RI), E100_STRUCT_SHADOW(0,RI),
787 E100_STRUCT_PORT(0,DSR), E100_STRUCT_SHADOW(0,DSR),
788 E100_STRUCT_PORT(0,CD), E100_STRUCT_SHADOW(0,CD),
789 E100_STRUCT_MASK(0,DTR),
790 E100_STRUCT_MASK(0,RI),
791 E100_STRUCT_MASK(0,DSR),
792 E100_STRUCT_MASK(0,CD)
793#else
794 CONTROL_PINS_PORT_NOT_USED(0)
795#endif
796 },
797
798 /* Ser 1 */
799 {
800#ifdef CONFIG_ETRAX_SERIAL_PORT1
801 E100_STRUCT_PORT(1,DTR), E100_STRUCT_SHADOW(1,DTR),
802 E100_STRUCT_PORT(1,RI), E100_STRUCT_SHADOW(1,RI),
803 E100_STRUCT_PORT(1,DSR), E100_STRUCT_SHADOW(1,DSR),
804 E100_STRUCT_PORT(1,CD), E100_STRUCT_SHADOW(1,CD),
805 E100_STRUCT_MASK(1,DTR),
806 E100_STRUCT_MASK(1,RI),
807 E100_STRUCT_MASK(1,DSR),
808 E100_STRUCT_MASK(1,CD)
809#else
810 CONTROL_PINS_PORT_NOT_USED(1)
811#endif
812 },
813
814 /* Ser 2 */
815 {
816#ifdef CONFIG_ETRAX_SERIAL_PORT2
817 E100_STRUCT_PORT(2,DTR), E100_STRUCT_SHADOW(2,DTR),
818 E100_STRUCT_PORT(2,RI), E100_STRUCT_SHADOW(2,RI),
819 E100_STRUCT_PORT(2,DSR), E100_STRUCT_SHADOW(2,DSR),
820 E100_STRUCT_PORT(2,CD), E100_STRUCT_SHADOW(2,CD),
821 E100_STRUCT_MASK(2,DTR),
822 E100_STRUCT_MASK(2,RI),
823 E100_STRUCT_MASK(2,DSR),
824 E100_STRUCT_MASK(2,CD)
825#else
826 CONTROL_PINS_PORT_NOT_USED(2)
827#endif
828 },
829
830 /* Ser 3 */
831 {
832#ifdef CONFIG_ETRAX_SERIAL_PORT3
833 E100_STRUCT_PORT(3,DTR), E100_STRUCT_SHADOW(3,DTR),
834 E100_STRUCT_PORT(3,RI), E100_STRUCT_SHADOW(3,RI),
835 E100_STRUCT_PORT(3,DSR), E100_STRUCT_SHADOW(3,DSR),
836 E100_STRUCT_PORT(3,CD), E100_STRUCT_SHADOW(3,CD),
837 E100_STRUCT_MASK(3,DTR),
838 E100_STRUCT_MASK(3,RI),
839 E100_STRUCT_MASK(3,DSR),
840 E100_STRUCT_MASK(3,CD)
841#else
842 CONTROL_PINS_PORT_NOT_USED(3)
843#endif
844 }
845};
846#else /* CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED */
847
848/* All pins are on either PA or PB for each serial port */
849#define CONTROL_PINS_PORT_NOT_USED(line) \
850 &dummy_ser[line], &dummy_ser[line], \
851 DUMMY_DTR_MASK, DUMMY_RI_MASK, DUMMY_DSR_MASK, DUMMY_CD_MASK
852
853
854struct control_pins
855{
856 volatile unsigned char *port;
857 unsigned char *shadow;
858
859 unsigned char dtr_mask;
860 unsigned char ri_mask;
861 unsigned char dsr_mask;
862 unsigned char cd_mask;
863};
864
865#define dtr_port port
866#define dtr_shadow shadow
867#define ri_port port
868#define ri_shadow shadow
869#define dsr_port port
870#define dsr_shadow shadow
871#define cd_port port
872#define cd_shadow shadow
873
874static const struct control_pins e100_modem_pins[NR_PORTS] =
875{
876 /* Ser 0 */
877 {
878#ifdef CONFIG_ETRAX_SERIAL_PORT0
879 E100_STRUCT_PORT(0,DTR), E100_STRUCT_SHADOW(0,DTR),
880 E100_STRUCT_MASK(0,DTR),
881 E100_STRUCT_MASK(0,RI),
882 E100_STRUCT_MASK(0,DSR),
883 E100_STRUCT_MASK(0,CD)
884#else
885 CONTROL_PINS_PORT_NOT_USED(0)
886#endif
887 },
888
889 /* Ser 1 */
890 {
891#ifdef CONFIG_ETRAX_SERIAL_PORT1
892 E100_STRUCT_PORT(1,DTR), E100_STRUCT_SHADOW(1,DTR),
893 E100_STRUCT_MASK(1,DTR),
894 E100_STRUCT_MASK(1,RI),
895 E100_STRUCT_MASK(1,DSR),
896 E100_STRUCT_MASK(1,CD)
897#else
898 CONTROL_PINS_PORT_NOT_USED(1)
899#endif
900 },
901
902 /* Ser 2 */
903 {
904#ifdef CONFIG_ETRAX_SERIAL_PORT2
905 E100_STRUCT_PORT(2,DTR), E100_STRUCT_SHADOW(2,DTR),
906 E100_STRUCT_MASK(2,DTR),
907 E100_STRUCT_MASK(2,RI),
908 E100_STRUCT_MASK(2,DSR),
909 E100_STRUCT_MASK(2,CD)
910#else
911 CONTROL_PINS_PORT_NOT_USED(2)
912#endif
913 },
914
915 /* Ser 3 */
916 {
917#ifdef CONFIG_ETRAX_SERIAL_PORT3
918 E100_STRUCT_PORT(3,DTR), E100_STRUCT_SHADOW(3,DTR),
919 E100_STRUCT_MASK(3,DTR),
920 E100_STRUCT_MASK(3,RI),
921 E100_STRUCT_MASK(3,DSR),
922 E100_STRUCT_MASK(3,CD)
923#else
924 CONTROL_PINS_PORT_NOT_USED(3)
925#endif
926 }
927};
928#endif /* !CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED */
929
930#define E100_RTS_MASK 0x20
931#define E100_CTS_MASK 0x40
932
933/* All serial port signals are active low:
934 * active = 0 -> 3.3V to RS-232 driver -> -12V on RS-232 level
935 * inactive = 1 -> 0V to RS-232 driver -> +12V on RS-232 level
936 *
937 * These macros returns the pin value: 0=0V, >=1 = 3.3V on ETRAX chip
938 */
939
940/* Output */
941#define E100_RTS_GET(info) ((info)->rx_ctrl & E100_RTS_MASK)
942/* Input */
943#define E100_CTS_GET(info) ((info)->ioport[REG_STATUS] & E100_CTS_MASK)
944
945/* These are typically PA or PB and 0 means 0V, 1 means 3.3V */
946/* Is an output */
947#define E100_DTR_GET(info) ((*e100_modem_pins[(info)->line].dtr_shadow) & e100_modem_pins[(info)->line].dtr_mask)
948
949/* Normally inputs */
950#define E100_RI_GET(info) ((*e100_modem_pins[(info)->line].ri_port) & e100_modem_pins[(info)->line].ri_mask)
951#define E100_CD_GET(info) ((*e100_modem_pins[(info)->line].cd_port) & e100_modem_pins[(info)->line].cd_mask)
952
953/* Input */
954#define E100_DSR_GET(info) ((*e100_modem_pins[(info)->line].dsr_port) & e100_modem_pins[(info)->line].dsr_mask)
955
956
957/*
958 * tmp_buf is used as a temporary buffer by serial_write. We need to
959 * lock it in case the memcpy_fromfs blocks while swapping in a page,
960 * and some other program tries to do a serial write at the same time.
961 * Since the lock will only come under contention when the system is
962 * swapping and available memory is low, it makes sense to share one
963 * buffer across all the serial ports, since it significantly saves
964 * memory if large numbers of serial ports are open.
965 */
966static unsigned char *tmp_buf;
967static DEFINE_MUTEX(tmp_buf_mutex);
968
969/* Calculate the chartime depending on baudrate, numbor of bits etc. */
970static void update_char_time(struct e100_serial * info)
971{
972 tcflag_t cflags = info->port.tty->termios->c_cflag;
973 int bits;
974
975 /* calc. number of bits / data byte */
976 /* databits + startbit and 1 stopbit */
977 if ((cflags & CSIZE) == CS7)
978 bits = 9;
979 else
980 bits = 10;
981
982 if (cflags & CSTOPB) /* 2 stopbits ? */
983 bits++;
984
985 if (cflags & PARENB) /* parity bit ? */
986 bits++;
987
988 /* calc timeout */
989 info->char_time_usec = ((bits * 1000000) / info->baud) + 1;
990 info->flush_time_usec = 4*info->char_time_usec;
991 if (info->flush_time_usec < MIN_FLUSH_TIME_USEC)
992 info->flush_time_usec = MIN_FLUSH_TIME_USEC;
993
994}
995
996/*
997 * This function maps from the Bxxxx defines in asm/termbits.h into real
998 * baud rates.
999 */
1000
1001static int
1002cflag_to_baud(unsigned int cflag)
1003{
1004 static int baud_table[] = {
1005 0, 50, 75, 110, 134, 150, 200, 300, 600, 1200, 1800, 2400,
1006 4800, 9600, 19200, 38400 };
1007
1008 static int ext_baud_table[] = {
1009 0, 57600, 115200, 230400, 460800, 921600, 1843200, 6250000,
1010 0, 0, 0, 0, 0, 0, 0, 0 };
1011
1012 if (cflag & CBAUDEX)
1013 return ext_baud_table[(cflag & CBAUD) & ~CBAUDEX];
1014 else
1015 return baud_table[cflag & CBAUD];
1016}
1017
1018/* and this maps to an etrax100 hardware baud constant */
1019
1020static unsigned char
1021cflag_to_etrax_baud(unsigned int cflag)
1022{
1023 char retval;
1024
1025 static char baud_table[] = {
1026 -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, -1, 3, 4, 5, 6, 7 };
1027
1028 static char ext_baud_table[] = {
1029 -1, 8, 9, 10, 11, 12, 13, 14, -1, -1, -1, -1, -1, -1, -1, -1 };
1030
1031 if (cflag & CBAUDEX)
1032 retval = ext_baud_table[(cflag & CBAUD) & ~CBAUDEX];
1033 else
1034 retval = baud_table[cflag & CBAUD];
1035
1036 if (retval < 0) {
1037 printk(KERN_WARNING "serdriver tried setting invalid baud rate, flags %x.\n", cflag);
1038 retval = 5; /* choose default 9600 instead */
1039 }
1040
1041 return retval | (retval << 4); /* choose same for both TX and RX */
1042}
1043
1044
1045/* Various static support functions */
1046
1047/* Functions to set or clear DTR/RTS on the requested line */
1048/* It is complicated by the fact that RTS is a serial port register, while
1049 * DTR might not be implemented in the HW at all, and if it is, it can be on
1050 * any general port.
1051 */
1052
1053
1054static inline void
1055e100_dtr(struct e100_serial *info, int set)
1056{
1057#ifndef CONFIG_SVINTO_SIM
1058 unsigned char mask = e100_modem_pins[info->line].dtr_mask;
1059
1060#ifdef SERIAL_DEBUG_IO
1061 printk("ser%i dtr %i mask: 0x%02X\n", info->line, set, mask);
1062 printk("ser%i shadow before 0x%02X get: %i\n",
1063 info->line, *e100_modem_pins[info->line].dtr_shadow,
1064 E100_DTR_GET(info));
1065#endif
1066 /* DTR is active low */
1067 {
1068 unsigned long flags;
1069
1070 local_irq_save(flags);
1071 *e100_modem_pins[info->line].dtr_shadow &= ~mask;
1072 *e100_modem_pins[info->line].dtr_shadow |= (set ? 0 : mask);
1073 *e100_modem_pins[info->line].dtr_port = *e100_modem_pins[info->line].dtr_shadow;
1074 local_irq_restore(flags);
1075 }
1076
1077#ifdef SERIAL_DEBUG_IO
1078 printk("ser%i shadow after 0x%02X get: %i\n",
1079 info->line, *e100_modem_pins[info->line].dtr_shadow,
1080 E100_DTR_GET(info));
1081#endif
1082#endif
1083}
1084
1085/* set = 0 means 3.3V on the pin, bitvalue: 0=active, 1=inactive
1086 * 0=0V , 1=3.3V
1087 */
1088static inline void
1089e100_rts(struct e100_serial *info, int set)
1090{
1091#ifndef CONFIG_SVINTO_SIM
1092 unsigned long flags;
1093 local_irq_save(flags);
1094 info->rx_ctrl &= ~E100_RTS_MASK;
1095 info->rx_ctrl |= (set ? 0 : E100_RTS_MASK); /* RTS is active low */
1096 info->ioport[REG_REC_CTRL] = info->rx_ctrl;
1097 local_irq_restore(flags);
1098#ifdef SERIAL_DEBUG_IO
1099 printk("ser%i rts %i\n", info->line, set);
1100#endif
1101#endif
1102}
1103
1104
1105/* If this behaves as a modem, RI and CD is an output */
1106static inline void
1107e100_ri_out(struct e100_serial *info, int set)
1108{
1109#ifndef CONFIG_SVINTO_SIM
1110 /* RI is active low */
1111 {
1112 unsigned char mask = e100_modem_pins[info->line].ri_mask;
1113 unsigned long flags;
1114
1115 local_irq_save(flags);
1116 *e100_modem_pins[info->line].ri_shadow &= ~mask;
1117 *e100_modem_pins[info->line].ri_shadow |= (set ? 0 : mask);
1118 *e100_modem_pins[info->line].ri_port = *e100_modem_pins[info->line].ri_shadow;
1119 local_irq_restore(flags);
1120 }
1121#endif
1122}
1123static inline void
1124e100_cd_out(struct e100_serial *info, int set)
1125{
1126#ifndef CONFIG_SVINTO_SIM
1127 /* CD is active low */
1128 {
1129 unsigned char mask = e100_modem_pins[info->line].cd_mask;
1130 unsigned long flags;
1131
1132 local_irq_save(flags);
1133 *e100_modem_pins[info->line].cd_shadow &= ~mask;
1134 *e100_modem_pins[info->line].cd_shadow |= (set ? 0 : mask);
1135 *e100_modem_pins[info->line].cd_port = *e100_modem_pins[info->line].cd_shadow;
1136 local_irq_restore(flags);
1137 }
1138#endif
1139}
1140
1141static inline void
1142e100_disable_rx(struct e100_serial *info)
1143{
1144#ifndef CONFIG_SVINTO_SIM
1145 /* disable the receiver */
1146 info->ioport[REG_REC_CTRL] =
1147 (info->rx_ctrl &= ~IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));
1148#endif
1149}
1150
1151static inline void
1152e100_enable_rx(struct e100_serial *info)
1153{
1154#ifndef CONFIG_SVINTO_SIM
1155 /* enable the receiver */
1156 info->ioport[REG_REC_CTRL] =
1157 (info->rx_ctrl |= IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));
1158#endif
1159}
1160
1161/* the rx DMA uses both the dma_descr and the dma_eop interrupts */
1162
1163static inline void
1164e100_disable_rxdma_irq(struct e100_serial *info)
1165{
1166#ifdef SERIAL_DEBUG_INTR
1167 printk("rxdma_irq(%d): 0\n",info->line);
1168#endif
1169 DINTR1(DEBUG_LOG(info->line,"IRQ disable_rxdma_irq %i\n", info->line));
1170 *R_IRQ_MASK2_CLR = (info->irq << 2) | (info->irq << 3);
1171}
1172
1173static inline void
1174e100_enable_rxdma_irq(struct e100_serial *info)
1175{
1176#ifdef SERIAL_DEBUG_INTR
1177 printk("rxdma_irq(%d): 1\n",info->line);
1178#endif
1179 DINTR1(DEBUG_LOG(info->line,"IRQ enable_rxdma_irq %i\n", info->line));
1180 *R_IRQ_MASK2_SET = (info->irq << 2) | (info->irq << 3);
1181}
1182
1183/* the tx DMA uses only dma_descr interrupt */
1184
1185static void e100_disable_txdma_irq(struct e100_serial *info)
1186{
1187#ifdef SERIAL_DEBUG_INTR
1188 printk("txdma_irq(%d): 0\n",info->line);
1189#endif
1190 DINTR1(DEBUG_LOG(info->line,"IRQ disable_txdma_irq %i\n", info->line));
1191 *R_IRQ_MASK2_CLR = info->irq;
1192}
1193
1194static void e100_enable_txdma_irq(struct e100_serial *info)
1195{
1196#ifdef SERIAL_DEBUG_INTR
1197 printk("txdma_irq(%d): 1\n",info->line);
1198#endif
1199 DINTR1(DEBUG_LOG(info->line,"IRQ enable_txdma_irq %i\n", info->line));
1200 *R_IRQ_MASK2_SET = info->irq;
1201}
1202
1203static void e100_disable_txdma_channel(struct e100_serial *info)
1204{
1205 unsigned long flags;
1206
1207 /* Disable output DMA channel for the serial port in question
1208 * ( set to something other than serialX)
1209 */
1210 local_irq_save(flags);
1211 DFLOW(DEBUG_LOG(info->line, "disable_txdma_channel %i\n", info->line));
1212 if (info->line == 0) {
1213 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma6)) ==
1214 IO_STATE(R_GEN_CONFIG, dma6, serial0)) {
1215 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6);
1216 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, unused);
1217 }
1218 } else if (info->line == 1) {
1219 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma8)) ==
1220 IO_STATE(R_GEN_CONFIG, dma8, serial1)) {
1221 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8);
1222 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, usb);
1223 }
1224 } else if (info->line == 2) {
1225 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma2)) ==
1226 IO_STATE(R_GEN_CONFIG, dma2, serial2)) {
1227 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2);
1228 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, par0);
1229 }
1230 } else if (info->line == 3) {
1231 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma4)) ==
1232 IO_STATE(R_GEN_CONFIG, dma4, serial3)) {
1233 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4);
1234 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, par1);
1235 }
1236 }
1237 *R_GEN_CONFIG = genconfig_shadow;
1238 local_irq_restore(flags);
1239}
1240
1241
1242static void e100_enable_txdma_channel(struct e100_serial *info)
1243{
1244 unsigned long flags;
1245
1246 local_irq_save(flags);
1247 DFLOW(DEBUG_LOG(info->line, "enable_txdma_channel %i\n", info->line));
1248 /* Enable output DMA channel for the serial port in question */
1249 if (info->line == 0) {
1250 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6);
1251 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, serial0);
1252 } else if (info->line == 1) {
1253 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8);
1254 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, serial1);
1255 } else if (info->line == 2) {
1256 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2);
1257 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, serial2);
1258 } else if (info->line == 3) {
1259 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4);
1260 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, serial3);
1261 }
1262 *R_GEN_CONFIG = genconfig_shadow;
1263 local_irq_restore(flags);
1264}
1265
1266static void e100_disable_rxdma_channel(struct e100_serial *info)
1267{
1268 unsigned long flags;
1269
1270 /* Disable input DMA channel for the serial port in question
1271 * ( set to something other than serialX)
1272 */
1273 local_irq_save(flags);
1274 if (info->line == 0) {
1275 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma7)) ==
1276 IO_STATE(R_GEN_CONFIG, dma7, serial0)) {
1277 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma7);
1278 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, unused);
1279 }
1280 } else if (info->line == 1) {
1281 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma9)) ==
1282 IO_STATE(R_GEN_CONFIG, dma9, serial1)) {
1283 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma9);
1284 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, usb);
1285 }
1286 } else if (info->line == 2) {
1287 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma3)) ==
1288 IO_STATE(R_GEN_CONFIG, dma3, serial2)) {
1289 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3);
1290 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, par0);
1291 }
1292 } else if (info->line == 3) {
1293 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma5)) ==
1294 IO_STATE(R_GEN_CONFIG, dma5, serial3)) {
1295 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5);
1296 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, par1);
1297 }
1298 }
1299 *R_GEN_CONFIG = genconfig_shadow;
1300 local_irq_restore(flags);
1301}
1302
1303
1304static void e100_enable_rxdma_channel(struct e100_serial *info)
1305{
1306 unsigned long flags;
1307
1308 local_irq_save(flags);
1309 /* Enable input DMA channel for the serial port in question */
1310 if (info->line == 0) {
1311 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma7);
1312 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, serial0);
1313 } else if (info->line == 1) {
1314 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma9);
1315 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, serial1);
1316 } else if (info->line == 2) {
1317 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3);
1318 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, serial2);
1319 } else if (info->line == 3) {
1320 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5);
1321 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, serial3);
1322 }
1323 *R_GEN_CONFIG = genconfig_shadow;
1324 local_irq_restore(flags);
1325}
1326
1327#ifdef SERIAL_HANDLE_EARLY_ERRORS
1328/* in order to detect and fix errors on the first byte
1329 we have to use the serial interrupts as well. */
1330
1331static inline void
1332e100_disable_serial_data_irq(struct e100_serial *info)
1333{
1334#ifdef SERIAL_DEBUG_INTR
1335 printk("ser_irq(%d): 0\n",info->line);
1336#endif
1337 DINTR1(DEBUG_LOG(info->line,"IRQ disable data_irq %i\n", info->line));
1338 *R_IRQ_MASK1_CLR = (1U << (8+2*info->line));
1339}
1340
1341static inline void
1342e100_enable_serial_data_irq(struct e100_serial *info)
1343{
1344#ifdef SERIAL_DEBUG_INTR
1345 printk("ser_irq(%d): 1\n",info->line);
1346 printk("**** %d = %d\n",
1347 (8+2*info->line),
1348 (1U << (8+2*info->line)));
1349#endif
1350 DINTR1(DEBUG_LOG(info->line,"IRQ enable data_irq %i\n", info->line));
1351 *R_IRQ_MASK1_SET = (1U << (8+2*info->line));
1352}
1353#endif
1354
1355static inline void
1356e100_disable_serial_tx_ready_irq(struct e100_serial *info)
1357{
1358#ifdef SERIAL_DEBUG_INTR
1359 printk("ser_tx_irq(%d): 0\n",info->line);
1360#endif
1361 DINTR1(DEBUG_LOG(info->line,"IRQ disable ready_irq %i\n", info->line));
1362 *R_IRQ_MASK1_CLR = (1U << (8+1+2*info->line));
1363}
1364
1365static inline void
1366e100_enable_serial_tx_ready_irq(struct e100_serial *info)
1367{
1368#ifdef SERIAL_DEBUG_INTR
1369 printk("ser_tx_irq(%d): 1\n",info->line);
1370 printk("**** %d = %d\n",
1371 (8+1+2*info->line),
1372 (1U << (8+1+2*info->line)));
1373#endif
1374 DINTR2(DEBUG_LOG(info->line,"IRQ enable ready_irq %i\n", info->line));
1375 *R_IRQ_MASK1_SET = (1U << (8+1+2*info->line));
1376}
1377
1378static inline void e100_enable_rx_irq(struct e100_serial *info)
1379{
1380 if (info->uses_dma_in)
1381 e100_enable_rxdma_irq(info);
1382 else
1383 e100_enable_serial_data_irq(info);
1384}
1385static inline void e100_disable_rx_irq(struct e100_serial *info)
1386{
1387 if (info->uses_dma_in)
1388 e100_disable_rxdma_irq(info);
1389 else
1390 e100_disable_serial_data_irq(info);
1391}
1392
1393#if defined(CONFIG_ETRAX_RS485)
1394/* Enable RS-485 mode on selected port. This is UGLY. */
1395static int
1396e100_enable_rs485(struct tty_struct *tty, struct serial_rs485 *r)
1397{
1398 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
1399
1400#if defined(CONFIG_ETRAX_RS485_ON_PA)
1401 *R_PORT_PA_DATA = port_pa_data_shadow |= (1 << rs485_pa_bit);
1402#endif
1403#if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
1404 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
1405 rs485_port_g_bit, 1);
1406#endif
1407#if defined(CONFIG_ETRAX_RS485_LTC1387)
1408 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
1409 CONFIG_ETRAX_RS485_LTC1387_DXEN_PORT_G_BIT, 1);
1410 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
1411 CONFIG_ETRAX_RS485_LTC1387_RXEN_PORT_G_BIT, 1);
1412#endif
1413
1414 info->rs485.flags = r->flags;
1415 if (r->delay_rts_before_send >= 1000)
1416 info->rs485.delay_rts_before_send = 1000;
1417 else
1418 info->rs485.delay_rts_before_send = r->delay_rts_before_send;
1419/* printk("rts: on send = %i, after = %i, enabled = %i",
1420 info->rs485.rts_on_send,
1421 info->rs485.rts_after_sent,
1422 info->rs485.enabled
1423 );
1424*/
1425 return 0;
1426}
1427
1428static int
1429e100_write_rs485(struct tty_struct *tty,
1430 const unsigned char *buf, int count)
1431{
1432 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
1433 int old_value = (info->rs485.flags) & SER_RS485_ENABLED;
1434
1435 /* rs485 is always implicitly enabled if we're using the ioctl()
1436 * but it doesn't have to be set in the serial_rs485
1437 * (to be backward compatible with old apps)
1438 * So we store, set and restore it.
1439 */
1440 info->rs485.flags |= SER_RS485_ENABLED;
1441 /* rs_write now deals with RS485 if enabled */
1442 count = rs_write(tty, buf, count);
1443 if (!old_value)
1444 info->rs485.flags &= ~(SER_RS485_ENABLED);
1445 return count;
1446}
1447
1448#ifdef CONFIG_ETRAX_FAST_TIMER
1449/* Timer function to toggle RTS when using FAST_TIMER */
1450static void rs485_toggle_rts_timer_function(unsigned long data)
1451{
1452 struct e100_serial *info = (struct e100_serial *)data;
1453
1454 fast_timers_rs485[info->line].function = NULL;
1455 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_AFTER_SEND));
1456#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
1457 e100_enable_rx(info);
1458 e100_enable_rx_irq(info);
1459#endif
1460}
1461#endif
1462#endif /* CONFIG_ETRAX_RS485 */
1463
1464/*
1465 * ------------------------------------------------------------
1466 * rs_stop() and rs_start()
1467 *
1468 * This routines are called before setting or resetting tty->stopped.
1469 * They enable or disable transmitter using the XOFF registers, as necessary.
1470 * ------------------------------------------------------------
1471 */
1472
1473static void
1474rs_stop(struct tty_struct *tty)
1475{
1476 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
1477 if (info) {
1478 unsigned long flags;
1479 unsigned long xoff;
1480
1481 local_irq_save(flags);
1482 DFLOW(DEBUG_LOG(info->line, "XOFF rs_stop xmit %i\n",
1483 CIRC_CNT(info->xmit.head,
1484 info->xmit.tail,SERIAL_XMIT_SIZE)));
1485
1486 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char,
1487 STOP_CHAR(info->port.tty));
1488 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, stop);
1489 if (tty->termios->c_iflag & IXON ) {
1490 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
1491 }
1492
1493 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
1494 local_irq_restore(flags);
1495 }
1496}
1497
1498static void
1499rs_start(struct tty_struct *tty)
1500{
1501 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
1502 if (info) {
1503 unsigned long flags;
1504 unsigned long xoff;
1505
1506 local_irq_save(flags);
1507 DFLOW(DEBUG_LOG(info->line, "XOFF rs_start xmit %i\n",
1508 CIRC_CNT(info->xmit.head,
1509 info->xmit.tail,SERIAL_XMIT_SIZE)));
1510 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(tty));
1511 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable);
1512 if (tty->termios->c_iflag & IXON ) {
1513 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
1514 }
1515
1516 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
1517 if (!info->uses_dma_out &&
1518 info->xmit.head != info->xmit.tail && info->xmit.buf)
1519 e100_enable_serial_tx_ready_irq(info);
1520
1521 local_irq_restore(flags);
1522 }
1523}
1524
1525/*
1526 * ----------------------------------------------------------------------
1527 *
1528 * Here starts the interrupt handling routines. All of the following
1529 * subroutines are declared as inline and are folded into
1530 * rs_interrupt(). They were separated out for readability's sake.
1531 *
1532 * Note: rs_interrupt() is a "fast" interrupt, which means that it
1533 * runs with interrupts turned off. People who may want to modify
1534 * rs_interrupt() should try to keep the interrupt handler as fast as
1535 * possible. After you are done making modifications, it is not a bad
1536 * idea to do:
1537 *
1538 * gcc -S -DKERNEL -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer serial.c
1539 *
1540 * and look at the resulting assemble code in serial.s.
1541 *
1542 * - Ted Ts'o (tytso@mit.edu), 7-Mar-93
1543 * -----------------------------------------------------------------------
1544 */
1545
1546/*
1547 * This routine is used by the interrupt handler to schedule
1548 * processing in the software interrupt portion of the driver.
1549 */
1550static void rs_sched_event(struct e100_serial *info, int event)
1551{
1552 if (info->event & (1 << event))
1553 return;
1554 info->event |= 1 << event;
1555 schedule_work(&info->work);
1556}
1557
1558/* The output DMA channel is free - use it to send as many chars as possible
1559 * NOTES:
1560 * We don't pay attention to info->x_char, which means if the TTY wants to
1561 * use XON/XOFF it will set info->x_char but we won't send any X char!
1562 *
1563 * To implement this, we'd just start a DMA send of 1 byte pointing at a
1564 * buffer containing the X char, and skip updating xmit. We'd also have to
1565 * check if the last sent char was the X char when we enter this function
1566 * the next time, to avoid updating xmit with the sent X value.
1567 */
1568
1569static void
1570transmit_chars_dma(struct e100_serial *info)
1571{
1572 unsigned int c, sentl;
1573 struct etrax_dma_descr *descr;
1574
1575#ifdef CONFIG_SVINTO_SIM
1576 /* This will output too little if tail is not 0 always since
1577 * we don't reloop to send the other part. Anyway this SHOULD be a
1578 * no-op - transmit_chars_dma would never really be called during sim
1579 * since rs_write does not write into the xmit buffer then.
1580 */
1581 if (info->xmit.tail)
1582 printk("Error in serial.c:transmit_chars-dma(), tail!=0\n");
1583 if (info->xmit.head != info->xmit.tail) {
1584 SIMCOUT(info->xmit.buf + info->xmit.tail,
1585 CIRC_CNT(info->xmit.head,
1586 info->xmit.tail,
1587 SERIAL_XMIT_SIZE));
1588 info->xmit.head = info->xmit.tail; /* move back head */
1589 info->tr_running = 0;
1590 }
1591 return;
1592#endif
1593 /* acknowledge both dma_descr and dma_eop irq in R_DMA_CHx_CLR_INTR */
1594 *info->oclrintradr =
1595 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
1596 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
1597
1598#ifdef SERIAL_DEBUG_INTR
1599 if (info->line == SERIAL_DEBUG_LINE)
1600 printk("tc\n");
1601#endif
1602 if (!info->tr_running) {
1603 /* weirdo... we shouldn't get here! */
1604 printk(KERN_WARNING "Achtung: transmit_chars_dma with !tr_running\n");
1605 return;
1606 }
1607
1608 descr = &info->tr_descr;
1609
1610 /* first get the amount of bytes sent during the last DMA transfer,
1611 and update xmit accordingly */
1612
1613 /* if the stop bit was not set, all data has been sent */
1614 if (!(descr->status & d_stop)) {
1615 sentl = descr->sw_len;
1616 } else
1617 /* otherwise we find the amount of data sent here */
1618 sentl = descr->hw_len;
1619
1620 DFLOW(DEBUG_LOG(info->line, "TX %i done\n", sentl));
1621
1622 /* update stats */
1623 info->icount.tx += sentl;
1624
1625 /* update xmit buffer */
1626 info->xmit.tail = (info->xmit.tail + sentl) & (SERIAL_XMIT_SIZE - 1);
1627
1628 /* if there is only a few chars left in the buf, wake up the blocked
1629 write if any */
1630 if (CIRC_CNT(info->xmit.head,
1631 info->xmit.tail,
1632 SERIAL_XMIT_SIZE) < WAKEUP_CHARS)
1633 rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
1634
1635 /* find out the largest amount of consecutive bytes we want to send now */
1636
1637 c = CIRC_CNT_TO_END(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
1638
1639 /* Don't send all in one DMA transfer - divide it so we wake up
1640 * application before all is sent
1641 */
1642
1643 if (c >= 4*WAKEUP_CHARS)
1644 c = c/2;
1645
1646 if (c <= 0) {
1647 /* our job here is done, don't schedule any new DMA transfer */
1648 info->tr_running = 0;
1649
1650#if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER)
1651 if (info->rs485.flags & SER_RS485_ENABLED) {
1652 /* Set a short timer to toggle RTS */
1653 start_one_shot_timer(&fast_timers_rs485[info->line],
1654 rs485_toggle_rts_timer_function,
1655 (unsigned long)info,
1656 info->char_time_usec*2,
1657 "RS-485");
1658 }
1659#endif /* RS485 */
1660 return;
1661 }
1662
1663 /* ok we can schedule a dma send of c chars starting at info->xmit.tail */
1664 /* set up the descriptor correctly for output */
1665 DFLOW(DEBUG_LOG(info->line, "TX %i\n", c));
1666 descr->ctrl = d_int | d_eol | d_wait; /* Wait needed for tty_wait_until_sent() */
1667 descr->sw_len = c;
1668 descr->buf = virt_to_phys(info->xmit.buf + info->xmit.tail);
1669 descr->status = 0;
1670
1671 *info->ofirstadr = virt_to_phys(descr); /* write to R_DMAx_FIRST */
1672 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start);
1673
1674 /* DMA is now running (hopefully) */
1675} /* transmit_chars_dma */
1676
1677static void
1678start_transmit(struct e100_serial *info)
1679{
1680#if 0
1681 if (info->line == SERIAL_DEBUG_LINE)
1682 printk("x\n");
1683#endif
1684
1685 info->tr_descr.sw_len = 0;
1686 info->tr_descr.hw_len = 0;
1687 info->tr_descr.status = 0;
1688 info->tr_running = 1;
1689 if (info->uses_dma_out)
1690 transmit_chars_dma(info);
1691 else
1692 e100_enable_serial_tx_ready_irq(info);
1693} /* start_transmit */
1694
1695#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
1696static int serial_fast_timer_started = 0;
1697static int serial_fast_timer_expired = 0;
1698static void flush_timeout_function(unsigned long data);
1699#define START_FLUSH_FAST_TIMER_TIME(info, string, usec) {\
1700 unsigned long timer_flags; \
1701 local_irq_save(timer_flags); \
1702 if (fast_timers[info->line].function == NULL) { \
1703 serial_fast_timer_started++; \
1704 TIMERD(DEBUG_LOG(info->line, "start_timer %i ", info->line)); \
1705 TIMERD(DEBUG_LOG(info->line, "num started: %i\n", serial_fast_timer_started)); \
1706 start_one_shot_timer(&fast_timers[info->line], \
1707 flush_timeout_function, \
1708 (unsigned long)info, \
1709 (usec), \
1710 string); \
1711 } \
1712 else { \
1713 TIMERD(DEBUG_LOG(info->line, "timer %i already running\n", info->line)); \
1714 } \
1715 local_irq_restore(timer_flags); \
1716}
1717#define START_FLUSH_FAST_TIMER(info, string) START_FLUSH_FAST_TIMER_TIME(info, string, info->flush_time_usec)
1718
1719#else
1720#define START_FLUSH_FAST_TIMER_TIME(info, string, usec)
1721#define START_FLUSH_FAST_TIMER(info, string)
1722#endif
1723
1724static struct etrax_recv_buffer *
1725alloc_recv_buffer(unsigned int size)
1726{
1727 struct etrax_recv_buffer *buffer;
1728
1729 if (!(buffer = kmalloc(sizeof *buffer + size, GFP_ATOMIC)))
1730 return NULL;
1731
1732 buffer->next = NULL;
1733 buffer->length = 0;
1734 buffer->error = TTY_NORMAL;
1735
1736 return buffer;
1737}
1738
1739static void
1740append_recv_buffer(struct e100_serial *info, struct etrax_recv_buffer *buffer)
1741{
1742 unsigned long flags;
1743
1744 local_irq_save(flags);
1745
1746 if (!info->first_recv_buffer)
1747 info->first_recv_buffer = buffer;
1748 else
1749 info->last_recv_buffer->next = buffer;
1750
1751 info->last_recv_buffer = buffer;
1752
1753 info->recv_cnt += buffer->length;
1754 if (info->recv_cnt > info->max_recv_cnt)
1755 info->max_recv_cnt = info->recv_cnt;
1756
1757 local_irq_restore(flags);
1758}
1759
1760static int
1761add_char_and_flag(struct e100_serial *info, unsigned char data, unsigned char flag)
1762{
1763 struct etrax_recv_buffer *buffer;
1764 if (info->uses_dma_in) {
1765 if (!(buffer = alloc_recv_buffer(4)))
1766 return 0;
1767
1768 buffer->length = 1;
1769 buffer->error = flag;
1770 buffer->buffer[0] = data;
1771
1772 append_recv_buffer(info, buffer);
1773
1774 info->icount.rx++;
1775 } else {
1776 struct tty_struct *tty = info->port.tty;
1777 tty_insert_flip_char(tty, data, flag);
1778 info->icount.rx++;
1779 }
1780
1781 return 1;
1782}
1783
1784static unsigned int handle_descr_data(struct e100_serial *info,
1785 struct etrax_dma_descr *descr,
1786 unsigned int recvl)
1787{
1788 struct etrax_recv_buffer *buffer = phys_to_virt(descr->buf) - sizeof *buffer;
1789
1790 if (info->recv_cnt + recvl > 65536) {
1791 printk(KERN_CRIT
1792 "%s: Too much pending incoming serial data! Dropping %u bytes.\n", __func__, recvl);
1793 return 0;
1794 }
1795
1796 buffer->length = recvl;
1797
1798 if (info->errorcode == ERRCODE_SET_BREAK)
1799 buffer->error = TTY_BREAK;
1800 info->errorcode = 0;
1801
1802 append_recv_buffer(info, buffer);
1803
1804 if (!(buffer = alloc_recv_buffer(SERIAL_DESCR_BUF_SIZE)))
1805 panic("%s: Failed to allocate memory for receive buffer!\n", __func__);
1806
1807 descr->buf = virt_to_phys(buffer->buffer);
1808
1809 return recvl;
1810}
1811
1812static unsigned int handle_all_descr_data(struct e100_serial *info)
1813{
1814 struct etrax_dma_descr *descr;
1815 unsigned int recvl;
1816 unsigned int ret = 0;
1817
1818 while (1)
1819 {
1820 descr = &info->rec_descr[info->cur_rec_descr];
1821
1822 if (descr == phys_to_virt(*info->idescradr))
1823 break;
1824
1825 if (++info->cur_rec_descr == SERIAL_RECV_DESCRIPTORS)
1826 info->cur_rec_descr = 0;
1827
1828 /* find out how many bytes were read */
1829
1830 /* if the eop bit was not set, all data has been received */
1831 if (!(descr->status & d_eop)) {
1832 recvl = descr->sw_len;
1833 } else {
1834 /* otherwise we find the amount of data received here */
1835 recvl = descr->hw_len;
1836 }
1837
1838 /* Reset the status information */
1839 descr->status = 0;
1840
1841 DFLOW( DEBUG_LOG(info->line, "RX %lu\n", recvl);
1842 if (info->port.tty->stopped) {
1843 unsigned char *buf = phys_to_virt(descr->buf);
1844 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[0]);
1845 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[1]);
1846 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[2]);
1847 }
1848 );
1849
1850 /* update stats */
1851 info->icount.rx += recvl;
1852
1853 ret += handle_descr_data(info, descr, recvl);
1854 }
1855
1856 return ret;
1857}
1858
1859static void receive_chars_dma(struct e100_serial *info)
1860{
1861 struct tty_struct *tty;
1862 unsigned char rstat;
1863
1864#ifdef CONFIG_SVINTO_SIM
1865 /* No receive in the simulator. Will probably be when the rest of
1866 * the serial interface works, and this piece will just be removed.
1867 */
1868 return;
1869#endif
1870
1871 /* Acknowledge both dma_descr and dma_eop irq in R_DMA_CHx_CLR_INTR */
1872 *info->iclrintradr =
1873 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
1874 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
1875
1876 tty = info->port.tty;
1877 if (!tty) /* Something wrong... */
1878 return;
1879
1880#ifdef SERIAL_HANDLE_EARLY_ERRORS
1881 if (info->uses_dma_in)
1882 e100_enable_serial_data_irq(info);
1883#endif
1884
1885 if (info->errorcode == ERRCODE_INSERT_BREAK)
1886 add_char_and_flag(info, '\0', TTY_BREAK);
1887
1888 handle_all_descr_data(info);
1889
1890 /* Read the status register to detect errors */
1891 rstat = info->ioport[REG_STATUS];
1892 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {
1893 DFLOW(DEBUG_LOG(info->line, "XOFF detect stat %x\n", rstat));
1894 }
1895
1896 if (rstat & SER_ERROR_MASK) {
1897 /* If we got an error, we must reset it by reading the
1898 * data_in field
1899 */
1900 unsigned char data = info->ioport[REG_DATA];
1901
1902 PROCSTAT(ser_stat[info->line].errors_cnt++);
1903 DEBUG_LOG(info->line, "#dERR: s d 0x%04X\n",
1904 ((rstat & SER_ERROR_MASK) << 8) | data);
1905
1906 if (rstat & SER_PAR_ERR_MASK)
1907 add_char_and_flag(info, data, TTY_PARITY);
1908 else if (rstat & SER_OVERRUN_MASK)
1909 add_char_and_flag(info, data, TTY_OVERRUN);
1910 else if (rstat & SER_FRAMING_ERR_MASK)
1911 add_char_and_flag(info, data, TTY_FRAME);
1912 }
1913
1914 START_FLUSH_FAST_TIMER(info, "receive_chars");
1915
1916 /* Restart the receiving DMA */
1917 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart);
1918}
1919
1920static int start_recv_dma(struct e100_serial *info)
1921{
1922 struct etrax_dma_descr *descr = info->rec_descr;
1923 struct etrax_recv_buffer *buffer;
1924 int i;
1925
1926 /* Set up the receiving descriptors */
1927 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++) {
1928 if (!(buffer = alloc_recv_buffer(SERIAL_DESCR_BUF_SIZE)))
1929 panic("%s: Failed to allocate memory for receive buffer!\n", __func__);
1930
1931 descr[i].ctrl = d_int;
1932 descr[i].buf = virt_to_phys(buffer->buffer);
1933 descr[i].sw_len = SERIAL_DESCR_BUF_SIZE;
1934 descr[i].hw_len = 0;
1935 descr[i].status = 0;
1936 descr[i].next = virt_to_phys(&descr[i+1]);
1937 }
1938
1939 /* Link the last descriptor to the first */
1940 descr[i-1].next = virt_to_phys(&descr[0]);
1941
1942 /* Start with the first descriptor in the list */
1943 info->cur_rec_descr = 0;
1944
1945 /* Start the DMA */
1946 *info->ifirstadr = virt_to_phys(&descr[info->cur_rec_descr]);
1947 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start);
1948
1949 /* Input DMA should be running now */
1950 return 1;
1951}
1952
1953static void
1954start_receive(struct e100_serial *info)
1955{
1956#ifdef CONFIG_SVINTO_SIM
1957 /* No receive in the simulator. Will probably be when the rest of
1958 * the serial interface works, and this piece will just be removed.
1959 */
1960 return;
1961#endif
1962 if (info->uses_dma_in) {
1963 /* reset the input dma channel to be sure it works */
1964
1965 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
1966 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->icmdadr) ==
1967 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
1968
1969 start_recv_dma(info);
1970 }
1971}
1972
1973
1974/* the bits in the MASK2 register are laid out like this:
1975 DMAI_EOP DMAI_DESCR DMAO_EOP DMAO_DESCR
1976 where I is the input channel and O is the output channel for the port.
1977 info->irq is the bit number for the DMAO_DESCR so to check the others we
1978 shift info->irq to the left.
1979*/
1980
1981/* dma output channel interrupt handler
1982 this interrupt is called from DMA2(ser2), DMA4(ser3), DMA6(ser0) or
1983 DMA8(ser1) when they have finished a descriptor with the intr flag set.
1984*/
1985
1986static irqreturn_t
1987tr_interrupt(int irq, void *dev_id)
1988{
1989 struct e100_serial *info;
1990 unsigned long ireg;
1991 int i;
1992 int handled = 0;
1993
1994#ifdef CONFIG_SVINTO_SIM
1995 /* No receive in the simulator. Will probably be when the rest of
1996 * the serial interface works, and this piece will just be removed.
1997 */
1998 {
1999 const char *s = "What? tr_interrupt in simulator??\n";
2000 SIMCOUT(s,strlen(s));
2001 }
2002 return IRQ_HANDLED;
2003#endif
2004
2005 /* find out the line that caused this irq and get it from rs_table */
2006
2007 ireg = *R_IRQ_MASK2_RD; /* get the active irq bits for the dma channels */
2008
2009 for (i = 0; i < NR_PORTS; i++) {
2010 info = rs_table + i;
2011 if (!info->enabled || !info->uses_dma_out)
2012 continue;
2013 /* check for dma_descr (don't need to check for dma_eop in output dma for serial */
2014 if (ireg & info->irq) {
2015 handled = 1;
2016 /* we can send a new dma bunch. make it so. */
2017 DINTR2(DEBUG_LOG(info->line, "tr_interrupt %i\n", i));
2018 /* Read jiffies_usec first,
2019 * we want this time to be as late as possible
2020 */
2021 PROCSTAT(ser_stat[info->line].tx_dma_ints++);
2022 info->last_tx_active_usec = GET_JIFFIES_USEC();
2023 info->last_tx_active = jiffies;
2024 transmit_chars_dma(info);
2025 }
2026
2027 /* FIXME: here we should really check for a change in the
2028 status lines and if so call status_handle(info) */
2029 }
2030 return IRQ_RETVAL(handled);
2031} /* tr_interrupt */
2032
2033/* dma input channel interrupt handler */
2034
2035static irqreturn_t
2036rec_interrupt(int irq, void *dev_id)
2037{
2038 struct e100_serial *info;
2039 unsigned long ireg;
2040 int i;
2041 int handled = 0;
2042
2043#ifdef CONFIG_SVINTO_SIM
2044 /* No receive in the simulator. Will probably be when the rest of
2045 * the serial interface works, and this piece will just be removed.
2046 */
2047 {
2048 const char *s = "What? rec_interrupt in simulator??\n";
2049 SIMCOUT(s,strlen(s));
2050 }
2051 return IRQ_HANDLED;
2052#endif
2053
2054 /* find out the line that caused this irq and get it from rs_table */
2055
2056 ireg = *R_IRQ_MASK2_RD; /* get the active irq bits for the dma channels */
2057
2058 for (i = 0; i < NR_PORTS; i++) {
2059 info = rs_table + i;
2060 if (!info->enabled || !info->uses_dma_in)
2061 continue;
2062 /* check for both dma_eop and dma_descr for the input dma channel */
2063 if (ireg & ((info->irq << 2) | (info->irq << 3))) {
2064 handled = 1;
2065 /* we have received something */
2066 receive_chars_dma(info);
2067 }
2068
2069 /* FIXME: here we should really check for a change in the
2070 status lines and if so call status_handle(info) */
2071 }
2072 return IRQ_RETVAL(handled);
2073} /* rec_interrupt */
2074
2075static int force_eop_if_needed(struct e100_serial *info)
2076{
2077 /* We check data_avail bit to determine if data has
2078 * arrived since last time
2079 */
2080 unsigned char rstat = info->ioport[REG_STATUS];
2081
2082 /* error or datavail? */
2083 if (rstat & SER_ERROR_MASK) {
2084 /* Some error has occurred. If there has been valid data, an
2085 * EOP interrupt will be made automatically. If no data, the
2086 * normal ser_interrupt should be enabled and handle it.
2087 * So do nothing!
2088 */
2089 DEBUG_LOG(info->line, "timeout err: rstat 0x%03X\n",
2090 rstat | (info->line << 8));
2091 return 0;
2092 }
2093
2094 if (rstat & SER_DATA_AVAIL_MASK) {
2095 /* Ok data, no error, count it */
2096 TIMERD(DEBUG_LOG(info->line, "timeout: rstat 0x%03X\n",
2097 rstat | (info->line << 8)));
2098 /* Read data to clear status flags */
2099 (void)info->ioport[REG_DATA];
2100
2101 info->forced_eop = 0;
2102 START_FLUSH_FAST_TIMER(info, "magic");
2103 return 0;
2104 }
2105
2106 /* hit the timeout, force an EOP for the input
2107 * dma channel if we haven't already
2108 */
2109 if (!info->forced_eop) {
2110 info->forced_eop = 1;
2111 PROCSTAT(ser_stat[info->line].timeout_flush_cnt++);
2112 TIMERD(DEBUG_LOG(info->line, "timeout EOP %i\n", info->line));
2113 FORCE_EOP(info);
2114 }
2115
2116 return 1;
2117}
2118
2119static void flush_to_flip_buffer(struct e100_serial *info)
2120{
2121 struct tty_struct *tty;
2122 struct etrax_recv_buffer *buffer;
2123 unsigned long flags;
2124
2125 local_irq_save(flags);
2126 tty = info->port.tty;
2127
2128 if (!tty) {
2129 local_irq_restore(flags);
2130 return;
2131 }
2132
2133 while ((buffer = info->first_recv_buffer) != NULL) {
2134 unsigned int count = buffer->length;
2135
2136 tty_insert_flip_string(tty, buffer->buffer, count);
2137 info->recv_cnt -= count;
2138
2139 if (count == buffer->length) {
2140 info->first_recv_buffer = buffer->next;
2141 kfree(buffer);
2142 } else {
2143 buffer->length -= count;
2144 memmove(buffer->buffer, buffer->buffer + count, buffer->length);
2145 buffer->error = TTY_NORMAL;
2146 }
2147 }
2148
2149 if (!info->first_recv_buffer)
2150 info->last_recv_buffer = NULL;
2151
2152 local_irq_restore(flags);
2153
2154 /* This includes a check for low-latency */
2155 tty_flip_buffer_push(tty);
2156}
2157
2158static void check_flush_timeout(struct e100_serial *info)
2159{
2160 /* Flip what we've got (if we can) */
2161 flush_to_flip_buffer(info);
2162
2163 /* We might need to flip later, but not to fast
2164 * since the system is busy processing input... */
2165 if (info->first_recv_buffer)
2166 START_FLUSH_FAST_TIMER_TIME(info, "flip", 2000);
2167
2168 /* Force eop last, since data might have come while we're processing
2169 * and if we started the slow timer above, we won't start a fast
2170 * below.
2171 */
2172 force_eop_if_needed(info);
2173}
2174
2175#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
2176static void flush_timeout_function(unsigned long data)
2177{
2178 struct e100_serial *info = (struct e100_serial *)data;
2179
2180 fast_timers[info->line].function = NULL;
2181 serial_fast_timer_expired++;
2182 TIMERD(DEBUG_LOG(info->line, "flush_timout %i ", info->line));
2183 TIMERD(DEBUG_LOG(info->line, "num expired: %i\n", serial_fast_timer_expired));
2184 check_flush_timeout(info);
2185}
2186
2187#else
2188
2189/* dma fifo/buffer timeout handler
2190 forces an end-of-packet for the dma input channel if no chars
2191 have been received for CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS/100 s.
2192*/
2193
2194static struct timer_list flush_timer;
2195
2196static void
2197timed_flush_handler(unsigned long ptr)
2198{
2199 struct e100_serial *info;
2200 int i;
2201
2202#ifdef CONFIG_SVINTO_SIM
2203 return;
2204#endif
2205
2206 for (i = 0; i < NR_PORTS; i++) {
2207 info = rs_table + i;
2208 if (info->uses_dma_in)
2209 check_flush_timeout(info);
2210 }
2211
2212 /* restart flush timer */
2213 mod_timer(&flush_timer, jiffies + CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS);
2214}
2215#endif
2216
2217#ifdef SERIAL_HANDLE_EARLY_ERRORS
2218
2219/* If there is an error (ie break) when the DMA is running and
2220 * there are no bytes in the fifo the DMA is stopped and we get no
2221 * eop interrupt. Thus we have to monitor the first bytes on a DMA
2222 * transfer, and if it is without error we can turn the serial
2223 * interrupts off.
2224 */
2225
2226/*
2227BREAK handling on ETRAX 100:
2228ETRAX will generate interrupt although there is no stop bit between the
2229characters.
2230
2231Depending on how long the break sequence is, the end of the breaksequence
2232will look differently:
2233| indicates start/end of a character.
2234
2235B= Break character (0x00) with framing error.
2236E= Error byte with parity error received after B characters.
2237F= "Faked" valid byte received immediately after B characters.
2238V= Valid byte
2239
22401.
2241 B BL ___________________________ V
2242.._|__________|__________| |valid data |
2243
2244Multiple frame errors with data == 0x00 (B),
2245the timing matches up "perfectly" so no extra ending char is detected.
2246The RXD pin is 1 in the last interrupt, in that case
2247we set info->errorcode = ERRCODE_INSERT_BREAK, but we can't really
2248know if another byte will come and this really is case 2. below
2249(e.g F=0xFF or 0xFE)
2250If RXD pin is 0 we can expect another character (see 2. below).
2251
2252
22532.
2254
2255 B B E or F__________________..__ V
2256.._|__________|__________|______ | |valid data
2257 "valid" or
2258 parity error
2259
2260Multiple frame errors with data == 0x00 (B),
2261but the part of the break trigs is interpreted as a start bit (and possibly
2262some 0 bits followed by a number of 1 bits and a stop bit).
2263Depending on parity settings etc. this last character can be either
2264a fake "valid" char (F) or have a parity error (E).
2265
2266If the character is valid it will be put in the buffer,
2267we set info->errorcode = ERRCODE_SET_BREAK so the receive interrupt
2268will set the flags so the tty will handle it,
2269if it's an error byte it will not be put in the buffer
2270and we set info->errorcode = ERRCODE_INSERT_BREAK.
2271
2272To distinguish a V byte in 1. from an F byte in 2. we keep a timestamp
2273of the last faulty char (B) and compares it with the current time:
2274If the time elapsed time is less then 2*char_time_usec we will assume
2275it's a faked F char and not a Valid char and set
2276info->errorcode = ERRCODE_SET_BREAK.
2277
2278Flaws in the above solution:
2279~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2280We use the timer to distinguish a F character from a V character,
2281if a V character is to close after the break we might make the wrong decision.
2282
2283TODO: The break will be delayed until an F or V character is received.
2284
2285*/
2286
2287static
2288struct e100_serial * handle_ser_rx_interrupt_no_dma(struct e100_serial *info)
2289{
2290 unsigned long data_read;
2291 struct tty_struct *tty = info->port.tty;
2292
2293 if (!tty) {
2294 printk("!NO TTY!\n");
2295 return info;
2296 }
2297
2298 /* Read data and status at the same time */
2299 data_read = *((unsigned long *)&info->ioport[REG_DATA_STATUS32]);
2300more_data:
2301 if (data_read & IO_MASK(R_SERIAL0_READ, xoff_detect) ) {
2302 DFLOW(DEBUG_LOG(info->line, "XOFF detect\n", 0));
2303 }
2304 DINTR2(DEBUG_LOG(info->line, "ser_rx %c\n", IO_EXTRACT(R_SERIAL0_READ, data_in, data_read)));
2305
2306 if (data_read & ( IO_MASK(R_SERIAL0_READ, framing_err) |
2307 IO_MASK(R_SERIAL0_READ, par_err) |
2308 IO_MASK(R_SERIAL0_READ, overrun) )) {
2309 /* An error */
2310 info->last_rx_active_usec = GET_JIFFIES_USEC();
2311 info->last_rx_active = jiffies;
2312 DINTR1(DEBUG_LOG(info->line, "ser_rx err stat_data %04X\n", data_read));
2313 DLOG_INT_TRIG(
2314 if (!log_int_trig1_pos) {
2315 log_int_trig1_pos = log_int_pos;
2316 log_int(rdpc(), 0, 0);
2317 }
2318 );
2319
2320
2321 if ( ((data_read & IO_MASK(R_SERIAL0_READ, data_in)) == 0) &&
2322 (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) ) {
2323 /* Most likely a break, but we get interrupts over and
2324 * over again.
2325 */
2326
2327 if (!info->break_detected_cnt) {
2328 DEBUG_LOG(info->line, "#BRK start\n", 0);
2329 }
2330 if (data_read & IO_MASK(R_SERIAL0_READ, rxd)) {
2331 /* The RX pin is high now, so the break
2332 * must be over, but....
2333 * we can't really know if we will get another
2334 * last byte ending the break or not.
2335 * And we don't know if the byte (if any) will
2336 * have an error or look valid.
2337 */
2338 DEBUG_LOG(info->line, "# BL BRK\n", 0);
2339 info->errorcode = ERRCODE_INSERT_BREAK;
2340 }
2341 info->break_detected_cnt++;
2342 } else {
2343 /* The error does not look like a break, but could be
2344 * the end of one
2345 */
2346 if (info->break_detected_cnt) {
2347 DEBUG_LOG(info->line, "EBRK %i\n", info->break_detected_cnt);
2348 info->errorcode = ERRCODE_INSERT_BREAK;
2349 } else {
2350 unsigned char data = IO_EXTRACT(R_SERIAL0_READ,
2351 data_in, data_read);
2352 char flag = TTY_NORMAL;
2353 if (info->errorcode == ERRCODE_INSERT_BREAK) {
2354 struct tty_struct *tty = info->port.tty;
2355 tty_insert_flip_char(tty, 0, flag);
2356 info->icount.rx++;
2357 }
2358
2359 if (data_read & IO_MASK(R_SERIAL0_READ, par_err)) {
2360 info->icount.parity++;
2361 flag = TTY_PARITY;
2362 } else if (data_read & IO_MASK(R_SERIAL0_READ, overrun)) {
2363 info->icount.overrun++;
2364 flag = TTY_OVERRUN;
2365 } else if (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) {
2366 info->icount.frame++;
2367 flag = TTY_FRAME;
2368 }
2369 tty_insert_flip_char(tty, data, flag);
2370 info->errorcode = 0;
2371 }
2372 info->break_detected_cnt = 0;
2373 }
2374 } else if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {
2375 /* No error */
2376 DLOG_INT_TRIG(
2377 if (!log_int_trig1_pos) {
2378 if (log_int_pos >= log_int_size) {
2379 log_int_pos = 0;
2380 }
2381 log_int_trig0_pos = log_int_pos;
2382 log_int(rdpc(), 0, 0);
2383 }
2384 );
2385 tty_insert_flip_char(tty,
2386 IO_EXTRACT(R_SERIAL0_READ, data_in, data_read),
2387 TTY_NORMAL);
2388 } else {
2389 DEBUG_LOG(info->line, "ser_rx int but no data_avail %08lX\n", data_read);
2390 }
2391
2392
2393 info->icount.rx++;
2394 data_read = *((unsigned long *)&info->ioport[REG_DATA_STATUS32]);
2395 if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {
2396 DEBUG_LOG(info->line, "ser_rx %c in loop\n", IO_EXTRACT(R_SERIAL0_READ, data_in, data_read));
2397 goto more_data;
2398 }
2399
2400 tty_flip_buffer_push(info->port.tty);
2401 return info;
2402}
2403
2404static struct e100_serial* handle_ser_rx_interrupt(struct e100_serial *info)
2405{
2406 unsigned char rstat;
2407
2408#ifdef SERIAL_DEBUG_INTR
2409 printk("Interrupt from serport %d\n", i);
2410#endif
2411/* DEBUG_LOG(info->line, "ser_interrupt stat %03X\n", rstat | (i << 8)); */
2412 if (!info->uses_dma_in) {
2413 return handle_ser_rx_interrupt_no_dma(info);
2414 }
2415 /* DMA is used */
2416 rstat = info->ioport[REG_STATUS];
2417 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {
2418 DFLOW(DEBUG_LOG(info->line, "XOFF detect\n", 0));
2419 }
2420
2421 if (rstat & SER_ERROR_MASK) {
2422 unsigned char data;
2423
2424 info->last_rx_active_usec = GET_JIFFIES_USEC();
2425 info->last_rx_active = jiffies;
2426 /* If we got an error, we must reset it by reading the
2427 * data_in field
2428 */
2429 data = info->ioport[REG_DATA];
2430 DINTR1(DEBUG_LOG(info->line, "ser_rx! %c\n", data));
2431 DINTR1(DEBUG_LOG(info->line, "ser_rx err stat %02X\n", rstat));
2432 if (!data && (rstat & SER_FRAMING_ERR_MASK)) {
2433 /* Most likely a break, but we get interrupts over and
2434 * over again.
2435 */
2436
2437 if (!info->break_detected_cnt) {
2438 DEBUG_LOG(info->line, "#BRK start\n", 0);
2439 }
2440 if (rstat & SER_RXD_MASK) {
2441 /* The RX pin is high now, so the break
2442 * must be over, but....
2443 * we can't really know if we will get another
2444 * last byte ending the break or not.
2445 * And we don't know if the byte (if any) will
2446 * have an error or look valid.
2447 */
2448 DEBUG_LOG(info->line, "# BL BRK\n", 0);
2449 info->errorcode = ERRCODE_INSERT_BREAK;
2450 }
2451 info->break_detected_cnt++;
2452 } else {
2453 /* The error does not look like a break, but could be
2454 * the end of one
2455 */
2456 if (info->break_detected_cnt) {
2457 DEBUG_LOG(info->line, "EBRK %i\n", info->break_detected_cnt);
2458 info->errorcode = ERRCODE_INSERT_BREAK;
2459 } else {
2460 if (info->errorcode == ERRCODE_INSERT_BREAK) {
2461 info->icount.brk++;
2462 add_char_and_flag(info, '\0', TTY_BREAK);
2463 }
2464
2465 if (rstat & SER_PAR_ERR_MASK) {
2466 info->icount.parity++;
2467 add_char_and_flag(info, data, TTY_PARITY);
2468 } else if (rstat & SER_OVERRUN_MASK) {
2469 info->icount.overrun++;
2470 add_char_and_flag(info, data, TTY_OVERRUN);
2471 } else if (rstat & SER_FRAMING_ERR_MASK) {
2472 info->icount.frame++;
2473 add_char_and_flag(info, data, TTY_FRAME);
2474 }
2475
2476 info->errorcode = 0;
2477 }
2478 info->break_detected_cnt = 0;
2479 DEBUG_LOG(info->line, "#iERR s d %04X\n",
2480 ((rstat & SER_ERROR_MASK) << 8) | data);
2481 }
2482 PROCSTAT(ser_stat[info->line].early_errors_cnt++);
2483 } else { /* It was a valid byte, now let the DMA do the rest */
2484 unsigned long curr_time_u = GET_JIFFIES_USEC();
2485 unsigned long curr_time = jiffies;
2486
2487 if (info->break_detected_cnt) {
2488 /* Detect if this character is a new valid char or the
2489 * last char in a break sequence: If LSBits are 0 and
2490 * MSBits are high AND the time is close to the
2491 * previous interrupt we should discard it.
2492 */
2493 long elapsed_usec =
2494 (curr_time - info->last_rx_active) * (1000000/HZ) +
2495 curr_time_u - info->last_rx_active_usec;
2496 if (elapsed_usec < 2*info->char_time_usec) {
2497 DEBUG_LOG(info->line, "FBRK %i\n", info->line);
2498 /* Report as BREAK (error) and let
2499 * receive_chars_dma() handle it
2500 */
2501 info->errorcode = ERRCODE_SET_BREAK;
2502 } else {
2503 DEBUG_LOG(info->line, "Not end of BRK (V)%i\n", info->line);
2504 }
2505 DEBUG_LOG(info->line, "num brk %i\n", info->break_detected_cnt);
2506 }
2507
2508#ifdef SERIAL_DEBUG_INTR
2509 printk("** OK, disabling ser_interrupts\n");
2510#endif
2511 e100_disable_serial_data_irq(info);
2512 DINTR2(DEBUG_LOG(info->line, "ser_rx OK %d\n", info->line));
2513 info->break_detected_cnt = 0;
2514
2515 PROCSTAT(ser_stat[info->line].ser_ints_ok_cnt++);
2516 }
2517 /* Restarting the DMA never hurts */
2518 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart);
2519 START_FLUSH_FAST_TIMER(info, "ser_int");
2520 return info;
2521} /* handle_ser_rx_interrupt */
2522
2523static void handle_ser_tx_interrupt(struct e100_serial *info)
2524{
2525 unsigned long flags;
2526
2527 if (info->x_char) {
2528 unsigned char rstat;
2529 DFLOW(DEBUG_LOG(info->line, "tx_int: xchar 0x%02X\n", info->x_char));
2530 local_irq_save(flags);
2531 rstat = info->ioport[REG_STATUS];
2532 DFLOW(DEBUG_LOG(info->line, "stat %x\n", rstat));
2533
2534 info->ioport[REG_TR_DATA] = info->x_char;
2535 info->icount.tx++;
2536 info->x_char = 0;
2537 /* We must enable since it is disabled in ser_interrupt */
2538 e100_enable_serial_tx_ready_irq(info);
2539 local_irq_restore(flags);
2540 return;
2541 }
2542 if (info->uses_dma_out) {
2543 unsigned char rstat;
2544 int i;
2545 /* We only use normal tx interrupt when sending x_char */
2546 DFLOW(DEBUG_LOG(info->line, "tx_int: xchar sent\n", 0));
2547 local_irq_save(flags);
2548 rstat = info->ioport[REG_STATUS];
2549 DFLOW(DEBUG_LOG(info->line, "stat %x\n", rstat));
2550 e100_disable_serial_tx_ready_irq(info);
2551 if (info->port.tty->stopped)
2552 rs_stop(info->port.tty);
2553 /* Enable the DMA channel and tell it to continue */
2554 e100_enable_txdma_channel(info);
2555 /* Wait 12 cycles before doing the DMA command */
2556 for(i = 6; i > 0; i--)
2557 nop();
2558
2559 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, continue);
2560 local_irq_restore(flags);
2561 return;
2562 }
2563 /* Normal char-by-char interrupt */
2564 if (info->xmit.head == info->xmit.tail
2565 || info->port.tty->stopped
2566 || info->port.tty->hw_stopped) {
2567 DFLOW(DEBUG_LOG(info->line, "tx_int: stopped %i\n",
2568 info->port.tty->stopped));
2569 e100_disable_serial_tx_ready_irq(info);
2570 info->tr_running = 0;
2571 return;
2572 }
2573 DINTR2(DEBUG_LOG(info->line, "tx_int %c\n", info->xmit.buf[info->xmit.tail]));
2574 /* Send a byte, rs485 timing is critical so turn of ints */
2575 local_irq_save(flags);
2576 info->ioport[REG_TR_DATA] = info->xmit.buf[info->xmit.tail];
2577 info->xmit.tail = (info->xmit.tail + 1) & (SERIAL_XMIT_SIZE-1);
2578 info->icount.tx++;
2579 if (info->xmit.head == info->xmit.tail) {
2580#if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER)
2581 if (info->rs485.flags & SER_RS485_ENABLED) {
2582 /* Set a short timer to toggle RTS */
2583 start_one_shot_timer(&fast_timers_rs485[info->line],
2584 rs485_toggle_rts_timer_function,
2585 (unsigned long)info,
2586 info->char_time_usec*2,
2587 "RS-485");
2588 }
2589#endif /* RS485 */
2590 info->last_tx_active_usec = GET_JIFFIES_USEC();
2591 info->last_tx_active = jiffies;
2592 e100_disable_serial_tx_ready_irq(info);
2593 info->tr_running = 0;
2594 DFLOW(DEBUG_LOG(info->line, "tx_int: stop2\n", 0));
2595 } else {
2596 /* We must enable since it is disabled in ser_interrupt */
2597 e100_enable_serial_tx_ready_irq(info);
2598 }
2599 local_irq_restore(flags);
2600
2601 if (CIRC_CNT(info->xmit.head,
2602 info->xmit.tail,
2603 SERIAL_XMIT_SIZE) < WAKEUP_CHARS)
2604 rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
2605
2606} /* handle_ser_tx_interrupt */
2607
2608/* result of time measurements:
2609 * RX duration 54-60 us when doing something, otherwise 6-9 us
2610 * ser_int duration: just sending: 8-15 us normally, up to 73 us
2611 */
2612static irqreturn_t
2613ser_interrupt(int irq, void *dev_id)
2614{
2615 static volatile int tx_started = 0;
2616 struct e100_serial *info;
2617 int i;
2618 unsigned long flags;
2619 unsigned long irq_mask1_rd;
2620 unsigned long data_mask = (1 << (8+2*0)); /* ser0 data_avail */
2621 int handled = 0;
2622 static volatile unsigned long reentered_ready_mask = 0;
2623
2624 local_irq_save(flags);
2625 irq_mask1_rd = *R_IRQ_MASK1_RD;
2626 /* First handle all rx interrupts with ints disabled */
2627 info = rs_table;
2628 irq_mask1_rd &= e100_ser_int_mask;
2629 for (i = 0; i < NR_PORTS; i++) {
2630 /* Which line caused the data irq? */
2631 if (irq_mask1_rd & data_mask) {
2632 handled = 1;
2633 handle_ser_rx_interrupt(info);
2634 }
2635 info += 1;
2636 data_mask <<= 2;
2637 }
2638 /* Handle tx interrupts with interrupts enabled so we
2639 * can take care of new data interrupts while transmitting
2640 * We protect the tx part with the tx_started flag.
2641 * We disable the tr_ready interrupts we are about to handle and
2642 * unblock the serial interrupt so new serial interrupts may come.
2643 *
2644 * If we get a new interrupt:
2645 * - it migth be due to synchronous serial ports.
2646 * - serial irq will be blocked by general irq handler.
2647 * - async data will be handled above (sync will be ignored).
2648 * - tx_started flag will prevent us from trying to send again and
2649 * we will exit fast - no need to unblock serial irq.
2650 * - Next (sync) serial interrupt handler will be runned with
2651 * disabled interrupt due to restore_flags() at end of function,
2652 * so sync handler will not be preempted or reentered.
2653 */
2654 if (!tx_started) {
2655 unsigned long ready_mask;
2656 unsigned long
2657 tx_started = 1;
2658 /* Only the tr_ready interrupts left */
2659 irq_mask1_rd &= (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |
2660 IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |
2661 IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |
2662 IO_MASK(R_IRQ_MASK1_RD, ser3_ready));
2663 while (irq_mask1_rd) {
2664 /* Disable those we are about to handle */
2665 *R_IRQ_MASK1_CLR = irq_mask1_rd;
2666 /* Unblock the serial interrupt */
2667 *R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, serial, set);
2668
2669 local_irq_enable();
2670 ready_mask = (1 << (8+1+2*0)); /* ser0 tr_ready */
2671 info = rs_table;
2672 for (i = 0; i < NR_PORTS; i++) {
2673 /* Which line caused the ready irq? */
2674 if (irq_mask1_rd & ready_mask) {
2675 handled = 1;
2676 handle_ser_tx_interrupt(info);
2677 }
2678 info += 1;
2679 ready_mask <<= 2;
2680 }
2681 /* handle_ser_tx_interrupt enables tr_ready interrupts */
2682 local_irq_disable();
2683 /* Handle reentered TX interrupt */
2684 irq_mask1_rd = reentered_ready_mask;
2685 }
2686 local_irq_disable();
2687 tx_started = 0;
2688 } else {
2689 unsigned long ready_mask;
2690 ready_mask = irq_mask1_rd & (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |
2691 IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |
2692 IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |
2693 IO_MASK(R_IRQ_MASK1_RD, ser3_ready));
2694 if (ready_mask) {
2695 reentered_ready_mask |= ready_mask;
2696 /* Disable those we are about to handle */
2697 *R_IRQ_MASK1_CLR = ready_mask;
2698 DFLOW(DEBUG_LOG(SERIAL_DEBUG_LINE, "ser_int reentered with TX %X\n", ready_mask));
2699 }
2700 }
2701
2702 local_irq_restore(flags);
2703 return IRQ_RETVAL(handled);
2704} /* ser_interrupt */
2705#endif
2706
2707/*
2708 * -------------------------------------------------------------------
2709 * Here ends the serial interrupt routines.
2710 * -------------------------------------------------------------------
2711 */
2712
2713/*
2714 * This routine is used to handle the "bottom half" processing for the
2715 * serial driver, known also the "software interrupt" processing.
2716 * This processing is done at the kernel interrupt level, after the
2717 * rs_interrupt() has returned, BUT WITH INTERRUPTS TURNED ON. This
2718 * is where time-consuming activities which can not be done in the
2719 * interrupt driver proper are done; the interrupt driver schedules
2720 * them using rs_sched_event(), and they get done here.
2721 */
2722static void
2723do_softint(struct work_struct *work)
2724{
2725 struct e100_serial *info;
2726 struct tty_struct *tty;
2727
2728 info = container_of(work, struct e100_serial, work);
2729
2730 tty = info->port.tty;
2731 if (!tty)
2732 return;
2733
2734 if (test_and_clear_bit(RS_EVENT_WRITE_WAKEUP, &info->event))
2735 tty_wakeup(tty);
2736}
2737
2738static int
2739startup(struct e100_serial * info)
2740{
2741 unsigned long flags;
2742 unsigned long xmit_page;
2743 int i;
2744
2745 xmit_page = get_zeroed_page(GFP_KERNEL);
2746 if (!xmit_page)
2747 return -ENOMEM;
2748
2749 local_irq_save(flags);
2750
2751 /* if it was already initialized, skip this */
2752
2753 if (info->flags & ASYNC_INITIALIZED) {
2754 local_irq_restore(flags);
2755 free_page(xmit_page);
2756 return 0;
2757 }
2758
2759 if (info->xmit.buf)
2760 free_page(xmit_page);
2761 else
2762 info->xmit.buf = (unsigned char *) xmit_page;
2763
2764#ifdef SERIAL_DEBUG_OPEN
2765 printk("starting up ttyS%d (xmit_buf 0x%p)...\n", info->line, info->xmit.buf);
2766#endif
2767
2768#ifdef CONFIG_SVINTO_SIM
2769 /* Bits and pieces collected from below. Better to have them
2770 in one ifdef:ed clause than to mix in a lot of ifdefs,
2771 right? */
2772 if (info->port.tty)
2773 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2774
2775 info->xmit.head = info->xmit.tail = 0;
2776 info->first_recv_buffer = info->last_recv_buffer = NULL;
2777 info->recv_cnt = info->max_recv_cnt = 0;
2778
2779 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2780 info->rec_descr[i].buf = NULL;
2781
2782 /* No real action in the simulator, but may set info important
2783 to ioctl. */
2784 change_speed(info);
2785#else
2786
2787 /*
2788 * Clear the FIFO buffers and disable them
2789 * (they will be reenabled in change_speed())
2790 */
2791
2792 /*
2793 * Reset the DMA channels and make sure their interrupts are cleared
2794 */
2795
2796 if (info->dma_in_enabled) {
2797 info->uses_dma_in = 1;
2798 e100_enable_rxdma_channel(info);
2799
2800 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2801
2802 /* Wait until reset cycle is complete */
2803 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->icmdadr) ==
2804 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
2805
2806 /* Make sure the irqs are cleared */
2807 *info->iclrintradr =
2808 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
2809 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
2810 } else {
2811 e100_disable_rxdma_channel(info);
2812 }
2813
2814 if (info->dma_out_enabled) {
2815 info->uses_dma_out = 1;
2816 e100_enable_txdma_channel(info);
2817 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2818
2819 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->ocmdadr) ==
2820 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
2821
2822 /* Make sure the irqs are cleared */
2823 *info->oclrintradr =
2824 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
2825 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
2826 } else {
2827 e100_disable_txdma_channel(info);
2828 }
2829
2830 if (info->port.tty)
2831 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2832
2833 info->xmit.head = info->xmit.tail = 0;
2834 info->first_recv_buffer = info->last_recv_buffer = NULL;
2835 info->recv_cnt = info->max_recv_cnt = 0;
2836
2837 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2838 info->rec_descr[i].buf = 0;
2839
2840 /*
2841 * and set the speed and other flags of the serial port
2842 * this will start the rx/tx as well
2843 */
2844#ifdef SERIAL_HANDLE_EARLY_ERRORS
2845 e100_enable_serial_data_irq(info);
2846#endif
2847 change_speed(info);
2848
2849 /* dummy read to reset any serial errors */
2850
2851 (void)info->ioport[REG_DATA];
2852
2853 /* enable the interrupts */
2854 if (info->uses_dma_out)
2855 e100_enable_txdma_irq(info);
2856
2857 e100_enable_rx_irq(info);
2858
2859 info->tr_running = 0; /* to be sure we don't lock up the transmitter */
2860
2861 /* setup the dma input descriptor and start dma */
2862
2863 start_receive(info);
2864
2865 /* for safety, make sure the descriptors last result is 0 bytes written */
2866
2867 info->tr_descr.sw_len = 0;
2868 info->tr_descr.hw_len = 0;
2869 info->tr_descr.status = 0;
2870
2871 /* enable RTS/DTR last */
2872
2873 e100_rts(info, 1);
2874 e100_dtr(info, 1);
2875
2876#endif /* CONFIG_SVINTO_SIM */
2877
2878 info->flags |= ASYNC_INITIALIZED;
2879
2880 local_irq_restore(flags);
2881 return 0;
2882}
2883
2884/*
2885 * This routine will shutdown a serial port; interrupts are disabled, and
2886 * DTR is dropped if the hangup on close termio flag is on.
2887 */
2888static void
2889shutdown(struct e100_serial * info)
2890{
2891 unsigned long flags;
2892 struct etrax_dma_descr *descr = info->rec_descr;
2893 struct etrax_recv_buffer *buffer;
2894 int i;
2895
2896#ifndef CONFIG_SVINTO_SIM
2897 /* shut down the transmitter and receiver */
2898 DFLOW(DEBUG_LOG(info->line, "shutdown %i\n", info->line));
2899 e100_disable_rx(info);
2900 info->ioport[REG_TR_CTRL] = (info->tx_ctrl &= ~0x40);
2901
2902 /* disable interrupts, reset dma channels */
2903 if (info->uses_dma_in) {
2904 e100_disable_rxdma_irq(info);
2905 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2906 info->uses_dma_in = 0;
2907 } else {
2908 e100_disable_serial_data_irq(info);
2909 }
2910
2911 if (info->uses_dma_out) {
2912 e100_disable_txdma_irq(info);
2913 info->tr_running = 0;
2914 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2915 info->uses_dma_out = 0;
2916 } else {
2917 e100_disable_serial_tx_ready_irq(info);
2918 info->tr_running = 0;
2919 }
2920
2921#endif /* CONFIG_SVINTO_SIM */
2922
2923 if (!(info->flags & ASYNC_INITIALIZED))
2924 return;
2925
2926#ifdef SERIAL_DEBUG_OPEN
2927 printk("Shutting down serial port %d (irq %d)....\n", info->line,
2928 info->irq);
2929#endif
2930
2931 local_irq_save(flags);
2932
2933 if (info->xmit.buf) {
2934 free_page((unsigned long)info->xmit.buf);
2935 info->xmit.buf = NULL;
2936 }
2937
2938 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2939 if (descr[i].buf) {
2940 buffer = phys_to_virt(descr[i].buf) - sizeof *buffer;
2941 kfree(buffer);
2942 descr[i].buf = 0;
2943 }
2944
2945 if (!info->port.tty || (info->port.tty->termios->c_cflag & HUPCL)) {
2946 /* hang up DTR and RTS if HUPCL is enabled */
2947 e100_dtr(info, 0);
2948 e100_rts(info, 0); /* could check CRTSCTS before doing this */
2949 }
2950
2951 if (info->port.tty)
2952 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2953
2954 info->flags &= ~ASYNC_INITIALIZED;
2955 local_irq_restore(flags);
2956}
2957
2958
2959/* change baud rate and other assorted parameters */
2960
2961static void
2962change_speed(struct e100_serial *info)
2963{
2964 unsigned int cflag;
2965 unsigned long xoff;
2966 unsigned long flags;
2967 /* first some safety checks */
2968
2969 if (!info->port.tty || !info->port.tty->termios)
2970 return;
2971 if (!info->ioport)
2972 return;
2973
2974 cflag = info->port.tty->termios->c_cflag;
2975
2976 /* possibly, the tx/rx should be disabled first to do this safely */
2977
2978 /* change baud-rate and write it to the hardware */
2979 if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST) {
2980 /* Special baudrate */
2981 u32 mask = 0xFF << (info->line*8); /* Each port has 8 bits */
2982 unsigned long alt_source =
2983 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, normal) |
2984 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, normal);
2985 /* R_ALT_SER_BAUDRATE selects the source */
2986 DBAUD(printk("Custom baudrate: baud_base/divisor %lu/%i\n",
2987 (unsigned long)info->baud_base, info->custom_divisor));
2988 if (info->baud_base == SERIAL_PRESCALE_BASE) {
2989 /* 0, 2-65535 (0=65536) */
2990 u16 divisor = info->custom_divisor;
2991 /* R_SERIAL_PRESCALE (upper 16 bits of R_CLOCK_PRESCALE) */
2992 /* baudrate is 3.125MHz/custom_divisor */
2993 alt_source =
2994 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, prescale) |
2995 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, prescale);
2996 alt_source = 0x11;
2997 DBAUD(printk("Writing SERIAL_PRESCALE: divisor %i\n", divisor));
2998 *R_SERIAL_PRESCALE = divisor;
2999 info->baud = SERIAL_PRESCALE_BASE/divisor;
3000 }
3001#ifdef CONFIG_ETRAX_EXTERN_PB6CLK_ENABLED
3002 else if ((info->baud_base==CONFIG_ETRAX_EXTERN_PB6CLK_FREQ/8 &&
3003 info->custom_divisor == 1) ||
3004 (info->baud_base==CONFIG_ETRAX_EXTERN_PB6CLK_FREQ &&
3005 info->custom_divisor == 8)) {
3006 /* ext_clk selected */
3007 alt_source =
3008 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, extern) |
3009 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, extern);
3010 DBAUD(printk("using external baudrate: %lu\n", CONFIG_ETRAX_EXTERN_PB6CLK_FREQ/8));
3011 info->baud = CONFIG_ETRAX_EXTERN_PB6CLK_FREQ/8;
3012 }
3013#endif
3014 else
3015 {
3016 /* Bad baudbase, we don't support using timer0
3017 * for baudrate.
3018 */
3019 printk(KERN_WARNING "Bad baud_base/custom_divisor: %lu/%i\n",
3020 (unsigned long)info->baud_base, info->custom_divisor);
3021 }
3022 r_alt_ser_baudrate_shadow &= ~mask;
3023 r_alt_ser_baudrate_shadow |= (alt_source << (info->line*8));
3024 *R_ALT_SER_BAUDRATE = r_alt_ser_baudrate_shadow;
3025 } else {
3026 /* Normal baudrate */
3027 /* Make sure we use normal baudrate */
3028 u32 mask = 0xFF << (info->line*8); /* Each port has 8 bits */
3029 unsigned long alt_source =
3030 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, normal) |
3031 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, normal);
3032 r_alt_ser_baudrate_shadow &= ~mask;
3033 r_alt_ser_baudrate_shadow |= (alt_source << (info->line*8));
3034#ifndef CONFIG_SVINTO_SIM
3035 *R_ALT_SER_BAUDRATE = r_alt_ser_baudrate_shadow;
3036#endif /* CONFIG_SVINTO_SIM */
3037
3038 info->baud = cflag_to_baud(cflag);
3039#ifndef CONFIG_SVINTO_SIM
3040 info->ioport[REG_BAUD] = cflag_to_etrax_baud(cflag);
3041#endif /* CONFIG_SVINTO_SIM */
3042 }
3043
3044#ifndef CONFIG_SVINTO_SIM
3045 /* start with default settings and then fill in changes */
3046 local_irq_save(flags);
3047 /* 8 bit, no/even parity */
3048 info->rx_ctrl &= ~(IO_MASK(R_SERIAL0_REC_CTRL, rec_bitnr) |
3049 IO_MASK(R_SERIAL0_REC_CTRL, rec_par_en) |
3050 IO_MASK(R_SERIAL0_REC_CTRL, rec_par));
3051
3052 /* 8 bit, no/even parity, 1 stop bit, no cts */
3053 info->tx_ctrl &= ~(IO_MASK(R_SERIAL0_TR_CTRL, tr_bitnr) |
3054 IO_MASK(R_SERIAL0_TR_CTRL, tr_par_en) |
3055 IO_MASK(R_SERIAL0_TR_CTRL, tr_par) |
3056 IO_MASK(R_SERIAL0_TR_CTRL, stop_bits) |
3057 IO_MASK(R_SERIAL0_TR_CTRL, auto_cts));
3058
3059 if ((cflag & CSIZE) == CS7) {
3060 /* set 7 bit mode */
3061 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_bitnr, tr_7bit);
3062 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_bitnr, rec_7bit);
3063 }
3064
3065 if (cflag & CSTOPB) {
3066 /* set 2 stop bit mode */
3067 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, stop_bits, two_bits);
3068 }
3069
3070 if (cflag & PARENB) {
3071 /* enable parity */
3072 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, enable);
3073 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, enable);
3074 }
3075
3076 if (cflag & CMSPAR) {
3077 /* enable stick parity, PARODD mean Mark which matches ETRAX */
3078 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_stick_par, stick);
3079 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_stick_par, stick);
3080 }
3081 if (cflag & PARODD) {
3082 /* set odd parity (or Mark if CMSPAR) */
3083 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par, odd);
3084 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_par, odd);
3085 }
3086
3087 if (cflag & CRTSCTS) {
3088 /* enable automatic CTS handling */
3089 DFLOW(DEBUG_LOG(info->line, "FLOW auto_cts enabled\n", 0));
3090 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, auto_cts, active);
3091 }
3092
3093 /* make sure the tx and rx are enabled */
3094
3095 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_enable, enable);
3096 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_enable, enable);
3097
3098 /* actually write the control regs to the hardware */
3099
3100 info->ioport[REG_TR_CTRL] = info->tx_ctrl;
3101 info->ioport[REG_REC_CTRL] = info->rx_ctrl;
3102 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(info->port.tty));
3103 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable);
3104 if (info->port.tty->termios->c_iflag & IXON ) {
3105 DFLOW(DEBUG_LOG(info->line, "FLOW XOFF enabled 0x%02X\n",
3106 STOP_CHAR(info->port.tty)));
3107 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
3108 }
3109
3110 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
3111 local_irq_restore(flags);
3112#endif /* !CONFIG_SVINTO_SIM */
3113
3114 update_char_time(info);
3115
3116} /* change_speed */
3117
3118/* start transmitting chars NOW */
3119
3120static void
3121rs_flush_chars(struct tty_struct *tty)
3122{
3123 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3124 unsigned long flags;
3125
3126 if (info->tr_running ||
3127 info->xmit.head == info->xmit.tail ||
3128 tty->stopped ||
3129 tty->hw_stopped ||
3130 !info->xmit.buf)
3131 return;
3132
3133#ifdef SERIAL_DEBUG_FLOW
3134 printk("rs_flush_chars\n");
3135#endif
3136
3137 /* this protection might not exactly be necessary here */
3138
3139 local_irq_save(flags);
3140 start_transmit(info);
3141 local_irq_restore(flags);
3142}
3143
3144static int rs_raw_write(struct tty_struct *tty,
3145 const unsigned char *buf, int count)
3146{
3147 int c, ret = 0;
3148 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3149 unsigned long flags;
3150
3151 /* first some sanity checks */
3152
3153 if (!tty || !info->xmit.buf || !tmp_buf)
3154 return 0;
3155
3156#ifdef SERIAL_DEBUG_DATA
3157 if (info->line == SERIAL_DEBUG_LINE)
3158 printk("rs_raw_write (%d), status %d\n",
3159 count, info->ioport[REG_STATUS]);
3160#endif
3161
3162#ifdef CONFIG_SVINTO_SIM
3163 /* Really simple. The output is here and now. */
3164 SIMCOUT(buf, count);
3165 return count;
3166#endif
3167 local_save_flags(flags);
3168 DFLOW(DEBUG_LOG(info->line, "write count %i ", count));
3169 DFLOW(DEBUG_LOG(info->line, "ldisc %i\n", tty->ldisc.chars_in_buffer(tty)));
3170
3171
3172 /* The local_irq_disable/restore_flags pairs below are needed
3173 * because the DMA interrupt handler moves the info->xmit values.
3174 * the memcpy needs to be in the critical region unfortunately,
3175 * because we need to read xmit values, memcpy, write xmit values
3176 * in one atomic operation... this could perhaps be avoided by
3177 * more clever design.
3178 */
3179 local_irq_disable();
3180 while (count) {
3181 c = CIRC_SPACE_TO_END(info->xmit.head,
3182 info->xmit.tail,
3183 SERIAL_XMIT_SIZE);
3184
3185 if (count < c)
3186 c = count;
3187 if (c <= 0)
3188 break;
3189
3190 memcpy(info->xmit.buf + info->xmit.head, buf, c);
3191 info->xmit.head = (info->xmit.head + c) &
3192 (SERIAL_XMIT_SIZE-1);
3193 buf += c;
3194 count -= c;
3195 ret += c;
3196 }
3197 local_irq_restore(flags);
3198
3199 /* enable transmitter if not running, unless the tty is stopped
3200 * this does not need IRQ protection since if tr_running == 0
3201 * the IRQ's are not running anyway for this port.
3202 */
3203 DFLOW(DEBUG_LOG(info->line, "write ret %i\n", ret));
3204
3205 if (info->xmit.head != info->xmit.tail &&
3206 !tty->stopped &&
3207 !tty->hw_stopped &&
3208 !info->tr_running) {
3209 start_transmit(info);
3210 }
3211
3212 return ret;
3213} /* raw_raw_write() */
3214
3215static int
3216rs_write(struct tty_struct *tty,
3217 const unsigned char *buf, int count)
3218{
3219#if defined(CONFIG_ETRAX_RS485)
3220 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3221
3222 if (info->rs485.flags & SER_RS485_ENABLED)
3223 {
3224 /* If we are in RS-485 mode, we need to toggle RTS and disable
3225 * the receiver before initiating a DMA transfer
3226 */
3227#ifdef CONFIG_ETRAX_FAST_TIMER
3228 /* Abort any started timer */
3229 fast_timers_rs485[info->line].function = NULL;
3230 del_fast_timer(&fast_timers_rs485[info->line]);
3231#endif
3232 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_ON_SEND));
3233#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
3234 e100_disable_rx(info);
3235 e100_enable_rx_irq(info);
3236#endif
3237
3238 if (info->rs485.delay_rts_before_send > 0)
3239 msleep(info->rs485.delay_rts_before_send);
3240 }
3241#endif /* CONFIG_ETRAX_RS485 */
3242
3243 count = rs_raw_write(tty, buf, count);
3244
3245#if defined(CONFIG_ETRAX_RS485)
3246 if (info->rs485.flags & SER_RS485_ENABLED)
3247 {
3248 unsigned int val;
3249 /* If we are in RS-485 mode the following has to be done:
3250 * wait until DMA is ready
3251 * wait on transmit shift register
3252 * toggle RTS
3253 * enable the receiver
3254 */
3255
3256 /* Sleep until all sent */
3257 tty_wait_until_sent(tty, 0);
3258#ifdef CONFIG_ETRAX_FAST_TIMER
3259 /* Now sleep a little more so that shift register is empty */
3260 schedule_usleep(info->char_time_usec * 2);
3261#endif
3262 /* wait on transmit shift register */
3263 do{
3264 get_lsr_info(info, &val);
3265 }while (!(val & TIOCSER_TEMT));
3266
3267 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_AFTER_SEND));
3268
3269#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
3270 e100_enable_rx(info);
3271 e100_enable_rxdma_irq(info);
3272#endif
3273 }
3274#endif /* CONFIG_ETRAX_RS485 */
3275
3276 return count;
3277} /* rs_write */
3278
3279
3280/* how much space is available in the xmit buffer? */
3281
3282static int
3283rs_write_room(struct tty_struct *tty)
3284{
3285 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3286
3287 return CIRC_SPACE(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
3288}
3289
3290/* How many chars are in the xmit buffer?
3291 * This does not include any chars in the transmitter FIFO.
3292 * Use wait_until_sent for waiting for FIFO drain.
3293 */
3294
3295static int
3296rs_chars_in_buffer(struct tty_struct *tty)
3297{
3298 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3299
3300 return CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
3301}
3302
3303/* discard everything in the xmit buffer */
3304
3305static void
3306rs_flush_buffer(struct tty_struct *tty)
3307{
3308 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3309 unsigned long flags;
3310
3311 local_irq_save(flags);
3312 info->xmit.head = info->xmit.tail = 0;
3313 local_irq_restore(flags);
3314
3315 tty_wakeup(tty);
3316}
3317
3318/*
3319 * This function is used to send a high-priority XON/XOFF character to
3320 * the device
3321 *
3322 * Since we use DMA we don't check for info->x_char in transmit_chars_dma(),
3323 * but we do it in handle_ser_tx_interrupt().
3324 * We disable DMA channel and enable tx ready interrupt and write the
3325 * character when possible.
3326 */
3327static void rs_send_xchar(struct tty_struct *tty, char ch)
3328{
3329 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3330 unsigned long flags;
3331 local_irq_save(flags);
3332 if (info->uses_dma_out) {
3333 /* Put the DMA on hold and disable the channel */
3334 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, hold);
3335 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->ocmdadr) !=
3336 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, hold));
3337 e100_disable_txdma_channel(info);
3338 }
3339
3340 /* Must make sure transmitter is not stopped before we can transmit */
3341 if (tty->stopped)
3342 rs_start(tty);
3343
3344 /* Enable manual transmit interrupt and send from there */
3345 DFLOW(DEBUG_LOG(info->line, "rs_send_xchar 0x%02X\n", ch));
3346 info->x_char = ch;
3347 e100_enable_serial_tx_ready_irq(info);
3348 local_irq_restore(flags);
3349}
3350
3351/*
3352 * ------------------------------------------------------------
3353 * rs_throttle()
3354 *
3355 * This routine is called by the upper-layer tty layer to signal that
3356 * incoming characters should be throttled.
3357 * ------------------------------------------------------------
3358 */
3359static void
3360rs_throttle(struct tty_struct * tty)
3361{
3362 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3363#ifdef SERIAL_DEBUG_THROTTLE
3364 char buf[64];
3365
3366 printk("throttle %s: %lu....\n", tty_name(tty, buf),
3367 (unsigned long)tty->ldisc.chars_in_buffer(tty));
3368#endif
3369 DFLOW(DEBUG_LOG(info->line,"rs_throttle %lu\n", tty->ldisc.chars_in_buffer(tty)));
3370
3371 /* Do RTS before XOFF since XOFF might take some time */
3372 if (tty->termios->c_cflag & CRTSCTS) {
3373 /* Turn off RTS line */
3374 e100_rts(info, 0);
3375 }
3376 if (I_IXOFF(tty))
3377 rs_send_xchar(tty, STOP_CHAR(tty));
3378
3379}
3380
3381static void
3382rs_unthrottle(struct tty_struct * tty)
3383{
3384 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3385#ifdef SERIAL_DEBUG_THROTTLE
3386 char buf[64];
3387
3388 printk("unthrottle %s: %lu....\n", tty_name(tty, buf),
3389 (unsigned long)tty->ldisc.chars_in_buffer(tty));
3390#endif
3391 DFLOW(DEBUG_LOG(info->line,"rs_unthrottle ldisc %d\n", tty->ldisc.chars_in_buffer(tty)));
3392 DFLOW(DEBUG_LOG(info->line,"rs_unthrottle flip.count: %i\n", tty->flip.count));
3393 /* Do RTS before XOFF since XOFF might take some time */
3394 if (tty->termios->c_cflag & CRTSCTS) {
3395 /* Assert RTS line */
3396 e100_rts(info, 1);
3397 }
3398
3399 if (I_IXOFF(tty)) {
3400 if (info->x_char)
3401 info->x_char = 0;
3402 else
3403 rs_send_xchar(tty, START_CHAR(tty));
3404 }
3405
3406}
3407
3408/*
3409 * ------------------------------------------------------------
3410 * rs_ioctl() and friends
3411 * ------------------------------------------------------------
3412 */
3413
3414static int
3415get_serial_info(struct e100_serial * info,
3416 struct serial_struct * retinfo)
3417{
3418 struct serial_struct tmp;
3419
3420 /* this is all probably wrong, there are a lot of fields
3421 * here that we don't have in e100_serial and maybe we
3422 * should set them to something else than 0.
3423 */
3424
3425 if (!retinfo)
3426 return -EFAULT;
3427 memset(&tmp, 0, sizeof(tmp));
3428 tmp.type = info->type;
3429 tmp.line = info->line;
3430 tmp.port = (int)info->ioport;
3431 tmp.irq = info->irq;
3432 tmp.flags = info->flags;
3433 tmp.baud_base = info->baud_base;
3434 tmp.close_delay = info->close_delay;
3435 tmp.closing_wait = info->closing_wait;
3436 tmp.custom_divisor = info->custom_divisor;
3437 if (copy_to_user(retinfo, &tmp, sizeof(*retinfo)))
3438 return -EFAULT;
3439 return 0;
3440}
3441
3442static int
3443set_serial_info(struct e100_serial *info,
3444 struct serial_struct *new_info)
3445{
3446 struct serial_struct new_serial;
3447 struct e100_serial old_info;
3448 int retval = 0;
3449
3450 if (copy_from_user(&new_serial, new_info, sizeof(new_serial)))
3451 return -EFAULT;
3452
3453 old_info = *info;
3454
3455 if (!capable(CAP_SYS_ADMIN)) {
3456 if ((new_serial.type != info->type) ||
3457 (new_serial.close_delay != info->close_delay) ||
3458 ((new_serial.flags & ~ASYNC_USR_MASK) !=
3459 (info->flags & ~ASYNC_USR_MASK)))
3460 return -EPERM;
3461 info->flags = ((info->flags & ~ASYNC_USR_MASK) |
3462 (new_serial.flags & ASYNC_USR_MASK));
3463 goto check_and_exit;
3464 }
3465
3466 if (info->count > 1)
3467 return -EBUSY;
3468
3469 /*
3470 * OK, past this point, all the error checking has been done.
3471 * At this point, we start making changes.....
3472 */
3473
3474 info->baud_base = new_serial.baud_base;
3475 info->flags = ((info->flags & ~ASYNC_FLAGS) |
3476 (new_serial.flags & ASYNC_FLAGS));
3477 info->custom_divisor = new_serial.custom_divisor;
3478 info->type = new_serial.type;
3479 info->close_delay = new_serial.close_delay;
3480 info->closing_wait = new_serial.closing_wait;
3481 info->port.tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
3482
3483 check_and_exit:
3484 if (info->flags & ASYNC_INITIALIZED) {
3485 change_speed(info);
3486 } else
3487 retval = startup(info);
3488 return retval;
3489}
3490
3491/*
3492 * get_lsr_info - get line status register info
3493 *
3494 * Purpose: Let user call ioctl() to get info when the UART physically
3495 * is emptied. On bus types like RS485, the transmitter must
3496 * release the bus after transmitting. This must be done when
3497 * the transmit shift register is empty, not be done when the
3498 * transmit holding register is empty. This functionality
3499 * allows an RS485 driver to be written in user space.
3500 */
3501static int
3502get_lsr_info(struct e100_serial * info, unsigned int *value)
3503{
3504 unsigned int result = TIOCSER_TEMT;
3505#ifndef CONFIG_SVINTO_SIM
3506 unsigned long curr_time = jiffies;
3507 unsigned long curr_time_usec = GET_JIFFIES_USEC();
3508 unsigned long elapsed_usec =
3509 (curr_time - info->last_tx_active) * 1000000/HZ +
3510 curr_time_usec - info->last_tx_active_usec;
3511
3512 if (info->xmit.head != info->xmit.tail ||
3513 elapsed_usec < 2*info->char_time_usec) {
3514 result = 0;
3515 }
3516#endif
3517
3518 if (copy_to_user(value, &result, sizeof(int)))
3519 return -EFAULT;
3520 return 0;
3521}
3522
3523#ifdef SERIAL_DEBUG_IO
3524struct state_str
3525{
3526 int state;
3527 const char *str;
3528};
3529
3530const struct state_str control_state_str[] = {
3531 {TIOCM_DTR, "DTR" },
3532 {TIOCM_RTS, "RTS"},
3533 {TIOCM_ST, "ST?" },
3534 {TIOCM_SR, "SR?" },
3535 {TIOCM_CTS, "CTS" },
3536 {TIOCM_CD, "CD" },
3537 {TIOCM_RI, "RI" },
3538 {TIOCM_DSR, "DSR" },
3539 {0, NULL }
3540};
3541
3542char *get_control_state_str(int MLines, char *s)
3543{
3544 int i = 0;
3545
3546 s[0]='\0';
3547 while (control_state_str[i].str != NULL) {
3548 if (MLines & control_state_str[i].state) {
3549 if (s[0] != '\0') {
3550 strcat(s, ", ");
3551 }
3552 strcat(s, control_state_str[i].str);
3553 }
3554 i++;
3555 }
3556 return s;
3557}
3558#endif
3559
3560static int
3561rs_break(struct tty_struct *tty, int break_state)
3562{
3563 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3564 unsigned long flags;
3565
3566 if (!info->ioport)
3567 return -EIO;
3568
3569 local_irq_save(flags);
3570 if (break_state == -1) {
3571 /* Go to manual mode and set the txd pin to 0 */
3572 /* Clear bit 7 (txd) and 6 (tr_enable) */
3573 info->tx_ctrl &= 0x3F;
3574 } else {
3575 /* Set bit 7 (txd) and 6 (tr_enable) */
3576 info->tx_ctrl |= (0x80 | 0x40);
3577 }
3578 info->ioport[REG_TR_CTRL] = info->tx_ctrl;
3579 local_irq_restore(flags);
3580 return 0;
3581}
3582
3583static int
3584rs_tiocmset(struct tty_struct *tty, struct file *file,
3585 unsigned int set, unsigned int clear)
3586{
3587 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3588 unsigned long flags;
3589
3590 local_irq_save(flags);
3591
3592 if (clear & TIOCM_RTS)
3593 e100_rts(info, 0);
3594 if (clear & TIOCM_DTR)
3595 e100_dtr(info, 0);
3596 /* Handle FEMALE behaviour */
3597 if (clear & TIOCM_RI)
3598 e100_ri_out(info, 0);
3599 if (clear & TIOCM_CD)
3600 e100_cd_out(info, 0);
3601
3602 if (set & TIOCM_RTS)
3603 e100_rts(info, 1);
3604 if (set & TIOCM_DTR)
3605 e100_dtr(info, 1);
3606 /* Handle FEMALE behaviour */
3607 if (set & TIOCM_RI)
3608 e100_ri_out(info, 1);
3609 if (set & TIOCM_CD)
3610 e100_cd_out(info, 1);
3611
3612 local_irq_restore(flags);
3613 return 0;
3614}
3615
3616static int
3617rs_tiocmget(struct tty_struct *tty, struct file *file)
3618{
3619 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3620 unsigned int result;
3621 unsigned long flags;
3622
3623 local_irq_save(flags);
3624
3625 result =
3626 (!E100_RTS_GET(info) ? TIOCM_RTS : 0)
3627 | (!E100_DTR_GET(info) ? TIOCM_DTR : 0)
3628 | (!E100_RI_GET(info) ? TIOCM_RNG : 0)
3629 | (!E100_DSR_GET(info) ? TIOCM_DSR : 0)
3630 | (!E100_CD_GET(info) ? TIOCM_CAR : 0)
3631 | (!E100_CTS_GET(info) ? TIOCM_CTS : 0);
3632
3633 local_irq_restore(flags);
3634
3635#ifdef SERIAL_DEBUG_IO
3636 printk(KERN_DEBUG "ser%i: modem state: %i 0x%08X\n",
3637 info->line, result, result);
3638 {
3639 char s[100];
3640
3641 get_control_state_str(result, s);
3642 printk(KERN_DEBUG "state: %s\n", s);
3643 }
3644#endif
3645 return result;
3646
3647}
3648
3649
3650static int
3651rs_ioctl(struct tty_struct *tty, struct file * file,
3652 unsigned int cmd, unsigned long arg)
3653{
3654 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3655
3656 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
3657 (cmd != TIOCSERCONFIG) && (cmd != TIOCSERGWILD) &&
3658 (cmd != TIOCSERSWILD) && (cmd != TIOCSERGSTRUCT)) {
3659 if (tty->flags & (1 << TTY_IO_ERROR))
3660 return -EIO;
3661 }
3662
3663 switch (cmd) {
3664 case TIOCGSERIAL:
3665 return get_serial_info(info,
3666 (struct serial_struct *) arg);
3667 case TIOCSSERIAL:
3668 return set_serial_info(info,
3669 (struct serial_struct *) arg);
3670 case TIOCSERGETLSR: /* Get line status register */
3671 return get_lsr_info(info, (unsigned int *) arg);
3672
3673 case TIOCSERGSTRUCT:
3674 if (copy_to_user((struct e100_serial *) arg,
3675 info, sizeof(struct e100_serial)))
3676 return -EFAULT;
3677 return 0;
3678
3679#if defined(CONFIG_ETRAX_RS485)
3680 case TIOCSERSETRS485:
3681 {
3682 /* In this ioctl we still use the old structure
3683 * rs485_control for backward compatibility
3684 * (if we use serial_rs485, then old user-level code
3685 * wouldn't work anymore...).
3686 * The use of this ioctl is deprecated: use TIOCSRS485
3687 * instead.*/
3688 struct rs485_control rs485ctrl;
3689 struct serial_rs485 rs485data;
3690 printk(KERN_DEBUG "The use of this ioctl is deprecated. Use TIOCSRS485 instead\n");
3691 if (copy_from_user(&rs485ctrl, (struct rs485_control *)arg,
3692 sizeof(rs485ctrl)))
3693 return -EFAULT;
3694
3695 rs485data.delay_rts_before_send = rs485ctrl.delay_rts_before_send;
3696 rs485data.flags = 0;
3697 if (rs485ctrl.enabled)
3698 rs485data.flags |= SER_RS485_ENABLED;
3699 else
3700 rs485data.flags &= ~(SER_RS485_ENABLED);
3701
3702 if (rs485ctrl.rts_on_send)
3703 rs485data.flags |= SER_RS485_RTS_ON_SEND;
3704 else
3705 rs485data.flags &= ~(SER_RS485_RTS_ON_SEND);
3706
3707 if (rs485ctrl.rts_after_sent)
3708 rs485data.flags |= SER_RS485_RTS_AFTER_SEND;
3709 else
3710 rs485data.flags &= ~(SER_RS485_RTS_AFTER_SEND);
3711
3712 return e100_enable_rs485(tty, &rs485data);
3713 }
3714
3715 case TIOCSRS485:
3716 {
3717 /* This is the new version of TIOCSRS485, with new
3718 * data structure serial_rs485 */
3719 struct serial_rs485 rs485data;
3720 if (copy_from_user(&rs485data, (struct rs485_control *)arg,
3721 sizeof(rs485data)))
3722 return -EFAULT;
3723
3724 return e100_enable_rs485(tty, &rs485data);
3725 }
3726
3727 case TIOCGRS485:
3728 {
3729 struct serial_rs485 *rs485data =
3730 &(((struct e100_serial *)tty->driver_data)->rs485);
3731 /* This is the ioctl to get RS485 data from user-space */
3732 if (copy_to_user((struct serial_rs485 *) arg,
3733 rs485data,
3734 sizeof(serial_rs485)))
3735 return -EFAULT;
3736 break;
3737 }
3738
3739 case TIOCSERWRRS485:
3740 {
3741 struct rs485_write rs485wr;
3742 if (copy_from_user(&rs485wr, (struct rs485_write *)arg,
3743 sizeof(rs485wr)))
3744 return -EFAULT;
3745
3746 return e100_write_rs485(tty, rs485wr.outc, rs485wr.outc_size);
3747 }
3748#endif
3749
3750 default:
3751 return -ENOIOCTLCMD;
3752 }
3753 return 0;
3754}
3755
3756static void
3757rs_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
3758{
3759 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3760
3761 change_speed(info);
3762
3763 /* Handle turning off CRTSCTS */
3764 if ((old_termios->c_cflag & CRTSCTS) &&
3765 !(tty->termios->c_cflag & CRTSCTS)) {
3766 tty->hw_stopped = 0;
3767 rs_start(tty);
3768 }
3769
3770}
3771
3772/*
3773 * ------------------------------------------------------------
3774 * rs_close()
3775 *
3776 * This routine is called when the serial port gets closed. First, we
3777 * wait for the last remaining data to be sent. Then, we unlink its
3778 * S structure from the interrupt chain if necessary, and we free
3779 * that IRQ if nothing is left in the chain.
3780 * ------------------------------------------------------------
3781 */
3782static void
3783rs_close(struct tty_struct *tty, struct file * filp)
3784{
3785 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3786 unsigned long flags;
3787
3788 if (!info)
3789 return;
3790
3791 /* interrupts are disabled for this entire function */
3792
3793 local_irq_save(flags);
3794
3795 if (tty_hung_up_p(filp)) {
3796 local_irq_restore(flags);
3797 return;
3798 }
3799
3800#ifdef SERIAL_DEBUG_OPEN
3801 printk("[%d] rs_close ttyS%d, count = %d\n", current->pid,
3802 info->line, info->count);
3803#endif
3804 if ((tty->count == 1) && (info->count != 1)) {
3805 /*
3806 * Uh, oh. tty->count is 1, which means that the tty
3807 * structure will be freed. Info->count should always
3808 * be one in these conditions. If it's greater than
3809 * one, we've got real problems, since it means the
3810 * serial port won't be shutdown.
3811 */
3812 printk(KERN_CRIT
3813 "rs_close: bad serial port count; tty->count is 1, "
3814 "info->count is %d\n", info->count);
3815 info->count = 1;
3816 }
3817 if (--info->count < 0) {
3818 printk(KERN_CRIT "rs_close: bad serial port count for ttyS%d: %d\n",
3819 info->line, info->count);
3820 info->count = 0;
3821 }
3822 if (info->count) {
3823 local_irq_restore(flags);
3824 return;
3825 }
3826 info->flags |= ASYNC_CLOSING;
3827 /*
3828 * Save the termios structure, since this port may have
3829 * separate termios for callout and dialin.
3830 */
3831 if (info->flags & ASYNC_NORMAL_ACTIVE)
3832 info->normal_termios = *tty->termios;
3833 /*
3834 * Now we wait for the transmit buffer to clear; and we notify
3835 * the line discipline to only process XON/XOFF characters.
3836 */
3837 tty->closing = 1;
3838 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE)
3839 tty_wait_until_sent(tty, info->closing_wait);
3840 /*
3841 * At this point we stop accepting input. To do this, we
3842 * disable the serial receiver and the DMA receive interrupt.
3843 */
3844#ifdef SERIAL_HANDLE_EARLY_ERRORS
3845 e100_disable_serial_data_irq(info);
3846#endif
3847
3848#ifndef CONFIG_SVINTO_SIM
3849 e100_disable_rx(info);
3850 e100_disable_rx_irq(info);
3851
3852 if (info->flags & ASYNC_INITIALIZED) {
3853 /*
3854 * Before we drop DTR, make sure the UART transmitter
3855 * has completely drained; this is especially
3856 * important as we have a transmit FIFO!
3857 */
3858 rs_wait_until_sent(tty, HZ);
3859 }
3860#endif
3861
3862 shutdown(info);
3863 rs_flush_buffer(tty);
3864 tty_ldisc_flush(tty);
3865 tty->closing = 0;
3866 info->event = 0;
3867 info->port.tty = NULL;
3868 if (info->blocked_open) {
3869 if (info->close_delay)
3870 schedule_timeout_interruptible(info->close_delay);
3871 wake_up_interruptible(&info->open_wait);
3872 }
3873 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
3874 wake_up_interruptible(&info->close_wait);
3875 local_irq_restore(flags);
3876
3877 /* port closed */
3878
3879#if defined(CONFIG_ETRAX_RS485)
3880 if (info->rs485.flags & SER_RS485_ENABLED) {
3881 info->rs485.flags &= ~(SER_RS485_ENABLED);
3882#if defined(CONFIG_ETRAX_RS485_ON_PA)
3883 *R_PORT_PA_DATA = port_pa_data_shadow &= ~(1 << rs485_pa_bit);
3884#endif
3885#if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
3886 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
3887 rs485_port_g_bit, 0);
3888#endif
3889#if defined(CONFIG_ETRAX_RS485_LTC1387)
3890 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
3891 CONFIG_ETRAX_RS485_LTC1387_DXEN_PORT_G_BIT, 0);
3892 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
3893 CONFIG_ETRAX_RS485_LTC1387_RXEN_PORT_G_BIT, 0);
3894#endif
3895 }
3896#endif
3897
3898 /*
3899 * Release any allocated DMA irq's.
3900 */
3901 if (info->dma_in_enabled) {
3902 free_irq(info->dma_in_irq_nbr, info);
3903 cris_free_dma(info->dma_in_nbr, info->dma_in_irq_description);
3904 info->uses_dma_in = 0;
3905#ifdef SERIAL_DEBUG_OPEN
3906 printk(KERN_DEBUG "DMA irq '%s' freed\n",
3907 info->dma_in_irq_description);
3908#endif
3909 }
3910 if (info->dma_out_enabled) {
3911 free_irq(info->dma_out_irq_nbr, info);
3912 cris_free_dma(info->dma_out_nbr, info->dma_out_irq_description);
3913 info->uses_dma_out = 0;
3914#ifdef SERIAL_DEBUG_OPEN
3915 printk(KERN_DEBUG "DMA irq '%s' freed\n",
3916 info->dma_out_irq_description);
3917#endif
3918 }
3919}
3920
3921/*
3922 * rs_wait_until_sent() --- wait until the transmitter is empty
3923 */
3924static void rs_wait_until_sent(struct tty_struct *tty, int timeout)
3925{
3926 unsigned long orig_jiffies;
3927 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3928 unsigned long curr_time = jiffies;
3929 unsigned long curr_time_usec = GET_JIFFIES_USEC();
3930 long elapsed_usec =
3931 (curr_time - info->last_tx_active) * (1000000/HZ) +
3932 curr_time_usec - info->last_tx_active_usec;
3933
3934 /*
3935 * Check R_DMA_CHx_STATUS bit 0-6=number of available bytes in FIFO
3936 * R_DMA_CHx_HWSW bit 31-16=nbr of bytes left in DMA buffer (0=64k)
3937 */
3938 orig_jiffies = jiffies;
3939 while (info->xmit.head != info->xmit.tail || /* More in send queue */
3940 (*info->ostatusadr & 0x007f) || /* more in FIFO */
3941 (elapsed_usec < 2*info->char_time_usec)) {
3942 schedule_timeout_interruptible(1);
3943 if (signal_pending(current))
3944 break;
3945 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3946 break;
3947 curr_time = jiffies;
3948 curr_time_usec = GET_JIFFIES_USEC();
3949 elapsed_usec =
3950 (curr_time - info->last_tx_active) * (1000000/HZ) +
3951 curr_time_usec - info->last_tx_active_usec;
3952 }
3953 set_current_state(TASK_RUNNING);
3954}
3955
3956/*
3957 * rs_hangup() --- called by tty_hangup() when a hangup is signaled.
3958 */
3959void
3960rs_hangup(struct tty_struct *tty)
3961{
3962 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3963
3964 rs_flush_buffer(tty);
3965 shutdown(info);
3966 info->event = 0;
3967 info->count = 0;
3968 info->flags &= ~ASYNC_NORMAL_ACTIVE;
3969 info->port.tty = NULL;
3970 wake_up_interruptible(&info->open_wait);
3971}
3972
3973/*
3974 * ------------------------------------------------------------
3975 * rs_open() and friends
3976 * ------------------------------------------------------------
3977 */
3978static int
3979block_til_ready(struct tty_struct *tty, struct file * filp,
3980 struct e100_serial *info)
3981{
3982 DECLARE_WAITQUEUE(wait, current);
3983 unsigned long flags;
3984 int retval;
3985 int do_clocal = 0, extra_count = 0;
3986
3987 /*
3988 * If the device is in the middle of being closed, then block
3989 * until it's done, and then try again.
3990 */
3991 if (tty_hung_up_p(filp) ||
3992 (info->flags & ASYNC_CLOSING)) {
3993 wait_event_interruptible_tty(info->close_wait,
3994 !(info->flags & ASYNC_CLOSING));
3995#ifdef SERIAL_DO_RESTART
3996 if (info->flags & ASYNC_HUP_NOTIFY)
3997 return -EAGAIN;
3998 else
3999 return -ERESTARTSYS;
4000#else
4001 return -EAGAIN;
4002#endif
4003 }
4004
4005 /*
4006 * If non-blocking mode is set, or the port is not enabled,
4007 * then make the check up front and then exit.
4008 */
4009 if ((filp->f_flags & O_NONBLOCK) ||
4010 (tty->flags & (1 << TTY_IO_ERROR))) {
4011 info->flags |= ASYNC_NORMAL_ACTIVE;
4012 return 0;
4013 }
4014
4015 if (tty->termios->c_cflag & CLOCAL) {
4016 do_clocal = 1;
4017 }
4018
4019 /*
4020 * Block waiting for the carrier detect and the line to become
4021 * free (i.e., not in use by the callout). While we are in
4022 * this loop, info->count is dropped by one, so that
4023 * rs_close() knows when to free things. We restore it upon
4024 * exit, either normal or abnormal.
4025 */
4026 retval = 0;
4027 add_wait_queue(&info->open_wait, &wait);
4028#ifdef SERIAL_DEBUG_OPEN
4029 printk("block_til_ready before block: ttyS%d, count = %d\n",
4030 info->line, info->count);
4031#endif
4032 local_irq_save(flags);
4033 if (!tty_hung_up_p(filp)) {
4034 extra_count++;
4035 info->count--;
4036 }
4037 local_irq_restore(flags);
4038 info->blocked_open++;
4039 while (1) {
4040 local_irq_save(flags);
4041 /* assert RTS and DTR */
4042 e100_rts(info, 1);
4043 e100_dtr(info, 1);
4044 local_irq_restore(flags);
4045 set_current_state(TASK_INTERRUPTIBLE);
4046 if (tty_hung_up_p(filp) ||
4047 !(info->flags & ASYNC_INITIALIZED)) {
4048#ifdef SERIAL_DO_RESTART
4049 if (info->flags & ASYNC_HUP_NOTIFY)
4050 retval = -EAGAIN;
4051 else
4052 retval = -ERESTARTSYS;
4053#else
4054 retval = -EAGAIN;
4055#endif
4056 break;
4057 }
4058 if (!(info->flags & ASYNC_CLOSING) && do_clocal)
4059 /* && (do_clocal || DCD_IS_ASSERTED) */
4060 break;
4061 if (signal_pending(current)) {
4062 retval = -ERESTARTSYS;
4063 break;
4064 }
4065#ifdef SERIAL_DEBUG_OPEN
4066 printk("block_til_ready blocking: ttyS%d, count = %d\n",
4067 info->line, info->count);
4068#endif
4069 tty_unlock();
4070 schedule();
4071 tty_lock();
4072 }
4073 set_current_state(TASK_RUNNING);
4074 remove_wait_queue(&info->open_wait, &wait);
4075 if (extra_count)
4076 info->count++;
4077 info->blocked_open--;
4078#ifdef SERIAL_DEBUG_OPEN
4079 printk("block_til_ready after blocking: ttyS%d, count = %d\n",
4080 info->line, info->count);
4081#endif
4082 if (retval)
4083 return retval;
4084 info->flags |= ASYNC_NORMAL_ACTIVE;
4085 return 0;
4086}
4087
4088static void
4089deinit_port(struct e100_serial *info)
4090{
4091 if (info->dma_out_enabled) {
4092 cris_free_dma(info->dma_out_nbr, info->dma_out_irq_description);
4093 free_irq(info->dma_out_irq_nbr, info);
4094 }
4095 if (info->dma_in_enabled) {
4096 cris_free_dma(info->dma_in_nbr, info->dma_in_irq_description);
4097 free_irq(info->dma_in_irq_nbr, info);
4098 }
4099}
4100
4101/*
4102 * This routine is called whenever a serial port is opened.
4103 * It performs the serial-specific initialization for the tty structure.
4104 */
4105static int
4106rs_open(struct tty_struct *tty, struct file * filp)
4107{
4108 struct e100_serial *info;
4109 int retval, line;
4110 unsigned long page;
4111 int allocated_resources = 0;
4112
4113 /* find which port we want to open */
4114 line = tty->index;
4115
4116 if (line < 0 || line >= NR_PORTS)
4117 return -ENODEV;
4118
4119 /* find the corresponding e100_serial struct in the table */
4120 info = rs_table + line;
4121
4122 /* don't allow the opening of ports that are not enabled in the HW config */
4123 if (!info->enabled)
4124 return -ENODEV;
4125
4126#ifdef SERIAL_DEBUG_OPEN
4127 printk("[%d] rs_open %s, count = %d\n", current->pid, tty->name,
4128 info->count);
4129#endif
4130
4131 info->count++;
4132 tty->driver_data = info;
4133 info->port.tty = tty;
4134
4135 info->port.tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
4136
4137 if (!tmp_buf) {
4138 page = get_zeroed_page(GFP_KERNEL);
4139 if (!page) {
4140 return -ENOMEM;
4141 }
4142 if (tmp_buf)
4143 free_page(page);
4144 else
4145 tmp_buf = (unsigned char *) page;
4146 }
4147
4148 /*
4149 * If the port is in the middle of closing, bail out now
4150 */
4151 if (tty_hung_up_p(filp) ||
4152 (info->flags & ASYNC_CLOSING)) {
4153 wait_event_interruptible_tty(info->close_wait,
4154 !(info->flags & ASYNC_CLOSING));
4155#ifdef SERIAL_DO_RESTART
4156 return ((info->flags & ASYNC_HUP_NOTIFY) ?
4157 -EAGAIN : -ERESTARTSYS);
4158#else
4159 return -EAGAIN;
4160#endif
4161 }
4162
4163 /*
4164 * If DMA is enabled try to allocate the irq's.
4165 */
4166 if (info->count == 1) {
4167 allocated_resources = 1;
4168 if (info->dma_in_enabled) {
4169 if (request_irq(info->dma_in_irq_nbr,
4170 rec_interrupt,
4171 info->dma_in_irq_flags,
4172 info->dma_in_irq_description,
4173 info)) {
4174 printk(KERN_WARNING "DMA irq '%s' busy; "
4175 "falling back to non-DMA mode\n",
4176 info->dma_in_irq_description);
4177 /* Make sure we never try to use DMA in */
4178 /* for the port again. */
4179 info->dma_in_enabled = 0;
4180 } else if (cris_request_dma(info->dma_in_nbr,
4181 info->dma_in_irq_description,
4182 DMA_VERBOSE_ON_ERROR,
4183 info->dma_owner)) {
4184 free_irq(info->dma_in_irq_nbr, info);
4185 printk(KERN_WARNING "DMA '%s' busy; "
4186 "falling back to non-DMA mode\n",
4187 info->dma_in_irq_description);
4188 /* Make sure we never try to use DMA in */
4189 /* for the port again. */
4190 info->dma_in_enabled = 0;
4191 }
4192#ifdef SERIAL_DEBUG_OPEN
4193 else
4194 printk(KERN_DEBUG "DMA irq '%s' allocated\n",
4195 info->dma_in_irq_description);
4196#endif
4197 }
4198 if (info->dma_out_enabled) {
4199 if (request_irq(info->dma_out_irq_nbr,
4200 tr_interrupt,
4201 info->dma_out_irq_flags,
4202 info->dma_out_irq_description,
4203 info)) {
4204 printk(KERN_WARNING "DMA irq '%s' busy; "
4205 "falling back to non-DMA mode\n",
4206 info->dma_out_irq_description);
4207 /* Make sure we never try to use DMA out */
4208 /* for the port again. */
4209 info->dma_out_enabled = 0;
4210 } else if (cris_request_dma(info->dma_out_nbr,
4211 info->dma_out_irq_description,
4212 DMA_VERBOSE_ON_ERROR,
4213 info->dma_owner)) {
4214 free_irq(info->dma_out_irq_nbr, info);
4215 printk(KERN_WARNING "DMA '%s' busy; "
4216 "falling back to non-DMA mode\n",
4217 info->dma_out_irq_description);
4218 /* Make sure we never try to use DMA out */
4219 /* for the port again. */
4220 info->dma_out_enabled = 0;
4221 }
4222#ifdef SERIAL_DEBUG_OPEN
4223 else
4224 printk(KERN_DEBUG "DMA irq '%s' allocated\n",
4225 info->dma_out_irq_description);
4226#endif
4227 }
4228 }
4229
4230 /*
4231 * Start up the serial port
4232 */
4233
4234 retval = startup(info);
4235 if (retval) {
4236 if (allocated_resources)
4237 deinit_port(info);
4238
4239 /* FIXME Decrease count info->count here too? */
4240 return retval;
4241 }
4242
4243
4244 retval = block_til_ready(tty, filp, info);
4245 if (retval) {
4246#ifdef SERIAL_DEBUG_OPEN
4247 printk("rs_open returning after block_til_ready with %d\n",
4248 retval);
4249#endif
4250 if (allocated_resources)
4251 deinit_port(info);
4252
4253 return retval;
4254 }
4255
4256 if ((info->count == 1) && (info->flags & ASYNC_SPLIT_TERMIOS)) {
4257 *tty->termios = info->normal_termios;
4258 change_speed(info);
4259 }
4260
4261#ifdef SERIAL_DEBUG_OPEN
4262 printk("rs_open ttyS%d successful...\n", info->line);
4263#endif
4264 DLOG_INT_TRIG( log_int_pos = 0);
4265
4266 DFLIP( if (info->line == SERIAL_DEBUG_LINE) {
4267 info->icount.rx = 0;
4268 } );
4269
4270 return 0;
4271}
4272
4273#ifdef CONFIG_PROC_FS
4274/*
4275 * /proc fs routines....
4276 */
4277
4278static void seq_line_info(struct seq_file *m, struct e100_serial *info)
4279{
4280 unsigned long tmp;
4281
4282 seq_printf(m, "%d: uart:E100 port:%lX irq:%d",
4283 info->line, (unsigned long)info->ioport, info->irq);
4284
4285 if (!info->ioport || (info->type == PORT_UNKNOWN)) {
4286 seq_printf(m, "\n");
4287 return;
4288 }
4289
4290 seq_printf(m, " baud:%d", info->baud);
4291 seq_printf(m, " tx:%lu rx:%lu",
4292 (unsigned long)info->icount.tx,
4293 (unsigned long)info->icount.rx);
4294 tmp = CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
4295 if (tmp)
4296 seq_printf(m, " tx_pend:%lu/%lu",
4297 (unsigned long)tmp,
4298 (unsigned long)SERIAL_XMIT_SIZE);
4299
4300 seq_printf(m, " rx_pend:%lu/%lu",
4301 (unsigned long)info->recv_cnt,
4302 (unsigned long)info->max_recv_cnt);
4303
4304#if 1
4305 if (info->port.tty) {
4306 if (info->port.tty->stopped)
4307 seq_printf(m, " stopped:%i",
4308 (int)info->port.tty->stopped);
4309 if (info->port.tty->hw_stopped)
4310 seq_printf(m, " hw_stopped:%i",
4311 (int)info->port.tty->hw_stopped);
4312 }
4313
4314 {
4315 unsigned char rstat = info->ioport[REG_STATUS];
4316 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect))
4317 seq_printf(m, " xoff_detect:1");
4318 }
4319
4320#endif
4321
4322 if (info->icount.frame)
4323 seq_printf(m, " fe:%lu", (unsigned long)info->icount.frame);
4324
4325 if (info->icount.parity)
4326 seq_printf(m, " pe:%lu", (unsigned long)info->icount.parity);
4327
4328 if (info->icount.brk)
4329 seq_printf(m, " brk:%lu", (unsigned long)info->icount.brk);
4330
4331 if (info->icount.overrun)
4332 seq_printf(m, " oe:%lu", (unsigned long)info->icount.overrun);
4333
4334 /*
4335 * Last thing is the RS-232 status lines
4336 */
4337 if (!E100_RTS_GET(info))
4338 seq_puts(m, "|RTS");
4339 if (!E100_CTS_GET(info))
4340 seq_puts(m, "|CTS");
4341 if (!E100_DTR_GET(info))
4342 seq_puts(m, "|DTR");
4343 if (!E100_DSR_GET(info))
4344 seq_puts(m, "|DSR");
4345 if (!E100_CD_GET(info))
4346 seq_puts(m, "|CD");
4347 if (!E100_RI_GET(info))
4348 seq_puts(m, "|RI");
4349 seq_puts(m, "\n");
4350}
4351
4352
4353static int crisv10_proc_show(struct seq_file *m, void *v)
4354{
4355 int i;
4356
4357 seq_printf(m, "serinfo:1.0 driver:%s\n", serial_version);
4358
4359 for (i = 0; i < NR_PORTS; i++) {
4360 if (!rs_table[i].enabled)
4361 continue;
4362 seq_line_info(m, &rs_table[i]);
4363 }
4364#ifdef DEBUG_LOG_INCLUDED
4365 for (i = 0; i < debug_log_pos; i++) {
4366 seq_printf(m, "%-4i %lu.%lu ",
4367 i, debug_log[i].time,
4368 timer_data_to_ns(debug_log[i].timer_data));
4369 seq_printf(m, debug_log[i].string, debug_log[i].value);
4370 }
4371 seq_printf(m, "debug_log %i/%i\n", i, DEBUG_LOG_SIZE);
4372 debug_log_pos = 0;
4373#endif
4374 return 0;
4375}
4376
4377static int crisv10_proc_open(struct inode *inode, struct file *file)
4378{
4379 return single_open(file, crisv10_proc_show, NULL);
4380}
4381
4382static const struct file_operations crisv10_proc_fops = {
4383 .owner = THIS_MODULE,
4384 .open = crisv10_proc_open,
4385 .read = seq_read,
4386 .llseek = seq_lseek,
4387 .release = single_release,
4388};
4389#endif
4390
4391
4392/* Finally, routines used to initialize the serial driver. */
4393
4394static void show_serial_version(void)
4395{
4396 printk(KERN_INFO
4397 "ETRAX 100LX serial-driver %s, "
4398 "(c) 2000-2004 Axis Communications AB\r\n",
4399 &serial_version[11]); /* "$Revision: x.yy" */
4400}
4401
4402/* rs_init inits the driver at boot (using the module_init chain) */
4403
4404static const struct tty_operations rs_ops = {
4405 .open = rs_open,
4406 .close = rs_close,
4407 .write = rs_write,
4408 .flush_chars = rs_flush_chars,
4409 .write_room = rs_write_room,
4410 .chars_in_buffer = rs_chars_in_buffer,
4411 .flush_buffer = rs_flush_buffer,
4412 .ioctl = rs_ioctl,
4413 .throttle = rs_throttle,
4414 .unthrottle = rs_unthrottle,
4415 .set_termios = rs_set_termios,
4416 .stop = rs_stop,
4417 .start = rs_start,
4418 .hangup = rs_hangup,
4419 .break_ctl = rs_break,
4420 .send_xchar = rs_send_xchar,
4421 .wait_until_sent = rs_wait_until_sent,
4422 .tiocmget = rs_tiocmget,
4423 .tiocmset = rs_tiocmset,
4424#ifdef CONFIG_PROC_FS
4425 .proc_fops = &crisv10_proc_fops,
4426#endif
4427};
4428
4429static int __init rs_init(void)
4430{
4431 int i;
4432 struct e100_serial *info;
4433 struct tty_driver *driver = alloc_tty_driver(NR_PORTS);
4434
4435 if (!driver)
4436 return -ENOMEM;
4437
4438 show_serial_version();
4439
4440 /* Setup the timed flush handler system */
4441
4442#if !defined(CONFIG_ETRAX_SERIAL_FAST_TIMER)
4443 setup_timer(&flush_timer, timed_flush_handler, 0);
4444 mod_timer(&flush_timer, jiffies + 5);
4445#endif
4446
4447#if defined(CONFIG_ETRAX_RS485)
4448#if defined(CONFIG_ETRAX_RS485_ON_PA)
4449 if (cris_io_interface_allocate_pins(if_ser0, 'a', rs485_pa_bit,
4450 rs485_pa_bit)) {
4451 printk(KERN_CRIT "ETRAX100LX serial: Could not allocate "
4452 "RS485 pin\n");
4453 put_tty_driver(driver);
4454 return -EBUSY;
4455 }
4456#endif
4457#if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
4458 if (cris_io_interface_allocate_pins(if_ser0, 'g', rs485_pa_bit,
4459 rs485_port_g_bit)) {
4460 printk(KERN_CRIT "ETRAX100LX serial: Could not allocate "
4461 "RS485 pin\n");
4462 put_tty_driver(driver);
4463 return -EBUSY;
4464 }
4465#endif
4466#endif
4467
4468 /* Initialize the tty_driver structure */
4469
4470 driver->driver_name = "serial";
4471 driver->name = "ttyS";
4472 driver->major = TTY_MAJOR;
4473 driver->minor_start = 64;
4474 driver->type = TTY_DRIVER_TYPE_SERIAL;
4475 driver->subtype = SERIAL_TYPE_NORMAL;
4476 driver->init_termios = tty_std_termios;
4477 driver->init_termios.c_cflag =
4478 B115200 | CS8 | CREAD | HUPCL | CLOCAL; /* is normally B9600 default... */
4479 driver->init_termios.c_ispeed = 115200;
4480 driver->init_termios.c_ospeed = 115200;
4481 driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
4482
4483 tty_set_operations(driver, &rs_ops);
4484 serial_driver = driver;
4485 if (tty_register_driver(driver))
4486 panic("Couldn't register serial driver\n");
4487 /* do some initializing for the separate ports */
4488
4489 for (i = 0, info = rs_table; i < NR_PORTS; i++,info++) {
4490 if (info->enabled) {
4491 if (cris_request_io_interface(info->io_if,
4492 info->io_if_description)) {
4493 printk(KERN_CRIT "ETRAX100LX async serial: "
4494 "Could not allocate IO pins for "
4495 "%s, port %d\n",
4496 info->io_if_description, i);
4497 info->enabled = 0;
4498 }
4499 }
4500 info->uses_dma_in = 0;
4501 info->uses_dma_out = 0;
4502 info->line = i;
4503 info->port.tty = NULL;
4504 info->type = PORT_ETRAX;
4505 info->tr_running = 0;
4506 info->forced_eop = 0;
4507 info->baud_base = DEF_BAUD_BASE;
4508 info->custom_divisor = 0;
4509 info->flags = 0;
4510 info->close_delay = 5*HZ/10;
4511 info->closing_wait = 30*HZ;
4512 info->x_char = 0;
4513 info->event = 0;
4514 info->count = 0;
4515 info->blocked_open = 0;
4516 info->normal_termios = driver->init_termios;
4517 init_waitqueue_head(&info->open_wait);
4518 init_waitqueue_head(&info->close_wait);
4519 info->xmit.buf = NULL;
4520 info->xmit.tail = info->xmit.head = 0;
4521 info->first_recv_buffer = info->last_recv_buffer = NULL;
4522 info->recv_cnt = info->max_recv_cnt = 0;
4523 info->last_tx_active_usec = 0;
4524 info->last_tx_active = 0;
4525
4526#if defined(CONFIG_ETRAX_RS485)
4527 /* Set sane defaults */
4528 info->rs485.flags &= ~(SER_RS485_RTS_ON_SEND);
4529 info->rs485.flags |= SER_RS485_RTS_AFTER_SEND;
4530 info->rs485.delay_rts_before_send = 0;
4531 info->rs485.flags &= ~(SER_RS485_ENABLED);
4532#endif
4533 INIT_WORK(&info->work, do_softint);
4534
4535 if (info->enabled) {
4536 printk(KERN_INFO "%s%d at %p is a builtin UART with DMA\n",
4537 serial_driver->name, info->line, info->ioport);
4538 }
4539 }
4540#ifdef CONFIG_ETRAX_FAST_TIMER
4541#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
4542 memset(fast_timers, 0, sizeof(fast_timers));
4543#endif
4544#ifdef CONFIG_ETRAX_RS485
4545 memset(fast_timers_rs485, 0, sizeof(fast_timers_rs485));
4546#endif
4547 fast_timer_init();
4548#endif
4549
4550#ifndef CONFIG_SVINTO_SIM
4551#ifndef CONFIG_ETRAX_KGDB
4552 /* Not needed in simulator. May only complicate stuff. */
4553 /* hook the irq's for DMA channel 6 and 7, serial output and input, and some more... */
4554
4555 if (request_irq(SERIAL_IRQ_NBR, ser_interrupt,
4556 IRQF_SHARED | IRQF_DISABLED, "serial ", driver))
4557 panic("%s: Failed to request irq8", __func__);
4558
4559#endif
4560#endif /* CONFIG_SVINTO_SIM */
4561
4562 return 0;
4563}
4564
4565/* this makes sure that rs_init is called during kernel boot */
4566
4567module_init(rs_init);
diff --git a/drivers/serial/crisv10.h b/drivers/serial/crisv10.h
deleted file mode 100644
index ea0beb46a10d..000000000000
--- a/drivers/serial/crisv10.h
+++ /dev/null
@@ -1,147 +0,0 @@
1/*
2 * serial.h: Arch-dep definitions for the Etrax100 serial driver.
3 *
4 * Copyright (C) 1998-2007 Axis Communications AB
5 */
6
7#ifndef _ETRAX_SERIAL_H
8#define _ETRAX_SERIAL_H
9
10#include <linux/circ_buf.h>
11#include <asm/termios.h>
12#include <asm/dma.h>
13#include <arch/io_interface_mux.h>
14
15/* Software state per channel */
16
17#ifdef __KERNEL__
18/*
19 * This is our internal structure for each serial port's state.
20 *
21 * Many fields are paralleled by the structure used by the serial_struct
22 * structure.
23 *
24 * For definitions of the flags field, see tty.h
25 */
26
27#define SERIAL_RECV_DESCRIPTORS 8
28
29struct etrax_recv_buffer {
30 struct etrax_recv_buffer *next;
31 unsigned short length;
32 unsigned char error;
33 unsigned char pad;
34
35 unsigned char buffer[0];
36};
37
38struct e100_serial {
39 struct tty_port port;
40 int baud;
41 volatile u8 *ioport; /* R_SERIALx_CTRL */
42 u32 irq; /* bitnr in R_IRQ_MASK2 for dmaX_descr */
43
44 /* Output registers */
45 volatile u8 *oclrintradr; /* adr to R_DMA_CHx_CLR_INTR */
46 volatile u32 *ofirstadr; /* adr to R_DMA_CHx_FIRST */
47 volatile u8 *ocmdadr; /* adr to R_DMA_CHx_CMD */
48 const volatile u8 *ostatusadr; /* adr to R_DMA_CHx_STATUS */
49
50 /* Input registers */
51 volatile u8 *iclrintradr; /* adr to R_DMA_CHx_CLR_INTR */
52 volatile u32 *ifirstadr; /* adr to R_DMA_CHx_FIRST */
53 volatile u8 *icmdadr; /* adr to R_DMA_CHx_CMD */
54 volatile u32 *idescradr; /* adr to R_DMA_CHx_DESCR */
55
56 int flags; /* defined in tty.h */
57
58 u8 rx_ctrl; /* shadow for R_SERIALx_REC_CTRL */
59 u8 tx_ctrl; /* shadow for R_SERIALx_TR_CTRL */
60 u8 iseteop; /* bit number for R_SET_EOP for the input dma */
61 int enabled; /* Set to 1 if the port is enabled in HW config */
62
63 u8 dma_out_enabled; /* Set to 1 if DMA should be used */
64 u8 dma_in_enabled; /* Set to 1 if DMA should be used */
65
66 /* end of fields defined in rs_table[] in .c-file */
67 int dma_owner;
68 unsigned int dma_in_nbr;
69 unsigned int dma_out_nbr;
70 unsigned int dma_in_irq_nbr;
71 unsigned int dma_out_irq_nbr;
72 unsigned long dma_in_irq_flags;
73 unsigned long dma_out_irq_flags;
74 char *dma_in_irq_description;
75 char *dma_out_irq_description;
76
77 enum cris_io_interface io_if;
78 char *io_if_description;
79
80 u8 uses_dma_in; /* Set to 1 if DMA is used */
81 u8 uses_dma_out; /* Set to 1 if DMA is used */
82 u8 forced_eop; /* a fifo eop has been forced */
83 int baud_base; /* For special baudrates */
84 int custom_divisor; /* For special baudrates */
85 struct etrax_dma_descr tr_descr;
86 struct etrax_dma_descr rec_descr[SERIAL_RECV_DESCRIPTORS];
87 int cur_rec_descr;
88
89 volatile int tr_running; /* 1 if output is running */
90
91 struct tty_struct *tty;
92 int read_status_mask;
93 int ignore_status_mask;
94 int x_char; /* xon/xoff character */
95 int close_delay;
96 unsigned short closing_wait;
97 unsigned short closing_wait2;
98 unsigned long event;
99 unsigned long last_active;
100 int line;
101 int type; /* PORT_ETRAX */
102 int count; /* # of fd on device */
103 int blocked_open; /* # of blocked opens */
104 struct circ_buf xmit;
105 struct etrax_recv_buffer *first_recv_buffer;
106 struct etrax_recv_buffer *last_recv_buffer;
107 unsigned int recv_cnt;
108 unsigned int max_recv_cnt;
109
110 struct work_struct work;
111 struct async_icount icount; /* error-statistics etc.*/
112 struct ktermios normal_termios;
113 struct ktermios callout_termios;
114 wait_queue_head_t open_wait;
115 wait_queue_head_t close_wait;
116
117 unsigned long char_time_usec; /* The time for 1 char, in usecs */
118 unsigned long flush_time_usec; /* How often we should flush */
119 unsigned long last_tx_active_usec; /* Last tx usec in the jiffies */
120 unsigned long last_tx_active; /* Last tx time in jiffies */
121 unsigned long last_rx_active_usec; /* Last rx usec in the jiffies */
122 unsigned long last_rx_active; /* Last rx time in jiffies */
123
124 int break_detected_cnt;
125 int errorcode;
126
127#ifdef CONFIG_ETRAX_RS485
128 struct serial_rs485 rs485; /* RS-485 support */
129#endif
130};
131
132/* this PORT is not in the standard serial.h. it's not actually used for
133 * anything since we only have one type of async serial-port anyway in this
134 * system.
135 */
136
137#define PORT_ETRAX 1
138
139/*
140 * Events are used to schedule things to happen at timer-interrupt
141 * time, instead of at rs interrupt time.
142 */
143#define RS_EVENT_WRITE_WAKEUP 0
144
145#endif /* __KERNEL__ */
146
147#endif /* !_ETRAX_SERIAL_H */
diff --git a/drivers/serial/dz.c b/drivers/serial/dz.c
deleted file mode 100644
index 57421d776329..000000000000
--- a/drivers/serial/dz.c
+++ /dev/null
@@ -1,955 +0,0 @@
1/*
2 * dz.c: Serial port driver for DECstations equipped
3 * with the DZ chipset.
4 *
5 * Copyright (C) 1998 Olivier A. D. Lebaillif
6 *
7 * Email: olivier.lebaillif@ifrsys.com
8 *
9 * Copyright (C) 2004, 2006, 2007 Maciej W. Rozycki
10 *
11 * [31-AUG-98] triemer
12 * Changed IRQ to use Harald's dec internals interrupts.h
13 * removed base_addr code - moving address assignment to setup.c
14 * Changed name of dz_init to rs_init to be consistent with tc code
15 * [13-NOV-98] triemer fixed code to receive characters
16 * after patches by harald to irq code.
17 * [09-JAN-99] triemer minor fix for schedule - due to removal of timeout
18 * field from "current" - somewhere between 2.1.121 and 2.1.131
19 Qua Jun 27 15:02:26 BRT 2001
20 * [27-JUN-2001] Arnaldo Carvalho de Melo <acme@conectiva.com.br> - cleanups
21 *
22 * Parts (C) 1999 David Airlie, airlied@linux.ie
23 * [07-SEP-99] Bugfixes
24 *
25 * [06-Jan-2002] Russell King <rmk@arm.linux.org.uk>
26 * Converted to new serial core
27 */
28
29#undef DEBUG_DZ
30
31#if defined(CONFIG_SERIAL_DZ_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
32#define SUPPORT_SYSRQ
33#endif
34
35#include <linux/bitops.h>
36#include <linux/compiler.h>
37#include <linux/console.h>
38#include <linux/delay.h>
39#include <linux/errno.h>
40#include <linux/init.h>
41#include <linux/interrupt.h>
42#include <linux/ioport.h>
43#include <linux/kernel.h>
44#include <linux/major.h>
45#include <linux/module.h>
46#include <linux/serial.h>
47#include <linux/serial_core.h>
48#include <linux/sysrq.h>
49#include <linux/tty.h>
50
51#include <asm/atomic.h>
52#include <asm/bootinfo.h>
53#include <asm/io.h>
54#include <asm/system.h>
55
56#include <asm/dec/interrupts.h>
57#include <asm/dec/kn01.h>
58#include <asm/dec/kn02.h>
59#include <asm/dec/machtype.h>
60#include <asm/dec/prom.h>
61#include <asm/dec/system.h>
62
63#include "dz.h"
64
65
66MODULE_DESCRIPTION("DECstation DZ serial driver");
67MODULE_LICENSE("GPL");
68
69
70static char dz_name[] __initdata = "DECstation DZ serial driver version ";
71static char dz_version[] __initdata = "1.04";
72
73struct dz_port {
74 struct dz_mux *mux;
75 struct uart_port port;
76 unsigned int cflag;
77};
78
79struct dz_mux {
80 struct dz_port dport[DZ_NB_PORT];
81 atomic_t map_guard;
82 atomic_t irq_guard;
83 int initialised;
84};
85
86static struct dz_mux dz_mux;
87
88static inline struct dz_port *to_dport(struct uart_port *uport)
89{
90 return container_of(uport, struct dz_port, port);
91}
92
93/*
94 * ------------------------------------------------------------
95 * dz_in () and dz_out ()
96 *
97 * These routines are used to access the registers of the DZ
98 * chip, hiding relocation differences between implementation.
99 * ------------------------------------------------------------
100 */
101
102static u16 dz_in(struct dz_port *dport, unsigned offset)
103{
104 void __iomem *addr = dport->port.membase + offset;
105
106 return readw(addr);
107}
108
109static void dz_out(struct dz_port *dport, unsigned offset, u16 value)
110{
111 void __iomem *addr = dport->port.membase + offset;
112
113 writew(value, addr);
114}
115
116/*
117 * ------------------------------------------------------------
118 * rs_stop () and rs_start ()
119 *
120 * These routines are called before setting or resetting
121 * tty->stopped. They enable or disable transmitter interrupts,
122 * as necessary.
123 * ------------------------------------------------------------
124 */
125
126static void dz_stop_tx(struct uart_port *uport)
127{
128 struct dz_port *dport = to_dport(uport);
129 u16 tmp, mask = 1 << dport->port.line;
130
131 tmp = dz_in(dport, DZ_TCR); /* read the TX flag */
132 tmp &= ~mask; /* clear the TX flag */
133 dz_out(dport, DZ_TCR, tmp);
134}
135
136static void dz_start_tx(struct uart_port *uport)
137{
138 struct dz_port *dport = to_dport(uport);
139 u16 tmp, mask = 1 << dport->port.line;
140
141 tmp = dz_in(dport, DZ_TCR); /* read the TX flag */
142 tmp |= mask; /* set the TX flag */
143 dz_out(dport, DZ_TCR, tmp);
144}
145
146static void dz_stop_rx(struct uart_port *uport)
147{
148 struct dz_port *dport = to_dport(uport);
149
150 dport->cflag &= ~DZ_RXENAB;
151 dz_out(dport, DZ_LPR, dport->cflag);
152}
153
154static void dz_enable_ms(struct uart_port *uport)
155{
156 /* nothing to do */
157}
158
159/*
160 * ------------------------------------------------------------
161 *
162 * Here start the interrupt handling routines. All of the following
163 * subroutines are declared as inline and are folded into
164 * dz_interrupt. They were separated out for readability's sake.
165 *
166 * Note: dz_interrupt() is a "fast" interrupt, which means that it
167 * runs with interrupts turned off. People who may want to modify
168 * dz_interrupt() should try to keep the interrupt handler as fast as
169 * possible. After you are done making modifications, it is not a bad
170 * idea to do:
171 *
172 * make drivers/serial/dz.s
173 *
174 * and look at the resulting assemble code in dz.s.
175 *
176 * ------------------------------------------------------------
177 */
178
179/*
180 * ------------------------------------------------------------
181 * receive_char ()
182 *
183 * This routine deals with inputs from any lines.
184 * ------------------------------------------------------------
185 */
186static inline void dz_receive_chars(struct dz_mux *mux)
187{
188 struct uart_port *uport;
189 struct dz_port *dport = &mux->dport[0];
190 struct tty_struct *tty = NULL;
191 struct uart_icount *icount;
192 int lines_rx[DZ_NB_PORT] = { [0 ... DZ_NB_PORT - 1] = 0 };
193 unsigned char ch, flag;
194 u16 status;
195 int i;
196
197 while ((status = dz_in(dport, DZ_RBUF)) & DZ_DVAL) {
198 dport = &mux->dport[LINE(status)];
199 uport = &dport->port;
200 tty = uport->state->port.tty; /* point to the proper dev */
201
202 ch = UCHAR(status); /* grab the char */
203 flag = TTY_NORMAL;
204
205 icount = &uport->icount;
206 icount->rx++;
207
208 if (unlikely(status & (DZ_OERR | DZ_FERR | DZ_PERR))) {
209
210 /*
211 * There is no separate BREAK status bit, so treat
212 * null characters with framing errors as BREAKs;
213 * normally, otherwise. For this move the Framing
214 * Error bit to a simulated BREAK bit.
215 */
216 if (!ch) {
217 status |= (status & DZ_FERR) >>
218 (ffs(DZ_FERR) - ffs(DZ_BREAK));
219 status &= ~DZ_FERR;
220 }
221
222 /* Handle SysRq/SAK & keep track of the statistics. */
223 if (status & DZ_BREAK) {
224 icount->brk++;
225 if (uart_handle_break(uport))
226 continue;
227 } else if (status & DZ_FERR)
228 icount->frame++;
229 else if (status & DZ_PERR)
230 icount->parity++;
231 if (status & DZ_OERR)
232 icount->overrun++;
233
234 status &= uport->read_status_mask;
235 if (status & DZ_BREAK)
236 flag = TTY_BREAK;
237 else if (status & DZ_FERR)
238 flag = TTY_FRAME;
239 else if (status & DZ_PERR)
240 flag = TTY_PARITY;
241
242 }
243
244 if (uart_handle_sysrq_char(uport, ch))
245 continue;
246
247 uart_insert_char(uport, status, DZ_OERR, ch, flag);
248 lines_rx[LINE(status)] = 1;
249 }
250 for (i = 0; i < DZ_NB_PORT; i++)
251 if (lines_rx[i])
252 tty_flip_buffer_push(mux->dport[i].port.state->port.tty);
253}
254
255/*
256 * ------------------------------------------------------------
257 * transmit_char ()
258 *
259 * This routine deals with outputs to any lines.
260 * ------------------------------------------------------------
261 */
262static inline void dz_transmit_chars(struct dz_mux *mux)
263{
264 struct dz_port *dport = &mux->dport[0];
265 struct circ_buf *xmit;
266 unsigned char tmp;
267 u16 status;
268
269 status = dz_in(dport, DZ_CSR);
270 dport = &mux->dport[LINE(status)];
271 xmit = &dport->port.state->xmit;
272
273 if (dport->port.x_char) { /* XON/XOFF chars */
274 dz_out(dport, DZ_TDR, dport->port.x_char);
275 dport->port.icount.tx++;
276 dport->port.x_char = 0;
277 return;
278 }
279 /* If nothing to do or stopped or hardware stopped. */
280 if (uart_circ_empty(xmit) || uart_tx_stopped(&dport->port)) {
281 spin_lock(&dport->port.lock);
282 dz_stop_tx(&dport->port);
283 spin_unlock(&dport->port.lock);
284 return;
285 }
286
287 /*
288 * If something to do... (remember the dz has no output fifo,
289 * so we go one char at a time) :-<
290 */
291 tmp = xmit->buf[xmit->tail];
292 xmit->tail = (xmit->tail + 1) & (DZ_XMIT_SIZE - 1);
293 dz_out(dport, DZ_TDR, tmp);
294 dport->port.icount.tx++;
295
296 if (uart_circ_chars_pending(xmit) < DZ_WAKEUP_CHARS)
297 uart_write_wakeup(&dport->port);
298
299 /* Are we are done. */
300 if (uart_circ_empty(xmit)) {
301 spin_lock(&dport->port.lock);
302 dz_stop_tx(&dport->port);
303 spin_unlock(&dport->port.lock);
304 }
305}
306
307/*
308 * ------------------------------------------------------------
309 * check_modem_status()
310 *
311 * DS 3100 & 5100: Only valid for the MODEM line, duh!
312 * DS 5000/200: Valid for the MODEM and PRINTER line.
313 * ------------------------------------------------------------
314 */
315static inline void check_modem_status(struct dz_port *dport)
316{
317 /*
318 * FIXME:
319 * 1. No status change interrupt; use a timer.
320 * 2. Handle the 3100/5000 as appropriate. --macro
321 */
322 u16 status;
323
324 /* If not the modem line just return. */
325 if (dport->port.line != DZ_MODEM)
326 return;
327
328 status = dz_in(dport, DZ_MSR);
329
330 /* it's easy, since DSR2 is the only bit in the register */
331 if (status)
332 dport->port.icount.dsr++;
333}
334
335/*
336 * ------------------------------------------------------------
337 * dz_interrupt ()
338 *
339 * this is the main interrupt routine for the DZ chip.
340 * It deals with the multiple ports.
341 * ------------------------------------------------------------
342 */
343static irqreturn_t dz_interrupt(int irq, void *dev_id)
344{
345 struct dz_mux *mux = dev_id;
346 struct dz_port *dport = &mux->dport[0];
347 u16 status;
348
349 /* get the reason why we just got an irq */
350 status = dz_in(dport, DZ_CSR);
351
352 if ((status & (DZ_RDONE | DZ_RIE)) == (DZ_RDONE | DZ_RIE))
353 dz_receive_chars(mux);
354
355 if ((status & (DZ_TRDY | DZ_TIE)) == (DZ_TRDY | DZ_TIE))
356 dz_transmit_chars(mux);
357
358 return IRQ_HANDLED;
359}
360
361/*
362 * -------------------------------------------------------------------
363 * Here ends the DZ interrupt routines.
364 * -------------------------------------------------------------------
365 */
366
367static unsigned int dz_get_mctrl(struct uart_port *uport)
368{
369 /*
370 * FIXME: Handle the 3100/5000 as appropriate. --macro
371 */
372 struct dz_port *dport = to_dport(uport);
373 unsigned int mctrl = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
374
375 if (dport->port.line == DZ_MODEM) {
376 if (dz_in(dport, DZ_MSR) & DZ_MODEM_DSR)
377 mctrl &= ~TIOCM_DSR;
378 }
379
380 return mctrl;
381}
382
383static void dz_set_mctrl(struct uart_port *uport, unsigned int mctrl)
384{
385 /*
386 * FIXME: Handle the 3100/5000 as appropriate. --macro
387 */
388 struct dz_port *dport = to_dport(uport);
389 u16 tmp;
390
391 if (dport->port.line == DZ_MODEM) {
392 tmp = dz_in(dport, DZ_TCR);
393 if (mctrl & TIOCM_DTR)
394 tmp &= ~DZ_MODEM_DTR;
395 else
396 tmp |= DZ_MODEM_DTR;
397 dz_out(dport, DZ_TCR, tmp);
398 }
399}
400
401/*
402 * -------------------------------------------------------------------
403 * startup ()
404 *
405 * various initialization tasks
406 * -------------------------------------------------------------------
407 */
408static int dz_startup(struct uart_port *uport)
409{
410 struct dz_port *dport = to_dport(uport);
411 struct dz_mux *mux = dport->mux;
412 unsigned long flags;
413 int irq_guard;
414 int ret;
415 u16 tmp;
416
417 irq_guard = atomic_add_return(1, &mux->irq_guard);
418 if (irq_guard != 1)
419 return 0;
420
421 ret = request_irq(dport->port.irq, dz_interrupt,
422 IRQF_SHARED, "dz", mux);
423 if (ret) {
424 atomic_add(-1, &mux->irq_guard);
425 printk(KERN_ERR "dz: Cannot get IRQ %d!\n", dport->port.irq);
426 return ret;
427 }
428
429 spin_lock_irqsave(&dport->port.lock, flags);
430
431 /* Enable interrupts. */
432 tmp = dz_in(dport, DZ_CSR);
433 tmp |= DZ_RIE | DZ_TIE;
434 dz_out(dport, DZ_CSR, tmp);
435
436 spin_unlock_irqrestore(&dport->port.lock, flags);
437
438 return 0;
439}
440
441/*
442 * -------------------------------------------------------------------
443 * shutdown ()
444 *
445 * This routine will shutdown a serial port; interrupts are disabled, and
446 * DTR is dropped if the hangup on close termio flag is on.
447 * -------------------------------------------------------------------
448 */
449static void dz_shutdown(struct uart_port *uport)
450{
451 struct dz_port *dport = to_dport(uport);
452 struct dz_mux *mux = dport->mux;
453 unsigned long flags;
454 int irq_guard;
455 u16 tmp;
456
457 spin_lock_irqsave(&dport->port.lock, flags);
458 dz_stop_tx(&dport->port);
459 spin_unlock_irqrestore(&dport->port.lock, flags);
460
461 irq_guard = atomic_add_return(-1, &mux->irq_guard);
462 if (!irq_guard) {
463 /* Disable interrupts. */
464 tmp = dz_in(dport, DZ_CSR);
465 tmp &= ~(DZ_RIE | DZ_TIE);
466 dz_out(dport, DZ_CSR, tmp);
467
468 free_irq(dport->port.irq, mux);
469 }
470}
471
472/*
473 * -------------------------------------------------------------------
474 * dz_tx_empty() -- get the transmitter empty status
475 *
476 * Purpose: Let user call ioctl() to get info when the UART physically
477 * is emptied. On bus types like RS485, the transmitter must
478 * release the bus after transmitting. This must be done when
479 * the transmit shift register is empty, not be done when the
480 * transmit holding register is empty. This functionality
481 * allows an RS485 driver to be written in user space.
482 * -------------------------------------------------------------------
483 */
484static unsigned int dz_tx_empty(struct uart_port *uport)
485{
486 struct dz_port *dport = to_dport(uport);
487 unsigned short tmp, mask = 1 << dport->port.line;
488
489 tmp = dz_in(dport, DZ_TCR);
490 tmp &= mask;
491
492 return tmp ? 0 : TIOCSER_TEMT;
493}
494
495static void dz_break_ctl(struct uart_port *uport, int break_state)
496{
497 /*
498 * FIXME: Can't access BREAK bits in TDR easily;
499 * reuse the code for polled TX. --macro
500 */
501 struct dz_port *dport = to_dport(uport);
502 unsigned long flags;
503 unsigned short tmp, mask = 1 << dport->port.line;
504
505 spin_lock_irqsave(&uport->lock, flags);
506 tmp = dz_in(dport, DZ_TCR);
507 if (break_state)
508 tmp |= mask;
509 else
510 tmp &= ~mask;
511 dz_out(dport, DZ_TCR, tmp);
512 spin_unlock_irqrestore(&uport->lock, flags);
513}
514
515static int dz_encode_baud_rate(unsigned int baud)
516{
517 switch (baud) {
518 case 50:
519 return DZ_B50;
520 case 75:
521 return DZ_B75;
522 case 110:
523 return DZ_B110;
524 case 134:
525 return DZ_B134;
526 case 150:
527 return DZ_B150;
528 case 300:
529 return DZ_B300;
530 case 600:
531 return DZ_B600;
532 case 1200:
533 return DZ_B1200;
534 case 1800:
535 return DZ_B1800;
536 case 2000:
537 return DZ_B2000;
538 case 2400:
539 return DZ_B2400;
540 case 3600:
541 return DZ_B3600;
542 case 4800:
543 return DZ_B4800;
544 case 7200:
545 return DZ_B7200;
546 case 9600:
547 return DZ_B9600;
548 default:
549 return -1;
550 }
551}
552
553
554static void dz_reset(struct dz_port *dport)
555{
556 struct dz_mux *mux = dport->mux;
557
558 if (mux->initialised)
559 return;
560
561 dz_out(dport, DZ_CSR, DZ_CLR);
562 while (dz_in(dport, DZ_CSR) & DZ_CLR);
563 iob();
564
565 /* Enable scanning. */
566 dz_out(dport, DZ_CSR, DZ_MSE);
567
568 mux->initialised = 1;
569}
570
571static void dz_set_termios(struct uart_port *uport, struct ktermios *termios,
572 struct ktermios *old_termios)
573{
574 struct dz_port *dport = to_dport(uport);
575 unsigned long flags;
576 unsigned int cflag, baud;
577 int bflag;
578
579 cflag = dport->port.line;
580
581 switch (termios->c_cflag & CSIZE) {
582 case CS5:
583 cflag |= DZ_CS5;
584 break;
585 case CS6:
586 cflag |= DZ_CS6;
587 break;
588 case CS7:
589 cflag |= DZ_CS7;
590 break;
591 case CS8:
592 default:
593 cflag |= DZ_CS8;
594 }
595
596 if (termios->c_cflag & CSTOPB)
597 cflag |= DZ_CSTOPB;
598 if (termios->c_cflag & PARENB)
599 cflag |= DZ_PARENB;
600 if (termios->c_cflag & PARODD)
601 cflag |= DZ_PARODD;
602
603 baud = uart_get_baud_rate(uport, termios, old_termios, 50, 9600);
604 bflag = dz_encode_baud_rate(baud);
605 if (bflag < 0) { /* Try to keep unchanged. */
606 baud = uart_get_baud_rate(uport, old_termios, NULL, 50, 9600);
607 bflag = dz_encode_baud_rate(baud);
608 if (bflag < 0) { /* Resort to 9600. */
609 baud = 9600;
610 bflag = DZ_B9600;
611 }
612 tty_termios_encode_baud_rate(termios, baud, baud);
613 }
614 cflag |= bflag;
615
616 if (termios->c_cflag & CREAD)
617 cflag |= DZ_RXENAB;
618
619 spin_lock_irqsave(&dport->port.lock, flags);
620
621 uart_update_timeout(uport, termios->c_cflag, baud);
622
623 dz_out(dport, DZ_LPR, cflag);
624 dport->cflag = cflag;
625
626 /* setup accept flag */
627 dport->port.read_status_mask = DZ_OERR;
628 if (termios->c_iflag & INPCK)
629 dport->port.read_status_mask |= DZ_FERR | DZ_PERR;
630 if (termios->c_iflag & (BRKINT | PARMRK))
631 dport->port.read_status_mask |= DZ_BREAK;
632
633 /* characters to ignore */
634 uport->ignore_status_mask = 0;
635 if ((termios->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
636 dport->port.ignore_status_mask |= DZ_OERR;
637 if (termios->c_iflag & IGNPAR)
638 dport->port.ignore_status_mask |= DZ_FERR | DZ_PERR;
639 if (termios->c_iflag & IGNBRK)
640 dport->port.ignore_status_mask |= DZ_BREAK;
641
642 spin_unlock_irqrestore(&dport->port.lock, flags);
643}
644
645/*
646 * Hack alert!
647 * Required solely so that the initial PROM-based console
648 * works undisturbed in parallel with this one.
649 */
650static void dz_pm(struct uart_port *uport, unsigned int state,
651 unsigned int oldstate)
652{
653 struct dz_port *dport = to_dport(uport);
654 unsigned long flags;
655
656 spin_lock_irqsave(&dport->port.lock, flags);
657 if (state < 3)
658 dz_start_tx(&dport->port);
659 else
660 dz_stop_tx(&dport->port);
661 spin_unlock_irqrestore(&dport->port.lock, flags);
662}
663
664
665static const char *dz_type(struct uart_port *uport)
666{
667 return "DZ";
668}
669
670static void dz_release_port(struct uart_port *uport)
671{
672 struct dz_mux *mux = to_dport(uport)->mux;
673 int map_guard;
674
675 iounmap(uport->membase);
676 uport->membase = NULL;
677
678 map_guard = atomic_add_return(-1, &mux->map_guard);
679 if (!map_guard)
680 release_mem_region(uport->mapbase, dec_kn_slot_size);
681}
682
683static int dz_map_port(struct uart_port *uport)
684{
685 if (!uport->membase)
686 uport->membase = ioremap_nocache(uport->mapbase,
687 dec_kn_slot_size);
688 if (!uport->membase) {
689 printk(KERN_ERR "dz: Cannot map MMIO\n");
690 return -ENOMEM;
691 }
692 return 0;
693}
694
695static int dz_request_port(struct uart_port *uport)
696{
697 struct dz_mux *mux = to_dport(uport)->mux;
698 int map_guard;
699 int ret;
700
701 map_guard = atomic_add_return(1, &mux->map_guard);
702 if (map_guard == 1) {
703 if (!request_mem_region(uport->mapbase, dec_kn_slot_size,
704 "dz")) {
705 atomic_add(-1, &mux->map_guard);
706 printk(KERN_ERR
707 "dz: Unable to reserve MMIO resource\n");
708 return -EBUSY;
709 }
710 }
711 ret = dz_map_port(uport);
712 if (ret) {
713 map_guard = atomic_add_return(-1, &mux->map_guard);
714 if (!map_guard)
715 release_mem_region(uport->mapbase, dec_kn_slot_size);
716 return ret;
717 }
718 return 0;
719}
720
721static void dz_config_port(struct uart_port *uport, int flags)
722{
723 struct dz_port *dport = to_dport(uport);
724
725 if (flags & UART_CONFIG_TYPE) {
726 if (dz_request_port(uport))
727 return;
728
729 uport->type = PORT_DZ;
730
731 dz_reset(dport);
732 }
733}
734
735/*
736 * Verify the new serial_struct (for TIOCSSERIAL).
737 */
738static int dz_verify_port(struct uart_port *uport, struct serial_struct *ser)
739{
740 int ret = 0;
741
742 if (ser->type != PORT_UNKNOWN && ser->type != PORT_DZ)
743 ret = -EINVAL;
744 if (ser->irq != uport->irq)
745 ret = -EINVAL;
746 return ret;
747}
748
749static struct uart_ops dz_ops = {
750 .tx_empty = dz_tx_empty,
751 .get_mctrl = dz_get_mctrl,
752 .set_mctrl = dz_set_mctrl,
753 .stop_tx = dz_stop_tx,
754 .start_tx = dz_start_tx,
755 .stop_rx = dz_stop_rx,
756 .enable_ms = dz_enable_ms,
757 .break_ctl = dz_break_ctl,
758 .startup = dz_startup,
759 .shutdown = dz_shutdown,
760 .set_termios = dz_set_termios,
761 .pm = dz_pm,
762 .type = dz_type,
763 .release_port = dz_release_port,
764 .request_port = dz_request_port,
765 .config_port = dz_config_port,
766 .verify_port = dz_verify_port,
767};
768
769static void __init dz_init_ports(void)
770{
771 static int first = 1;
772 unsigned long base;
773 int line;
774
775 if (!first)
776 return;
777 first = 0;
778
779 if (mips_machtype == MACH_DS23100 || mips_machtype == MACH_DS5100)
780 base = dec_kn_slot_base + KN01_DZ11;
781 else
782 base = dec_kn_slot_base + KN02_DZ11;
783
784 for (line = 0; line < DZ_NB_PORT; line++) {
785 struct dz_port *dport = &dz_mux.dport[line];
786 struct uart_port *uport = &dport->port;
787
788 dport->mux = &dz_mux;
789
790 uport->irq = dec_interrupt[DEC_IRQ_DZ11];
791 uport->fifosize = 1;
792 uport->iotype = UPIO_MEM;
793 uport->flags = UPF_BOOT_AUTOCONF;
794 uport->ops = &dz_ops;
795 uport->line = line;
796 uport->mapbase = base;
797 }
798}
799
800#ifdef CONFIG_SERIAL_DZ_CONSOLE
801/*
802 * -------------------------------------------------------------------
803 * dz_console_putchar() -- transmit a character
804 *
805 * Polled transmission. This is tricky. We need to mask transmit
806 * interrupts so that they do not interfere, enable the transmitter
807 * for the line requested and then wait till the transmit scanner
808 * requests data for this line. But it may request data for another
809 * line first, in which case we have to disable its transmitter and
810 * repeat waiting till our line pops up. Only then the character may
811 * be transmitted. Finally, the state of the transmitter mask is
812 * restored. Welcome to the world of PDP-11!
813 * -------------------------------------------------------------------
814 */
815static void dz_console_putchar(struct uart_port *uport, int ch)
816{
817 struct dz_port *dport = to_dport(uport);
818 unsigned long flags;
819 unsigned short csr, tcr, trdy, mask;
820 int loops = 10000;
821
822 spin_lock_irqsave(&dport->port.lock, flags);
823 csr = dz_in(dport, DZ_CSR);
824 dz_out(dport, DZ_CSR, csr & ~DZ_TIE);
825 tcr = dz_in(dport, DZ_TCR);
826 tcr |= 1 << dport->port.line;
827 mask = tcr;
828 dz_out(dport, DZ_TCR, mask);
829 iob();
830 spin_unlock_irqrestore(&dport->port.lock, flags);
831
832 do {
833 trdy = dz_in(dport, DZ_CSR);
834 if (!(trdy & DZ_TRDY))
835 continue;
836 trdy = (trdy & DZ_TLINE) >> 8;
837 if (trdy == dport->port.line)
838 break;
839 mask &= ~(1 << trdy);
840 dz_out(dport, DZ_TCR, mask);
841 iob();
842 udelay(2);
843 } while (--loops);
844
845 if (loops) /* Cannot send otherwise. */
846 dz_out(dport, DZ_TDR, ch);
847
848 dz_out(dport, DZ_TCR, tcr);
849 dz_out(dport, DZ_CSR, csr);
850}
851
852/*
853 * -------------------------------------------------------------------
854 * dz_console_print ()
855 *
856 * dz_console_print is registered for printk.
857 * The console must be locked when we get here.
858 * -------------------------------------------------------------------
859 */
860static void dz_console_print(struct console *co,
861 const char *str,
862 unsigned int count)
863{
864 struct dz_port *dport = &dz_mux.dport[co->index];
865#ifdef DEBUG_DZ
866 prom_printf((char *) str);
867#endif
868 uart_console_write(&dport->port, str, count, dz_console_putchar);
869}
870
871static int __init dz_console_setup(struct console *co, char *options)
872{
873 struct dz_port *dport = &dz_mux.dport[co->index];
874 struct uart_port *uport = &dport->port;
875 int baud = 9600;
876 int bits = 8;
877 int parity = 'n';
878 int flow = 'n';
879 int ret;
880
881 ret = dz_map_port(uport);
882 if (ret)
883 return ret;
884
885 spin_lock_init(&dport->port.lock); /* For dz_pm(). */
886
887 dz_reset(dport);
888 dz_pm(uport, 0, -1);
889
890 if (options)
891 uart_parse_options(options, &baud, &parity, &bits, &flow);
892
893 return uart_set_options(&dport->port, co, baud, parity, bits, flow);
894}
895
896static struct uart_driver dz_reg;
897static struct console dz_console = {
898 .name = "ttyS",
899 .write = dz_console_print,
900 .device = uart_console_device,
901 .setup = dz_console_setup,
902 .flags = CON_PRINTBUFFER,
903 .index = -1,
904 .data = &dz_reg,
905};
906
907static int __init dz_serial_console_init(void)
908{
909 if (!IOASIC) {
910 dz_init_ports();
911 register_console(&dz_console);
912 return 0;
913 } else
914 return -ENXIO;
915}
916
917console_initcall(dz_serial_console_init);
918
919#define SERIAL_DZ_CONSOLE &dz_console
920#else
921#define SERIAL_DZ_CONSOLE NULL
922#endif /* CONFIG_SERIAL_DZ_CONSOLE */
923
924static struct uart_driver dz_reg = {
925 .owner = THIS_MODULE,
926 .driver_name = "serial",
927 .dev_name = "ttyS",
928 .major = TTY_MAJOR,
929 .minor = 64,
930 .nr = DZ_NB_PORT,
931 .cons = SERIAL_DZ_CONSOLE,
932};
933
934static int __init dz_init(void)
935{
936 int ret, i;
937
938 if (IOASIC)
939 return -ENXIO;
940
941 printk("%s%s\n", dz_name, dz_version);
942
943 dz_init_ports();
944
945 ret = uart_register_driver(&dz_reg);
946 if (ret)
947 return ret;
948
949 for (i = 0; i < DZ_NB_PORT; i++)
950 uart_add_one_port(&dz_reg, &dz_mux.dport[i].port);
951
952 return 0;
953}
954
955module_init(dz_init);
diff --git a/drivers/serial/dz.h b/drivers/serial/dz.h
deleted file mode 100644
index faf169ed27b3..000000000000
--- a/drivers/serial/dz.h
+++ /dev/null
@@ -1,129 +0,0 @@
1/*
2 * dz.h: Serial port driver for DECstations equipped
3 * with the DZ chipset.
4 *
5 * Copyright (C) 1998 Olivier A. D. Lebaillif
6 *
7 * Email: olivier.lebaillif@ifrsys.com
8 *
9 * Copyright (C) 2004, 2006 Maciej W. Rozycki
10 */
11#ifndef DZ_SERIAL_H
12#define DZ_SERIAL_H
13
14/*
15 * Definitions for the Control and Status Register.
16 */
17#define DZ_TRDY 0x8000 /* Transmitter empty */
18#define DZ_TIE 0x4000 /* Transmitter Interrupt Enbl */
19#define DZ_TLINE 0x0300 /* Transmitter Line Number */
20#define DZ_RDONE 0x0080 /* Receiver data ready */
21#define DZ_RIE 0x0040 /* Receive Interrupt Enable */
22#define DZ_MSE 0x0020 /* Master Scan Enable */
23#define DZ_CLR 0x0010 /* Master reset */
24#define DZ_MAINT 0x0008 /* Loop Back Mode */
25
26/*
27 * Definitions for the Receiver Buffer Register.
28 */
29#define DZ_RBUF_MASK 0x00FF /* Data Mask */
30#define DZ_LINE_MASK 0x0300 /* Line Mask */
31#define DZ_DVAL 0x8000 /* Valid Data indicator */
32#define DZ_OERR 0x4000 /* Overrun error indicator */
33#define DZ_FERR 0x2000 /* Frame error indicator */
34#define DZ_PERR 0x1000 /* Parity error indicator */
35
36#define DZ_BREAK 0x0800 /* BREAK event software flag */
37
38#define LINE(x) ((x & DZ_LINE_MASK) >> 8) /* Get the line number
39 from the input buffer */
40#define UCHAR(x) ((unsigned char)(x & DZ_RBUF_MASK))
41
42/*
43 * Definitions for the Transmit Control Register.
44 */
45#define DZ_LINE_KEYBOARD 0x0001
46#define DZ_LINE_MOUSE 0x0002
47#define DZ_LINE_MODEM 0x0004
48#define DZ_LINE_PRINTER 0x0008
49
50#define DZ_MODEM_RTS 0x0800 /* RTS for the modem line (2) */
51#define DZ_MODEM_DTR 0x0400 /* DTR for the modem line (2) */
52#define DZ_PRINT_RTS 0x0200 /* RTS for the prntr line (3) */
53#define DZ_PRINT_DTR 0x0100 /* DTR for the prntr line (3) */
54#define DZ_LNENB 0x000f /* Transmitter Line Enable */
55
56/*
57 * Definitions for the Modem Status Register.
58 */
59#define DZ_MODEM_RI 0x0800 /* RI for the modem line (2) */
60#define DZ_MODEM_CD 0x0400 /* CD for the modem line (2) */
61#define DZ_MODEM_DSR 0x0200 /* DSR for the modem line (2) */
62#define DZ_MODEM_CTS 0x0100 /* CTS for the modem line (2) */
63#define DZ_PRINT_RI 0x0008 /* RI for the printer line (3) */
64#define DZ_PRINT_CD 0x0004 /* CD for the printer line (3) */
65#define DZ_PRINT_DSR 0x0002 /* DSR for the prntr line (3) */
66#define DZ_PRINT_CTS 0x0001 /* CTS for the prntr line (3) */
67
68/*
69 * Definitions for the Transmit Data Register.
70 */
71#define DZ_BRK0 0x0100 /* Break assertion for line 0 */
72#define DZ_BRK1 0x0200 /* Break assertion for line 1 */
73#define DZ_BRK2 0x0400 /* Break assertion for line 2 */
74#define DZ_BRK3 0x0800 /* Break assertion for line 3 */
75
76/*
77 * Definitions for the Line Parameter Register.
78 */
79#define DZ_KEYBOARD 0x0000 /* line 0 = keyboard */
80#define DZ_MOUSE 0x0001 /* line 1 = mouse */
81#define DZ_MODEM 0x0002 /* line 2 = modem */
82#define DZ_PRINTER 0x0003 /* line 3 = printer */
83
84#define DZ_CSIZE 0x0018 /* Number of bits per byte (mask) */
85#define DZ_CS5 0x0000 /* 5 bits per byte */
86#define DZ_CS6 0x0008 /* 6 bits per byte */
87#define DZ_CS7 0x0010 /* 7 bits per byte */
88#define DZ_CS8 0x0018 /* 8 bits per byte */
89
90#define DZ_CSTOPB 0x0020 /* 2 stop bits instead of one */
91
92#define DZ_PARENB 0x0040 /* Parity enable */
93#define DZ_PARODD 0x0080 /* Odd parity instead of even */
94
95#define DZ_CBAUD 0x0E00 /* Baud Rate (mask) */
96#define DZ_B50 0x0000
97#define DZ_B75 0x0100
98#define DZ_B110 0x0200
99#define DZ_B134 0x0300
100#define DZ_B150 0x0400
101#define DZ_B300 0x0500
102#define DZ_B600 0x0600
103#define DZ_B1200 0x0700
104#define DZ_B1800 0x0800
105#define DZ_B2000 0x0900
106#define DZ_B2400 0x0A00
107#define DZ_B3600 0x0B00
108#define DZ_B4800 0x0C00
109#define DZ_B7200 0x0D00
110#define DZ_B9600 0x0E00
111
112#define DZ_RXENAB 0x1000 /* Receiver Enable */
113
114/*
115 * Addresses for the DZ registers
116 */
117#define DZ_CSR 0x00 /* Control and Status Register */
118#define DZ_RBUF 0x08 /* Receive Buffer */
119#define DZ_LPR 0x08 /* Line Parameters Register */
120#define DZ_TCR 0x10 /* Transmitter Control Register */
121#define DZ_MSR 0x18 /* Modem Status Register */
122#define DZ_TDR 0x18 /* Transmit Data Register */
123
124#define DZ_NB_PORT 4
125
126#define DZ_XMIT_SIZE 4096 /* buffer size */
127#define DZ_WAKEUP_CHARS DZ_XMIT_SIZE/4
128
129#endif /* DZ_SERIAL_H */
diff --git a/drivers/serial/icom.c b/drivers/serial/icom.c
deleted file mode 100644
index 53a468227056..000000000000
--- a/drivers/serial/icom.c
+++ /dev/null
@@ -1,1658 +0,0 @@
1/*
2 * icom.c
3 *
4 * Copyright (C) 2001 IBM Corporation. All rights reserved.
5 *
6 * Serial device driver.
7 *
8 * Based on code from serial.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25#define SERIAL_DO_RESTART
26#include <linux/module.h>
27#include <linux/kernel.h>
28#include <linux/errno.h>
29#include <linux/signal.h>
30#include <linux/timer.h>
31#include <linux/interrupt.h>
32#include <linux/tty.h>
33#include <linux/termios.h>
34#include <linux/fs.h>
35#include <linux/tty_flip.h>
36#include <linux/serial.h>
37#include <linux/serial_reg.h>
38#include <linux/major.h>
39#include <linux/string.h>
40#include <linux/fcntl.h>
41#include <linux/ptrace.h>
42#include <linux/ioport.h>
43#include <linux/mm.h>
44#include <linux/slab.h>
45#include <linux/init.h>
46#include <linux/delay.h>
47#include <linux/pci.h>
48#include <linux/vmalloc.h>
49#include <linux/smp.h>
50#include <linux/spinlock.h>
51#include <linux/kref.h>
52#include <linux/firmware.h>
53#include <linux/bitops.h>
54
55#include <asm/system.h>
56#include <asm/io.h>
57#include <asm/irq.h>
58#include <asm/uaccess.h>
59
60#include "icom.h"
61
62/*#define ICOM_TRACE enable port trace capabilities */
63
64#define ICOM_DRIVER_NAME "icom"
65#define ICOM_VERSION_STR "1.3.1"
66#define NR_PORTS 128
67#define ICOM_PORT ((struct icom_port *)port)
68#define to_icom_adapter(d) container_of(d, struct icom_adapter, kref)
69
70static const struct pci_device_id icom_pci_table[] = {
71 {
72 .vendor = PCI_VENDOR_ID_IBM,
73 .device = PCI_DEVICE_ID_IBM_ICOM_DEV_ID_1,
74 .subvendor = PCI_ANY_ID,
75 .subdevice = PCI_ANY_ID,
76 .driver_data = ADAPTER_V1,
77 },
78 {
79 .vendor = PCI_VENDOR_ID_IBM,
80 .device = PCI_DEVICE_ID_IBM_ICOM_DEV_ID_2,
81 .subvendor = PCI_VENDOR_ID_IBM,
82 .subdevice = PCI_DEVICE_ID_IBM_ICOM_V2_TWO_PORTS_RVX,
83 .driver_data = ADAPTER_V2,
84 },
85 {
86 .vendor = PCI_VENDOR_ID_IBM,
87 .device = PCI_DEVICE_ID_IBM_ICOM_DEV_ID_2,
88 .subvendor = PCI_VENDOR_ID_IBM,
89 .subdevice = PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM,
90 .driver_data = ADAPTER_V2,
91 },
92 {
93 .vendor = PCI_VENDOR_ID_IBM,
94 .device = PCI_DEVICE_ID_IBM_ICOM_DEV_ID_2,
95 .subvendor = PCI_VENDOR_ID_IBM,
96 .subdevice = PCI_DEVICE_ID_IBM_ICOM_FOUR_PORT_MODEL,
97 .driver_data = ADAPTER_V2,
98 },
99 {
100 .vendor = PCI_VENDOR_ID_IBM,
101 .device = PCI_DEVICE_ID_IBM_ICOM_DEV_ID_2,
102 .subvendor = PCI_VENDOR_ID_IBM,
103 .subdevice = PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM_PCIE,
104 .driver_data = ADAPTER_V2,
105 },
106 {}
107};
108
109struct lookup_proc_table start_proc[4] = {
110 {NULL, ICOM_CONTROL_START_A},
111 {NULL, ICOM_CONTROL_START_B},
112 {NULL, ICOM_CONTROL_START_C},
113 {NULL, ICOM_CONTROL_START_D}
114};
115
116
117struct lookup_proc_table stop_proc[4] = {
118 {NULL, ICOM_CONTROL_STOP_A},
119 {NULL, ICOM_CONTROL_STOP_B},
120 {NULL, ICOM_CONTROL_STOP_C},
121 {NULL, ICOM_CONTROL_STOP_D}
122};
123
124struct lookup_int_table int_mask_tbl[4] = {
125 {NULL, ICOM_INT_MASK_PRC_A},
126 {NULL, ICOM_INT_MASK_PRC_B},
127 {NULL, ICOM_INT_MASK_PRC_C},
128 {NULL, ICOM_INT_MASK_PRC_D},
129};
130
131
132MODULE_DEVICE_TABLE(pci, icom_pci_table);
133
134static LIST_HEAD(icom_adapter_head);
135
136/* spinlock for adapter initialization and changing adapter operations */
137static spinlock_t icom_lock;
138
139#ifdef ICOM_TRACE
140static inline void trace(struct icom_port *icom_port, char *trace_pt,
141 unsigned long trace_data)
142{
143 dev_info(&icom_port->adapter->pci_dev->dev, ":%d:%s - %lx\n",
144 icom_port->port, trace_pt, trace_data);
145}
146#else
147static inline void trace(struct icom_port *icom_port, char *trace_pt, unsigned long trace_data) {};
148#endif
149static void icom_kref_release(struct kref *kref);
150
151static void free_port_memory(struct icom_port *icom_port)
152{
153 struct pci_dev *dev = icom_port->adapter->pci_dev;
154
155 trace(icom_port, "RET_PORT_MEM", 0);
156 if (icom_port->recv_buf) {
157 pci_free_consistent(dev, 4096, icom_port->recv_buf,
158 icom_port->recv_buf_pci);
159 icom_port->recv_buf = NULL;
160 }
161 if (icom_port->xmit_buf) {
162 pci_free_consistent(dev, 4096, icom_port->xmit_buf,
163 icom_port->xmit_buf_pci);
164 icom_port->xmit_buf = NULL;
165 }
166 if (icom_port->statStg) {
167 pci_free_consistent(dev, 4096, icom_port->statStg,
168 icom_port->statStg_pci);
169 icom_port->statStg = NULL;
170 }
171
172 if (icom_port->xmitRestart) {
173 pci_free_consistent(dev, 4096, icom_port->xmitRestart,
174 icom_port->xmitRestart_pci);
175 icom_port->xmitRestart = NULL;
176 }
177}
178
179static int __devinit get_port_memory(struct icom_port *icom_port)
180{
181 int index;
182 unsigned long stgAddr;
183 unsigned long startStgAddr;
184 unsigned long offset;
185 struct pci_dev *dev = icom_port->adapter->pci_dev;
186
187 icom_port->xmit_buf =
188 pci_alloc_consistent(dev, 4096, &icom_port->xmit_buf_pci);
189 if (!icom_port->xmit_buf) {
190 dev_err(&dev->dev, "Can not allocate Transmit buffer\n");
191 return -ENOMEM;
192 }
193
194 trace(icom_port, "GET_PORT_MEM",
195 (unsigned long) icom_port->xmit_buf);
196
197 icom_port->recv_buf =
198 pci_alloc_consistent(dev, 4096, &icom_port->recv_buf_pci);
199 if (!icom_port->recv_buf) {
200 dev_err(&dev->dev, "Can not allocate Receive buffer\n");
201 free_port_memory(icom_port);
202 return -ENOMEM;
203 }
204 trace(icom_port, "GET_PORT_MEM",
205 (unsigned long) icom_port->recv_buf);
206
207 icom_port->statStg =
208 pci_alloc_consistent(dev, 4096, &icom_port->statStg_pci);
209 if (!icom_port->statStg) {
210 dev_err(&dev->dev, "Can not allocate Status buffer\n");
211 free_port_memory(icom_port);
212 return -ENOMEM;
213 }
214 trace(icom_port, "GET_PORT_MEM",
215 (unsigned long) icom_port->statStg);
216
217 icom_port->xmitRestart =
218 pci_alloc_consistent(dev, 4096, &icom_port->xmitRestart_pci);
219 if (!icom_port->xmitRestart) {
220 dev_err(&dev->dev,
221 "Can not allocate xmit Restart buffer\n");
222 free_port_memory(icom_port);
223 return -ENOMEM;
224 }
225
226 memset(icom_port->statStg, 0, 4096);
227
228 /* FODs: Frame Out Descriptor Queue, this is a FIFO queue that
229 indicates that frames are to be transmitted
230 */
231
232 stgAddr = (unsigned long) icom_port->statStg;
233 for (index = 0; index < NUM_XBUFFS; index++) {
234 trace(icom_port, "FOD_ADDR", stgAddr);
235 stgAddr = stgAddr + sizeof(icom_port->statStg->xmit[0]);
236 if (index < (NUM_XBUFFS - 1)) {
237 memset(&icom_port->statStg->xmit[index], 0, sizeof(struct xmit_status_area));
238 icom_port->statStg->xmit[index].leLengthASD =
239 (unsigned short int) cpu_to_le16(XMIT_BUFF_SZ);
240 trace(icom_port, "FOD_ADDR", stgAddr);
241 trace(icom_port, "FOD_XBUFF",
242 (unsigned long) icom_port->xmit_buf);
243 icom_port->statStg->xmit[index].leBuffer =
244 cpu_to_le32(icom_port->xmit_buf_pci);
245 } else if (index == (NUM_XBUFFS - 1)) {
246 memset(&icom_port->statStg->xmit[index], 0, sizeof(struct xmit_status_area));
247 icom_port->statStg->xmit[index].leLengthASD =
248 (unsigned short int) cpu_to_le16(XMIT_BUFF_SZ);
249 trace(icom_port, "FOD_XBUFF",
250 (unsigned long) icom_port->xmit_buf);
251 icom_port->statStg->xmit[index].leBuffer =
252 cpu_to_le32(icom_port->xmit_buf_pci);
253 } else {
254 memset(&icom_port->statStg->xmit[index], 0, sizeof(struct xmit_status_area));
255 }
256 }
257 /* FIDs */
258 startStgAddr = stgAddr;
259
260 /* fill in every entry, even if no buffer */
261 for (index = 0; index < NUM_RBUFFS; index++) {
262 trace(icom_port, "FID_ADDR", stgAddr);
263 stgAddr = stgAddr + sizeof(icom_port->statStg->rcv[0]);
264 icom_port->statStg->rcv[index].leLength = 0;
265 icom_port->statStg->rcv[index].WorkingLength =
266 (unsigned short int) cpu_to_le16(RCV_BUFF_SZ);
267 if (index < (NUM_RBUFFS - 1) ) {
268 offset = stgAddr - (unsigned long) icom_port->statStg;
269 icom_port->statStg->rcv[index].leNext =
270 cpu_to_le32(icom_port-> statStg_pci + offset);
271 trace(icom_port, "FID_RBUFF",
272 (unsigned long) icom_port->recv_buf);
273 icom_port->statStg->rcv[index].leBuffer =
274 cpu_to_le32(icom_port->recv_buf_pci);
275 } else if (index == (NUM_RBUFFS -1) ) {
276 offset = startStgAddr - (unsigned long) icom_port->statStg;
277 icom_port->statStg->rcv[index].leNext =
278 cpu_to_le32(icom_port-> statStg_pci + offset);
279 trace(icom_port, "FID_RBUFF",
280 (unsigned long) icom_port->recv_buf + 2048);
281 icom_port->statStg->rcv[index].leBuffer =
282 cpu_to_le32(icom_port->recv_buf_pci + 2048);
283 } else {
284 icom_port->statStg->rcv[index].leNext = 0;
285 icom_port->statStg->rcv[index].leBuffer = 0;
286 }
287 }
288
289 return 0;
290}
291
292static void stop_processor(struct icom_port *icom_port)
293{
294 unsigned long temp;
295 unsigned long flags;
296 int port;
297
298 spin_lock_irqsave(&icom_lock, flags);
299
300 port = icom_port->port;
301 if (port == 0 || port == 1)
302 stop_proc[port].global_control_reg = &icom_port->global_reg->control;
303 else
304 stop_proc[port].global_control_reg = &icom_port->global_reg->control_2;
305
306
307 if (port < 4) {
308 temp = readl(stop_proc[port].global_control_reg);
309 temp =
310 (temp & ~start_proc[port].processor_id) | stop_proc[port].processor_id;
311 writel(temp, stop_proc[port].global_control_reg);
312
313 /* write flush */
314 readl(stop_proc[port].global_control_reg);
315 } else {
316 dev_err(&icom_port->adapter->pci_dev->dev,
317 "Invalid port assignment\n");
318 }
319
320 spin_unlock_irqrestore(&icom_lock, flags);
321}
322
323static void start_processor(struct icom_port *icom_port)
324{
325 unsigned long temp;
326 unsigned long flags;
327 int port;
328
329 spin_lock_irqsave(&icom_lock, flags);
330
331 port = icom_port->port;
332 if (port == 0 || port == 1)
333 start_proc[port].global_control_reg = &icom_port->global_reg->control;
334 else
335 start_proc[port].global_control_reg = &icom_port->global_reg->control_2;
336 if (port < 4) {
337 temp = readl(start_proc[port].global_control_reg);
338 temp =
339 (temp & ~stop_proc[port].processor_id) | start_proc[port].processor_id;
340 writel(temp, start_proc[port].global_control_reg);
341
342 /* write flush */
343 readl(start_proc[port].global_control_reg);
344 } else {
345 dev_err(&icom_port->adapter->pci_dev->dev,
346 "Invalid port assignment\n");
347 }
348
349 spin_unlock_irqrestore(&icom_lock, flags);
350}
351
352static void load_code(struct icom_port *icom_port)
353{
354 const struct firmware *fw;
355 char __iomem *iram_ptr;
356 int index;
357 int status = 0;
358 void __iomem *dram_ptr = icom_port->dram;
359 dma_addr_t temp_pci;
360 unsigned char *new_page = NULL;
361 unsigned char cable_id = NO_CABLE;
362 struct pci_dev *dev = icom_port->adapter->pci_dev;
363
364 /* Clear out any pending interrupts */
365 writew(0x3FFF, icom_port->int_reg);
366
367 trace(icom_port, "CLEAR_INTERRUPTS", 0);
368
369 /* Stop processor */
370 stop_processor(icom_port);
371
372 /* Zero out DRAM */
373 memset_io(dram_ptr, 0, 512);
374
375 /* Load Call Setup into Adapter */
376 if (request_firmware(&fw, "icom_call_setup.bin", &dev->dev) < 0) {
377 dev_err(&dev->dev,"Unable to load icom_call_setup.bin firmware image\n");
378 status = -1;
379 goto load_code_exit;
380 }
381
382 if (fw->size > ICOM_DCE_IRAM_OFFSET) {
383 dev_err(&dev->dev, "Invalid firmware image for icom_call_setup.bin found.\n");
384 release_firmware(fw);
385 status = -1;
386 goto load_code_exit;
387 }
388
389 iram_ptr = (char __iomem *)icom_port->dram + ICOM_IRAM_OFFSET;
390 for (index = 0; index < fw->size; index++)
391 writeb(fw->data[index], &iram_ptr[index]);
392
393 release_firmware(fw);
394
395 /* Load Resident DCE portion of Adapter */
396 if (request_firmware(&fw, "icom_res_dce.bin", &dev->dev) < 0) {
397 dev_err(&dev->dev,"Unable to load icom_res_dce.bin firmware image\n");
398 status = -1;
399 goto load_code_exit;
400 }
401
402 if (fw->size > ICOM_IRAM_SIZE) {
403 dev_err(&dev->dev, "Invalid firmware image for icom_res_dce.bin found.\n");
404 release_firmware(fw);
405 status = -1;
406 goto load_code_exit;
407 }
408
409 iram_ptr = (char __iomem *) icom_port->dram + ICOM_IRAM_OFFSET;
410 for (index = ICOM_DCE_IRAM_OFFSET; index < fw->size; index++)
411 writeb(fw->data[index], &iram_ptr[index]);
412
413 release_firmware(fw);
414
415 /* Set Hardware level */
416 if (icom_port->adapter->version == ADAPTER_V2)
417 writeb(V2_HARDWARE, &(icom_port->dram->misc_flags));
418
419 /* Start the processor in Adapter */
420 start_processor(icom_port);
421
422 writeb((HDLC_PPP_PURE_ASYNC | HDLC_FF_FILL),
423 &(icom_port->dram->HDLCConfigReg));
424 writeb(0x04, &(icom_port->dram->FlagFillIdleTimer)); /* 0.5 seconds */
425 writeb(0x00, &(icom_port->dram->CmdReg));
426 writeb(0x10, &(icom_port->dram->async_config3));
427 writeb((ICOM_ACFG_DRIVE1 | ICOM_ACFG_NO_PARITY | ICOM_ACFG_8BPC |
428 ICOM_ACFG_1STOP_BIT), &(icom_port->dram->async_config2));
429
430 /*Set up data in icom DRAM to indicate where personality
431 *code is located and its length.
432 */
433 new_page = pci_alloc_consistent(dev, 4096, &temp_pci);
434
435 if (!new_page) {
436 dev_err(&dev->dev, "Can not allocate DMA buffer\n");
437 status = -1;
438 goto load_code_exit;
439 }
440
441 if (request_firmware(&fw, "icom_asc.bin", &dev->dev) < 0) {
442 dev_err(&dev->dev,"Unable to load icom_asc.bin firmware image\n");
443 status = -1;
444 goto load_code_exit;
445 }
446
447 if (fw->size > ICOM_DCE_IRAM_OFFSET) {
448 dev_err(&dev->dev, "Invalid firmware image for icom_asc.bin found.\n");
449 release_firmware(fw);
450 status = -1;
451 goto load_code_exit;
452 }
453
454 for (index = 0; index < fw->size; index++)
455 new_page[index] = fw->data[index];
456
457 release_firmware(fw);
458
459 writeb((char) ((fw->size + 16)/16), &icom_port->dram->mac_length);
460 writel(temp_pci, &icom_port->dram->mac_load_addr);
461
462 /*Setting the syncReg to 0x80 causes adapter to start downloading
463 the personality code into adapter instruction RAM.
464 Once code is loaded, it will begin executing and, based on
465 information provided above, will start DMAing data from
466 shared memory to adapter DRAM.
467 */
468 /* the wait loop below verifies this write operation has been done
469 and processed
470 */
471 writeb(START_DOWNLOAD, &icom_port->dram->sync);
472
473 /* Wait max 1 Sec for data download and processor to start */
474 for (index = 0; index < 10; index++) {
475 msleep(100);
476 if (readb(&icom_port->dram->misc_flags) & ICOM_HDW_ACTIVE)
477 break;
478 }
479
480 if (index == 10)
481 status = -1;
482
483 /*
484 * check Cable ID
485 */
486 cable_id = readb(&icom_port->dram->cable_id);
487
488 if (cable_id & ICOM_CABLE_ID_VALID) {
489 /* Get cable ID into the lower 4 bits (standard form) */
490 cable_id = (cable_id & ICOM_CABLE_ID_MASK) >> 4;
491 icom_port->cable_id = cable_id;
492 } else {
493 dev_err(&dev->dev,"Invalid or no cable attached\n");
494 icom_port->cable_id = NO_CABLE;
495 }
496
497 load_code_exit:
498
499 if (status != 0) {
500 /* Clear out any pending interrupts */
501 writew(0x3FFF, icom_port->int_reg);
502
503 /* Turn off port */
504 writeb(ICOM_DISABLE, &(icom_port->dram->disable));
505
506 /* Stop processor */
507 stop_processor(icom_port);
508
509 dev_err(&icom_port->adapter->pci_dev->dev,"Port not opertional\n");
510 }
511
512 if (new_page != NULL)
513 pci_free_consistent(dev, 4096, new_page, temp_pci);
514}
515
516static int startup(struct icom_port *icom_port)
517{
518 unsigned long temp;
519 unsigned char cable_id, raw_cable_id;
520 unsigned long flags;
521 int port;
522
523 trace(icom_port, "STARTUP", 0);
524
525 if (!icom_port->dram) {
526 /* should NEVER be NULL */
527 dev_err(&icom_port->adapter->pci_dev->dev,
528 "Unusable Port, port configuration missing\n");
529 return -ENODEV;
530 }
531
532 /*
533 * check Cable ID
534 */
535 raw_cable_id = readb(&icom_port->dram->cable_id);
536 trace(icom_port, "CABLE_ID", raw_cable_id);
537
538 /* Get cable ID into the lower 4 bits (standard form) */
539 cable_id = (raw_cable_id & ICOM_CABLE_ID_MASK) >> 4;
540
541 /* Check for valid Cable ID */
542 if (!(raw_cable_id & ICOM_CABLE_ID_VALID) ||
543 (cable_id != icom_port->cable_id)) {
544
545 /* reload adapter code, pick up any potential changes in cable id */
546 load_code(icom_port);
547
548 /* still no sign of cable, error out */
549 raw_cable_id = readb(&icom_port->dram->cable_id);
550 cable_id = (raw_cable_id & ICOM_CABLE_ID_MASK) >> 4;
551 if (!(raw_cable_id & ICOM_CABLE_ID_VALID) ||
552 (icom_port->cable_id == NO_CABLE))
553 return -EIO;
554 }
555
556 /*
557 * Finally, clear and enable interrupts
558 */
559 spin_lock_irqsave(&icom_lock, flags);
560 port = icom_port->port;
561 if (port == 0 || port == 1)
562 int_mask_tbl[port].global_int_mask = &icom_port->global_reg->int_mask;
563 else
564 int_mask_tbl[port].global_int_mask = &icom_port->global_reg->int_mask_2;
565
566 if (port == 0 || port == 2)
567 writew(0x00FF, icom_port->int_reg);
568 else
569 writew(0x3F00, icom_port->int_reg);
570 if (port < 4) {
571 temp = readl(int_mask_tbl[port].global_int_mask);
572 writel(temp & ~int_mask_tbl[port].processor_id, int_mask_tbl[port].global_int_mask);
573
574 /* write flush */
575 readl(int_mask_tbl[port].global_int_mask);
576 } else {
577 dev_err(&icom_port->adapter->pci_dev->dev,
578 "Invalid port assignment\n");
579 }
580
581 spin_unlock_irqrestore(&icom_lock, flags);
582 return 0;
583}
584
585static void shutdown(struct icom_port *icom_port)
586{
587 unsigned long temp;
588 unsigned char cmdReg;
589 unsigned long flags;
590 int port;
591
592 spin_lock_irqsave(&icom_lock, flags);
593 trace(icom_port, "SHUTDOWN", 0);
594
595 /*
596 * disable all interrupts
597 */
598 port = icom_port->port;
599 if (port == 0 || port == 1)
600 int_mask_tbl[port].global_int_mask = &icom_port->global_reg->int_mask;
601 else
602 int_mask_tbl[port].global_int_mask = &icom_port->global_reg->int_mask_2;
603
604 if (port < 4) {
605 temp = readl(int_mask_tbl[port].global_int_mask);
606 writel(temp | int_mask_tbl[port].processor_id, int_mask_tbl[port].global_int_mask);
607
608 /* write flush */
609 readl(int_mask_tbl[port].global_int_mask);
610 } else {
611 dev_err(&icom_port->adapter->pci_dev->dev,
612 "Invalid port assignment\n");
613 }
614 spin_unlock_irqrestore(&icom_lock, flags);
615
616 /*
617 * disable break condition
618 */
619 cmdReg = readb(&icom_port->dram->CmdReg);
620 if (cmdReg & CMD_SND_BREAK) {
621 writeb(cmdReg & ~CMD_SND_BREAK, &icom_port->dram->CmdReg);
622 }
623}
624
625static int icom_write(struct uart_port *port)
626{
627 unsigned long data_count;
628 unsigned char cmdReg;
629 unsigned long offset;
630 int temp_tail = port->state->xmit.tail;
631
632 trace(ICOM_PORT, "WRITE", 0);
633
634 if (cpu_to_le16(ICOM_PORT->statStg->xmit[0].flags) &
635 SA_FLAGS_READY_TO_XMIT) {
636 trace(ICOM_PORT, "WRITE_FULL", 0);
637 return 0;
638 }
639
640 data_count = 0;
641 while ((port->state->xmit.head != temp_tail) &&
642 (data_count <= XMIT_BUFF_SZ)) {
643
644 ICOM_PORT->xmit_buf[data_count++] =
645 port->state->xmit.buf[temp_tail];
646
647 temp_tail++;
648 temp_tail &= (UART_XMIT_SIZE - 1);
649 }
650
651 if (data_count) {
652 ICOM_PORT->statStg->xmit[0].flags =
653 cpu_to_le16(SA_FLAGS_READY_TO_XMIT);
654 ICOM_PORT->statStg->xmit[0].leLength =
655 cpu_to_le16(data_count);
656 offset =
657 (unsigned long) &ICOM_PORT->statStg->xmit[0] -
658 (unsigned long) ICOM_PORT->statStg;
659 *ICOM_PORT->xmitRestart =
660 cpu_to_le32(ICOM_PORT->statStg_pci + offset);
661 cmdReg = readb(&ICOM_PORT->dram->CmdReg);
662 writeb(cmdReg | CMD_XMIT_RCV_ENABLE,
663 &ICOM_PORT->dram->CmdReg);
664 writeb(START_XMIT, &ICOM_PORT->dram->StartXmitCmd);
665 trace(ICOM_PORT, "WRITE_START", data_count);
666 /* write flush */
667 readb(&ICOM_PORT->dram->StartXmitCmd);
668 }
669
670 return data_count;
671}
672
673static inline void check_modem_status(struct icom_port *icom_port)
674{
675 static char old_status = 0;
676 char delta_status;
677 unsigned char status;
678
679 spin_lock(&icom_port->uart_port.lock);
680
681 /*modem input register */
682 status = readb(&icom_port->dram->isr);
683 trace(icom_port, "CHECK_MODEM", status);
684 delta_status = status ^ old_status;
685 if (delta_status) {
686 if (delta_status & ICOM_RI)
687 icom_port->uart_port.icount.rng++;
688 if (delta_status & ICOM_DSR)
689 icom_port->uart_port.icount.dsr++;
690 if (delta_status & ICOM_DCD)
691 uart_handle_dcd_change(&icom_port->uart_port,
692 delta_status & ICOM_DCD);
693 if (delta_status & ICOM_CTS)
694 uart_handle_cts_change(&icom_port->uart_port,
695 delta_status & ICOM_CTS);
696
697 wake_up_interruptible(&icom_port->uart_port.state->
698 port.delta_msr_wait);
699 old_status = status;
700 }
701 spin_unlock(&icom_port->uart_port.lock);
702}
703
704static void xmit_interrupt(u16 port_int_reg, struct icom_port *icom_port)
705{
706 unsigned short int count;
707 int i;
708
709 if (port_int_reg & (INT_XMIT_COMPLETED)) {
710 trace(icom_port, "XMIT_COMPLETE", 0);
711
712 /* clear buffer in use bit */
713 icom_port->statStg->xmit[0].flags &=
714 cpu_to_le16(~SA_FLAGS_READY_TO_XMIT);
715
716 count = (unsigned short int)
717 cpu_to_le16(icom_port->statStg->xmit[0].leLength);
718 icom_port->uart_port.icount.tx += count;
719
720 for (i=0; i<count &&
721 !uart_circ_empty(&icom_port->uart_port.state->xmit); i++) {
722
723 icom_port->uart_port.state->xmit.tail++;
724 icom_port->uart_port.state->xmit.tail &=
725 (UART_XMIT_SIZE - 1);
726 }
727
728 if (!icom_write(&icom_port->uart_port))
729 /* activate write queue */
730 uart_write_wakeup(&icom_port->uart_port);
731 } else
732 trace(icom_port, "XMIT_DISABLED", 0);
733}
734
735static void recv_interrupt(u16 port_int_reg, struct icom_port *icom_port)
736{
737 short int count, rcv_buff;
738 struct tty_struct *tty = icom_port->uart_port.state->port.tty;
739 unsigned short int status;
740 struct uart_icount *icount;
741 unsigned long offset;
742 unsigned char flag;
743
744 trace(icom_port, "RCV_COMPLETE", 0);
745 rcv_buff = icom_port->next_rcv;
746
747 status = cpu_to_le16(icom_port->statStg->rcv[rcv_buff].flags);
748 while (status & SA_FL_RCV_DONE) {
749 int first = -1;
750
751 trace(icom_port, "FID_STATUS", status);
752 count = cpu_to_le16(icom_port->statStg->rcv[rcv_buff].leLength);
753
754 trace(icom_port, "RCV_COUNT", count);
755
756 trace(icom_port, "REAL_COUNT", count);
757
758 offset =
759 cpu_to_le32(icom_port->statStg->rcv[rcv_buff].leBuffer) -
760 icom_port->recv_buf_pci;
761
762 /* Block copy all but the last byte as this may have status */
763 if (count > 0) {
764 first = icom_port->recv_buf[offset];
765 tty_insert_flip_string(tty, icom_port->recv_buf + offset, count - 1);
766 }
767
768 icount = &icom_port->uart_port.icount;
769 icount->rx += count;
770
771 /* Break detect logic */
772 if ((status & SA_FLAGS_FRAME_ERROR)
773 && first == 0) {
774 status &= ~SA_FLAGS_FRAME_ERROR;
775 status |= SA_FLAGS_BREAK_DET;
776 trace(icom_port, "BREAK_DET", 0);
777 }
778
779 flag = TTY_NORMAL;
780
781 if (status &
782 (SA_FLAGS_BREAK_DET | SA_FLAGS_PARITY_ERROR |
783 SA_FLAGS_FRAME_ERROR | SA_FLAGS_OVERRUN)) {
784
785 if (status & SA_FLAGS_BREAK_DET)
786 icount->brk++;
787 if (status & SA_FLAGS_PARITY_ERROR)
788 icount->parity++;
789 if (status & SA_FLAGS_FRAME_ERROR)
790 icount->frame++;
791 if (status & SA_FLAGS_OVERRUN)
792 icount->overrun++;
793
794 /*
795 * Now check to see if character should be
796 * ignored, and mask off conditions which
797 * should be ignored.
798 */
799 if (status & icom_port->ignore_status_mask) {
800 trace(icom_port, "IGNORE_CHAR", 0);
801 goto ignore_char;
802 }
803
804 status &= icom_port->read_status_mask;
805
806 if (status & SA_FLAGS_BREAK_DET) {
807 flag = TTY_BREAK;
808 } else if (status & SA_FLAGS_PARITY_ERROR) {
809 trace(icom_port, "PARITY_ERROR", 0);
810 flag = TTY_PARITY;
811 } else if (status & SA_FLAGS_FRAME_ERROR)
812 flag = TTY_FRAME;
813
814 }
815
816 tty_insert_flip_char(tty, *(icom_port->recv_buf + offset + count - 1), flag);
817
818 if (status & SA_FLAGS_OVERRUN)
819 /*
820 * Overrun is special, since it's
821 * reported immediately, and doesn't
822 * affect the current character
823 */
824 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
825ignore_char:
826 icom_port->statStg->rcv[rcv_buff].flags = 0;
827 icom_port->statStg->rcv[rcv_buff].leLength = 0;
828 icom_port->statStg->rcv[rcv_buff].WorkingLength =
829 (unsigned short int) cpu_to_le16(RCV_BUFF_SZ);
830
831 rcv_buff++;
832 if (rcv_buff == NUM_RBUFFS)
833 rcv_buff = 0;
834
835 status = cpu_to_le16(icom_port->statStg->rcv[rcv_buff].flags);
836 }
837 icom_port->next_rcv = rcv_buff;
838 tty_flip_buffer_push(tty);
839}
840
841static void process_interrupt(u16 port_int_reg,
842 struct icom_port *icom_port)
843{
844
845 spin_lock(&icom_port->uart_port.lock);
846 trace(icom_port, "INTERRUPT", port_int_reg);
847
848 if (port_int_reg & (INT_XMIT_COMPLETED | INT_XMIT_DISABLED))
849 xmit_interrupt(port_int_reg, icom_port);
850
851 if (port_int_reg & INT_RCV_COMPLETED)
852 recv_interrupt(port_int_reg, icom_port);
853
854 spin_unlock(&icom_port->uart_port.lock);
855}
856
857static irqreturn_t icom_interrupt(int irq, void *dev_id)
858{
859 void __iomem * int_reg;
860 u32 adapter_interrupts;
861 u16 port_int_reg;
862 struct icom_adapter *icom_adapter;
863 struct icom_port *icom_port;
864
865 /* find icom_port for this interrupt */
866 icom_adapter = (struct icom_adapter *) dev_id;
867
868 if (icom_adapter->version == ADAPTER_V2) {
869 int_reg = icom_adapter->base_addr + 0x8024;
870
871 adapter_interrupts = readl(int_reg);
872
873 if (adapter_interrupts & 0x00003FFF) {
874 /* port 2 interrupt, NOTE: for all ADAPTER_V2, port 2 will be active */
875 icom_port = &icom_adapter->port_info[2];
876 port_int_reg = (u16) adapter_interrupts;
877 process_interrupt(port_int_reg, icom_port);
878 check_modem_status(icom_port);
879 }
880 if (adapter_interrupts & 0x3FFF0000) {
881 /* port 3 interrupt */
882 icom_port = &icom_adapter->port_info[3];
883 if (icom_port->status == ICOM_PORT_ACTIVE) {
884 port_int_reg =
885 (u16) (adapter_interrupts >> 16);
886 process_interrupt(port_int_reg, icom_port);
887 check_modem_status(icom_port);
888 }
889 }
890
891 /* Clear out any pending interrupts */
892 writel(adapter_interrupts, int_reg);
893
894 int_reg = icom_adapter->base_addr + 0x8004;
895 } else {
896 int_reg = icom_adapter->base_addr + 0x4004;
897 }
898
899 adapter_interrupts = readl(int_reg);
900
901 if (adapter_interrupts & 0x00003FFF) {
902 /* port 0 interrupt, NOTE: for all adapters, port 0 will be active */
903 icom_port = &icom_adapter->port_info[0];
904 port_int_reg = (u16) adapter_interrupts;
905 process_interrupt(port_int_reg, icom_port);
906 check_modem_status(icom_port);
907 }
908 if (adapter_interrupts & 0x3FFF0000) {
909 /* port 1 interrupt */
910 icom_port = &icom_adapter->port_info[1];
911 if (icom_port->status == ICOM_PORT_ACTIVE) {
912 port_int_reg = (u16) (adapter_interrupts >> 16);
913 process_interrupt(port_int_reg, icom_port);
914 check_modem_status(icom_port);
915 }
916 }
917
918 /* Clear out any pending interrupts */
919 writel(adapter_interrupts, int_reg);
920
921 /* flush the write */
922 adapter_interrupts = readl(int_reg);
923
924 return IRQ_HANDLED;
925}
926
927/*
928 * ------------------------------------------------------------------
929 * Begin serial-core API
930 * ------------------------------------------------------------------
931 */
932static unsigned int icom_tx_empty(struct uart_port *port)
933{
934 int ret;
935 unsigned long flags;
936
937 spin_lock_irqsave(&port->lock, flags);
938 if (cpu_to_le16(ICOM_PORT->statStg->xmit[0].flags) &
939 SA_FLAGS_READY_TO_XMIT)
940 ret = TIOCSER_TEMT;
941 else
942 ret = 0;
943
944 spin_unlock_irqrestore(&port->lock, flags);
945 return ret;
946}
947
948static void icom_set_mctrl(struct uart_port *port, unsigned int mctrl)
949{
950 unsigned char local_osr;
951
952 trace(ICOM_PORT, "SET_MODEM", 0);
953 local_osr = readb(&ICOM_PORT->dram->osr);
954
955 if (mctrl & TIOCM_RTS) {
956 trace(ICOM_PORT, "RAISE_RTS", 0);
957 local_osr |= ICOM_RTS;
958 } else {
959 trace(ICOM_PORT, "LOWER_RTS", 0);
960 local_osr &= ~ICOM_RTS;
961 }
962
963 if (mctrl & TIOCM_DTR) {
964 trace(ICOM_PORT, "RAISE_DTR", 0);
965 local_osr |= ICOM_DTR;
966 } else {
967 trace(ICOM_PORT, "LOWER_DTR", 0);
968 local_osr &= ~ICOM_DTR;
969 }
970
971 writeb(local_osr, &ICOM_PORT->dram->osr);
972}
973
974static unsigned int icom_get_mctrl(struct uart_port *port)
975{
976 unsigned char status;
977 unsigned int result;
978
979 trace(ICOM_PORT, "GET_MODEM", 0);
980
981 status = readb(&ICOM_PORT->dram->isr);
982
983 result = ((status & ICOM_DCD) ? TIOCM_CAR : 0)
984 | ((status & ICOM_RI) ? TIOCM_RNG : 0)
985 | ((status & ICOM_DSR) ? TIOCM_DSR : 0)
986 | ((status & ICOM_CTS) ? TIOCM_CTS : 0);
987 return result;
988}
989
990static void icom_stop_tx(struct uart_port *port)
991{
992 unsigned char cmdReg;
993
994 trace(ICOM_PORT, "STOP", 0);
995 cmdReg = readb(&ICOM_PORT->dram->CmdReg);
996 writeb(cmdReg | CMD_HOLD_XMIT, &ICOM_PORT->dram->CmdReg);
997}
998
999static void icom_start_tx(struct uart_port *port)
1000{
1001 unsigned char cmdReg;
1002
1003 trace(ICOM_PORT, "START", 0);
1004 cmdReg = readb(&ICOM_PORT->dram->CmdReg);
1005 if ((cmdReg & CMD_HOLD_XMIT) == CMD_HOLD_XMIT)
1006 writeb(cmdReg & ~CMD_HOLD_XMIT,
1007 &ICOM_PORT->dram->CmdReg);
1008
1009 icom_write(port);
1010}
1011
1012static void icom_send_xchar(struct uart_port *port, char ch)
1013{
1014 unsigned char xdata;
1015 int index;
1016 unsigned long flags;
1017
1018 trace(ICOM_PORT, "SEND_XCHAR", ch);
1019
1020 /* wait .1 sec to send char */
1021 for (index = 0; index < 10; index++) {
1022 spin_lock_irqsave(&port->lock, flags);
1023 xdata = readb(&ICOM_PORT->dram->xchar);
1024 if (xdata == 0x00) {
1025 trace(ICOM_PORT, "QUICK_WRITE", 0);
1026 writeb(ch, &ICOM_PORT->dram->xchar);
1027
1028 /* flush write operation */
1029 xdata = readb(&ICOM_PORT->dram->xchar);
1030 spin_unlock_irqrestore(&port->lock, flags);
1031 break;
1032 }
1033 spin_unlock_irqrestore(&port->lock, flags);
1034 msleep(10);
1035 }
1036}
1037
1038static void icom_stop_rx(struct uart_port *port)
1039{
1040 unsigned char cmdReg;
1041
1042 cmdReg = readb(&ICOM_PORT->dram->CmdReg);
1043 writeb(cmdReg & ~CMD_RCV_ENABLE, &ICOM_PORT->dram->CmdReg);
1044}
1045
1046static void icom_enable_ms(struct uart_port *port)
1047{
1048 /* no-op */
1049}
1050
1051static void icom_break(struct uart_port *port, int break_state)
1052{
1053 unsigned char cmdReg;
1054 unsigned long flags;
1055
1056 spin_lock_irqsave(&port->lock, flags);
1057 trace(ICOM_PORT, "BREAK", 0);
1058 cmdReg = readb(&ICOM_PORT->dram->CmdReg);
1059 if (break_state == -1) {
1060 writeb(cmdReg | CMD_SND_BREAK, &ICOM_PORT->dram->CmdReg);
1061 } else {
1062 writeb(cmdReg & ~CMD_SND_BREAK, &ICOM_PORT->dram->CmdReg);
1063 }
1064 spin_unlock_irqrestore(&port->lock, flags);
1065}
1066
1067static int icom_open(struct uart_port *port)
1068{
1069 int retval;
1070
1071 kref_get(&ICOM_PORT->adapter->kref);
1072 retval = startup(ICOM_PORT);
1073
1074 if (retval) {
1075 kref_put(&ICOM_PORT->adapter->kref, icom_kref_release);
1076 trace(ICOM_PORT, "STARTUP_ERROR", 0);
1077 return retval;
1078 }
1079
1080 return 0;
1081}
1082
1083static void icom_close(struct uart_port *port)
1084{
1085 unsigned char cmdReg;
1086
1087 trace(ICOM_PORT, "CLOSE", 0);
1088
1089 /* stop receiver */
1090 cmdReg = readb(&ICOM_PORT->dram->CmdReg);
1091 writeb(cmdReg & (unsigned char) ~CMD_RCV_ENABLE,
1092 &ICOM_PORT->dram->CmdReg);
1093
1094 shutdown(ICOM_PORT);
1095
1096 kref_put(&ICOM_PORT->adapter->kref, icom_kref_release);
1097}
1098
1099static void icom_set_termios(struct uart_port *port,
1100 struct ktermios *termios,
1101 struct ktermios *old_termios)
1102{
1103 int baud;
1104 unsigned cflag, iflag;
1105 char new_config2;
1106 char new_config3 = 0;
1107 char tmp_byte;
1108 int index;
1109 int rcv_buff, xmit_buff;
1110 unsigned long offset;
1111 unsigned long flags;
1112
1113 spin_lock_irqsave(&port->lock, flags);
1114 trace(ICOM_PORT, "CHANGE_SPEED", 0);
1115
1116 cflag = termios->c_cflag;
1117 iflag = termios->c_iflag;
1118
1119 new_config2 = ICOM_ACFG_DRIVE1;
1120
1121 /* byte size and parity */
1122 switch (cflag & CSIZE) {
1123 case CS5: /* 5 bits/char */
1124 new_config2 |= ICOM_ACFG_5BPC;
1125 break;
1126 case CS6: /* 6 bits/char */
1127 new_config2 |= ICOM_ACFG_6BPC;
1128 break;
1129 case CS7: /* 7 bits/char */
1130 new_config2 |= ICOM_ACFG_7BPC;
1131 break;
1132 case CS8: /* 8 bits/char */
1133 new_config2 |= ICOM_ACFG_8BPC;
1134 break;
1135 default:
1136 break;
1137 }
1138 if (cflag & CSTOPB) {
1139 /* 2 stop bits */
1140 new_config2 |= ICOM_ACFG_2STOP_BIT;
1141 }
1142 if (cflag & PARENB) {
1143 /* parity bit enabled */
1144 new_config2 |= ICOM_ACFG_PARITY_ENAB;
1145 trace(ICOM_PORT, "PARENB", 0);
1146 }
1147 if (cflag & PARODD) {
1148 /* odd parity */
1149 new_config2 |= ICOM_ACFG_PARITY_ODD;
1150 trace(ICOM_PORT, "PARODD", 0);
1151 }
1152
1153 /* Determine divisor based on baud rate */
1154 baud = uart_get_baud_rate(port, termios, old_termios,
1155 icom_acfg_baud[0],
1156 icom_acfg_baud[BAUD_TABLE_LIMIT]);
1157 if (!baud)
1158 baud = 9600; /* B0 transition handled in rs_set_termios */
1159
1160 for (index = 0; index < BAUD_TABLE_LIMIT; index++) {
1161 if (icom_acfg_baud[index] == baud) {
1162 new_config3 = index;
1163 break;
1164 }
1165 }
1166
1167 uart_update_timeout(port, cflag, baud);
1168
1169 /* CTS flow control flag and modem status interrupts */
1170 tmp_byte = readb(&(ICOM_PORT->dram->HDLCConfigReg));
1171 if (cflag & CRTSCTS)
1172 tmp_byte |= HDLC_HDW_FLOW;
1173 else
1174 tmp_byte &= ~HDLC_HDW_FLOW;
1175 writeb(tmp_byte, &(ICOM_PORT->dram->HDLCConfigReg));
1176
1177 /*
1178 * Set up parity check flag
1179 */
1180 ICOM_PORT->read_status_mask = SA_FLAGS_OVERRUN | SA_FL_RCV_DONE;
1181 if (iflag & INPCK)
1182 ICOM_PORT->read_status_mask |=
1183 SA_FLAGS_FRAME_ERROR | SA_FLAGS_PARITY_ERROR;
1184
1185 if ((iflag & BRKINT) || (iflag & PARMRK))
1186 ICOM_PORT->read_status_mask |= SA_FLAGS_BREAK_DET;
1187
1188 /*
1189 * Characters to ignore
1190 */
1191 ICOM_PORT->ignore_status_mask = 0;
1192 if (iflag & IGNPAR)
1193 ICOM_PORT->ignore_status_mask |=
1194 SA_FLAGS_PARITY_ERROR | SA_FLAGS_FRAME_ERROR;
1195 if (iflag & IGNBRK) {
1196 ICOM_PORT->ignore_status_mask |= SA_FLAGS_BREAK_DET;
1197 /*
1198 * If we're ignore parity and break indicators, ignore
1199 * overruns too. (For real raw support).
1200 */
1201 if (iflag & IGNPAR)
1202 ICOM_PORT->ignore_status_mask |= SA_FLAGS_OVERRUN;
1203 }
1204
1205 /*
1206 * !!! ignore all characters if CREAD is not set
1207 */
1208 if ((cflag & CREAD) == 0)
1209 ICOM_PORT->ignore_status_mask |= SA_FL_RCV_DONE;
1210
1211 /* Turn off Receiver to prepare for reset */
1212 writeb(CMD_RCV_DISABLE, &ICOM_PORT->dram->CmdReg);
1213
1214 for (index = 0; index < 10; index++) {
1215 if (readb(&ICOM_PORT->dram->PrevCmdReg) == 0x00) {
1216 break;
1217 }
1218 }
1219
1220 /* clear all current buffers of data */
1221 for (rcv_buff = 0; rcv_buff < NUM_RBUFFS; rcv_buff++) {
1222 ICOM_PORT->statStg->rcv[rcv_buff].flags = 0;
1223 ICOM_PORT->statStg->rcv[rcv_buff].leLength = 0;
1224 ICOM_PORT->statStg->rcv[rcv_buff].WorkingLength =
1225 (unsigned short int) cpu_to_le16(RCV_BUFF_SZ);
1226 }
1227
1228 for (xmit_buff = 0; xmit_buff < NUM_XBUFFS; xmit_buff++) {
1229 ICOM_PORT->statStg->xmit[xmit_buff].flags = 0;
1230 }
1231
1232 /* activate changes and start xmit and receiver here */
1233 /* Enable the receiver */
1234 writeb(new_config3, &(ICOM_PORT->dram->async_config3));
1235 writeb(new_config2, &(ICOM_PORT->dram->async_config2));
1236 tmp_byte = readb(&(ICOM_PORT->dram->HDLCConfigReg));
1237 tmp_byte |= HDLC_PPP_PURE_ASYNC | HDLC_FF_FILL;
1238 writeb(tmp_byte, &(ICOM_PORT->dram->HDLCConfigReg));
1239 writeb(0x04, &(ICOM_PORT->dram->FlagFillIdleTimer)); /* 0.5 seconds */
1240 writeb(0xFF, &(ICOM_PORT->dram->ier)); /* enable modem signal interrupts */
1241
1242 /* reset processor */
1243 writeb(CMD_RESTART, &ICOM_PORT->dram->CmdReg);
1244
1245 for (index = 0; index < 10; index++) {
1246 if (readb(&ICOM_PORT->dram->CmdReg) == 0x00) {
1247 break;
1248 }
1249 }
1250
1251 /* Enable Transmitter and Reciever */
1252 offset =
1253 (unsigned long) &ICOM_PORT->statStg->rcv[0] -
1254 (unsigned long) ICOM_PORT->statStg;
1255 writel(ICOM_PORT->statStg_pci + offset,
1256 &ICOM_PORT->dram->RcvStatusAddr);
1257 ICOM_PORT->next_rcv = 0;
1258 ICOM_PORT->put_length = 0;
1259 *ICOM_PORT->xmitRestart = 0;
1260 writel(ICOM_PORT->xmitRestart_pci,
1261 &ICOM_PORT->dram->XmitStatusAddr);
1262 trace(ICOM_PORT, "XR_ENAB", 0);
1263 writeb(CMD_XMIT_RCV_ENABLE, &ICOM_PORT->dram->CmdReg);
1264
1265 spin_unlock_irqrestore(&port->lock, flags);
1266}
1267
1268static const char *icom_type(struct uart_port *port)
1269{
1270 return "icom";
1271}
1272
1273static void icom_release_port(struct uart_port *port)
1274{
1275}
1276
1277static int icom_request_port(struct uart_port *port)
1278{
1279 return 0;
1280}
1281
1282static void icom_config_port(struct uart_port *port, int flags)
1283{
1284 port->type = PORT_ICOM;
1285}
1286
1287static struct uart_ops icom_ops = {
1288 .tx_empty = icom_tx_empty,
1289 .set_mctrl = icom_set_mctrl,
1290 .get_mctrl = icom_get_mctrl,
1291 .stop_tx = icom_stop_tx,
1292 .start_tx = icom_start_tx,
1293 .send_xchar = icom_send_xchar,
1294 .stop_rx = icom_stop_rx,
1295 .enable_ms = icom_enable_ms,
1296 .break_ctl = icom_break,
1297 .startup = icom_open,
1298 .shutdown = icom_close,
1299 .set_termios = icom_set_termios,
1300 .type = icom_type,
1301 .release_port = icom_release_port,
1302 .request_port = icom_request_port,
1303 .config_port = icom_config_port,
1304};
1305
1306#define ICOM_CONSOLE NULL
1307
1308static struct uart_driver icom_uart_driver = {
1309 .owner = THIS_MODULE,
1310 .driver_name = ICOM_DRIVER_NAME,
1311 .dev_name = "ttyA",
1312 .major = ICOM_MAJOR,
1313 .minor = ICOM_MINOR_START,
1314 .nr = NR_PORTS,
1315 .cons = ICOM_CONSOLE,
1316};
1317
1318static int __devinit icom_init_ports(struct icom_adapter *icom_adapter)
1319{
1320 u32 subsystem_id = icom_adapter->subsystem_id;
1321 int i;
1322 struct icom_port *icom_port;
1323
1324 if (icom_adapter->version == ADAPTER_V1) {
1325 icom_adapter->numb_ports = 2;
1326
1327 for (i = 0; i < 2; i++) {
1328 icom_port = &icom_adapter->port_info[i];
1329 icom_port->port = i;
1330 icom_port->status = ICOM_PORT_ACTIVE;
1331 icom_port->imbed_modem = ICOM_UNKNOWN;
1332 }
1333 } else {
1334 if (subsystem_id == PCI_DEVICE_ID_IBM_ICOM_FOUR_PORT_MODEL) {
1335 icom_adapter->numb_ports = 4;
1336
1337 for (i = 0; i < 4; i++) {
1338 icom_port = &icom_adapter->port_info[i];
1339
1340 icom_port->port = i;
1341 icom_port->status = ICOM_PORT_ACTIVE;
1342 icom_port->imbed_modem = ICOM_IMBED_MODEM;
1343 }
1344 } else {
1345 icom_adapter->numb_ports = 4;
1346
1347 icom_adapter->port_info[0].port = 0;
1348 icom_adapter->port_info[0].status = ICOM_PORT_ACTIVE;
1349
1350 if (subsystem_id ==
1351 PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM) {
1352 icom_adapter->port_info[0].imbed_modem = ICOM_IMBED_MODEM;
1353 } else {
1354 icom_adapter->port_info[0].imbed_modem = ICOM_RVX;
1355 }
1356
1357 icom_adapter->port_info[1].status = ICOM_PORT_OFF;
1358
1359 icom_adapter->port_info[2].port = 2;
1360 icom_adapter->port_info[2].status = ICOM_PORT_ACTIVE;
1361 icom_adapter->port_info[2].imbed_modem = ICOM_RVX;
1362 icom_adapter->port_info[3].status = ICOM_PORT_OFF;
1363 }
1364 }
1365
1366 return 0;
1367}
1368
1369static void icom_port_active(struct icom_port *icom_port, struct icom_adapter *icom_adapter, int port_num)
1370{
1371 if (icom_adapter->version == ADAPTER_V1) {
1372 icom_port->global_reg = icom_adapter->base_addr + 0x4000;
1373 icom_port->int_reg = icom_adapter->base_addr +
1374 0x4004 + 2 - 2 * port_num;
1375 } else {
1376 icom_port->global_reg = icom_adapter->base_addr + 0x8000;
1377 if (icom_port->port < 2)
1378 icom_port->int_reg = icom_adapter->base_addr +
1379 0x8004 + 2 - 2 * icom_port->port;
1380 else
1381 icom_port->int_reg = icom_adapter->base_addr +
1382 0x8024 + 2 - 2 * (icom_port->port - 2);
1383 }
1384}
1385static int __devinit icom_load_ports(struct icom_adapter *icom_adapter)
1386{
1387 struct icom_port *icom_port;
1388 int port_num;
1389
1390 for (port_num = 0; port_num < icom_adapter->numb_ports; port_num++) {
1391
1392 icom_port = &icom_adapter->port_info[port_num];
1393
1394 if (icom_port->status == ICOM_PORT_ACTIVE) {
1395 icom_port_active(icom_port, icom_adapter, port_num);
1396 icom_port->dram = icom_adapter->base_addr +
1397 0x2000 * icom_port->port;
1398
1399 icom_port->adapter = icom_adapter;
1400
1401 /* get port memory */
1402 if (get_port_memory(icom_port) != 0) {
1403 dev_err(&icom_port->adapter->pci_dev->dev,
1404 "Memory allocation for port FAILED\n");
1405 }
1406 }
1407 }
1408 return 0;
1409}
1410
1411static int __devinit icom_alloc_adapter(struct icom_adapter
1412 **icom_adapter_ref)
1413{
1414 int adapter_count = 0;
1415 struct icom_adapter *icom_adapter;
1416 struct icom_adapter *cur_adapter_entry;
1417 struct list_head *tmp;
1418
1419 icom_adapter = (struct icom_adapter *)
1420 kzalloc(sizeof(struct icom_adapter), GFP_KERNEL);
1421
1422 if (!icom_adapter) {
1423 return -ENOMEM;
1424 }
1425
1426 list_for_each(tmp, &icom_adapter_head) {
1427 cur_adapter_entry =
1428 list_entry(tmp, struct icom_adapter,
1429 icom_adapter_entry);
1430 if (cur_adapter_entry->index != adapter_count) {
1431 break;
1432 }
1433 adapter_count++;
1434 }
1435
1436 icom_adapter->index = adapter_count;
1437 list_add_tail(&icom_adapter->icom_adapter_entry, tmp);
1438
1439 *icom_adapter_ref = icom_adapter;
1440 return 0;
1441}
1442
1443static void icom_free_adapter(struct icom_adapter *icom_adapter)
1444{
1445 list_del(&icom_adapter->icom_adapter_entry);
1446 kfree(icom_adapter);
1447}
1448
1449static void icom_remove_adapter(struct icom_adapter *icom_adapter)
1450{
1451 struct icom_port *icom_port;
1452 int index;
1453
1454 for (index = 0; index < icom_adapter->numb_ports; index++) {
1455 icom_port = &icom_adapter->port_info[index];
1456
1457 if (icom_port->status == ICOM_PORT_ACTIVE) {
1458 dev_info(&icom_adapter->pci_dev->dev,
1459 "Device removed\n");
1460
1461 uart_remove_one_port(&icom_uart_driver,
1462 &icom_port->uart_port);
1463
1464 /* be sure that DTR and RTS are dropped */
1465 writeb(0x00, &icom_port->dram->osr);
1466
1467 /* Wait 0.1 Sec for simple Init to complete */
1468 msleep(100);
1469
1470 /* Stop proccessor */
1471 stop_processor(icom_port);
1472
1473 free_port_memory(icom_port);
1474 }
1475 }
1476
1477 free_irq(icom_adapter->pci_dev->irq, (void *) icom_adapter);
1478 iounmap(icom_adapter->base_addr);
1479 pci_release_regions(icom_adapter->pci_dev);
1480 icom_free_adapter(icom_adapter);
1481}
1482
1483static void icom_kref_release(struct kref *kref)
1484{
1485 struct icom_adapter *icom_adapter;
1486
1487 icom_adapter = to_icom_adapter(kref);
1488 icom_remove_adapter(icom_adapter);
1489}
1490
1491static int __devinit icom_probe(struct pci_dev *dev,
1492 const struct pci_device_id *ent)
1493{
1494 int index;
1495 unsigned int command_reg;
1496 int retval;
1497 struct icom_adapter *icom_adapter;
1498 struct icom_port *icom_port;
1499
1500 retval = pci_enable_device(dev);
1501 if (retval) {
1502 dev_err(&dev->dev, "Device enable FAILED\n");
1503 return retval;
1504 }
1505
1506 if ( (retval = pci_request_regions(dev, "icom"))) {
1507 dev_err(&dev->dev, "pci_request_regions FAILED\n");
1508 pci_disable_device(dev);
1509 return retval;
1510 }
1511
1512 pci_set_master(dev);
1513
1514 if ( (retval = pci_read_config_dword(dev, PCI_COMMAND, &command_reg))) {
1515 dev_err(&dev->dev, "PCI Config read FAILED\n");
1516 return retval;
1517 }
1518
1519 pci_write_config_dword(dev, PCI_COMMAND,
1520 command_reg | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
1521 | PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1522
1523 if (ent->driver_data == ADAPTER_V1) {
1524 pci_write_config_dword(dev, 0x44, 0x8300830A);
1525 } else {
1526 pci_write_config_dword(dev, 0x44, 0x42004200);
1527 pci_write_config_dword(dev, 0x48, 0x42004200);
1528 }
1529
1530
1531 retval = icom_alloc_adapter(&icom_adapter);
1532 if (retval) {
1533 dev_err(&dev->dev, "icom_alloc_adapter FAILED\n");
1534 retval = -EIO;
1535 goto probe_exit0;
1536 }
1537
1538 icom_adapter->base_addr_pci = pci_resource_start(dev, 0);
1539 icom_adapter->pci_dev = dev;
1540 icom_adapter->version = ent->driver_data;
1541 icom_adapter->subsystem_id = ent->subdevice;
1542
1543
1544 retval = icom_init_ports(icom_adapter);
1545 if (retval) {
1546 dev_err(&dev->dev, "Port configuration failed\n");
1547 goto probe_exit1;
1548 }
1549
1550 icom_adapter->base_addr = pci_ioremap_bar(dev, 0);
1551
1552 if (!icom_adapter->base_addr)
1553 goto probe_exit1;
1554
1555 /* save off irq and request irq line */
1556 if ( (retval = request_irq(dev->irq, icom_interrupt,
1557 IRQF_DISABLED | IRQF_SHARED, ICOM_DRIVER_NAME,
1558 (void *) icom_adapter))) {
1559 goto probe_exit2;
1560 }
1561
1562 retval = icom_load_ports(icom_adapter);
1563
1564 for (index = 0; index < icom_adapter->numb_ports; index++) {
1565 icom_port = &icom_adapter->port_info[index];
1566
1567 if (icom_port->status == ICOM_PORT_ACTIVE) {
1568 icom_port->uart_port.irq = icom_port->adapter->pci_dev->irq;
1569 icom_port->uart_port.type = PORT_ICOM;
1570 icom_port->uart_port.iotype = UPIO_MEM;
1571 icom_port->uart_port.membase =
1572 (char *) icom_adapter->base_addr_pci;
1573 icom_port->uart_port.fifosize = 16;
1574 icom_port->uart_port.ops = &icom_ops;
1575 icom_port->uart_port.line =
1576 icom_port->port + icom_adapter->index * 4;
1577 if (uart_add_one_port (&icom_uart_driver, &icom_port->uart_port)) {
1578 icom_port->status = ICOM_PORT_OFF;
1579 dev_err(&dev->dev, "Device add failed\n");
1580 } else
1581 dev_info(&dev->dev, "Device added\n");
1582 }
1583 }
1584
1585 kref_init(&icom_adapter->kref);
1586 return 0;
1587
1588probe_exit2:
1589 iounmap(icom_adapter->base_addr);
1590probe_exit1:
1591 icom_free_adapter(icom_adapter);
1592
1593probe_exit0:
1594 pci_release_regions(dev);
1595 pci_disable_device(dev);
1596
1597 return retval;
1598}
1599
1600static void __devexit icom_remove(struct pci_dev *dev)
1601{
1602 struct icom_adapter *icom_adapter;
1603 struct list_head *tmp;
1604
1605 list_for_each(tmp, &icom_adapter_head) {
1606 icom_adapter = list_entry(tmp, struct icom_adapter,
1607 icom_adapter_entry);
1608 if (icom_adapter->pci_dev == dev) {
1609 kref_put(&icom_adapter->kref, icom_kref_release);
1610 return;
1611 }
1612 }
1613
1614 dev_err(&dev->dev, "Unable to find device to remove\n");
1615}
1616
1617static struct pci_driver icom_pci_driver = {
1618 .name = ICOM_DRIVER_NAME,
1619 .id_table = icom_pci_table,
1620 .probe = icom_probe,
1621 .remove = __devexit_p(icom_remove),
1622};
1623
1624static int __init icom_init(void)
1625{
1626 int ret;
1627
1628 spin_lock_init(&icom_lock);
1629
1630 ret = uart_register_driver(&icom_uart_driver);
1631 if (ret)
1632 return ret;
1633
1634 ret = pci_register_driver(&icom_pci_driver);
1635
1636 if (ret < 0)
1637 uart_unregister_driver(&icom_uart_driver);
1638
1639 return ret;
1640}
1641
1642static void __exit icom_exit(void)
1643{
1644 pci_unregister_driver(&icom_pci_driver);
1645 uart_unregister_driver(&icom_uart_driver);
1646}
1647
1648module_init(icom_init);
1649module_exit(icom_exit);
1650
1651MODULE_AUTHOR("Michael Anderson <mjanders@us.ibm.com>");
1652MODULE_DESCRIPTION("IBM iSeries Serial IOA driver");
1653MODULE_SUPPORTED_DEVICE
1654 ("IBM iSeries 2745, 2771, 2772, 2742, 2793 and 2805 Communications adapters");
1655MODULE_LICENSE("GPL");
1656MODULE_FIRMWARE("icom_call_setup.bin");
1657MODULE_FIRMWARE("icom_res_dce.bin");
1658MODULE_FIRMWARE("icom_asc.bin");
diff --git a/drivers/serial/icom.h b/drivers/serial/icom.h
deleted file mode 100644
index c8029e0025c9..000000000000
--- a/drivers/serial/icom.h
+++ /dev/null
@@ -1,287 +0,0 @@
1/*
2 * icom.h
3 *
4 * Copyright (C) 2001 Michael Anderson, IBM Corporation
5 *
6 * Serial device driver include file.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/serial_core.h>
24
25#define BAUD_TABLE_LIMIT ((sizeof(icom_acfg_baud)/sizeof(int)) - 1)
26static int icom_acfg_baud[] = {
27 300,
28 600,
29 900,
30 1200,
31 1800,
32 2400,
33 3600,
34 4800,
35 7200,
36 9600,
37 14400,
38 19200,
39 28800,
40 38400,
41 57600,
42 76800,
43 115200,
44 153600,
45 230400,
46 307200,
47 460800,
48};
49
50struct icom_regs {
51 u32 control; /* Adapter Control Register */
52 u32 interrupt; /* Adapter Interrupt Register */
53 u32 int_mask; /* Adapter Interrupt Mask Reg */
54 u32 int_pri; /* Adapter Interrupt Priority r */
55 u32 int_reg_b; /* Adapter non-masked Interrupt */
56 u32 resvd01;
57 u32 resvd02;
58 u32 resvd03;
59 u32 control_2; /* Adapter Control Register 2 */
60 u32 interrupt_2; /* Adapter Interrupt Register 2 */
61 u32 int_mask_2; /* Adapter Interrupt Mask 2 */
62 u32 int_pri_2; /* Adapter Interrupt Prior 2 */
63 u32 int_reg_2b; /* Adapter non-masked 2 */
64};
65
66struct func_dram {
67 u32 reserved[108]; /* 0-1B0 reserved by personality code */
68 u32 RcvStatusAddr; /* 1B0-1B3 Status Address for Next rcv */
69 u8 RcvStnAddr; /* 1B4 Receive Station Addr */
70 u8 IdleState; /* 1B5 Idle State */
71 u8 IdleMonitor; /* 1B6 Idle Monitor */
72 u8 FlagFillIdleTimer; /* 1B7 Flag Fill Idle Timer */
73 u32 XmitStatusAddr; /* 1B8-1BB Transmit Status Address */
74 u8 StartXmitCmd; /* 1BC Start Xmit Command */
75 u8 HDLCConfigReg; /* 1BD Reserved */
76 u8 CauseCode; /* 1BE Cause code for fatal error */
77 u8 xchar; /* 1BF High priority send */
78 u32 reserved3; /* 1C0-1C3 Reserved */
79 u8 PrevCmdReg; /* 1C4 Reserved */
80 u8 CmdReg; /* 1C5 Command Register */
81 u8 async_config2; /* 1C6 Async Config Byte 2 */
82 u8 async_config3; /* 1C7 Async Config Byte 3 */
83 u8 dce_resvd[20]; /* 1C8-1DB DCE Rsvd */
84 u8 dce_resvd21; /* 1DC DCE Rsvd (21st byte */
85 u8 misc_flags; /* 1DD misc flags */
86#define V2_HARDWARE 0x40
87#define ICOM_HDW_ACTIVE 0x01
88 u8 call_length; /* 1DE Phone #/CFI buff ln */
89 u8 call_length2; /* 1DF Upper byte (unused) */
90 u32 call_addr; /* 1E0-1E3 Phn #/CFI buff addr */
91 u16 timer_value; /* 1E4-1E5 general timer value */
92 u8 timer_command; /* 1E6 general timer cmd */
93 u8 dce_command; /* 1E7 dce command reg */
94 u8 dce_cmd_status; /* 1E8 dce command stat */
95 u8 x21_r1_ioff; /* 1E9 dce ready counter */
96 u8 x21_r0_ioff; /* 1EA dce not ready ctr */
97 u8 x21_ralt_ioff; /* 1EB dce CNR counter */
98 u8 x21_r1_ion; /* 1EC dce ready I on ctr */
99 u8 rsvd_ier; /* 1ED Rsvd for IER (if ne */
100 u8 ier; /* 1EE Interrupt Enable */
101 u8 isr; /* 1EF Input Signal Reg */
102 u8 osr; /* 1F0 Output Signal Reg */
103 u8 reset; /* 1F1 Reset/Reload Reg */
104 u8 disable; /* 1F2 Disable Reg */
105 u8 sync; /* 1F3 Sync Reg */
106 u8 error_stat; /* 1F4 Error Status */
107 u8 cable_id; /* 1F5 Cable ID */
108 u8 cs_length; /* 1F6 CS Load Length */
109 u8 mac_length; /* 1F7 Mac Load Length */
110 u32 cs_load_addr; /* 1F8-1FB Call Load PCI Addr */
111 u32 mac_load_addr; /* 1FC-1FF Mac Load PCI Addr */
112};
113
114/*
115 * adapter defines and structures
116 */
117#define ICOM_CONTROL_START_A 0x00000008
118#define ICOM_CONTROL_STOP_A 0x00000004
119#define ICOM_CONTROL_START_B 0x00000002
120#define ICOM_CONTROL_STOP_B 0x00000001
121#define ICOM_CONTROL_START_C 0x00000008
122#define ICOM_CONTROL_STOP_C 0x00000004
123#define ICOM_CONTROL_START_D 0x00000002
124#define ICOM_CONTROL_STOP_D 0x00000001
125#define ICOM_IRAM_OFFSET 0x1000
126#define ICOM_IRAM_SIZE 0x0C00
127#define ICOM_DCE_IRAM_OFFSET 0x0A00
128#define ICOM_CABLE_ID_VALID 0x01
129#define ICOM_CABLE_ID_MASK 0xF0
130#define ICOM_DISABLE 0x80
131#define CMD_XMIT_RCV_ENABLE 0xC0
132#define CMD_XMIT_ENABLE 0x40
133#define CMD_RCV_DISABLE 0x00
134#define CMD_RCV_ENABLE 0x80
135#define CMD_RESTART 0x01
136#define CMD_HOLD_XMIT 0x02
137#define CMD_SND_BREAK 0x04
138#define RS232_CABLE 0x06
139#define V24_CABLE 0x0E
140#define V35_CABLE 0x0C
141#define V36_CABLE 0x02
142#define NO_CABLE 0x00
143#define START_DOWNLOAD 0x80
144#define ICOM_INT_MASK_PRC_A 0x00003FFF
145#define ICOM_INT_MASK_PRC_B 0x3FFF0000
146#define ICOM_INT_MASK_PRC_C 0x00003FFF
147#define ICOM_INT_MASK_PRC_D 0x3FFF0000
148#define INT_RCV_COMPLETED 0x1000
149#define INT_XMIT_COMPLETED 0x2000
150#define INT_IDLE_DETECT 0x0800
151#define INT_RCV_DISABLED 0x0400
152#define INT_XMIT_DISABLED 0x0200
153#define INT_RCV_XMIT_SHUTDOWN 0x0100
154#define INT_FATAL_ERROR 0x0080
155#define INT_CABLE_PULL 0x0020
156#define INT_SIGNAL_CHANGE 0x0010
157#define HDLC_PPP_PURE_ASYNC 0x02
158#define HDLC_FF_FILL 0x00
159#define HDLC_HDW_FLOW 0x01
160#define START_XMIT 0x80
161#define ICOM_ACFG_DRIVE1 0x20
162#define ICOM_ACFG_NO_PARITY 0x00
163#define ICOM_ACFG_PARITY_ENAB 0x02
164#define ICOM_ACFG_PARITY_ODD 0x01
165#define ICOM_ACFG_8BPC 0x00
166#define ICOM_ACFG_7BPC 0x04
167#define ICOM_ACFG_6BPC 0x08
168#define ICOM_ACFG_5BPC 0x0C
169#define ICOM_ACFG_1STOP_BIT 0x00
170#define ICOM_ACFG_2STOP_BIT 0x10
171#define ICOM_DTR 0x80
172#define ICOM_RTS 0x40
173#define ICOM_RI 0x08
174#define ICOM_DSR 0x80
175#define ICOM_DCD 0x20
176#define ICOM_CTS 0x40
177
178#define NUM_XBUFFS 1
179#define NUM_RBUFFS 2
180#define RCV_BUFF_SZ 0x0200
181#define XMIT_BUFF_SZ 0x1000
182struct statusArea {
183 /**********************************************/
184 /* Transmit Status Area */
185 /**********************************************/
186 struct xmit_status_area{
187 u32 leNext; /* Next entry in Little Endian on Adapter */
188 u32 leNextASD;
189 u32 leBuffer; /* Buffer for entry in LE for Adapter */
190 u16 leLengthASD;
191 u16 leOffsetASD;
192 u16 leLength; /* Length of data in segment */
193 u16 flags;
194#define SA_FLAGS_DONE 0x0080 /* Done with Segment */
195#define SA_FLAGS_CONTINUED 0x8000 /* More Segments */
196#define SA_FLAGS_IDLE 0x4000 /* Mark IDLE after frm */
197#define SA_FLAGS_READY_TO_XMIT 0x0800
198#define SA_FLAGS_STAT_MASK 0x007F
199 } xmit[NUM_XBUFFS];
200
201 /**********************************************/
202 /* Receive Status Area */
203 /**********************************************/
204 struct {
205 u32 leNext; /* Next entry in Little Endian on Adapter */
206 u32 leNextASD;
207 u32 leBuffer; /* Buffer for entry in LE for Adapter */
208 u16 WorkingLength; /* size of segment */
209 u16 reserv01;
210 u16 leLength; /* Length of data in segment */
211 u16 flags;
212#define SA_FL_RCV_DONE 0x0010 /* Data ready */
213#define SA_FLAGS_OVERRUN 0x0040
214#define SA_FLAGS_PARITY_ERROR 0x0080
215#define SA_FLAGS_FRAME_ERROR 0x0001
216#define SA_FLAGS_FRAME_TRUNC 0x0002
217#define SA_FLAGS_BREAK_DET 0x0004 /* set conditionally by device driver, not hardware */
218#define SA_FLAGS_RCV_MASK 0xFFE6
219 } rcv[NUM_RBUFFS];
220};
221
222struct icom_adapter;
223
224
225#define ICOM_MAJOR 243
226#define ICOM_MINOR_START 0
227
228struct icom_port {
229 struct uart_port uart_port;
230 u8 imbed_modem;
231#define ICOM_UNKNOWN 1
232#define ICOM_RVX 2
233#define ICOM_IMBED_MODEM 3
234 unsigned char cable_id;
235 unsigned char read_status_mask;
236 unsigned char ignore_status_mask;
237 void __iomem * int_reg;
238 struct icom_regs __iomem *global_reg;
239 struct func_dram __iomem *dram;
240 int port;
241 struct statusArea *statStg;
242 dma_addr_t statStg_pci;
243 u32 *xmitRestart;
244 dma_addr_t xmitRestart_pci;
245 unsigned char *xmit_buf;
246 dma_addr_t xmit_buf_pci;
247 unsigned char *recv_buf;
248 dma_addr_t recv_buf_pci;
249 int next_rcv;
250 int put_length;
251 int status;
252#define ICOM_PORT_ACTIVE 1 /* Port exists. */
253#define ICOM_PORT_OFF 0 /* Port does not exist. */
254 int load_in_progress;
255 struct icom_adapter *adapter;
256};
257
258struct icom_adapter {
259 void __iomem * base_addr;
260 unsigned long base_addr_pci;
261 struct pci_dev *pci_dev;
262 struct icom_port port_info[4];
263 int index;
264 int version;
265#define ADAPTER_V1 0x0001
266#define ADAPTER_V2 0x0002
267 u32 subsystem_id;
268#define FOUR_PORT_MODEL 0x0252
269#define V2_TWO_PORTS_RVX 0x021A
270#define V2_ONE_PORT_RVX_ONE_PORT_IMBED_MDM 0x0251
271 int numb_ports;
272 struct list_head icom_adapter_entry;
273 struct kref kref;
274};
275
276/* prototype */
277extern void iCom_sercons_init(void);
278
279struct lookup_proc_table {
280 u32 __iomem *global_control_reg;
281 unsigned long processor_id;
282};
283
284struct lookup_int_table {
285 u32 __iomem *global_int_mask;
286 unsigned long processor_id;
287};
diff --git a/drivers/serial/imx.c b/drivers/serial/imx.c
deleted file mode 100644
index 66ecc7ab6dab..000000000000
--- a/drivers/serial/imx.c
+++ /dev/null
@@ -1,1381 +0,0 @@
1/*
2 * linux/drivers/serial/imx.c
3 *
4 * Driver for Motorola IMX serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Author: Sascha Hauer <sascha@saschahauer.de>
9 * Copyright (C) 2004 Pengutronix
10 *
11 * Copyright (C) 2009 emlix GmbH
12 * Author: Fabian Godehardt (added IrDA support for iMX)
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 *
28 * [29-Mar-2005] Mike Lee
29 * Added hardware handshake
30 */
31
32#if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
33#define SUPPORT_SYSRQ
34#endif
35
36#include <linux/module.h>
37#include <linux/ioport.h>
38#include <linux/init.h>
39#include <linux/console.h>
40#include <linux/sysrq.h>
41#include <linux/platform_device.h>
42#include <linux/tty.h>
43#include <linux/tty_flip.h>
44#include <linux/serial_core.h>
45#include <linux/serial.h>
46#include <linux/clk.h>
47#include <linux/delay.h>
48#include <linux/rational.h>
49#include <linux/slab.h>
50
51#include <asm/io.h>
52#include <asm/irq.h>
53#include <mach/hardware.h>
54#include <mach/imx-uart.h>
55
56/* Register definitions */
57#define URXD0 0x0 /* Receiver Register */
58#define URTX0 0x40 /* Transmitter Register */
59#define UCR1 0x80 /* Control Register 1 */
60#define UCR2 0x84 /* Control Register 2 */
61#define UCR3 0x88 /* Control Register 3 */
62#define UCR4 0x8c /* Control Register 4 */
63#define UFCR 0x90 /* FIFO Control Register */
64#define USR1 0x94 /* Status Register 1 */
65#define USR2 0x98 /* Status Register 2 */
66#define UESC 0x9c /* Escape Character Register */
67#define UTIM 0xa0 /* Escape Timer Register */
68#define UBIR 0xa4 /* BRM Incremental Register */
69#define UBMR 0xa8 /* BRM Modulator Register */
70#define UBRC 0xac /* Baud Rate Count Register */
71#define MX2_ONEMS 0xb0 /* One Millisecond register */
72#define UTS (cpu_is_mx1() ? 0xd0 : 0xb4) /* UART Test Register */
73
74/* UART Control Register Bit Fields.*/
75#define URXD_CHARRDY (1<<15)
76#define URXD_ERR (1<<14)
77#define URXD_OVRRUN (1<<13)
78#define URXD_FRMERR (1<<12)
79#define URXD_BRK (1<<11)
80#define URXD_PRERR (1<<10)
81#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
82#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
83#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
84#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
85#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
86#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
87#define UCR1_IREN (1<<7) /* Infrared interface enable */
88#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
89#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
90#define UCR1_SNDBRK (1<<4) /* Send break */
91#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
92#define MX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, mx1 only */
93#define UCR1_DOZE (1<<1) /* Doze */
94#define UCR1_UARTEN (1<<0) /* UART enabled */
95#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
96#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
97#define UCR2_CTSC (1<<13) /* CTS pin control */
98#define UCR2_CTS (1<<12) /* Clear to send */
99#define UCR2_ESCEN (1<<11) /* Escape enable */
100#define UCR2_PREN (1<<8) /* Parity enable */
101#define UCR2_PROE (1<<7) /* Parity odd/even */
102#define UCR2_STPB (1<<6) /* Stop */
103#define UCR2_WS (1<<5) /* Word size */
104#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
105#define UCR2_TXEN (1<<2) /* Transmitter enabled */
106#define UCR2_RXEN (1<<1) /* Receiver enabled */
107#define UCR2_SRST (1<<0) /* SW reset */
108#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
109#define UCR3_PARERREN (1<<12) /* Parity enable */
110#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
111#define UCR3_DSR (1<<10) /* Data set ready */
112#define UCR3_DCD (1<<9) /* Data carrier detect */
113#define UCR3_RI (1<<8) /* Ring indicator */
114#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
115#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
116#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
117#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
118#define MX1_UCR3_REF25 (1<<3) /* Ref freq 25 MHz, only on mx1 */
119#define MX1_UCR3_REF30 (1<<2) /* Ref Freq 30 MHz, only on mx1 */
120#define MX2_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select, on mx2/mx3 */
121#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
122#define UCR3_BPEN (1<<0) /* Preset registers enable */
123#define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
124#define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
125#define UCR4_INVR (1<<9) /* Inverted infrared reception */
126#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
127#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
128#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
129#define UCR4_IRSC (1<<5) /* IR special case */
130#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
131#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
132#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
133#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
134#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
135#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
136#define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
137#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
138#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
139#define USR1_RTSS (1<<14) /* RTS pin status */
140#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
141#define USR1_RTSD (1<<12) /* RTS delta */
142#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
143#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
144#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
145#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
146#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
147#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
148#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
149#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
150#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
151#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
152#define USR2_IDLE (1<<12) /* Idle condition */
153#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
154#define USR2_WAKE (1<<7) /* Wake */
155#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
156#define USR2_TXDC (1<<3) /* Transmitter complete */
157#define USR2_BRCD (1<<2) /* Break condition */
158#define USR2_ORE (1<<1) /* Overrun error */
159#define USR2_RDR (1<<0) /* Recv data ready */
160#define UTS_FRCPERR (1<<13) /* Force parity error */
161#define UTS_LOOP (1<<12) /* Loop tx and rx */
162#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
163#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
164#define UTS_TXFULL (1<<4) /* TxFIFO full */
165#define UTS_RXFULL (1<<3) /* RxFIFO full */
166#define UTS_SOFTRST (1<<0) /* Software reset */
167
168/* We've been assigned a range on the "Low-density serial ports" major */
169#define SERIAL_IMX_MAJOR 207
170#define MINOR_START 16
171#define DEV_NAME "ttymxc"
172#define MAX_INTERNAL_IRQ MXC_INTERNAL_IRQS
173
174/*
175 * This determines how often we check the modem status signals
176 * for any change. They generally aren't connected to an IRQ
177 * so we have to poll them. We also check immediately before
178 * filling the TX fifo incase CTS has been dropped.
179 */
180#define MCTRL_TIMEOUT (250*HZ/1000)
181
182#define DRIVER_NAME "IMX-uart"
183
184#define UART_NR 8
185
186struct imx_port {
187 struct uart_port port;
188 struct timer_list timer;
189 unsigned int old_status;
190 int txirq,rxirq,rtsirq;
191 unsigned int have_rtscts:1;
192 unsigned int use_irda:1;
193 unsigned int irda_inv_rx:1;
194 unsigned int irda_inv_tx:1;
195 unsigned short trcv_delay; /* transceiver delay */
196 struct clk *clk;
197};
198
199#ifdef CONFIG_IRDA
200#define USE_IRDA(sport) ((sport)->use_irda)
201#else
202#define USE_IRDA(sport) (0)
203#endif
204
205/*
206 * Handle any change of modem status signal since we were last called.
207 */
208static void imx_mctrl_check(struct imx_port *sport)
209{
210 unsigned int status, changed;
211
212 status = sport->port.ops->get_mctrl(&sport->port);
213 changed = status ^ sport->old_status;
214
215 if (changed == 0)
216 return;
217
218 sport->old_status = status;
219
220 if (changed & TIOCM_RI)
221 sport->port.icount.rng++;
222 if (changed & TIOCM_DSR)
223 sport->port.icount.dsr++;
224 if (changed & TIOCM_CAR)
225 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
226 if (changed & TIOCM_CTS)
227 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
228
229 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
230}
231
232/*
233 * This is our per-port timeout handler, for checking the
234 * modem status signals.
235 */
236static void imx_timeout(unsigned long data)
237{
238 struct imx_port *sport = (struct imx_port *)data;
239 unsigned long flags;
240
241 if (sport->port.state) {
242 spin_lock_irqsave(&sport->port.lock, flags);
243 imx_mctrl_check(sport);
244 spin_unlock_irqrestore(&sport->port.lock, flags);
245
246 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
247 }
248}
249
250/*
251 * interrupts disabled on entry
252 */
253static void imx_stop_tx(struct uart_port *port)
254{
255 struct imx_port *sport = (struct imx_port *)port;
256 unsigned long temp;
257
258 if (USE_IRDA(sport)) {
259 /* half duplex - wait for end of transmission */
260 int n = 256;
261 while ((--n > 0) &&
262 !(readl(sport->port.membase + USR2) & USR2_TXDC)) {
263 udelay(5);
264 barrier();
265 }
266 /*
267 * irda transceiver - wait a bit more to avoid
268 * cutoff, hardware dependent
269 */
270 udelay(sport->trcv_delay);
271
272 /*
273 * half duplex - reactivate receive mode,
274 * flush receive pipe echo crap
275 */
276 if (readl(sport->port.membase + USR2) & USR2_TXDC) {
277 temp = readl(sport->port.membase + UCR1);
278 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN);
279 writel(temp, sport->port.membase + UCR1);
280
281 temp = readl(sport->port.membase + UCR4);
282 temp &= ~(UCR4_TCEN);
283 writel(temp, sport->port.membase + UCR4);
284
285 while (readl(sport->port.membase + URXD0) &
286 URXD_CHARRDY)
287 barrier();
288
289 temp = readl(sport->port.membase + UCR1);
290 temp |= UCR1_RRDYEN;
291 writel(temp, sport->port.membase + UCR1);
292
293 temp = readl(sport->port.membase + UCR4);
294 temp |= UCR4_DREN;
295 writel(temp, sport->port.membase + UCR4);
296 }
297 return;
298 }
299
300 temp = readl(sport->port.membase + UCR1);
301 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
302}
303
304/*
305 * interrupts disabled on entry
306 */
307static void imx_stop_rx(struct uart_port *port)
308{
309 struct imx_port *sport = (struct imx_port *)port;
310 unsigned long temp;
311
312 temp = readl(sport->port.membase + UCR2);
313 writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2);
314}
315
316/*
317 * Set the modem control timer to fire immediately.
318 */
319static void imx_enable_ms(struct uart_port *port)
320{
321 struct imx_port *sport = (struct imx_port *)port;
322
323 mod_timer(&sport->timer, jiffies);
324}
325
326static inline void imx_transmit_buffer(struct imx_port *sport)
327{
328 struct circ_buf *xmit = &sport->port.state->xmit;
329
330 while (!(readl(sport->port.membase + UTS) & UTS_TXFULL)) {
331 /* send xmit->buf[xmit->tail]
332 * out the port here */
333 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
334 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
335 sport->port.icount.tx++;
336 if (uart_circ_empty(xmit))
337 break;
338 }
339
340 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
341 uart_write_wakeup(&sport->port);
342
343 if (uart_circ_empty(xmit))
344 imx_stop_tx(&sport->port);
345}
346
347/*
348 * interrupts disabled on entry
349 */
350static void imx_start_tx(struct uart_port *port)
351{
352 struct imx_port *sport = (struct imx_port *)port;
353 unsigned long temp;
354
355 if (USE_IRDA(sport)) {
356 /* half duplex in IrDA mode; have to disable receive mode */
357 temp = readl(sport->port.membase + UCR4);
358 temp &= ~(UCR4_DREN);
359 writel(temp, sport->port.membase + UCR4);
360
361 temp = readl(sport->port.membase + UCR1);
362 temp &= ~(UCR1_RRDYEN);
363 writel(temp, sport->port.membase + UCR1);
364 }
365
366 temp = readl(sport->port.membase + UCR1);
367 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
368
369 if (USE_IRDA(sport)) {
370 temp = readl(sport->port.membase + UCR1);
371 temp |= UCR1_TRDYEN;
372 writel(temp, sport->port.membase + UCR1);
373
374 temp = readl(sport->port.membase + UCR4);
375 temp |= UCR4_TCEN;
376 writel(temp, sport->port.membase + UCR4);
377 }
378
379 if (readl(sport->port.membase + UTS) & UTS_TXEMPTY)
380 imx_transmit_buffer(sport);
381}
382
383static irqreturn_t imx_rtsint(int irq, void *dev_id)
384{
385 struct imx_port *sport = dev_id;
386 unsigned int val = readl(sport->port.membase + USR1) & USR1_RTSS;
387 unsigned long flags;
388
389 spin_lock_irqsave(&sport->port.lock, flags);
390
391 writel(USR1_RTSD, sport->port.membase + USR1);
392 uart_handle_cts_change(&sport->port, !!val);
393 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
394
395 spin_unlock_irqrestore(&sport->port.lock, flags);
396 return IRQ_HANDLED;
397}
398
399static irqreturn_t imx_txint(int irq, void *dev_id)
400{
401 struct imx_port *sport = dev_id;
402 struct circ_buf *xmit = &sport->port.state->xmit;
403 unsigned long flags;
404
405 spin_lock_irqsave(&sport->port.lock,flags);
406 if (sport->port.x_char)
407 {
408 /* Send next char */
409 writel(sport->port.x_char, sport->port.membase + URTX0);
410 goto out;
411 }
412
413 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
414 imx_stop_tx(&sport->port);
415 goto out;
416 }
417
418 imx_transmit_buffer(sport);
419
420 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
421 uart_write_wakeup(&sport->port);
422
423out:
424 spin_unlock_irqrestore(&sport->port.lock,flags);
425 return IRQ_HANDLED;
426}
427
428static irqreturn_t imx_rxint(int irq, void *dev_id)
429{
430 struct imx_port *sport = dev_id;
431 unsigned int rx,flg,ignored = 0;
432 struct tty_struct *tty = sport->port.state->port.tty;
433 unsigned long flags, temp;
434
435 spin_lock_irqsave(&sport->port.lock,flags);
436
437 while (readl(sport->port.membase + USR2) & USR2_RDR) {
438 flg = TTY_NORMAL;
439 sport->port.icount.rx++;
440
441 rx = readl(sport->port.membase + URXD0);
442
443 temp = readl(sport->port.membase + USR2);
444 if (temp & USR2_BRCD) {
445 writel(USR2_BRCD, sport->port.membase + USR2);
446 if (uart_handle_break(&sport->port))
447 continue;
448 }
449
450 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
451 continue;
452
453 if (rx & (URXD_PRERR | URXD_OVRRUN | URXD_FRMERR) ) {
454 if (rx & URXD_PRERR)
455 sport->port.icount.parity++;
456 else if (rx & URXD_FRMERR)
457 sport->port.icount.frame++;
458 if (rx & URXD_OVRRUN)
459 sport->port.icount.overrun++;
460
461 if (rx & sport->port.ignore_status_mask) {
462 if (++ignored > 100)
463 goto out;
464 continue;
465 }
466
467 rx &= sport->port.read_status_mask;
468
469 if (rx & URXD_PRERR)
470 flg = TTY_PARITY;
471 else if (rx & URXD_FRMERR)
472 flg = TTY_FRAME;
473 if (rx & URXD_OVRRUN)
474 flg = TTY_OVERRUN;
475
476#ifdef SUPPORT_SYSRQ
477 sport->port.sysrq = 0;
478#endif
479 }
480
481 tty_insert_flip_char(tty, rx, flg);
482 }
483
484out:
485 spin_unlock_irqrestore(&sport->port.lock,flags);
486 tty_flip_buffer_push(tty);
487 return IRQ_HANDLED;
488}
489
490static irqreturn_t imx_int(int irq, void *dev_id)
491{
492 struct imx_port *sport = dev_id;
493 unsigned int sts;
494
495 sts = readl(sport->port.membase + USR1);
496
497 if (sts & USR1_RRDY)
498 imx_rxint(irq, dev_id);
499
500 if (sts & USR1_TRDY &&
501 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
502 imx_txint(irq, dev_id);
503
504 if (sts & USR1_RTSD)
505 imx_rtsint(irq, dev_id);
506
507 return IRQ_HANDLED;
508}
509
510/*
511 * Return TIOCSER_TEMT when transmitter is not busy.
512 */
513static unsigned int imx_tx_empty(struct uart_port *port)
514{
515 struct imx_port *sport = (struct imx_port *)port;
516
517 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
518}
519
520/*
521 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
522 */
523static unsigned int imx_get_mctrl(struct uart_port *port)
524{
525 struct imx_port *sport = (struct imx_port *)port;
526 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
527
528 if (readl(sport->port.membase + USR1) & USR1_RTSS)
529 tmp |= TIOCM_CTS;
530
531 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
532 tmp |= TIOCM_RTS;
533
534 return tmp;
535}
536
537static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
538{
539 struct imx_port *sport = (struct imx_port *)port;
540 unsigned long temp;
541
542 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
543
544 if (mctrl & TIOCM_RTS)
545 temp |= UCR2_CTS;
546
547 writel(temp, sport->port.membase + UCR2);
548}
549
550/*
551 * Interrupts always disabled.
552 */
553static void imx_break_ctl(struct uart_port *port, int break_state)
554{
555 struct imx_port *sport = (struct imx_port *)port;
556 unsigned long flags, temp;
557
558 spin_lock_irqsave(&sport->port.lock, flags);
559
560 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
561
562 if ( break_state != 0 )
563 temp |= UCR1_SNDBRK;
564
565 writel(temp, sport->port.membase + UCR1);
566
567 spin_unlock_irqrestore(&sport->port.lock, flags);
568}
569
570#define TXTL 2 /* reset default */
571#define RXTL 1 /* reset default */
572
573static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
574{
575 unsigned int val;
576 unsigned int ufcr_rfdiv;
577
578 /* set receiver / transmitter trigger level.
579 * RFDIV is set such way to satisfy requested uartclk value
580 */
581 val = TXTL << 10 | RXTL;
582 ufcr_rfdiv = (clk_get_rate(sport->clk) + sport->port.uartclk / 2)
583 / sport->port.uartclk;
584
585 if(!ufcr_rfdiv)
586 ufcr_rfdiv = 1;
587
588 val |= UFCR_RFDIV_REG(ufcr_rfdiv);
589
590 writel(val, sport->port.membase + UFCR);
591
592 return 0;
593}
594
595/* half the RX buffer size */
596#define CTSTL 16
597
598static int imx_startup(struct uart_port *port)
599{
600 struct imx_port *sport = (struct imx_port *)port;
601 int retval;
602 unsigned long flags, temp;
603
604 imx_setup_ufcr(sport, 0);
605
606 /* disable the DREN bit (Data Ready interrupt enable) before
607 * requesting IRQs
608 */
609 temp = readl(sport->port.membase + UCR4);
610
611 if (USE_IRDA(sport))
612 temp |= UCR4_IRSC;
613
614 /* set the trigger level for CTS */
615 temp &= ~(UCR4_CTSTL_MASK<< UCR4_CTSTL_SHF);
616 temp |= CTSTL<< UCR4_CTSTL_SHF;
617
618 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
619
620 if (USE_IRDA(sport)) {
621 /* reset fifo's and state machines */
622 int i = 100;
623 temp = readl(sport->port.membase + UCR2);
624 temp &= ~UCR2_SRST;
625 writel(temp, sport->port.membase + UCR2);
626 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) &&
627 (--i > 0)) {
628 udelay(1);
629 }
630 }
631
632 /*
633 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
634 * chips only have one interrupt.
635 */
636 if (sport->txirq > 0) {
637 retval = request_irq(sport->rxirq, imx_rxint, 0,
638 DRIVER_NAME, sport);
639 if (retval)
640 goto error_out1;
641
642 retval = request_irq(sport->txirq, imx_txint, 0,
643 DRIVER_NAME, sport);
644 if (retval)
645 goto error_out2;
646
647 /* do not use RTS IRQ on IrDA */
648 if (!USE_IRDA(sport)) {
649 retval = request_irq(sport->rtsirq, imx_rtsint,
650 (sport->rtsirq < MAX_INTERNAL_IRQ) ? 0 :
651 IRQF_TRIGGER_FALLING |
652 IRQF_TRIGGER_RISING,
653 DRIVER_NAME, sport);
654 if (retval)
655 goto error_out3;
656 }
657 } else {
658 retval = request_irq(sport->port.irq, imx_int, 0,
659 DRIVER_NAME, sport);
660 if (retval) {
661 free_irq(sport->port.irq, sport);
662 goto error_out1;
663 }
664 }
665
666 /*
667 * Finally, clear and enable interrupts
668 */
669 writel(USR1_RTSD, sport->port.membase + USR1);
670
671 temp = readl(sport->port.membase + UCR1);
672 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
673
674 if (USE_IRDA(sport)) {
675 temp |= UCR1_IREN;
676 temp &= ~(UCR1_RTSDEN);
677 }
678
679 writel(temp, sport->port.membase + UCR1);
680
681 temp = readl(sport->port.membase + UCR2);
682 temp |= (UCR2_RXEN | UCR2_TXEN);
683 writel(temp, sport->port.membase + UCR2);
684
685 if (USE_IRDA(sport)) {
686 /* clear RX-FIFO */
687 int i = 64;
688 while ((--i > 0) &&
689 (readl(sport->port.membase + URXD0) & URXD_CHARRDY)) {
690 barrier();
691 }
692 }
693
694 if (!cpu_is_mx1()) {
695 temp = readl(sport->port.membase + UCR3);
696 temp |= MX2_UCR3_RXDMUXSEL;
697 writel(temp, sport->port.membase + UCR3);
698 }
699
700 if (USE_IRDA(sport)) {
701 temp = readl(sport->port.membase + UCR4);
702 if (sport->irda_inv_rx)
703 temp |= UCR4_INVR;
704 else
705 temp &= ~(UCR4_INVR);
706 writel(temp | UCR4_DREN, sport->port.membase + UCR4);
707
708 temp = readl(sport->port.membase + UCR3);
709 if (sport->irda_inv_tx)
710 temp |= UCR3_INVT;
711 else
712 temp &= ~(UCR3_INVT);
713 writel(temp, sport->port.membase + UCR3);
714 }
715
716 /*
717 * Enable modem status interrupts
718 */
719 spin_lock_irqsave(&sport->port.lock,flags);
720 imx_enable_ms(&sport->port);
721 spin_unlock_irqrestore(&sport->port.lock,flags);
722
723 if (USE_IRDA(sport)) {
724 struct imxuart_platform_data *pdata;
725 pdata = sport->port.dev->platform_data;
726 sport->irda_inv_rx = pdata->irda_inv_rx;
727 sport->irda_inv_tx = pdata->irda_inv_tx;
728 sport->trcv_delay = pdata->transceiver_delay;
729 if (pdata->irda_enable)
730 pdata->irda_enable(1);
731 }
732
733 return 0;
734
735error_out3:
736 if (sport->txirq)
737 free_irq(sport->txirq, sport);
738error_out2:
739 if (sport->rxirq)
740 free_irq(sport->rxirq, sport);
741error_out1:
742 return retval;
743}
744
745static void imx_shutdown(struct uart_port *port)
746{
747 struct imx_port *sport = (struct imx_port *)port;
748 unsigned long temp;
749
750 temp = readl(sport->port.membase + UCR2);
751 temp &= ~(UCR2_TXEN);
752 writel(temp, sport->port.membase + UCR2);
753
754 if (USE_IRDA(sport)) {
755 struct imxuart_platform_data *pdata;
756 pdata = sport->port.dev->platform_data;
757 if (pdata->irda_enable)
758 pdata->irda_enable(0);
759 }
760
761 /*
762 * Stop our timer.
763 */
764 del_timer_sync(&sport->timer);
765
766 /*
767 * Free the interrupts
768 */
769 if (sport->txirq > 0) {
770 if (!USE_IRDA(sport))
771 free_irq(sport->rtsirq, sport);
772 free_irq(sport->txirq, sport);
773 free_irq(sport->rxirq, sport);
774 } else
775 free_irq(sport->port.irq, sport);
776
777 /*
778 * Disable all interrupts, port and break condition.
779 */
780
781 temp = readl(sport->port.membase + UCR1);
782 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
783 if (USE_IRDA(sport))
784 temp &= ~(UCR1_IREN);
785
786 writel(temp, sport->port.membase + UCR1);
787}
788
789static void
790imx_set_termios(struct uart_port *port, struct ktermios *termios,
791 struct ktermios *old)
792{
793 struct imx_port *sport = (struct imx_port *)port;
794 unsigned long flags;
795 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
796 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
797 unsigned int div, ufcr;
798 unsigned long num, denom;
799 uint64_t tdiv64;
800
801 /*
802 * If we don't support modem control lines, don't allow
803 * these to be set.
804 */
805 if (0) {
806 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
807 termios->c_cflag |= CLOCAL;
808 }
809
810 /*
811 * We only support CS7 and CS8.
812 */
813 while ((termios->c_cflag & CSIZE) != CS7 &&
814 (termios->c_cflag & CSIZE) != CS8) {
815 termios->c_cflag &= ~CSIZE;
816 termios->c_cflag |= old_csize;
817 old_csize = CS8;
818 }
819
820 if ((termios->c_cflag & CSIZE) == CS8)
821 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
822 else
823 ucr2 = UCR2_SRST | UCR2_IRTS;
824
825 if (termios->c_cflag & CRTSCTS) {
826 if( sport->have_rtscts ) {
827 ucr2 &= ~UCR2_IRTS;
828 ucr2 |= UCR2_CTSC;
829 } else {
830 termios->c_cflag &= ~CRTSCTS;
831 }
832 }
833
834 if (termios->c_cflag & CSTOPB)
835 ucr2 |= UCR2_STPB;
836 if (termios->c_cflag & PARENB) {
837 ucr2 |= UCR2_PREN;
838 if (termios->c_cflag & PARODD)
839 ucr2 |= UCR2_PROE;
840 }
841
842 /*
843 * Ask the core to calculate the divisor for us.
844 */
845 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
846 quot = uart_get_divisor(port, baud);
847
848 spin_lock_irqsave(&sport->port.lock, flags);
849
850 sport->port.read_status_mask = 0;
851 if (termios->c_iflag & INPCK)
852 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
853 if (termios->c_iflag & (BRKINT | PARMRK))
854 sport->port.read_status_mask |= URXD_BRK;
855
856 /*
857 * Characters to ignore
858 */
859 sport->port.ignore_status_mask = 0;
860 if (termios->c_iflag & IGNPAR)
861 sport->port.ignore_status_mask |= URXD_PRERR;
862 if (termios->c_iflag & IGNBRK) {
863 sport->port.ignore_status_mask |= URXD_BRK;
864 /*
865 * If we're ignoring parity and break indicators,
866 * ignore overruns too (for real raw support).
867 */
868 if (termios->c_iflag & IGNPAR)
869 sport->port.ignore_status_mask |= URXD_OVRRUN;
870 }
871
872 del_timer_sync(&sport->timer);
873
874 /*
875 * Update the per-port timeout.
876 */
877 uart_update_timeout(port, termios->c_cflag, baud);
878
879 /*
880 * disable interrupts and drain transmitter
881 */
882 old_ucr1 = readl(sport->port.membase + UCR1);
883 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
884 sport->port.membase + UCR1);
885
886 while ( !(readl(sport->port.membase + USR2) & USR2_TXDC))
887 barrier();
888
889 /* then, disable everything */
890 old_txrxen = readl(sport->port.membase + UCR2);
891 writel(old_txrxen & ~( UCR2_TXEN | UCR2_RXEN),
892 sport->port.membase + UCR2);
893 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
894
895 if (USE_IRDA(sport)) {
896 /*
897 * use maximum available submodule frequency to
898 * avoid missing short pulses due to low sampling rate
899 */
900 div = 1;
901 } else {
902 div = sport->port.uartclk / (baud * 16);
903 if (div > 7)
904 div = 7;
905 if (!div)
906 div = 1;
907 }
908
909 rational_best_approximation(16 * div * baud, sport->port.uartclk,
910 1 << 16, 1 << 16, &num, &denom);
911
912 tdiv64 = sport->port.uartclk;
913 tdiv64 *= num;
914 do_div(tdiv64, denom * 16 * div);
915 tty_termios_encode_baud_rate(termios,
916 (speed_t)tdiv64, (speed_t)tdiv64);
917
918 num -= 1;
919 denom -= 1;
920
921 ufcr = readl(sport->port.membase + UFCR);
922 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
923 writel(ufcr, sport->port.membase + UFCR);
924
925 writel(num, sport->port.membase + UBIR);
926 writel(denom, sport->port.membase + UBMR);
927
928 if (!cpu_is_mx1())
929 writel(sport->port.uartclk / div / 1000,
930 sport->port.membase + MX2_ONEMS);
931
932 writel(old_ucr1, sport->port.membase + UCR1);
933
934 /* set the parity, stop bits and data size */
935 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
936
937 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
938 imx_enable_ms(&sport->port);
939
940 spin_unlock_irqrestore(&sport->port.lock, flags);
941}
942
943static const char *imx_type(struct uart_port *port)
944{
945 struct imx_port *sport = (struct imx_port *)port;
946
947 return sport->port.type == PORT_IMX ? "IMX" : NULL;
948}
949
950/*
951 * Release the memory region(s) being used by 'port'.
952 */
953static void imx_release_port(struct uart_port *port)
954{
955 struct platform_device *pdev = to_platform_device(port->dev);
956 struct resource *mmres;
957
958 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
959 release_mem_region(mmres->start, mmres->end - mmres->start + 1);
960}
961
962/*
963 * Request the memory region(s) being used by 'port'.
964 */
965static int imx_request_port(struct uart_port *port)
966{
967 struct platform_device *pdev = to_platform_device(port->dev);
968 struct resource *mmres;
969 void *ret;
970
971 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
972 if (!mmres)
973 return -ENODEV;
974
975 ret = request_mem_region(mmres->start, mmres->end - mmres->start + 1,
976 "imx-uart");
977
978 return ret ? 0 : -EBUSY;
979}
980
981/*
982 * Configure/autoconfigure the port.
983 */
984static void imx_config_port(struct uart_port *port, int flags)
985{
986 struct imx_port *sport = (struct imx_port *)port;
987
988 if (flags & UART_CONFIG_TYPE &&
989 imx_request_port(&sport->port) == 0)
990 sport->port.type = PORT_IMX;
991}
992
993/*
994 * Verify the new serial_struct (for TIOCSSERIAL).
995 * The only change we allow are to the flags and type, and
996 * even then only between PORT_IMX and PORT_UNKNOWN
997 */
998static int
999imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1000{
1001 struct imx_port *sport = (struct imx_port *)port;
1002 int ret = 0;
1003
1004 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1005 ret = -EINVAL;
1006 if (sport->port.irq != ser->irq)
1007 ret = -EINVAL;
1008 if (ser->io_type != UPIO_MEM)
1009 ret = -EINVAL;
1010 if (sport->port.uartclk / 16 != ser->baud_base)
1011 ret = -EINVAL;
1012 if ((void *)sport->port.mapbase != ser->iomem_base)
1013 ret = -EINVAL;
1014 if (sport->port.iobase != ser->port)
1015 ret = -EINVAL;
1016 if (ser->hub6 != 0)
1017 ret = -EINVAL;
1018 return ret;
1019}
1020
1021static struct uart_ops imx_pops = {
1022 .tx_empty = imx_tx_empty,
1023 .set_mctrl = imx_set_mctrl,
1024 .get_mctrl = imx_get_mctrl,
1025 .stop_tx = imx_stop_tx,
1026 .start_tx = imx_start_tx,
1027 .stop_rx = imx_stop_rx,
1028 .enable_ms = imx_enable_ms,
1029 .break_ctl = imx_break_ctl,
1030 .startup = imx_startup,
1031 .shutdown = imx_shutdown,
1032 .set_termios = imx_set_termios,
1033 .type = imx_type,
1034 .release_port = imx_release_port,
1035 .request_port = imx_request_port,
1036 .config_port = imx_config_port,
1037 .verify_port = imx_verify_port,
1038};
1039
1040static struct imx_port *imx_ports[UART_NR];
1041
1042#ifdef CONFIG_SERIAL_IMX_CONSOLE
1043static void imx_console_putchar(struct uart_port *port, int ch)
1044{
1045 struct imx_port *sport = (struct imx_port *)port;
1046
1047 while (readl(sport->port.membase + UTS) & UTS_TXFULL)
1048 barrier();
1049
1050 writel(ch, sport->port.membase + URTX0);
1051}
1052
1053/*
1054 * Interrupts are disabled on entering
1055 */
1056static void
1057imx_console_write(struct console *co, const char *s, unsigned int count)
1058{
1059 struct imx_port *sport = imx_ports[co->index];
1060 unsigned int old_ucr1, old_ucr2, ucr1;
1061
1062 /*
1063 * First, save UCR1/2 and then disable interrupts
1064 */
1065 ucr1 = old_ucr1 = readl(sport->port.membase + UCR1);
1066 old_ucr2 = readl(sport->port.membase + UCR2);
1067
1068 if (cpu_is_mx1())
1069 ucr1 |= MX1_UCR1_UARTCLKEN;
1070 ucr1 |= UCR1_UARTEN;
1071 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1072
1073 writel(ucr1, sport->port.membase + UCR1);
1074
1075 writel(old_ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1076
1077 uart_console_write(&sport->port, s, count, imx_console_putchar);
1078
1079 /*
1080 * Finally, wait for transmitter to become empty
1081 * and restore UCR1/2
1082 */
1083 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1084
1085 writel(old_ucr1, sport->port.membase + UCR1);
1086 writel(old_ucr2, sport->port.membase + UCR2);
1087}
1088
1089/*
1090 * If the port was already initialised (eg, by a boot loader),
1091 * try to determine the current setup.
1092 */
1093static void __init
1094imx_console_get_options(struct imx_port *sport, int *baud,
1095 int *parity, int *bits)
1096{
1097
1098 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1099 /* ok, the port was enabled */
1100 unsigned int ucr2, ubir,ubmr, uartclk;
1101 unsigned int baud_raw;
1102 unsigned int ucfr_rfdiv;
1103
1104 ucr2 = readl(sport->port.membase + UCR2);
1105
1106 *parity = 'n';
1107 if (ucr2 & UCR2_PREN) {
1108 if (ucr2 & UCR2_PROE)
1109 *parity = 'o';
1110 else
1111 *parity = 'e';
1112 }
1113
1114 if (ucr2 & UCR2_WS)
1115 *bits = 8;
1116 else
1117 *bits = 7;
1118
1119 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1120 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1121
1122 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1123 if (ucfr_rfdiv == 6)
1124 ucfr_rfdiv = 7;
1125 else
1126 ucfr_rfdiv = 6 - ucfr_rfdiv;
1127
1128 uartclk = clk_get_rate(sport->clk);
1129 uartclk /= ucfr_rfdiv;
1130
1131 { /*
1132 * The next code provides exact computation of
1133 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1134 * without need of float support or long long division,
1135 * which would be required to prevent 32bit arithmetic overflow
1136 */
1137 unsigned int mul = ubir + 1;
1138 unsigned int div = 16 * (ubmr + 1);
1139 unsigned int rem = uartclk % div;
1140
1141 baud_raw = (uartclk / div) * mul;
1142 baud_raw += (rem * mul + div / 2) / div;
1143 *baud = (baud_raw + 50) / 100 * 100;
1144 }
1145
1146 if(*baud != baud_raw)
1147 printk(KERN_INFO "Serial: Console IMX rounded baud rate from %d to %d\n",
1148 baud_raw, *baud);
1149 }
1150}
1151
1152static int __init
1153imx_console_setup(struct console *co, char *options)
1154{
1155 struct imx_port *sport;
1156 int baud = 9600;
1157 int bits = 8;
1158 int parity = 'n';
1159 int flow = 'n';
1160
1161 /*
1162 * Check whether an invalid uart number has been specified, and
1163 * if so, search for the first available port that does have
1164 * console support.
1165 */
1166 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1167 co->index = 0;
1168 sport = imx_ports[co->index];
1169 if(sport == NULL)
1170 return -ENODEV;
1171
1172 if (options)
1173 uart_parse_options(options, &baud, &parity, &bits, &flow);
1174 else
1175 imx_console_get_options(sport, &baud, &parity, &bits);
1176
1177 imx_setup_ufcr(sport, 0);
1178
1179 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1180}
1181
1182static struct uart_driver imx_reg;
1183static struct console imx_console = {
1184 .name = DEV_NAME,
1185 .write = imx_console_write,
1186 .device = uart_console_device,
1187 .setup = imx_console_setup,
1188 .flags = CON_PRINTBUFFER,
1189 .index = -1,
1190 .data = &imx_reg,
1191};
1192
1193#define IMX_CONSOLE &imx_console
1194#else
1195#define IMX_CONSOLE NULL
1196#endif
1197
1198static struct uart_driver imx_reg = {
1199 .owner = THIS_MODULE,
1200 .driver_name = DRIVER_NAME,
1201 .dev_name = DEV_NAME,
1202 .major = SERIAL_IMX_MAJOR,
1203 .minor = MINOR_START,
1204 .nr = ARRAY_SIZE(imx_ports),
1205 .cons = IMX_CONSOLE,
1206};
1207
1208static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1209{
1210 struct imx_port *sport = platform_get_drvdata(dev);
1211
1212 if (sport)
1213 uart_suspend_port(&imx_reg, &sport->port);
1214
1215 return 0;
1216}
1217
1218static int serial_imx_resume(struct platform_device *dev)
1219{
1220 struct imx_port *sport = platform_get_drvdata(dev);
1221
1222 if (sport)
1223 uart_resume_port(&imx_reg, &sport->port);
1224
1225 return 0;
1226}
1227
1228static int serial_imx_probe(struct platform_device *pdev)
1229{
1230 struct imx_port *sport;
1231 struct imxuart_platform_data *pdata;
1232 void __iomem *base;
1233 int ret = 0;
1234 struct resource *res;
1235
1236 sport = kzalloc(sizeof(*sport), GFP_KERNEL);
1237 if (!sport)
1238 return -ENOMEM;
1239
1240 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1241 if (!res) {
1242 ret = -ENODEV;
1243 goto free;
1244 }
1245
1246 base = ioremap(res->start, PAGE_SIZE);
1247 if (!base) {
1248 ret = -ENOMEM;
1249 goto free;
1250 }
1251
1252 sport->port.dev = &pdev->dev;
1253 sport->port.mapbase = res->start;
1254 sport->port.membase = base;
1255 sport->port.type = PORT_IMX,
1256 sport->port.iotype = UPIO_MEM;
1257 sport->port.irq = platform_get_irq(pdev, 0);
1258 sport->rxirq = platform_get_irq(pdev, 0);
1259 sport->txirq = platform_get_irq(pdev, 1);
1260 sport->rtsirq = platform_get_irq(pdev, 2);
1261 sport->port.fifosize = 32;
1262 sport->port.ops = &imx_pops;
1263 sport->port.flags = UPF_BOOT_AUTOCONF;
1264 sport->port.line = pdev->id;
1265 init_timer(&sport->timer);
1266 sport->timer.function = imx_timeout;
1267 sport->timer.data = (unsigned long)sport;
1268
1269 sport->clk = clk_get(&pdev->dev, "uart");
1270 if (IS_ERR(sport->clk)) {
1271 ret = PTR_ERR(sport->clk);
1272 goto unmap;
1273 }
1274 clk_enable(sport->clk);
1275
1276 sport->port.uartclk = clk_get_rate(sport->clk);
1277
1278 imx_ports[pdev->id] = sport;
1279
1280 pdata = pdev->dev.platform_data;
1281 if (pdata && (pdata->flags & IMXUART_HAVE_RTSCTS))
1282 sport->have_rtscts = 1;
1283
1284#ifdef CONFIG_IRDA
1285 if (pdata && (pdata->flags & IMXUART_IRDA))
1286 sport->use_irda = 1;
1287#endif
1288
1289 if (pdata && pdata->init) {
1290 ret = pdata->init(pdev);
1291 if (ret)
1292 goto clkput;
1293 }
1294
1295 ret = uart_add_one_port(&imx_reg, &sport->port);
1296 if (ret)
1297 goto deinit;
1298 platform_set_drvdata(pdev, &sport->port);
1299
1300 return 0;
1301deinit:
1302 if (pdata && pdata->exit)
1303 pdata->exit(pdev);
1304clkput:
1305 clk_put(sport->clk);
1306 clk_disable(sport->clk);
1307unmap:
1308 iounmap(sport->port.membase);
1309free:
1310 kfree(sport);
1311
1312 return ret;
1313}
1314
1315static int serial_imx_remove(struct platform_device *pdev)
1316{
1317 struct imxuart_platform_data *pdata;
1318 struct imx_port *sport = platform_get_drvdata(pdev);
1319
1320 pdata = pdev->dev.platform_data;
1321
1322 platform_set_drvdata(pdev, NULL);
1323
1324 if (sport) {
1325 uart_remove_one_port(&imx_reg, &sport->port);
1326 clk_put(sport->clk);
1327 }
1328
1329 clk_disable(sport->clk);
1330
1331 if (pdata && pdata->exit)
1332 pdata->exit(pdev);
1333
1334 iounmap(sport->port.membase);
1335 kfree(sport);
1336
1337 return 0;
1338}
1339
1340static struct platform_driver serial_imx_driver = {
1341 .probe = serial_imx_probe,
1342 .remove = serial_imx_remove,
1343
1344 .suspend = serial_imx_suspend,
1345 .resume = serial_imx_resume,
1346 .driver = {
1347 .name = "imx-uart",
1348 .owner = THIS_MODULE,
1349 },
1350};
1351
1352static int __init imx_serial_init(void)
1353{
1354 int ret;
1355
1356 printk(KERN_INFO "Serial: IMX driver\n");
1357
1358 ret = uart_register_driver(&imx_reg);
1359 if (ret)
1360 return ret;
1361
1362 ret = platform_driver_register(&serial_imx_driver);
1363 if (ret != 0)
1364 uart_unregister_driver(&imx_reg);
1365
1366 return 0;
1367}
1368
1369static void __exit imx_serial_exit(void)
1370{
1371 platform_driver_unregister(&serial_imx_driver);
1372 uart_unregister_driver(&imx_reg);
1373}
1374
1375module_init(imx_serial_init);
1376module_exit(imx_serial_exit);
1377
1378MODULE_AUTHOR("Sascha Hauer");
1379MODULE_DESCRIPTION("IMX generic serial port driver");
1380MODULE_LICENSE("GPL");
1381MODULE_ALIAS("platform:imx-uart");
diff --git a/drivers/serial/ioc3_serial.c b/drivers/serial/ioc3_serial.c
deleted file mode 100644
index 800c54602339..000000000000
--- a/drivers/serial/ioc3_serial.c
+++ /dev/null
@@ -1,2195 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2005 Silicon Graphics, Inc. All Rights Reserved.
7 */
8
9/*
10 * This file contains a module version of the ioc3 serial driver. This
11 * includes all the support functions needed (support functions, etc.)
12 * and the serial driver itself.
13 */
14#include <linux/errno.h>
15#include <linux/tty.h>
16#include <linux/serial.h>
17#include <linux/circ_buf.h>
18#include <linux/serial_reg.h>
19#include <linux/module.h>
20#include <linux/pci.h>
21#include <linux/serial_core.h>
22#include <linux/ioc3.h>
23#include <linux/slab.h>
24
25/*
26 * Interesting things about the ioc3
27 */
28
29#define LOGICAL_PORTS 2 /* rs232(0) and rs422(1) */
30#define PORTS_PER_CARD 2
31#define LOGICAL_PORTS_PER_CARD (PORTS_PER_CARD * LOGICAL_PORTS)
32#define MAX_CARDS 8
33#define MAX_LOGICAL_PORTS (LOGICAL_PORTS_PER_CARD * MAX_CARDS)
34
35/* determine given the sio_ir what port it applies to */
36#define GET_PORT_FROM_SIO_IR(_x) (_x & SIO_IR_SA) ? 0 : 1
37
38
39/*
40 * we have 2 logical ports (rs232, rs422) for each physical port
41 * evens are rs232, odds are rs422
42 */
43#define GET_PHYSICAL_PORT(_x) ((_x) >> 1)
44#define GET_LOGICAL_PORT(_x) ((_x) & 1)
45#define IS_PHYSICAL_PORT(_x) !((_x) & 1)
46#define IS_RS232(_x) !((_x) & 1)
47
48static unsigned int Num_of_ioc3_cards;
49static unsigned int Submodule_slot;
50
51/* defining this will get you LOTS of great debug info */
52//#define DEBUG_INTERRUPTS
53#define DPRINT_CONFIG(_x...) ;
54//#define DPRINT_CONFIG(_x...) printk _x
55#define NOT_PROGRESS() ;
56//#define NOT_PROGRESS() printk("%s : fails %d\n", __func__, __LINE__)
57
58/* number of characters we want to transmit to the lower level at a time */
59#define MAX_CHARS 256
60#define FIFO_SIZE (MAX_CHARS-1) /* it's a uchar */
61
62/* Device name we're using */
63#define DEVICE_NAME "ttySIOC"
64#define DEVICE_MAJOR 204
65#define DEVICE_MINOR 116
66
67/* flags for next_char_state */
68#define NCS_BREAK 0x1
69#define NCS_PARITY 0x2
70#define NCS_FRAMING 0x4
71#define NCS_OVERRUN 0x8
72
73/* cause we need SOME parameters ... */
74#define MIN_BAUD_SUPPORTED 1200
75#define MAX_BAUD_SUPPORTED 115200
76
77/* protocol types supported */
78#define PROTO_RS232 0
79#define PROTO_RS422 1
80
81/* Notification types */
82#define N_DATA_READY 0x01
83#define N_OUTPUT_LOWAT 0x02
84#define N_BREAK 0x04
85#define N_PARITY_ERROR 0x08
86#define N_FRAMING_ERROR 0x10
87#define N_OVERRUN_ERROR 0x20
88#define N_DDCD 0x40
89#define N_DCTS 0x80
90
91#define N_ALL_INPUT (N_DATA_READY | N_BREAK \
92 | N_PARITY_ERROR | N_FRAMING_ERROR \
93 | N_OVERRUN_ERROR | N_DDCD | N_DCTS)
94
95#define N_ALL_OUTPUT N_OUTPUT_LOWAT
96
97#define N_ALL_ERRORS (N_PARITY_ERROR | N_FRAMING_ERROR \
98 | N_OVERRUN_ERROR)
99
100#define N_ALL (N_DATA_READY | N_OUTPUT_LOWAT | N_BREAK \
101 | N_PARITY_ERROR | N_FRAMING_ERROR \
102 | N_OVERRUN_ERROR | N_DDCD | N_DCTS)
103
104#define SER_CLK_SPEED(prediv) ((22000000 << 1) / prediv)
105#define SER_DIVISOR(x, clk) (((clk) + (x) * 8) / ((x) * 16))
106#define DIVISOR_TO_BAUD(div, clk) ((clk) / 16 / (div))
107
108/* Some masks */
109#define LCR_MASK_BITS_CHAR (UART_LCR_WLEN5 | UART_LCR_WLEN6 \
110 | UART_LCR_WLEN7 | UART_LCR_WLEN8)
111#define LCR_MASK_STOP_BITS (UART_LCR_STOP)
112
113#define PENDING(_a, _p) (readl(&(_p)->vma->sio_ir) & (_a)->ic_enable)
114
115#define RING_BUF_SIZE 4096
116#define BUF_SIZE_BIT SBBR_L_SIZE
117#define PROD_CONS_MASK PROD_CONS_PTR_4K
118
119#define TOTAL_RING_BUF_SIZE (RING_BUF_SIZE * 4)
120
121/* driver specific - one per card */
122struct ioc3_card {
123 struct {
124 /* uart ports are allocated here */
125 struct uart_port icp_uart_port[LOGICAL_PORTS];
126 /* the ioc3_port used for this port */
127 struct ioc3_port *icp_port;
128 } ic_port[PORTS_PER_CARD];
129 /* currently enabled interrupts */
130 uint32_t ic_enable;
131};
132
133/* Local port info for each IOC3 serial port */
134struct ioc3_port {
135 /* handy reference material */
136 struct uart_port *ip_port;
137 struct ioc3_card *ip_card;
138 struct ioc3_driver_data *ip_idd;
139 struct ioc3_submodule *ip_is;
140
141 /* pci mem addresses for this port */
142 struct ioc3_serialregs __iomem *ip_serial_regs;
143 struct ioc3_uartregs __iomem *ip_uart_regs;
144
145 /* Ring buffer page for this port */
146 dma_addr_t ip_dma_ringbuf;
147 /* vaddr of ring buffer */
148 struct ring_buffer *ip_cpu_ringbuf;
149
150 /* Rings for this port */
151 struct ring *ip_inring;
152 struct ring *ip_outring;
153
154 /* Hook to port specific values */
155 struct port_hooks *ip_hooks;
156
157 spinlock_t ip_lock;
158
159 /* Various rx/tx parameters */
160 int ip_baud;
161 int ip_tx_lowat;
162 int ip_rx_timeout;
163
164 /* Copy of notification bits */
165 int ip_notify;
166
167 /* Shadow copies of various registers so we don't need to PIO
168 * read them constantly
169 */
170 uint32_t ip_sscr;
171 uint32_t ip_tx_prod;
172 uint32_t ip_rx_cons;
173 unsigned char ip_flags;
174};
175
176/* tx low water mark. We need to notify the driver whenever tx is getting
177 * close to empty so it can refill the tx buffer and keep things going.
178 * Let's assume that if we interrupt 1 ms before the tx goes idle, we'll
179 * have no trouble getting in more chars in time (I certainly hope so).
180 */
181#define TX_LOWAT_LATENCY 1000
182#define TX_LOWAT_HZ (1000000 / TX_LOWAT_LATENCY)
183#define TX_LOWAT_CHARS(baud) (baud / 10 / TX_LOWAT_HZ)
184
185/* Flags per port */
186#define INPUT_HIGH 0x01
187 /* used to signify that we have turned off the rx_high
188 * temporarily - we need to drain the fifo and don't
189 * want to get blasted with interrupts.
190 */
191#define DCD_ON 0x02
192 /* DCD state is on */
193#define LOWAT_WRITTEN 0x04
194#define READ_ABORTED 0x08
195 /* the read was aborted - used to avaoid infinate looping
196 * in the interrupt handler
197 */
198#define INPUT_ENABLE 0x10
199
200/* Since each port has different register offsets and bitmasks
201 * for everything, we'll store those that we need in tables so we
202 * don't have to be constantly checking the port we are dealing with.
203 */
204struct port_hooks {
205 uint32_t intr_delta_dcd;
206 uint32_t intr_delta_cts;
207 uint32_t intr_tx_mt;
208 uint32_t intr_rx_timer;
209 uint32_t intr_rx_high;
210 uint32_t intr_tx_explicit;
211 uint32_t intr_clear;
212 uint32_t intr_all;
213 char rs422_select_pin;
214};
215
216static struct port_hooks hooks_array[PORTS_PER_CARD] = {
217 /* values for port A */
218 {
219 .intr_delta_dcd = SIO_IR_SA_DELTA_DCD,
220 .intr_delta_cts = SIO_IR_SA_DELTA_CTS,
221 .intr_tx_mt = SIO_IR_SA_TX_MT,
222 .intr_rx_timer = SIO_IR_SA_RX_TIMER,
223 .intr_rx_high = SIO_IR_SA_RX_HIGH,
224 .intr_tx_explicit = SIO_IR_SA_TX_EXPLICIT,
225 .intr_clear = (SIO_IR_SA_TX_MT | SIO_IR_SA_RX_FULL
226 | SIO_IR_SA_RX_HIGH
227 | SIO_IR_SA_RX_TIMER
228 | SIO_IR_SA_DELTA_DCD
229 | SIO_IR_SA_DELTA_CTS
230 | SIO_IR_SA_INT
231 | SIO_IR_SA_TX_EXPLICIT
232 | SIO_IR_SA_MEMERR),
233 .intr_all = SIO_IR_SA,
234 .rs422_select_pin = GPPR_UARTA_MODESEL_PIN,
235 },
236
237 /* values for port B */
238 {
239 .intr_delta_dcd = SIO_IR_SB_DELTA_DCD,
240 .intr_delta_cts = SIO_IR_SB_DELTA_CTS,
241 .intr_tx_mt = SIO_IR_SB_TX_MT,
242 .intr_rx_timer = SIO_IR_SB_RX_TIMER,
243 .intr_rx_high = SIO_IR_SB_RX_HIGH,
244 .intr_tx_explicit = SIO_IR_SB_TX_EXPLICIT,
245 .intr_clear = (SIO_IR_SB_TX_MT | SIO_IR_SB_RX_FULL
246 | SIO_IR_SB_RX_HIGH
247 | SIO_IR_SB_RX_TIMER
248 | SIO_IR_SB_DELTA_DCD
249 | SIO_IR_SB_DELTA_CTS
250 | SIO_IR_SB_INT
251 | SIO_IR_SB_TX_EXPLICIT
252 | SIO_IR_SB_MEMERR),
253 .intr_all = SIO_IR_SB,
254 .rs422_select_pin = GPPR_UARTB_MODESEL_PIN,
255 }
256};
257
258struct ring_entry {
259 union {
260 struct {
261 uint32_t alldata;
262 uint32_t allsc;
263 } all;
264 struct {
265 char data[4]; /* data bytes */
266 char sc[4]; /* status/control */
267 } s;
268 } u;
269};
270
271/* Test the valid bits in any of the 4 sc chars using "allsc" member */
272#define RING_ANY_VALID \
273 ((uint32_t)(RXSB_MODEM_VALID | RXSB_DATA_VALID) * 0x01010101)
274
275#define ring_sc u.s.sc
276#define ring_data u.s.data
277#define ring_allsc u.all.allsc
278
279/* Number of entries per ring buffer. */
280#define ENTRIES_PER_RING (RING_BUF_SIZE / (int) sizeof(struct ring_entry))
281
282/* An individual ring */
283struct ring {
284 struct ring_entry entries[ENTRIES_PER_RING];
285};
286
287/* The whole enchilada */
288struct ring_buffer {
289 struct ring TX_A;
290 struct ring RX_A;
291 struct ring TX_B;
292 struct ring RX_B;
293};
294
295/* Get a ring from a port struct */
296#define RING(_p, _wh) &(((struct ring_buffer *)((_p)->ip_cpu_ringbuf))->_wh)
297
298/* for Infinite loop detection */
299#define MAXITER 10000000
300
301
302/**
303 * set_baud - Baud rate setting code
304 * @port: port to set
305 * @baud: baud rate to use
306 */
307static int set_baud(struct ioc3_port *port, int baud)
308{
309 int divisor;
310 int actual_baud;
311 int diff;
312 int lcr, prediv;
313 struct ioc3_uartregs __iomem *uart;
314
315 for (prediv = 6; prediv < 64; prediv++) {
316 divisor = SER_DIVISOR(baud, SER_CLK_SPEED(prediv));
317 if (!divisor)
318 continue; /* invalid divisor */
319 actual_baud = DIVISOR_TO_BAUD(divisor, SER_CLK_SPEED(prediv));
320
321 diff = actual_baud - baud;
322 if (diff < 0)
323 diff = -diff;
324
325 /* if we're within 1% we've found a match */
326 if (diff * 100 <= actual_baud)
327 break;
328 }
329
330 /* if the above loop completed, we didn't match
331 * the baud rate. give up.
332 */
333 if (prediv == 64) {
334 NOT_PROGRESS();
335 return 1;
336 }
337
338 uart = port->ip_uart_regs;
339 lcr = readb(&uart->iu_lcr);
340
341 writeb(lcr | UART_LCR_DLAB, &uart->iu_lcr);
342 writeb((unsigned char)divisor, &uart->iu_dll);
343 writeb((unsigned char)(divisor >> 8), &uart->iu_dlm);
344 writeb((unsigned char)prediv, &uart->iu_scr);
345 writeb((unsigned char)lcr, &uart->iu_lcr);
346
347 return 0;
348}
349
350/**
351 * get_ioc3_port - given a uart port, return the control structure
352 * @the_port: uart port to find
353 */
354static struct ioc3_port *get_ioc3_port(struct uart_port *the_port)
355{
356 struct ioc3_driver_data *idd = dev_get_drvdata(the_port->dev);
357 struct ioc3_card *card_ptr = idd->data[Submodule_slot];
358 int ii, jj;
359
360 if (!card_ptr) {
361 NOT_PROGRESS();
362 return NULL;
363 }
364 for (ii = 0; ii < PORTS_PER_CARD; ii++) {
365 for (jj = 0; jj < LOGICAL_PORTS; jj++) {
366 if (the_port == &card_ptr->ic_port[ii].icp_uart_port[jj])
367 return card_ptr->ic_port[ii].icp_port;
368 }
369 }
370 NOT_PROGRESS();
371 return NULL;
372}
373
374/**
375 * port_init - Initialize the sio and ioc3 hardware for a given port
376 * called per port from attach...
377 * @port: port to initialize
378 */
379static int inline port_init(struct ioc3_port *port)
380{
381 uint32_t sio_cr;
382 struct port_hooks *hooks = port->ip_hooks;
383 struct ioc3_uartregs __iomem *uart;
384 int reset_loop_counter = 0xfffff;
385 struct ioc3_driver_data *idd = port->ip_idd;
386
387 /* Idle the IOC3 serial interface */
388 writel(SSCR_RESET, &port->ip_serial_regs->sscr);
389
390 /* Wait until any pending bus activity for this port has ceased */
391 do {
392 sio_cr = readl(&idd->vma->sio_cr);
393 if (reset_loop_counter-- <= 0) {
394 printk(KERN_WARNING
395 "IOC3 unable to come out of reset"
396 " scr 0x%x\n", sio_cr);
397 return -1;
398 }
399 } while (!(sio_cr & SIO_CR_ARB_DIAG_IDLE) &&
400 (((sio_cr &= SIO_CR_ARB_DIAG) == SIO_CR_ARB_DIAG_TXA)
401 || sio_cr == SIO_CR_ARB_DIAG_TXB
402 || sio_cr == SIO_CR_ARB_DIAG_RXA
403 || sio_cr == SIO_CR_ARB_DIAG_RXB));
404
405 /* Finish reset sequence */
406 writel(0, &port->ip_serial_regs->sscr);
407
408 /* Once RESET is done, reload cached tx_prod and rx_cons values
409 * and set rings to empty by making prod == cons
410 */
411 port->ip_tx_prod = readl(&port->ip_serial_regs->stcir) & PROD_CONS_MASK;
412 writel(port->ip_tx_prod, &port->ip_serial_regs->stpir);
413 port->ip_rx_cons = readl(&port->ip_serial_regs->srpir) & PROD_CONS_MASK;
414 writel(port->ip_rx_cons | SRCIR_ARM, &port->ip_serial_regs->srcir);
415
416 /* Disable interrupts for this 16550 */
417 uart = port->ip_uart_regs;
418 writeb(0, &uart->iu_lcr);
419 writeb(0, &uart->iu_ier);
420
421 /* Set the default baud */
422 set_baud(port, port->ip_baud);
423
424 /* Set line control to 8 bits no parity */
425 writeb(UART_LCR_WLEN8 | 0, &uart->iu_lcr);
426 /* UART_LCR_STOP == 1 stop */
427
428 /* Enable the FIFOs */
429 writeb(UART_FCR_ENABLE_FIFO, &uart->iu_fcr);
430 /* then reset 16550 FIFOs */
431 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
432 &uart->iu_fcr);
433
434 /* Clear modem control register */
435 writeb(0, &uart->iu_mcr);
436
437 /* Clear deltas in modem status register */
438 writel(0, &port->ip_serial_regs->shadow);
439
440 /* Only do this once per port pair */
441 if (port->ip_hooks == &hooks_array[0]) {
442 unsigned long ring_pci_addr;
443 uint32_t __iomem *sbbr_l, *sbbr_h;
444
445 sbbr_l = &idd->vma->sbbr_l;
446 sbbr_h = &idd->vma->sbbr_h;
447 ring_pci_addr = (unsigned long __iomem)port->ip_dma_ringbuf;
448 DPRINT_CONFIG(("%s: ring_pci_addr 0x%p\n",
449 __func__, (void *)ring_pci_addr));
450
451 writel((unsigned int)((uint64_t) ring_pci_addr >> 32), sbbr_h);
452 writel((unsigned int)ring_pci_addr | BUF_SIZE_BIT, sbbr_l);
453 }
454
455 /* Set the receive timeout value to 10 msec */
456 writel(SRTR_HZ / 100, &port->ip_serial_regs->srtr);
457
458 /* Set rx threshold, enable DMA */
459 /* Set high water mark at 3/4 of full ring */
460 port->ip_sscr = (ENTRIES_PER_RING * 3 / 4);
461
462 /* uart experiences pauses at high baud rate reducing actual
463 * throughput by 10% or so unless we enable high speed polling
464 * XXX when this hardware bug is resolved we should revert to
465 * normal polling speed
466 */
467 port->ip_sscr |= SSCR_HIGH_SPD;
468
469 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
470
471 /* Disable and clear all serial related interrupt bits */
472 port->ip_card->ic_enable &= ~hooks->intr_clear;
473 ioc3_disable(port->ip_is, idd, hooks->intr_clear);
474 ioc3_ack(port->ip_is, idd, hooks->intr_clear);
475 return 0;
476}
477
478/**
479 * enable_intrs - enable interrupts
480 * @port: port to enable
481 * @mask: mask to use
482 */
483static void enable_intrs(struct ioc3_port *port, uint32_t mask)
484{
485 if ((port->ip_card->ic_enable & mask) != mask) {
486 port->ip_card->ic_enable |= mask;
487 ioc3_enable(port->ip_is, port->ip_idd, mask);
488 }
489}
490
491/**
492 * local_open - local open a port
493 * @port: port to open
494 */
495static inline int local_open(struct ioc3_port *port)
496{
497 int spiniter = 0;
498
499 port->ip_flags = INPUT_ENABLE;
500
501 /* Pause the DMA interface if necessary */
502 if (port->ip_sscr & SSCR_DMA_EN) {
503 writel(port->ip_sscr | SSCR_DMA_PAUSE,
504 &port->ip_serial_regs->sscr);
505 while ((readl(&port->ip_serial_regs->sscr)
506 & SSCR_PAUSE_STATE) == 0) {
507 spiniter++;
508 if (spiniter > MAXITER) {
509 NOT_PROGRESS();
510 return -1;
511 }
512 }
513 }
514
515 /* Reset the input fifo. If the uart received chars while the port
516 * was closed and DMA is not enabled, the uart may have a bunch of
517 * chars hanging around in its rx fifo which will not be discarded
518 * by rclr in the upper layer. We must get rid of them here.
519 */
520 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR,
521 &port->ip_uart_regs->iu_fcr);
522
523 writeb(UART_LCR_WLEN8, &port->ip_uart_regs->iu_lcr);
524 /* UART_LCR_STOP == 1 stop */
525
526 /* Re-enable DMA, set default threshold to intr whenever there is
527 * data available.
528 */
529 port->ip_sscr &= ~SSCR_RX_THRESHOLD;
530 port->ip_sscr |= 1; /* default threshold */
531
532 /* Plug in the new sscr. This implicitly clears the DMA_PAUSE
533 * flag if it was set above
534 */
535 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
536 port->ip_tx_lowat = 1;
537 return 0;
538}
539
540/**
541 * set_rx_timeout - Set rx timeout and threshold values.
542 * @port: port to use
543 * @timeout: timeout value in ticks
544 */
545static inline int set_rx_timeout(struct ioc3_port *port, int timeout)
546{
547 int threshold;
548
549 port->ip_rx_timeout = timeout;
550
551 /* Timeout is in ticks. Let's figure out how many chars we
552 * can receive at the current baud rate in that interval
553 * and set the rx threshold to that amount. There are 4 chars
554 * per ring entry, so we'll divide the number of chars that will
555 * arrive in timeout by 4.
556 * So .... timeout * baud / 10 / HZ / 4, with HZ = 100.
557 */
558 threshold = timeout * port->ip_baud / 4000;
559 if (threshold == 0)
560 threshold = 1; /* otherwise we'll intr all the time! */
561
562 if ((unsigned)threshold > (unsigned)SSCR_RX_THRESHOLD)
563 return 1;
564
565 port->ip_sscr &= ~SSCR_RX_THRESHOLD;
566 port->ip_sscr |= threshold;
567 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
568
569 /* Now set the rx timeout to the given value
570 * again timeout * SRTR_HZ / HZ
571 */
572 timeout = timeout * SRTR_HZ / 100;
573 if (timeout > SRTR_CNT)
574 timeout = SRTR_CNT;
575 writel(timeout, &port->ip_serial_regs->srtr);
576 return 0;
577}
578
579/**
580 * config_port - config the hardware
581 * @port: port to config
582 * @baud: baud rate for the port
583 * @byte_size: data size
584 * @stop_bits: number of stop bits
585 * @parenb: parity enable ?
586 * @parodd: odd parity ?
587 */
588static inline int
589config_port(struct ioc3_port *port,
590 int baud, int byte_size, int stop_bits, int parenb, int parodd)
591{
592 char lcr, sizebits;
593 int spiniter = 0;
594
595 DPRINT_CONFIG(("%s: line %d baud %d byte_size %d stop %d parenb %d "
596 "parodd %d\n",
597 __func__, ((struct uart_port *)port->ip_port)->line,
598 baud, byte_size, stop_bits, parenb, parodd));
599
600 if (set_baud(port, baud))
601 return 1;
602
603 switch (byte_size) {
604 case 5:
605 sizebits = UART_LCR_WLEN5;
606 break;
607 case 6:
608 sizebits = UART_LCR_WLEN6;
609 break;
610 case 7:
611 sizebits = UART_LCR_WLEN7;
612 break;
613 case 8:
614 sizebits = UART_LCR_WLEN8;
615 break;
616 default:
617 return 1;
618 }
619
620 /* Pause the DMA interface if necessary */
621 if (port->ip_sscr & SSCR_DMA_EN) {
622 writel(port->ip_sscr | SSCR_DMA_PAUSE,
623 &port->ip_serial_regs->sscr);
624 while ((readl(&port->ip_serial_regs->sscr)
625 & SSCR_PAUSE_STATE) == 0) {
626 spiniter++;
627 if (spiniter > MAXITER)
628 return -1;
629 }
630 }
631
632 /* Clear relevant fields in lcr */
633 lcr = readb(&port->ip_uart_regs->iu_lcr);
634 lcr &= ~(LCR_MASK_BITS_CHAR | UART_LCR_EPAR |
635 UART_LCR_PARITY | LCR_MASK_STOP_BITS);
636
637 /* Set byte size in lcr */
638 lcr |= sizebits;
639
640 /* Set parity */
641 if (parenb) {
642 lcr |= UART_LCR_PARITY;
643 if (!parodd)
644 lcr |= UART_LCR_EPAR;
645 }
646
647 /* Set stop bits */
648 if (stop_bits)
649 lcr |= UART_LCR_STOP /* 2 stop bits */ ;
650
651 writeb(lcr, &port->ip_uart_regs->iu_lcr);
652
653 /* Re-enable the DMA interface if necessary */
654 if (port->ip_sscr & SSCR_DMA_EN) {
655 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
656 }
657 port->ip_baud = baud;
658
659 /* When we get within this number of ring entries of filling the
660 * entire ring on tx, place an EXPLICIT intr to generate a lowat
661 * notification when output has drained.
662 */
663 port->ip_tx_lowat = (TX_LOWAT_CHARS(baud) + 3) / 4;
664 if (port->ip_tx_lowat == 0)
665 port->ip_tx_lowat = 1;
666
667 set_rx_timeout(port, 2);
668 return 0;
669}
670
671/**
672 * do_write - Write bytes to the port. Returns the number of bytes
673 * actually written. Called from transmit_chars
674 * @port: port to use
675 * @buf: the stuff to write
676 * @len: how many bytes in 'buf'
677 */
678static inline int do_write(struct ioc3_port *port, char *buf, int len)
679{
680 int prod_ptr, cons_ptr, total = 0;
681 struct ring *outring;
682 struct ring_entry *entry;
683 struct port_hooks *hooks = port->ip_hooks;
684
685 BUG_ON(!(len >= 0));
686
687 prod_ptr = port->ip_tx_prod;
688 cons_ptr = readl(&port->ip_serial_regs->stcir) & PROD_CONS_MASK;
689 outring = port->ip_outring;
690
691 /* Maintain a 1-entry red-zone. The ring buffer is full when
692 * (cons - prod) % ring_size is 1. Rather than do this subtraction
693 * in the body of the loop, I'll do it now.
694 */
695 cons_ptr = (cons_ptr - (int)sizeof(struct ring_entry)) & PROD_CONS_MASK;
696
697 /* Stuff the bytes into the output */
698 while ((prod_ptr != cons_ptr) && (len > 0)) {
699 int xx;
700
701 /* Get 4 bytes (one ring entry) at a time */
702 entry = (struct ring_entry *)((caddr_t) outring + prod_ptr);
703
704 /* Invalidate all entries */
705 entry->ring_allsc = 0;
706
707 /* Copy in some bytes */
708 for (xx = 0; (xx < 4) && (len > 0); xx++) {
709 entry->ring_data[xx] = *buf++;
710 entry->ring_sc[xx] = TXCB_VALID;
711 len--;
712 total++;
713 }
714
715 /* If we are within some small threshold of filling up the
716 * entire ring buffer, we must place an EXPLICIT intr here
717 * to generate a lowat interrupt in case we subsequently
718 * really do fill up the ring and the caller goes to sleep.
719 * No need to place more than one though.
720 */
721 if (!(port->ip_flags & LOWAT_WRITTEN) &&
722 ((cons_ptr - prod_ptr) & PROD_CONS_MASK)
723 <= port->ip_tx_lowat * (int)sizeof(struct ring_entry)) {
724 port->ip_flags |= LOWAT_WRITTEN;
725 entry->ring_sc[0] |= TXCB_INT_WHEN_DONE;
726 }
727
728 /* Go on to next entry */
729 prod_ptr += sizeof(struct ring_entry);
730 prod_ptr &= PROD_CONS_MASK;
731 }
732
733 /* If we sent something, start DMA if necessary */
734 if (total > 0 && !(port->ip_sscr & SSCR_DMA_EN)) {
735 port->ip_sscr |= SSCR_DMA_EN;
736 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
737 }
738
739 /* Store the new producer pointer. If tx is disabled, we stuff the
740 * data into the ring buffer, but we don't actually start tx.
741 */
742 if (!uart_tx_stopped(port->ip_port)) {
743 writel(prod_ptr, &port->ip_serial_regs->stpir);
744
745 /* If we are now transmitting, enable tx_mt interrupt so we
746 * can disable DMA if necessary when the tx finishes.
747 */
748 if (total > 0)
749 enable_intrs(port, hooks->intr_tx_mt);
750 }
751 port->ip_tx_prod = prod_ptr;
752
753 return total;
754}
755
756/**
757 * disable_intrs - disable interrupts
758 * @port: port to enable
759 * @mask: mask to use
760 */
761static inline void disable_intrs(struct ioc3_port *port, uint32_t mask)
762{
763 if (port->ip_card->ic_enable & mask) {
764 ioc3_disable(port->ip_is, port->ip_idd, mask);
765 port->ip_card->ic_enable &= ~mask;
766 }
767}
768
769/**
770 * set_notification - Modify event notification
771 * @port: port to use
772 * @mask: events mask
773 * @set_on: set ?
774 */
775static int set_notification(struct ioc3_port *port, int mask, int set_on)
776{
777 struct port_hooks *hooks = port->ip_hooks;
778 uint32_t intrbits, sscrbits;
779
780 BUG_ON(!mask);
781
782 intrbits = sscrbits = 0;
783
784 if (mask & N_DATA_READY)
785 intrbits |= (hooks->intr_rx_timer | hooks->intr_rx_high);
786 if (mask & N_OUTPUT_LOWAT)
787 intrbits |= hooks->intr_tx_explicit;
788 if (mask & N_DDCD) {
789 intrbits |= hooks->intr_delta_dcd;
790 sscrbits |= SSCR_RX_RING_DCD;
791 }
792 if (mask & N_DCTS)
793 intrbits |= hooks->intr_delta_cts;
794
795 if (set_on) {
796 enable_intrs(port, intrbits);
797 port->ip_notify |= mask;
798 port->ip_sscr |= sscrbits;
799 } else {
800 disable_intrs(port, intrbits);
801 port->ip_notify &= ~mask;
802 port->ip_sscr &= ~sscrbits;
803 }
804
805 /* We require DMA if either DATA_READY or DDCD notification is
806 * currently requested. If neither of these is requested and
807 * there is currently no tx in progress, DMA may be disabled.
808 */
809 if (port->ip_notify & (N_DATA_READY | N_DDCD))
810 port->ip_sscr |= SSCR_DMA_EN;
811 else if (!(port->ip_card->ic_enable & hooks->intr_tx_mt))
812 port->ip_sscr &= ~SSCR_DMA_EN;
813
814 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
815 return 0;
816}
817
818/**
819 * set_mcr - set the master control reg
820 * @the_port: port to use
821 * @mask1: mcr mask
822 * @mask2: shadow mask
823 */
824static inline int set_mcr(struct uart_port *the_port,
825 int mask1, int mask2)
826{
827 struct ioc3_port *port = get_ioc3_port(the_port);
828 uint32_t shadow;
829 int spiniter = 0;
830 char mcr;
831
832 if (!port)
833 return -1;
834
835 /* Pause the DMA interface if necessary */
836 if (port->ip_sscr & SSCR_DMA_EN) {
837 writel(port->ip_sscr | SSCR_DMA_PAUSE,
838 &port->ip_serial_regs->sscr);
839 while ((readl(&port->ip_serial_regs->sscr)
840 & SSCR_PAUSE_STATE) == 0) {
841 spiniter++;
842 if (spiniter > MAXITER)
843 return -1;
844 }
845 }
846 shadow = readl(&port->ip_serial_regs->shadow);
847 mcr = (shadow & 0xff000000) >> 24;
848
849 /* Set new value */
850 mcr |= mask1;
851 shadow |= mask2;
852 writeb(mcr, &port->ip_uart_regs->iu_mcr);
853 writel(shadow, &port->ip_serial_regs->shadow);
854
855 /* Re-enable the DMA interface if necessary */
856 if (port->ip_sscr & SSCR_DMA_EN) {
857 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
858 }
859 return 0;
860}
861
862/**
863 * ioc3_set_proto - set the protocol for the port
864 * @port: port to use
865 * @proto: protocol to use
866 */
867static int ioc3_set_proto(struct ioc3_port *port, int proto)
868{
869 struct port_hooks *hooks = port->ip_hooks;
870
871 switch (proto) {
872 default:
873 case PROTO_RS232:
874 /* Clear the appropriate GIO pin */
875 DPRINT_CONFIG(("%s: rs232\n", __func__));
876 writel(0, (&port->ip_idd->vma->gppr[0]
877 + hooks->rs422_select_pin));
878 break;
879
880 case PROTO_RS422:
881 /* Set the appropriate GIO pin */
882 DPRINT_CONFIG(("%s: rs422\n", __func__));
883 writel(1, (&port->ip_idd->vma->gppr[0]
884 + hooks->rs422_select_pin));
885 break;
886 }
887 return 0;
888}
889
890/**
891 * transmit_chars - upper level write, called with the_port->lock
892 * @the_port: port to write
893 */
894static void transmit_chars(struct uart_port *the_port)
895{
896 int xmit_count, tail, head;
897 int result;
898 char *start;
899 struct tty_struct *tty;
900 struct ioc3_port *port = get_ioc3_port(the_port);
901 struct uart_state *state;
902
903 if (!the_port)
904 return;
905 if (!port)
906 return;
907
908 state = the_port->state;
909 tty = state->port.tty;
910
911 if (uart_circ_empty(&state->xmit) || uart_tx_stopped(the_port)) {
912 /* Nothing to do or hw stopped */
913 set_notification(port, N_ALL_OUTPUT, 0);
914 return;
915 }
916
917 head = state->xmit.head;
918 tail = state->xmit.tail;
919 start = (char *)&state->xmit.buf[tail];
920
921 /* write out all the data or until the end of the buffer */
922 xmit_count = (head < tail) ? (UART_XMIT_SIZE - tail) : (head - tail);
923 if (xmit_count > 0) {
924 result = do_write(port, start, xmit_count);
925 if (result > 0) {
926 /* booking */
927 xmit_count -= result;
928 the_port->icount.tx += result;
929 /* advance the pointers */
930 tail += result;
931 tail &= UART_XMIT_SIZE - 1;
932 state->xmit.tail = tail;
933 start = (char *)&state->xmit.buf[tail];
934 }
935 }
936 if (uart_circ_chars_pending(&state->xmit) < WAKEUP_CHARS)
937 uart_write_wakeup(the_port);
938
939 if (uart_circ_empty(&state->xmit)) {
940 set_notification(port, N_OUTPUT_LOWAT, 0);
941 } else {
942 set_notification(port, N_OUTPUT_LOWAT, 1);
943 }
944}
945
946/**
947 * ioc3_change_speed - change the speed of the port
948 * @the_port: port to change
949 * @new_termios: new termios settings
950 * @old_termios: old termios settings
951 */
952static void
953ioc3_change_speed(struct uart_port *the_port,
954 struct ktermios *new_termios, struct ktermios *old_termios)
955{
956 struct ioc3_port *port = get_ioc3_port(the_port);
957 unsigned int cflag, iflag;
958 int baud;
959 int new_parity = 0, new_parity_enable = 0, new_stop = 0, new_data = 8;
960 struct uart_state *state = the_port->state;
961
962 cflag = new_termios->c_cflag;
963 iflag = new_termios->c_iflag;
964
965 switch (cflag & CSIZE) {
966 case CS5:
967 new_data = 5;
968 break;
969 case CS6:
970 new_data = 6;
971 break;
972 case CS7:
973 new_data = 7;
974 break;
975 case CS8:
976 new_data = 8;
977 break;
978 default:
979 /* cuz we always need a default ... */
980 new_data = 5;
981 break;
982 }
983 if (cflag & CSTOPB) {
984 new_stop = 1;
985 }
986 if (cflag & PARENB) {
987 new_parity_enable = 1;
988 if (cflag & PARODD)
989 new_parity = 1;
990 }
991 baud = uart_get_baud_rate(the_port, new_termios, old_termios,
992 MIN_BAUD_SUPPORTED, MAX_BAUD_SUPPORTED);
993 DPRINT_CONFIG(("%s: returned baud %d for line %d\n", __func__, baud,
994 the_port->line));
995
996 if (!the_port->fifosize)
997 the_port->fifosize = FIFO_SIZE;
998 uart_update_timeout(the_port, cflag, baud);
999
1000 the_port->ignore_status_mask = N_ALL_INPUT;
1001
1002 state->port.tty->low_latency = 1;
1003
1004 if (iflag & IGNPAR)
1005 the_port->ignore_status_mask &= ~(N_PARITY_ERROR
1006 | N_FRAMING_ERROR);
1007 if (iflag & IGNBRK) {
1008 the_port->ignore_status_mask &= ~N_BREAK;
1009 if (iflag & IGNPAR)
1010 the_port->ignore_status_mask &= ~N_OVERRUN_ERROR;
1011 }
1012 if (!(cflag & CREAD)) {
1013 /* ignore everything */
1014 the_port->ignore_status_mask &= ~N_DATA_READY;
1015 }
1016
1017 if (cflag & CRTSCTS) {
1018 /* enable hardware flow control */
1019 port->ip_sscr |= SSCR_HFC_EN;
1020 }
1021 else {
1022 /* disable hardware flow control */
1023 port->ip_sscr &= ~SSCR_HFC_EN;
1024 }
1025 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1026
1027 /* Set the configuration and proper notification call */
1028 DPRINT_CONFIG(("%s : port 0x%p line %d cflag 0%o "
1029 "config_port(baud %d data %d stop %d penable %d "
1030 " parity %d), notification 0x%x\n",
1031 __func__, (void *)port, the_port->line, cflag, baud,
1032 new_data, new_stop, new_parity_enable, new_parity,
1033 the_port->ignore_status_mask));
1034
1035 if ((config_port(port, baud, /* baud */
1036 new_data, /* byte size */
1037 new_stop, /* stop bits */
1038 new_parity_enable, /* set parity */
1039 new_parity)) >= 0) { /* parity 1==odd */
1040 set_notification(port, the_port->ignore_status_mask, 1);
1041 }
1042}
1043
1044/**
1045 * ic3_startup_local - Start up the serial port - returns >= 0 if no errors
1046 * @the_port: Port to operate on
1047 */
1048static inline int ic3_startup_local(struct uart_port *the_port)
1049{
1050 struct ioc3_port *port;
1051
1052 if (!the_port) {
1053 NOT_PROGRESS();
1054 return -1;
1055 }
1056
1057 port = get_ioc3_port(the_port);
1058 if (!port) {
1059 NOT_PROGRESS();
1060 return -1;
1061 }
1062
1063 local_open(port);
1064
1065 /* set the protocol */
1066 ioc3_set_proto(port, IS_RS232(the_port->line) ? PROTO_RS232 :
1067 PROTO_RS422);
1068 return 0;
1069}
1070
1071/*
1072 * ioc3_cb_output_lowat - called when the output low water mark is hit
1073 * @port: port to output
1074 */
1075static void ioc3_cb_output_lowat(struct ioc3_port *port)
1076{
1077 unsigned long pflags;
1078
1079 /* the_port->lock is set on the call here */
1080 if (port->ip_port) {
1081 spin_lock_irqsave(&port->ip_port->lock, pflags);
1082 transmit_chars(port->ip_port);
1083 spin_unlock_irqrestore(&port->ip_port->lock, pflags);
1084 }
1085}
1086
1087/*
1088 * ioc3_cb_post_ncs - called for some basic errors
1089 * @port: port to use
1090 * @ncs: event
1091 */
1092static void ioc3_cb_post_ncs(struct uart_port *the_port, int ncs)
1093{
1094 struct uart_icount *icount;
1095
1096 icount = &the_port->icount;
1097
1098 if (ncs & NCS_BREAK)
1099 icount->brk++;
1100 if (ncs & NCS_FRAMING)
1101 icount->frame++;
1102 if (ncs & NCS_OVERRUN)
1103 icount->overrun++;
1104 if (ncs & NCS_PARITY)
1105 icount->parity++;
1106}
1107
1108/**
1109 * do_read - Read in bytes from the port. Return the number of bytes
1110 * actually read.
1111 * @the_port: port to use
1112 * @buf: place to put the stuff we read
1113 * @len: how big 'buf' is
1114 */
1115
1116static inline int do_read(struct uart_port *the_port, char *buf, int len)
1117{
1118 int prod_ptr, cons_ptr, total;
1119 struct ioc3_port *port = get_ioc3_port(the_port);
1120 struct ring *inring;
1121 struct ring_entry *entry;
1122 struct port_hooks *hooks = port->ip_hooks;
1123 int byte_num;
1124 char *sc;
1125 int loop_counter;
1126
1127 BUG_ON(!(len >= 0));
1128 BUG_ON(!port);
1129
1130 /* There is a nasty timing issue in the IOC3. When the rx_timer
1131 * expires or the rx_high condition arises, we take an interrupt.
1132 * At some point while servicing the interrupt, we read bytes from
1133 * the ring buffer and re-arm the rx_timer. However the rx_timer is
1134 * not started until the first byte is received *after* it is armed,
1135 * and any bytes pending in the rx construction buffers are not drained
1136 * to memory until either there are 4 bytes available or the rx_timer
1137 * expires. This leads to a potential situation where data is left
1138 * in the construction buffers forever - 1 to 3 bytes were received
1139 * after the interrupt was generated but before the rx_timer was
1140 * re-armed. At that point as long as no subsequent bytes are received
1141 * the timer will never be started and the bytes will remain in the
1142 * construction buffer forever. The solution is to execute a DRAIN
1143 * command after rearming the timer. This way any bytes received before
1144 * the DRAIN will be drained to memory, and any bytes received after
1145 * the DRAIN will start the TIMER and be drained when it expires.
1146 * Luckily, this only needs to be done when the DMA buffer is empty
1147 * since there is no requirement that this function return all
1148 * available data as long as it returns some.
1149 */
1150 /* Re-arm the timer */
1151
1152 writel(port->ip_rx_cons | SRCIR_ARM, &port->ip_serial_regs->srcir);
1153
1154 prod_ptr = readl(&port->ip_serial_regs->srpir) & PROD_CONS_MASK;
1155 cons_ptr = port->ip_rx_cons;
1156
1157 if (prod_ptr == cons_ptr) {
1158 int reset_dma = 0;
1159
1160 /* Input buffer appears empty, do a flush. */
1161
1162 /* DMA must be enabled for this to work. */
1163 if (!(port->ip_sscr & SSCR_DMA_EN)) {
1164 port->ip_sscr |= SSCR_DMA_EN;
1165 reset_dma = 1;
1166 }
1167
1168 /* Potential race condition: we must reload the srpir after
1169 * issuing the drain command, otherwise we could think the rx
1170 * buffer is empty, then take a very long interrupt, and when
1171 * we come back it's full and we wait forever for the drain to
1172 * complete.
1173 */
1174 writel(port->ip_sscr | SSCR_RX_DRAIN,
1175 &port->ip_serial_regs->sscr);
1176 prod_ptr = readl(&port->ip_serial_regs->srpir) & PROD_CONS_MASK;
1177
1178 /* We must not wait for the DRAIN to complete unless there are
1179 * at least 8 bytes (2 ring entries) available to receive the
1180 * data otherwise the DRAIN will never complete and we'll
1181 * deadlock here.
1182 * In fact, to make things easier, I'll just ignore the flush if
1183 * there is any data at all now available.
1184 */
1185 if (prod_ptr == cons_ptr) {
1186 loop_counter = 0;
1187 while (readl(&port->ip_serial_regs->sscr) &
1188 SSCR_RX_DRAIN) {
1189 loop_counter++;
1190 if (loop_counter > MAXITER)
1191 return -1;
1192 }
1193
1194 /* SIGH. We have to reload the prod_ptr *again* since
1195 * the drain may have caused it to change
1196 */
1197 prod_ptr = readl(&port->ip_serial_regs->srpir)
1198 & PROD_CONS_MASK;
1199 }
1200 if (reset_dma) {
1201 port->ip_sscr &= ~SSCR_DMA_EN;
1202 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1203 }
1204 }
1205 inring = port->ip_inring;
1206 port->ip_flags &= ~READ_ABORTED;
1207
1208 total = 0;
1209 loop_counter = 0xfffff; /* to avoid hangs */
1210
1211 /* Grab bytes from the hardware */
1212 while ((prod_ptr != cons_ptr) && (len > 0)) {
1213 entry = (struct ring_entry *)((caddr_t) inring + cons_ptr);
1214
1215 if (loop_counter-- <= 0) {
1216 printk(KERN_WARNING "IOC3 serial: "
1217 "possible hang condition/"
1218 "port stuck on read (line %d).\n",
1219 the_port->line);
1220 break;
1221 }
1222
1223 /* According to the producer pointer, this ring entry
1224 * must contain some data. But if the PIO happened faster
1225 * than the DMA, the data may not be available yet, so let's
1226 * wait until it arrives.
1227 */
1228 if ((entry->ring_allsc & RING_ANY_VALID) == 0) {
1229 /* Indicate the read is aborted so we don't disable
1230 * the interrupt thinking that the consumer is
1231 * congested.
1232 */
1233 port->ip_flags |= READ_ABORTED;
1234 len = 0;
1235 break;
1236 }
1237
1238 /* Load the bytes/status out of the ring entry */
1239 for (byte_num = 0; byte_num < 4 && len > 0; byte_num++) {
1240 sc = &(entry->ring_sc[byte_num]);
1241
1242 /* Check for change in modem state or overrun */
1243 if ((*sc & RXSB_MODEM_VALID)
1244 && (port->ip_notify & N_DDCD)) {
1245 /* Notify upper layer if DCD dropped */
1246 if ((port->ip_flags & DCD_ON)
1247 && !(*sc & RXSB_DCD)) {
1248 /* If we have already copied some data,
1249 * return it. We'll pick up the carrier
1250 * drop on the next pass. That way we
1251 * don't throw away the data that has
1252 * already been copied back to
1253 * the caller's buffer.
1254 */
1255 if (total > 0) {
1256 len = 0;
1257 break;
1258 }
1259 port->ip_flags &= ~DCD_ON;
1260
1261 /* Turn off this notification so the
1262 * carrier drop protocol won't see it
1263 * again when it does a read.
1264 */
1265 *sc &= ~RXSB_MODEM_VALID;
1266
1267 /* To keep things consistent, we need
1268 * to update the consumer pointer so
1269 * the next reader won't come in and
1270 * try to read the same ring entries
1271 * again. This must be done here before
1272 * the dcd change.
1273 */
1274
1275 if ((entry->ring_allsc & RING_ANY_VALID)
1276 == 0) {
1277 cons_ptr += (int)sizeof
1278 (struct ring_entry);
1279 cons_ptr &= PROD_CONS_MASK;
1280 }
1281 writel(cons_ptr,
1282 &port->ip_serial_regs->srcir);
1283 port->ip_rx_cons = cons_ptr;
1284
1285 /* Notify upper layer of carrier drop */
1286 if ((port->ip_notify & N_DDCD)
1287 && port->ip_port) {
1288 uart_handle_dcd_change
1289 (port->ip_port, 0);
1290 wake_up_interruptible
1291 (&the_port->state->
1292 port.delta_msr_wait);
1293 }
1294
1295 /* If we had any data to return, we
1296 * would have returned it above.
1297 */
1298 return 0;
1299 }
1300 }
1301 if (*sc & RXSB_MODEM_VALID) {
1302 /* Notify that an input overrun occurred */
1303 if ((*sc & RXSB_OVERRUN)
1304 && (port->ip_notify & N_OVERRUN_ERROR)) {
1305 ioc3_cb_post_ncs(the_port, NCS_OVERRUN);
1306 }
1307 /* Don't look at this byte again */
1308 *sc &= ~RXSB_MODEM_VALID;
1309 }
1310
1311 /* Check for valid data or RX errors */
1312 if ((*sc & RXSB_DATA_VALID) &&
1313 ((*sc & (RXSB_PAR_ERR
1314 | RXSB_FRAME_ERR | RXSB_BREAK))
1315 && (port->ip_notify & (N_PARITY_ERROR
1316 | N_FRAMING_ERROR
1317 | N_BREAK)))) {
1318 /* There is an error condition on the next byte.
1319 * If we have already transferred some bytes,
1320 * we'll stop here. Otherwise if this is the
1321 * first byte to be read, we'll just transfer
1322 * it alone after notifying the
1323 * upper layer of its status.
1324 */
1325 if (total > 0) {
1326 len = 0;
1327 break;
1328 } else {
1329 if ((*sc & RXSB_PAR_ERR) &&
1330 (port->
1331 ip_notify & N_PARITY_ERROR)) {
1332 ioc3_cb_post_ncs(the_port,
1333 NCS_PARITY);
1334 }
1335 if ((*sc & RXSB_FRAME_ERR) &&
1336 (port->
1337 ip_notify & N_FRAMING_ERROR)) {
1338 ioc3_cb_post_ncs(the_port,
1339 NCS_FRAMING);
1340 }
1341 if ((*sc & RXSB_BREAK)
1342 && (port->ip_notify & N_BREAK)) {
1343 ioc3_cb_post_ncs
1344 (the_port, NCS_BREAK);
1345 }
1346 len = 1;
1347 }
1348 }
1349 if (*sc & RXSB_DATA_VALID) {
1350 *sc &= ~RXSB_DATA_VALID;
1351 *buf = entry->ring_data[byte_num];
1352 buf++;
1353 len--;
1354 total++;
1355 }
1356 }
1357
1358 /* If we used up this entry entirely, go on to the next one,
1359 * otherwise we must have run out of buffer space, so
1360 * leave the consumer pointer here for the next read in case
1361 * there are still unread bytes in this entry.
1362 */
1363 if ((entry->ring_allsc & RING_ANY_VALID) == 0) {
1364 cons_ptr += (int)sizeof(struct ring_entry);
1365 cons_ptr &= PROD_CONS_MASK;
1366 }
1367 }
1368
1369 /* Update consumer pointer and re-arm rx timer interrupt */
1370 writel(cons_ptr, &port->ip_serial_regs->srcir);
1371 port->ip_rx_cons = cons_ptr;
1372
1373 /* If we have now dipped below the rx high water mark and we have
1374 * rx_high interrupt turned off, we can now turn it back on again.
1375 */
1376 if ((port->ip_flags & INPUT_HIGH) && (((prod_ptr - cons_ptr)
1377 & PROD_CONS_MASK) <
1378 ((port->
1379 ip_sscr &
1380 SSCR_RX_THRESHOLD)
1381 << PROD_CONS_PTR_OFF))) {
1382 port->ip_flags &= ~INPUT_HIGH;
1383 enable_intrs(port, hooks->intr_rx_high);
1384 }
1385 return total;
1386}
1387
1388/**
1389 * receive_chars - upper level read.
1390 * @the_port: port to read from
1391 */
1392static int receive_chars(struct uart_port *the_port)
1393{
1394 struct tty_struct *tty;
1395 unsigned char ch[MAX_CHARS];
1396 int read_count = 0, read_room, flip = 0;
1397 struct uart_state *state = the_port->state;
1398 struct ioc3_port *port = get_ioc3_port(the_port);
1399 unsigned long pflags;
1400
1401 /* Make sure all the pointers are "good" ones */
1402 if (!state)
1403 return 0;
1404 if (!state->port.tty)
1405 return 0;
1406
1407 if (!(port->ip_flags & INPUT_ENABLE))
1408 return 0;
1409
1410 spin_lock_irqsave(&the_port->lock, pflags);
1411 tty = state->port.tty;
1412
1413 read_count = do_read(the_port, ch, MAX_CHARS);
1414 if (read_count > 0) {
1415 flip = 1;
1416 read_room = tty_insert_flip_string(tty, ch, read_count);
1417 the_port->icount.rx += read_count;
1418 }
1419 spin_unlock_irqrestore(&the_port->lock, pflags);
1420
1421 if (flip)
1422 tty_flip_buffer_push(tty);
1423
1424 return read_count;
1425}
1426
1427/**
1428 * ioc3uart_intr_one - lowest level (per port) interrupt handler.
1429 * @is : submodule
1430 * @idd: driver data
1431 * @pending: interrupts to handle
1432 */
1433
1434static int inline
1435ioc3uart_intr_one(struct ioc3_submodule *is,
1436 struct ioc3_driver_data *idd,
1437 unsigned int pending)
1438{
1439 int port_num = GET_PORT_FROM_SIO_IR(pending);
1440 struct port_hooks *hooks;
1441 unsigned int rx_high_rd_aborted = 0;
1442 unsigned long flags;
1443 struct uart_port *the_port;
1444 struct ioc3_port *port;
1445 int loop_counter;
1446 struct ioc3_card *card_ptr;
1447 unsigned int sio_ir;
1448
1449 card_ptr = idd->data[is->id];
1450 port = card_ptr->ic_port[port_num].icp_port;
1451 hooks = port->ip_hooks;
1452
1453 /* Possible race condition here: The tx_mt interrupt bit may be
1454 * cleared without the intervention of the interrupt handler,
1455 * e.g. by a write. If the top level interrupt handler reads a
1456 * tx_mt, then some other processor does a write, starting up
1457 * output, then we come in here, see the tx_mt and stop DMA, the
1458 * output started by the other processor will hang. Thus we can
1459 * only rely on tx_mt being legitimate if it is read while the
1460 * port lock is held. Therefore this bit must be ignored in the
1461 * passed in interrupt mask which was read by the top level
1462 * interrupt handler since the port lock was not held at the time
1463 * it was read. We can only rely on this bit being accurate if it
1464 * is read while the port lock is held. So we'll clear it for now,
1465 * and reload it later once we have the port lock.
1466 */
1467
1468 sio_ir = pending & ~(hooks->intr_tx_mt);
1469 spin_lock_irqsave(&port->ip_lock, flags);
1470
1471 loop_counter = MAXITER; /* to avoid hangs */
1472
1473 do {
1474 uint32_t shadow;
1475
1476 if (loop_counter-- <= 0) {
1477 printk(KERN_WARNING "IOC3 serial: "
1478 "possible hang condition/"
1479 "port stuck on interrupt (line %d).\n",
1480 ((struct uart_port *)port->ip_port)->line);
1481 break;
1482 }
1483 /* Handle a DCD change */
1484 if (sio_ir & hooks->intr_delta_dcd) {
1485 ioc3_ack(is, idd, hooks->intr_delta_dcd);
1486 shadow = readl(&port->ip_serial_regs->shadow);
1487
1488 if ((port->ip_notify & N_DDCD)
1489 && (shadow & SHADOW_DCD)
1490 && (port->ip_port)) {
1491 the_port = port->ip_port;
1492 uart_handle_dcd_change(the_port,
1493 shadow & SHADOW_DCD);
1494 wake_up_interruptible
1495 (&the_port->state->port.delta_msr_wait);
1496 } else if ((port->ip_notify & N_DDCD)
1497 && !(shadow & SHADOW_DCD)) {
1498 /* Flag delta DCD/no DCD */
1499 uart_handle_dcd_change(port->ip_port,
1500 shadow & SHADOW_DCD);
1501 port->ip_flags |= DCD_ON;
1502 }
1503 }
1504
1505 /* Handle a CTS change */
1506 if (sio_ir & hooks->intr_delta_cts) {
1507 ioc3_ack(is, idd, hooks->intr_delta_cts);
1508 shadow = readl(&port->ip_serial_regs->shadow);
1509
1510 if ((port->ip_notify & N_DCTS) && (port->ip_port)) {
1511 the_port = port->ip_port;
1512 uart_handle_cts_change(the_port, shadow
1513 & SHADOW_CTS);
1514 wake_up_interruptible
1515 (&the_port->state->port.delta_msr_wait);
1516 }
1517 }
1518
1519 /* rx timeout interrupt. Must be some data available. Put this
1520 * before the check for rx_high since servicing this condition
1521 * may cause that condition to clear.
1522 */
1523 if (sio_ir & hooks->intr_rx_timer) {
1524 ioc3_ack(is, idd, hooks->intr_rx_timer);
1525 if ((port->ip_notify & N_DATA_READY)
1526 && (port->ip_port)) {
1527 receive_chars(port->ip_port);
1528 }
1529 }
1530
1531 /* rx high interrupt. Must be after rx_timer. */
1532 else if (sio_ir & hooks->intr_rx_high) {
1533 /* Data available, notify upper layer */
1534 if ((port->ip_notify & N_DATA_READY) && port->ip_port) {
1535 receive_chars(port->ip_port);
1536 }
1537
1538 /* We can't ACK this interrupt. If receive_chars didn't
1539 * cause the condition to clear, we'll have to disable
1540 * the interrupt until the data is drained.
1541 * If the read was aborted, don't disable the interrupt
1542 * as this may cause us to hang indefinitely. An
1543 * aborted read generally means that this interrupt
1544 * hasn't been delivered to the cpu yet anyway, even
1545 * though we see it as asserted when we read the sio_ir.
1546 */
1547 if ((sio_ir = PENDING(card_ptr, idd))
1548 & hooks->intr_rx_high) {
1549 if (port->ip_flags & READ_ABORTED) {
1550 rx_high_rd_aborted++;
1551 }
1552 else {
1553 card_ptr->ic_enable &= ~hooks->intr_rx_high;
1554 port->ip_flags |= INPUT_HIGH;
1555 }
1556 }
1557 }
1558
1559 /* We got a low water interrupt: notify upper layer to
1560 * send more data. Must come before tx_mt since servicing
1561 * this condition may cause that condition to clear.
1562 */
1563 if (sio_ir & hooks->intr_tx_explicit) {
1564 port->ip_flags &= ~LOWAT_WRITTEN;
1565 ioc3_ack(is, idd, hooks->intr_tx_explicit);
1566 if (port->ip_notify & N_OUTPUT_LOWAT)
1567 ioc3_cb_output_lowat(port);
1568 }
1569
1570 /* Handle tx_mt. Must come after tx_explicit. */
1571 else if (sio_ir & hooks->intr_tx_mt) {
1572 /* If we are expecting a lowat notification
1573 * and we get to this point it probably means that for
1574 * some reason the tx_explicit didn't work as expected
1575 * (that can legitimately happen if the output buffer is
1576 * filled up in just the right way).
1577 * So send the notification now.
1578 */
1579 if (port->ip_notify & N_OUTPUT_LOWAT) {
1580 ioc3_cb_output_lowat(port);
1581
1582 /* We need to reload the sio_ir since the lowat
1583 * call may have caused another write to occur,
1584 * clearing the tx_mt condition.
1585 */
1586 sio_ir = PENDING(card_ptr, idd);
1587 }
1588
1589 /* If the tx_mt condition still persists even after the
1590 * lowat call, we've got some work to do.
1591 */
1592 if (sio_ir & hooks->intr_tx_mt) {
1593 /* If we are not currently expecting DMA input,
1594 * and the transmitter has just gone idle,
1595 * there is no longer any reason for DMA, so
1596 * disable it.
1597 */
1598 if (!(port->ip_notify
1599 & (N_DATA_READY | N_DDCD))) {
1600 BUG_ON(!(port->ip_sscr
1601 & SSCR_DMA_EN));
1602 port->ip_sscr &= ~SSCR_DMA_EN;
1603 writel(port->ip_sscr,
1604 &port->ip_serial_regs->sscr);
1605 }
1606 /* Prevent infinite tx_mt interrupt */
1607 card_ptr->ic_enable &= ~hooks->intr_tx_mt;
1608 }
1609 }
1610 sio_ir = PENDING(card_ptr, idd);
1611
1612 /* if the read was aborted and only hooks->intr_rx_high,
1613 * clear hooks->intr_rx_high, so we do not loop forever.
1614 */
1615
1616 if (rx_high_rd_aborted && (sio_ir == hooks->intr_rx_high)) {
1617 sio_ir &= ~hooks->intr_rx_high;
1618 }
1619 } while (sio_ir & hooks->intr_all);
1620
1621 spin_unlock_irqrestore(&port->ip_lock, flags);
1622 ioc3_enable(is, idd, card_ptr->ic_enable);
1623 return 0;
1624}
1625
1626/**
1627 * ioc3uart_intr - field all serial interrupts
1628 * @is : submodule
1629 * @idd: driver data
1630 * @pending: interrupts to handle
1631 *
1632 */
1633
1634static int ioc3uart_intr(struct ioc3_submodule *is,
1635 struct ioc3_driver_data *idd,
1636 unsigned int pending)
1637{
1638 int ret = 0;
1639
1640 /*
1641 * The upper level interrupt handler sends interrupts for both ports
1642 * here. So we need to call for each port with its interrupts.
1643 */
1644
1645 if (pending & SIO_IR_SA)
1646 ret |= ioc3uart_intr_one(is, idd, pending & SIO_IR_SA);
1647 if (pending & SIO_IR_SB)
1648 ret |= ioc3uart_intr_one(is, idd, pending & SIO_IR_SB);
1649
1650 return ret;
1651}
1652
1653/**
1654 * ic3_type
1655 * @port: Port to operate with (we ignore since we only have one port)
1656 *
1657 */
1658static const char *ic3_type(struct uart_port *the_port)
1659{
1660 if (IS_RS232(the_port->line))
1661 return "SGI IOC3 Serial [rs232]";
1662 else
1663 return "SGI IOC3 Serial [rs422]";
1664}
1665
1666/**
1667 * ic3_tx_empty - Is the transmitter empty?
1668 * @port: Port to operate on
1669 *
1670 */
1671static unsigned int ic3_tx_empty(struct uart_port *the_port)
1672{
1673 unsigned int ret = 0;
1674 struct ioc3_port *port = get_ioc3_port(the_port);
1675
1676 if (readl(&port->ip_serial_regs->shadow) & SHADOW_TEMT)
1677 ret = TIOCSER_TEMT;
1678 return ret;
1679}
1680
1681/**
1682 * ic3_stop_tx - stop the transmitter
1683 * @port: Port to operate on
1684 *
1685 */
1686static void ic3_stop_tx(struct uart_port *the_port)
1687{
1688 struct ioc3_port *port = get_ioc3_port(the_port);
1689
1690 if (port)
1691 set_notification(port, N_OUTPUT_LOWAT, 0);
1692}
1693
1694/**
1695 * ic3_stop_rx - stop the receiver
1696 * @port: Port to operate on
1697 *
1698 */
1699static void ic3_stop_rx(struct uart_port *the_port)
1700{
1701 struct ioc3_port *port = get_ioc3_port(the_port);
1702
1703 if (port)
1704 port->ip_flags &= ~INPUT_ENABLE;
1705}
1706
1707/**
1708 * null_void_function
1709 * @port: Port to operate on
1710 *
1711 */
1712static void null_void_function(struct uart_port *the_port)
1713{
1714}
1715
1716/**
1717 * ic3_shutdown - shut down the port - free irq and disable
1718 * @port: port to shut down
1719 *
1720 */
1721static void ic3_shutdown(struct uart_port *the_port)
1722{
1723 unsigned long port_flags;
1724 struct ioc3_port *port;
1725 struct uart_state *state;
1726
1727 port = get_ioc3_port(the_port);
1728 if (!port)
1729 return;
1730
1731 state = the_port->state;
1732 wake_up_interruptible(&state->port.delta_msr_wait);
1733
1734 spin_lock_irqsave(&the_port->lock, port_flags);
1735 set_notification(port, N_ALL, 0);
1736 spin_unlock_irqrestore(&the_port->lock, port_flags);
1737}
1738
1739/**
1740 * ic3_set_mctrl - set control lines (dtr, rts, etc)
1741 * @port: Port to operate on
1742 * @mctrl: Lines to set/unset
1743 *
1744 */
1745static void ic3_set_mctrl(struct uart_port *the_port, unsigned int mctrl)
1746{
1747 unsigned char mcr = 0;
1748
1749 if (mctrl & TIOCM_RTS)
1750 mcr |= UART_MCR_RTS;
1751 if (mctrl & TIOCM_DTR)
1752 mcr |= UART_MCR_DTR;
1753 if (mctrl & TIOCM_OUT1)
1754 mcr |= UART_MCR_OUT1;
1755 if (mctrl & TIOCM_OUT2)
1756 mcr |= UART_MCR_OUT2;
1757 if (mctrl & TIOCM_LOOP)
1758 mcr |= UART_MCR_LOOP;
1759
1760 set_mcr(the_port, mcr, SHADOW_DTR);
1761}
1762
1763/**
1764 * ic3_get_mctrl - get control line info
1765 * @port: port to operate on
1766 *
1767 */
1768static unsigned int ic3_get_mctrl(struct uart_port *the_port)
1769{
1770 struct ioc3_port *port = get_ioc3_port(the_port);
1771 uint32_t shadow;
1772 unsigned int ret = 0;
1773
1774 if (!port)
1775 return 0;
1776
1777 shadow = readl(&port->ip_serial_regs->shadow);
1778 if (shadow & SHADOW_DCD)
1779 ret |= TIOCM_CD;
1780 if (shadow & SHADOW_DR)
1781 ret |= TIOCM_DSR;
1782 if (shadow & SHADOW_CTS)
1783 ret |= TIOCM_CTS;
1784 return ret;
1785}
1786
1787/**
1788 * ic3_start_tx - Start transmitter. Called with the_port->lock
1789 * @port: Port to operate on
1790 *
1791 */
1792static void ic3_start_tx(struct uart_port *the_port)
1793{
1794 struct ioc3_port *port = get_ioc3_port(the_port);
1795
1796 if (port) {
1797 set_notification(port, N_OUTPUT_LOWAT, 1);
1798 enable_intrs(port, port->ip_hooks->intr_tx_mt);
1799 }
1800}
1801
1802/**
1803 * ic3_break_ctl - handle breaks
1804 * @port: Port to operate on
1805 * @break_state: Break state
1806 *
1807 */
1808static void ic3_break_ctl(struct uart_port *the_port, int break_state)
1809{
1810}
1811
1812/**
1813 * ic3_startup - Start up the serial port - always return 0 (We're always on)
1814 * @port: Port to operate on
1815 *
1816 */
1817static int ic3_startup(struct uart_port *the_port)
1818{
1819 int retval;
1820 struct ioc3_port *port;
1821 struct ioc3_card *card_ptr;
1822 unsigned long port_flags;
1823
1824 if (!the_port) {
1825 NOT_PROGRESS();
1826 return -ENODEV;
1827 }
1828 port = get_ioc3_port(the_port);
1829 if (!port) {
1830 NOT_PROGRESS();
1831 return -ENODEV;
1832 }
1833 card_ptr = port->ip_card;
1834 port->ip_port = the_port;
1835
1836 if (!card_ptr) {
1837 NOT_PROGRESS();
1838 return -ENODEV;
1839 }
1840
1841 /* Start up the serial port */
1842 spin_lock_irqsave(&the_port->lock, port_flags);
1843 retval = ic3_startup_local(the_port);
1844 spin_unlock_irqrestore(&the_port->lock, port_flags);
1845 return retval;
1846}
1847
1848/**
1849 * ic3_set_termios - set termios stuff
1850 * @port: port to operate on
1851 * @termios: New settings
1852 * @termios: Old
1853 *
1854 */
1855static void
1856ic3_set_termios(struct uart_port *the_port,
1857 struct ktermios *termios, struct ktermios *old_termios)
1858{
1859 unsigned long port_flags;
1860
1861 spin_lock_irqsave(&the_port->lock, port_flags);
1862 ioc3_change_speed(the_port, termios, old_termios);
1863 spin_unlock_irqrestore(&the_port->lock, port_flags);
1864}
1865
1866/**
1867 * ic3_request_port - allocate resources for port - no op....
1868 * @port: port to operate on
1869 *
1870 */
1871static int ic3_request_port(struct uart_port *port)
1872{
1873 return 0;
1874}
1875
1876/* Associate the uart functions above - given to serial core */
1877static struct uart_ops ioc3_ops = {
1878 .tx_empty = ic3_tx_empty,
1879 .set_mctrl = ic3_set_mctrl,
1880 .get_mctrl = ic3_get_mctrl,
1881 .stop_tx = ic3_stop_tx,
1882 .start_tx = ic3_start_tx,
1883 .stop_rx = ic3_stop_rx,
1884 .enable_ms = null_void_function,
1885 .break_ctl = ic3_break_ctl,
1886 .startup = ic3_startup,
1887 .shutdown = ic3_shutdown,
1888 .set_termios = ic3_set_termios,
1889 .type = ic3_type,
1890 .release_port = null_void_function,
1891 .request_port = ic3_request_port,
1892};
1893
1894/*
1895 * Boot-time initialization code
1896 */
1897
1898static struct uart_driver ioc3_uart = {
1899 .owner = THIS_MODULE,
1900 .driver_name = "ioc3_serial",
1901 .dev_name = DEVICE_NAME,
1902 .major = DEVICE_MAJOR,
1903 .minor = DEVICE_MINOR,
1904 .nr = MAX_LOGICAL_PORTS
1905};
1906
1907/**
1908 * ioc3_serial_core_attach - register with serial core
1909 * This is done during pci probing
1910 * @is: submodule struct for this
1911 * @idd: handle for this card
1912 */
1913static inline int ioc3_serial_core_attach( struct ioc3_submodule *is,
1914 struct ioc3_driver_data *idd)
1915{
1916 struct ioc3_port *port;
1917 struct uart_port *the_port;
1918 struct ioc3_card *card_ptr = idd->data[is->id];
1919 int ii, phys_port;
1920 struct pci_dev *pdev = idd->pdev;
1921
1922 DPRINT_CONFIG(("%s: attach pdev 0x%p - card_ptr 0x%p\n",
1923 __func__, pdev, (void *)card_ptr));
1924
1925 if (!card_ptr)
1926 return -ENODEV;
1927
1928 /* once around for each logical port on this card */
1929 for (ii = 0; ii < LOGICAL_PORTS_PER_CARD; ii++) {
1930 phys_port = GET_PHYSICAL_PORT(ii);
1931 the_port = &card_ptr->ic_port[phys_port].
1932 icp_uart_port[GET_LOGICAL_PORT(ii)];
1933 port = card_ptr->ic_port[phys_port].icp_port;
1934 port->ip_port = the_port;
1935
1936 DPRINT_CONFIG(("%s: attach the_port 0x%p / port 0x%p [%d/%d]\n",
1937 __func__, (void *)the_port, (void *)port,
1938 phys_port, ii));
1939
1940 /* membase, iobase and mapbase just need to be non-0 */
1941 the_port->membase = (unsigned char __iomem *)1;
1942 the_port->iobase = (pdev->bus->number << 16) | ii;
1943 the_port->line = (Num_of_ioc3_cards << 2) | ii;
1944 the_port->mapbase = 1;
1945 the_port->type = PORT_16550A;
1946 the_port->fifosize = FIFO_SIZE;
1947 the_port->ops = &ioc3_ops;
1948 the_port->irq = idd->irq_io;
1949 the_port->dev = &pdev->dev;
1950
1951 if (uart_add_one_port(&ioc3_uart, the_port) < 0) {
1952 printk(KERN_WARNING
1953 "%s: unable to add port %d bus %d\n",
1954 __func__, the_port->line, pdev->bus->number);
1955 } else {
1956 DPRINT_CONFIG(("IOC3 serial port %d irq %d bus %d\n",
1957 the_port->line, the_port->irq, pdev->bus->number));
1958 }
1959
1960 /* all ports are rs232 for now */
1961 if (IS_PHYSICAL_PORT(ii))
1962 ioc3_set_proto(port, PROTO_RS232);
1963 }
1964 return 0;
1965}
1966
1967/**
1968 * ioc3uart_remove - register detach function
1969 * @is: submodule struct for this submodule
1970 * @idd: ioc3 driver data for this submodule
1971 */
1972
1973static int ioc3uart_remove(struct ioc3_submodule *is,
1974 struct ioc3_driver_data *idd)
1975{
1976 struct ioc3_card *card_ptr = idd->data[is->id];
1977 struct uart_port *the_port;
1978 struct ioc3_port *port;
1979 int ii;
1980
1981 if (card_ptr) {
1982 for (ii = 0; ii < LOGICAL_PORTS_PER_CARD; ii++) {
1983 the_port = &card_ptr->ic_port[GET_PHYSICAL_PORT(ii)].
1984 icp_uart_port[GET_LOGICAL_PORT(ii)];
1985 if (the_port)
1986 uart_remove_one_port(&ioc3_uart, the_port);
1987 port = card_ptr->ic_port[GET_PHYSICAL_PORT(ii)].icp_port;
1988 if (port && IS_PHYSICAL_PORT(ii)
1989 && (GET_PHYSICAL_PORT(ii) == 0)) {
1990 pci_free_consistent(port->ip_idd->pdev,
1991 TOTAL_RING_BUF_SIZE,
1992 (void *)port->ip_cpu_ringbuf,
1993 port->ip_dma_ringbuf);
1994 kfree(port);
1995 card_ptr->ic_port[GET_PHYSICAL_PORT(ii)].
1996 icp_port = NULL;
1997 }
1998 }
1999 kfree(card_ptr);
2000 idd->data[is->id] = NULL;
2001 }
2002 return 0;
2003}
2004
2005/**
2006 * ioc3uart_probe - card probe function called from shim driver
2007 * @is: submodule struct for this submodule
2008 * @idd: ioc3 driver data for this card
2009 */
2010
2011static int __devinit
2012ioc3uart_probe(struct ioc3_submodule *is, struct ioc3_driver_data *idd)
2013{
2014 struct pci_dev *pdev = idd->pdev;
2015 struct ioc3_card *card_ptr;
2016 int ret = 0;
2017 struct ioc3_port *port;
2018 struct ioc3_port *ports[PORTS_PER_CARD];
2019 int phys_port;
2020
2021 DPRINT_CONFIG(("%s (0x%p, 0x%p)\n", __func__, is, idd));
2022
2023 card_ptr = kzalloc(sizeof(struct ioc3_card), GFP_KERNEL);
2024 if (!card_ptr) {
2025 printk(KERN_WARNING "ioc3_attach_one"
2026 ": unable to get memory for the IOC3\n");
2027 return -ENOMEM;
2028 }
2029 idd->data[is->id] = card_ptr;
2030 Submodule_slot = is->id;
2031
2032 writel(((UARTA_BASE >> 3) << SIO_CR_SER_A_BASE_SHIFT) |
2033 ((UARTB_BASE >> 3) << SIO_CR_SER_B_BASE_SHIFT) |
2034 (0xf << SIO_CR_CMD_PULSE_SHIFT), &idd->vma->sio_cr);
2035
2036 pci_write_config_dword(pdev, PCI_LAT, 0xff00);
2037
2038 /* Enable serial port mode select generic PIO pins as outputs */
2039 ioc3_gpcr_set(idd, GPCR_UARTA_MODESEL | GPCR_UARTB_MODESEL);
2040
2041 /* Create port structures for each port */
2042 for (phys_port = 0; phys_port < PORTS_PER_CARD; phys_port++) {
2043 port = kzalloc(sizeof(struct ioc3_port), GFP_KERNEL);
2044 if (!port) {
2045 printk(KERN_WARNING
2046 "IOC3 serial memory not available for port\n");
2047 ret = -ENOMEM;
2048 goto out4;
2049 }
2050 spin_lock_init(&port->ip_lock);
2051
2052 /* we need to remember the previous ones, to point back to
2053 * them farther down - setting up the ring buffers.
2054 */
2055 ports[phys_port] = port;
2056
2057 /* init to something useful */
2058 card_ptr->ic_port[phys_port].icp_port = port;
2059 port->ip_is = is;
2060 port->ip_idd = idd;
2061 port->ip_baud = 9600;
2062 port->ip_card = card_ptr;
2063 port->ip_hooks = &hooks_array[phys_port];
2064
2065 /* Setup each port */
2066 if (phys_port == 0) {
2067 port->ip_serial_regs = &idd->vma->port_a;
2068 port->ip_uart_regs = &idd->vma->sregs.uarta;
2069
2070 DPRINT_CONFIG(("%s : Port A ip_serial_regs 0x%p "
2071 "ip_uart_regs 0x%p\n",
2072 __func__,
2073 (void *)port->ip_serial_regs,
2074 (void *)port->ip_uart_regs));
2075
2076 /* setup ring buffers */
2077 port->ip_cpu_ringbuf = pci_alloc_consistent(pdev,
2078 TOTAL_RING_BUF_SIZE, &port->ip_dma_ringbuf);
2079
2080 BUG_ON(!((((int64_t) port->ip_dma_ringbuf) &
2081 (TOTAL_RING_BUF_SIZE - 1)) == 0));
2082 port->ip_inring = RING(port, RX_A);
2083 port->ip_outring = RING(port, TX_A);
2084 DPRINT_CONFIG(("%s : Port A ip_cpu_ringbuf 0x%p "
2085 "ip_dma_ringbuf 0x%p, ip_inring 0x%p "
2086 "ip_outring 0x%p\n",
2087 __func__,
2088 (void *)port->ip_cpu_ringbuf,
2089 (void *)port->ip_dma_ringbuf,
2090 (void *)port->ip_inring,
2091 (void *)port->ip_outring));
2092 }
2093 else {
2094 port->ip_serial_regs = &idd->vma->port_b;
2095 port->ip_uart_regs = &idd->vma->sregs.uartb;
2096
2097 DPRINT_CONFIG(("%s : Port B ip_serial_regs 0x%p "
2098 "ip_uart_regs 0x%p\n",
2099 __func__,
2100 (void *)port->ip_serial_regs,
2101 (void *)port->ip_uart_regs));
2102
2103 /* share the ring buffers */
2104 port->ip_dma_ringbuf =
2105 ports[phys_port - 1]->ip_dma_ringbuf;
2106 port->ip_cpu_ringbuf =
2107 ports[phys_port - 1]->ip_cpu_ringbuf;
2108 port->ip_inring = RING(port, RX_B);
2109 port->ip_outring = RING(port, TX_B);
2110 DPRINT_CONFIG(("%s : Port B ip_cpu_ringbuf 0x%p "
2111 "ip_dma_ringbuf 0x%p, ip_inring 0x%p "
2112 "ip_outring 0x%p\n",
2113 __func__,
2114 (void *)port->ip_cpu_ringbuf,
2115 (void *)port->ip_dma_ringbuf,
2116 (void *)port->ip_inring,
2117 (void *)port->ip_outring));
2118 }
2119
2120 DPRINT_CONFIG(("%s : port %d [addr 0x%p] card_ptr 0x%p",
2121 __func__,
2122 phys_port, (void *)port, (void *)card_ptr));
2123 DPRINT_CONFIG((" ip_serial_regs 0x%p ip_uart_regs 0x%p\n",
2124 (void *)port->ip_serial_regs,
2125 (void *)port->ip_uart_regs));
2126
2127 /* Initialize the hardware for IOC3 */
2128 port_init(port);
2129
2130 DPRINT_CONFIG(("%s: phys_port %d port 0x%p inring 0x%p "
2131 "outring 0x%p\n",
2132 __func__,
2133 phys_port, (void *)port,
2134 (void *)port->ip_inring,
2135 (void *)port->ip_outring));
2136
2137 }
2138
2139 /* register port with the serial core */
2140
2141 if ((ret = ioc3_serial_core_attach(is, idd)))
2142 goto out4;
2143
2144 Num_of_ioc3_cards++;
2145
2146 return ret;
2147
2148 /* error exits that give back resources */
2149out4:
2150 kfree(card_ptr);
2151 return ret;
2152}
2153
2154static struct ioc3_submodule ioc3uart_ops = {
2155 .name = "IOC3uart",
2156 .probe = ioc3uart_probe,
2157 .remove = ioc3uart_remove,
2158 /* call .intr for both ports initially */
2159 .irq_mask = SIO_IR_SA | SIO_IR_SB,
2160 .intr = ioc3uart_intr,
2161 .owner = THIS_MODULE,
2162};
2163
2164/**
2165 * ioc3_detect - module init called,
2166 */
2167static int __init ioc3uart_init(void)
2168{
2169 int ret;
2170
2171 /* register with serial core */
2172 if ((ret = uart_register_driver(&ioc3_uart)) < 0) {
2173 printk(KERN_WARNING
2174 "%s: Couldn't register IOC3 uart serial driver\n",
2175 __func__);
2176 return ret;
2177 }
2178 ret = ioc3_register_submodule(&ioc3uart_ops);
2179 if (ret)
2180 uart_unregister_driver(&ioc3_uart);
2181 return ret;
2182}
2183
2184static void __exit ioc3uart_exit(void)
2185{
2186 ioc3_unregister_submodule(&ioc3uart_ops);
2187 uart_unregister_driver(&ioc3_uart);
2188}
2189
2190module_init(ioc3uart_init);
2191module_exit(ioc3uart_exit);
2192
2193MODULE_AUTHOR("Pat Gefre - Silicon Graphics Inc. (SGI) <pfg@sgi.com>");
2194MODULE_DESCRIPTION("Serial PCI driver module for SGI IOC3 card");
2195MODULE_LICENSE("GPL");
diff --git a/drivers/serial/ioc4_serial.c b/drivers/serial/ioc4_serial.c
deleted file mode 100644
index fcfe82653ac8..000000000000
--- a/drivers/serial/ioc4_serial.c
+++ /dev/null
@@ -1,2953 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003-2006 Silicon Graphics, Inc. All Rights Reserved.
7 */
8
9
10/*
11 * This file contains a module version of the ioc4 serial driver. This
12 * includes all the support functions needed (support functions, etc.)
13 * and the serial driver itself.
14 */
15#include <linux/errno.h>
16#include <linux/tty.h>
17#include <linux/serial.h>
18#include <linux/serialP.h>
19#include <linux/circ_buf.h>
20#include <linux/serial_reg.h>
21#include <linux/module.h>
22#include <linux/pci.h>
23#include <linux/ioc4.h>
24#include <linux/serial_core.h>
25#include <linux/slab.h>
26
27/*
28 * interesting things about the ioc4
29 */
30
31#define IOC4_NUM_SERIAL_PORTS 4 /* max ports per card */
32#define IOC4_NUM_CARDS 8 /* max cards per partition */
33
34#define GET_SIO_IR(_n) (_n == 0) ? (IOC4_SIO_IR_S0) : \
35 (_n == 1) ? (IOC4_SIO_IR_S1) : \
36 (_n == 2) ? (IOC4_SIO_IR_S2) : \
37 (IOC4_SIO_IR_S3)
38
39#define GET_OTHER_IR(_n) (_n == 0) ? (IOC4_OTHER_IR_S0_MEMERR) : \
40 (_n == 1) ? (IOC4_OTHER_IR_S1_MEMERR) : \
41 (_n == 2) ? (IOC4_OTHER_IR_S2_MEMERR) : \
42 (IOC4_OTHER_IR_S3_MEMERR)
43
44
45/*
46 * All IOC4 registers are 32 bits wide.
47 */
48
49/*
50 * PCI Memory Space Map
51 */
52#define IOC4_PCI_ERR_ADDR_L 0x000 /* Low Error Address */
53#define IOC4_PCI_ERR_ADDR_VLD (0x1 << 0)
54#define IOC4_PCI_ERR_ADDR_MST_ID_MSK (0xf << 1)
55#define IOC4_PCI_ERR_ADDR_MST_NUM_MSK (0xe << 1)
56#define IOC4_PCI_ERR_ADDR_MST_TYP_MSK (0x1 << 1)
57#define IOC4_PCI_ERR_ADDR_MUL_ERR (0x1 << 5)
58#define IOC4_PCI_ERR_ADDR_ADDR_MSK (0x3ffffff << 6)
59
60/* Interrupt types */
61#define IOC4_SIO_INTR_TYPE 0
62#define IOC4_OTHER_INTR_TYPE 1
63#define IOC4_NUM_INTR_TYPES 2
64
65/* Bitmasks for IOC4_SIO_IR, IOC4_SIO_IEC, and IOC4_SIO_IES */
66#define IOC4_SIO_IR_S0_TX_MT 0x00000001 /* Serial port 0 TX empty */
67#define IOC4_SIO_IR_S0_RX_FULL 0x00000002 /* Port 0 RX buf full */
68#define IOC4_SIO_IR_S0_RX_HIGH 0x00000004 /* Port 0 RX hiwat */
69#define IOC4_SIO_IR_S0_RX_TIMER 0x00000008 /* Port 0 RX timeout */
70#define IOC4_SIO_IR_S0_DELTA_DCD 0x00000010 /* Port 0 delta DCD */
71#define IOC4_SIO_IR_S0_DELTA_CTS 0x00000020 /* Port 0 delta CTS */
72#define IOC4_SIO_IR_S0_INT 0x00000040 /* Port 0 pass-thru intr */
73#define IOC4_SIO_IR_S0_TX_EXPLICIT 0x00000080 /* Port 0 explicit TX thru */
74#define IOC4_SIO_IR_S1_TX_MT 0x00000100 /* Serial port 1 */
75#define IOC4_SIO_IR_S1_RX_FULL 0x00000200 /* */
76#define IOC4_SIO_IR_S1_RX_HIGH 0x00000400 /* */
77#define IOC4_SIO_IR_S1_RX_TIMER 0x00000800 /* */
78#define IOC4_SIO_IR_S1_DELTA_DCD 0x00001000 /* */
79#define IOC4_SIO_IR_S1_DELTA_CTS 0x00002000 /* */
80#define IOC4_SIO_IR_S1_INT 0x00004000 /* */
81#define IOC4_SIO_IR_S1_TX_EXPLICIT 0x00008000 /* */
82#define IOC4_SIO_IR_S2_TX_MT 0x00010000 /* Serial port 2 */
83#define IOC4_SIO_IR_S2_RX_FULL 0x00020000 /* */
84#define IOC4_SIO_IR_S2_RX_HIGH 0x00040000 /* */
85#define IOC4_SIO_IR_S2_RX_TIMER 0x00080000 /* */
86#define IOC4_SIO_IR_S2_DELTA_DCD 0x00100000 /* */
87#define IOC4_SIO_IR_S2_DELTA_CTS 0x00200000 /* */
88#define IOC4_SIO_IR_S2_INT 0x00400000 /* */
89#define IOC4_SIO_IR_S2_TX_EXPLICIT 0x00800000 /* */
90#define IOC4_SIO_IR_S3_TX_MT 0x01000000 /* Serial port 3 */
91#define IOC4_SIO_IR_S3_RX_FULL 0x02000000 /* */
92#define IOC4_SIO_IR_S3_RX_HIGH 0x04000000 /* */
93#define IOC4_SIO_IR_S3_RX_TIMER 0x08000000 /* */
94#define IOC4_SIO_IR_S3_DELTA_DCD 0x10000000 /* */
95#define IOC4_SIO_IR_S3_DELTA_CTS 0x20000000 /* */
96#define IOC4_SIO_IR_S3_INT 0x40000000 /* */
97#define IOC4_SIO_IR_S3_TX_EXPLICIT 0x80000000 /* */
98
99/* Per device interrupt masks */
100#define IOC4_SIO_IR_S0 (IOC4_SIO_IR_S0_TX_MT | \
101 IOC4_SIO_IR_S0_RX_FULL | \
102 IOC4_SIO_IR_S0_RX_HIGH | \
103 IOC4_SIO_IR_S0_RX_TIMER | \
104 IOC4_SIO_IR_S0_DELTA_DCD | \
105 IOC4_SIO_IR_S0_DELTA_CTS | \
106 IOC4_SIO_IR_S0_INT | \
107 IOC4_SIO_IR_S0_TX_EXPLICIT)
108#define IOC4_SIO_IR_S1 (IOC4_SIO_IR_S1_TX_MT | \
109 IOC4_SIO_IR_S1_RX_FULL | \
110 IOC4_SIO_IR_S1_RX_HIGH | \
111 IOC4_SIO_IR_S1_RX_TIMER | \
112 IOC4_SIO_IR_S1_DELTA_DCD | \
113 IOC4_SIO_IR_S1_DELTA_CTS | \
114 IOC4_SIO_IR_S1_INT | \
115 IOC4_SIO_IR_S1_TX_EXPLICIT)
116#define IOC4_SIO_IR_S2 (IOC4_SIO_IR_S2_TX_MT | \
117 IOC4_SIO_IR_S2_RX_FULL | \
118 IOC4_SIO_IR_S2_RX_HIGH | \
119 IOC4_SIO_IR_S2_RX_TIMER | \
120 IOC4_SIO_IR_S2_DELTA_DCD | \
121 IOC4_SIO_IR_S2_DELTA_CTS | \
122 IOC4_SIO_IR_S2_INT | \
123 IOC4_SIO_IR_S2_TX_EXPLICIT)
124#define IOC4_SIO_IR_S3 (IOC4_SIO_IR_S3_TX_MT | \
125 IOC4_SIO_IR_S3_RX_FULL | \
126 IOC4_SIO_IR_S3_RX_HIGH | \
127 IOC4_SIO_IR_S3_RX_TIMER | \
128 IOC4_SIO_IR_S3_DELTA_DCD | \
129 IOC4_SIO_IR_S3_DELTA_CTS | \
130 IOC4_SIO_IR_S3_INT | \
131 IOC4_SIO_IR_S3_TX_EXPLICIT)
132
133/* Bitmasks for IOC4_OTHER_IR, IOC4_OTHER_IEC, and IOC4_OTHER_IES */
134#define IOC4_OTHER_IR_ATA_INT 0x00000001 /* ATAPI intr pass-thru */
135#define IOC4_OTHER_IR_ATA_MEMERR 0x00000002 /* ATAPI DMA PCI error */
136#define IOC4_OTHER_IR_S0_MEMERR 0x00000004 /* Port 0 PCI error */
137#define IOC4_OTHER_IR_S1_MEMERR 0x00000008 /* Port 1 PCI error */
138#define IOC4_OTHER_IR_S2_MEMERR 0x00000010 /* Port 2 PCI error */
139#define IOC4_OTHER_IR_S3_MEMERR 0x00000020 /* Port 3 PCI error */
140#define IOC4_OTHER_IR_KBD_INT 0x00000040 /* Keyboard/mouse */
141#define IOC4_OTHER_IR_RESERVED 0x007fff80 /* Reserved */
142#define IOC4_OTHER_IR_RT_INT 0x00800000 /* INT_OUT section output */
143#define IOC4_OTHER_IR_GEN_INT 0xff000000 /* Generic pins */
144
145#define IOC4_OTHER_IR_SER_MEMERR (IOC4_OTHER_IR_S0_MEMERR | IOC4_OTHER_IR_S1_MEMERR | \
146 IOC4_OTHER_IR_S2_MEMERR | IOC4_OTHER_IR_S3_MEMERR)
147
148/* Bitmasks for IOC4_SIO_CR */
149#define IOC4_SIO_CR_CMD_PULSE_SHIFT 0 /* byte bus strobe shift */
150#define IOC4_SIO_CR_ARB_DIAG_TX0 0x00000000
151#define IOC4_SIO_CR_ARB_DIAG_RX0 0x00000010
152#define IOC4_SIO_CR_ARB_DIAG_TX1 0x00000020
153#define IOC4_SIO_CR_ARB_DIAG_RX1 0x00000030
154#define IOC4_SIO_CR_ARB_DIAG_TX2 0x00000040
155#define IOC4_SIO_CR_ARB_DIAG_RX2 0x00000050
156#define IOC4_SIO_CR_ARB_DIAG_TX3 0x00000060
157#define IOC4_SIO_CR_ARB_DIAG_RX3 0x00000070
158#define IOC4_SIO_CR_SIO_DIAG_IDLE 0x00000080 /* 0 -> active request among
159 serial ports (ro) */
160/* Defs for some of the generic I/O pins */
161#define IOC4_GPCR_UART0_MODESEL 0x10 /* Pin is output to port 0
162 mode sel */
163#define IOC4_GPCR_UART1_MODESEL 0x20 /* Pin is output to port 1
164 mode sel */
165#define IOC4_GPCR_UART2_MODESEL 0x40 /* Pin is output to port 2
166 mode sel */
167#define IOC4_GPCR_UART3_MODESEL 0x80 /* Pin is output to port 3
168 mode sel */
169
170#define IOC4_GPPR_UART0_MODESEL_PIN 4 /* GIO pin controlling
171 uart 0 mode select */
172#define IOC4_GPPR_UART1_MODESEL_PIN 5 /* GIO pin controlling
173 uart 1 mode select */
174#define IOC4_GPPR_UART2_MODESEL_PIN 6 /* GIO pin controlling
175 uart 2 mode select */
176#define IOC4_GPPR_UART3_MODESEL_PIN 7 /* GIO pin controlling
177 uart 3 mode select */
178
179/* Bitmasks for serial RX status byte */
180#define IOC4_RXSB_OVERRUN 0x01 /* Char(s) lost */
181#define IOC4_RXSB_PAR_ERR 0x02 /* Parity error */
182#define IOC4_RXSB_FRAME_ERR 0x04 /* Framing error */
183#define IOC4_RXSB_BREAK 0x08 /* Break character */
184#define IOC4_RXSB_CTS 0x10 /* State of CTS */
185#define IOC4_RXSB_DCD 0x20 /* State of DCD */
186#define IOC4_RXSB_MODEM_VALID 0x40 /* DCD, CTS, and OVERRUN are valid */
187#define IOC4_RXSB_DATA_VALID 0x80 /* Data byte, FRAME_ERR PAR_ERR
188 * & BREAK valid */
189
190/* Bitmasks for serial TX control byte */
191#define IOC4_TXCB_INT_WHEN_DONE 0x20 /* Interrupt after this byte is sent */
192#define IOC4_TXCB_INVALID 0x00 /* Byte is invalid */
193#define IOC4_TXCB_VALID 0x40 /* Byte is valid */
194#define IOC4_TXCB_MCR 0x80 /* Data<7:0> to modem control reg */
195#define IOC4_TXCB_DELAY 0xc0 /* Delay data<7:0> mSec */
196
197/* Bitmasks for IOC4_SBBR_L */
198#define IOC4_SBBR_L_SIZE 0x00000001 /* 0 == 1KB rings, 1 == 4KB rings */
199
200/* Bitmasks for IOC4_SSCR_<3:0> */
201#define IOC4_SSCR_RX_THRESHOLD 0x000001ff /* Hiwater mark */
202#define IOC4_SSCR_TX_TIMER_BUSY 0x00010000 /* TX timer in progress */
203#define IOC4_SSCR_HFC_EN 0x00020000 /* Hardware flow control enabled */
204#define IOC4_SSCR_RX_RING_DCD 0x00040000 /* Post RX record on delta-DCD */
205#define IOC4_SSCR_RX_RING_CTS 0x00080000 /* Post RX record on delta-CTS */
206#define IOC4_SSCR_DIAG 0x00200000 /* Bypass clock divider for sim */
207#define IOC4_SSCR_RX_DRAIN 0x08000000 /* Drain RX buffer to memory */
208#define IOC4_SSCR_DMA_EN 0x10000000 /* Enable ring buffer DMA */
209#define IOC4_SSCR_DMA_PAUSE 0x20000000 /* Pause DMA */
210#define IOC4_SSCR_PAUSE_STATE 0x40000000 /* Sets when PAUSE takes effect */
211#define IOC4_SSCR_RESET 0x80000000 /* Reset DMA channels */
212
213/* All producer/comsumer pointers are the same bitfield */
214#define IOC4_PROD_CONS_PTR_4K 0x00000ff8 /* For 4K buffers */
215#define IOC4_PROD_CONS_PTR_1K 0x000003f8 /* For 1K buffers */
216#define IOC4_PROD_CONS_PTR_OFF 3
217
218/* Bitmasks for IOC4_SRCIR_<3:0> */
219#define IOC4_SRCIR_ARM 0x80000000 /* Arm RX timer */
220
221/* Bitmasks for IOC4_SHADOW_<3:0> */
222#define IOC4_SHADOW_DR 0x00000001 /* Data ready */
223#define IOC4_SHADOW_OE 0x00000002 /* Overrun error */
224#define IOC4_SHADOW_PE 0x00000004 /* Parity error */
225#define IOC4_SHADOW_FE 0x00000008 /* Framing error */
226#define IOC4_SHADOW_BI 0x00000010 /* Break interrupt */
227#define IOC4_SHADOW_THRE 0x00000020 /* Xmit holding register empty */
228#define IOC4_SHADOW_TEMT 0x00000040 /* Xmit shift register empty */
229#define IOC4_SHADOW_RFCE 0x00000080 /* Char in RX fifo has an error */
230#define IOC4_SHADOW_DCTS 0x00010000 /* Delta clear to send */
231#define IOC4_SHADOW_DDCD 0x00080000 /* Delta data carrier detect */
232#define IOC4_SHADOW_CTS 0x00100000 /* Clear to send */
233#define IOC4_SHADOW_DCD 0x00800000 /* Data carrier detect */
234#define IOC4_SHADOW_DTR 0x01000000 /* Data terminal ready */
235#define IOC4_SHADOW_RTS 0x02000000 /* Request to send */
236#define IOC4_SHADOW_OUT1 0x04000000 /* 16550 OUT1 bit */
237#define IOC4_SHADOW_OUT2 0x08000000 /* 16550 OUT2 bit */
238#define IOC4_SHADOW_LOOP 0x10000000 /* Loopback enabled */
239
240/* Bitmasks for IOC4_SRTR_<3:0> */
241#define IOC4_SRTR_CNT 0x00000fff /* Reload value for RX timer */
242#define IOC4_SRTR_CNT_VAL 0x0fff0000 /* Current value of RX timer */
243#define IOC4_SRTR_CNT_VAL_SHIFT 16
244#define IOC4_SRTR_HZ 16000 /* SRTR clock frequency */
245
246/* Serial port register map used for DMA and PIO serial I/O */
247struct ioc4_serialregs {
248 uint32_t sscr;
249 uint32_t stpir;
250 uint32_t stcir;
251 uint32_t srpir;
252 uint32_t srcir;
253 uint32_t srtr;
254 uint32_t shadow;
255};
256
257/* IOC4 UART register map */
258struct ioc4_uartregs {
259 char i4u_lcr;
260 union {
261 char iir; /* read only */
262 char fcr; /* write only */
263 } u3;
264 union {
265 char ier; /* DLAB == 0 */
266 char dlm; /* DLAB == 1 */
267 } u2;
268 union {
269 char rbr; /* read only, DLAB == 0 */
270 char thr; /* write only, DLAB == 0 */
271 char dll; /* DLAB == 1 */
272 } u1;
273 char i4u_scr;
274 char i4u_msr;
275 char i4u_lsr;
276 char i4u_mcr;
277};
278
279/* short names */
280#define i4u_dll u1.dll
281#define i4u_ier u2.ier
282#define i4u_dlm u2.dlm
283#define i4u_fcr u3.fcr
284
285/* Serial port registers used for DMA serial I/O */
286struct ioc4_serial {
287 uint32_t sbbr01_l;
288 uint32_t sbbr01_h;
289 uint32_t sbbr23_l;
290 uint32_t sbbr23_h;
291
292 struct ioc4_serialregs port_0;
293 struct ioc4_serialregs port_1;
294 struct ioc4_serialregs port_2;
295 struct ioc4_serialregs port_3;
296 struct ioc4_uartregs uart_0;
297 struct ioc4_uartregs uart_1;
298 struct ioc4_uartregs uart_2;
299 struct ioc4_uartregs uart_3;
300} ioc4_serial;
301
302/* UART clock speed */
303#define IOC4_SER_XIN_CLK_66 66666667
304#define IOC4_SER_XIN_CLK_33 33333333
305
306#define IOC4_W_IES 0
307#define IOC4_W_IEC 1
308
309typedef void ioc4_intr_func_f(void *, uint32_t);
310typedef ioc4_intr_func_f *ioc4_intr_func_t;
311
312static unsigned int Num_of_ioc4_cards;
313
314/* defining this will get you LOTS of great debug info */
315//#define DEBUG_INTERRUPTS
316#define DPRINT_CONFIG(_x...) ;
317//#define DPRINT_CONFIG(_x...) printk _x
318
319/* number of characters left in xmit buffer before we ask for more */
320#define WAKEUP_CHARS 256
321
322/* number of characters we want to transmit to the lower level at a time */
323#define IOC4_MAX_CHARS 256
324#define IOC4_FIFO_CHARS 255
325
326/* Device name we're using */
327#define DEVICE_NAME_RS232 "ttyIOC"
328#define DEVICE_NAME_RS422 "ttyAIOC"
329#define DEVICE_MAJOR 204
330#define DEVICE_MINOR_RS232 50
331#define DEVICE_MINOR_RS422 84
332
333
334/* register offsets */
335#define IOC4_SERIAL_OFFSET 0x300
336
337/* flags for next_char_state */
338#define NCS_BREAK 0x1
339#define NCS_PARITY 0x2
340#define NCS_FRAMING 0x4
341#define NCS_OVERRUN 0x8
342
343/* cause we need SOME parameters ... */
344#define MIN_BAUD_SUPPORTED 1200
345#define MAX_BAUD_SUPPORTED 115200
346
347/* protocol types supported */
348#define PROTO_RS232 3
349#define PROTO_RS422 7
350
351/* Notification types */
352#define N_DATA_READY 0x01
353#define N_OUTPUT_LOWAT 0x02
354#define N_BREAK 0x04
355#define N_PARITY_ERROR 0x08
356#define N_FRAMING_ERROR 0x10
357#define N_OVERRUN_ERROR 0x20
358#define N_DDCD 0x40
359#define N_DCTS 0x80
360
361#define N_ALL_INPUT (N_DATA_READY | N_BREAK | \
362 N_PARITY_ERROR | N_FRAMING_ERROR | \
363 N_OVERRUN_ERROR | N_DDCD | N_DCTS)
364
365#define N_ALL_OUTPUT N_OUTPUT_LOWAT
366
367#define N_ALL_ERRORS (N_PARITY_ERROR | N_FRAMING_ERROR | N_OVERRUN_ERROR)
368
369#define N_ALL (N_DATA_READY | N_OUTPUT_LOWAT | N_BREAK | \
370 N_PARITY_ERROR | N_FRAMING_ERROR | \
371 N_OVERRUN_ERROR | N_DDCD | N_DCTS)
372
373#define SER_DIVISOR(_x, clk) (((clk) + (_x) * 8) / ((_x) * 16))
374#define DIVISOR_TO_BAUD(div, clk) ((clk) / 16 / (div))
375
376/* Some masks */
377#define LCR_MASK_BITS_CHAR (UART_LCR_WLEN5 | UART_LCR_WLEN6 \
378 | UART_LCR_WLEN7 | UART_LCR_WLEN8)
379#define LCR_MASK_STOP_BITS (UART_LCR_STOP)
380
381#define PENDING(_p) (readl(&(_p)->ip_mem->sio_ir.raw) & _p->ip_ienb)
382#define READ_SIO_IR(_p) readl(&(_p)->ip_mem->sio_ir.raw)
383
384/* Default to 4k buffers */
385#ifdef IOC4_1K_BUFFERS
386#define RING_BUF_SIZE 1024
387#define IOC4_BUF_SIZE_BIT 0
388#define PROD_CONS_MASK IOC4_PROD_CONS_PTR_1K
389#else
390#define RING_BUF_SIZE 4096
391#define IOC4_BUF_SIZE_BIT IOC4_SBBR_L_SIZE
392#define PROD_CONS_MASK IOC4_PROD_CONS_PTR_4K
393#endif
394
395#define TOTAL_RING_BUF_SIZE (RING_BUF_SIZE * 4)
396
397/*
398 * This is the entry saved by the driver - one per card
399 */
400
401#define UART_PORT_MIN 0
402#define UART_PORT_RS232 UART_PORT_MIN
403#define UART_PORT_RS422 1
404#define UART_PORT_COUNT 2 /* one for each mode */
405
406struct ioc4_control {
407 int ic_irq;
408 struct {
409 /* uart ports are allocated here - 1 for rs232, 1 for rs422 */
410 struct uart_port icp_uart_port[UART_PORT_COUNT];
411 /* Handy reference material */
412 struct ioc4_port *icp_port;
413 } ic_port[IOC4_NUM_SERIAL_PORTS];
414 struct ioc4_soft *ic_soft;
415};
416
417/*
418 * per-IOC4 data structure
419 */
420#define MAX_IOC4_INTR_ENTS (8 * sizeof(uint32_t))
421struct ioc4_soft {
422 struct ioc4_misc_regs __iomem *is_ioc4_misc_addr;
423 struct ioc4_serial __iomem *is_ioc4_serial_addr;
424
425 /* Each interrupt type has an entry in the array */
426 struct ioc4_intr_type {
427
428 /*
429 * Each in-use entry in this array contains at least
430 * one nonzero bit in sd_bits; no two entries in this
431 * array have overlapping sd_bits values.
432 */
433 struct ioc4_intr_info {
434 uint32_t sd_bits;
435 ioc4_intr_func_f *sd_intr;
436 void *sd_info;
437 } is_intr_info[MAX_IOC4_INTR_ENTS];
438
439 /* Number of entries active in the above array */
440 atomic_t is_num_intrs;
441 } is_intr_type[IOC4_NUM_INTR_TYPES];
442
443 /* is_ir_lock must be held while
444 * modifying sio_ie values, so
445 * we can be sure that sio_ie is
446 * not changing when we read it
447 * along with sio_ir.
448 */
449 spinlock_t is_ir_lock; /* SIO_IE[SC] mod lock */
450};
451
452/* Local port info for each IOC4 serial ports */
453struct ioc4_port {
454 struct uart_port *ip_port; /* current active port ptr */
455 /* Ptrs for all ports */
456 struct uart_port *ip_all_ports[UART_PORT_COUNT];
457 /* Back ptrs for this port */
458 struct ioc4_control *ip_control;
459 struct pci_dev *ip_pdev;
460 struct ioc4_soft *ip_ioc4_soft;
461
462 /* pci mem addresses */
463 struct ioc4_misc_regs __iomem *ip_mem;
464 struct ioc4_serial __iomem *ip_serial;
465 struct ioc4_serialregs __iomem *ip_serial_regs;
466 struct ioc4_uartregs __iomem *ip_uart_regs;
467
468 /* Ring buffer page for this port */
469 dma_addr_t ip_dma_ringbuf;
470 /* vaddr of ring buffer */
471 struct ring_buffer *ip_cpu_ringbuf;
472
473 /* Rings for this port */
474 struct ring *ip_inring;
475 struct ring *ip_outring;
476
477 /* Hook to port specific values */
478 struct hooks *ip_hooks;
479
480 spinlock_t ip_lock;
481
482 /* Various rx/tx parameters */
483 int ip_baud;
484 int ip_tx_lowat;
485 int ip_rx_timeout;
486
487 /* Copy of notification bits */
488 int ip_notify;
489
490 /* Shadow copies of various registers so we don't need to PIO
491 * read them constantly
492 */
493 uint32_t ip_ienb; /* Enabled interrupts */
494 uint32_t ip_sscr;
495 uint32_t ip_tx_prod;
496 uint32_t ip_rx_cons;
497 int ip_pci_bus_speed;
498 unsigned char ip_flags;
499};
500
501/* tx low water mark. We need to notify the driver whenever tx is getting
502 * close to empty so it can refill the tx buffer and keep things going.
503 * Let's assume that if we interrupt 1 ms before the tx goes idle, we'll
504 * have no trouble getting in more chars in time (I certainly hope so).
505 */
506#define TX_LOWAT_LATENCY 1000
507#define TX_LOWAT_HZ (1000000 / TX_LOWAT_LATENCY)
508#define TX_LOWAT_CHARS(baud) (baud / 10 / TX_LOWAT_HZ)
509
510/* Flags per port */
511#define INPUT_HIGH 0x01
512#define DCD_ON 0x02
513#define LOWAT_WRITTEN 0x04
514#define READ_ABORTED 0x08
515#define PORT_ACTIVE 0x10
516#define PORT_INACTIVE 0 /* This is the value when "off" */
517
518
519/* Since each port has different register offsets and bitmasks
520 * for everything, we'll store those that we need in tables so we
521 * don't have to be constantly checking the port we are dealing with.
522 */
523struct hooks {
524 uint32_t intr_delta_dcd;
525 uint32_t intr_delta_cts;
526 uint32_t intr_tx_mt;
527 uint32_t intr_rx_timer;
528 uint32_t intr_rx_high;
529 uint32_t intr_tx_explicit;
530 uint32_t intr_dma_error;
531 uint32_t intr_clear;
532 uint32_t intr_all;
533 int rs422_select_pin;
534};
535
536static struct hooks hooks_array[IOC4_NUM_SERIAL_PORTS] = {
537 /* Values for port 0 */
538 {
539 IOC4_SIO_IR_S0_DELTA_DCD, IOC4_SIO_IR_S0_DELTA_CTS,
540 IOC4_SIO_IR_S0_TX_MT, IOC4_SIO_IR_S0_RX_TIMER,
541 IOC4_SIO_IR_S0_RX_HIGH, IOC4_SIO_IR_S0_TX_EXPLICIT,
542 IOC4_OTHER_IR_S0_MEMERR,
543 (IOC4_SIO_IR_S0_TX_MT | IOC4_SIO_IR_S0_RX_FULL |
544 IOC4_SIO_IR_S0_RX_HIGH | IOC4_SIO_IR_S0_RX_TIMER |
545 IOC4_SIO_IR_S0_DELTA_DCD | IOC4_SIO_IR_S0_DELTA_CTS |
546 IOC4_SIO_IR_S0_INT | IOC4_SIO_IR_S0_TX_EXPLICIT),
547 IOC4_SIO_IR_S0, IOC4_GPPR_UART0_MODESEL_PIN,
548 },
549
550 /* Values for port 1 */
551 {
552 IOC4_SIO_IR_S1_DELTA_DCD, IOC4_SIO_IR_S1_DELTA_CTS,
553 IOC4_SIO_IR_S1_TX_MT, IOC4_SIO_IR_S1_RX_TIMER,
554 IOC4_SIO_IR_S1_RX_HIGH, IOC4_SIO_IR_S1_TX_EXPLICIT,
555 IOC4_OTHER_IR_S1_MEMERR,
556 (IOC4_SIO_IR_S1_TX_MT | IOC4_SIO_IR_S1_RX_FULL |
557 IOC4_SIO_IR_S1_RX_HIGH | IOC4_SIO_IR_S1_RX_TIMER |
558 IOC4_SIO_IR_S1_DELTA_DCD | IOC4_SIO_IR_S1_DELTA_CTS |
559 IOC4_SIO_IR_S1_INT | IOC4_SIO_IR_S1_TX_EXPLICIT),
560 IOC4_SIO_IR_S1, IOC4_GPPR_UART1_MODESEL_PIN,
561 },
562
563 /* Values for port 2 */
564 {
565 IOC4_SIO_IR_S2_DELTA_DCD, IOC4_SIO_IR_S2_DELTA_CTS,
566 IOC4_SIO_IR_S2_TX_MT, IOC4_SIO_IR_S2_RX_TIMER,
567 IOC4_SIO_IR_S2_RX_HIGH, IOC4_SIO_IR_S2_TX_EXPLICIT,
568 IOC4_OTHER_IR_S2_MEMERR,
569 (IOC4_SIO_IR_S2_TX_MT | IOC4_SIO_IR_S2_RX_FULL |
570 IOC4_SIO_IR_S2_RX_HIGH | IOC4_SIO_IR_S2_RX_TIMER |
571 IOC4_SIO_IR_S2_DELTA_DCD | IOC4_SIO_IR_S2_DELTA_CTS |
572 IOC4_SIO_IR_S2_INT | IOC4_SIO_IR_S2_TX_EXPLICIT),
573 IOC4_SIO_IR_S2, IOC4_GPPR_UART2_MODESEL_PIN,
574 },
575
576 /* Values for port 3 */
577 {
578 IOC4_SIO_IR_S3_DELTA_DCD, IOC4_SIO_IR_S3_DELTA_CTS,
579 IOC4_SIO_IR_S3_TX_MT, IOC4_SIO_IR_S3_RX_TIMER,
580 IOC4_SIO_IR_S3_RX_HIGH, IOC4_SIO_IR_S3_TX_EXPLICIT,
581 IOC4_OTHER_IR_S3_MEMERR,
582 (IOC4_SIO_IR_S3_TX_MT | IOC4_SIO_IR_S3_RX_FULL |
583 IOC4_SIO_IR_S3_RX_HIGH | IOC4_SIO_IR_S3_RX_TIMER |
584 IOC4_SIO_IR_S3_DELTA_DCD | IOC4_SIO_IR_S3_DELTA_CTS |
585 IOC4_SIO_IR_S3_INT | IOC4_SIO_IR_S3_TX_EXPLICIT),
586 IOC4_SIO_IR_S3, IOC4_GPPR_UART3_MODESEL_PIN,
587 }
588};
589
590/* A ring buffer entry */
591struct ring_entry {
592 union {
593 struct {
594 uint32_t alldata;
595 uint32_t allsc;
596 } all;
597 struct {
598 char data[4]; /* data bytes */
599 char sc[4]; /* status/control */
600 } s;
601 } u;
602};
603
604/* Test the valid bits in any of the 4 sc chars using "allsc" member */
605#define RING_ANY_VALID \
606 ((uint32_t)(IOC4_RXSB_MODEM_VALID | IOC4_RXSB_DATA_VALID) * 0x01010101)
607
608#define ring_sc u.s.sc
609#define ring_data u.s.data
610#define ring_allsc u.all.allsc
611
612/* Number of entries per ring buffer. */
613#define ENTRIES_PER_RING (RING_BUF_SIZE / (int) sizeof(struct ring_entry))
614
615/* An individual ring */
616struct ring {
617 struct ring_entry entries[ENTRIES_PER_RING];
618};
619
620/* The whole enchilada */
621struct ring_buffer {
622 struct ring TX_0_OR_2;
623 struct ring RX_0_OR_2;
624 struct ring TX_1_OR_3;
625 struct ring RX_1_OR_3;
626};
627
628/* Get a ring from a port struct */
629#define RING(_p, _wh) &(((struct ring_buffer *)((_p)->ip_cpu_ringbuf))->_wh)
630
631/* Infinite loop detection.
632 */
633#define MAXITER 10000000
634
635/* Prototypes */
636static void receive_chars(struct uart_port *);
637static void handle_intr(void *arg, uint32_t sio_ir);
638
639/*
640 * port_is_active - determines if this port is currently active
641 * @port: ptr to soft struct for this port
642 * @uart_port: uart port to test for
643 */
644static inline int port_is_active(struct ioc4_port *port,
645 struct uart_port *uart_port)
646{
647 if (port) {
648 if ((port->ip_flags & PORT_ACTIVE)
649 && (port->ip_port == uart_port))
650 return 1;
651 }
652 return 0;
653}
654
655
656/**
657 * write_ireg - write the interrupt regs
658 * @ioc4_soft: ptr to soft struct for this port
659 * @val: value to write
660 * @which: which register
661 * @type: which ireg set
662 */
663static inline void
664write_ireg(struct ioc4_soft *ioc4_soft, uint32_t val, int which, int type)
665{
666 struct ioc4_misc_regs __iomem *mem = ioc4_soft->is_ioc4_misc_addr;
667 unsigned long flags;
668
669 spin_lock_irqsave(&ioc4_soft->is_ir_lock, flags);
670
671 switch (type) {
672 case IOC4_SIO_INTR_TYPE:
673 switch (which) {
674 case IOC4_W_IES:
675 writel(val, &mem->sio_ies.raw);
676 break;
677
678 case IOC4_W_IEC:
679 writel(val, &mem->sio_iec.raw);
680 break;
681 }
682 break;
683
684 case IOC4_OTHER_INTR_TYPE:
685 switch (which) {
686 case IOC4_W_IES:
687 writel(val, &mem->other_ies.raw);
688 break;
689
690 case IOC4_W_IEC:
691 writel(val, &mem->other_iec.raw);
692 break;
693 }
694 break;
695
696 default:
697 break;
698 }
699 spin_unlock_irqrestore(&ioc4_soft->is_ir_lock, flags);
700}
701
702/**
703 * set_baud - Baud rate setting code
704 * @port: port to set
705 * @baud: baud rate to use
706 */
707static int set_baud(struct ioc4_port *port, int baud)
708{
709 int actual_baud;
710 int diff;
711 int lcr;
712 unsigned short divisor;
713 struct ioc4_uartregs __iomem *uart;
714
715 divisor = SER_DIVISOR(baud, port->ip_pci_bus_speed);
716 if (!divisor)
717 return 1;
718 actual_baud = DIVISOR_TO_BAUD(divisor, port->ip_pci_bus_speed);
719
720 diff = actual_baud - baud;
721 if (diff < 0)
722 diff = -diff;
723
724 /* If we're within 1%, we've found a match */
725 if (diff * 100 > actual_baud)
726 return 1;
727
728 uart = port->ip_uart_regs;
729 lcr = readb(&uart->i4u_lcr);
730 writeb(lcr | UART_LCR_DLAB, &uart->i4u_lcr);
731 writeb((unsigned char)divisor, &uart->i4u_dll);
732 writeb((unsigned char)(divisor >> 8), &uart->i4u_dlm);
733 writeb(lcr, &uart->i4u_lcr);
734 return 0;
735}
736
737
738/**
739 * get_ioc4_port - given a uart port, return the control structure
740 * @port: uart port
741 * @set: set this port as current
742 */
743static struct ioc4_port *get_ioc4_port(struct uart_port *the_port, int set)
744{
745 struct ioc4_driver_data *idd = dev_get_drvdata(the_port->dev);
746 struct ioc4_control *control = idd->idd_serial_data;
747 struct ioc4_port *port;
748 int port_num, port_type;
749
750 if (control) {
751 for ( port_num = 0; port_num < IOC4_NUM_SERIAL_PORTS;
752 port_num++ ) {
753 port = control->ic_port[port_num].icp_port;
754 if (!port)
755 continue;
756 for (port_type = UART_PORT_MIN;
757 port_type < UART_PORT_COUNT;
758 port_type++) {
759 if (the_port == port->ip_all_ports
760 [port_type]) {
761 /* set local copy */
762 if (set) {
763 port->ip_port = the_port;
764 }
765 return port;
766 }
767 }
768 }
769 }
770 return NULL;
771}
772
773/* The IOC4 hardware provides no atomic way to determine if interrupts
774 * are pending since two reads are required to do so. The handler must
775 * read the SIO_IR and the SIO_IES, and take the logical and of the
776 * two. When this value is zero, all interrupts have been serviced and
777 * the handler may return.
778 *
779 * This has the unfortunate "hole" that, if some other CPU or
780 * some other thread or some higher level interrupt manages to
781 * modify SIO_IE between our reads of SIO_IR and SIO_IE, we may
782 * think we have observed SIO_IR&SIO_IE==0 when in fact this
783 * condition never really occurred.
784 *
785 * To solve this, we use a simple spinlock that must be held
786 * whenever modifying SIO_IE; holding this lock while observing
787 * both SIO_IR and SIO_IE guarantees that we do not falsely
788 * conclude that no enabled interrupts are pending.
789 */
790
791static inline uint32_t
792pending_intrs(struct ioc4_soft *soft, int type)
793{
794 struct ioc4_misc_regs __iomem *mem = soft->is_ioc4_misc_addr;
795 unsigned long flag;
796 uint32_t intrs = 0;
797
798 BUG_ON(!((type == IOC4_SIO_INTR_TYPE)
799 || (type == IOC4_OTHER_INTR_TYPE)));
800
801 spin_lock_irqsave(&soft->is_ir_lock, flag);
802
803 switch (type) {
804 case IOC4_SIO_INTR_TYPE:
805 intrs = readl(&mem->sio_ir.raw) & readl(&mem->sio_ies.raw);
806 break;
807
808 case IOC4_OTHER_INTR_TYPE:
809 intrs = readl(&mem->other_ir.raw) & readl(&mem->other_ies.raw);
810
811 /* Don't process any ATA interrupte */
812 intrs &= ~(IOC4_OTHER_IR_ATA_INT | IOC4_OTHER_IR_ATA_MEMERR);
813 break;
814
815 default:
816 break;
817 }
818 spin_unlock_irqrestore(&soft->is_ir_lock, flag);
819 return intrs;
820}
821
822/**
823 * port_init - Initialize the sio and ioc4 hardware for a given port
824 * called per port from attach...
825 * @port: port to initialize
826 */
827static int inline port_init(struct ioc4_port *port)
828{
829 uint32_t sio_cr;
830 struct hooks *hooks = port->ip_hooks;
831 struct ioc4_uartregs __iomem *uart;
832
833 /* Idle the IOC4 serial interface */
834 writel(IOC4_SSCR_RESET, &port->ip_serial_regs->sscr);
835
836 /* Wait until any pending bus activity for this port has ceased */
837 do
838 sio_cr = readl(&port->ip_mem->sio_cr.raw);
839 while (!(sio_cr & IOC4_SIO_CR_SIO_DIAG_IDLE));
840
841 /* Finish reset sequence */
842 writel(0, &port->ip_serial_regs->sscr);
843
844 /* Once RESET is done, reload cached tx_prod and rx_cons values
845 * and set rings to empty by making prod == cons
846 */
847 port->ip_tx_prod = readl(&port->ip_serial_regs->stcir) & PROD_CONS_MASK;
848 writel(port->ip_tx_prod, &port->ip_serial_regs->stpir);
849 port->ip_rx_cons = readl(&port->ip_serial_regs->srpir) & PROD_CONS_MASK;
850 writel(port->ip_rx_cons | IOC4_SRCIR_ARM, &port->ip_serial_regs->srcir);
851
852 /* Disable interrupts for this 16550 */
853 uart = port->ip_uart_regs;
854 writeb(0, &uart->i4u_lcr);
855 writeb(0, &uart->i4u_ier);
856
857 /* Set the default baud */
858 set_baud(port, port->ip_baud);
859
860 /* Set line control to 8 bits no parity */
861 writeb(UART_LCR_WLEN8 | 0, &uart->i4u_lcr);
862 /* UART_LCR_STOP == 1 stop */
863
864 /* Enable the FIFOs */
865 writeb(UART_FCR_ENABLE_FIFO, &uart->i4u_fcr);
866 /* then reset 16550 FIFOs */
867 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
868 &uart->i4u_fcr);
869
870 /* Clear modem control register */
871 writeb(0, &uart->i4u_mcr);
872
873 /* Clear deltas in modem status register */
874 readb(&uart->i4u_msr);
875
876 /* Only do this once per port pair */
877 if (port->ip_hooks == &hooks_array[0]
878 || port->ip_hooks == &hooks_array[2]) {
879 unsigned long ring_pci_addr;
880 uint32_t __iomem *sbbr_l;
881 uint32_t __iomem *sbbr_h;
882
883 if (port->ip_hooks == &hooks_array[0]) {
884 sbbr_l = &port->ip_serial->sbbr01_l;
885 sbbr_h = &port->ip_serial->sbbr01_h;
886 } else {
887 sbbr_l = &port->ip_serial->sbbr23_l;
888 sbbr_h = &port->ip_serial->sbbr23_h;
889 }
890
891 ring_pci_addr = (unsigned long __iomem)port->ip_dma_ringbuf;
892 DPRINT_CONFIG(("%s: ring_pci_addr 0x%lx\n",
893 __func__, ring_pci_addr));
894
895 writel((unsigned int)((uint64_t)ring_pci_addr >> 32), sbbr_h);
896 writel((unsigned int)ring_pci_addr | IOC4_BUF_SIZE_BIT, sbbr_l);
897 }
898
899 /* Set the receive timeout value to 10 msec */
900 writel(IOC4_SRTR_HZ / 100, &port->ip_serial_regs->srtr);
901
902 /* Set rx threshold, enable DMA */
903 /* Set high water mark at 3/4 of full ring */
904 port->ip_sscr = (ENTRIES_PER_RING * 3 / 4);
905 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
906
907 /* Disable and clear all serial related interrupt bits */
908 write_ireg(port->ip_ioc4_soft, hooks->intr_clear,
909 IOC4_W_IEC, IOC4_SIO_INTR_TYPE);
910 port->ip_ienb &= ~hooks->intr_clear;
911 writel(hooks->intr_clear, &port->ip_mem->sio_ir.raw);
912 return 0;
913}
914
915/**
916 * handle_dma_error_intr - service any pending DMA error interrupts for the
917 * given port - 2nd level called via sd_intr
918 * @arg: handler arg
919 * @other_ir: ioc4regs
920 */
921static void handle_dma_error_intr(void *arg, uint32_t other_ir)
922{
923 struct ioc4_port *port = (struct ioc4_port *)arg;
924 struct hooks *hooks = port->ip_hooks;
925 unsigned long flags;
926
927 spin_lock_irqsave(&port->ip_lock, flags);
928
929 /* ACK the interrupt */
930 writel(hooks->intr_dma_error, &port->ip_mem->other_ir.raw);
931
932 if (readl(&port->ip_mem->pci_err_addr_l.raw) & IOC4_PCI_ERR_ADDR_VLD) {
933 printk(KERN_ERR
934 "PCI error address is 0x%llx, "
935 "master is serial port %c %s\n",
936 (((uint64_t)readl(&port->ip_mem->pci_err_addr_h)
937 << 32)
938 | readl(&port->ip_mem->pci_err_addr_l.raw))
939 & IOC4_PCI_ERR_ADDR_ADDR_MSK, '1' +
940 ((char)(readl(&port->ip_mem->pci_err_addr_l.raw) &
941 IOC4_PCI_ERR_ADDR_MST_NUM_MSK) >> 1),
942 (readl(&port->ip_mem->pci_err_addr_l.raw)
943 & IOC4_PCI_ERR_ADDR_MST_TYP_MSK)
944 ? "RX" : "TX");
945
946 if (readl(&port->ip_mem->pci_err_addr_l.raw)
947 & IOC4_PCI_ERR_ADDR_MUL_ERR) {
948 printk(KERN_ERR
949 "Multiple errors occurred\n");
950 }
951 }
952 spin_unlock_irqrestore(&port->ip_lock, flags);
953
954 /* Re-enable DMA error interrupts */
955 write_ireg(port->ip_ioc4_soft, hooks->intr_dma_error, IOC4_W_IES,
956 IOC4_OTHER_INTR_TYPE);
957}
958
959/**
960 * intr_connect - interrupt connect function
961 * @soft: soft struct for this card
962 * @type: interrupt type
963 * @intrbits: bit pattern to set
964 * @intr: handler function
965 * @info: handler arg
966 */
967static void
968intr_connect(struct ioc4_soft *soft, int type,
969 uint32_t intrbits, ioc4_intr_func_f * intr, void *info)
970{
971 int i;
972 struct ioc4_intr_info *intr_ptr;
973
974 BUG_ON(!((type == IOC4_SIO_INTR_TYPE)
975 || (type == IOC4_OTHER_INTR_TYPE)));
976
977 i = atomic_inc(&soft-> is_intr_type[type].is_num_intrs) - 1;
978 BUG_ON(!(i < MAX_IOC4_INTR_ENTS || (printk("i %d\n", i), 0)));
979
980 /* Save off the lower level interrupt handler */
981 intr_ptr = &soft->is_intr_type[type].is_intr_info[i];
982 intr_ptr->sd_bits = intrbits;
983 intr_ptr->sd_intr = intr;
984 intr_ptr->sd_info = info;
985}
986
987/**
988 * ioc4_intr - Top level IOC4 interrupt handler.
989 * @irq: irq value
990 * @arg: handler arg
991 */
992
993static irqreturn_t ioc4_intr(int irq, void *arg)
994{
995 struct ioc4_soft *soft;
996 uint32_t this_ir, this_mir;
997 int xx, num_intrs = 0;
998 int intr_type;
999 int handled = 0;
1000 struct ioc4_intr_info *intr_info;
1001
1002 soft = arg;
1003 for (intr_type = 0; intr_type < IOC4_NUM_INTR_TYPES; intr_type++) {
1004 num_intrs = (int)atomic_read(
1005 &soft->is_intr_type[intr_type].is_num_intrs);
1006
1007 this_mir = this_ir = pending_intrs(soft, intr_type);
1008
1009 /* Farm out the interrupt to the various drivers depending on
1010 * which interrupt bits are set.
1011 */
1012 for (xx = 0; xx < num_intrs; xx++) {
1013 intr_info = &soft->is_intr_type[intr_type].is_intr_info[xx];
1014 if ((this_mir = this_ir & intr_info->sd_bits)) {
1015 /* Disable owned interrupts, call handler */
1016 handled++;
1017 write_ireg(soft, intr_info->sd_bits, IOC4_W_IEC,
1018 intr_type);
1019 intr_info->sd_intr(intr_info->sd_info, this_mir);
1020 this_ir &= ~this_mir;
1021 }
1022 }
1023 }
1024#ifdef DEBUG_INTERRUPTS
1025 {
1026 struct ioc4_misc_regs __iomem *mem = soft->is_ioc4_misc_addr;
1027 unsigned long flag;
1028
1029 spin_lock_irqsave(&soft->is_ir_lock, flag);
1030 printk ("%s : %d : mem 0x%p sio_ir 0x%x sio_ies 0x%x "
1031 "other_ir 0x%x other_ies 0x%x mask 0x%x\n",
1032 __func__, __LINE__,
1033 (void *)mem, readl(&mem->sio_ir.raw),
1034 readl(&mem->sio_ies.raw),
1035 readl(&mem->other_ir.raw),
1036 readl(&mem->other_ies.raw),
1037 IOC4_OTHER_IR_ATA_INT | IOC4_OTHER_IR_ATA_MEMERR);
1038 spin_unlock_irqrestore(&soft->is_ir_lock, flag);
1039 }
1040#endif
1041 return handled ? IRQ_HANDLED : IRQ_NONE;
1042}
1043
1044/**
1045 * ioc4_attach_local - Device initialization.
1046 * Called at *_attach() time for each
1047 * IOC4 with serial ports in the system.
1048 * @idd: Master module data for this IOC4
1049 */
1050static int inline ioc4_attach_local(struct ioc4_driver_data *idd)
1051{
1052 struct ioc4_port *port;
1053 struct ioc4_port *ports[IOC4_NUM_SERIAL_PORTS];
1054 int port_number;
1055 uint16_t ioc4_revid_min = 62;
1056 uint16_t ioc4_revid;
1057 struct pci_dev *pdev = idd->idd_pdev;
1058 struct ioc4_control* control = idd->idd_serial_data;
1059 struct ioc4_soft *soft = control->ic_soft;
1060 void __iomem *ioc4_misc = idd->idd_misc_regs;
1061 void __iomem *ioc4_serial = soft->is_ioc4_serial_addr;
1062
1063 /* IOC4 firmware must be at least rev 62 */
1064 pci_read_config_word(pdev, PCI_COMMAND_SPECIAL, &ioc4_revid);
1065
1066 printk(KERN_INFO "IOC4 firmware revision %d\n", ioc4_revid);
1067 if (ioc4_revid < ioc4_revid_min) {
1068 printk(KERN_WARNING
1069 "IOC4 serial not supported on firmware rev %d, "
1070 "please upgrade to rev %d or higher\n",
1071 ioc4_revid, ioc4_revid_min);
1072 return -EPERM;
1073 }
1074 BUG_ON(ioc4_misc == NULL);
1075 BUG_ON(ioc4_serial == NULL);
1076
1077 /* Create port structures for each port */
1078 for (port_number = 0; port_number < IOC4_NUM_SERIAL_PORTS;
1079 port_number++) {
1080 port = kzalloc(sizeof(struct ioc4_port), GFP_KERNEL);
1081 if (!port) {
1082 printk(KERN_WARNING
1083 "IOC4 serial memory not available for port\n");
1084 return -ENOMEM;
1085 }
1086 spin_lock_init(&port->ip_lock);
1087
1088 /* we need to remember the previous ones, to point back to
1089 * them farther down - setting up the ring buffers.
1090 */
1091 ports[port_number] = port;
1092
1093 /* Allocate buffers and jumpstart the hardware. */
1094 control->ic_port[port_number].icp_port = port;
1095 port->ip_ioc4_soft = soft;
1096 port->ip_pdev = pdev;
1097 port->ip_ienb = 0;
1098 /* Use baud rate calculations based on detected PCI
1099 * bus speed. Simply test whether the PCI clock is
1100 * running closer to 66MHz or 33MHz.
1101 */
1102 if (idd->count_period/IOC4_EXTINT_COUNT_DIVISOR < 20) {
1103 port->ip_pci_bus_speed = IOC4_SER_XIN_CLK_66;
1104 } else {
1105 port->ip_pci_bus_speed = IOC4_SER_XIN_CLK_33;
1106 }
1107 port->ip_baud = 9600;
1108 port->ip_control = control;
1109 port->ip_mem = ioc4_misc;
1110 port->ip_serial = ioc4_serial;
1111
1112 /* point to the right hook */
1113 port->ip_hooks = &hooks_array[port_number];
1114
1115 /* Get direct hooks to the serial regs and uart regs
1116 * for this port
1117 */
1118 switch (port_number) {
1119 case 0:
1120 port->ip_serial_regs = &(port->ip_serial->port_0);
1121 port->ip_uart_regs = &(port->ip_serial->uart_0);
1122 break;
1123 case 1:
1124 port->ip_serial_regs = &(port->ip_serial->port_1);
1125 port->ip_uart_regs = &(port->ip_serial->uart_1);
1126 break;
1127 case 2:
1128 port->ip_serial_regs = &(port->ip_serial->port_2);
1129 port->ip_uart_regs = &(port->ip_serial->uart_2);
1130 break;
1131 default:
1132 case 3:
1133 port->ip_serial_regs = &(port->ip_serial->port_3);
1134 port->ip_uart_regs = &(port->ip_serial->uart_3);
1135 break;
1136 }
1137
1138 /* ring buffers are 1 to a pair of ports */
1139 if (port_number && (port_number & 1)) {
1140 /* odd use the evens buffer */
1141 port->ip_dma_ringbuf =
1142 ports[port_number - 1]->ip_dma_ringbuf;
1143 port->ip_cpu_ringbuf =
1144 ports[port_number - 1]->ip_cpu_ringbuf;
1145 port->ip_inring = RING(port, RX_1_OR_3);
1146 port->ip_outring = RING(port, TX_1_OR_3);
1147
1148 } else {
1149 if (port->ip_dma_ringbuf == 0) {
1150 port->ip_cpu_ringbuf = pci_alloc_consistent
1151 (pdev, TOTAL_RING_BUF_SIZE,
1152 &port->ip_dma_ringbuf);
1153
1154 }
1155 BUG_ON(!((((int64_t)port->ip_dma_ringbuf) &
1156 (TOTAL_RING_BUF_SIZE - 1)) == 0));
1157 DPRINT_CONFIG(("%s : ip_cpu_ringbuf 0x%p "
1158 "ip_dma_ringbuf 0x%p\n",
1159 __func__,
1160 (void *)port->ip_cpu_ringbuf,
1161 (void *)port->ip_dma_ringbuf));
1162 port->ip_inring = RING(port, RX_0_OR_2);
1163 port->ip_outring = RING(port, TX_0_OR_2);
1164 }
1165 DPRINT_CONFIG(("%s : port %d [addr 0x%p] control 0x%p",
1166 __func__,
1167 port_number, (void *)port, (void *)control));
1168 DPRINT_CONFIG((" ip_serial_regs 0x%p ip_uart_regs 0x%p\n",
1169 (void *)port->ip_serial_regs,
1170 (void *)port->ip_uart_regs));
1171
1172 /* Initialize the hardware for IOC4 */
1173 port_init(port);
1174
1175 DPRINT_CONFIG(("%s: port_number %d port 0x%p inring 0x%p "
1176 "outring 0x%p\n",
1177 __func__,
1178 port_number, (void *)port,
1179 (void *)port->ip_inring,
1180 (void *)port->ip_outring));
1181
1182 /* Attach interrupt handlers */
1183 intr_connect(soft, IOC4_SIO_INTR_TYPE,
1184 GET_SIO_IR(port_number),
1185 handle_intr, port);
1186
1187 intr_connect(soft, IOC4_OTHER_INTR_TYPE,
1188 GET_OTHER_IR(port_number),
1189 handle_dma_error_intr, port);
1190 }
1191 return 0;
1192}
1193
1194/**
1195 * enable_intrs - enable interrupts
1196 * @port: port to enable
1197 * @mask: mask to use
1198 */
1199static void enable_intrs(struct ioc4_port *port, uint32_t mask)
1200{
1201 struct hooks *hooks = port->ip_hooks;
1202
1203 if ((port->ip_ienb & mask) != mask) {
1204 write_ireg(port->ip_ioc4_soft, mask, IOC4_W_IES,
1205 IOC4_SIO_INTR_TYPE);
1206 port->ip_ienb |= mask;
1207 }
1208
1209 if (port->ip_ienb)
1210 write_ireg(port->ip_ioc4_soft, hooks->intr_dma_error,
1211 IOC4_W_IES, IOC4_OTHER_INTR_TYPE);
1212}
1213
1214/**
1215 * local_open - local open a port
1216 * @port: port to open
1217 */
1218static inline int local_open(struct ioc4_port *port)
1219{
1220 int spiniter = 0;
1221
1222 port->ip_flags = PORT_ACTIVE;
1223
1224 /* Pause the DMA interface if necessary */
1225 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1226 writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE,
1227 &port->ip_serial_regs->sscr);
1228 while((readl(&port->ip_serial_regs-> sscr)
1229 & IOC4_SSCR_PAUSE_STATE) == 0) {
1230 spiniter++;
1231 if (spiniter > MAXITER) {
1232 port->ip_flags = PORT_INACTIVE;
1233 return -1;
1234 }
1235 }
1236 }
1237
1238 /* Reset the input fifo. If the uart received chars while the port
1239 * was closed and DMA is not enabled, the uart may have a bunch of
1240 * chars hanging around in its rx fifo which will not be discarded
1241 * by rclr in the upper layer. We must get rid of them here.
1242 */
1243 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR,
1244 &port->ip_uart_regs->i4u_fcr);
1245
1246 writeb(UART_LCR_WLEN8, &port->ip_uart_regs->i4u_lcr);
1247 /* UART_LCR_STOP == 1 stop */
1248
1249 /* Re-enable DMA, set default threshold to intr whenever there is
1250 * data available.
1251 */
1252 port->ip_sscr &= ~IOC4_SSCR_RX_THRESHOLD;
1253 port->ip_sscr |= 1; /* default threshold */
1254
1255 /* Plug in the new sscr. This implicitly clears the DMA_PAUSE
1256 * flag if it was set above
1257 */
1258 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1259 port->ip_tx_lowat = 1;
1260 return 0;
1261}
1262
1263/**
1264 * set_rx_timeout - Set rx timeout and threshold values.
1265 * @port: port to use
1266 * @timeout: timeout value in ticks
1267 */
1268static inline int set_rx_timeout(struct ioc4_port *port, int timeout)
1269{
1270 int threshold;
1271
1272 port->ip_rx_timeout = timeout;
1273
1274 /* Timeout is in ticks. Let's figure out how many chars we
1275 * can receive at the current baud rate in that interval
1276 * and set the rx threshold to that amount. There are 4 chars
1277 * per ring entry, so we'll divide the number of chars that will
1278 * arrive in timeout by 4.
1279 * So .... timeout * baud / 10 / HZ / 4, with HZ = 100.
1280 */
1281 threshold = timeout * port->ip_baud / 4000;
1282 if (threshold == 0)
1283 threshold = 1; /* otherwise we'll intr all the time! */
1284
1285 if ((unsigned)threshold > (unsigned)IOC4_SSCR_RX_THRESHOLD)
1286 return 1;
1287
1288 port->ip_sscr &= ~IOC4_SSCR_RX_THRESHOLD;
1289 port->ip_sscr |= threshold;
1290
1291 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1292
1293 /* Now set the rx timeout to the given value
1294 * again timeout * IOC4_SRTR_HZ / HZ
1295 */
1296 timeout = timeout * IOC4_SRTR_HZ / 100;
1297 if (timeout > IOC4_SRTR_CNT)
1298 timeout = IOC4_SRTR_CNT;
1299
1300 writel(timeout, &port->ip_serial_regs->srtr);
1301 return 0;
1302}
1303
1304/**
1305 * config_port - config the hardware
1306 * @port: port to config
1307 * @baud: baud rate for the port
1308 * @byte_size: data size
1309 * @stop_bits: number of stop bits
1310 * @parenb: parity enable ?
1311 * @parodd: odd parity ?
1312 */
1313static inline int
1314config_port(struct ioc4_port *port,
1315 int baud, int byte_size, int stop_bits, int parenb, int parodd)
1316{
1317 char lcr, sizebits;
1318 int spiniter = 0;
1319
1320 DPRINT_CONFIG(("%s: baud %d byte_size %d stop %d parenb %d parodd %d\n",
1321 __func__, baud, byte_size, stop_bits, parenb, parodd));
1322
1323 if (set_baud(port, baud))
1324 return 1;
1325
1326 switch (byte_size) {
1327 case 5:
1328 sizebits = UART_LCR_WLEN5;
1329 break;
1330 case 6:
1331 sizebits = UART_LCR_WLEN6;
1332 break;
1333 case 7:
1334 sizebits = UART_LCR_WLEN7;
1335 break;
1336 case 8:
1337 sizebits = UART_LCR_WLEN8;
1338 break;
1339 default:
1340 return 1;
1341 }
1342
1343 /* Pause the DMA interface if necessary */
1344 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1345 writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE,
1346 &port->ip_serial_regs->sscr);
1347 while((readl(&port->ip_serial_regs->sscr)
1348 & IOC4_SSCR_PAUSE_STATE) == 0) {
1349 spiniter++;
1350 if (spiniter > MAXITER)
1351 return -1;
1352 }
1353 }
1354
1355 /* Clear relevant fields in lcr */
1356 lcr = readb(&port->ip_uart_regs->i4u_lcr);
1357 lcr &= ~(LCR_MASK_BITS_CHAR | UART_LCR_EPAR |
1358 UART_LCR_PARITY | LCR_MASK_STOP_BITS);
1359
1360 /* Set byte size in lcr */
1361 lcr |= sizebits;
1362
1363 /* Set parity */
1364 if (parenb) {
1365 lcr |= UART_LCR_PARITY;
1366 if (!parodd)
1367 lcr |= UART_LCR_EPAR;
1368 }
1369
1370 /* Set stop bits */
1371 if (stop_bits)
1372 lcr |= UART_LCR_STOP /* 2 stop bits */ ;
1373
1374 writeb(lcr, &port->ip_uart_regs->i4u_lcr);
1375
1376 /* Re-enable the DMA interface if necessary */
1377 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1378 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1379 }
1380 port->ip_baud = baud;
1381
1382 /* When we get within this number of ring entries of filling the
1383 * entire ring on tx, place an EXPLICIT intr to generate a lowat
1384 * notification when output has drained.
1385 */
1386 port->ip_tx_lowat = (TX_LOWAT_CHARS(baud) + 3) / 4;
1387 if (port->ip_tx_lowat == 0)
1388 port->ip_tx_lowat = 1;
1389
1390 set_rx_timeout(port, 2);
1391
1392 return 0;
1393}
1394
1395/**
1396 * do_write - Write bytes to the port. Returns the number of bytes
1397 * actually written. Called from transmit_chars
1398 * @port: port to use
1399 * @buf: the stuff to write
1400 * @len: how many bytes in 'buf'
1401 */
1402static inline int do_write(struct ioc4_port *port, char *buf, int len)
1403{
1404 int prod_ptr, cons_ptr, total = 0;
1405 struct ring *outring;
1406 struct ring_entry *entry;
1407 struct hooks *hooks = port->ip_hooks;
1408
1409 BUG_ON(!(len >= 0));
1410
1411 prod_ptr = port->ip_tx_prod;
1412 cons_ptr = readl(&port->ip_serial_regs->stcir) & PROD_CONS_MASK;
1413 outring = port->ip_outring;
1414
1415 /* Maintain a 1-entry red-zone. The ring buffer is full when
1416 * (cons - prod) % ring_size is 1. Rather than do this subtraction
1417 * in the body of the loop, I'll do it now.
1418 */
1419 cons_ptr = (cons_ptr - (int)sizeof(struct ring_entry)) & PROD_CONS_MASK;
1420
1421 /* Stuff the bytes into the output */
1422 while ((prod_ptr != cons_ptr) && (len > 0)) {
1423 int xx;
1424
1425 /* Get 4 bytes (one ring entry) at a time */
1426 entry = (struct ring_entry *)((caddr_t) outring + prod_ptr);
1427
1428 /* Invalidate all entries */
1429 entry->ring_allsc = 0;
1430
1431 /* Copy in some bytes */
1432 for (xx = 0; (xx < 4) && (len > 0); xx++) {
1433 entry->ring_data[xx] = *buf++;
1434 entry->ring_sc[xx] = IOC4_TXCB_VALID;
1435 len--;
1436 total++;
1437 }
1438
1439 /* If we are within some small threshold of filling up the
1440 * entire ring buffer, we must place an EXPLICIT intr here
1441 * to generate a lowat interrupt in case we subsequently
1442 * really do fill up the ring and the caller goes to sleep.
1443 * No need to place more than one though.
1444 */
1445 if (!(port->ip_flags & LOWAT_WRITTEN) &&
1446 ((cons_ptr - prod_ptr) & PROD_CONS_MASK)
1447 <= port->ip_tx_lowat
1448 * (int)sizeof(struct ring_entry)) {
1449 port->ip_flags |= LOWAT_WRITTEN;
1450 entry->ring_sc[0] |= IOC4_TXCB_INT_WHEN_DONE;
1451 }
1452
1453 /* Go on to next entry */
1454 prod_ptr += sizeof(struct ring_entry);
1455 prod_ptr &= PROD_CONS_MASK;
1456 }
1457
1458 /* If we sent something, start DMA if necessary */
1459 if (total > 0 && !(port->ip_sscr & IOC4_SSCR_DMA_EN)) {
1460 port->ip_sscr |= IOC4_SSCR_DMA_EN;
1461 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1462 }
1463
1464 /* Store the new producer pointer. If tx is disabled, we stuff the
1465 * data into the ring buffer, but we don't actually start tx.
1466 */
1467 if (!uart_tx_stopped(port->ip_port)) {
1468 writel(prod_ptr, &port->ip_serial_regs->stpir);
1469
1470 /* If we are now transmitting, enable tx_mt interrupt so we
1471 * can disable DMA if necessary when the tx finishes.
1472 */
1473 if (total > 0)
1474 enable_intrs(port, hooks->intr_tx_mt);
1475 }
1476 port->ip_tx_prod = prod_ptr;
1477 return total;
1478}
1479
1480/**
1481 * disable_intrs - disable interrupts
1482 * @port: port to enable
1483 * @mask: mask to use
1484 */
1485static void disable_intrs(struct ioc4_port *port, uint32_t mask)
1486{
1487 struct hooks *hooks = port->ip_hooks;
1488
1489 if (port->ip_ienb & mask) {
1490 write_ireg(port->ip_ioc4_soft, mask, IOC4_W_IEC,
1491 IOC4_SIO_INTR_TYPE);
1492 port->ip_ienb &= ~mask;
1493 }
1494
1495 if (!port->ip_ienb)
1496 write_ireg(port->ip_ioc4_soft, hooks->intr_dma_error,
1497 IOC4_W_IEC, IOC4_OTHER_INTR_TYPE);
1498}
1499
1500/**
1501 * set_notification - Modify event notification
1502 * @port: port to use
1503 * @mask: events mask
1504 * @set_on: set ?
1505 */
1506static int set_notification(struct ioc4_port *port, int mask, int set_on)
1507{
1508 struct hooks *hooks = port->ip_hooks;
1509 uint32_t intrbits, sscrbits;
1510
1511 BUG_ON(!mask);
1512
1513 intrbits = sscrbits = 0;
1514
1515 if (mask & N_DATA_READY)
1516 intrbits |= (hooks->intr_rx_timer | hooks->intr_rx_high);
1517 if (mask & N_OUTPUT_LOWAT)
1518 intrbits |= hooks->intr_tx_explicit;
1519 if (mask & N_DDCD) {
1520 intrbits |= hooks->intr_delta_dcd;
1521 sscrbits |= IOC4_SSCR_RX_RING_DCD;
1522 }
1523 if (mask & N_DCTS)
1524 intrbits |= hooks->intr_delta_cts;
1525
1526 if (set_on) {
1527 enable_intrs(port, intrbits);
1528 port->ip_notify |= mask;
1529 port->ip_sscr |= sscrbits;
1530 } else {
1531 disable_intrs(port, intrbits);
1532 port->ip_notify &= ~mask;
1533 port->ip_sscr &= ~sscrbits;
1534 }
1535
1536 /* We require DMA if either DATA_READY or DDCD notification is
1537 * currently requested. If neither of these is requested and
1538 * there is currently no tx in progress, DMA may be disabled.
1539 */
1540 if (port->ip_notify & (N_DATA_READY | N_DDCD))
1541 port->ip_sscr |= IOC4_SSCR_DMA_EN;
1542 else if (!(port->ip_ienb & hooks->intr_tx_mt))
1543 port->ip_sscr &= ~IOC4_SSCR_DMA_EN;
1544
1545 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1546 return 0;
1547}
1548
1549/**
1550 * set_mcr - set the master control reg
1551 * @the_port: port to use
1552 * @mask1: mcr mask
1553 * @mask2: shadow mask
1554 */
1555static inline int set_mcr(struct uart_port *the_port,
1556 int mask1, int mask2)
1557{
1558 struct ioc4_port *port = get_ioc4_port(the_port, 0);
1559 uint32_t shadow;
1560 int spiniter = 0;
1561 char mcr;
1562
1563 if (!port)
1564 return -1;
1565
1566 /* Pause the DMA interface if necessary */
1567 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1568 writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE,
1569 &port->ip_serial_regs->sscr);
1570 while ((readl(&port->ip_serial_regs->sscr)
1571 & IOC4_SSCR_PAUSE_STATE) == 0) {
1572 spiniter++;
1573 if (spiniter > MAXITER)
1574 return -1;
1575 }
1576 }
1577 shadow = readl(&port->ip_serial_regs->shadow);
1578 mcr = (shadow & 0xff000000) >> 24;
1579
1580 /* Set new value */
1581 mcr |= mask1;
1582 shadow |= mask2;
1583
1584 writeb(mcr, &port->ip_uart_regs->i4u_mcr);
1585 writel(shadow, &port->ip_serial_regs->shadow);
1586
1587 /* Re-enable the DMA interface if necessary */
1588 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1589 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1590 }
1591 return 0;
1592}
1593
1594/**
1595 * ioc4_set_proto - set the protocol for the port
1596 * @port: port to use
1597 * @proto: protocol to use
1598 */
1599static int ioc4_set_proto(struct ioc4_port *port, int proto)
1600{
1601 struct hooks *hooks = port->ip_hooks;
1602
1603 switch (proto) {
1604 case PROTO_RS232:
1605 /* Clear the appropriate GIO pin */
1606 writel(0, (&port->ip_mem->gppr[hooks->rs422_select_pin].raw));
1607 break;
1608
1609 case PROTO_RS422:
1610 /* Set the appropriate GIO pin */
1611 writel(1, (&port->ip_mem->gppr[hooks->rs422_select_pin].raw));
1612 break;
1613
1614 default:
1615 return 1;
1616 }
1617 return 0;
1618}
1619
1620/**
1621 * transmit_chars - upper level write, called with ip_lock
1622 * @the_port: port to write
1623 */
1624static void transmit_chars(struct uart_port *the_port)
1625{
1626 int xmit_count, tail, head;
1627 int result;
1628 char *start;
1629 struct tty_struct *tty;
1630 struct ioc4_port *port = get_ioc4_port(the_port, 0);
1631 struct uart_state *state;
1632
1633 if (!the_port)
1634 return;
1635 if (!port)
1636 return;
1637
1638 state = the_port->state;
1639 tty = state->port.tty;
1640
1641 if (uart_circ_empty(&state->xmit) || uart_tx_stopped(the_port)) {
1642 /* Nothing to do or hw stopped */
1643 set_notification(port, N_ALL_OUTPUT, 0);
1644 return;
1645 }
1646
1647 head = state->xmit.head;
1648 tail = state->xmit.tail;
1649 start = (char *)&state->xmit.buf[tail];
1650
1651 /* write out all the data or until the end of the buffer */
1652 xmit_count = (head < tail) ? (UART_XMIT_SIZE - tail) : (head - tail);
1653 if (xmit_count > 0) {
1654 result = do_write(port, start, xmit_count);
1655 if (result > 0) {
1656 /* booking */
1657 xmit_count -= result;
1658 the_port->icount.tx += result;
1659 /* advance the pointers */
1660 tail += result;
1661 tail &= UART_XMIT_SIZE - 1;
1662 state->xmit.tail = tail;
1663 start = (char *)&state->xmit.buf[tail];
1664 }
1665 }
1666 if (uart_circ_chars_pending(&state->xmit) < WAKEUP_CHARS)
1667 uart_write_wakeup(the_port);
1668
1669 if (uart_circ_empty(&state->xmit)) {
1670 set_notification(port, N_OUTPUT_LOWAT, 0);
1671 } else {
1672 set_notification(port, N_OUTPUT_LOWAT, 1);
1673 }
1674}
1675
1676/**
1677 * ioc4_change_speed - change the speed of the port
1678 * @the_port: port to change
1679 * @new_termios: new termios settings
1680 * @old_termios: old termios settings
1681 */
1682static void
1683ioc4_change_speed(struct uart_port *the_port,
1684 struct ktermios *new_termios, struct ktermios *old_termios)
1685{
1686 struct ioc4_port *port = get_ioc4_port(the_port, 0);
1687 int baud, bits;
1688 unsigned cflag, iflag;
1689 int new_parity = 0, new_parity_enable = 0, new_stop = 0, new_data = 8;
1690 struct uart_state *state = the_port->state;
1691
1692 cflag = new_termios->c_cflag;
1693 iflag = new_termios->c_iflag;
1694
1695 switch (cflag & CSIZE) {
1696 case CS5:
1697 new_data = 5;
1698 bits = 7;
1699 break;
1700 case CS6:
1701 new_data = 6;
1702 bits = 8;
1703 break;
1704 case CS7:
1705 new_data = 7;
1706 bits = 9;
1707 break;
1708 case CS8:
1709 new_data = 8;
1710 bits = 10;
1711 break;
1712 default:
1713 /* cuz we always need a default ... */
1714 new_data = 5;
1715 bits = 7;
1716 break;
1717 }
1718 if (cflag & CSTOPB) {
1719 bits++;
1720 new_stop = 1;
1721 }
1722 if (cflag & PARENB) {
1723 bits++;
1724 new_parity_enable = 1;
1725 if (cflag & PARODD)
1726 new_parity = 1;
1727 }
1728 baud = uart_get_baud_rate(the_port, new_termios, old_termios,
1729 MIN_BAUD_SUPPORTED, MAX_BAUD_SUPPORTED);
1730 DPRINT_CONFIG(("%s: returned baud %d\n", __func__, baud));
1731
1732 /* default is 9600 */
1733 if (!baud)
1734 baud = 9600;
1735
1736 if (!the_port->fifosize)
1737 the_port->fifosize = IOC4_FIFO_CHARS;
1738 the_port->timeout = ((the_port->fifosize * HZ * bits) / (baud / 10));
1739 the_port->timeout += HZ / 50; /* Add .02 seconds of slop */
1740
1741 the_port->ignore_status_mask = N_ALL_INPUT;
1742
1743 state->port.tty->low_latency = 1;
1744
1745 if (iflag & IGNPAR)
1746 the_port->ignore_status_mask &= ~(N_PARITY_ERROR
1747 | N_FRAMING_ERROR);
1748 if (iflag & IGNBRK) {
1749 the_port->ignore_status_mask &= ~N_BREAK;
1750 if (iflag & IGNPAR)
1751 the_port->ignore_status_mask &= ~N_OVERRUN_ERROR;
1752 }
1753 if (!(cflag & CREAD)) {
1754 /* ignore everything */
1755 the_port->ignore_status_mask &= ~N_DATA_READY;
1756 }
1757
1758 if (cflag & CRTSCTS) {
1759 port->ip_sscr |= IOC4_SSCR_HFC_EN;
1760 }
1761 else {
1762 port->ip_sscr &= ~IOC4_SSCR_HFC_EN;
1763 }
1764 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1765
1766 /* Set the configuration and proper notification call */
1767 DPRINT_CONFIG(("%s : port 0x%p cflag 0%o "
1768 "config_port(baud %d data %d stop %d p enable %d parity %d),"
1769 " notification 0x%x\n",
1770 __func__, (void *)port, cflag, baud, new_data, new_stop,
1771 new_parity_enable, new_parity, the_port->ignore_status_mask));
1772
1773 if ((config_port(port, baud, /* baud */
1774 new_data, /* byte size */
1775 new_stop, /* stop bits */
1776 new_parity_enable, /* set parity */
1777 new_parity)) >= 0) { /* parity 1==odd */
1778 set_notification(port, the_port->ignore_status_mask, 1);
1779 }
1780}
1781
1782/**
1783 * ic4_startup_local - Start up the serial port - returns >= 0 if no errors
1784 * @the_port: Port to operate on
1785 */
1786static inline int ic4_startup_local(struct uart_port *the_port)
1787{
1788 struct ioc4_port *port;
1789 struct uart_state *state;
1790
1791 if (!the_port)
1792 return -1;
1793
1794 port = get_ioc4_port(the_port, 0);
1795 if (!port)
1796 return -1;
1797
1798 state = the_port->state;
1799
1800 local_open(port);
1801
1802 /* set the protocol - mapbase has the port type */
1803 ioc4_set_proto(port, the_port->mapbase);
1804
1805 /* set the speed of the serial port */
1806 ioc4_change_speed(the_port, state->port.tty->termios,
1807 (struct ktermios *)0);
1808
1809 return 0;
1810}
1811
1812/*
1813 * ioc4_cb_output_lowat - called when the output low water mark is hit
1814 * @the_port: port to output
1815 */
1816static void ioc4_cb_output_lowat(struct uart_port *the_port)
1817{
1818 unsigned long pflags;
1819
1820 /* ip_lock is set on the call here */
1821 if (the_port) {
1822 spin_lock_irqsave(&the_port->lock, pflags);
1823 transmit_chars(the_port);
1824 spin_unlock_irqrestore(&the_port->lock, pflags);
1825 }
1826}
1827
1828/**
1829 * handle_intr - service any interrupts for the given port - 2nd level
1830 * called via sd_intr
1831 * @arg: handler arg
1832 * @sio_ir: ioc4regs
1833 */
1834static void handle_intr(void *arg, uint32_t sio_ir)
1835{
1836 struct ioc4_port *port = (struct ioc4_port *)arg;
1837 struct hooks *hooks = port->ip_hooks;
1838 unsigned int rx_high_rd_aborted = 0;
1839 unsigned long flags;
1840 struct uart_port *the_port;
1841 int loop_counter;
1842
1843 /* Possible race condition here: The tx_mt interrupt bit may be
1844 * cleared without the intervention of the interrupt handler,
1845 * e.g. by a write. If the top level interrupt handler reads a
1846 * tx_mt, then some other processor does a write, starting up
1847 * output, then we come in here, see the tx_mt and stop DMA, the
1848 * output started by the other processor will hang. Thus we can
1849 * only rely on tx_mt being legitimate if it is read while the
1850 * port lock is held. Therefore this bit must be ignored in the
1851 * passed in interrupt mask which was read by the top level
1852 * interrupt handler since the port lock was not held at the time
1853 * it was read. We can only rely on this bit being accurate if it
1854 * is read while the port lock is held. So we'll clear it for now,
1855 * and reload it later once we have the port lock.
1856 */
1857 sio_ir &= ~(hooks->intr_tx_mt);
1858
1859 spin_lock_irqsave(&port->ip_lock, flags);
1860
1861 loop_counter = MAXITER; /* to avoid hangs */
1862
1863 do {
1864 uint32_t shadow;
1865
1866 if ( loop_counter-- <= 0 ) {
1867 printk(KERN_WARNING "IOC4 serial: "
1868 "possible hang condition/"
1869 "port stuck on interrupt.\n");
1870 break;
1871 }
1872
1873 /* Handle a DCD change */
1874 if (sio_ir & hooks->intr_delta_dcd) {
1875 /* ACK the interrupt */
1876 writel(hooks->intr_delta_dcd,
1877 &port->ip_mem->sio_ir.raw);
1878
1879 shadow = readl(&port->ip_serial_regs->shadow);
1880
1881 if ((port->ip_notify & N_DDCD)
1882 && (shadow & IOC4_SHADOW_DCD)
1883 && (port->ip_port)) {
1884 the_port = port->ip_port;
1885 the_port->icount.dcd = 1;
1886 wake_up_interruptible
1887 (&the_port->state->port.delta_msr_wait);
1888 } else if ((port->ip_notify & N_DDCD)
1889 && !(shadow & IOC4_SHADOW_DCD)) {
1890 /* Flag delta DCD/no DCD */
1891 port->ip_flags |= DCD_ON;
1892 }
1893 }
1894
1895 /* Handle a CTS change */
1896 if (sio_ir & hooks->intr_delta_cts) {
1897 /* ACK the interrupt */
1898 writel(hooks->intr_delta_cts,
1899 &port->ip_mem->sio_ir.raw);
1900
1901 shadow = readl(&port->ip_serial_regs->shadow);
1902
1903 if ((port->ip_notify & N_DCTS)
1904 && (port->ip_port)) {
1905 the_port = port->ip_port;
1906 the_port->icount.cts =
1907 (shadow & IOC4_SHADOW_CTS) ? 1 : 0;
1908 wake_up_interruptible
1909 (&the_port->state->port.delta_msr_wait);
1910 }
1911 }
1912
1913 /* rx timeout interrupt. Must be some data available. Put this
1914 * before the check for rx_high since servicing this condition
1915 * may cause that condition to clear.
1916 */
1917 if (sio_ir & hooks->intr_rx_timer) {
1918 /* ACK the interrupt */
1919 writel(hooks->intr_rx_timer,
1920 &port->ip_mem->sio_ir.raw);
1921
1922 if ((port->ip_notify & N_DATA_READY)
1923 && (port->ip_port)) {
1924 /* ip_lock is set on call here */
1925 receive_chars(port->ip_port);
1926 }
1927 }
1928
1929 /* rx high interrupt. Must be after rx_timer. */
1930 else if (sio_ir & hooks->intr_rx_high) {
1931 /* Data available, notify upper layer */
1932 if ((port->ip_notify & N_DATA_READY)
1933 && port->ip_port) {
1934 /* ip_lock is set on call here */
1935 receive_chars(port->ip_port);
1936 }
1937
1938 /* We can't ACK this interrupt. If receive_chars didn't
1939 * cause the condition to clear, we'll have to disable
1940 * the interrupt until the data is drained.
1941 * If the read was aborted, don't disable the interrupt
1942 * as this may cause us to hang indefinitely. An
1943 * aborted read generally means that this interrupt
1944 * hasn't been delivered to the cpu yet anyway, even
1945 * though we see it as asserted when we read the sio_ir.
1946 */
1947 if ((sio_ir = PENDING(port)) & hooks->intr_rx_high) {
1948 if ((port->ip_flags & READ_ABORTED) == 0) {
1949 port->ip_ienb &= ~hooks->intr_rx_high;
1950 port->ip_flags |= INPUT_HIGH;
1951 } else {
1952 rx_high_rd_aborted++;
1953 }
1954 }
1955 }
1956
1957 /* We got a low water interrupt: notify upper layer to
1958 * send more data. Must come before tx_mt since servicing
1959 * this condition may cause that condition to clear.
1960 */
1961 if (sio_ir & hooks->intr_tx_explicit) {
1962 port->ip_flags &= ~LOWAT_WRITTEN;
1963
1964 /* ACK the interrupt */
1965 writel(hooks->intr_tx_explicit,
1966 &port->ip_mem->sio_ir.raw);
1967
1968 if (port->ip_notify & N_OUTPUT_LOWAT)
1969 ioc4_cb_output_lowat(port->ip_port);
1970 }
1971
1972 /* Handle tx_mt. Must come after tx_explicit. */
1973 else if (sio_ir & hooks->intr_tx_mt) {
1974 /* If we are expecting a lowat notification
1975 * and we get to this point it probably means that for
1976 * some reason the tx_explicit didn't work as expected
1977 * (that can legitimately happen if the output buffer is
1978 * filled up in just the right way).
1979 * So send the notification now.
1980 */
1981 if (port->ip_notify & N_OUTPUT_LOWAT) {
1982 ioc4_cb_output_lowat(port->ip_port);
1983
1984 /* We need to reload the sio_ir since the lowat
1985 * call may have caused another write to occur,
1986 * clearing the tx_mt condition.
1987 */
1988 sio_ir = PENDING(port);
1989 }
1990
1991 /* If the tx_mt condition still persists even after the
1992 * lowat call, we've got some work to do.
1993 */
1994 if (sio_ir & hooks->intr_tx_mt) {
1995
1996 /* If we are not currently expecting DMA input,
1997 * and the transmitter has just gone idle,
1998 * there is no longer any reason for DMA, so
1999 * disable it.
2000 */
2001 if (!(port->ip_notify
2002 & (N_DATA_READY | N_DDCD))) {
2003 BUG_ON(!(port->ip_sscr
2004 & IOC4_SSCR_DMA_EN));
2005 port->ip_sscr &= ~IOC4_SSCR_DMA_EN;
2006 writel(port->ip_sscr,
2007 &port->ip_serial_regs->sscr);
2008 }
2009
2010 /* Prevent infinite tx_mt interrupt */
2011 port->ip_ienb &= ~hooks->intr_tx_mt;
2012 }
2013 }
2014 sio_ir = PENDING(port);
2015
2016 /* if the read was aborted and only hooks->intr_rx_high,
2017 * clear hooks->intr_rx_high, so we do not loop forever.
2018 */
2019
2020 if (rx_high_rd_aborted && (sio_ir == hooks->intr_rx_high)) {
2021 sio_ir &= ~hooks->intr_rx_high;
2022 }
2023 } while (sio_ir & hooks->intr_all);
2024
2025 spin_unlock_irqrestore(&port->ip_lock, flags);
2026
2027 /* Re-enable interrupts before returning from interrupt handler.
2028 * Getting interrupted here is okay. It'll just v() our semaphore, and
2029 * we'll come through the loop again.
2030 */
2031
2032 write_ireg(port->ip_ioc4_soft, port->ip_ienb, IOC4_W_IES,
2033 IOC4_SIO_INTR_TYPE);
2034}
2035
2036/*
2037 * ioc4_cb_post_ncs - called for some basic errors
2038 * @port: port to use
2039 * @ncs: event
2040 */
2041static void ioc4_cb_post_ncs(struct uart_port *the_port, int ncs)
2042{
2043 struct uart_icount *icount;
2044
2045 icount = &the_port->icount;
2046
2047 if (ncs & NCS_BREAK)
2048 icount->brk++;
2049 if (ncs & NCS_FRAMING)
2050 icount->frame++;
2051 if (ncs & NCS_OVERRUN)
2052 icount->overrun++;
2053 if (ncs & NCS_PARITY)
2054 icount->parity++;
2055}
2056
2057/**
2058 * do_read - Read in bytes from the port. Return the number of bytes
2059 * actually read.
2060 * @the_port: port to use
2061 * @buf: place to put the stuff we read
2062 * @len: how big 'buf' is
2063 */
2064
2065static inline int do_read(struct uart_port *the_port, unsigned char *buf,
2066 int len)
2067{
2068 int prod_ptr, cons_ptr, total;
2069 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2070 struct ring *inring;
2071 struct ring_entry *entry;
2072 struct hooks *hooks = port->ip_hooks;
2073 int byte_num;
2074 char *sc;
2075 int loop_counter;
2076
2077 BUG_ON(!(len >= 0));
2078 BUG_ON(!port);
2079
2080 /* There is a nasty timing issue in the IOC4. When the rx_timer
2081 * expires or the rx_high condition arises, we take an interrupt.
2082 * At some point while servicing the interrupt, we read bytes from
2083 * the ring buffer and re-arm the rx_timer. However the rx_timer is
2084 * not started until the first byte is received *after* it is armed,
2085 * and any bytes pending in the rx construction buffers are not drained
2086 * to memory until either there are 4 bytes available or the rx_timer
2087 * expires. This leads to a potential situation where data is left
2088 * in the construction buffers forever - 1 to 3 bytes were received
2089 * after the interrupt was generated but before the rx_timer was
2090 * re-armed. At that point as long as no subsequent bytes are received
2091 * the timer will never be started and the bytes will remain in the
2092 * construction buffer forever. The solution is to execute a DRAIN
2093 * command after rearming the timer. This way any bytes received before
2094 * the DRAIN will be drained to memory, and any bytes received after
2095 * the DRAIN will start the TIMER and be drained when it expires.
2096 * Luckily, this only needs to be done when the DMA buffer is empty
2097 * since there is no requirement that this function return all
2098 * available data as long as it returns some.
2099 */
2100 /* Re-arm the timer */
2101 writel(port->ip_rx_cons | IOC4_SRCIR_ARM, &port->ip_serial_regs->srcir);
2102
2103 prod_ptr = readl(&port->ip_serial_regs->srpir) & PROD_CONS_MASK;
2104 cons_ptr = port->ip_rx_cons;
2105
2106 if (prod_ptr == cons_ptr) {
2107 int reset_dma = 0;
2108
2109 /* Input buffer appears empty, do a flush. */
2110
2111 /* DMA must be enabled for this to work. */
2112 if (!(port->ip_sscr & IOC4_SSCR_DMA_EN)) {
2113 port->ip_sscr |= IOC4_SSCR_DMA_EN;
2114 reset_dma = 1;
2115 }
2116
2117 /* Potential race condition: we must reload the srpir after
2118 * issuing the drain command, otherwise we could think the rx
2119 * buffer is empty, then take a very long interrupt, and when
2120 * we come back it's full and we wait forever for the drain to
2121 * complete.
2122 */
2123 writel(port->ip_sscr | IOC4_SSCR_RX_DRAIN,
2124 &port->ip_serial_regs->sscr);
2125 prod_ptr = readl(&port->ip_serial_regs->srpir)
2126 & PROD_CONS_MASK;
2127
2128 /* We must not wait for the DRAIN to complete unless there are
2129 * at least 8 bytes (2 ring entries) available to receive the
2130 * data otherwise the DRAIN will never complete and we'll
2131 * deadlock here.
2132 * In fact, to make things easier, I'll just ignore the flush if
2133 * there is any data at all now available.
2134 */
2135 if (prod_ptr == cons_ptr) {
2136 loop_counter = 0;
2137 while (readl(&port->ip_serial_regs->sscr) &
2138 IOC4_SSCR_RX_DRAIN) {
2139 loop_counter++;
2140 if (loop_counter > MAXITER)
2141 return -1;
2142 }
2143
2144 /* SIGH. We have to reload the prod_ptr *again* since
2145 * the drain may have caused it to change
2146 */
2147 prod_ptr = readl(&port->ip_serial_regs->srpir)
2148 & PROD_CONS_MASK;
2149 }
2150 if (reset_dma) {
2151 port->ip_sscr &= ~IOC4_SSCR_DMA_EN;
2152 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
2153 }
2154 }
2155 inring = port->ip_inring;
2156 port->ip_flags &= ~READ_ABORTED;
2157
2158 total = 0;
2159 loop_counter = 0xfffff; /* to avoid hangs */
2160
2161 /* Grab bytes from the hardware */
2162 while ((prod_ptr != cons_ptr) && (len > 0)) {
2163 entry = (struct ring_entry *)((caddr_t)inring + cons_ptr);
2164
2165 if ( loop_counter-- <= 0 ) {
2166 printk(KERN_WARNING "IOC4 serial: "
2167 "possible hang condition/"
2168 "port stuck on read.\n");
2169 break;
2170 }
2171
2172 /* According to the producer pointer, this ring entry
2173 * must contain some data. But if the PIO happened faster
2174 * than the DMA, the data may not be available yet, so let's
2175 * wait until it arrives.
2176 */
2177 if ((entry->ring_allsc & RING_ANY_VALID) == 0) {
2178 /* Indicate the read is aborted so we don't disable
2179 * the interrupt thinking that the consumer is
2180 * congested.
2181 */
2182 port->ip_flags |= READ_ABORTED;
2183 len = 0;
2184 break;
2185 }
2186
2187 /* Load the bytes/status out of the ring entry */
2188 for (byte_num = 0; byte_num < 4 && len > 0; byte_num++) {
2189 sc = &(entry->ring_sc[byte_num]);
2190
2191 /* Check for change in modem state or overrun */
2192 if ((*sc & IOC4_RXSB_MODEM_VALID)
2193 && (port->ip_notify & N_DDCD)) {
2194 /* Notify upper layer if DCD dropped */
2195
2196 if ((port->ip_flags & DCD_ON)
2197 && !(*sc & IOC4_RXSB_DCD)) {
2198
2199 /* If we have already copied some data,
2200 * return it. We'll pick up the carrier
2201 * drop on the next pass. That way we
2202 * don't throw away the data that has
2203 * already been copied back to
2204 * the caller's buffer.
2205 */
2206 if (total > 0) {
2207 len = 0;
2208 break;
2209 }
2210 port->ip_flags &= ~DCD_ON;
2211
2212 /* Turn off this notification so the
2213 * carrier drop protocol won't see it
2214 * again when it does a read.
2215 */
2216 *sc &= ~IOC4_RXSB_MODEM_VALID;
2217
2218 /* To keep things consistent, we need
2219 * to update the consumer pointer so
2220 * the next reader won't come in and
2221 * try to read the same ring entries
2222 * again. This must be done here before
2223 * the dcd change.
2224 */
2225
2226 if ((entry->ring_allsc & RING_ANY_VALID)
2227 == 0) {
2228 cons_ptr += (int)sizeof
2229 (struct ring_entry);
2230 cons_ptr &= PROD_CONS_MASK;
2231 }
2232 writel(cons_ptr,
2233 &port->ip_serial_regs->srcir);
2234 port->ip_rx_cons = cons_ptr;
2235
2236 /* Notify upper layer of carrier drop */
2237 if ((port->ip_notify & N_DDCD)
2238 && port->ip_port) {
2239 the_port->icount.dcd = 0;
2240 wake_up_interruptible
2241 (&the_port->state->
2242 port.delta_msr_wait);
2243 }
2244
2245 /* If we had any data to return, we
2246 * would have returned it above.
2247 */
2248 return 0;
2249 }
2250 }
2251 if (*sc & IOC4_RXSB_MODEM_VALID) {
2252 /* Notify that an input overrun occurred */
2253 if ((*sc & IOC4_RXSB_OVERRUN)
2254 && (port->ip_notify & N_OVERRUN_ERROR)) {
2255 ioc4_cb_post_ncs(the_port, NCS_OVERRUN);
2256 }
2257 /* Don't look at this byte again */
2258 *sc &= ~IOC4_RXSB_MODEM_VALID;
2259 }
2260
2261 /* Check for valid data or RX errors */
2262 if ((*sc & IOC4_RXSB_DATA_VALID) &&
2263 ((*sc & (IOC4_RXSB_PAR_ERR
2264 | IOC4_RXSB_FRAME_ERR
2265 | IOC4_RXSB_BREAK))
2266 && (port->ip_notify & (N_PARITY_ERROR
2267 | N_FRAMING_ERROR
2268 | N_BREAK)))) {
2269 /* There is an error condition on the next byte.
2270 * If we have already transferred some bytes,
2271 * we'll stop here. Otherwise if this is the
2272 * first byte to be read, we'll just transfer
2273 * it alone after notifying the
2274 * upper layer of its status.
2275 */
2276 if (total > 0) {
2277 len = 0;
2278 break;
2279 } else {
2280 if ((*sc & IOC4_RXSB_PAR_ERR) &&
2281 (port->ip_notify & N_PARITY_ERROR)) {
2282 ioc4_cb_post_ncs(the_port,
2283 NCS_PARITY);
2284 }
2285 if ((*sc & IOC4_RXSB_FRAME_ERR) &&
2286 (port->ip_notify & N_FRAMING_ERROR)){
2287 ioc4_cb_post_ncs(the_port,
2288 NCS_FRAMING);
2289 }
2290 if ((*sc & IOC4_RXSB_BREAK)
2291 && (port->ip_notify & N_BREAK)) {
2292 ioc4_cb_post_ncs
2293 (the_port,
2294 NCS_BREAK);
2295 }
2296 len = 1;
2297 }
2298 }
2299 if (*sc & IOC4_RXSB_DATA_VALID) {
2300 *sc &= ~IOC4_RXSB_DATA_VALID;
2301 *buf = entry->ring_data[byte_num];
2302 buf++;
2303 len--;
2304 total++;
2305 }
2306 }
2307
2308 /* If we used up this entry entirely, go on to the next one,
2309 * otherwise we must have run out of buffer space, so
2310 * leave the consumer pointer here for the next read in case
2311 * there are still unread bytes in this entry.
2312 */
2313 if ((entry->ring_allsc & RING_ANY_VALID) == 0) {
2314 cons_ptr += (int)sizeof(struct ring_entry);
2315 cons_ptr &= PROD_CONS_MASK;
2316 }
2317 }
2318
2319 /* Update consumer pointer and re-arm rx timer interrupt */
2320 writel(cons_ptr, &port->ip_serial_regs->srcir);
2321 port->ip_rx_cons = cons_ptr;
2322
2323 /* If we have now dipped below the rx high water mark and we have
2324 * rx_high interrupt turned off, we can now turn it back on again.
2325 */
2326 if ((port->ip_flags & INPUT_HIGH) && (((prod_ptr - cons_ptr)
2327 & PROD_CONS_MASK) < ((port->ip_sscr &
2328 IOC4_SSCR_RX_THRESHOLD)
2329 << IOC4_PROD_CONS_PTR_OFF))) {
2330 port->ip_flags &= ~INPUT_HIGH;
2331 enable_intrs(port, hooks->intr_rx_high);
2332 }
2333 return total;
2334}
2335
2336/**
2337 * receive_chars - upper level read. Called with ip_lock.
2338 * @the_port: port to read from
2339 */
2340static void receive_chars(struct uart_port *the_port)
2341{
2342 struct tty_struct *tty;
2343 unsigned char ch[IOC4_MAX_CHARS];
2344 int read_count, request_count = IOC4_MAX_CHARS;
2345 struct uart_icount *icount;
2346 struct uart_state *state = the_port->state;
2347 unsigned long pflags;
2348
2349 /* Make sure all the pointers are "good" ones */
2350 if (!state)
2351 return;
2352 if (!state->port.tty)
2353 return;
2354
2355 spin_lock_irqsave(&the_port->lock, pflags);
2356 tty = state->port.tty;
2357
2358 request_count = tty_buffer_request_room(tty, IOC4_MAX_CHARS);
2359
2360 if (request_count > 0) {
2361 icount = &the_port->icount;
2362 read_count = do_read(the_port, ch, request_count);
2363 if (read_count > 0) {
2364 tty_insert_flip_string(tty, ch, read_count);
2365 icount->rx += read_count;
2366 }
2367 }
2368
2369 spin_unlock_irqrestore(&the_port->lock, pflags);
2370
2371 tty_flip_buffer_push(tty);
2372}
2373
2374/**
2375 * ic4_type - What type of console are we?
2376 * @port: Port to operate with (we ignore since we only have one port)
2377 *
2378 */
2379static const char *ic4_type(struct uart_port *the_port)
2380{
2381 if (the_port->mapbase == PROTO_RS232)
2382 return "SGI IOC4 Serial [rs232]";
2383 else
2384 return "SGI IOC4 Serial [rs422]";
2385}
2386
2387/**
2388 * ic4_tx_empty - Is the transmitter empty?
2389 * @port: Port to operate on
2390 *
2391 */
2392static unsigned int ic4_tx_empty(struct uart_port *the_port)
2393{
2394 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2395 unsigned int ret = 0;
2396
2397 if (port_is_active(port, the_port)) {
2398 if (readl(&port->ip_serial_regs->shadow) & IOC4_SHADOW_TEMT)
2399 ret = TIOCSER_TEMT;
2400 }
2401 return ret;
2402}
2403
2404/**
2405 * ic4_stop_tx - stop the transmitter
2406 * @port: Port to operate on
2407 *
2408 */
2409static void ic4_stop_tx(struct uart_port *the_port)
2410{
2411 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2412
2413 if (port_is_active(port, the_port))
2414 set_notification(port, N_OUTPUT_LOWAT, 0);
2415}
2416
2417/**
2418 * null_void_function -
2419 * @port: Port to operate on
2420 *
2421 */
2422static void null_void_function(struct uart_port *the_port)
2423{
2424}
2425
2426/**
2427 * ic4_shutdown - shut down the port - free irq and disable
2428 * @port: Port to shut down
2429 *
2430 */
2431static void ic4_shutdown(struct uart_port *the_port)
2432{
2433 unsigned long port_flags;
2434 struct ioc4_port *port;
2435 struct uart_state *state;
2436
2437 port = get_ioc4_port(the_port, 0);
2438 if (!port)
2439 return;
2440
2441 state = the_port->state;
2442 port->ip_port = NULL;
2443
2444 wake_up_interruptible(&state->port.delta_msr_wait);
2445
2446 if (state->port.tty)
2447 set_bit(TTY_IO_ERROR, &state->port.tty->flags);
2448
2449 spin_lock_irqsave(&the_port->lock, port_flags);
2450 set_notification(port, N_ALL, 0);
2451 port->ip_flags = PORT_INACTIVE;
2452 spin_unlock_irqrestore(&the_port->lock, port_flags);
2453}
2454
2455/**
2456 * ic4_set_mctrl - set control lines (dtr, rts, etc)
2457 * @port: Port to operate on
2458 * @mctrl: Lines to set/unset
2459 *
2460 */
2461static void ic4_set_mctrl(struct uart_port *the_port, unsigned int mctrl)
2462{
2463 unsigned char mcr = 0;
2464 struct ioc4_port *port;
2465
2466 port = get_ioc4_port(the_port, 0);
2467 if (!port_is_active(port, the_port))
2468 return;
2469
2470 if (mctrl & TIOCM_RTS)
2471 mcr |= UART_MCR_RTS;
2472 if (mctrl & TIOCM_DTR)
2473 mcr |= UART_MCR_DTR;
2474 if (mctrl & TIOCM_OUT1)
2475 mcr |= UART_MCR_OUT1;
2476 if (mctrl & TIOCM_OUT2)
2477 mcr |= UART_MCR_OUT2;
2478 if (mctrl & TIOCM_LOOP)
2479 mcr |= UART_MCR_LOOP;
2480
2481 set_mcr(the_port, mcr, IOC4_SHADOW_DTR);
2482}
2483
2484/**
2485 * ic4_get_mctrl - get control line info
2486 * @port: port to operate on
2487 *
2488 */
2489static unsigned int ic4_get_mctrl(struct uart_port *the_port)
2490{
2491 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2492 uint32_t shadow;
2493 unsigned int ret = 0;
2494
2495 if (!port_is_active(port, the_port))
2496 return 0;
2497
2498 shadow = readl(&port->ip_serial_regs->shadow);
2499 if (shadow & IOC4_SHADOW_DCD)
2500 ret |= TIOCM_CAR;
2501 if (shadow & IOC4_SHADOW_DR)
2502 ret |= TIOCM_DSR;
2503 if (shadow & IOC4_SHADOW_CTS)
2504 ret |= TIOCM_CTS;
2505 return ret;
2506}
2507
2508/**
2509 * ic4_start_tx - Start transmitter, flush any output
2510 * @port: Port to operate on
2511 *
2512 */
2513static void ic4_start_tx(struct uart_port *the_port)
2514{
2515 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2516
2517 if (port_is_active(port, the_port)) {
2518 set_notification(port, N_OUTPUT_LOWAT, 1);
2519 enable_intrs(port, port->ip_hooks->intr_tx_mt);
2520 }
2521}
2522
2523/**
2524 * ic4_break_ctl - handle breaks
2525 * @port: Port to operate on
2526 * @break_state: Break state
2527 *
2528 */
2529static void ic4_break_ctl(struct uart_port *the_port, int break_state)
2530{
2531}
2532
2533/**
2534 * ic4_startup - Start up the serial port
2535 * @port: Port to operate on
2536 *
2537 */
2538static int ic4_startup(struct uart_port *the_port)
2539{
2540 int retval;
2541 struct ioc4_port *port;
2542 struct ioc4_control *control;
2543 struct uart_state *state;
2544 unsigned long port_flags;
2545
2546 if (!the_port)
2547 return -ENODEV;
2548 port = get_ioc4_port(the_port, 1);
2549 if (!port)
2550 return -ENODEV;
2551 state = the_port->state;
2552
2553 control = port->ip_control;
2554 if (!control) {
2555 port->ip_port = NULL;
2556 return -ENODEV;
2557 }
2558
2559 /* Start up the serial port */
2560 spin_lock_irqsave(&the_port->lock, port_flags);
2561 retval = ic4_startup_local(the_port);
2562 spin_unlock_irqrestore(&the_port->lock, port_flags);
2563 return retval;
2564}
2565
2566/**
2567 * ic4_set_termios - set termios stuff
2568 * @port: port to operate on
2569 * @termios: New settings
2570 * @termios: Old
2571 *
2572 */
2573static void
2574ic4_set_termios(struct uart_port *the_port,
2575 struct ktermios *termios, struct ktermios *old_termios)
2576{
2577 unsigned long port_flags;
2578
2579 spin_lock_irqsave(&the_port->lock, port_flags);
2580 ioc4_change_speed(the_port, termios, old_termios);
2581 spin_unlock_irqrestore(&the_port->lock, port_flags);
2582}
2583
2584/**
2585 * ic4_request_port - allocate resources for port - no op....
2586 * @port: port to operate on
2587 *
2588 */
2589static int ic4_request_port(struct uart_port *port)
2590{
2591 return 0;
2592}
2593
2594/* Associate the uart functions above - given to serial core */
2595
2596static struct uart_ops ioc4_ops = {
2597 .tx_empty = ic4_tx_empty,
2598 .set_mctrl = ic4_set_mctrl,
2599 .get_mctrl = ic4_get_mctrl,
2600 .stop_tx = ic4_stop_tx,
2601 .start_tx = ic4_start_tx,
2602 .stop_rx = null_void_function,
2603 .enable_ms = null_void_function,
2604 .break_ctl = ic4_break_ctl,
2605 .startup = ic4_startup,
2606 .shutdown = ic4_shutdown,
2607 .set_termios = ic4_set_termios,
2608 .type = ic4_type,
2609 .release_port = null_void_function,
2610 .request_port = ic4_request_port,
2611};
2612
2613/*
2614 * Boot-time initialization code
2615 */
2616
2617static struct uart_driver ioc4_uart_rs232 = {
2618 .owner = THIS_MODULE,
2619 .driver_name = "ioc4_serial_rs232",
2620 .dev_name = DEVICE_NAME_RS232,
2621 .major = DEVICE_MAJOR,
2622 .minor = DEVICE_MINOR_RS232,
2623 .nr = IOC4_NUM_CARDS * IOC4_NUM_SERIAL_PORTS,
2624};
2625
2626static struct uart_driver ioc4_uart_rs422 = {
2627 .owner = THIS_MODULE,
2628 .driver_name = "ioc4_serial_rs422",
2629 .dev_name = DEVICE_NAME_RS422,
2630 .major = DEVICE_MAJOR,
2631 .minor = DEVICE_MINOR_RS422,
2632 .nr = IOC4_NUM_CARDS * IOC4_NUM_SERIAL_PORTS,
2633};
2634
2635
2636/**
2637 * ioc4_serial_remove_one - detach function
2638 *
2639 * @idd: IOC4 master module data for this IOC4
2640 */
2641
2642static int ioc4_serial_remove_one(struct ioc4_driver_data *idd)
2643{
2644 int port_num, port_type;
2645 struct ioc4_control *control;
2646 struct uart_port *the_port;
2647 struct ioc4_port *port;
2648 struct ioc4_soft *soft;
2649
2650 /* If serial driver did not attach, don't try to detach */
2651 control = idd->idd_serial_data;
2652 if (!control)
2653 return 0;
2654
2655 for (port_num = 0; port_num < IOC4_NUM_SERIAL_PORTS; port_num++) {
2656 for (port_type = UART_PORT_MIN;
2657 port_type < UART_PORT_COUNT;
2658 port_type++) {
2659 the_port = &control->ic_port[port_num].icp_uart_port
2660 [port_type];
2661 if (the_port) {
2662 switch (port_type) {
2663 case UART_PORT_RS422:
2664 uart_remove_one_port(&ioc4_uart_rs422,
2665 the_port);
2666 break;
2667 default:
2668 case UART_PORT_RS232:
2669 uart_remove_one_port(&ioc4_uart_rs232,
2670 the_port);
2671 break;
2672 }
2673 }
2674 }
2675 port = control->ic_port[port_num].icp_port;
2676 /* we allocate in pairs */
2677 if (!(port_num & 1) && port) {
2678 pci_free_consistent(port->ip_pdev,
2679 TOTAL_RING_BUF_SIZE,
2680 port->ip_cpu_ringbuf,
2681 port->ip_dma_ringbuf);
2682 kfree(port);
2683 }
2684 }
2685 soft = control->ic_soft;
2686 if (soft) {
2687 free_irq(control->ic_irq, soft);
2688 if (soft->is_ioc4_serial_addr) {
2689 iounmap(soft->is_ioc4_serial_addr);
2690 release_mem_region((unsigned long)
2691 soft->is_ioc4_serial_addr,
2692 sizeof(struct ioc4_serial));
2693 }
2694 kfree(soft);
2695 }
2696 kfree(control);
2697 idd->idd_serial_data = NULL;
2698
2699 return 0;
2700}
2701
2702
2703/**
2704 * ioc4_serial_core_attach_rs232 - register with serial core
2705 * This is done during pci probing
2706 * @pdev: handle for this card
2707 */
2708static inline int
2709ioc4_serial_core_attach(struct pci_dev *pdev, int port_type)
2710{
2711 struct ioc4_port *port;
2712 struct uart_port *the_port;
2713 struct ioc4_driver_data *idd = pci_get_drvdata(pdev);
2714 struct ioc4_control *control = idd->idd_serial_data;
2715 int port_num;
2716 int port_type_idx;
2717 struct uart_driver *u_driver;
2718
2719
2720 DPRINT_CONFIG(("%s: attach pdev 0x%p - control 0x%p\n",
2721 __func__, pdev, (void *)control));
2722
2723 if (!control)
2724 return -ENODEV;
2725
2726 port_type_idx = (port_type == PROTO_RS232) ? UART_PORT_RS232
2727 : UART_PORT_RS422;
2728
2729 u_driver = (port_type == PROTO_RS232) ? &ioc4_uart_rs232
2730 : &ioc4_uart_rs422;
2731
2732 /* once around for each port on this card */
2733 for (port_num = 0; port_num < IOC4_NUM_SERIAL_PORTS; port_num++) {
2734 the_port = &control->ic_port[port_num].icp_uart_port
2735 [port_type_idx];
2736 port = control->ic_port[port_num].icp_port;
2737 port->ip_all_ports[port_type_idx] = the_port;
2738
2739 DPRINT_CONFIG(("%s: attach the_port 0x%p / port 0x%p : type %s\n",
2740 __func__, (void *)the_port,
2741 (void *)port,
2742 port_type == PROTO_RS232 ? "rs232" : "rs422"));
2743
2744 /* membase, iobase and mapbase just need to be non-0 */
2745 the_port->membase = (unsigned char __iomem *)1;
2746 the_port->iobase = (pdev->bus->number << 16) | port_num;
2747 the_port->line = (Num_of_ioc4_cards << 2) | port_num;
2748 the_port->mapbase = port_type;
2749 the_port->type = PORT_16550A;
2750 the_port->fifosize = IOC4_FIFO_CHARS;
2751 the_port->ops = &ioc4_ops;
2752 the_port->irq = control->ic_irq;
2753 the_port->dev = &pdev->dev;
2754 spin_lock_init(&the_port->lock);
2755 if (uart_add_one_port(u_driver, the_port) < 0) {
2756 printk(KERN_WARNING
2757 "%s: unable to add port %d bus %d\n",
2758 __func__, the_port->line, pdev->bus->number);
2759 } else {
2760 DPRINT_CONFIG(
2761 ("IOC4 serial port %d irq = %d, bus %d\n",
2762 the_port->line, the_port->irq, pdev->bus->number));
2763 }
2764 }
2765 return 0;
2766}
2767
2768/**
2769 * ioc4_serial_attach_one - register attach function
2770 * called per card found from IOC4 master module.
2771 * @idd: Master module data for this IOC4
2772 */
2773int
2774ioc4_serial_attach_one(struct ioc4_driver_data *idd)
2775{
2776 unsigned long tmp_addr1;
2777 struct ioc4_serial __iomem *serial;
2778 struct ioc4_soft *soft;
2779 struct ioc4_control *control;
2780 int ret = 0;
2781
2782
2783 DPRINT_CONFIG(("%s (0x%p, 0x%p)\n", __func__, idd->idd_pdev,
2784 idd->idd_pci_id));
2785
2786 /* PCI-RT does not bring out serial connections.
2787 * Do not attach to this particular IOC4.
2788 */
2789 if (idd->idd_variant == IOC4_VARIANT_PCI_RT)
2790 return 0;
2791
2792 /* request serial registers */
2793 tmp_addr1 = idd->idd_bar0 + IOC4_SERIAL_OFFSET;
2794
2795 if (!request_mem_region(tmp_addr1, sizeof(struct ioc4_serial),
2796 "sioc4_uart")) {
2797 printk(KERN_WARNING
2798 "ioc4 (%p): unable to get request region for "
2799 "uart space\n", (void *)idd->idd_pdev);
2800 ret = -ENODEV;
2801 goto out1;
2802 }
2803 serial = ioremap(tmp_addr1, sizeof(struct ioc4_serial));
2804 if (!serial) {
2805 printk(KERN_WARNING
2806 "ioc4 (%p) : unable to remap ioc4 serial register\n",
2807 (void *)idd->idd_pdev);
2808 ret = -ENODEV;
2809 goto out2;
2810 }
2811 DPRINT_CONFIG(("%s : mem 0x%p, serial 0x%p\n",
2812 __func__, (void *)idd->idd_misc_regs,
2813 (void *)serial));
2814
2815 /* Get memory for the new card */
2816 control = kzalloc(sizeof(struct ioc4_control), GFP_KERNEL);
2817
2818 if (!control) {
2819 printk(KERN_WARNING "ioc4_attach_one"
2820 ": unable to get memory for the IOC4\n");
2821 ret = -ENOMEM;
2822 goto out2;
2823 }
2824 idd->idd_serial_data = control;
2825
2826 /* Allocate the soft structure */
2827 soft = kzalloc(sizeof(struct ioc4_soft), GFP_KERNEL);
2828 if (!soft) {
2829 printk(KERN_WARNING
2830 "ioc4 (%p): unable to get memory for the soft struct\n",
2831 (void *)idd->idd_pdev);
2832 ret = -ENOMEM;
2833 goto out3;
2834 }
2835
2836 spin_lock_init(&soft->is_ir_lock);
2837 soft->is_ioc4_misc_addr = idd->idd_misc_regs;
2838 soft->is_ioc4_serial_addr = serial;
2839
2840 /* Init the IOC4 */
2841 writel(0xf << IOC4_SIO_CR_CMD_PULSE_SHIFT,
2842 &idd->idd_misc_regs->sio_cr.raw);
2843
2844 /* Enable serial port mode select generic PIO pins as outputs */
2845 writel(IOC4_GPCR_UART0_MODESEL | IOC4_GPCR_UART1_MODESEL
2846 | IOC4_GPCR_UART2_MODESEL | IOC4_GPCR_UART3_MODESEL,
2847 &idd->idd_misc_regs->gpcr_s.raw);
2848
2849 /* Clear and disable all serial interrupts */
2850 write_ireg(soft, ~0, IOC4_W_IEC, IOC4_SIO_INTR_TYPE);
2851 writel(~0, &idd->idd_misc_regs->sio_ir.raw);
2852 write_ireg(soft, IOC4_OTHER_IR_SER_MEMERR, IOC4_W_IEC,
2853 IOC4_OTHER_INTR_TYPE);
2854 writel(IOC4_OTHER_IR_SER_MEMERR, &idd->idd_misc_regs->other_ir.raw);
2855 control->ic_soft = soft;
2856
2857 /* Hook up interrupt handler */
2858 if (!request_irq(idd->idd_pdev->irq, ioc4_intr, IRQF_SHARED,
2859 "sgi-ioc4serial", soft)) {
2860 control->ic_irq = idd->idd_pdev->irq;
2861 } else {
2862 printk(KERN_WARNING
2863 "%s : request_irq fails for IRQ 0x%x\n ",
2864 __func__, idd->idd_pdev->irq);
2865 }
2866 ret = ioc4_attach_local(idd);
2867 if (ret)
2868 goto out4;
2869
2870 /* register port with the serial core - 1 rs232, 1 rs422 */
2871
2872 if ((ret = ioc4_serial_core_attach(idd->idd_pdev, PROTO_RS232)))
2873 goto out4;
2874
2875 if ((ret = ioc4_serial_core_attach(idd->idd_pdev, PROTO_RS422)))
2876 goto out5;
2877
2878 Num_of_ioc4_cards++;
2879
2880 return ret;
2881
2882 /* error exits that give back resources */
2883out5:
2884 ioc4_serial_remove_one(idd);
2885out4:
2886 kfree(soft);
2887out3:
2888 kfree(control);
2889out2:
2890 if (serial)
2891 iounmap(serial);
2892 release_mem_region(tmp_addr1, sizeof(struct ioc4_serial));
2893out1:
2894
2895 return ret;
2896}
2897
2898
2899static struct ioc4_submodule ioc4_serial_submodule = {
2900 .is_name = "IOC4_serial",
2901 .is_owner = THIS_MODULE,
2902 .is_probe = ioc4_serial_attach_one,
2903 .is_remove = ioc4_serial_remove_one,
2904};
2905
2906/**
2907 * ioc4_serial_init - module init
2908 */
2909static int __init ioc4_serial_init(void)
2910{
2911 int ret;
2912
2913 /* register with serial core */
2914 if ((ret = uart_register_driver(&ioc4_uart_rs232)) < 0) {
2915 printk(KERN_WARNING
2916 "%s: Couldn't register rs232 IOC4 serial driver\n",
2917 __func__);
2918 goto out;
2919 }
2920 if ((ret = uart_register_driver(&ioc4_uart_rs422)) < 0) {
2921 printk(KERN_WARNING
2922 "%s: Couldn't register rs422 IOC4 serial driver\n",
2923 __func__);
2924 goto out_uart_rs232;
2925 }
2926
2927 /* register with IOC4 main module */
2928 ret = ioc4_register_submodule(&ioc4_serial_submodule);
2929 if (ret)
2930 goto out_uart_rs422;
2931 return 0;
2932
2933out_uart_rs422:
2934 uart_unregister_driver(&ioc4_uart_rs422);
2935out_uart_rs232:
2936 uart_unregister_driver(&ioc4_uart_rs232);
2937out:
2938 return ret;
2939}
2940
2941static void __exit ioc4_serial_exit(void)
2942{
2943 ioc4_unregister_submodule(&ioc4_serial_submodule);
2944 uart_unregister_driver(&ioc4_uart_rs232);
2945 uart_unregister_driver(&ioc4_uart_rs422);
2946}
2947
2948late_initcall(ioc4_serial_init); /* Call only after tty init is done */
2949module_exit(ioc4_serial_exit);
2950
2951MODULE_AUTHOR("Pat Gefre - Silicon Graphics Inc. (SGI) <pfg@sgi.com>");
2952MODULE_DESCRIPTION("Serial PCI driver module for SGI IOC4 Base-IO Card");
2953MODULE_LICENSE("GPL");
diff --git a/drivers/serial/ip22zilog.c b/drivers/serial/ip22zilog.c
deleted file mode 100644
index ebff4a1d4bcc..000000000000
--- a/drivers/serial/ip22zilog.c
+++ /dev/null
@@ -1,1221 +0,0 @@
1/*
2 * Driver for Zilog serial chips found on SGI workstations and
3 * servers. This driver could actually be made more generic.
4 *
5 * This is based on the drivers/serial/sunzilog.c code as of 2.6.0-test7 and the
6 * old drivers/sgi/char/sgiserial.c code which itself is based of the original
7 * drivers/sbus/char/zs.c code. A lot of code has been simply moved over
8 * directly from there but much has been rewritten. Credits therefore go out
9 * to David S. Miller, Eddie C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell
10 * for their work there.
11 *
12 * Copyright (C) 2002 Ralf Baechle (ralf@linux-mips.org)
13 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
14 */
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/errno.h>
18#include <linux/delay.h>
19#include <linux/tty.h>
20#include <linux/tty_flip.h>
21#include <linux/major.h>
22#include <linux/string.h>
23#include <linux/ptrace.h>
24#include <linux/ioport.h>
25#include <linux/slab.h>
26#include <linux/circ_buf.h>
27#include <linux/serial.h>
28#include <linux/sysrq.h>
29#include <linux/console.h>
30#include <linux/spinlock.h>
31#include <linux/init.h>
32
33#include <asm/io.h>
34#include <asm/irq.h>
35#include <asm/sgialib.h>
36#include <asm/sgi/ioc.h>
37#include <asm/sgi/hpc3.h>
38#include <asm/sgi/ip22.h>
39
40#if defined(CONFIG_SERIAL_IP22_ZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
41#define SUPPORT_SYSRQ
42#endif
43
44#include <linux/serial_core.h>
45
46#include "ip22zilog.h"
47
48/*
49 * On IP22 we need to delay after register accesses but we do not need to
50 * flush writes.
51 */
52#define ZSDELAY() udelay(5)
53#define ZSDELAY_LONG() udelay(20)
54#define ZS_WSYNC(channel) do { } while (0)
55
56#define NUM_IP22ZILOG 1
57#define NUM_CHANNELS (NUM_IP22ZILOG * 2)
58
59#define ZS_CLOCK 3672000 /* Zilog input clock rate. */
60#define ZS_CLOCK_DIVISOR 16 /* Divisor this driver uses. */
61
62/*
63 * We wrap our port structure around the generic uart_port.
64 */
65struct uart_ip22zilog_port {
66 struct uart_port port;
67
68 /* IRQ servicing chain. */
69 struct uart_ip22zilog_port *next;
70
71 /* Current values of Zilog write registers. */
72 unsigned char curregs[NUM_ZSREGS];
73
74 unsigned int flags;
75#define IP22ZILOG_FLAG_IS_CONS 0x00000004
76#define IP22ZILOG_FLAG_IS_KGDB 0x00000008
77#define IP22ZILOG_FLAG_MODEM_STATUS 0x00000010
78#define IP22ZILOG_FLAG_IS_CHANNEL_A 0x00000020
79#define IP22ZILOG_FLAG_REGS_HELD 0x00000040
80#define IP22ZILOG_FLAG_TX_STOPPED 0x00000080
81#define IP22ZILOG_FLAG_TX_ACTIVE 0x00000100
82#define IP22ZILOG_FLAG_RESET_DONE 0x00000200
83
84 unsigned int tty_break;
85
86 unsigned char parity_mask;
87 unsigned char prev_status;
88};
89
90#define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel *)((PORT)->membase))
91#define UART_ZILOG(PORT) ((struct uart_ip22zilog_port *)(PORT))
92#define IP22ZILOG_GET_CURR_REG(PORT, REGNUM) \
93 (UART_ZILOG(PORT)->curregs[REGNUM])
94#define IP22ZILOG_SET_CURR_REG(PORT, REGNUM, REGVAL) \
95 ((UART_ZILOG(PORT)->curregs[REGNUM]) = (REGVAL))
96#define ZS_IS_CONS(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CONS)
97#define ZS_IS_KGDB(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_KGDB)
98#define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & IP22ZILOG_FLAG_MODEM_STATUS)
99#define ZS_IS_CHANNEL_A(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CHANNEL_A)
100#define ZS_REGS_HELD(UP) ((UP)->flags & IP22ZILOG_FLAG_REGS_HELD)
101#define ZS_TX_STOPPED(UP) ((UP)->flags & IP22ZILOG_FLAG_TX_STOPPED)
102#define ZS_TX_ACTIVE(UP) ((UP)->flags & IP22ZILOG_FLAG_TX_ACTIVE)
103
104/* Reading and writing Zilog8530 registers. The delays are to make this
105 * driver work on the IP22 which needs a settling delay after each chip
106 * register access, other machines handle this in hardware via auxiliary
107 * flip-flops which implement the settle time we do in software.
108 *
109 * The port lock must be held and local IRQs must be disabled
110 * when {read,write}_zsreg is invoked.
111 */
112static unsigned char read_zsreg(struct zilog_channel *channel,
113 unsigned char reg)
114{
115 unsigned char retval;
116
117 writeb(reg, &channel->control);
118 ZSDELAY();
119 retval = readb(&channel->control);
120 ZSDELAY();
121
122 return retval;
123}
124
125static void write_zsreg(struct zilog_channel *channel,
126 unsigned char reg, unsigned char value)
127{
128 writeb(reg, &channel->control);
129 ZSDELAY();
130 writeb(value, &channel->control);
131 ZSDELAY();
132}
133
134static void ip22zilog_clear_fifo(struct zilog_channel *channel)
135{
136 int i;
137
138 for (i = 0; i < 32; i++) {
139 unsigned char regval;
140
141 regval = readb(&channel->control);
142 ZSDELAY();
143 if (regval & Rx_CH_AV)
144 break;
145
146 regval = read_zsreg(channel, R1);
147 readb(&channel->data);
148 ZSDELAY();
149
150 if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) {
151 writeb(ERR_RES, &channel->control);
152 ZSDELAY();
153 ZS_WSYNC(channel);
154 }
155 }
156}
157
158/* This function must only be called when the TX is not busy. The UART
159 * port lock must be held and local interrupts disabled.
160 */
161static void __load_zsregs(struct zilog_channel *channel, unsigned char *regs)
162{
163 int i;
164
165 /* Let pending transmits finish. */
166 for (i = 0; i < 1000; i++) {
167 unsigned char stat = read_zsreg(channel, R1);
168 if (stat & ALL_SNT)
169 break;
170 udelay(100);
171 }
172
173 writeb(ERR_RES, &channel->control);
174 ZSDELAY();
175 ZS_WSYNC(channel);
176
177 ip22zilog_clear_fifo(channel);
178
179 /* Disable all interrupts. */
180 write_zsreg(channel, R1,
181 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
182
183 /* Set parity, sync config, stop bits, and clock divisor. */
184 write_zsreg(channel, R4, regs[R4]);
185
186 /* Set misc. TX/RX control bits. */
187 write_zsreg(channel, R10, regs[R10]);
188
189 /* Set TX/RX controls sans the enable bits. */
190 write_zsreg(channel, R3, regs[R3] & ~RxENAB);
191 write_zsreg(channel, R5, regs[R5] & ~TxENAB);
192
193 /* Synchronous mode config. */
194 write_zsreg(channel, R6, regs[R6]);
195 write_zsreg(channel, R7, regs[R7]);
196
197 /* Don't mess with the interrupt vector (R2, unused by us) and
198 * master interrupt control (R9). We make sure this is setup
199 * properly at probe time then never touch it again.
200 */
201
202 /* Disable baud generator. */
203 write_zsreg(channel, R14, regs[R14] & ~BRENAB);
204
205 /* Clock mode control. */
206 write_zsreg(channel, R11, regs[R11]);
207
208 /* Lower and upper byte of baud rate generator divisor. */
209 write_zsreg(channel, R12, regs[R12]);
210 write_zsreg(channel, R13, regs[R13]);
211
212 /* Now rewrite R14, with BRENAB (if set). */
213 write_zsreg(channel, R14, regs[R14]);
214
215 /* External status interrupt control. */
216 write_zsreg(channel, R15, regs[R15]);
217
218 /* Reset external status interrupts. */
219 write_zsreg(channel, R0, RES_EXT_INT);
220 write_zsreg(channel, R0, RES_EXT_INT);
221
222 /* Rewrite R3/R5, this time without enables masked. */
223 write_zsreg(channel, R3, regs[R3]);
224 write_zsreg(channel, R5, regs[R5]);
225
226 /* Rewrite R1, this time without IRQ enabled masked. */
227 write_zsreg(channel, R1, regs[R1]);
228}
229
230/* Reprogram the Zilog channel HW registers with the copies found in the
231 * software state struct. If the transmitter is busy, we defer this update
232 * until the next TX complete interrupt. Else, we do it right now.
233 *
234 * The UART port lock must be held and local interrupts disabled.
235 */
236static void ip22zilog_maybe_update_regs(struct uart_ip22zilog_port *up,
237 struct zilog_channel *channel)
238{
239 if (!ZS_REGS_HELD(up)) {
240 if (ZS_TX_ACTIVE(up)) {
241 up->flags |= IP22ZILOG_FLAG_REGS_HELD;
242 } else {
243 __load_zsregs(channel, up->curregs);
244 }
245 }
246}
247
248#define Rx_BRK 0x0100 /* BREAK event software flag. */
249#define Rx_SYS 0x0200 /* SysRq event software flag. */
250
251static struct tty_struct *ip22zilog_receive_chars(struct uart_ip22zilog_port *up,
252 struct zilog_channel *channel)
253{
254 struct tty_struct *tty;
255 unsigned char ch, flag;
256 unsigned int r1;
257
258 tty = NULL;
259 if (up->port.state != NULL &&
260 up->port.state->port.tty != NULL)
261 tty = up->port.state->port.tty;
262
263 for (;;) {
264 ch = readb(&channel->control);
265 ZSDELAY();
266 if (!(ch & Rx_CH_AV))
267 break;
268
269 r1 = read_zsreg(channel, R1);
270 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
271 writeb(ERR_RES, &channel->control);
272 ZSDELAY();
273 ZS_WSYNC(channel);
274 }
275
276 ch = readb(&channel->data);
277 ZSDELAY();
278
279 ch &= up->parity_mask;
280
281 /* Handle the null char got when BREAK is removed. */
282 if (!ch)
283 r1 |= up->tty_break;
284
285 /* A real serial line, record the character and status. */
286 flag = TTY_NORMAL;
287 up->port.icount.rx++;
288 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | Rx_SYS | Rx_BRK)) {
289 up->tty_break = 0;
290
291 if (r1 & (Rx_SYS | Rx_BRK)) {
292 up->port.icount.brk++;
293 if (r1 & Rx_SYS)
294 continue;
295 r1 &= ~(PAR_ERR | CRC_ERR);
296 }
297 else if (r1 & PAR_ERR)
298 up->port.icount.parity++;
299 else if (r1 & CRC_ERR)
300 up->port.icount.frame++;
301 if (r1 & Rx_OVR)
302 up->port.icount.overrun++;
303 r1 &= up->port.read_status_mask;
304 if (r1 & Rx_BRK)
305 flag = TTY_BREAK;
306 else if (r1 & PAR_ERR)
307 flag = TTY_PARITY;
308 else if (r1 & CRC_ERR)
309 flag = TTY_FRAME;
310 }
311
312 if (uart_handle_sysrq_char(&up->port, ch))
313 continue;
314
315 if (tty)
316 uart_insert_char(&up->port, r1, Rx_OVR, ch, flag);
317 }
318 return tty;
319}
320
321static void ip22zilog_status_handle(struct uart_ip22zilog_port *up,
322 struct zilog_channel *channel)
323{
324 unsigned char status;
325
326 status = readb(&channel->control);
327 ZSDELAY();
328
329 writeb(RES_EXT_INT, &channel->control);
330 ZSDELAY();
331 ZS_WSYNC(channel);
332
333 if (up->curregs[R15] & BRKIE) {
334 if ((status & BRK_ABRT) && !(up->prev_status & BRK_ABRT)) {
335 if (uart_handle_break(&up->port))
336 up->tty_break = Rx_SYS;
337 else
338 up->tty_break = Rx_BRK;
339 }
340 }
341
342 if (ZS_WANTS_MODEM_STATUS(up)) {
343 if (status & SYNC)
344 up->port.icount.dsr++;
345
346 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
347 * But it does not tell us which bit has changed, we have to keep
348 * track of this ourselves.
349 */
350 if ((status ^ up->prev_status) ^ DCD)
351 uart_handle_dcd_change(&up->port,
352 (status & DCD));
353 if ((status ^ up->prev_status) ^ CTS)
354 uart_handle_cts_change(&up->port,
355 (status & CTS));
356
357 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
358 }
359
360 up->prev_status = status;
361}
362
363static void ip22zilog_transmit_chars(struct uart_ip22zilog_port *up,
364 struct zilog_channel *channel)
365{
366 struct circ_buf *xmit;
367
368 if (ZS_IS_CONS(up)) {
369 unsigned char status = readb(&channel->control);
370 ZSDELAY();
371
372 /* TX still busy? Just wait for the next TX done interrupt.
373 *
374 * It can occur because of how we do serial console writes. It would
375 * be nice to transmit console writes just like we normally would for
376 * a TTY line. (ie. buffered and TX interrupt driven). That is not
377 * easy because console writes cannot sleep. One solution might be
378 * to poll on enough port->xmit space becomming free. -DaveM
379 */
380 if (!(status & Tx_BUF_EMP))
381 return;
382 }
383
384 up->flags &= ~IP22ZILOG_FLAG_TX_ACTIVE;
385
386 if (ZS_REGS_HELD(up)) {
387 __load_zsregs(channel, up->curregs);
388 up->flags &= ~IP22ZILOG_FLAG_REGS_HELD;
389 }
390
391 if (ZS_TX_STOPPED(up)) {
392 up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED;
393 goto ack_tx_int;
394 }
395
396 if (up->port.x_char) {
397 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
398 writeb(up->port.x_char, &channel->data);
399 ZSDELAY();
400 ZS_WSYNC(channel);
401
402 up->port.icount.tx++;
403 up->port.x_char = 0;
404 return;
405 }
406
407 if (up->port.state == NULL)
408 goto ack_tx_int;
409 xmit = &up->port.state->xmit;
410 if (uart_circ_empty(xmit))
411 goto ack_tx_int;
412 if (uart_tx_stopped(&up->port))
413 goto ack_tx_int;
414
415 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
416 writeb(xmit->buf[xmit->tail], &channel->data);
417 ZSDELAY();
418 ZS_WSYNC(channel);
419
420 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
421 up->port.icount.tx++;
422
423 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
424 uart_write_wakeup(&up->port);
425
426 return;
427
428ack_tx_int:
429 writeb(RES_Tx_P, &channel->control);
430 ZSDELAY();
431 ZS_WSYNC(channel);
432}
433
434static irqreturn_t ip22zilog_interrupt(int irq, void *dev_id)
435{
436 struct uart_ip22zilog_port *up = dev_id;
437
438 while (up) {
439 struct zilog_channel *channel
440 = ZILOG_CHANNEL_FROM_PORT(&up->port);
441 struct tty_struct *tty;
442 unsigned char r3;
443
444 spin_lock(&up->port.lock);
445 r3 = read_zsreg(channel, R3);
446
447 /* Channel A */
448 tty = NULL;
449 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
450 writeb(RES_H_IUS, &channel->control);
451 ZSDELAY();
452 ZS_WSYNC(channel);
453
454 if (r3 & CHARxIP)
455 tty = ip22zilog_receive_chars(up, channel);
456 if (r3 & CHAEXT)
457 ip22zilog_status_handle(up, channel);
458 if (r3 & CHATxIP)
459 ip22zilog_transmit_chars(up, channel);
460 }
461 spin_unlock(&up->port.lock);
462
463 if (tty)
464 tty_flip_buffer_push(tty);
465
466 /* Channel B */
467 up = up->next;
468 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
469
470 spin_lock(&up->port.lock);
471 tty = NULL;
472 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
473 writeb(RES_H_IUS, &channel->control);
474 ZSDELAY();
475 ZS_WSYNC(channel);
476
477 if (r3 & CHBRxIP)
478 tty = ip22zilog_receive_chars(up, channel);
479 if (r3 & CHBEXT)
480 ip22zilog_status_handle(up, channel);
481 if (r3 & CHBTxIP)
482 ip22zilog_transmit_chars(up, channel);
483 }
484 spin_unlock(&up->port.lock);
485
486 if (tty)
487 tty_flip_buffer_push(tty);
488
489 up = up->next;
490 }
491
492 return IRQ_HANDLED;
493}
494
495/* A convenient way to quickly get R0 status. The caller must _not_ hold the
496 * port lock, it is acquired here.
497 */
498static __inline__ unsigned char ip22zilog_read_channel_status(struct uart_port *port)
499{
500 struct zilog_channel *channel;
501 unsigned char status;
502
503 channel = ZILOG_CHANNEL_FROM_PORT(port);
504 status = readb(&channel->control);
505 ZSDELAY();
506
507 return status;
508}
509
510/* The port lock is not held. */
511static unsigned int ip22zilog_tx_empty(struct uart_port *port)
512{
513 unsigned long flags;
514 unsigned char status;
515 unsigned int ret;
516
517 spin_lock_irqsave(&port->lock, flags);
518
519 status = ip22zilog_read_channel_status(port);
520
521 spin_unlock_irqrestore(&port->lock, flags);
522
523 if (status & Tx_BUF_EMP)
524 ret = TIOCSER_TEMT;
525 else
526 ret = 0;
527
528 return ret;
529}
530
531/* The port lock is held and interrupts are disabled. */
532static unsigned int ip22zilog_get_mctrl(struct uart_port *port)
533{
534 unsigned char status;
535 unsigned int ret;
536
537 status = ip22zilog_read_channel_status(port);
538
539 ret = 0;
540 if (status & DCD)
541 ret |= TIOCM_CAR;
542 if (status & SYNC)
543 ret |= TIOCM_DSR;
544 if (status & CTS)
545 ret |= TIOCM_CTS;
546
547 return ret;
548}
549
550/* The port lock is held and interrupts are disabled. */
551static void ip22zilog_set_mctrl(struct uart_port *port, unsigned int mctrl)
552{
553 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
554 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
555 unsigned char set_bits, clear_bits;
556
557 set_bits = clear_bits = 0;
558
559 if (mctrl & TIOCM_RTS)
560 set_bits |= RTS;
561 else
562 clear_bits |= RTS;
563 if (mctrl & TIOCM_DTR)
564 set_bits |= DTR;
565 else
566 clear_bits |= DTR;
567
568 /* NOTE: Not subject to 'transmitter active' rule. */
569 up->curregs[R5] |= set_bits;
570 up->curregs[R5] &= ~clear_bits;
571 write_zsreg(channel, R5, up->curregs[R5]);
572}
573
574/* The port lock is held and interrupts are disabled. */
575static void ip22zilog_stop_tx(struct uart_port *port)
576{
577 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
578
579 up->flags |= IP22ZILOG_FLAG_TX_STOPPED;
580}
581
582/* The port lock is held and interrupts are disabled. */
583static void ip22zilog_start_tx(struct uart_port *port)
584{
585 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
586 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
587 unsigned char status;
588
589 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
590 up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED;
591
592 status = readb(&channel->control);
593 ZSDELAY();
594
595 /* TX busy? Just wait for the TX done interrupt. */
596 if (!(status & Tx_BUF_EMP))
597 return;
598
599 /* Send the first character to jump-start the TX done
600 * IRQ sending engine.
601 */
602 if (port->x_char) {
603 writeb(port->x_char, &channel->data);
604 ZSDELAY();
605 ZS_WSYNC(channel);
606
607 port->icount.tx++;
608 port->x_char = 0;
609 } else {
610 struct circ_buf *xmit = &port->state->xmit;
611
612 writeb(xmit->buf[xmit->tail], &channel->data);
613 ZSDELAY();
614 ZS_WSYNC(channel);
615
616 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
617 port->icount.tx++;
618
619 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
620 uart_write_wakeup(&up->port);
621 }
622}
623
624/* The port lock is held and interrupts are disabled. */
625static void ip22zilog_stop_rx(struct uart_port *port)
626{
627 struct uart_ip22zilog_port *up = UART_ZILOG(port);
628 struct zilog_channel *channel;
629
630 if (ZS_IS_CONS(up))
631 return;
632
633 channel = ZILOG_CHANNEL_FROM_PORT(port);
634
635 /* Disable all RX interrupts. */
636 up->curregs[R1] &= ~RxINT_MASK;
637 ip22zilog_maybe_update_regs(up, channel);
638}
639
640/* The port lock is held. */
641static void ip22zilog_enable_ms(struct uart_port *port)
642{
643 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
644 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
645 unsigned char new_reg;
646
647 new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
648 if (new_reg != up->curregs[R15]) {
649 up->curregs[R15] = new_reg;
650
651 /* NOTE: Not subject to 'transmitter active' rule. */
652 write_zsreg(channel, R15, up->curregs[R15]);
653 }
654}
655
656/* The port lock is not held. */
657static void ip22zilog_break_ctl(struct uart_port *port, int break_state)
658{
659 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
660 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
661 unsigned char set_bits, clear_bits, new_reg;
662 unsigned long flags;
663
664 set_bits = clear_bits = 0;
665
666 if (break_state)
667 set_bits |= SND_BRK;
668 else
669 clear_bits |= SND_BRK;
670
671 spin_lock_irqsave(&port->lock, flags);
672
673 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
674 if (new_reg != up->curregs[R5]) {
675 up->curregs[R5] = new_reg;
676
677 /* NOTE: Not subject to 'transmitter active' rule. */
678 write_zsreg(channel, R5, up->curregs[R5]);
679 }
680
681 spin_unlock_irqrestore(&port->lock, flags);
682}
683
684static void __ip22zilog_reset(struct uart_ip22zilog_port *up)
685{
686 struct zilog_channel *channel;
687 int i;
688
689 if (up->flags & IP22ZILOG_FLAG_RESET_DONE)
690 return;
691
692 /* Let pending transmits finish. */
693 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
694 for (i = 0; i < 1000; i++) {
695 unsigned char stat = read_zsreg(channel, R1);
696 if (stat & ALL_SNT)
697 break;
698 udelay(100);
699 }
700
701 if (!ZS_IS_CHANNEL_A(up)) {
702 up++;
703 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
704 }
705 write_zsreg(channel, R9, FHWRES);
706 ZSDELAY_LONG();
707 (void) read_zsreg(channel, R0);
708
709 up->flags |= IP22ZILOG_FLAG_RESET_DONE;
710 up->next->flags |= IP22ZILOG_FLAG_RESET_DONE;
711}
712
713static void __ip22zilog_startup(struct uart_ip22zilog_port *up)
714{
715 struct zilog_channel *channel;
716
717 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
718
719 __ip22zilog_reset(up);
720
721 __load_zsregs(channel, up->curregs);
722 /* set master interrupt enable */
723 write_zsreg(channel, R9, up->curregs[R9]);
724 up->prev_status = readb(&channel->control);
725
726 /* Enable receiver and transmitter. */
727 up->curregs[R3] |= RxENAB;
728 up->curregs[R5] |= TxENAB;
729
730 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
731 ip22zilog_maybe_update_regs(up, channel);
732}
733
734static int ip22zilog_startup(struct uart_port *port)
735{
736 struct uart_ip22zilog_port *up = UART_ZILOG(port);
737 unsigned long flags;
738
739 if (ZS_IS_CONS(up))
740 return 0;
741
742 spin_lock_irqsave(&port->lock, flags);
743 __ip22zilog_startup(up);
744 spin_unlock_irqrestore(&port->lock, flags);
745 return 0;
746}
747
748/*
749 * The test for ZS_IS_CONS is explained by the following e-mail:
750 *****
751 * From: Russell King <rmk@arm.linux.org.uk>
752 * Date: Sun, 8 Dec 2002 10:18:38 +0000
753 *
754 * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote:
755 * > I boot my 2.5 boxes using "console=ttyS0,9600" argument,
756 * > and I noticed that something is not right with reference
757 * > counting in this case. It seems that when the console
758 * > is open by kernel initially, this is not accounted
759 * > as an open, and uart_startup is not called.
760 *
761 * That is correct. We are unable to call uart_startup when the serial
762 * console is initialised because it may need to allocate memory (as
763 * request_irq does) and the memory allocators may not have been
764 * initialised.
765 *
766 * 1. initialise the port into a state where it can send characters in the
767 * console write method.
768 *
769 * 2. don't do the actual hardware shutdown in your shutdown() method (but
770 * do the normal software shutdown - ie, free irqs etc)
771 *****
772 */
773static void ip22zilog_shutdown(struct uart_port *port)
774{
775 struct uart_ip22zilog_port *up = UART_ZILOG(port);
776 struct zilog_channel *channel;
777 unsigned long flags;
778
779 if (ZS_IS_CONS(up))
780 return;
781
782 spin_lock_irqsave(&port->lock, flags);
783
784 channel = ZILOG_CHANNEL_FROM_PORT(port);
785
786 /* Disable receiver and transmitter. */
787 up->curregs[R3] &= ~RxENAB;
788 up->curregs[R5] &= ~TxENAB;
789
790 /* Disable all interrupts and BRK assertion. */
791 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
792 up->curregs[R5] &= ~SND_BRK;
793 ip22zilog_maybe_update_regs(up, channel);
794
795 spin_unlock_irqrestore(&port->lock, flags);
796}
797
798/* Shared by TTY driver and serial console setup. The port lock is held
799 * and local interrupts are disabled.
800 */
801static void
802ip22zilog_convert_to_zs(struct uart_ip22zilog_port *up, unsigned int cflag,
803 unsigned int iflag, int brg)
804{
805
806 up->curregs[R10] = NRZ;
807 up->curregs[R11] = TCBR | RCBR;
808
809 /* Program BAUD and clock source. */
810 up->curregs[R4] &= ~XCLK_MASK;
811 up->curregs[R4] |= X16CLK;
812 up->curregs[R12] = brg & 0xff;
813 up->curregs[R13] = (brg >> 8) & 0xff;
814 up->curregs[R14] = BRENAB;
815
816 /* Character size, stop bits, and parity. */
817 up->curregs[3] &= ~RxN_MASK;
818 up->curregs[5] &= ~TxN_MASK;
819 switch (cflag & CSIZE) {
820 case CS5:
821 up->curregs[3] |= Rx5;
822 up->curregs[5] |= Tx5;
823 up->parity_mask = 0x1f;
824 break;
825 case CS6:
826 up->curregs[3] |= Rx6;
827 up->curregs[5] |= Tx6;
828 up->parity_mask = 0x3f;
829 break;
830 case CS7:
831 up->curregs[3] |= Rx7;
832 up->curregs[5] |= Tx7;
833 up->parity_mask = 0x7f;
834 break;
835 case CS8:
836 default:
837 up->curregs[3] |= Rx8;
838 up->curregs[5] |= Tx8;
839 up->parity_mask = 0xff;
840 break;
841 };
842 up->curregs[4] &= ~0x0c;
843 if (cflag & CSTOPB)
844 up->curregs[4] |= SB2;
845 else
846 up->curregs[4] |= SB1;
847 if (cflag & PARENB)
848 up->curregs[4] |= PAR_ENAB;
849 else
850 up->curregs[4] &= ~PAR_ENAB;
851 if (!(cflag & PARODD))
852 up->curregs[4] |= PAR_EVEN;
853 else
854 up->curregs[4] &= ~PAR_EVEN;
855
856 up->port.read_status_mask = Rx_OVR;
857 if (iflag & INPCK)
858 up->port.read_status_mask |= CRC_ERR | PAR_ERR;
859 if (iflag & (BRKINT | PARMRK))
860 up->port.read_status_mask |= BRK_ABRT;
861
862 up->port.ignore_status_mask = 0;
863 if (iflag & IGNPAR)
864 up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
865 if (iflag & IGNBRK) {
866 up->port.ignore_status_mask |= BRK_ABRT;
867 if (iflag & IGNPAR)
868 up->port.ignore_status_mask |= Rx_OVR;
869 }
870
871 if ((cflag & CREAD) == 0)
872 up->port.ignore_status_mask = 0xff;
873}
874
875/* The port lock is not held. */
876static void
877ip22zilog_set_termios(struct uart_port *port, struct ktermios *termios,
878 struct ktermios *old)
879{
880 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
881 unsigned long flags;
882 int baud, brg;
883
884 baud = uart_get_baud_rate(port, termios, old, 1200, 76800);
885
886 spin_lock_irqsave(&up->port.lock, flags);
887
888 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
889
890 ip22zilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
891
892 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
893 up->flags |= IP22ZILOG_FLAG_MODEM_STATUS;
894 else
895 up->flags &= ~IP22ZILOG_FLAG_MODEM_STATUS;
896
897 ip22zilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
898 uart_update_timeout(port, termios->c_cflag, baud);
899
900 spin_unlock_irqrestore(&up->port.lock, flags);
901}
902
903static const char *ip22zilog_type(struct uart_port *port)
904{
905 return "IP22-Zilog";
906}
907
908/* We do not request/release mappings of the registers here, this
909 * happens at early serial probe time.
910 */
911static void ip22zilog_release_port(struct uart_port *port)
912{
913}
914
915static int ip22zilog_request_port(struct uart_port *port)
916{
917 return 0;
918}
919
920/* These do not need to do anything interesting either. */
921static void ip22zilog_config_port(struct uart_port *port, int flags)
922{
923}
924
925/* We do not support letting the user mess with the divisor, IRQ, etc. */
926static int ip22zilog_verify_port(struct uart_port *port, struct serial_struct *ser)
927{
928 return -EINVAL;
929}
930
931static struct uart_ops ip22zilog_pops = {
932 .tx_empty = ip22zilog_tx_empty,
933 .set_mctrl = ip22zilog_set_mctrl,
934 .get_mctrl = ip22zilog_get_mctrl,
935 .stop_tx = ip22zilog_stop_tx,
936 .start_tx = ip22zilog_start_tx,
937 .stop_rx = ip22zilog_stop_rx,
938 .enable_ms = ip22zilog_enable_ms,
939 .break_ctl = ip22zilog_break_ctl,
940 .startup = ip22zilog_startup,
941 .shutdown = ip22zilog_shutdown,
942 .set_termios = ip22zilog_set_termios,
943 .type = ip22zilog_type,
944 .release_port = ip22zilog_release_port,
945 .request_port = ip22zilog_request_port,
946 .config_port = ip22zilog_config_port,
947 .verify_port = ip22zilog_verify_port,
948};
949
950static struct uart_ip22zilog_port *ip22zilog_port_table;
951static struct zilog_layout **ip22zilog_chip_regs;
952
953static struct uart_ip22zilog_port *ip22zilog_irq_chain;
954static int zilog_irq = -1;
955
956static void * __init alloc_one_table(unsigned long size)
957{
958 return kzalloc(size, GFP_KERNEL);
959}
960
961static void __init ip22zilog_alloc_tables(void)
962{
963 ip22zilog_port_table = (struct uart_ip22zilog_port *)
964 alloc_one_table(NUM_CHANNELS * sizeof(struct uart_ip22zilog_port));
965 ip22zilog_chip_regs = (struct zilog_layout **)
966 alloc_one_table(NUM_IP22ZILOG * sizeof(struct zilog_layout *));
967
968 if (ip22zilog_port_table == NULL || ip22zilog_chip_regs == NULL) {
969 panic("IP22-Zilog: Cannot allocate IP22-Zilog tables.");
970 }
971}
972
973/* Get the address of the registers for IP22-Zilog instance CHIP. */
974static struct zilog_layout * __init get_zs(int chip)
975{
976 unsigned long base;
977
978 if (chip < 0 || chip >= NUM_IP22ZILOG) {
979 panic("IP22-Zilog: Illegal chip number %d in get_zs.", chip);
980 }
981
982 /* Not probe-able, hard code it. */
983 base = (unsigned long) &sgioc->uart;
984
985 zilog_irq = SGI_SERIAL_IRQ;
986 request_mem_region(base, 8, "IP22-Zilog");
987
988 return (struct zilog_layout *) base;
989}
990
991#define ZS_PUT_CHAR_MAX_DELAY 2000 /* 10 ms */
992
993#ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE
994static void ip22zilog_put_char(struct uart_port *port, int ch)
995{
996 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
997 int loops = ZS_PUT_CHAR_MAX_DELAY;
998
999 /* This is a timed polling loop so do not switch the explicit
1000 * udelay with ZSDELAY as that is a NOP on some platforms. -DaveM
1001 */
1002 do {
1003 unsigned char val = readb(&channel->control);
1004 if (val & Tx_BUF_EMP) {
1005 ZSDELAY();
1006 break;
1007 }
1008 udelay(5);
1009 } while (--loops);
1010
1011 writeb(ch, &channel->data);
1012 ZSDELAY();
1013 ZS_WSYNC(channel);
1014}
1015
1016static void
1017ip22zilog_console_write(struct console *con, const char *s, unsigned int count)
1018{
1019 struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index];
1020 unsigned long flags;
1021
1022 spin_lock_irqsave(&up->port.lock, flags);
1023 uart_console_write(&up->port, s, count, ip22zilog_put_char);
1024 udelay(2);
1025 spin_unlock_irqrestore(&up->port.lock, flags);
1026}
1027
1028static int __init ip22zilog_console_setup(struct console *con, char *options)
1029{
1030 struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index];
1031 unsigned long flags;
1032 int baud = 9600, bits = 8;
1033 int parity = 'n';
1034 int flow = 'n';
1035
1036 up->flags |= IP22ZILOG_FLAG_IS_CONS;
1037
1038 printk(KERN_INFO "Console: ttyS%d (IP22-Zilog)\n", con->index);
1039
1040 spin_lock_irqsave(&up->port.lock, flags);
1041
1042 up->curregs[R15] |= BRKIE;
1043
1044 __ip22zilog_startup(up);
1045
1046 spin_unlock_irqrestore(&up->port.lock, flags);
1047
1048 if (options)
1049 uart_parse_options(options, &baud, &parity, &bits, &flow);
1050 return uart_set_options(&up->port, con, baud, parity, bits, flow);
1051}
1052
1053static struct uart_driver ip22zilog_reg;
1054
1055static struct console ip22zilog_console = {
1056 .name = "ttyS",
1057 .write = ip22zilog_console_write,
1058 .device = uart_console_device,
1059 .setup = ip22zilog_console_setup,
1060 .flags = CON_PRINTBUFFER,
1061 .index = -1,
1062 .data = &ip22zilog_reg,
1063};
1064#endif /* CONFIG_SERIAL_IP22_ZILOG_CONSOLE */
1065
1066static struct uart_driver ip22zilog_reg = {
1067 .owner = THIS_MODULE,
1068 .driver_name = "serial",
1069 .dev_name = "ttyS",
1070 .major = TTY_MAJOR,
1071 .minor = 64,
1072 .nr = NUM_CHANNELS,
1073#ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE
1074 .cons = &ip22zilog_console,
1075#endif
1076};
1077
1078static void __init ip22zilog_prepare(void)
1079{
1080 struct uart_ip22zilog_port *up;
1081 struct zilog_layout *rp;
1082 int channel, chip;
1083
1084 /*
1085 * Temporary fix.
1086 */
1087 for (channel = 0; channel < NUM_CHANNELS; channel++)
1088 spin_lock_init(&ip22zilog_port_table[channel].port.lock);
1089
1090 ip22zilog_irq_chain = &ip22zilog_port_table[NUM_CHANNELS - 1];
1091 up = &ip22zilog_port_table[0];
1092 for (channel = NUM_CHANNELS - 1 ; channel > 0; channel--)
1093 up[channel].next = &up[channel - 1];
1094 up[channel].next = NULL;
1095
1096 for (chip = 0; chip < NUM_IP22ZILOG; chip++) {
1097 if (!ip22zilog_chip_regs[chip]) {
1098 ip22zilog_chip_regs[chip] = rp = get_zs(chip);
1099
1100 up[(chip * 2) + 0].port.membase = (char *) &rp->channelB;
1101 up[(chip * 2) + 1].port.membase = (char *) &rp->channelA;
1102
1103 /* In theory mapbase is the physical address ... */
1104 up[(chip * 2) + 0].port.mapbase =
1105 (unsigned long) ioremap((unsigned long) &rp->channelB, 8);
1106 up[(chip * 2) + 1].port.mapbase =
1107 (unsigned long) ioremap((unsigned long) &rp->channelA, 8);
1108 }
1109
1110 /* Channel A */
1111 up[(chip * 2) + 0].port.iotype = UPIO_MEM;
1112 up[(chip * 2) + 0].port.irq = zilog_irq;
1113 up[(chip * 2) + 0].port.uartclk = ZS_CLOCK;
1114 up[(chip * 2) + 0].port.fifosize = 1;
1115 up[(chip * 2) + 0].port.ops = &ip22zilog_pops;
1116 up[(chip * 2) + 0].port.type = PORT_IP22ZILOG;
1117 up[(chip * 2) + 0].port.flags = 0;
1118 up[(chip * 2) + 0].port.line = (chip * 2) + 0;
1119 up[(chip * 2) + 0].flags = 0;
1120
1121 /* Channel B */
1122 up[(chip * 2) + 1].port.iotype = UPIO_MEM;
1123 up[(chip * 2) + 1].port.irq = zilog_irq;
1124 up[(chip * 2) + 1].port.uartclk = ZS_CLOCK;
1125 up[(chip * 2) + 1].port.fifosize = 1;
1126 up[(chip * 2) + 1].port.ops = &ip22zilog_pops;
1127 up[(chip * 2) + 1].port.type = PORT_IP22ZILOG;
1128 up[(chip * 2) + 1].port.line = (chip * 2) + 1;
1129 up[(chip * 2) + 1].flags |= IP22ZILOG_FLAG_IS_CHANNEL_A;
1130 }
1131
1132 for (channel = 0; channel < NUM_CHANNELS; channel++) {
1133 struct uart_ip22zilog_port *up = &ip22zilog_port_table[channel];
1134 int brg;
1135
1136 /* Normal serial TTY. */
1137 up->parity_mask = 0xff;
1138 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1139 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1140 up->curregs[R3] = RxENAB | Rx8;
1141 up->curregs[R5] = TxENAB | Tx8;
1142 up->curregs[R9] = NV | MIE;
1143 up->curregs[R10] = NRZ;
1144 up->curregs[R11] = TCBR | RCBR;
1145 brg = BPS_TO_BRG(9600, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1146 up->curregs[R12] = (brg & 0xff);
1147 up->curregs[R13] = (brg >> 8) & 0xff;
1148 up->curregs[R14] = BRENAB;
1149 }
1150}
1151
1152static int __init ip22zilog_ports_init(void)
1153{
1154 int ret;
1155
1156 printk(KERN_INFO "Serial: IP22 Zilog driver (%d chips).\n", NUM_IP22ZILOG);
1157
1158 ip22zilog_prepare();
1159
1160 if (request_irq(zilog_irq, ip22zilog_interrupt, 0,
1161 "IP22-Zilog", ip22zilog_irq_chain)) {
1162 panic("IP22-Zilog: Unable to register zs interrupt handler.\n");
1163 }
1164
1165 ret = uart_register_driver(&ip22zilog_reg);
1166 if (ret == 0) {
1167 int i;
1168
1169 for (i = 0; i < NUM_CHANNELS; i++) {
1170 struct uart_ip22zilog_port *up = &ip22zilog_port_table[i];
1171
1172 uart_add_one_port(&ip22zilog_reg, &up->port);
1173 }
1174 }
1175
1176 return ret;
1177}
1178
1179static int __init ip22zilog_init(void)
1180{
1181 /* IP22 Zilog setup is hard coded, no probing to do. */
1182 ip22zilog_alloc_tables();
1183 ip22zilog_ports_init();
1184
1185 return 0;
1186}
1187
1188static void __exit ip22zilog_exit(void)
1189{
1190 int i;
1191 struct uart_ip22zilog_port *up;
1192
1193 for (i = 0; i < NUM_CHANNELS; i++) {
1194 up = &ip22zilog_port_table[i];
1195
1196 uart_remove_one_port(&ip22zilog_reg, &up->port);
1197 }
1198
1199 /* Free IO mem */
1200 up = &ip22zilog_port_table[0];
1201 for (i = 0; i < NUM_IP22ZILOG; i++) {
1202 if (up[(i * 2) + 0].port.mapbase) {
1203 iounmap((void*)up[(i * 2) + 0].port.mapbase);
1204 up[(i * 2) + 0].port.mapbase = 0;
1205 }
1206 if (up[(i * 2) + 1].port.mapbase) {
1207 iounmap((void*)up[(i * 2) + 1].port.mapbase);
1208 up[(i * 2) + 1].port.mapbase = 0;
1209 }
1210 }
1211
1212 uart_unregister_driver(&ip22zilog_reg);
1213}
1214
1215module_init(ip22zilog_init);
1216module_exit(ip22zilog_exit);
1217
1218/* David wrote it but I'm to blame for the bugs ... */
1219MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
1220MODULE_DESCRIPTION("SGI Zilog serial port driver");
1221MODULE_LICENSE("GPL");
diff --git a/drivers/serial/ip22zilog.h b/drivers/serial/ip22zilog.h
deleted file mode 100644
index a59a9a8341d2..000000000000
--- a/drivers/serial/ip22zilog.h
+++ /dev/null
@@ -1,281 +0,0 @@
1#ifndef _IP22_ZILOG_H
2#define _IP22_ZILOG_H
3
4#include <asm/byteorder.h>
5
6struct zilog_channel {
7#ifdef __BIG_ENDIAN
8 volatile unsigned char unused0[3];
9 volatile unsigned char control;
10 volatile unsigned char unused1[3];
11 volatile unsigned char data;
12#else /* __LITTLE_ENDIAN */
13 volatile unsigned char control;
14 volatile unsigned char unused0[3];
15 volatile unsigned char data;
16 volatile unsigned char unused1[3];
17#endif
18};
19
20struct zilog_layout {
21 struct zilog_channel channelB;
22 struct zilog_channel channelA;
23};
24
25#define NUM_ZSREGS 16
26
27/* Conversion routines to/from brg time constants from/to bits
28 * per second.
29 */
30#define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
31#define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
32
33/* The Zilog register set */
34
35#define FLAG 0x7e
36
37/* Write Register 0 */
38#define R0 0 /* Register selects */
39#define R1 1
40#define R2 2
41#define R3 3
42#define R4 4
43#define R5 5
44#define R6 6
45#define R7 7
46#define R8 8
47#define R9 9
48#define R10 10
49#define R11 11
50#define R12 12
51#define R13 13
52#define R14 14
53#define R15 15
54
55#define NULLCODE 0 /* Null Code */
56#define POINT_HIGH 0x8 /* Select upper half of registers */
57#define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
58#define SEND_ABORT 0x18 /* HDLC Abort */
59#define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
60#define RES_Tx_P 0x28 /* Reset TxINT Pending */
61#define ERR_RES 0x30 /* Error Reset */
62#define RES_H_IUS 0x38 /* Reset highest IUS */
63
64#define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
65#define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
66#define RES_EOM_L 0xC0 /* Reset EOM latch */
67
68/* Write Register 1 */
69
70#define EXT_INT_ENAB 0x1 /* Ext Int Enable */
71#define TxINT_ENAB 0x2 /* Tx Int Enable */
72#define PAR_SPEC 0x4 /* Parity is special condition */
73
74#define RxINT_DISAB 0 /* Rx Int Disable */
75#define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
76#define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */
77#define INT_ERR_Rx 0x18 /* Int on error only */
78#define RxINT_MASK 0x18
79
80#define WT_RDY_RT 0x20 /* Wait/Ready on R/T */
81#define WT_FN_RDYFN 0x40 /* Wait/FN/Ready FN */
82#define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
83
84/* Write Register #2 (Interrupt Vector) */
85
86/* Write Register 3 */
87
88#define RxENAB 0x1 /* Rx Enable */
89#define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
90#define ADD_SM 0x4 /* Address Search Mode (SDLC) */
91#define RxCRC_ENAB 0x8 /* Rx CRC Enable */
92#define ENT_HM 0x10 /* Enter Hunt Mode */
93#define AUTO_ENAB 0x20 /* Auto Enables */
94#define Rx5 0x0 /* Rx 5 Bits/Character */
95#define Rx7 0x40 /* Rx 7 Bits/Character */
96#define Rx6 0x80 /* Rx 6 Bits/Character */
97#define Rx8 0xc0 /* Rx 8 Bits/Character */
98#define RxN_MASK 0xc0
99
100/* Write Register 4 */
101
102#define PAR_ENAB 0x1 /* Parity Enable */
103#define PAR_EVEN 0x2 /* Parity Even/Odd* */
104
105#define SYNC_ENAB 0 /* Sync Modes Enable */
106#define SB1 0x4 /* 1 stop bit/char */
107#define SB15 0x8 /* 1.5 stop bits/char */
108#define SB2 0xc /* 2 stop bits/char */
109
110#define MONSYNC 0 /* 8 Bit Sync character */
111#define BISYNC 0x10 /* 16 bit sync character */
112#define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
113#define EXTSYNC 0x30 /* External Sync Mode */
114
115#define X1CLK 0x0 /* x1 clock mode */
116#define X16CLK 0x40 /* x16 clock mode */
117#define X32CLK 0x80 /* x32 clock mode */
118#define X64CLK 0xC0 /* x64 clock mode */
119#define XCLK_MASK 0xC0
120
121/* Write Register 5 */
122
123#define TxCRC_ENAB 0x1 /* Tx CRC Enable */
124#define RTS 0x2 /* RTS */
125#define SDLC_CRC 0x4 /* SDLC/CRC-16 */
126#define TxENAB 0x8 /* Tx Enable */
127#define SND_BRK 0x10 /* Send Break */
128#define Tx5 0x0 /* Tx 5 bits (or less)/character */
129#define Tx7 0x20 /* Tx 7 bits/character */
130#define Tx6 0x40 /* Tx 6 bits/character */
131#define Tx8 0x60 /* Tx 8 bits/character */
132#define TxN_MASK 0x60
133#define DTR 0x80 /* DTR */
134
135/* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
136
137/* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
138
139/* Write Register 8 (transmit buffer) */
140
141/* Write Register 9 (Master interrupt control) */
142#define VIS 1 /* Vector Includes Status */
143#define NV 2 /* No Vector */
144#define DLC 4 /* Disable Lower Chain */
145#define MIE 8 /* Master Interrupt Enable */
146#define STATHI 0x10 /* Status high */
147#define NORESET 0 /* No reset on write to R9 */
148#define CHRB 0x40 /* Reset channel B */
149#define CHRA 0x80 /* Reset channel A */
150#define FHWRES 0xc0 /* Force hardware reset */
151
152/* Write Register 10 (misc control bits) */
153#define BIT6 1 /* 6 bit/8bit sync */
154#define LOOPMODE 2 /* SDLC Loop mode */
155#define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */
156#define MARKIDLE 8 /* Mark/flag on idle */
157#define GAOP 0x10 /* Go active on poll */
158#define NRZ 0 /* NRZ mode */
159#define NRZI 0x20 /* NRZI mode */
160#define FM1 0x40 /* FM1 (transition = 1) */
161#define FM0 0x60 /* FM0 (transition = 0) */
162#define CRCPS 0x80 /* CRC Preset I/O */
163
164/* Write Register 11 (Clock Mode control) */
165#define TRxCXT 0 /* TRxC = Xtal output */
166#define TRxCTC 1 /* TRxC = Transmit clock */
167#define TRxCBR 2 /* TRxC = BR Generator Output */
168#define TRxCDP 3 /* TRxC = DPLL output */
169#define TRxCOI 4 /* TRxC O/I */
170#define TCRTxCP 0 /* Transmit clock = RTxC pin */
171#define TCTRxCP 8 /* Transmit clock = TRxC pin */
172#define TCBR 0x10 /* Transmit clock = BR Generator output */
173#define TCDPLL 0x18 /* Transmit clock = DPLL output */
174#define RCRTxCP 0 /* Receive clock = RTxC pin */
175#define RCTRxCP 0x20 /* Receive clock = TRxC pin */
176#define RCBR 0x40 /* Receive clock = BR Generator output */
177#define RCDPLL 0x60 /* Receive clock = DPLL output */
178#define RTxCX 0x80 /* RTxC Xtal/No Xtal */
179
180/* Write Register 12 (lower byte of baud rate generator time constant) */
181
182/* Write Register 13 (upper byte of baud rate generator time constant) */
183
184/* Write Register 14 (Misc control bits) */
185#define BRENAB 1 /* Baud rate generator enable */
186#define BRSRC 2 /* Baud rate generator source */
187#define DTRREQ 4 /* DTR/Request function */
188#define AUTOECHO 8 /* Auto Echo */
189#define LOOPBAK 0x10 /* Local loopback */
190#define SEARCH 0x20 /* Enter search mode */
191#define RMC 0x40 /* Reset missing clock */
192#define DISDPLL 0x60 /* Disable DPLL */
193#define SSBR 0x80 /* Set DPLL source = BR generator */
194#define SSRTxC 0xa0 /* Set DPLL source = RTxC */
195#define SFMM 0xc0 /* Set FM mode */
196#define SNRZI 0xe0 /* Set NRZI mode */
197
198/* Write Register 15 (external/status interrupt control) */
199#define ZCIE 2 /* Zero count IE */
200#define DCDIE 8 /* DCD IE */
201#define SYNCIE 0x10 /* Sync/hunt IE */
202#define CTSIE 0x20 /* CTS IE */
203#define TxUIE 0x40 /* Tx Underrun/EOM IE */
204#define BRKIE 0x80 /* Break/Abort IE */
205
206
207/* Read Register 0 */
208#define Rx_CH_AV 0x1 /* Rx Character Available */
209#define ZCOUNT 0x2 /* Zero count */
210#define Tx_BUF_EMP 0x4 /* Tx Buffer empty */
211#define DCD 0x8 /* DCD */
212#define SYNC 0x10 /* Sync/hunt */
213#define CTS 0x20 /* CTS */
214#define TxEOM 0x40 /* Tx underrun */
215#define BRK_ABRT 0x80 /* Break/Abort */
216
217/* Read Register 1 */
218#define ALL_SNT 0x1 /* All sent */
219/* Residue Data for 8 Rx bits/char programmed */
220#define RES3 0x8 /* 0/3 */
221#define RES4 0x4 /* 0/4 */
222#define RES5 0xc /* 0/5 */
223#define RES6 0x2 /* 0/6 */
224#define RES7 0xa /* 0/7 */
225#define RES8 0x6 /* 0/8 */
226#define RES18 0xe /* 1/8 */
227#define RES28 0x0 /* 2/8 */
228/* Special Rx Condition Interrupts */
229#define PAR_ERR 0x10 /* Parity error */
230#define Rx_OVR 0x20 /* Rx Overrun Error */
231#define CRC_ERR 0x40 /* CRC/Framing Error */
232#define END_FR 0x80 /* End of Frame (SDLC) */
233
234/* Read Register 2 (channel b only) - Interrupt vector */
235#define CHB_Tx_EMPTY 0x00
236#define CHB_EXT_STAT 0x02
237#define CHB_Rx_AVAIL 0x04
238#define CHB_SPECIAL 0x06
239#define CHA_Tx_EMPTY 0x08
240#define CHA_EXT_STAT 0x0a
241#define CHA_Rx_AVAIL 0x0c
242#define CHA_SPECIAL 0x0e
243#define STATUS_MASK 0x0e
244
245/* Read Register 3 (interrupt pending register) ch a only */
246#define CHBEXT 0x1 /* Channel B Ext/Stat IP */
247#define CHBTxIP 0x2 /* Channel B Tx IP */
248#define CHBRxIP 0x4 /* Channel B Rx IP */
249#define CHAEXT 0x8 /* Channel A Ext/Stat IP */
250#define CHATxIP 0x10 /* Channel A Tx IP */
251#define CHARxIP 0x20 /* Channel A Rx IP */
252
253/* Read Register 8 (receive data register) */
254
255/* Read Register 10 (misc status bits) */
256#define ONLOOP 2 /* On loop */
257#define LOOPSEND 0x10 /* Loop sending */
258#define CLK2MIS 0x40 /* Two clocks missing */
259#define CLK1MIS 0x80 /* One clock missing */
260
261/* Read Register 12 (lower byte of baud rate generator constant) */
262
263/* Read Register 13 (upper byte of baud rate generator constant) */
264
265/* Read Register 15 (value of WR 15) */
266
267/* Misc macros */
268#define ZS_CLEARERR(channel) do { writeb(ERR_RES, &channel->control); \
269 udelay(5); } while(0)
270
271#define ZS_CLEARSTAT(channel) do { writeb(RES_EXT_INT, &channel->control); \
272 udelay(5); } while(0)
273
274#define ZS_CLEARFIFO(channel) do { readb(&channel->data); \
275 udelay(2); \
276 readb(&channel->data); \
277 udelay(2); \
278 readb(&channel->data); \
279 udelay(2); } while(0)
280
281#endif /* _IP22_ZILOG_H */
diff --git a/drivers/serial/jsm/Makefile b/drivers/serial/jsm/Makefile
deleted file mode 100644
index e46b6e0f8b18..000000000000
--- a/drivers/serial/jsm/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
1#
2# Makefile for Jasmine adapter
3#
4
5obj-$(CONFIG_SERIAL_JSM) += jsm.o
6
7jsm-objs := jsm_driver.o jsm_neo.o jsm_tty.o
8
diff --git a/drivers/serial/jsm/jsm.h b/drivers/serial/jsm/jsm.h
deleted file mode 100644
index 38a509c684cd..000000000000
--- a/drivers/serial/jsm/jsm.h
+++ /dev/null
@@ -1,388 +0,0 @@
1/************************************************************************
2 * Copyright 2003 Digi International (www.digi.com)
3 *
4 * Copyright (C) 2004 IBM Corporation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2, or (at your option)
9 * any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
13 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
14 * PURPOSE. See the GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 * Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
20 *
21 * Contact Information:
22 * Scott H Kilau <Scott_Kilau@digi.com>
23 * Wendy Xiong <wendyx@us.ibm.com>
24 *
25 ***********************************************************************/
26
27#ifndef __JSM_DRIVER_H
28#define __JSM_DRIVER_H
29
30#include <linux/kernel.h>
31#include <linux/types.h> /* To pick up the varions Linux types */
32#include <linux/tty.h>
33#include <linux/serial_core.h>
34#include <linux/device.h>
35
36/*
37 * Debugging levels can be set using debug insmod variable
38 * They can also be compiled out completely.
39 */
40enum {
41 DBG_INIT = 0x01,
42 DBG_BASIC = 0x02,
43 DBG_CORE = 0x04,
44 DBG_OPEN = 0x08,
45 DBG_CLOSE = 0x10,
46 DBG_READ = 0x20,
47 DBG_WRITE = 0x40,
48 DBG_IOCTL = 0x80,
49 DBG_PROC = 0x100,
50 DBG_PARAM = 0x200,
51 DBG_PSCAN = 0x400,
52 DBG_EVENT = 0x800,
53 DBG_DRAIN = 0x1000,
54 DBG_MSIGS = 0x2000,
55 DBG_MGMT = 0x4000,
56 DBG_INTR = 0x8000,
57 DBG_CARR = 0x10000,
58};
59
60#define jsm_printk(nlevel, klevel, pdev, fmt, args...) \
61 if ((DBG_##nlevel & jsm_debug)) \
62 dev_printk(KERN_##klevel, pdev->dev, fmt, ## args)
63
64#define MAXLINES 256
65#define MAXPORTS 8
66#define MAX_STOPS_SENT 5
67
68/* Board type definitions */
69
70#define T_NEO 0000
71#define T_CLASSIC 0001
72#define T_PCIBUS 0400
73
74/* Board State Definitions */
75
76#define BD_RUNNING 0x0
77#define BD_REASON 0x7f
78#define BD_NOTFOUND 0x1
79#define BD_NOIOPORT 0x2
80#define BD_NOMEM 0x3
81#define BD_NOBIOS 0x4
82#define BD_NOFEP 0x5
83#define BD_FAILED 0x6
84#define BD_ALLOCATED 0x7
85#define BD_TRIBOOT 0x8
86#define BD_BADKME 0x80
87
88
89/* 4 extra for alignment play space */
90#define WRITEBUFLEN ((4096) + 4)
91#define MYFLIPLEN N_TTY_BUF_SIZE
92
93#define JSM_VERSION "jsm: 1.2-1-INKERNEL"
94#define JSM_PARTNUM "40002438_A-INKERNEL"
95
96struct jsm_board;
97struct jsm_channel;
98
99/************************************************************************
100 * Per board operations structure *
101 ************************************************************************/
102struct board_ops {
103 irq_handler_t intr;
104 void (*uart_init) (struct jsm_channel *ch);
105 void (*uart_off) (struct jsm_channel *ch);
106 void (*param) (struct jsm_channel *ch);
107 void (*assert_modem_signals) (struct jsm_channel *ch);
108 void (*flush_uart_write) (struct jsm_channel *ch);
109 void (*flush_uart_read) (struct jsm_channel *ch);
110 void (*disable_receiver) (struct jsm_channel *ch);
111 void (*enable_receiver) (struct jsm_channel *ch);
112 void (*send_break) (struct jsm_channel *ch);
113 void (*clear_break) (struct jsm_channel *ch, int);
114 void (*send_start_character) (struct jsm_channel *ch);
115 void (*send_stop_character) (struct jsm_channel *ch);
116 void (*copy_data_from_queue_to_uart) (struct jsm_channel *ch);
117 u32 (*get_uart_bytes_left) (struct jsm_channel *ch);
118 void (*send_immediate_char) (struct jsm_channel *ch, unsigned char);
119};
120
121
122/*
123 * Per-board information
124 */
125struct jsm_board
126{
127 int boardnum; /* Board number: 0-32 */
128
129 int type; /* Type of board */
130 u8 rev; /* PCI revision ID */
131 struct pci_dev *pci_dev;
132 u32 maxports; /* MAX ports this board can handle */
133
134 spinlock_t bd_intr_lock; /* Used to protect the poller tasklet and
135 * the interrupt routine from each other.
136 */
137
138 u32 nasync; /* Number of ports on card */
139
140 u32 irq; /* Interrupt request number */
141
142 u64 membase; /* Start of base memory of the card */
143 u64 membase_end; /* End of base memory of the card */
144
145 u8 __iomem *re_map_membase;/* Remapped memory of the card */
146
147 u64 iobase; /* Start of io base of the card */
148 u64 iobase_end; /* End of io base of the card */
149
150 u32 bd_uart_offset; /* Space between each UART */
151
152 struct jsm_channel *channels[MAXPORTS]; /* array of pointers to our channels. */
153 char *flipbuf; /* Our flip buffer, alloced if board is found */
154
155 u32 bd_dividend; /* Board/UARTs specific dividend */
156
157 struct board_ops *bd_ops;
158
159 struct list_head jsm_board_entry;
160};
161
162/************************************************************************
163 * Device flag definitions for ch_flags.
164 ************************************************************************/
165#define CH_PRON 0x0001 /* Printer on string */
166#define CH_STOP 0x0002 /* Output is stopped */
167#define CH_STOPI 0x0004 /* Input is stopped */
168#define CH_CD 0x0008 /* Carrier is present */
169#define CH_FCAR 0x0010 /* Carrier forced on */
170#define CH_HANGUP 0x0020 /* Hangup received */
171
172#define CH_RECEIVER_OFF 0x0040 /* Receiver is off */
173#define CH_OPENING 0x0080 /* Port in fragile open state */
174#define CH_CLOSING 0x0100 /* Port in fragile close state */
175#define CH_FIFO_ENABLED 0x0200 /* Port has FIFOs enabled */
176#define CH_TX_FIFO_EMPTY 0x0400 /* TX Fifo is completely empty */
177#define CH_TX_FIFO_LWM 0x0800 /* TX Fifo is below Low Water */
178#define CH_BREAK_SENDING 0x1000 /* Break is being sent */
179#define CH_LOOPBACK 0x2000 /* Channel is in lookback mode */
180#define CH_FLIPBUF_IN_USE 0x4000 /* Channel's flipbuf is in use */
181#define CH_BAUD0 0x08000 /* Used for checking B0 transitions */
182
183/* Our Read/Error/Write queue sizes */
184#define RQUEUEMASK 0x1FFF /* 8 K - 1 */
185#define EQUEUEMASK 0x1FFF /* 8 K - 1 */
186#define WQUEUEMASK 0x0FFF /* 4 K - 1 */
187#define RQUEUESIZE (RQUEUEMASK + 1)
188#define EQUEUESIZE RQUEUESIZE
189#define WQUEUESIZE (WQUEUEMASK + 1)
190
191
192/************************************************************************
193 * Channel information structure.
194 ************************************************************************/
195struct jsm_channel {
196 struct uart_port uart_port;
197 struct jsm_board *ch_bd; /* Board structure pointer */
198
199 spinlock_t ch_lock; /* provide for serialization */
200 wait_queue_head_t ch_flags_wait;
201
202 u32 ch_portnum; /* Port number, 0 offset. */
203 u32 ch_open_count; /* open count */
204 u32 ch_flags; /* Channel flags */
205
206 u64 ch_close_delay; /* How long we should drop RTS/DTR for */
207
208 tcflag_t ch_c_iflag; /* channel iflags */
209 tcflag_t ch_c_cflag; /* channel cflags */
210 tcflag_t ch_c_oflag; /* channel oflags */
211 tcflag_t ch_c_lflag; /* channel lflags */
212 u8 ch_stopc; /* Stop character */
213 u8 ch_startc; /* Start character */
214
215 u8 ch_mostat; /* FEP output modem status */
216 u8 ch_mistat; /* FEP input modem status */
217
218 struct neo_uart_struct __iomem *ch_neo_uart; /* Pointer to the "mapped" UART struct */
219 u8 ch_cached_lsr; /* Cached value of the LSR register */
220
221 u8 *ch_rqueue; /* Our read queue buffer - malloc'ed */
222 u16 ch_r_head; /* Head location of the read queue */
223 u16 ch_r_tail; /* Tail location of the read queue */
224
225 u8 *ch_equeue; /* Our error queue buffer - malloc'ed */
226 u16 ch_e_head; /* Head location of the error queue */
227 u16 ch_e_tail; /* Tail location of the error queue */
228
229 u8 *ch_wqueue; /* Our write queue buffer - malloc'ed */
230 u16 ch_w_head; /* Head location of the write queue */
231 u16 ch_w_tail; /* Tail location of the write queue */
232
233 u64 ch_rxcount; /* total of data received so far */
234 u64 ch_txcount; /* total of data transmitted so far */
235
236 u8 ch_r_tlevel; /* Receive Trigger level */
237 u8 ch_t_tlevel; /* Transmit Trigger level */
238
239 u8 ch_r_watermark; /* Receive Watermark */
240
241
242 u32 ch_stops_sent; /* How many times I have sent a stop character
243 * to try to stop the other guy sending.
244 */
245 u64 ch_err_parity; /* Count of parity errors on channel */
246 u64 ch_err_frame; /* Count of framing errors on channel */
247 u64 ch_err_break; /* Count of breaks on channel */
248 u64 ch_err_overrun; /* Count of overruns on channel */
249
250 u64 ch_xon_sends; /* Count of xons transmitted */
251 u64 ch_xoff_sends; /* Count of xoffs transmitted */
252};
253
254
255/************************************************************************
256 * Per channel/port NEO UART structure *
257 ************************************************************************
258 * Base Structure Entries Usage Meanings to Host *
259 * *
260 * W = read write R = read only *
261 * U = Unused. *
262 ************************************************************************/
263
264struct neo_uart_struct {
265 u8 txrx; /* WR RHR/THR - Holding Reg */
266 u8 ier; /* WR IER - Interrupt Enable Reg */
267 u8 isr_fcr; /* WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg */
268 u8 lcr; /* WR LCR - Line Control Reg */
269 u8 mcr; /* WR MCR - Modem Control Reg */
270 u8 lsr; /* WR LSR - Line Status Reg */
271 u8 msr; /* WR MSR - Modem Status Reg */
272 u8 spr; /* WR SPR - Scratch Pad Reg */
273 u8 fctr; /* WR FCTR - Feature Control Reg */
274 u8 efr; /* WR EFR - Enhanced Function Reg */
275 u8 tfifo; /* WR TXCNT/TXTRG - Transmit FIFO Reg */
276 u8 rfifo; /* WR RXCNT/RXTRG - Recieve FIFO Reg */
277 u8 xoffchar1; /* WR XOFF 1 - XOff Character 1 Reg */
278 u8 xoffchar2; /* WR XOFF 2 - XOff Character 2 Reg */
279 u8 xonchar1; /* WR XON 1 - Xon Character 1 Reg */
280 u8 xonchar2; /* WR XON 2 - XOn Character 2 Reg */
281
282 u8 reserved1[0x2ff - 0x200]; /* U Reserved by Exar */
283 u8 txrxburst[64]; /* RW 64 bytes of RX/TX FIFO Data */
284 u8 reserved2[0x37f - 0x340]; /* U Reserved by Exar */
285 u8 rxburst_with_errors[64]; /* R 64 bytes of RX FIFO Data + LSR */
286};
287
288/* Where to read the extended interrupt register (32bits instead of 8bits) */
289#define UART_17158_POLL_ADDR_OFFSET 0x80
290
291/*
292 * These are the redefinitions for the FCTR on the XR17C158, since
293 * Exar made them different than their earlier design. (XR16C854)
294 */
295
296/* These are only applicable when table D is selected */
297#define UART_17158_FCTR_RTS_NODELAY 0x00
298#define UART_17158_FCTR_RTS_4DELAY 0x01
299#define UART_17158_FCTR_RTS_6DELAY 0x02
300#define UART_17158_FCTR_RTS_8DELAY 0x03
301#define UART_17158_FCTR_RTS_12DELAY 0x12
302#define UART_17158_FCTR_RTS_16DELAY 0x05
303#define UART_17158_FCTR_RTS_20DELAY 0x13
304#define UART_17158_FCTR_RTS_24DELAY 0x06
305#define UART_17158_FCTR_RTS_28DELAY 0x14
306#define UART_17158_FCTR_RTS_32DELAY 0x07
307#define UART_17158_FCTR_RTS_36DELAY 0x16
308#define UART_17158_FCTR_RTS_40DELAY 0x08
309#define UART_17158_FCTR_RTS_44DELAY 0x09
310#define UART_17158_FCTR_RTS_48DELAY 0x10
311#define UART_17158_FCTR_RTS_52DELAY 0x11
312
313#define UART_17158_FCTR_RTS_IRDA 0x10
314#define UART_17158_FCTR_RS485 0x20
315#define UART_17158_FCTR_TRGA 0x00
316#define UART_17158_FCTR_TRGB 0x40
317#define UART_17158_FCTR_TRGC 0x80
318#define UART_17158_FCTR_TRGD 0xC0
319
320/* 17158 trigger table selects.. */
321#define UART_17158_FCTR_BIT6 0x40
322#define UART_17158_FCTR_BIT7 0x80
323
324/* 17158 TX/RX memmapped buffer offsets */
325#define UART_17158_RX_FIFOSIZE 64
326#define UART_17158_TX_FIFOSIZE 64
327
328/* 17158 Extended IIR's */
329#define UART_17158_IIR_RDI_TIMEOUT 0x0C /* Receiver data TIMEOUT */
330#define UART_17158_IIR_XONXOFF 0x10 /* Received an XON/XOFF char */
331#define UART_17158_IIR_HWFLOW_STATE_CHANGE 0x20 /* CTS/DSR or RTS/DTR state change */
332#define UART_17158_IIR_FIFO_ENABLED 0xC0 /* 16550 FIFOs are Enabled */
333
334/*
335 * These are the extended interrupts that get sent
336 * back to us from the UART's 32bit interrupt register
337 */
338#define UART_17158_RX_LINE_STATUS 0x1 /* RX Ready */
339#define UART_17158_RXRDY_TIMEOUT 0x2 /* RX Ready Timeout */
340#define UART_17158_TXRDY 0x3 /* TX Ready */
341#define UART_17158_MSR 0x4 /* Modem State Change */
342#define UART_17158_TX_AND_FIFO_CLR 0x40 /* Transmitter Holding Reg Empty */
343#define UART_17158_RX_FIFO_DATA_ERROR 0x80 /* UART detected an RX FIFO Data error */
344
345/*
346 * These are the EXTENDED definitions for the 17C158's Interrupt
347 * Enable Register.
348 */
349#define UART_17158_EFR_ECB 0x10 /* Enhanced control bit */
350#define UART_17158_EFR_IXON 0x2 /* Receiver compares Xon1/Xoff1 */
351#define UART_17158_EFR_IXOFF 0x8 /* Transmit Xon1/Xoff1 */
352#define UART_17158_EFR_RTSDTR 0x40 /* Auto RTS/DTR Flow Control Enable */
353#define UART_17158_EFR_CTSDSR 0x80 /* Auto CTS/DSR Flow COntrol Enable */
354
355#define UART_17158_XOFF_DETECT 0x1 /* Indicates whether chip saw an incoming XOFF char */
356#define UART_17158_XON_DETECT 0x2 /* Indicates whether chip saw an incoming XON char */
357
358#define UART_17158_IER_RSVD1 0x10 /* Reserved by Exar */
359#define UART_17158_IER_XOFF 0x20 /* Xoff Interrupt Enable */
360#define UART_17158_IER_RTSDTR 0x40 /* Output Interrupt Enable */
361#define UART_17158_IER_CTSDSR 0x80 /* Input Interrupt Enable */
362
363#define PCI_DEVICE_NEO_2DB9_PCI_NAME "Neo 2 - DB9 Universal PCI"
364#define PCI_DEVICE_NEO_2DB9PRI_PCI_NAME "Neo 2 - DB9 Universal PCI - Powered Ring Indicator"
365#define PCI_DEVICE_NEO_2RJ45_PCI_NAME "Neo 2 - RJ45 Universal PCI"
366#define PCI_DEVICE_NEO_2RJ45PRI_PCI_NAME "Neo 2 - RJ45 Universal PCI - Powered Ring Indicator"
367#define PCIE_DEVICE_NEO_IBM_PCI_NAME "Neo 4 - PCI Express - IBM"
368
369/*
370 * Our Global Variables.
371 */
372extern struct uart_driver jsm_uart_driver;
373extern struct board_ops jsm_neo_ops;
374extern int jsm_debug;
375
376/*************************************************************************
377 *
378 * Prototypes for non-static functions used in more than one module
379 *
380 *************************************************************************/
381int jsm_tty_write(struct uart_port *port);
382int jsm_tty_init(struct jsm_board *);
383int jsm_uart_port_init(struct jsm_board *);
384int jsm_remove_uart_port(struct jsm_board *);
385void jsm_input(struct jsm_channel *ch);
386void jsm_check_queue_flow_control(struct jsm_channel *ch);
387
388#endif
diff --git a/drivers/serial/jsm/jsm_driver.c b/drivers/serial/jsm/jsm_driver.c
deleted file mode 100644
index eaf545014119..000000000000
--- a/drivers/serial/jsm/jsm_driver.c
+++ /dev/null
@@ -1,295 +0,0 @@
1/************************************************************************
2 * Copyright 2003 Digi International (www.digi.com)
3 *
4 * Copyright (C) 2004 IBM Corporation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2, or (at your option)
9 * any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
13 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
14 * PURPOSE. See the GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 * Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
20 *
21 * Contact Information:
22 * Scott H Kilau <Scott_Kilau@digi.com>
23 * Wendy Xiong <wendyx@us.ibm.com>
24 *
25 *
26 ***********************************************************************/
27#include <linux/moduleparam.h>
28#include <linux/pci.h>
29#include <linux/slab.h>
30
31#include "jsm.h"
32
33MODULE_AUTHOR("Digi International, http://www.digi.com");
34MODULE_DESCRIPTION("Driver for the Digi International "
35 "Neo PCI based product line");
36MODULE_LICENSE("GPL");
37MODULE_SUPPORTED_DEVICE("jsm");
38
39#define JSM_DRIVER_NAME "jsm"
40#define NR_PORTS 32
41#define JSM_MINOR_START 0
42
43struct uart_driver jsm_uart_driver = {
44 .owner = THIS_MODULE,
45 .driver_name = JSM_DRIVER_NAME,
46 .dev_name = "ttyn",
47 .major = 0,
48 .minor = JSM_MINOR_START,
49 .nr = NR_PORTS,
50};
51
52static pci_ers_result_t jsm_io_error_detected(struct pci_dev *pdev,
53 pci_channel_state_t state);
54static pci_ers_result_t jsm_io_slot_reset(struct pci_dev *pdev);
55static void jsm_io_resume(struct pci_dev *pdev);
56
57static struct pci_error_handlers jsm_err_handler = {
58 .error_detected = jsm_io_error_detected,
59 .slot_reset = jsm_io_slot_reset,
60 .resume = jsm_io_resume,
61};
62
63int jsm_debug;
64module_param(jsm_debug, int, 0);
65MODULE_PARM_DESC(jsm_debug, "Driver debugging level");
66
67static int __devinit jsm_probe_one(struct pci_dev *pdev, const struct pci_device_id *ent)
68{
69 int rc = 0;
70 struct jsm_board *brd;
71 static int adapter_count = 0;
72
73 rc = pci_enable_device(pdev);
74 if (rc) {
75 dev_err(&pdev->dev, "Device enable FAILED\n");
76 goto out;
77 }
78
79 rc = pci_request_regions(pdev, "jsm");
80 if (rc) {
81 dev_err(&pdev->dev, "pci_request_region FAILED\n");
82 goto out_disable_device;
83 }
84
85 brd = kzalloc(sizeof(struct jsm_board), GFP_KERNEL);
86 if (!brd) {
87 dev_err(&pdev->dev,
88 "memory allocation for board structure failed\n");
89 rc = -ENOMEM;
90 goto out_release_regions;
91 }
92
93 /* store the info for the board we've found */
94 brd->boardnum = adapter_count++;
95 brd->pci_dev = pdev;
96 if (pdev->device == PCIE_DEVICE_ID_NEO_4_IBM)
97 brd->maxports = 4;
98 else if (pdev->device == PCI_DEVICE_ID_DIGI_NEO_8)
99 brd->maxports = 8;
100 else
101 brd->maxports = 2;
102
103 spin_lock_init(&brd->bd_intr_lock);
104
105 /* store which revision we have */
106 brd->rev = pdev->revision;
107
108 brd->irq = pdev->irq;
109
110 jsm_printk(INIT, INFO, &brd->pci_dev,
111 "jsm_found_board - NEO adapter\n");
112
113 /* get the PCI Base Address Registers */
114 brd->membase = pci_resource_start(pdev, 0);
115 brd->membase_end = pci_resource_end(pdev, 0);
116
117 if (brd->membase & 1)
118 brd->membase &= ~3;
119 else
120 brd->membase &= ~15;
121
122 /* Assign the board_ops struct */
123 brd->bd_ops = &jsm_neo_ops;
124
125 brd->bd_uart_offset = 0x200;
126 brd->bd_dividend = 921600;
127
128 brd->re_map_membase = ioremap(brd->membase, 0x1000);
129 if (!brd->re_map_membase) {
130 dev_err(&pdev->dev,
131 "card has no PCI Memory resources, "
132 "failing board.\n");
133 rc = -ENOMEM;
134 goto out_kfree_brd;
135 }
136
137 rc = request_irq(brd->irq, brd->bd_ops->intr,
138 IRQF_SHARED, "JSM", brd);
139 if (rc) {
140 printk(KERN_WARNING "Failed to hook IRQ %d\n",brd->irq);
141 goto out_iounmap;
142 }
143
144 rc = jsm_tty_init(brd);
145 if (rc < 0) {
146 dev_err(&pdev->dev, "Can't init tty devices (%d)\n", rc);
147 rc = -ENXIO;
148 goto out_free_irq;
149 }
150
151 rc = jsm_uart_port_init(brd);
152 if (rc < 0) {
153 /* XXX: leaking all resources from jsm_tty_init here! */
154 dev_err(&pdev->dev, "Can't init uart port (%d)\n", rc);
155 rc = -ENXIO;
156 goto out_free_irq;
157 }
158
159 /* Log the information about the board */
160 dev_info(&pdev->dev, "board %d: Digi Neo (rev %d), irq %d\n",
161 adapter_count, brd->rev, brd->irq);
162
163 /*
164 * allocate flip buffer for board.
165 *
166 * Okay to malloc with GFP_KERNEL, we are not at interrupt
167 * context, and there are no locks held.
168 */
169 brd->flipbuf = kzalloc(MYFLIPLEN, GFP_KERNEL);
170 if (!brd->flipbuf) {
171 /* XXX: leaking all resources from jsm_tty_init and
172 jsm_uart_port_init here! */
173 dev_err(&pdev->dev, "memory allocation for flipbuf failed\n");
174 rc = -ENOMEM;
175 goto out_free_irq;
176 }
177
178 pci_set_drvdata(pdev, brd);
179 pci_save_state(pdev);
180
181 return 0;
182 out_free_irq:
183 jsm_remove_uart_port(brd);
184 free_irq(brd->irq, brd);
185 out_iounmap:
186 iounmap(brd->re_map_membase);
187 out_kfree_brd:
188 kfree(brd);
189 out_release_regions:
190 pci_release_regions(pdev);
191 out_disable_device:
192 pci_disable_device(pdev);
193 out:
194 return rc;
195}
196
197static void __devexit jsm_remove_one(struct pci_dev *pdev)
198{
199 struct jsm_board *brd = pci_get_drvdata(pdev);
200 int i = 0;
201
202 jsm_remove_uart_port(brd);
203
204 free_irq(brd->irq, brd);
205 iounmap(brd->re_map_membase);
206
207 /* Free all allocated channels structs */
208 for (i = 0; i < brd->maxports; i++) {
209 if (brd->channels[i]) {
210 kfree(brd->channels[i]->ch_rqueue);
211 kfree(brd->channels[i]->ch_equeue);
212 kfree(brd->channels[i]->ch_wqueue);
213 kfree(brd->channels[i]);
214 }
215 }
216
217 pci_release_regions(pdev);
218 pci_disable_device(pdev);
219 kfree(brd->flipbuf);
220 kfree(brd);
221}
222
223static struct pci_device_id jsm_pci_tbl[] = {
224 { PCI_DEVICE(PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_NEO_2DB9), 0, 0, 0 },
225 { PCI_DEVICE(PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_NEO_2DB9PRI), 0, 0, 1 },
226 { PCI_DEVICE(PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_NEO_2RJ45), 0, 0, 2 },
227 { PCI_DEVICE(PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_NEO_2RJ45PRI), 0, 0, 3 },
228 { PCI_DEVICE(PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_4_IBM), 0, 0, 4 },
229 { PCI_DEVICE(PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_NEO_8), 0, 0, 5 },
230 { 0, }
231};
232MODULE_DEVICE_TABLE(pci, jsm_pci_tbl);
233
234static struct pci_driver jsm_driver = {
235 .name = "jsm",
236 .id_table = jsm_pci_tbl,
237 .probe = jsm_probe_one,
238 .remove = __devexit_p(jsm_remove_one),
239 .err_handler = &jsm_err_handler,
240};
241
242static pci_ers_result_t jsm_io_error_detected(struct pci_dev *pdev,
243 pci_channel_state_t state)
244{
245 struct jsm_board *brd = pci_get_drvdata(pdev);
246
247 jsm_remove_uart_port(brd);
248
249 return PCI_ERS_RESULT_NEED_RESET;
250}
251
252static pci_ers_result_t jsm_io_slot_reset(struct pci_dev *pdev)
253{
254 int rc;
255
256 rc = pci_enable_device(pdev);
257
258 if (rc)
259 return PCI_ERS_RESULT_DISCONNECT;
260
261 pci_set_master(pdev);
262
263 return PCI_ERS_RESULT_RECOVERED;
264}
265
266static void jsm_io_resume(struct pci_dev *pdev)
267{
268 struct jsm_board *brd = pci_get_drvdata(pdev);
269
270 pci_restore_state(pdev);
271
272 jsm_uart_port_init(brd);
273}
274
275static int __init jsm_init_module(void)
276{
277 int rc;
278
279 rc = uart_register_driver(&jsm_uart_driver);
280 if (!rc) {
281 rc = pci_register_driver(&jsm_driver);
282 if (rc)
283 uart_unregister_driver(&jsm_uart_driver);
284 }
285 return rc;
286}
287
288static void __exit jsm_exit_module(void)
289{
290 pci_unregister_driver(&jsm_driver);
291 uart_unregister_driver(&jsm_uart_driver);
292}
293
294module_init(jsm_init_module);
295module_exit(jsm_exit_module);
diff --git a/drivers/serial/jsm/jsm_neo.c b/drivers/serial/jsm/jsm_neo.c
deleted file mode 100644
index 7960d9633c15..000000000000
--- a/drivers/serial/jsm/jsm_neo.c
+++ /dev/null
@@ -1,1412 +0,0 @@
1/************************************************************************
2 * Copyright 2003 Digi International (www.digi.com)
3 *
4 * Copyright (C) 2004 IBM Corporation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2, or (at your option)
9 * any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
13 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
14 * PURPOSE. See the GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 * Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
20 *
21 * Contact Information:
22 * Scott H Kilau <Scott_Kilau@digi.com>
23 * Wendy Xiong <wendyx@us.ibm.com>
24 *
25 ***********************************************************************/
26#include <linux/delay.h> /* For udelay */
27#include <linux/serial_reg.h> /* For the various UART offsets */
28#include <linux/tty.h>
29#include <linux/pci.h>
30#include <asm/io.h>
31
32#include "jsm.h" /* Driver main header file */
33
34static u32 jsm_offset_table[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 };
35
36/*
37 * This function allows calls to ensure that all outstanding
38 * PCI writes have been completed, by doing a PCI read against
39 * a non-destructive, read-only location on the Neo card.
40 *
41 * In this case, we are reading the DVID (Read-only Device Identification)
42 * value of the Neo card.
43 */
44static inline void neo_pci_posting_flush(struct jsm_board *bd)
45{
46 readb(bd->re_map_membase + 0x8D);
47}
48
49static void neo_set_cts_flow_control(struct jsm_channel *ch)
50{
51 u8 ier, efr;
52 ier = readb(&ch->ch_neo_uart->ier);
53 efr = readb(&ch->ch_neo_uart->efr);
54
55 jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n");
56
57 /* Turn on auto CTS flow control */
58 ier |= (UART_17158_IER_CTSDSR);
59 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR);
60
61 /* Turn off auto Xon flow control */
62 efr &= ~(UART_17158_EFR_IXON);
63
64 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
65 writeb(0, &ch->ch_neo_uart->efr);
66
67 /* Turn on UART enhanced bits */
68 writeb(efr, &ch->ch_neo_uart->efr);
69
70 /* Turn on table D, with 8 char hi/low watermarks */
71 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
72
73 /* Feed the UART our trigger levels */
74 writeb(8, &ch->ch_neo_uart->tfifo);
75 ch->ch_t_tlevel = 8;
76
77 writeb(ier, &ch->ch_neo_uart->ier);
78}
79
80static void neo_set_rts_flow_control(struct jsm_channel *ch)
81{
82 u8 ier, efr;
83 ier = readb(&ch->ch_neo_uart->ier);
84 efr = readb(&ch->ch_neo_uart->efr);
85
86 jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting RTSFLOW\n");
87
88 /* Turn on auto RTS flow control */
89 ier |= (UART_17158_IER_RTSDTR);
90 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR);
91
92 /* Turn off auto Xoff flow control */
93 ier &= ~(UART_17158_IER_XOFF);
94 efr &= ~(UART_17158_EFR_IXOFF);
95
96 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
97 writeb(0, &ch->ch_neo_uart->efr);
98
99 /* Turn on UART enhanced bits */
100 writeb(efr, &ch->ch_neo_uart->efr);
101
102 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
103 ch->ch_r_watermark = 4;
104
105 writeb(56, &ch->ch_neo_uart->rfifo);
106 ch->ch_r_tlevel = 56;
107
108 writeb(ier, &ch->ch_neo_uart->ier);
109
110 /*
111 * From the Neo UART spec sheet:
112 * The auto RTS/DTR function must be started by asserting
113 * RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after
114 * it is enabled.
115 */
116 ch->ch_mostat |= (UART_MCR_RTS);
117}
118
119
120static void neo_set_ixon_flow_control(struct jsm_channel *ch)
121{
122 u8 ier, efr;
123 ier = readb(&ch->ch_neo_uart->ier);
124 efr = readb(&ch->ch_neo_uart->efr);
125
126 jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting IXON FLOW\n");
127
128 /* Turn off auto CTS flow control */
129 ier &= ~(UART_17158_IER_CTSDSR);
130 efr &= ~(UART_17158_EFR_CTSDSR);
131
132 /* Turn on auto Xon flow control */
133 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON);
134
135 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
136 writeb(0, &ch->ch_neo_uart->efr);
137
138 /* Turn on UART enhanced bits */
139 writeb(efr, &ch->ch_neo_uart->efr);
140
141 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
142 ch->ch_r_watermark = 4;
143
144 writeb(32, &ch->ch_neo_uart->rfifo);
145 ch->ch_r_tlevel = 32;
146
147 /* Tell UART what start/stop chars it should be looking for */
148 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
149 writeb(0, &ch->ch_neo_uart->xonchar2);
150
151 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
152 writeb(0, &ch->ch_neo_uart->xoffchar2);
153
154 writeb(ier, &ch->ch_neo_uart->ier);
155}
156
157static void neo_set_ixoff_flow_control(struct jsm_channel *ch)
158{
159 u8 ier, efr;
160 ier = readb(&ch->ch_neo_uart->ier);
161 efr = readb(&ch->ch_neo_uart->efr);
162
163 jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting IXOFF FLOW\n");
164
165 /* Turn off auto RTS flow control */
166 ier &= ~(UART_17158_IER_RTSDTR);
167 efr &= ~(UART_17158_EFR_RTSDTR);
168
169 /* Turn on auto Xoff flow control */
170 ier |= (UART_17158_IER_XOFF);
171 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
172
173 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
174 writeb(0, &ch->ch_neo_uart->efr);
175
176 /* Turn on UART enhanced bits */
177 writeb(efr, &ch->ch_neo_uart->efr);
178
179 /* Turn on table D, with 8 char hi/low watermarks */
180 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
181
182 writeb(8, &ch->ch_neo_uart->tfifo);
183 ch->ch_t_tlevel = 8;
184
185 /* Tell UART what start/stop chars it should be looking for */
186 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
187 writeb(0, &ch->ch_neo_uart->xonchar2);
188
189 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
190 writeb(0, &ch->ch_neo_uart->xoffchar2);
191
192 writeb(ier, &ch->ch_neo_uart->ier);
193}
194
195static void neo_set_no_input_flow_control(struct jsm_channel *ch)
196{
197 u8 ier, efr;
198 ier = readb(&ch->ch_neo_uart->ier);
199 efr = readb(&ch->ch_neo_uart->efr);
200
201 jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Unsetting Input FLOW\n");
202
203 /* Turn off auto RTS flow control */
204 ier &= ~(UART_17158_IER_RTSDTR);
205 efr &= ~(UART_17158_EFR_RTSDTR);
206
207 /* Turn off auto Xoff flow control */
208 ier &= ~(UART_17158_IER_XOFF);
209 if (ch->ch_c_iflag & IXON)
210 efr &= ~(UART_17158_EFR_IXOFF);
211 else
212 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
213
214 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
215 writeb(0, &ch->ch_neo_uart->efr);
216
217 /* Turn on UART enhanced bits */
218 writeb(efr, &ch->ch_neo_uart->efr);
219
220 /* Turn on table D, with 8 char hi/low watermarks */
221 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
222
223 ch->ch_r_watermark = 0;
224
225 writeb(16, &ch->ch_neo_uart->tfifo);
226 ch->ch_t_tlevel = 16;
227
228 writeb(16, &ch->ch_neo_uart->rfifo);
229 ch->ch_r_tlevel = 16;
230
231 writeb(ier, &ch->ch_neo_uart->ier);
232}
233
234static void neo_set_no_output_flow_control(struct jsm_channel *ch)
235{
236 u8 ier, efr;
237 ier = readb(&ch->ch_neo_uart->ier);
238 efr = readb(&ch->ch_neo_uart->efr);
239
240 jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Unsetting Output FLOW\n");
241
242 /* Turn off auto CTS flow control */
243 ier &= ~(UART_17158_IER_CTSDSR);
244 efr &= ~(UART_17158_EFR_CTSDSR);
245
246 /* Turn off auto Xon flow control */
247 if (ch->ch_c_iflag & IXOFF)
248 efr &= ~(UART_17158_EFR_IXON);
249 else
250 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXON);
251
252 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
253 writeb(0, &ch->ch_neo_uart->efr);
254
255 /* Turn on UART enhanced bits */
256 writeb(efr, &ch->ch_neo_uart->efr);
257
258 /* Turn on table D, with 8 char hi/low watermarks */
259 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
260
261 ch->ch_r_watermark = 0;
262
263 writeb(16, &ch->ch_neo_uart->tfifo);
264 ch->ch_t_tlevel = 16;
265
266 writeb(16, &ch->ch_neo_uart->rfifo);
267 ch->ch_r_tlevel = 16;
268
269 writeb(ier, &ch->ch_neo_uart->ier);
270}
271
272static inline void neo_set_new_start_stop_chars(struct jsm_channel *ch)
273{
274
275 /* if hardware flow control is set, then skip this whole thing */
276 if (ch->ch_c_cflag & CRTSCTS)
277 return;
278
279 jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "start\n");
280
281 /* Tell UART what start/stop chars it should be looking for */
282 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
283 writeb(0, &ch->ch_neo_uart->xonchar2);
284
285 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
286 writeb(0, &ch->ch_neo_uart->xoffchar2);
287}
288
289static void neo_copy_data_from_uart_to_queue(struct jsm_channel *ch)
290{
291 int qleft = 0;
292 u8 linestatus = 0;
293 u8 error_mask = 0;
294 int n = 0;
295 int total = 0;
296 u16 head;
297 u16 tail;
298
299 if (!ch)
300 return;
301
302 /* cache head and tail of queue */
303 head = ch->ch_r_head & RQUEUEMASK;
304 tail = ch->ch_r_tail & RQUEUEMASK;
305
306 /* Get our cached LSR */
307 linestatus = ch->ch_cached_lsr;
308 ch->ch_cached_lsr = 0;
309
310 /* Store how much space we have left in the queue */
311 if ((qleft = tail - head - 1) < 0)
312 qleft += RQUEUEMASK + 1;
313
314 /*
315 * If the UART is not in FIFO mode, force the FIFO copy to
316 * NOT be run, by setting total to 0.
317 *
318 * On the other hand, if the UART IS in FIFO mode, then ask
319 * the UART to give us an approximation of data it has RX'ed.
320 */
321 if (!(ch->ch_flags & CH_FIFO_ENABLED))
322 total = 0;
323 else {
324 total = readb(&ch->ch_neo_uart->rfifo);
325
326 /*
327 * EXAR chip bug - RX FIFO COUNT - Fudge factor.
328 *
329 * This resolves a problem/bug with the Exar chip that sometimes
330 * returns a bogus value in the rfifo register.
331 * The count can be any where from 0-3 bytes "off".
332 * Bizarre, but true.
333 */
334 total -= 3;
335 }
336
337 /*
338 * Finally, bound the copy to make sure we don't overflow
339 * our own queue...
340 * The byte by byte copy loop below this loop this will
341 * deal with the queue overflow possibility.
342 */
343 total = min(total, qleft);
344
345 while (total > 0) {
346 /*
347 * Grab the linestatus register, we need to check
348 * to see if there are any errors in the FIFO.
349 */
350 linestatus = readb(&ch->ch_neo_uart->lsr);
351
352 /*
353 * Break out if there is a FIFO error somewhere.
354 * This will allow us to go byte by byte down below,
355 * finding the exact location of the error.
356 */
357 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
358 break;
359
360 /* Make sure we don't go over the end of our queue */
361 n = min(((u32) total), (RQUEUESIZE - (u32) head));
362
363 /*
364 * Cut down n even further if needed, this is to fix
365 * a problem with memcpy_fromio() with the Neo on the
366 * IBM pSeries platform.
367 * 15 bytes max appears to be the magic number.
368 */
369 n = min((u32) n, (u32) 12);
370
371 /*
372 * Since we are grabbing the linestatus register, which
373 * will reset some bits after our read, we need to ensure
374 * we don't miss our TX FIFO emptys.
375 */
376 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR))
377 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
378
379 linestatus = 0;
380
381 /* Copy data from uart to the queue */
382 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, n);
383 /*
384 * Since RX_FIFO_DATA_ERROR was 0, we are guarenteed
385 * that all the data currently in the FIFO is free of
386 * breaks and parity/frame/orun errors.
387 */
388 memset(ch->ch_equeue + head, 0, n);
389
390 /* Add to and flip head if needed */
391 head = (head + n) & RQUEUEMASK;
392 total -= n;
393 qleft -= n;
394 ch->ch_rxcount += n;
395 }
396
397 /*
398 * Create a mask to determine whether we should
399 * insert the character (if any) into our queue.
400 */
401 if (ch->ch_c_iflag & IGNBRK)
402 error_mask |= UART_LSR_BI;
403
404 /*
405 * Now cleanup any leftover bytes still in the UART.
406 * Also deal with any possible queue overflow here as well.
407 */
408 while (1) {
409
410 /*
411 * Its possible we have a linestatus from the loop above
412 * this, so we "OR" on any extra bits.
413 */
414 linestatus |= readb(&ch->ch_neo_uart->lsr);
415
416 /*
417 * If the chip tells us there is no more data pending to
418 * be read, we can then leave.
419 * But before we do, cache the linestatus, just in case.
420 */
421 if (!(linestatus & UART_LSR_DR)) {
422 ch->ch_cached_lsr = linestatus;
423 break;
424 }
425
426 /* No need to store this bit */
427 linestatus &= ~UART_LSR_DR;
428
429 /*
430 * Since we are grabbing the linestatus register, which
431 * will reset some bits after our read, we need to ensure
432 * we don't miss our TX FIFO emptys.
433 */
434 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) {
435 linestatus &= ~(UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR);
436 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
437 }
438
439 /*
440 * Discard character if we are ignoring the error mask.
441 */
442 if (linestatus & error_mask) {
443 u8 discard;
444 linestatus = 0;
445 memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1);
446 continue;
447 }
448
449 /*
450 * If our queue is full, we have no choice but to drop some data.
451 * The assumption is that HWFLOW or SWFLOW should have stopped
452 * things way way before we got to this point.
453 *
454 * I decided that I wanted to ditch the oldest data first,
455 * I hope thats okay with everyone? Yes? Good.
456 */
457 while (qleft < 1) {
458 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev,
459 "Queue full, dropping DATA:%x LSR:%x\n",
460 ch->ch_rqueue[tail], ch->ch_equeue[tail]);
461
462 ch->ch_r_tail = tail = (tail + 1) & RQUEUEMASK;
463 ch->ch_err_overrun++;
464 qleft++;
465 }
466
467 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, 1);
468 ch->ch_equeue[head] = (u8) linestatus;
469
470 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev,
471 "DATA/LSR pair: %x %x\n", ch->ch_rqueue[head], ch->ch_equeue[head]);
472
473 /* Ditch any remaining linestatus value. */
474 linestatus = 0;
475
476 /* Add to and flip head if needed */
477 head = (head + 1) & RQUEUEMASK;
478
479 qleft--;
480 ch->ch_rxcount++;
481 }
482
483 /*
484 * Write new final heads to channel structure.
485 */
486 ch->ch_r_head = head & RQUEUEMASK;
487 ch->ch_e_head = head & EQUEUEMASK;
488 jsm_input(ch);
489}
490
491static void neo_copy_data_from_queue_to_uart(struct jsm_channel *ch)
492{
493 u16 head;
494 u16 tail;
495 int n;
496 int s;
497 int qlen;
498 u32 len_written = 0;
499
500 if (!ch)
501 return;
502
503 /* No data to write to the UART */
504 if (ch->ch_w_tail == ch->ch_w_head)
505 return;
506
507 /* If port is "stopped", don't send any data to the UART */
508 if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING))
509 return;
510 /*
511 * If FIFOs are disabled. Send data directly to txrx register
512 */
513 if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
514 u8 lsrbits = readb(&ch->ch_neo_uart->lsr);
515
516 ch->ch_cached_lsr |= lsrbits;
517 if (ch->ch_cached_lsr & UART_LSR_THRE) {
518 ch->ch_cached_lsr &= ~(UART_LSR_THRE);
519
520 writeb(ch->ch_wqueue[ch->ch_w_tail], &ch->ch_neo_uart->txrx);
521 jsm_printk(WRITE, INFO, &ch->ch_bd->pci_dev,
522 "Tx data: %x\n", ch->ch_wqueue[ch->ch_w_head]);
523 ch->ch_w_tail++;
524 ch->ch_w_tail &= WQUEUEMASK;
525 ch->ch_txcount++;
526 }
527 return;
528 }
529
530 /*
531 * We have to do it this way, because of the EXAR TXFIFO count bug.
532 */
533 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
534 return;
535
536 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel;
537
538 /* cache head and tail of queue */
539 head = ch->ch_w_head & WQUEUEMASK;
540 tail = ch->ch_w_tail & WQUEUEMASK;
541 qlen = (head - tail) & WQUEUEMASK;
542
543 /* Find minimum of the FIFO space, versus queue length */
544 n = min(n, qlen);
545
546 while (n > 0) {
547
548 s = ((head >= tail) ? head : WQUEUESIZE) - tail;
549 s = min(s, n);
550
551 if (s <= 0)
552 break;
553
554 memcpy_toio(&ch->ch_neo_uart->txrxburst, ch->ch_wqueue + tail, s);
555 /* Add and flip queue if needed */
556 tail = (tail + s) & WQUEUEMASK;
557 n -= s;
558 ch->ch_txcount += s;
559 len_written += s;
560 }
561
562 /* Update the final tail */
563 ch->ch_w_tail = tail & WQUEUEMASK;
564
565 if (len_written >= ch->ch_t_tlevel)
566 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
567
568 if (!jsm_tty_write(&ch->uart_port))
569 uart_write_wakeup(&ch->uart_port);
570}
571
572static void neo_parse_modem(struct jsm_channel *ch, u8 signals)
573{
574 u8 msignals = signals;
575
576 jsm_printk(MSIGS, INFO, &ch->ch_bd->pci_dev,
577 "neo_parse_modem: port: %d msignals: %x\n", ch->ch_portnum, msignals);
578
579 /* Scrub off lower bits. They signify delta's, which I don't care about */
580 /* Keep DDCD and DDSR though */
581 msignals &= 0xf8;
582
583 if (msignals & UART_MSR_DDCD)
584 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_DCD);
585 if (msignals & UART_MSR_DDSR)
586 uart_handle_cts_change(&ch->uart_port, msignals & UART_MSR_CTS);
587 if (msignals & UART_MSR_DCD)
588 ch->ch_mistat |= UART_MSR_DCD;
589 else
590 ch->ch_mistat &= ~UART_MSR_DCD;
591
592 if (msignals & UART_MSR_DSR)
593 ch->ch_mistat |= UART_MSR_DSR;
594 else
595 ch->ch_mistat &= ~UART_MSR_DSR;
596
597 if (msignals & UART_MSR_RI)
598 ch->ch_mistat |= UART_MSR_RI;
599 else
600 ch->ch_mistat &= ~UART_MSR_RI;
601
602 if (msignals & UART_MSR_CTS)
603 ch->ch_mistat |= UART_MSR_CTS;
604 else
605 ch->ch_mistat &= ~UART_MSR_CTS;
606
607 jsm_printk(MSIGS, INFO, &ch->ch_bd->pci_dev,
608 "Port: %d DTR: %d RTS: %d CTS: %d DSR: %d " "RI: %d CD: %d\n",
609 ch->ch_portnum,
610 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR),
611 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS),
612 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS),
613 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR),
614 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI),
615 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD));
616}
617
618/* Make the UART raise any of the output signals we want up */
619static void neo_assert_modem_signals(struct jsm_channel *ch)
620{
621 if (!ch)
622 return;
623
624 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
625
626 /* flush write operation */
627 neo_pci_posting_flush(ch->ch_bd);
628}
629
630/*
631 * Flush the WRITE FIFO on the Neo.
632 *
633 * NOTE: Channel lock MUST be held before calling this function!
634 */
635static void neo_flush_uart_write(struct jsm_channel *ch)
636{
637 u8 tmp = 0;
638 int i = 0;
639
640 if (!ch)
641 return;
642
643 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
644
645 for (i = 0; i < 10; i++) {
646
647 /* Check to see if the UART feels it completely flushed the FIFO. */
648 tmp = readb(&ch->ch_neo_uart->isr_fcr);
649 if (tmp & 4) {
650 jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev,
651 "Still flushing TX UART... i: %d\n", i);
652 udelay(10);
653 }
654 else
655 break;
656 }
657
658 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
659}
660
661
662/*
663 * Flush the READ FIFO on the Neo.
664 *
665 * NOTE: Channel lock MUST be held before calling this function!
666 */
667static void neo_flush_uart_read(struct jsm_channel *ch)
668{
669 u8 tmp = 0;
670 int i = 0;
671
672 if (!ch)
673 return;
674
675 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_neo_uart->isr_fcr);
676
677 for (i = 0; i < 10; i++) {
678
679 /* Check to see if the UART feels it completely flushed the FIFO. */
680 tmp = readb(&ch->ch_neo_uart->isr_fcr);
681 if (tmp & 2) {
682 jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev,
683 "Still flushing RX UART... i: %d\n", i);
684 udelay(10);
685 }
686 else
687 break;
688 }
689}
690
691/*
692 * No locks are assumed to be held when calling this function.
693 */
694static void neo_clear_break(struct jsm_channel *ch, int force)
695{
696 unsigned long lock_flags;
697
698 spin_lock_irqsave(&ch->ch_lock, lock_flags);
699
700 /* Turn break off, and unset some variables */
701 if (ch->ch_flags & CH_BREAK_SENDING) {
702 u8 temp = readb(&ch->ch_neo_uart->lcr);
703 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
704
705 ch->ch_flags &= ~(CH_BREAK_SENDING);
706 jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev,
707 "clear break Finishing UART_LCR_SBC! finished: %lx\n", jiffies);
708
709 /* flush write operation */
710 neo_pci_posting_flush(ch->ch_bd);
711 }
712 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
713}
714
715/*
716 * Parse the ISR register.
717 */
718static inline void neo_parse_isr(struct jsm_board *brd, u32 port)
719{
720 struct jsm_channel *ch;
721 u8 isr;
722 u8 cause;
723 unsigned long lock_flags;
724
725 if (!brd)
726 return;
727
728 if (port > brd->maxports)
729 return;
730
731 ch = brd->channels[port];
732 if (!ch)
733 return;
734
735 /* Here we try to figure out what caused the interrupt to happen */
736 while (1) {
737
738 isr = readb(&ch->ch_neo_uart->isr_fcr);
739
740 /* Bail if no pending interrupt */
741 if (isr & UART_IIR_NO_INT)
742 break;
743
744 /*
745 * Yank off the upper 2 bits, which just show that the FIFO's are enabled.
746 */
747 isr &= ~(UART_17158_IIR_FIFO_ENABLED);
748
749 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
750 "%s:%d isr: %x\n", __FILE__, __LINE__, isr);
751
752 if (isr & (UART_17158_IIR_RDI_TIMEOUT | UART_IIR_RDI)) {
753 /* Read data from uart -> queue */
754 neo_copy_data_from_uart_to_queue(ch);
755
756 /* Call our tty layer to enforce queue flow control if needed. */
757 spin_lock_irqsave(&ch->ch_lock, lock_flags);
758 jsm_check_queue_flow_control(ch);
759 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
760 }
761
762 if (isr & UART_IIR_THRI) {
763 /* Transfer data (if any) from Write Queue -> UART. */
764 spin_lock_irqsave(&ch->ch_lock, lock_flags);
765 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
766 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
767 neo_copy_data_from_queue_to_uart(ch);
768 }
769
770 if (isr & UART_17158_IIR_XONXOFF) {
771 cause = readb(&ch->ch_neo_uart->xoffchar1);
772
773 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
774 "Port %d. Got ISR_XONXOFF: cause:%x\n", port, cause);
775
776 /*
777 * Since the UART detected either an XON or
778 * XOFF match, we need to figure out which
779 * one it was, so we can suspend or resume data flow.
780 */
781 spin_lock_irqsave(&ch->ch_lock, lock_flags);
782 if (cause == UART_17158_XON_DETECT) {
783 /* Is output stopped right now, if so, resume it */
784 if (brd->channels[port]->ch_flags & CH_STOP) {
785 ch->ch_flags &= ~(CH_STOP);
786 }
787 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
788 "Port %d. XON detected in incoming data\n", port);
789 }
790 else if (cause == UART_17158_XOFF_DETECT) {
791 if (!(brd->channels[port]->ch_flags & CH_STOP)) {
792 ch->ch_flags |= CH_STOP;
793 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
794 "Setting CH_STOP\n");
795 }
796 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
797 "Port: %d. XOFF detected in incoming data\n", port);
798 }
799 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
800 }
801
802 if (isr & UART_17158_IIR_HWFLOW_STATE_CHANGE) {
803 /*
804 * If we get here, this means the hardware is doing auto flow control.
805 * Check to see whether RTS/DTR or CTS/DSR caused this interrupt.
806 */
807 cause = readb(&ch->ch_neo_uart->mcr);
808
809 /* Which pin is doing auto flow? RTS or DTR? */
810 spin_lock_irqsave(&ch->ch_lock, lock_flags);
811 if ((cause & 0x4) == 0) {
812 if (cause & UART_MCR_RTS)
813 ch->ch_mostat |= UART_MCR_RTS;
814 else
815 ch->ch_mostat &= ~(UART_MCR_RTS);
816 } else {
817 if (cause & UART_MCR_DTR)
818 ch->ch_mostat |= UART_MCR_DTR;
819 else
820 ch->ch_mostat &= ~(UART_MCR_DTR);
821 }
822 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
823 }
824
825 /* Parse any modem signal changes */
826 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
827 "MOD_STAT: sending to parse_modem_sigs\n");
828 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
829 }
830}
831
832static inline void neo_parse_lsr(struct jsm_board *brd, u32 port)
833{
834 struct jsm_channel *ch;
835 int linestatus;
836 unsigned long lock_flags;
837
838 if (!brd)
839 return;
840
841 if (port > brd->maxports)
842 return;
843
844 ch = brd->channels[port];
845 if (!ch)
846 return;
847
848 linestatus = readb(&ch->ch_neo_uart->lsr);
849
850 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
851 "%s:%d port: %d linestatus: %x\n", __FILE__, __LINE__, port, linestatus);
852
853 ch->ch_cached_lsr |= linestatus;
854
855 if (ch->ch_cached_lsr & UART_LSR_DR) {
856 /* Read data from uart -> queue */
857 neo_copy_data_from_uart_to_queue(ch);
858 spin_lock_irqsave(&ch->ch_lock, lock_flags);
859 jsm_check_queue_flow_control(ch);
860 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
861 }
862
863 /*
864 * This is a special flag. It indicates that at least 1
865 * RX error (parity, framing, or break) has happened.
866 * Mark this in our struct, which will tell me that I have
867 *to do the special RX+LSR read for this FIFO load.
868 */
869 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
870 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev,
871 "%s:%d Port: %d Got an RX error, need to parse LSR\n",
872 __FILE__, __LINE__, port);
873
874 /*
875 * The next 3 tests should *NOT* happen, as the above test
876 * should encapsulate all 3... At least, thats what Exar says.
877 */
878
879 if (linestatus & UART_LSR_PE) {
880 ch->ch_err_parity++;
881 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev,
882 "%s:%d Port: %d. PAR ERR!\n", __FILE__, __LINE__, port);
883 }
884
885 if (linestatus & UART_LSR_FE) {
886 ch->ch_err_frame++;
887 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev,
888 "%s:%d Port: %d. FRM ERR!\n", __FILE__, __LINE__, port);
889 }
890
891 if (linestatus & UART_LSR_BI) {
892 ch->ch_err_break++;
893 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev,
894 "%s:%d Port: %d. BRK INTR!\n", __FILE__, __LINE__, port);
895 }
896
897 if (linestatus & UART_LSR_OE) {
898 /*
899 * Rx Oruns. Exar says that an orun will NOT corrupt
900 * the FIFO. It will just replace the holding register
901 * with this new data byte. So basically just ignore this.
902 * Probably we should eventually have an orun stat in our driver...
903 */
904 ch->ch_err_overrun++;
905 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev,
906 "%s:%d Port: %d. Rx Overrun!\n", __FILE__, __LINE__, port);
907 }
908
909 if (linestatus & UART_LSR_THRE) {
910 spin_lock_irqsave(&ch->ch_lock, lock_flags);
911 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
912 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
913
914 /* Transfer data (if any) from Write Queue -> UART. */
915 neo_copy_data_from_queue_to_uart(ch);
916 }
917 else if (linestatus & UART_17158_TX_AND_FIFO_CLR) {
918 spin_lock_irqsave(&ch->ch_lock, lock_flags);
919 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
920 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
921
922 /* Transfer data (if any) from Write Queue -> UART. */
923 neo_copy_data_from_queue_to_uart(ch);
924 }
925}
926
927/*
928 * neo_param()
929 * Send any/all changes to the line to the UART.
930 */
931static void neo_param(struct jsm_channel *ch)
932{
933 u8 lcr = 0;
934 u8 uart_lcr, ier;
935 u32 baud;
936 int quot;
937 struct jsm_board *bd;
938
939 bd = ch->ch_bd;
940 if (!bd)
941 return;
942
943 /*
944 * If baud rate is zero, flush queues, and set mval to drop DTR.
945 */
946 if ((ch->ch_c_cflag & (CBAUD)) == 0) {
947 ch->ch_r_head = ch->ch_r_tail = 0;
948 ch->ch_e_head = ch->ch_e_tail = 0;
949 ch->ch_w_head = ch->ch_w_tail = 0;
950
951 neo_flush_uart_write(ch);
952 neo_flush_uart_read(ch);
953
954 ch->ch_flags |= (CH_BAUD0);
955 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
956 neo_assert_modem_signals(ch);
957 return;
958
959 } else {
960 int i;
961 unsigned int cflag;
962 static struct {
963 unsigned int rate;
964 unsigned int cflag;
965 } baud_rates[] = {
966 { 921600, B921600 },
967 { 460800, B460800 },
968 { 230400, B230400 },
969 { 115200, B115200 },
970 { 57600, B57600 },
971 { 38400, B38400 },
972 { 19200, B19200 },
973 { 9600, B9600 },
974 { 4800, B4800 },
975 { 2400, B2400 },
976 { 1200, B1200 },
977 { 600, B600 },
978 { 300, B300 },
979 { 200, B200 },
980 { 150, B150 },
981 { 134, B134 },
982 { 110, B110 },
983 { 75, B75 },
984 { 50, B50 },
985 };
986
987 cflag = C_BAUD(ch->uart_port.state->port.tty);
988 baud = 9600;
989 for (i = 0; i < ARRAY_SIZE(baud_rates); i++) {
990 if (baud_rates[i].cflag == cflag) {
991 baud = baud_rates[i].rate;
992 break;
993 }
994 }
995
996 if (ch->ch_flags & CH_BAUD0)
997 ch->ch_flags &= ~(CH_BAUD0);
998 }
999
1000 if (ch->ch_c_cflag & PARENB)
1001 lcr |= UART_LCR_PARITY;
1002
1003 if (!(ch->ch_c_cflag & PARODD))
1004 lcr |= UART_LCR_EPAR;
1005
1006 /*
1007 * Not all platforms support mark/space parity,
1008 * so this will hide behind an ifdef.
1009 */
1010#ifdef CMSPAR
1011 if (ch->ch_c_cflag & CMSPAR)
1012 lcr |= UART_LCR_SPAR;
1013#endif
1014
1015 if (ch->ch_c_cflag & CSTOPB)
1016 lcr |= UART_LCR_STOP;
1017
1018 switch (ch->ch_c_cflag & CSIZE) {
1019 case CS5:
1020 lcr |= UART_LCR_WLEN5;
1021 break;
1022 case CS6:
1023 lcr |= UART_LCR_WLEN6;
1024 break;
1025 case CS7:
1026 lcr |= UART_LCR_WLEN7;
1027 break;
1028 case CS8:
1029 default:
1030 lcr |= UART_LCR_WLEN8;
1031 break;
1032 }
1033
1034 ier = readb(&ch->ch_neo_uart->ier);
1035 uart_lcr = readb(&ch->ch_neo_uart->lcr);
1036
1037 if (baud == 0)
1038 baud = 9600;
1039
1040 quot = ch->ch_bd->bd_dividend / baud;
1041
1042 if (quot != 0) {
1043 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr);
1044 writeb((quot & 0xff), &ch->ch_neo_uart->txrx);
1045 writeb((quot >> 8), &ch->ch_neo_uart->ier);
1046 writeb(lcr, &ch->ch_neo_uart->lcr);
1047 }
1048
1049 if (uart_lcr != lcr)
1050 writeb(lcr, &ch->ch_neo_uart->lcr);
1051
1052 if (ch->ch_c_cflag & CREAD)
1053 ier |= (UART_IER_RDI | UART_IER_RLSI);
1054
1055 ier |= (UART_IER_THRI | UART_IER_MSI);
1056
1057 writeb(ier, &ch->ch_neo_uart->ier);
1058
1059 /* Set new start/stop chars */
1060 neo_set_new_start_stop_chars(ch);
1061
1062 if (ch->ch_c_cflag & CRTSCTS)
1063 neo_set_cts_flow_control(ch);
1064 else if (ch->ch_c_iflag & IXON) {
1065 /* If start/stop is set to disable, then we should disable flow control */
1066 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR))
1067 neo_set_no_output_flow_control(ch);
1068 else
1069 neo_set_ixon_flow_control(ch);
1070 }
1071 else
1072 neo_set_no_output_flow_control(ch);
1073
1074 if (ch->ch_c_cflag & CRTSCTS)
1075 neo_set_rts_flow_control(ch);
1076 else if (ch->ch_c_iflag & IXOFF) {
1077 /* If start/stop is set to disable, then we should disable flow control */
1078 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR))
1079 neo_set_no_input_flow_control(ch);
1080 else
1081 neo_set_ixoff_flow_control(ch);
1082 }
1083 else
1084 neo_set_no_input_flow_control(ch);
1085 /*
1086 * Adjust the RX FIFO Trigger level if baud is less than 9600.
1087 * Not exactly elegant, but this is needed because of the Exar chip's
1088 * delay on firing off the RX FIFO interrupt on slower baud rates.
1089 */
1090 if (baud < 9600) {
1091 writeb(1, &ch->ch_neo_uart->rfifo);
1092 ch->ch_r_tlevel = 1;
1093 }
1094
1095 neo_assert_modem_signals(ch);
1096
1097 /* Get current status of the modem signals now */
1098 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
1099 return;
1100}
1101
1102/*
1103 * jsm_neo_intr()
1104 *
1105 * Neo specific interrupt handler.
1106 */
1107static irqreturn_t neo_intr(int irq, void *voidbrd)
1108{
1109 struct jsm_board *brd = voidbrd;
1110 struct jsm_channel *ch;
1111 int port = 0;
1112 int type = 0;
1113 int current_port;
1114 u32 tmp;
1115 u32 uart_poll;
1116 unsigned long lock_flags;
1117 unsigned long lock_flags2;
1118 int outofloop_count = 0;
1119
1120 /* Lock out the slow poller from running on this board. */
1121 spin_lock_irqsave(&brd->bd_intr_lock, lock_flags);
1122
1123 /*
1124 * Read in "extended" IRQ information from the 32bit Neo register.
1125 * Bits 0-7: What port triggered the interrupt.
1126 * Bits 8-31: Each 3bits indicate what type of interrupt occurred.
1127 */
1128 uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET);
1129
1130 jsm_printk(INTR, INFO, &brd->pci_dev,
1131 "%s:%d uart_poll: %x\n", __FILE__, __LINE__, uart_poll);
1132
1133 if (!uart_poll) {
1134 jsm_printk(INTR, INFO, &brd->pci_dev,
1135 "Kernel interrupted to me, but no pending interrupts...\n");
1136 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags);
1137 return IRQ_NONE;
1138 }
1139
1140 /* At this point, we have at least SOMETHING to service, dig further... */
1141
1142 current_port = 0;
1143
1144 /* Loop on each port */
1145 while (((uart_poll & 0xff) != 0) && (outofloop_count < 0xff)){
1146
1147 tmp = uart_poll;
1148 outofloop_count++;
1149
1150 /* Check current port to see if it has interrupt pending */
1151 if ((tmp & jsm_offset_table[current_port]) != 0) {
1152 port = current_port;
1153 type = tmp >> (8 + (port * 3));
1154 type &= 0x7;
1155 } else {
1156 current_port++;
1157 continue;
1158 }
1159
1160 jsm_printk(INTR, INFO, &brd->pci_dev,
1161 "%s:%d port: %x type: %x\n", __FILE__, __LINE__, port, type);
1162
1163 /* Remove this port + type from uart_poll */
1164 uart_poll &= ~(jsm_offset_table[port]);
1165
1166 if (!type) {
1167 /* If no type, just ignore it, and move onto next port */
1168 jsm_printk(INTR, ERR, &brd->pci_dev,
1169 "Interrupt with no type! port: %d\n", port);
1170 continue;
1171 }
1172
1173 /* Switch on type of interrupt we have */
1174 switch (type) {
1175
1176 case UART_17158_RXRDY_TIMEOUT:
1177 /*
1178 * RXRDY Time-out is cleared by reading data in the
1179 * RX FIFO until it falls below the trigger level.
1180 */
1181
1182 /* Verify the port is in range. */
1183 if (port > brd->nasync)
1184 continue;
1185
1186 ch = brd->channels[port];
1187 neo_copy_data_from_uart_to_queue(ch);
1188
1189 /* Call our tty layer to enforce queue flow control if needed. */
1190 spin_lock_irqsave(&ch->ch_lock, lock_flags2);
1191 jsm_check_queue_flow_control(ch);
1192 spin_unlock_irqrestore(&ch->ch_lock, lock_flags2);
1193
1194 continue;
1195
1196 case UART_17158_RX_LINE_STATUS:
1197 /*
1198 * RXRDY and RX LINE Status (logic OR of LSR[4:1])
1199 */
1200 neo_parse_lsr(brd, port);
1201 continue;
1202
1203 case UART_17158_TXRDY:
1204 /*
1205 * TXRDY interrupt clears after reading ISR register for the UART channel.
1206 */
1207
1208 /*
1209 * Yes, this is odd...
1210 * Why would I check EVERY possibility of type of
1211 * interrupt, when we know its TXRDY???
1212 * Becuz for some reason, even tho we got triggered for TXRDY,
1213 * it seems to be occassionally wrong. Instead of TX, which
1214 * it should be, I was getting things like RXDY too. Weird.
1215 */
1216 neo_parse_isr(brd, port);
1217 continue;
1218
1219 case UART_17158_MSR:
1220 /*
1221 * MSR or flow control was seen.
1222 */
1223 neo_parse_isr(brd, port);
1224 continue;
1225
1226 default:
1227 /*
1228 * The UART triggered us with a bogus interrupt type.
1229 * It appears the Exar chip, when REALLY bogged down, will throw
1230 * these once and awhile.
1231 * Its harmless, just ignore it and move on.
1232 */
1233 jsm_printk(INTR, ERR, &brd->pci_dev,
1234 "%s:%d Unknown Interrupt type: %x\n", __FILE__, __LINE__, type);
1235 continue;
1236 }
1237 }
1238
1239 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags);
1240
1241 jsm_printk(INTR, INFO, &brd->pci_dev, "finish.\n");
1242 return IRQ_HANDLED;
1243}
1244
1245/*
1246 * Neo specific way of turning off the receiver.
1247 * Used as a way to enforce queue flow control when in
1248 * hardware flow control mode.
1249 */
1250static void neo_disable_receiver(struct jsm_channel *ch)
1251{
1252 u8 tmp = readb(&ch->ch_neo_uart->ier);
1253 tmp &= ~(UART_IER_RDI);
1254 writeb(tmp, &ch->ch_neo_uart->ier);
1255
1256 /* flush write operation */
1257 neo_pci_posting_flush(ch->ch_bd);
1258}
1259
1260
1261/*
1262 * Neo specific way of turning on the receiver.
1263 * Used as a way to un-enforce queue flow control when in
1264 * hardware flow control mode.
1265 */
1266static void neo_enable_receiver(struct jsm_channel *ch)
1267{
1268 u8 tmp = readb(&ch->ch_neo_uart->ier);
1269 tmp |= (UART_IER_RDI);
1270 writeb(tmp, &ch->ch_neo_uart->ier);
1271
1272 /* flush write operation */
1273 neo_pci_posting_flush(ch->ch_bd);
1274}
1275
1276static void neo_send_start_character(struct jsm_channel *ch)
1277{
1278 if (!ch)
1279 return;
1280
1281 if (ch->ch_startc != __DISABLED_CHAR) {
1282 ch->ch_xon_sends++;
1283 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx);
1284
1285 /* flush write operation */
1286 neo_pci_posting_flush(ch->ch_bd);
1287 }
1288}
1289
1290static void neo_send_stop_character(struct jsm_channel *ch)
1291{
1292 if (!ch)
1293 return;
1294
1295 if (ch->ch_stopc != __DISABLED_CHAR) {
1296 ch->ch_xoff_sends++;
1297 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx);
1298
1299 /* flush write operation */
1300 neo_pci_posting_flush(ch->ch_bd);
1301 }
1302}
1303
1304/*
1305 * neo_uart_init
1306 */
1307static void neo_uart_init(struct jsm_channel *ch)
1308{
1309 writeb(0, &ch->ch_neo_uart->ier);
1310 writeb(0, &ch->ch_neo_uart->efr);
1311 writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr);
1312
1313 /* Clear out UART and FIFO */
1314 readb(&ch->ch_neo_uart->txrx);
1315 writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
1316 readb(&ch->ch_neo_uart->lsr);
1317 readb(&ch->ch_neo_uart->msr);
1318
1319 ch->ch_flags |= CH_FIFO_ENABLED;
1320
1321 /* Assert any signals we want up */
1322 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
1323}
1324
1325/*
1326 * Make the UART completely turn off.
1327 */
1328static void neo_uart_off(struct jsm_channel *ch)
1329{
1330 /* Turn off UART enhanced bits */
1331 writeb(0, &ch->ch_neo_uart->efr);
1332
1333 /* Stop all interrupts from occurring. */
1334 writeb(0, &ch->ch_neo_uart->ier);
1335}
1336
1337static u32 neo_get_uart_bytes_left(struct jsm_channel *ch)
1338{
1339 u8 left = 0;
1340 u8 lsr = readb(&ch->ch_neo_uart->lsr);
1341
1342 /* We must cache the LSR as some of the bits get reset once read... */
1343 ch->ch_cached_lsr |= lsr;
1344
1345 /* Determine whether the Transmitter is empty or not */
1346 if (!(lsr & UART_LSR_TEMT))
1347 left = 1;
1348 else {
1349 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1350 left = 0;
1351 }
1352
1353 return left;
1354}
1355
1356/* Channel lock MUST be held by the calling function! */
1357static void neo_send_break(struct jsm_channel *ch)
1358{
1359 /*
1360 * Set the time we should stop sending the break.
1361 * If we are already sending a break, toss away the existing
1362 * time to stop, and use this new value instead.
1363 */
1364
1365 /* Tell the UART to start sending the break */
1366 if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1367 u8 temp = readb(&ch->ch_neo_uart->lcr);
1368 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1369 ch->ch_flags |= (CH_BREAK_SENDING);
1370
1371 /* flush write operation */
1372 neo_pci_posting_flush(ch->ch_bd);
1373 }
1374}
1375
1376/*
1377 * neo_send_immediate_char.
1378 *
1379 * Sends a specific character as soon as possible to the UART,
1380 * jumping over any bytes that might be in the write queue.
1381 *
1382 * The channel lock MUST be held by the calling function.
1383 */
1384static void neo_send_immediate_char(struct jsm_channel *ch, unsigned char c)
1385{
1386 if (!ch)
1387 return;
1388
1389 writeb(c, &ch->ch_neo_uart->txrx);
1390
1391 /* flush write operation */
1392 neo_pci_posting_flush(ch->ch_bd);
1393}
1394
1395struct board_ops jsm_neo_ops = {
1396 .intr = neo_intr,
1397 .uart_init = neo_uart_init,
1398 .uart_off = neo_uart_off,
1399 .param = neo_param,
1400 .assert_modem_signals = neo_assert_modem_signals,
1401 .flush_uart_write = neo_flush_uart_write,
1402 .flush_uart_read = neo_flush_uart_read,
1403 .disable_receiver = neo_disable_receiver,
1404 .enable_receiver = neo_enable_receiver,
1405 .send_break = neo_send_break,
1406 .clear_break = neo_clear_break,
1407 .send_start_character = neo_send_start_character,
1408 .send_stop_character = neo_send_stop_character,
1409 .copy_data_from_queue_to_uart = neo_copy_data_from_queue_to_uart,
1410 .get_uart_bytes_left = neo_get_uart_bytes_left,
1411 .send_immediate_char = neo_send_immediate_char
1412};
diff --git a/drivers/serial/jsm/jsm_tty.c b/drivers/serial/jsm/jsm_tty.c
deleted file mode 100644
index 7a4a914ecff0..000000000000
--- a/drivers/serial/jsm/jsm_tty.c
+++ /dev/null
@@ -1,910 +0,0 @@
1/************************************************************************
2 * Copyright 2003 Digi International (www.digi.com)
3 *
4 * Copyright (C) 2004 IBM Corporation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2, or (at your option)
9 * any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
13 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
14 * PURPOSE. See the GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 * Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
20 *
21 * Contact Information:
22 * Scott H Kilau <Scott_Kilau@digi.com>
23 * Ananda Venkatarman <mansarov@us.ibm.com>
24 * Modifications:
25 * 01/19/06: changed jsm_input routine to use the dynamically allocated
26 * tty_buffer changes. Contributors: Scott Kilau and Ananda V.
27 ***********************************************************************/
28#include <linux/tty.h>
29#include <linux/tty_flip.h>
30#include <linux/serial_reg.h>
31#include <linux/delay.h> /* For udelay */
32#include <linux/pci.h>
33#include <linux/slab.h>
34
35#include "jsm.h"
36
37static DECLARE_BITMAP(linemap, MAXLINES);
38
39static void jsm_carrier(struct jsm_channel *ch);
40
41static inline int jsm_get_mstat(struct jsm_channel *ch)
42{
43 unsigned char mstat;
44 unsigned result;
45
46 jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev, "start\n");
47
48 mstat = (ch->ch_mostat | ch->ch_mistat);
49
50 result = 0;
51
52 if (mstat & UART_MCR_DTR)
53 result |= TIOCM_DTR;
54 if (mstat & UART_MCR_RTS)
55 result |= TIOCM_RTS;
56 if (mstat & UART_MSR_CTS)
57 result |= TIOCM_CTS;
58 if (mstat & UART_MSR_DSR)
59 result |= TIOCM_DSR;
60 if (mstat & UART_MSR_RI)
61 result |= TIOCM_RI;
62 if (mstat & UART_MSR_DCD)
63 result |= TIOCM_CD;
64
65 jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev, "finish\n");
66 return result;
67}
68
69static unsigned int jsm_tty_tx_empty(struct uart_port *port)
70{
71 return TIOCSER_TEMT;
72}
73
74/*
75 * Return modem signals to ld.
76 */
77static unsigned int jsm_tty_get_mctrl(struct uart_port *port)
78{
79 int result;
80 struct jsm_channel *channel = (struct jsm_channel *)port;
81
82 jsm_printk(IOCTL, INFO, &channel->ch_bd->pci_dev, "start\n");
83
84 result = jsm_get_mstat(channel);
85
86 if (result < 0)
87 return -ENXIO;
88
89 jsm_printk(IOCTL, INFO, &channel->ch_bd->pci_dev, "finish\n");
90
91 return result;
92}
93
94/*
95 * jsm_set_modem_info()
96 *
97 * Set modem signals, called by ld.
98 */
99static void jsm_tty_set_mctrl(struct uart_port *port, unsigned int mctrl)
100{
101 struct jsm_channel *channel = (struct jsm_channel *)port;
102
103 jsm_printk(IOCTL, INFO, &channel->ch_bd->pci_dev, "start\n");
104
105 if (mctrl & TIOCM_RTS)
106 channel->ch_mostat |= UART_MCR_RTS;
107 else
108 channel->ch_mostat &= ~UART_MCR_RTS;
109
110 if (mctrl & TIOCM_DTR)
111 channel->ch_mostat |= UART_MCR_DTR;
112 else
113 channel->ch_mostat &= ~UART_MCR_DTR;
114
115 channel->ch_bd->bd_ops->assert_modem_signals(channel);
116
117 jsm_printk(IOCTL, INFO, &channel->ch_bd->pci_dev, "finish\n");
118 udelay(10);
119}
120
121static void jsm_tty_start_tx(struct uart_port *port)
122{
123 struct jsm_channel *channel = (struct jsm_channel *)port;
124
125 jsm_printk(IOCTL, INFO, &channel->ch_bd->pci_dev, "start\n");
126
127 channel->ch_flags &= ~(CH_STOP);
128 jsm_tty_write(port);
129
130 jsm_printk(IOCTL, INFO, &channel->ch_bd->pci_dev, "finish\n");
131}
132
133static void jsm_tty_stop_tx(struct uart_port *port)
134{
135 struct jsm_channel *channel = (struct jsm_channel *)port;
136
137 jsm_printk(IOCTL, INFO, &channel->ch_bd->pci_dev, "start\n");
138
139 channel->ch_flags |= (CH_STOP);
140
141 jsm_printk(IOCTL, INFO, &channel->ch_bd->pci_dev, "finish\n");
142}
143
144static void jsm_tty_send_xchar(struct uart_port *port, char ch)
145{
146 unsigned long lock_flags;
147 struct jsm_channel *channel = (struct jsm_channel *)port;
148 struct ktermios *termios;
149
150 spin_lock_irqsave(&port->lock, lock_flags);
151 termios = port->state->port.tty->termios;
152 if (ch == termios->c_cc[VSTART])
153 channel->ch_bd->bd_ops->send_start_character(channel);
154
155 if (ch == termios->c_cc[VSTOP])
156 channel->ch_bd->bd_ops->send_stop_character(channel);
157 spin_unlock_irqrestore(&port->lock, lock_flags);
158}
159
160static void jsm_tty_stop_rx(struct uart_port *port)
161{
162 struct jsm_channel *channel = (struct jsm_channel *)port;
163
164 channel->ch_bd->bd_ops->disable_receiver(channel);
165}
166
167static void jsm_tty_enable_ms(struct uart_port *port)
168{
169 /* Nothing needed */
170}
171
172static void jsm_tty_break(struct uart_port *port, int break_state)
173{
174 unsigned long lock_flags;
175 struct jsm_channel *channel = (struct jsm_channel *)port;
176
177 spin_lock_irqsave(&port->lock, lock_flags);
178 if (break_state == -1)
179 channel->ch_bd->bd_ops->send_break(channel);
180 else
181 channel->ch_bd->bd_ops->clear_break(channel, 0);
182
183 spin_unlock_irqrestore(&port->lock, lock_flags);
184}
185
186static int jsm_tty_open(struct uart_port *port)
187{
188 struct jsm_board *brd;
189 struct jsm_channel *channel = (struct jsm_channel *)port;
190 struct ktermios *termios;
191
192 /* Get board pointer from our array of majors we have allocated */
193 brd = channel->ch_bd;
194
195 /*
196 * Allocate channel buffers for read/write/error.
197 * Set flag, so we don't get trounced on.
198 */
199 channel->ch_flags |= (CH_OPENING);
200
201 /* Drop locks, as malloc with GFP_KERNEL can sleep */
202
203 if (!channel->ch_rqueue) {
204 channel->ch_rqueue = kzalloc(RQUEUESIZE, GFP_KERNEL);
205 if (!channel->ch_rqueue) {
206 jsm_printk(INIT, ERR, &channel->ch_bd->pci_dev,
207 "unable to allocate read queue buf");
208 return -ENOMEM;
209 }
210 }
211 if (!channel->ch_equeue) {
212 channel->ch_equeue = kzalloc(EQUEUESIZE, GFP_KERNEL);
213 if (!channel->ch_equeue) {
214 jsm_printk(INIT, ERR, &channel->ch_bd->pci_dev,
215 "unable to allocate error queue buf");
216 return -ENOMEM;
217 }
218 }
219 if (!channel->ch_wqueue) {
220 channel->ch_wqueue = kzalloc(WQUEUESIZE, GFP_KERNEL);
221 if (!channel->ch_wqueue) {
222 jsm_printk(INIT, ERR, &channel->ch_bd->pci_dev,
223 "unable to allocate write queue buf");
224 return -ENOMEM;
225 }
226 }
227
228 channel->ch_flags &= ~(CH_OPENING);
229 /*
230 * Initialize if neither terminal is open.
231 */
232 jsm_printk(OPEN, INFO, &channel->ch_bd->pci_dev,
233 "jsm_open: initializing channel in open...\n");
234
235 /*
236 * Flush input queues.
237 */
238 channel->ch_r_head = channel->ch_r_tail = 0;
239 channel->ch_e_head = channel->ch_e_tail = 0;
240 channel->ch_w_head = channel->ch_w_tail = 0;
241
242 brd->bd_ops->flush_uart_write(channel);
243 brd->bd_ops->flush_uart_read(channel);
244
245 channel->ch_flags = 0;
246 channel->ch_cached_lsr = 0;
247 channel->ch_stops_sent = 0;
248
249 termios = port->state->port.tty->termios;
250 channel->ch_c_cflag = termios->c_cflag;
251 channel->ch_c_iflag = termios->c_iflag;
252 channel->ch_c_oflag = termios->c_oflag;
253 channel->ch_c_lflag = termios->c_lflag;
254 channel->ch_startc = termios->c_cc[VSTART];
255 channel->ch_stopc = termios->c_cc[VSTOP];
256
257 /* Tell UART to init itself */
258 brd->bd_ops->uart_init(channel);
259
260 /*
261 * Run param in case we changed anything
262 */
263 brd->bd_ops->param(channel);
264
265 jsm_carrier(channel);
266
267 channel->ch_open_count++;
268
269 jsm_printk(OPEN, INFO, &channel->ch_bd->pci_dev, "finish\n");
270 return 0;
271}
272
273static void jsm_tty_close(struct uart_port *port)
274{
275 struct jsm_board *bd;
276 struct ktermios *ts;
277 struct jsm_channel *channel = (struct jsm_channel *)port;
278
279 jsm_printk(CLOSE, INFO, &channel->ch_bd->pci_dev, "start\n");
280
281 bd = channel->ch_bd;
282 ts = port->state->port.tty->termios;
283
284 channel->ch_flags &= ~(CH_STOPI);
285
286 channel->ch_open_count--;
287
288 /*
289 * If we have HUPCL set, lower DTR and RTS
290 */
291 if (channel->ch_c_cflag & HUPCL) {
292 jsm_printk(CLOSE, INFO, &channel->ch_bd->pci_dev,
293 "Close. HUPCL set, dropping DTR/RTS\n");
294
295 /* Drop RTS/DTR */
296 channel->ch_mostat &= ~(UART_MCR_DTR | UART_MCR_RTS);
297 bd->bd_ops->assert_modem_signals(channel);
298 }
299
300 /* Turn off UART interrupts for this port */
301 channel->ch_bd->bd_ops->uart_off(channel);
302
303 jsm_printk(CLOSE, INFO, &channel->ch_bd->pci_dev, "finish\n");
304}
305
306static void jsm_tty_set_termios(struct uart_port *port,
307 struct ktermios *termios,
308 struct ktermios *old_termios)
309{
310 unsigned long lock_flags;
311 struct jsm_channel *channel = (struct jsm_channel *)port;
312
313 spin_lock_irqsave(&port->lock, lock_flags);
314 channel->ch_c_cflag = termios->c_cflag;
315 channel->ch_c_iflag = termios->c_iflag;
316 channel->ch_c_oflag = termios->c_oflag;
317 channel->ch_c_lflag = termios->c_lflag;
318 channel->ch_startc = termios->c_cc[VSTART];
319 channel->ch_stopc = termios->c_cc[VSTOP];
320
321 channel->ch_bd->bd_ops->param(channel);
322 jsm_carrier(channel);
323 spin_unlock_irqrestore(&port->lock, lock_flags);
324}
325
326static const char *jsm_tty_type(struct uart_port *port)
327{
328 return "jsm";
329}
330
331static void jsm_tty_release_port(struct uart_port *port)
332{
333}
334
335static int jsm_tty_request_port(struct uart_port *port)
336{
337 return 0;
338}
339
340static void jsm_config_port(struct uart_port *port, int flags)
341{
342 port->type = PORT_JSM;
343}
344
345static struct uart_ops jsm_ops = {
346 .tx_empty = jsm_tty_tx_empty,
347 .set_mctrl = jsm_tty_set_mctrl,
348 .get_mctrl = jsm_tty_get_mctrl,
349 .stop_tx = jsm_tty_stop_tx,
350 .start_tx = jsm_tty_start_tx,
351 .send_xchar = jsm_tty_send_xchar,
352 .stop_rx = jsm_tty_stop_rx,
353 .enable_ms = jsm_tty_enable_ms,
354 .break_ctl = jsm_tty_break,
355 .startup = jsm_tty_open,
356 .shutdown = jsm_tty_close,
357 .set_termios = jsm_tty_set_termios,
358 .type = jsm_tty_type,
359 .release_port = jsm_tty_release_port,
360 .request_port = jsm_tty_request_port,
361 .config_port = jsm_config_port,
362};
363
364/*
365 * jsm_tty_init()
366 *
367 * Init the tty subsystem. Called once per board after board has been
368 * downloaded and init'ed.
369 */
370int __devinit jsm_tty_init(struct jsm_board *brd)
371{
372 int i;
373 void __iomem *vaddr;
374 struct jsm_channel *ch;
375
376 if (!brd)
377 return -ENXIO;
378
379 jsm_printk(INIT, INFO, &brd->pci_dev, "start\n");
380
381 /*
382 * Initialize board structure elements.
383 */
384
385 brd->nasync = brd->maxports;
386
387 /*
388 * Allocate channel memory that might not have been allocated
389 * when the driver was first loaded.
390 */
391 for (i = 0; i < brd->nasync; i++) {
392 if (!brd->channels[i]) {
393
394 /*
395 * Okay to malloc with GFP_KERNEL, we are not at
396 * interrupt context, and there are no locks held.
397 */
398 brd->channels[i] = kzalloc(sizeof(struct jsm_channel), GFP_KERNEL);
399 if (!brd->channels[i]) {
400 jsm_printk(CORE, ERR, &brd->pci_dev,
401 "%s:%d Unable to allocate memory for channel struct\n",
402 __FILE__, __LINE__);
403 }
404 }
405 }
406
407 ch = brd->channels[0];
408 vaddr = brd->re_map_membase;
409
410 /* Set up channel variables */
411 for (i = 0; i < brd->nasync; i++, ch = brd->channels[i]) {
412
413 if (!brd->channels[i])
414 continue;
415
416 spin_lock_init(&ch->ch_lock);
417
418 if (brd->bd_uart_offset == 0x200)
419 ch->ch_neo_uart = vaddr + (brd->bd_uart_offset * i);
420
421 ch->ch_bd = brd;
422 ch->ch_portnum = i;
423
424 /* .25 second delay */
425 ch->ch_close_delay = 250;
426
427 init_waitqueue_head(&ch->ch_flags_wait);
428 }
429
430 jsm_printk(INIT, INFO, &brd->pci_dev, "finish\n");
431 return 0;
432}
433
434int jsm_uart_port_init(struct jsm_board *brd)
435{
436 int i, rc;
437 unsigned int line;
438 struct jsm_channel *ch;
439
440 if (!brd)
441 return -ENXIO;
442
443 jsm_printk(INIT, INFO, &brd->pci_dev, "start\n");
444
445 /*
446 * Initialize board structure elements.
447 */
448
449 brd->nasync = brd->maxports;
450
451 /* Set up channel variables */
452 for (i = 0; i < brd->nasync; i++, ch = brd->channels[i]) {
453
454 if (!brd->channels[i])
455 continue;
456
457 brd->channels[i]->uart_port.irq = brd->irq;
458 brd->channels[i]->uart_port.uartclk = 14745600;
459 brd->channels[i]->uart_port.type = PORT_JSM;
460 brd->channels[i]->uart_port.iotype = UPIO_MEM;
461 brd->channels[i]->uart_port.membase = brd->re_map_membase;
462 brd->channels[i]->uart_port.fifosize = 16;
463 brd->channels[i]->uart_port.ops = &jsm_ops;
464 line = find_first_zero_bit(linemap, MAXLINES);
465 if (line >= MAXLINES) {
466 printk(KERN_INFO "jsm: linemap is full, added device failed\n");
467 continue;
468 } else
469 set_bit(line, linemap);
470 brd->channels[i]->uart_port.line = line;
471 rc = uart_add_one_port (&jsm_uart_driver, &brd->channels[i]->uart_port);
472 if (rc){
473 printk(KERN_INFO "jsm: Port %d failed. Aborting...\n", i);
474 return rc;
475 }
476 else
477 printk(KERN_INFO "jsm: Port %d added\n", i);
478 }
479
480 jsm_printk(INIT, INFO, &brd->pci_dev, "finish\n");
481 return 0;
482}
483
484int jsm_remove_uart_port(struct jsm_board *brd)
485{
486 int i;
487 struct jsm_channel *ch;
488
489 if (!brd)
490 return -ENXIO;
491
492 jsm_printk(INIT, INFO, &brd->pci_dev, "start\n");
493
494 /*
495 * Initialize board structure elements.
496 */
497
498 brd->nasync = brd->maxports;
499
500 /* Set up channel variables */
501 for (i = 0; i < brd->nasync; i++) {
502
503 if (!brd->channels[i])
504 continue;
505
506 ch = brd->channels[i];
507
508 clear_bit(ch->uart_port.line, linemap);
509 uart_remove_one_port(&jsm_uart_driver, &brd->channels[i]->uart_port);
510 }
511
512 jsm_printk(INIT, INFO, &brd->pci_dev, "finish\n");
513 return 0;
514}
515
516void jsm_input(struct jsm_channel *ch)
517{
518 struct jsm_board *bd;
519 struct tty_struct *tp;
520 u32 rmask;
521 u16 head;
522 u16 tail;
523 int data_len;
524 unsigned long lock_flags;
525 int len = 0;
526 int n = 0;
527 int s = 0;
528 int i = 0;
529
530 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev, "start\n");
531
532 if (!ch)
533 return;
534
535 tp = ch->uart_port.state->port.tty;
536
537 bd = ch->ch_bd;
538 if(!bd)
539 return;
540
541 spin_lock_irqsave(&ch->ch_lock, lock_flags);
542
543 /*
544 *Figure the number of characters in the buffer.
545 *Exit immediately if none.
546 */
547
548 rmask = RQUEUEMASK;
549
550 head = ch->ch_r_head & rmask;
551 tail = ch->ch_r_tail & rmask;
552
553 data_len = (head - tail) & rmask;
554 if (data_len == 0) {
555 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
556 return;
557 }
558
559 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev, "start\n");
560
561 /*
562 *If the device is not open, or CREAD is off, flush
563 *input data and return immediately.
564 */
565 if (!tp ||
566 !(tp->termios->c_cflag & CREAD) ) {
567
568 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev,
569 "input. dropping %d bytes on port %d...\n", data_len, ch->ch_portnum);
570 ch->ch_r_head = tail;
571
572 /* Force queue flow control to be released, if needed */
573 jsm_check_queue_flow_control(ch);
574
575 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
576 return;
577 }
578
579 /*
580 * If we are throttled, simply don't read any data.
581 */
582 if (ch->ch_flags & CH_STOPI) {
583 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
584 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev,
585 "Port %d throttled, not reading any data. head: %x tail: %x\n",
586 ch->ch_portnum, head, tail);
587 return;
588 }
589
590 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev, "start 2\n");
591
592 if (data_len <= 0) {
593 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
594 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev, "jsm_input 1\n");
595 return;
596 }
597
598 len = tty_buffer_request_room(tp, data_len);
599 n = len;
600
601 /*
602 * n now contains the most amount of data we can copy,
603 * bounded either by the flip buffer size or the amount
604 * of data the card actually has pending...
605 */
606 while (n) {
607 s = ((head >= tail) ? head : RQUEUESIZE) - tail;
608 s = min(s, n);
609
610 if (s <= 0)
611 break;
612
613 /*
614 * If conditions are such that ld needs to see all
615 * UART errors, we will have to walk each character
616 * and error byte and send them to the buffer one at
617 * a time.
618 */
619
620 if (I_PARMRK(tp) || I_BRKINT(tp) || I_INPCK(tp)) {
621 for (i = 0; i < s; i++) {
622 /*
623 * Give the Linux ld the flags in the
624 * format it likes.
625 */
626 if (*(ch->ch_equeue +tail +i) & UART_LSR_BI)
627 tty_insert_flip_char(tp, *(ch->ch_rqueue +tail +i), TTY_BREAK);
628 else if (*(ch->ch_equeue +tail +i) & UART_LSR_PE)
629 tty_insert_flip_char(tp, *(ch->ch_rqueue +tail +i), TTY_PARITY);
630 else if (*(ch->ch_equeue +tail +i) & UART_LSR_FE)
631 tty_insert_flip_char(tp, *(ch->ch_rqueue +tail +i), TTY_FRAME);
632 else
633 tty_insert_flip_char(tp, *(ch->ch_rqueue +tail +i), TTY_NORMAL);
634 }
635 } else {
636 tty_insert_flip_string(tp, ch->ch_rqueue + tail, s) ;
637 }
638 tail += s;
639 n -= s;
640 /* Flip queue if needed */
641 tail &= rmask;
642 }
643
644 ch->ch_r_tail = tail & rmask;
645 ch->ch_e_tail = tail & rmask;
646 jsm_check_queue_flow_control(ch);
647 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
648
649 /* Tell the tty layer its okay to "eat" the data now */
650 tty_flip_buffer_push(tp);
651
652 jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev, "finish\n");
653}
654
655static void jsm_carrier(struct jsm_channel *ch)
656{
657 struct jsm_board *bd;
658
659 int virt_carrier = 0;
660 int phys_carrier = 0;
661
662 jsm_printk(CARR, INFO, &ch->ch_bd->pci_dev, "start\n");
663 if (!ch)
664 return;
665
666 bd = ch->ch_bd;
667
668 if (!bd)
669 return;
670
671 if (ch->ch_mistat & UART_MSR_DCD) {
672 jsm_printk(CARR, INFO, &ch->ch_bd->pci_dev,
673 "mistat: %x D_CD: %x\n", ch->ch_mistat, ch->ch_mistat & UART_MSR_DCD);
674 phys_carrier = 1;
675 }
676
677 if (ch->ch_c_cflag & CLOCAL)
678 virt_carrier = 1;
679
680 jsm_printk(CARR, INFO, &ch->ch_bd->pci_dev,
681 "DCD: physical: %d virt: %d\n", phys_carrier, virt_carrier);
682
683 /*
684 * Test for a VIRTUAL carrier transition to HIGH.
685 */
686 if (((ch->ch_flags & CH_FCAR) == 0) && (virt_carrier == 1)) {
687
688 /*
689 * When carrier rises, wake any threads waiting
690 * for carrier in the open routine.
691 */
692
693 jsm_printk(CARR, INFO, &ch->ch_bd->pci_dev,
694 "carrier: virt DCD rose\n");
695
696 if (waitqueue_active(&(ch->ch_flags_wait)))
697 wake_up_interruptible(&ch->ch_flags_wait);
698 }
699
700 /*
701 * Test for a PHYSICAL carrier transition to HIGH.
702 */
703 if (((ch->ch_flags & CH_CD) == 0) && (phys_carrier == 1)) {
704
705 /*
706 * When carrier rises, wake any threads waiting
707 * for carrier in the open routine.
708 */
709
710 jsm_printk(CARR, INFO, &ch->ch_bd->pci_dev,
711 "carrier: physical DCD rose\n");
712
713 if (waitqueue_active(&(ch->ch_flags_wait)))
714 wake_up_interruptible(&ch->ch_flags_wait);
715 }
716
717 /*
718 * Test for a PHYSICAL transition to low, so long as we aren't
719 * currently ignoring physical transitions (which is what "virtual
720 * carrier" indicates).
721 *
722 * The transition of the virtual carrier to low really doesn't
723 * matter... it really only means "ignore carrier state", not
724 * "make pretend that carrier is there".
725 */
726 if ((virt_carrier == 0) && ((ch->ch_flags & CH_CD) != 0)
727 && (phys_carrier == 0)) {
728 /*
729 * When carrier drops:
730 *
731 * Drop carrier on all open units.
732 *
733 * Flush queues, waking up any task waiting in the
734 * line discipline.
735 *
736 * Send a hangup to the control terminal.
737 *
738 * Enable all select calls.
739 */
740 if (waitqueue_active(&(ch->ch_flags_wait)))
741 wake_up_interruptible(&ch->ch_flags_wait);
742 }
743
744 /*
745 * Make sure that our cached values reflect the current reality.
746 */
747 if (virt_carrier == 1)
748 ch->ch_flags |= CH_FCAR;
749 else
750 ch->ch_flags &= ~CH_FCAR;
751
752 if (phys_carrier == 1)
753 ch->ch_flags |= CH_CD;
754 else
755 ch->ch_flags &= ~CH_CD;
756}
757
758
759void jsm_check_queue_flow_control(struct jsm_channel *ch)
760{
761 struct board_ops *bd_ops = ch->ch_bd->bd_ops;
762 int qleft;
763
764 /* Store how much space we have left in the queue */
765 if ((qleft = ch->ch_r_tail - ch->ch_r_head - 1) < 0)
766 qleft += RQUEUEMASK + 1;
767
768 /*
769 * Check to see if we should enforce flow control on our queue because
770 * the ld (or user) isn't reading data out of our queue fast enuf.
771 *
772 * NOTE: This is done based on what the current flow control of the
773 * port is set for.
774 *
775 * 1) HWFLOW (RTS) - Turn off the UART's Receive interrupt.
776 * This will cause the UART's FIFO to back up, and force
777 * the RTS signal to be dropped.
778 * 2) SWFLOW (IXOFF) - Keep trying to send a stop character to
779 * the other side, in hopes it will stop sending data to us.
780 * 3) NONE - Nothing we can do. We will simply drop any extra data
781 * that gets sent into us when the queue fills up.
782 */
783 if (qleft < 256) {
784 /* HWFLOW */
785 if (ch->ch_c_cflag & CRTSCTS) {
786 if(!(ch->ch_flags & CH_RECEIVER_OFF)) {
787 bd_ops->disable_receiver(ch);
788 ch->ch_flags |= (CH_RECEIVER_OFF);
789 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev,
790 "Internal queue hit hilevel mark (%d)! Turning off interrupts.\n",
791 qleft);
792 }
793 }
794 /* SWFLOW */
795 else if (ch->ch_c_iflag & IXOFF) {
796 if (ch->ch_stops_sent <= MAX_STOPS_SENT) {
797 bd_ops->send_stop_character(ch);
798 ch->ch_stops_sent++;
799 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev,
800 "Sending stop char! Times sent: %x\n", ch->ch_stops_sent);
801 }
802 }
803 }
804
805 /*
806 * Check to see if we should unenforce flow control because
807 * ld (or user) finally read enuf data out of our queue.
808 *
809 * NOTE: This is done based on what the current flow control of the
810 * port is set for.
811 *
812 * 1) HWFLOW (RTS) - Turn back on the UART's Receive interrupt.
813 * This will cause the UART's FIFO to raise RTS back up,
814 * which will allow the other side to start sending data again.
815 * 2) SWFLOW (IXOFF) - Send a start character to
816 * the other side, so it will start sending data to us again.
817 * 3) NONE - Do nothing. Since we didn't do anything to turn off the
818 * other side, we don't need to do anything now.
819 */
820 if (qleft > (RQUEUESIZE / 2)) {
821 /* HWFLOW */
822 if (ch->ch_c_cflag & CRTSCTS) {
823 if (ch->ch_flags & CH_RECEIVER_OFF) {
824 bd_ops->enable_receiver(ch);
825 ch->ch_flags &= ~(CH_RECEIVER_OFF);
826 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev,
827 "Internal queue hit lowlevel mark (%d)! Turning on interrupts.\n",
828 qleft);
829 }
830 }
831 /* SWFLOW */
832 else if (ch->ch_c_iflag & IXOFF && ch->ch_stops_sent) {
833 ch->ch_stops_sent = 0;
834 bd_ops->send_start_character(ch);
835 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev, "Sending start char!\n");
836 }
837 }
838}
839
840/*
841 * jsm_tty_write()
842 *
843 * Take data from the user or kernel and send it out to the FEP.
844 * In here exists all the Transparent Print magic as well.
845 */
846int jsm_tty_write(struct uart_port *port)
847{
848 int bufcount;
849 int data_count = 0,data_count1 =0;
850 u16 head;
851 u16 tail;
852 u16 tmask;
853 u32 remain;
854 int temp_tail = port->state->xmit.tail;
855 struct jsm_channel *channel = (struct jsm_channel *)port;
856
857 tmask = WQUEUEMASK;
858 head = (channel->ch_w_head) & tmask;
859 tail = (channel->ch_w_tail) & tmask;
860
861 if ((bufcount = tail - head - 1) < 0)
862 bufcount += WQUEUESIZE;
863
864 bufcount = min(bufcount, 56);
865 remain = WQUEUESIZE - head;
866
867 data_count = 0;
868 if (bufcount >= remain) {
869 bufcount -= remain;
870 while ((port->state->xmit.head != temp_tail) &&
871 (data_count < remain)) {
872 channel->ch_wqueue[head++] =
873 port->state->xmit.buf[temp_tail];
874
875 temp_tail++;
876 temp_tail &= (UART_XMIT_SIZE - 1);
877 data_count++;
878 }
879 if (data_count == remain) head = 0;
880 }
881
882 data_count1 = 0;
883 if (bufcount > 0) {
884 remain = bufcount;
885 while ((port->state->xmit.head != temp_tail) &&
886 (data_count1 < remain)) {
887 channel->ch_wqueue[head++] =
888 port->state->xmit.buf[temp_tail];
889
890 temp_tail++;
891 temp_tail &= (UART_XMIT_SIZE - 1);
892 data_count1++;
893
894 }
895 }
896
897 port->state->xmit.tail = temp_tail;
898
899 data_count += data_count1;
900 if (data_count) {
901 head &= tmask;
902 channel->ch_w_head = head;
903 }
904
905 if (data_count) {
906 channel->ch_bd->bd_ops->copy_data_from_queue_to_uart(channel);
907 }
908
909 return data_count;
910}
diff --git a/drivers/serial/kgdboc.c b/drivers/serial/kgdboc.c
deleted file mode 100644
index 39f9a1adaa75..000000000000
--- a/drivers/serial/kgdboc.c
+++ /dev/null
@@ -1,268 +0,0 @@
1/*
2 * Based on the same principle as kgdboe using the NETPOLL api, this
3 * driver uses a console polling api to implement a gdb serial inteface
4 * which is multiplexed on a console port.
5 *
6 * Maintainer: Jason Wessel <jason.wessel@windriver.com>
7 *
8 * 2007-2008 (c) Jason Wessel - Wind River Systems, Inc.
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14#include <linux/kernel.h>
15#include <linux/ctype.h>
16#include <linux/kgdb.h>
17#include <linux/kdb.h>
18#include <linux/tty.h>
19#include <linux/console.h>
20#include <linux/vt_kern.h>
21
22#define MAX_CONFIG_LEN 40
23
24static struct kgdb_io kgdboc_io_ops;
25
26/* -1 = init not run yet, 0 = unconfigured, 1 = configured. */
27static int configured = -1;
28
29static char config[MAX_CONFIG_LEN];
30static struct kparam_string kps = {
31 .string = config,
32 .maxlen = MAX_CONFIG_LEN,
33};
34
35static int kgdboc_use_kms; /* 1 if we use kernel mode switching */
36static struct tty_driver *kgdb_tty_driver;
37static int kgdb_tty_line;
38
39#ifdef CONFIG_KDB_KEYBOARD
40static int kgdboc_register_kbd(char **cptr)
41{
42 if (strncmp(*cptr, "kbd", 3) == 0) {
43 if (kdb_poll_idx < KDB_POLL_FUNC_MAX) {
44 kdb_poll_funcs[kdb_poll_idx] = kdb_get_kbd_char;
45 kdb_poll_idx++;
46 if (cptr[0][3] == ',')
47 *cptr += 4;
48 else
49 return 1;
50 }
51 }
52 return 0;
53}
54
55static void kgdboc_unregister_kbd(void)
56{
57 int i;
58
59 for (i = 0; i < kdb_poll_idx; i++) {
60 if (kdb_poll_funcs[i] == kdb_get_kbd_char) {
61 kdb_poll_idx--;
62 kdb_poll_funcs[i] = kdb_poll_funcs[kdb_poll_idx];
63 kdb_poll_funcs[kdb_poll_idx] = NULL;
64 i--;
65 }
66 }
67}
68#else /* ! CONFIG_KDB_KEYBOARD */
69#define kgdboc_register_kbd(x) 0
70#define kgdboc_unregister_kbd()
71#endif /* ! CONFIG_KDB_KEYBOARD */
72
73static int kgdboc_option_setup(char *opt)
74{
75 if (strlen(opt) > MAX_CONFIG_LEN) {
76 printk(KERN_ERR "kgdboc: config string too long\n");
77 return -ENOSPC;
78 }
79 strcpy(config, opt);
80
81 return 0;
82}
83
84__setup("kgdboc=", kgdboc_option_setup);
85
86static void cleanup_kgdboc(void)
87{
88 kgdboc_unregister_kbd();
89 if (configured == 1)
90 kgdb_unregister_io_module(&kgdboc_io_ops);
91}
92
93static int configure_kgdboc(void)
94{
95 struct tty_driver *p;
96 int tty_line = 0;
97 int err;
98 char *cptr = config;
99 struct console *cons;
100
101 err = kgdboc_option_setup(config);
102 if (err || !strlen(config) || isspace(config[0]))
103 goto noconfig;
104
105 err = -ENODEV;
106 kgdboc_io_ops.is_console = 0;
107 kgdb_tty_driver = NULL;
108
109 kgdboc_use_kms = 0;
110 if (strncmp(cptr, "kms,", 4) == 0) {
111 cptr += 4;
112 kgdboc_use_kms = 1;
113 }
114
115 if (kgdboc_register_kbd(&cptr))
116 goto do_register;
117
118 p = tty_find_polling_driver(cptr, &tty_line);
119 if (!p)
120 goto noconfig;
121
122 cons = console_drivers;
123 while (cons) {
124 int idx;
125 if (cons->device && cons->device(cons, &idx) == p &&
126 idx == tty_line) {
127 kgdboc_io_ops.is_console = 1;
128 break;
129 }
130 cons = cons->next;
131 }
132
133 kgdb_tty_driver = p;
134 kgdb_tty_line = tty_line;
135
136do_register:
137 err = kgdb_register_io_module(&kgdboc_io_ops);
138 if (err)
139 goto noconfig;
140
141 configured = 1;
142
143 return 0;
144
145noconfig:
146 config[0] = 0;
147 configured = 0;
148 cleanup_kgdboc();
149
150 return err;
151}
152
153static int __init init_kgdboc(void)
154{
155 /* Already configured? */
156 if (configured == 1)
157 return 0;
158
159 return configure_kgdboc();
160}
161
162static int kgdboc_get_char(void)
163{
164 if (!kgdb_tty_driver)
165 return -1;
166 return kgdb_tty_driver->ops->poll_get_char(kgdb_tty_driver,
167 kgdb_tty_line);
168}
169
170static void kgdboc_put_char(u8 chr)
171{
172 if (!kgdb_tty_driver)
173 return;
174 kgdb_tty_driver->ops->poll_put_char(kgdb_tty_driver,
175 kgdb_tty_line, chr);
176}
177
178static int param_set_kgdboc_var(const char *kmessage, struct kernel_param *kp)
179{
180 int len = strlen(kmessage);
181
182 if (len >= MAX_CONFIG_LEN) {
183 printk(KERN_ERR "kgdboc: config string too long\n");
184 return -ENOSPC;
185 }
186
187 /* Only copy in the string if the init function has not run yet */
188 if (configured < 0) {
189 strcpy(config, kmessage);
190 return 0;
191 }
192
193 if (kgdb_connected) {
194 printk(KERN_ERR
195 "kgdboc: Cannot reconfigure while KGDB is connected.\n");
196
197 return -EBUSY;
198 }
199
200 strcpy(config, kmessage);
201 /* Chop out \n char as a result of echo */
202 if (config[len - 1] == '\n')
203 config[len - 1] = '\0';
204
205 if (configured == 1)
206 cleanup_kgdboc();
207
208 /* Go and configure with the new params. */
209 return configure_kgdboc();
210}
211
212static int dbg_restore_graphics;
213
214static void kgdboc_pre_exp_handler(void)
215{
216 if (!dbg_restore_graphics && kgdboc_use_kms) {
217 dbg_restore_graphics = 1;
218 con_debug_enter(vc_cons[fg_console].d);
219 }
220 /* Increment the module count when the debugger is active */
221 if (!kgdb_connected)
222 try_module_get(THIS_MODULE);
223}
224
225static void kgdboc_post_exp_handler(void)
226{
227 /* decrement the module count when the debugger detaches */
228 if (!kgdb_connected)
229 module_put(THIS_MODULE);
230 if (kgdboc_use_kms && dbg_restore_graphics) {
231 dbg_restore_graphics = 0;
232 con_debug_leave();
233 }
234}
235
236static struct kgdb_io kgdboc_io_ops = {
237 .name = "kgdboc",
238 .read_char = kgdboc_get_char,
239 .write_char = kgdboc_put_char,
240 .pre_exception = kgdboc_pre_exp_handler,
241 .post_exception = kgdboc_post_exp_handler,
242};
243
244#ifdef CONFIG_KGDB_SERIAL_CONSOLE
245/* This is only available if kgdboc is a built in for early debugging */
246int __init kgdboc_early_init(char *opt)
247{
248 /* save the first character of the config string because the
249 * init routine can destroy it.
250 */
251 char save_ch;
252
253 kgdboc_option_setup(opt);
254 save_ch = config[0];
255 init_kgdboc();
256 config[0] = save_ch;
257 return 0;
258}
259
260early_param("ekgdboc", kgdboc_early_init);
261#endif /* CONFIG_KGDB_SERIAL_CONSOLE */
262
263module_init(init_kgdboc);
264module_exit(cleanup_kgdboc);
265module_param_call(kgdboc, param_set_kgdboc_var, param_get_string, &kps, 0644);
266MODULE_PARM_DESC(kgdboc, "<serial_device>[,baud]");
267MODULE_DESCRIPTION("KGDB Console TTY Driver");
268MODULE_LICENSE("GPL");
diff --git a/drivers/serial/m32r_sio.c b/drivers/serial/m32r_sio.c
deleted file mode 100644
index bea5c215460c..000000000000
--- a/drivers/serial/m32r_sio.c
+++ /dev/null
@@ -1,1192 +0,0 @@
1/*
2 * m32r_sio.c
3 *
4 * Driver for M32R serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 * Based on drivers/serial/8250.c.
8 *
9 * Copyright (C) 2001 Russell King.
10 * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 */
17
18/*
19 * A note about mapbase / membase
20 *
21 * mapbase is the physical address of the IO port. Currently, we don't
22 * support this very well, and it may well be dropped from this driver
23 * in future. As such, mapbase should be NULL.
24 *
25 * membase is an 'ioremapped' cookie. This is compatible with the old
26 * serial.c driver, and is currently the preferred form.
27 */
28
29#if defined(CONFIG_SERIAL_M32R_SIO_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
30#define SUPPORT_SYSRQ
31#endif
32
33#include <linux/module.h>
34#include <linux/tty.h>
35#include <linux/ioport.h>
36#include <linux/init.h>
37#include <linux/console.h>
38#include <linux/sysrq.h>
39#include <linux/serial.h>
40#include <linux/serialP.h>
41#include <linux/delay.h>
42
43#include <asm/m32r.h>
44#include <asm/io.h>
45#include <asm/irq.h>
46
47#define PORT_M32R_BASE PORT_M32R_SIO
48#define PORT_INDEX(x) (x - PORT_M32R_BASE + 1)
49#define BAUD_RATE 115200
50
51#include <linux/serial_core.h>
52#include "m32r_sio.h"
53#include "m32r_sio_reg.h"
54
55/*
56 * Debugging.
57 */
58#if 0
59#define DEBUG_AUTOCONF(fmt...) printk(fmt)
60#else
61#define DEBUG_AUTOCONF(fmt...) do { } while (0)
62#endif
63
64#if 0
65#define DEBUG_INTR(fmt...) printk(fmt)
66#else
67#define DEBUG_INTR(fmt...) do { } while (0)
68#endif
69
70#define PASS_LIMIT 256
71
72/*
73 * We default to IRQ0 for the "no irq" hack. Some
74 * machine types want others as well - they're free
75 * to redefine this in their header file.
76 */
77#define is_real_interrupt(irq) ((irq) != 0)
78
79#define BASE_BAUD 115200
80
81/* Standard COM flags */
82#define STD_COM_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST)
83
84/*
85 * SERIAL_PORT_DFNS tells us about built-in ports that have no
86 * standard enumeration mechanism. Platforms that can find all
87 * serial ports via mechanisms like ACPI or PCI need not supply it.
88 */
89#if defined(CONFIG_PLAT_USRV)
90
91#define SERIAL_PORT_DFNS \
92 /* UART CLK PORT IRQ FLAGS */ \
93 { 0, BASE_BAUD, 0x3F8, PLD_IRQ_UART0, STD_COM_FLAGS }, /* ttyS0 */ \
94 { 0, BASE_BAUD, 0x2F8, PLD_IRQ_UART1, STD_COM_FLAGS }, /* ttyS1 */
95
96#else /* !CONFIG_PLAT_USRV */
97
98#if defined(CONFIG_SERIAL_M32R_PLDSIO)
99#define SERIAL_PORT_DFNS \
100 { 0, BASE_BAUD, ((unsigned long)PLD_ESIO0CR), PLD_IRQ_SIO0_RCV, \
101 STD_COM_FLAGS }, /* ttyS0 */
102#else
103#define SERIAL_PORT_DFNS \
104 { 0, BASE_BAUD, M32R_SIO_OFFSET, M32R_IRQ_SIO0_R, \
105 STD_COM_FLAGS }, /* ttyS0 */
106#endif
107
108#endif /* !CONFIG_PLAT_USRV */
109
110static struct old_serial_port old_serial_port[] = {
111 SERIAL_PORT_DFNS
112};
113
114#define UART_NR ARRAY_SIZE(old_serial_port)
115
116struct uart_sio_port {
117 struct uart_port port;
118 struct timer_list timer; /* "no irq" timer */
119 struct list_head list; /* ports on this IRQ */
120 unsigned short rev;
121 unsigned char acr;
122 unsigned char ier;
123 unsigned char lcr;
124 unsigned char mcr_mask; /* mask of user bits */
125 unsigned char mcr_force; /* mask of forced bits */
126 unsigned char lsr_break_flag;
127
128 /*
129 * We provide a per-port pm hook.
130 */
131 void (*pm)(struct uart_port *port,
132 unsigned int state, unsigned int old);
133};
134
135struct irq_info {
136 spinlock_t lock;
137 struct list_head *head;
138};
139
140static struct irq_info irq_lists[NR_IRQS];
141
142/*
143 * Here we define the default xmit fifo size used for each type of UART.
144 */
145static const struct serial_uart_config uart_config[] = {
146 [PORT_UNKNOWN] = {
147 .name = "unknown",
148 .dfl_xmit_fifo_size = 1,
149 .flags = 0,
150 },
151 [PORT_INDEX(PORT_M32R_SIO)] = {
152 .name = "M32RSIO",
153 .dfl_xmit_fifo_size = 1,
154 .flags = 0,
155 },
156};
157
158#ifdef CONFIG_SERIAL_M32R_PLDSIO
159
160#define __sio_in(x) inw((unsigned long)(x))
161#define __sio_out(v,x) outw((v),(unsigned long)(x))
162
163static inline void sio_set_baud_rate(unsigned long baud)
164{
165 unsigned short sbaud;
166 sbaud = (boot_cpu_data.bus_clock / (baud * 4))-1;
167 __sio_out(sbaud, PLD_ESIO0BAUR);
168}
169
170static void sio_reset(void)
171{
172 unsigned short tmp;
173
174 tmp = __sio_in(PLD_ESIO0RXB);
175 tmp = __sio_in(PLD_ESIO0RXB);
176 tmp = __sio_in(PLD_ESIO0CR);
177 sio_set_baud_rate(BAUD_RATE);
178 __sio_out(0x0300, PLD_ESIO0CR);
179 __sio_out(0x0003, PLD_ESIO0CR);
180}
181
182static void sio_init(void)
183{
184 unsigned short tmp;
185
186 tmp = __sio_in(PLD_ESIO0RXB);
187 tmp = __sio_in(PLD_ESIO0RXB);
188 tmp = __sio_in(PLD_ESIO0CR);
189 __sio_out(0x0300, PLD_ESIO0CR);
190 __sio_out(0x0003, PLD_ESIO0CR);
191}
192
193static void sio_error(int *status)
194{
195 printk("SIO0 error[%04x]\n", *status);
196 do {
197 sio_init();
198 } while ((*status = __sio_in(PLD_ESIO0CR)) != 3);
199}
200
201#else /* not CONFIG_SERIAL_M32R_PLDSIO */
202
203#define __sio_in(x) inl(x)
204#define __sio_out(v,x) outl((v),(x))
205
206static inline void sio_set_baud_rate(unsigned long baud)
207{
208 unsigned long i, j;
209
210 i = boot_cpu_data.bus_clock / (baud * 16);
211 j = (boot_cpu_data.bus_clock - (i * baud * 16)) / baud;
212 i -= 1;
213 j = (j + 1) >> 1;
214
215 __sio_out(i, M32R_SIO0_BAUR_PORTL);
216 __sio_out(j, M32R_SIO0_RBAUR_PORTL);
217}
218
219static void sio_reset(void)
220{
221 __sio_out(0x00000300, M32R_SIO0_CR_PORTL); /* init status */
222 __sio_out(0x00000800, M32R_SIO0_MOD1_PORTL); /* 8bit */
223 __sio_out(0x00000080, M32R_SIO0_MOD0_PORTL); /* 1stop non */
224 sio_set_baud_rate(BAUD_RATE);
225 __sio_out(0x00000000, M32R_SIO0_TRCR_PORTL);
226 __sio_out(0x00000003, M32R_SIO0_CR_PORTL); /* RXCEN */
227}
228
229static void sio_init(void)
230{
231 unsigned int tmp;
232
233 tmp = __sio_in(M32R_SIO0_RXB_PORTL);
234 tmp = __sio_in(M32R_SIO0_RXB_PORTL);
235 tmp = __sio_in(M32R_SIO0_STS_PORTL);
236 __sio_out(0x00000003, M32R_SIO0_CR_PORTL);
237}
238
239static void sio_error(int *status)
240{
241 printk("SIO0 error[%04x]\n", *status);
242 do {
243 sio_init();
244 } while ((*status = __sio_in(M32R_SIO0_CR_PORTL)) != 3);
245}
246
247#endif /* CONFIG_SERIAL_M32R_PLDSIO */
248
249static unsigned int sio_in(struct uart_sio_port *up, int offset)
250{
251 return __sio_in(up->port.iobase + offset);
252}
253
254static void sio_out(struct uart_sio_port *up, int offset, int value)
255{
256 __sio_out(value, up->port.iobase + offset);
257}
258
259static unsigned int serial_in(struct uart_sio_port *up, int offset)
260{
261 if (!offset)
262 return 0;
263
264 return __sio_in(offset);
265}
266
267static void serial_out(struct uart_sio_port *up, int offset, int value)
268{
269 if (!offset)
270 return;
271
272 __sio_out(value, offset);
273}
274
275static void m32r_sio_stop_tx(struct uart_port *port)
276{
277 struct uart_sio_port *up = (struct uart_sio_port *)port;
278
279 if (up->ier & UART_IER_THRI) {
280 up->ier &= ~UART_IER_THRI;
281 serial_out(up, UART_IER, up->ier);
282 }
283}
284
285static void m32r_sio_start_tx(struct uart_port *port)
286{
287#ifdef CONFIG_SERIAL_M32R_PLDSIO
288 struct uart_sio_port *up = (struct uart_sio_port *)port;
289 struct circ_buf *xmit = &up->port.state->xmit;
290
291 if (!(up->ier & UART_IER_THRI)) {
292 up->ier |= UART_IER_THRI;
293 serial_out(up, UART_IER, up->ier);
294 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
295 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
296 up->port.icount.tx++;
297 }
298 while((serial_in(up, UART_LSR) & UART_EMPTY) != UART_EMPTY);
299#else
300 struct uart_sio_port *up = (struct uart_sio_port *)port;
301
302 if (!(up->ier & UART_IER_THRI)) {
303 up->ier |= UART_IER_THRI;
304 serial_out(up, UART_IER, up->ier);
305 }
306#endif
307}
308
309static void m32r_sio_stop_rx(struct uart_port *port)
310{
311 struct uart_sio_port *up = (struct uart_sio_port *)port;
312
313 up->ier &= ~UART_IER_RLSI;
314 up->port.read_status_mask &= ~UART_LSR_DR;
315 serial_out(up, UART_IER, up->ier);
316}
317
318static void m32r_sio_enable_ms(struct uart_port *port)
319{
320 struct uart_sio_port *up = (struct uart_sio_port *)port;
321
322 up->ier |= UART_IER_MSI;
323 serial_out(up, UART_IER, up->ier);
324}
325
326static void receive_chars(struct uart_sio_port *up, int *status)
327{
328 struct tty_struct *tty = up->port.state->port.tty;
329 unsigned char ch;
330 unsigned char flag;
331 int max_count = 256;
332
333 do {
334 ch = sio_in(up, SIORXB);
335 flag = TTY_NORMAL;
336 up->port.icount.rx++;
337
338 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
339 UART_LSR_FE | UART_LSR_OE))) {
340 /*
341 * For statistics only
342 */
343 if (*status & UART_LSR_BI) {
344 *status &= ~(UART_LSR_FE | UART_LSR_PE);
345 up->port.icount.brk++;
346 /*
347 * We do the SysRQ and SAK checking
348 * here because otherwise the break
349 * may get masked by ignore_status_mask
350 * or read_status_mask.
351 */
352 if (uart_handle_break(&up->port))
353 goto ignore_char;
354 } else if (*status & UART_LSR_PE)
355 up->port.icount.parity++;
356 else if (*status & UART_LSR_FE)
357 up->port.icount.frame++;
358 if (*status & UART_LSR_OE)
359 up->port.icount.overrun++;
360
361 /*
362 * Mask off conditions which should be ingored.
363 */
364 *status &= up->port.read_status_mask;
365
366 if (up->port.line == up->port.cons->index) {
367 /* Recover the break flag from console xmit */
368 *status |= up->lsr_break_flag;
369 up->lsr_break_flag = 0;
370 }
371
372 if (*status & UART_LSR_BI) {
373 DEBUG_INTR("handling break....");
374 flag = TTY_BREAK;
375 } else if (*status & UART_LSR_PE)
376 flag = TTY_PARITY;
377 else if (*status & UART_LSR_FE)
378 flag = TTY_FRAME;
379 }
380 if (uart_handle_sysrq_char(&up->port, ch))
381 goto ignore_char;
382 if ((*status & up->port.ignore_status_mask) == 0)
383 tty_insert_flip_char(tty, ch, flag);
384
385 if (*status & UART_LSR_OE) {
386 /*
387 * Overrun is special, since it's reported
388 * immediately, and doesn't affect the current
389 * character.
390 */
391 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
392 }
393 ignore_char:
394 *status = serial_in(up, UART_LSR);
395 } while ((*status & UART_LSR_DR) && (max_count-- > 0));
396 tty_flip_buffer_push(tty);
397}
398
399static void transmit_chars(struct uart_sio_port *up)
400{
401 struct circ_buf *xmit = &up->port.state->xmit;
402 int count;
403
404 if (up->port.x_char) {
405#ifndef CONFIG_SERIAL_M32R_PLDSIO /* XXX */
406 serial_out(up, UART_TX, up->port.x_char);
407#endif
408 up->port.icount.tx++;
409 up->port.x_char = 0;
410 return;
411 }
412 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
413 m32r_sio_stop_tx(&up->port);
414 return;
415 }
416
417 count = up->port.fifosize;
418 do {
419 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
420 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
421 up->port.icount.tx++;
422 if (uart_circ_empty(xmit))
423 break;
424 while (!(serial_in(up, UART_LSR) & UART_LSR_THRE));
425
426 } while (--count > 0);
427
428 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
429 uart_write_wakeup(&up->port);
430
431 DEBUG_INTR("THRE...");
432
433 if (uart_circ_empty(xmit))
434 m32r_sio_stop_tx(&up->port);
435}
436
437/*
438 * This handles the interrupt from one port.
439 */
440static inline void m32r_sio_handle_port(struct uart_sio_port *up,
441 unsigned int status)
442{
443 DEBUG_INTR("status = %x...", status);
444
445 if (status & 0x04)
446 receive_chars(up, &status);
447 if (status & 0x01)
448 transmit_chars(up);
449}
450
451/*
452 * This is the serial driver's interrupt routine.
453 *
454 * Arjan thinks the old way was overly complex, so it got simplified.
455 * Alan disagrees, saying that need the complexity to handle the weird
456 * nature of ISA shared interrupts. (This is a special exception.)
457 *
458 * In order to handle ISA shared interrupts properly, we need to check
459 * that all ports have been serviced, and therefore the ISA interrupt
460 * line has been de-asserted.
461 *
462 * This means we need to loop through all ports. checking that they
463 * don't have an interrupt pending.
464 */
465static irqreturn_t m32r_sio_interrupt(int irq, void *dev_id)
466{
467 struct irq_info *i = dev_id;
468 struct list_head *l, *end = NULL;
469 int pass_counter = 0;
470
471 DEBUG_INTR("m32r_sio_interrupt(%d)...", irq);
472
473#ifdef CONFIG_SERIAL_M32R_PLDSIO
474// if (irq == PLD_IRQ_SIO0_SND)
475// irq = PLD_IRQ_SIO0_RCV;
476#else
477 if (irq == M32R_IRQ_SIO0_S)
478 irq = M32R_IRQ_SIO0_R;
479#endif
480
481 spin_lock(&i->lock);
482
483 l = i->head;
484 do {
485 struct uart_sio_port *up;
486 unsigned int sts;
487
488 up = list_entry(l, struct uart_sio_port, list);
489
490 sts = sio_in(up, SIOSTS);
491 if (sts & 0x5) {
492 spin_lock(&up->port.lock);
493 m32r_sio_handle_port(up, sts);
494 spin_unlock(&up->port.lock);
495
496 end = NULL;
497 } else if (end == NULL)
498 end = l;
499
500 l = l->next;
501
502 if (l == i->head && pass_counter++ > PASS_LIMIT) {
503 if (sts & 0xe0)
504 sio_error(&sts);
505 break;
506 }
507 } while (l != end);
508
509 spin_unlock(&i->lock);
510
511 DEBUG_INTR("end.\n");
512
513 return IRQ_HANDLED;
514}
515
516/*
517 * To support ISA shared interrupts, we need to have one interrupt
518 * handler that ensures that the IRQ line has been deasserted
519 * before returning. Failing to do this will result in the IRQ
520 * line being stuck active, and, since ISA irqs are edge triggered,
521 * no more IRQs will be seen.
522 */
523static void serial_do_unlink(struct irq_info *i, struct uart_sio_port *up)
524{
525 spin_lock_irq(&i->lock);
526
527 if (!list_empty(i->head)) {
528 if (i->head == &up->list)
529 i->head = i->head->next;
530 list_del(&up->list);
531 } else {
532 BUG_ON(i->head != &up->list);
533 i->head = NULL;
534 }
535
536 spin_unlock_irq(&i->lock);
537}
538
539static int serial_link_irq_chain(struct uart_sio_port *up)
540{
541 struct irq_info *i = irq_lists + up->port.irq;
542 int ret, irq_flags = 0;
543
544 spin_lock_irq(&i->lock);
545
546 if (i->head) {
547 list_add(&up->list, i->head);
548 spin_unlock_irq(&i->lock);
549
550 ret = 0;
551 } else {
552 INIT_LIST_HEAD(&up->list);
553 i->head = &up->list;
554 spin_unlock_irq(&i->lock);
555
556 ret = request_irq(up->port.irq, m32r_sio_interrupt,
557 irq_flags, "SIO0-RX", i);
558 ret |= request_irq(up->port.irq + 1, m32r_sio_interrupt,
559 irq_flags, "SIO0-TX", i);
560 if (ret < 0)
561 serial_do_unlink(i, up);
562 }
563
564 return ret;
565}
566
567static void serial_unlink_irq_chain(struct uart_sio_port *up)
568{
569 struct irq_info *i = irq_lists + up->port.irq;
570
571 BUG_ON(i->head == NULL);
572
573 if (list_empty(i->head)) {
574 free_irq(up->port.irq, i);
575 free_irq(up->port.irq + 1, i);
576 }
577
578 serial_do_unlink(i, up);
579}
580
581/*
582 * This function is used to handle ports that do not have an interrupt.
583 */
584static void m32r_sio_timeout(unsigned long data)
585{
586 struct uart_sio_port *up = (struct uart_sio_port *)data;
587 unsigned int timeout;
588 unsigned int sts;
589
590 sts = sio_in(up, SIOSTS);
591 if (sts & 0x5) {
592 spin_lock(&up->port.lock);
593 m32r_sio_handle_port(up, sts);
594 spin_unlock(&up->port.lock);
595 }
596
597 timeout = up->port.timeout;
598 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
599 mod_timer(&up->timer, jiffies + timeout);
600}
601
602static unsigned int m32r_sio_tx_empty(struct uart_port *port)
603{
604 struct uart_sio_port *up = (struct uart_sio_port *)port;
605 unsigned long flags;
606 unsigned int ret;
607
608 spin_lock_irqsave(&up->port.lock, flags);
609 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
610 spin_unlock_irqrestore(&up->port.lock, flags);
611
612 return ret;
613}
614
615static unsigned int m32r_sio_get_mctrl(struct uart_port *port)
616{
617 return 0;
618}
619
620static void m32r_sio_set_mctrl(struct uart_port *port, unsigned int mctrl)
621{
622
623}
624
625static void m32r_sio_break_ctl(struct uart_port *port, int break_state)
626{
627
628}
629
630static int m32r_sio_startup(struct uart_port *port)
631{
632 struct uart_sio_port *up = (struct uart_sio_port *)port;
633 int retval;
634
635 sio_init();
636
637 /*
638 * If the "interrupt" for this port doesn't correspond with any
639 * hardware interrupt, we use a timer-based system. The original
640 * driver used to do this with IRQ0.
641 */
642 if (!is_real_interrupt(up->port.irq)) {
643 unsigned int timeout = up->port.timeout;
644
645 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
646
647 up->timer.data = (unsigned long)up;
648 mod_timer(&up->timer, jiffies + timeout);
649 } else {
650 retval = serial_link_irq_chain(up);
651 if (retval)
652 return retval;
653 }
654
655 /*
656 * Finally, enable interrupts. Note: Modem status interrupts
657 * are set via set_termios(), which will be occurring imminently
658 * anyway, so we don't enable them here.
659 * - M32R_SIO: 0x0c
660 * - M32R_PLDSIO: 0x04
661 */
662 up->ier = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI;
663 sio_out(up, SIOTRCR, up->ier);
664
665 /*
666 * And clear the interrupt registers again for luck.
667 */
668 sio_reset();
669
670 return 0;
671}
672
673static void m32r_sio_shutdown(struct uart_port *port)
674{
675 struct uart_sio_port *up = (struct uart_sio_port *)port;
676
677 /*
678 * Disable interrupts from this port
679 */
680 up->ier = 0;
681 sio_out(up, SIOTRCR, 0);
682
683 /*
684 * Disable break condition and FIFOs
685 */
686
687 sio_init();
688
689 if (!is_real_interrupt(up->port.irq))
690 del_timer_sync(&up->timer);
691 else
692 serial_unlink_irq_chain(up);
693}
694
695static unsigned int m32r_sio_get_divisor(struct uart_port *port,
696 unsigned int baud)
697{
698 return uart_get_divisor(port, baud);
699}
700
701static void m32r_sio_set_termios(struct uart_port *port,
702 struct ktermios *termios, struct ktermios *old)
703{
704 struct uart_sio_port *up = (struct uart_sio_port *)port;
705 unsigned char cval = 0;
706 unsigned long flags;
707 unsigned int baud, quot;
708
709 switch (termios->c_cflag & CSIZE) {
710 case CS5:
711 cval = UART_LCR_WLEN5;
712 break;
713 case CS6:
714 cval = UART_LCR_WLEN6;
715 break;
716 case CS7:
717 cval = UART_LCR_WLEN7;
718 break;
719 default:
720 case CS8:
721 cval = UART_LCR_WLEN8;
722 break;
723 }
724
725 if (termios->c_cflag & CSTOPB)
726 cval |= UART_LCR_STOP;
727 if (termios->c_cflag & PARENB)
728 cval |= UART_LCR_PARITY;
729 if (!(termios->c_cflag & PARODD))
730 cval |= UART_LCR_EPAR;
731#ifdef CMSPAR
732 if (termios->c_cflag & CMSPAR)
733 cval |= UART_LCR_SPAR;
734#endif
735
736 /*
737 * Ask the core to calculate the divisor for us.
738 */
739#ifdef CONFIG_SERIAL_M32R_PLDSIO
740 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/4);
741#else
742 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
743#endif
744 quot = m32r_sio_get_divisor(port, baud);
745
746 /*
747 * Ok, we're now changing the port state. Do it with
748 * interrupts disabled.
749 */
750 spin_lock_irqsave(&up->port.lock, flags);
751
752 sio_set_baud_rate(baud);
753
754 /*
755 * Update the per-port timeout.
756 */
757 uart_update_timeout(port, termios->c_cflag, baud);
758
759 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
760 if (termios->c_iflag & INPCK)
761 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
762 if (termios->c_iflag & (BRKINT | PARMRK))
763 up->port.read_status_mask |= UART_LSR_BI;
764
765 /*
766 * Characteres to ignore
767 */
768 up->port.ignore_status_mask = 0;
769 if (termios->c_iflag & IGNPAR)
770 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
771 if (termios->c_iflag & IGNBRK) {
772 up->port.ignore_status_mask |= UART_LSR_BI;
773 /*
774 * If we're ignoring parity and break indicators,
775 * ignore overruns too (for real raw support).
776 */
777 if (termios->c_iflag & IGNPAR)
778 up->port.ignore_status_mask |= UART_LSR_OE;
779 }
780
781 /*
782 * ignore all characters if CREAD is not set
783 */
784 if ((termios->c_cflag & CREAD) == 0)
785 up->port.ignore_status_mask |= UART_LSR_DR;
786
787 /*
788 * CTS flow control flag and modem status interrupts
789 */
790 up->ier &= ~UART_IER_MSI;
791 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
792 up->ier |= UART_IER_MSI;
793
794 serial_out(up, UART_IER, up->ier);
795
796 up->lcr = cval; /* Save LCR */
797 spin_unlock_irqrestore(&up->port.lock, flags);
798}
799
800static void m32r_sio_pm(struct uart_port *port, unsigned int state,
801 unsigned int oldstate)
802{
803 struct uart_sio_port *up = (struct uart_sio_port *)port;
804
805 if (up->pm)
806 up->pm(port, state, oldstate);
807}
808
809/*
810 * Resource handling. This is complicated by the fact that resources
811 * depend on the port type. Maybe we should be claiming the standard
812 * 8250 ports, and then trying to get other resources as necessary?
813 */
814static int
815m32r_sio_request_std_resource(struct uart_sio_port *up, struct resource **res)
816{
817 unsigned int size = 8 << up->port.regshift;
818#ifndef CONFIG_SERIAL_M32R_PLDSIO
819 unsigned long start;
820#endif
821 int ret = 0;
822
823 switch (up->port.iotype) {
824 case UPIO_MEM:
825 if (up->port.mapbase) {
826#ifdef CONFIG_SERIAL_M32R_PLDSIO
827 *res = request_mem_region(up->port.mapbase, size, "serial");
828#else
829 start = up->port.mapbase;
830 *res = request_mem_region(start, size, "serial");
831#endif
832 if (!*res)
833 ret = -EBUSY;
834 }
835 break;
836
837 case UPIO_PORT:
838 *res = request_region(up->port.iobase, size, "serial");
839 if (!*res)
840 ret = -EBUSY;
841 break;
842 }
843 return ret;
844}
845
846static void m32r_sio_release_port(struct uart_port *port)
847{
848 struct uart_sio_port *up = (struct uart_sio_port *)port;
849 unsigned long start, offset = 0, size = 0;
850
851 size <<= up->port.regshift;
852
853 switch (up->port.iotype) {
854 case UPIO_MEM:
855 if (up->port.mapbase) {
856 /*
857 * Unmap the area.
858 */
859 iounmap(up->port.membase);
860 up->port.membase = NULL;
861
862 start = up->port.mapbase;
863
864 if (size)
865 release_mem_region(start + offset, size);
866 release_mem_region(start, 8 << up->port.regshift);
867 }
868 break;
869
870 case UPIO_PORT:
871 start = up->port.iobase;
872
873 if (size)
874 release_region(start + offset, size);
875 release_region(start + offset, 8 << up->port.regshift);
876 break;
877
878 default:
879 break;
880 }
881}
882
883static int m32r_sio_request_port(struct uart_port *port)
884{
885 struct uart_sio_port *up = (struct uart_sio_port *)port;
886 struct resource *res = NULL;
887 int ret = 0;
888
889 ret = m32r_sio_request_std_resource(up, &res);
890
891 /*
892 * If we have a mapbase, then request that as well.
893 */
894 if (ret == 0 && up->port.flags & UPF_IOREMAP) {
895 int size = res->end - res->start + 1;
896
897 up->port.membase = ioremap(up->port.mapbase, size);
898 if (!up->port.membase)
899 ret = -ENOMEM;
900 }
901
902 if (ret < 0) {
903 if (res)
904 release_resource(res);
905 }
906
907 return ret;
908}
909
910static void m32r_sio_config_port(struct uart_port *port, int flags)
911{
912 struct uart_sio_port *up = (struct uart_sio_port *)port;
913
914 spin_lock_irqsave(&up->port.lock, flags);
915
916 up->port.type = (PORT_M32R_SIO - PORT_M32R_BASE + 1);
917 up->port.fifosize = uart_config[up->port.type].dfl_xmit_fifo_size;
918
919 spin_unlock_irqrestore(&up->port.lock, flags);
920}
921
922static int
923m32r_sio_verify_port(struct uart_port *port, struct serial_struct *ser)
924{
925 if (ser->irq >= nr_irqs || ser->irq < 0 ||
926 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
927 ser->type >= ARRAY_SIZE(uart_config))
928 return -EINVAL;
929 return 0;
930}
931
932static const char *
933m32r_sio_type(struct uart_port *port)
934{
935 int type = port->type;
936
937 if (type >= ARRAY_SIZE(uart_config))
938 type = 0;
939 return uart_config[type].name;
940}
941
942static struct uart_ops m32r_sio_pops = {
943 .tx_empty = m32r_sio_tx_empty,
944 .set_mctrl = m32r_sio_set_mctrl,
945 .get_mctrl = m32r_sio_get_mctrl,
946 .stop_tx = m32r_sio_stop_tx,
947 .start_tx = m32r_sio_start_tx,
948 .stop_rx = m32r_sio_stop_rx,
949 .enable_ms = m32r_sio_enable_ms,
950 .break_ctl = m32r_sio_break_ctl,
951 .startup = m32r_sio_startup,
952 .shutdown = m32r_sio_shutdown,
953 .set_termios = m32r_sio_set_termios,
954 .pm = m32r_sio_pm,
955 .type = m32r_sio_type,
956 .release_port = m32r_sio_release_port,
957 .request_port = m32r_sio_request_port,
958 .config_port = m32r_sio_config_port,
959 .verify_port = m32r_sio_verify_port,
960};
961
962static struct uart_sio_port m32r_sio_ports[UART_NR];
963
964static void __init m32r_sio_init_ports(void)
965{
966 struct uart_sio_port *up;
967 static int first = 1;
968 int i;
969
970 if (!first)
971 return;
972 first = 0;
973
974 for (i = 0, up = m32r_sio_ports; i < ARRAY_SIZE(old_serial_port);
975 i++, up++) {
976 up->port.iobase = old_serial_port[i].port;
977 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
978 up->port.uartclk = old_serial_port[i].baud_base * 16;
979 up->port.flags = old_serial_port[i].flags;
980 up->port.membase = old_serial_port[i].iomem_base;
981 up->port.iotype = old_serial_port[i].io_type;
982 up->port.regshift = old_serial_port[i].iomem_reg_shift;
983 up->port.ops = &m32r_sio_pops;
984 }
985}
986
987static void __init m32r_sio_register_ports(struct uart_driver *drv)
988{
989 int i;
990
991 m32r_sio_init_ports();
992
993 for (i = 0; i < UART_NR; i++) {
994 struct uart_sio_port *up = &m32r_sio_ports[i];
995
996 up->port.line = i;
997 up->port.ops = &m32r_sio_pops;
998 init_timer(&up->timer);
999 up->timer.function = m32r_sio_timeout;
1000
1001 /*
1002 * ALPHA_KLUDGE_MCR needs to be killed.
1003 */
1004 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
1005 up->mcr_force = ALPHA_KLUDGE_MCR;
1006
1007 uart_add_one_port(drv, &up->port);
1008 }
1009}
1010
1011#ifdef CONFIG_SERIAL_M32R_SIO_CONSOLE
1012
1013/*
1014 * Wait for transmitter & holding register to empty
1015 */
1016static inline void wait_for_xmitr(struct uart_sio_port *up)
1017{
1018 unsigned int status, tmout = 10000;
1019
1020 /* Wait up to 10ms for the character(s) to be sent. */
1021 do {
1022 status = sio_in(up, SIOSTS);
1023
1024 if (--tmout == 0)
1025 break;
1026 udelay(1);
1027 } while ((status & UART_EMPTY) != UART_EMPTY);
1028
1029 /* Wait up to 1s for flow control if necessary */
1030 if (up->port.flags & UPF_CONS_FLOW) {
1031 tmout = 1000000;
1032 while (--tmout)
1033 udelay(1);
1034 }
1035}
1036
1037static void m32r_sio_console_putchar(struct uart_port *port, int ch)
1038{
1039 struct uart_sio_port *up = (struct uart_sio_port *)port;
1040
1041 wait_for_xmitr(up);
1042 sio_out(up, SIOTXB, ch);
1043}
1044
1045/*
1046 * Print a string to the serial port trying not to disturb
1047 * any possible real use of the port...
1048 *
1049 * The console_lock must be held when we get here.
1050 */
1051static void m32r_sio_console_write(struct console *co, const char *s,
1052 unsigned int count)
1053{
1054 struct uart_sio_port *up = &m32r_sio_ports[co->index];
1055 unsigned int ier;
1056
1057 /*
1058 * First save the UER then disable the interrupts
1059 */
1060 ier = sio_in(up, SIOTRCR);
1061 sio_out(up, SIOTRCR, 0);
1062
1063 uart_console_write(&up->port, s, count, m32r_sio_console_putchar);
1064
1065 /*
1066 * Finally, wait for transmitter to become empty
1067 * and restore the IER
1068 */
1069 wait_for_xmitr(up);
1070 sio_out(up, SIOTRCR, ier);
1071}
1072
1073static int __init m32r_sio_console_setup(struct console *co, char *options)
1074{
1075 struct uart_port *port;
1076 int baud = 9600;
1077 int bits = 8;
1078 int parity = 'n';
1079 int flow = 'n';
1080
1081 /*
1082 * Check whether an invalid uart number has been specified, and
1083 * if so, search for the first available port that does have
1084 * console support.
1085 */
1086 if (co->index >= UART_NR)
1087 co->index = 0;
1088 port = &m32r_sio_ports[co->index].port;
1089
1090 /*
1091 * Temporary fix.
1092 */
1093 spin_lock_init(&port->lock);
1094
1095 if (options)
1096 uart_parse_options(options, &baud, &parity, &bits, &flow);
1097
1098 return uart_set_options(port, co, baud, parity, bits, flow);
1099}
1100
1101static struct uart_driver m32r_sio_reg;
1102static struct console m32r_sio_console = {
1103 .name = "ttyS",
1104 .write = m32r_sio_console_write,
1105 .device = uart_console_device,
1106 .setup = m32r_sio_console_setup,
1107 .flags = CON_PRINTBUFFER,
1108 .index = -1,
1109 .data = &m32r_sio_reg,
1110};
1111
1112static int __init m32r_sio_console_init(void)
1113{
1114 sio_reset();
1115 sio_init();
1116 m32r_sio_init_ports();
1117 register_console(&m32r_sio_console);
1118 return 0;
1119}
1120console_initcall(m32r_sio_console_init);
1121
1122#define M32R_SIO_CONSOLE &m32r_sio_console
1123#else
1124#define M32R_SIO_CONSOLE NULL
1125#endif
1126
1127static struct uart_driver m32r_sio_reg = {
1128 .owner = THIS_MODULE,
1129 .driver_name = "sio",
1130 .dev_name = "ttyS",
1131 .major = TTY_MAJOR,
1132 .minor = 64,
1133 .nr = UART_NR,
1134 .cons = M32R_SIO_CONSOLE,
1135};
1136
1137/**
1138 * m32r_sio_suspend_port - suspend one serial port
1139 * @line: serial line number
1140 *
1141 * Suspend one serial port.
1142 */
1143void m32r_sio_suspend_port(int line)
1144{
1145 uart_suspend_port(&m32r_sio_reg, &m32r_sio_ports[line].port);
1146}
1147
1148/**
1149 * m32r_sio_resume_port - resume one serial port
1150 * @line: serial line number
1151 *
1152 * Resume one serial port.
1153 */
1154void m32r_sio_resume_port(int line)
1155{
1156 uart_resume_port(&m32r_sio_reg, &m32r_sio_ports[line].port);
1157}
1158
1159static int __init m32r_sio_init(void)
1160{
1161 int ret, i;
1162
1163 printk(KERN_INFO "Serial: M32R SIO driver\n");
1164
1165 for (i = 0; i < nr_irqs; i++)
1166 spin_lock_init(&irq_lists[i].lock);
1167
1168 ret = uart_register_driver(&m32r_sio_reg);
1169 if (ret >= 0)
1170 m32r_sio_register_ports(&m32r_sio_reg);
1171
1172 return ret;
1173}
1174
1175static void __exit m32r_sio_exit(void)
1176{
1177 int i;
1178
1179 for (i = 0; i < UART_NR; i++)
1180 uart_remove_one_port(&m32r_sio_reg, &m32r_sio_ports[i].port);
1181
1182 uart_unregister_driver(&m32r_sio_reg);
1183}
1184
1185module_init(m32r_sio_init);
1186module_exit(m32r_sio_exit);
1187
1188EXPORT_SYMBOL(m32r_sio_suspend_port);
1189EXPORT_SYMBOL(m32r_sio_resume_port);
1190
1191MODULE_LICENSE("GPL");
1192MODULE_DESCRIPTION("Generic M32R SIO serial driver");
diff --git a/drivers/serial/m32r_sio.h b/drivers/serial/m32r_sio.h
deleted file mode 100644
index e9b7e11793b1..000000000000
--- a/drivers/serial/m32r_sio.h
+++ /dev/null
@@ -1,48 +0,0 @@
1/*
2 * m32r_sio.h
3 *
4 * Driver for M32R serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 * Based on drivers/serial/8250.h.
8 *
9 * Copyright (C) 2001 Russell King.
10 * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 */
17
18
19struct m32r_sio_probe {
20 struct module *owner;
21 int (*pci_init_one)(struct pci_dev *dev);
22 void (*pci_remove_one)(struct pci_dev *dev);
23 void (*pnp_init)(void);
24};
25
26int m32r_sio_register_probe(struct m32r_sio_probe *probe);
27void m32r_sio_unregister_probe(struct m32r_sio_probe *probe);
28void m32r_sio_get_irq_map(unsigned int *map);
29void m32r_sio_suspend_port(int line);
30void m32r_sio_resume_port(int line);
31
32struct old_serial_port {
33 unsigned int uart;
34 unsigned int baud_base;
35 unsigned int port;
36 unsigned int irq;
37 unsigned int flags;
38 unsigned char io_type;
39 unsigned char __iomem *iomem_base;
40 unsigned short iomem_reg_shift;
41};
42
43#define _INLINE_ inline
44
45#define PROBE_RSA (1 << 0)
46#define PROBE_ANY (~0)
47
48#define HIGH_BITS_OFFSET ((sizeof(long)-sizeof(int))*8)
diff --git a/drivers/serial/m32r_sio_reg.h b/drivers/serial/m32r_sio_reg.h
deleted file mode 100644
index 4671473793e3..000000000000
--- a/drivers/serial/m32r_sio_reg.h
+++ /dev/null
@@ -1,152 +0,0 @@
1/*
2 * m32r_sio_reg.h
3 *
4 * Copyright (C) 1992, 1994 by Theodore Ts'o.
5 * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
6 *
7 * Redistribution of this file is permitted under the terms of the GNU
8 * Public License (GPL)
9 *
10 * These are the UART port assignments, expressed as offsets from the base
11 * register. These assignments should hold for any serial port based on
12 * a 8250, 16450, or 16550(A).
13 */
14
15#ifndef _M32R_SIO_REG_H
16#define _M32R_SIO_REG_H
17
18
19#ifdef CONFIG_SERIAL_M32R_PLDSIO
20
21#define SIOCR 0x000
22#define SIOMOD0 0x002
23#define SIOMOD1 0x004
24#define SIOSTS 0x006
25#define SIOTRCR 0x008
26#define SIOBAUR 0x00a
27// #define SIORBAUR 0x018
28#define SIOTXB 0x00c
29#define SIORXB 0x00e
30
31#define UART_RX ((unsigned long) PLD_ESIO0RXB)
32 /* In: Receive buffer (DLAB=0) */
33#define UART_TX ((unsigned long) PLD_ESIO0TXB)
34 /* Out: Transmit buffer (DLAB=0) */
35#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
36#define UART_TRG 0 /* (LCR=BF) FCTR bit 7 selects Rx or Tx
37 * In: Fifo count
38 * Out: Fifo custom trigger levels
39 * XR16C85x only */
40
41#define UART_DLM 0 /* Out: Divisor Latch High (DLAB=1) */
42#define UART_IER ((unsigned long) PLD_ESIO0INTCR)
43 /* Out: Interrupt Enable Register */
44#define UART_FCTR 0 /* (LCR=BF) Feature Control Register
45 * XR16C85x only */
46
47#define UART_IIR 0 /* In: Interrupt ID Register */
48#define UART_FCR 0 /* Out: FIFO Control Register */
49#define UART_EFR 0 /* I/O: Extended Features Register */
50 /* (DLAB=1, 16C660 only) */
51
52#define UART_LCR 0 /* Out: Line Control Register */
53#define UART_MCR 0 /* Out: Modem Control Register */
54#define UART_LSR ((unsigned long) PLD_ESIO0STS)
55 /* In: Line Status Register */
56#define UART_MSR 0 /* In: Modem Status Register */
57#define UART_SCR 0 /* I/O: Scratch Register */
58#define UART_EMSR 0 /* (LCR=BF) Extended Mode Select Register
59 * FCTR bit 6 selects SCR or EMSR
60 * XR16c85x only */
61
62#else /* not CONFIG_SERIAL_M32R_PLDSIO */
63
64#define SIOCR 0x000
65#define SIOMOD0 0x004
66#define SIOMOD1 0x008
67#define SIOSTS 0x00c
68#define SIOTRCR 0x010
69#define SIOBAUR 0x014
70#define SIORBAUR 0x018
71#define SIOTXB 0x01c
72#define SIORXB 0x020
73
74#define UART_RX M32R_SIO0_RXB_PORTL /* In: Receive buffer (DLAB=0) */
75#define UART_TX M32R_SIO0_TXB_PORTL /* Out: Transmit buffer (DLAB=0) */
76#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
77#define UART_TRG 0 /* (LCR=BF) FCTR bit 7 selects Rx or Tx
78 * In: Fifo count
79 * Out: Fifo custom trigger levels
80 * XR16C85x only */
81
82#define UART_DLM 0 /* Out: Divisor Latch High (DLAB=1) */
83#define UART_IER M32R_SIO0_TRCR_PORTL /* Out: Interrupt Enable Register */
84#define UART_FCTR 0 /* (LCR=BF) Feature Control Register
85 * XR16C85x only */
86
87#define UART_IIR 0 /* In: Interrupt ID Register */
88#define UART_FCR 0 /* Out: FIFO Control Register */
89#define UART_EFR 0 /* I/O: Extended Features Register */
90 /* (DLAB=1, 16C660 only) */
91
92#define UART_LCR 0 /* Out: Line Control Register */
93#define UART_MCR 0 /* Out: Modem Control Register */
94#define UART_LSR M32R_SIO0_STS_PORTL /* In: Line Status Register */
95#define UART_MSR 0 /* In: Modem Status Register */
96#define UART_SCR 0 /* I/O: Scratch Register */
97#define UART_EMSR 0 /* (LCR=BF) Extended Mode Select Register
98 * FCTR bit 6 selects SCR or EMSR
99 * XR16c85x only */
100
101#endif /* CONFIG_SERIAL_M32R_PLDSIO */
102
103#define UART_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
104
105/*
106 * These are the definitions for the Line Control Register
107 *
108 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
109 * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
110 */
111#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
112#define UART_LCR_SBC 0x40 /* Set break control */
113#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
114#define UART_LCR_EPAR 0x10 /* Even parity select */
115#define UART_LCR_PARITY 0x08 /* Parity Enable */
116#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
117#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
118#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
119#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
120#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
121
122/*
123 * These are the definitions for the Line Status Register
124 */
125#define UART_LSR_TEMT 0x02 /* Transmitter empty */
126#define UART_LSR_THRE 0x01 /* Transmit-hold-register empty */
127#define UART_LSR_BI 0x00 /* Break interrupt indicator */
128#define UART_LSR_FE 0x80 /* Frame error indicator */
129#define UART_LSR_PE 0x40 /* Parity error indicator */
130#define UART_LSR_OE 0x20 /* Overrun error indicator */
131#define UART_LSR_DR 0x04 /* Receiver data ready */
132
133/*
134 * These are the definitions for the Interrupt Identification Register
135 */
136#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
137#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
138
139#define UART_IIR_MSI 0x00 /* Modem status interrupt */
140#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
141#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
142#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
143
144/*
145 * These are the definitions for the Interrupt Enable Register
146 */
147#define UART_IER_MSI 0x00 /* Enable Modem status interrupt */
148#define UART_IER_RLSI 0x08 /* Enable receiver line status interrupt */
149#define UART_IER_THRI 0x03 /* Enable Transmitter holding register int. */
150#define UART_IER_RDI 0x04 /* Enable receiver data interrupt */
151
152#endif /* _M32R_SIO_REG_H */
diff --git a/drivers/serial/max3100.c b/drivers/serial/max3100.c
deleted file mode 100644
index beb1afa27d8d..000000000000
--- a/drivers/serial/max3100.c
+++ /dev/null
@@ -1,926 +0,0 @@
1/*
2 *
3 * Copyright (C) 2008 Christian Pellegrin <chripell@evolware.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 *
11 * Notes: the MAX3100 doesn't provide an interrupt on CTS so we have
12 * to use polling for flow control. TX empty IRQ is unusable, since
13 * writing conf clears FIFO buffer and we cannot have this interrupt
14 * always asking us for attention.
15 *
16 * Example platform data:
17
18 static struct plat_max3100 max3100_plat_data = {
19 .loopback = 0,
20 .crystal = 0,
21 .poll_time = 100,
22 };
23
24 static struct spi_board_info spi_board_info[] = {
25 {
26 .modalias = "max3100",
27 .platform_data = &max3100_plat_data,
28 .irq = IRQ_EINT12,
29 .max_speed_hz = 5*1000*1000,
30 .chip_select = 0,
31 },
32 };
33
34 * The initial minor number is 209 in the low-density serial port:
35 * mknod /dev/ttyMAX0 c 204 209
36 */
37
38#define MAX3100_MAJOR 204
39#define MAX3100_MINOR 209
40/* 4 MAX3100s should be enough for everyone */
41#define MAX_MAX3100 4
42
43#include <linux/delay.h>
44#include <linux/slab.h>
45#include <linux/device.h>
46#include <linux/serial_core.h>
47#include <linux/serial.h>
48#include <linux/spi/spi.h>
49#include <linux/freezer.h>
50
51#include <linux/serial_max3100.h>
52
53#define MAX3100_C (1<<14)
54#define MAX3100_D (0<<14)
55#define MAX3100_W (1<<15)
56#define MAX3100_RX (0<<15)
57
58#define MAX3100_WC (MAX3100_W | MAX3100_C)
59#define MAX3100_RC (MAX3100_RX | MAX3100_C)
60#define MAX3100_WD (MAX3100_W | MAX3100_D)
61#define MAX3100_RD (MAX3100_RX | MAX3100_D)
62#define MAX3100_CMD (3 << 14)
63
64#define MAX3100_T (1<<14)
65#define MAX3100_R (1<<15)
66
67#define MAX3100_FEN (1<<13)
68#define MAX3100_SHDN (1<<12)
69#define MAX3100_TM (1<<11)
70#define MAX3100_RM (1<<10)
71#define MAX3100_PM (1<<9)
72#define MAX3100_RAM (1<<8)
73#define MAX3100_IR (1<<7)
74#define MAX3100_ST (1<<6)
75#define MAX3100_PE (1<<5)
76#define MAX3100_L (1<<4)
77#define MAX3100_BAUD (0xf)
78
79#define MAX3100_TE (1<<10)
80#define MAX3100_RAFE (1<<10)
81#define MAX3100_RTS (1<<9)
82#define MAX3100_CTS (1<<9)
83#define MAX3100_PT (1<<8)
84#define MAX3100_DATA (0xff)
85
86#define MAX3100_RT (MAX3100_R | MAX3100_T)
87#define MAX3100_RTC (MAX3100_RT | MAX3100_CTS | MAX3100_RAFE)
88
89/* the following simulate a status reg for ignore_status_mask */
90#define MAX3100_STATUS_PE 1
91#define MAX3100_STATUS_FE 2
92#define MAX3100_STATUS_OE 4
93
94struct max3100_port {
95 struct uart_port port;
96 struct spi_device *spi;
97
98 int cts; /* last CTS received for flow ctrl */
99 int tx_empty; /* last TX empty bit */
100
101 spinlock_t conf_lock; /* shared data */
102 int conf_commit; /* need to make changes */
103 int conf; /* configuration for the MAX31000
104 * (bits 0-7, bits 8-11 are irqs) */
105 int rts_commit; /* need to change rts */
106 int rts; /* rts status */
107 int baud; /* current baud rate */
108
109 int parity; /* keeps track if we should send parity */
110#define MAX3100_PARITY_ON 1
111#define MAX3100_PARITY_ODD 2
112#define MAX3100_7BIT 4
113 int rx_enabled; /* if we should rx chars */
114
115 int irq; /* irq assigned to the max3100 */
116
117 int minor; /* minor number */
118 int crystal; /* 1 if 3.6864Mhz crystal 0 for 1.8432 */
119 int loopback; /* 1 if we are in loopback mode */
120
121 /* for handling irqs: need workqueue since we do spi_sync */
122 struct workqueue_struct *workqueue;
123 struct work_struct work;
124 /* set to 1 to make the workhandler exit as soon as possible */
125 int force_end_work;
126 /* need to know we are suspending to avoid deadlock on workqueue */
127 int suspending;
128
129 /* hook for suspending MAX3100 via dedicated pin */
130 void (*max3100_hw_suspend) (int suspend);
131
132 /* poll time (in ms) for ctrl lines */
133 int poll_time;
134 /* and its timer */
135 struct timer_list timer;
136};
137
138static struct max3100_port *max3100s[MAX_MAX3100]; /* the chips */
139static DEFINE_MUTEX(max3100s_lock); /* race on probe */
140
141static int max3100_do_parity(struct max3100_port *s, u16 c)
142{
143 int parity;
144
145 if (s->parity & MAX3100_PARITY_ODD)
146 parity = 1;
147 else
148 parity = 0;
149
150 if (s->parity & MAX3100_7BIT)
151 c &= 0x7f;
152 else
153 c &= 0xff;
154
155 parity = parity ^ (hweight8(c) & 1);
156 return parity;
157}
158
159static int max3100_check_parity(struct max3100_port *s, u16 c)
160{
161 return max3100_do_parity(s, c) == ((c >> 8) & 1);
162}
163
164static void max3100_calc_parity(struct max3100_port *s, u16 *c)
165{
166 if (s->parity & MAX3100_7BIT)
167 *c &= 0x7f;
168 else
169 *c &= 0xff;
170
171 if (s->parity & MAX3100_PARITY_ON)
172 *c |= max3100_do_parity(s, *c) << 8;
173}
174
175static void max3100_work(struct work_struct *w);
176
177static void max3100_dowork(struct max3100_port *s)
178{
179 if (!s->force_end_work && !work_pending(&s->work) &&
180 !freezing(current) && !s->suspending)
181 queue_work(s->workqueue, &s->work);
182}
183
184static void max3100_timeout(unsigned long data)
185{
186 struct max3100_port *s = (struct max3100_port *)data;
187
188 if (s->port.state) {
189 max3100_dowork(s);
190 mod_timer(&s->timer, jiffies + s->poll_time);
191 }
192}
193
194static int max3100_sr(struct max3100_port *s, u16 tx, u16 *rx)
195{
196 struct spi_message message;
197 u16 etx, erx;
198 int status;
199 struct spi_transfer tran = {
200 .tx_buf = &etx,
201 .rx_buf = &erx,
202 .len = 2,
203 };
204
205 etx = cpu_to_be16(tx);
206 spi_message_init(&message);
207 spi_message_add_tail(&tran, &message);
208 status = spi_sync(s->spi, &message);
209 if (status) {
210 dev_warn(&s->spi->dev, "error while calling spi_sync\n");
211 return -EIO;
212 }
213 *rx = be16_to_cpu(erx);
214 s->tx_empty = (*rx & MAX3100_T) > 0;
215 dev_dbg(&s->spi->dev, "%04x - %04x\n", tx, *rx);
216 return 0;
217}
218
219static int max3100_handlerx(struct max3100_port *s, u16 rx)
220{
221 unsigned int ch, flg, status = 0;
222 int ret = 0, cts;
223
224 if (rx & MAX3100_R && s->rx_enabled) {
225 dev_dbg(&s->spi->dev, "%s\n", __func__);
226 ch = rx & (s->parity & MAX3100_7BIT ? 0x7f : 0xff);
227 if (rx & MAX3100_RAFE) {
228 s->port.icount.frame++;
229 flg = TTY_FRAME;
230 status |= MAX3100_STATUS_FE;
231 } else {
232 if (s->parity & MAX3100_PARITY_ON) {
233 if (max3100_check_parity(s, rx)) {
234 s->port.icount.rx++;
235 flg = TTY_NORMAL;
236 } else {
237 s->port.icount.parity++;
238 flg = TTY_PARITY;
239 status |= MAX3100_STATUS_PE;
240 }
241 } else {
242 s->port.icount.rx++;
243 flg = TTY_NORMAL;
244 }
245 }
246 uart_insert_char(&s->port, status, MAX3100_STATUS_OE, ch, flg);
247 ret = 1;
248 }
249
250 cts = (rx & MAX3100_CTS) > 0;
251 if (s->cts != cts) {
252 s->cts = cts;
253 uart_handle_cts_change(&s->port, cts ? TIOCM_CTS : 0);
254 }
255
256 return ret;
257}
258
259static void max3100_work(struct work_struct *w)
260{
261 struct max3100_port *s = container_of(w, struct max3100_port, work);
262 int rxchars;
263 u16 tx, rx;
264 int conf, cconf, rts, crts;
265 struct circ_buf *xmit = &s->port.state->xmit;
266
267 dev_dbg(&s->spi->dev, "%s\n", __func__);
268
269 rxchars = 0;
270 do {
271 spin_lock(&s->conf_lock);
272 conf = s->conf;
273 cconf = s->conf_commit;
274 s->conf_commit = 0;
275 rts = s->rts;
276 crts = s->rts_commit;
277 s->rts_commit = 0;
278 spin_unlock(&s->conf_lock);
279 if (cconf)
280 max3100_sr(s, MAX3100_WC | conf, &rx);
281 if (crts) {
282 max3100_sr(s, MAX3100_WD | MAX3100_TE |
283 (s->rts ? MAX3100_RTS : 0), &rx);
284 rxchars += max3100_handlerx(s, rx);
285 }
286
287 max3100_sr(s, MAX3100_RD, &rx);
288 rxchars += max3100_handlerx(s, rx);
289
290 if (rx & MAX3100_T) {
291 tx = 0xffff;
292 if (s->port.x_char) {
293 tx = s->port.x_char;
294 s->port.icount.tx++;
295 s->port.x_char = 0;
296 } else if (!uart_circ_empty(xmit) &&
297 !uart_tx_stopped(&s->port)) {
298 tx = xmit->buf[xmit->tail];
299 xmit->tail = (xmit->tail + 1) &
300 (UART_XMIT_SIZE - 1);
301 s->port.icount.tx++;
302 }
303 if (tx != 0xffff) {
304 max3100_calc_parity(s, &tx);
305 tx |= MAX3100_WD | (s->rts ? MAX3100_RTS : 0);
306 max3100_sr(s, tx, &rx);
307 rxchars += max3100_handlerx(s, rx);
308 }
309 }
310
311 if (rxchars > 16 && s->port.state->port.tty != NULL) {
312 tty_flip_buffer_push(s->port.state->port.tty);
313 rxchars = 0;
314 }
315 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
316 uart_write_wakeup(&s->port);
317
318 } while (!s->force_end_work &&
319 !freezing(current) &&
320 ((rx & MAX3100_R) ||
321 (!uart_circ_empty(xmit) &&
322 !uart_tx_stopped(&s->port))));
323
324 if (rxchars > 0 && s->port.state->port.tty != NULL)
325 tty_flip_buffer_push(s->port.state->port.tty);
326}
327
328static irqreturn_t max3100_irq(int irqno, void *dev_id)
329{
330 struct max3100_port *s = dev_id;
331
332 dev_dbg(&s->spi->dev, "%s\n", __func__);
333
334 max3100_dowork(s);
335 return IRQ_HANDLED;
336}
337
338static void max3100_enable_ms(struct uart_port *port)
339{
340 struct max3100_port *s = container_of(port,
341 struct max3100_port,
342 port);
343
344 if (s->poll_time > 0)
345 mod_timer(&s->timer, jiffies);
346 dev_dbg(&s->spi->dev, "%s\n", __func__);
347}
348
349static void max3100_start_tx(struct uart_port *port)
350{
351 struct max3100_port *s = container_of(port,
352 struct max3100_port,
353 port);
354
355 dev_dbg(&s->spi->dev, "%s\n", __func__);
356
357 max3100_dowork(s);
358}
359
360static void max3100_stop_rx(struct uart_port *port)
361{
362 struct max3100_port *s = container_of(port,
363 struct max3100_port,
364 port);
365
366 dev_dbg(&s->spi->dev, "%s\n", __func__);
367
368 s->rx_enabled = 0;
369 spin_lock(&s->conf_lock);
370 s->conf &= ~MAX3100_RM;
371 s->conf_commit = 1;
372 spin_unlock(&s->conf_lock);
373 max3100_dowork(s);
374}
375
376static unsigned int max3100_tx_empty(struct uart_port *port)
377{
378 struct max3100_port *s = container_of(port,
379 struct max3100_port,
380 port);
381
382 dev_dbg(&s->spi->dev, "%s\n", __func__);
383
384 /* may not be truly up-to-date */
385 max3100_dowork(s);
386 return s->tx_empty;
387}
388
389static unsigned int max3100_get_mctrl(struct uart_port *port)
390{
391 struct max3100_port *s = container_of(port,
392 struct max3100_port,
393 port);
394
395 dev_dbg(&s->spi->dev, "%s\n", __func__);
396
397 /* may not be truly up-to-date */
398 max3100_dowork(s);
399 /* always assert DCD and DSR since these lines are not wired */
400 return (s->cts ? TIOCM_CTS : 0) | TIOCM_DSR | TIOCM_CAR;
401}
402
403static void max3100_set_mctrl(struct uart_port *port, unsigned int mctrl)
404{
405 struct max3100_port *s = container_of(port,
406 struct max3100_port,
407 port);
408 int rts;
409
410 dev_dbg(&s->spi->dev, "%s\n", __func__);
411
412 rts = (mctrl & TIOCM_RTS) > 0;
413
414 spin_lock(&s->conf_lock);
415 if (s->rts != rts) {
416 s->rts = rts;
417 s->rts_commit = 1;
418 max3100_dowork(s);
419 }
420 spin_unlock(&s->conf_lock);
421}
422
423static void
424max3100_set_termios(struct uart_port *port, struct ktermios *termios,
425 struct ktermios *old)
426{
427 struct max3100_port *s = container_of(port,
428 struct max3100_port,
429 port);
430 int baud = 0;
431 unsigned cflag;
432 u32 param_new, param_mask, parity = 0;
433
434 dev_dbg(&s->spi->dev, "%s\n", __func__);
435
436 cflag = termios->c_cflag;
437 param_new = 0;
438 param_mask = 0;
439
440 baud = tty_termios_baud_rate(termios);
441 param_new = s->conf & MAX3100_BAUD;
442 switch (baud) {
443 case 300:
444 if (s->crystal)
445 baud = s->baud;
446 else
447 param_new = 15;
448 break;
449 case 600:
450 param_new = 14 + s->crystal;
451 break;
452 case 1200:
453 param_new = 13 + s->crystal;
454 break;
455 case 2400:
456 param_new = 12 + s->crystal;
457 break;
458 case 4800:
459 param_new = 11 + s->crystal;
460 break;
461 case 9600:
462 param_new = 10 + s->crystal;
463 break;
464 case 19200:
465 param_new = 9 + s->crystal;
466 break;
467 case 38400:
468 param_new = 8 + s->crystal;
469 break;
470 case 57600:
471 param_new = 1 + s->crystal;
472 break;
473 case 115200:
474 param_new = 0 + s->crystal;
475 break;
476 case 230400:
477 if (s->crystal)
478 param_new = 0;
479 else
480 baud = s->baud;
481 break;
482 default:
483 baud = s->baud;
484 }
485 tty_termios_encode_baud_rate(termios, baud, baud);
486 s->baud = baud;
487 param_mask |= MAX3100_BAUD;
488
489 if ((cflag & CSIZE) == CS8) {
490 param_new &= ~MAX3100_L;
491 parity &= ~MAX3100_7BIT;
492 } else {
493 param_new |= MAX3100_L;
494 parity |= MAX3100_7BIT;
495 cflag = (cflag & ~CSIZE) | CS7;
496 }
497 param_mask |= MAX3100_L;
498
499 if (cflag & CSTOPB)
500 param_new |= MAX3100_ST;
501 else
502 param_new &= ~MAX3100_ST;
503 param_mask |= MAX3100_ST;
504
505 if (cflag & PARENB) {
506 param_new |= MAX3100_PE;
507 parity |= MAX3100_PARITY_ON;
508 } else {
509 param_new &= ~MAX3100_PE;
510 parity &= ~MAX3100_PARITY_ON;
511 }
512 param_mask |= MAX3100_PE;
513
514 if (cflag & PARODD)
515 parity |= MAX3100_PARITY_ODD;
516 else
517 parity &= ~MAX3100_PARITY_ODD;
518
519 /* mask termios capabilities we don't support */
520 cflag &= ~CMSPAR;
521 termios->c_cflag = cflag;
522
523 s->port.ignore_status_mask = 0;
524 if (termios->c_iflag & IGNPAR)
525 s->port.ignore_status_mask |=
526 MAX3100_STATUS_PE | MAX3100_STATUS_FE |
527 MAX3100_STATUS_OE;
528
529 /* we are sending char from a workqueue so enable */
530 s->port.state->port.tty->low_latency = 1;
531
532 if (s->poll_time > 0)
533 del_timer_sync(&s->timer);
534
535 uart_update_timeout(port, termios->c_cflag, baud);
536
537 spin_lock(&s->conf_lock);
538 s->conf = (s->conf & ~param_mask) | (param_new & param_mask);
539 s->conf_commit = 1;
540 s->parity = parity;
541 spin_unlock(&s->conf_lock);
542 max3100_dowork(s);
543
544 if (UART_ENABLE_MS(&s->port, termios->c_cflag))
545 max3100_enable_ms(&s->port);
546}
547
548static void max3100_shutdown(struct uart_port *port)
549{
550 struct max3100_port *s = container_of(port,
551 struct max3100_port,
552 port);
553
554 dev_dbg(&s->spi->dev, "%s\n", __func__);
555
556 if (s->suspending)
557 return;
558
559 s->force_end_work = 1;
560
561 if (s->poll_time > 0)
562 del_timer_sync(&s->timer);
563
564 if (s->workqueue) {
565 flush_workqueue(s->workqueue);
566 destroy_workqueue(s->workqueue);
567 s->workqueue = NULL;
568 }
569 if (s->irq)
570 free_irq(s->irq, s);
571
572 /* set shutdown mode to save power */
573 if (s->max3100_hw_suspend)
574 s->max3100_hw_suspend(1);
575 else {
576 u16 tx, rx;
577
578 tx = MAX3100_WC | MAX3100_SHDN;
579 max3100_sr(s, tx, &rx);
580 }
581}
582
583static int max3100_startup(struct uart_port *port)
584{
585 struct max3100_port *s = container_of(port,
586 struct max3100_port,
587 port);
588 char b[12];
589
590 dev_dbg(&s->spi->dev, "%s\n", __func__);
591
592 s->conf = MAX3100_RM;
593 s->baud = s->crystal ? 230400 : 115200;
594 s->rx_enabled = 1;
595
596 if (s->suspending)
597 return 0;
598
599 s->force_end_work = 0;
600 s->parity = 0;
601 s->rts = 0;
602
603 sprintf(b, "max3100-%d", s->minor);
604 s->workqueue = create_freezeable_workqueue(b);
605 if (!s->workqueue) {
606 dev_warn(&s->spi->dev, "cannot create workqueue\n");
607 return -EBUSY;
608 }
609 INIT_WORK(&s->work, max3100_work);
610
611 if (request_irq(s->irq, max3100_irq,
612 IRQF_TRIGGER_FALLING, "max3100", s) < 0) {
613 dev_warn(&s->spi->dev, "cannot allocate irq %d\n", s->irq);
614 s->irq = 0;
615 destroy_workqueue(s->workqueue);
616 s->workqueue = NULL;
617 return -EBUSY;
618 }
619
620 if (s->loopback) {
621 u16 tx, rx;
622 tx = 0x4001;
623 max3100_sr(s, tx, &rx);
624 }
625
626 if (s->max3100_hw_suspend)
627 s->max3100_hw_suspend(0);
628 s->conf_commit = 1;
629 max3100_dowork(s);
630 /* wait for clock to settle */
631 msleep(50);
632
633 max3100_enable_ms(&s->port);
634
635 return 0;
636}
637
638static const char *max3100_type(struct uart_port *port)
639{
640 struct max3100_port *s = container_of(port,
641 struct max3100_port,
642 port);
643
644 dev_dbg(&s->spi->dev, "%s\n", __func__);
645
646 return s->port.type == PORT_MAX3100 ? "MAX3100" : NULL;
647}
648
649static void max3100_release_port(struct uart_port *port)
650{
651 struct max3100_port *s = container_of(port,
652 struct max3100_port,
653 port);
654
655 dev_dbg(&s->spi->dev, "%s\n", __func__);
656}
657
658static void max3100_config_port(struct uart_port *port, int flags)
659{
660 struct max3100_port *s = container_of(port,
661 struct max3100_port,
662 port);
663
664 dev_dbg(&s->spi->dev, "%s\n", __func__);
665
666 if (flags & UART_CONFIG_TYPE)
667 s->port.type = PORT_MAX3100;
668}
669
670static int max3100_verify_port(struct uart_port *port,
671 struct serial_struct *ser)
672{
673 struct max3100_port *s = container_of(port,
674 struct max3100_port,
675 port);
676 int ret = -EINVAL;
677
678 dev_dbg(&s->spi->dev, "%s\n", __func__);
679
680 if (ser->type == PORT_UNKNOWN || ser->type == PORT_MAX3100)
681 ret = 0;
682 return ret;
683}
684
685static void max3100_stop_tx(struct uart_port *port)
686{
687 struct max3100_port *s = container_of(port,
688 struct max3100_port,
689 port);
690
691 dev_dbg(&s->spi->dev, "%s\n", __func__);
692}
693
694static int max3100_request_port(struct uart_port *port)
695{
696 struct max3100_port *s = container_of(port,
697 struct max3100_port,
698 port);
699
700 dev_dbg(&s->spi->dev, "%s\n", __func__);
701 return 0;
702}
703
704static void max3100_break_ctl(struct uart_port *port, int break_state)
705{
706 struct max3100_port *s = container_of(port,
707 struct max3100_port,
708 port);
709
710 dev_dbg(&s->spi->dev, "%s\n", __func__);
711}
712
713static struct uart_ops max3100_ops = {
714 .tx_empty = max3100_tx_empty,
715 .set_mctrl = max3100_set_mctrl,
716 .get_mctrl = max3100_get_mctrl,
717 .stop_tx = max3100_stop_tx,
718 .start_tx = max3100_start_tx,
719 .stop_rx = max3100_stop_rx,
720 .enable_ms = max3100_enable_ms,
721 .break_ctl = max3100_break_ctl,
722 .startup = max3100_startup,
723 .shutdown = max3100_shutdown,
724 .set_termios = max3100_set_termios,
725 .type = max3100_type,
726 .release_port = max3100_release_port,
727 .request_port = max3100_request_port,
728 .config_port = max3100_config_port,
729 .verify_port = max3100_verify_port,
730};
731
732static struct uart_driver max3100_uart_driver = {
733 .owner = THIS_MODULE,
734 .driver_name = "ttyMAX",
735 .dev_name = "ttyMAX",
736 .major = MAX3100_MAJOR,
737 .minor = MAX3100_MINOR,
738 .nr = MAX_MAX3100,
739};
740static int uart_driver_registered;
741
742static int __devinit max3100_probe(struct spi_device *spi)
743{
744 int i, retval;
745 struct plat_max3100 *pdata;
746 u16 tx, rx;
747
748 mutex_lock(&max3100s_lock);
749
750 if (!uart_driver_registered) {
751 uart_driver_registered = 1;
752 retval = uart_register_driver(&max3100_uart_driver);
753 if (retval) {
754 printk(KERN_ERR "Couldn't register max3100 uart driver\n");
755 mutex_unlock(&max3100s_lock);
756 return retval;
757 }
758 }
759
760 for (i = 0; i < MAX_MAX3100; i++)
761 if (!max3100s[i])
762 break;
763 if (i == MAX_MAX3100) {
764 dev_warn(&spi->dev, "too many MAX3100 chips\n");
765 mutex_unlock(&max3100s_lock);
766 return -ENOMEM;
767 }
768
769 max3100s[i] = kzalloc(sizeof(struct max3100_port), GFP_KERNEL);
770 if (!max3100s[i]) {
771 dev_warn(&spi->dev,
772 "kmalloc for max3100 structure %d failed!\n", i);
773 mutex_unlock(&max3100s_lock);
774 return -ENOMEM;
775 }
776 max3100s[i]->spi = spi;
777 max3100s[i]->irq = spi->irq;
778 spin_lock_init(&max3100s[i]->conf_lock);
779 dev_set_drvdata(&spi->dev, max3100s[i]);
780 pdata = spi->dev.platform_data;
781 max3100s[i]->crystal = pdata->crystal;
782 max3100s[i]->loopback = pdata->loopback;
783 max3100s[i]->poll_time = pdata->poll_time * HZ / 1000;
784 if (pdata->poll_time > 0 && max3100s[i]->poll_time == 0)
785 max3100s[i]->poll_time = 1;
786 max3100s[i]->max3100_hw_suspend = pdata->max3100_hw_suspend;
787 max3100s[i]->minor = i;
788 init_timer(&max3100s[i]->timer);
789 max3100s[i]->timer.function = max3100_timeout;
790 max3100s[i]->timer.data = (unsigned long) max3100s[i];
791
792 dev_dbg(&spi->dev, "%s: adding port %d\n", __func__, i);
793 max3100s[i]->port.irq = max3100s[i]->irq;
794 max3100s[i]->port.uartclk = max3100s[i]->crystal ? 3686400 : 1843200;
795 max3100s[i]->port.fifosize = 16;
796 max3100s[i]->port.ops = &max3100_ops;
797 max3100s[i]->port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF;
798 max3100s[i]->port.line = i;
799 max3100s[i]->port.type = PORT_MAX3100;
800 max3100s[i]->port.dev = &spi->dev;
801 retval = uart_add_one_port(&max3100_uart_driver, &max3100s[i]->port);
802 if (retval < 0)
803 dev_warn(&spi->dev,
804 "uart_add_one_port failed for line %d with error %d\n",
805 i, retval);
806
807 /* set shutdown mode to save power. Will be woken-up on open */
808 if (max3100s[i]->max3100_hw_suspend)
809 max3100s[i]->max3100_hw_suspend(1);
810 else {
811 tx = MAX3100_WC | MAX3100_SHDN;
812 max3100_sr(max3100s[i], tx, &rx);
813 }
814 mutex_unlock(&max3100s_lock);
815 return 0;
816}
817
818static int __devexit max3100_remove(struct spi_device *spi)
819{
820 struct max3100_port *s = dev_get_drvdata(&spi->dev);
821 int i;
822
823 mutex_lock(&max3100s_lock);
824
825 /* find out the index for the chip we are removing */
826 for (i = 0; i < MAX_MAX3100; i++)
827 if (max3100s[i] == s)
828 break;
829
830 dev_dbg(&spi->dev, "%s: removing port %d\n", __func__, i);
831 uart_remove_one_port(&max3100_uart_driver, &max3100s[i]->port);
832 kfree(max3100s[i]);
833 max3100s[i] = NULL;
834
835 /* check if this is the last chip we have */
836 for (i = 0; i < MAX_MAX3100; i++)
837 if (max3100s[i]) {
838 mutex_unlock(&max3100s_lock);
839 return 0;
840 }
841 pr_debug("removing max3100 driver\n");
842 uart_unregister_driver(&max3100_uart_driver);
843
844 mutex_unlock(&max3100s_lock);
845 return 0;
846}
847
848#ifdef CONFIG_PM
849
850static int max3100_suspend(struct spi_device *spi, pm_message_t state)
851{
852 struct max3100_port *s = dev_get_drvdata(&spi->dev);
853
854 dev_dbg(&s->spi->dev, "%s\n", __func__);
855
856 disable_irq(s->irq);
857
858 s->suspending = 1;
859 uart_suspend_port(&max3100_uart_driver, &s->port);
860
861 if (s->max3100_hw_suspend)
862 s->max3100_hw_suspend(1);
863 else {
864 /* no HW suspend, so do SW one */
865 u16 tx, rx;
866
867 tx = MAX3100_WC | MAX3100_SHDN;
868 max3100_sr(s, tx, &rx);
869 }
870 return 0;
871}
872
873static int max3100_resume(struct spi_device *spi)
874{
875 struct max3100_port *s = dev_get_drvdata(&spi->dev);
876
877 dev_dbg(&s->spi->dev, "%s\n", __func__);
878
879 if (s->max3100_hw_suspend)
880 s->max3100_hw_suspend(0);
881 uart_resume_port(&max3100_uart_driver, &s->port);
882 s->suspending = 0;
883
884 enable_irq(s->irq);
885
886 s->conf_commit = 1;
887 if (s->workqueue)
888 max3100_dowork(s);
889
890 return 0;
891}
892
893#else
894#define max3100_suspend NULL
895#define max3100_resume NULL
896#endif
897
898static struct spi_driver max3100_driver = {
899 .driver = {
900 .name = "max3100",
901 .bus = &spi_bus_type,
902 .owner = THIS_MODULE,
903 },
904
905 .probe = max3100_probe,
906 .remove = __devexit_p(max3100_remove),
907 .suspend = max3100_suspend,
908 .resume = max3100_resume,
909};
910
911static int __init max3100_init(void)
912{
913 return spi_register_driver(&max3100_driver);
914}
915module_init(max3100_init);
916
917static void __exit max3100_exit(void)
918{
919 spi_unregister_driver(&max3100_driver);
920}
921module_exit(max3100_exit);
922
923MODULE_DESCRIPTION("MAX3100 driver");
924MODULE_AUTHOR("Christian Pellegrin <chripell@evolware.org>");
925MODULE_LICENSE("GPL");
926MODULE_ALIAS("spi:max3100");
diff --git a/drivers/serial/max3107-aava.c b/drivers/serial/max3107-aava.c
deleted file mode 100644
index a1fe304f2f52..000000000000
--- a/drivers/serial/max3107-aava.c
+++ /dev/null
@@ -1,344 +0,0 @@
1/*
2 * max3107.c - spi uart protocol driver for Maxim 3107
3 * Based on max3100.c
4 * by Christian Pellegrin <chripell@evolware.org>
5 * and max3110.c
6 * by Feng Tang <feng.tang@intel.com>
7 *
8 * Copyright (C) Aavamobile 2009
9 *
10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
27 *
28 */
29
30#include <linux/delay.h>
31#include <linux/device.h>
32#include <linux/serial_core.h>
33#include <linux/serial.h>
34#include <linux/spi/spi.h>
35#include <linux/freezer.h>
36#include <linux/platform_device.h>
37#include <linux/gpio.h>
38#include <linux/sfi.h>
39#include <asm/mrst.h>
40#include "max3107.h"
41
42/* GPIO direction to input function */
43static int max3107_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
44{
45 struct max3107_port *s = container_of(chip, struct max3107_port, chip);
46 u16 buf[1]; /* Buffer for SPI transfer */
47
48 if (offset >= MAX3107_GPIO_COUNT) {
49 dev_err(&s->spi->dev, "Invalid GPIO\n");
50 return -EINVAL;
51 }
52
53 /* Read current GPIO configuration register */
54 buf[0] = MAX3107_GPIOCFG_REG;
55 /* Perform SPI transfer */
56 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
57 dev_err(&s->spi->dev, "SPI transfer GPIO read failed\n");
58 return -EIO;
59 }
60 buf[0] &= MAX3107_SPI_RX_DATA_MASK;
61
62 /* Set GPIO to input */
63 buf[0] &= ~(0x0001 << offset);
64
65 /* Write new GPIO configuration register value */
66 buf[0] |= (MAX3107_WRITE_BIT | MAX3107_GPIOCFG_REG);
67 /* Perform SPI transfer */
68 if (max3107_rw(s, (u8 *)buf, NULL, 2)) {
69 dev_err(&s->spi->dev, "SPI transfer GPIO write failed\n");
70 return -EIO;
71 }
72 return 0;
73}
74
75/* GPIO direction to output function */
76static int max3107_gpio_direction_out(struct gpio_chip *chip, unsigned offset,
77 int value)
78{
79 struct max3107_port *s = container_of(chip, struct max3107_port, chip);
80 u16 buf[2]; /* Buffer for SPI transfers */
81
82 if (offset >= MAX3107_GPIO_COUNT) {
83 dev_err(&s->spi->dev, "Invalid GPIO\n");
84 return -EINVAL;
85 }
86
87 /* Read current GPIO configuration and data registers */
88 buf[0] = MAX3107_GPIOCFG_REG;
89 buf[1] = MAX3107_GPIODATA_REG;
90 /* Perform SPI transfer */
91 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 4)) {
92 dev_err(&s->spi->dev, "SPI transfer gpio failed\n");
93 return -EIO;
94 }
95 buf[0] &= MAX3107_SPI_RX_DATA_MASK;
96 buf[1] &= MAX3107_SPI_RX_DATA_MASK;
97
98 /* Set GPIO to output */
99 buf[0] |= (0x0001 << offset);
100 /* Set value */
101 if (value)
102 buf[1] |= (0x0001 << offset);
103 else
104 buf[1] &= ~(0x0001 << offset);
105
106 /* Write new GPIO configuration and data register values */
107 buf[0] |= (MAX3107_WRITE_BIT | MAX3107_GPIOCFG_REG);
108 buf[1] |= (MAX3107_WRITE_BIT | MAX3107_GPIODATA_REG);
109 /* Perform SPI transfer */
110 if (max3107_rw(s, (u8 *)buf, NULL, 4)) {
111 dev_err(&s->spi->dev,
112 "SPI transfer for GPIO conf data w failed\n");
113 return -EIO;
114 }
115 return 0;
116}
117
118/* GPIO value query function */
119static int max3107_gpio_get(struct gpio_chip *chip, unsigned offset)
120{
121 struct max3107_port *s = container_of(chip, struct max3107_port, chip);
122 u16 buf[1]; /* Buffer for SPI transfer */
123
124 if (offset >= MAX3107_GPIO_COUNT) {
125 dev_err(&s->spi->dev, "Invalid GPIO\n");
126 return -EINVAL;
127 }
128
129 /* Read current GPIO data register */
130 buf[0] = MAX3107_GPIODATA_REG;
131 /* Perform SPI transfer */
132 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
133 dev_err(&s->spi->dev, "SPI transfer GPIO data r failed\n");
134 return -EIO;
135 }
136 buf[0] &= MAX3107_SPI_RX_DATA_MASK;
137
138 /* Return value */
139 return buf[0] & (0x0001 << offset);
140}
141
142/* GPIO value set function */
143static void max3107_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
144{
145 struct max3107_port *s = container_of(chip, struct max3107_port, chip);
146 u16 buf[2]; /* Buffer for SPI transfers */
147
148 if (offset >= MAX3107_GPIO_COUNT) {
149 dev_err(&s->spi->dev, "Invalid GPIO\n");
150 return;
151 }
152
153 /* Read current GPIO configuration registers*/
154 buf[0] = MAX3107_GPIODATA_REG;
155 buf[1] = MAX3107_GPIOCFG_REG;
156 /* Perform SPI transfer */
157 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 4)) {
158 dev_err(&s->spi->dev,
159 "SPI transfer for GPIO data and config read failed\n");
160 return;
161 }
162 buf[0] &= MAX3107_SPI_RX_DATA_MASK;
163 buf[1] &= MAX3107_SPI_RX_DATA_MASK;
164
165 if (!(buf[1] & (0x0001 << offset))) {
166 /* Configured as input, can't set value */
167 dev_warn(&s->spi->dev,
168 "Trying to set value for input GPIO\n");
169 return;
170 }
171
172 /* Set value */
173 if (value)
174 buf[0] |= (0x0001 << offset);
175 else
176 buf[0] &= ~(0x0001 << offset);
177
178 /* Write new GPIO data register value */
179 buf[0] |= (MAX3107_WRITE_BIT | MAX3107_GPIODATA_REG);
180 /* Perform SPI transfer */
181 if (max3107_rw(s, (u8 *)buf, NULL, 2))
182 dev_err(&s->spi->dev, "SPI transfer GPIO data w failed\n");
183}
184
185/* GPIO chip data */
186static struct gpio_chip max3107_gpio_chip = {
187 .owner = THIS_MODULE,
188 .direction_input = max3107_gpio_direction_in,
189 .direction_output = max3107_gpio_direction_out,
190 .get = max3107_gpio_get,
191 .set = max3107_gpio_set,
192 .can_sleep = 1,
193 .base = MAX3107_GPIO_BASE,
194 .ngpio = MAX3107_GPIO_COUNT,
195};
196
197/**
198 * max3107_aava_reset - reset on AAVA systems
199 * @spi: The SPI device we are probing
200 *
201 * Reset the device ready for probing.
202 */
203
204static int max3107_aava_reset(struct spi_device *spi)
205{
206 /* Reset the chip */
207 if (gpio_request(MAX3107_RESET_GPIO, "max3107")) {
208 pr_err("Requesting RESET GPIO failed\n");
209 return -EIO;
210 }
211 if (gpio_direction_output(MAX3107_RESET_GPIO, 0)) {
212 pr_err("Setting RESET GPIO to 0 failed\n");
213 gpio_free(MAX3107_RESET_GPIO);
214 return -EIO;
215 }
216 msleep(MAX3107_RESET_DELAY);
217 if (gpio_direction_output(MAX3107_RESET_GPIO, 1)) {
218 pr_err("Setting RESET GPIO to 1 failed\n");
219 gpio_free(MAX3107_RESET_GPIO);
220 return -EIO;
221 }
222 gpio_free(MAX3107_RESET_GPIO);
223 msleep(MAX3107_WAKEUP_DELAY);
224 return 0;
225}
226
227static int max3107_aava_configure(struct max3107_port *s)
228{
229 int retval;
230
231 /* Initialize GPIO chip data */
232 s->chip = max3107_gpio_chip;
233 s->chip.label = s->spi->modalias;
234 s->chip.dev = &s->spi->dev;
235
236 /* Add GPIO chip */
237 retval = gpiochip_add(&s->chip);
238 if (retval) {
239 dev_err(&s->spi->dev, "Adding GPIO chip failed\n");
240 return retval;
241 }
242
243 /* Temporary fix for EV2 boot problems, set modem reset to 0 */
244 max3107_gpio_direction_out(&s->chip, 3, 0);
245 return 0;
246}
247
248#if 0
249/* This will get enabled once we have the board stuff merged for this
250 specific case */
251
252static const struct baud_table brg13_ext[] = {
253 { 300, MAX3107_BRG13_B300 },
254 { 600, MAX3107_BRG13_B600 },
255 { 1200, MAX3107_BRG13_B1200 },
256 { 2400, MAX3107_BRG13_B2400 },
257 { 4800, MAX3107_BRG13_B4800 },
258 { 9600, MAX3107_BRG13_B9600 },
259 { 19200, MAX3107_BRG13_B19200 },
260 { 57600, MAX3107_BRG13_B57600 },
261 { 115200, MAX3107_BRG13_B115200 },
262 { 230400, MAX3107_BRG13_B230400 },
263 { 460800, MAX3107_BRG13_B460800 },
264 { 921600, MAX3107_BRG13_B921600 },
265 { 0, 0 }
266};
267
268static void max3107_aava_init(struct max3107_port *s)
269{
270 /*override for AAVA SC specific*/
271 if (mrst_platform_id() == MRST_PLATFORM_AAVA_SC) {
272 if (get_koski_build_id() <= KOSKI_EV2)
273 if (s->ext_clk) {
274 s->brg_cfg = MAX3107_BRG13_B9600;
275 s->baud_tbl = (struct baud_table *)brg13_ext;
276 }
277 }
278}
279#endif
280
281static int __devexit max3107_aava_remove(struct spi_device *spi)
282{
283 struct max3107_port *s = dev_get_drvdata(&spi->dev);
284
285 /* Remove GPIO chip */
286 if (gpiochip_remove(&s->chip))
287 dev_warn(&spi->dev, "Removing GPIO chip failed\n");
288
289 /* Then do the default remove */
290 return max3107_remove(spi);
291}
292
293/* Platform data */
294static struct max3107_plat aava_plat_data = {
295 .loopback = 0,
296 .ext_clk = 1,
297/* .init = max3107_aava_init, */
298 .configure = max3107_aava_configure,
299 .hw_suspend = max3107_hw_susp,
300 .polled_mode = 0,
301 .poll_time = 0,
302};
303
304
305static int __devinit max3107_probe_aava(struct spi_device *spi)
306{
307 int err = max3107_aava_reset(spi);
308 if (err < 0)
309 return err;
310 return max3107_probe(spi, &aava_plat_data);
311}
312
313/* Spi driver data */
314static struct spi_driver max3107_driver = {
315 .driver = {
316 .name = "aava-max3107",
317 .bus = &spi_bus_type,
318 .owner = THIS_MODULE,
319 },
320 .probe = max3107_probe_aava,
321 .remove = __devexit_p(max3107_aava_remove),
322 .suspend = max3107_suspend,
323 .resume = max3107_resume,
324};
325
326/* Driver init function */
327static int __init max3107_init(void)
328{
329 return spi_register_driver(&max3107_driver);
330}
331
332/* Driver exit function */
333static void __exit max3107_exit(void)
334{
335 spi_unregister_driver(&max3107_driver);
336}
337
338module_init(max3107_init);
339module_exit(max3107_exit);
340
341MODULE_DESCRIPTION("MAX3107 driver");
342MODULE_AUTHOR("Aavamobile");
343MODULE_ALIAS("aava-max3107-spi");
344MODULE_LICENSE("GPL v2");
diff --git a/drivers/serial/max3107.c b/drivers/serial/max3107.c
deleted file mode 100644
index 67283c1a57ff..000000000000
--- a/drivers/serial/max3107.c
+++ /dev/null
@@ -1,1197 +0,0 @@
1/*
2 * max3107.c - spi uart protocol driver for Maxim 3107
3 * Based on max3100.c
4 * by Christian Pellegrin <chripell@evolware.org>
5 * and max3110.c
6 * by Feng Tang <feng.tang@intel.com>
7 *
8 * Copyright (C) Aavamobile 2009
9 *
10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
27 *
28 */
29
30#include <linux/delay.h>
31#include <linux/device.h>
32#include <linux/serial_core.h>
33#include <linux/serial.h>
34#include <linux/gpio.h>
35#include <linux/spi/spi.h>
36#include <linux/freezer.h>
37#include "max3107.h"
38
39static const struct baud_table brg26_ext[] = {
40 { 300, MAX3107_BRG26_B300 },
41 { 600, MAX3107_BRG26_B600 },
42 { 1200, MAX3107_BRG26_B1200 },
43 { 2400, MAX3107_BRG26_B2400 },
44 { 4800, MAX3107_BRG26_B4800 },
45 { 9600, MAX3107_BRG26_B9600 },
46 { 19200, MAX3107_BRG26_B19200 },
47 { 57600, MAX3107_BRG26_B57600 },
48 { 115200, MAX3107_BRG26_B115200 },
49 { 230400, MAX3107_BRG26_B230400 },
50 { 460800, MAX3107_BRG26_B460800 },
51 { 921600, MAX3107_BRG26_B921600 },
52 { 0, 0 }
53};
54
55static const struct baud_table brg13_int[] = {
56 { 300, MAX3107_BRG13_IB300 },
57 { 600, MAX3107_BRG13_IB600 },
58 { 1200, MAX3107_BRG13_IB1200 },
59 { 2400, MAX3107_BRG13_IB2400 },
60 { 4800, MAX3107_BRG13_IB4800 },
61 { 9600, MAX3107_BRG13_IB9600 },
62 { 19200, MAX3107_BRG13_IB19200 },
63 { 57600, MAX3107_BRG13_IB57600 },
64 { 115200, MAX3107_BRG13_IB115200 },
65 { 230400, MAX3107_BRG13_IB230400 },
66 { 460800, MAX3107_BRG13_IB460800 },
67 { 921600, MAX3107_BRG13_IB921600 },
68 { 0, 0 }
69};
70
71static u32 get_new_brg(int baud, struct max3107_port *s)
72{
73 int i;
74 const struct baud_table *baud_tbl = s->baud_tbl;
75
76 for (i = 0; i < 13; i++) {
77 if (baud == baud_tbl[i].baud)
78 return baud_tbl[i].new_brg;
79 }
80
81 return 0;
82}
83
84/* Perform SPI transfer for write/read of device register(s) */
85int max3107_rw(struct max3107_port *s, u8 *tx, u8 *rx, int len)
86{
87 struct spi_message spi_msg;
88 struct spi_transfer spi_xfer;
89
90 /* Initialize SPI ,message */
91 spi_message_init(&spi_msg);
92
93 /* Initialize SPI transfer */
94 memset(&spi_xfer, 0, sizeof spi_xfer);
95 spi_xfer.len = len;
96 spi_xfer.tx_buf = tx;
97 spi_xfer.rx_buf = rx;
98 spi_xfer.speed_hz = MAX3107_SPI_SPEED;
99
100 /* Add SPI transfer to SPI message */
101 spi_message_add_tail(&spi_xfer, &spi_msg);
102
103#ifdef DBG_TRACE_SPI_DATA
104 {
105 int i;
106 pr_info("tx len %d:\n", spi_xfer.len);
107 for (i = 0 ; i < spi_xfer.len && i < 32 ; i++)
108 pr_info(" %x", ((u8 *)spi_xfer.tx_buf)[i]);
109 pr_info("\n");
110 }
111#endif
112
113 /* Perform synchronous SPI transfer */
114 if (spi_sync(s->spi, &spi_msg)) {
115 dev_err(&s->spi->dev, "spi_sync failure\n");
116 return -EIO;
117 }
118
119#ifdef DBG_TRACE_SPI_DATA
120 if (spi_xfer.rx_buf) {
121 int i;
122 pr_info("rx len %d:\n", spi_xfer.len);
123 for (i = 0 ; i < spi_xfer.len && i < 32 ; i++)
124 pr_info(" %x", ((u8 *)spi_xfer.rx_buf)[i]);
125 pr_info("\n");
126 }
127#endif
128 return 0;
129}
130EXPORT_SYMBOL_GPL(max3107_rw);
131
132/* Puts received data to circular buffer */
133static void put_data_to_circ_buf(struct max3107_port *s, unsigned char *data,
134 int len)
135{
136 struct uart_port *port = &s->port;
137 struct tty_struct *tty;
138
139 if (!port->state)
140 return;
141
142 tty = port->state->port.tty;
143 if (!tty)
144 return;
145
146 /* Insert received data */
147 tty_insert_flip_string(tty, data, len);
148 /* Update RX counter */
149 port->icount.rx += len;
150}
151
152/* Handle data receiving */
153static void max3107_handlerx(struct max3107_port *s, u16 rxlvl)
154{
155 int i;
156 int j;
157 int len; /* SPI transfer buffer length */
158 u16 *buf;
159 u8 *valid_str;
160
161 if (!s->rx_enabled)
162 /* RX is disabled */
163 return;
164
165 if (rxlvl == 0) {
166 /* RX fifo is empty */
167 return;
168 } else if (rxlvl >= MAX3107_RX_FIFO_SIZE) {
169 dev_warn(&s->spi->dev, "Possible RX FIFO overrun %d\n", rxlvl);
170 /* Ensure sanity of RX level */
171 rxlvl = MAX3107_RX_FIFO_SIZE;
172 }
173 if ((s->rxbuf == 0) || (s->rxstr == 0)) {
174 dev_warn(&s->spi->dev, "Rx buffer/str isn't ready\n");
175 return;
176 }
177 buf = s->rxbuf;
178 valid_str = s->rxstr;
179 while (rxlvl) {
180 pr_debug("rxlvl %d\n", rxlvl);
181 /* Clear buffer */
182 memset(buf, 0, sizeof(u16) * (MAX3107_RX_FIFO_SIZE + 2));
183 len = 0;
184 if (s->irqen_reg & MAX3107_IRQ_RXFIFO_BIT) {
185 /* First disable RX FIFO interrupt */
186 pr_debug("Disabling RX INT\n");
187 buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
188 s->irqen_reg &= ~MAX3107_IRQ_RXFIFO_BIT;
189 buf[0] |= s->irqen_reg;
190 len++;
191 }
192 /* Just increase the length by amount of words in FIFO since
193 * buffer was zeroed and SPI transfer of 0x0000 means reading
194 * from RX FIFO
195 */
196 len += rxlvl;
197 /* Append RX level query */
198 buf[len] = MAX3107_RXFIFOLVL_REG;
199 len++;
200
201 /* Perform the SPI transfer */
202 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, len * 2)) {
203 dev_err(&s->spi->dev, "SPI transfer for RX h failed\n");
204 return;
205 }
206
207 /* Skip RX FIFO interrupt disabling word if it was added */
208 j = ((len - 1) - rxlvl);
209 /* Read received words */
210 for (i = 0; i < rxlvl; i++, j++)
211 valid_str[i] = (u8)buf[j];
212 put_data_to_circ_buf(s, valid_str, rxlvl);
213 /* Get new RX level */
214 rxlvl = (buf[len - 1] & MAX3107_SPI_RX_DATA_MASK);
215 }
216
217 if (s->rx_enabled) {
218 /* RX still enabled, re-enable RX FIFO interrupt */
219 pr_debug("Enabling RX INT\n");
220 buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
221 s->irqen_reg |= MAX3107_IRQ_RXFIFO_BIT;
222 buf[0] |= s->irqen_reg;
223 if (max3107_rw(s, (u8 *)buf, NULL, 2))
224 dev_err(&s->spi->dev, "RX FIFO INT enabling failed\n");
225 }
226
227 /* Push the received data to receivers */
228 if (s->port.state->port.tty)
229 tty_flip_buffer_push(s->port.state->port.tty);
230}
231
232
233/* Handle data sending */
234static void max3107_handletx(struct max3107_port *s)
235{
236 struct circ_buf *xmit = &s->port.state->xmit;
237 int i;
238 unsigned long flags;
239 int len; /* SPI transfer buffer length */
240 u16 *buf;
241
242 if (!s->tx_fifo_empty)
243 /* Don't send more data before previous data is sent */
244 return;
245
246 if (uart_circ_empty(xmit) || uart_tx_stopped(&s->port))
247 /* No data to send or TX is stopped */
248 return;
249
250 if (!s->txbuf) {
251 dev_warn(&s->spi->dev, "Txbuf isn't ready\n");
252 return;
253 }
254 buf = s->txbuf;
255 /* Get length of data pending in circular buffer */
256 len = uart_circ_chars_pending(xmit);
257 if (len) {
258 /* Limit to size of TX FIFO */
259 if (len > MAX3107_TX_FIFO_SIZE)
260 len = MAX3107_TX_FIFO_SIZE;
261
262 pr_debug("txlen %d\n", len);
263
264 /* Update TX counter */
265 s->port.icount.tx += len;
266
267 /* TX FIFO will no longer be empty */
268 s->tx_fifo_empty = 0;
269
270 i = 0;
271 if (s->irqen_reg & MAX3107_IRQ_TXEMPTY_BIT) {
272 /* First disable TX empty interrupt */
273 pr_debug("Disabling TE INT\n");
274 buf[i] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
275 s->irqen_reg &= ~MAX3107_IRQ_TXEMPTY_BIT;
276 buf[i] |= s->irqen_reg;
277 i++;
278 len++;
279 }
280 /* Add data to send */
281 spin_lock_irqsave(&s->port.lock, flags);
282 for ( ; i < len ; i++) {
283 buf[i] = (MAX3107_WRITE_BIT | MAX3107_THR_REG);
284 buf[i] |= ((u16)xmit->buf[xmit->tail] &
285 MAX3107_SPI_TX_DATA_MASK);
286 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
287 }
288 spin_unlock_irqrestore(&s->port.lock, flags);
289 if (!(s->irqen_reg & MAX3107_IRQ_TXEMPTY_BIT)) {
290 /* Enable TX empty interrupt */
291 pr_debug("Enabling TE INT\n");
292 buf[i] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
293 s->irqen_reg |= MAX3107_IRQ_TXEMPTY_BIT;
294 buf[i] |= s->irqen_reg;
295 i++;
296 len++;
297 }
298 if (!s->tx_enabled) {
299 /* Enable TX */
300 pr_debug("Enable TX\n");
301 buf[i] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
302 spin_lock_irqsave(&s->data_lock, flags);
303 s->mode1_reg &= ~MAX3107_MODE1_TXDIS_BIT;
304 buf[i] |= s->mode1_reg;
305 spin_unlock_irqrestore(&s->data_lock, flags);
306 s->tx_enabled = 1;
307 i++;
308 len++;
309 }
310
311 /* Perform the SPI transfer */
312 if (max3107_rw(s, (u8 *)buf, NULL, len*2)) {
313 dev_err(&s->spi->dev,
314 "SPI transfer TX handling failed\n");
315 return;
316 }
317 }
318
319 /* Indicate wake up if circular buffer is getting low on data */
320 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
321 uart_write_wakeup(&s->port);
322
323}
324
325/* Handle interrupts
326 * Also reads and returns current RX FIFO level
327 */
328static u16 handle_interrupt(struct max3107_port *s)
329{
330 u16 buf[4]; /* Buffer for SPI transfers */
331 u8 irq_status;
332 u16 rx_level;
333 unsigned long flags;
334
335 /* Read IRQ status register */
336 buf[0] = MAX3107_IRQSTS_REG;
337 /* Read status IRQ status register */
338 buf[1] = MAX3107_STS_IRQSTS_REG;
339 /* Read LSR IRQ status register */
340 buf[2] = MAX3107_LSR_IRQSTS_REG;
341 /* Query RX level */
342 buf[3] = MAX3107_RXFIFOLVL_REG;
343
344 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 8)) {
345 dev_err(&s->spi->dev,
346 "SPI transfer for INTR handling failed\n");
347 return 0;
348 }
349
350 irq_status = (u8)buf[0];
351 pr_debug("IRQSTS %x\n", irq_status);
352 rx_level = (buf[3] & MAX3107_SPI_RX_DATA_MASK);
353
354 if (irq_status & MAX3107_IRQ_LSR_BIT) {
355 /* LSR interrupt */
356 if (buf[2] & MAX3107_LSR_RXTO_BIT)
357 /* RX timeout interrupt,
358 * handled by normal RX handling
359 */
360 pr_debug("RX TO INT\n");
361 }
362
363 if (irq_status & MAX3107_IRQ_TXEMPTY_BIT) {
364 /* Tx empty interrupt,
365 * disable TX and set tx_fifo_empty flag
366 */
367 pr_debug("TE INT, disabling TX\n");
368 buf[0] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
369 spin_lock_irqsave(&s->data_lock, flags);
370 s->mode1_reg |= MAX3107_MODE1_TXDIS_BIT;
371 buf[0] |= s->mode1_reg;
372 spin_unlock_irqrestore(&s->data_lock, flags);
373 if (max3107_rw(s, (u8 *)buf, NULL, 2))
374 dev_err(&s->spi->dev, "SPI transfer TX dis failed\n");
375 s->tx_enabled = 0;
376 s->tx_fifo_empty = 1;
377 }
378
379 if (irq_status & MAX3107_IRQ_RXFIFO_BIT)
380 /* RX FIFO interrupt,
381 * handled by normal RX handling
382 */
383 pr_debug("RFIFO INT\n");
384
385 /* Return RX level */
386 return rx_level;
387}
388
389/* Trigger work thread*/
390static void max3107_dowork(struct max3107_port *s)
391{
392 if (!work_pending(&s->work) && !freezing(current) && !s->suspended)
393 queue_work(s->workqueue, &s->work);
394 else
395 dev_warn(&s->spi->dev, "interrup isn't serviced normally!\n");
396}
397
398/* Work thread */
399static void max3107_work(struct work_struct *w)
400{
401 struct max3107_port *s = container_of(w, struct max3107_port, work);
402 u16 rxlvl = 0;
403 int len; /* SPI transfer buffer length */
404 u16 buf[5]; /* Buffer for SPI transfers */
405 unsigned long flags;
406
407 /* Start by reading current RX FIFO level */
408 buf[0] = MAX3107_RXFIFOLVL_REG;
409 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
410 dev_err(&s->spi->dev, "SPI transfer RX lev failed\n");
411 rxlvl = 0;
412 } else {
413 rxlvl = (buf[0] & MAX3107_SPI_RX_DATA_MASK);
414 }
415
416 do {
417 pr_debug("rxlvl %d\n", rxlvl);
418
419 /* Handle RX */
420 max3107_handlerx(s, rxlvl);
421 rxlvl = 0;
422
423 if (s->handle_irq) {
424 /* Handle pending interrupts
425 * We also get new RX FIFO level since new data may
426 * have been received while pushing received data to
427 * receivers
428 */
429 s->handle_irq = 0;
430 rxlvl = handle_interrupt(s);
431 }
432
433 /* Handle TX */
434 max3107_handletx(s);
435
436 /* Handle configuration changes */
437 len = 0;
438 spin_lock_irqsave(&s->data_lock, flags);
439 if (s->mode1_commit) {
440 pr_debug("mode1_commit\n");
441 buf[len] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
442 buf[len++] |= s->mode1_reg;
443 s->mode1_commit = 0;
444 }
445 if (s->lcr_commit) {
446 pr_debug("lcr_commit\n");
447 buf[len] = (MAX3107_WRITE_BIT | MAX3107_LCR_REG);
448 buf[len++] |= s->lcr_reg;
449 s->lcr_commit = 0;
450 }
451 if (s->brg_commit) {
452 pr_debug("brg_commit\n");
453 buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVMSB_REG);
454 buf[len++] |= ((s->brg_cfg >> 16) &
455 MAX3107_SPI_TX_DATA_MASK);
456 buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVLSB_REG);
457 buf[len++] |= ((s->brg_cfg >> 8) &
458 MAX3107_SPI_TX_DATA_MASK);
459 buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGCFG_REG);
460 buf[len++] |= ((s->brg_cfg) & 0xff);
461 s->brg_commit = 0;
462 }
463 spin_unlock_irqrestore(&s->data_lock, flags);
464
465 if (len > 0) {
466 if (max3107_rw(s, (u8 *)buf, NULL, len * 2))
467 dev_err(&s->spi->dev,
468 "SPI transfer config failed\n");
469 }
470
471 /* Reloop if interrupt handling indicated data in RX FIFO */
472 } while (rxlvl);
473
474}
475
476/* Set sleep mode */
477static void max3107_set_sleep(struct max3107_port *s, int mode)
478{
479 u16 buf[1]; /* Buffer for SPI transfer */
480 unsigned long flags;
481 pr_debug("enter, mode %d\n", mode);
482
483 buf[0] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
484 spin_lock_irqsave(&s->data_lock, flags);
485 switch (mode) {
486 case MAX3107_DISABLE_FORCED_SLEEP:
487 s->mode1_reg &= ~MAX3107_MODE1_FORCESLEEP_BIT;
488 break;
489 case MAX3107_ENABLE_FORCED_SLEEP:
490 s->mode1_reg |= MAX3107_MODE1_FORCESLEEP_BIT;
491 break;
492 case MAX3107_DISABLE_AUTOSLEEP:
493 s->mode1_reg &= ~MAX3107_MODE1_AUTOSLEEP_BIT;
494 break;
495 case MAX3107_ENABLE_AUTOSLEEP:
496 s->mode1_reg |= MAX3107_MODE1_AUTOSLEEP_BIT;
497 break;
498 default:
499 spin_unlock_irqrestore(&s->data_lock, flags);
500 dev_warn(&s->spi->dev, "invalid sleep mode\n");
501 return;
502 }
503 buf[0] |= s->mode1_reg;
504 spin_unlock_irqrestore(&s->data_lock, flags);
505
506 if (max3107_rw(s, (u8 *)buf, NULL, 2))
507 dev_err(&s->spi->dev, "SPI transfer sleep mode failed\n");
508
509 if (mode == MAX3107_DISABLE_AUTOSLEEP ||
510 mode == MAX3107_DISABLE_FORCED_SLEEP)
511 msleep(MAX3107_WAKEUP_DELAY);
512}
513
514/* Perform full register initialization */
515static void max3107_register_init(struct max3107_port *s)
516{
517 u16 buf[11]; /* Buffer for SPI transfers */
518
519 /* 1. Configure baud rate, 9600 as default */
520 s->baud = 9600;
521 /* the below is default*/
522 if (s->ext_clk) {
523 s->brg_cfg = MAX3107_BRG26_B9600;
524 s->baud_tbl = (struct baud_table *)brg26_ext;
525 } else {
526 s->brg_cfg = MAX3107_BRG13_IB9600;
527 s->baud_tbl = (struct baud_table *)brg13_int;
528 }
529
530 if (s->pdata->init)
531 s->pdata->init(s);
532
533 buf[0] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVMSB_REG)
534 | ((s->brg_cfg >> 16) & MAX3107_SPI_TX_DATA_MASK);
535 buf[1] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVLSB_REG)
536 | ((s->brg_cfg >> 8) & MAX3107_SPI_TX_DATA_MASK);
537 buf[2] = (MAX3107_WRITE_BIT | MAX3107_BRGCFG_REG)
538 | ((s->brg_cfg) & 0xff);
539
540 /* 2. Configure LCR register, 8N1 mode by default */
541 s->lcr_reg = MAX3107_LCR_WORD_LEN_8;
542 buf[3] = (MAX3107_WRITE_BIT | MAX3107_LCR_REG)
543 | s->lcr_reg;
544
545 /* 3. Configure MODE 1 register */
546 s->mode1_reg = 0;
547 /* Enable IRQ pin */
548 s->mode1_reg |= MAX3107_MODE1_IRQSEL_BIT;
549 /* Disable TX */
550 s->mode1_reg |= MAX3107_MODE1_TXDIS_BIT;
551 s->tx_enabled = 0;
552 /* RX is enabled */
553 s->rx_enabled = 1;
554 buf[4] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG)
555 | s->mode1_reg;
556
557 /* 4. Configure MODE 2 register */
558 buf[5] = (MAX3107_WRITE_BIT | MAX3107_MODE2_REG);
559 if (s->loopback) {
560 /* Enable loopback */
561 buf[5] |= MAX3107_MODE2_LOOPBACK_BIT;
562 }
563 /* Reset FIFOs */
564 buf[5] |= MAX3107_MODE2_FIFORST_BIT;
565 s->tx_fifo_empty = 1;
566
567 /* 5. Configure FIFO trigger level register */
568 buf[6] = (MAX3107_WRITE_BIT | MAX3107_FIFOTRIGLVL_REG);
569 /* RX FIFO trigger for 16 words, TX FIFO trigger not used */
570 buf[6] |= (MAX3107_FIFOTRIGLVL_RX(16) | MAX3107_FIFOTRIGLVL_TX(0));
571
572 /* 6. Configure flow control levels */
573 buf[7] = (MAX3107_WRITE_BIT | MAX3107_FLOWLVL_REG);
574 /* Flow control halt level 96, resume level 48 */
575 buf[7] |= (MAX3107_FLOWLVL_RES(48) | MAX3107_FLOWLVL_HALT(96));
576
577 /* 7. Configure flow control */
578 buf[8] = (MAX3107_WRITE_BIT | MAX3107_FLOWCTRL_REG);
579 /* Enable auto CTS and auto RTS flow control */
580 buf[8] |= (MAX3107_FLOWCTRL_AUTOCTS_BIT | MAX3107_FLOWCTRL_AUTORTS_BIT);
581
582 /* 8. Configure RX timeout register */
583 buf[9] = (MAX3107_WRITE_BIT | MAX3107_RXTO_REG);
584 /* Timeout after 48 character intervals */
585 buf[9] |= 0x0030;
586
587 /* 9. Configure LSR interrupt enable register */
588 buf[10] = (MAX3107_WRITE_BIT | MAX3107_LSR_IRQEN_REG);
589 /* Enable RX timeout interrupt */
590 buf[10] |= MAX3107_LSR_RXTO_BIT;
591
592 /* Perform SPI transfer */
593 if (max3107_rw(s, (u8 *)buf, NULL, 22))
594 dev_err(&s->spi->dev, "SPI transfer for init failed\n");
595
596 /* 10. Clear IRQ status register by reading it */
597 buf[0] = MAX3107_IRQSTS_REG;
598
599 /* 11. Configure interrupt enable register */
600 /* Enable LSR interrupt */
601 s->irqen_reg = MAX3107_IRQ_LSR_BIT;
602 /* Enable RX FIFO interrupt */
603 s->irqen_reg |= MAX3107_IRQ_RXFIFO_BIT;
604 buf[1] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG)
605 | s->irqen_reg;
606
607 /* 12. Clear FIFO reset that was set in step 6 */
608 buf[2] = (MAX3107_WRITE_BIT | MAX3107_MODE2_REG);
609 if (s->loopback) {
610 /* Keep loopback enabled */
611 buf[2] |= MAX3107_MODE2_LOOPBACK_BIT;
612 }
613
614 /* Perform SPI transfer */
615 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 6))
616 dev_err(&s->spi->dev, "SPI transfer for init failed\n");
617
618}
619
620/* IRQ handler */
621static irqreturn_t max3107_irq(int irqno, void *dev_id)
622{
623 struct max3107_port *s = dev_id;
624
625 if (irqno != s->spi->irq) {
626 /* Unexpected IRQ */
627 return IRQ_NONE;
628 }
629
630 /* Indicate irq */
631 s->handle_irq = 1;
632
633 /* Trigger work thread */
634 max3107_dowork(s);
635
636 return IRQ_HANDLED;
637}
638
639/* HW suspension function
640 *
641 * Currently autosleep is used to decrease current consumption, alternative
642 * approach would be to set the chip to reset mode if UART is not being
643 * used but that would mess the GPIOs
644 *
645 */
646void max3107_hw_susp(struct max3107_port *s, int suspend)
647{
648 pr_debug("enter, suspend %d\n", suspend);
649
650 if (suspend) {
651 /* Suspend requested,
652 * enable autosleep to decrease current consumption
653 */
654 s->suspended = 1;
655 max3107_set_sleep(s, MAX3107_ENABLE_AUTOSLEEP);
656 } else {
657 /* Resume requested,
658 * disable autosleep
659 */
660 s->suspended = 0;
661 max3107_set_sleep(s, MAX3107_DISABLE_AUTOSLEEP);
662 }
663}
664EXPORT_SYMBOL_GPL(max3107_hw_susp);
665
666/* Modem status IRQ enabling */
667static void max3107_enable_ms(struct uart_port *port)
668{
669 /* Modem status not supported */
670}
671
672/* Data send function */
673static void max3107_start_tx(struct uart_port *port)
674{
675 struct max3107_port *s = container_of(port, struct max3107_port, port);
676
677 /* Trigger work thread for sending data */
678 max3107_dowork(s);
679}
680
681/* Function for checking that there is no pending transfers */
682static unsigned int max3107_tx_empty(struct uart_port *port)
683{
684 struct max3107_port *s = container_of(port, struct max3107_port, port);
685
686 pr_debug("returning %d\n",
687 (s->tx_fifo_empty && uart_circ_empty(&s->port.state->xmit)));
688 return s->tx_fifo_empty && uart_circ_empty(&s->port.state->xmit);
689}
690
691/* Function for stopping RX */
692static void max3107_stop_rx(struct uart_port *port)
693{
694 struct max3107_port *s = container_of(port, struct max3107_port, port);
695 unsigned long flags;
696
697 /* Set RX disabled in MODE 1 register */
698 spin_lock_irqsave(&s->data_lock, flags);
699 s->mode1_reg |= MAX3107_MODE1_RXDIS_BIT;
700 s->mode1_commit = 1;
701 spin_unlock_irqrestore(&s->data_lock, flags);
702 /* Set RX disabled */
703 s->rx_enabled = 0;
704 /* Trigger work thread for doing the actual configuration change */
705 max3107_dowork(s);
706}
707
708/* Function for returning control pin states */
709static unsigned int max3107_get_mctrl(struct uart_port *port)
710{
711 /* DCD and DSR are not wired and CTS/RTS is handled automatically
712 * so just indicate DSR and CAR asserted
713 */
714 return TIOCM_DSR | TIOCM_CAR;
715}
716
717/* Function for setting control pin states */
718static void max3107_set_mctrl(struct uart_port *port, unsigned int mctrl)
719{
720 /* DCD and DSR are not wired and CTS/RTS is hadnled automatically
721 * so do nothing
722 */
723}
724
725/* Function for configuring UART parameters */
726static void max3107_set_termios(struct uart_port *port,
727 struct ktermios *termios,
728 struct ktermios *old)
729{
730 struct max3107_port *s = container_of(port, struct max3107_port, port);
731 struct tty_struct *tty;
732 int baud;
733 u16 new_lcr = 0;
734 u32 new_brg = 0;
735 unsigned long flags;
736
737 if (!port->state)
738 return;
739
740 tty = port->state->port.tty;
741 if (!tty)
742 return;
743
744 /* Get new LCR register values */
745 /* Word size */
746 if ((termios->c_cflag & CSIZE) == CS7)
747 new_lcr |= MAX3107_LCR_WORD_LEN_7;
748 else
749 new_lcr |= MAX3107_LCR_WORD_LEN_8;
750
751 /* Parity */
752 if (termios->c_cflag & PARENB) {
753 new_lcr |= MAX3107_LCR_PARITY_BIT;
754 if (!(termios->c_cflag & PARODD))
755 new_lcr |= MAX3107_LCR_EVENPARITY_BIT;
756 }
757
758 /* Stop bits */
759 if (termios->c_cflag & CSTOPB) {
760 /* 2 stop bits */
761 new_lcr |= MAX3107_LCR_STOPLEN_BIT;
762 }
763
764 /* Mask termios capabilities we don't support */
765 termios->c_cflag &= ~CMSPAR;
766
767 /* Set status ignore mask */
768 s->port.ignore_status_mask = 0;
769 if (termios->c_iflag & IGNPAR)
770 s->port.ignore_status_mask |= MAX3107_ALL_ERRORS;
771
772 /* Set low latency to immediately handle pushed data */
773 s->port.state->port.tty->low_latency = 1;
774
775 /* Get new baud rate generator configuration */
776 baud = tty_get_baud_rate(tty);
777
778 spin_lock_irqsave(&s->data_lock, flags);
779 new_brg = get_new_brg(baud, s);
780 /* if can't find the corrent config, use previous */
781 if (!new_brg) {
782 baud = s->baud;
783 new_brg = s->brg_cfg;
784 }
785 spin_unlock_irqrestore(&s->data_lock, flags);
786 tty_termios_encode_baud_rate(termios, baud, baud);
787 s->baud = baud;
788
789 /* Update timeout according to new baud rate */
790 uart_update_timeout(port, termios->c_cflag, baud);
791
792 spin_lock_irqsave(&s->data_lock, flags);
793 if (s->lcr_reg != new_lcr) {
794 s->lcr_reg = new_lcr;
795 s->lcr_commit = 1;
796 }
797 if (s->brg_cfg != new_brg) {
798 s->brg_cfg = new_brg;
799 s->brg_commit = 1;
800 }
801 spin_unlock_irqrestore(&s->data_lock, flags);
802
803 /* Trigger work thread for doing the actual configuration change */
804 max3107_dowork(s);
805}
806
807/* Port shutdown function */
808static void max3107_shutdown(struct uart_port *port)
809{
810 struct max3107_port *s = container_of(port, struct max3107_port, port);
811
812 if (s->suspended && s->pdata->hw_suspend)
813 s->pdata->hw_suspend(s, 0);
814
815 /* Free the interrupt */
816 free_irq(s->spi->irq, s);
817
818 if (s->workqueue) {
819 /* Flush and destroy work queue */
820 flush_workqueue(s->workqueue);
821 destroy_workqueue(s->workqueue);
822 s->workqueue = NULL;
823 }
824
825 /* Suspend HW */
826 if (s->pdata->hw_suspend)
827 s->pdata->hw_suspend(s, 1);
828}
829
830/* Port startup function */
831static int max3107_startup(struct uart_port *port)
832{
833 struct max3107_port *s = container_of(port, struct max3107_port, port);
834
835 /* Initialize work queue */
836 s->workqueue = create_freezeable_workqueue("max3107");
837 if (!s->workqueue) {
838 dev_err(&s->spi->dev, "Workqueue creation failed\n");
839 return -EBUSY;
840 }
841 INIT_WORK(&s->work, max3107_work);
842
843 /* Setup IRQ */
844 if (request_irq(s->spi->irq, max3107_irq, IRQF_TRIGGER_FALLING,
845 "max3107", s)) {
846 dev_err(&s->spi->dev, "IRQ reguest failed\n");
847 destroy_workqueue(s->workqueue);
848 s->workqueue = NULL;
849 return -EBUSY;
850 }
851
852 /* Resume HW */
853 if (s->pdata->hw_suspend)
854 s->pdata->hw_suspend(s, 0);
855
856 /* Init registers */
857 max3107_register_init(s);
858
859 return 0;
860}
861
862/* Port type function */
863static const char *max3107_type(struct uart_port *port)
864{
865 struct max3107_port *s = container_of(port, struct max3107_port, port);
866 return s->spi->modalias;
867}
868
869/* Port release function */
870static void max3107_release_port(struct uart_port *port)
871{
872 /* Do nothing */
873}
874
875/* Port request function */
876static int max3107_request_port(struct uart_port *port)
877{
878 /* Do nothing */
879 return 0;
880}
881
882/* Port config function */
883static void max3107_config_port(struct uart_port *port, int flags)
884{
885 struct max3107_port *s = container_of(port, struct max3107_port, port);
886 s->port.type = PORT_MAX3107;
887}
888
889/* Port verify function */
890static int max3107_verify_port(struct uart_port *port,
891 struct serial_struct *ser)
892{
893 if (ser->type == PORT_UNKNOWN || ser->type == PORT_MAX3107)
894 return 0;
895
896 return -EINVAL;
897}
898
899/* Port stop TX function */
900static void max3107_stop_tx(struct uart_port *port)
901{
902 /* Do nothing */
903}
904
905/* Port break control function */
906static void max3107_break_ctl(struct uart_port *port, int break_state)
907{
908 /* We don't support break control, do nothing */
909}
910
911
912/* Port functions */
913static struct uart_ops max3107_ops = {
914 .tx_empty = max3107_tx_empty,
915 .set_mctrl = max3107_set_mctrl,
916 .get_mctrl = max3107_get_mctrl,
917 .stop_tx = max3107_stop_tx,
918 .start_tx = max3107_start_tx,
919 .stop_rx = max3107_stop_rx,
920 .enable_ms = max3107_enable_ms,
921 .break_ctl = max3107_break_ctl,
922 .startup = max3107_startup,
923 .shutdown = max3107_shutdown,
924 .set_termios = max3107_set_termios,
925 .type = max3107_type,
926 .release_port = max3107_release_port,
927 .request_port = max3107_request_port,
928 .config_port = max3107_config_port,
929 .verify_port = max3107_verify_port,
930};
931
932/* UART driver data */
933static struct uart_driver max3107_uart_driver = {
934 .owner = THIS_MODULE,
935 .driver_name = "ttyMAX",
936 .dev_name = "ttyMAX",
937 .nr = 1,
938};
939
940static int driver_registered = 0;
941
942
943
944/* 'Generic' platform data */
945static struct max3107_plat generic_plat_data = {
946 .loopback = 0,
947 .ext_clk = 1,
948 .hw_suspend = max3107_hw_susp,
949 .polled_mode = 0,
950 .poll_time = 0,
951};
952
953
954/*******************************************************************/
955
956/**
957 * max3107_probe - SPI bus probe entry point
958 * @spi: the spi device
959 *
960 * SPI wants us to probe this device and if appropriate claim it.
961 * Perform any platform specific requirements and then initialise
962 * the device.
963 */
964
965int max3107_probe(struct spi_device *spi, struct max3107_plat *pdata)
966{
967 struct max3107_port *s;
968 u16 buf[2]; /* Buffer for SPI transfers */
969 int retval;
970
971 pr_info("enter max3107 probe\n");
972
973 /* Allocate port structure */
974 s = kzalloc(sizeof(*s), GFP_KERNEL);
975 if (!s) {
976 pr_err("Allocating port structure failed\n");
977 return -ENOMEM;
978 }
979
980 s->pdata = pdata;
981
982 /* SPI Rx buffer
983 * +2 for RX FIFO interrupt
984 * disabling and RX level query
985 */
986 s->rxbuf = kzalloc(sizeof(u16) * (MAX3107_RX_FIFO_SIZE+2), GFP_KERNEL);
987 if (!s->rxbuf) {
988 pr_err("Allocating RX buffer failed\n");
989 return -ENOMEM;
990 }
991 s->rxstr = kzalloc(sizeof(u8) * MAX3107_RX_FIFO_SIZE, GFP_KERNEL);
992 if (!s->rxstr) {
993 pr_err("Allocating RX buffer failed\n");
994 return -ENOMEM;
995 }
996 /* SPI Tx buffer
997 * SPI transfer buffer
998 * +3 for TX FIFO empty
999 * interrupt disabling and
1000 * enabling and TX enabling
1001 */
1002 s->txbuf = kzalloc(sizeof(u16) * MAX3107_TX_FIFO_SIZE + 3, GFP_KERNEL);
1003 if (!s->txbuf) {
1004 pr_err("Allocating TX buffer failed\n");
1005 return -ENOMEM;
1006 }
1007 /* Initialize shared data lock */
1008 spin_lock_init(&s->data_lock);
1009
1010 /* SPI intializations */
1011 dev_set_drvdata(&spi->dev, s);
1012 spi->mode = SPI_MODE_0;
1013 spi->dev.platform_data = pdata;
1014 spi->bits_per_word = 16;
1015 s->ext_clk = pdata->ext_clk;
1016 s->loopback = pdata->loopback;
1017 spi_setup(spi);
1018 s->spi = spi;
1019
1020 /* Check REV ID to ensure we are talking to what we expect */
1021 buf[0] = MAX3107_REVID_REG;
1022 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
1023 dev_err(&s->spi->dev, "SPI transfer for REVID read failed\n");
1024 return -EIO;
1025 }
1026 if ((buf[0] & MAX3107_SPI_RX_DATA_MASK) != MAX3107_REVID1 &&
1027 (buf[0] & MAX3107_SPI_RX_DATA_MASK) != MAX3107_REVID2) {
1028 dev_err(&s->spi->dev, "REVID %x does not match\n",
1029 (buf[0] & MAX3107_SPI_RX_DATA_MASK));
1030 return -ENODEV;
1031 }
1032
1033 /* Disable all interrupts */
1034 buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG | 0x0000);
1035 buf[0] |= 0x0000;
1036
1037 /* Configure clock source */
1038 buf[1] = (MAX3107_WRITE_BIT | MAX3107_CLKSRC_REG);
1039 if (s->ext_clk) {
1040 /* External clock */
1041 buf[1] |= MAX3107_CLKSRC_EXTCLK_BIT;
1042 }
1043
1044 /* PLL bypass ON */
1045 buf[1] |= MAX3107_CLKSRC_PLLBYP_BIT;
1046
1047 /* Perform SPI transfer */
1048 if (max3107_rw(s, (u8 *)buf, NULL, 4)) {
1049 dev_err(&s->spi->dev, "SPI transfer for init failed\n");
1050 return -EIO;
1051 }
1052
1053 /* Register UART driver */
1054 if (!driver_registered) {
1055 retval = uart_register_driver(&max3107_uart_driver);
1056 if (retval) {
1057 dev_err(&s->spi->dev, "Registering UART driver failed\n");
1058 return retval;
1059 }
1060 driver_registered = 1;
1061 }
1062
1063 /* Initialize UART port data */
1064 s->port.fifosize = 128;
1065 s->port.ops = &max3107_ops;
1066 s->port.line = 0;
1067 s->port.dev = &spi->dev;
1068 s->port.uartclk = 9600;
1069 s->port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF;
1070 s->port.irq = s->spi->irq;
1071 s->port.type = PORT_MAX3107;
1072
1073 /* Add UART port */
1074 retval = uart_add_one_port(&max3107_uart_driver, &s->port);
1075 if (retval < 0) {
1076 dev_err(&s->spi->dev, "Adding UART port failed\n");
1077 return retval;
1078 }
1079
1080 if (pdata->configure) {
1081 retval = pdata->configure(s);
1082 if (retval < 0)
1083 return retval;
1084 }
1085
1086 /* Go to suspend mode */
1087 if (pdata->hw_suspend)
1088 pdata->hw_suspend(s, 1);
1089
1090 return 0;
1091}
1092EXPORT_SYMBOL_GPL(max3107_probe);
1093
1094/* Driver remove function */
1095int max3107_remove(struct spi_device *spi)
1096{
1097 struct max3107_port *s = dev_get_drvdata(&spi->dev);
1098
1099 pr_info("enter max3107 remove\n");
1100
1101 /* Remove port */
1102 if (uart_remove_one_port(&max3107_uart_driver, &s->port))
1103 dev_warn(&s->spi->dev, "Removing UART port failed\n");
1104
1105
1106 /* Free TxRx buffer */
1107 kfree(s->rxbuf);
1108 kfree(s->rxstr);
1109 kfree(s->txbuf);
1110
1111 /* Free port structure */
1112 kfree(s);
1113
1114 return 0;
1115}
1116EXPORT_SYMBOL_GPL(max3107_remove);
1117
1118/* Driver suspend function */
1119int max3107_suspend(struct spi_device *spi, pm_message_t state)
1120{
1121#ifdef CONFIG_PM
1122 struct max3107_port *s = dev_get_drvdata(&spi->dev);
1123
1124 pr_debug("enter suspend\n");
1125
1126 /* Suspend UART port */
1127 uart_suspend_port(&max3107_uart_driver, &s->port);
1128
1129 /* Go to suspend mode */
1130 if (s->pdata->hw_suspend)
1131 s->pdata->hw_suspend(s, 1);
1132#endif /* CONFIG_PM */
1133 return 0;
1134}
1135EXPORT_SYMBOL_GPL(max3107_suspend);
1136
1137/* Driver resume function */
1138int max3107_resume(struct spi_device *spi)
1139{
1140#ifdef CONFIG_PM
1141 struct max3107_port *s = dev_get_drvdata(&spi->dev);
1142
1143 pr_debug("enter resume\n");
1144
1145 /* Resume from suspend */
1146 if (s->pdata->hw_suspend)
1147 s->pdata->hw_suspend(s, 0);
1148
1149 /* Resume UART port */
1150 uart_resume_port(&max3107_uart_driver, &s->port);
1151#endif /* CONFIG_PM */
1152 return 0;
1153}
1154EXPORT_SYMBOL_GPL(max3107_resume);
1155
1156static int max3107_probe_generic(struct spi_device *spi)
1157{
1158 return max3107_probe(spi, &generic_plat_data);
1159}
1160
1161/* Spi driver data */
1162static struct spi_driver max3107_driver = {
1163 .driver = {
1164 .name = "max3107",
1165 .bus = &spi_bus_type,
1166 .owner = THIS_MODULE,
1167 },
1168 .probe = max3107_probe_generic,
1169 .remove = __devexit_p(max3107_remove),
1170 .suspend = max3107_suspend,
1171 .resume = max3107_resume,
1172};
1173
1174/* Driver init function */
1175static int __init max3107_init(void)
1176{
1177 pr_info("enter max3107 init\n");
1178 return spi_register_driver(&max3107_driver);
1179}
1180
1181/* Driver exit function */
1182static void __exit max3107_exit(void)
1183{
1184 pr_info("enter max3107 exit\n");
1185 /* Unregister UART driver */
1186 if (driver_registered)
1187 uart_unregister_driver(&max3107_uart_driver);
1188 spi_unregister_driver(&max3107_driver);
1189}
1190
1191module_init(max3107_init);
1192module_exit(max3107_exit);
1193
1194MODULE_DESCRIPTION("MAX3107 driver");
1195MODULE_AUTHOR("Aavamobile");
1196MODULE_ALIAS("max3107-spi");
1197MODULE_LICENSE("GPL v2");
diff --git a/drivers/serial/max3107.h b/drivers/serial/max3107.h
deleted file mode 100644
index 7ab632392502..000000000000
--- a/drivers/serial/max3107.h
+++ /dev/null
@@ -1,441 +0,0 @@
1/*
2 * max3107.h - spi uart protocol driver header for Maxim 3107
3 *
4 * Copyright (C) Aavamobile 2009
5 * Based on serial_max3100.h by Christian Pellegrin
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#ifndef _MAX3107_H
14#define _MAX3107_H
15
16/* Serial error status definitions */
17#define MAX3107_PARITY_ERROR 1
18#define MAX3107_FRAME_ERROR 2
19#define MAX3107_OVERRUN_ERROR 4
20#define MAX3107_ALL_ERRORS (MAX3107_PARITY_ERROR | \
21 MAX3107_FRAME_ERROR | \
22 MAX3107_OVERRUN_ERROR)
23
24/* GPIO definitions */
25#define MAX3107_GPIO_BASE 88
26#define MAX3107_GPIO_COUNT 4
27
28
29/* GPIO connected to chip's reset pin */
30#define MAX3107_RESET_GPIO 87
31
32
33/* Chip reset delay */
34#define MAX3107_RESET_DELAY 10
35
36/* Chip wakeup delay */
37#define MAX3107_WAKEUP_DELAY 50
38
39
40/* Sleep mode definitions */
41#define MAX3107_DISABLE_FORCED_SLEEP 0
42#define MAX3107_ENABLE_FORCED_SLEEP 1
43#define MAX3107_DISABLE_AUTOSLEEP 2
44#define MAX3107_ENABLE_AUTOSLEEP 3
45
46
47/* Definitions for register access with SPI transfers
48 *
49 * SPI transfer format:
50 *
51 * Master to slave bits xzzzzzzzyyyyyyyy
52 * Slave to master bits aaaaaaaabbbbbbbb
53 *
54 * where:
55 * x = 0 for reads, 1 for writes
56 * z = register address
57 * y = new register value if write, 0 if read
58 * a = unspecified
59 * b = register value if read, unspecified if write
60 */
61
62/* SPI speed */
63#define MAX3107_SPI_SPEED (3125000 * 2)
64
65/* Write bit */
66#define MAX3107_WRITE_BIT (1 << 15)
67
68/* SPI TX data mask */
69#define MAX3107_SPI_RX_DATA_MASK (0x00ff)
70
71/* SPI RX data mask */
72#define MAX3107_SPI_TX_DATA_MASK (0x00ff)
73
74/* Register access masks */
75#define MAX3107_RHR_REG (0x0000) /* RX FIFO */
76#define MAX3107_THR_REG (0x0000) /* TX FIFO */
77#define MAX3107_IRQEN_REG (0x0100) /* IRQ enable */
78#define MAX3107_IRQSTS_REG (0x0200) /* IRQ status */
79#define MAX3107_LSR_IRQEN_REG (0x0300) /* LSR IRQ enable */
80#define MAX3107_LSR_IRQSTS_REG (0x0400) /* LSR IRQ status */
81#define MAX3107_SPCHR_IRQEN_REG (0x0500) /* Special char IRQ enable */
82#define MAX3107_SPCHR_IRQSTS_REG (0x0600) /* Special char IRQ status */
83#define MAX3107_STS_IRQEN_REG (0x0700) /* Status IRQ enable */
84#define MAX3107_STS_IRQSTS_REG (0x0800) /* Status IRQ status */
85#define MAX3107_MODE1_REG (0x0900) /* MODE1 */
86#define MAX3107_MODE2_REG (0x0a00) /* MODE2 */
87#define MAX3107_LCR_REG (0x0b00) /* LCR */
88#define MAX3107_RXTO_REG (0x0c00) /* RX timeout */
89#define MAX3107_HDPIXDELAY_REG (0x0d00) /* Auto transceiver delays */
90#define MAX3107_IRDA_REG (0x0e00) /* IRDA settings */
91#define MAX3107_FLOWLVL_REG (0x0f00) /* Flow control levels */
92#define MAX3107_FIFOTRIGLVL_REG (0x1000) /* FIFO IRQ trigger levels */
93#define MAX3107_TXFIFOLVL_REG (0x1100) /* TX FIFO level */
94#define MAX3107_RXFIFOLVL_REG (0x1200) /* RX FIFO level */
95#define MAX3107_FLOWCTRL_REG (0x1300) /* Flow control */
96#define MAX3107_XON1_REG (0x1400) /* XON1 character */
97#define MAX3107_XON2_REG (0x1500) /* XON2 character */
98#define MAX3107_XOFF1_REG (0x1600) /* XOFF1 character */
99#define MAX3107_XOFF2_REG (0x1700) /* XOFF2 character */
100#define MAX3107_GPIOCFG_REG (0x1800) /* GPIO config */
101#define MAX3107_GPIODATA_REG (0x1900) /* GPIO data */
102#define MAX3107_PLLCFG_REG (0x1a00) /* PLL config */
103#define MAX3107_BRGCFG_REG (0x1b00) /* Baud rate generator conf */
104#define MAX3107_BRGDIVLSB_REG (0x1c00) /* Baud rate divisor LSB */
105#define MAX3107_BRGDIVMSB_REG (0x1d00) /* Baud rate divisor MSB */
106#define MAX3107_CLKSRC_REG (0x1e00) /* Clock source */
107#define MAX3107_REVID_REG (0x1f00) /* Revision identification */
108
109/* IRQ register bits */
110#define MAX3107_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */
111#define MAX3107_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */
112#define MAX3107_IRQ_STS_BIT (1 << 2) /* Status interrupt */
113#define MAX3107_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */
114#define MAX3107_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */
115#define MAX3107_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */
116#define MAX3107_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */
117#define MAX3107_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */
118
119/* LSR register bits */
120#define MAX3107_LSR_RXTO_BIT (1 << 0) /* RX timeout */
121#define MAX3107_LSR_RXOVR_BIT (1 << 1) /* RX overrun */
122#define MAX3107_LSR_RXPAR_BIT (1 << 2) /* RX parity error */
123#define MAX3107_LSR_FRERR_BIT (1 << 3) /* Frame error */
124#define MAX3107_LSR_RXBRK_BIT (1 << 4) /* RX break */
125#define MAX3107_LSR_RXNOISE_BIT (1 << 5) /* RX noise */
126#define MAX3107_LSR_UNDEF6_BIT (1 << 6) /* Undefined/not used */
127#define MAX3107_LSR_CTS_BIT (1 << 7) /* CTS pin state */
128
129/* Special character register bits */
130#define MAX3107_SPCHR_XON1_BIT (1 << 0) /* XON1 character */
131#define MAX3107_SPCHR_XON2_BIT (1 << 1) /* XON2 character */
132#define MAX3107_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */
133#define MAX3107_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */
134#define MAX3107_SPCHR_BREAK_BIT (1 << 4) /* RX break */
135#define MAX3107_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */
136#define MAX3107_SPCHR_UNDEF6_BIT (1 << 6) /* Undefined/not used */
137#define MAX3107_SPCHR_UNDEF7_BIT (1 << 7) /* Undefined/not used */
138
139/* Status register bits */
140#define MAX3107_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */
141#define MAX3107_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */
142#define MAX3107_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */
143#define MAX3107_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */
144#define MAX3107_STS_UNDEF4_BIT (1 << 4) /* Undefined/not used */
145#define MAX3107_STS_CLKREADY_BIT (1 << 5) /* Clock ready */
146#define MAX3107_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */
147#define MAX3107_STS_UNDEF7_BIT (1 << 7) /* Undefined/not used */
148
149/* MODE1 register bits */
150#define MAX3107_MODE1_RXDIS_BIT (1 << 0) /* RX disable */
151#define MAX3107_MODE1_TXDIS_BIT (1 << 1) /* TX disable */
152#define MAX3107_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */
153#define MAX3107_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */
154#define MAX3107_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */
155#define MAX3107_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */
156#define MAX3107_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */
157#define MAX3107_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */
158
159/* MODE2 register bits */
160#define MAX3107_MODE2_RST_BIT (1 << 0) /* Chip reset */
161#define MAX3107_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */
162#define MAX3107_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */
163#define MAX3107_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */
164#define MAX3107_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */
165#define MAX3107_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */
166#define MAX3107_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */
167#define MAX3107_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */
168
169/* LCR register bits */
170#define MAX3107_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
171#define MAX3107_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
172 *
173 * Word length bits table:
174 * 00 -> 5 bit words
175 * 01 -> 6 bit words
176 * 10 -> 7 bit words
177 * 11 -> 8 bit words
178 */
179#define MAX3107_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
180 *
181 * STOP length bit table:
182 * 0 -> 1 stop bit
183 * 1 -> 1-1.5 stop bits if
184 * word length is 5,
185 * 2 stop bits otherwise
186 */
187#define MAX3107_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
188#define MAX3107_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
189#define MAX3107_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
190#define MAX3107_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
191#define MAX3107_LCR_RTS_BIT (1 << 7) /* RTS pin control */
192#define MAX3107_LCR_WORD_LEN_5 (0x0000)
193#define MAX3107_LCR_WORD_LEN_6 (0x0001)
194#define MAX3107_LCR_WORD_LEN_7 (0x0002)
195#define MAX3107_LCR_WORD_LEN_8 (0x0003)
196
197
198/* IRDA register bits */
199#define MAX3107_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */
200#define MAX3107_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */
201#define MAX3107_IRDA_SHORTIR_BIT (1 << 2) /* Short SIR mode enable */
202#define MAX3107_IRDA_MIR_BIT (1 << 3) /* MIR mode enable */
203#define MAX3107_IRDA_RXINV_BIT (1 << 4) /* RX logic inversion enable */
204#define MAX3107_IRDA_TXINV_BIT (1 << 5) /* TX logic inversion enable */
205#define MAX3107_IRDA_UNDEF6_BIT (1 << 6) /* Undefined/not used */
206#define MAX3107_IRDA_UNDEF7_BIT (1 << 7) /* Undefined/not used */
207
208/* Flow control trigger level register masks */
209#define MAX3107_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */
210#define MAX3107_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */
211#define MAX3107_FLOWLVL_HALT(words) ((words/8) & 0x000f)
212#define MAX3107_FLOWLVL_RES(words) (((words/8) & 0x000f) << 4)
213
214/* FIFO interrupt trigger level register masks */
215#define MAX3107_FIFOTRIGLVL_TX_MASK (0x000f) /* TX FIFO trigger level */
216#define MAX3107_FIFOTRIGLVL_RX_MASK (0x00f0) /* RX FIFO trigger level */
217#define MAX3107_FIFOTRIGLVL_TX(words) ((words/8) & 0x000f)
218#define MAX3107_FIFOTRIGLVL_RX(words) (((words/8) & 0x000f) << 4)
219
220/* Flow control register bits */
221#define MAX3107_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */
222#define MAX3107_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */
223#define MAX3107_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs
224 * are used in conjunction with
225 * XOFF2 for definition of
226 * special character */
227#define MAX3107_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */
228#define MAX3107_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */
229#define MAX3107_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1
230 *
231 * SWFLOW bits 1 & 0 table:
232 * 00 -> no transmitter flow
233 * control
234 * 01 -> receiver compares
235 * XON2 and XOFF2
236 * and controls
237 * transmitter
238 * 10 -> receiver compares
239 * XON1 and XOFF1
240 * and controls
241 * transmitter
242 * 11 -> receiver compares
243 * XON1, XON2, XOFF1 and
244 * XOFF2 and controls
245 * transmitter
246 */
247#define MAX3107_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */
248#define MAX3107_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3
249 *
250 * SWFLOW bits 3 & 2 table:
251 * 00 -> no received flow
252 * control
253 * 01 -> transmitter generates
254 * XON2 and XOFF2
255 * 10 -> transmitter generates
256 * XON1 and XOFF1
257 * 11 -> transmitter generates
258 * XON1, XON2, XOFF1 and
259 * XOFF2
260 */
261
262/* GPIO configuration register bits */
263#define MAX3107_GPIOCFG_GP0OUT_BIT (1 << 0) /* GPIO 0 output enable */
264#define MAX3107_GPIOCFG_GP1OUT_BIT (1 << 1) /* GPIO 1 output enable */
265#define MAX3107_GPIOCFG_GP2OUT_BIT (1 << 2) /* GPIO 2 output enable */
266#define MAX3107_GPIOCFG_GP3OUT_BIT (1 << 3) /* GPIO 3 output enable */
267#define MAX3107_GPIOCFG_GP0OD_BIT (1 << 4) /* GPIO 0 open-drain enable */
268#define MAX3107_GPIOCFG_GP1OD_BIT (1 << 5) /* GPIO 1 open-drain enable */
269#define MAX3107_GPIOCFG_GP2OD_BIT (1 << 6) /* GPIO 2 open-drain enable */
270#define MAX3107_GPIOCFG_GP3OD_BIT (1 << 7) /* GPIO 3 open-drain enable */
271
272/* GPIO DATA register bits */
273#define MAX3107_GPIODATA_GP0OUT_BIT (1 << 0) /* GPIO 0 output value */
274#define MAX3107_GPIODATA_GP1OUT_BIT (1 << 1) /* GPIO 1 output value */
275#define MAX3107_GPIODATA_GP2OUT_BIT (1 << 2) /* GPIO 2 output value */
276#define MAX3107_GPIODATA_GP3OUT_BIT (1 << 3) /* GPIO 3 output value */
277#define MAX3107_GPIODATA_GP0IN_BIT (1 << 4) /* GPIO 0 input value */
278#define MAX3107_GPIODATA_GP1IN_BIT (1 << 5) /* GPIO 1 input value */
279#define MAX3107_GPIODATA_GP2IN_BIT (1 << 6) /* GPIO 2 input value */
280#define MAX3107_GPIODATA_GP3IN_BIT (1 << 7) /* GPIO 3 input value */
281
282/* PLL configuration register masks */
283#define MAX3107_PLLCFG_PREDIV_MASK (0x003f) /* PLL predivision value */
284#define MAX3107_PLLCFG_PLLFACTOR_MASK (0x00c0) /* PLL multiplication factor */
285
286/* Baud rate generator configuration register masks and bits */
287#define MAX3107_BRGCFG_FRACT_MASK (0x000f) /* Fractional portion of
288 * Baud rate generator divisor
289 */
290#define MAX3107_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */
291#define MAX3107_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */
292#define MAX3107_BRGCFG_UNDEF6_BIT (1 << 6) /* Undefined/not used */
293#define MAX3107_BRGCFG_UNDEF7_BIT (1 << 7) /* Undefined/not used */
294
295/* Clock source register bits */
296#define MAX3107_CLKSRC_INTOSC_BIT (1 << 0) /* Internal osc enable */
297#define MAX3107_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */
298#define MAX3107_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */
299#define MAX3107_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */
300#define MAX3107_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */
301#define MAX3107_CLKSRC_UNDEF5_BIT (1 << 5) /* Undefined/not used */
302#define MAX3107_CLKSRC_UNDEF6_BIT (1 << 6) /* Undefined/not used */
303#define MAX3107_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */
304
305
306/* HW definitions */
307#define MAX3107_RX_FIFO_SIZE 128
308#define MAX3107_TX_FIFO_SIZE 128
309#define MAX3107_REVID1 0x00a0
310#define MAX3107_REVID2 0x00a1
311
312
313/* Baud rate generator configuration values for external clock 13MHz */
314#define MAX3107_BRG13_B300 (0x0A9400 | 0x05)
315#define MAX3107_BRG13_B600 (0x054A00 | 0x03)
316#define MAX3107_BRG13_B1200 (0x02A500 | 0x01)
317#define MAX3107_BRG13_B2400 (0x015200 | 0x09)
318#define MAX3107_BRG13_B4800 (0x00A900 | 0x04)
319#define MAX3107_BRG13_B9600 (0x005400 | 0x0A)
320#define MAX3107_BRG13_B19200 (0x002A00 | 0x05)
321#define MAX3107_BRG13_B38400 (0x001500 | 0x03)
322#define MAX3107_BRG13_B57600 (0x000E00 | 0x02)
323#define MAX3107_BRG13_B115200 (0x000700 | 0x01)
324#define MAX3107_BRG13_B230400 (0x000300 | 0x08)
325#define MAX3107_BRG13_B460800 (0x000100 | 0x0c)
326#define MAX3107_BRG13_B921600 (0x000100 | 0x1c)
327
328/* Baud rate generator configuration values for external clock 26MHz */
329#define MAX3107_BRG26_B300 (0x152800 | 0x0A)
330#define MAX3107_BRG26_B600 (0x0A9400 | 0x05)
331#define MAX3107_BRG26_B1200 (0x054A00 | 0x03)
332#define MAX3107_BRG26_B2400 (0x02A500 | 0x01)
333#define MAX3107_BRG26_B4800 (0x015200 | 0x09)
334#define MAX3107_BRG26_B9600 (0x00A900 | 0x04)
335#define MAX3107_BRG26_B19200 (0x005400 | 0x0A)
336#define MAX3107_BRG26_B38400 (0x002A00 | 0x05)
337#define MAX3107_BRG26_B57600 (0x001C00 | 0x03)
338#define MAX3107_BRG26_B115200 (0x000E00 | 0x02)
339#define MAX3107_BRG26_B230400 (0x000700 | 0x01)
340#define MAX3107_BRG26_B460800 (0x000300 | 0x08)
341#define MAX3107_BRG26_B921600 (0x000100 | 0x0C)
342
343/* Baud rate generator configuration values for internal clock */
344#define MAX3107_BRG13_IB300 (0x008000 | 0x00)
345#define MAX3107_BRG13_IB600 (0x004000 | 0x00)
346#define MAX3107_BRG13_IB1200 (0x002000 | 0x00)
347#define MAX3107_BRG13_IB2400 (0x001000 | 0x00)
348#define MAX3107_BRG13_IB4800 (0x000800 | 0x00)
349#define MAX3107_BRG13_IB9600 (0x000400 | 0x00)
350#define MAX3107_BRG13_IB19200 (0x000200 | 0x00)
351#define MAX3107_BRG13_IB38400 (0x000100 | 0x00)
352#define MAX3107_BRG13_IB57600 (0x000000 | 0x0B)
353#define MAX3107_BRG13_IB115200 (0x000000 | 0x05)
354#define MAX3107_BRG13_IB230400 (0x000000 | 0x03)
355#define MAX3107_BRG13_IB460800 (0x000000 | 0x00)
356#define MAX3107_BRG13_IB921600 (0x000000 | 0x00)
357
358
359struct baud_table {
360 int baud;
361 u32 new_brg;
362};
363
364struct max3107_port {
365 /* UART port structure */
366 struct uart_port port;
367
368 /* SPI device structure */
369 struct spi_device *spi;
370
371#if defined(CONFIG_GPIOLIB)
372 /* GPIO chip stucture */
373 struct gpio_chip chip;
374#endif
375
376 /* Workqueue that does all the magic */
377 struct workqueue_struct *workqueue;
378 struct work_struct work;
379
380 /* Lock for shared data */
381 spinlock_t data_lock;
382
383 /* Device configuration */
384 int ext_clk; /* 1 if external clock used */
385 int loopback; /* Current loopback mode state */
386 int baud; /* Current baud rate */
387
388 /* State flags */
389 int suspended; /* Indicates suspend mode */
390 int tx_fifo_empty; /* Flag for TX FIFO state */
391 int rx_enabled; /* Flag for receiver state */
392 int tx_enabled; /* Flag for transmitter state */
393
394 u16 irqen_reg; /* Current IRQ enable register value */
395 /* Shared data */
396 u16 mode1_reg; /* Current mode1 register value*/
397 int mode1_commit; /* Flag for setting new mode1 register value */
398 u16 lcr_reg; /* Current LCR register value */
399 int lcr_commit; /* Flag for setting new LCR register value */
400 u32 brg_cfg; /* Current Baud rate generator config */
401 int brg_commit; /* Flag for setting new baud rate generator
402 * config
403 */
404 struct baud_table *baud_tbl;
405 int handle_irq; /* Indicates that IRQ should be handled */
406
407 /* Rx buffer and str*/
408 u16 *rxbuf;
409 u8 *rxstr;
410 /* Tx buffer*/
411 u16 *txbuf;
412
413 struct max3107_plat *pdata; /* Platform data */
414};
415
416/* Platform data structure */
417struct max3107_plat {
418 /* Loopback mode enable */
419 int loopback;
420 /* External clock enable */
421 int ext_clk;
422 /* Called during the register initialisation */
423 void (*init)(struct max3107_port *s);
424 /* Called when the port is found and configured */
425 int (*configure)(struct max3107_port *s);
426 /* HW suspend function */
427 void (*hw_suspend) (struct max3107_port *s, int suspend);
428 /* Polling mode enable */
429 int polled_mode;
430 /* Polling period if polling mode enabled */
431 int poll_time;
432};
433
434extern int max3107_rw(struct max3107_port *s, u8 *tx, u8 *rx, int len);
435extern void max3107_hw_susp(struct max3107_port *s, int suspend);
436extern int max3107_probe(struct spi_device *spi, struct max3107_plat *pdata);
437extern int max3107_remove(struct spi_device *spi);
438extern int max3107_suspend(struct spi_device *spi, pm_message_t state);
439extern int max3107_resume(struct spi_device *spi);
440
441#endif /* _LINUX_SERIAL_MAX3107_H */
diff --git a/drivers/serial/mcf.c b/drivers/serial/mcf.c
deleted file mode 100644
index 3394b7cc1722..000000000000
--- a/drivers/serial/mcf.c
+++ /dev/null
@@ -1,662 +0,0 @@
1/****************************************************************************/
2
3/*
4 * mcf.c -- Freescale ColdFire UART driver
5 *
6 * (C) Copyright 2003-2007, Greg Ungerer <gerg@snapgear.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14/****************************************************************************/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/interrupt.h>
19#include <linux/module.h>
20#include <linux/console.h>
21#include <linux/tty.h>
22#include <linux/tty_flip.h>
23#include <linux/serial.h>
24#include <linux/serial_core.h>
25#include <linux/io.h>
26#include <asm/coldfire.h>
27#include <asm/mcfsim.h>
28#include <asm/mcfuart.h>
29#include <asm/nettel.h>
30
31/****************************************************************************/
32
33/*
34 * Some boards implement the DTR/DCD lines using GPIO lines, most
35 * don't. Dummy out the access macros for those that don't. Those
36 * that do should define these macros somewhere in there board
37 * specific inlude files.
38 */
39#if !defined(mcf_getppdcd)
40#define mcf_getppdcd(p) (1)
41#endif
42#if !defined(mcf_getppdtr)
43#define mcf_getppdtr(p) (1)
44#endif
45#if !defined(mcf_setppdtr)
46#define mcf_setppdtr(p, v) do { } while (0)
47#endif
48
49/****************************************************************************/
50
51/*
52 * Local per-uart structure.
53 */
54struct mcf_uart {
55 struct uart_port port;
56 unsigned int sigs; /* Local copy of line sigs */
57 unsigned char imr; /* Local IMR mirror */
58};
59
60/****************************************************************************/
61
62static unsigned int mcf_tx_empty(struct uart_port *port)
63{
64 return (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXEMPTY) ?
65 TIOCSER_TEMT : 0;
66}
67
68/****************************************************************************/
69
70static unsigned int mcf_get_mctrl(struct uart_port *port)
71{
72 struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
73 unsigned int sigs;
74
75 sigs = (readb(port->membase + MCFUART_UIPR) & MCFUART_UIPR_CTS) ?
76 0 : TIOCM_CTS;
77 sigs |= (pp->sigs & TIOCM_RTS);
78 sigs |= (mcf_getppdcd(port->line) ? TIOCM_CD : 0);
79 sigs |= (mcf_getppdtr(port->line) ? TIOCM_DTR : 0);
80
81 return sigs;
82}
83
84/****************************************************************************/
85
86static void mcf_set_mctrl(struct uart_port *port, unsigned int sigs)
87{
88 struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
89
90 pp->sigs = sigs;
91 mcf_setppdtr(port->line, (sigs & TIOCM_DTR));
92 if (sigs & TIOCM_RTS)
93 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1);
94 else
95 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP0);
96}
97
98/****************************************************************************/
99
100static void mcf_start_tx(struct uart_port *port)
101{
102 struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
103
104 pp->imr |= MCFUART_UIR_TXREADY;
105 writeb(pp->imr, port->membase + MCFUART_UIMR);
106}
107
108/****************************************************************************/
109
110static void mcf_stop_tx(struct uart_port *port)
111{
112 struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
113
114 pp->imr &= ~MCFUART_UIR_TXREADY;
115 writeb(pp->imr, port->membase + MCFUART_UIMR);
116}
117
118/****************************************************************************/
119
120static void mcf_stop_rx(struct uart_port *port)
121{
122 struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
123
124 pp->imr &= ~MCFUART_UIR_RXREADY;
125 writeb(pp->imr, port->membase + MCFUART_UIMR);
126}
127
128/****************************************************************************/
129
130static void mcf_break_ctl(struct uart_port *port, int break_state)
131{
132 unsigned long flags;
133
134 spin_lock_irqsave(&port->lock, flags);
135 if (break_state == -1)
136 writeb(MCFUART_UCR_CMDBREAKSTART, port->membase + MCFUART_UCR);
137 else
138 writeb(MCFUART_UCR_CMDBREAKSTOP, port->membase + MCFUART_UCR);
139 spin_unlock_irqrestore(&port->lock, flags);
140}
141
142/****************************************************************************/
143
144static void mcf_enable_ms(struct uart_port *port)
145{
146}
147
148/****************************************************************************/
149
150static int mcf_startup(struct uart_port *port)
151{
152 struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
153 unsigned long flags;
154
155 spin_lock_irqsave(&port->lock, flags);
156
157 /* Reset UART, get it into known state... */
158 writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
159 writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
160
161 /* Enable the UART transmitter and receiver */
162 writeb(MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE,
163 port->membase + MCFUART_UCR);
164
165 /* Enable RX interrupts now */
166 pp->imr = MCFUART_UIR_RXREADY;
167 writeb(pp->imr, port->membase + MCFUART_UIMR);
168
169 spin_unlock_irqrestore(&port->lock, flags);
170
171 return 0;
172}
173
174/****************************************************************************/
175
176static void mcf_shutdown(struct uart_port *port)
177{
178 struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
179 unsigned long flags;
180
181 spin_lock_irqsave(&port->lock, flags);
182
183 /* Disable all interrupts now */
184 pp->imr = 0;
185 writeb(pp->imr, port->membase + MCFUART_UIMR);
186
187 /* Disable UART transmitter and receiver */
188 writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
189 writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
190
191 spin_unlock_irqrestore(&port->lock, flags);
192}
193
194/****************************************************************************/
195
196static void mcf_set_termios(struct uart_port *port, struct ktermios *termios,
197 struct ktermios *old)
198{
199 unsigned long flags;
200 unsigned int baud, baudclk;
201#if defined(CONFIG_M5272)
202 unsigned int baudfr;
203#endif
204 unsigned char mr1, mr2;
205
206 baud = uart_get_baud_rate(port, termios, old, 0, 230400);
207#if defined(CONFIG_M5272)
208 baudclk = (MCF_BUSCLK / baud) / 32;
209 baudfr = (((MCF_BUSCLK / baud) + 1) / 2) % 16;
210#else
211 baudclk = ((MCF_BUSCLK / baud) + 16) / 32;
212#endif
213
214 mr1 = MCFUART_MR1_RXIRQRDY | MCFUART_MR1_RXERRCHAR;
215 mr2 = 0;
216
217 switch (termios->c_cflag & CSIZE) {
218 case CS5: mr1 |= MCFUART_MR1_CS5; break;
219 case CS6: mr1 |= MCFUART_MR1_CS6; break;
220 case CS7: mr1 |= MCFUART_MR1_CS7; break;
221 case CS8:
222 default: mr1 |= MCFUART_MR1_CS8; break;
223 }
224
225 if (termios->c_cflag & PARENB) {
226 if (termios->c_cflag & CMSPAR) {
227 if (termios->c_cflag & PARODD)
228 mr1 |= MCFUART_MR1_PARITYMARK;
229 else
230 mr1 |= MCFUART_MR1_PARITYSPACE;
231 } else {
232 if (termios->c_cflag & PARODD)
233 mr1 |= MCFUART_MR1_PARITYODD;
234 else
235 mr1 |= MCFUART_MR1_PARITYEVEN;
236 }
237 } else {
238 mr1 |= MCFUART_MR1_PARITYNONE;
239 }
240
241 if (termios->c_cflag & CSTOPB)
242 mr2 |= MCFUART_MR2_STOP2;
243 else
244 mr2 |= MCFUART_MR2_STOP1;
245
246 if (termios->c_cflag & CRTSCTS) {
247 mr1 |= MCFUART_MR1_RXRTS;
248 mr2 |= MCFUART_MR2_TXCTS;
249 }
250
251 spin_lock_irqsave(&port->lock, flags);
252 uart_update_timeout(port, termios->c_cflag, baud);
253 writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
254 writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
255 writeb(MCFUART_UCR_CMDRESETMRPTR, port->membase + MCFUART_UCR);
256 writeb(mr1, port->membase + MCFUART_UMR);
257 writeb(mr2, port->membase + MCFUART_UMR);
258 writeb((baudclk & 0xff00) >> 8, port->membase + MCFUART_UBG1);
259 writeb((baudclk & 0xff), port->membase + MCFUART_UBG2);
260#if defined(CONFIG_M5272)
261 writeb((baudfr & 0x0f), port->membase + MCFUART_UFPD);
262#endif
263 writeb(MCFUART_UCSR_RXCLKTIMER | MCFUART_UCSR_TXCLKTIMER,
264 port->membase + MCFUART_UCSR);
265 writeb(MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE,
266 port->membase + MCFUART_UCR);
267 spin_unlock_irqrestore(&port->lock, flags);
268}
269
270/****************************************************************************/
271
272static void mcf_rx_chars(struct mcf_uart *pp)
273{
274 struct uart_port *port = &pp->port;
275 unsigned char status, ch, flag;
276
277 while ((status = readb(port->membase + MCFUART_USR)) & MCFUART_USR_RXREADY) {
278 ch = readb(port->membase + MCFUART_URB);
279 flag = TTY_NORMAL;
280 port->icount.rx++;
281
282 if (status & MCFUART_USR_RXERR) {
283 writeb(MCFUART_UCR_CMDRESETERR,
284 port->membase + MCFUART_UCR);
285
286 if (status & MCFUART_USR_RXBREAK) {
287 port->icount.brk++;
288 if (uart_handle_break(port))
289 continue;
290 } else if (status & MCFUART_USR_RXPARITY) {
291 port->icount.parity++;
292 } else if (status & MCFUART_USR_RXOVERRUN) {
293 port->icount.overrun++;
294 } else if (status & MCFUART_USR_RXFRAMING) {
295 port->icount.frame++;
296 }
297
298 status &= port->read_status_mask;
299
300 if (status & MCFUART_USR_RXBREAK)
301 flag = TTY_BREAK;
302 else if (status & MCFUART_USR_RXPARITY)
303 flag = TTY_PARITY;
304 else if (status & MCFUART_USR_RXFRAMING)
305 flag = TTY_FRAME;
306 }
307
308 if (uart_handle_sysrq_char(port, ch))
309 continue;
310 uart_insert_char(port, status, MCFUART_USR_RXOVERRUN, ch, flag);
311 }
312
313 tty_flip_buffer_push(port->state->port.tty);
314}
315
316/****************************************************************************/
317
318static void mcf_tx_chars(struct mcf_uart *pp)
319{
320 struct uart_port *port = &pp->port;
321 struct circ_buf *xmit = &port->state->xmit;
322
323 if (port->x_char) {
324 /* Send special char - probably flow control */
325 writeb(port->x_char, port->membase + MCFUART_UTB);
326 port->x_char = 0;
327 port->icount.tx++;
328 return;
329 }
330
331 while (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY) {
332 if (xmit->head == xmit->tail)
333 break;
334 writeb(xmit->buf[xmit->tail], port->membase + MCFUART_UTB);
335 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1);
336 port->icount.tx++;
337 }
338
339 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
340 uart_write_wakeup(port);
341
342 if (xmit->head == xmit->tail) {
343 pp->imr &= ~MCFUART_UIR_TXREADY;
344 writeb(pp->imr, port->membase + MCFUART_UIMR);
345 }
346}
347
348/****************************************************************************/
349
350static irqreturn_t mcf_interrupt(int irq, void *data)
351{
352 struct uart_port *port = data;
353 struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
354 unsigned int isr;
355 irqreturn_t ret = IRQ_NONE;
356
357 isr = readb(port->membase + MCFUART_UISR) & pp->imr;
358
359 spin_lock(&port->lock);
360 if (isr & MCFUART_UIR_RXREADY) {
361 mcf_rx_chars(pp);
362 ret = IRQ_HANDLED;
363 }
364 if (isr & MCFUART_UIR_TXREADY) {
365 mcf_tx_chars(pp);
366 ret = IRQ_HANDLED;
367 }
368 spin_unlock(&port->lock);
369
370 return ret;
371}
372
373/****************************************************************************/
374
375static void mcf_config_port(struct uart_port *port, int flags)
376{
377 port->type = PORT_MCF;
378 port->fifosize = MCFUART_TXFIFOSIZE;
379
380 /* Clear mask, so no surprise interrupts. */
381 writeb(0, port->membase + MCFUART_UIMR);
382
383 if (request_irq(port->irq, mcf_interrupt, IRQF_DISABLED, "UART", port))
384 printk(KERN_ERR "MCF: unable to attach ColdFire UART %d "
385 "interrupt vector=%d\n", port->line, port->irq);
386}
387
388/****************************************************************************/
389
390static const char *mcf_type(struct uart_port *port)
391{
392 return (port->type == PORT_MCF) ? "ColdFire UART" : NULL;
393}
394
395/****************************************************************************/
396
397static int mcf_request_port(struct uart_port *port)
398{
399 /* UARTs always present */
400 return 0;
401}
402
403/****************************************************************************/
404
405static void mcf_release_port(struct uart_port *port)
406{
407 /* Nothing to release... */
408}
409
410/****************************************************************************/
411
412static int mcf_verify_port(struct uart_port *port, struct serial_struct *ser)
413{
414 if ((ser->type != PORT_UNKNOWN) && (ser->type != PORT_MCF))
415 return -EINVAL;
416 return 0;
417}
418
419/****************************************************************************/
420
421/*
422 * Define the basic serial functions we support.
423 */
424static const struct uart_ops mcf_uart_ops = {
425 .tx_empty = mcf_tx_empty,
426 .get_mctrl = mcf_get_mctrl,
427 .set_mctrl = mcf_set_mctrl,
428 .start_tx = mcf_start_tx,
429 .stop_tx = mcf_stop_tx,
430 .stop_rx = mcf_stop_rx,
431 .enable_ms = mcf_enable_ms,
432 .break_ctl = mcf_break_ctl,
433 .startup = mcf_startup,
434 .shutdown = mcf_shutdown,
435 .set_termios = mcf_set_termios,
436 .type = mcf_type,
437 .request_port = mcf_request_port,
438 .release_port = mcf_release_port,
439 .config_port = mcf_config_port,
440 .verify_port = mcf_verify_port,
441};
442
443static struct mcf_uart mcf_ports[4];
444
445#define MCF_MAXPORTS ARRAY_SIZE(mcf_ports)
446
447/****************************************************************************/
448#if defined(CONFIG_SERIAL_MCF_CONSOLE)
449/****************************************************************************/
450
451int __init early_mcf_setup(struct mcf_platform_uart *platp)
452{
453 struct uart_port *port;
454 int i;
455
456 for (i = 0; ((i < MCF_MAXPORTS) && (platp[i].mapbase)); i++) {
457 port = &mcf_ports[i].port;
458
459 port->line = i;
460 port->type = PORT_MCF;
461 port->mapbase = platp[i].mapbase;
462 port->membase = (platp[i].membase) ? platp[i].membase :
463 (unsigned char __iomem *) port->mapbase;
464 port->iotype = SERIAL_IO_MEM;
465 port->irq = platp[i].irq;
466 port->uartclk = MCF_BUSCLK;
467 port->flags = ASYNC_BOOT_AUTOCONF;
468 port->ops = &mcf_uart_ops;
469 }
470
471 return 0;
472}
473
474/****************************************************************************/
475
476static void mcf_console_putc(struct console *co, const char c)
477{
478 struct uart_port *port = &(mcf_ports + co->index)->port;
479 int i;
480
481 for (i = 0; (i < 0x10000); i++) {
482 if (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY)
483 break;
484 }
485 writeb(c, port->membase + MCFUART_UTB);
486 for (i = 0; (i < 0x10000); i++) {
487 if (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY)
488 break;
489 }
490}
491
492/****************************************************************************/
493
494static void mcf_console_write(struct console *co, const char *s, unsigned int count)
495{
496 for (; (count); count--, s++) {
497 mcf_console_putc(co, *s);
498 if (*s == '\n')
499 mcf_console_putc(co, '\r');
500 }
501}
502
503/****************************************************************************/
504
505static int __init mcf_console_setup(struct console *co, char *options)
506{
507 struct uart_port *port;
508 int baud = CONFIG_SERIAL_MCF_BAUDRATE;
509 int bits = 8;
510 int parity = 'n';
511 int flow = 'n';
512
513 if ((co->index < 0) || (co->index >= MCF_MAXPORTS))
514 co->index = 0;
515 port = &mcf_ports[co->index].port;
516 if (port->membase == 0)
517 return -ENODEV;
518
519 if (options)
520 uart_parse_options(options, &baud, &parity, &bits, &flow);
521
522 return uart_set_options(port, co, baud, parity, bits, flow);
523}
524
525/****************************************************************************/
526
527static struct uart_driver mcf_driver;
528
529static struct console mcf_console = {
530 .name = "ttyS",
531 .write = mcf_console_write,
532 .device = uart_console_device,
533 .setup = mcf_console_setup,
534 .flags = CON_PRINTBUFFER,
535 .index = -1,
536 .data = &mcf_driver,
537};
538
539static int __init mcf_console_init(void)
540{
541 register_console(&mcf_console);
542 return 0;
543}
544
545console_initcall(mcf_console_init);
546
547#define MCF_CONSOLE &mcf_console
548
549/****************************************************************************/
550#else
551/****************************************************************************/
552
553#define MCF_CONSOLE NULL
554
555/****************************************************************************/
556#endif /* CONFIG_MCF_CONSOLE */
557/****************************************************************************/
558
559/*
560 * Define the mcf UART driver structure.
561 */
562static struct uart_driver mcf_driver = {
563 .owner = THIS_MODULE,
564 .driver_name = "mcf",
565 .dev_name = "ttyS",
566 .major = TTY_MAJOR,
567 .minor = 64,
568 .nr = MCF_MAXPORTS,
569 .cons = MCF_CONSOLE,
570};
571
572/****************************************************************************/
573
574static int __devinit mcf_probe(struct platform_device *pdev)
575{
576 struct mcf_platform_uart *platp = pdev->dev.platform_data;
577 struct uart_port *port;
578 int i;
579
580 for (i = 0; ((i < MCF_MAXPORTS) && (platp[i].mapbase)); i++) {
581 port = &mcf_ports[i].port;
582
583 port->line = i;
584 port->type = PORT_MCF;
585 port->mapbase = platp[i].mapbase;
586 port->membase = (platp[i].membase) ? platp[i].membase :
587 (unsigned char __iomem *) platp[i].mapbase;
588 port->iotype = SERIAL_IO_MEM;
589 port->irq = platp[i].irq;
590 port->uartclk = MCF_BUSCLK;
591 port->ops = &mcf_uart_ops;
592 port->flags = ASYNC_BOOT_AUTOCONF;
593
594 uart_add_one_port(&mcf_driver, port);
595 }
596
597 return 0;
598}
599
600/****************************************************************************/
601
602static int __devexit mcf_remove(struct platform_device *pdev)
603{
604 struct uart_port *port;
605 int i;
606
607 for (i = 0; (i < MCF_MAXPORTS); i++) {
608 port = &mcf_ports[i].port;
609 if (port)
610 uart_remove_one_port(&mcf_driver, port);
611 }
612
613 return 0;
614}
615
616/****************************************************************************/
617
618static struct platform_driver mcf_platform_driver = {
619 .probe = mcf_probe,
620 .remove = __devexit_p(mcf_remove),
621 .driver = {
622 .name = "mcfuart",
623 .owner = THIS_MODULE,
624 },
625};
626
627/****************************************************************************/
628
629static int __init mcf_init(void)
630{
631 int rc;
632
633 printk("ColdFire internal UART serial driver\n");
634
635 rc = uart_register_driver(&mcf_driver);
636 if (rc)
637 return rc;
638 rc = platform_driver_register(&mcf_platform_driver);
639 if (rc)
640 return rc;
641 return 0;
642}
643
644/****************************************************************************/
645
646static void __exit mcf_exit(void)
647{
648 platform_driver_unregister(&mcf_platform_driver);
649 uart_unregister_driver(&mcf_driver);
650}
651
652/****************************************************************************/
653
654module_init(mcf_init);
655module_exit(mcf_exit);
656
657MODULE_AUTHOR("Greg Ungerer <gerg@snapgear.com>");
658MODULE_DESCRIPTION("Freescale ColdFire UART driver");
659MODULE_LICENSE("GPL");
660MODULE_ALIAS("platform:mcfuart");
661
662/****************************************************************************/
diff --git a/drivers/serial/mfd.c b/drivers/serial/mfd.c
deleted file mode 100644
index 5dff45c76d32..000000000000
--- a/drivers/serial/mfd.c
+++ /dev/null
@@ -1,1500 +0,0 @@
1/*
2 * mfd.c: driver for High Speed UART device of Intel Medfield platform
3 *
4 * Refer pxa.c, 8250.c and some other drivers in drivers/serial/
5 *
6 * (C) Copyright 2010 Intel Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; version 2
11 * of the License.
12 */
13
14/* Notes:
15 * 1. DMA channel allocation: 0/1 channel are assigned to port 0,
16 * 2/3 chan to port 1, 4/5 chan to port 3. Even number chans
17 * are used for RX, odd chans for TX
18 *
19 * 2. In A0 stepping, UART will not support TX half empty flag
20 *
21 * 3. The RI/DSR/DCD/DTR are not pinned out, DCD & DSR are always
22 * asserted, only when the HW is reset the DDCD and DDSR will
23 * be triggered
24 */
25
26#include <linux/module.h>
27#include <linux/init.h>
28#include <linux/console.h>
29#include <linux/sysrq.h>
30#include <linux/slab.h>
31#include <linux/serial_reg.h>
32#include <linux/circ_buf.h>
33#include <linux/delay.h>
34#include <linux/interrupt.h>
35#include <linux/tty.h>
36#include <linux/tty_flip.h>
37#include <linux/serial_core.h>
38#include <linux/serial_mfd.h>
39#include <linux/dma-mapping.h>
40#include <linux/pci.h>
41#include <linux/io.h>
42#include <linux/debugfs.h>
43
44#define MFD_HSU_A0_STEPPING 1
45
46#define HSU_DMA_BUF_SIZE 2048
47
48#define chan_readl(chan, offset) readl(chan->reg + offset)
49#define chan_writel(chan, offset, val) writel(val, chan->reg + offset)
50
51#define mfd_readl(obj, offset) readl(obj->reg + offset)
52#define mfd_writel(obj, offset, val) writel(val, obj->reg + offset)
53
54#define HSU_DMA_TIMEOUT_CHECK_FREQ (HZ/10)
55
56struct hsu_dma_buffer {
57 u8 *buf;
58 dma_addr_t dma_addr;
59 u32 dma_size;
60 u32 ofs;
61};
62
63struct hsu_dma_chan {
64 u32 id;
65 enum dma_data_direction dirt;
66 struct uart_hsu_port *uport;
67 void __iomem *reg;
68 struct timer_list rx_timer; /* only needed by RX channel */
69};
70
71struct uart_hsu_port {
72 struct uart_port port;
73 unsigned char ier;
74 unsigned char lcr;
75 unsigned char mcr;
76 unsigned int lsr_break_flag;
77 char name[12];
78 int index;
79 struct device *dev;
80
81 struct hsu_dma_chan *txc;
82 struct hsu_dma_chan *rxc;
83 struct hsu_dma_buffer txbuf;
84 struct hsu_dma_buffer rxbuf;
85 int use_dma; /* flag for DMA/PIO */
86 int running;
87 int dma_tx_on;
88};
89
90/* Top level data structure of HSU */
91struct hsu_port {
92 void __iomem *reg;
93 unsigned long paddr;
94 unsigned long iolen;
95 u32 irq;
96
97 struct uart_hsu_port port[3];
98 struct hsu_dma_chan chans[10];
99
100 struct dentry *debugfs;
101};
102
103static inline unsigned int serial_in(struct uart_hsu_port *up, int offset)
104{
105 unsigned int val;
106
107 if (offset > UART_MSR) {
108 offset <<= 2;
109 val = readl(up->port.membase + offset);
110 } else
111 val = (unsigned int)readb(up->port.membase + offset);
112
113 return val;
114}
115
116static inline void serial_out(struct uart_hsu_port *up, int offset, int value)
117{
118 if (offset > UART_MSR) {
119 offset <<= 2;
120 writel(value, up->port.membase + offset);
121 } else {
122 unsigned char val = value & 0xff;
123 writeb(val, up->port.membase + offset);
124 }
125}
126
127#ifdef CONFIG_DEBUG_FS
128
129#define HSU_REGS_BUFSIZE 1024
130
131static int hsu_show_regs_open(struct inode *inode, struct file *file)
132{
133 file->private_data = inode->i_private;
134 return 0;
135}
136
137static ssize_t port_show_regs(struct file *file, char __user *user_buf,
138 size_t count, loff_t *ppos)
139{
140 struct uart_hsu_port *up = file->private_data;
141 char *buf;
142 u32 len = 0;
143 ssize_t ret;
144
145 buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL);
146 if (!buf)
147 return 0;
148
149 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
150 "MFD HSU port[%d] regs:\n", up->index);
151
152 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
153 "=================================\n");
154 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
155 "IER: \t\t0x%08x\n", serial_in(up, UART_IER));
156 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
157 "IIR: \t\t0x%08x\n", serial_in(up, UART_IIR));
158 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
159 "LCR: \t\t0x%08x\n", serial_in(up, UART_LCR));
160 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
161 "MCR: \t\t0x%08x\n", serial_in(up, UART_MCR));
162 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
163 "LSR: \t\t0x%08x\n", serial_in(up, UART_LSR));
164 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
165 "MSR: \t\t0x%08x\n", serial_in(up, UART_MSR));
166 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
167 "FOR: \t\t0x%08x\n", serial_in(up, UART_FOR));
168 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
169 "PS: \t\t0x%08x\n", serial_in(up, UART_PS));
170 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
171 "MUL: \t\t0x%08x\n", serial_in(up, UART_MUL));
172 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
173 "DIV: \t\t0x%08x\n", serial_in(up, UART_DIV));
174
175 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
176 kfree(buf);
177 return ret;
178}
179
180static ssize_t dma_show_regs(struct file *file, char __user *user_buf,
181 size_t count, loff_t *ppos)
182{
183 struct hsu_dma_chan *chan = file->private_data;
184 char *buf;
185 u32 len = 0;
186 ssize_t ret;
187
188 buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL);
189 if (!buf)
190 return 0;
191
192 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
193 "MFD HSU DMA channel [%d] regs:\n", chan->id);
194
195 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
196 "=================================\n");
197 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
198 "CR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_CR));
199 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
200 "DCR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_DCR));
201 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
202 "BSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_BSR));
203 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
204 "MOTSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_MOTSR));
205 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
206 "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0SAR));
207 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
208 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0TSR));
209 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
210 "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1SAR));
211 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
212 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1TSR));
213 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
214 "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2SAR));
215 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
216 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2TSR));
217 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
218 "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3SAR));
219 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
220 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3TSR));
221
222 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
223 kfree(buf);
224 return ret;
225}
226
227static const struct file_operations port_regs_ops = {
228 .owner = THIS_MODULE,
229 .open = hsu_show_regs_open,
230 .read = port_show_regs,
231};
232
233static const struct file_operations dma_regs_ops = {
234 .owner = THIS_MODULE,
235 .open = hsu_show_regs_open,
236 .read = dma_show_regs,
237};
238
239static int hsu_debugfs_init(struct hsu_port *hsu)
240{
241 int i;
242 char name[32];
243
244 hsu->debugfs = debugfs_create_dir("hsu", NULL);
245 if (!hsu->debugfs)
246 return -ENOMEM;
247
248 for (i = 0; i < 3; i++) {
249 snprintf(name, sizeof(name), "port_%d_regs", i);
250 debugfs_create_file(name, S_IFREG | S_IRUGO,
251 hsu->debugfs, (void *)(&hsu->port[i]), &port_regs_ops);
252 }
253
254 for (i = 0; i < 6; i++) {
255 snprintf(name, sizeof(name), "dma_chan_%d_regs", i);
256 debugfs_create_file(name, S_IFREG | S_IRUGO,
257 hsu->debugfs, (void *)&hsu->chans[i], &dma_regs_ops);
258 }
259
260 return 0;
261}
262
263static void hsu_debugfs_remove(struct hsu_port *hsu)
264{
265 if (hsu->debugfs)
266 debugfs_remove_recursive(hsu->debugfs);
267}
268
269#else
270static inline int hsu_debugfs_init(struct hsu_port *hsu)
271{
272 return 0;
273}
274
275static inline void hsu_debugfs_remove(struct hsu_port *hsu)
276{
277}
278#endif /* CONFIG_DEBUG_FS */
279
280static void serial_hsu_enable_ms(struct uart_port *port)
281{
282 struct uart_hsu_port *up =
283 container_of(port, struct uart_hsu_port, port);
284
285 up->ier |= UART_IER_MSI;
286 serial_out(up, UART_IER, up->ier);
287}
288
289void hsu_dma_tx(struct uart_hsu_port *up)
290{
291 struct circ_buf *xmit = &up->port.state->xmit;
292 struct hsu_dma_buffer *dbuf = &up->txbuf;
293 int count;
294
295 /* test_and_set_bit may be better, but anyway it's in lock protected mode */
296 if (up->dma_tx_on)
297 return;
298
299 /* Update the circ buf info */
300 xmit->tail += dbuf->ofs;
301 xmit->tail &= UART_XMIT_SIZE - 1;
302
303 up->port.icount.tx += dbuf->ofs;
304 dbuf->ofs = 0;
305
306 /* Disable the channel */
307 chan_writel(up->txc, HSU_CH_CR, 0x0);
308
309 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&up->port)) {
310 dma_sync_single_for_device(up->port.dev,
311 dbuf->dma_addr,
312 dbuf->dma_size,
313 DMA_TO_DEVICE);
314
315 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
316 dbuf->ofs = count;
317
318 /* Reprogram the channel */
319 chan_writel(up->txc, HSU_CH_D0SAR, dbuf->dma_addr + xmit->tail);
320 chan_writel(up->txc, HSU_CH_D0TSR, count);
321
322 /* Reenable the channel */
323 chan_writel(up->txc, HSU_CH_DCR, 0x1
324 | (0x1 << 8)
325 | (0x1 << 16)
326 | (0x1 << 24));
327 up->dma_tx_on = 1;
328 chan_writel(up->txc, HSU_CH_CR, 0x1);
329 }
330
331 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
332 uart_write_wakeup(&up->port);
333}
334
335/* The buffer is already cache coherent */
336void hsu_dma_start_rx_chan(struct hsu_dma_chan *rxc, struct hsu_dma_buffer *dbuf)
337{
338 dbuf->ofs = 0;
339
340 chan_writel(rxc, HSU_CH_BSR, 32);
341 chan_writel(rxc, HSU_CH_MOTSR, 4);
342
343 chan_writel(rxc, HSU_CH_D0SAR, dbuf->dma_addr);
344 chan_writel(rxc, HSU_CH_D0TSR, dbuf->dma_size);
345 chan_writel(rxc, HSU_CH_DCR, 0x1 | (0x1 << 8)
346 | (0x1 << 16)
347 | (0x1 << 24) /* timeout bit, see HSU Errata 1 */
348 );
349 chan_writel(rxc, HSU_CH_CR, 0x3);
350
351 mod_timer(&rxc->rx_timer, jiffies + HSU_DMA_TIMEOUT_CHECK_FREQ);
352}
353
354/* Protected by spin_lock_irqsave(port->lock) */
355static void serial_hsu_start_tx(struct uart_port *port)
356{
357 struct uart_hsu_port *up =
358 container_of(port, struct uart_hsu_port, port);
359
360 if (up->use_dma) {
361 hsu_dma_tx(up);
362 } else if (!(up->ier & UART_IER_THRI)) {
363 up->ier |= UART_IER_THRI;
364 serial_out(up, UART_IER, up->ier);
365 }
366}
367
368static void serial_hsu_stop_tx(struct uart_port *port)
369{
370 struct uart_hsu_port *up =
371 container_of(port, struct uart_hsu_port, port);
372 struct hsu_dma_chan *txc = up->txc;
373
374 if (up->use_dma)
375 chan_writel(txc, HSU_CH_CR, 0x0);
376 else if (up->ier & UART_IER_THRI) {
377 up->ier &= ~UART_IER_THRI;
378 serial_out(up, UART_IER, up->ier);
379 }
380}
381
382/* This is always called in spinlock protected mode, so
383 * modify timeout timer is safe here */
384void hsu_dma_rx(struct uart_hsu_port *up, u32 int_sts)
385{
386 struct hsu_dma_buffer *dbuf = &up->rxbuf;
387 struct hsu_dma_chan *chan = up->rxc;
388 struct uart_port *port = &up->port;
389 struct tty_struct *tty = port->state->port.tty;
390 int count;
391
392 if (!tty)
393 return;
394
395 /*
396 * First need to know how many is already transferred,
397 * then check if its a timeout DMA irq, and return
398 * the trail bytes out, push them up and reenable the
399 * channel
400 */
401
402 /* Timeout IRQ, need wait some time, see Errata 2 */
403 if (int_sts & 0xf00)
404 udelay(2);
405
406 /* Stop the channel */
407 chan_writel(chan, HSU_CH_CR, 0x0);
408
409 count = chan_readl(chan, HSU_CH_D0SAR) - dbuf->dma_addr;
410 if (!count) {
411 /* Restart the channel before we leave */
412 chan_writel(chan, HSU_CH_CR, 0x3);
413 return;
414 }
415 del_timer(&chan->rx_timer);
416
417 dma_sync_single_for_cpu(port->dev, dbuf->dma_addr,
418 dbuf->dma_size, DMA_FROM_DEVICE);
419
420 /*
421 * Head will only wrap around when we recycle
422 * the DMA buffer, and when that happens, we
423 * explicitly set tail to 0. So head will
424 * always be greater than tail.
425 */
426 tty_insert_flip_string(tty, dbuf->buf, count);
427 port->icount.rx += count;
428
429 dma_sync_single_for_device(up->port.dev, dbuf->dma_addr,
430 dbuf->dma_size, DMA_FROM_DEVICE);
431
432 /* Reprogram the channel */
433 chan_writel(chan, HSU_CH_D0SAR, dbuf->dma_addr);
434 chan_writel(chan, HSU_CH_D0TSR, dbuf->dma_size);
435 chan_writel(chan, HSU_CH_DCR, 0x1
436 | (0x1 << 8)
437 | (0x1 << 16)
438 | (0x1 << 24) /* timeout bit, see HSU Errata 1 */
439 );
440 tty_flip_buffer_push(tty);
441
442 chan_writel(chan, HSU_CH_CR, 0x3);
443 chan->rx_timer.expires = jiffies + HSU_DMA_TIMEOUT_CHECK_FREQ;
444 add_timer(&chan->rx_timer);
445
446}
447
448static void serial_hsu_stop_rx(struct uart_port *port)
449{
450 struct uart_hsu_port *up =
451 container_of(port, struct uart_hsu_port, port);
452 struct hsu_dma_chan *chan = up->rxc;
453
454 if (up->use_dma)
455 chan_writel(chan, HSU_CH_CR, 0x2);
456 else {
457 up->ier &= ~UART_IER_RLSI;
458 up->port.read_status_mask &= ~UART_LSR_DR;
459 serial_out(up, UART_IER, up->ier);
460 }
461}
462
463static inline void receive_chars(struct uart_hsu_port *up, int *status)
464{
465 struct tty_struct *tty = up->port.state->port.tty;
466 unsigned int ch, flag;
467 unsigned int max_count = 256;
468
469 if (!tty)
470 return;
471
472 do {
473 ch = serial_in(up, UART_RX);
474 flag = TTY_NORMAL;
475 up->port.icount.rx++;
476
477 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
478 UART_LSR_FE | UART_LSR_OE))) {
479
480 dev_warn(up->dev, "We really rush into ERR/BI case"
481 "status = 0x%02x", *status);
482 /* For statistics only */
483 if (*status & UART_LSR_BI) {
484 *status &= ~(UART_LSR_FE | UART_LSR_PE);
485 up->port.icount.brk++;
486 /*
487 * We do the SysRQ and SAK checking
488 * here because otherwise the break
489 * may get masked by ignore_status_mask
490 * or read_status_mask.
491 */
492 if (uart_handle_break(&up->port))
493 goto ignore_char;
494 } else if (*status & UART_LSR_PE)
495 up->port.icount.parity++;
496 else if (*status & UART_LSR_FE)
497 up->port.icount.frame++;
498 if (*status & UART_LSR_OE)
499 up->port.icount.overrun++;
500
501 /* Mask off conditions which should be ignored. */
502 *status &= up->port.read_status_mask;
503
504#ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
505 if (up->port.cons &&
506 up->port.cons->index == up->port.line) {
507 /* Recover the break flag from console xmit */
508 *status |= up->lsr_break_flag;
509 up->lsr_break_flag = 0;
510 }
511#endif
512 if (*status & UART_LSR_BI) {
513 flag = TTY_BREAK;
514 } else if (*status & UART_LSR_PE)
515 flag = TTY_PARITY;
516 else if (*status & UART_LSR_FE)
517 flag = TTY_FRAME;
518 }
519
520 if (uart_handle_sysrq_char(&up->port, ch))
521 goto ignore_char;
522
523 uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag);
524 ignore_char:
525 *status = serial_in(up, UART_LSR);
526 } while ((*status & UART_LSR_DR) && max_count--);
527 tty_flip_buffer_push(tty);
528}
529
530static void transmit_chars(struct uart_hsu_port *up)
531{
532 struct circ_buf *xmit = &up->port.state->xmit;
533 int count;
534
535 if (up->port.x_char) {
536 serial_out(up, UART_TX, up->port.x_char);
537 up->port.icount.tx++;
538 up->port.x_char = 0;
539 return;
540 }
541 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
542 serial_hsu_stop_tx(&up->port);
543 return;
544 }
545
546#ifndef MFD_HSU_A0_STEPPING
547 count = up->port.fifosize / 2;
548#else
549 /*
550 * A0 only supports fully empty IRQ, and the first char written
551 * into it won't clear the EMPT bit, so we may need be cautious
552 * by useing a shorter buffer
553 */
554 count = up->port.fifosize - 4;
555#endif
556 do {
557 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
558 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
559
560 up->port.icount.tx++;
561 if (uart_circ_empty(xmit))
562 break;
563 } while (--count > 0);
564
565 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
566 uart_write_wakeup(&up->port);
567
568 if (uart_circ_empty(xmit))
569 serial_hsu_stop_tx(&up->port);
570}
571
572static inline void check_modem_status(struct uart_hsu_port *up)
573{
574 int status;
575
576 status = serial_in(up, UART_MSR);
577
578 if ((status & UART_MSR_ANY_DELTA) == 0)
579 return;
580
581 if (status & UART_MSR_TERI)
582 up->port.icount.rng++;
583 if (status & UART_MSR_DDSR)
584 up->port.icount.dsr++;
585 /* We may only get DDCD when HW init and reset */
586 if (status & UART_MSR_DDCD)
587 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
588 /* Will start/stop_tx accordingly */
589 if (status & UART_MSR_DCTS)
590 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
591
592 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
593}
594
595/*
596 * This handles the interrupt from one port.
597 */
598static irqreturn_t port_irq(int irq, void *dev_id)
599{
600 struct uart_hsu_port *up = dev_id;
601 unsigned int iir, lsr;
602 unsigned long flags;
603
604 if (unlikely(!up->running))
605 return IRQ_NONE;
606
607 spin_lock_irqsave(&up->port.lock, flags);
608 if (up->use_dma) {
609 lsr = serial_in(up, UART_LSR);
610 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
611 UART_LSR_FE | UART_LSR_OE)))
612 dev_warn(up->dev,
613 "Got lsr irq while using DMA, lsr = 0x%2x\n",
614 lsr);
615 check_modem_status(up);
616 spin_unlock_irqrestore(&up->port.lock, flags);
617 return IRQ_HANDLED;
618 }
619
620 iir = serial_in(up, UART_IIR);
621 if (iir & UART_IIR_NO_INT) {
622 spin_unlock_irqrestore(&up->port.lock, flags);
623 return IRQ_NONE;
624 }
625
626 lsr = serial_in(up, UART_LSR);
627 if (lsr & UART_LSR_DR)
628 receive_chars(up, &lsr);
629 check_modem_status(up);
630
631 /* lsr will be renewed during the receive_chars */
632 if (lsr & UART_LSR_THRE)
633 transmit_chars(up);
634
635 spin_unlock_irqrestore(&up->port.lock, flags);
636 return IRQ_HANDLED;
637}
638
639static inline void dma_chan_irq(struct hsu_dma_chan *chan)
640{
641 struct uart_hsu_port *up = chan->uport;
642 unsigned long flags;
643 u32 int_sts;
644
645 spin_lock_irqsave(&up->port.lock, flags);
646
647 if (!up->use_dma || !up->running)
648 goto exit;
649
650 /*
651 * No matter what situation, need read clear the IRQ status
652 * There is a bug, see Errata 5, HSD 2900918
653 */
654 int_sts = chan_readl(chan, HSU_CH_SR);
655
656 /* Rx channel */
657 if (chan->dirt == DMA_FROM_DEVICE)
658 hsu_dma_rx(up, int_sts);
659
660 /* Tx channel */
661 if (chan->dirt == DMA_TO_DEVICE) {
662 chan_writel(chan, HSU_CH_CR, 0x0);
663 up->dma_tx_on = 0;
664 hsu_dma_tx(up);
665 }
666
667exit:
668 spin_unlock_irqrestore(&up->port.lock, flags);
669 return;
670}
671
672static irqreturn_t dma_irq(int irq, void *dev_id)
673{
674 struct hsu_port *hsu = dev_id;
675 u32 int_sts, i;
676
677 int_sts = mfd_readl(hsu, HSU_GBL_DMAISR);
678
679 /* Currently we only have 6 channels may be used */
680 for (i = 0; i < 6; i++) {
681 if (int_sts & 0x1)
682 dma_chan_irq(&hsu->chans[i]);
683 int_sts >>= 1;
684 }
685
686 return IRQ_HANDLED;
687}
688
689static unsigned int serial_hsu_tx_empty(struct uart_port *port)
690{
691 struct uart_hsu_port *up =
692 container_of(port, struct uart_hsu_port, port);
693 unsigned long flags;
694 unsigned int ret;
695
696 spin_lock_irqsave(&up->port.lock, flags);
697 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
698 spin_unlock_irqrestore(&up->port.lock, flags);
699
700 return ret;
701}
702
703static unsigned int serial_hsu_get_mctrl(struct uart_port *port)
704{
705 struct uart_hsu_port *up =
706 container_of(port, struct uart_hsu_port, port);
707 unsigned char status;
708 unsigned int ret;
709
710 status = serial_in(up, UART_MSR);
711
712 ret = 0;
713 if (status & UART_MSR_DCD)
714 ret |= TIOCM_CAR;
715 if (status & UART_MSR_RI)
716 ret |= TIOCM_RNG;
717 if (status & UART_MSR_DSR)
718 ret |= TIOCM_DSR;
719 if (status & UART_MSR_CTS)
720 ret |= TIOCM_CTS;
721 return ret;
722}
723
724static void serial_hsu_set_mctrl(struct uart_port *port, unsigned int mctrl)
725{
726 struct uart_hsu_port *up =
727 container_of(port, struct uart_hsu_port, port);
728 unsigned char mcr = 0;
729
730 if (mctrl & TIOCM_RTS)
731 mcr |= UART_MCR_RTS;
732 if (mctrl & TIOCM_DTR)
733 mcr |= UART_MCR_DTR;
734 if (mctrl & TIOCM_OUT1)
735 mcr |= UART_MCR_OUT1;
736 if (mctrl & TIOCM_OUT2)
737 mcr |= UART_MCR_OUT2;
738 if (mctrl & TIOCM_LOOP)
739 mcr |= UART_MCR_LOOP;
740
741 mcr |= up->mcr;
742
743 serial_out(up, UART_MCR, mcr);
744}
745
746static void serial_hsu_break_ctl(struct uart_port *port, int break_state)
747{
748 struct uart_hsu_port *up =
749 container_of(port, struct uart_hsu_port, port);
750 unsigned long flags;
751
752 spin_lock_irqsave(&up->port.lock, flags);
753 if (break_state == -1)
754 up->lcr |= UART_LCR_SBC;
755 else
756 up->lcr &= ~UART_LCR_SBC;
757 serial_out(up, UART_LCR, up->lcr);
758 spin_unlock_irqrestore(&up->port.lock, flags);
759}
760
761/*
762 * What special to do:
763 * 1. chose the 64B fifo mode
764 * 2. make sure not to select half empty mode for A0 stepping
765 * 3. start dma or pio depends on configuration
766 * 4. we only allocate dma memory when needed
767 */
768static int serial_hsu_startup(struct uart_port *port)
769{
770 struct uart_hsu_port *up =
771 container_of(port, struct uart_hsu_port, port);
772 unsigned long flags;
773
774 /*
775 * Clear the FIFO buffers and disable them.
776 * (they will be reenabled in set_termios())
777 */
778 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
779 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
780 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
781 serial_out(up, UART_FCR, 0);
782
783 /* Clear the interrupt registers. */
784 (void) serial_in(up, UART_LSR);
785 (void) serial_in(up, UART_RX);
786 (void) serial_in(up, UART_IIR);
787 (void) serial_in(up, UART_MSR);
788
789 /* Now, initialize the UART, default is 8n1 */
790 serial_out(up, UART_LCR, UART_LCR_WLEN8);
791
792 spin_lock_irqsave(&up->port.lock, flags);
793
794 up->port.mctrl |= TIOCM_OUT2;
795 serial_hsu_set_mctrl(&up->port, up->port.mctrl);
796
797 /*
798 * Finally, enable interrupts. Note: Modem status interrupts
799 * are set via set_termios(), which will be occurring imminently
800 * anyway, so we don't enable them here.
801 */
802 if (!up->use_dma)
803 up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE;
804 else
805 up->ier = 0;
806 serial_out(up, UART_IER, up->ier);
807
808 spin_unlock_irqrestore(&up->port.lock, flags);
809
810 /* DMA init */
811 if (up->use_dma) {
812 struct hsu_dma_buffer *dbuf;
813 struct circ_buf *xmit = &port->state->xmit;
814
815 up->dma_tx_on = 0;
816
817 /* First allocate the RX buffer */
818 dbuf = &up->rxbuf;
819 dbuf->buf = kzalloc(HSU_DMA_BUF_SIZE, GFP_KERNEL);
820 if (!dbuf->buf) {
821 up->use_dma = 0;
822 goto exit;
823 }
824 dbuf->dma_addr = dma_map_single(port->dev,
825 dbuf->buf,
826 HSU_DMA_BUF_SIZE,
827 DMA_FROM_DEVICE);
828 dbuf->dma_size = HSU_DMA_BUF_SIZE;
829
830 /* Start the RX channel right now */
831 hsu_dma_start_rx_chan(up->rxc, dbuf);
832
833 /* Next init the TX DMA */
834 dbuf = &up->txbuf;
835 dbuf->buf = xmit->buf;
836 dbuf->dma_addr = dma_map_single(port->dev,
837 dbuf->buf,
838 UART_XMIT_SIZE,
839 DMA_TO_DEVICE);
840 dbuf->dma_size = UART_XMIT_SIZE;
841
842 /* This should not be changed all around */
843 chan_writel(up->txc, HSU_CH_BSR, 32);
844 chan_writel(up->txc, HSU_CH_MOTSR, 4);
845 dbuf->ofs = 0;
846 }
847
848exit:
849 /* And clear the interrupt registers again for luck. */
850 (void) serial_in(up, UART_LSR);
851 (void) serial_in(up, UART_RX);
852 (void) serial_in(up, UART_IIR);
853 (void) serial_in(up, UART_MSR);
854
855 up->running = 1;
856 return 0;
857}
858
859static void serial_hsu_shutdown(struct uart_port *port)
860{
861 struct uart_hsu_port *up =
862 container_of(port, struct uart_hsu_port, port);
863 unsigned long flags;
864
865 del_timer_sync(&up->rxc->rx_timer);
866
867 /* Disable interrupts from this port */
868 up->ier = 0;
869 serial_out(up, UART_IER, 0);
870 up->running = 0;
871
872 spin_lock_irqsave(&up->port.lock, flags);
873 up->port.mctrl &= ~TIOCM_OUT2;
874 serial_hsu_set_mctrl(&up->port, up->port.mctrl);
875 spin_unlock_irqrestore(&up->port.lock, flags);
876
877 /* Disable break condition and FIFOs */
878 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
879 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
880 UART_FCR_CLEAR_RCVR |
881 UART_FCR_CLEAR_XMIT);
882 serial_out(up, UART_FCR, 0);
883}
884
885static void
886serial_hsu_set_termios(struct uart_port *port, struct ktermios *termios,
887 struct ktermios *old)
888{
889 struct uart_hsu_port *up =
890 container_of(port, struct uart_hsu_port, port);
891 struct tty_struct *tty = port->state->port.tty;
892 unsigned char cval, fcr = 0;
893 unsigned long flags;
894 unsigned int baud, quot;
895 u32 mul = 0x3600;
896 u32 ps = 0x10;
897
898 switch (termios->c_cflag & CSIZE) {
899 case CS5:
900 cval = UART_LCR_WLEN5;
901 break;
902 case CS6:
903 cval = UART_LCR_WLEN6;
904 break;
905 case CS7:
906 cval = UART_LCR_WLEN7;
907 break;
908 default:
909 case CS8:
910 cval = UART_LCR_WLEN8;
911 break;
912 }
913
914 /* CMSPAR isn't supported by this driver */
915 if (tty)
916 tty->termios->c_cflag &= ~CMSPAR;
917
918 if (termios->c_cflag & CSTOPB)
919 cval |= UART_LCR_STOP;
920 if (termios->c_cflag & PARENB)
921 cval |= UART_LCR_PARITY;
922 if (!(termios->c_cflag & PARODD))
923 cval |= UART_LCR_EPAR;
924
925 /*
926 * For those basic low baud rate we can get the direct
927 * scalar from 2746800, like 115200 = 2746800/24, for those
928 * higher baud rate, we have to handle them case by case,
929 * but DIV reg is never touched as its default value 0x3d09
930 */
931 baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
932 quot = uart_get_divisor(port, baud);
933
934 switch (baud) {
935 case 3500000:
936 mul = 0x3345;
937 ps = 0xC;
938 quot = 1;
939 break;
940 case 2500000:
941 mul = 0x2710;
942 ps = 0x10;
943 quot = 1;
944 break;
945 case 18432000:
946 mul = 0x2400;
947 ps = 0x10;
948 quot = 1;
949 break;
950 case 1500000:
951 mul = 0x1D4C;
952 ps = 0xc;
953 quot = 1;
954 break;
955 default:
956 ;
957 }
958
959 if ((up->port.uartclk / quot) < (2400 * 16))
960 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_1B;
961 else if ((up->port.uartclk / quot) < (230400 * 16))
962 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_16B;
963 else
964 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_32B;
965
966 fcr |= UART_FCR_HSU_64B_FIFO;
967#ifdef MFD_HSU_A0_STEPPING
968 /* A0 doesn't support half empty IRQ */
969 fcr |= UART_FCR_FULL_EMPT_TXI;
970#endif
971
972 /*
973 * Ok, we're now changing the port state. Do it with
974 * interrupts disabled.
975 */
976 spin_lock_irqsave(&up->port.lock, flags);
977
978 /* Update the per-port timeout */
979 uart_update_timeout(port, termios->c_cflag, baud);
980
981 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
982 if (termios->c_iflag & INPCK)
983 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
984 if (termios->c_iflag & (BRKINT | PARMRK))
985 up->port.read_status_mask |= UART_LSR_BI;
986
987 /* Characters to ignore */
988 up->port.ignore_status_mask = 0;
989 if (termios->c_iflag & IGNPAR)
990 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
991 if (termios->c_iflag & IGNBRK) {
992 up->port.ignore_status_mask |= UART_LSR_BI;
993 /*
994 * If we're ignoring parity and break indicators,
995 * ignore overruns too (for real raw support).
996 */
997 if (termios->c_iflag & IGNPAR)
998 up->port.ignore_status_mask |= UART_LSR_OE;
999 }
1000
1001 /* Ignore all characters if CREAD is not set */
1002 if ((termios->c_cflag & CREAD) == 0)
1003 up->port.ignore_status_mask |= UART_LSR_DR;
1004
1005 /*
1006 * CTS flow control flag and modem status interrupts, disable
1007 * MSI by default
1008 */
1009 up->ier &= ~UART_IER_MSI;
1010 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
1011 up->ier |= UART_IER_MSI;
1012
1013 serial_out(up, UART_IER, up->ier);
1014
1015 if (termios->c_cflag & CRTSCTS)
1016 up->mcr |= UART_MCR_AFE | UART_MCR_RTS;
1017 else
1018 up->mcr &= ~UART_MCR_AFE;
1019
1020 serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
1021 serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */
1022 serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
1023 serial_out(up, UART_LCR, cval); /* reset DLAB */
1024 serial_out(up, UART_MUL, mul); /* set MUL */
1025 serial_out(up, UART_PS, ps); /* set PS */
1026 up->lcr = cval; /* Save LCR */
1027 serial_hsu_set_mctrl(&up->port, up->port.mctrl);
1028 serial_out(up, UART_FCR, fcr);
1029 spin_unlock_irqrestore(&up->port.lock, flags);
1030}
1031
1032static void
1033serial_hsu_pm(struct uart_port *port, unsigned int state,
1034 unsigned int oldstate)
1035{
1036}
1037
1038static void serial_hsu_release_port(struct uart_port *port)
1039{
1040}
1041
1042static int serial_hsu_request_port(struct uart_port *port)
1043{
1044 return 0;
1045}
1046
1047static void serial_hsu_config_port(struct uart_port *port, int flags)
1048{
1049 struct uart_hsu_port *up =
1050 container_of(port, struct uart_hsu_port, port);
1051 up->port.type = PORT_MFD;
1052}
1053
1054static int
1055serial_hsu_verify_port(struct uart_port *port, struct serial_struct *ser)
1056{
1057 /* We don't want the core code to modify any port params */
1058 return -EINVAL;
1059}
1060
1061static const char *
1062serial_hsu_type(struct uart_port *port)
1063{
1064 struct uart_hsu_port *up =
1065 container_of(port, struct uart_hsu_port, port);
1066 return up->name;
1067}
1068
1069/* Mainly for uart console use */
1070static struct uart_hsu_port *serial_hsu_ports[3];
1071static struct uart_driver serial_hsu_reg;
1072
1073#ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
1074
1075#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1076
1077/* Wait for transmitter & holding register to empty */
1078static inline void wait_for_xmitr(struct uart_hsu_port *up)
1079{
1080 unsigned int status, tmout = 1000;
1081
1082 /* Wait up to 1ms for the character to be sent. */
1083 do {
1084 status = serial_in(up, UART_LSR);
1085
1086 if (status & UART_LSR_BI)
1087 up->lsr_break_flag = UART_LSR_BI;
1088
1089 if (--tmout == 0)
1090 break;
1091 udelay(1);
1092 } while (!(status & BOTH_EMPTY));
1093
1094 /* Wait up to 1s for flow control if necessary */
1095 if (up->port.flags & UPF_CONS_FLOW) {
1096 tmout = 1000000;
1097 while (--tmout &&
1098 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
1099 udelay(1);
1100 }
1101}
1102
1103static void serial_hsu_console_putchar(struct uart_port *port, int ch)
1104{
1105 struct uart_hsu_port *up =
1106 container_of(port, struct uart_hsu_port, port);
1107
1108 wait_for_xmitr(up);
1109 serial_out(up, UART_TX, ch);
1110}
1111
1112/*
1113 * Print a string to the serial port trying not to disturb
1114 * any possible real use of the port...
1115 *
1116 * The console_lock must be held when we get here.
1117 */
1118static void
1119serial_hsu_console_write(struct console *co, const char *s, unsigned int count)
1120{
1121 struct uart_hsu_port *up = serial_hsu_ports[co->index];
1122 unsigned long flags;
1123 unsigned int ier;
1124 int locked = 1;
1125
1126 local_irq_save(flags);
1127 if (up->port.sysrq)
1128 locked = 0;
1129 else if (oops_in_progress) {
1130 locked = spin_trylock(&up->port.lock);
1131 } else
1132 spin_lock(&up->port.lock);
1133
1134 /* First save the IER then disable the interrupts */
1135 ier = serial_in(up, UART_IER);
1136 serial_out(up, UART_IER, 0);
1137
1138 uart_console_write(&up->port, s, count, serial_hsu_console_putchar);
1139
1140 /*
1141 * Finally, wait for transmitter to become empty
1142 * and restore the IER
1143 */
1144 wait_for_xmitr(up);
1145 serial_out(up, UART_IER, ier);
1146
1147 if (locked)
1148 spin_unlock(&up->port.lock);
1149 local_irq_restore(flags);
1150}
1151
1152static struct console serial_hsu_console;
1153
1154static int __init
1155serial_hsu_console_setup(struct console *co, char *options)
1156{
1157 struct uart_hsu_port *up;
1158 int baud = 115200;
1159 int bits = 8;
1160 int parity = 'n';
1161 int flow = 'n';
1162 int ret;
1163
1164 if (co->index == -1 || co->index >= serial_hsu_reg.nr)
1165 co->index = 0;
1166 up = serial_hsu_ports[co->index];
1167 if (!up)
1168 return -ENODEV;
1169
1170 if (options)
1171 uart_parse_options(options, &baud, &parity, &bits, &flow);
1172
1173 ret = uart_set_options(&up->port, co, baud, parity, bits, flow);
1174
1175 return ret;
1176}
1177
1178static struct console serial_hsu_console = {
1179 .name = "ttyMFD",
1180 .write = serial_hsu_console_write,
1181 .device = uart_console_device,
1182 .setup = serial_hsu_console_setup,
1183 .flags = CON_PRINTBUFFER,
1184 .index = 2,
1185 .data = &serial_hsu_reg,
1186};
1187#endif
1188
1189struct uart_ops serial_hsu_pops = {
1190 .tx_empty = serial_hsu_tx_empty,
1191 .set_mctrl = serial_hsu_set_mctrl,
1192 .get_mctrl = serial_hsu_get_mctrl,
1193 .stop_tx = serial_hsu_stop_tx,
1194 .start_tx = serial_hsu_start_tx,
1195 .stop_rx = serial_hsu_stop_rx,
1196 .enable_ms = serial_hsu_enable_ms,
1197 .break_ctl = serial_hsu_break_ctl,
1198 .startup = serial_hsu_startup,
1199 .shutdown = serial_hsu_shutdown,
1200 .set_termios = serial_hsu_set_termios,
1201 .pm = serial_hsu_pm,
1202 .type = serial_hsu_type,
1203 .release_port = serial_hsu_release_port,
1204 .request_port = serial_hsu_request_port,
1205 .config_port = serial_hsu_config_port,
1206 .verify_port = serial_hsu_verify_port,
1207};
1208
1209static struct uart_driver serial_hsu_reg = {
1210 .owner = THIS_MODULE,
1211 .driver_name = "MFD serial",
1212 .dev_name = "ttyMFD",
1213 .major = TTY_MAJOR,
1214 .minor = 128,
1215 .nr = 3,
1216};
1217
1218#ifdef CONFIG_PM
1219static int serial_hsu_suspend(struct pci_dev *pdev, pm_message_t state)
1220{
1221 void *priv = pci_get_drvdata(pdev);
1222 struct uart_hsu_port *up;
1223
1224 /* Make sure this is not the internal dma controller */
1225 if (priv && (pdev->device != 0x081E)) {
1226 up = priv;
1227 uart_suspend_port(&serial_hsu_reg, &up->port);
1228 }
1229
1230 pci_save_state(pdev);
1231 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1232 return 0;
1233}
1234
1235static int serial_hsu_resume(struct pci_dev *pdev)
1236{
1237 void *priv = pci_get_drvdata(pdev);
1238 struct uart_hsu_port *up;
1239 int ret;
1240
1241 pci_set_power_state(pdev, PCI_D0);
1242 pci_restore_state(pdev);
1243
1244 ret = pci_enable_device(pdev);
1245 if (ret)
1246 dev_warn(&pdev->dev,
1247 "HSU: can't re-enable device, try to continue\n");
1248
1249 if (priv && (pdev->device != 0x081E)) {
1250 up = priv;
1251 uart_resume_port(&serial_hsu_reg, &up->port);
1252 }
1253 return 0;
1254}
1255#else
1256#define serial_hsu_suspend NULL
1257#define serial_hsu_resume NULL
1258#endif
1259
1260/* temp global pointer before we settle down on using one or four PCI dev */
1261static struct hsu_port *phsu;
1262
1263static int serial_hsu_probe(struct pci_dev *pdev,
1264 const struct pci_device_id *ent)
1265{
1266 struct uart_hsu_port *uport;
1267 int index, ret;
1268
1269 printk(KERN_INFO "HSU: found PCI Serial controller(ID: %04x:%04x)\n",
1270 pdev->vendor, pdev->device);
1271
1272 switch (pdev->device) {
1273 case 0x081B:
1274 index = 0;
1275 break;
1276 case 0x081C:
1277 index = 1;
1278 break;
1279 case 0x081D:
1280 index = 2;
1281 break;
1282 case 0x081E:
1283 /* internal DMA controller */
1284 index = 3;
1285 break;
1286 default:
1287 dev_err(&pdev->dev, "HSU: out of index!");
1288 return -ENODEV;
1289 }
1290
1291 ret = pci_enable_device(pdev);
1292 if (ret)
1293 return ret;
1294
1295 if (index == 3) {
1296 /* DMA controller */
1297 ret = request_irq(pdev->irq, dma_irq, 0, "hsu_dma", phsu);
1298 if (ret) {
1299 dev_err(&pdev->dev, "can not get IRQ\n");
1300 goto err_disable;
1301 }
1302 pci_set_drvdata(pdev, phsu);
1303 } else {
1304 /* UART port 0~2 */
1305 uport = &phsu->port[index];
1306 uport->port.irq = pdev->irq;
1307 uport->port.dev = &pdev->dev;
1308 uport->dev = &pdev->dev;
1309
1310 ret = request_irq(pdev->irq, port_irq, 0, uport->name, uport);
1311 if (ret) {
1312 dev_err(&pdev->dev, "can not get IRQ\n");
1313 goto err_disable;
1314 }
1315 uart_add_one_port(&serial_hsu_reg, &uport->port);
1316
1317#ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
1318 if (index == 2) {
1319 register_console(&serial_hsu_console);
1320 uport->port.cons = &serial_hsu_console;
1321 }
1322#endif
1323 pci_set_drvdata(pdev, uport);
1324 }
1325
1326 return 0;
1327
1328err_disable:
1329 pci_disable_device(pdev);
1330 return ret;
1331}
1332
1333static void hsu_dma_rx_timeout(unsigned long data)
1334{
1335 struct hsu_dma_chan *chan = (void *)data;
1336 struct uart_hsu_port *up = chan->uport;
1337 struct hsu_dma_buffer *dbuf = &up->rxbuf;
1338 int count = 0;
1339 unsigned long flags;
1340
1341 spin_lock_irqsave(&up->port.lock, flags);
1342
1343 count = chan_readl(chan, HSU_CH_D0SAR) - dbuf->dma_addr;
1344
1345 if (!count) {
1346 mod_timer(&chan->rx_timer, jiffies + HSU_DMA_TIMEOUT_CHECK_FREQ);
1347 goto exit;
1348 }
1349
1350 hsu_dma_rx(up, 0);
1351exit:
1352 spin_unlock_irqrestore(&up->port.lock, flags);
1353}
1354
1355static void hsu_global_init(void)
1356{
1357 struct hsu_port *hsu;
1358 struct uart_hsu_port *uport;
1359 struct hsu_dma_chan *dchan;
1360 int i, ret;
1361
1362 hsu = kzalloc(sizeof(struct hsu_port), GFP_KERNEL);
1363 if (!hsu)
1364 return;
1365
1366 /* Get basic io resource and map it */
1367 hsu->paddr = 0xffa28000;
1368 hsu->iolen = 0x1000;
1369
1370 if (!(request_mem_region(hsu->paddr, hsu->iolen, "HSU global")))
1371 pr_warning("HSU: error in request mem region\n");
1372
1373 hsu->reg = ioremap_nocache((unsigned long)hsu->paddr, hsu->iolen);
1374 if (!hsu->reg) {
1375 pr_err("HSU: error in ioremap\n");
1376 ret = -ENOMEM;
1377 goto err_free_region;
1378 }
1379
1380 /* Initialise the 3 UART ports */
1381 uport = hsu->port;
1382 for (i = 0; i < 3; i++) {
1383 uport->port.type = PORT_MFD;
1384 uport->port.iotype = UPIO_MEM;
1385 uport->port.mapbase = (resource_size_t)hsu->paddr
1386 + HSU_PORT_REG_OFFSET
1387 + i * HSU_PORT_REG_LENGTH;
1388 uport->port.membase = hsu->reg + HSU_PORT_REG_OFFSET
1389 + i * HSU_PORT_REG_LENGTH;
1390
1391 sprintf(uport->name, "hsu_port%d", i);
1392 uport->port.fifosize = 64;
1393 uport->port.ops = &serial_hsu_pops;
1394 uport->port.line = i;
1395 uport->port.flags = UPF_IOREMAP;
1396 /* set the scalable maxim support rate to 2746800 bps */
1397 uport->port.uartclk = 115200 * 24 * 16;
1398
1399 uport->running = 0;
1400 uport->txc = &hsu->chans[i * 2];
1401 uport->rxc = &hsu->chans[i * 2 + 1];
1402
1403 serial_hsu_ports[i] = uport;
1404 uport->index = i;
1405 uport++;
1406 }
1407
1408 /* Initialise 6 dma channels */
1409 dchan = hsu->chans;
1410 for (i = 0; i < 6; i++) {
1411 dchan->id = i;
1412 dchan->dirt = (i & 0x1) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1413 dchan->uport = &hsu->port[i/2];
1414 dchan->reg = hsu->reg + HSU_DMA_CHANS_REG_OFFSET +
1415 i * HSU_DMA_CHANS_REG_LENGTH;
1416
1417 /* Work around for RX */
1418 if (dchan->dirt == DMA_FROM_DEVICE) {
1419 init_timer(&dchan->rx_timer);
1420 dchan->rx_timer.function = hsu_dma_rx_timeout;
1421 dchan->rx_timer.data = (unsigned long)dchan;
1422 }
1423 dchan++;
1424 }
1425
1426 phsu = hsu;
1427 hsu_debugfs_init(hsu);
1428 return;
1429
1430err_free_region:
1431 release_mem_region(hsu->paddr, hsu->iolen);
1432 kfree(hsu);
1433 return;
1434}
1435
1436static void serial_hsu_remove(struct pci_dev *pdev)
1437{
1438 void *priv = pci_get_drvdata(pdev);
1439 struct uart_hsu_port *up;
1440
1441 if (!priv)
1442 return;
1443
1444 /* For port 0/1/2, priv is the address of uart_hsu_port */
1445 if (pdev->device != 0x081E) {
1446 up = priv;
1447 uart_remove_one_port(&serial_hsu_reg, &up->port);
1448 }
1449
1450 pci_set_drvdata(pdev, NULL);
1451 free_irq(pdev->irq, priv);
1452 pci_disable_device(pdev);
1453}
1454
1455/* First 3 are UART ports, and the 4th is the DMA */
1456static const struct pci_device_id pci_ids[] __devinitdata = {
1457 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081B) },
1458 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081C) },
1459 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081D) },
1460 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081E) },
1461 {},
1462};
1463
1464static struct pci_driver hsu_pci_driver = {
1465 .name = "HSU serial",
1466 .id_table = pci_ids,
1467 .probe = serial_hsu_probe,
1468 .remove = __devexit_p(serial_hsu_remove),
1469 .suspend = serial_hsu_suspend,
1470 .resume = serial_hsu_resume,
1471};
1472
1473static int __init hsu_pci_init(void)
1474{
1475 int ret;
1476
1477 hsu_global_init();
1478
1479 ret = uart_register_driver(&serial_hsu_reg);
1480 if (ret)
1481 return ret;
1482
1483 return pci_register_driver(&hsu_pci_driver);
1484}
1485
1486static void __exit hsu_pci_exit(void)
1487{
1488 pci_unregister_driver(&hsu_pci_driver);
1489 uart_unregister_driver(&serial_hsu_reg);
1490
1491 hsu_debugfs_remove(phsu);
1492
1493 kfree(phsu);
1494}
1495
1496module_init(hsu_pci_init);
1497module_exit(hsu_pci_exit);
1498
1499MODULE_LICENSE("GPL v2");
1500MODULE_ALIAS("platform:medfield-hsu");
diff --git a/drivers/serial/mpc52xx_uart.c b/drivers/serial/mpc52xx_uart.c
deleted file mode 100644
index c4399e23565a..000000000000
--- a/drivers/serial/mpc52xx_uart.c
+++ /dev/null
@@ -1,1523 +0,0 @@
1/*
2 * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs.
3 *
4 * FIXME According to the usermanual the status bits in the status register
5 * are only updated when the peripherals access the FIFO and not when the
6 * CPU access them. So since we use this bits to know when we stop writing
7 * and reading, they may not be updated in-time and a race condition may
8 * exists. But I haven't be able to prove this and I don't care. But if
9 * any problem arises, it might worth checking. The TX/RX FIFO Stats
10 * registers should be used in addition.
11 * Update: Actually, they seem updated ... At least the bits we use.
12 *
13 *
14 * Maintainer : Sylvain Munaut <tnt@246tNt.com>
15 *
16 * Some of the code has been inspired/copied from the 2.4 code written
17 * by Dale Farnsworth <dfarnsworth@mvista.com>.
18 *
19 * Copyright (C) 2008 Freescale Semiconductor Inc.
20 * John Rigby <jrigby@gmail.com>
21 * Added support for MPC5121
22 * Copyright (C) 2006 Secret Lab Technologies Ltd.
23 * Grant Likely <grant.likely@secretlab.ca>
24 * Copyright (C) 2004-2006 Sylvain Munaut <tnt@246tNt.com>
25 * Copyright (C) 2003 MontaVista, Software, Inc.
26 *
27 * This file is licensed under the terms of the GNU General Public License
28 * version 2. This program is licensed "as is" without any warranty of any
29 * kind, whether express or implied.
30 */
31
32#undef DEBUG
33
34#include <linux/device.h>
35#include <linux/module.h>
36#include <linux/tty.h>
37#include <linux/serial.h>
38#include <linux/sysrq.h>
39#include <linux/console.h>
40#include <linux/delay.h>
41#include <linux/io.h>
42#include <linux/of.h>
43#include <linux/of_platform.h>
44#include <linux/clk.h>
45
46#include <asm/mpc52xx.h>
47#include <asm/mpc52xx_psc.h>
48
49#if defined(CONFIG_SERIAL_MPC52xx_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
50#define SUPPORT_SYSRQ
51#endif
52
53#include <linux/serial_core.h>
54
55
56/* We've been assigned a range on the "Low-density serial ports" major */
57#define SERIAL_PSC_MAJOR 204
58#define SERIAL_PSC_MINOR 148
59
60
61#define ISR_PASS_LIMIT 256 /* Max number of iteration in the interrupt */
62
63
64static struct uart_port mpc52xx_uart_ports[MPC52xx_PSC_MAXNUM];
65 /* Rem: - We use the read_status_mask as a shadow of
66 * psc->mpc52xx_psc_imr
67 * - It's important that is array is all zero on start as we
68 * use it to know if it's initialized or not ! If it's not sure
69 * it's cleared, then a memset(...,0,...) should be added to
70 * the console_init
71 */
72
73/* lookup table for matching device nodes to index numbers */
74static struct device_node *mpc52xx_uart_nodes[MPC52xx_PSC_MAXNUM];
75
76static void mpc52xx_uart_of_enumerate(void);
77
78
79#define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase))
80
81
82/* Forward declaration of the interruption handling routine */
83static irqreturn_t mpc52xx_uart_int(int irq, void *dev_id);
84static irqreturn_t mpc5xxx_uart_process_int(struct uart_port *port);
85
86
87/* Simple macro to test if a port is console or not. This one is taken
88 * for serial_core.c and maybe should be moved to serial_core.h ? */
89#ifdef CONFIG_SERIAL_CORE_CONSOLE
90#define uart_console(port) \
91 ((port)->cons && (port)->cons->index == (port)->line)
92#else
93#define uart_console(port) (0)
94#endif
95
96/* ======================================================================== */
97/* PSC fifo operations for isolating differences between 52xx and 512x */
98/* ======================================================================== */
99
100struct psc_ops {
101 void (*fifo_init)(struct uart_port *port);
102 int (*raw_rx_rdy)(struct uart_port *port);
103 int (*raw_tx_rdy)(struct uart_port *port);
104 int (*rx_rdy)(struct uart_port *port);
105 int (*tx_rdy)(struct uart_port *port);
106 int (*tx_empty)(struct uart_port *port);
107 void (*stop_rx)(struct uart_port *port);
108 void (*start_tx)(struct uart_port *port);
109 void (*stop_tx)(struct uart_port *port);
110 void (*rx_clr_irq)(struct uart_port *port);
111 void (*tx_clr_irq)(struct uart_port *port);
112 void (*write_char)(struct uart_port *port, unsigned char c);
113 unsigned char (*read_char)(struct uart_port *port);
114 void (*cw_disable_ints)(struct uart_port *port);
115 void (*cw_restore_ints)(struct uart_port *port);
116 unsigned int (*set_baudrate)(struct uart_port *port,
117 struct ktermios *new,
118 struct ktermios *old);
119 int (*clock)(struct uart_port *port, int enable);
120 int (*fifoc_init)(void);
121 void (*fifoc_uninit)(void);
122 void (*get_irq)(struct uart_port *, struct device_node *);
123 irqreturn_t (*handle_irq)(struct uart_port *port);
124};
125
126/* setting the prescaler and divisor reg is common for all chips */
127static inline void mpc52xx_set_divisor(struct mpc52xx_psc __iomem *psc,
128 u16 prescaler, unsigned int divisor)
129{
130 /* select prescaler */
131 out_be16(&psc->mpc52xx_psc_clock_select, prescaler);
132 out_8(&psc->ctur, divisor >> 8);
133 out_8(&psc->ctlr, divisor & 0xff);
134}
135
136#ifdef CONFIG_PPC_MPC52xx
137#define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1))
138static void mpc52xx_psc_fifo_init(struct uart_port *port)
139{
140 struct mpc52xx_psc __iomem *psc = PSC(port);
141 struct mpc52xx_psc_fifo __iomem *fifo = FIFO_52xx(port);
142
143 out_8(&fifo->rfcntl, 0x00);
144 out_be16(&fifo->rfalarm, 0x1ff);
145 out_8(&fifo->tfcntl, 0x07);
146 out_be16(&fifo->tfalarm, 0x80);
147
148 port->read_status_mask |= MPC52xx_PSC_IMR_RXRDY | MPC52xx_PSC_IMR_TXRDY;
149 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
150}
151
152static int mpc52xx_psc_raw_rx_rdy(struct uart_port *port)
153{
154 return in_be16(&PSC(port)->mpc52xx_psc_status)
155 & MPC52xx_PSC_SR_RXRDY;
156}
157
158static int mpc52xx_psc_raw_tx_rdy(struct uart_port *port)
159{
160 return in_be16(&PSC(port)->mpc52xx_psc_status)
161 & MPC52xx_PSC_SR_TXRDY;
162}
163
164
165static int mpc52xx_psc_rx_rdy(struct uart_port *port)
166{
167 return in_be16(&PSC(port)->mpc52xx_psc_isr)
168 & port->read_status_mask
169 & MPC52xx_PSC_IMR_RXRDY;
170}
171
172static int mpc52xx_psc_tx_rdy(struct uart_port *port)
173{
174 return in_be16(&PSC(port)->mpc52xx_psc_isr)
175 & port->read_status_mask
176 & MPC52xx_PSC_IMR_TXRDY;
177}
178
179static int mpc52xx_psc_tx_empty(struct uart_port *port)
180{
181 return in_be16(&PSC(port)->mpc52xx_psc_status)
182 & MPC52xx_PSC_SR_TXEMP;
183}
184
185static void mpc52xx_psc_start_tx(struct uart_port *port)
186{
187 port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY;
188 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
189}
190
191static void mpc52xx_psc_stop_tx(struct uart_port *port)
192{
193 port->read_status_mask &= ~MPC52xx_PSC_IMR_TXRDY;
194 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
195}
196
197static void mpc52xx_psc_stop_rx(struct uart_port *port)
198{
199 port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY;
200 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
201}
202
203static void mpc52xx_psc_rx_clr_irq(struct uart_port *port)
204{
205}
206
207static void mpc52xx_psc_tx_clr_irq(struct uart_port *port)
208{
209}
210
211static void mpc52xx_psc_write_char(struct uart_port *port, unsigned char c)
212{
213 out_8(&PSC(port)->mpc52xx_psc_buffer_8, c);
214}
215
216static unsigned char mpc52xx_psc_read_char(struct uart_port *port)
217{
218 return in_8(&PSC(port)->mpc52xx_psc_buffer_8);
219}
220
221static void mpc52xx_psc_cw_disable_ints(struct uart_port *port)
222{
223 out_be16(&PSC(port)->mpc52xx_psc_imr, 0);
224}
225
226static void mpc52xx_psc_cw_restore_ints(struct uart_port *port)
227{
228 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
229}
230
231static unsigned int mpc5200_psc_set_baudrate(struct uart_port *port,
232 struct ktermios *new,
233 struct ktermios *old)
234{
235 unsigned int baud;
236 unsigned int divisor;
237
238 /* The 5200 has a fixed /32 prescaler, uartclk contains the ipb freq */
239 baud = uart_get_baud_rate(port, new, old,
240 port->uartclk / (32 * 0xffff) + 1,
241 port->uartclk / 32);
242 divisor = (port->uartclk + 16 * baud) / (32 * baud);
243
244 /* enable the /32 prescaler and set the divisor */
245 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
246 return baud;
247}
248
249static unsigned int mpc5200b_psc_set_baudrate(struct uart_port *port,
250 struct ktermios *new,
251 struct ktermios *old)
252{
253 unsigned int baud;
254 unsigned int divisor;
255 u16 prescaler;
256
257 /* The 5200B has a selectable /4 or /32 prescaler, uartclk contains the
258 * ipb freq */
259 baud = uart_get_baud_rate(port, new, old,
260 port->uartclk / (32 * 0xffff) + 1,
261 port->uartclk / 4);
262 divisor = (port->uartclk + 2 * baud) / (4 * baud);
263
264 /* select the proper prescaler and set the divisor */
265 if (divisor > 0xffff) {
266 divisor = (divisor + 4) / 8;
267 prescaler = 0xdd00; /* /32 */
268 } else
269 prescaler = 0xff00; /* /4 */
270 mpc52xx_set_divisor(PSC(port), prescaler, divisor);
271 return baud;
272}
273
274static void mpc52xx_psc_get_irq(struct uart_port *port, struct device_node *np)
275{
276 port->irqflags = IRQF_DISABLED;
277 port->irq = irq_of_parse_and_map(np, 0);
278}
279
280/* 52xx specific interrupt handler. The caller holds the port lock */
281static irqreturn_t mpc52xx_psc_handle_irq(struct uart_port *port)
282{
283 return mpc5xxx_uart_process_int(port);
284}
285
286static struct psc_ops mpc52xx_psc_ops = {
287 .fifo_init = mpc52xx_psc_fifo_init,
288 .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy,
289 .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy,
290 .rx_rdy = mpc52xx_psc_rx_rdy,
291 .tx_rdy = mpc52xx_psc_tx_rdy,
292 .tx_empty = mpc52xx_psc_tx_empty,
293 .stop_rx = mpc52xx_psc_stop_rx,
294 .start_tx = mpc52xx_psc_start_tx,
295 .stop_tx = mpc52xx_psc_stop_tx,
296 .rx_clr_irq = mpc52xx_psc_rx_clr_irq,
297 .tx_clr_irq = mpc52xx_psc_tx_clr_irq,
298 .write_char = mpc52xx_psc_write_char,
299 .read_char = mpc52xx_psc_read_char,
300 .cw_disable_ints = mpc52xx_psc_cw_disable_ints,
301 .cw_restore_ints = mpc52xx_psc_cw_restore_ints,
302 .set_baudrate = mpc5200_psc_set_baudrate,
303 .get_irq = mpc52xx_psc_get_irq,
304 .handle_irq = mpc52xx_psc_handle_irq,
305};
306
307static struct psc_ops mpc5200b_psc_ops = {
308 .fifo_init = mpc52xx_psc_fifo_init,
309 .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy,
310 .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy,
311 .rx_rdy = mpc52xx_psc_rx_rdy,
312 .tx_rdy = mpc52xx_psc_tx_rdy,
313 .tx_empty = mpc52xx_psc_tx_empty,
314 .stop_rx = mpc52xx_psc_stop_rx,
315 .start_tx = mpc52xx_psc_start_tx,
316 .stop_tx = mpc52xx_psc_stop_tx,
317 .rx_clr_irq = mpc52xx_psc_rx_clr_irq,
318 .tx_clr_irq = mpc52xx_psc_tx_clr_irq,
319 .write_char = mpc52xx_psc_write_char,
320 .read_char = mpc52xx_psc_read_char,
321 .cw_disable_ints = mpc52xx_psc_cw_disable_ints,
322 .cw_restore_ints = mpc52xx_psc_cw_restore_ints,
323 .set_baudrate = mpc5200b_psc_set_baudrate,
324 .get_irq = mpc52xx_psc_get_irq,
325 .handle_irq = mpc52xx_psc_handle_irq,
326};
327
328#endif /* CONFIG_MPC52xx */
329
330#ifdef CONFIG_PPC_MPC512x
331#define FIFO_512x(port) ((struct mpc512x_psc_fifo __iomem *)(PSC(port)+1))
332
333/* PSC FIFO Controller for mpc512x */
334struct psc_fifoc {
335 u32 fifoc_cmd;
336 u32 fifoc_int;
337 u32 fifoc_dma;
338 u32 fifoc_axe;
339 u32 fifoc_debug;
340};
341
342static struct psc_fifoc __iomem *psc_fifoc;
343static unsigned int psc_fifoc_irq;
344
345static void mpc512x_psc_fifo_init(struct uart_port *port)
346{
347 /* /32 prescaler */
348 out_be16(&PSC(port)->mpc52xx_psc_clock_select, 0xdd00);
349
350 out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);
351 out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
352 out_be32(&FIFO_512x(port)->txalarm, 1);
353 out_be32(&FIFO_512x(port)->tximr, 0);
354
355 out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);
356 out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
357 out_be32(&FIFO_512x(port)->rxalarm, 1);
358 out_be32(&FIFO_512x(port)->rximr, 0);
359
360 out_be32(&FIFO_512x(port)->tximr, MPC512x_PSC_FIFO_ALARM);
361 out_be32(&FIFO_512x(port)->rximr, MPC512x_PSC_FIFO_ALARM);
362}
363
364static int mpc512x_psc_raw_rx_rdy(struct uart_port *port)
365{
366 return !(in_be32(&FIFO_512x(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY);
367}
368
369static int mpc512x_psc_raw_tx_rdy(struct uart_port *port)
370{
371 return !(in_be32(&FIFO_512x(port)->txsr) & MPC512x_PSC_FIFO_FULL);
372}
373
374static int mpc512x_psc_rx_rdy(struct uart_port *port)
375{
376 return in_be32(&FIFO_512x(port)->rxsr)
377 & in_be32(&FIFO_512x(port)->rximr)
378 & MPC512x_PSC_FIFO_ALARM;
379}
380
381static int mpc512x_psc_tx_rdy(struct uart_port *port)
382{
383 return in_be32(&FIFO_512x(port)->txsr)
384 & in_be32(&FIFO_512x(port)->tximr)
385 & MPC512x_PSC_FIFO_ALARM;
386}
387
388static int mpc512x_psc_tx_empty(struct uart_port *port)
389{
390 return in_be32(&FIFO_512x(port)->txsr)
391 & MPC512x_PSC_FIFO_EMPTY;
392}
393
394static void mpc512x_psc_stop_rx(struct uart_port *port)
395{
396 unsigned long rx_fifo_imr;
397
398 rx_fifo_imr = in_be32(&FIFO_512x(port)->rximr);
399 rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
400 out_be32(&FIFO_512x(port)->rximr, rx_fifo_imr);
401}
402
403static void mpc512x_psc_start_tx(struct uart_port *port)
404{
405 unsigned long tx_fifo_imr;
406
407 tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
408 tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM;
409 out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
410}
411
412static void mpc512x_psc_stop_tx(struct uart_port *port)
413{
414 unsigned long tx_fifo_imr;
415
416 tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
417 tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
418 out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
419}
420
421static void mpc512x_psc_rx_clr_irq(struct uart_port *port)
422{
423 out_be32(&FIFO_512x(port)->rxisr, in_be32(&FIFO_512x(port)->rxisr));
424}
425
426static void mpc512x_psc_tx_clr_irq(struct uart_port *port)
427{
428 out_be32(&FIFO_512x(port)->txisr, in_be32(&FIFO_512x(port)->txisr));
429}
430
431static void mpc512x_psc_write_char(struct uart_port *port, unsigned char c)
432{
433 out_8(&FIFO_512x(port)->txdata_8, c);
434}
435
436static unsigned char mpc512x_psc_read_char(struct uart_port *port)
437{
438 return in_8(&FIFO_512x(port)->rxdata_8);
439}
440
441static void mpc512x_psc_cw_disable_ints(struct uart_port *port)
442{
443 port->read_status_mask =
444 in_be32(&FIFO_512x(port)->tximr) << 16 |
445 in_be32(&FIFO_512x(port)->rximr);
446 out_be32(&FIFO_512x(port)->tximr, 0);
447 out_be32(&FIFO_512x(port)->rximr, 0);
448}
449
450static void mpc512x_psc_cw_restore_ints(struct uart_port *port)
451{
452 out_be32(&FIFO_512x(port)->tximr,
453 (port->read_status_mask >> 16) & 0x7f);
454 out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f);
455}
456
457static unsigned int mpc512x_psc_set_baudrate(struct uart_port *port,
458 struct ktermios *new,
459 struct ktermios *old)
460{
461 unsigned int baud;
462 unsigned int divisor;
463
464 /*
465 * The "MPC5121e Microcontroller Reference Manual, Rev. 3" says on
466 * pg. 30-10 that the chip supports a /32 and a /10 prescaler.
467 * Furthermore, it states that "After reset, the prescaler by 10
468 * for the UART mode is selected", but the reset register value is
469 * 0x0000 which means a /32 prescaler. This is wrong.
470 *
471 * In reality using /32 prescaler doesn't work, as it is not supported!
472 * Use /16 or /10 prescaler, see "MPC5121e Hardware Design Guide",
473 * Chapter 4.1 PSC in UART Mode.
474 * Calculate with a /16 prescaler here.
475 */
476
477 /* uartclk contains the ips freq */
478 baud = uart_get_baud_rate(port, new, old,
479 port->uartclk / (16 * 0xffff) + 1,
480 port->uartclk / 16);
481 divisor = (port->uartclk + 8 * baud) / (16 * baud);
482
483 /* enable the /16 prescaler and set the divisor */
484 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
485 return baud;
486}
487
488/* Init PSC FIFO Controller */
489static int __init mpc512x_psc_fifoc_init(void)
490{
491 struct device_node *np;
492
493 np = of_find_compatible_node(NULL, NULL,
494 "fsl,mpc5121-psc-fifo");
495 if (!np) {
496 pr_err("%s: Can't find FIFOC node\n", __func__);
497 return -ENODEV;
498 }
499
500 psc_fifoc = of_iomap(np, 0);
501 if (!psc_fifoc) {
502 pr_err("%s: Can't map FIFOC\n", __func__);
503 of_node_put(np);
504 return -ENODEV;
505 }
506
507 psc_fifoc_irq = irq_of_parse_and_map(np, 0);
508 of_node_put(np);
509 if (psc_fifoc_irq == NO_IRQ) {
510 pr_err("%s: Can't get FIFOC irq\n", __func__);
511 iounmap(psc_fifoc);
512 return -ENODEV;
513 }
514
515 return 0;
516}
517
518static void __exit mpc512x_psc_fifoc_uninit(void)
519{
520 iounmap(psc_fifoc);
521}
522
523/* 512x specific interrupt handler. The caller holds the port lock */
524static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port)
525{
526 unsigned long fifoc_int;
527 int psc_num;
528
529 /* Read pending PSC FIFOC interrupts */
530 fifoc_int = in_be32(&psc_fifoc->fifoc_int);
531
532 /* Check if it is an interrupt for this port */
533 psc_num = (port->mapbase & 0xf00) >> 8;
534 if (test_bit(psc_num, &fifoc_int) ||
535 test_bit(psc_num + 16, &fifoc_int))
536 return mpc5xxx_uart_process_int(port);
537
538 return IRQ_NONE;
539}
540
541static int mpc512x_psc_clock(struct uart_port *port, int enable)
542{
543 struct clk *psc_clk;
544 int psc_num;
545 char clk_name[10];
546
547 if (uart_console(port))
548 return 0;
549
550 psc_num = (port->mapbase & 0xf00) >> 8;
551 snprintf(clk_name, sizeof(clk_name), "psc%d_clk", psc_num);
552 psc_clk = clk_get(port->dev, clk_name);
553 if (IS_ERR(psc_clk)) {
554 dev_err(port->dev, "Failed to get PSC clock entry!\n");
555 return -ENODEV;
556 }
557
558 dev_dbg(port->dev, "%s %sable\n", clk_name, enable ? "en" : "dis");
559
560 if (enable)
561 clk_enable(psc_clk);
562 else
563 clk_disable(psc_clk);
564
565 return 0;
566}
567
568static void mpc512x_psc_get_irq(struct uart_port *port, struct device_node *np)
569{
570 port->irqflags = IRQF_SHARED;
571 port->irq = psc_fifoc_irq;
572}
573
574static struct psc_ops mpc512x_psc_ops = {
575 .fifo_init = mpc512x_psc_fifo_init,
576 .raw_rx_rdy = mpc512x_psc_raw_rx_rdy,
577 .raw_tx_rdy = mpc512x_psc_raw_tx_rdy,
578 .rx_rdy = mpc512x_psc_rx_rdy,
579 .tx_rdy = mpc512x_psc_tx_rdy,
580 .tx_empty = mpc512x_psc_tx_empty,
581 .stop_rx = mpc512x_psc_stop_rx,
582 .start_tx = mpc512x_psc_start_tx,
583 .stop_tx = mpc512x_psc_stop_tx,
584 .rx_clr_irq = mpc512x_psc_rx_clr_irq,
585 .tx_clr_irq = mpc512x_psc_tx_clr_irq,
586 .write_char = mpc512x_psc_write_char,
587 .read_char = mpc512x_psc_read_char,
588 .cw_disable_ints = mpc512x_psc_cw_disable_ints,
589 .cw_restore_ints = mpc512x_psc_cw_restore_ints,
590 .set_baudrate = mpc512x_psc_set_baudrate,
591 .clock = mpc512x_psc_clock,
592 .fifoc_init = mpc512x_psc_fifoc_init,
593 .fifoc_uninit = mpc512x_psc_fifoc_uninit,
594 .get_irq = mpc512x_psc_get_irq,
595 .handle_irq = mpc512x_psc_handle_irq,
596};
597#endif
598
599static struct psc_ops *psc_ops;
600
601/* ======================================================================== */
602/* UART operations */
603/* ======================================================================== */
604
605static unsigned int
606mpc52xx_uart_tx_empty(struct uart_port *port)
607{
608 return psc_ops->tx_empty(port) ? TIOCSER_TEMT : 0;
609}
610
611static void
612mpc52xx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
613{
614 if (mctrl & TIOCM_RTS)
615 out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS);
616 else
617 out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS);
618}
619
620static unsigned int
621mpc52xx_uart_get_mctrl(struct uart_port *port)
622{
623 unsigned int ret = TIOCM_DSR;
624 u8 status = in_8(&PSC(port)->mpc52xx_psc_ipcr);
625
626 if (!(status & MPC52xx_PSC_CTS))
627 ret |= TIOCM_CTS;
628 if (!(status & MPC52xx_PSC_DCD))
629 ret |= TIOCM_CAR;
630
631 return ret;
632}
633
634static void
635mpc52xx_uart_stop_tx(struct uart_port *port)
636{
637 /* port->lock taken by caller */
638 psc_ops->stop_tx(port);
639}
640
641static void
642mpc52xx_uart_start_tx(struct uart_port *port)
643{
644 /* port->lock taken by caller */
645 psc_ops->start_tx(port);
646}
647
648static void
649mpc52xx_uart_send_xchar(struct uart_port *port, char ch)
650{
651 unsigned long flags;
652 spin_lock_irqsave(&port->lock, flags);
653
654 port->x_char = ch;
655 if (ch) {
656 /* Make sure tx interrupts are on */
657 /* Truly necessary ??? They should be anyway */
658 psc_ops->start_tx(port);
659 }
660
661 spin_unlock_irqrestore(&port->lock, flags);
662}
663
664static void
665mpc52xx_uart_stop_rx(struct uart_port *port)
666{
667 /* port->lock taken by caller */
668 psc_ops->stop_rx(port);
669}
670
671static void
672mpc52xx_uart_enable_ms(struct uart_port *port)
673{
674 struct mpc52xx_psc __iomem *psc = PSC(port);
675
676 /* clear D_*-bits by reading them */
677 in_8(&psc->mpc52xx_psc_ipcr);
678 /* enable CTS and DCD as IPC interrupts */
679 out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);
680
681 port->read_status_mask |= MPC52xx_PSC_IMR_IPC;
682 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
683}
684
685static void
686mpc52xx_uart_break_ctl(struct uart_port *port, int ctl)
687{
688 unsigned long flags;
689 spin_lock_irqsave(&port->lock, flags);
690
691 if (ctl == -1)
692 out_8(&PSC(port)->command, MPC52xx_PSC_START_BRK);
693 else
694 out_8(&PSC(port)->command, MPC52xx_PSC_STOP_BRK);
695
696 spin_unlock_irqrestore(&port->lock, flags);
697}
698
699static int
700mpc52xx_uart_startup(struct uart_port *port)
701{
702 struct mpc52xx_psc __iomem *psc = PSC(port);
703 int ret;
704
705 if (psc_ops->clock) {
706 ret = psc_ops->clock(port, 1);
707 if (ret)
708 return ret;
709 }
710
711 /* Request IRQ */
712 ret = request_irq(port->irq, mpc52xx_uart_int,
713 port->irqflags, "mpc52xx_psc_uart", port);
714 if (ret)
715 return ret;
716
717 /* Reset/activate the port, clear and enable interrupts */
718 out_8(&psc->command, MPC52xx_PSC_RST_RX);
719 out_8(&psc->command, MPC52xx_PSC_RST_TX);
720
721 out_be32(&psc->sicr, 0); /* UART mode DCD ignored */
722
723 psc_ops->fifo_init(port);
724
725 out_8(&psc->command, MPC52xx_PSC_TX_ENABLE);
726 out_8(&psc->command, MPC52xx_PSC_RX_ENABLE);
727
728 return 0;
729}
730
731static void
732mpc52xx_uart_shutdown(struct uart_port *port)
733{
734 struct mpc52xx_psc __iomem *psc = PSC(port);
735
736 /* Shut down the port. Leave TX active if on a console port */
737 out_8(&psc->command, MPC52xx_PSC_RST_RX);
738 if (!uart_console(port))
739 out_8(&psc->command, MPC52xx_PSC_RST_TX);
740
741 port->read_status_mask = 0;
742 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
743
744 if (psc_ops->clock)
745 psc_ops->clock(port, 0);
746
747 /* Release interrupt */
748 free_irq(port->irq, port);
749}
750
751static void
752mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new,
753 struct ktermios *old)
754{
755 struct mpc52xx_psc __iomem *psc = PSC(port);
756 unsigned long flags;
757 unsigned char mr1, mr2;
758 unsigned int j;
759 unsigned int baud;
760
761 /* Prepare what we're gonna write */
762 mr1 = 0;
763
764 switch (new->c_cflag & CSIZE) {
765 case CS5: mr1 |= MPC52xx_PSC_MODE_5_BITS;
766 break;
767 case CS6: mr1 |= MPC52xx_PSC_MODE_6_BITS;
768 break;
769 case CS7: mr1 |= MPC52xx_PSC_MODE_7_BITS;
770 break;
771 case CS8:
772 default: mr1 |= MPC52xx_PSC_MODE_8_BITS;
773 }
774
775 if (new->c_cflag & PARENB) {
776 mr1 |= (new->c_cflag & PARODD) ?
777 MPC52xx_PSC_MODE_PARODD : MPC52xx_PSC_MODE_PAREVEN;
778 } else
779 mr1 |= MPC52xx_PSC_MODE_PARNONE;
780
781
782 mr2 = 0;
783
784 if (new->c_cflag & CSTOPB)
785 mr2 |= MPC52xx_PSC_MODE_TWO_STOP;
786 else
787 mr2 |= ((new->c_cflag & CSIZE) == CS5) ?
788 MPC52xx_PSC_MODE_ONE_STOP_5_BITS :
789 MPC52xx_PSC_MODE_ONE_STOP;
790
791 if (new->c_cflag & CRTSCTS) {
792 mr1 |= MPC52xx_PSC_MODE_RXRTS;
793 mr2 |= MPC52xx_PSC_MODE_TXCTS;
794 }
795
796 /* Get the lock */
797 spin_lock_irqsave(&port->lock, flags);
798
799 /* Do our best to flush TX & RX, so we don't lose anything */
800 /* But we don't wait indefinitely ! */
801 j = 5000000; /* Maximum wait */
802 /* FIXME Can't receive chars since set_termios might be called at early
803 * boot for the console, all stuff is not yet ready to receive at that
804 * time and that just makes the kernel oops */
805 /* while (j-- && mpc52xx_uart_int_rx_chars(port)); */
806 while (!mpc52xx_uart_tx_empty(port) && --j)
807 udelay(1);
808
809 if (!j)
810 printk(KERN_ERR "mpc52xx_uart.c: "
811 "Unable to flush RX & TX fifos in-time in set_termios."
812 "Some chars may have been lost.\n");
813
814 /* Reset the TX & RX */
815 out_8(&psc->command, MPC52xx_PSC_RST_RX);
816 out_8(&psc->command, MPC52xx_PSC_RST_TX);
817
818 /* Send new mode settings */
819 out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
820 out_8(&psc->mode, mr1);
821 out_8(&psc->mode, mr2);
822 baud = psc_ops->set_baudrate(port, new, old);
823
824 /* Update the per-port timeout */
825 uart_update_timeout(port, new->c_cflag, baud);
826
827 if (UART_ENABLE_MS(port, new->c_cflag))
828 mpc52xx_uart_enable_ms(port);
829
830 /* Reenable TX & RX */
831 out_8(&psc->command, MPC52xx_PSC_TX_ENABLE);
832 out_8(&psc->command, MPC52xx_PSC_RX_ENABLE);
833
834 /* We're all set, release the lock */
835 spin_unlock_irqrestore(&port->lock, flags);
836}
837
838static const char *
839mpc52xx_uart_type(struct uart_port *port)
840{
841 return port->type == PORT_MPC52xx ? "MPC52xx PSC" : NULL;
842}
843
844static void
845mpc52xx_uart_release_port(struct uart_port *port)
846{
847 /* remapped by us ? */
848 if (port->flags & UPF_IOREMAP) {
849 iounmap(port->membase);
850 port->membase = NULL;
851 }
852
853 release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc));
854}
855
856static int
857mpc52xx_uart_request_port(struct uart_port *port)
858{
859 int err;
860
861 if (port->flags & UPF_IOREMAP) /* Need to remap ? */
862 port->membase = ioremap(port->mapbase,
863 sizeof(struct mpc52xx_psc));
864
865 if (!port->membase)
866 return -EINVAL;
867
868 err = request_mem_region(port->mapbase, sizeof(struct mpc52xx_psc),
869 "mpc52xx_psc_uart") != NULL ? 0 : -EBUSY;
870
871 if (err && (port->flags & UPF_IOREMAP)) {
872 iounmap(port->membase);
873 port->membase = NULL;
874 }
875
876 return err;
877}
878
879static void
880mpc52xx_uart_config_port(struct uart_port *port, int flags)
881{
882 if ((flags & UART_CONFIG_TYPE)
883 && (mpc52xx_uart_request_port(port) == 0))
884 port->type = PORT_MPC52xx;
885}
886
887static int
888mpc52xx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
889{
890 if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPC52xx)
891 return -EINVAL;
892
893 if ((ser->irq != port->irq) ||
894 (ser->io_type != UPIO_MEM) ||
895 (ser->baud_base != port->uartclk) ||
896 (ser->iomem_base != (void *)port->mapbase) ||
897 (ser->hub6 != 0))
898 return -EINVAL;
899
900 return 0;
901}
902
903
904static struct uart_ops mpc52xx_uart_ops = {
905 .tx_empty = mpc52xx_uart_tx_empty,
906 .set_mctrl = mpc52xx_uart_set_mctrl,
907 .get_mctrl = mpc52xx_uart_get_mctrl,
908 .stop_tx = mpc52xx_uart_stop_tx,
909 .start_tx = mpc52xx_uart_start_tx,
910 .send_xchar = mpc52xx_uart_send_xchar,
911 .stop_rx = mpc52xx_uart_stop_rx,
912 .enable_ms = mpc52xx_uart_enable_ms,
913 .break_ctl = mpc52xx_uart_break_ctl,
914 .startup = mpc52xx_uart_startup,
915 .shutdown = mpc52xx_uart_shutdown,
916 .set_termios = mpc52xx_uart_set_termios,
917/* .pm = mpc52xx_uart_pm, Not supported yet */
918/* .set_wake = mpc52xx_uart_set_wake, Not supported yet */
919 .type = mpc52xx_uart_type,
920 .release_port = mpc52xx_uart_release_port,
921 .request_port = mpc52xx_uart_request_port,
922 .config_port = mpc52xx_uart_config_port,
923 .verify_port = mpc52xx_uart_verify_port
924};
925
926
927/* ======================================================================== */
928/* Interrupt handling */
929/* ======================================================================== */
930
931static inline int
932mpc52xx_uart_int_rx_chars(struct uart_port *port)
933{
934 struct tty_struct *tty = port->state->port.tty;
935 unsigned char ch, flag;
936 unsigned short status;
937
938 /* While we can read, do so ! */
939 while (psc_ops->raw_rx_rdy(port)) {
940 /* Get the char */
941 ch = psc_ops->read_char(port);
942
943 /* Handle sysreq char */
944#ifdef SUPPORT_SYSRQ
945 if (uart_handle_sysrq_char(port, ch)) {
946 port->sysrq = 0;
947 continue;
948 }
949#endif
950
951 /* Store it */
952
953 flag = TTY_NORMAL;
954 port->icount.rx++;
955
956 status = in_be16(&PSC(port)->mpc52xx_psc_status);
957
958 if (status & (MPC52xx_PSC_SR_PE |
959 MPC52xx_PSC_SR_FE |
960 MPC52xx_PSC_SR_RB)) {
961
962 if (status & MPC52xx_PSC_SR_RB) {
963 flag = TTY_BREAK;
964 uart_handle_break(port);
965 port->icount.brk++;
966 } else if (status & MPC52xx_PSC_SR_PE) {
967 flag = TTY_PARITY;
968 port->icount.parity++;
969 }
970 else if (status & MPC52xx_PSC_SR_FE) {
971 flag = TTY_FRAME;
972 port->icount.frame++;
973 }
974
975 /* Clear error condition */
976 out_8(&PSC(port)->command, MPC52xx_PSC_RST_ERR_STAT);
977
978 }
979 tty_insert_flip_char(tty, ch, flag);
980 if (status & MPC52xx_PSC_SR_OE) {
981 /*
982 * Overrun is special, since it's
983 * reported immediately, and doesn't
984 * affect the current character
985 */
986 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
987 port->icount.overrun++;
988 }
989 }
990
991 spin_unlock(&port->lock);
992 tty_flip_buffer_push(tty);
993 spin_lock(&port->lock);
994
995 return psc_ops->raw_rx_rdy(port);
996}
997
998static inline int
999mpc52xx_uart_int_tx_chars(struct uart_port *port)
1000{
1001 struct circ_buf *xmit = &port->state->xmit;
1002
1003 /* Process out of band chars */
1004 if (port->x_char) {
1005 psc_ops->write_char(port, port->x_char);
1006 port->icount.tx++;
1007 port->x_char = 0;
1008 return 1;
1009 }
1010
1011 /* Nothing to do ? */
1012 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
1013 mpc52xx_uart_stop_tx(port);
1014 return 0;
1015 }
1016
1017 /* Send chars */
1018 while (psc_ops->raw_tx_rdy(port)) {
1019 psc_ops->write_char(port, xmit->buf[xmit->tail]);
1020 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1021 port->icount.tx++;
1022 if (uart_circ_empty(xmit))
1023 break;
1024 }
1025
1026 /* Wake up */
1027 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1028 uart_write_wakeup(port);
1029
1030 /* Maybe we're done after all */
1031 if (uart_circ_empty(xmit)) {
1032 mpc52xx_uart_stop_tx(port);
1033 return 0;
1034 }
1035
1036 return 1;
1037}
1038
1039static irqreturn_t
1040mpc5xxx_uart_process_int(struct uart_port *port)
1041{
1042 unsigned long pass = ISR_PASS_LIMIT;
1043 unsigned int keepgoing;
1044 u8 status;
1045
1046 /* While we have stuff to do, we continue */
1047 do {
1048 /* If we don't find anything to do, we stop */
1049 keepgoing = 0;
1050
1051 psc_ops->rx_clr_irq(port);
1052 if (psc_ops->rx_rdy(port))
1053 keepgoing |= mpc52xx_uart_int_rx_chars(port);
1054
1055 psc_ops->tx_clr_irq(port);
1056 if (psc_ops->tx_rdy(port))
1057 keepgoing |= mpc52xx_uart_int_tx_chars(port);
1058
1059 status = in_8(&PSC(port)->mpc52xx_psc_ipcr);
1060 if (status & MPC52xx_PSC_D_DCD)
1061 uart_handle_dcd_change(port, !(status & MPC52xx_PSC_DCD));
1062
1063 if (status & MPC52xx_PSC_D_CTS)
1064 uart_handle_cts_change(port, !(status & MPC52xx_PSC_CTS));
1065
1066 /* Limit number of iteration */
1067 if (!(--pass))
1068 keepgoing = 0;
1069
1070 } while (keepgoing);
1071
1072 return IRQ_HANDLED;
1073}
1074
1075static irqreturn_t
1076mpc52xx_uart_int(int irq, void *dev_id)
1077{
1078 struct uart_port *port = dev_id;
1079 irqreturn_t ret;
1080
1081 spin_lock(&port->lock);
1082
1083 ret = psc_ops->handle_irq(port);
1084
1085 spin_unlock(&port->lock);
1086
1087 return ret;
1088}
1089
1090/* ======================================================================== */
1091/* Console ( if applicable ) */
1092/* ======================================================================== */
1093
1094#ifdef CONFIG_SERIAL_MPC52xx_CONSOLE
1095
1096static void __init
1097mpc52xx_console_get_options(struct uart_port *port,
1098 int *baud, int *parity, int *bits, int *flow)
1099{
1100 struct mpc52xx_psc __iomem *psc = PSC(port);
1101 unsigned char mr1;
1102
1103 pr_debug("mpc52xx_console_get_options(port=%p)\n", port);
1104
1105 /* Read the mode registers */
1106 out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
1107 mr1 = in_8(&psc->mode);
1108
1109 /* CT{U,L}R are write-only ! */
1110 *baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
1111
1112 /* Parse them */
1113 switch (mr1 & MPC52xx_PSC_MODE_BITS_MASK) {
1114 case MPC52xx_PSC_MODE_5_BITS:
1115 *bits = 5;
1116 break;
1117 case MPC52xx_PSC_MODE_6_BITS:
1118 *bits = 6;
1119 break;
1120 case MPC52xx_PSC_MODE_7_BITS:
1121 *bits = 7;
1122 break;
1123 case MPC52xx_PSC_MODE_8_BITS:
1124 default:
1125 *bits = 8;
1126 }
1127
1128 if (mr1 & MPC52xx_PSC_MODE_PARNONE)
1129 *parity = 'n';
1130 else
1131 *parity = mr1 & MPC52xx_PSC_MODE_PARODD ? 'o' : 'e';
1132}
1133
1134static void
1135mpc52xx_console_write(struct console *co, const char *s, unsigned int count)
1136{
1137 struct uart_port *port = &mpc52xx_uart_ports[co->index];
1138 unsigned int i, j;
1139
1140 /* Disable interrupts */
1141 psc_ops->cw_disable_ints(port);
1142
1143 /* Wait the TX buffer to be empty */
1144 j = 5000000; /* Maximum wait */
1145 while (!mpc52xx_uart_tx_empty(port) && --j)
1146 udelay(1);
1147
1148 /* Write all the chars */
1149 for (i = 0; i < count; i++, s++) {
1150 /* Line return handling */
1151 if (*s == '\n')
1152 psc_ops->write_char(port, '\r');
1153
1154 /* Send the char */
1155 psc_ops->write_char(port, *s);
1156
1157 /* Wait the TX buffer to be empty */
1158 j = 20000; /* Maximum wait */
1159 while (!mpc52xx_uart_tx_empty(port) && --j)
1160 udelay(1);
1161 }
1162
1163 /* Restore interrupt state */
1164 psc_ops->cw_restore_ints(port);
1165}
1166
1167
1168static int __init
1169mpc52xx_console_setup(struct console *co, char *options)
1170{
1171 struct uart_port *port = &mpc52xx_uart_ports[co->index];
1172 struct device_node *np = mpc52xx_uart_nodes[co->index];
1173 unsigned int uartclk;
1174 struct resource res;
1175 int ret;
1176
1177 int baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
1178 int bits = 8;
1179 int parity = 'n';
1180 int flow = 'n';
1181
1182 pr_debug("mpc52xx_console_setup co=%p, co->index=%i, options=%s\n",
1183 co, co->index, options);
1184
1185 if ((co->index < 0) || (co->index >= MPC52xx_PSC_MAXNUM)) {
1186 pr_debug("PSC%x out of range\n", co->index);
1187 return -EINVAL;
1188 }
1189
1190 if (!np) {
1191 pr_debug("PSC%x not found in device tree\n", co->index);
1192 return -EINVAL;
1193 }
1194
1195 pr_debug("Console on ttyPSC%x is %s\n",
1196 co->index, mpc52xx_uart_nodes[co->index]->full_name);
1197
1198 /* Fetch register locations */
1199 ret = of_address_to_resource(np, 0, &res);
1200 if (ret) {
1201 pr_debug("Could not get resources for PSC%x\n", co->index);
1202 return ret;
1203 }
1204
1205 uartclk = mpc5xxx_get_bus_frequency(np);
1206 if (uartclk == 0) {
1207 pr_debug("Could not find uart clock frequency!\n");
1208 return -EINVAL;
1209 }
1210
1211 /* Basic port init. Needed since we use some uart_??? func before
1212 * real init for early access */
1213 spin_lock_init(&port->lock);
1214 port->uartclk = uartclk;
1215 port->ops = &mpc52xx_uart_ops;
1216 port->mapbase = res.start;
1217 port->membase = ioremap(res.start, sizeof(struct mpc52xx_psc));
1218 port->irq = irq_of_parse_and_map(np, 0);
1219
1220 if (port->membase == NULL)
1221 return -EINVAL;
1222
1223 pr_debug("mpc52xx-psc uart at %p, mapped to %p, irq=%x, freq=%i\n",
1224 (void *)port->mapbase, port->membase,
1225 port->irq, port->uartclk);
1226
1227 /* Setup the port parameters accoding to options */
1228 if (options)
1229 uart_parse_options(options, &baud, &parity, &bits, &flow);
1230 else
1231 mpc52xx_console_get_options(port, &baud, &parity, &bits, &flow);
1232
1233 pr_debug("Setting console parameters: %i %i%c1 flow=%c\n",
1234 baud, bits, parity, flow);
1235
1236 return uart_set_options(port, co, baud, parity, bits, flow);
1237}
1238
1239
1240static struct uart_driver mpc52xx_uart_driver;
1241
1242static struct console mpc52xx_console = {
1243 .name = "ttyPSC",
1244 .write = mpc52xx_console_write,
1245 .device = uart_console_device,
1246 .setup = mpc52xx_console_setup,
1247 .flags = CON_PRINTBUFFER,
1248 .index = -1, /* Specified on the cmdline (e.g. console=ttyPSC0) */
1249 .data = &mpc52xx_uart_driver,
1250};
1251
1252
1253static int __init
1254mpc52xx_console_init(void)
1255{
1256 mpc52xx_uart_of_enumerate();
1257 register_console(&mpc52xx_console);
1258 return 0;
1259}
1260
1261console_initcall(mpc52xx_console_init);
1262
1263#define MPC52xx_PSC_CONSOLE &mpc52xx_console
1264#else
1265#define MPC52xx_PSC_CONSOLE NULL
1266#endif
1267
1268
1269/* ======================================================================== */
1270/* UART Driver */
1271/* ======================================================================== */
1272
1273static struct uart_driver mpc52xx_uart_driver = {
1274 .driver_name = "mpc52xx_psc_uart",
1275 .dev_name = "ttyPSC",
1276 .major = SERIAL_PSC_MAJOR,
1277 .minor = SERIAL_PSC_MINOR,
1278 .nr = MPC52xx_PSC_MAXNUM,
1279 .cons = MPC52xx_PSC_CONSOLE,
1280};
1281
1282/* ======================================================================== */
1283/* OF Platform Driver */
1284/* ======================================================================== */
1285
1286static struct of_device_id mpc52xx_uart_of_match[] = {
1287#ifdef CONFIG_PPC_MPC52xx
1288 { .compatible = "fsl,mpc5200b-psc-uart", .data = &mpc5200b_psc_ops, },
1289 { .compatible = "fsl,mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1290 /* binding used by old lite5200 device trees: */
1291 { .compatible = "mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1292 /* binding used by efika: */
1293 { .compatible = "mpc5200-serial", .data = &mpc52xx_psc_ops, },
1294#endif
1295#ifdef CONFIG_PPC_MPC512x
1296 { .compatible = "fsl,mpc5121-psc-uart", .data = &mpc512x_psc_ops, },
1297#endif
1298 {},
1299};
1300
1301static int __devinit
1302mpc52xx_uart_of_probe(struct platform_device *op, const struct of_device_id *match)
1303{
1304 int idx = -1;
1305 unsigned int uartclk;
1306 struct uart_port *port = NULL;
1307 struct resource res;
1308 int ret;
1309
1310 dev_dbg(&op->dev, "mpc52xx_uart_probe(op=%p, match=%p)\n", op, match);
1311
1312 /* Check validity & presence */
1313 for (idx = 0; idx < MPC52xx_PSC_MAXNUM; idx++)
1314 if (mpc52xx_uart_nodes[idx] == op->dev.of_node)
1315 break;
1316 if (idx >= MPC52xx_PSC_MAXNUM)
1317 return -EINVAL;
1318 pr_debug("Found %s assigned to ttyPSC%x\n",
1319 mpc52xx_uart_nodes[idx]->full_name, idx);
1320
1321 /* set the uart clock to the input clock of the psc, the different
1322 * prescalers are taken into account in the set_baudrate() methods
1323 * of the respective chip */
1324 uartclk = mpc5xxx_get_bus_frequency(op->dev.of_node);
1325 if (uartclk == 0) {
1326 dev_dbg(&op->dev, "Could not find uart clock frequency!\n");
1327 return -EINVAL;
1328 }
1329
1330 /* Init the port structure */
1331 port = &mpc52xx_uart_ports[idx];
1332
1333 spin_lock_init(&port->lock);
1334 port->uartclk = uartclk;
1335 port->fifosize = 512;
1336 port->iotype = UPIO_MEM;
1337 port->flags = UPF_BOOT_AUTOCONF |
1338 (uart_console(port) ? 0 : UPF_IOREMAP);
1339 port->line = idx;
1340 port->ops = &mpc52xx_uart_ops;
1341 port->dev = &op->dev;
1342
1343 /* Search for IRQ and mapbase */
1344 ret = of_address_to_resource(op->dev.of_node, 0, &res);
1345 if (ret)
1346 return ret;
1347
1348 port->mapbase = res.start;
1349 if (!port->mapbase) {
1350 dev_dbg(&op->dev, "Could not allocate resources for PSC\n");
1351 return -EINVAL;
1352 }
1353
1354 psc_ops->get_irq(port, op->dev.of_node);
1355 if (port->irq == NO_IRQ) {
1356 dev_dbg(&op->dev, "Could not get irq\n");
1357 return -EINVAL;
1358 }
1359
1360 dev_dbg(&op->dev, "mpc52xx-psc uart at %p, irq=%x, freq=%i\n",
1361 (void *)port->mapbase, port->irq, port->uartclk);
1362
1363 /* Add the port to the uart sub-system */
1364 ret = uart_add_one_port(&mpc52xx_uart_driver, port);
1365 if (ret)
1366 return ret;
1367
1368 dev_set_drvdata(&op->dev, (void *)port);
1369 return 0;
1370}
1371
1372static int
1373mpc52xx_uart_of_remove(struct platform_device *op)
1374{
1375 struct uart_port *port = dev_get_drvdata(&op->dev);
1376 dev_set_drvdata(&op->dev, NULL);
1377
1378 if (port)
1379 uart_remove_one_port(&mpc52xx_uart_driver, port);
1380
1381 return 0;
1382}
1383
1384#ifdef CONFIG_PM
1385static int
1386mpc52xx_uart_of_suspend(struct platform_device *op, pm_message_t state)
1387{
1388 struct uart_port *port = (struct uart_port *) dev_get_drvdata(&op->dev);
1389
1390 if (port)
1391 uart_suspend_port(&mpc52xx_uart_driver, port);
1392
1393 return 0;
1394}
1395
1396static int
1397mpc52xx_uart_of_resume(struct platform_device *op)
1398{
1399 struct uart_port *port = (struct uart_port *) dev_get_drvdata(&op->dev);
1400
1401 if (port)
1402 uart_resume_port(&mpc52xx_uart_driver, port);
1403
1404 return 0;
1405}
1406#endif
1407
1408static void
1409mpc52xx_uart_of_assign(struct device_node *np)
1410{
1411 int i;
1412
1413 /* Find the first free PSC number */
1414 for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
1415 if (mpc52xx_uart_nodes[i] == NULL) {
1416 of_node_get(np);
1417 mpc52xx_uart_nodes[i] = np;
1418 return;
1419 }
1420 }
1421}
1422
1423static void
1424mpc52xx_uart_of_enumerate(void)
1425{
1426 static int enum_done;
1427 struct device_node *np;
1428 const struct of_device_id *match;
1429 int i;
1430
1431 if (enum_done)
1432 return;
1433
1434 /* Assign index to each PSC in device tree */
1435 for_each_matching_node(np, mpc52xx_uart_of_match) {
1436 match = of_match_node(mpc52xx_uart_of_match, np);
1437 psc_ops = match->data;
1438 mpc52xx_uart_of_assign(np);
1439 }
1440
1441 enum_done = 1;
1442
1443 for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
1444 if (mpc52xx_uart_nodes[i])
1445 pr_debug("%s assigned to ttyPSC%x\n",
1446 mpc52xx_uart_nodes[i]->full_name, i);
1447 }
1448}
1449
1450MODULE_DEVICE_TABLE(of, mpc52xx_uart_of_match);
1451
1452static struct of_platform_driver mpc52xx_uart_of_driver = {
1453 .probe = mpc52xx_uart_of_probe,
1454 .remove = mpc52xx_uart_of_remove,
1455#ifdef CONFIG_PM
1456 .suspend = mpc52xx_uart_of_suspend,
1457 .resume = mpc52xx_uart_of_resume,
1458#endif
1459 .driver = {
1460 .name = "mpc52xx-psc-uart",
1461 .owner = THIS_MODULE,
1462 .of_match_table = mpc52xx_uart_of_match,
1463 },
1464};
1465
1466
1467/* ======================================================================== */
1468/* Module */
1469/* ======================================================================== */
1470
1471static int __init
1472mpc52xx_uart_init(void)
1473{
1474 int ret;
1475
1476 printk(KERN_INFO "Serial: MPC52xx PSC UART driver\n");
1477
1478 ret = uart_register_driver(&mpc52xx_uart_driver);
1479 if (ret) {
1480 printk(KERN_ERR "%s: uart_register_driver failed (%i)\n",
1481 __FILE__, ret);
1482 return ret;
1483 }
1484
1485 mpc52xx_uart_of_enumerate();
1486
1487 /*
1488 * Map the PSC FIFO Controller and init if on MPC512x.
1489 */
1490 if (psc_ops && psc_ops->fifoc_init) {
1491 ret = psc_ops->fifoc_init();
1492 if (ret)
1493 return ret;
1494 }
1495
1496 ret = of_register_platform_driver(&mpc52xx_uart_of_driver);
1497 if (ret) {
1498 printk(KERN_ERR "%s: of_register_platform_driver failed (%i)\n",
1499 __FILE__, ret);
1500 uart_unregister_driver(&mpc52xx_uart_driver);
1501 return ret;
1502 }
1503
1504 return 0;
1505}
1506
1507static void __exit
1508mpc52xx_uart_exit(void)
1509{
1510 if (psc_ops->fifoc_uninit)
1511 psc_ops->fifoc_uninit();
1512
1513 of_unregister_platform_driver(&mpc52xx_uart_of_driver);
1514 uart_unregister_driver(&mpc52xx_uart_driver);
1515}
1516
1517
1518module_init(mpc52xx_uart_init);
1519module_exit(mpc52xx_uart_exit);
1520
1521MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>");
1522MODULE_DESCRIPTION("Freescale MPC52xx PSC UART");
1523MODULE_LICENSE("GPL");
diff --git a/drivers/serial/mpsc.c b/drivers/serial/mpsc.c
deleted file mode 100644
index 6a9c6605666a..000000000000
--- a/drivers/serial/mpsc.c
+++ /dev/null
@@ -1,2159 +0,0 @@
1/*
2 * Generic driver for the MPSC (UART mode) on Marvell parts (e.g., GT64240,
3 * GT64260, MV64340, MV64360, GT96100, ... ).
4 *
5 * Author: Mark A. Greer <mgreer@mvista.com>
6 *
7 * Based on an old MPSC driver that was in the linuxppc tree. It appears to
8 * have been created by Chris Zankel (formerly of MontaVista) but there
9 * is no proper Copyright so I'm not sure. Apparently, parts were also
10 * taken from PPCBoot (now U-Boot). Also based on drivers/serial/8250.c
11 * by Russell King.
12 *
13 * 2004 (c) MontaVista, Software, Inc. This file is licensed under
14 * the terms of the GNU General Public License version 2. This program
15 * is licensed "as is" without any warranty of any kind, whether express
16 * or implied.
17 */
18/*
19 * The MPSC interface is much like a typical network controller's interface.
20 * That is, you set up separate rings of descriptors for transmitting and
21 * receiving data. There is also a pool of buffers with (one buffer per
22 * descriptor) that incoming data are dma'd into or outgoing data are dma'd
23 * out of.
24 *
25 * The MPSC requires two other controllers to be able to work. The Baud Rate
26 * Generator (BRG) provides a clock at programmable frequencies which determines
27 * the baud rate. The Serial DMA Controller (SDMA) takes incoming data from the
28 * MPSC and DMA's it into memory or DMA's outgoing data and passes it to the
29 * MPSC. It is actually the SDMA interrupt that the driver uses to keep the
30 * transmit and receive "engines" going (i.e., indicate data has been
31 * transmitted or received).
32 *
33 * NOTES:
34 *
35 * 1) Some chips have an erratum where several regs cannot be
36 * read. To work around that, we keep a local copy of those regs in
37 * 'mpsc_port_info'.
38 *
39 * 2) Some chips have an erratum where the ctlr will hang when the SDMA ctlr
40 * accesses system mem with coherency enabled. For that reason, the driver
41 * assumes that coherency for that ctlr has been disabled. This means
42 * that when in a cache coherent system, the driver has to manually manage
43 * the data cache on the areas that it touches because the dma_* macro are
44 * basically no-ops.
45 *
46 * 3) There is an erratum (on PPC) where you can't use the instruction to do
47 * a DMA_TO_DEVICE/cache clean so DMA_BIDIRECTIONAL/flushes are used in places
48 * where a DMA_TO_DEVICE/clean would have [otherwise] sufficed.
49 *
50 * 4) AFAICT, hardware flow control isn't supported by the controller --MAG.
51 */
52
53
54#if defined(CONFIG_SERIAL_MPSC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
55#define SUPPORT_SYSRQ
56#endif
57
58#include <linux/module.h>
59#include <linux/moduleparam.h>
60#include <linux/tty.h>
61#include <linux/tty_flip.h>
62#include <linux/ioport.h>
63#include <linux/init.h>
64#include <linux/console.h>
65#include <linux/sysrq.h>
66#include <linux/serial.h>
67#include <linux/serial_core.h>
68#include <linux/delay.h>
69#include <linux/device.h>
70#include <linux/dma-mapping.h>
71#include <linux/mv643xx.h>
72#include <linux/platform_device.h>
73#include <linux/gfp.h>
74
75#include <asm/io.h>
76#include <asm/irq.h>
77
78#define MPSC_NUM_CTLRS 2
79
80/*
81 * Descriptors and buffers must be cache line aligned.
82 * Buffers lengths must be multiple of cache line size.
83 * Number of Tx & Rx descriptors must be powers of 2.
84 */
85#define MPSC_RXR_ENTRIES 32
86#define MPSC_RXRE_SIZE dma_get_cache_alignment()
87#define MPSC_RXR_SIZE (MPSC_RXR_ENTRIES * MPSC_RXRE_SIZE)
88#define MPSC_RXBE_SIZE dma_get_cache_alignment()
89#define MPSC_RXB_SIZE (MPSC_RXR_ENTRIES * MPSC_RXBE_SIZE)
90
91#define MPSC_TXR_ENTRIES 32
92#define MPSC_TXRE_SIZE dma_get_cache_alignment()
93#define MPSC_TXR_SIZE (MPSC_TXR_ENTRIES * MPSC_TXRE_SIZE)
94#define MPSC_TXBE_SIZE dma_get_cache_alignment()
95#define MPSC_TXB_SIZE (MPSC_TXR_ENTRIES * MPSC_TXBE_SIZE)
96
97#define MPSC_DMA_ALLOC_SIZE (MPSC_RXR_SIZE + MPSC_RXB_SIZE + MPSC_TXR_SIZE \
98 + MPSC_TXB_SIZE + dma_get_cache_alignment() /* for alignment */)
99
100/* Rx and Tx Ring entry descriptors -- assume entry size is <= cacheline size */
101struct mpsc_rx_desc {
102 u16 bufsize;
103 u16 bytecnt;
104 u32 cmdstat;
105 u32 link;
106 u32 buf_ptr;
107} __attribute((packed));
108
109struct mpsc_tx_desc {
110 u16 bytecnt;
111 u16 shadow;
112 u32 cmdstat;
113 u32 link;
114 u32 buf_ptr;
115} __attribute((packed));
116
117/*
118 * Some regs that have the erratum that you can't read them are are shared
119 * between the two MPSC controllers. This struct contains those shared regs.
120 */
121struct mpsc_shared_regs {
122 phys_addr_t mpsc_routing_base_p;
123 phys_addr_t sdma_intr_base_p;
124
125 void __iomem *mpsc_routing_base;
126 void __iomem *sdma_intr_base;
127
128 u32 MPSC_MRR_m;
129 u32 MPSC_RCRR_m;
130 u32 MPSC_TCRR_m;
131 u32 SDMA_INTR_CAUSE_m;
132 u32 SDMA_INTR_MASK_m;
133};
134
135/* The main driver data structure */
136struct mpsc_port_info {
137 struct uart_port port; /* Overlay uart_port structure */
138
139 /* Internal driver state for this ctlr */
140 u8 ready;
141 u8 rcv_data;
142 tcflag_t c_iflag; /* save termios->c_iflag */
143 tcflag_t c_cflag; /* save termios->c_cflag */
144
145 /* Info passed in from platform */
146 u8 mirror_regs; /* Need to mirror regs? */
147 u8 cache_mgmt; /* Need manual cache mgmt? */
148 u8 brg_can_tune; /* BRG has baud tuning? */
149 u32 brg_clk_src;
150 u16 mpsc_max_idle;
151 int default_baud;
152 int default_bits;
153 int default_parity;
154 int default_flow;
155
156 /* Physical addresses of various blocks of registers (from platform) */
157 phys_addr_t mpsc_base_p;
158 phys_addr_t sdma_base_p;
159 phys_addr_t brg_base_p;
160
161 /* Virtual addresses of various blocks of registers (from platform) */
162 void __iomem *mpsc_base;
163 void __iomem *sdma_base;
164 void __iomem *brg_base;
165
166 /* Descriptor ring and buffer allocations */
167 void *dma_region;
168 dma_addr_t dma_region_p;
169
170 dma_addr_t rxr; /* Rx descriptor ring */
171 dma_addr_t rxr_p; /* Phys addr of rxr */
172 u8 *rxb; /* Rx Ring I/O buf */
173 u8 *rxb_p; /* Phys addr of rxb */
174 u32 rxr_posn; /* First desc w/ Rx data */
175
176 dma_addr_t txr; /* Tx descriptor ring */
177 dma_addr_t txr_p; /* Phys addr of txr */
178 u8 *txb; /* Tx Ring I/O buf */
179 u8 *txb_p; /* Phys addr of txb */
180 int txr_head; /* Where new data goes */
181 int txr_tail; /* Where sent data comes off */
182 spinlock_t tx_lock; /* transmit lock */
183
184 /* Mirrored values of regs we can't read (if 'mirror_regs' set) */
185 u32 MPSC_MPCR_m;
186 u32 MPSC_CHR_1_m;
187 u32 MPSC_CHR_2_m;
188 u32 MPSC_CHR_10_m;
189 u32 BRG_BCR_m;
190 struct mpsc_shared_regs *shared_regs;
191};
192
193/* Hooks to platform-specific code */
194int mpsc_platform_register_driver(void);
195void mpsc_platform_unregister_driver(void);
196
197/* Hooks back in to mpsc common to be called by platform-specific code */
198struct mpsc_port_info *mpsc_device_probe(int index);
199struct mpsc_port_info *mpsc_device_remove(int index);
200
201/* Main MPSC Configuration Register Offsets */
202#define MPSC_MMCRL 0x0000
203#define MPSC_MMCRH 0x0004
204#define MPSC_MPCR 0x0008
205#define MPSC_CHR_1 0x000c
206#define MPSC_CHR_2 0x0010
207#define MPSC_CHR_3 0x0014
208#define MPSC_CHR_4 0x0018
209#define MPSC_CHR_5 0x001c
210#define MPSC_CHR_6 0x0020
211#define MPSC_CHR_7 0x0024
212#define MPSC_CHR_8 0x0028
213#define MPSC_CHR_9 0x002c
214#define MPSC_CHR_10 0x0030
215#define MPSC_CHR_11 0x0034
216
217#define MPSC_MPCR_FRZ (1 << 9)
218#define MPSC_MPCR_CL_5 0
219#define MPSC_MPCR_CL_6 1
220#define MPSC_MPCR_CL_7 2
221#define MPSC_MPCR_CL_8 3
222#define MPSC_MPCR_SBL_1 0
223#define MPSC_MPCR_SBL_2 1
224
225#define MPSC_CHR_2_TEV (1<<1)
226#define MPSC_CHR_2_TA (1<<7)
227#define MPSC_CHR_2_TTCS (1<<9)
228#define MPSC_CHR_2_REV (1<<17)
229#define MPSC_CHR_2_RA (1<<23)
230#define MPSC_CHR_2_CRD (1<<25)
231#define MPSC_CHR_2_EH (1<<31)
232#define MPSC_CHR_2_PAR_ODD 0
233#define MPSC_CHR_2_PAR_SPACE 1
234#define MPSC_CHR_2_PAR_EVEN 2
235#define MPSC_CHR_2_PAR_MARK 3
236
237/* MPSC Signal Routing */
238#define MPSC_MRR 0x0000
239#define MPSC_RCRR 0x0004
240#define MPSC_TCRR 0x0008
241
242/* Serial DMA Controller Interface Registers */
243#define SDMA_SDC 0x0000
244#define SDMA_SDCM 0x0008
245#define SDMA_RX_DESC 0x0800
246#define SDMA_RX_BUF_PTR 0x0808
247#define SDMA_SCRDP 0x0810
248#define SDMA_TX_DESC 0x0c00
249#define SDMA_SCTDP 0x0c10
250#define SDMA_SFTDP 0x0c14
251
252#define SDMA_DESC_CMDSTAT_PE (1<<0)
253#define SDMA_DESC_CMDSTAT_CDL (1<<1)
254#define SDMA_DESC_CMDSTAT_FR (1<<3)
255#define SDMA_DESC_CMDSTAT_OR (1<<6)
256#define SDMA_DESC_CMDSTAT_BR (1<<9)
257#define SDMA_DESC_CMDSTAT_MI (1<<10)
258#define SDMA_DESC_CMDSTAT_A (1<<11)
259#define SDMA_DESC_CMDSTAT_AM (1<<12)
260#define SDMA_DESC_CMDSTAT_CT (1<<13)
261#define SDMA_DESC_CMDSTAT_C (1<<14)
262#define SDMA_DESC_CMDSTAT_ES (1<<15)
263#define SDMA_DESC_CMDSTAT_L (1<<16)
264#define SDMA_DESC_CMDSTAT_F (1<<17)
265#define SDMA_DESC_CMDSTAT_P (1<<18)
266#define SDMA_DESC_CMDSTAT_EI (1<<23)
267#define SDMA_DESC_CMDSTAT_O (1<<31)
268
269#define SDMA_DESC_DFLT (SDMA_DESC_CMDSTAT_O \
270 | SDMA_DESC_CMDSTAT_EI)
271
272#define SDMA_SDC_RFT (1<<0)
273#define SDMA_SDC_SFM (1<<1)
274#define SDMA_SDC_BLMR (1<<6)
275#define SDMA_SDC_BLMT (1<<7)
276#define SDMA_SDC_POVR (1<<8)
277#define SDMA_SDC_RIFB (1<<9)
278
279#define SDMA_SDCM_ERD (1<<7)
280#define SDMA_SDCM_AR (1<<15)
281#define SDMA_SDCM_STD (1<<16)
282#define SDMA_SDCM_TXD (1<<23)
283#define SDMA_SDCM_AT (1<<31)
284
285#define SDMA_0_CAUSE_RXBUF (1<<0)
286#define SDMA_0_CAUSE_RXERR (1<<1)
287#define SDMA_0_CAUSE_TXBUF (1<<2)
288#define SDMA_0_CAUSE_TXEND (1<<3)
289#define SDMA_1_CAUSE_RXBUF (1<<8)
290#define SDMA_1_CAUSE_RXERR (1<<9)
291#define SDMA_1_CAUSE_TXBUF (1<<10)
292#define SDMA_1_CAUSE_TXEND (1<<11)
293
294#define SDMA_CAUSE_RX_MASK (SDMA_0_CAUSE_RXBUF | SDMA_0_CAUSE_RXERR \
295 | SDMA_1_CAUSE_RXBUF | SDMA_1_CAUSE_RXERR)
296#define SDMA_CAUSE_TX_MASK (SDMA_0_CAUSE_TXBUF | SDMA_0_CAUSE_TXEND \
297 | SDMA_1_CAUSE_TXBUF | SDMA_1_CAUSE_TXEND)
298
299/* SDMA Interrupt registers */
300#define SDMA_INTR_CAUSE 0x0000
301#define SDMA_INTR_MASK 0x0080
302
303/* Baud Rate Generator Interface Registers */
304#define BRG_BCR 0x0000
305#define BRG_BTR 0x0004
306
307/*
308 * Define how this driver is known to the outside (we've been assigned a
309 * range on the "Low-density serial ports" major).
310 */
311#define MPSC_MAJOR 204
312#define MPSC_MINOR_START 44
313#define MPSC_DRIVER_NAME "MPSC"
314#define MPSC_DEV_NAME "ttyMM"
315#define MPSC_VERSION "1.00"
316
317static struct mpsc_port_info mpsc_ports[MPSC_NUM_CTLRS];
318static struct mpsc_shared_regs mpsc_shared_regs;
319static struct uart_driver mpsc_reg;
320
321static void mpsc_start_rx(struct mpsc_port_info *pi);
322static void mpsc_free_ring_mem(struct mpsc_port_info *pi);
323static void mpsc_release_port(struct uart_port *port);
324/*
325 ******************************************************************************
326 *
327 * Baud Rate Generator Routines (BRG)
328 *
329 ******************************************************************************
330 */
331static void mpsc_brg_init(struct mpsc_port_info *pi, u32 clk_src)
332{
333 u32 v;
334
335 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
336 v = (v & ~(0xf << 18)) | ((clk_src & 0xf) << 18);
337
338 if (pi->brg_can_tune)
339 v &= ~(1 << 25);
340
341 if (pi->mirror_regs)
342 pi->BRG_BCR_m = v;
343 writel(v, pi->brg_base + BRG_BCR);
344
345 writel(readl(pi->brg_base + BRG_BTR) & 0xffff0000,
346 pi->brg_base + BRG_BTR);
347}
348
349static void mpsc_brg_enable(struct mpsc_port_info *pi)
350{
351 u32 v;
352
353 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
354 v |= (1 << 16);
355
356 if (pi->mirror_regs)
357 pi->BRG_BCR_m = v;
358 writel(v, pi->brg_base + BRG_BCR);
359}
360
361static void mpsc_brg_disable(struct mpsc_port_info *pi)
362{
363 u32 v;
364
365 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
366 v &= ~(1 << 16);
367
368 if (pi->mirror_regs)
369 pi->BRG_BCR_m = v;
370 writel(v, pi->brg_base + BRG_BCR);
371}
372
373/*
374 * To set the baud, we adjust the CDV field in the BRG_BCR reg.
375 * From manual: Baud = clk / ((CDV+1)*2) ==> CDV = (clk / (baud*2)) - 1.
376 * However, the input clock is divided by 16 in the MPSC b/c of how
377 * 'MPSC_MMCRH' was set up so we have to divide the 'clk' used in our
378 * calculation by 16 to account for that. So the real calculation
379 * that accounts for the way the mpsc is set up is:
380 * CDV = (clk / (baud*2*16)) - 1 ==> CDV = (clk / (baud << 5)) - 1.
381 */
382static void mpsc_set_baudrate(struct mpsc_port_info *pi, u32 baud)
383{
384 u32 cdv = (pi->port.uartclk / (baud << 5)) - 1;
385 u32 v;
386
387 mpsc_brg_disable(pi);
388 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
389 v = (v & 0xffff0000) | (cdv & 0xffff);
390
391 if (pi->mirror_regs)
392 pi->BRG_BCR_m = v;
393 writel(v, pi->brg_base + BRG_BCR);
394 mpsc_brg_enable(pi);
395}
396
397/*
398 ******************************************************************************
399 *
400 * Serial DMA Routines (SDMA)
401 *
402 ******************************************************************************
403 */
404
405static void mpsc_sdma_burstsize(struct mpsc_port_info *pi, u32 burst_size)
406{
407 u32 v;
408
409 pr_debug("mpsc_sdma_burstsize[%d]: burst_size: %d\n",
410 pi->port.line, burst_size);
411
412 burst_size >>= 3; /* Divide by 8 b/c reg values are 8-byte chunks */
413
414 if (burst_size < 2)
415 v = 0x0; /* 1 64-bit word */
416 else if (burst_size < 4)
417 v = 0x1; /* 2 64-bit words */
418 else if (burst_size < 8)
419 v = 0x2; /* 4 64-bit words */
420 else
421 v = 0x3; /* 8 64-bit words */
422
423 writel((readl(pi->sdma_base + SDMA_SDC) & (0x3 << 12)) | (v << 12),
424 pi->sdma_base + SDMA_SDC);
425}
426
427static void mpsc_sdma_init(struct mpsc_port_info *pi, u32 burst_size)
428{
429 pr_debug("mpsc_sdma_init[%d]: burst_size: %d\n", pi->port.line,
430 burst_size);
431
432 writel((readl(pi->sdma_base + SDMA_SDC) & 0x3ff) | 0x03f,
433 pi->sdma_base + SDMA_SDC);
434 mpsc_sdma_burstsize(pi, burst_size);
435}
436
437static u32 mpsc_sdma_intr_mask(struct mpsc_port_info *pi, u32 mask)
438{
439 u32 old, v;
440
441 pr_debug("mpsc_sdma_intr_mask[%d]: mask: 0x%x\n", pi->port.line, mask);
442
443 old = v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m :
444 readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
445
446 mask &= 0xf;
447 if (pi->port.line)
448 mask <<= 8;
449 v &= ~mask;
450
451 if (pi->mirror_regs)
452 pi->shared_regs->SDMA_INTR_MASK_m = v;
453 writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
454
455 if (pi->port.line)
456 old >>= 8;
457 return old & 0xf;
458}
459
460static void mpsc_sdma_intr_unmask(struct mpsc_port_info *pi, u32 mask)
461{
462 u32 v;
463
464 pr_debug("mpsc_sdma_intr_unmask[%d]: mask: 0x%x\n", pi->port.line,mask);
465
466 v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m
467 : readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
468
469 mask &= 0xf;
470 if (pi->port.line)
471 mask <<= 8;
472 v |= mask;
473
474 if (pi->mirror_regs)
475 pi->shared_regs->SDMA_INTR_MASK_m = v;
476 writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
477}
478
479static void mpsc_sdma_intr_ack(struct mpsc_port_info *pi)
480{
481 pr_debug("mpsc_sdma_intr_ack[%d]: Acknowledging IRQ\n", pi->port.line);
482
483 if (pi->mirror_regs)
484 pi->shared_regs->SDMA_INTR_CAUSE_m = 0;
485 writeb(0x00, pi->shared_regs->sdma_intr_base + SDMA_INTR_CAUSE
486 + pi->port.line);
487}
488
489static void mpsc_sdma_set_rx_ring(struct mpsc_port_info *pi,
490 struct mpsc_rx_desc *rxre_p)
491{
492 pr_debug("mpsc_sdma_set_rx_ring[%d]: rxre_p: 0x%x\n",
493 pi->port.line, (u32)rxre_p);
494
495 writel((u32)rxre_p, pi->sdma_base + SDMA_SCRDP);
496}
497
498static void mpsc_sdma_set_tx_ring(struct mpsc_port_info *pi,
499 struct mpsc_tx_desc *txre_p)
500{
501 writel((u32)txre_p, pi->sdma_base + SDMA_SFTDP);
502 writel((u32)txre_p, pi->sdma_base + SDMA_SCTDP);
503}
504
505static void mpsc_sdma_cmd(struct mpsc_port_info *pi, u32 val)
506{
507 u32 v;
508
509 v = readl(pi->sdma_base + SDMA_SDCM);
510 if (val)
511 v |= val;
512 else
513 v = 0;
514 wmb();
515 writel(v, pi->sdma_base + SDMA_SDCM);
516 wmb();
517}
518
519static uint mpsc_sdma_tx_active(struct mpsc_port_info *pi)
520{
521 return readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_TXD;
522}
523
524static void mpsc_sdma_start_tx(struct mpsc_port_info *pi)
525{
526 struct mpsc_tx_desc *txre, *txre_p;
527
528 /* If tx isn't running & there's a desc ready to go, start it */
529 if (!mpsc_sdma_tx_active(pi)) {
530 txre = (struct mpsc_tx_desc *)(pi->txr
531 + (pi->txr_tail * MPSC_TXRE_SIZE));
532 dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE,
533 DMA_FROM_DEVICE);
534#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
535 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
536 invalidate_dcache_range((ulong)txre,
537 (ulong)txre + MPSC_TXRE_SIZE);
538#endif
539
540 if (be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O) {
541 txre_p = (struct mpsc_tx_desc *)
542 (pi->txr_p + (pi->txr_tail * MPSC_TXRE_SIZE));
543
544 mpsc_sdma_set_tx_ring(pi, txre_p);
545 mpsc_sdma_cmd(pi, SDMA_SDCM_STD | SDMA_SDCM_TXD);
546 }
547 }
548}
549
550static void mpsc_sdma_stop(struct mpsc_port_info *pi)
551{
552 pr_debug("mpsc_sdma_stop[%d]: Stopping SDMA\n", pi->port.line);
553
554 /* Abort any SDMA transfers */
555 mpsc_sdma_cmd(pi, 0);
556 mpsc_sdma_cmd(pi, SDMA_SDCM_AR | SDMA_SDCM_AT);
557
558 /* Clear the SDMA current and first TX and RX pointers */
559 mpsc_sdma_set_tx_ring(pi, NULL);
560 mpsc_sdma_set_rx_ring(pi, NULL);
561
562 /* Disable interrupts */
563 mpsc_sdma_intr_mask(pi, 0xf);
564 mpsc_sdma_intr_ack(pi);
565}
566
567/*
568 ******************************************************************************
569 *
570 * Multi-Protocol Serial Controller Routines (MPSC)
571 *
572 ******************************************************************************
573 */
574
575static void mpsc_hw_init(struct mpsc_port_info *pi)
576{
577 u32 v;
578
579 pr_debug("mpsc_hw_init[%d]: Initializing hardware\n", pi->port.line);
580
581 /* Set up clock routing */
582 if (pi->mirror_regs) {
583 v = pi->shared_regs->MPSC_MRR_m;
584 v &= ~0x1c7;
585 pi->shared_regs->MPSC_MRR_m = v;
586 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR);
587
588 v = pi->shared_regs->MPSC_RCRR_m;
589 v = (v & ~0xf0f) | 0x100;
590 pi->shared_regs->MPSC_RCRR_m = v;
591 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
592
593 v = pi->shared_regs->MPSC_TCRR_m;
594 v = (v & ~0xf0f) | 0x100;
595 pi->shared_regs->MPSC_TCRR_m = v;
596 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
597 } else {
598 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_MRR);
599 v &= ~0x1c7;
600 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR);
601
602 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
603 v = (v & ~0xf0f) | 0x100;
604 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
605
606 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
607 v = (v & ~0xf0f) | 0x100;
608 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
609 }
610
611 /* Put MPSC in UART mode & enabel Tx/Rx egines */
612 writel(0x000004c4, pi->mpsc_base + MPSC_MMCRL);
613
614 /* No preamble, 16x divider, low-latency, */
615 writel(0x04400400, pi->mpsc_base + MPSC_MMCRH);
616 mpsc_set_baudrate(pi, pi->default_baud);
617
618 if (pi->mirror_regs) {
619 pi->MPSC_CHR_1_m = 0;
620 pi->MPSC_CHR_2_m = 0;
621 }
622 writel(0, pi->mpsc_base + MPSC_CHR_1);
623 writel(0, pi->mpsc_base + MPSC_CHR_2);
624 writel(pi->mpsc_max_idle, pi->mpsc_base + MPSC_CHR_3);
625 writel(0, pi->mpsc_base + MPSC_CHR_4);
626 writel(0, pi->mpsc_base + MPSC_CHR_5);
627 writel(0, pi->mpsc_base + MPSC_CHR_6);
628 writel(0, pi->mpsc_base + MPSC_CHR_7);
629 writel(0, pi->mpsc_base + MPSC_CHR_8);
630 writel(0, pi->mpsc_base + MPSC_CHR_9);
631 writel(0, pi->mpsc_base + MPSC_CHR_10);
632}
633
634static void mpsc_enter_hunt(struct mpsc_port_info *pi)
635{
636 pr_debug("mpsc_enter_hunt[%d]: Hunting...\n", pi->port.line);
637
638 if (pi->mirror_regs) {
639 writel(pi->MPSC_CHR_2_m | MPSC_CHR_2_EH,
640 pi->mpsc_base + MPSC_CHR_2);
641 /* Erratum prevents reading CHR_2 so just delay for a while */
642 udelay(100);
643 } else {
644 writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_EH,
645 pi->mpsc_base + MPSC_CHR_2);
646
647 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_EH)
648 udelay(10);
649 }
650}
651
652static void mpsc_freeze(struct mpsc_port_info *pi)
653{
654 u32 v;
655
656 pr_debug("mpsc_freeze[%d]: Freezing\n", pi->port.line);
657
658 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
659 readl(pi->mpsc_base + MPSC_MPCR);
660 v |= MPSC_MPCR_FRZ;
661
662 if (pi->mirror_regs)
663 pi->MPSC_MPCR_m = v;
664 writel(v, pi->mpsc_base + MPSC_MPCR);
665}
666
667static void mpsc_unfreeze(struct mpsc_port_info *pi)
668{
669 u32 v;
670
671 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
672 readl(pi->mpsc_base + MPSC_MPCR);
673 v &= ~MPSC_MPCR_FRZ;
674
675 if (pi->mirror_regs)
676 pi->MPSC_MPCR_m = v;
677 writel(v, pi->mpsc_base + MPSC_MPCR);
678
679 pr_debug("mpsc_unfreeze[%d]: Unfrozen\n", pi->port.line);
680}
681
682static void mpsc_set_char_length(struct mpsc_port_info *pi, u32 len)
683{
684 u32 v;
685
686 pr_debug("mpsc_set_char_length[%d]: char len: %d\n", pi->port.line,len);
687
688 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
689 readl(pi->mpsc_base + MPSC_MPCR);
690 v = (v & ~(0x3 << 12)) | ((len & 0x3) << 12);
691
692 if (pi->mirror_regs)
693 pi->MPSC_MPCR_m = v;
694 writel(v, pi->mpsc_base + MPSC_MPCR);
695}
696
697static void mpsc_set_stop_bit_length(struct mpsc_port_info *pi, u32 len)
698{
699 u32 v;
700
701 pr_debug("mpsc_set_stop_bit_length[%d]: stop bits: %d\n",
702 pi->port.line, len);
703
704 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
705 readl(pi->mpsc_base + MPSC_MPCR);
706
707 v = (v & ~(1 << 14)) | ((len & 0x1) << 14);
708
709 if (pi->mirror_regs)
710 pi->MPSC_MPCR_m = v;
711 writel(v, pi->mpsc_base + MPSC_MPCR);
712}
713
714static void mpsc_set_parity(struct mpsc_port_info *pi, u32 p)
715{
716 u32 v;
717
718 pr_debug("mpsc_set_parity[%d]: parity bits: 0x%x\n", pi->port.line, p);
719
720 v = (pi->mirror_regs) ? pi->MPSC_CHR_2_m :
721 readl(pi->mpsc_base + MPSC_CHR_2);
722
723 p &= 0x3;
724 v = (v & ~0xc000c) | (p << 18) | (p << 2);
725
726 if (pi->mirror_regs)
727 pi->MPSC_CHR_2_m = v;
728 writel(v, pi->mpsc_base + MPSC_CHR_2);
729}
730
731/*
732 ******************************************************************************
733 *
734 * Driver Init Routines
735 *
736 ******************************************************************************
737 */
738
739static void mpsc_init_hw(struct mpsc_port_info *pi)
740{
741 pr_debug("mpsc_init_hw[%d]: Initializing\n", pi->port.line);
742
743 mpsc_brg_init(pi, pi->brg_clk_src);
744 mpsc_brg_enable(pi);
745 mpsc_sdma_init(pi, dma_get_cache_alignment()); /* burst a cacheline */
746 mpsc_sdma_stop(pi);
747 mpsc_hw_init(pi);
748}
749
750static int mpsc_alloc_ring_mem(struct mpsc_port_info *pi)
751{
752 int rc = 0;
753
754 pr_debug("mpsc_alloc_ring_mem[%d]: Allocating ring mem\n",
755 pi->port.line);
756
757 if (!pi->dma_region) {
758 if (!dma_supported(pi->port.dev, 0xffffffff)) {
759 printk(KERN_ERR "MPSC: Inadequate DMA support\n");
760 rc = -ENXIO;
761 } else if ((pi->dma_region = dma_alloc_noncoherent(pi->port.dev,
762 MPSC_DMA_ALLOC_SIZE,
763 &pi->dma_region_p, GFP_KERNEL))
764 == NULL) {
765 printk(KERN_ERR "MPSC: Can't alloc Desc region\n");
766 rc = -ENOMEM;
767 }
768 }
769
770 return rc;
771}
772
773static void mpsc_free_ring_mem(struct mpsc_port_info *pi)
774{
775 pr_debug("mpsc_free_ring_mem[%d]: Freeing ring mem\n", pi->port.line);
776
777 if (pi->dma_region) {
778 dma_free_noncoherent(pi->port.dev, MPSC_DMA_ALLOC_SIZE,
779 pi->dma_region, pi->dma_region_p);
780 pi->dma_region = NULL;
781 pi->dma_region_p = (dma_addr_t)NULL;
782 }
783}
784
785static void mpsc_init_rings(struct mpsc_port_info *pi)
786{
787 struct mpsc_rx_desc *rxre;
788 struct mpsc_tx_desc *txre;
789 dma_addr_t dp, dp_p;
790 u8 *bp, *bp_p;
791 int i;
792
793 pr_debug("mpsc_init_rings[%d]: Initializing rings\n", pi->port.line);
794
795 BUG_ON(pi->dma_region == NULL);
796
797 memset(pi->dma_region, 0, MPSC_DMA_ALLOC_SIZE);
798
799 /*
800 * Descriptors & buffers are multiples of cacheline size and must be
801 * cacheline aligned.
802 */
803 dp = ALIGN((u32)pi->dma_region, dma_get_cache_alignment());
804 dp_p = ALIGN((u32)pi->dma_region_p, dma_get_cache_alignment());
805
806 /*
807 * Partition dma region into rx ring descriptor, rx buffers,
808 * tx ring descriptors, and tx buffers.
809 */
810 pi->rxr = dp;
811 pi->rxr_p = dp_p;
812 dp += MPSC_RXR_SIZE;
813 dp_p += MPSC_RXR_SIZE;
814
815 pi->rxb = (u8 *)dp;
816 pi->rxb_p = (u8 *)dp_p;
817 dp += MPSC_RXB_SIZE;
818 dp_p += MPSC_RXB_SIZE;
819
820 pi->rxr_posn = 0;
821
822 pi->txr = dp;
823 pi->txr_p = dp_p;
824 dp += MPSC_TXR_SIZE;
825 dp_p += MPSC_TXR_SIZE;
826
827 pi->txb = (u8 *)dp;
828 pi->txb_p = (u8 *)dp_p;
829
830 pi->txr_head = 0;
831 pi->txr_tail = 0;
832
833 /* Init rx ring descriptors */
834 dp = pi->rxr;
835 dp_p = pi->rxr_p;
836 bp = pi->rxb;
837 bp_p = pi->rxb_p;
838
839 for (i = 0; i < MPSC_RXR_ENTRIES; i++) {
840 rxre = (struct mpsc_rx_desc *)dp;
841
842 rxre->bufsize = cpu_to_be16(MPSC_RXBE_SIZE);
843 rxre->bytecnt = cpu_to_be16(0);
844 rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O
845 | SDMA_DESC_CMDSTAT_EI | SDMA_DESC_CMDSTAT_F
846 | SDMA_DESC_CMDSTAT_L);
847 rxre->link = cpu_to_be32(dp_p + MPSC_RXRE_SIZE);
848 rxre->buf_ptr = cpu_to_be32(bp_p);
849
850 dp += MPSC_RXRE_SIZE;
851 dp_p += MPSC_RXRE_SIZE;
852 bp += MPSC_RXBE_SIZE;
853 bp_p += MPSC_RXBE_SIZE;
854 }
855 rxre->link = cpu_to_be32(pi->rxr_p); /* Wrap last back to first */
856
857 /* Init tx ring descriptors */
858 dp = pi->txr;
859 dp_p = pi->txr_p;
860 bp = pi->txb;
861 bp_p = pi->txb_p;
862
863 for (i = 0; i < MPSC_TXR_ENTRIES; i++) {
864 txre = (struct mpsc_tx_desc *)dp;
865
866 txre->link = cpu_to_be32(dp_p + MPSC_TXRE_SIZE);
867 txre->buf_ptr = cpu_to_be32(bp_p);
868
869 dp += MPSC_TXRE_SIZE;
870 dp_p += MPSC_TXRE_SIZE;
871 bp += MPSC_TXBE_SIZE;
872 bp_p += MPSC_TXBE_SIZE;
873 }
874 txre->link = cpu_to_be32(pi->txr_p); /* Wrap last back to first */
875
876 dma_cache_sync(pi->port.dev, (void *)pi->dma_region,
877 MPSC_DMA_ALLOC_SIZE, DMA_BIDIRECTIONAL);
878#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
879 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
880 flush_dcache_range((ulong)pi->dma_region,
881 (ulong)pi->dma_region
882 + MPSC_DMA_ALLOC_SIZE);
883#endif
884
885 return;
886}
887
888static void mpsc_uninit_rings(struct mpsc_port_info *pi)
889{
890 pr_debug("mpsc_uninit_rings[%d]: Uninitializing rings\n",pi->port.line);
891
892 BUG_ON(pi->dma_region == NULL);
893
894 pi->rxr = 0;
895 pi->rxr_p = 0;
896 pi->rxb = NULL;
897 pi->rxb_p = NULL;
898 pi->rxr_posn = 0;
899
900 pi->txr = 0;
901 pi->txr_p = 0;
902 pi->txb = NULL;
903 pi->txb_p = NULL;
904 pi->txr_head = 0;
905 pi->txr_tail = 0;
906}
907
908static int mpsc_make_ready(struct mpsc_port_info *pi)
909{
910 int rc;
911
912 pr_debug("mpsc_make_ready[%d]: Making cltr ready\n", pi->port.line);
913
914 if (!pi->ready) {
915 mpsc_init_hw(pi);
916 if ((rc = mpsc_alloc_ring_mem(pi)))
917 return rc;
918 mpsc_init_rings(pi);
919 pi->ready = 1;
920 }
921
922 return 0;
923}
924
925#ifdef CONFIG_CONSOLE_POLL
926static int serial_polled;
927#endif
928
929/*
930 ******************************************************************************
931 *
932 * Interrupt Handling Routines
933 *
934 ******************************************************************************
935 */
936
937static int mpsc_rx_intr(struct mpsc_port_info *pi)
938{
939 struct mpsc_rx_desc *rxre;
940 struct tty_struct *tty = pi->port.state->port.tty;
941 u32 cmdstat, bytes_in, i;
942 int rc = 0;
943 u8 *bp;
944 char flag = TTY_NORMAL;
945
946 pr_debug("mpsc_rx_intr[%d]: Handling Rx intr\n", pi->port.line);
947
948 rxre = (struct mpsc_rx_desc *)(pi->rxr + (pi->rxr_posn*MPSC_RXRE_SIZE));
949
950 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE,
951 DMA_FROM_DEVICE);
952#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
953 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
954 invalidate_dcache_range((ulong)rxre,
955 (ulong)rxre + MPSC_RXRE_SIZE);
956#endif
957
958 /*
959 * Loop through Rx descriptors handling ones that have been completed.
960 */
961 while (!((cmdstat = be32_to_cpu(rxre->cmdstat))
962 & SDMA_DESC_CMDSTAT_O)) {
963 bytes_in = be16_to_cpu(rxre->bytecnt);
964#ifdef CONFIG_CONSOLE_POLL
965 if (unlikely(serial_polled)) {
966 serial_polled = 0;
967 return 0;
968 }
969#endif
970 /* Following use of tty struct directly is deprecated */
971 if (unlikely(tty_buffer_request_room(tty, bytes_in)
972 < bytes_in)) {
973 if (tty->low_latency)
974 tty_flip_buffer_push(tty);
975 /*
976 * If this failed then we will throw away the bytes
977 * but must do so to clear interrupts.
978 */
979 }
980
981 bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE);
982 dma_cache_sync(pi->port.dev, (void *)bp, MPSC_RXBE_SIZE,
983 DMA_FROM_DEVICE);
984#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
985 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
986 invalidate_dcache_range((ulong)bp,
987 (ulong)bp + MPSC_RXBE_SIZE);
988#endif
989
990 /*
991 * Other than for parity error, the manual provides little
992 * info on what data will be in a frame flagged by any of
993 * these errors. For parity error, it is the last byte in
994 * the buffer that had the error. As for the rest, I guess
995 * we'll assume there is no data in the buffer.
996 * If there is...it gets lost.
997 */
998 if (unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR
999 | SDMA_DESC_CMDSTAT_FR
1000 | SDMA_DESC_CMDSTAT_OR))) {
1001
1002 pi->port.icount.rx++;
1003
1004 if (cmdstat & SDMA_DESC_CMDSTAT_BR) { /* Break */
1005 pi->port.icount.brk++;
1006
1007 if (uart_handle_break(&pi->port))
1008 goto next_frame;
1009 } else if (cmdstat & SDMA_DESC_CMDSTAT_FR) {
1010 pi->port.icount.frame++;
1011 } else if (cmdstat & SDMA_DESC_CMDSTAT_OR) {
1012 pi->port.icount.overrun++;
1013 }
1014
1015 cmdstat &= pi->port.read_status_mask;
1016
1017 if (cmdstat & SDMA_DESC_CMDSTAT_BR)
1018 flag = TTY_BREAK;
1019 else if (cmdstat & SDMA_DESC_CMDSTAT_FR)
1020 flag = TTY_FRAME;
1021 else if (cmdstat & SDMA_DESC_CMDSTAT_OR)
1022 flag = TTY_OVERRUN;
1023 else if (cmdstat & SDMA_DESC_CMDSTAT_PE)
1024 flag = TTY_PARITY;
1025 }
1026
1027 if (uart_handle_sysrq_char(&pi->port, *bp)) {
1028 bp++;
1029 bytes_in--;
1030#ifdef CONFIG_CONSOLE_POLL
1031 if (unlikely(serial_polled)) {
1032 serial_polled = 0;
1033 return 0;
1034 }
1035#endif
1036 goto next_frame;
1037 }
1038
1039 if ((unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR
1040 | SDMA_DESC_CMDSTAT_FR
1041 | SDMA_DESC_CMDSTAT_OR)))
1042 && !(cmdstat & pi->port.ignore_status_mask)) {
1043 tty_insert_flip_char(tty, *bp, flag);
1044 } else {
1045 for (i=0; i<bytes_in; i++)
1046 tty_insert_flip_char(tty, *bp++, TTY_NORMAL);
1047
1048 pi->port.icount.rx += bytes_in;
1049 }
1050
1051next_frame:
1052 rxre->bytecnt = cpu_to_be16(0);
1053 wmb();
1054 rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O
1055 | SDMA_DESC_CMDSTAT_EI | SDMA_DESC_CMDSTAT_F
1056 | SDMA_DESC_CMDSTAT_L);
1057 wmb();
1058 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE,
1059 DMA_BIDIRECTIONAL);
1060#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1061 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1062 flush_dcache_range((ulong)rxre,
1063 (ulong)rxre + MPSC_RXRE_SIZE);
1064#endif
1065
1066 /* Advance to next descriptor */
1067 pi->rxr_posn = (pi->rxr_posn + 1) & (MPSC_RXR_ENTRIES - 1);
1068 rxre = (struct mpsc_rx_desc *)
1069 (pi->rxr + (pi->rxr_posn * MPSC_RXRE_SIZE));
1070 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE,
1071 DMA_FROM_DEVICE);
1072#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1073 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1074 invalidate_dcache_range((ulong)rxre,
1075 (ulong)rxre + MPSC_RXRE_SIZE);
1076#endif
1077 rc = 1;
1078 }
1079
1080 /* Restart rx engine, if its stopped */
1081 if ((readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_ERD) == 0)
1082 mpsc_start_rx(pi);
1083
1084 tty_flip_buffer_push(tty);
1085 return rc;
1086}
1087
1088static void mpsc_setup_tx_desc(struct mpsc_port_info *pi, u32 count, u32 intr)
1089{
1090 struct mpsc_tx_desc *txre;
1091
1092 txre = (struct mpsc_tx_desc *)(pi->txr
1093 + (pi->txr_head * MPSC_TXRE_SIZE));
1094
1095 txre->bytecnt = cpu_to_be16(count);
1096 txre->shadow = txre->bytecnt;
1097 wmb(); /* ensure cmdstat is last field updated */
1098 txre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O | SDMA_DESC_CMDSTAT_F
1099 | SDMA_DESC_CMDSTAT_L
1100 | ((intr) ? SDMA_DESC_CMDSTAT_EI : 0));
1101 wmb();
1102 dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE,
1103 DMA_BIDIRECTIONAL);
1104#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1105 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1106 flush_dcache_range((ulong)txre,
1107 (ulong)txre + MPSC_TXRE_SIZE);
1108#endif
1109}
1110
1111static void mpsc_copy_tx_data(struct mpsc_port_info *pi)
1112{
1113 struct circ_buf *xmit = &pi->port.state->xmit;
1114 u8 *bp;
1115 u32 i;
1116
1117 /* Make sure the desc ring isn't full */
1118 while (CIRC_CNT(pi->txr_head, pi->txr_tail, MPSC_TXR_ENTRIES)
1119 < (MPSC_TXR_ENTRIES - 1)) {
1120 if (pi->port.x_char) {
1121 /*
1122 * Ideally, we should use the TCS field in
1123 * CHR_1 to put the x_char out immediately but
1124 * errata prevents us from being able to read
1125 * CHR_2 to know that its safe to write to
1126 * CHR_1. Instead, just put it in-band with
1127 * all the other Tx data.
1128 */
1129 bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
1130 *bp = pi->port.x_char;
1131 pi->port.x_char = 0;
1132 i = 1;
1133 } else if (!uart_circ_empty(xmit)
1134 && !uart_tx_stopped(&pi->port)) {
1135 i = min((u32)MPSC_TXBE_SIZE,
1136 (u32)uart_circ_chars_pending(xmit));
1137 i = min(i, (u32)CIRC_CNT_TO_END(xmit->head, xmit->tail,
1138 UART_XMIT_SIZE));
1139 bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
1140 memcpy(bp, &xmit->buf[xmit->tail], i);
1141 xmit->tail = (xmit->tail + i) & (UART_XMIT_SIZE - 1);
1142
1143 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1144 uart_write_wakeup(&pi->port);
1145 } else { /* All tx data copied into ring bufs */
1146 return;
1147 }
1148
1149 dma_cache_sync(pi->port.dev, (void *)bp, MPSC_TXBE_SIZE,
1150 DMA_BIDIRECTIONAL);
1151#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1152 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1153 flush_dcache_range((ulong)bp,
1154 (ulong)bp + MPSC_TXBE_SIZE);
1155#endif
1156 mpsc_setup_tx_desc(pi, i, 1);
1157
1158 /* Advance to next descriptor */
1159 pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1);
1160 }
1161}
1162
1163static int mpsc_tx_intr(struct mpsc_port_info *pi)
1164{
1165 struct mpsc_tx_desc *txre;
1166 int rc = 0;
1167 unsigned long iflags;
1168
1169 spin_lock_irqsave(&pi->tx_lock, iflags);
1170
1171 if (!mpsc_sdma_tx_active(pi)) {
1172 txre = (struct mpsc_tx_desc *)(pi->txr
1173 + (pi->txr_tail * MPSC_TXRE_SIZE));
1174
1175 dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE,
1176 DMA_FROM_DEVICE);
1177#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1178 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1179 invalidate_dcache_range((ulong)txre,
1180 (ulong)txre + MPSC_TXRE_SIZE);
1181#endif
1182
1183 while (!(be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O)) {
1184 rc = 1;
1185 pi->port.icount.tx += be16_to_cpu(txre->bytecnt);
1186 pi->txr_tail = (pi->txr_tail+1) & (MPSC_TXR_ENTRIES-1);
1187
1188 /* If no more data to tx, fall out of loop */
1189 if (pi->txr_head == pi->txr_tail)
1190 break;
1191
1192 txre = (struct mpsc_tx_desc *)(pi->txr
1193 + (pi->txr_tail * MPSC_TXRE_SIZE));
1194 dma_cache_sync(pi->port.dev, (void *)txre,
1195 MPSC_TXRE_SIZE, DMA_FROM_DEVICE);
1196#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1197 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1198 invalidate_dcache_range((ulong)txre,
1199 (ulong)txre + MPSC_TXRE_SIZE);
1200#endif
1201 }
1202
1203 mpsc_copy_tx_data(pi);
1204 mpsc_sdma_start_tx(pi); /* start next desc if ready */
1205 }
1206
1207 spin_unlock_irqrestore(&pi->tx_lock, iflags);
1208 return rc;
1209}
1210
1211/*
1212 * This is the driver's interrupt handler. To avoid a race, we first clear
1213 * the interrupt, then handle any completed Rx/Tx descriptors. When done
1214 * handling those descriptors, we restart the Rx/Tx engines if they're stopped.
1215 */
1216static irqreturn_t mpsc_sdma_intr(int irq, void *dev_id)
1217{
1218 struct mpsc_port_info *pi = dev_id;
1219 ulong iflags;
1220 int rc = IRQ_NONE;
1221
1222 pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Received\n",pi->port.line);
1223
1224 spin_lock_irqsave(&pi->port.lock, iflags);
1225 mpsc_sdma_intr_ack(pi);
1226 if (mpsc_rx_intr(pi))
1227 rc = IRQ_HANDLED;
1228 if (mpsc_tx_intr(pi))
1229 rc = IRQ_HANDLED;
1230 spin_unlock_irqrestore(&pi->port.lock, iflags);
1231
1232 pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Handled\n", pi->port.line);
1233 return rc;
1234}
1235
1236/*
1237 ******************************************************************************
1238 *
1239 * serial_core.c Interface routines
1240 *
1241 ******************************************************************************
1242 */
1243static uint mpsc_tx_empty(struct uart_port *port)
1244{
1245 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1246 ulong iflags;
1247 uint rc;
1248
1249 spin_lock_irqsave(&pi->port.lock, iflags);
1250 rc = mpsc_sdma_tx_active(pi) ? 0 : TIOCSER_TEMT;
1251 spin_unlock_irqrestore(&pi->port.lock, iflags);
1252
1253 return rc;
1254}
1255
1256static void mpsc_set_mctrl(struct uart_port *port, uint mctrl)
1257{
1258 /* Have no way to set modem control lines AFAICT */
1259}
1260
1261static uint mpsc_get_mctrl(struct uart_port *port)
1262{
1263 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1264 u32 mflags, status;
1265
1266 status = (pi->mirror_regs) ? pi->MPSC_CHR_10_m
1267 : readl(pi->mpsc_base + MPSC_CHR_10);
1268
1269 mflags = 0;
1270 if (status & 0x1)
1271 mflags |= TIOCM_CTS;
1272 if (status & 0x2)
1273 mflags |= TIOCM_CAR;
1274
1275 return mflags | TIOCM_DSR; /* No way to tell if DSR asserted */
1276}
1277
1278static void mpsc_stop_tx(struct uart_port *port)
1279{
1280 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1281
1282 pr_debug("mpsc_stop_tx[%d]\n", port->line);
1283
1284 mpsc_freeze(pi);
1285}
1286
1287static void mpsc_start_tx(struct uart_port *port)
1288{
1289 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1290 unsigned long iflags;
1291
1292 spin_lock_irqsave(&pi->tx_lock, iflags);
1293
1294 mpsc_unfreeze(pi);
1295 mpsc_copy_tx_data(pi);
1296 mpsc_sdma_start_tx(pi);
1297
1298 spin_unlock_irqrestore(&pi->tx_lock, iflags);
1299
1300 pr_debug("mpsc_start_tx[%d]\n", port->line);
1301}
1302
1303static void mpsc_start_rx(struct mpsc_port_info *pi)
1304{
1305 pr_debug("mpsc_start_rx[%d]: Starting...\n", pi->port.line);
1306
1307 if (pi->rcv_data) {
1308 mpsc_enter_hunt(pi);
1309 mpsc_sdma_cmd(pi, SDMA_SDCM_ERD);
1310 }
1311}
1312
1313static void mpsc_stop_rx(struct uart_port *port)
1314{
1315 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1316
1317 pr_debug("mpsc_stop_rx[%d]: Stopping...\n", port->line);
1318
1319 if (pi->mirror_regs) {
1320 writel(pi->MPSC_CHR_2_m | MPSC_CHR_2_RA,
1321 pi->mpsc_base + MPSC_CHR_2);
1322 /* Erratum prevents reading CHR_2 so just delay for a while */
1323 udelay(100);
1324 } else {
1325 writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_RA,
1326 pi->mpsc_base + MPSC_CHR_2);
1327
1328 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_RA)
1329 udelay(10);
1330 }
1331
1332 mpsc_sdma_cmd(pi, SDMA_SDCM_AR);
1333}
1334
1335static void mpsc_enable_ms(struct uart_port *port)
1336{
1337}
1338
1339static void mpsc_break_ctl(struct uart_port *port, int ctl)
1340{
1341 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1342 ulong flags;
1343 u32 v;
1344
1345 v = ctl ? 0x00ff0000 : 0;
1346
1347 spin_lock_irqsave(&pi->port.lock, flags);
1348 if (pi->mirror_regs)
1349 pi->MPSC_CHR_1_m = v;
1350 writel(v, pi->mpsc_base + MPSC_CHR_1);
1351 spin_unlock_irqrestore(&pi->port.lock, flags);
1352}
1353
1354static int mpsc_startup(struct uart_port *port)
1355{
1356 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1357 u32 flag = 0;
1358 int rc;
1359
1360 pr_debug("mpsc_startup[%d]: Starting up MPSC, irq: %d\n",
1361 port->line, pi->port.irq);
1362
1363 if ((rc = mpsc_make_ready(pi)) == 0) {
1364 /* Setup IRQ handler */
1365 mpsc_sdma_intr_ack(pi);
1366
1367 /* If irq's are shared, need to set flag */
1368 if (mpsc_ports[0].port.irq == mpsc_ports[1].port.irq)
1369 flag = IRQF_SHARED;
1370
1371 if (request_irq(pi->port.irq, mpsc_sdma_intr, flag,
1372 "mpsc-sdma", pi))
1373 printk(KERN_ERR "MPSC: Can't get SDMA IRQ %d\n",
1374 pi->port.irq);
1375
1376 mpsc_sdma_intr_unmask(pi, 0xf);
1377 mpsc_sdma_set_rx_ring(pi, (struct mpsc_rx_desc *)(pi->rxr_p
1378 + (pi->rxr_posn * MPSC_RXRE_SIZE)));
1379 }
1380
1381 return rc;
1382}
1383
1384static void mpsc_shutdown(struct uart_port *port)
1385{
1386 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1387
1388 pr_debug("mpsc_shutdown[%d]: Shutting down MPSC\n", port->line);
1389
1390 mpsc_sdma_stop(pi);
1391 free_irq(pi->port.irq, pi);
1392}
1393
1394static void mpsc_set_termios(struct uart_port *port, struct ktermios *termios,
1395 struct ktermios *old)
1396{
1397 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1398 u32 baud;
1399 ulong flags;
1400 u32 chr_bits, stop_bits, par;
1401
1402 pi->c_iflag = termios->c_iflag;
1403 pi->c_cflag = termios->c_cflag;
1404
1405 switch (termios->c_cflag & CSIZE) {
1406 case CS5:
1407 chr_bits = MPSC_MPCR_CL_5;
1408 break;
1409 case CS6:
1410 chr_bits = MPSC_MPCR_CL_6;
1411 break;
1412 case CS7:
1413 chr_bits = MPSC_MPCR_CL_7;
1414 break;
1415 case CS8:
1416 default:
1417 chr_bits = MPSC_MPCR_CL_8;
1418 break;
1419 }
1420
1421 if (termios->c_cflag & CSTOPB)
1422 stop_bits = MPSC_MPCR_SBL_2;
1423 else
1424 stop_bits = MPSC_MPCR_SBL_1;
1425
1426 par = MPSC_CHR_2_PAR_EVEN;
1427 if (termios->c_cflag & PARENB)
1428 if (termios->c_cflag & PARODD)
1429 par = MPSC_CHR_2_PAR_ODD;
1430#ifdef CMSPAR
1431 if (termios->c_cflag & CMSPAR) {
1432 if (termios->c_cflag & PARODD)
1433 par = MPSC_CHR_2_PAR_MARK;
1434 else
1435 par = MPSC_CHR_2_PAR_SPACE;
1436 }
1437#endif
1438
1439 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk);
1440
1441 spin_lock_irqsave(&pi->port.lock, flags);
1442
1443 uart_update_timeout(port, termios->c_cflag, baud);
1444
1445 mpsc_set_char_length(pi, chr_bits);
1446 mpsc_set_stop_bit_length(pi, stop_bits);
1447 mpsc_set_parity(pi, par);
1448 mpsc_set_baudrate(pi, baud);
1449
1450 /* Characters/events to read */
1451 pi->port.read_status_mask = SDMA_DESC_CMDSTAT_OR;
1452
1453 if (termios->c_iflag & INPCK)
1454 pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_PE
1455 | SDMA_DESC_CMDSTAT_FR;
1456
1457 if (termios->c_iflag & (BRKINT | PARMRK))
1458 pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_BR;
1459
1460 /* Characters/events to ignore */
1461 pi->port.ignore_status_mask = 0;
1462
1463 if (termios->c_iflag & IGNPAR)
1464 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_PE
1465 | SDMA_DESC_CMDSTAT_FR;
1466
1467 if (termios->c_iflag & IGNBRK) {
1468 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_BR;
1469
1470 if (termios->c_iflag & IGNPAR)
1471 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_OR;
1472 }
1473
1474 if ((termios->c_cflag & CREAD)) {
1475 if (!pi->rcv_data) {
1476 pi->rcv_data = 1;
1477 mpsc_start_rx(pi);
1478 }
1479 } else if (pi->rcv_data) {
1480 mpsc_stop_rx(port);
1481 pi->rcv_data = 0;
1482 }
1483
1484 spin_unlock_irqrestore(&pi->port.lock, flags);
1485}
1486
1487static const char *mpsc_type(struct uart_port *port)
1488{
1489 pr_debug("mpsc_type[%d]: port type: %s\n", port->line,MPSC_DRIVER_NAME);
1490 return MPSC_DRIVER_NAME;
1491}
1492
1493static int mpsc_request_port(struct uart_port *port)
1494{
1495 /* Should make chip/platform specific call */
1496 return 0;
1497}
1498
1499static void mpsc_release_port(struct uart_port *port)
1500{
1501 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1502
1503 if (pi->ready) {
1504 mpsc_uninit_rings(pi);
1505 mpsc_free_ring_mem(pi);
1506 pi->ready = 0;
1507 }
1508}
1509
1510static void mpsc_config_port(struct uart_port *port, int flags)
1511{
1512}
1513
1514static int mpsc_verify_port(struct uart_port *port, struct serial_struct *ser)
1515{
1516 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1517 int rc = 0;
1518
1519 pr_debug("mpsc_verify_port[%d]: Verifying port data\n", pi->port.line);
1520
1521 if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPSC)
1522 rc = -EINVAL;
1523 else if (pi->port.irq != ser->irq)
1524 rc = -EINVAL;
1525 else if (ser->io_type != SERIAL_IO_MEM)
1526 rc = -EINVAL;
1527 else if (pi->port.uartclk / 16 != ser->baud_base) /* Not sure */
1528 rc = -EINVAL;
1529 else if ((void *)pi->port.mapbase != ser->iomem_base)
1530 rc = -EINVAL;
1531 else if (pi->port.iobase != ser->port)
1532 rc = -EINVAL;
1533 else if (ser->hub6 != 0)
1534 rc = -EINVAL;
1535
1536 return rc;
1537}
1538#ifdef CONFIG_CONSOLE_POLL
1539/* Serial polling routines for writing and reading from the uart while
1540 * in an interrupt or debug context.
1541 */
1542
1543static char poll_buf[2048];
1544static int poll_ptr;
1545static int poll_cnt;
1546static void mpsc_put_poll_char(struct uart_port *port,
1547 unsigned char c);
1548
1549static int mpsc_get_poll_char(struct uart_port *port)
1550{
1551 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1552 struct mpsc_rx_desc *rxre;
1553 u32 cmdstat, bytes_in, i;
1554 u8 *bp;
1555
1556 if (!serial_polled)
1557 serial_polled = 1;
1558
1559 pr_debug("mpsc_rx_intr[%d]: Handling Rx intr\n", pi->port.line);
1560
1561 if (poll_cnt) {
1562 poll_cnt--;
1563 return poll_buf[poll_ptr++];
1564 }
1565 poll_ptr = 0;
1566 poll_cnt = 0;
1567
1568 while (poll_cnt == 0) {
1569 rxre = (struct mpsc_rx_desc *)(pi->rxr +
1570 (pi->rxr_posn*MPSC_RXRE_SIZE));
1571 dma_cache_sync(pi->port.dev, (void *)rxre,
1572 MPSC_RXRE_SIZE, DMA_FROM_DEVICE);
1573#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1574 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1575 invalidate_dcache_range((ulong)rxre,
1576 (ulong)rxre + MPSC_RXRE_SIZE);
1577#endif
1578 /*
1579 * Loop through Rx descriptors handling ones that have
1580 * been completed.
1581 */
1582 while (poll_cnt == 0 &&
1583 !((cmdstat = be32_to_cpu(rxre->cmdstat)) &
1584 SDMA_DESC_CMDSTAT_O)){
1585 bytes_in = be16_to_cpu(rxre->bytecnt);
1586 bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE);
1587 dma_cache_sync(pi->port.dev, (void *) bp,
1588 MPSC_RXBE_SIZE, DMA_FROM_DEVICE);
1589#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1590 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1591 invalidate_dcache_range((ulong)bp,
1592 (ulong)bp + MPSC_RXBE_SIZE);
1593#endif
1594 if ((unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR |
1595 SDMA_DESC_CMDSTAT_FR | SDMA_DESC_CMDSTAT_OR))) &&
1596 !(cmdstat & pi->port.ignore_status_mask)) {
1597 poll_buf[poll_cnt] = *bp;
1598 poll_cnt++;
1599 } else {
1600 for (i = 0; i < bytes_in; i++) {
1601 poll_buf[poll_cnt] = *bp++;
1602 poll_cnt++;
1603 }
1604 pi->port.icount.rx += bytes_in;
1605 }
1606 rxre->bytecnt = cpu_to_be16(0);
1607 wmb();
1608 rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O |
1609 SDMA_DESC_CMDSTAT_EI |
1610 SDMA_DESC_CMDSTAT_F |
1611 SDMA_DESC_CMDSTAT_L);
1612 wmb();
1613 dma_cache_sync(pi->port.dev, (void *)rxre,
1614 MPSC_RXRE_SIZE, DMA_BIDIRECTIONAL);
1615#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1616 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1617 flush_dcache_range((ulong)rxre,
1618 (ulong)rxre + MPSC_RXRE_SIZE);
1619#endif
1620
1621 /* Advance to next descriptor */
1622 pi->rxr_posn = (pi->rxr_posn + 1) &
1623 (MPSC_RXR_ENTRIES - 1);
1624 rxre = (struct mpsc_rx_desc *)(pi->rxr +
1625 (pi->rxr_posn * MPSC_RXRE_SIZE));
1626 dma_cache_sync(pi->port.dev, (void *)rxre,
1627 MPSC_RXRE_SIZE, DMA_FROM_DEVICE);
1628#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1629 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1630 invalidate_dcache_range((ulong)rxre,
1631 (ulong)rxre + MPSC_RXRE_SIZE);
1632#endif
1633 }
1634
1635 /* Restart rx engine, if its stopped */
1636 if ((readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_ERD) == 0)
1637 mpsc_start_rx(pi);
1638 }
1639 if (poll_cnt) {
1640 poll_cnt--;
1641 return poll_buf[poll_ptr++];
1642 }
1643
1644 return 0;
1645}
1646
1647
1648static void mpsc_put_poll_char(struct uart_port *port,
1649 unsigned char c)
1650{
1651 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1652 u32 data;
1653
1654 data = readl(pi->mpsc_base + MPSC_MPCR);
1655 writeb(c, pi->mpsc_base + MPSC_CHR_1);
1656 mb();
1657 data = readl(pi->mpsc_base + MPSC_CHR_2);
1658 data |= MPSC_CHR_2_TTCS;
1659 writel(data, pi->mpsc_base + MPSC_CHR_2);
1660 mb();
1661
1662 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_TTCS);
1663}
1664#endif
1665
1666static struct uart_ops mpsc_pops = {
1667 .tx_empty = mpsc_tx_empty,
1668 .set_mctrl = mpsc_set_mctrl,
1669 .get_mctrl = mpsc_get_mctrl,
1670 .stop_tx = mpsc_stop_tx,
1671 .start_tx = mpsc_start_tx,
1672 .stop_rx = mpsc_stop_rx,
1673 .enable_ms = mpsc_enable_ms,
1674 .break_ctl = mpsc_break_ctl,
1675 .startup = mpsc_startup,
1676 .shutdown = mpsc_shutdown,
1677 .set_termios = mpsc_set_termios,
1678 .type = mpsc_type,
1679 .release_port = mpsc_release_port,
1680 .request_port = mpsc_request_port,
1681 .config_port = mpsc_config_port,
1682 .verify_port = mpsc_verify_port,
1683#ifdef CONFIG_CONSOLE_POLL
1684 .poll_get_char = mpsc_get_poll_char,
1685 .poll_put_char = mpsc_put_poll_char,
1686#endif
1687};
1688
1689/*
1690 ******************************************************************************
1691 *
1692 * Console Interface Routines
1693 *
1694 ******************************************************************************
1695 */
1696
1697#ifdef CONFIG_SERIAL_MPSC_CONSOLE
1698static void mpsc_console_write(struct console *co, const char *s, uint count)
1699{
1700 struct mpsc_port_info *pi = &mpsc_ports[co->index];
1701 u8 *bp, *dp, add_cr = 0;
1702 int i;
1703 unsigned long iflags;
1704
1705 spin_lock_irqsave(&pi->tx_lock, iflags);
1706
1707 while (pi->txr_head != pi->txr_tail) {
1708 while (mpsc_sdma_tx_active(pi))
1709 udelay(100);
1710 mpsc_sdma_intr_ack(pi);
1711 mpsc_tx_intr(pi);
1712 }
1713
1714 while (mpsc_sdma_tx_active(pi))
1715 udelay(100);
1716
1717 while (count > 0) {
1718 bp = dp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
1719
1720 for (i = 0; i < MPSC_TXBE_SIZE; i++) {
1721 if (count == 0)
1722 break;
1723
1724 if (add_cr) {
1725 *(dp++) = '\r';
1726 add_cr = 0;
1727 } else {
1728 *(dp++) = *s;
1729
1730 if (*(s++) == '\n') { /* add '\r' after '\n' */
1731 add_cr = 1;
1732 count++;
1733 }
1734 }
1735
1736 count--;
1737 }
1738
1739 dma_cache_sync(pi->port.dev, (void *)bp, MPSC_TXBE_SIZE,
1740 DMA_BIDIRECTIONAL);
1741#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1742 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1743 flush_dcache_range((ulong)bp,
1744 (ulong)bp + MPSC_TXBE_SIZE);
1745#endif
1746 mpsc_setup_tx_desc(pi, i, 0);
1747 pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1);
1748 mpsc_sdma_start_tx(pi);
1749
1750 while (mpsc_sdma_tx_active(pi))
1751 udelay(100);
1752
1753 pi->txr_tail = (pi->txr_tail + 1) & (MPSC_TXR_ENTRIES - 1);
1754 }
1755
1756 spin_unlock_irqrestore(&pi->tx_lock, iflags);
1757}
1758
1759static int __init mpsc_console_setup(struct console *co, char *options)
1760{
1761 struct mpsc_port_info *pi;
1762 int baud, bits, parity, flow;
1763
1764 pr_debug("mpsc_console_setup[%d]: options: %s\n", co->index, options);
1765
1766 if (co->index >= MPSC_NUM_CTLRS)
1767 co->index = 0;
1768
1769 pi = &mpsc_ports[co->index];
1770
1771 baud = pi->default_baud;
1772 bits = pi->default_bits;
1773 parity = pi->default_parity;
1774 flow = pi->default_flow;
1775
1776 if (!pi->port.ops)
1777 return -ENODEV;
1778
1779 spin_lock_init(&pi->port.lock); /* Temporary fix--copied from 8250.c */
1780
1781 if (options)
1782 uart_parse_options(options, &baud, &parity, &bits, &flow);
1783
1784 return uart_set_options(&pi->port, co, baud, parity, bits, flow);
1785}
1786
1787static struct console mpsc_console = {
1788 .name = MPSC_DEV_NAME,
1789 .write = mpsc_console_write,
1790 .device = uart_console_device,
1791 .setup = mpsc_console_setup,
1792 .flags = CON_PRINTBUFFER,
1793 .index = -1,
1794 .data = &mpsc_reg,
1795};
1796
1797static int __init mpsc_late_console_init(void)
1798{
1799 pr_debug("mpsc_late_console_init: Enter\n");
1800
1801 if (!(mpsc_console.flags & CON_ENABLED))
1802 register_console(&mpsc_console);
1803 return 0;
1804}
1805
1806late_initcall(mpsc_late_console_init);
1807
1808#define MPSC_CONSOLE &mpsc_console
1809#else
1810#define MPSC_CONSOLE NULL
1811#endif
1812/*
1813 ******************************************************************************
1814 *
1815 * Dummy Platform Driver to extract & map shared register regions
1816 *
1817 ******************************************************************************
1818 */
1819static void mpsc_resource_err(char *s)
1820{
1821 printk(KERN_WARNING "MPSC: Platform device resource error in %s\n", s);
1822}
1823
1824static int mpsc_shared_map_regs(struct platform_device *pd)
1825{
1826 struct resource *r;
1827
1828 if ((r = platform_get_resource(pd, IORESOURCE_MEM,
1829 MPSC_ROUTING_BASE_ORDER))
1830 && request_mem_region(r->start,
1831 MPSC_ROUTING_REG_BLOCK_SIZE,
1832 "mpsc_routing_regs")) {
1833 mpsc_shared_regs.mpsc_routing_base = ioremap(r->start,
1834 MPSC_ROUTING_REG_BLOCK_SIZE);
1835 mpsc_shared_regs.mpsc_routing_base_p = r->start;
1836 } else {
1837 mpsc_resource_err("MPSC routing base");
1838 return -ENOMEM;
1839 }
1840
1841 if ((r = platform_get_resource(pd, IORESOURCE_MEM,
1842 MPSC_SDMA_INTR_BASE_ORDER))
1843 && request_mem_region(r->start,
1844 MPSC_SDMA_INTR_REG_BLOCK_SIZE,
1845 "sdma_intr_regs")) {
1846 mpsc_shared_regs.sdma_intr_base = ioremap(r->start,
1847 MPSC_SDMA_INTR_REG_BLOCK_SIZE);
1848 mpsc_shared_regs.sdma_intr_base_p = r->start;
1849 } else {
1850 iounmap(mpsc_shared_regs.mpsc_routing_base);
1851 release_mem_region(mpsc_shared_regs.mpsc_routing_base_p,
1852 MPSC_ROUTING_REG_BLOCK_SIZE);
1853 mpsc_resource_err("SDMA intr base");
1854 return -ENOMEM;
1855 }
1856
1857 return 0;
1858}
1859
1860static void mpsc_shared_unmap_regs(void)
1861{
1862 if (!mpsc_shared_regs.mpsc_routing_base) {
1863 iounmap(mpsc_shared_regs.mpsc_routing_base);
1864 release_mem_region(mpsc_shared_regs.mpsc_routing_base_p,
1865 MPSC_ROUTING_REG_BLOCK_SIZE);
1866 }
1867 if (!mpsc_shared_regs.sdma_intr_base) {
1868 iounmap(mpsc_shared_regs.sdma_intr_base);
1869 release_mem_region(mpsc_shared_regs.sdma_intr_base_p,
1870 MPSC_SDMA_INTR_REG_BLOCK_SIZE);
1871 }
1872
1873 mpsc_shared_regs.mpsc_routing_base = NULL;
1874 mpsc_shared_regs.sdma_intr_base = NULL;
1875
1876 mpsc_shared_regs.mpsc_routing_base_p = 0;
1877 mpsc_shared_regs.sdma_intr_base_p = 0;
1878}
1879
1880static int mpsc_shared_drv_probe(struct platform_device *dev)
1881{
1882 struct mpsc_shared_pdata *pdata;
1883 int rc = -ENODEV;
1884
1885 if (dev->id == 0) {
1886 if (!(rc = mpsc_shared_map_regs(dev))) {
1887 pdata = (struct mpsc_shared_pdata *)
1888 dev->dev.platform_data;
1889
1890 mpsc_shared_regs.MPSC_MRR_m = pdata->mrr_val;
1891 mpsc_shared_regs.MPSC_RCRR_m= pdata->rcrr_val;
1892 mpsc_shared_regs.MPSC_TCRR_m= pdata->tcrr_val;
1893 mpsc_shared_regs.SDMA_INTR_CAUSE_m =
1894 pdata->intr_cause_val;
1895 mpsc_shared_regs.SDMA_INTR_MASK_m =
1896 pdata->intr_mask_val;
1897
1898 rc = 0;
1899 }
1900 }
1901
1902 return rc;
1903}
1904
1905static int mpsc_shared_drv_remove(struct platform_device *dev)
1906{
1907 int rc = -ENODEV;
1908
1909 if (dev->id == 0) {
1910 mpsc_shared_unmap_regs();
1911 mpsc_shared_regs.MPSC_MRR_m = 0;
1912 mpsc_shared_regs.MPSC_RCRR_m = 0;
1913 mpsc_shared_regs.MPSC_TCRR_m = 0;
1914 mpsc_shared_regs.SDMA_INTR_CAUSE_m = 0;
1915 mpsc_shared_regs.SDMA_INTR_MASK_m = 0;
1916 rc = 0;
1917 }
1918
1919 return rc;
1920}
1921
1922static struct platform_driver mpsc_shared_driver = {
1923 .probe = mpsc_shared_drv_probe,
1924 .remove = mpsc_shared_drv_remove,
1925 .driver = {
1926 .name = MPSC_SHARED_NAME,
1927 },
1928};
1929
1930/*
1931 ******************************************************************************
1932 *
1933 * Driver Interface Routines
1934 *
1935 ******************************************************************************
1936 */
1937static struct uart_driver mpsc_reg = {
1938 .owner = THIS_MODULE,
1939 .driver_name = MPSC_DRIVER_NAME,
1940 .dev_name = MPSC_DEV_NAME,
1941 .major = MPSC_MAJOR,
1942 .minor = MPSC_MINOR_START,
1943 .nr = MPSC_NUM_CTLRS,
1944 .cons = MPSC_CONSOLE,
1945};
1946
1947static int mpsc_drv_map_regs(struct mpsc_port_info *pi,
1948 struct platform_device *pd)
1949{
1950 struct resource *r;
1951
1952 if ((r = platform_get_resource(pd, IORESOURCE_MEM, MPSC_BASE_ORDER))
1953 && request_mem_region(r->start, MPSC_REG_BLOCK_SIZE,
1954 "mpsc_regs")) {
1955 pi->mpsc_base = ioremap(r->start, MPSC_REG_BLOCK_SIZE);
1956 pi->mpsc_base_p = r->start;
1957 } else {
1958 mpsc_resource_err("MPSC base");
1959 goto err;
1960 }
1961
1962 if ((r = platform_get_resource(pd, IORESOURCE_MEM,
1963 MPSC_SDMA_BASE_ORDER))
1964 && request_mem_region(r->start,
1965 MPSC_SDMA_REG_BLOCK_SIZE, "sdma_regs")) {
1966 pi->sdma_base = ioremap(r->start,MPSC_SDMA_REG_BLOCK_SIZE);
1967 pi->sdma_base_p = r->start;
1968 } else {
1969 mpsc_resource_err("SDMA base");
1970 if (pi->mpsc_base) {
1971 iounmap(pi->mpsc_base);
1972 pi->mpsc_base = NULL;
1973 }
1974 goto err;
1975 }
1976
1977 if ((r = platform_get_resource(pd,IORESOURCE_MEM,MPSC_BRG_BASE_ORDER))
1978 && request_mem_region(r->start,
1979 MPSC_BRG_REG_BLOCK_SIZE, "brg_regs")) {
1980 pi->brg_base = ioremap(r->start, MPSC_BRG_REG_BLOCK_SIZE);
1981 pi->brg_base_p = r->start;
1982 } else {
1983 mpsc_resource_err("BRG base");
1984 if (pi->mpsc_base) {
1985 iounmap(pi->mpsc_base);
1986 pi->mpsc_base = NULL;
1987 }
1988 if (pi->sdma_base) {
1989 iounmap(pi->sdma_base);
1990 pi->sdma_base = NULL;
1991 }
1992 goto err;
1993 }
1994 return 0;
1995
1996err:
1997 return -ENOMEM;
1998}
1999
2000static void mpsc_drv_unmap_regs(struct mpsc_port_info *pi)
2001{
2002 if (!pi->mpsc_base) {
2003 iounmap(pi->mpsc_base);
2004 release_mem_region(pi->mpsc_base_p, MPSC_REG_BLOCK_SIZE);
2005 }
2006 if (!pi->sdma_base) {
2007 iounmap(pi->sdma_base);
2008 release_mem_region(pi->sdma_base_p, MPSC_SDMA_REG_BLOCK_SIZE);
2009 }
2010 if (!pi->brg_base) {
2011 iounmap(pi->brg_base);
2012 release_mem_region(pi->brg_base_p, MPSC_BRG_REG_BLOCK_SIZE);
2013 }
2014
2015 pi->mpsc_base = NULL;
2016 pi->sdma_base = NULL;
2017 pi->brg_base = NULL;
2018
2019 pi->mpsc_base_p = 0;
2020 pi->sdma_base_p = 0;
2021 pi->brg_base_p = 0;
2022}
2023
2024static void mpsc_drv_get_platform_data(struct mpsc_port_info *pi,
2025 struct platform_device *pd, int num)
2026{
2027 struct mpsc_pdata *pdata;
2028
2029 pdata = (struct mpsc_pdata *)pd->dev.platform_data;
2030
2031 pi->port.uartclk = pdata->brg_clk_freq;
2032 pi->port.iotype = UPIO_MEM;
2033 pi->port.line = num;
2034 pi->port.type = PORT_MPSC;
2035 pi->port.fifosize = MPSC_TXBE_SIZE;
2036 pi->port.membase = pi->mpsc_base;
2037 pi->port.mapbase = (ulong)pi->mpsc_base;
2038 pi->port.ops = &mpsc_pops;
2039
2040 pi->mirror_regs = pdata->mirror_regs;
2041 pi->cache_mgmt = pdata->cache_mgmt;
2042 pi->brg_can_tune = pdata->brg_can_tune;
2043 pi->brg_clk_src = pdata->brg_clk_src;
2044 pi->mpsc_max_idle = pdata->max_idle;
2045 pi->default_baud = pdata->default_baud;
2046 pi->default_bits = pdata->default_bits;
2047 pi->default_parity = pdata->default_parity;
2048 pi->default_flow = pdata->default_flow;
2049
2050 /* Initial values of mirrored regs */
2051 pi->MPSC_CHR_1_m = pdata->chr_1_val;
2052 pi->MPSC_CHR_2_m = pdata->chr_2_val;
2053 pi->MPSC_CHR_10_m = pdata->chr_10_val;
2054 pi->MPSC_MPCR_m = pdata->mpcr_val;
2055 pi->BRG_BCR_m = pdata->bcr_val;
2056
2057 pi->shared_regs = &mpsc_shared_regs;
2058
2059 pi->port.irq = platform_get_irq(pd, 0);
2060}
2061
2062static int mpsc_drv_probe(struct platform_device *dev)
2063{
2064 struct mpsc_port_info *pi;
2065 int rc = -ENODEV;
2066
2067 pr_debug("mpsc_drv_probe: Adding MPSC %d\n", dev->id);
2068
2069 if (dev->id < MPSC_NUM_CTLRS) {
2070 pi = &mpsc_ports[dev->id];
2071
2072 if (!(rc = mpsc_drv_map_regs(pi, dev))) {
2073 mpsc_drv_get_platform_data(pi, dev, dev->id);
2074 pi->port.dev = &dev->dev;
2075
2076 if (!(rc = mpsc_make_ready(pi))) {
2077 spin_lock_init(&pi->tx_lock);
2078 if (!(rc = uart_add_one_port(&mpsc_reg,
2079 &pi->port))) {
2080 rc = 0;
2081 } else {
2082 mpsc_release_port((struct uart_port *)
2083 pi);
2084 mpsc_drv_unmap_regs(pi);
2085 }
2086 } else {
2087 mpsc_drv_unmap_regs(pi);
2088 }
2089 }
2090 }
2091
2092 return rc;
2093}
2094
2095static int mpsc_drv_remove(struct platform_device *dev)
2096{
2097 pr_debug("mpsc_drv_exit: Removing MPSC %d\n", dev->id);
2098
2099 if (dev->id < MPSC_NUM_CTLRS) {
2100 uart_remove_one_port(&mpsc_reg, &mpsc_ports[dev->id].port);
2101 mpsc_release_port((struct uart_port *)
2102 &mpsc_ports[dev->id].port);
2103 mpsc_drv_unmap_regs(&mpsc_ports[dev->id]);
2104 return 0;
2105 } else {
2106 return -ENODEV;
2107 }
2108}
2109
2110static struct platform_driver mpsc_driver = {
2111 .probe = mpsc_drv_probe,
2112 .remove = mpsc_drv_remove,
2113 .driver = {
2114 .name = MPSC_CTLR_NAME,
2115 .owner = THIS_MODULE,
2116 },
2117};
2118
2119static int __init mpsc_drv_init(void)
2120{
2121 int rc;
2122
2123 printk(KERN_INFO "Serial: MPSC driver\n");
2124
2125 memset(mpsc_ports, 0, sizeof(mpsc_ports));
2126 memset(&mpsc_shared_regs, 0, sizeof(mpsc_shared_regs));
2127
2128 if (!(rc = uart_register_driver(&mpsc_reg))) {
2129 if (!(rc = platform_driver_register(&mpsc_shared_driver))) {
2130 if ((rc = platform_driver_register(&mpsc_driver))) {
2131 platform_driver_unregister(&mpsc_shared_driver);
2132 uart_unregister_driver(&mpsc_reg);
2133 }
2134 } else {
2135 uart_unregister_driver(&mpsc_reg);
2136 }
2137 }
2138
2139 return rc;
2140}
2141
2142static void __exit mpsc_drv_exit(void)
2143{
2144 platform_driver_unregister(&mpsc_driver);
2145 platform_driver_unregister(&mpsc_shared_driver);
2146 uart_unregister_driver(&mpsc_reg);
2147 memset(mpsc_ports, 0, sizeof(mpsc_ports));
2148 memset(&mpsc_shared_regs, 0, sizeof(mpsc_shared_regs));
2149}
2150
2151module_init(mpsc_drv_init);
2152module_exit(mpsc_drv_exit);
2153
2154MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
2155MODULE_DESCRIPTION("Generic Marvell MPSC serial/UART driver");
2156MODULE_VERSION(MPSC_VERSION);
2157MODULE_LICENSE("GPL");
2158MODULE_ALIAS_CHARDEV_MAJOR(MPSC_MAJOR);
2159MODULE_ALIAS("platform:" MPSC_CTLR_NAME);
diff --git a/drivers/serial/mrst_max3110.c b/drivers/serial/mrst_max3110.c
deleted file mode 100644
index 51c15f58e01e..000000000000
--- a/drivers/serial/mrst_max3110.c
+++ /dev/null
@@ -1,845 +0,0 @@
1/*
2 * max3110.c - spi uart protocol driver for Maxim 3110 on Moorestown
3 *
4 * Copyright (C) Intel 2008 Feng Tang <feng.tang@intel.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 */
19
20/*
21 * Note:
22 * 1. From Max3110 spec, the Rx FIFO has 8 words, while the Tx FIFO only has
23 * 1 word. If SPI master controller doesn't support sclk frequency change,
24 * then the char need be sent out one by one with some delay
25 *
26 * 2. Currently only RX availabe interrrupt is used, no need for waiting TXE
27 * interrupt for a low speed UART device
28 */
29
30#include <linux/module.h>
31#include <linux/ioport.h>
32#include <linux/irq.h>
33#include <linux/init.h>
34#include <linux/console.h>
35#include <linux/sysrq.h>
36#include <linux/platform_device.h>
37#include <linux/tty.h>
38#include <linux/tty_flip.h>
39#include <linux/serial_core.h>
40#include <linux/serial_reg.h>
41
42#include <linux/kthread.h>
43#include <linux/delay.h>
44#include <asm/atomic.h>
45#include <linux/spi/spi.h>
46#include <linux/spi/dw_spi.h>
47
48#include "mrst_max3110.h"
49
50#define PR_FMT "mrst_max3110: "
51
52#define UART_TX_NEEDED 1
53#define CON_TX_NEEDED 2
54#define BIT_IRQ_PENDING 3
55
56struct uart_max3110 {
57 struct uart_port port;
58 struct spi_device *spi;
59 char *name;
60
61 wait_queue_head_t wq;
62 struct task_struct *main_thread;
63 struct task_struct *read_thread;
64 struct mutex thread_mutex;;
65
66 u32 baud;
67 u16 cur_conf;
68 u8 clock;
69 u8 parity, word_7bits;
70
71 unsigned long uart_flags;
72
73 /* console related */
74 struct circ_buf con_xmit;
75
76 /* irq related */
77 u16 irq;
78};
79
80/* global data structure, may need be removed */
81struct uart_max3110 *pmax;
82static inline void receive_char(struct uart_max3110 *max, u8 ch);
83static void receive_chars(struct uart_max3110 *max,
84 unsigned char *str, int len);
85static int max3110_read_multi(struct uart_max3110 *max, int len, u8 *buf);
86static void max3110_console_receive(struct uart_max3110 *max);
87
88int max3110_write_then_read(struct uart_max3110 *max,
89 const u8 *txbuf, u8 *rxbuf, unsigned len, int always_fast)
90{
91 struct spi_device *spi = max->spi;
92 struct spi_message message;
93 struct spi_transfer x;
94 int ret;
95
96 if (!txbuf || !rxbuf)
97 return -EINVAL;
98
99 spi_message_init(&message);
100 memset(&x, 0, sizeof x);
101 x.len = len;
102 x.tx_buf = txbuf;
103 x.rx_buf = rxbuf;
104 spi_message_add_tail(&x, &message);
105
106 if (always_fast)
107 x.speed_hz = 3125000;
108 else if (max->baud)
109 x.speed_hz = max->baud;
110
111 /* Do the i/o */
112 ret = spi_sync(spi, &message);
113 return ret;
114}
115
116/* Write a u16 to the device, and return one u16 read back */
117int max3110_out(struct uart_max3110 *max, const u16 out)
118{
119 u16 tmp;
120 int ret;
121
122 ret = max3110_write_then_read(max, (u8 *)&out, (u8 *)&tmp, 2, 1);
123 if (ret)
124 return ret;
125
126 /* If some valid data is read back */
127 if (tmp & MAX3110_READ_DATA_AVAILABLE)
128 receive_char(max, (tmp & 0xff));
129
130 return ret;
131}
132
133#define MAX_READ_LEN 20
134/*
135 * This is usually used to read data from SPIC RX FIFO, which doesn't
136 * need any delay like flushing character out. It returns how many
137 * valide bytes are read back
138 */
139static int max3110_read_multi(struct uart_max3110 *max, int len, u8 *buf)
140{
141 u16 out[MAX_READ_LEN], in[MAX_READ_LEN];
142 u8 *pbuf, valid_str[MAX_READ_LEN];
143 int i, j, bytelen;
144
145 if (len > MAX_READ_LEN) {
146 pr_err(PR_FMT "read len %d is too large\n", len);
147 return 0;
148 }
149
150 bytelen = len * 2;
151 memset(out, 0, bytelen);
152 memset(in, 0, bytelen);
153
154 if (max3110_write_then_read(max, (u8 *)out, (u8 *)in, bytelen, 1))
155 return 0;
156
157 /* If caller don't provide a buffer, then handle received char */
158 pbuf = buf ? buf : valid_str;
159
160 for (i = 0, j = 0; i < len; i++) {
161 if (in[i] & MAX3110_READ_DATA_AVAILABLE)
162 pbuf[j++] = (u8)(in[i] & 0xff);
163 }
164
165 if (j && (pbuf == valid_str))
166 receive_chars(max, valid_str, j);
167
168 return j;
169}
170
171static void serial_m3110_con_putchar(struct uart_port *port, int ch)
172{
173 struct uart_max3110 *max =
174 container_of(port, struct uart_max3110, port);
175 struct circ_buf *xmit = &max->con_xmit;
176
177 if (uart_circ_chars_free(xmit)) {
178 xmit->buf[xmit->head] = (char)ch;
179 xmit->head = (xmit->head + 1) & (PAGE_SIZE - 1);
180 }
181
182
183 if (!test_and_set_bit(CON_TX_NEEDED, &max->uart_flags))
184 wake_up_process(max->main_thread);
185}
186
187/*
188 * Print a string to the serial port trying not to disturb
189 * any possible real use of the port...
190 *
191 * The console_lock must be held when we get here.
192 */
193static void serial_m3110_con_write(struct console *co,
194 const char *s, unsigned int count)
195{
196 if (!pmax)
197 return;
198
199 uart_console_write(&pmax->port, s, count, serial_m3110_con_putchar);
200}
201
202static int __init
203serial_m3110_con_setup(struct console *co, char *options)
204{
205 struct uart_max3110 *max = pmax;
206 int baud = 115200;
207 int bits = 8;
208 int parity = 'n';
209 int flow = 'n';
210
211 pr_info(PR_FMT "setting up console\n");
212
213 if (!max) {
214 pr_err(PR_FMT "pmax is NULL, return");
215 return -ENODEV;
216 }
217
218 if (options)
219 uart_parse_options(options, &baud, &parity, &bits, &flow);
220
221 return uart_set_options(&max->port, co, baud, parity, bits, flow);
222}
223
224static struct tty_driver *serial_m3110_con_device(struct console *co,
225 int *index)
226{
227 struct uart_driver *p = co->data;
228 *index = co->index;
229 return p->tty_driver;
230}
231
232static struct uart_driver serial_m3110_reg;
233static struct console serial_m3110_console = {
234 .name = "ttyS",
235 .write = serial_m3110_con_write,
236 .device = serial_m3110_con_device,
237 .setup = serial_m3110_con_setup,
238 .flags = CON_PRINTBUFFER,
239 .index = -1,
240 .data = &serial_m3110_reg,
241};
242
243#define MRST_CONSOLE (&serial_m3110_console)
244
245static unsigned int serial_m3110_tx_empty(struct uart_port *port)
246{
247 return 1;
248}
249
250static void serial_m3110_stop_tx(struct uart_port *port)
251{
252 return;
253}
254
255/* stop_rx will be called in spin_lock env */
256static void serial_m3110_stop_rx(struct uart_port *port)
257{
258 return;
259}
260
261#define WORDS_PER_XFER 128
262static inline void send_circ_buf(struct uart_max3110 *max,
263 struct circ_buf *xmit)
264{
265 int len, left = 0;
266 u16 obuf[WORDS_PER_XFER], ibuf[WORDS_PER_XFER];
267 u8 valid_str[WORDS_PER_XFER];
268 int i, j;
269
270 while (!uart_circ_empty(xmit)) {
271 left = uart_circ_chars_pending(xmit);
272 while (left) {
273 len = (left >= WORDS_PER_XFER) ? WORDS_PER_XFER : left;
274
275 memset(obuf, 0, len * 2);
276 memset(ibuf, 0, len * 2);
277 for (i = 0; i < len; i++) {
278 obuf[i] = (u8)xmit->buf[xmit->tail] | WD_TAG;
279 xmit->tail = (xmit->tail + 1) &
280 (UART_XMIT_SIZE - 1);
281 }
282 max3110_write_then_read(max, (u8 *)obuf,
283 (u8 *)ibuf, len * 2, 0);
284
285 for (i = 0, j = 0; i < len; i++) {
286 if (ibuf[i] & MAX3110_READ_DATA_AVAILABLE)
287 valid_str[j++] = (u8)(ibuf[i] & 0xff);
288 }
289
290 if (j)
291 receive_chars(max, valid_str, j);
292
293 max->port.icount.tx += len;
294 left -= len;
295 }
296 }
297}
298
299static void transmit_char(struct uart_max3110 *max)
300{
301 struct uart_port *port = &max->port;
302 struct circ_buf *xmit = &port->state->xmit;
303
304 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
305 return;
306
307 send_circ_buf(max, xmit);
308
309 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
310 uart_write_wakeup(port);
311
312 if (uart_circ_empty(xmit))
313 serial_m3110_stop_tx(port);
314}
315
316/* This will be called by uart_write() and tty_write, can't
317 * go to sleep */
318static void serial_m3110_start_tx(struct uart_port *port)
319{
320 struct uart_max3110 *max =
321 container_of(port, struct uart_max3110, port);
322
323 if (!test_and_set_bit(UART_TX_NEEDED, &max->uart_flags))
324 wake_up_process(max->main_thread);
325}
326
327static void receive_chars(struct uart_max3110 *max, unsigned char *str, int len)
328{
329 struct uart_port *port = &max->port;
330 struct tty_struct *tty;
331 int usable;
332
333 /* If uart is not opened, just return */
334 if (!port->state)
335 return;
336
337 tty = port->state->port.tty;
338 if (!tty)
339 return; /* receive some char before the tty is opened */
340
341 while (len) {
342 usable = tty_buffer_request_room(tty, len);
343 if (usable) {
344 tty_insert_flip_string(tty, str, usable);
345 str += usable;
346 port->icount.rx += usable;
347 tty_flip_buffer_push(tty);
348 }
349 len -= usable;
350 }
351}
352
353static inline void receive_char(struct uart_max3110 *max, u8 ch)
354{
355 receive_chars(max, &ch, 1);
356}
357
358static void max3110_console_receive(struct uart_max3110 *max)
359{
360 int loop = 1, num, total = 0;
361 u8 recv_buf[512], *pbuf;
362
363 pbuf = recv_buf;
364 do {
365 num = max3110_read_multi(max, 8, pbuf);
366
367 if (num) {
368 loop = 10;
369 pbuf += num;
370 total += num;
371
372 if (total >= 500) {
373 receive_chars(max, recv_buf, total);
374 pbuf = recv_buf;
375 total = 0;
376 }
377 }
378 } while (--loop);
379
380 if (total)
381 receive_chars(max, recv_buf, total);
382}
383
384static int max3110_main_thread(void *_max)
385{
386 struct uart_max3110 *max = _max;
387 wait_queue_head_t *wq = &max->wq;
388 int ret = 0;
389 struct circ_buf *xmit = &max->con_xmit;
390
391 init_waitqueue_head(wq);
392 pr_info(PR_FMT "start main thread\n");
393
394 do {
395 wait_event_interruptible(*wq, max->uart_flags || kthread_should_stop());
396
397 mutex_lock(&max->thread_mutex);
398
399 if (test_and_clear_bit(BIT_IRQ_PENDING, &max->uart_flags))
400 max3110_console_receive(max);
401
402 /* first handle console output */
403 if (test_and_clear_bit(CON_TX_NEEDED, &max->uart_flags))
404 send_circ_buf(max, xmit);
405
406 /* handle uart output */
407 if (test_and_clear_bit(UART_TX_NEEDED, &max->uart_flags))
408 transmit_char(max);
409
410 mutex_unlock(&max->thread_mutex);
411
412 } while (!kthread_should_stop());
413
414 return ret;
415}
416
417#ifdef CONFIG_MRST_MAX3110_IRQ
418static irqreturn_t serial_m3110_irq(int irq, void *dev_id)
419{
420 struct uart_max3110 *max = dev_id;
421
422 /* max3110's irq is a falling edge, not level triggered,
423 * so no need to disable the irq */
424 if (!test_and_set_bit(BIT_IRQ_PENDING, &max->uart_flags))
425 wake_up_process(max->main_thread);
426
427 return IRQ_HANDLED;
428}
429#else
430/* if don't use RX IRQ, then need a thread to polling read */
431static int max3110_read_thread(void *_max)
432{
433 struct uart_max3110 *max = _max;
434
435 pr_info(PR_FMT "start read thread\n");
436 do {
437 mutex_lock(&max->thread_mutex);
438 max3110_console_receive(max);
439 mutex_unlock(&max->thread_mutex);
440
441 set_current_state(TASK_INTERRUPTIBLE);
442 schedule_timeout(HZ / 20);
443 } while (!kthread_should_stop());
444
445 return 0;
446}
447#endif
448
449static int serial_m3110_startup(struct uart_port *port)
450{
451 struct uart_max3110 *max =
452 container_of(port, struct uart_max3110, port);
453 u16 config = 0;
454 int ret = 0;
455
456 if (port->line != 0)
457 pr_err(PR_FMT "uart port startup failed\n");
458
459 /* firstly disable all IRQ and config it to 115200, 8n1 */
460 config = WC_TAG | WC_FIFO_ENABLE
461 | WC_1_STOPBITS
462 | WC_8BIT_WORD
463 | WC_BAUD_DR2;
464 ret = max3110_out(max, config);
465
466 /* as we use thread to handle tx/rx, need set low latency */
467 port->state->port.tty->low_latency = 1;
468
469#ifdef CONFIG_MRST_MAX3110_IRQ
470 ret = request_irq(max->irq, serial_m3110_irq,
471 IRQ_TYPE_EDGE_FALLING, "max3110", max);
472 if (ret)
473 return ret;
474
475 /* enable RX IRQ only */
476 config |= WC_RXA_IRQ_ENABLE;
477 max3110_out(max, config);
478#else
479 /* if IRQ is disabled, start a read thread for input data */
480 max->read_thread =
481 kthread_run(max3110_read_thread, max, "max3110_read");
482#endif
483
484 max->cur_conf = config;
485 return 0;
486}
487
488static void serial_m3110_shutdown(struct uart_port *port)
489{
490 struct uart_max3110 *max =
491 container_of(port, struct uart_max3110, port);
492 u16 config;
493
494 if (max->read_thread) {
495 kthread_stop(max->read_thread);
496 max->read_thread = NULL;
497 }
498
499#ifdef CONFIG_MRST_MAX3110_IRQ
500 free_irq(max->irq, max);
501#endif
502
503 /* Disable interrupts from this port */
504 config = WC_TAG | WC_SW_SHDI;
505 max3110_out(max, config);
506}
507
508static void serial_m3110_release_port(struct uart_port *port)
509{
510}
511
512static int serial_m3110_request_port(struct uart_port *port)
513{
514 return 0;
515}
516
517static void serial_m3110_config_port(struct uart_port *port, int flags)
518{
519 /* give it fake type */
520 port->type = PORT_PXA;
521}
522
523static int
524serial_m3110_verify_port(struct uart_port *port, struct serial_struct *ser)
525{
526 /* we don't want the core code to modify any port params */
527 return -EINVAL;
528}
529
530
531static const char *serial_m3110_type(struct uart_port *port)
532{
533 struct uart_max3110 *max =
534 container_of(port, struct uart_max3110, port);
535 return max->name;
536}
537
538static void
539serial_m3110_set_termios(struct uart_port *port, struct ktermios *termios,
540 struct ktermios *old)
541{
542 struct uart_max3110 *max =
543 container_of(port, struct uart_max3110, port);
544 unsigned char cval;
545 unsigned int baud, parity = 0;
546 int clk_div = -1;
547 u16 new_conf = max->cur_conf;
548
549 switch (termios->c_cflag & CSIZE) {
550 case CS7:
551 cval = UART_LCR_WLEN7;
552 new_conf |= WC_7BIT_WORD;
553 break;
554 default:
555 case CS8:
556 cval = UART_LCR_WLEN8;
557 new_conf |= WC_8BIT_WORD;
558 break;
559 }
560
561 baud = uart_get_baud_rate(port, termios, old, 0, 230400);
562
563 /* first calc the div for 1.8MHZ clock case */
564 switch (baud) {
565 case 300:
566 clk_div = WC_BAUD_DR384;
567 break;
568 case 600:
569 clk_div = WC_BAUD_DR192;
570 break;
571 case 1200:
572 clk_div = WC_BAUD_DR96;
573 break;
574 case 2400:
575 clk_div = WC_BAUD_DR48;
576 break;
577 case 4800:
578 clk_div = WC_BAUD_DR24;
579 break;
580 case 9600:
581 clk_div = WC_BAUD_DR12;
582 break;
583 case 19200:
584 clk_div = WC_BAUD_DR6;
585 break;
586 case 38400:
587 clk_div = WC_BAUD_DR3;
588 break;
589 case 57600:
590 clk_div = WC_BAUD_DR2;
591 break;
592 case 115200:
593 clk_div = WC_BAUD_DR1;
594 break;
595 case 230400:
596 if (max->clock & MAX3110_HIGH_CLK)
597 break;
598 default:
599 /* pick the previous baud rate */
600 baud = max->baud;
601 clk_div = max->cur_conf & WC_BAUD_DIV_MASK;
602 tty_termios_encode_baud_rate(termios, baud, baud);
603 }
604
605 if (max->clock & MAX3110_HIGH_CLK) {
606 clk_div += 1;
607 /* high clk version max3110 doesn't support B300 */
608 if (baud == 300)
609 baud = 600;
610 if (baud == 230400)
611 clk_div = WC_BAUD_DR1;
612 tty_termios_encode_baud_rate(termios, baud, baud);
613 }
614
615 new_conf = (new_conf & ~WC_BAUD_DIV_MASK) | clk_div;
616 if (termios->c_cflag & CSTOPB)
617 new_conf |= WC_2_STOPBITS;
618 else
619 new_conf &= ~WC_2_STOPBITS;
620
621 if (termios->c_cflag & PARENB) {
622 new_conf |= WC_PARITY_ENABLE;
623 parity |= UART_LCR_PARITY;
624 } else
625 new_conf &= ~WC_PARITY_ENABLE;
626
627 if (!(termios->c_cflag & PARODD))
628 parity |= UART_LCR_EPAR;
629 max->parity = parity;
630
631 uart_update_timeout(port, termios->c_cflag, baud);
632
633 new_conf |= WC_TAG;
634 if (new_conf != max->cur_conf) {
635 max3110_out(max, new_conf);
636 max->cur_conf = new_conf;
637 max->baud = baud;
638 }
639}
640
641/* don't handle hw handshaking */
642static unsigned int serial_m3110_get_mctrl(struct uart_port *port)
643{
644 return TIOCM_DSR | TIOCM_CAR | TIOCM_DSR;
645}
646
647static void serial_m3110_set_mctrl(struct uart_port *port, unsigned int mctrl)
648{
649}
650
651static void serial_m3110_break_ctl(struct uart_port *port, int break_state)
652{
653}
654
655static void serial_m3110_pm(struct uart_port *port, unsigned int state,
656 unsigned int oldstate)
657{
658}
659
660static void serial_m3110_enable_ms(struct uart_port *port)
661{
662}
663
664struct uart_ops serial_m3110_ops = {
665 .tx_empty = serial_m3110_tx_empty,
666 .set_mctrl = serial_m3110_set_mctrl,
667 .get_mctrl = serial_m3110_get_mctrl,
668 .stop_tx = serial_m3110_stop_tx,
669 .start_tx = serial_m3110_start_tx,
670 .stop_rx = serial_m3110_stop_rx,
671 .enable_ms = serial_m3110_enable_ms,
672 .break_ctl = serial_m3110_break_ctl,
673 .startup = serial_m3110_startup,
674 .shutdown = serial_m3110_shutdown,
675 .set_termios = serial_m3110_set_termios, /* must have */
676 .pm = serial_m3110_pm,
677 .type = serial_m3110_type,
678 .release_port = serial_m3110_release_port,
679 .request_port = serial_m3110_request_port,
680 .config_port = serial_m3110_config_port,
681 .verify_port = serial_m3110_verify_port,
682};
683
684static struct uart_driver serial_m3110_reg = {
685 .owner = THIS_MODULE,
686 .driver_name = "MRST serial",
687 .dev_name = "ttyS",
688 .major = TTY_MAJOR,
689 .minor = 64,
690 .nr = 1,
691 .cons = MRST_CONSOLE,
692};
693
694static int serial_m3110_suspend(struct spi_device *spi, pm_message_t state)
695{
696 return 0;
697}
698
699static int serial_m3110_resume(struct spi_device *spi)
700{
701 return 0;
702}
703
704static struct dw_spi_chip spi0_uart = {
705 .poll_mode = 1,
706 .enable_dma = 0,
707 .type = SPI_FRF_SPI,
708};
709
710static int serial_m3110_probe(struct spi_device *spi)
711{
712 struct uart_max3110 *max;
713 int ret;
714 unsigned char *buffer;
715 u16 res;
716 max = kzalloc(sizeof(*max), GFP_KERNEL);
717 if (!max)
718 return -ENOMEM;
719
720 /* set spi info */
721 spi->mode = SPI_MODE_0;
722 spi->bits_per_word = 16;
723 max->clock = MAX3110_HIGH_CLK;
724 spi->controller_data = &spi0_uart;
725
726 spi_setup(spi);
727
728 max->port.type = PORT_PXA; /* need apply for a max3110 type */
729 max->port.fifosize = 2; /* only have 16b buffer */
730 max->port.ops = &serial_m3110_ops;
731 max->port.line = 0;
732 max->port.dev = &spi->dev;
733 max->port.uartclk = 115200;
734
735 max->spi = spi;
736 max->name = spi->modalias; /* use spi name as the name */
737 max->irq = (u16)spi->irq;
738
739 mutex_init(&max->thread_mutex);
740
741 max->word_7bits = 0;
742 max->parity = 0;
743 max->baud = 0;
744
745 max->cur_conf = 0;
746 max->uart_flags = 0;
747
748 /* Check if reading configuration register returns something sane */
749
750 res = RC_TAG;
751 ret = max3110_write_then_read(max, (u8 *)&res, (u8 *)&res, 2, 0);
752 if (ret < 0 || res == 0 || res == 0xffff) {
753 printk(KERN_ERR "MAX3111 deemed not present (conf reg %04x)",
754 res);
755 ret = -ENODEV;
756 goto err_get_page;
757 }
758 buffer = (unsigned char *)__get_free_page(GFP_KERNEL);
759 if (!buffer) {
760 ret = -ENOMEM;
761 goto err_get_page;
762 }
763 max->con_xmit.buf = (unsigned char *)buffer;
764 max->con_xmit.head = max->con_xmit.tail = 0;
765
766 max->main_thread = kthread_run(max3110_main_thread,
767 max, "max3110_main");
768 if (IS_ERR(max->main_thread)) {
769 ret = PTR_ERR(max->main_thread);
770 goto err_kthread;
771 }
772
773 pmax = max;
774 /* give membase a psudo value to pass serial_core's check */
775 max->port.membase = (void *)0xff110000;
776 uart_add_one_port(&serial_m3110_reg, &max->port);
777
778 return 0;
779
780err_kthread:
781 free_page((unsigned long)buffer);
782err_get_page:
783 pmax = NULL;
784 kfree(max);
785 return ret;
786}
787
788static int max3110_remove(struct spi_device *dev)
789{
790 struct uart_max3110 *max = pmax;
791
792 if (!pmax)
793 return 0;
794
795 pmax = NULL;
796 uart_remove_one_port(&serial_m3110_reg, &max->port);
797
798 free_page((unsigned long)max->con_xmit.buf);
799
800 if (max->main_thread)
801 kthread_stop(max->main_thread);
802
803 kfree(max);
804 return 0;
805}
806
807static struct spi_driver uart_max3110_driver = {
808 .driver = {
809 .name = "spi_max3111",
810 .bus = &spi_bus_type,
811 .owner = THIS_MODULE,
812 },
813 .probe = serial_m3110_probe,
814 .remove = __devexit_p(max3110_remove),
815 .suspend = serial_m3110_suspend,
816 .resume = serial_m3110_resume,
817};
818
819
820int __init serial_m3110_init(void)
821{
822 int ret = 0;
823
824 ret = uart_register_driver(&serial_m3110_reg);
825 if (ret)
826 return ret;
827
828 ret = spi_register_driver(&uart_max3110_driver);
829 if (ret)
830 uart_unregister_driver(&serial_m3110_reg);
831
832 return ret;
833}
834
835void __exit serial_m3110_exit(void)
836{
837 spi_unregister_driver(&uart_max3110_driver);
838 uart_unregister_driver(&serial_m3110_reg);
839}
840
841module_init(serial_m3110_init);
842module_exit(serial_m3110_exit);
843
844MODULE_LICENSE("GPL");
845MODULE_ALIAS("max3110-uart");
diff --git a/drivers/serial/mrst_max3110.h b/drivers/serial/mrst_max3110.h
deleted file mode 100644
index 363478acb2c3..000000000000
--- a/drivers/serial/mrst_max3110.h
+++ /dev/null
@@ -1,59 +0,0 @@
1#ifndef _MRST_MAX3110_H
2#define _MRST_MAX3110_H
3
4#define MAX3110_HIGH_CLK 0x1 /* 3.6864 MHZ */
5#define MAX3110_LOW_CLK 0x0 /* 1.8432 MHZ */
6
7/* status bits for all 4 MAX3110 operate modes */
8#define MAX3110_READ_DATA_AVAILABLE (1 << 15)
9#define MAX3110_WRITE_BUF_EMPTY (1 << 14)
10
11#define WC_TAG (3 << 14)
12#define RC_TAG (1 << 14)
13#define WD_TAG (2 << 14)
14#define RD_TAG (0 << 14)
15
16/* bits def for write configuration */
17#define WC_FIFO_ENABLE_MASK (1 << 13)
18#define WC_FIFO_ENABLE (0 << 13)
19
20#define WC_SW_SHDI (1 << 12)
21
22#define WC_IRQ_MASK (0xF << 8)
23#define WC_TXE_IRQ_ENABLE (1 << 11) /* TX empty irq */
24#define WC_RXA_IRQ_ENABLE (1 << 10) /* RX availabe irq */
25#define WC_PAR_HIGH_IRQ_ENABLE (1 << 9)
26#define WC_REC_ACT_IRQ_ENABLE (1 << 8)
27
28#define WC_IRDA_ENABLE (1 << 7)
29
30#define WC_STOPBITS_MASK (1 << 6)
31#define WC_2_STOPBITS (1 << 6)
32#define WC_1_STOPBITS (0 << 6)
33
34#define WC_PARITY_ENABLE_MASK (1 << 5)
35#define WC_PARITY_ENABLE (1 << 5)
36
37#define WC_WORDLEN_MASK (1 << 4)
38#define WC_7BIT_WORD (1 << 4)
39#define WC_8BIT_WORD (0 << 4)
40
41#define WC_BAUD_DIV_MASK (0xF)
42#define WC_BAUD_DR1 (0x0)
43#define WC_BAUD_DR2 (0x1)
44#define WC_BAUD_DR4 (0x2)
45#define WC_BAUD_DR8 (0x3)
46#define WC_BAUD_DR16 (0x4)
47#define WC_BAUD_DR32 (0x5)
48#define WC_BAUD_DR64 (0x6)
49#define WC_BAUD_DR128 (0x7)
50#define WC_BAUD_DR3 (0x8)
51#define WC_BAUD_DR6 (0x9)
52#define WC_BAUD_DR12 (0xA)
53#define WC_BAUD_DR24 (0xB)
54#define WC_BAUD_DR48 (0xC)
55#define WC_BAUD_DR96 (0xD)
56#define WC_BAUD_DR192 (0xE)
57#define WC_BAUD_DR384 (0xF)
58
59#endif
diff --git a/drivers/serial/msm_serial.c b/drivers/serial/msm_serial.c
deleted file mode 100644
index f8c816e7725d..000000000000
--- a/drivers/serial/msm_serial.c
+++ /dev/null
@@ -1,758 +0,0 @@
1/*
2 * drivers/serial/msm_serial.c - driver for msm7k serial device and console
3 *
4 * Copyright (C) 2007 Google, Inc.
5 * Author: Robert Love <rlove@google.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#if defined(CONFIG_SERIAL_MSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
18# define SUPPORT_SYSRQ
19#endif
20
21#include <linux/hrtimer.h>
22#include <linux/module.h>
23#include <linux/io.h>
24#include <linux/ioport.h>
25#include <linux/irq.h>
26#include <linux/init.h>
27#include <linux/console.h>
28#include <linux/tty.h>
29#include <linux/tty_flip.h>
30#include <linux/serial_core.h>
31#include <linux/serial.h>
32#include <linux/clk.h>
33#include <linux/platform_device.h>
34
35#include "msm_serial.h"
36
37struct msm_port {
38 struct uart_port uart;
39 char name[16];
40 struct clk *clk;
41 unsigned int imr;
42};
43
44static void msm_stop_tx(struct uart_port *port)
45{
46 struct msm_port *msm_port = UART_TO_MSM(port);
47
48 msm_port->imr &= ~UART_IMR_TXLEV;
49 msm_write(port, msm_port->imr, UART_IMR);
50}
51
52static void msm_start_tx(struct uart_port *port)
53{
54 struct msm_port *msm_port = UART_TO_MSM(port);
55
56 msm_port->imr |= UART_IMR_TXLEV;
57 msm_write(port, msm_port->imr, UART_IMR);
58}
59
60static void msm_stop_rx(struct uart_port *port)
61{
62 struct msm_port *msm_port = UART_TO_MSM(port);
63
64 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
65 msm_write(port, msm_port->imr, UART_IMR);
66}
67
68static void msm_enable_ms(struct uart_port *port)
69{
70 struct msm_port *msm_port = UART_TO_MSM(port);
71
72 msm_port->imr |= UART_IMR_DELTA_CTS;
73 msm_write(port, msm_port->imr, UART_IMR);
74}
75
76static void handle_rx(struct uart_port *port)
77{
78 struct tty_struct *tty = port->state->port.tty;
79 unsigned int sr;
80
81 /*
82 * Handle overrun. My understanding of the hardware is that overrun
83 * is not tied to the RX buffer, so we handle the case out of band.
84 */
85 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
86 port->icount.overrun++;
87 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
88 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
89 }
90
91 /* and now the main RX loop */
92 while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) {
93 unsigned int c;
94 char flag = TTY_NORMAL;
95
96 c = msm_read(port, UART_RF);
97
98 if (sr & UART_SR_RX_BREAK) {
99 port->icount.brk++;
100 if (uart_handle_break(port))
101 continue;
102 } else if (sr & UART_SR_PAR_FRAME_ERR) {
103 port->icount.frame++;
104 } else {
105 port->icount.rx++;
106 }
107
108 /* Mask conditions we're ignorning. */
109 sr &= port->read_status_mask;
110
111 if (sr & UART_SR_RX_BREAK) {
112 flag = TTY_BREAK;
113 } else if (sr & UART_SR_PAR_FRAME_ERR) {
114 flag = TTY_FRAME;
115 }
116
117 if (!uart_handle_sysrq_char(port, c))
118 tty_insert_flip_char(tty, c, flag);
119 }
120
121 tty_flip_buffer_push(tty);
122}
123
124static void handle_tx(struct uart_port *port)
125{
126 struct circ_buf *xmit = &port->state->xmit;
127 struct msm_port *msm_port = UART_TO_MSM(port);
128 int sent_tx;
129
130 if (port->x_char) {
131 msm_write(port, port->x_char, UART_TF);
132 port->icount.tx++;
133 port->x_char = 0;
134 }
135
136 while (msm_read(port, UART_SR) & UART_SR_TX_READY) {
137 if (uart_circ_empty(xmit)) {
138 /* disable tx interrupts */
139 msm_port->imr &= ~UART_IMR_TXLEV;
140 msm_write(port, msm_port->imr, UART_IMR);
141 break;
142 }
143
144 msm_write(port, xmit->buf[xmit->tail], UART_TF);
145
146 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
147 port->icount.tx++;
148 sent_tx = 1;
149 }
150
151 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
152 uart_write_wakeup(port);
153}
154
155static void handle_delta_cts(struct uart_port *port)
156{
157 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
158 port->icount.cts++;
159 wake_up_interruptible(&port->state->port.delta_msr_wait);
160}
161
162static irqreturn_t msm_irq(int irq, void *dev_id)
163{
164 struct uart_port *port = dev_id;
165 struct msm_port *msm_port = UART_TO_MSM(port);
166 unsigned int misr;
167
168 spin_lock(&port->lock);
169 misr = msm_read(port, UART_MISR);
170 msm_write(port, 0, UART_IMR); /* disable interrupt */
171
172 if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE))
173 handle_rx(port);
174 if (misr & UART_IMR_TXLEV)
175 handle_tx(port);
176 if (misr & UART_IMR_DELTA_CTS)
177 handle_delta_cts(port);
178
179 msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */
180 spin_unlock(&port->lock);
181
182 return IRQ_HANDLED;
183}
184
185static unsigned int msm_tx_empty(struct uart_port *port)
186{
187 return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
188}
189
190static unsigned int msm_get_mctrl(struct uart_port *port)
191{
192 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
193}
194
195static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
196{
197 unsigned int mr;
198
199 mr = msm_read(port, UART_MR1);
200
201 if (!(mctrl & TIOCM_RTS)) {
202 mr &= ~UART_MR1_RX_RDY_CTL;
203 msm_write(port, mr, UART_MR1);
204 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
205 } else {
206 mr |= UART_MR1_RX_RDY_CTL;
207 msm_write(port, mr, UART_MR1);
208 }
209}
210
211static void msm_break_ctl(struct uart_port *port, int break_ctl)
212{
213 if (break_ctl)
214 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);
215 else
216 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);
217}
218
219static int msm_set_baud_rate(struct uart_port *port, unsigned int baud)
220{
221 unsigned int baud_code, rxstale, watermark;
222
223 switch (baud) {
224 case 300:
225 baud_code = UART_CSR_300;
226 rxstale = 1;
227 break;
228 case 600:
229 baud_code = UART_CSR_600;
230 rxstale = 1;
231 break;
232 case 1200:
233 baud_code = UART_CSR_1200;
234 rxstale = 1;
235 break;
236 case 2400:
237 baud_code = UART_CSR_2400;
238 rxstale = 1;
239 break;
240 case 4800:
241 baud_code = UART_CSR_4800;
242 rxstale = 1;
243 break;
244 case 9600:
245 baud_code = UART_CSR_9600;
246 rxstale = 2;
247 break;
248 case 14400:
249 baud_code = UART_CSR_14400;
250 rxstale = 3;
251 break;
252 case 19200:
253 baud_code = UART_CSR_19200;
254 rxstale = 4;
255 break;
256 case 28800:
257 baud_code = UART_CSR_28800;
258 rxstale = 6;
259 break;
260 case 38400:
261 baud_code = UART_CSR_38400;
262 rxstale = 8;
263 break;
264 case 57600:
265 baud_code = UART_CSR_57600;
266 rxstale = 16;
267 break;
268 case 115200:
269 default:
270 baud_code = UART_CSR_115200;
271 baud = 115200;
272 rxstale = 31;
273 break;
274 }
275
276 msm_write(port, baud_code, UART_CSR);
277
278 /* RX stale watermark */
279 watermark = UART_IPR_STALE_LSB & rxstale;
280 watermark |= UART_IPR_RXSTALE_LAST;
281 watermark |= UART_IPR_STALE_TIMEOUT_MSB & (rxstale << 2);
282 msm_write(port, watermark, UART_IPR);
283
284 /* set RX watermark */
285 watermark = (port->fifosize * 3) / 4;
286 msm_write(port, watermark, UART_RFWR);
287
288 /* set TX watermark */
289 msm_write(port, 10, UART_TFWR);
290
291 return baud;
292}
293
294static void msm_reset(struct uart_port *port)
295{
296 /* reset everything */
297 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
298 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
299 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
300 msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
301 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
302 msm_write(port, UART_CR_CMD_SET_RFR, UART_CR);
303}
304
305static void msm_init_clock(struct uart_port *port)
306{
307 struct msm_port *msm_port = UART_TO_MSM(port);
308
309 clk_enable(msm_port->clk);
310 msm_serial_set_mnd_regs(port);
311}
312
313static int msm_startup(struct uart_port *port)
314{
315 struct msm_port *msm_port = UART_TO_MSM(port);
316 unsigned int data, rfr_level;
317 int ret;
318
319 snprintf(msm_port->name, sizeof(msm_port->name),
320 "msm_serial%d", port->line);
321
322 ret = request_irq(port->irq, msm_irq, IRQF_TRIGGER_HIGH,
323 msm_port->name, port);
324 if (unlikely(ret))
325 return ret;
326
327 msm_init_clock(port);
328
329 if (likely(port->fifosize > 12))
330 rfr_level = port->fifosize - 12;
331 else
332 rfr_level = port->fifosize;
333
334 /* set automatic RFR level */
335 data = msm_read(port, UART_MR1);
336 data &= ~UART_MR1_AUTO_RFR_LEVEL1;
337 data &= ~UART_MR1_AUTO_RFR_LEVEL0;
338 data |= UART_MR1_AUTO_RFR_LEVEL1 & (rfr_level << 2);
339 data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
340 msm_write(port, data, UART_MR1);
341
342 /* make sure that RXSTALE count is non-zero */
343 data = msm_read(port, UART_IPR);
344 if (unlikely(!data)) {
345 data |= UART_IPR_RXSTALE_LAST;
346 data |= UART_IPR_STALE_LSB;
347 msm_write(port, data, UART_IPR);
348 }
349
350 msm_reset(port);
351
352 msm_write(port, 0x05, UART_CR); /* enable TX & RX */
353
354 /* turn on RX and CTS interrupts */
355 msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE |
356 UART_IMR_CURRENT_CTS;
357 msm_write(port, msm_port->imr, UART_IMR);
358
359 return 0;
360}
361
362static void msm_shutdown(struct uart_port *port)
363{
364 struct msm_port *msm_port = UART_TO_MSM(port);
365
366 msm_port->imr = 0;
367 msm_write(port, 0, UART_IMR); /* disable interrupts */
368
369 clk_disable(msm_port->clk);
370
371 free_irq(port->irq, port);
372}
373
374static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
375 struct ktermios *old)
376{
377 unsigned long flags;
378 unsigned int baud, mr;
379
380 spin_lock_irqsave(&port->lock, flags);
381
382 /* calculate and set baud rate */
383 baud = uart_get_baud_rate(port, termios, old, 300, 115200);
384 baud = msm_set_baud_rate(port, baud);
385 if (tty_termios_baud_rate(termios))
386 tty_termios_encode_baud_rate(termios, baud, baud);
387
388 /* calculate parity */
389 mr = msm_read(port, UART_MR2);
390 mr &= ~UART_MR2_PARITY_MODE;
391 if (termios->c_cflag & PARENB) {
392 if (termios->c_cflag & PARODD)
393 mr |= UART_MR2_PARITY_MODE_ODD;
394 else if (termios->c_cflag & CMSPAR)
395 mr |= UART_MR2_PARITY_MODE_SPACE;
396 else
397 mr |= UART_MR2_PARITY_MODE_EVEN;
398 }
399
400 /* calculate bits per char */
401 mr &= ~UART_MR2_BITS_PER_CHAR;
402 switch (termios->c_cflag & CSIZE) {
403 case CS5:
404 mr |= UART_MR2_BITS_PER_CHAR_5;
405 break;
406 case CS6:
407 mr |= UART_MR2_BITS_PER_CHAR_6;
408 break;
409 case CS7:
410 mr |= UART_MR2_BITS_PER_CHAR_7;
411 break;
412 case CS8:
413 default:
414 mr |= UART_MR2_BITS_PER_CHAR_8;
415 break;
416 }
417
418 /* calculate stop bits */
419 mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO);
420 if (termios->c_cflag & CSTOPB)
421 mr |= UART_MR2_STOP_BIT_LEN_TWO;
422 else
423 mr |= UART_MR2_STOP_BIT_LEN_ONE;
424
425 /* set parity, bits per char, and stop bit */
426 msm_write(port, mr, UART_MR2);
427
428 /* calculate and set hardware flow control */
429 mr = msm_read(port, UART_MR1);
430 mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL);
431 if (termios->c_cflag & CRTSCTS) {
432 mr |= UART_MR1_CTS_CTL;
433 mr |= UART_MR1_RX_RDY_CTL;
434 }
435 msm_write(port, mr, UART_MR1);
436
437 /* Configure status bits to ignore based on termio flags. */
438 port->read_status_mask = 0;
439 if (termios->c_iflag & INPCK)
440 port->read_status_mask |= UART_SR_PAR_FRAME_ERR;
441 if (termios->c_iflag & (BRKINT | PARMRK))
442 port->read_status_mask |= UART_SR_RX_BREAK;
443
444 uart_update_timeout(port, termios->c_cflag, baud);
445
446 spin_unlock_irqrestore(&port->lock, flags);
447}
448
449static const char *msm_type(struct uart_port *port)
450{
451 return "MSM";
452}
453
454static void msm_release_port(struct uart_port *port)
455{
456 struct platform_device *pdev = to_platform_device(port->dev);
457 struct resource *resource;
458 resource_size_t size;
459
460 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
461 if (unlikely(!resource))
462 return;
463 size = resource->end - resource->start + 1;
464
465 release_mem_region(port->mapbase, size);
466 iounmap(port->membase);
467 port->membase = NULL;
468}
469
470static int msm_request_port(struct uart_port *port)
471{
472 struct platform_device *pdev = to_platform_device(port->dev);
473 struct resource *resource;
474 resource_size_t size;
475
476 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
477 if (unlikely(!resource))
478 return -ENXIO;
479 size = resource->end - resource->start + 1;
480
481 if (unlikely(!request_mem_region(port->mapbase, size, "msm_serial")))
482 return -EBUSY;
483
484 port->membase = ioremap(port->mapbase, size);
485 if (!port->membase) {
486 release_mem_region(port->mapbase, size);
487 return -EBUSY;
488 }
489
490 return 0;
491}
492
493static void msm_config_port(struct uart_port *port, int flags)
494{
495 if (flags & UART_CONFIG_TYPE) {
496 port->type = PORT_MSM;
497 msm_request_port(port);
498 }
499}
500
501static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
502{
503 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
504 return -EINVAL;
505 if (unlikely(port->irq != ser->irq))
506 return -EINVAL;
507 return 0;
508}
509
510static void msm_power(struct uart_port *port, unsigned int state,
511 unsigned int oldstate)
512{
513 struct msm_port *msm_port = UART_TO_MSM(port);
514
515 switch (state) {
516 case 0:
517 clk_enable(msm_port->clk);
518 break;
519 case 3:
520 clk_disable(msm_port->clk);
521 break;
522 default:
523 printk(KERN_ERR "msm_serial: Unknown PM state %d\n", state);
524 }
525}
526
527static struct uart_ops msm_uart_pops = {
528 .tx_empty = msm_tx_empty,
529 .set_mctrl = msm_set_mctrl,
530 .get_mctrl = msm_get_mctrl,
531 .stop_tx = msm_stop_tx,
532 .start_tx = msm_start_tx,
533 .stop_rx = msm_stop_rx,
534 .enable_ms = msm_enable_ms,
535 .break_ctl = msm_break_ctl,
536 .startup = msm_startup,
537 .shutdown = msm_shutdown,
538 .set_termios = msm_set_termios,
539 .type = msm_type,
540 .release_port = msm_release_port,
541 .request_port = msm_request_port,
542 .config_port = msm_config_port,
543 .verify_port = msm_verify_port,
544 .pm = msm_power,
545};
546
547static struct msm_port msm_uart_ports[] = {
548 {
549 .uart = {
550 .iotype = UPIO_MEM,
551 .ops = &msm_uart_pops,
552 .flags = UPF_BOOT_AUTOCONF,
553 .fifosize = 512,
554 .line = 0,
555 },
556 },
557 {
558 .uart = {
559 .iotype = UPIO_MEM,
560 .ops = &msm_uart_pops,
561 .flags = UPF_BOOT_AUTOCONF,
562 .fifosize = 512,
563 .line = 1,
564 },
565 },
566 {
567 .uart = {
568 .iotype = UPIO_MEM,
569 .ops = &msm_uart_pops,
570 .flags = UPF_BOOT_AUTOCONF,
571 .fifosize = 64,
572 .line = 2,
573 },
574 },
575};
576
577#define UART_NR ARRAY_SIZE(msm_uart_ports)
578
579static inline struct uart_port *get_port_from_line(unsigned int line)
580{
581 return &msm_uart_ports[line].uart;
582}
583
584#ifdef CONFIG_SERIAL_MSM_CONSOLE
585
586static void msm_console_putchar(struct uart_port *port, int c)
587{
588 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
589 ;
590 msm_write(port, c, UART_TF);
591}
592
593static void msm_console_write(struct console *co, const char *s,
594 unsigned int count)
595{
596 struct uart_port *port;
597 struct msm_port *msm_port;
598
599 BUG_ON(co->index < 0 || co->index >= UART_NR);
600
601 port = get_port_from_line(co->index);
602 msm_port = UART_TO_MSM(port);
603
604 spin_lock(&port->lock);
605 uart_console_write(port, s, count, msm_console_putchar);
606 spin_unlock(&port->lock);
607}
608
609static int __init msm_console_setup(struct console *co, char *options)
610{
611 struct uart_port *port;
612 int baud, flow, bits, parity;
613
614 if (unlikely(co->index >= UART_NR || co->index < 0))
615 return -ENXIO;
616
617 port = get_port_from_line(co->index);
618
619 if (unlikely(!port->membase))
620 return -ENXIO;
621
622 port->cons = co;
623
624 msm_init_clock(port);
625
626 if (options)
627 uart_parse_options(options, &baud, &parity, &bits, &flow);
628
629 bits = 8;
630 parity = 'n';
631 flow = 'n';
632 msm_write(port, UART_MR2_BITS_PER_CHAR_8 | UART_MR2_STOP_BIT_LEN_ONE,
633 UART_MR2); /* 8N1 */
634
635 if (baud < 300 || baud > 115200)
636 baud = 115200;
637 msm_set_baud_rate(port, baud);
638
639 msm_reset(port);
640
641 printk(KERN_INFO "msm_serial: console setup on port #%d\n", port->line);
642
643 return uart_set_options(port, co, baud, parity, bits, flow);
644}
645
646static struct uart_driver msm_uart_driver;
647
648static struct console msm_console = {
649 .name = "ttyMSM",
650 .write = msm_console_write,
651 .device = uart_console_device,
652 .setup = msm_console_setup,
653 .flags = CON_PRINTBUFFER,
654 .index = -1,
655 .data = &msm_uart_driver,
656};
657
658#define MSM_CONSOLE (&msm_console)
659
660#else
661#define MSM_CONSOLE NULL
662#endif
663
664static struct uart_driver msm_uart_driver = {
665 .owner = THIS_MODULE,
666 .driver_name = "msm_serial",
667 .dev_name = "ttyMSM",
668 .nr = UART_NR,
669 .cons = MSM_CONSOLE,
670};
671
672static int __init msm_serial_probe(struct platform_device *pdev)
673{
674 struct msm_port *msm_port;
675 struct resource *resource;
676 struct uart_port *port;
677 int irq;
678
679 if (unlikely(pdev->id < 0 || pdev->id >= UART_NR))
680 return -ENXIO;
681
682 printk(KERN_INFO "msm_serial: detected port #%d\n", pdev->id);
683
684 port = get_port_from_line(pdev->id);
685 port->dev = &pdev->dev;
686 msm_port = UART_TO_MSM(port);
687
688 msm_port->clk = clk_get(&pdev->dev, "uart_clk");
689 if (unlikely(IS_ERR(msm_port->clk)))
690 return PTR_ERR(msm_port->clk);
691 port->uartclk = clk_get_rate(msm_port->clk);
692 printk(KERN_INFO "uartclk = %d\n", port->uartclk);
693
694
695 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
696 if (unlikely(!resource))
697 return -ENXIO;
698 port->mapbase = resource->start;
699
700 irq = platform_get_irq(pdev, 0);
701 if (unlikely(irq < 0))
702 return -ENXIO;
703 port->irq = irq;
704
705 platform_set_drvdata(pdev, port);
706
707 return uart_add_one_port(&msm_uart_driver, port);
708}
709
710static int __devexit msm_serial_remove(struct platform_device *pdev)
711{
712 struct msm_port *msm_port = platform_get_drvdata(pdev);
713
714 clk_put(msm_port->clk);
715
716 return 0;
717}
718
719static struct platform_driver msm_platform_driver = {
720 .remove = msm_serial_remove,
721 .driver = {
722 .name = "msm_serial",
723 .owner = THIS_MODULE,
724 },
725};
726
727static int __init msm_serial_init(void)
728{
729 int ret;
730
731 ret = uart_register_driver(&msm_uart_driver);
732 if (unlikely(ret))
733 return ret;
734
735 ret = platform_driver_probe(&msm_platform_driver, msm_serial_probe);
736 if (unlikely(ret))
737 uart_unregister_driver(&msm_uart_driver);
738
739 printk(KERN_INFO "msm_serial: driver initialized\n");
740
741 return ret;
742}
743
744static void __exit msm_serial_exit(void)
745{
746#ifdef CONFIG_SERIAL_MSM_CONSOLE
747 unregister_console(&msm_console);
748#endif
749 platform_driver_unregister(&msm_platform_driver);
750 uart_unregister_driver(&msm_uart_driver);
751}
752
753module_init(msm_serial_init);
754module_exit(msm_serial_exit);
755
756MODULE_AUTHOR("Robert Love <rlove@google.com>");
757MODULE_DESCRIPTION("Driver for msm7x serial device");
758MODULE_LICENSE("GPL");
diff --git a/drivers/serial/msm_serial.h b/drivers/serial/msm_serial.h
deleted file mode 100644
index f6ca9ca79e98..000000000000
--- a/drivers/serial/msm_serial.h
+++ /dev/null
@@ -1,173 +0,0 @@
1/*
2 * drivers/serial/msm_serial.h
3 *
4 * Copyright (C) 2007 Google, Inc.
5 * Author: Robert Love <rlove@google.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef __DRIVERS_SERIAL_MSM_SERIAL_H
18#define __DRIVERS_SERIAL_MSM_SERIAL_H
19
20#define UART_MR1 0x0000
21
22#define UART_MR1_AUTO_RFR_LEVEL0 0x3F
23#define UART_MR1_AUTO_RFR_LEVEL1 0x3FF00
24#define UART_MR1_RX_RDY_CTL (1 << 7)
25#define UART_MR1_CTS_CTL (1 << 6)
26
27#define UART_MR2 0x0004
28#define UART_MR2_ERROR_MODE (1 << 6)
29#define UART_MR2_BITS_PER_CHAR 0x30
30#define UART_MR2_BITS_PER_CHAR_5 (0x0 << 4)
31#define UART_MR2_BITS_PER_CHAR_6 (0x1 << 4)
32#define UART_MR2_BITS_PER_CHAR_7 (0x2 << 4)
33#define UART_MR2_BITS_PER_CHAR_8 (0x3 << 4)
34#define UART_MR2_STOP_BIT_LEN_ONE (0x1 << 2)
35#define UART_MR2_STOP_BIT_LEN_TWO (0x3 << 2)
36#define UART_MR2_PARITY_MODE_NONE 0x0
37#define UART_MR2_PARITY_MODE_ODD 0x1
38#define UART_MR2_PARITY_MODE_EVEN 0x2
39#define UART_MR2_PARITY_MODE_SPACE 0x3
40#define UART_MR2_PARITY_MODE 0x3
41
42#define UART_CSR 0x0008
43#define UART_CSR_115200 0xFF
44#define UART_CSR_57600 0xEE
45#define UART_CSR_38400 0xDD
46#define UART_CSR_28800 0xCC
47#define UART_CSR_19200 0xBB
48#define UART_CSR_14400 0xAA
49#define UART_CSR_9600 0x99
50#define UART_CSR_4800 0x77
51#define UART_CSR_2400 0x55
52#define UART_CSR_1200 0x44
53#define UART_CSR_600 0x33
54#define UART_CSR_300 0x22
55
56#define UART_TF 0x000C
57
58#define UART_CR 0x0010
59#define UART_CR_CMD_NULL (0 << 4)
60#define UART_CR_CMD_RESET_RX (1 << 4)
61#define UART_CR_CMD_RESET_TX (2 << 4)
62#define UART_CR_CMD_RESET_ERR (3 << 4)
63#define UART_CR_CMD_RESET_BREAK_INT (4 << 4)
64#define UART_CR_CMD_START_BREAK (5 << 4)
65#define UART_CR_CMD_STOP_BREAK (6 << 4)
66#define UART_CR_CMD_RESET_CTS (7 << 4)
67#define UART_CR_CMD_PACKET_MODE (9 << 4)
68#define UART_CR_CMD_MODE_RESET (12 << 4)
69#define UART_CR_CMD_SET_RFR (13 << 4)
70#define UART_CR_CMD_RESET_RFR (14 << 4)
71#define UART_CR_TX_DISABLE (1 << 3)
72#define UART_CR_TX_ENABLE (1 << 3)
73#define UART_CR_RX_DISABLE (1 << 3)
74#define UART_CR_RX_ENABLE (1 << 3)
75
76#define UART_IMR 0x0014
77#define UART_IMR_TXLEV (1 << 0)
78#define UART_IMR_RXSTALE (1 << 3)
79#define UART_IMR_RXLEV (1 << 4)
80#define UART_IMR_DELTA_CTS (1 << 5)
81#define UART_IMR_CURRENT_CTS (1 << 6)
82
83#define UART_IPR_RXSTALE_LAST 0x20
84#define UART_IPR_STALE_LSB 0x1F
85#define UART_IPR_STALE_TIMEOUT_MSB 0x3FF80
86
87#define UART_IPR 0x0018
88#define UART_TFWR 0x001C
89#define UART_RFWR 0x0020
90#define UART_HCR 0x0024
91
92#define UART_MREG 0x0028
93#define UART_NREG 0x002C
94#define UART_DREG 0x0030
95#define UART_MNDREG 0x0034
96#define UART_IRDA 0x0038
97#define UART_MISR_MODE 0x0040
98#define UART_MISR_RESET 0x0044
99#define UART_MISR_EXPORT 0x0048
100#define UART_MISR_VAL 0x004C
101#define UART_TEST_CTRL 0x0050
102
103#define UART_SR 0x0008
104#define UART_SR_HUNT_CHAR (1 << 7)
105#define UART_SR_RX_BREAK (1 << 6)
106#define UART_SR_PAR_FRAME_ERR (1 << 5)
107#define UART_SR_OVERRUN (1 << 4)
108#define UART_SR_TX_EMPTY (1 << 3)
109#define UART_SR_TX_READY (1 << 2)
110#define UART_SR_RX_FULL (1 << 1)
111#define UART_SR_RX_READY (1 << 0)
112
113#define UART_RF 0x000C
114#define UART_MISR 0x0010
115#define UART_ISR 0x0014
116
117#define UART_TO_MSM(uart_port) ((struct msm_port *) uart_port)
118
119static inline
120void msm_write(struct uart_port *port, unsigned int val, unsigned int off)
121{
122 __raw_writel(val, port->membase + off);
123}
124
125static inline
126unsigned int msm_read(struct uart_port *port, unsigned int off)
127{
128 return __raw_readl(port->membase + off);
129}
130
131/*
132 * Setup the MND registers to use the TCXO clock.
133 */
134static inline void msm_serial_set_mnd_regs_tcxo(struct uart_port *port)
135{
136 msm_write(port, 0x06, UART_MREG);
137 msm_write(port, 0xF1, UART_NREG);
138 msm_write(port, 0x0F, UART_DREG);
139 msm_write(port, 0x1A, UART_MNDREG);
140}
141
142/*
143 * Setup the MND registers to use the TCXO clock divided by 4.
144 */
145static inline void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port)
146{
147 msm_write(port, 0x18, UART_MREG);
148 msm_write(port, 0xF6, UART_NREG);
149 msm_write(port, 0x0F, UART_DREG);
150 msm_write(port, 0x0A, UART_MNDREG);
151}
152
153static inline
154void msm_serial_set_mnd_regs_from_uartclk(struct uart_port *port)
155{
156 if (port->uartclk == 19200000)
157 msm_serial_set_mnd_regs_tcxo(port);
158 else
159 msm_serial_set_mnd_regs_tcxoby4(port);
160}
161
162/*
163 * TROUT has a specific defect that makes it report it's uartclk
164 * as 19.2Mhz (TCXO) when it's actually 4.8Mhz (TCXO/4). This special
165 * cases TROUT to use the right clock.
166 */
167#ifdef CONFIG_MACH_TROUT
168#define msm_serial_set_mnd_regs msm_serial_set_mnd_regs_tcxoby4
169#else
170#define msm_serial_set_mnd_regs msm_serial_set_mnd_regs_from_uartclk
171#endif
172
173#endif /* __DRIVERS_SERIAL_MSM_SERIAL_H */
diff --git a/drivers/serial/mux.c b/drivers/serial/mux.c
deleted file mode 100644
index 9711e06a8374..000000000000
--- a/drivers/serial/mux.c
+++ /dev/null
@@ -1,633 +0,0 @@
1/*
2** mux.c:
3** serial driver for the Mux console found in some PA-RISC servers.
4**
5** (c) Copyright 2002 Ryan Bradetich
6** (c) Copyright 2002 Hewlett-Packard Company
7**
8** This program is free software; you can redistribute it and/or modify
9** it under the terms of the GNU General Public License as published by
10** the Free Software Foundation; either version 2 of the License, or
11** (at your option) any later version.
12**
13** This Driver currently only supports the console (port 0) on the MUX.
14** Additional work will be needed on this driver to enable the full
15** functionality of the MUX.
16**
17*/
18
19#include <linux/module.h>
20#include <linux/tty.h>
21#include <linux/ioport.h>
22#include <linux/init.h>
23#include <linux/serial.h>
24#include <linux/console.h>
25#include <linux/delay.h> /* for udelay */
26#include <linux/device.h>
27#include <asm/io.h>
28#include <asm/irq.h>
29#include <asm/parisc-device.h>
30
31#ifdef CONFIG_MAGIC_SYSRQ
32#include <linux/sysrq.h>
33#define SUPPORT_SYSRQ
34#endif
35
36#include <linux/serial_core.h>
37
38#define MUX_OFFSET 0x800
39#define MUX_LINE_OFFSET 0x80
40
41#define MUX_FIFO_SIZE 255
42#define MUX_POLL_DELAY (30 * HZ / 1000)
43
44#define IO_DATA_REG_OFFSET 0x3c
45#define IO_DCOUNT_REG_OFFSET 0x40
46
47#define MUX_EOFIFO(status) ((status & 0xF000) == 0xF000)
48#define MUX_STATUS(status) ((status & 0xF000) == 0x8000)
49#define MUX_BREAK(status) ((status & 0xF000) == 0x2000)
50
51#define MUX_NR 256
52static unsigned int port_cnt __read_mostly;
53struct mux_port {
54 struct uart_port port;
55 int enabled;
56};
57static struct mux_port mux_ports[MUX_NR];
58
59static struct uart_driver mux_driver = {
60 .owner = THIS_MODULE,
61 .driver_name = "ttyB",
62 .dev_name = "ttyB",
63 .major = MUX_MAJOR,
64 .minor = 0,
65 .nr = MUX_NR,
66};
67
68static struct timer_list mux_timer;
69
70#define UART_PUT_CHAR(p, c) __raw_writel((c), (p)->membase + IO_DATA_REG_OFFSET)
71#define UART_GET_FIFO_CNT(p) __raw_readl((p)->membase + IO_DCOUNT_REG_OFFSET)
72
73/**
74 * get_mux_port_count - Get the number of available ports on the Mux.
75 * @dev: The parisc device.
76 *
77 * This function is used to determine the number of ports the Mux
78 * supports. The IODC data reports the number of ports the Mux
79 * can support, but there are cases where not all the Mux ports
80 * are connected. This function can override the IODC and
81 * return the true port count.
82 */
83static int __init get_mux_port_count(struct parisc_device *dev)
84{
85 int status;
86 u8 iodc_data[32];
87 unsigned long bytecnt;
88
89 /* If this is the built-in Mux for the K-Class (Eole CAP/MUX),
90 * we only need to allocate resources for 1 port since the
91 * other 7 ports are not connected.
92 */
93 if(dev->id.hversion == 0x15)
94 return 1;
95
96 status = pdc_iodc_read(&bytecnt, dev->hpa.start, 0, iodc_data, 32);
97 BUG_ON(status != PDC_OK);
98
99 /* Return the number of ports specified in the iodc data. */
100 return ((((iodc_data)[4] & 0xf0) >> 4) * 8) + 8;
101}
102
103/**
104 * mux_tx_empty - Check if the transmitter fifo is empty.
105 * @port: Ptr to the uart_port.
106 *
107 * This function test if the transmitter fifo for the port
108 * described by 'port' is empty. If it is empty, this function
109 * should return TIOCSER_TEMT, otherwise return 0.
110 */
111static unsigned int mux_tx_empty(struct uart_port *port)
112{
113 return UART_GET_FIFO_CNT(port) ? 0 : TIOCSER_TEMT;
114}
115
116/**
117 * mux_set_mctrl - Set the current state of the modem control inputs.
118 * @ports: Ptr to the uart_port.
119 * @mctrl: Modem control bits.
120 *
121 * The Serial MUX does not support CTS, DCD or DSR so this function
122 * is ignored.
123 */
124static void mux_set_mctrl(struct uart_port *port, unsigned int mctrl)
125{
126}
127
128/**
129 * mux_get_mctrl - Returns the current state of modem control inputs.
130 * @port: Ptr to the uart_port.
131 *
132 * The Serial MUX does not support CTS, DCD or DSR so these lines are
133 * treated as permanently active.
134 */
135static unsigned int mux_get_mctrl(struct uart_port *port)
136{
137 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
138}
139
140/**
141 * mux_stop_tx - Stop transmitting characters.
142 * @port: Ptr to the uart_port.
143 *
144 * The Serial MUX does not support this function.
145 */
146static void mux_stop_tx(struct uart_port *port)
147{
148}
149
150/**
151 * mux_start_tx - Start transmitting characters.
152 * @port: Ptr to the uart_port.
153 *
154 * The Serial Mux does not support this function.
155 */
156static void mux_start_tx(struct uart_port *port)
157{
158}
159
160/**
161 * mux_stop_rx - Stop receiving characters.
162 * @port: Ptr to the uart_port.
163 *
164 * The Serial Mux does not support this function.
165 */
166static void mux_stop_rx(struct uart_port *port)
167{
168}
169
170/**
171 * mux_enable_ms - Enable modum status interrupts.
172 * @port: Ptr to the uart_port.
173 *
174 * The Serial Mux does not support this function.
175 */
176static void mux_enable_ms(struct uart_port *port)
177{
178}
179
180/**
181 * mux_break_ctl - Control the transmitssion of a break signal.
182 * @port: Ptr to the uart_port.
183 * @break_state: Raise/Lower the break signal.
184 *
185 * The Serial Mux does not support this function.
186 */
187static void mux_break_ctl(struct uart_port *port, int break_state)
188{
189}
190
191/**
192 * mux_write - Write chars to the mux fifo.
193 * @port: Ptr to the uart_port.
194 *
195 * This function writes all the data from the uart buffer to
196 * the mux fifo.
197 */
198static void mux_write(struct uart_port *port)
199{
200 int count;
201 struct circ_buf *xmit = &port->state->xmit;
202
203 if(port->x_char) {
204 UART_PUT_CHAR(port, port->x_char);
205 port->icount.tx++;
206 port->x_char = 0;
207 return;
208 }
209
210 if(uart_circ_empty(xmit) || uart_tx_stopped(port)) {
211 mux_stop_tx(port);
212 return;
213 }
214
215 count = (port->fifosize) - UART_GET_FIFO_CNT(port);
216 do {
217 UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
218 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
219 port->icount.tx++;
220 if(uart_circ_empty(xmit))
221 break;
222
223 } while(--count > 0);
224
225 while(UART_GET_FIFO_CNT(port))
226 udelay(1);
227
228 if(uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
229 uart_write_wakeup(port);
230
231 if (uart_circ_empty(xmit))
232 mux_stop_tx(port);
233}
234
235/**
236 * mux_read - Read chars from the mux fifo.
237 * @port: Ptr to the uart_port.
238 *
239 * This reads all available data from the mux's fifo and pushes
240 * the data to the tty layer.
241 */
242static void mux_read(struct uart_port *port)
243{
244 int data;
245 struct tty_struct *tty = port->state->port.tty;
246 __u32 start_count = port->icount.rx;
247
248 while(1) {
249 data = __raw_readl(port->membase + IO_DATA_REG_OFFSET);
250
251 if (MUX_STATUS(data))
252 continue;
253
254 if (MUX_EOFIFO(data))
255 break;
256
257 port->icount.rx++;
258
259 if (MUX_BREAK(data)) {
260 port->icount.brk++;
261 if(uart_handle_break(port))
262 continue;
263 }
264
265 if (uart_handle_sysrq_char(port, data & 0xffu))
266 continue;
267
268 tty_insert_flip_char(tty, data & 0xFF, TTY_NORMAL);
269 }
270
271 if (start_count != port->icount.rx) {
272 tty_flip_buffer_push(tty);
273 }
274}
275
276/**
277 * mux_startup - Initialize the port.
278 * @port: Ptr to the uart_port.
279 *
280 * Grab any resources needed for this port and start the
281 * mux timer.
282 */
283static int mux_startup(struct uart_port *port)
284{
285 mux_ports[port->line].enabled = 1;
286 return 0;
287}
288
289/**
290 * mux_shutdown - Disable the port.
291 * @port: Ptr to the uart_port.
292 *
293 * Release any resources needed for the port.
294 */
295static void mux_shutdown(struct uart_port *port)
296{
297 mux_ports[port->line].enabled = 0;
298}
299
300/**
301 * mux_set_termios - Chane port parameters.
302 * @port: Ptr to the uart_port.
303 * @termios: new termios settings.
304 * @old: old termios settings.
305 *
306 * The Serial Mux does not support this function.
307 */
308static void
309mux_set_termios(struct uart_port *port, struct ktermios *termios,
310 struct ktermios *old)
311{
312}
313
314/**
315 * mux_type - Describe the port.
316 * @port: Ptr to the uart_port.
317 *
318 * Return a pointer to a string constant describing the
319 * specified port.
320 */
321static const char *mux_type(struct uart_port *port)
322{
323 return "Mux";
324}
325
326/**
327 * mux_release_port - Release memory and IO regions.
328 * @port: Ptr to the uart_port.
329 *
330 * Release any memory and IO region resources currently in use by
331 * the port.
332 */
333static void mux_release_port(struct uart_port *port)
334{
335}
336
337/**
338 * mux_request_port - Request memory and IO regions.
339 * @port: Ptr to the uart_port.
340 *
341 * Request any memory and IO region resources required by the port.
342 * If any fail, no resources should be registered when this function
343 * returns, and it should return -EBUSY on failure.
344 */
345static int mux_request_port(struct uart_port *port)
346{
347 return 0;
348}
349
350/**
351 * mux_config_port - Perform port autoconfiguration.
352 * @port: Ptr to the uart_port.
353 * @type: Bitmask of required configurations.
354 *
355 * Perform any autoconfiguration steps for the port. This function is
356 * called if the UPF_BOOT_AUTOCONF flag is specified for the port.
357 * [Note: This is required for now because of a bug in the Serial core.
358 * rmk has already submitted a patch to linus, should be available for
359 * 2.5.47.]
360 */
361static void mux_config_port(struct uart_port *port, int type)
362{
363 port->type = PORT_MUX;
364}
365
366/**
367 * mux_verify_port - Verify the port information.
368 * @port: Ptr to the uart_port.
369 * @ser: Ptr to the serial information.
370 *
371 * Verify the new serial port information contained within serinfo is
372 * suitable for this port type.
373 */
374static int mux_verify_port(struct uart_port *port, struct serial_struct *ser)
375{
376 if(port->membase == NULL)
377 return -EINVAL;
378
379 return 0;
380}
381
382/**
383 * mux_drv_poll - Mux poll function.
384 * @unused: Unused variable
385 *
386 * This function periodically polls the Serial MUX to check for new data.
387 */
388static void mux_poll(unsigned long unused)
389{
390 int i;
391
392 for(i = 0; i < port_cnt; ++i) {
393 if(!mux_ports[i].enabled)
394 continue;
395
396 mux_read(&mux_ports[i].port);
397 mux_write(&mux_ports[i].port);
398 }
399
400 mod_timer(&mux_timer, jiffies + MUX_POLL_DELAY);
401}
402
403
404#ifdef CONFIG_SERIAL_MUX_CONSOLE
405static void mux_console_write(struct console *co, const char *s, unsigned count)
406{
407 /* Wait until the FIFO drains. */
408 while(UART_GET_FIFO_CNT(&mux_ports[0].port))
409 udelay(1);
410
411 while(count--) {
412 if(*s == '\n') {
413 UART_PUT_CHAR(&mux_ports[0].port, '\r');
414 }
415 UART_PUT_CHAR(&mux_ports[0].port, *s++);
416 }
417
418}
419
420static int mux_console_setup(struct console *co, char *options)
421{
422 return 0;
423}
424
425struct tty_driver *mux_console_device(struct console *co, int *index)
426{
427 *index = co->index;
428 return mux_driver.tty_driver;
429}
430
431static struct console mux_console = {
432 .name = "ttyB",
433 .write = mux_console_write,
434 .device = mux_console_device,
435 .setup = mux_console_setup,
436 .flags = CON_ENABLED | CON_PRINTBUFFER,
437 .index = 0,
438};
439
440#define MUX_CONSOLE &mux_console
441#else
442#define MUX_CONSOLE NULL
443#endif
444
445static struct uart_ops mux_pops = {
446 .tx_empty = mux_tx_empty,
447 .set_mctrl = mux_set_mctrl,
448 .get_mctrl = mux_get_mctrl,
449 .stop_tx = mux_stop_tx,
450 .start_tx = mux_start_tx,
451 .stop_rx = mux_stop_rx,
452 .enable_ms = mux_enable_ms,
453 .break_ctl = mux_break_ctl,
454 .startup = mux_startup,
455 .shutdown = mux_shutdown,
456 .set_termios = mux_set_termios,
457 .type = mux_type,
458 .release_port = mux_release_port,
459 .request_port = mux_request_port,
460 .config_port = mux_config_port,
461 .verify_port = mux_verify_port,
462};
463
464/**
465 * mux_probe - Determine if the Serial Mux should claim this device.
466 * @dev: The parisc device.
467 *
468 * Deterimine if the Serial Mux should claim this chip (return 0)
469 * or not (return 1).
470 */
471static int __init mux_probe(struct parisc_device *dev)
472{
473 int i, status;
474
475 int port_count = get_mux_port_count(dev);
476 printk(KERN_INFO "Serial mux driver (%d ports) Revision: 0.6\n", port_count);
477
478 dev_set_drvdata(&dev->dev, (void *)(long)port_count);
479 request_mem_region(dev->hpa.start + MUX_OFFSET,
480 port_count * MUX_LINE_OFFSET, "Mux");
481
482 if(!port_cnt) {
483 mux_driver.cons = MUX_CONSOLE;
484
485 status = uart_register_driver(&mux_driver);
486 if(status) {
487 printk(KERN_ERR "Serial mux: Unable to register driver.\n");
488 return 1;
489 }
490 }
491
492 for(i = 0; i < port_count; ++i, ++port_cnt) {
493 struct uart_port *port = &mux_ports[port_cnt].port;
494 port->iobase = 0;
495 port->mapbase = dev->hpa.start + MUX_OFFSET +
496 (i * MUX_LINE_OFFSET);
497 port->membase = ioremap_nocache(port->mapbase, MUX_LINE_OFFSET);
498 port->iotype = UPIO_MEM;
499 port->type = PORT_MUX;
500 port->irq = NO_IRQ;
501 port->uartclk = 0;
502 port->fifosize = MUX_FIFO_SIZE;
503 port->ops = &mux_pops;
504 port->flags = UPF_BOOT_AUTOCONF;
505 port->line = port_cnt;
506
507 /* The port->timeout needs to match what is present in
508 * uart_wait_until_sent in serial_core.c. Otherwise
509 * the time spent in msleep_interruptable will be very
510 * long, causing the appearance of a console hang.
511 */
512 port->timeout = HZ / 50;
513 spin_lock_init(&port->lock);
514
515 status = uart_add_one_port(&mux_driver, port);
516 BUG_ON(status);
517 }
518
519 return 0;
520}
521
522static int __devexit mux_remove(struct parisc_device *dev)
523{
524 int i, j;
525 int port_count = (long)dev_get_drvdata(&dev->dev);
526
527 /* Find Port 0 for this card in the mux_ports list. */
528 for(i = 0; i < port_cnt; ++i) {
529 if(mux_ports[i].port.mapbase == dev->hpa.start + MUX_OFFSET)
530 break;
531 }
532 BUG_ON(i + port_count > port_cnt);
533
534 /* Release the resources associated with each port on the device. */
535 for(j = 0; j < port_count; ++j, ++i) {
536 struct uart_port *port = &mux_ports[i].port;
537
538 uart_remove_one_port(&mux_driver, port);
539 if(port->membase)
540 iounmap(port->membase);
541 }
542
543 release_mem_region(dev->hpa.start + MUX_OFFSET, port_count * MUX_LINE_OFFSET);
544 return 0;
545}
546
547/* Hack. This idea was taken from the 8250_gsc.c on how to properly order
548 * the serial port detection in the proper order. The idea is we always
549 * want the builtin mux to be detected before addin mux cards, so we
550 * specifically probe for the builtin mux cards first.
551 *
552 * This table only contains the parisc_device_id of known builtin mux
553 * devices. All other mux cards will be detected by the generic mux_tbl.
554 */
555static struct parisc_device_id builtin_mux_tbl[] = {
556 { HPHW_A_DIRECT, HVERSION_REV_ANY_ID, 0x15, 0x0000D }, /* All K-class */
557 { HPHW_A_DIRECT, HVERSION_REV_ANY_ID, 0x44, 0x0000D }, /* E35, E45, and E55 */
558 { 0, }
559};
560
561static struct parisc_device_id mux_tbl[] = {
562 { HPHW_A_DIRECT, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x0000D },
563 { 0, }
564};
565
566MODULE_DEVICE_TABLE(parisc, builtin_mux_tbl);
567MODULE_DEVICE_TABLE(parisc, mux_tbl);
568
569static struct parisc_driver builtin_serial_mux_driver = {
570 .name = "builtin_serial_mux",
571 .id_table = builtin_mux_tbl,
572 .probe = mux_probe,
573 .remove = __devexit_p(mux_remove),
574};
575
576static struct parisc_driver serial_mux_driver = {
577 .name = "serial_mux",
578 .id_table = mux_tbl,
579 .probe = mux_probe,
580 .remove = __devexit_p(mux_remove),
581};
582
583/**
584 * mux_init - Serial MUX initialization procedure.
585 *
586 * Register the Serial MUX driver.
587 */
588static int __init mux_init(void)
589{
590 register_parisc_driver(&builtin_serial_mux_driver);
591 register_parisc_driver(&serial_mux_driver);
592
593 if(port_cnt > 0) {
594 /* Start the Mux timer */
595 init_timer(&mux_timer);
596 mux_timer.function = mux_poll;
597 mod_timer(&mux_timer, jiffies + MUX_POLL_DELAY);
598
599#ifdef CONFIG_SERIAL_MUX_CONSOLE
600 register_console(&mux_console);
601#endif
602 }
603
604 return 0;
605}
606
607/**
608 * mux_exit - Serial MUX cleanup procedure.
609 *
610 * Unregister the Serial MUX driver from the tty layer.
611 */
612static void __exit mux_exit(void)
613{
614 /* Delete the Mux timer. */
615 if(port_cnt > 0) {
616 del_timer(&mux_timer);
617#ifdef CONFIG_SERIAL_MUX_CONSOLE
618 unregister_console(&mux_console);
619#endif
620 }
621
622 unregister_parisc_driver(&builtin_serial_mux_driver);
623 unregister_parisc_driver(&serial_mux_driver);
624 uart_unregister_driver(&mux_driver);
625}
626
627module_init(mux_init);
628module_exit(mux_exit);
629
630MODULE_AUTHOR("Ryan Bradetich");
631MODULE_DESCRIPTION("Serial MUX driver");
632MODULE_LICENSE("GPL");
633MODULE_ALIAS_CHARDEV_MAJOR(MUX_MAJOR);
diff --git a/drivers/serial/netx-serial.c b/drivers/serial/netx-serial.c
deleted file mode 100644
index 7735c9f35fa0..000000000000
--- a/drivers/serial/netx-serial.c
+++ /dev/null
@@ -1,750 +0,0 @@
1/*
2 * drivers/serial/netx-serial.c
3 *
4 * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2
8 * as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#if defined(CONFIG_SERIAL_NETX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
23
24#include <linux/device.h>
25#include <linux/module.h>
26#include <linux/ioport.h>
27#include <linux/init.h>
28#include <linux/console.h>
29#include <linux/sysrq.h>
30#include <linux/platform_device.h>
31#include <linux/tty.h>
32#include <linux/tty_flip.h>
33#include <linux/serial_core.h>
34#include <linux/serial.h>
35
36#include <asm/io.h>
37#include <asm/irq.h>
38#include <mach/hardware.h>
39#include <mach/netx-regs.h>
40
41/* We've been assigned a range on the "Low-density serial ports" major */
42#define SERIAL_NX_MAJOR 204
43#define MINOR_START 170
44
45enum uart_regs {
46 UART_DR = 0x00,
47 UART_SR = 0x04,
48 UART_LINE_CR = 0x08,
49 UART_BAUDDIV_MSB = 0x0c,
50 UART_BAUDDIV_LSB = 0x10,
51 UART_CR = 0x14,
52 UART_FR = 0x18,
53 UART_IIR = 0x1c,
54 UART_ILPR = 0x20,
55 UART_RTS_CR = 0x24,
56 UART_RTS_LEAD = 0x28,
57 UART_RTS_TRAIL = 0x2c,
58 UART_DRV_ENABLE = 0x30,
59 UART_BRM_CR = 0x34,
60 UART_RXFIFO_IRQLEVEL = 0x38,
61 UART_TXFIFO_IRQLEVEL = 0x3c,
62};
63
64#define SR_FE (1<<0)
65#define SR_PE (1<<1)
66#define SR_BE (1<<2)
67#define SR_OE (1<<3)
68
69#define LINE_CR_BRK (1<<0)
70#define LINE_CR_PEN (1<<1)
71#define LINE_CR_EPS (1<<2)
72#define LINE_CR_STP2 (1<<3)
73#define LINE_CR_FEN (1<<4)
74#define LINE_CR_5BIT (0<<5)
75#define LINE_CR_6BIT (1<<5)
76#define LINE_CR_7BIT (2<<5)
77#define LINE_CR_8BIT (3<<5)
78#define LINE_CR_BITS_MASK (3<<5)
79
80#define CR_UART_EN (1<<0)
81#define CR_SIREN (1<<1)
82#define CR_SIRLP (1<<2)
83#define CR_MSIE (1<<3)
84#define CR_RIE (1<<4)
85#define CR_TIE (1<<5)
86#define CR_RTIE (1<<6)
87#define CR_LBE (1<<7)
88
89#define FR_CTS (1<<0)
90#define FR_DSR (1<<1)
91#define FR_DCD (1<<2)
92#define FR_BUSY (1<<3)
93#define FR_RXFE (1<<4)
94#define FR_TXFF (1<<5)
95#define FR_RXFF (1<<6)
96#define FR_TXFE (1<<7)
97
98#define IIR_MIS (1<<0)
99#define IIR_RIS (1<<1)
100#define IIR_TIS (1<<2)
101#define IIR_RTIS (1<<3)
102#define IIR_MASK 0xf
103
104#define RTS_CR_AUTO (1<<0)
105#define RTS_CR_RTS (1<<1)
106#define RTS_CR_COUNT (1<<2)
107#define RTS_CR_MOD2 (1<<3)
108#define RTS_CR_RTS_POL (1<<4)
109#define RTS_CR_CTS_CTR (1<<5)
110#define RTS_CR_CTS_POL (1<<6)
111#define RTS_CR_STICK (1<<7)
112
113#define UART_PORT_SIZE 0x40
114#define DRIVER_NAME "netx-uart"
115
116struct netx_port {
117 struct uart_port port;
118};
119
120static void netx_stop_tx(struct uart_port *port)
121{
122 unsigned int val;
123 val = readl(port->membase + UART_CR);
124 writel(val & ~CR_TIE, port->membase + UART_CR);
125}
126
127static void netx_stop_rx(struct uart_port *port)
128{
129 unsigned int val;
130 val = readl(port->membase + UART_CR);
131 writel(val & ~CR_RIE, port->membase + UART_CR);
132}
133
134static void netx_enable_ms(struct uart_port *port)
135{
136 unsigned int val;
137 val = readl(port->membase + UART_CR);
138 writel(val | CR_MSIE, port->membase + UART_CR);
139}
140
141static inline void netx_transmit_buffer(struct uart_port *port)
142{
143 struct circ_buf *xmit = &port->state->xmit;
144
145 if (port->x_char) {
146 writel(port->x_char, port->membase + UART_DR);
147 port->icount.tx++;
148 port->x_char = 0;
149 return;
150 }
151
152 if (uart_tx_stopped(port) || uart_circ_empty(xmit)) {
153 netx_stop_tx(port);
154 return;
155 }
156
157 do {
158 /* send xmit->buf[xmit->tail]
159 * out the port here */
160 writel(xmit->buf[xmit->tail], port->membase + UART_DR);
161 xmit->tail = (xmit->tail + 1) &
162 (UART_XMIT_SIZE - 1);
163 port->icount.tx++;
164 if (uart_circ_empty(xmit))
165 break;
166 } while (!(readl(port->membase + UART_FR) & FR_TXFF));
167
168 if (uart_circ_empty(xmit))
169 netx_stop_tx(port);
170}
171
172static void netx_start_tx(struct uart_port *port)
173{
174 writel(
175 readl(port->membase + UART_CR) | CR_TIE, port->membase + UART_CR);
176
177 if (!(readl(port->membase + UART_FR) & FR_TXFF))
178 netx_transmit_buffer(port);
179}
180
181static unsigned int netx_tx_empty(struct uart_port *port)
182{
183 return readl(port->membase + UART_FR) & FR_BUSY ? 0 : TIOCSER_TEMT;
184}
185
186static void netx_txint(struct uart_port *port)
187{
188 struct circ_buf *xmit = &port->state->xmit;
189
190 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
191 netx_stop_tx(port);
192 return;
193 }
194
195 netx_transmit_buffer(port);
196
197 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
198 uart_write_wakeup(port);
199}
200
201static void netx_rxint(struct uart_port *port)
202{
203 unsigned char rx, flg, status;
204 struct tty_struct *tty = port->state->port.tty;
205
206 while (!(readl(port->membase + UART_FR) & FR_RXFE)) {
207 rx = readl(port->membase + UART_DR);
208 flg = TTY_NORMAL;
209 port->icount.rx++;
210 status = readl(port->membase + UART_SR);
211 if (status & SR_BE) {
212 writel(0, port->membase + UART_SR);
213 if (uart_handle_break(port))
214 continue;
215 }
216
217 if (unlikely(status & (SR_FE | SR_PE | SR_OE))) {
218
219 if (status & SR_PE)
220 port->icount.parity++;
221 else if (status & SR_FE)
222 port->icount.frame++;
223 if (status & SR_OE)
224 port->icount.overrun++;
225
226 status &= port->read_status_mask;
227
228 if (status & SR_BE)
229 flg = TTY_BREAK;
230 else if (status & SR_PE)
231 flg = TTY_PARITY;
232 else if (status & SR_FE)
233 flg = TTY_FRAME;
234 }
235
236 if (uart_handle_sysrq_char(port, rx))
237 continue;
238
239 uart_insert_char(port, status, SR_OE, rx, flg);
240 }
241
242 tty_flip_buffer_push(tty);
243 return;
244}
245
246static irqreturn_t netx_int(int irq, void *dev_id)
247{
248 struct uart_port *port = dev_id;
249 unsigned long flags;
250 unsigned char status;
251
252 spin_lock_irqsave(&port->lock,flags);
253
254 status = readl(port->membase + UART_IIR) & IIR_MASK;
255 while (status) {
256 if (status & IIR_RIS)
257 netx_rxint(port);
258 if (status & IIR_TIS)
259 netx_txint(port);
260 if (status & IIR_MIS) {
261 if (readl(port->membase + UART_FR) & FR_CTS)
262 uart_handle_cts_change(port, 1);
263 else
264 uart_handle_cts_change(port, 0);
265 }
266 writel(0, port->membase + UART_IIR);
267 status = readl(port->membase + UART_IIR) & IIR_MASK;
268 }
269
270 spin_unlock_irqrestore(&port->lock,flags);
271 return IRQ_HANDLED;
272}
273
274static unsigned int netx_get_mctrl(struct uart_port *port)
275{
276 unsigned int ret = TIOCM_DSR | TIOCM_CAR;
277
278 if (readl(port->membase + UART_FR) & FR_CTS)
279 ret |= TIOCM_CTS;
280
281 return ret;
282}
283
284static void netx_set_mctrl(struct uart_port *port, unsigned int mctrl)
285{
286 unsigned int val;
287
288 /* FIXME: Locking needed ? */
289 if (mctrl & TIOCM_RTS) {
290 val = readl(port->membase + UART_RTS_CR);
291 writel(val | RTS_CR_RTS, port->membase + UART_RTS_CR);
292 }
293}
294
295static void netx_break_ctl(struct uart_port *port, int break_state)
296{
297 unsigned int line_cr;
298 spin_lock_irq(&port->lock);
299
300 line_cr = readl(port->membase + UART_LINE_CR);
301 if (break_state != 0)
302 line_cr |= LINE_CR_BRK;
303 else
304 line_cr &= ~LINE_CR_BRK;
305 writel(line_cr, port->membase + UART_LINE_CR);
306
307 spin_unlock_irq(&port->lock);
308}
309
310static int netx_startup(struct uart_port *port)
311{
312 int ret;
313
314 ret = request_irq(port->irq, netx_int, 0,
315 DRIVER_NAME, port);
316 if (ret) {
317 dev_err(port->dev, "unable to grab irq%d\n",port->irq);
318 goto exit;
319 }
320
321 writel(readl(port->membase + UART_LINE_CR) | LINE_CR_FEN,
322 port->membase + UART_LINE_CR);
323
324 writel(CR_MSIE | CR_RIE | CR_TIE | CR_RTIE | CR_UART_EN,
325 port->membase + UART_CR);
326
327exit:
328 return ret;
329}
330
331static void netx_shutdown(struct uart_port *port)
332{
333 writel(0, port->membase + UART_CR) ;
334
335 free_irq(port->irq, port);
336}
337
338static void
339netx_set_termios(struct uart_port *port, struct ktermios *termios,
340 struct ktermios *old)
341{
342 unsigned int baud, quot;
343 unsigned char old_cr;
344 unsigned char line_cr = LINE_CR_FEN;
345 unsigned char rts_cr = 0;
346
347 switch (termios->c_cflag & CSIZE) {
348 case CS5:
349 line_cr |= LINE_CR_5BIT;
350 break;
351 case CS6:
352 line_cr |= LINE_CR_6BIT;
353 break;
354 case CS7:
355 line_cr |= LINE_CR_7BIT;
356 break;
357 case CS8:
358 line_cr |= LINE_CR_8BIT;
359 break;
360 }
361
362 if (termios->c_cflag & CSTOPB)
363 line_cr |= LINE_CR_STP2;
364
365 if (termios->c_cflag & PARENB) {
366 line_cr |= LINE_CR_PEN;
367 if (!(termios->c_cflag & PARODD))
368 line_cr |= LINE_CR_EPS;
369 }
370
371 if (termios->c_cflag & CRTSCTS)
372 rts_cr = RTS_CR_AUTO | RTS_CR_CTS_CTR | RTS_CR_RTS_POL;
373
374 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
375 quot = baud * 4096;
376 quot /= 1000;
377 quot *= 256;
378 quot /= 100000;
379
380 spin_lock_irq(&port->lock);
381
382 uart_update_timeout(port, termios->c_cflag, baud);
383
384 old_cr = readl(port->membase + UART_CR);
385
386 /* disable interrupts */
387 writel(old_cr & ~(CR_MSIE | CR_RIE | CR_TIE | CR_RTIE),
388 port->membase + UART_CR);
389
390 /* drain transmitter */
391 while (readl(port->membase + UART_FR) & FR_BUSY);
392
393 /* disable UART */
394 writel(old_cr & ~CR_UART_EN, port->membase + UART_CR);
395
396 /* modem status interrupts */
397 old_cr &= ~CR_MSIE;
398 if (UART_ENABLE_MS(port, termios->c_cflag))
399 old_cr |= CR_MSIE;
400
401 writel((quot>>8) & 0xff, port->membase + UART_BAUDDIV_MSB);
402 writel(quot & 0xff, port->membase + UART_BAUDDIV_LSB);
403 writel(line_cr, port->membase + UART_LINE_CR);
404
405 writel(rts_cr, port->membase + UART_RTS_CR);
406
407 /*
408 * Characters to ignore
409 */
410 port->ignore_status_mask = 0;
411 if (termios->c_iflag & IGNPAR)
412 port->ignore_status_mask |= SR_PE;
413 if (termios->c_iflag & IGNBRK) {
414 port->ignore_status_mask |= SR_BE;
415 /*
416 * If we're ignoring parity and break indicators,
417 * ignore overruns too (for real raw support).
418 */
419 if (termios->c_iflag & IGNPAR)
420 port->ignore_status_mask |= SR_PE;
421 }
422
423 port->read_status_mask = 0;
424 if (termios->c_iflag & (BRKINT | PARMRK))
425 port->read_status_mask |= SR_BE;
426 if (termios->c_iflag & INPCK)
427 port->read_status_mask |= SR_PE | SR_FE;
428
429 writel(old_cr, port->membase + UART_CR);
430
431 spin_unlock_irq(&port->lock);
432}
433
434static const char *netx_type(struct uart_port *port)
435{
436 return port->type == PORT_NETX ? "NETX" : NULL;
437}
438
439static void netx_release_port(struct uart_port *port)
440{
441 release_mem_region(port->mapbase, UART_PORT_SIZE);
442}
443
444static int netx_request_port(struct uart_port *port)
445{
446 return request_mem_region(port->mapbase, UART_PORT_SIZE,
447 DRIVER_NAME) != NULL ? 0 : -EBUSY;
448}
449
450static void netx_config_port(struct uart_port *port, int flags)
451{
452 if (flags & UART_CONFIG_TYPE && netx_request_port(port) == 0)
453 port->type = PORT_NETX;
454}
455
456static int
457netx_verify_port(struct uart_port *port, struct serial_struct *ser)
458{
459 int ret = 0;
460
461 if (ser->type != PORT_UNKNOWN && ser->type != PORT_NETX)
462 ret = -EINVAL;
463
464 return ret;
465}
466
467static struct uart_ops netx_pops = {
468 .tx_empty = netx_tx_empty,
469 .set_mctrl = netx_set_mctrl,
470 .get_mctrl = netx_get_mctrl,
471 .stop_tx = netx_stop_tx,
472 .start_tx = netx_start_tx,
473 .stop_rx = netx_stop_rx,
474 .enable_ms = netx_enable_ms,
475 .break_ctl = netx_break_ctl,
476 .startup = netx_startup,
477 .shutdown = netx_shutdown,
478 .set_termios = netx_set_termios,
479 .type = netx_type,
480 .release_port = netx_release_port,
481 .request_port = netx_request_port,
482 .config_port = netx_config_port,
483 .verify_port = netx_verify_port,
484};
485
486static struct netx_port netx_ports[] = {
487 {
488 .port = {
489 .type = PORT_NETX,
490 .iotype = UPIO_MEM,
491 .membase = (char __iomem *)io_p2v(NETX_PA_UART0),
492 .mapbase = NETX_PA_UART0,
493 .irq = NETX_IRQ_UART0,
494 .uartclk = 100000000,
495 .fifosize = 16,
496 .flags = UPF_BOOT_AUTOCONF,
497 .ops = &netx_pops,
498 .line = 0,
499 },
500 }, {
501 .port = {
502 .type = PORT_NETX,
503 .iotype = UPIO_MEM,
504 .membase = (char __iomem *)io_p2v(NETX_PA_UART1),
505 .mapbase = NETX_PA_UART1,
506 .irq = NETX_IRQ_UART1,
507 .uartclk = 100000000,
508 .fifosize = 16,
509 .flags = UPF_BOOT_AUTOCONF,
510 .ops = &netx_pops,
511 .line = 1,
512 },
513 }, {
514 .port = {
515 .type = PORT_NETX,
516 .iotype = UPIO_MEM,
517 .membase = (char __iomem *)io_p2v(NETX_PA_UART2),
518 .mapbase = NETX_PA_UART2,
519 .irq = NETX_IRQ_UART2,
520 .uartclk = 100000000,
521 .fifosize = 16,
522 .flags = UPF_BOOT_AUTOCONF,
523 .ops = &netx_pops,
524 .line = 2,
525 },
526 }
527};
528
529#ifdef CONFIG_SERIAL_NETX_CONSOLE
530
531static void netx_console_putchar(struct uart_port *port, int ch)
532{
533 while (readl(port->membase + UART_FR) & FR_BUSY);
534 writel(ch, port->membase + UART_DR);
535}
536
537static void
538netx_console_write(struct console *co, const char *s, unsigned int count)
539{
540 struct uart_port *port = &netx_ports[co->index].port;
541 unsigned char cr_save;
542
543 cr_save = readl(port->membase + UART_CR);
544 writel(cr_save | CR_UART_EN, port->membase + UART_CR);
545
546 uart_console_write(port, s, count, netx_console_putchar);
547
548 while (readl(port->membase + UART_FR) & FR_BUSY);
549 writel(cr_save, port->membase + UART_CR);
550}
551
552static void __init
553netx_console_get_options(struct uart_port *port, int *baud,
554 int *parity, int *bits, int *flow)
555{
556 unsigned char line_cr;
557
558 *baud = (readl(port->membase + UART_BAUDDIV_MSB) << 8) |
559 readl(port->membase + UART_BAUDDIV_LSB);
560 *baud *= 1000;
561 *baud /= 4096;
562 *baud *= 1000;
563 *baud /= 256;
564 *baud *= 100;
565
566 line_cr = readl(port->membase + UART_LINE_CR);
567 *parity = 'n';
568 if (line_cr & LINE_CR_PEN) {
569 if (line_cr & LINE_CR_EPS)
570 *parity = 'e';
571 else
572 *parity = 'o';
573 }
574
575 switch (line_cr & LINE_CR_BITS_MASK) {
576 case LINE_CR_8BIT:
577 *bits = 8;
578 break;
579 case LINE_CR_7BIT:
580 *bits = 7;
581 break;
582 case LINE_CR_6BIT:
583 *bits = 6;
584 break;
585 case LINE_CR_5BIT:
586 *bits = 5;
587 break;
588 }
589
590 if (readl(port->membase + UART_RTS_CR) & RTS_CR_AUTO)
591 *flow = 'r';
592}
593
594static int __init
595netx_console_setup(struct console *co, char *options)
596{
597 struct netx_port *sport;
598 int baud = 9600;
599 int bits = 8;
600 int parity = 'n';
601 int flow = 'n';
602
603 /*
604 * Check whether an invalid uart number has been specified, and
605 * if so, search for the first available port that does have
606 * console support.
607 */
608 if (co->index == -1 || co->index >= ARRAY_SIZE(netx_ports))
609 co->index = 0;
610 sport = &netx_ports[co->index];
611
612 if (options) {
613 uart_parse_options(options, &baud, &parity, &bits, &flow);
614 } else {
615 /* if the UART is enabled, assume it has been correctly setup
616 * by the bootloader and get the options
617 */
618 if (readl(sport->port.membase + UART_CR) & CR_UART_EN) {
619 netx_console_get_options(&sport->port, &baud,
620 &parity, &bits, &flow);
621 }
622
623 }
624
625 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
626}
627
628static struct uart_driver netx_reg;
629static struct console netx_console = {
630 .name = "ttyNX",
631 .write = netx_console_write,
632 .device = uart_console_device,
633 .setup = netx_console_setup,
634 .flags = CON_PRINTBUFFER,
635 .index = -1,
636 .data = &netx_reg,
637};
638
639static int __init netx_console_init(void)
640{
641 register_console(&netx_console);
642 return 0;
643}
644console_initcall(netx_console_init);
645
646#define NETX_CONSOLE &netx_console
647#else
648#define NETX_CONSOLE NULL
649#endif
650
651static struct uart_driver netx_reg = {
652 .owner = THIS_MODULE,
653 .driver_name = DRIVER_NAME,
654 .dev_name = "ttyNX",
655 .major = SERIAL_NX_MAJOR,
656 .minor = MINOR_START,
657 .nr = ARRAY_SIZE(netx_ports),
658 .cons = NETX_CONSOLE,
659};
660
661static int serial_netx_suspend(struct platform_device *pdev, pm_message_t state)
662{
663 struct netx_port *sport = platform_get_drvdata(pdev);
664
665 if (sport)
666 uart_suspend_port(&netx_reg, &sport->port);
667
668 return 0;
669}
670
671static int serial_netx_resume(struct platform_device *pdev)
672{
673 struct netx_port *sport = platform_get_drvdata(pdev);
674
675 if (sport)
676 uart_resume_port(&netx_reg, &sport->port);
677
678 return 0;
679}
680
681static int serial_netx_probe(struct platform_device *pdev)
682{
683 struct uart_port *port = &netx_ports[pdev->id].port;
684
685 dev_info(&pdev->dev, "initialising\n");
686
687 port->dev = &pdev->dev;
688
689 writel(1, port->membase + UART_RXFIFO_IRQLEVEL);
690 uart_add_one_port(&netx_reg, &netx_ports[pdev->id].port);
691 platform_set_drvdata(pdev, &netx_ports[pdev->id]);
692
693 return 0;
694}
695
696static int serial_netx_remove(struct platform_device *pdev)
697{
698 struct netx_port *sport = platform_get_drvdata(pdev);
699
700 platform_set_drvdata(pdev, NULL);
701
702 if (sport)
703 uart_remove_one_port(&netx_reg, &sport->port);
704
705 return 0;
706}
707
708static struct platform_driver serial_netx_driver = {
709 .probe = serial_netx_probe,
710 .remove = serial_netx_remove,
711
712 .suspend = serial_netx_suspend,
713 .resume = serial_netx_resume,
714
715 .driver = {
716 .name = DRIVER_NAME,
717 .owner = THIS_MODULE,
718 },
719};
720
721static int __init netx_serial_init(void)
722{
723 int ret;
724
725 printk(KERN_INFO "Serial: NetX driver\n");
726
727 ret = uart_register_driver(&netx_reg);
728 if (ret)
729 return ret;
730
731 ret = platform_driver_register(&serial_netx_driver);
732 if (ret != 0)
733 uart_unregister_driver(&netx_reg);
734
735 return 0;
736}
737
738static void __exit netx_serial_exit(void)
739{
740 platform_driver_unregister(&serial_netx_driver);
741 uart_unregister_driver(&netx_reg);
742}
743
744module_init(netx_serial_init);
745module_exit(netx_serial_exit);
746
747MODULE_AUTHOR("Sascha Hauer");
748MODULE_DESCRIPTION("NetX serial port driver");
749MODULE_LICENSE("GPL");
750MODULE_ALIAS("platform:" DRIVER_NAME);
diff --git a/drivers/serial/nwpserial.c b/drivers/serial/nwpserial.c
deleted file mode 100644
index de173671e3d0..000000000000
--- a/drivers/serial/nwpserial.c
+++ /dev/null
@@ -1,477 +0,0 @@
1/*
2 * Serial Port driver for a NWP uart device
3 *
4 * Copyright (C) 2008 IBM Corp., Benjamin Krill <ben@codiert.org>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 */
12#include <linux/init.h>
13#include <linux/console.h>
14#include <linux/serial.h>
15#include <linux/serial_reg.h>
16#include <linux/serial_core.h>
17#include <linux/tty.h>
18#include <linux/irqreturn.h>
19#include <linux/mutex.h>
20#include <linux/of_platform.h>
21#include <linux/of_device.h>
22#include <linux/nwpserial.h>
23#include <asm/prom.h>
24#include <asm/dcr.h>
25
26#define NWPSERIAL_NR 2
27
28#define NWPSERIAL_STATUS_RXVALID 0x1
29#define NWPSERIAL_STATUS_TXFULL 0x2
30
31struct nwpserial_port {
32 struct uart_port port;
33 dcr_host_t dcr_host;
34 unsigned int ier;
35 unsigned int mcr;
36};
37
38static DEFINE_MUTEX(nwpserial_mutex);
39static struct nwpserial_port nwpserial_ports[NWPSERIAL_NR];
40
41static void wait_for_bits(struct nwpserial_port *up, int bits)
42{
43 unsigned int status, tmout = 10000;
44
45 /* Wait up to 10ms for the character(s) to be sent. */
46 do {
47 status = dcr_read(up->dcr_host, UART_LSR);
48
49 if (--tmout == 0)
50 break;
51 udelay(1);
52 } while ((status & bits) != bits);
53}
54
55#ifdef CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL_CONSOLE
56static void nwpserial_console_putchar(struct uart_port *port, int c)
57{
58 struct nwpserial_port *up;
59 up = container_of(port, struct nwpserial_port, port);
60 /* check if tx buffer is full */
61 wait_for_bits(up, UART_LSR_THRE);
62 dcr_write(up->dcr_host, UART_TX, c);
63 up->port.icount.tx++;
64}
65
66static void
67nwpserial_console_write(struct console *co, const char *s, unsigned int count)
68{
69 struct nwpserial_port *up = &nwpserial_ports[co->index];
70 unsigned long flags;
71 int locked = 1;
72
73 if (oops_in_progress)
74 locked = spin_trylock_irqsave(&up->port.lock, flags);
75 else
76 spin_lock_irqsave(&up->port.lock, flags);
77
78 /* save and disable interrupt */
79 up->ier = dcr_read(up->dcr_host, UART_IER);
80 dcr_write(up->dcr_host, UART_IER, up->ier & ~UART_IER_RDI);
81
82 uart_console_write(&up->port, s, count, nwpserial_console_putchar);
83
84 /* wait for transmitter to become empty */
85 while ((dcr_read(up->dcr_host, UART_LSR) & UART_LSR_THRE) == 0)
86 cpu_relax();
87
88 /* restore interrupt state */
89 dcr_write(up->dcr_host, UART_IER, up->ier);
90
91 if (locked)
92 spin_unlock_irqrestore(&up->port.lock, flags);
93}
94
95static struct uart_driver nwpserial_reg;
96static struct console nwpserial_console = {
97 .name = "ttySQ",
98 .write = nwpserial_console_write,
99 .device = uart_console_device,
100 .flags = CON_PRINTBUFFER,
101 .index = -1,
102 .data = &nwpserial_reg,
103};
104#define NWPSERIAL_CONSOLE (&nwpserial_console)
105#else
106#define NWPSERIAL_CONSOLE NULL
107#endif /* CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL_CONSOLE */
108
109/**************************************************************************/
110
111static int nwpserial_request_port(struct uart_port *port)
112{
113 return 0;
114}
115
116static void nwpserial_release_port(struct uart_port *port)
117{
118 /* N/A */
119}
120
121static void nwpserial_config_port(struct uart_port *port, int flags)
122{
123 port->type = PORT_NWPSERIAL;
124}
125
126static irqreturn_t nwpserial_interrupt(int irq, void *dev_id)
127{
128 struct nwpserial_port *up = dev_id;
129 struct tty_struct *tty = up->port.state->port.tty;
130 irqreturn_t ret;
131 unsigned int iir;
132 unsigned char ch;
133
134 spin_lock(&up->port.lock);
135
136 /* check if the uart was the interrupt source. */
137 iir = dcr_read(up->dcr_host, UART_IIR);
138 if (!iir) {
139 ret = IRQ_NONE;
140 goto out;
141 }
142
143 do {
144 up->port.icount.rx++;
145 ch = dcr_read(up->dcr_host, UART_RX);
146 if (up->port.ignore_status_mask != NWPSERIAL_STATUS_RXVALID)
147 tty_insert_flip_char(tty, ch, TTY_NORMAL);
148 } while (dcr_read(up->dcr_host, UART_LSR) & UART_LSR_DR);
149
150 tty_flip_buffer_push(tty);
151 ret = IRQ_HANDLED;
152
153 /* clear interrupt */
154 dcr_write(up->dcr_host, UART_IIR, 1);
155out:
156 spin_unlock(&up->port.lock);
157 return ret;
158}
159
160static int nwpserial_startup(struct uart_port *port)
161{
162 struct nwpserial_port *up;
163 int err;
164
165 up = container_of(port, struct nwpserial_port, port);
166
167 /* disable flow control by default */
168 up->mcr = dcr_read(up->dcr_host, UART_MCR) & ~UART_MCR_AFE;
169 dcr_write(up->dcr_host, UART_MCR, up->mcr);
170
171 /* register interrupt handler */
172 err = request_irq(up->port.irq, nwpserial_interrupt,
173 IRQF_SHARED, "nwpserial", up);
174 if (err)
175 return err;
176
177 /* enable interrupts */
178 up->ier = UART_IER_RDI;
179 dcr_write(up->dcr_host, UART_IER, up->ier);
180
181 /* enable receiving */
182 up->port.ignore_status_mask &= ~NWPSERIAL_STATUS_RXVALID;
183
184 return 0;
185}
186
187static void nwpserial_shutdown(struct uart_port *port)
188{
189 struct nwpserial_port *up;
190 up = container_of(port, struct nwpserial_port, port);
191
192 /* disable receiving */
193 up->port.ignore_status_mask |= NWPSERIAL_STATUS_RXVALID;
194
195 /* disable interrupts from this port */
196 up->ier = 0;
197 dcr_write(up->dcr_host, UART_IER, up->ier);
198
199 /* free irq */
200 free_irq(up->port.irq, port);
201}
202
203static int nwpserial_verify_port(struct uart_port *port,
204 struct serial_struct *ser)
205{
206 return -EINVAL;
207}
208
209static const char *nwpserial_type(struct uart_port *port)
210{
211 return port->type == PORT_NWPSERIAL ? "nwpserial" : NULL;
212}
213
214static void nwpserial_set_termios(struct uart_port *port,
215 struct ktermios *termios, struct ktermios *old)
216{
217 struct nwpserial_port *up;
218 up = container_of(port, struct nwpserial_port, port);
219
220 up->port.read_status_mask = NWPSERIAL_STATUS_RXVALID
221 | NWPSERIAL_STATUS_TXFULL;
222
223 up->port.ignore_status_mask = 0;
224 /* ignore all characters if CREAD is not set */
225 if ((termios->c_cflag & CREAD) == 0)
226 up->port.ignore_status_mask |= NWPSERIAL_STATUS_RXVALID;
227
228 /* Copy back the old hardware settings */
229 if (old)
230 tty_termios_copy_hw(termios, old);
231}
232
233static void nwpserial_break_ctl(struct uart_port *port, int ctl)
234{
235 /* N/A */
236}
237
238static void nwpserial_enable_ms(struct uart_port *port)
239{
240 /* N/A */
241}
242
243static void nwpserial_stop_rx(struct uart_port *port)
244{
245 struct nwpserial_port *up;
246 up = container_of(port, struct nwpserial_port, port);
247 /* don't forward any more data (like !CREAD) */
248 up->port.ignore_status_mask = NWPSERIAL_STATUS_RXVALID;
249}
250
251static void nwpserial_putchar(struct nwpserial_port *up, unsigned char c)
252{
253 /* check if tx buffer is full */
254 wait_for_bits(up, UART_LSR_THRE);
255 dcr_write(up->dcr_host, UART_TX, c);
256 up->port.icount.tx++;
257}
258
259static void nwpserial_start_tx(struct uart_port *port)
260{
261 struct nwpserial_port *up;
262 struct circ_buf *xmit;
263 up = container_of(port, struct nwpserial_port, port);
264 xmit = &up->port.state->xmit;
265
266 if (port->x_char) {
267 nwpserial_putchar(up, up->port.x_char);
268 port->x_char = 0;
269 }
270
271 while (!(uart_circ_empty(xmit) || uart_tx_stopped(&up->port))) {
272 nwpserial_putchar(up, xmit->buf[xmit->tail]);
273 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1);
274 }
275}
276
277static unsigned int nwpserial_get_mctrl(struct uart_port *port)
278{
279 return 0;
280}
281
282static void nwpserial_set_mctrl(struct uart_port *port, unsigned int mctrl)
283{
284 /* N/A */
285}
286
287static void nwpserial_stop_tx(struct uart_port *port)
288{
289 /* N/A */
290}
291
292static unsigned int nwpserial_tx_empty(struct uart_port *port)
293{
294 struct nwpserial_port *up;
295 unsigned long flags;
296 int ret;
297 up = container_of(port, struct nwpserial_port, port);
298
299 spin_lock_irqsave(&up->port.lock, flags);
300 ret = dcr_read(up->dcr_host, UART_LSR);
301 spin_unlock_irqrestore(&up->port.lock, flags);
302
303 return ret & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
304}
305
306static struct uart_ops nwpserial_pops = {
307 .tx_empty = nwpserial_tx_empty,
308 .set_mctrl = nwpserial_set_mctrl,
309 .get_mctrl = nwpserial_get_mctrl,
310 .stop_tx = nwpserial_stop_tx,
311 .start_tx = nwpserial_start_tx,
312 .stop_rx = nwpserial_stop_rx,
313 .enable_ms = nwpserial_enable_ms,
314 .break_ctl = nwpserial_break_ctl,
315 .startup = nwpserial_startup,
316 .shutdown = nwpserial_shutdown,
317 .set_termios = nwpserial_set_termios,
318 .type = nwpserial_type,
319 .release_port = nwpserial_release_port,
320 .request_port = nwpserial_request_port,
321 .config_port = nwpserial_config_port,
322 .verify_port = nwpserial_verify_port,
323};
324
325static struct uart_driver nwpserial_reg = {
326 .owner = THIS_MODULE,
327 .driver_name = "nwpserial",
328 .dev_name = "ttySQ",
329 .major = TTY_MAJOR,
330 .minor = 68,
331 .nr = NWPSERIAL_NR,
332 .cons = NWPSERIAL_CONSOLE,
333};
334
335int nwpserial_register_port(struct uart_port *port)
336{
337 struct nwpserial_port *up = NULL;
338 int ret = -1;
339 int i;
340 static int first = 1;
341 int dcr_len;
342 int dcr_base;
343 struct device_node *dn;
344
345 mutex_lock(&nwpserial_mutex);
346
347 dn = port->dev->of_node;
348 if (dn == NULL)
349 goto out;
350
351 /* get dcr base. */
352 dcr_base = dcr_resource_start(dn, 0);
353
354 /* find matching entry */
355 for (i = 0; i < NWPSERIAL_NR; i++)
356 if (nwpserial_ports[i].port.iobase == dcr_base) {
357 up = &nwpserial_ports[i];
358 break;
359 }
360
361 /* we didn't find a mtching entry, search for a free port */
362 if (up == NULL)
363 for (i = 0; i < NWPSERIAL_NR; i++)
364 if (nwpserial_ports[i].port.type == PORT_UNKNOWN &&
365 nwpserial_ports[i].port.iobase == 0) {
366 up = &nwpserial_ports[i];
367 break;
368 }
369
370 if (up == NULL) {
371 ret = -EBUSY;
372 goto out;
373 }
374
375 if (first)
376 uart_register_driver(&nwpserial_reg);
377 first = 0;
378
379 up->port.membase = port->membase;
380 up->port.irq = port->irq;
381 up->port.uartclk = port->uartclk;
382 up->port.fifosize = port->fifosize;
383 up->port.regshift = port->regshift;
384 up->port.iotype = port->iotype;
385 up->port.flags = port->flags;
386 up->port.mapbase = port->mapbase;
387 up->port.private_data = port->private_data;
388
389 if (port->dev)
390 up->port.dev = port->dev;
391
392 if (up->port.iobase != dcr_base) {
393 up->port.ops = &nwpserial_pops;
394 up->port.fifosize = 16;
395
396 spin_lock_init(&up->port.lock);
397
398 up->port.iobase = dcr_base;
399 dcr_len = dcr_resource_len(dn, 0);
400
401 up->dcr_host = dcr_map(dn, dcr_base, dcr_len);
402 if (!DCR_MAP_OK(up->dcr_host)) {
403 printk(KERN_ERR "Cannot map DCR resources for NWPSERIAL");
404 goto out;
405 }
406 }
407
408 ret = uart_add_one_port(&nwpserial_reg, &up->port);
409 if (ret == 0)
410 ret = up->port.line;
411
412out:
413 mutex_unlock(&nwpserial_mutex);
414
415 return ret;
416}
417EXPORT_SYMBOL(nwpserial_register_port);
418
419void nwpserial_unregister_port(int line)
420{
421 struct nwpserial_port *up = &nwpserial_ports[line];
422 mutex_lock(&nwpserial_mutex);
423 uart_remove_one_port(&nwpserial_reg, &up->port);
424
425 up->port.type = PORT_UNKNOWN;
426
427 mutex_unlock(&nwpserial_mutex);
428}
429EXPORT_SYMBOL(nwpserial_unregister_port);
430
431#ifdef CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL_CONSOLE
432static int __init nwpserial_console_init(void)
433{
434 struct nwpserial_port *up = NULL;
435 struct device_node *dn;
436 const char *name;
437 int dcr_base;
438 int dcr_len;
439 int i;
440
441 /* search for a free port */
442 for (i = 0; i < NWPSERIAL_NR; i++)
443 if (nwpserial_ports[i].port.type == PORT_UNKNOWN) {
444 up = &nwpserial_ports[i];
445 break;
446 }
447
448 if (up == NULL)
449 return -1;
450
451 name = of_get_property(of_chosen, "linux,stdout-path", NULL);
452 if (name == NULL)
453 return -1;
454
455 dn = of_find_node_by_path(name);
456 if (!dn)
457 return -1;
458
459 spin_lock_init(&up->port.lock);
460 up->port.ops = &nwpserial_pops;
461 up->port.type = PORT_NWPSERIAL;
462 up->port.fifosize = 16;
463
464 dcr_base = dcr_resource_start(dn, 0);
465 dcr_len = dcr_resource_len(dn, 0);
466 up->port.iobase = dcr_base;
467
468 up->dcr_host = dcr_map(dn, dcr_base, dcr_len);
469 if (!DCR_MAP_OK(up->dcr_host)) {
470 printk("Cannot map DCR resources for SERIAL");
471 return -1;
472 }
473 register_console(&nwpserial_console);
474 return 0;
475}
476console_initcall(nwpserial_console_init);
477#endif /* CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL_CONSOLE */
diff --git a/drivers/serial/of_serial.c b/drivers/serial/of_serial.c
deleted file mode 100644
index 2af8fd113123..000000000000
--- a/drivers/serial/of_serial.c
+++ /dev/null
@@ -1,200 +0,0 @@
1/*
2 * Serial Port driver for Open Firmware platform devices
3 *
4 * Copyright (C) 2006 Arnd Bergmann <arnd@arndb.de>, IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 */
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/slab.h>
15#include <linux/serial_core.h>
16#include <linux/serial_8250.h>
17#include <linux/of_address.h>
18#include <linux/of_platform.h>
19#include <linux/nwpserial.h>
20
21struct of_serial_info {
22 int type;
23 int line;
24};
25
26/*
27 * Fill a struct uart_port for a given device node
28 */
29static int __devinit of_platform_serial_setup(struct platform_device *ofdev,
30 int type, struct uart_port *port)
31{
32 struct resource resource;
33 struct device_node *np = ofdev->dev.of_node;
34 const unsigned int *clk, *spd;
35 const u32 *prop;
36 int ret, prop_size;
37
38 memset(port, 0, sizeof *port);
39 spd = of_get_property(np, "current-speed", NULL);
40 clk = of_get_property(np, "clock-frequency", NULL);
41 if (!clk) {
42 dev_warn(&ofdev->dev, "no clock-frequency property set\n");
43 return -ENODEV;
44 }
45
46 ret = of_address_to_resource(np, 0, &resource);
47 if (ret) {
48 dev_warn(&ofdev->dev, "invalid address\n");
49 return ret;
50 }
51
52 spin_lock_init(&port->lock);
53 port->mapbase = resource.start;
54
55 /* Check for shifted address mapping */
56 prop = of_get_property(np, "reg-offset", &prop_size);
57 if (prop && (prop_size == sizeof(u32)))
58 port->mapbase += *prop;
59
60 /* Check for registers offset within the devices address range */
61 prop = of_get_property(np, "reg-shift", &prop_size);
62 if (prop && (prop_size == sizeof(u32)))
63 port->regshift = *prop;
64
65 port->irq = irq_of_parse_and_map(np, 0);
66 port->iotype = UPIO_MEM;
67 port->type = type;
68 port->uartclk = *clk;
69 port->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_IOREMAP
70 | UPF_FIXED_PORT | UPF_FIXED_TYPE;
71 port->dev = &ofdev->dev;
72 /* If current-speed was set, then try not to change it. */
73 if (spd)
74 port->custom_divisor = *clk / (16 * (*spd));
75
76 return 0;
77}
78
79/*
80 * Try to register a serial port
81 */
82static int __devinit of_platform_serial_probe(struct platform_device *ofdev,
83 const struct of_device_id *id)
84{
85 struct of_serial_info *info;
86 struct uart_port port;
87 int port_type;
88 int ret;
89
90 if (of_find_property(ofdev->dev.of_node, "used-by-rtas", NULL))
91 return -EBUSY;
92
93 info = kmalloc(sizeof(*info), GFP_KERNEL);
94 if (info == NULL)
95 return -ENOMEM;
96
97 port_type = (unsigned long)id->data;
98 ret = of_platform_serial_setup(ofdev, port_type, &port);
99 if (ret)
100 goto out;
101
102 switch (port_type) {
103#ifdef CONFIG_SERIAL_8250
104 case PORT_8250 ... PORT_MAX_8250:
105 ret = serial8250_register_port(&port);
106 break;
107#endif
108#ifdef CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL
109 case PORT_NWPSERIAL:
110 ret = nwpserial_register_port(&port);
111 break;
112#endif
113 default:
114 /* need to add code for these */
115 case PORT_UNKNOWN:
116 dev_info(&ofdev->dev, "Unknown serial port found, ignored\n");
117 ret = -ENODEV;
118 break;
119 }
120 if (ret < 0)
121 goto out;
122
123 info->type = port_type;
124 info->line = ret;
125 dev_set_drvdata(&ofdev->dev, info);
126 return 0;
127out:
128 kfree(info);
129 irq_dispose_mapping(port.irq);
130 return ret;
131}
132
133/*
134 * Release a line
135 */
136static int of_platform_serial_remove(struct platform_device *ofdev)
137{
138 struct of_serial_info *info = dev_get_drvdata(&ofdev->dev);
139 switch (info->type) {
140#ifdef CONFIG_SERIAL_8250
141 case PORT_8250 ... PORT_MAX_8250:
142 serial8250_unregister_port(info->line);
143 break;
144#endif
145#ifdef CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL
146 case PORT_NWPSERIAL:
147 nwpserial_unregister_port(info->line);
148 break;
149#endif
150 default:
151 /* need to add code for these */
152 break;
153 }
154 kfree(info);
155 return 0;
156}
157
158/*
159 * A few common types, add more as needed.
160 */
161static struct of_device_id __devinitdata of_platform_serial_table[] = {
162 { .type = "serial", .compatible = "ns8250", .data = (void *)PORT_8250, },
163 { .type = "serial", .compatible = "ns16450", .data = (void *)PORT_16450, },
164 { .type = "serial", .compatible = "ns16550a", .data = (void *)PORT_16550A, },
165 { .type = "serial", .compatible = "ns16550", .data = (void *)PORT_16550, },
166 { .type = "serial", .compatible = "ns16750", .data = (void *)PORT_16750, },
167 { .type = "serial", .compatible = "ns16850", .data = (void *)PORT_16850, },
168#ifdef CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL
169 { .type = "serial", .compatible = "ibm,qpace-nwp-serial",
170 .data = (void *)PORT_NWPSERIAL, },
171#endif
172 { .type = "serial", .data = (void *)PORT_UNKNOWN, },
173 { /* end of list */ },
174};
175
176static struct of_platform_driver of_platform_serial_driver = {
177 .driver = {
178 .name = "of_serial",
179 .owner = THIS_MODULE,
180 .of_match_table = of_platform_serial_table,
181 },
182 .probe = of_platform_serial_probe,
183 .remove = of_platform_serial_remove,
184};
185
186static int __init of_platform_serial_init(void)
187{
188 return of_register_platform_driver(&of_platform_serial_driver);
189}
190module_init(of_platform_serial_init);
191
192static void __exit of_platform_serial_exit(void)
193{
194 return of_unregister_platform_driver(&of_platform_serial_driver);
195};
196module_exit(of_platform_serial_exit);
197
198MODULE_AUTHOR("Arnd Bergmann <arnd@arndb.de>");
199MODULE_LICENSE("GPL");
200MODULE_DESCRIPTION("Serial Port driver for Open Firmware platform devices");
diff --git a/drivers/serial/pmac_zilog.c b/drivers/serial/pmac_zilog.c
deleted file mode 100644
index 5b9cde79e4ea..000000000000
--- a/drivers/serial/pmac_zilog.c
+++ /dev/null
@@ -1,2208 +0,0 @@
1/*
2 * linux/drivers/serial/pmac_zilog.c
3 *
4 * Driver for PowerMac Z85c30 based ESCC cell found in the
5 * "macio" ASICs of various PowerMac models
6 *
7 * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org)
8 *
9 * Derived from drivers/macintosh/macserial.c by Paul Mackerras
10 * and drivers/serial/sunzilog.c by David S. Miller
11 *
12 * Hrm... actually, I ripped most of sunzilog (Thanks David !) and
13 * adapted special tweaks needed for us. I don't think it's worth
14 * merging back those though. The DMA code still has to get in
15 * and once done, I expect that driver to remain fairly stable in
16 * the long term, unless we change the driver model again...
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 *
32 * 2004-08-06 Harald Welte <laforge@gnumonks.org>
33 * - Enable BREAK interrupt
34 * - Add support for sysreq
35 *
36 * TODO: - Add DMA support
37 * - Defer port shutdown to a few seconds after close
38 * - maybe put something right into uap->clk_divisor
39 */
40
41#undef DEBUG
42#undef DEBUG_HARD
43#undef USE_CTRL_O_SYSRQ
44
45#include <linux/module.h>
46#include <linux/tty.h>
47
48#include <linux/tty_flip.h>
49#include <linux/major.h>
50#include <linux/string.h>
51#include <linux/fcntl.h>
52#include <linux/mm.h>
53#include <linux/kernel.h>
54#include <linux/delay.h>
55#include <linux/init.h>
56#include <linux/console.h>
57#include <linux/adb.h>
58#include <linux/pmu.h>
59#include <linux/bitops.h>
60#include <linux/sysrq.h>
61#include <linux/mutex.h>
62#include <asm/sections.h>
63#include <asm/io.h>
64#include <asm/irq.h>
65
66#ifdef CONFIG_PPC_PMAC
67#include <asm/prom.h>
68#include <asm/machdep.h>
69#include <asm/pmac_feature.h>
70#include <asm/dbdma.h>
71#include <asm/macio.h>
72#else
73#include <linux/platform_device.h>
74#define of_machine_is_compatible(x) (0)
75#endif
76
77#if defined (CONFIG_SERIAL_PMACZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
78#define SUPPORT_SYSRQ
79#endif
80
81#include <linux/serial.h>
82#include <linux/serial_core.h>
83
84#include "pmac_zilog.h"
85
86/* Not yet implemented */
87#undef HAS_DBDMA
88
89static char version[] __initdata = "pmac_zilog: 0.6 (Benjamin Herrenschmidt <benh@kernel.crashing.org>)";
90MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
91MODULE_DESCRIPTION("Driver for the Mac and PowerMac serial ports.");
92MODULE_LICENSE("GPL");
93
94#ifdef CONFIG_SERIAL_PMACZILOG_TTYS
95#define PMACZILOG_MAJOR TTY_MAJOR
96#define PMACZILOG_MINOR 64
97#define PMACZILOG_NAME "ttyS"
98#else
99#define PMACZILOG_MAJOR 204
100#define PMACZILOG_MINOR 192
101#define PMACZILOG_NAME "ttyPZ"
102#endif
103
104
105/*
106 * For the sake of early serial console, we can do a pre-probe
107 * (optional) of the ports at rather early boot time.
108 */
109static struct uart_pmac_port pmz_ports[MAX_ZS_PORTS];
110static int pmz_ports_count;
111static DEFINE_MUTEX(pmz_irq_mutex);
112
113static struct uart_driver pmz_uart_reg = {
114 .owner = THIS_MODULE,
115 .driver_name = PMACZILOG_NAME,
116 .dev_name = PMACZILOG_NAME,
117 .major = PMACZILOG_MAJOR,
118 .minor = PMACZILOG_MINOR,
119};
120
121
122/*
123 * Load all registers to reprogram the port
124 * This function must only be called when the TX is not busy. The UART
125 * port lock must be held and local interrupts disabled.
126 */
127static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs)
128{
129 int i;
130
131 if (ZS_IS_ASLEEP(uap))
132 return;
133
134 /* Let pending transmits finish. */
135 for (i = 0; i < 1000; i++) {
136 unsigned char stat = read_zsreg(uap, R1);
137 if (stat & ALL_SNT)
138 break;
139 udelay(100);
140 }
141
142 ZS_CLEARERR(uap);
143 zssync(uap);
144 ZS_CLEARFIFO(uap);
145 zssync(uap);
146 ZS_CLEARERR(uap);
147
148 /* Disable all interrupts. */
149 write_zsreg(uap, R1,
150 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
151
152 /* Set parity, sync config, stop bits, and clock divisor. */
153 write_zsreg(uap, R4, regs[R4]);
154
155 /* Set misc. TX/RX control bits. */
156 write_zsreg(uap, R10, regs[R10]);
157
158 /* Set TX/RX controls sans the enable bits. */
159 write_zsreg(uap, R3, regs[R3] & ~RxENABLE);
160 write_zsreg(uap, R5, regs[R5] & ~TxENABLE);
161
162 /* now set R7 "prime" on ESCC */
163 write_zsreg(uap, R15, regs[R15] | EN85C30);
164 write_zsreg(uap, R7, regs[R7P]);
165
166 /* make sure we use R7 "non-prime" on ESCC */
167 write_zsreg(uap, R15, regs[R15] & ~EN85C30);
168
169 /* Synchronous mode config. */
170 write_zsreg(uap, R6, regs[R6]);
171 write_zsreg(uap, R7, regs[R7]);
172
173 /* Disable baud generator. */
174 write_zsreg(uap, R14, regs[R14] & ~BRENAB);
175
176 /* Clock mode control. */
177 write_zsreg(uap, R11, regs[R11]);
178
179 /* Lower and upper byte of baud rate generator divisor. */
180 write_zsreg(uap, R12, regs[R12]);
181 write_zsreg(uap, R13, regs[R13]);
182
183 /* Now rewrite R14, with BRENAB (if set). */
184 write_zsreg(uap, R14, regs[R14]);
185
186 /* Reset external status interrupts. */
187 write_zsreg(uap, R0, RES_EXT_INT);
188 write_zsreg(uap, R0, RES_EXT_INT);
189
190 /* Rewrite R3/R5, this time without enables masked. */
191 write_zsreg(uap, R3, regs[R3]);
192 write_zsreg(uap, R5, regs[R5]);
193
194 /* Rewrite R1, this time without IRQ enabled masked. */
195 write_zsreg(uap, R1, regs[R1]);
196
197 /* Enable interrupts */
198 write_zsreg(uap, R9, regs[R9]);
199}
200
201/*
202 * We do like sunzilog to avoid disrupting pending Tx
203 * Reprogram the Zilog channel HW registers with the copies found in the
204 * software state struct. If the transmitter is busy, we defer this update
205 * until the next TX complete interrupt. Else, we do it right now.
206 *
207 * The UART port lock must be held and local interrupts disabled.
208 */
209static void pmz_maybe_update_regs(struct uart_pmac_port *uap)
210{
211 if (!ZS_REGS_HELD(uap)) {
212 if (ZS_TX_ACTIVE(uap)) {
213 uap->flags |= PMACZILOG_FLAG_REGS_HELD;
214 } else {
215 pmz_debug("pmz: maybe_update_regs: updating\n");
216 pmz_load_zsregs(uap, uap->curregs);
217 }
218 }
219}
220
221static struct tty_struct *pmz_receive_chars(struct uart_pmac_port *uap)
222{
223 struct tty_struct *tty = NULL;
224 unsigned char ch, r1, drop, error, flag;
225 int loops = 0;
226
227 /* The interrupt can be enabled when the port isn't open, typically
228 * that happens when using one port is open and the other closed (stale
229 * interrupt) or when one port is used as a console.
230 */
231 if (!ZS_IS_OPEN(uap)) {
232 pmz_debug("pmz: draining input\n");
233 /* Port is closed, drain input data */
234 for (;;) {
235 if ((++loops) > 1000)
236 goto flood;
237 (void)read_zsreg(uap, R1);
238 write_zsreg(uap, R0, ERR_RES);
239 (void)read_zsdata(uap);
240 ch = read_zsreg(uap, R0);
241 if (!(ch & Rx_CH_AV))
242 break;
243 }
244 return NULL;
245 }
246
247 /* Sanity check, make sure the old bug is no longer happening */
248 if (uap->port.state == NULL || uap->port.state->port.tty == NULL) {
249 WARN_ON(1);
250 (void)read_zsdata(uap);
251 return NULL;
252 }
253 tty = uap->port.state->port.tty;
254
255 while (1) {
256 error = 0;
257 drop = 0;
258
259 r1 = read_zsreg(uap, R1);
260 ch = read_zsdata(uap);
261
262 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
263 write_zsreg(uap, R0, ERR_RES);
264 zssync(uap);
265 }
266
267 ch &= uap->parity_mask;
268 if (ch == 0 && uap->flags & PMACZILOG_FLAG_BREAK) {
269 uap->flags &= ~PMACZILOG_FLAG_BREAK;
270 }
271
272#if defined(CONFIG_MAGIC_SYSRQ) && defined(CONFIG_SERIAL_CORE_CONSOLE)
273#ifdef USE_CTRL_O_SYSRQ
274 /* Handle the SysRq ^O Hack */
275 if (ch == '\x0f') {
276 uap->port.sysrq = jiffies + HZ*5;
277 goto next_char;
278 }
279#endif /* USE_CTRL_O_SYSRQ */
280 if (uap->port.sysrq) {
281 int swallow;
282 spin_unlock(&uap->port.lock);
283 swallow = uart_handle_sysrq_char(&uap->port, ch);
284 spin_lock(&uap->port.lock);
285 if (swallow)
286 goto next_char;
287 }
288#endif /* CONFIG_MAGIC_SYSRQ && CONFIG_SERIAL_CORE_CONSOLE */
289
290 /* A real serial line, record the character and status. */
291 if (drop)
292 goto next_char;
293
294 flag = TTY_NORMAL;
295 uap->port.icount.rx++;
296
297 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | BRK_ABRT)) {
298 error = 1;
299 if (r1 & BRK_ABRT) {
300 pmz_debug("pmz: got break !\n");
301 r1 &= ~(PAR_ERR | CRC_ERR);
302 uap->port.icount.brk++;
303 if (uart_handle_break(&uap->port))
304 goto next_char;
305 }
306 else if (r1 & PAR_ERR)
307 uap->port.icount.parity++;
308 else if (r1 & CRC_ERR)
309 uap->port.icount.frame++;
310 if (r1 & Rx_OVR)
311 uap->port.icount.overrun++;
312 r1 &= uap->port.read_status_mask;
313 if (r1 & BRK_ABRT)
314 flag = TTY_BREAK;
315 else if (r1 & PAR_ERR)
316 flag = TTY_PARITY;
317 else if (r1 & CRC_ERR)
318 flag = TTY_FRAME;
319 }
320
321 if (uap->port.ignore_status_mask == 0xff ||
322 (r1 & uap->port.ignore_status_mask) == 0) {
323 tty_insert_flip_char(tty, ch, flag);
324 }
325 if (r1 & Rx_OVR)
326 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
327 next_char:
328 /* We can get stuck in an infinite loop getting char 0 when the
329 * line is in a wrong HW state, we break that here.
330 * When that happens, I disable the receive side of the driver.
331 * Note that what I've been experiencing is a real irq loop where
332 * I'm getting flooded regardless of the actual port speed.
333 * Something stange is going on with the HW
334 */
335 if ((++loops) > 1000)
336 goto flood;
337 ch = read_zsreg(uap, R0);
338 if (!(ch & Rx_CH_AV))
339 break;
340 }
341
342 return tty;
343 flood:
344 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
345 write_zsreg(uap, R1, uap->curregs[R1]);
346 zssync(uap);
347 pmz_error("pmz: rx irq flood !\n");
348 return tty;
349}
350
351static void pmz_status_handle(struct uart_pmac_port *uap)
352{
353 unsigned char status;
354
355 status = read_zsreg(uap, R0);
356 write_zsreg(uap, R0, RES_EXT_INT);
357 zssync(uap);
358
359 if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) {
360 if (status & SYNC_HUNT)
361 uap->port.icount.dsr++;
362
363 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
364 * But it does not tell us which bit has changed, we have to keep
365 * track of this ourselves.
366 * The CTS input is inverted for some reason. -- paulus
367 */
368 if ((status ^ uap->prev_status) & DCD)
369 uart_handle_dcd_change(&uap->port,
370 (status & DCD));
371 if ((status ^ uap->prev_status) & CTS)
372 uart_handle_cts_change(&uap->port,
373 !(status & CTS));
374
375 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
376 }
377
378 if (status & BRK_ABRT)
379 uap->flags |= PMACZILOG_FLAG_BREAK;
380
381 uap->prev_status = status;
382}
383
384static void pmz_transmit_chars(struct uart_pmac_port *uap)
385{
386 struct circ_buf *xmit;
387
388 if (ZS_IS_ASLEEP(uap))
389 return;
390 if (ZS_IS_CONS(uap)) {
391 unsigned char status = read_zsreg(uap, R0);
392
393 /* TX still busy? Just wait for the next TX done interrupt.
394 *
395 * It can occur because of how we do serial console writes. It would
396 * be nice to transmit console writes just like we normally would for
397 * a TTY line. (ie. buffered and TX interrupt driven). That is not
398 * easy because console writes cannot sleep. One solution might be
399 * to poll on enough port->xmit space becomming free. -DaveM
400 */
401 if (!(status & Tx_BUF_EMP))
402 return;
403 }
404
405 uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE;
406
407 if (ZS_REGS_HELD(uap)) {
408 pmz_load_zsregs(uap, uap->curregs);
409 uap->flags &= ~PMACZILOG_FLAG_REGS_HELD;
410 }
411
412 if (ZS_TX_STOPPED(uap)) {
413 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
414 goto ack_tx_int;
415 }
416
417 /* Under some circumstances, we see interrupts reported for
418 * a closed channel. The interrupt mask in R1 is clear, but
419 * R3 still signals the interrupts and we see them when taking
420 * an interrupt for the other channel (this could be a qemu
421 * bug but since the ESCC doc doesn't specify precsiely whether
422 * R3 interrup status bits are masked by R1 interrupt enable
423 * bits, better safe than sorry). --BenH.
424 */
425 if (!ZS_IS_OPEN(uap))
426 goto ack_tx_int;
427
428 if (uap->port.x_char) {
429 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
430 write_zsdata(uap, uap->port.x_char);
431 zssync(uap);
432 uap->port.icount.tx++;
433 uap->port.x_char = 0;
434 return;
435 }
436
437 if (uap->port.state == NULL)
438 goto ack_tx_int;
439 xmit = &uap->port.state->xmit;
440 if (uart_circ_empty(xmit)) {
441 uart_write_wakeup(&uap->port);
442 goto ack_tx_int;
443 }
444 if (uart_tx_stopped(&uap->port))
445 goto ack_tx_int;
446
447 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
448 write_zsdata(uap, xmit->buf[xmit->tail]);
449 zssync(uap);
450
451 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
452 uap->port.icount.tx++;
453
454 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
455 uart_write_wakeup(&uap->port);
456
457 return;
458
459ack_tx_int:
460 write_zsreg(uap, R0, RES_Tx_P);
461 zssync(uap);
462}
463
464/* Hrm... we register that twice, fixme later.... */
465static irqreturn_t pmz_interrupt(int irq, void *dev_id)
466{
467 struct uart_pmac_port *uap = dev_id;
468 struct uart_pmac_port *uap_a;
469 struct uart_pmac_port *uap_b;
470 int rc = IRQ_NONE;
471 struct tty_struct *tty;
472 u8 r3;
473
474 uap_a = pmz_get_port_A(uap);
475 uap_b = uap_a->mate;
476
477 spin_lock(&uap_a->port.lock);
478 r3 = read_zsreg(uap_a, R3);
479
480#ifdef DEBUG_HARD
481 pmz_debug("irq, r3: %x\n", r3);
482#endif
483 /* Channel A */
484 tty = NULL;
485 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
486 write_zsreg(uap_a, R0, RES_H_IUS);
487 zssync(uap_a);
488 if (r3 & CHAEXT)
489 pmz_status_handle(uap_a);
490 if (r3 & CHARxIP)
491 tty = pmz_receive_chars(uap_a);
492 if (r3 & CHATxIP)
493 pmz_transmit_chars(uap_a);
494 rc = IRQ_HANDLED;
495 }
496 spin_unlock(&uap_a->port.lock);
497 if (tty != NULL)
498 tty_flip_buffer_push(tty);
499
500 if (uap_b->node == NULL)
501 goto out;
502
503 spin_lock(&uap_b->port.lock);
504 tty = NULL;
505 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
506 write_zsreg(uap_b, R0, RES_H_IUS);
507 zssync(uap_b);
508 if (r3 & CHBEXT)
509 pmz_status_handle(uap_b);
510 if (r3 & CHBRxIP)
511 tty = pmz_receive_chars(uap_b);
512 if (r3 & CHBTxIP)
513 pmz_transmit_chars(uap_b);
514 rc = IRQ_HANDLED;
515 }
516 spin_unlock(&uap_b->port.lock);
517 if (tty != NULL)
518 tty_flip_buffer_push(tty);
519
520 out:
521#ifdef DEBUG_HARD
522 pmz_debug("irq done.\n");
523#endif
524 return rc;
525}
526
527/*
528 * Peek the status register, lock not held by caller
529 */
530static inline u8 pmz_peek_status(struct uart_pmac_port *uap)
531{
532 unsigned long flags;
533 u8 status;
534
535 spin_lock_irqsave(&uap->port.lock, flags);
536 status = read_zsreg(uap, R0);
537 spin_unlock_irqrestore(&uap->port.lock, flags);
538
539 return status;
540}
541
542/*
543 * Check if transmitter is empty
544 * The port lock is not held.
545 */
546static unsigned int pmz_tx_empty(struct uart_port *port)
547{
548 struct uart_pmac_port *uap = to_pmz(port);
549 unsigned char status;
550
551 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
552 return TIOCSER_TEMT;
553
554 status = pmz_peek_status(to_pmz(port));
555 if (status & Tx_BUF_EMP)
556 return TIOCSER_TEMT;
557 return 0;
558}
559
560/*
561 * Set Modem Control (RTS & DTR) bits
562 * The port lock is held and interrupts are disabled.
563 * Note: Shall we really filter out RTS on external ports or
564 * should that be dealt at higher level only ?
565 */
566static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl)
567{
568 struct uart_pmac_port *uap = to_pmz(port);
569 unsigned char set_bits, clear_bits;
570
571 /* Do nothing for irda for now... */
572 if (ZS_IS_IRDA(uap))
573 return;
574 /* We get called during boot with a port not up yet */
575 if (ZS_IS_ASLEEP(uap) ||
576 !(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)))
577 return;
578
579 set_bits = clear_bits = 0;
580
581 if (ZS_IS_INTMODEM(uap)) {
582 if (mctrl & TIOCM_RTS)
583 set_bits |= RTS;
584 else
585 clear_bits |= RTS;
586 }
587 if (mctrl & TIOCM_DTR)
588 set_bits |= DTR;
589 else
590 clear_bits |= DTR;
591
592 /* NOTE: Not subject to 'transmitter active' rule. */
593 uap->curregs[R5] |= set_bits;
594 uap->curregs[R5] &= ~clear_bits;
595 if (ZS_IS_ASLEEP(uap))
596 return;
597 write_zsreg(uap, R5, uap->curregs[R5]);
598 pmz_debug("pmz_set_mctrl: set bits: %x, clear bits: %x -> %x\n",
599 set_bits, clear_bits, uap->curregs[R5]);
600 zssync(uap);
601}
602
603/*
604 * Get Modem Control bits (only the input ones, the core will
605 * or that with a cached value of the control ones)
606 * The port lock is held and interrupts are disabled.
607 */
608static unsigned int pmz_get_mctrl(struct uart_port *port)
609{
610 struct uart_pmac_port *uap = to_pmz(port);
611 unsigned char status;
612 unsigned int ret;
613
614 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
615 return 0;
616
617 status = read_zsreg(uap, R0);
618
619 ret = 0;
620 if (status & DCD)
621 ret |= TIOCM_CAR;
622 if (status & SYNC_HUNT)
623 ret |= TIOCM_DSR;
624 if (!(status & CTS))
625 ret |= TIOCM_CTS;
626
627 return ret;
628}
629
630/*
631 * Stop TX side. Dealt like sunzilog at next Tx interrupt,
632 * though for DMA, we will have to do a bit more.
633 * The port lock is held and interrupts are disabled.
634 */
635static void pmz_stop_tx(struct uart_port *port)
636{
637 to_pmz(port)->flags |= PMACZILOG_FLAG_TX_STOPPED;
638}
639
640/*
641 * Kick the Tx side.
642 * The port lock is held and interrupts are disabled.
643 */
644static void pmz_start_tx(struct uart_port *port)
645{
646 struct uart_pmac_port *uap = to_pmz(port);
647 unsigned char status;
648
649 pmz_debug("pmz: start_tx()\n");
650
651 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
652 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
653
654 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
655 return;
656
657 status = read_zsreg(uap, R0);
658
659 /* TX busy? Just wait for the TX done interrupt. */
660 if (!(status & Tx_BUF_EMP))
661 return;
662
663 /* Send the first character to jump-start the TX done
664 * IRQ sending engine.
665 */
666 if (port->x_char) {
667 write_zsdata(uap, port->x_char);
668 zssync(uap);
669 port->icount.tx++;
670 port->x_char = 0;
671 } else {
672 struct circ_buf *xmit = &port->state->xmit;
673
674 write_zsdata(uap, xmit->buf[xmit->tail]);
675 zssync(uap);
676 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
677 port->icount.tx++;
678
679 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
680 uart_write_wakeup(&uap->port);
681 }
682 pmz_debug("pmz: start_tx() done.\n");
683}
684
685/*
686 * Stop Rx side, basically disable emitting of
687 * Rx interrupts on the port. We don't disable the rx
688 * side of the chip proper though
689 * The port lock is held.
690 */
691static void pmz_stop_rx(struct uart_port *port)
692{
693 struct uart_pmac_port *uap = to_pmz(port);
694
695 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
696 return;
697
698 pmz_debug("pmz: stop_rx()()\n");
699
700 /* Disable all RX interrupts. */
701 uap->curregs[R1] &= ~RxINT_MASK;
702 pmz_maybe_update_regs(uap);
703
704 pmz_debug("pmz: stop_rx() done.\n");
705}
706
707/*
708 * Enable modem status change interrupts
709 * The port lock is held.
710 */
711static void pmz_enable_ms(struct uart_port *port)
712{
713 struct uart_pmac_port *uap = to_pmz(port);
714 unsigned char new_reg;
715
716 if (ZS_IS_IRDA(uap) || uap->node == NULL)
717 return;
718 new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
719 if (new_reg != uap->curregs[R15]) {
720 uap->curregs[R15] = new_reg;
721
722 if (ZS_IS_ASLEEP(uap))
723 return;
724 /* NOTE: Not subject to 'transmitter active' rule. */
725 write_zsreg(uap, R15, uap->curregs[R15]);
726 }
727}
728
729/*
730 * Control break state emission
731 * The port lock is not held.
732 */
733static void pmz_break_ctl(struct uart_port *port, int break_state)
734{
735 struct uart_pmac_port *uap = to_pmz(port);
736 unsigned char set_bits, clear_bits, new_reg;
737 unsigned long flags;
738
739 if (uap->node == NULL)
740 return;
741 set_bits = clear_bits = 0;
742
743 if (break_state)
744 set_bits |= SND_BRK;
745 else
746 clear_bits |= SND_BRK;
747
748 spin_lock_irqsave(&port->lock, flags);
749
750 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits;
751 if (new_reg != uap->curregs[R5]) {
752 uap->curregs[R5] = new_reg;
753
754 /* NOTE: Not subject to 'transmitter active' rule. */
755 if (ZS_IS_ASLEEP(uap)) {
756 spin_unlock_irqrestore(&port->lock, flags);
757 return;
758 }
759 write_zsreg(uap, R5, uap->curregs[R5]);
760 }
761
762 spin_unlock_irqrestore(&port->lock, flags);
763}
764
765#ifdef CONFIG_PPC_PMAC
766
767/*
768 * Turn power on or off to the SCC and associated stuff
769 * (port drivers, modem, IR port, etc.)
770 * Returns the number of milliseconds we should wait before
771 * trying to use the port.
772 */
773static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
774{
775 int delay = 0;
776 int rc;
777
778 if (state) {
779 rc = pmac_call_feature(
780 PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1);
781 pmz_debug("port power on result: %d\n", rc);
782 if (ZS_IS_INTMODEM(uap)) {
783 rc = pmac_call_feature(
784 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1);
785 delay = 2500; /* wait for 2.5s before using */
786 pmz_debug("modem power result: %d\n", rc);
787 }
788 } else {
789 /* TODO: Make that depend on a timer, don't power down
790 * immediately
791 */
792 if (ZS_IS_INTMODEM(uap)) {
793 rc = pmac_call_feature(
794 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0);
795 pmz_debug("port power off result: %d\n", rc);
796 }
797 pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0);
798 }
799 return delay;
800}
801
802#else
803
804static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
805{
806 return 0;
807}
808
809#endif /* !CONFIG_PPC_PMAC */
810
811/*
812 * FixZeroBug....Works around a bug in the SCC receving channel.
813 * Inspired from Darwin code, 15 Sept. 2000 -DanM
814 *
815 * The following sequence prevents a problem that is seen with O'Hare ASICs
816 * (most versions -- also with some Heathrow and Hydra ASICs) where a zero
817 * at the input to the receiver becomes 'stuck' and locks up the receiver.
818 * This problem can occur as a result of a zero bit at the receiver input
819 * coincident with any of the following events:
820 *
821 * The SCC is initialized (hardware or software).
822 * A framing error is detected.
823 * The clocking option changes from synchronous or X1 asynchronous
824 * clocking to X16, X32, or X64 asynchronous clocking.
825 * The decoding mode is changed among NRZ, NRZI, FM0, or FM1.
826 *
827 * This workaround attempts to recover from the lockup condition by placing
828 * the SCC in synchronous loopback mode with a fast clock before programming
829 * any of the asynchronous modes.
830 */
831static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap)
832{
833 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
834 zssync(uap);
835 udelay(10);
836 write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV);
837 zssync(uap);
838
839 write_zsreg(uap, 4, X1CLK | MONSYNC);
840 write_zsreg(uap, 3, Rx8);
841 write_zsreg(uap, 5, Tx8 | RTS);
842 write_zsreg(uap, 9, NV); /* Didn't we already do this? */
843 write_zsreg(uap, 11, RCBR | TCBR);
844 write_zsreg(uap, 12, 0);
845 write_zsreg(uap, 13, 0);
846 write_zsreg(uap, 14, (LOOPBAK | BRSRC));
847 write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB));
848 write_zsreg(uap, 3, Rx8 | RxENABLE);
849 write_zsreg(uap, 0, RES_EXT_INT);
850 write_zsreg(uap, 0, RES_EXT_INT);
851 write_zsreg(uap, 0, RES_EXT_INT); /* to kill some time */
852
853 /* The channel should be OK now, but it is probably receiving
854 * loopback garbage.
855 * Switch to asynchronous mode, disable the receiver,
856 * and discard everything in the receive buffer.
857 */
858 write_zsreg(uap, 9, NV);
859 write_zsreg(uap, 4, X16CLK | SB_MASK);
860 write_zsreg(uap, 3, Rx8);
861
862 while (read_zsreg(uap, 0) & Rx_CH_AV) {
863 (void)read_zsreg(uap, 8);
864 write_zsreg(uap, 0, RES_EXT_INT);
865 write_zsreg(uap, 0, ERR_RES);
866 }
867}
868
869/*
870 * Real startup routine, powers up the hardware and sets up
871 * the SCC. Returns a delay in ms where you need to wait before
872 * actually using the port, this is typically the internal modem
873 * powerup delay. This routine expect the lock to be taken.
874 */
875static int __pmz_startup(struct uart_pmac_port *uap)
876{
877 int pwr_delay = 0;
878
879 memset(&uap->curregs, 0, sizeof(uap->curregs));
880
881 /* Power up the SCC & underlying hardware (modem/irda) */
882 pwr_delay = pmz_set_scc_power(uap, 1);
883
884 /* Nice buggy HW ... */
885 pmz_fix_zero_bug_scc(uap);
886
887 /* Reset the channel */
888 uap->curregs[R9] = 0;
889 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
890 zssync(uap);
891 udelay(10);
892 write_zsreg(uap, 9, 0);
893 zssync(uap);
894
895 /* Clear the interrupt registers */
896 write_zsreg(uap, R1, 0);
897 write_zsreg(uap, R0, ERR_RES);
898 write_zsreg(uap, R0, ERR_RES);
899 write_zsreg(uap, R0, RES_H_IUS);
900 write_zsreg(uap, R0, RES_H_IUS);
901
902 /* Setup some valid baud rate */
903 uap->curregs[R4] = X16CLK | SB1;
904 uap->curregs[R3] = Rx8;
905 uap->curregs[R5] = Tx8 | RTS;
906 if (!ZS_IS_IRDA(uap))
907 uap->curregs[R5] |= DTR;
908 uap->curregs[R12] = 0;
909 uap->curregs[R13] = 0;
910 uap->curregs[R14] = BRENAB;
911
912 /* Clear handshaking, enable BREAK interrupts */
913 uap->curregs[R15] = BRKIE;
914
915 /* Master interrupt enable */
916 uap->curregs[R9] |= NV | MIE;
917
918 pmz_load_zsregs(uap, uap->curregs);
919
920 /* Enable receiver and transmitter. */
921 write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE);
922 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE);
923
924 /* Remember status for DCD/CTS changes */
925 uap->prev_status = read_zsreg(uap, R0);
926
927 return pwr_delay;
928}
929
930static void pmz_irda_reset(struct uart_pmac_port *uap)
931{
932 uap->curregs[R5] |= DTR;
933 write_zsreg(uap, R5, uap->curregs[R5]);
934 zssync(uap);
935 mdelay(110);
936 uap->curregs[R5] &= ~DTR;
937 write_zsreg(uap, R5, uap->curregs[R5]);
938 zssync(uap);
939 mdelay(10);
940}
941
942/*
943 * This is the "normal" startup routine, using the above one
944 * wrapped with the lock and doing a schedule delay
945 */
946static int pmz_startup(struct uart_port *port)
947{
948 struct uart_pmac_port *uap = to_pmz(port);
949 unsigned long flags;
950 int pwr_delay = 0;
951
952 pmz_debug("pmz: startup()\n");
953
954 if (ZS_IS_ASLEEP(uap))
955 return -EAGAIN;
956 if (uap->node == NULL)
957 return -ENODEV;
958
959 mutex_lock(&pmz_irq_mutex);
960
961 uap->flags |= PMACZILOG_FLAG_IS_OPEN;
962
963 /* A console is never powered down. Else, power up and
964 * initialize the chip
965 */
966 if (!ZS_IS_CONS(uap)) {
967 spin_lock_irqsave(&port->lock, flags);
968 pwr_delay = __pmz_startup(uap);
969 spin_unlock_irqrestore(&port->lock, flags);
970 }
971
972 pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON;
973 if (request_irq(uap->port.irq, pmz_interrupt, IRQF_SHARED,
974 "SCC", uap)) {
975 pmz_error("Unable to register zs interrupt handler.\n");
976 pmz_set_scc_power(uap, 0);
977 mutex_unlock(&pmz_irq_mutex);
978 return -ENXIO;
979 }
980
981 mutex_unlock(&pmz_irq_mutex);
982
983 /* Right now, we deal with delay by blocking here, I'll be
984 * smarter later on
985 */
986 if (pwr_delay != 0) {
987 pmz_debug("pmz: delaying %d ms\n", pwr_delay);
988 msleep(pwr_delay);
989 }
990
991 /* IrDA reset is done now */
992 if (ZS_IS_IRDA(uap))
993 pmz_irda_reset(uap);
994
995 /* Enable interrupts emission from the chip */
996 spin_lock_irqsave(&port->lock, flags);
997 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
998 if (!ZS_IS_EXTCLK(uap))
999 uap->curregs[R1] |= EXT_INT_ENAB;
1000 write_zsreg(uap, R1, uap->curregs[R1]);
1001 spin_unlock_irqrestore(&port->lock, flags);
1002
1003 pmz_debug("pmz: startup() done.\n");
1004
1005 return 0;
1006}
1007
1008static void pmz_shutdown(struct uart_port *port)
1009{
1010 struct uart_pmac_port *uap = to_pmz(port);
1011 unsigned long flags;
1012
1013 pmz_debug("pmz: shutdown()\n");
1014
1015 if (uap->node == NULL)
1016 return;
1017
1018 mutex_lock(&pmz_irq_mutex);
1019
1020 /* Release interrupt handler */
1021 free_irq(uap->port.irq, uap);
1022
1023 spin_lock_irqsave(&port->lock, flags);
1024
1025 uap->flags &= ~PMACZILOG_FLAG_IS_OPEN;
1026
1027 if (!ZS_IS_OPEN(uap->mate))
1028 pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON;
1029
1030 /* Disable interrupts */
1031 if (!ZS_IS_ASLEEP(uap)) {
1032 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
1033 write_zsreg(uap, R1, uap->curregs[R1]);
1034 zssync(uap);
1035 }
1036
1037 if (ZS_IS_CONS(uap) || ZS_IS_ASLEEP(uap)) {
1038 spin_unlock_irqrestore(&port->lock, flags);
1039 mutex_unlock(&pmz_irq_mutex);
1040 return;
1041 }
1042
1043 /* Disable receiver and transmitter. */
1044 uap->curregs[R3] &= ~RxENABLE;
1045 uap->curregs[R5] &= ~TxENABLE;
1046
1047 /* Disable all interrupts and BRK assertion. */
1048 uap->curregs[R5] &= ~SND_BRK;
1049 pmz_maybe_update_regs(uap);
1050
1051 /* Shut the chip down */
1052 pmz_set_scc_power(uap, 0);
1053
1054 spin_unlock_irqrestore(&port->lock, flags);
1055
1056 mutex_unlock(&pmz_irq_mutex);
1057
1058 pmz_debug("pmz: shutdown() done.\n");
1059}
1060
1061/* Shared by TTY driver and serial console setup. The port lock is held
1062 * and local interrupts are disabled.
1063 */
1064static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag,
1065 unsigned int iflag, unsigned long baud)
1066{
1067 int brg;
1068
1069 /* Switch to external clocking for IrDA high clock rates. That
1070 * code could be re-used for Midi interfaces with different
1071 * multipliers
1072 */
1073 if (baud >= 115200 && ZS_IS_IRDA(uap)) {
1074 uap->curregs[R4] = X1CLK;
1075 uap->curregs[R11] = RCTRxCP | TCTRxCP;
1076 uap->curregs[R14] = 0; /* BRG off */
1077 uap->curregs[R12] = 0;
1078 uap->curregs[R13] = 0;
1079 uap->flags |= PMACZILOG_FLAG_IS_EXTCLK;
1080 } else {
1081 switch (baud) {
1082 case ZS_CLOCK/16: /* 230400 */
1083 uap->curregs[R4] = X16CLK;
1084 uap->curregs[R11] = 0;
1085 uap->curregs[R14] = 0;
1086 break;
1087 case ZS_CLOCK/32: /* 115200 */
1088 uap->curregs[R4] = X32CLK;
1089 uap->curregs[R11] = 0;
1090 uap->curregs[R14] = 0;
1091 break;
1092 default:
1093 uap->curregs[R4] = X16CLK;
1094 uap->curregs[R11] = TCBR | RCBR;
1095 brg = BPS_TO_BRG(baud, ZS_CLOCK / 16);
1096 uap->curregs[R12] = (brg & 255);
1097 uap->curregs[R13] = ((brg >> 8) & 255);
1098 uap->curregs[R14] = BRENAB;
1099 }
1100 uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK;
1101 }
1102
1103 /* Character size, stop bits, and parity. */
1104 uap->curregs[3] &= ~RxN_MASK;
1105 uap->curregs[5] &= ~TxN_MASK;
1106
1107 switch (cflag & CSIZE) {
1108 case CS5:
1109 uap->curregs[3] |= Rx5;
1110 uap->curregs[5] |= Tx5;
1111 uap->parity_mask = 0x1f;
1112 break;
1113 case CS6:
1114 uap->curregs[3] |= Rx6;
1115 uap->curregs[5] |= Tx6;
1116 uap->parity_mask = 0x3f;
1117 break;
1118 case CS7:
1119 uap->curregs[3] |= Rx7;
1120 uap->curregs[5] |= Tx7;
1121 uap->parity_mask = 0x7f;
1122 break;
1123 case CS8:
1124 default:
1125 uap->curregs[3] |= Rx8;
1126 uap->curregs[5] |= Tx8;
1127 uap->parity_mask = 0xff;
1128 break;
1129 };
1130 uap->curregs[4] &= ~(SB_MASK);
1131 if (cflag & CSTOPB)
1132 uap->curregs[4] |= SB2;
1133 else
1134 uap->curregs[4] |= SB1;
1135 if (cflag & PARENB)
1136 uap->curregs[4] |= PAR_ENAB;
1137 else
1138 uap->curregs[4] &= ~PAR_ENAB;
1139 if (!(cflag & PARODD))
1140 uap->curregs[4] |= PAR_EVEN;
1141 else
1142 uap->curregs[4] &= ~PAR_EVEN;
1143
1144 uap->port.read_status_mask = Rx_OVR;
1145 if (iflag & INPCK)
1146 uap->port.read_status_mask |= CRC_ERR | PAR_ERR;
1147 if (iflag & (BRKINT | PARMRK))
1148 uap->port.read_status_mask |= BRK_ABRT;
1149
1150 uap->port.ignore_status_mask = 0;
1151 if (iflag & IGNPAR)
1152 uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
1153 if (iflag & IGNBRK) {
1154 uap->port.ignore_status_mask |= BRK_ABRT;
1155 if (iflag & IGNPAR)
1156 uap->port.ignore_status_mask |= Rx_OVR;
1157 }
1158
1159 if ((cflag & CREAD) == 0)
1160 uap->port.ignore_status_mask = 0xff;
1161}
1162
1163
1164/*
1165 * Set the irda codec on the imac to the specified baud rate.
1166 */
1167static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud)
1168{
1169 u8 cmdbyte;
1170 int t, version;
1171
1172 switch (*baud) {
1173 /* SIR modes */
1174 case 2400:
1175 cmdbyte = 0x53;
1176 break;
1177 case 4800:
1178 cmdbyte = 0x52;
1179 break;
1180 case 9600:
1181 cmdbyte = 0x51;
1182 break;
1183 case 19200:
1184 cmdbyte = 0x50;
1185 break;
1186 case 38400:
1187 cmdbyte = 0x4f;
1188 break;
1189 case 57600:
1190 cmdbyte = 0x4e;
1191 break;
1192 case 115200:
1193 cmdbyte = 0x4d;
1194 break;
1195 /* The FIR modes aren't really supported at this point, how
1196 * do we select the speed ? via the FCR on KeyLargo ?
1197 */
1198 case 1152000:
1199 cmdbyte = 0;
1200 break;
1201 case 4000000:
1202 cmdbyte = 0;
1203 break;
1204 default: /* 9600 */
1205 cmdbyte = 0x51;
1206 *baud = 9600;
1207 break;
1208 }
1209
1210 /* Wait for transmitter to drain */
1211 t = 10000;
1212 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0
1213 || (read_zsreg(uap, R1) & ALL_SNT) == 0) {
1214 if (--t <= 0) {
1215 pmz_error("transmitter didn't drain\n");
1216 return;
1217 }
1218 udelay(10);
1219 }
1220
1221 /* Drain the receiver too */
1222 t = 100;
1223 (void)read_zsdata(uap);
1224 (void)read_zsdata(uap);
1225 (void)read_zsdata(uap);
1226 mdelay(10);
1227 while (read_zsreg(uap, R0) & Rx_CH_AV) {
1228 read_zsdata(uap);
1229 mdelay(10);
1230 if (--t <= 0) {
1231 pmz_error("receiver didn't drain\n");
1232 return;
1233 }
1234 }
1235
1236 /* Switch to command mode */
1237 uap->curregs[R5] |= DTR;
1238 write_zsreg(uap, R5, uap->curregs[R5]);
1239 zssync(uap);
1240 mdelay(1);
1241
1242 /* Switch SCC to 19200 */
1243 pmz_convert_to_zs(uap, CS8, 0, 19200);
1244 pmz_load_zsregs(uap, uap->curregs);
1245 mdelay(1);
1246
1247 /* Write get_version command byte */
1248 write_zsdata(uap, 1);
1249 t = 5000;
1250 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1251 if (--t <= 0) {
1252 pmz_error("irda_setup timed out on get_version byte\n");
1253 goto out;
1254 }
1255 udelay(10);
1256 }
1257 version = read_zsdata(uap);
1258
1259 if (version < 4) {
1260 pmz_info("IrDA: dongle version %d not supported\n", version);
1261 goto out;
1262 }
1263
1264 /* Send speed mode */
1265 write_zsdata(uap, cmdbyte);
1266 t = 5000;
1267 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1268 if (--t <= 0) {
1269 pmz_error("irda_setup timed out on speed mode byte\n");
1270 goto out;
1271 }
1272 udelay(10);
1273 }
1274 t = read_zsdata(uap);
1275 if (t != cmdbyte)
1276 pmz_error("irda_setup speed mode byte = %x (%x)\n", t, cmdbyte);
1277
1278 pmz_info("IrDA setup for %ld bps, dongle version: %d\n",
1279 *baud, version);
1280
1281 (void)read_zsdata(uap);
1282 (void)read_zsdata(uap);
1283 (void)read_zsdata(uap);
1284
1285 out:
1286 /* Switch back to data mode */
1287 uap->curregs[R5] &= ~DTR;
1288 write_zsreg(uap, R5, uap->curregs[R5]);
1289 zssync(uap);
1290
1291 (void)read_zsdata(uap);
1292 (void)read_zsdata(uap);
1293 (void)read_zsdata(uap);
1294}
1295
1296
1297static void __pmz_set_termios(struct uart_port *port, struct ktermios *termios,
1298 struct ktermios *old)
1299{
1300 struct uart_pmac_port *uap = to_pmz(port);
1301 unsigned long baud;
1302
1303 pmz_debug("pmz: set_termios()\n");
1304
1305 if (ZS_IS_ASLEEP(uap))
1306 return;
1307
1308 memcpy(&uap->termios_cache, termios, sizeof(struct ktermios));
1309
1310 /* XXX Check which revs of machines actually allow 1 and 4Mb speeds
1311 * on the IR dongle. Note that the IRTTY driver currently doesn't know
1312 * about the FIR mode and high speed modes. So these are unused. For
1313 * implementing proper support for these, we should probably add some
1314 * DMA as well, at least on the Rx side, which isn't a simple thing
1315 * at this point.
1316 */
1317 if (ZS_IS_IRDA(uap)) {
1318 /* Calc baud rate */
1319 baud = uart_get_baud_rate(port, termios, old, 1200, 4000000);
1320 pmz_debug("pmz: switch IRDA to %ld bauds\n", baud);
1321 /* Cet the irda codec to the right rate */
1322 pmz_irda_setup(uap, &baud);
1323 /* Set final baud rate */
1324 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1325 pmz_load_zsregs(uap, uap->curregs);
1326 zssync(uap);
1327 } else {
1328 baud = uart_get_baud_rate(port, termios, old, 1200, 230400);
1329 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1330 /* Make sure modem status interrupts are correctly configured */
1331 if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) {
1332 uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE;
1333 uap->flags |= PMACZILOG_FLAG_MODEM_STATUS;
1334 } else {
1335 uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE);
1336 uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS;
1337 }
1338
1339 /* Load registers to the chip */
1340 pmz_maybe_update_regs(uap);
1341 }
1342 uart_update_timeout(port, termios->c_cflag, baud);
1343
1344 pmz_debug("pmz: set_termios() done.\n");
1345}
1346
1347/* The port lock is not held. */
1348static void pmz_set_termios(struct uart_port *port, struct ktermios *termios,
1349 struct ktermios *old)
1350{
1351 struct uart_pmac_port *uap = to_pmz(port);
1352 unsigned long flags;
1353
1354 spin_lock_irqsave(&port->lock, flags);
1355
1356 /* Disable IRQs on the port */
1357 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
1358 write_zsreg(uap, R1, uap->curregs[R1]);
1359
1360 /* Setup new port configuration */
1361 __pmz_set_termios(port, termios, old);
1362
1363 /* Re-enable IRQs on the port */
1364 if (ZS_IS_OPEN(uap)) {
1365 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
1366 if (!ZS_IS_EXTCLK(uap))
1367 uap->curregs[R1] |= EXT_INT_ENAB;
1368 write_zsreg(uap, R1, uap->curregs[R1]);
1369 }
1370 spin_unlock_irqrestore(&port->lock, flags);
1371}
1372
1373static const char *pmz_type(struct uart_port *port)
1374{
1375 struct uart_pmac_port *uap = to_pmz(port);
1376
1377 if (ZS_IS_IRDA(uap))
1378 return "Z85c30 ESCC - Infrared port";
1379 else if (ZS_IS_INTMODEM(uap))
1380 return "Z85c30 ESCC - Internal modem";
1381 return "Z85c30 ESCC - Serial port";
1382}
1383
1384/* We do not request/release mappings of the registers here, this
1385 * happens at early serial probe time.
1386 */
1387static void pmz_release_port(struct uart_port *port)
1388{
1389}
1390
1391static int pmz_request_port(struct uart_port *port)
1392{
1393 return 0;
1394}
1395
1396/* These do not need to do anything interesting either. */
1397static void pmz_config_port(struct uart_port *port, int flags)
1398{
1399}
1400
1401/* We do not support letting the user mess with the divisor, IRQ, etc. */
1402static int pmz_verify_port(struct uart_port *port, struct serial_struct *ser)
1403{
1404 return -EINVAL;
1405}
1406
1407#ifdef CONFIG_CONSOLE_POLL
1408
1409static int pmz_poll_get_char(struct uart_port *port)
1410{
1411 struct uart_pmac_port *uap = (struct uart_pmac_port *)port;
1412
1413 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0)
1414 udelay(5);
1415 return read_zsdata(uap);
1416}
1417
1418static void pmz_poll_put_char(struct uart_port *port, unsigned char c)
1419{
1420 struct uart_pmac_port *uap = (struct uart_pmac_port *)port;
1421
1422 /* Wait for the transmit buffer to empty. */
1423 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
1424 udelay(5);
1425 write_zsdata(uap, c);
1426}
1427
1428#endif /* CONFIG_CONSOLE_POLL */
1429
1430static struct uart_ops pmz_pops = {
1431 .tx_empty = pmz_tx_empty,
1432 .set_mctrl = pmz_set_mctrl,
1433 .get_mctrl = pmz_get_mctrl,
1434 .stop_tx = pmz_stop_tx,
1435 .start_tx = pmz_start_tx,
1436 .stop_rx = pmz_stop_rx,
1437 .enable_ms = pmz_enable_ms,
1438 .break_ctl = pmz_break_ctl,
1439 .startup = pmz_startup,
1440 .shutdown = pmz_shutdown,
1441 .set_termios = pmz_set_termios,
1442 .type = pmz_type,
1443 .release_port = pmz_release_port,
1444 .request_port = pmz_request_port,
1445 .config_port = pmz_config_port,
1446 .verify_port = pmz_verify_port,
1447#ifdef CONFIG_CONSOLE_POLL
1448 .poll_get_char = pmz_poll_get_char,
1449 .poll_put_char = pmz_poll_put_char,
1450#endif
1451};
1452
1453#ifdef CONFIG_PPC_PMAC
1454
1455/*
1456 * Setup one port structure after probing, HW is down at this point,
1457 * Unlike sunzilog, we don't need to pre-init the spinlock as we don't
1458 * register our console before uart_add_one_port() is called
1459 */
1460static int __init pmz_init_port(struct uart_pmac_port *uap)
1461{
1462 struct device_node *np = uap->node;
1463 const char *conn;
1464 const struct slot_names_prop {
1465 int count;
1466 char name[1];
1467 } *slots;
1468 int len;
1469 struct resource r_ports, r_rxdma, r_txdma;
1470
1471 /*
1472 * Request & map chip registers
1473 */
1474 if (of_address_to_resource(np, 0, &r_ports))
1475 return -ENODEV;
1476 uap->port.mapbase = r_ports.start;
1477 uap->port.membase = ioremap(uap->port.mapbase, 0x1000);
1478
1479 uap->control_reg = uap->port.membase;
1480 uap->data_reg = uap->control_reg + 0x10;
1481
1482 /*
1483 * Request & map DBDMA registers
1484 */
1485#ifdef HAS_DBDMA
1486 if (of_address_to_resource(np, 1, &r_txdma) == 0 &&
1487 of_address_to_resource(np, 2, &r_rxdma) == 0)
1488 uap->flags |= PMACZILOG_FLAG_HAS_DMA;
1489#else
1490 memset(&r_txdma, 0, sizeof(struct resource));
1491 memset(&r_rxdma, 0, sizeof(struct resource));
1492#endif
1493 if (ZS_HAS_DMA(uap)) {
1494 uap->tx_dma_regs = ioremap(r_txdma.start, 0x100);
1495 if (uap->tx_dma_regs == NULL) {
1496 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
1497 goto no_dma;
1498 }
1499 uap->rx_dma_regs = ioremap(r_rxdma.start, 0x100);
1500 if (uap->rx_dma_regs == NULL) {
1501 iounmap(uap->tx_dma_regs);
1502 uap->tx_dma_regs = NULL;
1503 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
1504 goto no_dma;
1505 }
1506 uap->tx_dma_irq = irq_of_parse_and_map(np, 1);
1507 uap->rx_dma_irq = irq_of_parse_and_map(np, 2);
1508 }
1509no_dma:
1510
1511 /*
1512 * Detect port type
1513 */
1514 if (of_device_is_compatible(np, "cobalt"))
1515 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1516 conn = of_get_property(np, "AAPL,connector", &len);
1517 if (conn && (strcmp(conn, "infrared") == 0))
1518 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1519 uap->port_type = PMAC_SCC_ASYNC;
1520 /* 1999 Powerbook G3 has slot-names property instead */
1521 slots = of_get_property(np, "slot-names", &len);
1522 if (slots && slots->count > 0) {
1523 if (strcmp(slots->name, "IrDA") == 0)
1524 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1525 else if (strcmp(slots->name, "Modem") == 0)
1526 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1527 }
1528 if (ZS_IS_IRDA(uap))
1529 uap->port_type = PMAC_SCC_IRDA;
1530 if (ZS_IS_INTMODEM(uap)) {
1531 struct device_node* i2c_modem =
1532 of_find_node_by_name(NULL, "i2c-modem");
1533 if (i2c_modem) {
1534 const char* mid =
1535 of_get_property(i2c_modem, "modem-id", NULL);
1536 if (mid) switch(*mid) {
1537 case 0x04 :
1538 case 0x05 :
1539 case 0x07 :
1540 case 0x08 :
1541 case 0x0b :
1542 case 0x0c :
1543 uap->port_type = PMAC_SCC_I2S1;
1544 }
1545 printk(KERN_INFO "pmac_zilog: i2c-modem detected, id: %d\n",
1546 mid ? (*mid) : 0);
1547 of_node_put(i2c_modem);
1548 } else {
1549 printk(KERN_INFO "pmac_zilog: serial modem detected\n");
1550 }
1551 }
1552
1553 /*
1554 * Init remaining bits of "port" structure
1555 */
1556 uap->port.iotype = UPIO_MEM;
1557 uap->port.irq = irq_of_parse_and_map(np, 0);
1558 uap->port.uartclk = ZS_CLOCK;
1559 uap->port.fifosize = 1;
1560 uap->port.ops = &pmz_pops;
1561 uap->port.type = PORT_PMAC_ZILOG;
1562 uap->port.flags = 0;
1563
1564 /*
1565 * Fixup for the port on Gatwick for which the device-tree has
1566 * missing interrupts. Normally, the macio_dev would contain
1567 * fixed up interrupt info, but we use the device-tree directly
1568 * here due to early probing so we need the fixup too.
1569 */
1570 if (uap->port.irq == NO_IRQ &&
1571 np->parent && np->parent->parent &&
1572 of_device_is_compatible(np->parent->parent, "gatwick")) {
1573 /* IRQs on gatwick are offset by 64 */
1574 uap->port.irq = irq_create_mapping(NULL, 64 + 15);
1575 uap->tx_dma_irq = irq_create_mapping(NULL, 64 + 4);
1576 uap->rx_dma_irq = irq_create_mapping(NULL, 64 + 5);
1577 }
1578
1579 /* Setup some valid baud rate information in the register
1580 * shadows so we don't write crap there before baud rate is
1581 * first initialized.
1582 */
1583 pmz_convert_to_zs(uap, CS8, 0, 9600);
1584
1585 return 0;
1586}
1587
1588/*
1589 * Get rid of a port on module removal
1590 */
1591static void pmz_dispose_port(struct uart_pmac_port *uap)
1592{
1593 struct device_node *np;
1594
1595 np = uap->node;
1596 iounmap(uap->rx_dma_regs);
1597 iounmap(uap->tx_dma_regs);
1598 iounmap(uap->control_reg);
1599 uap->node = NULL;
1600 of_node_put(np);
1601 memset(uap, 0, sizeof(struct uart_pmac_port));
1602}
1603
1604/*
1605 * Called upon match with an escc node in the device-tree.
1606 */
1607static int pmz_attach(struct macio_dev *mdev, const struct of_device_id *match)
1608{
1609 int i;
1610
1611 /* Iterate the pmz_ports array to find a matching entry
1612 */
1613 for (i = 0; i < MAX_ZS_PORTS; i++)
1614 if (pmz_ports[i].node == mdev->ofdev.dev.of_node) {
1615 struct uart_pmac_port *uap = &pmz_ports[i];
1616
1617 uap->dev = mdev;
1618 dev_set_drvdata(&mdev->ofdev.dev, uap);
1619 if (macio_request_resources(uap->dev, "pmac_zilog"))
1620 printk(KERN_WARNING "%s: Failed to request resource"
1621 ", port still active\n",
1622 uap->node->name);
1623 else
1624 uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED;
1625 return 0;
1626 }
1627 return -ENODEV;
1628}
1629
1630/*
1631 * That one should not be called, macio isn't really a hotswap device,
1632 * we don't expect one of those serial ports to go away...
1633 */
1634static int pmz_detach(struct macio_dev *mdev)
1635{
1636 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1637
1638 if (!uap)
1639 return -ENODEV;
1640
1641 if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) {
1642 macio_release_resources(uap->dev);
1643 uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED;
1644 }
1645 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1646 uap->dev = NULL;
1647
1648 return 0;
1649}
1650
1651
1652static int pmz_suspend(struct macio_dev *mdev, pm_message_t pm_state)
1653{
1654 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1655 struct uart_state *state;
1656 unsigned long flags;
1657
1658 if (uap == NULL) {
1659 printk("HRM... pmz_suspend with NULL uap\n");
1660 return 0;
1661 }
1662
1663 if (pm_state.event == mdev->ofdev.dev.power.power_state.event)
1664 return 0;
1665
1666 pmz_debug("suspend, switching to state %d\n", pm_state.event);
1667
1668 state = pmz_uart_reg.state + uap->port.line;
1669
1670 mutex_lock(&pmz_irq_mutex);
1671 mutex_lock(&state->port.mutex);
1672
1673 spin_lock_irqsave(&uap->port.lock, flags);
1674
1675 if (ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)) {
1676 /* Disable receiver and transmitter. */
1677 uap->curregs[R3] &= ~RxENABLE;
1678 uap->curregs[R5] &= ~TxENABLE;
1679
1680 /* Disable all interrupts and BRK assertion. */
1681 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
1682 uap->curregs[R5] &= ~SND_BRK;
1683 pmz_load_zsregs(uap, uap->curregs);
1684 uap->flags |= PMACZILOG_FLAG_IS_ASLEEP;
1685 mb();
1686 }
1687
1688 spin_unlock_irqrestore(&uap->port.lock, flags);
1689
1690 if (ZS_IS_OPEN(uap) || ZS_IS_OPEN(uap->mate))
1691 if (ZS_IS_ASLEEP(uap->mate) && ZS_IS_IRQ_ON(pmz_get_port_A(uap))) {
1692 pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON;
1693 disable_irq(uap->port.irq);
1694 }
1695
1696 if (ZS_IS_CONS(uap))
1697 uap->port.cons->flags &= ~CON_ENABLED;
1698
1699 /* Shut the chip down */
1700 pmz_set_scc_power(uap, 0);
1701
1702 mutex_unlock(&state->port.mutex);
1703 mutex_unlock(&pmz_irq_mutex);
1704
1705 pmz_debug("suspend, switching complete\n");
1706
1707 mdev->ofdev.dev.power.power_state = pm_state;
1708
1709 return 0;
1710}
1711
1712
1713static int pmz_resume(struct macio_dev *mdev)
1714{
1715 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1716 struct uart_state *state;
1717 unsigned long flags;
1718 int pwr_delay = 0;
1719
1720 if (uap == NULL)
1721 return 0;
1722
1723 if (mdev->ofdev.dev.power.power_state.event == PM_EVENT_ON)
1724 return 0;
1725
1726 pmz_debug("resume, switching to state 0\n");
1727
1728 state = pmz_uart_reg.state + uap->port.line;
1729
1730 mutex_lock(&pmz_irq_mutex);
1731 mutex_lock(&state->port.mutex);
1732
1733 spin_lock_irqsave(&uap->port.lock, flags);
1734 if (!ZS_IS_OPEN(uap) && !ZS_IS_CONS(uap)) {
1735 spin_unlock_irqrestore(&uap->port.lock, flags);
1736 goto bail;
1737 }
1738 pwr_delay = __pmz_startup(uap);
1739
1740 /* Take care of config that may have changed while asleep */
1741 __pmz_set_termios(&uap->port, &uap->termios_cache, NULL);
1742
1743 if (ZS_IS_OPEN(uap)) {
1744 /* Enable interrupts */
1745 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
1746 if (!ZS_IS_EXTCLK(uap))
1747 uap->curregs[R1] |= EXT_INT_ENAB;
1748 write_zsreg(uap, R1, uap->curregs[R1]);
1749 }
1750
1751 spin_unlock_irqrestore(&uap->port.lock, flags);
1752
1753 if (ZS_IS_CONS(uap))
1754 uap->port.cons->flags |= CON_ENABLED;
1755
1756 /* Re-enable IRQ on the controller */
1757 if (ZS_IS_OPEN(uap) && !ZS_IS_IRQ_ON(pmz_get_port_A(uap))) {
1758 pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON;
1759 enable_irq(uap->port.irq);
1760 }
1761
1762 bail:
1763 mutex_unlock(&state->port.mutex);
1764 mutex_unlock(&pmz_irq_mutex);
1765
1766 /* Right now, we deal with delay by blocking here, I'll be
1767 * smarter later on
1768 */
1769 if (pwr_delay != 0) {
1770 pmz_debug("pmz: delaying %d ms\n", pwr_delay);
1771 msleep(pwr_delay);
1772 }
1773
1774 pmz_debug("resume, switching complete\n");
1775
1776 mdev->ofdev.dev.power.power_state.event = PM_EVENT_ON;
1777
1778 return 0;
1779}
1780
1781/*
1782 * Probe all ports in the system and build the ports array, we register
1783 * with the serial layer at this point, the macio-type probing is only
1784 * used later to "attach" to the sysfs tree so we get power management
1785 * events
1786 */
1787static int __init pmz_probe(void)
1788{
1789 struct device_node *node_p, *node_a, *node_b, *np;
1790 int count = 0;
1791 int rc;
1792
1793 /*
1794 * Find all escc chips in the system
1795 */
1796 node_p = of_find_node_by_name(NULL, "escc");
1797 while (node_p) {
1798 /*
1799 * First get channel A/B node pointers
1800 *
1801 * TODO: Add routines with proper locking to do that...
1802 */
1803 node_a = node_b = NULL;
1804 for (np = NULL; (np = of_get_next_child(node_p, np)) != NULL;) {
1805 if (strncmp(np->name, "ch-a", 4) == 0)
1806 node_a = of_node_get(np);
1807 else if (strncmp(np->name, "ch-b", 4) == 0)
1808 node_b = of_node_get(np);
1809 }
1810 if (!node_a && !node_b) {
1811 of_node_put(node_a);
1812 of_node_put(node_b);
1813 printk(KERN_ERR "pmac_zilog: missing node %c for escc %s\n",
1814 (!node_a) ? 'a' : 'b', node_p->full_name);
1815 goto next;
1816 }
1817
1818 /*
1819 * Fill basic fields in the port structures
1820 */
1821 pmz_ports[count].mate = &pmz_ports[count+1];
1822 pmz_ports[count+1].mate = &pmz_ports[count];
1823 pmz_ports[count].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
1824 pmz_ports[count].node = node_a;
1825 pmz_ports[count+1].node = node_b;
1826 pmz_ports[count].port.line = count;
1827 pmz_ports[count+1].port.line = count+1;
1828
1829 /*
1830 * Setup the ports for real
1831 */
1832 rc = pmz_init_port(&pmz_ports[count]);
1833 if (rc == 0 && node_b != NULL)
1834 rc = pmz_init_port(&pmz_ports[count+1]);
1835 if (rc != 0) {
1836 of_node_put(node_a);
1837 of_node_put(node_b);
1838 memset(&pmz_ports[count], 0, sizeof(struct uart_pmac_port));
1839 memset(&pmz_ports[count+1], 0, sizeof(struct uart_pmac_port));
1840 goto next;
1841 }
1842 count += 2;
1843next:
1844 node_p = of_find_node_by_name(node_p, "escc");
1845 }
1846 pmz_ports_count = count;
1847
1848 return 0;
1849}
1850
1851#else
1852
1853extern struct platform_device scc_a_pdev, scc_b_pdev;
1854
1855static int __init pmz_init_port(struct uart_pmac_port *uap)
1856{
1857 struct resource *r_ports;
1858 int irq;
1859
1860 r_ports = platform_get_resource(uap->node, IORESOURCE_MEM, 0);
1861 irq = platform_get_irq(uap->node, 0);
1862 if (!r_ports || !irq)
1863 return -ENODEV;
1864
1865 uap->port.mapbase = r_ports->start;
1866 uap->port.membase = (unsigned char __iomem *) r_ports->start;
1867 uap->port.iotype = UPIO_MEM;
1868 uap->port.irq = irq;
1869 uap->port.uartclk = ZS_CLOCK;
1870 uap->port.fifosize = 1;
1871 uap->port.ops = &pmz_pops;
1872 uap->port.type = PORT_PMAC_ZILOG;
1873 uap->port.flags = 0;
1874
1875 uap->control_reg = uap->port.membase;
1876 uap->data_reg = uap->control_reg + 4;
1877 uap->port_type = 0;
1878
1879 pmz_convert_to_zs(uap, CS8, 0, 9600);
1880
1881 return 0;
1882}
1883
1884static int __init pmz_probe(void)
1885{
1886 int err;
1887
1888 pmz_ports_count = 0;
1889
1890 pmz_ports[0].mate = &pmz_ports[1];
1891 pmz_ports[0].port.line = 0;
1892 pmz_ports[0].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
1893 pmz_ports[0].node = &scc_a_pdev;
1894 err = pmz_init_port(&pmz_ports[0]);
1895 if (err)
1896 return err;
1897 pmz_ports_count++;
1898
1899 pmz_ports[1].mate = &pmz_ports[0];
1900 pmz_ports[1].port.line = 1;
1901 pmz_ports[1].flags = 0;
1902 pmz_ports[1].node = &scc_b_pdev;
1903 err = pmz_init_port(&pmz_ports[1]);
1904 if (err)
1905 return err;
1906 pmz_ports_count++;
1907
1908 return 0;
1909}
1910
1911static void pmz_dispose_port(struct uart_pmac_port *uap)
1912{
1913 memset(uap, 0, sizeof(struct uart_pmac_port));
1914}
1915
1916static int __init pmz_attach(struct platform_device *pdev)
1917{
1918 int i;
1919
1920 for (i = 0; i < pmz_ports_count; i++)
1921 if (pmz_ports[i].node == pdev)
1922 return 0;
1923 return -ENODEV;
1924}
1925
1926static int __exit pmz_detach(struct platform_device *pdev)
1927{
1928 return 0;
1929}
1930
1931#endif /* !CONFIG_PPC_PMAC */
1932
1933#ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
1934
1935static void pmz_console_write(struct console *con, const char *s, unsigned int count);
1936static int __init pmz_console_setup(struct console *co, char *options);
1937
1938static struct console pmz_console = {
1939 .name = PMACZILOG_NAME,
1940 .write = pmz_console_write,
1941 .device = uart_console_device,
1942 .setup = pmz_console_setup,
1943 .flags = CON_PRINTBUFFER,
1944 .index = -1,
1945 .data = &pmz_uart_reg,
1946};
1947
1948#define PMACZILOG_CONSOLE &pmz_console
1949#else /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1950#define PMACZILOG_CONSOLE (NULL)
1951#endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1952
1953/*
1954 * Register the driver, console driver and ports with the serial
1955 * core
1956 */
1957static int __init pmz_register(void)
1958{
1959 int i, rc;
1960
1961 pmz_uart_reg.nr = pmz_ports_count;
1962 pmz_uart_reg.cons = PMACZILOG_CONSOLE;
1963
1964 /*
1965 * Register this driver with the serial core
1966 */
1967 rc = uart_register_driver(&pmz_uart_reg);
1968 if (rc)
1969 return rc;
1970
1971 /*
1972 * Register each port with the serial core
1973 */
1974 for (i = 0; i < pmz_ports_count; i++) {
1975 struct uart_pmac_port *uport = &pmz_ports[i];
1976 /* NULL node may happen on wallstreet */
1977 if (uport->node != NULL)
1978 rc = uart_add_one_port(&pmz_uart_reg, &uport->port);
1979 if (rc)
1980 goto err_out;
1981 }
1982
1983 return 0;
1984err_out:
1985 while (i-- > 0) {
1986 struct uart_pmac_port *uport = &pmz_ports[i];
1987 uart_remove_one_port(&pmz_uart_reg, &uport->port);
1988 }
1989 uart_unregister_driver(&pmz_uart_reg);
1990 return rc;
1991}
1992
1993#ifdef CONFIG_PPC_PMAC
1994
1995static struct of_device_id pmz_match[] =
1996{
1997 {
1998 .name = "ch-a",
1999 },
2000 {
2001 .name = "ch-b",
2002 },
2003 {},
2004};
2005MODULE_DEVICE_TABLE (of, pmz_match);
2006
2007static struct macio_driver pmz_driver = {
2008 .driver = {
2009 .name = "pmac_zilog",
2010 .owner = THIS_MODULE,
2011 .of_match_table = pmz_match,
2012 },
2013 .probe = pmz_attach,
2014 .remove = pmz_detach,
2015 .suspend = pmz_suspend,
2016 .resume = pmz_resume,
2017};
2018
2019#else
2020
2021static struct platform_driver pmz_driver = {
2022 .remove = __exit_p(pmz_detach),
2023 .driver = {
2024 .name = "scc",
2025 .owner = THIS_MODULE,
2026 },
2027};
2028
2029#endif /* !CONFIG_PPC_PMAC */
2030
2031static int __init init_pmz(void)
2032{
2033 int rc, i;
2034 printk(KERN_INFO "%s\n", version);
2035
2036 /*
2037 * First, we need to do a direct OF-based probe pass. We
2038 * do that because we want serial console up before the
2039 * macio stuffs calls us back, and since that makes it
2040 * easier to pass the proper number of channels to
2041 * uart_register_driver()
2042 */
2043 if (pmz_ports_count == 0)
2044 pmz_probe();
2045
2046 /*
2047 * Bail early if no port found
2048 */
2049 if (pmz_ports_count == 0)
2050 return -ENODEV;
2051
2052 /*
2053 * Now we register with the serial layer
2054 */
2055 rc = pmz_register();
2056 if (rc) {
2057 printk(KERN_ERR
2058 "pmac_zilog: Error registering serial device, disabling pmac_zilog.\n"
2059 "pmac_zilog: Did another serial driver already claim the minors?\n");
2060 /* effectively "pmz_unprobe()" */
2061 for (i=0; i < pmz_ports_count; i++)
2062 pmz_dispose_port(&pmz_ports[i]);
2063 return rc;
2064 }
2065
2066 /*
2067 * Then we register the macio driver itself
2068 */
2069#ifdef CONFIG_PPC_PMAC
2070 return macio_register_driver(&pmz_driver);
2071#else
2072 return platform_driver_probe(&pmz_driver, pmz_attach);
2073#endif
2074}
2075
2076static void __exit exit_pmz(void)
2077{
2078 int i;
2079
2080#ifdef CONFIG_PPC_PMAC
2081 /* Get rid of macio-driver (detach from macio) */
2082 macio_unregister_driver(&pmz_driver);
2083#else
2084 platform_driver_unregister(&pmz_driver);
2085#endif
2086
2087 for (i = 0; i < pmz_ports_count; i++) {
2088 struct uart_pmac_port *uport = &pmz_ports[i];
2089 if (uport->node != NULL) {
2090 uart_remove_one_port(&pmz_uart_reg, &uport->port);
2091 pmz_dispose_port(uport);
2092 }
2093 }
2094 /* Unregister UART driver */
2095 uart_unregister_driver(&pmz_uart_reg);
2096}
2097
2098#ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
2099
2100static void pmz_console_putchar(struct uart_port *port, int ch)
2101{
2102 struct uart_pmac_port *uap = (struct uart_pmac_port *)port;
2103
2104 /* Wait for the transmit buffer to empty. */
2105 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
2106 udelay(5);
2107 write_zsdata(uap, ch);
2108}
2109
2110/*
2111 * Print a string to the serial port trying not to disturb
2112 * any possible real use of the port...
2113 */
2114static void pmz_console_write(struct console *con, const char *s, unsigned int count)
2115{
2116 struct uart_pmac_port *uap = &pmz_ports[con->index];
2117 unsigned long flags;
2118
2119 if (ZS_IS_ASLEEP(uap))
2120 return;
2121 spin_lock_irqsave(&uap->port.lock, flags);
2122
2123 /* Turn of interrupts and enable the transmitter. */
2124 write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB);
2125 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR);
2126
2127 uart_console_write(&uap->port, s, count, pmz_console_putchar);
2128
2129 /* Restore the values in the registers. */
2130 write_zsreg(uap, R1, uap->curregs[1]);
2131 /* Don't disable the transmitter. */
2132
2133 spin_unlock_irqrestore(&uap->port.lock, flags);
2134}
2135
2136/*
2137 * Setup the serial console
2138 */
2139static int __init pmz_console_setup(struct console *co, char *options)
2140{
2141 struct uart_pmac_port *uap;
2142 struct uart_port *port;
2143 int baud = 38400;
2144 int bits = 8;
2145 int parity = 'n';
2146 int flow = 'n';
2147 unsigned long pwr_delay;
2148
2149 /*
2150 * XServe's default to 57600 bps
2151 */
2152 if (of_machine_is_compatible("RackMac1,1")
2153 || of_machine_is_compatible("RackMac1,2")
2154 || of_machine_is_compatible("MacRISC4"))
2155 baud = 57600;
2156
2157 /*
2158 * Check whether an invalid uart number has been specified, and
2159 * if so, search for the first available port that does have
2160 * console support.
2161 */
2162 if (co->index >= pmz_ports_count)
2163 co->index = 0;
2164 uap = &pmz_ports[co->index];
2165 if (uap->node == NULL)
2166 return -ENODEV;
2167 port = &uap->port;
2168
2169 /*
2170 * Mark port as beeing a console
2171 */
2172 uap->flags |= PMACZILOG_FLAG_IS_CONS;
2173
2174 /*
2175 * Temporary fix for uart layer who didn't setup the spinlock yet
2176 */
2177 spin_lock_init(&port->lock);
2178
2179 /*
2180 * Enable the hardware
2181 */
2182 pwr_delay = __pmz_startup(uap);
2183 if (pwr_delay)
2184 mdelay(pwr_delay);
2185
2186 if (options)
2187 uart_parse_options(options, &baud, &parity, &bits, &flow);
2188
2189 return uart_set_options(port, co, baud, parity, bits, flow);
2190}
2191
2192static int __init pmz_console_init(void)
2193{
2194 /* Probe ports */
2195 pmz_probe();
2196
2197 /* TODO: Autoprobe console based on OF */
2198 /* pmz_console.index = i; */
2199 register_console(&pmz_console);
2200
2201 return 0;
2202
2203}
2204console_initcall(pmz_console_init);
2205#endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
2206
2207module_init(init_pmz);
2208module_exit(exit_pmz);
diff --git a/drivers/serial/pmac_zilog.h b/drivers/serial/pmac_zilog.h
deleted file mode 100644
index cbc34fbb1b20..000000000000
--- a/drivers/serial/pmac_zilog.h
+++ /dev/null
@@ -1,396 +0,0 @@
1#ifndef __PMAC_ZILOG_H__
2#define __PMAC_ZILOG_H__
3
4#ifdef CONFIG_PPC_PMAC
5#define pmz_debug(fmt, arg...) dev_dbg(&uap->dev->ofdev.dev, fmt, ## arg)
6#define pmz_error(fmt, arg...) dev_err(&uap->dev->ofdev.dev, fmt, ## arg)
7#define pmz_info(fmt, arg...) dev_info(&uap->dev->ofdev.dev, fmt, ## arg)
8#else
9#define pmz_debug(fmt, arg...) dev_dbg(&uap->node->dev, fmt, ## arg)
10#define pmz_error(fmt, arg...) dev_err(&uap->node->dev, fmt, ## arg)
11#define pmz_info(fmt, arg...) dev_info(&uap->node->dev, fmt, ## arg)
12#endif
13
14/*
15 * At most 2 ESCCs with 2 ports each
16 */
17#define MAX_ZS_PORTS 4
18
19/*
20 * We wrap our port structure around the generic uart_port.
21 */
22#define NUM_ZSREGS 17
23
24struct uart_pmac_port {
25 struct uart_port port;
26 struct uart_pmac_port *mate;
27
28#ifdef CONFIG_PPC_PMAC
29 /* macio_dev for the escc holding this port (maybe be null on
30 * early inited port)
31 */
32 struct macio_dev *dev;
33 /* device node to this port, this points to one of 2 childs
34 * of "escc" node (ie. ch-a or ch-b)
35 */
36 struct device_node *node;
37#else
38 struct platform_device *node;
39#endif
40
41 /* Port type as obtained from device tree (IRDA, modem, ...) */
42 int port_type;
43 u8 curregs[NUM_ZSREGS];
44
45 unsigned int flags;
46#define PMACZILOG_FLAG_IS_CONS 0x00000001
47#define PMACZILOG_FLAG_IS_KGDB 0x00000002
48#define PMACZILOG_FLAG_MODEM_STATUS 0x00000004
49#define PMACZILOG_FLAG_IS_CHANNEL_A 0x00000008
50#define PMACZILOG_FLAG_REGS_HELD 0x00000010
51#define PMACZILOG_FLAG_TX_STOPPED 0x00000020
52#define PMACZILOG_FLAG_TX_ACTIVE 0x00000040
53#define PMACZILOG_FLAG_ENABLED 0x00000080
54#define PMACZILOG_FLAG_IS_IRDA 0x00000100
55#define PMACZILOG_FLAG_IS_INTMODEM 0x00000200
56#define PMACZILOG_FLAG_HAS_DMA 0x00000400
57#define PMACZILOG_FLAG_RSRC_REQUESTED 0x00000800
58#define PMACZILOG_FLAG_IS_ASLEEP 0x00001000
59#define PMACZILOG_FLAG_IS_OPEN 0x00002000
60#define PMACZILOG_FLAG_IS_IRQ_ON 0x00004000
61#define PMACZILOG_FLAG_IS_EXTCLK 0x00008000
62#define PMACZILOG_FLAG_BREAK 0x00010000
63
64 unsigned char parity_mask;
65 unsigned char prev_status;
66
67 volatile u8 __iomem *control_reg;
68 volatile u8 __iomem *data_reg;
69
70#ifdef CONFIG_PPC_PMAC
71 unsigned int tx_dma_irq;
72 unsigned int rx_dma_irq;
73 volatile struct dbdma_regs __iomem *tx_dma_regs;
74 volatile struct dbdma_regs __iomem *rx_dma_regs;
75#endif
76
77 struct ktermios termios_cache;
78};
79
80#define to_pmz(p) ((struct uart_pmac_port *)(p))
81
82static inline struct uart_pmac_port *pmz_get_port_A(struct uart_pmac_port *uap)
83{
84 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A)
85 return uap;
86 return uap->mate;
87}
88
89/*
90 * Register accessors. Note that we don't need to enforce a recovery
91 * delay on PCI PowerMac hardware, it's dealt in HW by the MacIO chip,
92 * though if we try to use this driver on older machines, we might have
93 * to add it back
94 */
95static inline u8 read_zsreg(struct uart_pmac_port *port, u8 reg)
96{
97 if (reg != 0)
98 writeb(reg, port->control_reg);
99 return readb(port->control_reg);
100}
101
102static inline void write_zsreg(struct uart_pmac_port *port, u8 reg, u8 value)
103{
104 if (reg != 0)
105 writeb(reg, port->control_reg);
106 writeb(value, port->control_reg);
107}
108
109static inline u8 read_zsdata(struct uart_pmac_port *port)
110{
111 return readb(port->data_reg);
112}
113
114static inline void write_zsdata(struct uart_pmac_port *port, u8 data)
115{
116 writeb(data, port->data_reg);
117}
118
119static inline void zssync(struct uart_pmac_port *port)
120{
121 (void)readb(port->control_reg);
122}
123
124/* Conversion routines to/from brg time constants from/to bits
125 * per second.
126 */
127#define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
128#define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
129
130#define ZS_CLOCK 3686400 /* Z8530 RTxC input clock rate */
131
132/* The Zilog register set */
133
134#define FLAG 0x7e
135
136/* Write Register 0 */
137#define R0 0 /* Register selects */
138#define R1 1
139#define R2 2
140#define R3 3
141#define R4 4
142#define R5 5
143#define R6 6
144#define R7 7
145#define R8 8
146#define R9 9
147#define R10 10
148#define R11 11
149#define R12 12
150#define R13 13
151#define R14 14
152#define R15 15
153#define R7P 16
154
155#define NULLCODE 0 /* Null Code */
156#define POINT_HIGH 0x8 /* Select upper half of registers */
157#define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
158#define SEND_ABORT 0x18 /* HDLC Abort */
159#define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
160#define RES_Tx_P 0x28 /* Reset TxINT Pending */
161#define ERR_RES 0x30 /* Error Reset */
162#define RES_H_IUS 0x38 /* Reset highest IUS */
163
164#define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
165#define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
166#define RES_EOM_L 0xC0 /* Reset EOM latch */
167
168/* Write Register 1 */
169
170#define EXT_INT_ENAB 0x1 /* Ext Int Enable */
171#define TxINT_ENAB 0x2 /* Tx Int Enable */
172#define PAR_SPEC 0x4 /* Parity is special condition */
173
174#define RxINT_DISAB 0 /* Rx Int Disable */
175#define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
176#define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */
177#define INT_ERR_Rx 0x18 /* Int on error only */
178#define RxINT_MASK 0x18
179
180#define WT_RDY_RT 0x20 /* W/Req reflects recv if 1, xmit if 0 */
181#define WT_FN_RDYFN 0x40 /* W/Req pin is DMA request if 1, wait if 0 */
182#define WT_RDY_ENAB 0x80 /* Enable W/Req pin */
183
184/* Write Register #2 (Interrupt Vector) */
185
186/* Write Register 3 */
187
188#define RxENABLE 0x1 /* Rx Enable */
189#define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
190#define ADD_SM 0x4 /* Address Search Mode (SDLC) */
191#define RxCRC_ENAB 0x8 /* Rx CRC Enable */
192#define ENT_HM 0x10 /* Enter Hunt Mode */
193#define AUTO_ENAB 0x20 /* Auto Enables */
194#define Rx5 0x0 /* Rx 5 Bits/Character */
195#define Rx7 0x40 /* Rx 7 Bits/Character */
196#define Rx6 0x80 /* Rx 6 Bits/Character */
197#define Rx8 0xc0 /* Rx 8 Bits/Character */
198#define RxN_MASK 0xc0
199
200/* Write Register 4 */
201
202#define PAR_ENAB 0x1 /* Parity Enable */
203#define PAR_EVEN 0x2 /* Parity Even/Odd* */
204
205#define SYNC_ENAB 0 /* Sync Modes Enable */
206#define SB1 0x4 /* 1 stop bit/char */
207#define SB15 0x8 /* 1.5 stop bits/char */
208#define SB2 0xc /* 2 stop bits/char */
209#define SB_MASK 0xc
210
211#define MONSYNC 0 /* 8 Bit Sync character */
212#define BISYNC 0x10 /* 16 bit sync character */
213#define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
214#define EXTSYNC 0x30 /* External Sync Mode */
215
216#define X1CLK 0x0 /* x1 clock mode */
217#define X16CLK 0x40 /* x16 clock mode */
218#define X32CLK 0x80 /* x32 clock mode */
219#define X64CLK 0xC0 /* x64 clock mode */
220#define XCLK_MASK 0xC0
221
222/* Write Register 5 */
223
224#define TxCRC_ENAB 0x1 /* Tx CRC Enable */
225#define RTS 0x2 /* RTS */
226#define SDLC_CRC 0x4 /* SDLC/CRC-16 */
227#define TxENABLE 0x8 /* Tx Enable */
228#define SND_BRK 0x10 /* Send Break */
229#define Tx5 0x0 /* Tx 5 bits (or less)/character */
230#define Tx7 0x20 /* Tx 7 bits/character */
231#define Tx6 0x40 /* Tx 6 bits/character */
232#define Tx8 0x60 /* Tx 8 bits/character */
233#define TxN_MASK 0x60
234#define DTR 0x80 /* DTR */
235
236/* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
237
238/* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
239
240/* Write Register 7' (Some enhanced feature control) */
241#define ENEXREAD 0x40 /* Enable read of some write registers */
242
243/* Write Register 8 (transmit buffer) */
244
245/* Write Register 9 (Master interrupt control) */
246#define VIS 1 /* Vector Includes Status */
247#define NV 2 /* No Vector */
248#define DLC 4 /* Disable Lower Chain */
249#define MIE 8 /* Master Interrupt Enable */
250#define STATHI 0x10 /* Status high */
251#define NORESET 0 /* No reset on write to R9 */
252#define CHRB 0x40 /* Reset channel B */
253#define CHRA 0x80 /* Reset channel A */
254#define FHWRES 0xc0 /* Force hardware reset */
255
256/* Write Register 10 (misc control bits) */
257#define BIT6 1 /* 6 bit/8bit sync */
258#define LOOPMODE 2 /* SDLC Loop mode */
259#define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */
260#define MARKIDLE 8 /* Mark/flag on idle */
261#define GAOP 0x10 /* Go active on poll */
262#define NRZ 0 /* NRZ mode */
263#define NRZI 0x20 /* NRZI mode */
264#define FM1 0x40 /* FM1 (transition = 1) */
265#define FM0 0x60 /* FM0 (transition = 0) */
266#define CRCPS 0x80 /* CRC Preset I/O */
267
268/* Write Register 11 (Clock Mode control) */
269#define TRxCXT 0 /* TRxC = Xtal output */
270#define TRxCTC 1 /* TRxC = Transmit clock */
271#define TRxCBR 2 /* TRxC = BR Generator Output */
272#define TRxCDP 3 /* TRxC = DPLL output */
273#define TRxCOI 4 /* TRxC O/I */
274#define TCRTxCP 0 /* Transmit clock = RTxC pin */
275#define TCTRxCP 8 /* Transmit clock = TRxC pin */
276#define TCBR 0x10 /* Transmit clock = BR Generator output */
277#define TCDPLL 0x18 /* Transmit clock = DPLL output */
278#define RCRTxCP 0 /* Receive clock = RTxC pin */
279#define RCTRxCP 0x20 /* Receive clock = TRxC pin */
280#define RCBR 0x40 /* Receive clock = BR Generator output */
281#define RCDPLL 0x60 /* Receive clock = DPLL output */
282#define RTxCX 0x80 /* RTxC Xtal/No Xtal */
283
284/* Write Register 12 (lower byte of baud rate generator time constant) */
285
286/* Write Register 13 (upper byte of baud rate generator time constant) */
287
288/* Write Register 14 (Misc control bits) */
289#define BRENAB 1 /* Baud rate generator enable */
290#define BRSRC 2 /* Baud rate generator source */
291#define DTRREQ 4 /* DTR/Request function */
292#define AUTOECHO 8 /* Auto Echo */
293#define LOOPBAK 0x10 /* Local loopback */
294#define SEARCH 0x20 /* Enter search mode */
295#define RMC 0x40 /* Reset missing clock */
296#define DISDPLL 0x60 /* Disable DPLL */
297#define SSBR 0x80 /* Set DPLL source = BR generator */
298#define SSRTxC 0xa0 /* Set DPLL source = RTxC */
299#define SFMM 0xc0 /* Set FM mode */
300#define SNRZI 0xe0 /* Set NRZI mode */
301
302/* Write Register 15 (external/status interrupt control) */
303#define EN85C30 1 /* Enable some 85c30-enhanced registers */
304#define ZCIE 2 /* Zero count IE */
305#define ENSTFIFO 4 /* Enable status FIFO (SDLC) */
306#define DCDIE 8 /* DCD IE */
307#define SYNCIE 0x10 /* Sync/hunt IE */
308#define CTSIE 0x20 /* CTS IE */
309#define TxUIE 0x40 /* Tx Underrun/EOM IE */
310#define BRKIE 0x80 /* Break/Abort IE */
311
312
313/* Read Register 0 */
314#define Rx_CH_AV 0x1 /* Rx Character Available */
315#define ZCOUNT 0x2 /* Zero count */
316#define Tx_BUF_EMP 0x4 /* Tx Buffer empty */
317#define DCD 0x8 /* DCD */
318#define SYNC_HUNT 0x10 /* Sync/hunt */
319#define CTS 0x20 /* CTS */
320#define TxEOM 0x40 /* Tx underrun */
321#define BRK_ABRT 0x80 /* Break/Abort */
322
323/* Read Register 1 */
324#define ALL_SNT 0x1 /* All sent */
325/* Residue Data for 8 Rx bits/char programmed */
326#define RES3 0x8 /* 0/3 */
327#define RES4 0x4 /* 0/4 */
328#define RES5 0xc /* 0/5 */
329#define RES6 0x2 /* 0/6 */
330#define RES7 0xa /* 0/7 */
331#define RES8 0x6 /* 0/8 */
332#define RES18 0xe /* 1/8 */
333#define RES28 0x0 /* 2/8 */
334/* Special Rx Condition Interrupts */
335#define PAR_ERR 0x10 /* Parity error */
336#define Rx_OVR 0x20 /* Rx Overrun Error */
337#define CRC_ERR 0x40 /* CRC/Framing Error */
338#define END_FR 0x80 /* End of Frame (SDLC) */
339
340/* Read Register 2 (channel b only) - Interrupt vector */
341#define CHB_Tx_EMPTY 0x00
342#define CHB_EXT_STAT 0x02
343#define CHB_Rx_AVAIL 0x04
344#define CHB_SPECIAL 0x06
345#define CHA_Tx_EMPTY 0x08
346#define CHA_EXT_STAT 0x0a
347#define CHA_Rx_AVAIL 0x0c
348#define CHA_SPECIAL 0x0e
349#define STATUS_MASK 0x06
350
351/* Read Register 3 (interrupt pending register) ch a only */
352#define CHBEXT 0x1 /* Channel B Ext/Stat IP */
353#define CHBTxIP 0x2 /* Channel B Tx IP */
354#define CHBRxIP 0x4 /* Channel B Rx IP */
355#define CHAEXT 0x8 /* Channel A Ext/Stat IP */
356#define CHATxIP 0x10 /* Channel A Tx IP */
357#define CHARxIP 0x20 /* Channel A Rx IP */
358
359/* Read Register 8 (receive data register) */
360
361/* Read Register 10 (misc status bits) */
362#define ONLOOP 2 /* On loop */
363#define LOOPSEND 0x10 /* Loop sending */
364#define CLK2MIS 0x40 /* Two clocks missing */
365#define CLK1MIS 0x80 /* One clock missing */
366
367/* Read Register 12 (lower byte of baud rate generator constant) */
368
369/* Read Register 13 (upper byte of baud rate generator constant) */
370
371/* Read Register 15 (value of WR 15) */
372
373/* Misc macros */
374#define ZS_CLEARERR(port) (write_zsreg(port, 0, ERR_RES))
375#define ZS_CLEARFIFO(port) do { volatile unsigned char garbage; \
376 garbage = read_zsdata(port); \
377 garbage = read_zsdata(port); \
378 garbage = read_zsdata(port); \
379 } while(0)
380
381#define ZS_IS_CONS(UP) ((UP)->flags & PMACZILOG_FLAG_IS_CONS)
382#define ZS_IS_KGDB(UP) ((UP)->flags & PMACZILOG_FLAG_IS_KGDB)
383#define ZS_IS_CHANNEL_A(UP) ((UP)->flags & PMACZILOG_FLAG_IS_CHANNEL_A)
384#define ZS_REGS_HELD(UP) ((UP)->flags & PMACZILOG_FLAG_REGS_HELD)
385#define ZS_TX_STOPPED(UP) ((UP)->flags & PMACZILOG_FLAG_TX_STOPPED)
386#define ZS_TX_ACTIVE(UP) ((UP)->flags & PMACZILOG_FLAG_TX_ACTIVE)
387#define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & PMACZILOG_FLAG_MODEM_STATUS)
388#define ZS_IS_IRDA(UP) ((UP)->flags & PMACZILOG_FLAG_IS_IRDA)
389#define ZS_IS_INTMODEM(UP) ((UP)->flags & PMACZILOG_FLAG_IS_INTMODEM)
390#define ZS_HAS_DMA(UP) ((UP)->flags & PMACZILOG_FLAG_HAS_DMA)
391#define ZS_IS_ASLEEP(UP) ((UP)->flags & PMACZILOG_FLAG_IS_ASLEEP)
392#define ZS_IS_OPEN(UP) ((UP)->flags & PMACZILOG_FLAG_IS_OPEN)
393#define ZS_IS_IRQ_ON(UP) ((UP)->flags & PMACZILOG_FLAG_IS_IRQ_ON)
394#define ZS_IS_EXTCLK(UP) ((UP)->flags & PMACZILOG_FLAG_IS_EXTCLK)
395
396#endif /* __PMAC_ZILOG_H__ */
diff --git a/drivers/serial/pnx8xxx_uart.c b/drivers/serial/pnx8xxx_uart.c
deleted file mode 100644
index 0aa75a97531c..000000000000
--- a/drivers/serial/pnx8xxx_uart.c
+++ /dev/null
@@ -1,854 +0,0 @@
1/*
2 * UART driver for PNX8XXX SoCs
3 *
4 * Author: Per Hallsmark per.hallsmark@mvista.com
5 * Ported to 2.6 kernel by EmbeddedAlley
6 * Reworked by Vitaly Wool <vitalywool@gmail.com>
7 *
8 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
9 * Copyright (C) 2000 Deep Blue Solutions Ltd.
10 *
11 * This file is licensed under the terms of the GNU General Public License
12 * version 2. This program is licensed "as is" without any warranty of
13 * any kind, whether express or implied.
14 *
15 */
16
17#if defined(CONFIG_SERIAL_PNX8XXX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
18#define SUPPORT_SYSRQ
19#endif
20
21#include <linux/module.h>
22#include <linux/ioport.h>
23#include <linux/init.h>
24#include <linux/console.h>
25#include <linux/sysrq.h>
26#include <linux/device.h>
27#include <linux/platform_device.h>
28#include <linux/tty.h>
29#include <linux/tty_flip.h>
30#include <linux/serial_core.h>
31#include <linux/serial.h>
32#include <linux/serial_pnx8xxx.h>
33
34#include <asm/io.h>
35#include <asm/irq.h>
36
37/* We'll be using StrongARM sa1100 serial port major/minor */
38#define SERIAL_PNX8XXX_MAJOR 204
39#define MINOR_START 5
40
41#define NR_PORTS 2
42
43#define PNX8XXX_ISR_PASS_LIMIT 256
44
45/*
46 * Convert from ignore_status_mask or read_status_mask to FIFO
47 * and interrupt status bits
48 */
49#define SM_TO_FIFO(x) ((x) >> 10)
50#define SM_TO_ISTAT(x) ((x) & 0x000001ff)
51#define FIFO_TO_SM(x) ((x) << 10)
52#define ISTAT_TO_SM(x) ((x) & 0x000001ff)
53
54/*
55 * This is the size of our serial port register set.
56 */
57#define UART_PORT_SIZE 0x1000
58
59/*
60 * This determines how often we check the modem status signals
61 * for any change. They generally aren't connected to an IRQ
62 * so we have to poll them. We also check immediately before
63 * filling the TX fifo incase CTS has been dropped.
64 */
65#define MCTRL_TIMEOUT (250*HZ/1000)
66
67extern struct pnx8xxx_port pnx8xxx_ports[];
68
69static inline int serial_in(struct pnx8xxx_port *sport, int offset)
70{
71 return (__raw_readl(sport->port.membase + offset));
72}
73
74static inline void serial_out(struct pnx8xxx_port *sport, int offset, int value)
75{
76 __raw_writel(value, sport->port.membase + offset);
77}
78
79/*
80 * Handle any change of modem status signal since we were last called.
81 */
82static void pnx8xxx_mctrl_check(struct pnx8xxx_port *sport)
83{
84 unsigned int status, changed;
85
86 status = sport->port.ops->get_mctrl(&sport->port);
87 changed = status ^ sport->old_status;
88
89 if (changed == 0)
90 return;
91
92 sport->old_status = status;
93
94 if (changed & TIOCM_RI)
95 sport->port.icount.rng++;
96 if (changed & TIOCM_DSR)
97 sport->port.icount.dsr++;
98 if (changed & TIOCM_CAR)
99 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
100 if (changed & TIOCM_CTS)
101 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
102
103 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
104}
105
106/*
107 * This is our per-port timeout handler, for checking the
108 * modem status signals.
109 */
110static void pnx8xxx_timeout(unsigned long data)
111{
112 struct pnx8xxx_port *sport = (struct pnx8xxx_port *)data;
113 unsigned long flags;
114
115 if (sport->port.state) {
116 spin_lock_irqsave(&sport->port.lock, flags);
117 pnx8xxx_mctrl_check(sport);
118 spin_unlock_irqrestore(&sport->port.lock, flags);
119
120 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
121 }
122}
123
124/*
125 * interrupts disabled on entry
126 */
127static void pnx8xxx_stop_tx(struct uart_port *port)
128{
129 struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
130 u32 ien;
131
132 /* Disable TX intr */
133 ien = serial_in(sport, PNX8XXX_IEN);
134 serial_out(sport, PNX8XXX_IEN, ien & ~PNX8XXX_UART_INT_ALLTX);
135
136 /* Clear all pending TX intr */
137 serial_out(sport, PNX8XXX_ICLR, PNX8XXX_UART_INT_ALLTX);
138}
139
140/*
141 * interrupts may not be disabled on entry
142 */
143static void pnx8xxx_start_tx(struct uart_port *port)
144{
145 struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
146 u32 ien;
147
148 /* Clear all pending TX intr */
149 serial_out(sport, PNX8XXX_ICLR, PNX8XXX_UART_INT_ALLTX);
150
151 /* Enable TX intr */
152 ien = serial_in(sport, PNX8XXX_IEN);
153 serial_out(sport, PNX8XXX_IEN, ien | PNX8XXX_UART_INT_ALLTX);
154}
155
156/*
157 * Interrupts enabled
158 */
159static void pnx8xxx_stop_rx(struct uart_port *port)
160{
161 struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
162 u32 ien;
163
164 /* Disable RX intr */
165 ien = serial_in(sport, PNX8XXX_IEN);
166 serial_out(sport, PNX8XXX_IEN, ien & ~PNX8XXX_UART_INT_ALLRX);
167
168 /* Clear all pending RX intr */
169 serial_out(sport, PNX8XXX_ICLR, PNX8XXX_UART_INT_ALLRX);
170}
171
172/*
173 * Set the modem control timer to fire immediately.
174 */
175static void pnx8xxx_enable_ms(struct uart_port *port)
176{
177 struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
178
179 mod_timer(&sport->timer, jiffies);
180}
181
182static void pnx8xxx_rx_chars(struct pnx8xxx_port *sport)
183{
184 struct tty_struct *tty = sport->port.state->port.tty;
185 unsigned int status, ch, flg;
186
187 status = FIFO_TO_SM(serial_in(sport, PNX8XXX_FIFO)) |
188 ISTAT_TO_SM(serial_in(sport, PNX8XXX_ISTAT));
189 while (status & FIFO_TO_SM(PNX8XXX_UART_FIFO_RXFIFO)) {
190 ch = serial_in(sport, PNX8XXX_FIFO) & 0xff;
191
192 sport->port.icount.rx++;
193
194 flg = TTY_NORMAL;
195
196 /*
197 * note that the error handling code is
198 * out of the main execution path
199 */
200 if (status & (FIFO_TO_SM(PNX8XXX_UART_FIFO_RXFE |
201 PNX8XXX_UART_FIFO_RXPAR |
202 PNX8XXX_UART_FIFO_RXBRK) |
203 ISTAT_TO_SM(PNX8XXX_UART_INT_RXOVRN))) {
204 if (status & FIFO_TO_SM(PNX8XXX_UART_FIFO_RXBRK)) {
205 status &= ~(FIFO_TO_SM(PNX8XXX_UART_FIFO_RXFE) |
206 FIFO_TO_SM(PNX8XXX_UART_FIFO_RXPAR));
207 sport->port.icount.brk++;
208 if (uart_handle_break(&sport->port))
209 goto ignore_char;
210 } else if (status & FIFO_TO_SM(PNX8XXX_UART_FIFO_RXPAR))
211 sport->port.icount.parity++;
212 else if (status & FIFO_TO_SM(PNX8XXX_UART_FIFO_RXFE))
213 sport->port.icount.frame++;
214 if (status & ISTAT_TO_SM(PNX8XXX_UART_INT_RXOVRN))
215 sport->port.icount.overrun++;
216
217 status &= sport->port.read_status_mask;
218
219 if (status & FIFO_TO_SM(PNX8XXX_UART_FIFO_RXPAR))
220 flg = TTY_PARITY;
221 else if (status & FIFO_TO_SM(PNX8XXX_UART_FIFO_RXFE))
222 flg = TTY_FRAME;
223
224#ifdef SUPPORT_SYSRQ
225 sport->port.sysrq = 0;
226#endif
227 }
228
229 if (uart_handle_sysrq_char(&sport->port, ch))
230 goto ignore_char;
231
232 uart_insert_char(&sport->port, status,
233 ISTAT_TO_SM(PNX8XXX_UART_INT_RXOVRN), ch, flg);
234
235 ignore_char:
236 serial_out(sport, PNX8XXX_LCR, serial_in(sport, PNX8XXX_LCR) |
237 PNX8XXX_UART_LCR_RX_NEXT);
238 status = FIFO_TO_SM(serial_in(sport, PNX8XXX_FIFO)) |
239 ISTAT_TO_SM(serial_in(sport, PNX8XXX_ISTAT));
240 }
241 tty_flip_buffer_push(tty);
242}
243
244static void pnx8xxx_tx_chars(struct pnx8xxx_port *sport)
245{
246 struct circ_buf *xmit = &sport->port.state->xmit;
247
248 if (sport->port.x_char) {
249 serial_out(sport, PNX8XXX_FIFO, sport->port.x_char);
250 sport->port.icount.tx++;
251 sport->port.x_char = 0;
252 return;
253 }
254
255 /*
256 * Check the modem control lines before
257 * transmitting anything.
258 */
259 pnx8xxx_mctrl_check(sport);
260
261 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
262 pnx8xxx_stop_tx(&sport->port);
263 return;
264 }
265
266 /*
267 * TX while bytes available
268 */
269 while (((serial_in(sport, PNX8XXX_FIFO) &
270 PNX8XXX_UART_FIFO_TXFIFO) >> 16) < 16) {
271 serial_out(sport, PNX8XXX_FIFO, xmit->buf[xmit->tail]);
272 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
273 sport->port.icount.tx++;
274 if (uart_circ_empty(xmit))
275 break;
276 }
277
278 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
279 uart_write_wakeup(&sport->port);
280
281 if (uart_circ_empty(xmit))
282 pnx8xxx_stop_tx(&sport->port);
283}
284
285static irqreturn_t pnx8xxx_int(int irq, void *dev_id)
286{
287 struct pnx8xxx_port *sport = dev_id;
288 unsigned int status;
289
290 spin_lock(&sport->port.lock);
291 /* Get the interrupts */
292 status = serial_in(sport, PNX8XXX_ISTAT) & serial_in(sport, PNX8XXX_IEN);
293
294 /* Byte or break signal received */
295 if (status & (PNX8XXX_UART_INT_RX | PNX8XXX_UART_INT_BREAK))
296 pnx8xxx_rx_chars(sport);
297
298 /* TX holding register empty - transmit a byte */
299 if (status & PNX8XXX_UART_INT_TX)
300 pnx8xxx_tx_chars(sport);
301
302 /* Clear the ISTAT register */
303 serial_out(sport, PNX8XXX_ICLR, status);
304
305 spin_unlock(&sport->port.lock);
306 return IRQ_HANDLED;
307}
308
309/*
310 * Return TIOCSER_TEMT when transmitter is not busy.
311 */
312static unsigned int pnx8xxx_tx_empty(struct uart_port *port)
313{
314 struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
315
316 return serial_in(sport, PNX8XXX_FIFO) & PNX8XXX_UART_FIFO_TXFIFO_STA ? 0 : TIOCSER_TEMT;
317}
318
319static unsigned int pnx8xxx_get_mctrl(struct uart_port *port)
320{
321 struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
322 unsigned int mctrl = TIOCM_DSR;
323 unsigned int msr;
324
325 /* REVISIT */
326
327 msr = serial_in(sport, PNX8XXX_MCR);
328
329 mctrl |= msr & PNX8XXX_UART_MCR_CTS ? TIOCM_CTS : 0;
330 mctrl |= msr & PNX8XXX_UART_MCR_DCD ? TIOCM_CAR : 0;
331
332 return mctrl;
333}
334
335static void pnx8xxx_set_mctrl(struct uart_port *port, unsigned int mctrl)
336{
337#if 0 /* FIXME */
338 struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
339 unsigned int msr;
340#endif
341}
342
343/*
344 * Interrupts always disabled.
345 */
346static void pnx8xxx_break_ctl(struct uart_port *port, int break_state)
347{
348 struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
349 unsigned long flags;
350 unsigned int lcr;
351
352 spin_lock_irqsave(&sport->port.lock, flags);
353 lcr = serial_in(sport, PNX8XXX_LCR);
354 if (break_state == -1)
355 lcr |= PNX8XXX_UART_LCR_TXBREAK;
356 else
357 lcr &= ~PNX8XXX_UART_LCR_TXBREAK;
358 serial_out(sport, PNX8XXX_LCR, lcr);
359 spin_unlock_irqrestore(&sport->port.lock, flags);
360}
361
362static int pnx8xxx_startup(struct uart_port *port)
363{
364 struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
365 int retval;
366
367 /*
368 * Allocate the IRQ
369 */
370 retval = request_irq(sport->port.irq, pnx8xxx_int, 0,
371 "pnx8xxx-uart", sport);
372 if (retval)
373 return retval;
374
375 /*
376 * Finally, clear and enable interrupts
377 */
378
379 serial_out(sport, PNX8XXX_ICLR, PNX8XXX_UART_INT_ALLRX |
380 PNX8XXX_UART_INT_ALLTX);
381
382 serial_out(sport, PNX8XXX_IEN, serial_in(sport, PNX8XXX_IEN) |
383 PNX8XXX_UART_INT_ALLRX |
384 PNX8XXX_UART_INT_ALLTX);
385
386 /*
387 * Enable modem status interrupts
388 */
389 spin_lock_irq(&sport->port.lock);
390 pnx8xxx_enable_ms(&sport->port);
391 spin_unlock_irq(&sport->port.lock);
392
393 return 0;
394}
395
396static void pnx8xxx_shutdown(struct uart_port *port)
397{
398 struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
399 int lcr;
400
401 /*
402 * Stop our timer.
403 */
404 del_timer_sync(&sport->timer);
405
406 /*
407 * Disable all interrupts
408 */
409 serial_out(sport, PNX8XXX_IEN, 0);
410
411 /*
412 * Reset the Tx and Rx FIFOS, disable the break condition
413 */
414 lcr = serial_in(sport, PNX8XXX_LCR);
415 lcr &= ~PNX8XXX_UART_LCR_TXBREAK;
416 lcr |= PNX8XXX_UART_LCR_TX_RST | PNX8XXX_UART_LCR_RX_RST;
417 serial_out(sport, PNX8XXX_LCR, lcr);
418
419 /*
420 * Clear all interrupts
421 */
422 serial_out(sport, PNX8XXX_ICLR, PNX8XXX_UART_INT_ALLRX |
423 PNX8XXX_UART_INT_ALLTX);
424
425 /*
426 * Free the interrupt
427 */
428 free_irq(sport->port.irq, sport);
429}
430
431static void
432pnx8xxx_set_termios(struct uart_port *port, struct ktermios *termios,
433 struct ktermios *old)
434{
435 struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
436 unsigned long flags;
437 unsigned int lcr_fcr, old_ien, baud, quot;
438 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
439
440 /*
441 * We only support CS7 and CS8.
442 */
443 while ((termios->c_cflag & CSIZE) != CS7 &&
444 (termios->c_cflag & CSIZE) != CS8) {
445 termios->c_cflag &= ~CSIZE;
446 termios->c_cflag |= old_csize;
447 old_csize = CS8;
448 }
449
450 if ((termios->c_cflag & CSIZE) == CS8)
451 lcr_fcr = PNX8XXX_UART_LCR_8BIT;
452 else
453 lcr_fcr = 0;
454
455 if (termios->c_cflag & CSTOPB)
456 lcr_fcr |= PNX8XXX_UART_LCR_2STOPB;
457 if (termios->c_cflag & PARENB) {
458 lcr_fcr |= PNX8XXX_UART_LCR_PAREN;
459 if (!(termios->c_cflag & PARODD))
460 lcr_fcr |= PNX8XXX_UART_LCR_PAREVN;
461 }
462
463 /*
464 * Ask the core to calculate the divisor for us.
465 */
466 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
467 quot = uart_get_divisor(port, baud);
468
469 spin_lock_irqsave(&sport->port.lock, flags);
470
471 sport->port.read_status_mask = ISTAT_TO_SM(PNX8XXX_UART_INT_RXOVRN) |
472 ISTAT_TO_SM(PNX8XXX_UART_INT_EMPTY) |
473 ISTAT_TO_SM(PNX8XXX_UART_INT_RX);
474 if (termios->c_iflag & INPCK)
475 sport->port.read_status_mask |=
476 FIFO_TO_SM(PNX8XXX_UART_FIFO_RXFE) |
477 FIFO_TO_SM(PNX8XXX_UART_FIFO_RXPAR);
478 if (termios->c_iflag & (BRKINT | PARMRK))
479 sport->port.read_status_mask |=
480 ISTAT_TO_SM(PNX8XXX_UART_INT_BREAK);
481
482 /*
483 * Characters to ignore
484 */
485 sport->port.ignore_status_mask = 0;
486 if (termios->c_iflag & IGNPAR)
487 sport->port.ignore_status_mask |=
488 FIFO_TO_SM(PNX8XXX_UART_FIFO_RXFE) |
489 FIFO_TO_SM(PNX8XXX_UART_FIFO_RXPAR);
490 if (termios->c_iflag & IGNBRK) {
491 sport->port.ignore_status_mask |=
492 ISTAT_TO_SM(PNX8XXX_UART_INT_BREAK);
493 /*
494 * If we're ignoring parity and break indicators,
495 * ignore overruns too (for real raw support).
496 */
497 if (termios->c_iflag & IGNPAR)
498 sport->port.ignore_status_mask |=
499 ISTAT_TO_SM(PNX8XXX_UART_INT_RXOVRN);
500 }
501
502 /*
503 * ignore all characters if CREAD is not set
504 */
505 if ((termios->c_cflag & CREAD) == 0)
506 sport->port.ignore_status_mask |=
507 ISTAT_TO_SM(PNX8XXX_UART_INT_RX);
508
509 del_timer_sync(&sport->timer);
510
511 /*
512 * Update the per-port timeout.
513 */
514 uart_update_timeout(port, termios->c_cflag, baud);
515
516 /*
517 * disable interrupts and drain transmitter
518 */
519 old_ien = serial_in(sport, PNX8XXX_IEN);
520 serial_out(sport, PNX8XXX_IEN, old_ien & ~(PNX8XXX_UART_INT_ALLTX |
521 PNX8XXX_UART_INT_ALLRX));
522
523 while (serial_in(sport, PNX8XXX_FIFO) & PNX8XXX_UART_FIFO_TXFIFO_STA)
524 barrier();
525
526 /* then, disable everything */
527 serial_out(sport, PNX8XXX_IEN, 0);
528
529 /* Reset the Rx and Tx FIFOs too */
530 lcr_fcr |= PNX8XXX_UART_LCR_TX_RST;
531 lcr_fcr |= PNX8XXX_UART_LCR_RX_RST;
532
533 /* set the parity, stop bits and data size */
534 serial_out(sport, PNX8XXX_LCR, lcr_fcr);
535
536 /* set the baud rate */
537 quot -= 1;
538 serial_out(sport, PNX8XXX_BAUD, quot);
539
540 serial_out(sport, PNX8XXX_ICLR, -1);
541
542 serial_out(sport, PNX8XXX_IEN, old_ien);
543
544 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
545 pnx8xxx_enable_ms(&sport->port);
546
547 spin_unlock_irqrestore(&sport->port.lock, flags);
548}
549
550static const char *pnx8xxx_type(struct uart_port *port)
551{
552 struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
553
554 return sport->port.type == PORT_PNX8XXX ? "PNX8XXX" : NULL;
555}
556
557/*
558 * Release the memory region(s) being used by 'port'.
559 */
560static void pnx8xxx_release_port(struct uart_port *port)
561{
562 struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
563
564 release_mem_region(sport->port.mapbase, UART_PORT_SIZE);
565}
566
567/*
568 * Request the memory region(s) being used by 'port'.
569 */
570static int pnx8xxx_request_port(struct uart_port *port)
571{
572 struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
573 return request_mem_region(sport->port.mapbase, UART_PORT_SIZE,
574 "pnx8xxx-uart") != NULL ? 0 : -EBUSY;
575}
576
577/*
578 * Configure/autoconfigure the port.
579 */
580static void pnx8xxx_config_port(struct uart_port *port, int flags)
581{
582 struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
583
584 if (flags & UART_CONFIG_TYPE &&
585 pnx8xxx_request_port(&sport->port) == 0)
586 sport->port.type = PORT_PNX8XXX;
587}
588
589/*
590 * Verify the new serial_struct (for TIOCSSERIAL).
591 * The only change we allow are to the flags and type, and
592 * even then only between PORT_PNX8XXX and PORT_UNKNOWN
593 */
594static int
595pnx8xxx_verify_port(struct uart_port *port, struct serial_struct *ser)
596{
597 struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
598 int ret = 0;
599
600 if (ser->type != PORT_UNKNOWN && ser->type != PORT_PNX8XXX)
601 ret = -EINVAL;
602 if (sport->port.irq != ser->irq)
603 ret = -EINVAL;
604 if (ser->io_type != SERIAL_IO_MEM)
605 ret = -EINVAL;
606 if (sport->port.uartclk / 16 != ser->baud_base)
607 ret = -EINVAL;
608 if ((void *)sport->port.mapbase != ser->iomem_base)
609 ret = -EINVAL;
610 if (sport->port.iobase != ser->port)
611 ret = -EINVAL;
612 if (ser->hub6 != 0)
613 ret = -EINVAL;
614 return ret;
615}
616
617static struct uart_ops pnx8xxx_pops = {
618 .tx_empty = pnx8xxx_tx_empty,
619 .set_mctrl = pnx8xxx_set_mctrl,
620 .get_mctrl = pnx8xxx_get_mctrl,
621 .stop_tx = pnx8xxx_stop_tx,
622 .start_tx = pnx8xxx_start_tx,
623 .stop_rx = pnx8xxx_stop_rx,
624 .enable_ms = pnx8xxx_enable_ms,
625 .break_ctl = pnx8xxx_break_ctl,
626 .startup = pnx8xxx_startup,
627 .shutdown = pnx8xxx_shutdown,
628 .set_termios = pnx8xxx_set_termios,
629 .type = pnx8xxx_type,
630 .release_port = pnx8xxx_release_port,
631 .request_port = pnx8xxx_request_port,
632 .config_port = pnx8xxx_config_port,
633 .verify_port = pnx8xxx_verify_port,
634};
635
636
637/*
638 * Setup the PNX8XXX serial ports.
639 *
640 * Note also that we support "console=ttySx" where "x" is either 0 or 1.
641 */
642static void __init pnx8xxx_init_ports(void)
643{
644 static int first = 1;
645 int i;
646
647 if (!first)
648 return;
649 first = 0;
650
651 for (i = 0; i < NR_PORTS; i++) {
652 init_timer(&pnx8xxx_ports[i].timer);
653 pnx8xxx_ports[i].timer.function = pnx8xxx_timeout;
654 pnx8xxx_ports[i].timer.data = (unsigned long)&pnx8xxx_ports[i];
655 pnx8xxx_ports[i].port.ops = &pnx8xxx_pops;
656 }
657}
658
659#ifdef CONFIG_SERIAL_PNX8XXX_CONSOLE
660
661static void pnx8xxx_console_putchar(struct uart_port *port, int ch)
662{
663 struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
664 int status;
665
666 do {
667 /* Wait for UART_TX register to empty */
668 status = serial_in(sport, PNX8XXX_FIFO);
669 } while (status & PNX8XXX_UART_FIFO_TXFIFO);
670 serial_out(sport, PNX8XXX_FIFO, ch);
671}
672
673/*
674 * Interrupts are disabled on entering
675 */static void
676pnx8xxx_console_write(struct console *co, const char *s, unsigned int count)
677{
678 struct pnx8xxx_port *sport = &pnx8xxx_ports[co->index];
679 unsigned int old_ien, status;
680
681 /*
682 * First, save IEN and then disable interrupts
683 */
684 old_ien = serial_in(sport, PNX8XXX_IEN);
685 serial_out(sport, PNX8XXX_IEN, old_ien & ~(PNX8XXX_UART_INT_ALLTX |
686 PNX8XXX_UART_INT_ALLRX));
687
688 uart_console_write(&sport->port, s, count, pnx8xxx_console_putchar);
689
690 /*
691 * Finally, wait for transmitter to become empty
692 * and restore IEN
693 */
694 do {
695 /* Wait for UART_TX register to empty */
696 status = serial_in(sport, PNX8XXX_FIFO);
697 } while (status & PNX8XXX_UART_FIFO_TXFIFO);
698
699 /* Clear TX and EMPTY interrupt */
700 serial_out(sport, PNX8XXX_ICLR, PNX8XXX_UART_INT_TX |
701 PNX8XXX_UART_INT_EMPTY);
702
703 serial_out(sport, PNX8XXX_IEN, old_ien);
704}
705
706static int __init
707pnx8xxx_console_setup(struct console *co, char *options)
708{
709 struct pnx8xxx_port *sport;
710 int baud = 38400;
711 int bits = 8;
712 int parity = 'n';
713 int flow = 'n';
714
715 /*
716 * Check whether an invalid uart number has been specified, and
717 * if so, search for the first available port that does have
718 * console support.
719 */
720 if (co->index == -1 || co->index >= NR_PORTS)
721 co->index = 0;
722 sport = &pnx8xxx_ports[co->index];
723
724 if (options)
725 uart_parse_options(options, &baud, &parity, &bits, &flow);
726
727 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
728}
729
730static struct uart_driver pnx8xxx_reg;
731static struct console pnx8xxx_console = {
732 .name = "ttyS",
733 .write = pnx8xxx_console_write,
734 .device = uart_console_device,
735 .setup = pnx8xxx_console_setup,
736 .flags = CON_PRINTBUFFER,
737 .index = -1,
738 .data = &pnx8xxx_reg,
739};
740
741static int __init pnx8xxx_rs_console_init(void)
742{
743 pnx8xxx_init_ports();
744 register_console(&pnx8xxx_console);
745 return 0;
746}
747console_initcall(pnx8xxx_rs_console_init);
748
749#define PNX8XXX_CONSOLE &pnx8xxx_console
750#else
751#define PNX8XXX_CONSOLE NULL
752#endif
753
754static struct uart_driver pnx8xxx_reg = {
755 .owner = THIS_MODULE,
756 .driver_name = "ttyS",
757 .dev_name = "ttyS",
758 .major = SERIAL_PNX8XXX_MAJOR,
759 .minor = MINOR_START,
760 .nr = NR_PORTS,
761 .cons = PNX8XXX_CONSOLE,
762};
763
764static int pnx8xxx_serial_suspend(struct platform_device *pdev, pm_message_t state)
765{
766 struct pnx8xxx_port *sport = platform_get_drvdata(pdev);
767
768 return uart_suspend_port(&pnx8xxx_reg, &sport->port);
769}
770
771static int pnx8xxx_serial_resume(struct platform_device *pdev)
772{
773 struct pnx8xxx_port *sport = platform_get_drvdata(pdev);
774
775 return uart_resume_port(&pnx8xxx_reg, &sport->port);
776}
777
778static int pnx8xxx_serial_probe(struct platform_device *pdev)
779{
780 struct resource *res = pdev->resource;
781 int i;
782
783 for (i = 0; i < pdev->num_resources; i++, res++) {
784 if (!(res->flags & IORESOURCE_MEM))
785 continue;
786
787 for (i = 0; i < NR_PORTS; i++) {
788 if (pnx8xxx_ports[i].port.mapbase != res->start)
789 continue;
790
791 pnx8xxx_ports[i].port.dev = &pdev->dev;
792 uart_add_one_port(&pnx8xxx_reg, &pnx8xxx_ports[i].port);
793 platform_set_drvdata(pdev, &pnx8xxx_ports[i]);
794 break;
795 }
796 }
797
798 return 0;
799}
800
801static int pnx8xxx_serial_remove(struct platform_device *pdev)
802{
803 struct pnx8xxx_port *sport = platform_get_drvdata(pdev);
804
805 platform_set_drvdata(pdev, NULL);
806
807 if (sport)
808 uart_remove_one_port(&pnx8xxx_reg, &sport->port);
809
810 return 0;
811}
812
813static struct platform_driver pnx8xxx_serial_driver = {
814 .driver = {
815 .name = "pnx8xxx-uart",
816 .owner = THIS_MODULE,
817 },
818 .probe = pnx8xxx_serial_probe,
819 .remove = pnx8xxx_serial_remove,
820 .suspend = pnx8xxx_serial_suspend,
821 .resume = pnx8xxx_serial_resume,
822};
823
824static int __init pnx8xxx_serial_init(void)
825{
826 int ret;
827
828 printk(KERN_INFO "Serial: PNX8XXX driver\n");
829
830 pnx8xxx_init_ports();
831
832 ret = uart_register_driver(&pnx8xxx_reg);
833 if (ret == 0) {
834 ret = platform_driver_register(&pnx8xxx_serial_driver);
835 if (ret)
836 uart_unregister_driver(&pnx8xxx_reg);
837 }
838 return ret;
839}
840
841static void __exit pnx8xxx_serial_exit(void)
842{
843 platform_driver_unregister(&pnx8xxx_serial_driver);
844 uart_unregister_driver(&pnx8xxx_reg);
845}
846
847module_init(pnx8xxx_serial_init);
848module_exit(pnx8xxx_serial_exit);
849
850MODULE_AUTHOR("Embedded Alley Solutions, Inc.");
851MODULE_DESCRIPTION("PNX8XXX SoCs serial port driver");
852MODULE_LICENSE("GPL");
853MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_PNX8XXX_MAJOR);
854MODULE_ALIAS("platform:pnx8xxx-uart");
diff --git a/drivers/serial/pxa.c b/drivers/serial/pxa.c
deleted file mode 100644
index 1102a39b44f5..000000000000
--- a/drivers/serial/pxa.c
+++ /dev/null
@@ -1,879 +0,0 @@
1/*
2 * linux/drivers/serial/pxa.c
3 *
4 * Based on drivers/serial/8250.c by Russell King.
5 *
6 * Author: Nicolas Pitre
7 * Created: Feb 20, 2003
8 * Copyright: (C) 2003 Monta Vista Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * Note 1: This driver is made separate from the already too overloaded
16 * 8250.c because it needs some kirks of its own and that'll make it
17 * easier to add DMA support.
18 *
19 * Note 2: I'm too sick of device allocation policies for serial ports.
20 * If someone else wants to request an "official" allocation of major/minor
21 * for this driver please be my guest. And don't forget that new hardware
22 * to come from Intel might have more than 3 or 4 of those UARTs. Let's
23 * hope for a better port registration and dynamic device allocation scheme
24 * with the serial core maintainer satisfaction to appear soon.
25 */
26
27
28#if defined(CONFIG_SERIAL_PXA_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
29#define SUPPORT_SYSRQ
30#endif
31
32#include <linux/module.h>
33#include <linux/ioport.h>
34#include <linux/init.h>
35#include <linux/console.h>
36#include <linux/sysrq.h>
37#include <linux/serial_reg.h>
38#include <linux/circ_buf.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
41#include <linux/platform_device.h>
42#include <linux/tty.h>
43#include <linux/tty_flip.h>
44#include <linux/serial_core.h>
45#include <linux/clk.h>
46#include <linux/io.h>
47#include <linux/slab.h>
48
49struct uart_pxa_port {
50 struct uart_port port;
51 unsigned char ier;
52 unsigned char lcr;
53 unsigned char mcr;
54 unsigned int lsr_break_flag;
55 struct clk *clk;
56 char *name;
57};
58
59static inline unsigned int serial_in(struct uart_pxa_port *up, int offset)
60{
61 offset <<= 2;
62 return readl(up->port.membase + offset);
63}
64
65static inline void serial_out(struct uart_pxa_port *up, int offset, int value)
66{
67 offset <<= 2;
68 writel(value, up->port.membase + offset);
69}
70
71static void serial_pxa_enable_ms(struct uart_port *port)
72{
73 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
74
75 up->ier |= UART_IER_MSI;
76 serial_out(up, UART_IER, up->ier);
77}
78
79static void serial_pxa_stop_tx(struct uart_port *port)
80{
81 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
82
83 if (up->ier & UART_IER_THRI) {
84 up->ier &= ~UART_IER_THRI;
85 serial_out(up, UART_IER, up->ier);
86 }
87}
88
89static void serial_pxa_stop_rx(struct uart_port *port)
90{
91 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
92
93 up->ier &= ~UART_IER_RLSI;
94 up->port.read_status_mask &= ~UART_LSR_DR;
95 serial_out(up, UART_IER, up->ier);
96}
97
98static inline void receive_chars(struct uart_pxa_port *up, int *status)
99{
100 struct tty_struct *tty = up->port.state->port.tty;
101 unsigned int ch, flag;
102 int max_count = 256;
103
104 do {
105 ch = serial_in(up, UART_RX);
106 flag = TTY_NORMAL;
107 up->port.icount.rx++;
108
109 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
110 UART_LSR_FE | UART_LSR_OE))) {
111 /*
112 * For statistics only
113 */
114 if (*status & UART_LSR_BI) {
115 *status &= ~(UART_LSR_FE | UART_LSR_PE);
116 up->port.icount.brk++;
117 /*
118 * We do the SysRQ and SAK checking
119 * here because otherwise the break
120 * may get masked by ignore_status_mask
121 * or read_status_mask.
122 */
123 if (uart_handle_break(&up->port))
124 goto ignore_char;
125 } else if (*status & UART_LSR_PE)
126 up->port.icount.parity++;
127 else if (*status & UART_LSR_FE)
128 up->port.icount.frame++;
129 if (*status & UART_LSR_OE)
130 up->port.icount.overrun++;
131
132 /*
133 * Mask off conditions which should be ignored.
134 */
135 *status &= up->port.read_status_mask;
136
137#ifdef CONFIG_SERIAL_PXA_CONSOLE
138 if (up->port.line == up->port.cons->index) {
139 /* Recover the break flag from console xmit */
140 *status |= up->lsr_break_flag;
141 up->lsr_break_flag = 0;
142 }
143#endif
144 if (*status & UART_LSR_BI) {
145 flag = TTY_BREAK;
146 } else if (*status & UART_LSR_PE)
147 flag = TTY_PARITY;
148 else if (*status & UART_LSR_FE)
149 flag = TTY_FRAME;
150 }
151
152 if (uart_handle_sysrq_char(&up->port, ch))
153 goto ignore_char;
154
155 uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag);
156
157 ignore_char:
158 *status = serial_in(up, UART_LSR);
159 } while ((*status & UART_LSR_DR) && (max_count-- > 0));
160 tty_flip_buffer_push(tty);
161}
162
163static void transmit_chars(struct uart_pxa_port *up)
164{
165 struct circ_buf *xmit = &up->port.state->xmit;
166 int count;
167
168 if (up->port.x_char) {
169 serial_out(up, UART_TX, up->port.x_char);
170 up->port.icount.tx++;
171 up->port.x_char = 0;
172 return;
173 }
174 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
175 serial_pxa_stop_tx(&up->port);
176 return;
177 }
178
179 count = up->port.fifosize / 2;
180 do {
181 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
182 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
183 up->port.icount.tx++;
184 if (uart_circ_empty(xmit))
185 break;
186 } while (--count > 0);
187
188 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
189 uart_write_wakeup(&up->port);
190
191
192 if (uart_circ_empty(xmit))
193 serial_pxa_stop_tx(&up->port);
194}
195
196static void serial_pxa_start_tx(struct uart_port *port)
197{
198 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
199
200 if (!(up->ier & UART_IER_THRI)) {
201 up->ier |= UART_IER_THRI;
202 serial_out(up, UART_IER, up->ier);
203 }
204}
205
206static inline void check_modem_status(struct uart_pxa_port *up)
207{
208 int status;
209
210 status = serial_in(up, UART_MSR);
211
212 if ((status & UART_MSR_ANY_DELTA) == 0)
213 return;
214
215 if (status & UART_MSR_TERI)
216 up->port.icount.rng++;
217 if (status & UART_MSR_DDSR)
218 up->port.icount.dsr++;
219 if (status & UART_MSR_DDCD)
220 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
221 if (status & UART_MSR_DCTS)
222 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
223
224 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
225}
226
227/*
228 * This handles the interrupt from one port.
229 */
230static inline irqreturn_t serial_pxa_irq(int irq, void *dev_id)
231{
232 struct uart_pxa_port *up = dev_id;
233 unsigned int iir, lsr;
234
235 iir = serial_in(up, UART_IIR);
236 if (iir & UART_IIR_NO_INT)
237 return IRQ_NONE;
238 lsr = serial_in(up, UART_LSR);
239 if (lsr & UART_LSR_DR)
240 receive_chars(up, &lsr);
241 check_modem_status(up);
242 if (lsr & UART_LSR_THRE)
243 transmit_chars(up);
244 return IRQ_HANDLED;
245}
246
247static unsigned int serial_pxa_tx_empty(struct uart_port *port)
248{
249 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
250 unsigned long flags;
251 unsigned int ret;
252
253 spin_lock_irqsave(&up->port.lock, flags);
254 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
255 spin_unlock_irqrestore(&up->port.lock, flags);
256
257 return ret;
258}
259
260static unsigned int serial_pxa_get_mctrl(struct uart_port *port)
261{
262 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
263 unsigned char status;
264 unsigned int ret;
265
266 status = serial_in(up, UART_MSR);
267
268 ret = 0;
269 if (status & UART_MSR_DCD)
270 ret |= TIOCM_CAR;
271 if (status & UART_MSR_RI)
272 ret |= TIOCM_RNG;
273 if (status & UART_MSR_DSR)
274 ret |= TIOCM_DSR;
275 if (status & UART_MSR_CTS)
276 ret |= TIOCM_CTS;
277 return ret;
278}
279
280static void serial_pxa_set_mctrl(struct uart_port *port, unsigned int mctrl)
281{
282 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
283 unsigned char mcr = 0;
284
285 if (mctrl & TIOCM_RTS)
286 mcr |= UART_MCR_RTS;
287 if (mctrl & TIOCM_DTR)
288 mcr |= UART_MCR_DTR;
289 if (mctrl & TIOCM_OUT1)
290 mcr |= UART_MCR_OUT1;
291 if (mctrl & TIOCM_OUT2)
292 mcr |= UART_MCR_OUT2;
293 if (mctrl & TIOCM_LOOP)
294 mcr |= UART_MCR_LOOP;
295
296 mcr |= up->mcr;
297
298 serial_out(up, UART_MCR, mcr);
299}
300
301static void serial_pxa_break_ctl(struct uart_port *port, int break_state)
302{
303 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
304 unsigned long flags;
305
306 spin_lock_irqsave(&up->port.lock, flags);
307 if (break_state == -1)
308 up->lcr |= UART_LCR_SBC;
309 else
310 up->lcr &= ~UART_LCR_SBC;
311 serial_out(up, UART_LCR, up->lcr);
312 spin_unlock_irqrestore(&up->port.lock, flags);
313}
314
315#if 0
316static void serial_pxa_dma_init(struct pxa_uart *up)
317{
318 up->rxdma =
319 pxa_request_dma(up->name, DMA_PRIO_LOW, pxa_receive_dma, up);
320 if (up->rxdma < 0)
321 goto out;
322 up->txdma =
323 pxa_request_dma(up->name, DMA_PRIO_LOW, pxa_transmit_dma, up);
324 if (up->txdma < 0)
325 goto err_txdma;
326 up->dmadesc = kmalloc(4 * sizeof(pxa_dma_desc), GFP_KERNEL);
327 if (!up->dmadesc)
328 goto err_alloc;
329
330 /* ... */
331err_alloc:
332 pxa_free_dma(up->txdma);
333err_rxdma:
334 pxa_free_dma(up->rxdma);
335out:
336 return;
337}
338#endif
339
340static int serial_pxa_startup(struct uart_port *port)
341{
342 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
343 unsigned long flags;
344 int retval;
345
346 if (port->line == 3) /* HWUART */
347 up->mcr |= UART_MCR_AFE;
348 else
349 up->mcr = 0;
350
351 up->port.uartclk = clk_get_rate(up->clk);
352
353 /*
354 * Allocate the IRQ
355 */
356 retval = request_irq(up->port.irq, serial_pxa_irq, 0, up->name, up);
357 if (retval)
358 return retval;
359
360 /*
361 * Clear the FIFO buffers and disable them.
362 * (they will be reenabled in set_termios())
363 */
364 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
365 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
366 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
367 serial_out(up, UART_FCR, 0);
368
369 /*
370 * Clear the interrupt registers.
371 */
372 (void) serial_in(up, UART_LSR);
373 (void) serial_in(up, UART_RX);
374 (void) serial_in(up, UART_IIR);
375 (void) serial_in(up, UART_MSR);
376
377 /*
378 * Now, initialize the UART
379 */
380 serial_out(up, UART_LCR, UART_LCR_WLEN8);
381
382 spin_lock_irqsave(&up->port.lock, flags);
383 up->port.mctrl |= TIOCM_OUT2;
384 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
385 spin_unlock_irqrestore(&up->port.lock, flags);
386
387 /*
388 * Finally, enable interrupts. Note: Modem status interrupts
389 * are set via set_termios(), which will be occurring imminently
390 * anyway, so we don't enable them here.
391 */
392 up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE | UART_IER_UUE;
393 serial_out(up, UART_IER, up->ier);
394
395 /*
396 * And clear the interrupt registers again for luck.
397 */
398 (void) serial_in(up, UART_LSR);
399 (void) serial_in(up, UART_RX);
400 (void) serial_in(up, UART_IIR);
401 (void) serial_in(up, UART_MSR);
402
403 return 0;
404}
405
406static void serial_pxa_shutdown(struct uart_port *port)
407{
408 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
409 unsigned long flags;
410
411 free_irq(up->port.irq, up);
412
413 /*
414 * Disable interrupts from this port
415 */
416 up->ier = 0;
417 serial_out(up, UART_IER, 0);
418
419 spin_lock_irqsave(&up->port.lock, flags);
420 up->port.mctrl &= ~TIOCM_OUT2;
421 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
422 spin_unlock_irqrestore(&up->port.lock, flags);
423
424 /*
425 * Disable break condition and FIFOs
426 */
427 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
428 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
429 UART_FCR_CLEAR_RCVR |
430 UART_FCR_CLEAR_XMIT);
431 serial_out(up, UART_FCR, 0);
432}
433
434static void
435serial_pxa_set_termios(struct uart_port *port, struct ktermios *termios,
436 struct ktermios *old)
437{
438 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
439 unsigned char cval, fcr = 0;
440 unsigned long flags;
441 unsigned int baud, quot;
442 unsigned int dll;
443
444 switch (termios->c_cflag & CSIZE) {
445 case CS5:
446 cval = UART_LCR_WLEN5;
447 break;
448 case CS6:
449 cval = UART_LCR_WLEN6;
450 break;
451 case CS7:
452 cval = UART_LCR_WLEN7;
453 break;
454 default:
455 case CS8:
456 cval = UART_LCR_WLEN8;
457 break;
458 }
459
460 if (termios->c_cflag & CSTOPB)
461 cval |= UART_LCR_STOP;
462 if (termios->c_cflag & PARENB)
463 cval |= UART_LCR_PARITY;
464 if (!(termios->c_cflag & PARODD))
465 cval |= UART_LCR_EPAR;
466
467 /*
468 * Ask the core to calculate the divisor for us.
469 */
470 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
471 quot = uart_get_divisor(port, baud);
472
473 if ((up->port.uartclk / quot) < (2400 * 16))
474 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR1;
475 else if ((up->port.uartclk / quot) < (230400 * 16))
476 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR8;
477 else
478 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR32;
479
480 /*
481 * Ok, we're now changing the port state. Do it with
482 * interrupts disabled.
483 */
484 spin_lock_irqsave(&up->port.lock, flags);
485
486 /*
487 * Ensure the port will be enabled.
488 * This is required especially for serial console.
489 */
490 up->ier |= UART_IER_UUE;
491
492 /*
493 * Update the per-port timeout.
494 */
495 uart_update_timeout(port, termios->c_cflag, baud);
496
497 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
498 if (termios->c_iflag & INPCK)
499 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
500 if (termios->c_iflag & (BRKINT | PARMRK))
501 up->port.read_status_mask |= UART_LSR_BI;
502
503 /*
504 * Characters to ignore
505 */
506 up->port.ignore_status_mask = 0;
507 if (termios->c_iflag & IGNPAR)
508 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
509 if (termios->c_iflag & IGNBRK) {
510 up->port.ignore_status_mask |= UART_LSR_BI;
511 /*
512 * If we're ignoring parity and break indicators,
513 * ignore overruns too (for real raw support).
514 */
515 if (termios->c_iflag & IGNPAR)
516 up->port.ignore_status_mask |= UART_LSR_OE;
517 }
518
519 /*
520 * ignore all characters if CREAD is not set
521 */
522 if ((termios->c_cflag & CREAD) == 0)
523 up->port.ignore_status_mask |= UART_LSR_DR;
524
525 /*
526 * CTS flow control flag and modem status interrupts
527 */
528 up->ier &= ~UART_IER_MSI;
529 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
530 up->ier |= UART_IER_MSI;
531
532 serial_out(up, UART_IER, up->ier);
533
534 if (termios->c_cflag & CRTSCTS)
535 up->mcr |= UART_MCR_AFE;
536 else
537 up->mcr &= ~UART_MCR_AFE;
538
539 serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
540 serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */
541
542 /*
543 * work around Errata #75 according to Intel(R) PXA27x Processor Family
544 * Specification Update (Nov 2005)
545 */
546 dll = serial_in(up, UART_DLL);
547 WARN_ON(dll != (quot & 0xff));
548
549 serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
550 serial_out(up, UART_LCR, cval); /* reset DLAB */
551 up->lcr = cval; /* Save LCR */
552 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
553 serial_out(up, UART_FCR, fcr);
554 spin_unlock_irqrestore(&up->port.lock, flags);
555}
556
557static void
558serial_pxa_pm(struct uart_port *port, unsigned int state,
559 unsigned int oldstate)
560{
561 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
562
563 if (!state)
564 clk_enable(up->clk);
565 else
566 clk_disable(up->clk);
567}
568
569static void serial_pxa_release_port(struct uart_port *port)
570{
571}
572
573static int serial_pxa_request_port(struct uart_port *port)
574{
575 return 0;
576}
577
578static void serial_pxa_config_port(struct uart_port *port, int flags)
579{
580 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
581 up->port.type = PORT_PXA;
582}
583
584static int
585serial_pxa_verify_port(struct uart_port *port, struct serial_struct *ser)
586{
587 /* we don't want the core code to modify any port params */
588 return -EINVAL;
589}
590
591static const char *
592serial_pxa_type(struct uart_port *port)
593{
594 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
595 return up->name;
596}
597
598static struct uart_pxa_port *serial_pxa_ports[4];
599static struct uart_driver serial_pxa_reg;
600
601#ifdef CONFIG_SERIAL_PXA_CONSOLE
602
603#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
604
605/*
606 * Wait for transmitter & holding register to empty
607 */
608static inline void wait_for_xmitr(struct uart_pxa_port *up)
609{
610 unsigned int status, tmout = 10000;
611
612 /* Wait up to 10ms for the character(s) to be sent. */
613 do {
614 status = serial_in(up, UART_LSR);
615
616 if (status & UART_LSR_BI)
617 up->lsr_break_flag = UART_LSR_BI;
618
619 if (--tmout == 0)
620 break;
621 udelay(1);
622 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
623
624 /* Wait up to 1s for flow control if necessary */
625 if (up->port.flags & UPF_CONS_FLOW) {
626 tmout = 1000000;
627 while (--tmout &&
628 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
629 udelay(1);
630 }
631}
632
633static void serial_pxa_console_putchar(struct uart_port *port, int ch)
634{
635 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
636
637 wait_for_xmitr(up);
638 serial_out(up, UART_TX, ch);
639}
640
641/*
642 * Print a string to the serial port trying not to disturb
643 * any possible real use of the port...
644 *
645 * The console_lock must be held when we get here.
646 */
647static void
648serial_pxa_console_write(struct console *co, const char *s, unsigned int count)
649{
650 struct uart_pxa_port *up = serial_pxa_ports[co->index];
651 unsigned int ier;
652
653 clk_enable(up->clk);
654
655 /*
656 * First save the IER then disable the interrupts
657 */
658 ier = serial_in(up, UART_IER);
659 serial_out(up, UART_IER, UART_IER_UUE);
660
661 uart_console_write(&up->port, s, count, serial_pxa_console_putchar);
662
663 /*
664 * Finally, wait for transmitter to become empty
665 * and restore the IER
666 */
667 wait_for_xmitr(up);
668 serial_out(up, UART_IER, ier);
669
670 clk_disable(up->clk);
671}
672
673static int __init
674serial_pxa_console_setup(struct console *co, char *options)
675{
676 struct uart_pxa_port *up;
677 int baud = 9600;
678 int bits = 8;
679 int parity = 'n';
680 int flow = 'n';
681
682 if (co->index == -1 || co->index >= serial_pxa_reg.nr)
683 co->index = 0;
684 up = serial_pxa_ports[co->index];
685 if (!up)
686 return -ENODEV;
687
688 if (options)
689 uart_parse_options(options, &baud, &parity, &bits, &flow);
690
691 return uart_set_options(&up->port, co, baud, parity, bits, flow);
692}
693
694static struct console serial_pxa_console = {
695 .name = "ttyS",
696 .write = serial_pxa_console_write,
697 .device = uart_console_device,
698 .setup = serial_pxa_console_setup,
699 .flags = CON_PRINTBUFFER,
700 .index = -1,
701 .data = &serial_pxa_reg,
702};
703
704#define PXA_CONSOLE &serial_pxa_console
705#else
706#define PXA_CONSOLE NULL
707#endif
708
709struct uart_ops serial_pxa_pops = {
710 .tx_empty = serial_pxa_tx_empty,
711 .set_mctrl = serial_pxa_set_mctrl,
712 .get_mctrl = serial_pxa_get_mctrl,
713 .stop_tx = serial_pxa_stop_tx,
714 .start_tx = serial_pxa_start_tx,
715 .stop_rx = serial_pxa_stop_rx,
716 .enable_ms = serial_pxa_enable_ms,
717 .break_ctl = serial_pxa_break_ctl,
718 .startup = serial_pxa_startup,
719 .shutdown = serial_pxa_shutdown,
720 .set_termios = serial_pxa_set_termios,
721 .pm = serial_pxa_pm,
722 .type = serial_pxa_type,
723 .release_port = serial_pxa_release_port,
724 .request_port = serial_pxa_request_port,
725 .config_port = serial_pxa_config_port,
726 .verify_port = serial_pxa_verify_port,
727};
728
729static struct uart_driver serial_pxa_reg = {
730 .owner = THIS_MODULE,
731 .driver_name = "PXA serial",
732 .dev_name = "ttyS",
733 .major = TTY_MAJOR,
734 .minor = 64,
735 .nr = 4,
736 .cons = PXA_CONSOLE,
737};
738
739#ifdef CONFIG_PM
740static int serial_pxa_suspend(struct device *dev)
741{
742 struct uart_pxa_port *sport = dev_get_drvdata(dev);
743
744 if (sport)
745 uart_suspend_port(&serial_pxa_reg, &sport->port);
746
747 return 0;
748}
749
750static int serial_pxa_resume(struct device *dev)
751{
752 struct uart_pxa_port *sport = dev_get_drvdata(dev);
753
754 if (sport)
755 uart_resume_port(&serial_pxa_reg, &sport->port);
756
757 return 0;
758}
759
760static const struct dev_pm_ops serial_pxa_pm_ops = {
761 .suspend = serial_pxa_suspend,
762 .resume = serial_pxa_resume,
763};
764#endif
765
766static int serial_pxa_probe(struct platform_device *dev)
767{
768 struct uart_pxa_port *sport;
769 struct resource *mmres, *irqres;
770 int ret;
771
772 mmres = platform_get_resource(dev, IORESOURCE_MEM, 0);
773 irqres = platform_get_resource(dev, IORESOURCE_IRQ, 0);
774 if (!mmres || !irqres)
775 return -ENODEV;
776
777 sport = kzalloc(sizeof(struct uart_pxa_port), GFP_KERNEL);
778 if (!sport)
779 return -ENOMEM;
780
781 sport->clk = clk_get(&dev->dev, NULL);
782 if (IS_ERR(sport->clk)) {
783 ret = PTR_ERR(sport->clk);
784 goto err_free;
785 }
786
787 sport->port.type = PORT_PXA;
788 sport->port.iotype = UPIO_MEM;
789 sport->port.mapbase = mmres->start;
790 sport->port.irq = irqres->start;
791 sport->port.fifosize = 64;
792 sport->port.ops = &serial_pxa_pops;
793 sport->port.line = dev->id;
794 sport->port.dev = &dev->dev;
795 sport->port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
796 sport->port.uartclk = clk_get_rate(sport->clk);
797
798 switch (dev->id) {
799 case 0: sport->name = "FFUART"; break;
800 case 1: sport->name = "BTUART"; break;
801 case 2: sport->name = "STUART"; break;
802 case 3: sport->name = "HWUART"; break;
803 default:
804 sport->name = "???";
805 break;
806 }
807
808 sport->port.membase = ioremap(mmres->start, mmres->end - mmres->start + 1);
809 if (!sport->port.membase) {
810 ret = -ENOMEM;
811 goto err_clk;
812 }
813
814 serial_pxa_ports[dev->id] = sport;
815
816 uart_add_one_port(&serial_pxa_reg, &sport->port);
817 platform_set_drvdata(dev, sport);
818
819 return 0;
820
821 err_clk:
822 clk_put(sport->clk);
823 err_free:
824 kfree(sport);
825 return ret;
826}
827
828static int serial_pxa_remove(struct platform_device *dev)
829{
830 struct uart_pxa_port *sport = platform_get_drvdata(dev);
831
832 platform_set_drvdata(dev, NULL);
833
834 uart_remove_one_port(&serial_pxa_reg, &sport->port);
835 clk_put(sport->clk);
836 kfree(sport);
837
838 return 0;
839}
840
841static struct platform_driver serial_pxa_driver = {
842 .probe = serial_pxa_probe,
843 .remove = serial_pxa_remove,
844
845 .driver = {
846 .name = "pxa2xx-uart",
847 .owner = THIS_MODULE,
848#ifdef CONFIG_PM
849 .pm = &serial_pxa_pm_ops,
850#endif
851 },
852};
853
854int __init serial_pxa_init(void)
855{
856 int ret;
857
858 ret = uart_register_driver(&serial_pxa_reg);
859 if (ret != 0)
860 return ret;
861
862 ret = platform_driver_register(&serial_pxa_driver);
863 if (ret != 0)
864 uart_unregister_driver(&serial_pxa_reg);
865
866 return ret;
867}
868
869void __exit serial_pxa_exit(void)
870{
871 platform_driver_unregister(&serial_pxa_driver);
872 uart_unregister_driver(&serial_pxa_reg);
873}
874
875module_init(serial_pxa_init);
876module_exit(serial_pxa_exit);
877
878MODULE_LICENSE("GPL");
879MODULE_ALIAS("platform:pxa2xx-uart");
diff --git a/drivers/serial/s3c2400.c b/drivers/serial/s3c2400.c
deleted file mode 100644
index fed1a9a1ffb4..000000000000
--- a/drivers/serial/s3c2400.c
+++ /dev/null
@@ -1,106 +0,0 @@
1/* linux/drivers/serial/s3c240.c
2 *
3 * Driver for Samsung SoC onboard UARTs.
4 *
5 * Ben Dooks, Copyright (c) 2003-2005 Simtec Electronics
6 * http://armlinux.simtec.co.uk/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/module.h>
14#include <linux/ioport.h>
15#include <linux/io.h>
16#include <linux/platform_device.h>
17
18#include <asm/irq.h>
19
20#include <mach/hardware.h>
21
22#include <plat/regs-serial.h>
23#include <mach/regs-gpio.h>
24
25#include "samsung.h"
26
27static int s3c2400_serial_getsource(struct uart_port *port,
28 struct s3c24xx_uart_clksrc *clk)
29{
30 clk->divisor = 1;
31 clk->name = "pclk";
32
33 return 0;
34}
35
36static int s3c2400_serial_setsource(struct uart_port *port,
37 struct s3c24xx_uart_clksrc *clk)
38{
39 return 0;
40}
41
42static int s3c2400_serial_resetport(struct uart_port *port,
43 struct s3c2410_uartcfg *cfg)
44{
45 dbg("s3c2400_serial_resetport: port=%p (%08lx), cfg=%p\n",
46 port, port->mapbase, cfg);
47
48 wr_regl(port, S3C2410_UCON, cfg->ucon);
49 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
50
51 /* reset both fifos */
52
53 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
54 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
55
56 return 0;
57}
58
59static struct s3c24xx_uart_info s3c2400_uart_inf = {
60 .name = "Samsung S3C2400 UART",
61 .type = PORT_S3C2400,
62 .fifosize = 16,
63 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
64 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
65 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
66 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
67 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
68 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
69 .get_clksrc = s3c2400_serial_getsource,
70 .set_clksrc = s3c2400_serial_setsource,
71 .reset_port = s3c2400_serial_resetport,
72};
73
74static int s3c2400_serial_probe(struct platform_device *dev)
75{
76 return s3c24xx_serial_probe(dev, &s3c2400_uart_inf);
77}
78
79static struct platform_driver s3c2400_serial_driver = {
80 .probe = s3c2400_serial_probe,
81 .remove = __devexit_p(s3c24xx_serial_remove),
82 .driver = {
83 .name = "s3c2400-uart",
84 .owner = THIS_MODULE,
85 },
86};
87
88s3c24xx_console_init(&s3c2400_serial_driver, &s3c2400_uart_inf);
89
90static inline int s3c2400_serial_init(void)
91{
92 return s3c24xx_serial_init(&s3c2400_serial_driver, &s3c2400_uart_inf);
93}
94
95static inline void s3c2400_serial_exit(void)
96{
97 platform_driver_unregister(&s3c2400_serial_driver);
98}
99
100module_init(s3c2400_serial_init);
101module_exit(s3c2400_serial_exit);
102
103MODULE_LICENSE("GPL v2");
104MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
105MODULE_DESCRIPTION("Samsung S3C2400 SoC Serial port driver");
106MODULE_ALIAS("platform:s3c2400-uart");
diff --git a/drivers/serial/s3c2410.c b/drivers/serial/s3c2410.c
deleted file mode 100644
index 73f089d3efd6..000000000000
--- a/drivers/serial/s3c2410.c
+++ /dev/null
@@ -1,118 +0,0 @@
1/* linux/drivers/serial/s3c2410.c
2 *
3 * Driver for Samsung S3C2410 SoC onboard UARTs.
4 *
5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
6 * http://armlinux.simtec.co.uk/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/module.h>
14#include <linux/ioport.h>
15#include <linux/io.h>
16#include <linux/platform_device.h>
17#include <linux/init.h>
18#include <linux/serial_core.h>
19#include <linux/serial.h>
20
21#include <asm/irq.h>
22#include <mach/hardware.h>
23
24#include <plat/regs-serial.h>
25#include <mach/regs-gpio.h>
26
27#include "samsung.h"
28
29static int s3c2410_serial_setsource(struct uart_port *port,
30 struct s3c24xx_uart_clksrc *clk)
31{
32 unsigned long ucon = rd_regl(port, S3C2410_UCON);
33
34 if (strcmp(clk->name, "uclk") == 0)
35 ucon |= S3C2410_UCON_UCLK;
36 else
37 ucon &= ~S3C2410_UCON_UCLK;
38
39 wr_regl(port, S3C2410_UCON, ucon);
40 return 0;
41}
42
43static int s3c2410_serial_getsource(struct uart_port *port,
44 struct s3c24xx_uart_clksrc *clk)
45{
46 unsigned long ucon = rd_regl(port, S3C2410_UCON);
47
48 clk->divisor = 1;
49 clk->name = (ucon & S3C2410_UCON_UCLK) ? "uclk" : "pclk";
50
51 return 0;
52}
53
54static int s3c2410_serial_resetport(struct uart_port *port,
55 struct s3c2410_uartcfg *cfg)
56{
57 dbg("s3c2410_serial_resetport: port=%p (%08lx), cfg=%p\n",
58 port, port->mapbase, cfg);
59
60 wr_regl(port, S3C2410_UCON, cfg->ucon);
61 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
62
63 /* reset both fifos */
64
65 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
66 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
67
68 return 0;
69}
70
71static struct s3c24xx_uart_info s3c2410_uart_inf = {
72 .name = "Samsung S3C2410 UART",
73 .type = PORT_S3C2410,
74 .fifosize = 16,
75 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
76 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
77 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
78 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
79 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
80 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
81 .get_clksrc = s3c2410_serial_getsource,
82 .set_clksrc = s3c2410_serial_setsource,
83 .reset_port = s3c2410_serial_resetport,
84};
85
86static int s3c2410_serial_probe(struct platform_device *dev)
87{
88 return s3c24xx_serial_probe(dev, &s3c2410_uart_inf);
89}
90
91static struct platform_driver s3c2410_serial_driver = {
92 .probe = s3c2410_serial_probe,
93 .remove = __devexit_p(s3c24xx_serial_remove),
94 .driver = {
95 .name = "s3c2410-uart",
96 .owner = THIS_MODULE,
97 },
98};
99
100s3c24xx_console_init(&s3c2410_serial_driver, &s3c2410_uart_inf);
101
102static int __init s3c2410_serial_init(void)
103{
104 return s3c24xx_serial_init(&s3c2410_serial_driver, &s3c2410_uart_inf);
105}
106
107static void __exit s3c2410_serial_exit(void)
108{
109 platform_driver_unregister(&s3c2410_serial_driver);
110}
111
112module_init(s3c2410_serial_init);
113module_exit(s3c2410_serial_exit);
114
115MODULE_LICENSE("GPL v2");
116MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
117MODULE_DESCRIPTION("Samsung S3C2410 SoC Serial port driver");
118MODULE_ALIAS("platform:s3c2410-uart");
diff --git a/drivers/serial/s3c2412.c b/drivers/serial/s3c2412.c
deleted file mode 100644
index 1700b1a2fb7e..000000000000
--- a/drivers/serial/s3c2412.c
+++ /dev/null
@@ -1,152 +0,0 @@
1/* linux/drivers/serial/s3c2412.c
2 *
3 * Driver for Samsung S3C2412 and S3C2413 SoC onboard UARTs.
4 *
5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
6 * http://armlinux.simtec.co.uk/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/module.h>
14#include <linux/ioport.h>
15#include <linux/io.h>
16#include <linux/platform_device.h>
17#include <linux/init.h>
18#include <linux/serial_core.h>
19#include <linux/serial.h>
20
21#include <asm/irq.h>
22#include <mach/hardware.h>
23
24#include <plat/regs-serial.h>
25#include <mach/regs-gpio.h>
26
27#include "samsung.h"
28
29static int s3c2412_serial_setsource(struct uart_port *port,
30 struct s3c24xx_uart_clksrc *clk)
31{
32 unsigned long ucon = rd_regl(port, S3C2410_UCON);
33
34 ucon &= ~S3C2412_UCON_CLKMASK;
35
36 if (strcmp(clk->name, "uclk") == 0)
37 ucon |= S3C2440_UCON_UCLK;
38 else if (strcmp(clk->name, "pclk") == 0)
39 ucon |= S3C2440_UCON_PCLK;
40 else if (strcmp(clk->name, "usysclk") == 0)
41 ucon |= S3C2412_UCON_USYSCLK;
42 else {
43 printk(KERN_ERR "unknown clock source %s\n", clk->name);
44 return -EINVAL;
45 }
46
47 wr_regl(port, S3C2410_UCON, ucon);
48 return 0;
49}
50
51
52static int s3c2412_serial_getsource(struct uart_port *port,
53 struct s3c24xx_uart_clksrc *clk)
54{
55 unsigned long ucon = rd_regl(port, S3C2410_UCON);
56
57 switch (ucon & S3C2412_UCON_CLKMASK) {
58 case S3C2412_UCON_UCLK:
59 clk->divisor = 1;
60 clk->name = "uclk";
61 break;
62
63 case S3C2412_UCON_PCLK:
64 case S3C2412_UCON_PCLK2:
65 clk->divisor = 1;
66 clk->name = "pclk";
67 break;
68
69 case S3C2412_UCON_USYSCLK:
70 clk->divisor = 1;
71 clk->name = "usysclk";
72 break;
73 }
74
75 return 0;
76}
77
78static int s3c2412_serial_resetport(struct uart_port *port,
79 struct s3c2410_uartcfg *cfg)
80{
81 unsigned long ucon = rd_regl(port, S3C2410_UCON);
82
83 dbg("%s: port=%p (%08lx), cfg=%p\n",
84 __func__, port, port->mapbase, cfg);
85
86 /* ensure we don't change the clock settings... */
87
88 ucon &= S3C2412_UCON_CLKMASK;
89
90 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
91 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
92
93 /* reset both fifos */
94
95 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
96 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
97
98 return 0;
99}
100
101static struct s3c24xx_uart_info s3c2412_uart_inf = {
102 .name = "Samsung S3C2412 UART",
103 .type = PORT_S3C2412,
104 .fifosize = 64,
105 .has_divslot = 1,
106 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
107 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
108 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
109 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
110 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
111 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
112 .get_clksrc = s3c2412_serial_getsource,
113 .set_clksrc = s3c2412_serial_setsource,
114 .reset_port = s3c2412_serial_resetport,
115};
116
117/* device management */
118
119static int s3c2412_serial_probe(struct platform_device *dev)
120{
121 dbg("s3c2440_serial_probe: dev=%p\n", dev);
122 return s3c24xx_serial_probe(dev, &s3c2412_uart_inf);
123}
124
125static struct platform_driver s3c2412_serial_driver = {
126 .probe = s3c2412_serial_probe,
127 .remove = __devexit_p(s3c24xx_serial_remove),
128 .driver = {
129 .name = "s3c2412-uart",
130 .owner = THIS_MODULE,
131 },
132};
133
134s3c24xx_console_init(&s3c2412_serial_driver, &s3c2412_uart_inf);
135
136static inline int s3c2412_serial_init(void)
137{
138 return s3c24xx_serial_init(&s3c2412_serial_driver, &s3c2412_uart_inf);
139}
140
141static inline void s3c2412_serial_exit(void)
142{
143 platform_driver_unregister(&s3c2412_serial_driver);
144}
145
146module_init(s3c2412_serial_init);
147module_exit(s3c2412_serial_exit);
148
149MODULE_DESCRIPTION("Samsung S3C2412,S3C2413 SoC Serial port driver");
150MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
151MODULE_LICENSE("GPL v2");
152MODULE_ALIAS("platform:s3c2412-uart");
diff --git a/drivers/serial/s3c2440.c b/drivers/serial/s3c2440.c
deleted file mode 100644
index 094cc3904b13..000000000000
--- a/drivers/serial/s3c2440.c
+++ /dev/null
@@ -1,181 +0,0 @@
1/* linux/drivers/serial/s3c2440.c
2 *
3 * Driver for Samsung S3C2440 and S3C2442 SoC onboard UARTs.
4 *
5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
6 * http://armlinux.simtec.co.uk/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/module.h>
14#include <linux/ioport.h>
15#include <linux/io.h>
16#include <linux/platform_device.h>
17#include <linux/init.h>
18#include <linux/serial_core.h>
19#include <linux/serial.h>
20
21#include <asm/irq.h>
22#include <mach/hardware.h>
23
24#include <plat/regs-serial.h>
25#include <mach/regs-gpio.h>
26
27#include "samsung.h"
28
29
30static int s3c2440_serial_setsource(struct uart_port *port,
31 struct s3c24xx_uart_clksrc *clk)
32{
33 unsigned long ucon = rd_regl(port, S3C2410_UCON);
34
35 /* todo - proper fclk<>nonfclk switch. */
36
37 ucon &= ~S3C2440_UCON_CLKMASK;
38
39 if (strcmp(clk->name, "uclk") == 0)
40 ucon |= S3C2440_UCON_UCLK;
41 else if (strcmp(clk->name, "pclk") == 0)
42 ucon |= S3C2440_UCON_PCLK;
43 else if (strcmp(clk->name, "fclk") == 0)
44 ucon |= S3C2440_UCON_FCLK;
45 else {
46 printk(KERN_ERR "unknown clock source %s\n", clk->name);
47 return -EINVAL;
48 }
49
50 wr_regl(port, S3C2410_UCON, ucon);
51 return 0;
52}
53
54
55static int s3c2440_serial_getsource(struct uart_port *port,
56 struct s3c24xx_uart_clksrc *clk)
57{
58 unsigned long ucon = rd_regl(port, S3C2410_UCON);
59 unsigned long ucon0, ucon1, ucon2;
60
61 switch (ucon & S3C2440_UCON_CLKMASK) {
62 case S3C2440_UCON_UCLK:
63 clk->divisor = 1;
64 clk->name = "uclk";
65 break;
66
67 case S3C2440_UCON_PCLK:
68 case S3C2440_UCON_PCLK2:
69 clk->divisor = 1;
70 clk->name = "pclk";
71 break;
72
73 case S3C2440_UCON_FCLK:
74 /* the fun of calculating the uart divisors on
75 * the s3c2440 */
76
77 ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON);
78 ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON);
79 ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON);
80
81 printk("ucons: %08lx, %08lx, %08lx\n", ucon0, ucon1, ucon2);
82
83 ucon0 &= S3C2440_UCON0_DIVMASK;
84 ucon1 &= S3C2440_UCON1_DIVMASK;
85 ucon2 &= S3C2440_UCON2_DIVMASK;
86
87 if (ucon0 != 0) {
88 clk->divisor = ucon0 >> S3C2440_UCON_DIVSHIFT;
89 clk->divisor += 6;
90 } else if (ucon1 != 0) {
91 clk->divisor = ucon1 >> S3C2440_UCON_DIVSHIFT;
92 clk->divisor += 21;
93 } else if (ucon2 != 0) {
94 clk->divisor = ucon2 >> S3C2440_UCON_DIVSHIFT;
95 clk->divisor += 36;
96 } else {
97 /* manual calims 44, seems to be 9 */
98 clk->divisor = 9;
99 }
100
101 clk->name = "fclk";
102 break;
103 }
104
105 return 0;
106}
107
108static int s3c2440_serial_resetport(struct uart_port *port,
109 struct s3c2410_uartcfg *cfg)
110{
111 unsigned long ucon = rd_regl(port, S3C2410_UCON);
112
113 dbg("s3c2440_serial_resetport: port=%p (%08lx), cfg=%p\n",
114 port, port->mapbase, cfg);
115
116 /* ensure we don't change the clock settings... */
117
118 ucon &= (S3C2440_UCON0_DIVMASK | (3<<10));
119
120 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
121 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
122
123 /* reset both fifos */
124
125 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
126 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
127
128 return 0;
129}
130
131static struct s3c24xx_uart_info s3c2440_uart_inf = {
132 .name = "Samsung S3C2440 UART",
133 .type = PORT_S3C2440,
134 .fifosize = 64,
135 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
136 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
137 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
138 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
139 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
140 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
141 .get_clksrc = s3c2440_serial_getsource,
142 .set_clksrc = s3c2440_serial_setsource,
143 .reset_port = s3c2440_serial_resetport,
144};
145
146/* device management */
147
148static int s3c2440_serial_probe(struct platform_device *dev)
149{
150 dbg("s3c2440_serial_probe: dev=%p\n", dev);
151 return s3c24xx_serial_probe(dev, &s3c2440_uart_inf);
152}
153
154static struct platform_driver s3c2440_serial_driver = {
155 .probe = s3c2440_serial_probe,
156 .remove = __devexit_p(s3c24xx_serial_remove),
157 .driver = {
158 .name = "s3c2440-uart",
159 .owner = THIS_MODULE,
160 },
161};
162
163s3c24xx_console_init(&s3c2440_serial_driver, &s3c2440_uart_inf);
164
165static int __init s3c2440_serial_init(void)
166{
167 return s3c24xx_serial_init(&s3c2440_serial_driver, &s3c2440_uart_inf);
168}
169
170static void __exit s3c2440_serial_exit(void)
171{
172 platform_driver_unregister(&s3c2440_serial_driver);
173}
174
175module_init(s3c2440_serial_init);
176module_exit(s3c2440_serial_exit);
177
178MODULE_DESCRIPTION("Samsung S3C2440,S3C2442 SoC Serial port driver");
179MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
180MODULE_LICENSE("GPL v2");
181MODULE_ALIAS("platform:s3c2440-uart");
diff --git a/drivers/serial/s3c24a0.c b/drivers/serial/s3c24a0.c
deleted file mode 100644
index fad6083ca427..000000000000
--- a/drivers/serial/s3c24a0.c
+++ /dev/null
@@ -1,118 +0,0 @@
1/* linux/drivers/serial/s3c24a0.c
2 *
3 * Driver for Samsung S3C24A0 SoC onboard UARTs.
4 *
5 * Based on drivers/serial/s3c2410.c
6 *
7 * Author: Sandeep Patil <sandeep.patil@azingo.com>
8 *
9 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
10 * http://armlinux.simtec.co.uk/
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15*/
16
17#include <linux/module.h>
18#include <linux/ioport.h>
19#include <linux/platform_device.h>
20#include <linux/init.h>
21#include <linux/serial_core.h>
22#include <linux/serial.h>
23#include <linux/io.h>
24#include <linux/irq.h>
25
26#include <mach/hardware.h>
27
28#include <plat/regs-serial.h>
29#include <mach/regs-gpio.h>
30
31#include "samsung.h"
32
33static int s3c24a0_serial_setsource(struct uart_port *port,
34 struct s3c24xx_uart_clksrc *clk)
35{
36 unsigned long ucon = rd_regl(port, S3C2410_UCON);
37
38 if (strcmp(clk->name, "uclk") == 0)
39 ucon |= S3C2410_UCON_UCLK;
40 else
41 ucon &= ~S3C2410_UCON_UCLK;
42
43 wr_regl(port, S3C2410_UCON, ucon);
44 return 0;
45}
46
47static int s3c24a0_serial_getsource(struct uart_port *port,
48 struct s3c24xx_uart_clksrc *clk)
49{
50 unsigned long ucon = rd_regl(port, S3C2410_UCON);
51
52 clk->divisor = 1;
53 clk->name = (ucon & S3C2410_UCON_UCLK) ? "uclk" : "pclk";
54
55 return 0;
56}
57
58static int s3c24a0_serial_resetport(struct uart_port *port,
59 struct s3c2410_uartcfg *cfg)
60{
61 dbg("s3c24a0_serial_resetport: port=%p (%08lx), cfg=%p\n",
62 port, port->mapbase, cfg);
63
64 wr_regl(port, S3C2410_UCON, cfg->ucon);
65 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
66
67 /* reset both fifos */
68
69 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
70 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
71
72 return 0;
73}
74
75static struct s3c24xx_uart_info s3c24a0_uart_inf = {
76 .name = "Samsung S3C24A0 UART",
77 .type = PORT_S3C2410,
78 .fifosize = 16,
79 .rx_fifomask = S3C24A0_UFSTAT_RXMASK,
80 .rx_fifoshift = S3C24A0_UFSTAT_RXSHIFT,
81 .rx_fifofull = S3C24A0_UFSTAT_RXFULL,
82 .tx_fifofull = S3C24A0_UFSTAT_TXFULL,
83 .tx_fifomask = S3C24A0_UFSTAT_TXMASK,
84 .tx_fifoshift = S3C24A0_UFSTAT_TXSHIFT,
85 .get_clksrc = s3c24a0_serial_getsource,
86 .set_clksrc = s3c24a0_serial_setsource,
87 .reset_port = s3c24a0_serial_resetport,
88};
89
90static int s3c24a0_serial_probe(struct platform_device *dev)
91{
92 return s3c24xx_serial_probe(dev, &s3c24a0_uart_inf);
93}
94
95static struct platform_driver s3c24a0_serial_driver = {
96 .probe = s3c24a0_serial_probe,
97 .remove = __devexit_p(s3c24xx_serial_remove),
98 .driver = {
99 .name = "s3c24a0-uart",
100 .owner = THIS_MODULE,
101 },
102};
103
104s3c24xx_console_init(&s3c24a0_serial_driver, &s3c24a0_uart_inf);
105
106static int __init s3c24a0_serial_init(void)
107{
108 return s3c24xx_serial_init(&s3c24a0_serial_driver, &s3c24a0_uart_inf);
109}
110
111static void __exit s3c24a0_serial_exit(void)
112{
113 platform_driver_unregister(&s3c24a0_serial_driver);
114}
115
116module_init(s3c24a0_serial_init);
117module_exit(s3c24a0_serial_exit);
118
diff --git a/drivers/serial/s3c6400.c b/drivers/serial/s3c6400.c
deleted file mode 100644
index 4be92ab50058..000000000000
--- a/drivers/serial/s3c6400.c
+++ /dev/null
@@ -1,152 +0,0 @@
1/* linux/drivers/serial/s3c6400.c
2 *
3 * Driver for Samsung S3C6400 and S3C6410 SoC onboard UARTs.
4 *
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/module.h>
16#include <linux/ioport.h>
17#include <linux/io.h>
18#include <linux/platform_device.h>
19#include <linux/init.h>
20#include <linux/serial_core.h>
21#include <linux/serial.h>
22
23#include <asm/irq.h>
24#include <mach/hardware.h>
25
26#include <plat/regs-serial.h>
27
28#include "samsung.h"
29
30static int s3c6400_serial_setsource(struct uart_port *port,
31 struct s3c24xx_uart_clksrc *clk)
32{
33 unsigned long ucon = rd_regl(port, S3C2410_UCON);
34
35 if (strcmp(clk->name, "uclk0") == 0) {
36 ucon &= ~S3C6400_UCON_CLKMASK;
37 ucon |= S3C6400_UCON_UCLK0;
38 } else if (strcmp(clk->name, "uclk1") == 0)
39 ucon |= S3C6400_UCON_UCLK1;
40 else if (strcmp(clk->name, "pclk") == 0) {
41 /* See notes about transitioning from UCLK to PCLK */
42 ucon &= ~S3C6400_UCON_UCLK0;
43 } else {
44 printk(KERN_ERR "unknown clock source %s\n", clk->name);
45 return -EINVAL;
46 }
47
48 wr_regl(port, S3C2410_UCON, ucon);
49 return 0;
50}
51
52
53static int s3c6400_serial_getsource(struct uart_port *port,
54 struct s3c24xx_uart_clksrc *clk)
55{
56 u32 ucon = rd_regl(port, S3C2410_UCON);
57
58 clk->divisor = 1;
59
60 switch (ucon & S3C6400_UCON_CLKMASK) {
61 case S3C6400_UCON_UCLK0:
62 clk->name = "uclk0";
63 break;
64
65 case S3C6400_UCON_UCLK1:
66 clk->name = "uclk1";
67 break;
68
69 case S3C6400_UCON_PCLK:
70 case S3C6400_UCON_PCLK2:
71 clk->name = "pclk";
72 break;
73 }
74
75 return 0;
76}
77
78static int s3c6400_serial_resetport(struct uart_port *port,
79 struct s3c2410_uartcfg *cfg)
80{
81 unsigned long ucon = rd_regl(port, S3C2410_UCON);
82
83 dbg("s3c6400_serial_resetport: port=%p (%08lx), cfg=%p\n",
84 port, port->mapbase, cfg);
85
86 /* ensure we don't change the clock settings... */
87
88 ucon &= S3C6400_UCON_CLKMASK;
89
90 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
91 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
92
93 /* reset both fifos */
94
95 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
96 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
97
98 return 0;
99}
100
101static struct s3c24xx_uart_info s3c6400_uart_inf = {
102 .name = "Samsung S3C6400 UART",
103 .type = PORT_S3C6400,
104 .fifosize = 64,
105 .has_divslot = 1,
106 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
107 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
108 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
109 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
110 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
111 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
112 .get_clksrc = s3c6400_serial_getsource,
113 .set_clksrc = s3c6400_serial_setsource,
114 .reset_port = s3c6400_serial_resetport,
115};
116
117/* device management */
118
119static int s3c6400_serial_probe(struct platform_device *dev)
120{
121 dbg("s3c6400_serial_probe: dev=%p\n", dev);
122 return s3c24xx_serial_probe(dev, &s3c6400_uart_inf);
123}
124
125static struct platform_driver s3c6400_serial_driver = {
126 .probe = s3c6400_serial_probe,
127 .remove = __devexit_p(s3c24xx_serial_remove),
128 .driver = {
129 .name = "s3c6400-uart",
130 .owner = THIS_MODULE,
131 },
132};
133
134s3c24xx_console_init(&s3c6400_serial_driver, &s3c6400_uart_inf);
135
136static int __init s3c6400_serial_init(void)
137{
138 return s3c24xx_serial_init(&s3c6400_serial_driver, &s3c6400_uart_inf);
139}
140
141static void __exit s3c6400_serial_exit(void)
142{
143 platform_driver_unregister(&s3c6400_serial_driver);
144}
145
146module_init(s3c6400_serial_init);
147module_exit(s3c6400_serial_exit);
148
149MODULE_DESCRIPTION("Samsung S3C6400,S3C6410 SoC Serial port driver");
150MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
151MODULE_LICENSE("GPL v2");
152MODULE_ALIAS("platform:s3c6400-uart");
diff --git a/drivers/serial/s5pv210.c b/drivers/serial/s5pv210.c
deleted file mode 100644
index 6ebccd70a707..000000000000
--- a/drivers/serial/s5pv210.c
+++ /dev/null
@@ -1,162 +0,0 @@
1/* linux/drivers/serial/s5pv210.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Based on drivers/serial/s3c6400.c
7 *
8 * Driver for Samsung S5PV210 SoC UARTs.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/module.h>
16#include <linux/ioport.h>
17#include <linux/io.h>
18#include <linux/platform_device.h>
19#include <linux/init.h>
20#include <linux/serial_core.h>
21#include <linux/serial.h>
22
23#include <asm/irq.h>
24#include <mach/hardware.h>
25#include <plat/regs-serial.h>
26#include "samsung.h"
27
28static int s5pv210_serial_setsource(struct uart_port *port,
29 struct s3c24xx_uart_clksrc *clk)
30{
31 struct s3c2410_uartcfg *cfg = port->dev->platform_data;
32 unsigned long ucon = rd_regl(port, S3C2410_UCON);
33
34 if ((cfg->clocks_size) == 1)
35 return 0;
36
37 if (strcmp(clk->name, "pclk") == 0)
38 ucon &= ~S5PV210_UCON_CLKMASK;
39 else if (strcmp(clk->name, "uclk1") == 0)
40 ucon |= S5PV210_UCON_CLKMASK;
41 else {
42 printk(KERN_ERR "unknown clock source %s\n", clk->name);
43 return -EINVAL;
44 }
45
46 wr_regl(port, S3C2410_UCON, ucon);
47 return 0;
48}
49
50
51static int s5pv210_serial_getsource(struct uart_port *port,
52 struct s3c24xx_uart_clksrc *clk)
53{
54 struct s3c2410_uartcfg *cfg = port->dev->platform_data;
55 u32 ucon = rd_regl(port, S3C2410_UCON);
56
57 clk->divisor = 1;
58
59 if ((cfg->clocks_size) == 1)
60 return 0;
61
62 switch (ucon & S5PV210_UCON_CLKMASK) {
63 case S5PV210_UCON_PCLK:
64 clk->name = "pclk";
65 break;
66 case S5PV210_UCON_UCLK:
67 clk->name = "uclk1";
68 break;
69 }
70
71 return 0;
72}
73
74static int s5pv210_serial_resetport(struct uart_port *port,
75 struct s3c2410_uartcfg *cfg)
76{
77 unsigned long ucon = rd_regl(port, S3C2410_UCON);
78
79 ucon &= S5PV210_UCON_CLKMASK;
80 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
81 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
82
83 /* reset both fifos */
84 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
85 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
86
87 return 0;
88}
89
90#define S5PV210_UART_DEFAULT_INFO(fifo_size) \
91 .name = "Samsung S5PV210 UART0", \
92 .type = PORT_S3C6400, \
93 .fifosize = fifo_size, \
94 .has_divslot = 1, \
95 .rx_fifomask = S5PV210_UFSTAT_RXMASK, \
96 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \
97 .rx_fifofull = S5PV210_UFSTAT_RXFULL, \
98 .tx_fifofull = S5PV210_UFSTAT_TXFULL, \
99 .tx_fifomask = S5PV210_UFSTAT_TXMASK, \
100 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \
101 .get_clksrc = s5pv210_serial_getsource, \
102 .set_clksrc = s5pv210_serial_setsource, \
103 .reset_port = s5pv210_serial_resetport
104
105static struct s3c24xx_uart_info s5p_port_fifo256 = {
106 S5PV210_UART_DEFAULT_INFO(256),
107};
108
109static struct s3c24xx_uart_info s5p_port_fifo64 = {
110 S5PV210_UART_DEFAULT_INFO(64),
111};
112
113static struct s3c24xx_uart_info s5p_port_fifo16 = {
114 S5PV210_UART_DEFAULT_INFO(16),
115};
116
117static struct s3c24xx_uart_info *s5p_uart_inf[] = {
118 [0] = &s5p_port_fifo256,
119 [1] = &s5p_port_fifo64,
120 [2] = &s5p_port_fifo16,
121 [3] = &s5p_port_fifo16,
122};
123
124/* device management */
125static int s5p_serial_probe(struct platform_device *pdev)
126{
127 return s3c24xx_serial_probe(pdev, s5p_uart_inf[pdev->id]);
128}
129
130static struct platform_driver s5p_serial_driver = {
131 .probe = s5p_serial_probe,
132 .remove = __devexit_p(s3c24xx_serial_remove),
133 .driver = {
134 .name = "s5pv210-uart",
135 .owner = THIS_MODULE,
136 },
137};
138
139static int __init s5pv210_serial_console_init(void)
140{
141 return s3c24xx_serial_initconsole(&s5p_serial_driver, s5p_uart_inf);
142}
143
144console_initcall(s5pv210_serial_console_init);
145
146static int __init s5p_serial_init(void)
147{
148 return s3c24xx_serial_init(&s5p_serial_driver, *s5p_uart_inf);
149}
150
151static void __exit s5p_serial_exit(void)
152{
153 platform_driver_unregister(&s5p_serial_driver);
154}
155
156module_init(s5p_serial_init);
157module_exit(s5p_serial_exit);
158
159MODULE_LICENSE("GPL");
160MODULE_ALIAS("platform:s5pv210-uart");
161MODULE_DESCRIPTION("Samsung S5PV210 UART Driver support");
162MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com>");
diff --git a/drivers/serial/sa1100.c b/drivers/serial/sa1100.c
deleted file mode 100644
index 2199d819a987..000000000000
--- a/drivers/serial/sa1100.c
+++ /dev/null
@@ -1,918 +0,0 @@
1/*
2 * linux/drivers/char/sa1100.c
3 *
4 * Driver for SA11x0 serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2000 Deep Blue Solutions Ltd.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */
24
25#if defined(CONFIG_SERIAL_SA1100_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
26#define SUPPORT_SYSRQ
27#endif
28
29#include <linux/module.h>
30#include <linux/ioport.h>
31#include <linux/init.h>
32#include <linux/console.h>
33#include <linux/sysrq.h>
34#include <linux/platform_device.h>
35#include <linux/tty.h>
36#include <linux/tty_flip.h>
37#include <linux/serial_core.h>
38#include <linux/serial.h>
39#include <linux/io.h>
40
41#include <asm/irq.h>
42#include <mach/hardware.h>
43#include <asm/mach/serial_sa1100.h>
44
45/* We've been assigned a range on the "Low-density serial ports" major */
46#define SERIAL_SA1100_MAJOR 204
47#define MINOR_START 5
48
49#define NR_PORTS 3
50
51#define SA1100_ISR_PASS_LIMIT 256
52
53/*
54 * Convert from ignore_status_mask or read_status_mask to UTSR[01]
55 */
56#define SM_TO_UTSR0(x) ((x) & 0xff)
57#define SM_TO_UTSR1(x) ((x) >> 8)
58#define UTSR0_TO_SM(x) ((x))
59#define UTSR1_TO_SM(x) ((x) << 8)
60
61#define UART_GET_UTCR0(sport) __raw_readl((sport)->port.membase + UTCR0)
62#define UART_GET_UTCR1(sport) __raw_readl((sport)->port.membase + UTCR1)
63#define UART_GET_UTCR2(sport) __raw_readl((sport)->port.membase + UTCR2)
64#define UART_GET_UTCR3(sport) __raw_readl((sport)->port.membase + UTCR3)
65#define UART_GET_UTSR0(sport) __raw_readl((sport)->port.membase + UTSR0)
66#define UART_GET_UTSR1(sport) __raw_readl((sport)->port.membase + UTSR1)
67#define UART_GET_CHAR(sport) __raw_readl((sport)->port.membase + UTDR)
68
69#define UART_PUT_UTCR0(sport,v) __raw_writel((v),(sport)->port.membase + UTCR0)
70#define UART_PUT_UTCR1(sport,v) __raw_writel((v),(sport)->port.membase + UTCR1)
71#define UART_PUT_UTCR2(sport,v) __raw_writel((v),(sport)->port.membase + UTCR2)
72#define UART_PUT_UTCR3(sport,v) __raw_writel((v),(sport)->port.membase + UTCR3)
73#define UART_PUT_UTSR0(sport,v) __raw_writel((v),(sport)->port.membase + UTSR0)
74#define UART_PUT_UTSR1(sport,v) __raw_writel((v),(sport)->port.membase + UTSR1)
75#define UART_PUT_CHAR(sport,v) __raw_writel((v),(sport)->port.membase + UTDR)
76
77/*
78 * This is the size of our serial port register set.
79 */
80#define UART_PORT_SIZE 0x24
81
82/*
83 * This determines how often we check the modem status signals
84 * for any change. They generally aren't connected to an IRQ
85 * so we have to poll them. We also check immediately before
86 * filling the TX fifo incase CTS has been dropped.
87 */
88#define MCTRL_TIMEOUT (250*HZ/1000)
89
90struct sa1100_port {
91 struct uart_port port;
92 struct timer_list timer;
93 unsigned int old_status;
94};
95
96/*
97 * Handle any change of modem status signal since we were last called.
98 */
99static void sa1100_mctrl_check(struct sa1100_port *sport)
100{
101 unsigned int status, changed;
102
103 status = sport->port.ops->get_mctrl(&sport->port);
104 changed = status ^ sport->old_status;
105
106 if (changed == 0)
107 return;
108
109 sport->old_status = status;
110
111 if (changed & TIOCM_RI)
112 sport->port.icount.rng++;
113 if (changed & TIOCM_DSR)
114 sport->port.icount.dsr++;
115 if (changed & TIOCM_CAR)
116 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
117 if (changed & TIOCM_CTS)
118 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
119
120 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
121}
122
123/*
124 * This is our per-port timeout handler, for checking the
125 * modem status signals.
126 */
127static void sa1100_timeout(unsigned long data)
128{
129 struct sa1100_port *sport = (struct sa1100_port *)data;
130 unsigned long flags;
131
132 if (sport->port.state) {
133 spin_lock_irqsave(&sport->port.lock, flags);
134 sa1100_mctrl_check(sport);
135 spin_unlock_irqrestore(&sport->port.lock, flags);
136
137 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
138 }
139}
140
141/*
142 * interrupts disabled on entry
143 */
144static void sa1100_stop_tx(struct uart_port *port)
145{
146 struct sa1100_port *sport = (struct sa1100_port *)port;
147 u32 utcr3;
148
149 utcr3 = UART_GET_UTCR3(sport);
150 UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_TIE);
151 sport->port.read_status_mask &= ~UTSR0_TO_SM(UTSR0_TFS);
152}
153
154/*
155 * port locked and interrupts disabled
156 */
157static void sa1100_start_tx(struct uart_port *port)
158{
159 struct sa1100_port *sport = (struct sa1100_port *)port;
160 u32 utcr3;
161
162 utcr3 = UART_GET_UTCR3(sport);
163 sport->port.read_status_mask |= UTSR0_TO_SM(UTSR0_TFS);
164 UART_PUT_UTCR3(sport, utcr3 | UTCR3_TIE);
165}
166
167/*
168 * Interrupts enabled
169 */
170static void sa1100_stop_rx(struct uart_port *port)
171{
172 struct sa1100_port *sport = (struct sa1100_port *)port;
173 u32 utcr3;
174
175 utcr3 = UART_GET_UTCR3(sport);
176 UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_RIE);
177}
178
179/*
180 * Set the modem control timer to fire immediately.
181 */
182static void sa1100_enable_ms(struct uart_port *port)
183{
184 struct sa1100_port *sport = (struct sa1100_port *)port;
185
186 mod_timer(&sport->timer, jiffies);
187}
188
189static void
190sa1100_rx_chars(struct sa1100_port *sport)
191{
192 struct tty_struct *tty = sport->port.state->port.tty;
193 unsigned int status, ch, flg;
194
195 status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) |
196 UTSR0_TO_SM(UART_GET_UTSR0(sport));
197 while (status & UTSR1_TO_SM(UTSR1_RNE)) {
198 ch = UART_GET_CHAR(sport);
199
200 sport->port.icount.rx++;
201
202 flg = TTY_NORMAL;
203
204 /*
205 * note that the error handling code is
206 * out of the main execution path
207 */
208 if (status & UTSR1_TO_SM(UTSR1_PRE | UTSR1_FRE | UTSR1_ROR)) {
209 if (status & UTSR1_TO_SM(UTSR1_PRE))
210 sport->port.icount.parity++;
211 else if (status & UTSR1_TO_SM(UTSR1_FRE))
212 sport->port.icount.frame++;
213 if (status & UTSR1_TO_SM(UTSR1_ROR))
214 sport->port.icount.overrun++;
215
216 status &= sport->port.read_status_mask;
217
218 if (status & UTSR1_TO_SM(UTSR1_PRE))
219 flg = TTY_PARITY;
220 else if (status & UTSR1_TO_SM(UTSR1_FRE))
221 flg = TTY_FRAME;
222
223#ifdef SUPPORT_SYSRQ
224 sport->port.sysrq = 0;
225#endif
226 }
227
228 if (uart_handle_sysrq_char(&sport->port, ch))
229 goto ignore_char;
230
231 uart_insert_char(&sport->port, status, UTSR1_TO_SM(UTSR1_ROR), ch, flg);
232
233 ignore_char:
234 status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) |
235 UTSR0_TO_SM(UART_GET_UTSR0(sport));
236 }
237 tty_flip_buffer_push(tty);
238}
239
240static void sa1100_tx_chars(struct sa1100_port *sport)
241{
242 struct circ_buf *xmit = &sport->port.state->xmit;
243
244 if (sport->port.x_char) {
245 UART_PUT_CHAR(sport, sport->port.x_char);
246 sport->port.icount.tx++;
247 sport->port.x_char = 0;
248 return;
249 }
250
251 /*
252 * Check the modem control lines before
253 * transmitting anything.
254 */
255 sa1100_mctrl_check(sport);
256
257 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
258 sa1100_stop_tx(&sport->port);
259 return;
260 }
261
262 /*
263 * Tried using FIFO (not checking TNF) for fifo fill:
264 * still had the '4 bytes repeated' problem.
265 */
266 while (UART_GET_UTSR1(sport) & UTSR1_TNF) {
267 UART_PUT_CHAR(sport, xmit->buf[xmit->tail]);
268 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
269 sport->port.icount.tx++;
270 if (uart_circ_empty(xmit))
271 break;
272 }
273
274 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
275 uart_write_wakeup(&sport->port);
276
277 if (uart_circ_empty(xmit))
278 sa1100_stop_tx(&sport->port);
279}
280
281static irqreturn_t sa1100_int(int irq, void *dev_id)
282{
283 struct sa1100_port *sport = dev_id;
284 unsigned int status, pass_counter = 0;
285
286 spin_lock(&sport->port.lock);
287 status = UART_GET_UTSR0(sport);
288 status &= SM_TO_UTSR0(sport->port.read_status_mask) | ~UTSR0_TFS;
289 do {
290 if (status & (UTSR0_RFS | UTSR0_RID)) {
291 /* Clear the receiver idle bit, if set */
292 if (status & UTSR0_RID)
293 UART_PUT_UTSR0(sport, UTSR0_RID);
294 sa1100_rx_chars(sport);
295 }
296
297 /* Clear the relevant break bits */
298 if (status & (UTSR0_RBB | UTSR0_REB))
299 UART_PUT_UTSR0(sport, status & (UTSR0_RBB | UTSR0_REB));
300
301 if (status & UTSR0_RBB)
302 sport->port.icount.brk++;
303
304 if (status & UTSR0_REB)
305 uart_handle_break(&sport->port);
306
307 if (status & UTSR0_TFS)
308 sa1100_tx_chars(sport);
309 if (pass_counter++ > SA1100_ISR_PASS_LIMIT)
310 break;
311 status = UART_GET_UTSR0(sport);
312 status &= SM_TO_UTSR0(sport->port.read_status_mask) |
313 ~UTSR0_TFS;
314 } while (status & (UTSR0_TFS | UTSR0_RFS | UTSR0_RID));
315 spin_unlock(&sport->port.lock);
316
317 return IRQ_HANDLED;
318}
319
320/*
321 * Return TIOCSER_TEMT when transmitter is not busy.
322 */
323static unsigned int sa1100_tx_empty(struct uart_port *port)
324{
325 struct sa1100_port *sport = (struct sa1100_port *)port;
326
327 return UART_GET_UTSR1(sport) & UTSR1_TBY ? 0 : TIOCSER_TEMT;
328}
329
330static unsigned int sa1100_get_mctrl(struct uart_port *port)
331{
332 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
333}
334
335static void sa1100_set_mctrl(struct uart_port *port, unsigned int mctrl)
336{
337}
338
339/*
340 * Interrupts always disabled.
341 */
342static void sa1100_break_ctl(struct uart_port *port, int break_state)
343{
344 struct sa1100_port *sport = (struct sa1100_port *)port;
345 unsigned long flags;
346 unsigned int utcr3;
347
348 spin_lock_irqsave(&sport->port.lock, flags);
349 utcr3 = UART_GET_UTCR3(sport);
350 if (break_state == -1)
351 utcr3 |= UTCR3_BRK;
352 else
353 utcr3 &= ~UTCR3_BRK;
354 UART_PUT_UTCR3(sport, utcr3);
355 spin_unlock_irqrestore(&sport->port.lock, flags);
356}
357
358static int sa1100_startup(struct uart_port *port)
359{
360 struct sa1100_port *sport = (struct sa1100_port *)port;
361 int retval;
362
363 /*
364 * Allocate the IRQ
365 */
366 retval = request_irq(sport->port.irq, sa1100_int, 0,
367 "sa11x0-uart", sport);
368 if (retval)
369 return retval;
370
371 /*
372 * Finally, clear and enable interrupts
373 */
374 UART_PUT_UTSR0(sport, -1);
375 UART_PUT_UTCR3(sport, UTCR3_RXE | UTCR3_TXE | UTCR3_RIE);
376
377 /*
378 * Enable modem status interrupts
379 */
380 spin_lock_irq(&sport->port.lock);
381 sa1100_enable_ms(&sport->port);
382 spin_unlock_irq(&sport->port.lock);
383
384 return 0;
385}
386
387static void sa1100_shutdown(struct uart_port *port)
388{
389 struct sa1100_port *sport = (struct sa1100_port *)port;
390
391 /*
392 * Stop our timer.
393 */
394 del_timer_sync(&sport->timer);
395
396 /*
397 * Free the interrupt
398 */
399 free_irq(sport->port.irq, sport);
400
401 /*
402 * Disable all interrupts, port and break condition.
403 */
404 UART_PUT_UTCR3(sport, 0);
405}
406
407static void
408sa1100_set_termios(struct uart_port *port, struct ktermios *termios,
409 struct ktermios *old)
410{
411 struct sa1100_port *sport = (struct sa1100_port *)port;
412 unsigned long flags;
413 unsigned int utcr0, old_utcr3, baud, quot;
414 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
415
416 /*
417 * We only support CS7 and CS8.
418 */
419 while ((termios->c_cflag & CSIZE) != CS7 &&
420 (termios->c_cflag & CSIZE) != CS8) {
421 termios->c_cflag &= ~CSIZE;
422 termios->c_cflag |= old_csize;
423 old_csize = CS8;
424 }
425
426 if ((termios->c_cflag & CSIZE) == CS8)
427 utcr0 = UTCR0_DSS;
428 else
429 utcr0 = 0;
430
431 if (termios->c_cflag & CSTOPB)
432 utcr0 |= UTCR0_SBS;
433 if (termios->c_cflag & PARENB) {
434 utcr0 |= UTCR0_PE;
435 if (!(termios->c_cflag & PARODD))
436 utcr0 |= UTCR0_OES;
437 }
438
439 /*
440 * Ask the core to calculate the divisor for us.
441 */
442 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
443 quot = uart_get_divisor(port, baud);
444
445 spin_lock_irqsave(&sport->port.lock, flags);
446
447 sport->port.read_status_mask &= UTSR0_TO_SM(UTSR0_TFS);
448 sport->port.read_status_mask |= UTSR1_TO_SM(UTSR1_ROR);
449 if (termios->c_iflag & INPCK)
450 sport->port.read_status_mask |=
451 UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE);
452 if (termios->c_iflag & (BRKINT | PARMRK))
453 sport->port.read_status_mask |=
454 UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB);
455
456 /*
457 * Characters to ignore
458 */
459 sport->port.ignore_status_mask = 0;
460 if (termios->c_iflag & IGNPAR)
461 sport->port.ignore_status_mask |=
462 UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE);
463 if (termios->c_iflag & IGNBRK) {
464 sport->port.ignore_status_mask |=
465 UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB);
466 /*
467 * If we're ignoring parity and break indicators,
468 * ignore overruns too (for real raw support).
469 */
470 if (termios->c_iflag & IGNPAR)
471 sport->port.ignore_status_mask |=
472 UTSR1_TO_SM(UTSR1_ROR);
473 }
474
475 del_timer_sync(&sport->timer);
476
477 /*
478 * Update the per-port timeout.
479 */
480 uart_update_timeout(port, termios->c_cflag, baud);
481
482 /*
483 * disable interrupts and drain transmitter
484 */
485 old_utcr3 = UART_GET_UTCR3(sport);
486 UART_PUT_UTCR3(sport, old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE));
487
488 while (UART_GET_UTSR1(sport) & UTSR1_TBY)
489 barrier();
490
491 /* then, disable everything */
492 UART_PUT_UTCR3(sport, 0);
493
494 /* set the parity, stop bits and data size */
495 UART_PUT_UTCR0(sport, utcr0);
496
497 /* set the baud rate */
498 quot -= 1;
499 UART_PUT_UTCR1(sport, ((quot & 0xf00) >> 8));
500 UART_PUT_UTCR2(sport, (quot & 0xff));
501
502 UART_PUT_UTSR0(sport, -1);
503
504 UART_PUT_UTCR3(sport, old_utcr3);
505
506 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
507 sa1100_enable_ms(&sport->port);
508
509 spin_unlock_irqrestore(&sport->port.lock, flags);
510}
511
512static const char *sa1100_type(struct uart_port *port)
513{
514 struct sa1100_port *sport = (struct sa1100_port *)port;
515
516 return sport->port.type == PORT_SA1100 ? "SA1100" : NULL;
517}
518
519/*
520 * Release the memory region(s) being used by 'port'.
521 */
522static void sa1100_release_port(struct uart_port *port)
523{
524 struct sa1100_port *sport = (struct sa1100_port *)port;
525
526 release_mem_region(sport->port.mapbase, UART_PORT_SIZE);
527}
528
529/*
530 * Request the memory region(s) being used by 'port'.
531 */
532static int sa1100_request_port(struct uart_port *port)
533{
534 struct sa1100_port *sport = (struct sa1100_port *)port;
535
536 return request_mem_region(sport->port.mapbase, UART_PORT_SIZE,
537 "sa11x0-uart") != NULL ? 0 : -EBUSY;
538}
539
540/*
541 * Configure/autoconfigure the port.
542 */
543static void sa1100_config_port(struct uart_port *port, int flags)
544{
545 struct sa1100_port *sport = (struct sa1100_port *)port;
546
547 if (flags & UART_CONFIG_TYPE &&
548 sa1100_request_port(&sport->port) == 0)
549 sport->port.type = PORT_SA1100;
550}
551
552/*
553 * Verify the new serial_struct (for TIOCSSERIAL).
554 * The only change we allow are to the flags and type, and
555 * even then only between PORT_SA1100 and PORT_UNKNOWN
556 */
557static int
558sa1100_verify_port(struct uart_port *port, struct serial_struct *ser)
559{
560 struct sa1100_port *sport = (struct sa1100_port *)port;
561 int ret = 0;
562
563 if (ser->type != PORT_UNKNOWN && ser->type != PORT_SA1100)
564 ret = -EINVAL;
565 if (sport->port.irq != ser->irq)
566 ret = -EINVAL;
567 if (ser->io_type != SERIAL_IO_MEM)
568 ret = -EINVAL;
569 if (sport->port.uartclk / 16 != ser->baud_base)
570 ret = -EINVAL;
571 if ((void *)sport->port.mapbase != ser->iomem_base)
572 ret = -EINVAL;
573 if (sport->port.iobase != ser->port)
574 ret = -EINVAL;
575 if (ser->hub6 != 0)
576 ret = -EINVAL;
577 return ret;
578}
579
580static struct uart_ops sa1100_pops = {
581 .tx_empty = sa1100_tx_empty,
582 .set_mctrl = sa1100_set_mctrl,
583 .get_mctrl = sa1100_get_mctrl,
584 .stop_tx = sa1100_stop_tx,
585 .start_tx = sa1100_start_tx,
586 .stop_rx = sa1100_stop_rx,
587 .enable_ms = sa1100_enable_ms,
588 .break_ctl = sa1100_break_ctl,
589 .startup = sa1100_startup,
590 .shutdown = sa1100_shutdown,
591 .set_termios = sa1100_set_termios,
592 .type = sa1100_type,
593 .release_port = sa1100_release_port,
594 .request_port = sa1100_request_port,
595 .config_port = sa1100_config_port,
596 .verify_port = sa1100_verify_port,
597};
598
599static struct sa1100_port sa1100_ports[NR_PORTS];
600
601/*
602 * Setup the SA1100 serial ports. Note that we don't include the IrDA
603 * port here since we have our own SIR/FIR driver (see drivers/net/irda)
604 *
605 * Note also that we support "console=ttySAx" where "x" is either 0 or 1.
606 * Which serial port this ends up being depends on the machine you're
607 * running this kernel on. I'm not convinced that this is a good idea,
608 * but that's the way it traditionally works.
609 *
610 * Note that NanoEngine UART3 becomes UART2, and UART2 is no longer
611 * used here.
612 */
613static void __init sa1100_init_ports(void)
614{
615 static int first = 1;
616 int i;
617
618 if (!first)
619 return;
620 first = 0;
621
622 for (i = 0; i < NR_PORTS; i++) {
623 sa1100_ports[i].port.uartclk = 3686400;
624 sa1100_ports[i].port.ops = &sa1100_pops;
625 sa1100_ports[i].port.fifosize = 8;
626 sa1100_ports[i].port.line = i;
627 sa1100_ports[i].port.iotype = UPIO_MEM;
628 init_timer(&sa1100_ports[i].timer);
629 sa1100_ports[i].timer.function = sa1100_timeout;
630 sa1100_ports[i].timer.data = (unsigned long)&sa1100_ports[i];
631 }
632
633 /*
634 * make transmit lines outputs, so that when the port
635 * is closed, the output is in the MARK state.
636 */
637 PPDR |= PPC_TXD1 | PPC_TXD3;
638 PPSR |= PPC_TXD1 | PPC_TXD3;
639}
640
641void __devinit sa1100_register_uart_fns(struct sa1100_port_fns *fns)
642{
643 if (fns->get_mctrl)
644 sa1100_pops.get_mctrl = fns->get_mctrl;
645 if (fns->set_mctrl)
646 sa1100_pops.set_mctrl = fns->set_mctrl;
647
648 sa1100_pops.pm = fns->pm;
649 sa1100_pops.set_wake = fns->set_wake;
650}
651
652void __init sa1100_register_uart(int idx, int port)
653{
654 if (idx >= NR_PORTS) {
655 printk(KERN_ERR "%s: bad index number %d\n", __func__, idx);
656 return;
657 }
658
659 switch (port) {
660 case 1:
661 sa1100_ports[idx].port.membase = (void __iomem *)&Ser1UTCR0;
662 sa1100_ports[idx].port.mapbase = _Ser1UTCR0;
663 sa1100_ports[idx].port.irq = IRQ_Ser1UART;
664 sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF;
665 break;
666
667 case 2:
668 sa1100_ports[idx].port.membase = (void __iomem *)&Ser2UTCR0;
669 sa1100_ports[idx].port.mapbase = _Ser2UTCR0;
670 sa1100_ports[idx].port.irq = IRQ_Ser2ICP;
671 sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF;
672 break;
673
674 case 3:
675 sa1100_ports[idx].port.membase = (void __iomem *)&Ser3UTCR0;
676 sa1100_ports[idx].port.mapbase = _Ser3UTCR0;
677 sa1100_ports[idx].port.irq = IRQ_Ser3UART;
678 sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF;
679 break;
680
681 default:
682 printk(KERN_ERR "%s: bad port number %d\n", __func__, port);
683 }
684}
685
686
687#ifdef CONFIG_SERIAL_SA1100_CONSOLE
688static void sa1100_console_putchar(struct uart_port *port, int ch)
689{
690 struct sa1100_port *sport = (struct sa1100_port *)port;
691
692 while (!(UART_GET_UTSR1(sport) & UTSR1_TNF))
693 barrier();
694 UART_PUT_CHAR(sport, ch);
695}
696
697/*
698 * Interrupts are disabled on entering
699 */
700static void
701sa1100_console_write(struct console *co, const char *s, unsigned int count)
702{
703 struct sa1100_port *sport = &sa1100_ports[co->index];
704 unsigned int old_utcr3, status;
705
706 /*
707 * First, save UTCR3 and then disable interrupts
708 */
709 old_utcr3 = UART_GET_UTCR3(sport);
710 UART_PUT_UTCR3(sport, (old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE)) |
711 UTCR3_TXE);
712
713 uart_console_write(&sport->port, s, count, sa1100_console_putchar);
714
715 /*
716 * Finally, wait for transmitter to become empty
717 * and restore UTCR3
718 */
719 do {
720 status = UART_GET_UTSR1(sport);
721 } while (status & UTSR1_TBY);
722 UART_PUT_UTCR3(sport, old_utcr3);
723}
724
725/*
726 * If the port was already initialised (eg, by a boot loader),
727 * try to determine the current setup.
728 */
729static void __init
730sa1100_console_get_options(struct sa1100_port *sport, int *baud,
731 int *parity, int *bits)
732{
733 unsigned int utcr3;
734
735 utcr3 = UART_GET_UTCR3(sport) & (UTCR3_RXE | UTCR3_TXE);
736 if (utcr3 == (UTCR3_RXE | UTCR3_TXE)) {
737 /* ok, the port was enabled */
738 unsigned int utcr0, quot;
739
740 utcr0 = UART_GET_UTCR0(sport);
741
742 *parity = 'n';
743 if (utcr0 & UTCR0_PE) {
744 if (utcr0 & UTCR0_OES)
745 *parity = 'e';
746 else
747 *parity = 'o';
748 }
749
750 if (utcr0 & UTCR0_DSS)
751 *bits = 8;
752 else
753 *bits = 7;
754
755 quot = UART_GET_UTCR2(sport) | UART_GET_UTCR1(sport) << 8;
756 quot &= 0xfff;
757 *baud = sport->port.uartclk / (16 * (quot + 1));
758 }
759}
760
761static int __init
762sa1100_console_setup(struct console *co, char *options)
763{
764 struct sa1100_port *sport;
765 int baud = 9600;
766 int bits = 8;
767 int parity = 'n';
768 int flow = 'n';
769
770 /*
771 * Check whether an invalid uart number has been specified, and
772 * if so, search for the first available port that does have
773 * console support.
774 */
775 if (co->index == -1 || co->index >= NR_PORTS)
776 co->index = 0;
777 sport = &sa1100_ports[co->index];
778
779 if (options)
780 uart_parse_options(options, &baud, &parity, &bits, &flow);
781 else
782 sa1100_console_get_options(sport, &baud, &parity, &bits);
783
784 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
785}
786
787static struct uart_driver sa1100_reg;
788static struct console sa1100_console = {
789 .name = "ttySA",
790 .write = sa1100_console_write,
791 .device = uart_console_device,
792 .setup = sa1100_console_setup,
793 .flags = CON_PRINTBUFFER,
794 .index = -1,
795 .data = &sa1100_reg,
796};
797
798static int __init sa1100_rs_console_init(void)
799{
800 sa1100_init_ports();
801 register_console(&sa1100_console);
802 return 0;
803}
804console_initcall(sa1100_rs_console_init);
805
806#define SA1100_CONSOLE &sa1100_console
807#else
808#define SA1100_CONSOLE NULL
809#endif
810
811static struct uart_driver sa1100_reg = {
812 .owner = THIS_MODULE,
813 .driver_name = "ttySA",
814 .dev_name = "ttySA",
815 .major = SERIAL_SA1100_MAJOR,
816 .minor = MINOR_START,
817 .nr = NR_PORTS,
818 .cons = SA1100_CONSOLE,
819};
820
821static int sa1100_serial_suspend(struct platform_device *dev, pm_message_t state)
822{
823 struct sa1100_port *sport = platform_get_drvdata(dev);
824
825 if (sport)
826 uart_suspend_port(&sa1100_reg, &sport->port);
827
828 return 0;
829}
830
831static int sa1100_serial_resume(struct platform_device *dev)
832{
833 struct sa1100_port *sport = platform_get_drvdata(dev);
834
835 if (sport)
836 uart_resume_port(&sa1100_reg, &sport->port);
837
838 return 0;
839}
840
841static int sa1100_serial_probe(struct platform_device *dev)
842{
843 struct resource *res = dev->resource;
844 int i;
845
846 for (i = 0; i < dev->num_resources; i++, res++)
847 if (res->flags & IORESOURCE_MEM)
848 break;
849
850 if (i < dev->num_resources) {
851 for (i = 0; i < NR_PORTS; i++) {
852 if (sa1100_ports[i].port.mapbase != res->start)
853 continue;
854
855 sa1100_ports[i].port.dev = &dev->dev;
856 uart_add_one_port(&sa1100_reg, &sa1100_ports[i].port);
857 platform_set_drvdata(dev, &sa1100_ports[i]);
858 break;
859 }
860 }
861
862 return 0;
863}
864
865static int sa1100_serial_remove(struct platform_device *pdev)
866{
867 struct sa1100_port *sport = platform_get_drvdata(pdev);
868
869 platform_set_drvdata(pdev, NULL);
870
871 if (sport)
872 uart_remove_one_port(&sa1100_reg, &sport->port);
873
874 return 0;
875}
876
877static struct platform_driver sa11x0_serial_driver = {
878 .probe = sa1100_serial_probe,
879 .remove = sa1100_serial_remove,
880 .suspend = sa1100_serial_suspend,
881 .resume = sa1100_serial_resume,
882 .driver = {
883 .name = "sa11x0-uart",
884 .owner = THIS_MODULE,
885 },
886};
887
888static int __init sa1100_serial_init(void)
889{
890 int ret;
891
892 printk(KERN_INFO "Serial: SA11x0 driver\n");
893
894 sa1100_init_ports();
895
896 ret = uart_register_driver(&sa1100_reg);
897 if (ret == 0) {
898 ret = platform_driver_register(&sa11x0_serial_driver);
899 if (ret)
900 uart_unregister_driver(&sa1100_reg);
901 }
902 return ret;
903}
904
905static void __exit sa1100_serial_exit(void)
906{
907 platform_driver_unregister(&sa11x0_serial_driver);
908 uart_unregister_driver(&sa1100_reg);
909}
910
911module_init(sa1100_serial_init);
912module_exit(sa1100_serial_exit);
913
914MODULE_AUTHOR("Deep Blue Solutions Ltd");
915MODULE_DESCRIPTION("SA1100 generic serial port driver");
916MODULE_LICENSE("GPL");
917MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_SA1100_MAJOR);
918MODULE_ALIAS("platform:sa11x0-uart");
diff --git a/drivers/serial/samsung.c b/drivers/serial/samsung.c
deleted file mode 100644
index b1156ba8ad14..000000000000
--- a/drivers/serial/samsung.c
+++ /dev/null
@@ -1,1487 +0,0 @@
1/* linux/drivers/serial/samsuing.c
2 *
3 * Driver core for Samsung SoC onboard UARTs.
4 *
5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
6 * http://armlinux.simtec.co.uk/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* Hote on 2410 error handling
14 *
15 * The s3c2410 manual has a love/hate affair with the contents of the
16 * UERSTAT register in the UART blocks, and keeps marking some of the
17 * error bits as reserved. Having checked with the s3c2410x01,
18 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
19 * feature from the latter versions of the manual.
20 *
21 * If it becomes aparrent that latter versions of the 2410 remove these
22 * bits, then action will have to be taken to differentiate the versions
23 * and change the policy on BREAK
24 *
25 * BJD, 04-Nov-2004
26*/
27
28#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
29#define SUPPORT_SYSRQ
30#endif
31
32#include <linux/module.h>
33#include <linux/ioport.h>
34#include <linux/io.h>
35#include <linux/platform_device.h>
36#include <linux/init.h>
37#include <linux/sysrq.h>
38#include <linux/console.h>
39#include <linux/tty.h>
40#include <linux/tty_flip.h>
41#include <linux/serial_core.h>
42#include <linux/serial.h>
43#include <linux/delay.h>
44#include <linux/clk.h>
45#include <linux/cpufreq.h>
46
47#include <asm/irq.h>
48
49#include <mach/hardware.h>
50#include <mach/map.h>
51
52#include <plat/regs-serial.h>
53
54#include "samsung.h"
55
56/* UART name and device definitions */
57
58#define S3C24XX_SERIAL_NAME "ttySAC"
59#define S3C24XX_SERIAL_MAJOR 204
60#define S3C24XX_SERIAL_MINOR 64
61
62/* macros to change one thing to another */
63
64#define tx_enabled(port) ((port)->unused[0])
65#define rx_enabled(port) ((port)->unused[1])
66
67/* flag to ignore all characters comming in */
68#define RXSTAT_DUMMY_READ (0x10000000)
69
70static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
71{
72 return container_of(port, struct s3c24xx_uart_port, port);
73}
74
75/* translate a port to the device name */
76
77static inline const char *s3c24xx_serial_portname(struct uart_port *port)
78{
79 return to_platform_device(port->dev)->name;
80}
81
82static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
83{
84 return (rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE);
85}
86
87static void s3c24xx_serial_rx_enable(struct uart_port *port)
88{
89 unsigned long flags;
90 unsigned int ucon, ufcon;
91 int count = 10000;
92
93 spin_lock_irqsave(&port->lock, flags);
94
95 while (--count && !s3c24xx_serial_txempty_nofifo(port))
96 udelay(100);
97
98 ufcon = rd_regl(port, S3C2410_UFCON);
99 ufcon |= S3C2410_UFCON_RESETRX;
100 wr_regl(port, S3C2410_UFCON, ufcon);
101
102 ucon = rd_regl(port, S3C2410_UCON);
103 ucon |= S3C2410_UCON_RXIRQMODE;
104 wr_regl(port, S3C2410_UCON, ucon);
105
106 rx_enabled(port) = 1;
107 spin_unlock_irqrestore(&port->lock, flags);
108}
109
110static void s3c24xx_serial_rx_disable(struct uart_port *port)
111{
112 unsigned long flags;
113 unsigned int ucon;
114
115 spin_lock_irqsave(&port->lock, flags);
116
117 ucon = rd_regl(port, S3C2410_UCON);
118 ucon &= ~S3C2410_UCON_RXIRQMODE;
119 wr_regl(port, S3C2410_UCON, ucon);
120
121 rx_enabled(port) = 0;
122 spin_unlock_irqrestore(&port->lock, flags);
123}
124
125static void s3c24xx_serial_stop_tx(struct uart_port *port)
126{
127 struct s3c24xx_uart_port *ourport = to_ourport(port);
128
129 if (tx_enabled(port)) {
130 disable_irq_nosync(ourport->tx_irq);
131 tx_enabled(port) = 0;
132 if (port->flags & UPF_CONS_FLOW)
133 s3c24xx_serial_rx_enable(port);
134 }
135}
136
137static void s3c24xx_serial_start_tx(struct uart_port *port)
138{
139 struct s3c24xx_uart_port *ourport = to_ourport(port);
140
141 if (!tx_enabled(port)) {
142 if (port->flags & UPF_CONS_FLOW)
143 s3c24xx_serial_rx_disable(port);
144
145 enable_irq(ourport->tx_irq);
146 tx_enabled(port) = 1;
147 }
148}
149
150
151static void s3c24xx_serial_stop_rx(struct uart_port *port)
152{
153 struct s3c24xx_uart_port *ourport = to_ourport(port);
154
155 if (rx_enabled(port)) {
156 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
157 disable_irq_nosync(ourport->rx_irq);
158 rx_enabled(port) = 0;
159 }
160}
161
162static void s3c24xx_serial_enable_ms(struct uart_port *port)
163{
164}
165
166static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
167{
168 return to_ourport(port)->info;
169}
170
171static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
172{
173 if (port->dev == NULL)
174 return NULL;
175
176 return (struct s3c2410_uartcfg *)port->dev->platform_data;
177}
178
179static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
180 unsigned long ufstat)
181{
182 struct s3c24xx_uart_info *info = ourport->info;
183
184 if (ufstat & info->rx_fifofull)
185 return info->fifosize;
186
187 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
188}
189
190
191/* ? - where has parity gone?? */
192#define S3C2410_UERSTAT_PARITY (0x1000)
193
194static irqreturn_t
195s3c24xx_serial_rx_chars(int irq, void *dev_id)
196{
197 struct s3c24xx_uart_port *ourport = dev_id;
198 struct uart_port *port = &ourport->port;
199 struct tty_struct *tty = port->state->port.tty;
200 unsigned int ufcon, ch, flag, ufstat, uerstat;
201 int max_count = 64;
202
203 while (max_count-- > 0) {
204 ufcon = rd_regl(port, S3C2410_UFCON);
205 ufstat = rd_regl(port, S3C2410_UFSTAT);
206
207 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
208 break;
209
210 uerstat = rd_regl(port, S3C2410_UERSTAT);
211 ch = rd_regb(port, S3C2410_URXH);
212
213 if (port->flags & UPF_CONS_FLOW) {
214 int txe = s3c24xx_serial_txempty_nofifo(port);
215
216 if (rx_enabled(port)) {
217 if (!txe) {
218 rx_enabled(port) = 0;
219 continue;
220 }
221 } else {
222 if (txe) {
223 ufcon |= S3C2410_UFCON_RESETRX;
224 wr_regl(port, S3C2410_UFCON, ufcon);
225 rx_enabled(port) = 1;
226 goto out;
227 }
228 continue;
229 }
230 }
231
232 /* insert the character into the buffer */
233
234 flag = TTY_NORMAL;
235 port->icount.rx++;
236
237 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
238 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
239 ch, uerstat);
240
241 /* check for break */
242 if (uerstat & S3C2410_UERSTAT_BREAK) {
243 dbg("break!\n");
244 port->icount.brk++;
245 if (uart_handle_break(port))
246 goto ignore_char;
247 }
248
249 if (uerstat & S3C2410_UERSTAT_FRAME)
250 port->icount.frame++;
251 if (uerstat & S3C2410_UERSTAT_OVERRUN)
252 port->icount.overrun++;
253
254 uerstat &= port->read_status_mask;
255
256 if (uerstat & S3C2410_UERSTAT_BREAK)
257 flag = TTY_BREAK;
258 else if (uerstat & S3C2410_UERSTAT_PARITY)
259 flag = TTY_PARITY;
260 else if (uerstat & (S3C2410_UERSTAT_FRAME |
261 S3C2410_UERSTAT_OVERRUN))
262 flag = TTY_FRAME;
263 }
264
265 if (uart_handle_sysrq_char(port, ch))
266 goto ignore_char;
267
268 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
269 ch, flag);
270
271 ignore_char:
272 continue;
273 }
274 tty_flip_buffer_push(tty);
275
276 out:
277 return IRQ_HANDLED;
278}
279
280static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
281{
282 struct s3c24xx_uart_port *ourport = id;
283 struct uart_port *port = &ourport->port;
284 struct circ_buf *xmit = &port->state->xmit;
285 int count = 256;
286
287 if (port->x_char) {
288 wr_regb(port, S3C2410_UTXH, port->x_char);
289 port->icount.tx++;
290 port->x_char = 0;
291 goto out;
292 }
293
294 /* if there isnt anything more to transmit, or the uart is now
295 * stopped, disable the uart and exit
296 */
297
298 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
299 s3c24xx_serial_stop_tx(port);
300 goto out;
301 }
302
303 /* try and drain the buffer... */
304
305 while (!uart_circ_empty(xmit) && count-- > 0) {
306 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
307 break;
308
309 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
310 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
311 port->icount.tx++;
312 }
313
314 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
315 uart_write_wakeup(port);
316
317 if (uart_circ_empty(xmit))
318 s3c24xx_serial_stop_tx(port);
319
320 out:
321 return IRQ_HANDLED;
322}
323
324static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
325{
326 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
327 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
328 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
329
330 if (ufcon & S3C2410_UFCON_FIFOMODE) {
331 if ((ufstat & info->tx_fifomask) != 0 ||
332 (ufstat & info->tx_fifofull))
333 return 0;
334
335 return 1;
336 }
337
338 return s3c24xx_serial_txempty_nofifo(port);
339}
340
341/* no modem control lines */
342static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
343{
344 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
345
346 if (umstat & S3C2410_UMSTAT_CTS)
347 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
348 else
349 return TIOCM_CAR | TIOCM_DSR;
350}
351
352static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
353{
354 /* todo - possibly remove AFC and do manual CTS */
355}
356
357static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
358{
359 unsigned long flags;
360 unsigned int ucon;
361
362 spin_lock_irqsave(&port->lock, flags);
363
364 ucon = rd_regl(port, S3C2410_UCON);
365
366 if (break_state)
367 ucon |= S3C2410_UCON_SBREAK;
368 else
369 ucon &= ~S3C2410_UCON_SBREAK;
370
371 wr_regl(port, S3C2410_UCON, ucon);
372
373 spin_unlock_irqrestore(&port->lock, flags);
374}
375
376static void s3c24xx_serial_shutdown(struct uart_port *port)
377{
378 struct s3c24xx_uart_port *ourport = to_ourport(port);
379
380 if (ourport->tx_claimed) {
381 free_irq(ourport->tx_irq, ourport);
382 tx_enabled(port) = 0;
383 ourport->tx_claimed = 0;
384 }
385
386 if (ourport->rx_claimed) {
387 free_irq(ourport->rx_irq, ourport);
388 ourport->rx_claimed = 0;
389 rx_enabled(port) = 0;
390 }
391}
392
393
394static int s3c24xx_serial_startup(struct uart_port *port)
395{
396 struct s3c24xx_uart_port *ourport = to_ourport(port);
397 int ret;
398
399 dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
400 port->mapbase, port->membase);
401
402 rx_enabled(port) = 1;
403
404 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
405 s3c24xx_serial_portname(port), ourport);
406
407 if (ret != 0) {
408 printk(KERN_ERR "cannot get irq %d\n", ourport->rx_irq);
409 return ret;
410 }
411
412 ourport->rx_claimed = 1;
413
414 dbg("requesting tx irq...\n");
415
416 tx_enabled(port) = 1;
417
418 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
419 s3c24xx_serial_portname(port), ourport);
420
421 if (ret) {
422 printk(KERN_ERR "cannot get irq %d\n", ourport->tx_irq);
423 goto err;
424 }
425
426 ourport->tx_claimed = 1;
427
428 dbg("s3c24xx_serial_startup ok\n");
429
430 /* the port reset code should have done the correct
431 * register setup for the port controls */
432
433 return ret;
434
435 err:
436 s3c24xx_serial_shutdown(port);
437 return ret;
438}
439
440/* power power management control */
441
442static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
443 unsigned int old)
444{
445 struct s3c24xx_uart_port *ourport = to_ourport(port);
446
447 ourport->pm_level = level;
448
449 switch (level) {
450 case 3:
451 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
452 clk_disable(ourport->baudclk);
453
454 clk_disable(ourport->clk);
455 break;
456
457 case 0:
458 clk_enable(ourport->clk);
459
460 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
461 clk_enable(ourport->baudclk);
462
463 break;
464 default:
465 printk(KERN_ERR "s3c24xx_serial: unknown pm %d\n", level);
466 }
467}
468
469/* baud rate calculation
470 *
471 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
472 * of different sources, including the peripheral clock ("pclk") and an
473 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
474 * with a programmable extra divisor.
475 *
476 * The following code goes through the clock sources, and calculates the
477 * baud clocks (and the resultant actual baud rates) and then tries to
478 * pick the closest one and select that.
479 *
480*/
481
482
483#define MAX_CLKS (8)
484
485static struct s3c24xx_uart_clksrc tmp_clksrc = {
486 .name = "pclk",
487 .min_baud = 0,
488 .max_baud = 0,
489 .divisor = 1,
490};
491
492static inline int
493s3c24xx_serial_getsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
494{
495 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
496
497 return (info->get_clksrc)(port, c);
498}
499
500static inline int
501s3c24xx_serial_setsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
502{
503 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
504
505 return (info->set_clksrc)(port, c);
506}
507
508struct baud_calc {
509 struct s3c24xx_uart_clksrc *clksrc;
510 unsigned int calc;
511 unsigned int divslot;
512 unsigned int quot;
513 struct clk *src;
514};
515
516static int s3c24xx_serial_calcbaud(struct baud_calc *calc,
517 struct uart_port *port,
518 struct s3c24xx_uart_clksrc *clksrc,
519 unsigned int baud)
520{
521 struct s3c24xx_uart_port *ourport = to_ourport(port);
522 unsigned long rate;
523
524 calc->src = clk_get(port->dev, clksrc->name);
525 if (calc->src == NULL || IS_ERR(calc->src))
526 return 0;
527
528 rate = clk_get_rate(calc->src);
529 rate /= clksrc->divisor;
530
531 calc->clksrc = clksrc;
532
533 if (ourport->info->has_divslot) {
534 unsigned long div = rate / baud;
535
536 /* The UDIVSLOT register on the newer UARTs allows us to
537 * get a divisor adjustment of 1/16th on the baud clock.
538 *
539 * We don't keep the UDIVSLOT value (the 16ths we calculated
540 * by not multiplying the baud by 16) as it is easy enough
541 * to recalculate.
542 */
543
544 calc->quot = div / 16;
545 calc->calc = rate / div;
546 } else {
547 calc->quot = (rate + (8 * baud)) / (16 * baud);
548 calc->calc = (rate / (calc->quot * 16));
549 }
550
551 calc->quot--;
552 return 1;
553}
554
555static unsigned int s3c24xx_serial_getclk(struct uart_port *port,
556 struct s3c24xx_uart_clksrc **clksrc,
557 struct clk **clk,
558 unsigned int baud)
559{
560 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
561 struct s3c24xx_uart_clksrc *clkp;
562 struct baud_calc res[MAX_CLKS];
563 struct baud_calc *resptr, *best, *sptr;
564 int i;
565
566 clkp = cfg->clocks;
567 best = NULL;
568
569 if (cfg->clocks_size < 2) {
570 if (cfg->clocks_size == 0)
571 clkp = &tmp_clksrc;
572
573 /* check to see if we're sourcing fclk, and if so we're
574 * going to have to update the clock source
575 */
576
577 if (strcmp(clkp->name, "fclk") == 0) {
578 struct s3c24xx_uart_clksrc src;
579
580 s3c24xx_serial_getsource(port, &src);
581
582 /* check that the port already using fclk, and if
583 * not, then re-select fclk
584 */
585
586 if (strcmp(src.name, clkp->name) == 0) {
587 s3c24xx_serial_setsource(port, clkp);
588 s3c24xx_serial_getsource(port, &src);
589 }
590
591 clkp->divisor = src.divisor;
592 }
593
594 s3c24xx_serial_calcbaud(res, port, clkp, baud);
595 best = res;
596 resptr = best + 1;
597 } else {
598 resptr = res;
599
600 for (i = 0; i < cfg->clocks_size; i++, clkp++) {
601 if (s3c24xx_serial_calcbaud(resptr, port, clkp, baud))
602 resptr++;
603 }
604 }
605
606 /* ok, we now need to select the best clock we found */
607
608 if (!best) {
609 unsigned int deviation = (1<<30)|((1<<30)-1);
610 int calc_deviation;
611
612 for (sptr = res; sptr < resptr; sptr++) {
613 calc_deviation = baud - sptr->calc;
614 if (calc_deviation < 0)
615 calc_deviation = -calc_deviation;
616
617 if (calc_deviation < deviation) {
618 best = sptr;
619 deviation = calc_deviation;
620 }
621 }
622 }
623
624 /* store results to pass back */
625
626 *clksrc = best->clksrc;
627 *clk = best->src;
628
629 return best->quot;
630}
631
632/* udivslot_table[]
633 *
634 * This table takes the fractional value of the baud divisor and gives
635 * the recommended setting for the UDIVSLOT register.
636 */
637static u16 udivslot_table[16] = {
638 [0] = 0x0000,
639 [1] = 0x0080,
640 [2] = 0x0808,
641 [3] = 0x0888,
642 [4] = 0x2222,
643 [5] = 0x4924,
644 [6] = 0x4A52,
645 [7] = 0x54AA,
646 [8] = 0x5555,
647 [9] = 0xD555,
648 [10] = 0xD5D5,
649 [11] = 0xDDD5,
650 [12] = 0xDDDD,
651 [13] = 0xDFDD,
652 [14] = 0xDFDF,
653 [15] = 0xFFDF,
654};
655
656static void s3c24xx_serial_set_termios(struct uart_port *port,
657 struct ktermios *termios,
658 struct ktermios *old)
659{
660 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
661 struct s3c24xx_uart_port *ourport = to_ourport(port);
662 struct s3c24xx_uart_clksrc *clksrc = NULL;
663 struct clk *clk = NULL;
664 unsigned long flags;
665 unsigned int baud, quot;
666 unsigned int ulcon;
667 unsigned int umcon;
668 unsigned int udivslot = 0;
669
670 /*
671 * We don't support modem control lines.
672 */
673 termios->c_cflag &= ~(HUPCL | CMSPAR);
674 termios->c_cflag |= CLOCAL;
675
676 /*
677 * Ask the core to calculate the divisor for us.
678 */
679
680 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
681
682 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
683 quot = port->custom_divisor;
684 else
685 quot = s3c24xx_serial_getclk(port, &clksrc, &clk, baud);
686
687 /* check to see if we need to change clock source */
688
689 if (ourport->clksrc != clksrc || ourport->baudclk != clk) {
690 dbg("selecting clock %p\n", clk);
691 s3c24xx_serial_setsource(port, clksrc);
692
693 if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) {
694 clk_disable(ourport->baudclk);
695 ourport->baudclk = NULL;
696 }
697
698 clk_enable(clk);
699
700 ourport->clksrc = clksrc;
701 ourport->baudclk = clk;
702 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
703 }
704
705 if (ourport->info->has_divslot) {
706 unsigned int div = ourport->baudclk_rate / baud;
707
708 if (cfg->has_fracval) {
709 udivslot = (div & 15);
710 dbg("fracval = %04x\n", udivslot);
711 } else {
712 udivslot = udivslot_table[div & 15];
713 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
714 }
715 }
716
717 switch (termios->c_cflag & CSIZE) {
718 case CS5:
719 dbg("config: 5bits/char\n");
720 ulcon = S3C2410_LCON_CS5;
721 break;
722 case CS6:
723 dbg("config: 6bits/char\n");
724 ulcon = S3C2410_LCON_CS6;
725 break;
726 case CS7:
727 dbg("config: 7bits/char\n");
728 ulcon = S3C2410_LCON_CS7;
729 break;
730 case CS8:
731 default:
732 dbg("config: 8bits/char\n");
733 ulcon = S3C2410_LCON_CS8;
734 break;
735 }
736
737 /* preserve original lcon IR settings */
738 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
739
740 if (termios->c_cflag & CSTOPB)
741 ulcon |= S3C2410_LCON_STOPB;
742
743 umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0;
744
745 if (termios->c_cflag & PARENB) {
746 if (termios->c_cflag & PARODD)
747 ulcon |= S3C2410_LCON_PODD;
748 else
749 ulcon |= S3C2410_LCON_PEVEN;
750 } else {
751 ulcon |= S3C2410_LCON_PNONE;
752 }
753
754 spin_lock_irqsave(&port->lock, flags);
755
756 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
757 ulcon, quot, udivslot);
758
759 wr_regl(port, S3C2410_ULCON, ulcon);
760 wr_regl(port, S3C2410_UBRDIV, quot);
761 wr_regl(port, S3C2410_UMCON, umcon);
762
763 if (ourport->info->has_divslot)
764 wr_regl(port, S3C2443_DIVSLOT, udivslot);
765
766 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
767 rd_regl(port, S3C2410_ULCON),
768 rd_regl(port, S3C2410_UCON),
769 rd_regl(port, S3C2410_UFCON));
770
771 /*
772 * Update the per-port timeout.
773 */
774 uart_update_timeout(port, termios->c_cflag, baud);
775
776 /*
777 * Which character status flags are we interested in?
778 */
779 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
780 if (termios->c_iflag & INPCK)
781 port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
782
783 /*
784 * Which character status flags should we ignore?
785 */
786 port->ignore_status_mask = 0;
787 if (termios->c_iflag & IGNPAR)
788 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
789 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
790 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
791
792 /*
793 * Ignore all characters if CREAD is not set.
794 */
795 if ((termios->c_cflag & CREAD) == 0)
796 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
797
798 spin_unlock_irqrestore(&port->lock, flags);
799}
800
801static const char *s3c24xx_serial_type(struct uart_port *port)
802{
803 switch (port->type) {
804 case PORT_S3C2410:
805 return "S3C2410";
806 case PORT_S3C2440:
807 return "S3C2440";
808 case PORT_S3C2412:
809 return "S3C2412";
810 case PORT_S3C6400:
811 return "S3C6400/10";
812 default:
813 return NULL;
814 }
815}
816
817#define MAP_SIZE (0x100)
818
819static void s3c24xx_serial_release_port(struct uart_port *port)
820{
821 release_mem_region(port->mapbase, MAP_SIZE);
822}
823
824static int s3c24xx_serial_request_port(struct uart_port *port)
825{
826 const char *name = s3c24xx_serial_portname(port);
827 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
828}
829
830static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
831{
832 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
833
834 if (flags & UART_CONFIG_TYPE &&
835 s3c24xx_serial_request_port(port) == 0)
836 port->type = info->type;
837}
838
839/*
840 * verify the new serial_struct (for TIOCSSERIAL).
841 */
842static int
843s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
844{
845 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
846
847 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
848 return -EINVAL;
849
850 return 0;
851}
852
853
854#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
855
856static struct console s3c24xx_serial_console;
857
858#define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
859#else
860#define S3C24XX_SERIAL_CONSOLE NULL
861#endif
862
863static struct uart_ops s3c24xx_serial_ops = {
864 .pm = s3c24xx_serial_pm,
865 .tx_empty = s3c24xx_serial_tx_empty,
866 .get_mctrl = s3c24xx_serial_get_mctrl,
867 .set_mctrl = s3c24xx_serial_set_mctrl,
868 .stop_tx = s3c24xx_serial_stop_tx,
869 .start_tx = s3c24xx_serial_start_tx,
870 .stop_rx = s3c24xx_serial_stop_rx,
871 .enable_ms = s3c24xx_serial_enable_ms,
872 .break_ctl = s3c24xx_serial_break_ctl,
873 .startup = s3c24xx_serial_startup,
874 .shutdown = s3c24xx_serial_shutdown,
875 .set_termios = s3c24xx_serial_set_termios,
876 .type = s3c24xx_serial_type,
877 .release_port = s3c24xx_serial_release_port,
878 .request_port = s3c24xx_serial_request_port,
879 .config_port = s3c24xx_serial_config_port,
880 .verify_port = s3c24xx_serial_verify_port,
881};
882
883
884static struct uart_driver s3c24xx_uart_drv = {
885 .owner = THIS_MODULE,
886 .dev_name = "s3c2410_serial",
887 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
888 .cons = S3C24XX_SERIAL_CONSOLE,
889 .driver_name = S3C24XX_SERIAL_NAME,
890 .major = S3C24XX_SERIAL_MAJOR,
891 .minor = S3C24XX_SERIAL_MINOR,
892};
893
894static struct s3c24xx_uart_port s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
895 [0] = {
896 .port = {
897 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
898 .iotype = UPIO_MEM,
899 .irq = IRQ_S3CUART_RX0,
900 .uartclk = 0,
901 .fifosize = 16,
902 .ops = &s3c24xx_serial_ops,
903 .flags = UPF_BOOT_AUTOCONF,
904 .line = 0,
905 }
906 },
907 [1] = {
908 .port = {
909 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[1].port.lock),
910 .iotype = UPIO_MEM,
911 .irq = IRQ_S3CUART_RX1,
912 .uartclk = 0,
913 .fifosize = 16,
914 .ops = &s3c24xx_serial_ops,
915 .flags = UPF_BOOT_AUTOCONF,
916 .line = 1,
917 }
918 },
919#if CONFIG_SERIAL_SAMSUNG_UARTS > 2
920
921 [2] = {
922 .port = {
923 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock),
924 .iotype = UPIO_MEM,
925 .irq = IRQ_S3CUART_RX2,
926 .uartclk = 0,
927 .fifosize = 16,
928 .ops = &s3c24xx_serial_ops,
929 .flags = UPF_BOOT_AUTOCONF,
930 .line = 2,
931 }
932 },
933#endif
934#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
935 [3] = {
936 .port = {
937 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock),
938 .iotype = UPIO_MEM,
939 .irq = IRQ_S3CUART_RX3,
940 .uartclk = 0,
941 .fifosize = 16,
942 .ops = &s3c24xx_serial_ops,
943 .flags = UPF_BOOT_AUTOCONF,
944 .line = 3,
945 }
946 }
947#endif
948};
949
950/* s3c24xx_serial_resetport
951 *
952 * wrapper to call the specific reset for this port (reset the fifos
953 * and the settings)
954*/
955
956static inline int s3c24xx_serial_resetport(struct uart_port *port,
957 struct s3c2410_uartcfg *cfg)
958{
959 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
960
961 return (info->reset_port)(port, cfg);
962}
963
964
965#ifdef CONFIG_CPU_FREQ
966
967static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
968 unsigned long val, void *data)
969{
970 struct s3c24xx_uart_port *port;
971 struct uart_port *uport;
972
973 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
974 uport = &port->port;
975
976 /* check to see if port is enabled */
977
978 if (port->pm_level != 0)
979 return 0;
980
981 /* try and work out if the baudrate is changing, we can detect
982 * a change in rate, but we do not have support for detecting
983 * a disturbance in the clock-rate over the change.
984 */
985
986 if (IS_ERR(port->clk))
987 goto exit;
988
989 if (port->baudclk_rate == clk_get_rate(port->clk))
990 goto exit;
991
992 if (val == CPUFREQ_PRECHANGE) {
993 /* we should really shut the port down whilst the
994 * frequency change is in progress. */
995
996 } else if (val == CPUFREQ_POSTCHANGE) {
997 struct ktermios *termios;
998 struct tty_struct *tty;
999
1000 if (uport->state == NULL)
1001 goto exit;
1002
1003 tty = uport->state->port.tty;
1004
1005 if (tty == NULL)
1006 goto exit;
1007
1008 termios = tty->termios;
1009
1010 if (termios == NULL) {
1011 printk(KERN_WARNING "%s: no termios?\n", __func__);
1012 goto exit;
1013 }
1014
1015 s3c24xx_serial_set_termios(uport, termios, NULL);
1016 }
1017
1018 exit:
1019 return 0;
1020}
1021
1022static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1023{
1024 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1025
1026 return cpufreq_register_notifier(&port->freq_transition,
1027 CPUFREQ_TRANSITION_NOTIFIER);
1028}
1029
1030static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1031{
1032 cpufreq_unregister_notifier(&port->freq_transition,
1033 CPUFREQ_TRANSITION_NOTIFIER);
1034}
1035
1036#else
1037static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1038{
1039 return 0;
1040}
1041
1042static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1043{
1044}
1045#endif
1046
1047/* s3c24xx_serial_init_port
1048 *
1049 * initialise a single serial port from the platform device given
1050 */
1051
1052static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1053 struct s3c24xx_uart_info *info,
1054 struct platform_device *platdev)
1055{
1056 struct uart_port *port = &ourport->port;
1057 struct s3c2410_uartcfg *cfg;
1058 struct resource *res;
1059 int ret;
1060
1061 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1062
1063 if (platdev == NULL)
1064 return -ENODEV;
1065
1066 cfg = s3c24xx_dev_to_cfg(&platdev->dev);
1067
1068 if (port->mapbase != 0)
1069 return 0;
1070
1071 if (cfg->hwport > CONFIG_SERIAL_SAMSUNG_UARTS) {
1072 printk(KERN_ERR "%s: port %d bigger than %d\n", __func__,
1073 cfg->hwport, CONFIG_SERIAL_SAMSUNG_UARTS);
1074 return -ERANGE;
1075 }
1076
1077 /* setup info for port */
1078 port->dev = &platdev->dev;
1079 ourport->info = info;
1080
1081 /* copy the info in from provided structure */
1082 ourport->port.fifosize = info->fifosize;
1083
1084 dbg("s3c24xx_serial_init_port: %p (hw %d)...\n", port, cfg->hwport);
1085
1086 port->uartclk = 1;
1087
1088 if (cfg->uart_flags & UPF_CONS_FLOW) {
1089 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1090 port->flags |= UPF_CONS_FLOW;
1091 }
1092
1093 /* sort our the physical and virtual addresses for each UART */
1094
1095 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1096 if (res == NULL) {
1097 printk(KERN_ERR "failed to find memory resource for uart\n");
1098 return -EINVAL;
1099 }
1100
1101 dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
1102
1103 port->mapbase = res->start;
1104 port->membase = S3C_VA_UART + res->start - (S3C_PA_UART & 0xfff00000);
1105 ret = platform_get_irq(platdev, 0);
1106 if (ret < 0)
1107 port->irq = 0;
1108 else {
1109 port->irq = ret;
1110 ourport->rx_irq = ret;
1111 ourport->tx_irq = ret + 1;
1112 }
1113
1114 ret = platform_get_irq(platdev, 1);
1115 if (ret > 0)
1116 ourport->tx_irq = ret;
1117
1118 ourport->clk = clk_get(&platdev->dev, "uart");
1119
1120 dbg("port: map=%08x, mem=%08x, irq=%d (%d,%d), clock=%ld\n",
1121 port->mapbase, port->membase, port->irq,
1122 ourport->rx_irq, ourport->tx_irq, port->uartclk);
1123
1124 /* reset the fifos (and setup the uart) */
1125 s3c24xx_serial_resetport(port, cfg);
1126 return 0;
1127}
1128
1129static ssize_t s3c24xx_serial_show_clksrc(struct device *dev,
1130 struct device_attribute *attr,
1131 char *buf)
1132{
1133 struct uart_port *port = s3c24xx_dev_to_port(dev);
1134 struct s3c24xx_uart_port *ourport = to_ourport(port);
1135
1136 return snprintf(buf, PAGE_SIZE, "* %s\n", ourport->clksrc->name);
1137}
1138
1139static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL);
1140
1141/* Device driver serial port probe */
1142
1143static int probe_index;
1144
1145int s3c24xx_serial_probe(struct platform_device *dev,
1146 struct s3c24xx_uart_info *info)
1147{
1148 struct s3c24xx_uart_port *ourport;
1149 int ret;
1150
1151 dbg("s3c24xx_serial_probe(%p, %p) %d\n", dev, info, probe_index);
1152
1153 ourport = &s3c24xx_serial_ports[probe_index];
1154 probe_index++;
1155
1156 dbg("%s: initialising port %p...\n", __func__, ourport);
1157
1158 ret = s3c24xx_serial_init_port(ourport, info, dev);
1159 if (ret < 0)
1160 goto probe_err;
1161
1162 dbg("%s: adding port\n", __func__);
1163 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1164 platform_set_drvdata(dev, &ourport->port);
1165
1166 ret = device_create_file(&dev->dev, &dev_attr_clock_source);
1167 if (ret < 0)
1168 printk(KERN_ERR "%s: failed to add clksrc attr.\n", __func__);
1169
1170 ret = s3c24xx_serial_cpufreq_register(ourport);
1171 if (ret < 0)
1172 dev_err(&dev->dev, "failed to add cpufreq notifier\n");
1173
1174 return 0;
1175
1176 probe_err:
1177 return ret;
1178}
1179
1180EXPORT_SYMBOL_GPL(s3c24xx_serial_probe);
1181
1182int __devexit s3c24xx_serial_remove(struct platform_device *dev)
1183{
1184 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1185
1186 if (port) {
1187 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
1188 device_remove_file(&dev->dev, &dev_attr_clock_source);
1189 uart_remove_one_port(&s3c24xx_uart_drv, port);
1190 }
1191
1192 return 0;
1193}
1194
1195EXPORT_SYMBOL_GPL(s3c24xx_serial_remove);
1196
1197/* UART power management code */
1198
1199#ifdef CONFIG_PM
1200
1201static int s3c24xx_serial_suspend(struct platform_device *dev, pm_message_t state)
1202{
1203 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1204
1205 if (port)
1206 uart_suspend_port(&s3c24xx_uart_drv, port);
1207
1208 return 0;
1209}
1210
1211static int s3c24xx_serial_resume(struct platform_device *dev)
1212{
1213 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1214 struct s3c24xx_uart_port *ourport = to_ourport(port);
1215
1216 if (port) {
1217 clk_enable(ourport->clk);
1218 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1219 clk_disable(ourport->clk);
1220
1221 uart_resume_port(&s3c24xx_uart_drv, port);
1222 }
1223
1224 return 0;
1225}
1226#endif
1227
1228int s3c24xx_serial_init(struct platform_driver *drv,
1229 struct s3c24xx_uart_info *info)
1230{
1231 dbg("s3c24xx_serial_init(%p,%p)\n", drv, info);
1232
1233#ifdef CONFIG_PM
1234 drv->suspend = s3c24xx_serial_suspend;
1235 drv->resume = s3c24xx_serial_resume;
1236#endif
1237
1238 return platform_driver_register(drv);
1239}
1240
1241EXPORT_SYMBOL_GPL(s3c24xx_serial_init);
1242
1243/* module initialisation code */
1244
1245static int __init s3c24xx_serial_modinit(void)
1246{
1247 int ret;
1248
1249 ret = uart_register_driver(&s3c24xx_uart_drv);
1250 if (ret < 0) {
1251 printk(KERN_ERR "failed to register UART driver\n");
1252 return -1;
1253 }
1254
1255 return 0;
1256}
1257
1258static void __exit s3c24xx_serial_modexit(void)
1259{
1260 uart_unregister_driver(&s3c24xx_uart_drv);
1261}
1262
1263module_init(s3c24xx_serial_modinit);
1264module_exit(s3c24xx_serial_modexit);
1265
1266/* Console code */
1267
1268#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1269
1270static struct uart_port *cons_uart;
1271
1272static int
1273s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1274{
1275 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1276 unsigned long ufstat, utrstat;
1277
1278 if (ufcon & S3C2410_UFCON_FIFOMODE) {
1279 /* fifo mode - check amount of data in fifo registers... */
1280
1281 ufstat = rd_regl(port, S3C2410_UFSTAT);
1282 return (ufstat & info->tx_fifofull) ? 0 : 1;
1283 }
1284
1285 /* in non-fifo mode, we go and use the tx buffer empty */
1286
1287 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1288 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1289}
1290
1291static void
1292s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
1293{
1294 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1295 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1296 barrier();
1297 wr_regb(cons_uart, S3C2410_UTXH, ch);
1298}
1299
1300static void
1301s3c24xx_serial_console_write(struct console *co, const char *s,
1302 unsigned int count)
1303{
1304 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
1305}
1306
1307static void __init
1308s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1309 int *parity, int *bits)
1310{
1311 struct s3c24xx_uart_clksrc clksrc;
1312 struct clk *clk;
1313 unsigned int ulcon;
1314 unsigned int ucon;
1315 unsigned int ubrdiv;
1316 unsigned long rate;
1317
1318 ulcon = rd_regl(port, S3C2410_ULCON);
1319 ucon = rd_regl(port, S3C2410_UCON);
1320 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1321
1322 dbg("s3c24xx_serial_get_options: port=%p\n"
1323 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1324 port, ulcon, ucon, ubrdiv);
1325
1326 if ((ucon & 0xf) != 0) {
1327 /* consider the serial port configured if the tx/rx mode set */
1328
1329 switch (ulcon & S3C2410_LCON_CSMASK) {
1330 case S3C2410_LCON_CS5:
1331 *bits = 5;
1332 break;
1333 case S3C2410_LCON_CS6:
1334 *bits = 6;
1335 break;
1336 case S3C2410_LCON_CS7:
1337 *bits = 7;
1338 break;
1339 default:
1340 case S3C2410_LCON_CS8:
1341 *bits = 8;
1342 break;
1343 }
1344
1345 switch (ulcon & S3C2410_LCON_PMASK) {
1346 case S3C2410_LCON_PEVEN:
1347 *parity = 'e';
1348 break;
1349
1350 case S3C2410_LCON_PODD:
1351 *parity = 'o';
1352 break;
1353
1354 case S3C2410_LCON_PNONE:
1355 default:
1356 *parity = 'n';
1357 }
1358
1359 /* now calculate the baud rate */
1360
1361 s3c24xx_serial_getsource(port, &clksrc);
1362
1363 clk = clk_get(port->dev, clksrc.name);
1364 if (!IS_ERR(clk) && clk != NULL)
1365 rate = clk_get_rate(clk) / clksrc.divisor;
1366 else
1367 rate = 1;
1368
1369
1370 *baud = rate / (16 * (ubrdiv + 1));
1371 dbg("calculated baud %d\n", *baud);
1372 }
1373
1374}
1375
1376/* s3c24xx_serial_init_ports
1377 *
1378 * initialise the serial ports from the machine provided initialisation
1379 * data.
1380*/
1381
1382static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info **info)
1383{
1384 struct s3c24xx_uart_port *ptr = s3c24xx_serial_ports;
1385 struct platform_device **platdev_ptr;
1386 int i;
1387
1388 dbg("s3c24xx_serial_init_ports: initialising ports...\n");
1389
1390 platdev_ptr = s3c24xx_uart_devs;
1391
1392 for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++, ptr++, platdev_ptr++) {
1393 s3c24xx_serial_init_port(ptr, info[i], *platdev_ptr);
1394 }
1395
1396 return 0;
1397}
1398
1399static int __init
1400s3c24xx_serial_console_setup(struct console *co, char *options)
1401{
1402 struct uart_port *port;
1403 int baud = 9600;
1404 int bits = 8;
1405 int parity = 'n';
1406 int flow = 'n';
1407
1408 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1409 co, co->index, options);
1410
1411 /* is this a valid port */
1412
1413 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
1414 co->index = 0;
1415
1416 port = &s3c24xx_serial_ports[co->index].port;
1417
1418 /* is the port configured? */
1419
1420 if (port->mapbase == 0x0) {
1421 co->index = 0;
1422 port = &s3c24xx_serial_ports[co->index].port;
1423 }
1424
1425 cons_uart = port;
1426
1427 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1428
1429 /*
1430 * Check whether an invalid uart number has been specified, and
1431 * if so, search for the first available port that does have
1432 * console support.
1433 */
1434 if (options)
1435 uart_parse_options(options, &baud, &parity, &bits, &flow);
1436 else
1437 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1438
1439 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1440
1441 return uart_set_options(port, co, baud, parity, bits, flow);
1442}
1443
1444/* s3c24xx_serial_initconsole
1445 *
1446 * initialise the console from one of the uart drivers
1447*/
1448
1449static struct console s3c24xx_serial_console = {
1450 .name = S3C24XX_SERIAL_NAME,
1451 .device = uart_console_device,
1452 .flags = CON_PRINTBUFFER,
1453 .index = -1,
1454 .write = s3c24xx_serial_console_write,
1455 .setup = s3c24xx_serial_console_setup
1456};
1457
1458int s3c24xx_serial_initconsole(struct platform_driver *drv,
1459 struct s3c24xx_uart_info **info)
1460
1461{
1462 struct platform_device *dev = s3c24xx_uart_devs[0];
1463
1464 dbg("s3c24xx_serial_initconsole\n");
1465
1466 /* select driver based on the cpu */
1467
1468 if (dev == NULL) {
1469 printk(KERN_ERR "s3c24xx: no devices for console init\n");
1470 return 0;
1471 }
1472
1473 if (strcmp(dev->name, drv->driver.name) != 0)
1474 return 0;
1475
1476 s3c24xx_serial_console.data = &s3c24xx_uart_drv;
1477 s3c24xx_serial_init_ports(info);
1478
1479 register_console(&s3c24xx_serial_console);
1480 return 0;
1481}
1482
1483#endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
1484
1485MODULE_DESCRIPTION("Samsung SoC Serial port driver");
1486MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1487MODULE_LICENSE("GPL v2");
diff --git a/drivers/serial/samsung.h b/drivers/serial/samsung.h
deleted file mode 100644
index 0ac06a07d25f..000000000000
--- a/drivers/serial/samsung.h
+++ /dev/null
@@ -1,120 +0,0 @@
1/* linux/drivers/serial/samsung.h
2 *
3 * Driver for Samsung SoC onboard UARTs.
4 *
5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
6 * http://armlinux.simtec.co.uk/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13struct s3c24xx_uart_info {
14 char *name;
15 unsigned int type;
16 unsigned int fifosize;
17 unsigned long rx_fifomask;
18 unsigned long rx_fifoshift;
19 unsigned long rx_fifofull;
20 unsigned long tx_fifomask;
21 unsigned long tx_fifoshift;
22 unsigned long tx_fifofull;
23
24 /* uart port features */
25
26 unsigned int has_divslot:1;
27
28 /* clock source control */
29
30 int (*get_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
31 int (*set_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
32
33 /* uart controls */
34 int (*reset_port)(struct uart_port *, struct s3c2410_uartcfg *);
35};
36
37struct s3c24xx_uart_port {
38 unsigned char rx_claimed;
39 unsigned char tx_claimed;
40 unsigned int pm_level;
41 unsigned long baudclk_rate;
42
43 unsigned int rx_irq;
44 unsigned int tx_irq;
45
46 struct s3c24xx_uart_info *info;
47 struct s3c24xx_uart_clksrc *clksrc;
48 struct clk *clk;
49 struct clk *baudclk;
50 struct uart_port port;
51
52#ifdef CONFIG_CPU_FREQ
53 struct notifier_block freq_transition;
54#endif
55};
56
57/* conversion functions */
58
59#define s3c24xx_dev_to_port(__dev) (struct uart_port *)dev_get_drvdata(__dev)
60#define s3c24xx_dev_to_cfg(__dev) (struct s3c2410_uartcfg *)((__dev)->platform_data)
61
62/* register access controls */
63
64#define portaddr(port, reg) ((port)->membase + (reg))
65
66#define rd_regb(port, reg) (__raw_readb(portaddr(port, reg)))
67#define rd_regl(port, reg) (__raw_readl(portaddr(port, reg)))
68
69#define wr_regb(port, reg, val) __raw_writeb(val, portaddr(port, reg))
70#define wr_regl(port, reg, val) __raw_writel(val, portaddr(port, reg))
71
72extern int s3c24xx_serial_probe(struct platform_device *dev,
73 struct s3c24xx_uart_info *uart);
74
75extern int __devexit s3c24xx_serial_remove(struct platform_device *dev);
76
77extern int s3c24xx_serial_initconsole(struct platform_driver *drv,
78 struct s3c24xx_uart_info **uart);
79
80extern int s3c24xx_serial_init(struct platform_driver *drv,
81 struct s3c24xx_uart_info *info);
82
83#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
84
85#define s3c24xx_console_init(__drv, __inf) \
86static int __init s3c_serial_console_init(void) \
87{ \
88 struct s3c24xx_uart_info *uinfo[CONFIG_SERIAL_SAMSUNG_UARTS]; \
89 int i; \
90 \
91 for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++) \
92 uinfo[i] = __inf; \
93 return s3c24xx_serial_initconsole(__drv, uinfo); \
94} \
95 \
96console_initcall(s3c_serial_console_init)
97
98#else
99#define s3c24xx_console_init(drv, inf) extern void no_console(void)
100#endif
101
102#ifdef CONFIG_SERIAL_SAMSUNG_DEBUG
103
104extern void printascii(const char *);
105
106static void dbg(const char *fmt, ...)
107{
108 va_list va;
109 char buff[256];
110
111 va_start(va, fmt);
112 vsprintf(buff, fmt, va);
113 va_end(va);
114
115 printascii(buff);
116}
117
118#else
119#define dbg(x...) do { } while (0)
120#endif
diff --git a/drivers/serial/sb1250-duart.c b/drivers/serial/sb1250-duart.c
deleted file mode 100644
index a2f2b3254499..000000000000
--- a/drivers/serial/sb1250-duart.c
+++ /dev/null
@@ -1,976 +0,0 @@
1/*
2 * drivers/serial/sb1250-duart.c
3 *
4 * Support for the asynchronous serial interface (DUART) included
5 * in the BCM1250 and derived System-On-a-Chip (SOC) devices.
6 *
7 * Copyright (c) 2007 Maciej W. Rozycki
8 *
9 * Derived from drivers/char/sb1250_duart.c for which the following
10 * copyright applies:
11 *
12 * Copyright (c) 2000, 2001, 2002, 2003, 2004 Broadcom Corporation
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
18 *
19 * References:
20 *
21 * "BCM1250/BCM1125/BCM1125H User Manual", Broadcom Corporation
22 */
23
24#if defined(CONFIG_SERIAL_SB1250_DUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
25#define SUPPORT_SYSRQ
26#endif
27
28#include <linux/compiler.h>
29#include <linux/console.h>
30#include <linux/delay.h>
31#include <linux/errno.h>
32#include <linux/init.h>
33#include <linux/interrupt.h>
34#include <linux/ioport.h>
35#include <linux/kernel.h>
36#include <linux/major.h>
37#include <linux/serial.h>
38#include <linux/serial_core.h>
39#include <linux/spinlock.h>
40#include <linux/sysrq.h>
41#include <linux/tty.h>
42#include <linux/types.h>
43
44#include <asm/atomic.h>
45#include <asm/io.h>
46#include <asm/war.h>
47
48#include <asm/sibyte/sb1250.h>
49#include <asm/sibyte/sb1250_uart.h>
50#include <asm/sibyte/swarm.h>
51
52
53#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
54#include <asm/sibyte/bcm1480_regs.h>
55#include <asm/sibyte/bcm1480_int.h>
56
57#define SBD_CHANREGS(line) A_BCM1480_DUART_CHANREG((line), 0)
58#define SBD_CTRLREGS(line) A_BCM1480_DUART_CTRLREG((line), 0)
59#define SBD_INT(line) (K_BCM1480_INT_UART_0 + (line))
60
61#define DUART_CHANREG_SPACING BCM1480_DUART_CHANREG_SPACING
62
63#define R_DUART_IMRREG(line) R_BCM1480_DUART_IMRREG(line)
64#define R_DUART_INCHREG(line) R_BCM1480_DUART_INCHREG(line)
65#define R_DUART_ISRREG(line) R_BCM1480_DUART_ISRREG(line)
66
67#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
68#include <asm/sibyte/sb1250_regs.h>
69#include <asm/sibyte/sb1250_int.h>
70
71#define SBD_CHANREGS(line) A_DUART_CHANREG((line), 0)
72#define SBD_CTRLREGS(line) A_DUART_CTRLREG(0)
73#define SBD_INT(line) (K_INT_UART_0 + (line))
74
75#else
76#error invalid SB1250 UART configuration
77
78#endif
79
80
81MODULE_AUTHOR("Maciej W. Rozycki <macro@linux-mips.org>");
82MODULE_DESCRIPTION("BCM1xxx on-chip DUART serial driver");
83MODULE_LICENSE("GPL");
84
85
86#define DUART_MAX_CHIP 2
87#define DUART_MAX_SIDE 2
88
89/*
90 * Per-port state.
91 */
92struct sbd_port {
93 struct sbd_duart *duart;
94 struct uart_port port;
95 unsigned char __iomem *memctrl;
96 int tx_stopped;
97 int initialised;
98};
99
100/*
101 * Per-DUART state for the shared register space.
102 */
103struct sbd_duart {
104 struct sbd_port sport[2];
105 unsigned long mapctrl;
106 atomic_t map_guard;
107};
108
109#define to_sport(uport) container_of(uport, struct sbd_port, port)
110
111static struct sbd_duart sbd_duarts[DUART_MAX_CHIP];
112
113
114/*
115 * Reading and writing SB1250 DUART registers.
116 *
117 * There are three register spaces: two per-channel ones and
118 * a shared one. We have to define accessors appropriately.
119 * All registers are 64-bit and all but the Baud Rate Clock
120 * registers only define 8 least significant bits. There is
121 * also a workaround to take into account. Raw accessors use
122 * the full register width, but cooked ones truncate it
123 * intentionally so that the rest of the driver does not care.
124 */
125static u64 __read_sbdchn(struct sbd_port *sport, int reg)
126{
127 void __iomem *csr = sport->port.membase + reg;
128
129 return __raw_readq(csr);
130}
131
132static u64 __read_sbdshr(struct sbd_port *sport, int reg)
133{
134 void __iomem *csr = sport->memctrl + reg;
135
136 return __raw_readq(csr);
137}
138
139static void __write_sbdchn(struct sbd_port *sport, int reg, u64 value)
140{
141 void __iomem *csr = sport->port.membase + reg;
142
143 __raw_writeq(value, csr);
144}
145
146static void __write_sbdshr(struct sbd_port *sport, int reg, u64 value)
147{
148 void __iomem *csr = sport->memctrl + reg;
149
150 __raw_writeq(value, csr);
151}
152
153/*
154 * In bug 1956, we get glitches that can mess up uart registers. This
155 * "read-mode-reg after any register access" is an accepted workaround.
156 */
157static void __war_sbd1956(struct sbd_port *sport)
158{
159 __read_sbdchn(sport, R_DUART_MODE_REG_1);
160 __read_sbdchn(sport, R_DUART_MODE_REG_2);
161}
162
163static unsigned char read_sbdchn(struct sbd_port *sport, int reg)
164{
165 unsigned char retval;
166
167 retval = __read_sbdchn(sport, reg);
168 if (SIBYTE_1956_WAR)
169 __war_sbd1956(sport);
170 return retval;
171}
172
173static unsigned char read_sbdshr(struct sbd_port *sport, int reg)
174{
175 unsigned char retval;
176
177 retval = __read_sbdshr(sport, reg);
178 if (SIBYTE_1956_WAR)
179 __war_sbd1956(sport);
180 return retval;
181}
182
183static void write_sbdchn(struct sbd_port *sport, int reg, unsigned int value)
184{
185 __write_sbdchn(sport, reg, value);
186 if (SIBYTE_1956_WAR)
187 __war_sbd1956(sport);
188}
189
190static void write_sbdshr(struct sbd_port *sport, int reg, unsigned int value)
191{
192 __write_sbdshr(sport, reg, value);
193 if (SIBYTE_1956_WAR)
194 __war_sbd1956(sport);
195}
196
197
198static int sbd_receive_ready(struct sbd_port *sport)
199{
200 return read_sbdchn(sport, R_DUART_STATUS) & M_DUART_RX_RDY;
201}
202
203static int sbd_receive_drain(struct sbd_port *sport)
204{
205 int loops = 10000;
206
207 while (sbd_receive_ready(sport) && --loops)
208 read_sbdchn(sport, R_DUART_RX_HOLD);
209 return loops;
210}
211
212static int __maybe_unused sbd_transmit_ready(struct sbd_port *sport)
213{
214 return read_sbdchn(sport, R_DUART_STATUS) & M_DUART_TX_RDY;
215}
216
217static int __maybe_unused sbd_transmit_drain(struct sbd_port *sport)
218{
219 int loops = 10000;
220
221 while (!sbd_transmit_ready(sport) && --loops)
222 udelay(2);
223 return loops;
224}
225
226static int sbd_transmit_empty(struct sbd_port *sport)
227{
228 return read_sbdchn(sport, R_DUART_STATUS) & M_DUART_TX_EMT;
229}
230
231static int sbd_line_drain(struct sbd_port *sport)
232{
233 int loops = 10000;
234
235 while (!sbd_transmit_empty(sport) && --loops)
236 udelay(2);
237 return loops;
238}
239
240
241static unsigned int sbd_tx_empty(struct uart_port *uport)
242{
243 struct sbd_port *sport = to_sport(uport);
244
245 return sbd_transmit_empty(sport) ? TIOCSER_TEMT : 0;
246}
247
248static unsigned int sbd_get_mctrl(struct uart_port *uport)
249{
250 struct sbd_port *sport = to_sport(uport);
251 unsigned int mctrl, status;
252
253 status = read_sbdshr(sport, R_DUART_IN_PORT);
254 status >>= (uport->line) % 2;
255 mctrl = (!(status & M_DUART_IN_PIN0_VAL) ? TIOCM_CTS : 0) |
256 (!(status & M_DUART_IN_PIN4_VAL) ? TIOCM_CAR : 0) |
257 (!(status & M_DUART_RIN0_PIN) ? TIOCM_RNG : 0) |
258 (!(status & M_DUART_IN_PIN2_VAL) ? TIOCM_DSR : 0);
259 return mctrl;
260}
261
262static void sbd_set_mctrl(struct uart_port *uport, unsigned int mctrl)
263{
264 struct sbd_port *sport = to_sport(uport);
265 unsigned int clr = 0, set = 0, mode2;
266
267 if (mctrl & TIOCM_DTR)
268 set |= M_DUART_SET_OPR2;
269 else
270 clr |= M_DUART_CLR_OPR2;
271 if (mctrl & TIOCM_RTS)
272 set |= M_DUART_SET_OPR0;
273 else
274 clr |= M_DUART_CLR_OPR0;
275 clr <<= (uport->line) % 2;
276 set <<= (uport->line) % 2;
277
278 mode2 = read_sbdchn(sport, R_DUART_MODE_REG_2);
279 mode2 &= ~M_DUART_CHAN_MODE;
280 if (mctrl & TIOCM_LOOP)
281 mode2 |= V_DUART_CHAN_MODE_LCL_LOOP;
282 else
283 mode2 |= V_DUART_CHAN_MODE_NORMAL;
284
285 write_sbdshr(sport, R_DUART_CLEAR_OPR, clr);
286 write_sbdshr(sport, R_DUART_SET_OPR, set);
287 write_sbdchn(sport, R_DUART_MODE_REG_2, mode2);
288}
289
290static void sbd_stop_tx(struct uart_port *uport)
291{
292 struct sbd_port *sport = to_sport(uport);
293
294 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS);
295 sport->tx_stopped = 1;
296};
297
298static void sbd_start_tx(struct uart_port *uport)
299{
300 struct sbd_port *sport = to_sport(uport);
301 unsigned int mask;
302
303 /* Enable tx interrupts. */
304 mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2));
305 mask |= M_DUART_IMR_TX;
306 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask);
307
308 /* Go!, go!, go!... */
309 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_EN);
310 sport->tx_stopped = 0;
311};
312
313static void sbd_stop_rx(struct uart_port *uport)
314{
315 struct sbd_port *sport = to_sport(uport);
316
317 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), 0);
318};
319
320static void sbd_enable_ms(struct uart_port *uport)
321{
322 struct sbd_port *sport = to_sport(uport);
323
324 write_sbdchn(sport, R_DUART_AUXCTL_X,
325 M_DUART_CIN_CHNG_ENA | M_DUART_CTS_CHNG_ENA);
326}
327
328static void sbd_break_ctl(struct uart_port *uport, int break_state)
329{
330 struct sbd_port *sport = to_sport(uport);
331
332 if (break_state == -1)
333 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_START_BREAK);
334 else
335 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_STOP_BREAK);
336}
337
338
339static void sbd_receive_chars(struct sbd_port *sport)
340{
341 struct uart_port *uport = &sport->port;
342 struct uart_icount *icount;
343 unsigned int status, ch, flag;
344 int count;
345
346 for (count = 16; count; count--) {
347 status = read_sbdchn(sport, R_DUART_STATUS);
348 if (!(status & M_DUART_RX_RDY))
349 break;
350
351 ch = read_sbdchn(sport, R_DUART_RX_HOLD);
352
353 flag = TTY_NORMAL;
354
355 icount = &uport->icount;
356 icount->rx++;
357
358 if (unlikely(status &
359 (M_DUART_RCVD_BRK | M_DUART_FRM_ERR |
360 M_DUART_PARITY_ERR | M_DUART_OVRUN_ERR))) {
361 if (status & M_DUART_RCVD_BRK) {
362 icount->brk++;
363 if (uart_handle_break(uport))
364 continue;
365 } else if (status & M_DUART_FRM_ERR)
366 icount->frame++;
367 else if (status & M_DUART_PARITY_ERR)
368 icount->parity++;
369 if (status & M_DUART_OVRUN_ERR)
370 icount->overrun++;
371
372 status &= uport->read_status_mask;
373 if (status & M_DUART_RCVD_BRK)
374 flag = TTY_BREAK;
375 else if (status & M_DUART_FRM_ERR)
376 flag = TTY_FRAME;
377 else if (status & M_DUART_PARITY_ERR)
378 flag = TTY_PARITY;
379 }
380
381 if (uart_handle_sysrq_char(uport, ch))
382 continue;
383
384 uart_insert_char(uport, status, M_DUART_OVRUN_ERR, ch, flag);
385 }
386
387 tty_flip_buffer_push(uport->state->port.tty);
388}
389
390static void sbd_transmit_chars(struct sbd_port *sport)
391{
392 struct uart_port *uport = &sport->port;
393 struct circ_buf *xmit = &sport->port.state->xmit;
394 unsigned int mask;
395 int stop_tx;
396
397 /* XON/XOFF chars. */
398 if (sport->port.x_char) {
399 write_sbdchn(sport, R_DUART_TX_HOLD, sport->port.x_char);
400 sport->port.icount.tx++;
401 sport->port.x_char = 0;
402 return;
403 }
404
405 /* If nothing to do or stopped or hardware stopped. */
406 stop_tx = (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port));
407
408 /* Send char. */
409 if (!stop_tx) {
410 write_sbdchn(sport, R_DUART_TX_HOLD, xmit->buf[xmit->tail]);
411 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
412 sport->port.icount.tx++;
413
414 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
415 uart_write_wakeup(&sport->port);
416 }
417
418 /* Are we are done? */
419 if (stop_tx || uart_circ_empty(xmit)) {
420 /* Disable tx interrupts. */
421 mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2));
422 mask &= ~M_DUART_IMR_TX;
423 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask);
424 }
425}
426
427static void sbd_status_handle(struct sbd_port *sport)
428{
429 struct uart_port *uport = &sport->port;
430 unsigned int delta;
431
432 delta = read_sbdshr(sport, R_DUART_INCHREG((uport->line) % 2));
433 delta >>= (uport->line) % 2;
434
435 if (delta & (M_DUART_IN_PIN0_VAL << S_DUART_IN_PIN_CHNG))
436 uart_handle_cts_change(uport, !(delta & M_DUART_IN_PIN0_VAL));
437
438 if (delta & (M_DUART_IN_PIN2_VAL << S_DUART_IN_PIN_CHNG))
439 uport->icount.dsr++;
440
441 if (delta & ((M_DUART_IN_PIN2_VAL | M_DUART_IN_PIN0_VAL) <<
442 S_DUART_IN_PIN_CHNG))
443 wake_up_interruptible(&uport->state->port.delta_msr_wait);
444}
445
446static irqreturn_t sbd_interrupt(int irq, void *dev_id)
447{
448 struct sbd_port *sport = dev_id;
449 struct uart_port *uport = &sport->port;
450 irqreturn_t status = IRQ_NONE;
451 unsigned int intstat;
452 int count;
453
454 for (count = 16; count; count--) {
455 intstat = read_sbdshr(sport,
456 R_DUART_ISRREG((uport->line) % 2));
457 intstat &= read_sbdshr(sport,
458 R_DUART_IMRREG((uport->line) % 2));
459 intstat &= M_DUART_ISR_ALL;
460 if (!intstat)
461 break;
462
463 if (intstat & M_DUART_ISR_RX)
464 sbd_receive_chars(sport);
465 if (intstat & M_DUART_ISR_IN)
466 sbd_status_handle(sport);
467 if (intstat & M_DUART_ISR_TX)
468 sbd_transmit_chars(sport);
469
470 status = IRQ_HANDLED;
471 }
472
473 return status;
474}
475
476
477static int sbd_startup(struct uart_port *uport)
478{
479 struct sbd_port *sport = to_sport(uport);
480 unsigned int mode1;
481 int ret;
482
483 ret = request_irq(sport->port.irq, sbd_interrupt,
484 IRQF_SHARED, "sb1250-duart", sport);
485 if (ret)
486 return ret;
487
488 /* Clear the receive FIFO. */
489 sbd_receive_drain(sport);
490
491 /* Clear the interrupt registers. */
492 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT);
493 read_sbdshr(sport, R_DUART_INCHREG((uport->line) % 2));
494
495 /* Set rx/tx interrupt to FIFO available. */
496 mode1 = read_sbdchn(sport, R_DUART_MODE_REG_1);
497 mode1 &= ~(M_DUART_RX_IRQ_SEL_RXFULL | M_DUART_TX_IRQ_SEL_TXEMPT);
498 write_sbdchn(sport, R_DUART_MODE_REG_1, mode1);
499
500 /* Disable tx, enable rx. */
501 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS | M_DUART_RX_EN);
502 sport->tx_stopped = 1;
503
504 /* Enable interrupts. */
505 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2),
506 M_DUART_IMR_IN | M_DUART_IMR_RX);
507
508 return 0;
509}
510
511static void sbd_shutdown(struct uart_port *uport)
512{
513 struct sbd_port *sport = to_sport(uport);
514
515 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS | M_DUART_RX_DIS);
516 sport->tx_stopped = 1;
517 free_irq(sport->port.irq, sport);
518}
519
520
521static void sbd_init_port(struct sbd_port *sport)
522{
523 struct uart_port *uport = &sport->port;
524
525 if (sport->initialised)
526 return;
527
528 /* There is no DUART reset feature, so just set some sane defaults. */
529 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_RESET_TX);
530 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_RESET_RX);
531 write_sbdchn(sport, R_DUART_MODE_REG_1, V_DUART_BITS_PER_CHAR_8);
532 write_sbdchn(sport, R_DUART_MODE_REG_2, 0);
533 write_sbdchn(sport, R_DUART_FULL_CTL,
534 V_DUART_INT_TIME(0) | V_DUART_SIG_FULL(15));
535 write_sbdchn(sport, R_DUART_OPCR_X, 0);
536 write_sbdchn(sport, R_DUART_AUXCTL_X, 0);
537 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), 0);
538
539 sport->initialised = 1;
540}
541
542static void sbd_set_termios(struct uart_port *uport, struct ktermios *termios,
543 struct ktermios *old_termios)
544{
545 struct sbd_port *sport = to_sport(uport);
546 unsigned int mode1 = 0, mode2 = 0, aux = 0;
547 unsigned int mode1mask = 0, mode2mask = 0, auxmask = 0;
548 unsigned int oldmode1, oldmode2, oldaux;
549 unsigned int baud, brg;
550 unsigned int command;
551
552 mode1mask |= ~(M_DUART_PARITY_MODE | M_DUART_PARITY_TYPE_ODD |
553 M_DUART_BITS_PER_CHAR);
554 mode2mask |= ~M_DUART_STOP_BIT_LEN_2;
555 auxmask |= ~M_DUART_CTS_CHNG_ENA;
556
557 /* Byte size. */
558 switch (termios->c_cflag & CSIZE) {
559 case CS5:
560 case CS6:
561 /* Unsupported, leave unchanged. */
562 mode1mask |= M_DUART_PARITY_MODE;
563 break;
564 case CS7:
565 mode1 |= V_DUART_BITS_PER_CHAR_7;
566 break;
567 case CS8:
568 default:
569 mode1 |= V_DUART_BITS_PER_CHAR_8;
570 break;
571 }
572
573 /* Parity and stop bits. */
574 if (termios->c_cflag & CSTOPB)
575 mode2 |= M_DUART_STOP_BIT_LEN_2;
576 else
577 mode2 |= M_DUART_STOP_BIT_LEN_1;
578 if (termios->c_cflag & PARENB)
579 mode1 |= V_DUART_PARITY_MODE_ADD;
580 else
581 mode1 |= V_DUART_PARITY_MODE_NONE;
582 if (termios->c_cflag & PARODD)
583 mode1 |= M_DUART_PARITY_TYPE_ODD;
584 else
585 mode1 |= M_DUART_PARITY_TYPE_EVEN;
586
587 baud = uart_get_baud_rate(uport, termios, old_termios, 1200, 5000000);
588 brg = V_DUART_BAUD_RATE(baud);
589 /* The actual lower bound is 1221bps, so compensate. */
590 if (brg > M_DUART_CLK_COUNTER)
591 brg = M_DUART_CLK_COUNTER;
592
593 uart_update_timeout(uport, termios->c_cflag, baud);
594
595 uport->read_status_mask = M_DUART_OVRUN_ERR;
596 if (termios->c_iflag & INPCK)
597 uport->read_status_mask |= M_DUART_FRM_ERR |
598 M_DUART_PARITY_ERR;
599 if (termios->c_iflag & (BRKINT | PARMRK))
600 uport->read_status_mask |= M_DUART_RCVD_BRK;
601
602 uport->ignore_status_mask = 0;
603 if (termios->c_iflag & IGNPAR)
604 uport->ignore_status_mask |= M_DUART_FRM_ERR |
605 M_DUART_PARITY_ERR;
606 if (termios->c_iflag & IGNBRK) {
607 uport->ignore_status_mask |= M_DUART_RCVD_BRK;
608 if (termios->c_iflag & IGNPAR)
609 uport->ignore_status_mask |= M_DUART_OVRUN_ERR;
610 }
611
612 if (termios->c_cflag & CREAD)
613 command = M_DUART_RX_EN;
614 else
615 command = M_DUART_RX_DIS;
616
617 if (termios->c_cflag & CRTSCTS)
618 aux |= M_DUART_CTS_CHNG_ENA;
619 else
620 aux &= ~M_DUART_CTS_CHNG_ENA;
621
622 spin_lock(&uport->lock);
623
624 if (sport->tx_stopped)
625 command |= M_DUART_TX_DIS;
626 else
627 command |= M_DUART_TX_EN;
628
629 oldmode1 = read_sbdchn(sport, R_DUART_MODE_REG_1) & mode1mask;
630 oldmode2 = read_sbdchn(sport, R_DUART_MODE_REG_2) & mode2mask;
631 oldaux = read_sbdchn(sport, R_DUART_AUXCTL_X) & auxmask;
632
633 if (!sport->tx_stopped)
634 sbd_line_drain(sport);
635 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS | M_DUART_RX_DIS);
636
637 write_sbdchn(sport, R_DUART_MODE_REG_1, mode1 | oldmode1);
638 write_sbdchn(sport, R_DUART_MODE_REG_2, mode2 | oldmode2);
639 write_sbdchn(sport, R_DUART_CLK_SEL, brg);
640 write_sbdchn(sport, R_DUART_AUXCTL_X, aux | oldaux);
641
642 write_sbdchn(sport, R_DUART_CMD, command);
643
644 spin_unlock(&uport->lock);
645}
646
647
648static const char *sbd_type(struct uart_port *uport)
649{
650 return "SB1250 DUART";
651}
652
653static void sbd_release_port(struct uart_port *uport)
654{
655 struct sbd_port *sport = to_sport(uport);
656 struct sbd_duart *duart = sport->duart;
657 int map_guard;
658
659 iounmap(sport->memctrl);
660 sport->memctrl = NULL;
661 iounmap(uport->membase);
662 uport->membase = NULL;
663
664 map_guard = atomic_add_return(-1, &duart->map_guard);
665 if (!map_guard)
666 release_mem_region(duart->mapctrl, DUART_CHANREG_SPACING);
667 release_mem_region(uport->mapbase, DUART_CHANREG_SPACING);
668}
669
670static int sbd_map_port(struct uart_port *uport)
671{
672 const char *err = KERN_ERR "sbd: Cannot map MMIO\n";
673 struct sbd_port *sport = to_sport(uport);
674 struct sbd_duart *duart = sport->duart;
675
676 if (!uport->membase)
677 uport->membase = ioremap_nocache(uport->mapbase,
678 DUART_CHANREG_SPACING);
679 if (!uport->membase) {
680 printk(err);
681 return -ENOMEM;
682 }
683
684 if (!sport->memctrl)
685 sport->memctrl = ioremap_nocache(duart->mapctrl,
686 DUART_CHANREG_SPACING);
687 if (!sport->memctrl) {
688 printk(err);
689 iounmap(uport->membase);
690 uport->membase = NULL;
691 return -ENOMEM;
692 }
693
694 return 0;
695}
696
697static int sbd_request_port(struct uart_port *uport)
698{
699 const char *err = KERN_ERR "sbd: Unable to reserve MMIO resource\n";
700 struct sbd_duart *duart = to_sport(uport)->duart;
701 int map_guard;
702 int ret = 0;
703
704 if (!request_mem_region(uport->mapbase, DUART_CHANREG_SPACING,
705 "sb1250-duart")) {
706 printk(err);
707 return -EBUSY;
708 }
709 map_guard = atomic_add_return(1, &duart->map_guard);
710 if (map_guard == 1) {
711 if (!request_mem_region(duart->mapctrl, DUART_CHANREG_SPACING,
712 "sb1250-duart")) {
713 atomic_add(-1, &duart->map_guard);
714 printk(err);
715 ret = -EBUSY;
716 }
717 }
718 if (!ret) {
719 ret = sbd_map_port(uport);
720 if (ret) {
721 map_guard = atomic_add_return(-1, &duart->map_guard);
722 if (!map_guard)
723 release_mem_region(duart->mapctrl,
724 DUART_CHANREG_SPACING);
725 }
726 }
727 if (ret) {
728 release_mem_region(uport->mapbase, DUART_CHANREG_SPACING);
729 return ret;
730 }
731 return 0;
732}
733
734static void sbd_config_port(struct uart_port *uport, int flags)
735{
736 struct sbd_port *sport = to_sport(uport);
737
738 if (flags & UART_CONFIG_TYPE) {
739 if (sbd_request_port(uport))
740 return;
741
742 uport->type = PORT_SB1250_DUART;
743
744 sbd_init_port(sport);
745 }
746}
747
748static int sbd_verify_port(struct uart_port *uport, struct serial_struct *ser)
749{
750 int ret = 0;
751
752 if (ser->type != PORT_UNKNOWN && ser->type != PORT_SB1250_DUART)
753 ret = -EINVAL;
754 if (ser->irq != uport->irq)
755 ret = -EINVAL;
756 if (ser->baud_base != uport->uartclk / 16)
757 ret = -EINVAL;
758 return ret;
759}
760
761
762static const struct uart_ops sbd_ops = {
763 .tx_empty = sbd_tx_empty,
764 .set_mctrl = sbd_set_mctrl,
765 .get_mctrl = sbd_get_mctrl,
766 .stop_tx = sbd_stop_tx,
767 .start_tx = sbd_start_tx,
768 .stop_rx = sbd_stop_rx,
769 .enable_ms = sbd_enable_ms,
770 .break_ctl = sbd_break_ctl,
771 .startup = sbd_startup,
772 .shutdown = sbd_shutdown,
773 .set_termios = sbd_set_termios,
774 .type = sbd_type,
775 .release_port = sbd_release_port,
776 .request_port = sbd_request_port,
777 .config_port = sbd_config_port,
778 .verify_port = sbd_verify_port,
779};
780
781/* Initialize SB1250 DUART port structures. */
782static void __init sbd_probe_duarts(void)
783{
784 static int probed;
785 int chip, side;
786 int max_lines, line;
787
788 if (probed)
789 return;
790
791 /* Set the number of available units based on the SOC type. */
792 switch (soc_type) {
793 case K_SYS_SOC_TYPE_BCM1x55:
794 case K_SYS_SOC_TYPE_BCM1x80:
795 max_lines = 4;
796 break;
797 default:
798 /* Assume at least two serial ports at the normal address. */
799 max_lines = 2;
800 break;
801 }
802
803 probed = 1;
804
805 for (chip = 0, line = 0; chip < DUART_MAX_CHIP && line < max_lines;
806 chip++) {
807 sbd_duarts[chip].mapctrl = SBD_CTRLREGS(line);
808
809 for (side = 0; side < DUART_MAX_SIDE && line < max_lines;
810 side++, line++) {
811 struct sbd_port *sport = &sbd_duarts[chip].sport[side];
812 struct uart_port *uport = &sport->port;
813
814 sport->duart = &sbd_duarts[chip];
815
816 uport->irq = SBD_INT(line);
817 uport->uartclk = 100000000 / 20 * 16;
818 uport->fifosize = 16;
819 uport->iotype = UPIO_MEM;
820 uport->flags = UPF_BOOT_AUTOCONF;
821 uport->ops = &sbd_ops;
822 uport->line = line;
823 uport->mapbase = SBD_CHANREGS(line);
824 }
825 }
826}
827
828
829#ifdef CONFIG_SERIAL_SB1250_DUART_CONSOLE
830/*
831 * Serial console stuff. Very basic, polling driver for doing serial
832 * console output. The console_sem is held by the caller, so we
833 * shouldn't be interrupted for more console activity.
834 */
835static void sbd_console_putchar(struct uart_port *uport, int ch)
836{
837 struct sbd_port *sport = to_sport(uport);
838
839 sbd_transmit_drain(sport);
840 write_sbdchn(sport, R_DUART_TX_HOLD, ch);
841}
842
843static void sbd_console_write(struct console *co, const char *s,
844 unsigned int count)
845{
846 int chip = co->index / DUART_MAX_SIDE;
847 int side = co->index % DUART_MAX_SIDE;
848 struct sbd_port *sport = &sbd_duarts[chip].sport[side];
849 struct uart_port *uport = &sport->port;
850 unsigned long flags;
851 unsigned int mask;
852
853 /* Disable transmit interrupts and enable the transmitter. */
854 spin_lock_irqsave(&uport->lock, flags);
855 mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2));
856 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2),
857 mask & ~M_DUART_IMR_TX);
858 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_EN);
859 spin_unlock_irqrestore(&uport->lock, flags);
860
861 uart_console_write(&sport->port, s, count, sbd_console_putchar);
862
863 /* Restore transmit interrupts and the transmitter enable. */
864 spin_lock_irqsave(&uport->lock, flags);
865 sbd_line_drain(sport);
866 if (sport->tx_stopped)
867 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS);
868 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask);
869 spin_unlock_irqrestore(&uport->lock, flags);
870}
871
872static int __init sbd_console_setup(struct console *co, char *options)
873{
874 int chip = co->index / DUART_MAX_SIDE;
875 int side = co->index % DUART_MAX_SIDE;
876 struct sbd_port *sport = &sbd_duarts[chip].sport[side];
877 struct uart_port *uport = &sport->port;
878 int baud = 115200;
879 int bits = 8;
880 int parity = 'n';
881 int flow = 'n';
882 int ret;
883
884 if (!sport->duart)
885 return -ENXIO;
886
887 ret = sbd_map_port(uport);
888 if (ret)
889 return ret;
890
891 sbd_init_port(sport);
892
893 if (options)
894 uart_parse_options(options, &baud, &parity, &bits, &flow);
895 return uart_set_options(uport, co, baud, parity, bits, flow);
896}
897
898static struct uart_driver sbd_reg;
899static struct console sbd_console = {
900 .name = "duart",
901 .write = sbd_console_write,
902 .device = uart_console_device,
903 .setup = sbd_console_setup,
904 .flags = CON_PRINTBUFFER,
905 .index = -1,
906 .data = &sbd_reg
907};
908
909static int __init sbd_serial_console_init(void)
910{
911 sbd_probe_duarts();
912 register_console(&sbd_console);
913
914 return 0;
915}
916
917console_initcall(sbd_serial_console_init);
918
919#define SERIAL_SB1250_DUART_CONSOLE &sbd_console
920#else
921#define SERIAL_SB1250_DUART_CONSOLE NULL
922#endif /* CONFIG_SERIAL_SB1250_DUART_CONSOLE */
923
924
925static struct uart_driver sbd_reg = {
926 .owner = THIS_MODULE,
927 .driver_name = "sb1250_duart",
928 .dev_name = "duart",
929 .major = TTY_MAJOR,
930 .minor = SB1250_DUART_MINOR_BASE,
931 .nr = DUART_MAX_CHIP * DUART_MAX_SIDE,
932 .cons = SERIAL_SB1250_DUART_CONSOLE,
933};
934
935/* Set up the driver and register it. */
936static int __init sbd_init(void)
937{
938 int i, ret;
939
940 sbd_probe_duarts();
941
942 ret = uart_register_driver(&sbd_reg);
943 if (ret)
944 return ret;
945
946 for (i = 0; i < DUART_MAX_CHIP * DUART_MAX_SIDE; i++) {
947 struct sbd_duart *duart = &sbd_duarts[i / DUART_MAX_SIDE];
948 struct sbd_port *sport = &duart->sport[i % DUART_MAX_SIDE];
949 struct uart_port *uport = &sport->port;
950
951 if (sport->duart)
952 uart_add_one_port(&sbd_reg, uport);
953 }
954
955 return 0;
956}
957
958/* Unload the driver. Unregister stuff, get ready to go away. */
959static void __exit sbd_exit(void)
960{
961 int i;
962
963 for (i = DUART_MAX_CHIP * DUART_MAX_SIDE - 1; i >= 0; i--) {
964 struct sbd_duart *duart = &sbd_duarts[i / DUART_MAX_SIDE];
965 struct sbd_port *sport = &duart->sport[i % DUART_MAX_SIDE];
966 struct uart_port *uport = &sport->port;
967
968 if (sport->duart)
969 uart_remove_one_port(&sbd_reg, uport);
970 }
971
972 uart_unregister_driver(&sbd_reg);
973}
974
975module_init(sbd_init);
976module_exit(sbd_exit);
diff --git a/drivers/serial/sc26xx.c b/drivers/serial/sc26xx.c
deleted file mode 100644
index 75038ad2b242..000000000000
--- a/drivers/serial/sc26xx.c
+++ /dev/null
@@ -1,757 +0,0 @@
1/*
2 * SC268xx.c: Serial driver for Philiphs SC2681/SC2692 devices.
3 *
4 * Copyright (C) 2006,2007 Thomas Bogendörfer (tsbogend@alpha.franken.de)
5 */
6
7#include <linux/module.h>
8#include <linux/kernel.h>
9#include <linux/errno.h>
10#include <linux/tty.h>
11#include <linux/tty_flip.h>
12#include <linux/major.h>
13#include <linux/circ_buf.h>
14#include <linux/serial.h>
15#include <linux/sysrq.h>
16#include <linux/console.h>
17#include <linux/spinlock.h>
18#include <linux/slab.h>
19#include <linux/delay.h>
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/irq.h>
23
24#if defined(CONFIG_MAGIC_SYSRQ)
25#define SUPPORT_SYSRQ
26#endif
27
28#include <linux/serial_core.h>
29
30#define SC26XX_MAJOR 204
31#define SC26XX_MINOR_START 205
32#define SC26XX_NR 2
33
34struct uart_sc26xx_port {
35 struct uart_port port[2];
36 u8 dsr_mask[2];
37 u8 cts_mask[2];
38 u8 dcd_mask[2];
39 u8 ri_mask[2];
40 u8 dtr_mask[2];
41 u8 rts_mask[2];
42 u8 imr;
43};
44
45/* register common to both ports */
46#define RD_ISR 0x14
47#define RD_IPR 0x34
48
49#define WR_ACR 0x10
50#define WR_IMR 0x14
51#define WR_OPCR 0x34
52#define WR_OPR_SET 0x38
53#define WR_OPR_CLR 0x3C
54
55/* access common register */
56#define READ_SC(p, r) readb((p)->membase + RD_##r)
57#define WRITE_SC(p, r, v) writeb((v), (p)->membase + WR_##r)
58
59/* register per port */
60#define RD_PORT_MRx 0x00
61#define RD_PORT_SR 0x04
62#define RD_PORT_RHR 0x0c
63
64#define WR_PORT_MRx 0x00
65#define WR_PORT_CSR 0x04
66#define WR_PORT_CR 0x08
67#define WR_PORT_THR 0x0c
68
69/* SR bits */
70#define SR_BREAK (1 << 7)
71#define SR_FRAME (1 << 6)
72#define SR_PARITY (1 << 5)
73#define SR_OVERRUN (1 << 4)
74#define SR_TXRDY (1 << 2)
75#define SR_RXRDY (1 << 0)
76
77#define CR_RES_MR (1 << 4)
78#define CR_RES_RX (2 << 4)
79#define CR_RES_TX (3 << 4)
80#define CR_STRT_BRK (6 << 4)
81#define CR_STOP_BRK (7 << 4)
82#define CR_DIS_TX (1 << 3)
83#define CR_ENA_TX (1 << 2)
84#define CR_DIS_RX (1 << 1)
85#define CR_ENA_RX (1 << 0)
86
87/* ISR bits */
88#define ISR_RXRDYB (1 << 5)
89#define ISR_TXRDYB (1 << 4)
90#define ISR_RXRDYA (1 << 1)
91#define ISR_TXRDYA (1 << 0)
92
93/* IMR bits */
94#define IMR_RXRDY (1 << 1)
95#define IMR_TXRDY (1 << 0)
96
97/* access port register */
98static inline u8 read_sc_port(struct uart_port *p, u8 reg)
99{
100 return readb(p->membase + p->line * 0x20 + reg);
101}
102
103static inline void write_sc_port(struct uart_port *p, u8 reg, u8 val)
104{
105 writeb(val, p->membase + p->line * 0x20 + reg);
106}
107
108#define READ_SC_PORT(p, r) read_sc_port(p, RD_PORT_##r)
109#define WRITE_SC_PORT(p, r, v) write_sc_port(p, WR_PORT_##r, v)
110
111static void sc26xx_enable_irq(struct uart_port *port, int mask)
112{
113 struct uart_sc26xx_port *up;
114 int line = port->line;
115
116 port -= line;
117 up = container_of(port, struct uart_sc26xx_port, port[0]);
118
119 up->imr |= mask << (line * 4);
120 WRITE_SC(port, IMR, up->imr);
121}
122
123static void sc26xx_disable_irq(struct uart_port *port, int mask)
124{
125 struct uart_sc26xx_port *up;
126 int line = port->line;
127
128 port -= line;
129 up = container_of(port, struct uart_sc26xx_port, port[0]);
130
131 up->imr &= ~(mask << (line * 4));
132 WRITE_SC(port, IMR, up->imr);
133}
134
135static struct tty_struct *receive_chars(struct uart_port *port)
136{
137 struct tty_struct *tty = NULL;
138 int limit = 10000;
139 unsigned char ch;
140 char flag;
141 u8 status;
142
143 if (port->state != NULL) /* Unopened serial console */
144 tty = port->state->port.tty;
145
146 while (limit-- > 0) {
147 status = READ_SC_PORT(port, SR);
148 if (!(status & SR_RXRDY))
149 break;
150 ch = READ_SC_PORT(port, RHR);
151
152 flag = TTY_NORMAL;
153 port->icount.rx++;
154
155 if (unlikely(status & (SR_BREAK | SR_FRAME |
156 SR_PARITY | SR_OVERRUN))) {
157 if (status & SR_BREAK) {
158 status &= ~(SR_PARITY | SR_FRAME);
159 port->icount.brk++;
160 if (uart_handle_break(port))
161 continue;
162 } else if (status & SR_PARITY)
163 port->icount.parity++;
164 else if (status & SR_FRAME)
165 port->icount.frame++;
166 if (status & SR_OVERRUN)
167 port->icount.overrun++;
168
169 status &= port->read_status_mask;
170 if (status & SR_BREAK)
171 flag = TTY_BREAK;
172 else if (status & SR_PARITY)
173 flag = TTY_PARITY;
174 else if (status & SR_FRAME)
175 flag = TTY_FRAME;
176 }
177
178 if (uart_handle_sysrq_char(port, ch))
179 continue;
180
181 if (status & port->ignore_status_mask)
182 continue;
183
184 tty_insert_flip_char(tty, ch, flag);
185 }
186 return tty;
187}
188
189static void transmit_chars(struct uart_port *port)
190{
191 struct circ_buf *xmit;
192
193 if (!port->state)
194 return;
195
196 xmit = &port->state->xmit;
197 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
198 sc26xx_disable_irq(port, IMR_TXRDY);
199 return;
200 }
201 while (!uart_circ_empty(xmit)) {
202 if (!(READ_SC_PORT(port, SR) & SR_TXRDY))
203 break;
204
205 WRITE_SC_PORT(port, THR, xmit->buf[xmit->tail]);
206 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
207 port->icount.tx++;
208 }
209 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
210 uart_write_wakeup(port);
211}
212
213static irqreturn_t sc26xx_interrupt(int irq, void *dev_id)
214{
215 struct uart_sc26xx_port *up = dev_id;
216 struct tty_struct *tty;
217 unsigned long flags;
218 u8 isr;
219
220 spin_lock_irqsave(&up->port[0].lock, flags);
221
222 tty = NULL;
223 isr = READ_SC(&up->port[0], ISR);
224 if (isr & ISR_TXRDYA)
225 transmit_chars(&up->port[0]);
226 if (isr & ISR_RXRDYA)
227 tty = receive_chars(&up->port[0]);
228
229 spin_unlock(&up->port[0].lock);
230
231 if (tty)
232 tty_flip_buffer_push(tty);
233
234 spin_lock(&up->port[1].lock);
235
236 tty = NULL;
237 if (isr & ISR_TXRDYB)
238 transmit_chars(&up->port[1]);
239 if (isr & ISR_RXRDYB)
240 tty = receive_chars(&up->port[1]);
241
242 spin_unlock_irqrestore(&up->port[1].lock, flags);
243
244 if (tty)
245 tty_flip_buffer_push(tty);
246
247 return IRQ_HANDLED;
248}
249
250/* port->lock is not held. */
251static unsigned int sc26xx_tx_empty(struct uart_port *port)
252{
253 return (READ_SC_PORT(port, SR) & SR_TXRDY) ? TIOCSER_TEMT : 0;
254}
255
256/* port->lock held by caller. */
257static void sc26xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
258{
259 struct uart_sc26xx_port *up;
260 int line = port->line;
261
262 port -= line;
263 up = container_of(port, struct uart_sc26xx_port, port[0]);
264
265 if (up->dtr_mask[line]) {
266 if (mctrl & TIOCM_DTR)
267 WRITE_SC(port, OPR_SET, up->dtr_mask[line]);
268 else
269 WRITE_SC(port, OPR_CLR, up->dtr_mask[line]);
270 }
271 if (up->rts_mask[line]) {
272 if (mctrl & TIOCM_RTS)
273 WRITE_SC(port, OPR_SET, up->rts_mask[line]);
274 else
275 WRITE_SC(port, OPR_CLR, up->rts_mask[line]);
276 }
277}
278
279/* port->lock is held by caller and interrupts are disabled. */
280static unsigned int sc26xx_get_mctrl(struct uart_port *port)
281{
282 struct uart_sc26xx_port *up;
283 int line = port->line;
284 unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR;
285 u8 ipr;
286
287 port -= line;
288 up = container_of(port, struct uart_sc26xx_port, port[0]);
289 ipr = READ_SC(port, IPR) ^ 0xff;
290
291 if (up->dsr_mask[line]) {
292 mctrl &= ~TIOCM_DSR;
293 mctrl |= ipr & up->dsr_mask[line] ? TIOCM_DSR : 0;
294 }
295 if (up->cts_mask[line]) {
296 mctrl &= ~TIOCM_CTS;
297 mctrl |= ipr & up->cts_mask[line] ? TIOCM_CTS : 0;
298 }
299 if (up->dcd_mask[line]) {
300 mctrl &= ~TIOCM_CAR;
301 mctrl |= ipr & up->dcd_mask[line] ? TIOCM_CAR : 0;
302 }
303 if (up->ri_mask[line]) {
304 mctrl &= ~TIOCM_RNG;
305 mctrl |= ipr & up->ri_mask[line] ? TIOCM_RNG : 0;
306 }
307 return mctrl;
308}
309
310/* port->lock held by caller. */
311static void sc26xx_stop_tx(struct uart_port *port)
312{
313 return;
314}
315
316/* port->lock held by caller. */
317static void sc26xx_start_tx(struct uart_port *port)
318{
319 struct circ_buf *xmit = &port->state->xmit;
320
321 while (!uart_circ_empty(xmit)) {
322 if (!(READ_SC_PORT(port, SR) & SR_TXRDY)) {
323 sc26xx_enable_irq(port, IMR_TXRDY);
324 break;
325 }
326 WRITE_SC_PORT(port, THR, xmit->buf[xmit->tail]);
327 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
328 port->icount.tx++;
329 }
330}
331
332/* port->lock held by caller. */
333static void sc26xx_stop_rx(struct uart_port *port)
334{
335}
336
337/* port->lock held by caller. */
338static void sc26xx_enable_ms(struct uart_port *port)
339{
340}
341
342/* port->lock is not held. */
343static void sc26xx_break_ctl(struct uart_port *port, int break_state)
344{
345 if (break_state == -1)
346 WRITE_SC_PORT(port, CR, CR_STRT_BRK);
347 else
348 WRITE_SC_PORT(port, CR, CR_STOP_BRK);
349}
350
351/* port->lock is not held. */
352static int sc26xx_startup(struct uart_port *port)
353{
354 sc26xx_disable_irq(port, IMR_TXRDY | IMR_RXRDY);
355 WRITE_SC(port, OPCR, 0);
356
357 /* reset tx and rx */
358 WRITE_SC_PORT(port, CR, CR_RES_RX);
359 WRITE_SC_PORT(port, CR, CR_RES_TX);
360
361 /* start rx/tx */
362 WRITE_SC_PORT(port, CR, CR_ENA_TX | CR_ENA_RX);
363
364 /* enable irqs */
365 sc26xx_enable_irq(port, IMR_RXRDY);
366 return 0;
367}
368
369/* port->lock is not held. */
370static void sc26xx_shutdown(struct uart_port *port)
371{
372 /* disable interrupst */
373 sc26xx_disable_irq(port, IMR_TXRDY | IMR_RXRDY);
374
375 /* stop tx/rx */
376 WRITE_SC_PORT(port, CR, CR_DIS_TX | CR_DIS_RX);
377}
378
379/* port->lock is not held. */
380static void sc26xx_set_termios(struct uart_port *port, struct ktermios *termios,
381 struct ktermios *old)
382{
383 unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
384 unsigned int quot = uart_get_divisor(port, baud);
385 unsigned int iflag, cflag;
386 unsigned long flags;
387 u8 mr1, mr2, csr;
388
389 spin_lock_irqsave(&port->lock, flags);
390
391 while ((READ_SC_PORT(port, SR) & ((1 << 3) | (1 << 2))) != 0xc)
392 udelay(2);
393
394 WRITE_SC_PORT(port, CR, CR_DIS_TX | CR_DIS_RX);
395
396 iflag = termios->c_iflag;
397 cflag = termios->c_cflag;
398
399 port->read_status_mask = SR_OVERRUN;
400 if (iflag & INPCK)
401 port->read_status_mask |= SR_PARITY | SR_FRAME;
402 if (iflag & (BRKINT | PARMRK))
403 port->read_status_mask |= SR_BREAK;
404
405 port->ignore_status_mask = 0;
406 if (iflag & IGNBRK)
407 port->ignore_status_mask |= SR_BREAK;
408 if ((cflag & CREAD) == 0)
409 port->ignore_status_mask |= SR_BREAK | SR_FRAME |
410 SR_PARITY | SR_OVERRUN;
411
412 switch (cflag & CSIZE) {
413 case CS5:
414 mr1 = 0x00;
415 break;
416 case CS6:
417 mr1 = 0x01;
418 break;
419 case CS7:
420 mr1 = 0x02;
421 break;
422 default:
423 case CS8:
424 mr1 = 0x03;
425 break;
426 }
427 mr2 = 0x07;
428 if (cflag & CSTOPB)
429 mr2 = 0x0f;
430 if (cflag & PARENB) {
431 if (cflag & PARODD)
432 mr1 |= (1 << 2);
433 } else
434 mr1 |= (2 << 3);
435
436 switch (baud) {
437 case 50:
438 csr = 0x00;
439 break;
440 case 110:
441 csr = 0x11;
442 break;
443 case 134:
444 csr = 0x22;
445 break;
446 case 200:
447 csr = 0x33;
448 break;
449 case 300:
450 csr = 0x44;
451 break;
452 case 600:
453 csr = 0x55;
454 break;
455 case 1200:
456 csr = 0x66;
457 break;
458 case 2400:
459 csr = 0x88;
460 break;
461 case 4800:
462 csr = 0x99;
463 break;
464 default:
465 case 9600:
466 csr = 0xbb;
467 break;
468 case 19200:
469 csr = 0xcc;
470 break;
471 }
472
473 WRITE_SC_PORT(port, CR, CR_RES_MR);
474 WRITE_SC_PORT(port, MRx, mr1);
475 WRITE_SC_PORT(port, MRx, mr2);
476
477 WRITE_SC(port, ACR, 0x80);
478 WRITE_SC_PORT(port, CSR, csr);
479
480 /* reset tx and rx */
481 WRITE_SC_PORT(port, CR, CR_RES_RX);
482 WRITE_SC_PORT(port, CR, CR_RES_TX);
483
484 WRITE_SC_PORT(port, CR, CR_ENA_TX | CR_ENA_RX);
485 while ((READ_SC_PORT(port, SR) & ((1 << 3) | (1 << 2))) != 0xc)
486 udelay(2);
487
488 /* XXX */
489 uart_update_timeout(port, cflag,
490 (port->uartclk / (16 * quot)));
491
492 spin_unlock_irqrestore(&port->lock, flags);
493}
494
495static const char *sc26xx_type(struct uart_port *port)
496{
497 return "SC26XX";
498}
499
500static void sc26xx_release_port(struct uart_port *port)
501{
502}
503
504static int sc26xx_request_port(struct uart_port *port)
505{
506 return 0;
507}
508
509static void sc26xx_config_port(struct uart_port *port, int flags)
510{
511}
512
513static int sc26xx_verify_port(struct uart_port *port, struct serial_struct *ser)
514{
515 return -EINVAL;
516}
517
518static struct uart_ops sc26xx_ops = {
519 .tx_empty = sc26xx_tx_empty,
520 .set_mctrl = sc26xx_set_mctrl,
521 .get_mctrl = sc26xx_get_mctrl,
522 .stop_tx = sc26xx_stop_tx,
523 .start_tx = sc26xx_start_tx,
524 .stop_rx = sc26xx_stop_rx,
525 .enable_ms = sc26xx_enable_ms,
526 .break_ctl = sc26xx_break_ctl,
527 .startup = sc26xx_startup,
528 .shutdown = sc26xx_shutdown,
529 .set_termios = sc26xx_set_termios,
530 .type = sc26xx_type,
531 .release_port = sc26xx_release_port,
532 .request_port = sc26xx_request_port,
533 .config_port = sc26xx_config_port,
534 .verify_port = sc26xx_verify_port,
535};
536
537static struct uart_port *sc26xx_port;
538
539#ifdef CONFIG_SERIAL_SC26XX_CONSOLE
540static void sc26xx_console_putchar(struct uart_port *port, char c)
541{
542 unsigned long flags;
543 int limit = 1000000;
544
545 spin_lock_irqsave(&port->lock, flags);
546
547 while (limit-- > 0) {
548 if (READ_SC_PORT(port, SR) & SR_TXRDY) {
549 WRITE_SC_PORT(port, THR, c);
550 break;
551 }
552 udelay(2);
553 }
554
555 spin_unlock_irqrestore(&port->lock, flags);
556}
557
558static void sc26xx_console_write(struct console *con, const char *s, unsigned n)
559{
560 struct uart_port *port = sc26xx_port;
561 int i;
562
563 for (i = 0; i < n; i++) {
564 if (*s == '\n')
565 sc26xx_console_putchar(port, '\r');
566 sc26xx_console_putchar(port, *s++);
567 }
568}
569
570static int __init sc26xx_console_setup(struct console *con, char *options)
571{
572 struct uart_port *port = sc26xx_port;
573 int baud = 9600;
574 int bits = 8;
575 int parity = 'n';
576 int flow = 'n';
577
578 if (port->type != PORT_SC26XX)
579 return -1;
580
581 printk(KERN_INFO "Console: ttySC%d (SC26XX)\n", con->index);
582 if (options)
583 uart_parse_options(options, &baud, &parity, &bits, &flow);
584
585 return uart_set_options(port, con, baud, parity, bits, flow);
586}
587
588static struct uart_driver sc26xx_reg;
589static struct console sc26xx_console = {
590 .name = "ttySC",
591 .write = sc26xx_console_write,
592 .device = uart_console_device,
593 .setup = sc26xx_console_setup,
594 .flags = CON_PRINTBUFFER,
595 .index = -1,
596 .data = &sc26xx_reg,
597};
598#define SC26XX_CONSOLE &sc26xx_console
599#else
600#define SC26XX_CONSOLE NULL
601#endif
602
603static struct uart_driver sc26xx_reg = {
604 .owner = THIS_MODULE,
605 .driver_name = "SC26xx",
606 .dev_name = "ttySC",
607 .major = SC26XX_MAJOR,
608 .minor = SC26XX_MINOR_START,
609 .nr = SC26XX_NR,
610 .cons = SC26XX_CONSOLE,
611};
612
613static u8 sc26xx_flags2mask(unsigned int flags, unsigned int bitpos)
614{
615 unsigned int bit = (flags >> bitpos) & 15;
616
617 return bit ? (1 << (bit - 1)) : 0;
618}
619
620static void __devinit sc26xx_init_masks(struct uart_sc26xx_port *up,
621 int line, unsigned int data)
622{
623 up->dtr_mask[line] = sc26xx_flags2mask(data, 0);
624 up->rts_mask[line] = sc26xx_flags2mask(data, 4);
625 up->dsr_mask[line] = sc26xx_flags2mask(data, 8);
626 up->cts_mask[line] = sc26xx_flags2mask(data, 12);
627 up->dcd_mask[line] = sc26xx_flags2mask(data, 16);
628 up->ri_mask[line] = sc26xx_flags2mask(data, 20);
629}
630
631static int __devinit sc26xx_probe(struct platform_device *dev)
632{
633 struct resource *res;
634 struct uart_sc26xx_port *up;
635 unsigned int *sc26xx_data = dev->dev.platform_data;
636 int err;
637
638 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
639 if (!res)
640 return -ENODEV;
641
642 up = kzalloc(sizeof *up, GFP_KERNEL);
643 if (unlikely(!up))
644 return -ENOMEM;
645
646 up->port[0].line = 0;
647 up->port[0].ops = &sc26xx_ops;
648 up->port[0].type = PORT_SC26XX;
649 up->port[0].uartclk = (29491200 / 16); /* arbitrary */
650
651 up->port[0].mapbase = res->start;
652 up->port[0].membase = ioremap_nocache(up->port[0].mapbase, 0x40);
653 up->port[0].iotype = UPIO_MEM;
654 up->port[0].irq = platform_get_irq(dev, 0);
655
656 up->port[0].dev = &dev->dev;
657
658 sc26xx_init_masks(up, 0, sc26xx_data[0]);
659
660 sc26xx_port = &up->port[0];
661
662 up->port[1].line = 1;
663 up->port[1].ops = &sc26xx_ops;
664 up->port[1].type = PORT_SC26XX;
665 up->port[1].uartclk = (29491200 / 16); /* arbitrary */
666
667 up->port[1].mapbase = up->port[0].mapbase;
668 up->port[1].membase = up->port[0].membase;
669 up->port[1].iotype = UPIO_MEM;
670 up->port[1].irq = up->port[0].irq;
671
672 up->port[1].dev = &dev->dev;
673
674 sc26xx_init_masks(up, 1, sc26xx_data[1]);
675
676 err = uart_register_driver(&sc26xx_reg);
677 if (err)
678 goto out_free_port;
679
680 sc26xx_reg.tty_driver->name_base = sc26xx_reg.minor;
681
682 err = uart_add_one_port(&sc26xx_reg, &up->port[0]);
683 if (err)
684 goto out_unregister_driver;
685
686 err = uart_add_one_port(&sc26xx_reg, &up->port[1]);
687 if (err)
688 goto out_remove_port0;
689
690 err = request_irq(up->port[0].irq, sc26xx_interrupt, 0, "sc26xx", up);
691 if (err)
692 goto out_remove_ports;
693
694 dev_set_drvdata(&dev->dev, up);
695 return 0;
696
697out_remove_ports:
698 uart_remove_one_port(&sc26xx_reg, &up->port[1]);
699out_remove_port0:
700 uart_remove_one_port(&sc26xx_reg, &up->port[0]);
701
702out_unregister_driver:
703 uart_unregister_driver(&sc26xx_reg);
704
705out_free_port:
706 kfree(up);
707 sc26xx_port = NULL;
708 return err;
709}
710
711
712static int __exit sc26xx_driver_remove(struct platform_device *dev)
713{
714 struct uart_sc26xx_port *up = dev_get_drvdata(&dev->dev);
715
716 free_irq(up->port[0].irq, up);
717
718 uart_remove_one_port(&sc26xx_reg, &up->port[0]);
719 uart_remove_one_port(&sc26xx_reg, &up->port[1]);
720
721 uart_unregister_driver(&sc26xx_reg);
722
723 kfree(up);
724 sc26xx_port = NULL;
725
726 dev_set_drvdata(&dev->dev, NULL);
727 return 0;
728}
729
730static struct platform_driver sc26xx_driver = {
731 .probe = sc26xx_probe,
732 .remove = __devexit_p(sc26xx_driver_remove),
733 .driver = {
734 .name = "SC26xx",
735 .owner = THIS_MODULE,
736 },
737};
738
739static int __init sc26xx_init(void)
740{
741 return platform_driver_register(&sc26xx_driver);
742}
743
744static void __exit sc26xx_exit(void)
745{
746 platform_driver_unregister(&sc26xx_driver);
747}
748
749module_init(sc26xx_init);
750module_exit(sc26xx_exit);
751
752
753MODULE_AUTHOR("Thomas Bogendörfer");
754MODULE_DESCRIPTION("SC681/SC2692 serial driver");
755MODULE_VERSION("1.0");
756MODULE_LICENSE("GPL");
757MODULE_ALIAS("platform:SC26xx");
diff --git a/drivers/serial/serial_core.c b/drivers/serial/serial_core.c
deleted file mode 100644
index cd8511298bcb..000000000000
--- a/drivers/serial/serial_core.c
+++ /dev/null
@@ -1,2564 +0,0 @@
1/*
2 * linux/drivers/char/core.c
3 *
4 * Driver core for serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright 1999 ARM Limited
9 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25#include <linux/module.h>
26#include <linux/tty.h>
27#include <linux/slab.h>
28#include <linux/init.h>
29#include <linux/console.h>
30#include <linux/proc_fs.h>
31#include <linux/seq_file.h>
32#include <linux/smp_lock.h>
33#include <linux/device.h>
34#include <linux/serial.h> /* for serial_state and serial_icounter_struct */
35#include <linux/serial_core.h>
36#include <linux/delay.h>
37#include <linux/mutex.h>
38
39#include <asm/irq.h>
40#include <asm/uaccess.h>
41
42/*
43 * This is used to lock changes in serial line configuration.
44 */
45static DEFINE_MUTEX(port_mutex);
46
47/*
48 * lockdep: port->lock is initialized in two places, but we
49 * want only one lock-class:
50 */
51static struct lock_class_key port_lock_key;
52
53#define HIGH_BITS_OFFSET ((sizeof(long)-sizeof(int))*8)
54
55#ifdef CONFIG_SERIAL_CORE_CONSOLE
56#define uart_console(port) ((port)->cons && (port)->cons->index == (port)->line)
57#else
58#define uart_console(port) (0)
59#endif
60
61static void uart_change_speed(struct tty_struct *tty, struct uart_state *state,
62 struct ktermios *old_termios);
63static void __uart_wait_until_sent(struct uart_port *port, int timeout);
64static void uart_change_pm(struct uart_state *state, int pm_state);
65
66/*
67 * This routine is used by the interrupt handler to schedule processing in
68 * the software interrupt portion of the driver.
69 */
70void uart_write_wakeup(struct uart_port *port)
71{
72 struct uart_state *state = port->state;
73 /*
74 * This means you called this function _after_ the port was
75 * closed. No cookie for you.
76 */
77 BUG_ON(!state);
78 tasklet_schedule(&state->tlet);
79}
80
81static void uart_stop(struct tty_struct *tty)
82{
83 struct uart_state *state = tty->driver_data;
84 struct uart_port *port = state->uart_port;
85 unsigned long flags;
86
87 spin_lock_irqsave(&port->lock, flags);
88 port->ops->stop_tx(port);
89 spin_unlock_irqrestore(&port->lock, flags);
90}
91
92static void __uart_start(struct tty_struct *tty)
93{
94 struct uart_state *state = tty->driver_data;
95 struct uart_port *port = state->uart_port;
96
97 if (!uart_circ_empty(&state->xmit) && state->xmit.buf &&
98 !tty->stopped && !tty->hw_stopped)
99 port->ops->start_tx(port);
100}
101
102static void uart_start(struct tty_struct *tty)
103{
104 struct uart_state *state = tty->driver_data;
105 struct uart_port *port = state->uart_port;
106 unsigned long flags;
107
108 spin_lock_irqsave(&port->lock, flags);
109 __uart_start(tty);
110 spin_unlock_irqrestore(&port->lock, flags);
111}
112
113static void uart_tasklet_action(unsigned long data)
114{
115 struct uart_state *state = (struct uart_state *)data;
116 tty_wakeup(state->port.tty);
117}
118
119static inline void
120uart_update_mctrl(struct uart_port *port, unsigned int set, unsigned int clear)
121{
122 unsigned long flags;
123 unsigned int old;
124
125 spin_lock_irqsave(&port->lock, flags);
126 old = port->mctrl;
127 port->mctrl = (old & ~clear) | set;
128 if (old != port->mctrl)
129 port->ops->set_mctrl(port, port->mctrl);
130 spin_unlock_irqrestore(&port->lock, flags);
131}
132
133#define uart_set_mctrl(port, set) uart_update_mctrl(port, set, 0)
134#define uart_clear_mctrl(port, clear) uart_update_mctrl(port, 0, clear)
135
136/*
137 * Startup the port. This will be called once per open. All calls
138 * will be serialised by the per-port mutex.
139 */
140static int uart_startup(struct tty_struct *tty, struct uart_state *state, int init_hw)
141{
142 struct uart_port *uport = state->uart_port;
143 struct tty_port *port = &state->port;
144 unsigned long page;
145 int retval = 0;
146
147 if (port->flags & ASYNC_INITIALIZED)
148 return 0;
149
150 /*
151 * Set the TTY IO error marker - we will only clear this
152 * once we have successfully opened the port. Also set
153 * up the tty->alt_speed kludge
154 */
155 set_bit(TTY_IO_ERROR, &tty->flags);
156
157 if (uport->type == PORT_UNKNOWN)
158 return 0;
159
160 /*
161 * Initialise and allocate the transmit and temporary
162 * buffer.
163 */
164 if (!state->xmit.buf) {
165 /* This is protected by the per port mutex */
166 page = get_zeroed_page(GFP_KERNEL);
167 if (!page)
168 return -ENOMEM;
169
170 state->xmit.buf = (unsigned char *) page;
171 uart_circ_clear(&state->xmit);
172 }
173
174 retval = uport->ops->startup(uport);
175 if (retval == 0) {
176 if (init_hw) {
177 /*
178 * Initialise the hardware port settings.
179 */
180 uart_change_speed(tty, state, NULL);
181
182 /*
183 * Setup the RTS and DTR signals once the
184 * port is open and ready to respond.
185 */
186 if (tty->termios->c_cflag & CBAUD)
187 uart_set_mctrl(uport, TIOCM_RTS | TIOCM_DTR);
188 }
189
190 if (port->flags & ASYNC_CTS_FLOW) {
191 spin_lock_irq(&uport->lock);
192 if (!(uport->ops->get_mctrl(uport) & TIOCM_CTS))
193 tty->hw_stopped = 1;
194 spin_unlock_irq(&uport->lock);
195 }
196
197 set_bit(ASYNCB_INITIALIZED, &port->flags);
198
199 clear_bit(TTY_IO_ERROR, &tty->flags);
200 }
201
202 if (retval && capable(CAP_SYS_ADMIN))
203 retval = 0;
204
205 return retval;
206}
207
208/*
209 * This routine will shutdown a serial port; interrupts are disabled, and
210 * DTR is dropped if the hangup on close termio flag is on. Calls to
211 * uart_shutdown are serialised by the per-port semaphore.
212 */
213static void uart_shutdown(struct tty_struct *tty, struct uart_state *state)
214{
215 struct uart_port *uport = state->uart_port;
216 struct tty_port *port = &state->port;
217
218 /*
219 * Set the TTY IO error marker
220 */
221 if (tty)
222 set_bit(TTY_IO_ERROR, &tty->flags);
223
224 if (test_and_clear_bit(ASYNCB_INITIALIZED, &port->flags)) {
225 /*
226 * Turn off DTR and RTS early.
227 */
228 if (!tty || (tty->termios->c_cflag & HUPCL))
229 uart_clear_mctrl(uport, TIOCM_DTR | TIOCM_RTS);
230
231 /*
232 * clear delta_msr_wait queue to avoid mem leaks: we may free
233 * the irq here so the queue might never be woken up. Note
234 * that we won't end up waiting on delta_msr_wait again since
235 * any outstanding file descriptors should be pointing at
236 * hung_up_tty_fops now.
237 */
238 wake_up_interruptible(&port->delta_msr_wait);
239
240 /*
241 * Free the IRQ and disable the port.
242 */
243 uport->ops->shutdown(uport);
244
245 /*
246 * Ensure that the IRQ handler isn't running on another CPU.
247 */
248 synchronize_irq(uport->irq);
249 }
250
251 /*
252 * kill off our tasklet
253 */
254 tasklet_kill(&state->tlet);
255
256 /*
257 * Free the transmit buffer page.
258 */
259 if (state->xmit.buf) {
260 free_page((unsigned long)state->xmit.buf);
261 state->xmit.buf = NULL;
262 }
263}
264
265/**
266 * uart_update_timeout - update per-port FIFO timeout.
267 * @port: uart_port structure describing the port
268 * @cflag: termios cflag value
269 * @baud: speed of the port
270 *
271 * Set the port FIFO timeout value. The @cflag value should
272 * reflect the actual hardware settings.
273 */
274void
275uart_update_timeout(struct uart_port *port, unsigned int cflag,
276 unsigned int baud)
277{
278 unsigned int bits;
279
280 /* byte size and parity */
281 switch (cflag & CSIZE) {
282 case CS5:
283 bits = 7;
284 break;
285 case CS6:
286 bits = 8;
287 break;
288 case CS7:
289 bits = 9;
290 break;
291 default:
292 bits = 10;
293 break; /* CS8 */
294 }
295
296 if (cflag & CSTOPB)
297 bits++;
298 if (cflag & PARENB)
299 bits++;
300
301 /*
302 * The total number of bits to be transmitted in the fifo.
303 */
304 bits = bits * port->fifosize;
305
306 /*
307 * Figure the timeout to send the above number of bits.
308 * Add .02 seconds of slop
309 */
310 port->timeout = (HZ * bits) / baud + HZ/50;
311}
312
313EXPORT_SYMBOL(uart_update_timeout);
314
315/**
316 * uart_get_baud_rate - return baud rate for a particular port
317 * @port: uart_port structure describing the port in question.
318 * @termios: desired termios settings.
319 * @old: old termios (or NULL)
320 * @min: minimum acceptable baud rate
321 * @max: maximum acceptable baud rate
322 *
323 * Decode the termios structure into a numeric baud rate,
324 * taking account of the magic 38400 baud rate (with spd_*
325 * flags), and mapping the %B0 rate to 9600 baud.
326 *
327 * If the new baud rate is invalid, try the old termios setting.
328 * If it's still invalid, we try 9600 baud.
329 *
330 * Update the @termios structure to reflect the baud rate
331 * we're actually going to be using. Don't do this for the case
332 * where B0 is requested ("hang up").
333 */
334unsigned int
335uart_get_baud_rate(struct uart_port *port, struct ktermios *termios,
336 struct ktermios *old, unsigned int min, unsigned int max)
337{
338 unsigned int try, baud, altbaud = 38400;
339 int hung_up = 0;
340 upf_t flags = port->flags & UPF_SPD_MASK;
341
342 if (flags == UPF_SPD_HI)
343 altbaud = 57600;
344 else if (flags == UPF_SPD_VHI)
345 altbaud = 115200;
346 else if (flags == UPF_SPD_SHI)
347 altbaud = 230400;
348 else if (flags == UPF_SPD_WARP)
349 altbaud = 460800;
350
351 for (try = 0; try < 2; try++) {
352 baud = tty_termios_baud_rate(termios);
353
354 /*
355 * The spd_hi, spd_vhi, spd_shi, spd_warp kludge...
356 * Die! Die! Die!
357 */
358 if (baud == 38400)
359 baud = altbaud;
360
361 /*
362 * Special case: B0 rate.
363 */
364 if (baud == 0) {
365 hung_up = 1;
366 baud = 9600;
367 }
368
369 if (baud >= min && baud <= max)
370 return baud;
371
372 /*
373 * Oops, the quotient was zero. Try again with
374 * the old baud rate if possible.
375 */
376 termios->c_cflag &= ~CBAUD;
377 if (old) {
378 baud = tty_termios_baud_rate(old);
379 if (!hung_up)
380 tty_termios_encode_baud_rate(termios,
381 baud, baud);
382 old = NULL;
383 continue;
384 }
385
386 /*
387 * As a last resort, if the range cannot be met then clip to
388 * the nearest chip supported rate.
389 */
390 if (!hung_up) {
391 if (baud <= min)
392 tty_termios_encode_baud_rate(termios,
393 min + 1, min + 1);
394 else
395 tty_termios_encode_baud_rate(termios,
396 max - 1, max - 1);
397 }
398 }
399 /* Should never happen */
400 WARN_ON(1);
401 return 0;
402}
403
404EXPORT_SYMBOL(uart_get_baud_rate);
405
406/**
407 * uart_get_divisor - return uart clock divisor
408 * @port: uart_port structure describing the port.
409 * @baud: desired baud rate
410 *
411 * Calculate the uart clock divisor for the port.
412 */
413unsigned int
414uart_get_divisor(struct uart_port *port, unsigned int baud)
415{
416 unsigned int quot;
417
418 /*
419 * Old custom speed handling.
420 */
421 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
422 quot = port->custom_divisor;
423 else
424 quot = (port->uartclk + (8 * baud)) / (16 * baud);
425
426 return quot;
427}
428
429EXPORT_SYMBOL(uart_get_divisor);
430
431/* FIXME: Consistent locking policy */
432static void uart_change_speed(struct tty_struct *tty, struct uart_state *state,
433 struct ktermios *old_termios)
434{
435 struct tty_port *port = &state->port;
436 struct uart_port *uport = state->uart_port;
437 struct ktermios *termios;
438
439 /*
440 * If we have no tty, termios, or the port does not exist,
441 * then we can't set the parameters for this port.
442 */
443 if (!tty || !tty->termios || uport->type == PORT_UNKNOWN)
444 return;
445
446 termios = tty->termios;
447
448 /*
449 * Set flags based on termios cflag
450 */
451 if (termios->c_cflag & CRTSCTS)
452 set_bit(ASYNCB_CTS_FLOW, &port->flags);
453 else
454 clear_bit(ASYNCB_CTS_FLOW, &port->flags);
455
456 if (termios->c_cflag & CLOCAL)
457 clear_bit(ASYNCB_CHECK_CD, &port->flags);
458 else
459 set_bit(ASYNCB_CHECK_CD, &port->flags);
460
461 uport->ops->set_termios(uport, termios, old_termios);
462}
463
464static inline int __uart_put_char(struct uart_port *port,
465 struct circ_buf *circ, unsigned char c)
466{
467 unsigned long flags;
468 int ret = 0;
469
470 if (!circ->buf)
471 return 0;
472
473 spin_lock_irqsave(&port->lock, flags);
474 if (uart_circ_chars_free(circ) != 0) {
475 circ->buf[circ->head] = c;
476 circ->head = (circ->head + 1) & (UART_XMIT_SIZE - 1);
477 ret = 1;
478 }
479 spin_unlock_irqrestore(&port->lock, flags);
480 return ret;
481}
482
483static int uart_put_char(struct tty_struct *tty, unsigned char ch)
484{
485 struct uart_state *state = tty->driver_data;
486
487 return __uart_put_char(state->uart_port, &state->xmit, ch);
488}
489
490static void uart_flush_chars(struct tty_struct *tty)
491{
492 uart_start(tty);
493}
494
495static int uart_write(struct tty_struct *tty,
496 const unsigned char *buf, int count)
497{
498 struct uart_state *state = tty->driver_data;
499 struct uart_port *port;
500 struct circ_buf *circ;
501 unsigned long flags;
502 int c, ret = 0;
503
504 /*
505 * This means you called this function _after_ the port was
506 * closed. No cookie for you.
507 */
508 if (!state) {
509 WARN_ON(1);
510 return -EL3HLT;
511 }
512
513 port = state->uart_port;
514 circ = &state->xmit;
515
516 if (!circ->buf)
517 return 0;
518
519 spin_lock_irqsave(&port->lock, flags);
520 while (1) {
521 c = CIRC_SPACE_TO_END(circ->head, circ->tail, UART_XMIT_SIZE);
522 if (count < c)
523 c = count;
524 if (c <= 0)
525 break;
526 memcpy(circ->buf + circ->head, buf, c);
527 circ->head = (circ->head + c) & (UART_XMIT_SIZE - 1);
528 buf += c;
529 count -= c;
530 ret += c;
531 }
532 spin_unlock_irqrestore(&port->lock, flags);
533
534 uart_start(tty);
535 return ret;
536}
537
538static int uart_write_room(struct tty_struct *tty)
539{
540 struct uart_state *state = tty->driver_data;
541 unsigned long flags;
542 int ret;
543
544 spin_lock_irqsave(&state->uart_port->lock, flags);
545 ret = uart_circ_chars_free(&state->xmit);
546 spin_unlock_irqrestore(&state->uart_port->lock, flags);
547 return ret;
548}
549
550static int uart_chars_in_buffer(struct tty_struct *tty)
551{
552 struct uart_state *state = tty->driver_data;
553 unsigned long flags;
554 int ret;
555
556 spin_lock_irqsave(&state->uart_port->lock, flags);
557 ret = uart_circ_chars_pending(&state->xmit);
558 spin_unlock_irqrestore(&state->uart_port->lock, flags);
559 return ret;
560}
561
562static void uart_flush_buffer(struct tty_struct *tty)
563{
564 struct uart_state *state = tty->driver_data;
565 struct uart_port *port;
566 unsigned long flags;
567
568 /*
569 * This means you called this function _after_ the port was
570 * closed. No cookie for you.
571 */
572 if (!state) {
573 WARN_ON(1);
574 return;
575 }
576
577 port = state->uart_port;
578 pr_debug("uart_flush_buffer(%d) called\n", tty->index);
579
580 spin_lock_irqsave(&port->lock, flags);
581 uart_circ_clear(&state->xmit);
582 if (port->ops->flush_buffer)
583 port->ops->flush_buffer(port);
584 spin_unlock_irqrestore(&port->lock, flags);
585 tty_wakeup(tty);
586}
587
588/*
589 * This function is used to send a high-priority XON/XOFF character to
590 * the device
591 */
592static void uart_send_xchar(struct tty_struct *tty, char ch)
593{
594 struct uart_state *state = tty->driver_data;
595 struct uart_port *port = state->uart_port;
596 unsigned long flags;
597
598 if (port->ops->send_xchar)
599 port->ops->send_xchar(port, ch);
600 else {
601 port->x_char = ch;
602 if (ch) {
603 spin_lock_irqsave(&port->lock, flags);
604 port->ops->start_tx(port);
605 spin_unlock_irqrestore(&port->lock, flags);
606 }
607 }
608}
609
610static void uart_throttle(struct tty_struct *tty)
611{
612 struct uart_state *state = tty->driver_data;
613
614 if (I_IXOFF(tty))
615 uart_send_xchar(tty, STOP_CHAR(tty));
616
617 if (tty->termios->c_cflag & CRTSCTS)
618 uart_clear_mctrl(state->uart_port, TIOCM_RTS);
619}
620
621static void uart_unthrottle(struct tty_struct *tty)
622{
623 struct uart_state *state = tty->driver_data;
624 struct uart_port *port = state->uart_port;
625
626 if (I_IXOFF(tty)) {
627 if (port->x_char)
628 port->x_char = 0;
629 else
630 uart_send_xchar(tty, START_CHAR(tty));
631 }
632
633 if (tty->termios->c_cflag & CRTSCTS)
634 uart_set_mctrl(port, TIOCM_RTS);
635}
636
637static int uart_get_info(struct uart_state *state,
638 struct serial_struct __user *retinfo)
639{
640 struct uart_port *uport = state->uart_port;
641 struct tty_port *port = &state->port;
642 struct serial_struct tmp;
643
644 memset(&tmp, 0, sizeof(tmp));
645
646 /* Ensure the state we copy is consistent and no hardware changes
647 occur as we go */
648 mutex_lock(&port->mutex);
649
650 tmp.type = uport->type;
651 tmp.line = uport->line;
652 tmp.port = uport->iobase;
653 if (HIGH_BITS_OFFSET)
654 tmp.port_high = (long) uport->iobase >> HIGH_BITS_OFFSET;
655 tmp.irq = uport->irq;
656 tmp.flags = uport->flags;
657 tmp.xmit_fifo_size = uport->fifosize;
658 tmp.baud_base = uport->uartclk / 16;
659 tmp.close_delay = port->close_delay / 10;
660 tmp.closing_wait = port->closing_wait == ASYNC_CLOSING_WAIT_NONE ?
661 ASYNC_CLOSING_WAIT_NONE :
662 port->closing_wait / 10;
663 tmp.custom_divisor = uport->custom_divisor;
664 tmp.hub6 = uport->hub6;
665 tmp.io_type = uport->iotype;
666 tmp.iomem_reg_shift = uport->regshift;
667 tmp.iomem_base = (void *)(unsigned long)uport->mapbase;
668
669 mutex_unlock(&port->mutex);
670
671 if (copy_to_user(retinfo, &tmp, sizeof(*retinfo)))
672 return -EFAULT;
673 return 0;
674}
675
676static int uart_set_info(struct tty_struct *tty, struct uart_state *state,
677 struct serial_struct __user *newinfo)
678{
679 struct serial_struct new_serial;
680 struct uart_port *uport = state->uart_port;
681 struct tty_port *port = &state->port;
682 unsigned long new_port;
683 unsigned int change_irq, change_port, closing_wait;
684 unsigned int old_custom_divisor, close_delay;
685 upf_t old_flags, new_flags;
686 int retval = 0;
687
688 if (copy_from_user(&new_serial, newinfo, sizeof(new_serial)))
689 return -EFAULT;
690
691 new_port = new_serial.port;
692 if (HIGH_BITS_OFFSET)
693 new_port += (unsigned long) new_serial.port_high << HIGH_BITS_OFFSET;
694
695 new_serial.irq = irq_canonicalize(new_serial.irq);
696 close_delay = new_serial.close_delay * 10;
697 closing_wait = new_serial.closing_wait == ASYNC_CLOSING_WAIT_NONE ?
698 ASYNC_CLOSING_WAIT_NONE : new_serial.closing_wait * 10;
699
700 /*
701 * This semaphore protects port->count. It is also
702 * very useful to prevent opens. Also, take the
703 * port configuration semaphore to make sure that a
704 * module insertion/removal doesn't change anything
705 * under us.
706 */
707 mutex_lock(&port->mutex);
708
709 change_irq = !(uport->flags & UPF_FIXED_PORT)
710 && new_serial.irq != uport->irq;
711
712 /*
713 * Since changing the 'type' of the port changes its resource
714 * allocations, we should treat type changes the same as
715 * IO port changes.
716 */
717 change_port = !(uport->flags & UPF_FIXED_PORT)
718 && (new_port != uport->iobase ||
719 (unsigned long)new_serial.iomem_base != uport->mapbase ||
720 new_serial.hub6 != uport->hub6 ||
721 new_serial.io_type != uport->iotype ||
722 new_serial.iomem_reg_shift != uport->regshift ||
723 new_serial.type != uport->type);
724
725 old_flags = uport->flags;
726 new_flags = new_serial.flags;
727 old_custom_divisor = uport->custom_divisor;
728
729 if (!capable(CAP_SYS_ADMIN)) {
730 retval = -EPERM;
731 if (change_irq || change_port ||
732 (new_serial.baud_base != uport->uartclk / 16) ||
733 (close_delay != port->close_delay) ||
734 (closing_wait != port->closing_wait) ||
735 (new_serial.xmit_fifo_size &&
736 new_serial.xmit_fifo_size != uport->fifosize) ||
737 (((new_flags ^ old_flags) & ~UPF_USR_MASK) != 0))
738 goto exit;
739 uport->flags = ((uport->flags & ~UPF_USR_MASK) |
740 (new_flags & UPF_USR_MASK));
741 uport->custom_divisor = new_serial.custom_divisor;
742 goto check_and_exit;
743 }
744
745 /*
746 * Ask the low level driver to verify the settings.
747 */
748 if (uport->ops->verify_port)
749 retval = uport->ops->verify_port(uport, &new_serial);
750
751 if ((new_serial.irq >= nr_irqs) || (new_serial.irq < 0) ||
752 (new_serial.baud_base < 9600))
753 retval = -EINVAL;
754
755 if (retval)
756 goto exit;
757
758 if (change_port || change_irq) {
759 retval = -EBUSY;
760
761 /*
762 * Make sure that we are the sole user of this port.
763 */
764 if (tty_port_users(port) > 1)
765 goto exit;
766
767 /*
768 * We need to shutdown the serial port at the old
769 * port/type/irq combination.
770 */
771 uart_shutdown(tty, state);
772 }
773
774 if (change_port) {
775 unsigned long old_iobase, old_mapbase;
776 unsigned int old_type, old_iotype, old_hub6, old_shift;
777
778 old_iobase = uport->iobase;
779 old_mapbase = uport->mapbase;
780 old_type = uport->type;
781 old_hub6 = uport->hub6;
782 old_iotype = uport->iotype;
783 old_shift = uport->regshift;
784
785 /*
786 * Free and release old regions
787 */
788 if (old_type != PORT_UNKNOWN)
789 uport->ops->release_port(uport);
790
791 uport->iobase = new_port;
792 uport->type = new_serial.type;
793 uport->hub6 = new_serial.hub6;
794 uport->iotype = new_serial.io_type;
795 uport->regshift = new_serial.iomem_reg_shift;
796 uport->mapbase = (unsigned long)new_serial.iomem_base;
797
798 /*
799 * Claim and map the new regions
800 */
801 if (uport->type != PORT_UNKNOWN) {
802 retval = uport->ops->request_port(uport);
803 } else {
804 /* Always success - Jean II */
805 retval = 0;
806 }
807
808 /*
809 * If we fail to request resources for the
810 * new port, try to restore the old settings.
811 */
812 if (retval && old_type != PORT_UNKNOWN) {
813 uport->iobase = old_iobase;
814 uport->type = old_type;
815 uport->hub6 = old_hub6;
816 uport->iotype = old_iotype;
817 uport->regshift = old_shift;
818 uport->mapbase = old_mapbase;
819 retval = uport->ops->request_port(uport);
820 /*
821 * If we failed to restore the old settings,
822 * we fail like this.
823 */
824 if (retval)
825 uport->type = PORT_UNKNOWN;
826
827 /*
828 * We failed anyway.
829 */
830 retval = -EBUSY;
831 /* Added to return the correct error -Ram Gupta */
832 goto exit;
833 }
834 }
835
836 if (change_irq)
837 uport->irq = new_serial.irq;
838 if (!(uport->flags & UPF_FIXED_PORT))
839 uport->uartclk = new_serial.baud_base * 16;
840 uport->flags = (uport->flags & ~UPF_CHANGE_MASK) |
841 (new_flags & UPF_CHANGE_MASK);
842 uport->custom_divisor = new_serial.custom_divisor;
843 port->close_delay = close_delay;
844 port->closing_wait = closing_wait;
845 if (new_serial.xmit_fifo_size)
846 uport->fifosize = new_serial.xmit_fifo_size;
847 if (port->tty)
848 port->tty->low_latency =
849 (uport->flags & UPF_LOW_LATENCY) ? 1 : 0;
850
851 check_and_exit:
852 retval = 0;
853 if (uport->type == PORT_UNKNOWN)
854 goto exit;
855 if (port->flags & ASYNC_INITIALIZED) {
856 if (((old_flags ^ uport->flags) & UPF_SPD_MASK) ||
857 old_custom_divisor != uport->custom_divisor) {
858 /*
859 * If they're setting up a custom divisor or speed,
860 * instead of clearing it, then bitch about it. No
861 * need to rate-limit; it's CAP_SYS_ADMIN only.
862 */
863 if (uport->flags & UPF_SPD_MASK) {
864 char buf[64];
865 printk(KERN_NOTICE
866 "%s sets custom speed on %s. This "
867 "is deprecated.\n", current->comm,
868 tty_name(port->tty, buf));
869 }
870 uart_change_speed(tty, state, NULL);
871 }
872 } else
873 retval = uart_startup(tty, state, 1);
874 exit:
875 mutex_unlock(&port->mutex);
876 return retval;
877}
878
879/**
880 * uart_get_lsr_info - get line status register info
881 * @tty: tty associated with the UART
882 * @state: UART being queried
883 * @value: returned modem value
884 *
885 * Note: uart_ioctl protects us against hangups.
886 */
887static int uart_get_lsr_info(struct tty_struct *tty,
888 struct uart_state *state, unsigned int __user *value)
889{
890 struct uart_port *uport = state->uart_port;
891 unsigned int result;
892
893 result = uport->ops->tx_empty(uport);
894
895 /*
896 * If we're about to load something into the transmit
897 * register, we'll pretend the transmitter isn't empty to
898 * avoid a race condition (depending on when the transmit
899 * interrupt happens).
900 */
901 if (uport->x_char ||
902 ((uart_circ_chars_pending(&state->xmit) > 0) &&
903 !tty->stopped && !tty->hw_stopped))
904 result &= ~TIOCSER_TEMT;
905
906 return put_user(result, value);
907}
908
909static int uart_tiocmget(struct tty_struct *tty, struct file *file)
910{
911 struct uart_state *state = tty->driver_data;
912 struct tty_port *port = &state->port;
913 struct uart_port *uport = state->uart_port;
914 int result = -EIO;
915
916 mutex_lock(&port->mutex);
917 if ((!file || !tty_hung_up_p(file)) &&
918 !(tty->flags & (1 << TTY_IO_ERROR))) {
919 result = uport->mctrl;
920
921 spin_lock_irq(&uport->lock);
922 result |= uport->ops->get_mctrl(uport);
923 spin_unlock_irq(&uport->lock);
924 }
925 mutex_unlock(&port->mutex);
926
927 return result;
928}
929
930static int
931uart_tiocmset(struct tty_struct *tty, struct file *file,
932 unsigned int set, unsigned int clear)
933{
934 struct uart_state *state = tty->driver_data;
935 struct uart_port *uport = state->uart_port;
936 struct tty_port *port = &state->port;
937 int ret = -EIO;
938
939 mutex_lock(&port->mutex);
940 if ((!file || !tty_hung_up_p(file)) &&
941 !(tty->flags & (1 << TTY_IO_ERROR))) {
942 uart_update_mctrl(uport, set, clear);
943 ret = 0;
944 }
945 mutex_unlock(&port->mutex);
946 return ret;
947}
948
949static int uart_break_ctl(struct tty_struct *tty, int break_state)
950{
951 struct uart_state *state = tty->driver_data;
952 struct tty_port *port = &state->port;
953 struct uart_port *uport = state->uart_port;
954
955 mutex_lock(&port->mutex);
956
957 if (uport->type != PORT_UNKNOWN)
958 uport->ops->break_ctl(uport, break_state);
959
960 mutex_unlock(&port->mutex);
961 return 0;
962}
963
964static int uart_do_autoconfig(struct tty_struct *tty,struct uart_state *state)
965{
966 struct uart_port *uport = state->uart_port;
967 struct tty_port *port = &state->port;
968 int flags, ret;
969
970 if (!capable(CAP_SYS_ADMIN))
971 return -EPERM;
972
973 /*
974 * Take the per-port semaphore. This prevents count from
975 * changing, and hence any extra opens of the port while
976 * we're auto-configuring.
977 */
978 if (mutex_lock_interruptible(&port->mutex))
979 return -ERESTARTSYS;
980
981 ret = -EBUSY;
982 if (tty_port_users(port) == 1) {
983 uart_shutdown(tty, state);
984
985 /*
986 * If we already have a port type configured,
987 * we must release its resources.
988 */
989 if (uport->type != PORT_UNKNOWN)
990 uport->ops->release_port(uport);
991
992 flags = UART_CONFIG_TYPE;
993 if (uport->flags & UPF_AUTO_IRQ)
994 flags |= UART_CONFIG_IRQ;
995
996 /*
997 * This will claim the ports resources if
998 * a port is found.
999 */
1000 uport->ops->config_port(uport, flags);
1001
1002 ret = uart_startup(tty, state, 1);
1003 }
1004 mutex_unlock(&port->mutex);
1005 return ret;
1006}
1007
1008/*
1009 * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change
1010 * - mask passed in arg for lines of interest
1011 * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking)
1012 * Caller should use TIOCGICOUNT to see which one it was
1013 *
1014 * FIXME: This wants extracting into a common all driver implementation
1015 * of TIOCMWAIT using tty_port.
1016 */
1017static int
1018uart_wait_modem_status(struct uart_state *state, unsigned long arg)
1019{
1020 struct uart_port *uport = state->uart_port;
1021 struct tty_port *port = &state->port;
1022 DECLARE_WAITQUEUE(wait, current);
1023 struct uart_icount cprev, cnow;
1024 int ret;
1025
1026 /*
1027 * note the counters on entry
1028 */
1029 spin_lock_irq(&uport->lock);
1030 memcpy(&cprev, &uport->icount, sizeof(struct uart_icount));
1031
1032 /*
1033 * Force modem status interrupts on
1034 */
1035 uport->ops->enable_ms(uport);
1036 spin_unlock_irq(&uport->lock);
1037
1038 add_wait_queue(&port->delta_msr_wait, &wait);
1039 for (;;) {
1040 spin_lock_irq(&uport->lock);
1041 memcpy(&cnow, &uport->icount, sizeof(struct uart_icount));
1042 spin_unlock_irq(&uport->lock);
1043
1044 set_current_state(TASK_INTERRUPTIBLE);
1045
1046 if (((arg & TIOCM_RNG) && (cnow.rng != cprev.rng)) ||
1047 ((arg & TIOCM_DSR) && (cnow.dsr != cprev.dsr)) ||
1048 ((arg & TIOCM_CD) && (cnow.dcd != cprev.dcd)) ||
1049 ((arg & TIOCM_CTS) && (cnow.cts != cprev.cts))) {
1050 ret = 0;
1051 break;
1052 }
1053
1054 schedule();
1055
1056 /* see if a signal did it */
1057 if (signal_pending(current)) {
1058 ret = -ERESTARTSYS;
1059 break;
1060 }
1061
1062 cprev = cnow;
1063 }
1064
1065 current->state = TASK_RUNNING;
1066 remove_wait_queue(&port->delta_msr_wait, &wait);
1067
1068 return ret;
1069}
1070
1071/*
1072 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1073 * Return: write counters to the user passed counter struct
1074 * NB: both 1->0 and 0->1 transitions are counted except for
1075 * RI where only 0->1 is counted.
1076 */
1077static int uart_get_count(struct uart_state *state,
1078 struct serial_icounter_struct __user *icnt)
1079{
1080 struct serial_icounter_struct icount;
1081 struct uart_icount cnow;
1082 struct uart_port *uport = state->uart_port;
1083
1084 spin_lock_irq(&uport->lock);
1085 memcpy(&cnow, &uport->icount, sizeof(struct uart_icount));
1086 spin_unlock_irq(&uport->lock);
1087
1088 icount.cts = cnow.cts;
1089 icount.dsr = cnow.dsr;
1090 icount.rng = cnow.rng;
1091 icount.dcd = cnow.dcd;
1092 icount.rx = cnow.rx;
1093 icount.tx = cnow.tx;
1094 icount.frame = cnow.frame;
1095 icount.overrun = cnow.overrun;
1096 icount.parity = cnow.parity;
1097 icount.brk = cnow.brk;
1098 icount.buf_overrun = cnow.buf_overrun;
1099
1100 return copy_to_user(icnt, &icount, sizeof(icount)) ? -EFAULT : 0;
1101}
1102
1103/*
1104 * Called via sys_ioctl. We can use spin_lock_irq() here.
1105 */
1106static int
1107uart_ioctl(struct tty_struct *tty, struct file *filp, unsigned int cmd,
1108 unsigned long arg)
1109{
1110 struct uart_state *state = tty->driver_data;
1111 struct tty_port *port = &state->port;
1112 void __user *uarg = (void __user *)arg;
1113 int ret = -ENOIOCTLCMD;
1114
1115
1116 /*
1117 * These ioctls don't rely on the hardware to be present.
1118 */
1119 switch (cmd) {
1120 case TIOCGSERIAL:
1121 ret = uart_get_info(state, uarg);
1122 break;
1123
1124 case TIOCSSERIAL:
1125 ret = uart_set_info(tty, state, uarg);
1126 break;
1127
1128 case TIOCSERCONFIG:
1129 ret = uart_do_autoconfig(tty, state);
1130 break;
1131
1132 case TIOCSERGWILD: /* obsolete */
1133 case TIOCSERSWILD: /* obsolete */
1134 ret = 0;
1135 break;
1136 }
1137
1138 if (ret != -ENOIOCTLCMD)
1139 goto out;
1140
1141 if (tty->flags & (1 << TTY_IO_ERROR)) {
1142 ret = -EIO;
1143 goto out;
1144 }
1145
1146 /*
1147 * The following should only be used when hardware is present.
1148 */
1149 switch (cmd) {
1150 case TIOCMIWAIT:
1151 ret = uart_wait_modem_status(state, arg);
1152 break;
1153
1154 case TIOCGICOUNT:
1155 ret = uart_get_count(state, uarg);
1156 break;
1157 }
1158
1159 if (ret != -ENOIOCTLCMD)
1160 goto out;
1161
1162 mutex_lock(&port->mutex);
1163
1164 if (tty_hung_up_p(filp)) {
1165 ret = -EIO;
1166 goto out_up;
1167 }
1168
1169 /*
1170 * All these rely on hardware being present and need to be
1171 * protected against the tty being hung up.
1172 */
1173 switch (cmd) {
1174 case TIOCSERGETLSR: /* Get line status register */
1175 ret = uart_get_lsr_info(tty, state, uarg);
1176 break;
1177
1178 default: {
1179 struct uart_port *uport = state->uart_port;
1180 if (uport->ops->ioctl)
1181 ret = uport->ops->ioctl(uport, cmd, arg);
1182 break;
1183 }
1184 }
1185out_up:
1186 mutex_unlock(&port->mutex);
1187out:
1188 return ret;
1189}
1190
1191static void uart_set_ldisc(struct tty_struct *tty)
1192{
1193 struct uart_state *state = tty->driver_data;
1194 struct uart_port *uport = state->uart_port;
1195
1196 if (uport->ops->set_ldisc)
1197 uport->ops->set_ldisc(uport, tty->termios->c_line);
1198}
1199
1200static void uart_set_termios(struct tty_struct *tty,
1201 struct ktermios *old_termios)
1202{
1203 struct uart_state *state = tty->driver_data;
1204 unsigned long flags;
1205 unsigned int cflag = tty->termios->c_cflag;
1206
1207
1208 /*
1209 * These are the bits that are used to setup various
1210 * flags in the low level driver. We can ignore the Bfoo
1211 * bits in c_cflag; c_[io]speed will always be set
1212 * appropriately by set_termios() in tty_ioctl.c
1213 */
1214#define RELEVANT_IFLAG(iflag) ((iflag) & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
1215 if ((cflag ^ old_termios->c_cflag) == 0 &&
1216 tty->termios->c_ospeed == old_termios->c_ospeed &&
1217 tty->termios->c_ispeed == old_termios->c_ispeed &&
1218 RELEVANT_IFLAG(tty->termios->c_iflag ^ old_termios->c_iflag) == 0) {
1219 return;
1220 }
1221
1222 uart_change_speed(tty, state, old_termios);
1223
1224 /* Handle transition to B0 status */
1225 if ((old_termios->c_cflag & CBAUD) && !(cflag & CBAUD))
1226 uart_clear_mctrl(state->uart_port, TIOCM_RTS | TIOCM_DTR);
1227 /* Handle transition away from B0 status */
1228 else if (!(old_termios->c_cflag & CBAUD) && (cflag & CBAUD)) {
1229 unsigned int mask = TIOCM_DTR;
1230 if (!(cflag & CRTSCTS) ||
1231 !test_bit(TTY_THROTTLED, &tty->flags))
1232 mask |= TIOCM_RTS;
1233 uart_set_mctrl(state->uart_port, mask);
1234 }
1235
1236 /* Handle turning off CRTSCTS */
1237 if ((old_termios->c_cflag & CRTSCTS) && !(cflag & CRTSCTS)) {
1238 spin_lock_irqsave(&state->uart_port->lock, flags);
1239 tty->hw_stopped = 0;
1240 __uart_start(tty);
1241 spin_unlock_irqrestore(&state->uart_port->lock, flags);
1242 }
1243 /* Handle turning on CRTSCTS */
1244 else if (!(old_termios->c_cflag & CRTSCTS) && (cflag & CRTSCTS)) {
1245 spin_lock_irqsave(&state->uart_port->lock, flags);
1246 if (!(state->uart_port->ops->get_mctrl(state->uart_port) & TIOCM_CTS)) {
1247 tty->hw_stopped = 1;
1248 state->uart_port->ops->stop_tx(state->uart_port);
1249 }
1250 spin_unlock_irqrestore(&state->uart_port->lock, flags);
1251 }
1252#if 0
1253 /*
1254 * No need to wake up processes in open wait, since they
1255 * sample the CLOCAL flag once, and don't recheck it.
1256 * XXX It's not clear whether the current behavior is correct
1257 * or not. Hence, this may change.....
1258 */
1259 if (!(old_termios->c_cflag & CLOCAL) &&
1260 (tty->termios->c_cflag & CLOCAL))
1261 wake_up_interruptible(&state->uart_port.open_wait);
1262#endif
1263}
1264
1265/*
1266 * In 2.4.5, calls to this will be serialized via the BKL in
1267 * linux/drivers/char/tty_io.c:tty_release()
1268 * linux/drivers/char/tty_io.c:do_tty_handup()
1269 */
1270static void uart_close(struct tty_struct *tty, struct file *filp)
1271{
1272 struct uart_state *state = tty->driver_data;
1273 struct tty_port *port;
1274 struct uart_port *uport;
1275 unsigned long flags;
1276
1277 BUG_ON(!tty_locked());
1278
1279 if (!state)
1280 return;
1281
1282 uport = state->uart_port;
1283 port = &state->port;
1284
1285 pr_debug("uart_close(%d) called\n", uport->line);
1286
1287 mutex_lock(&port->mutex);
1288 spin_lock_irqsave(&port->lock, flags);
1289
1290 if (tty_hung_up_p(filp)) {
1291 spin_unlock_irqrestore(&port->lock, flags);
1292 goto done;
1293 }
1294
1295 if ((tty->count == 1) && (port->count != 1)) {
1296 /*
1297 * Uh, oh. tty->count is 1, which means that the tty
1298 * structure will be freed. port->count should always
1299 * be one in these conditions. If it's greater than
1300 * one, we've got real problems, since it means the
1301 * serial port won't be shutdown.
1302 */
1303 printk(KERN_ERR "uart_close: bad serial port count; tty->count is 1, "
1304 "port->count is %d\n", port->count);
1305 port->count = 1;
1306 }
1307 if (--port->count < 0) {
1308 printk(KERN_ERR "uart_close: bad serial port count for %s: %d\n",
1309 tty->name, port->count);
1310 port->count = 0;
1311 }
1312 if (port->count) {
1313 spin_unlock_irqrestore(&port->lock, flags);
1314 goto done;
1315 }
1316
1317 /*
1318 * Now we wait for the transmit buffer to clear; and we notify
1319 * the line discipline to only process XON/XOFF characters by
1320 * setting tty->closing.
1321 */
1322 tty->closing = 1;
1323 spin_unlock_irqrestore(&port->lock, flags);
1324
1325 if (port->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
1326 /*
1327 * hack: open-coded tty_wait_until_sent to avoid
1328 * recursive tty_lock
1329 */
1330 long timeout = msecs_to_jiffies(port->closing_wait);
1331 if (wait_event_interruptible_timeout(tty->write_wait,
1332 !tty_chars_in_buffer(tty), timeout) >= 0)
1333 __uart_wait_until_sent(uport, timeout);
1334 }
1335
1336 /*
1337 * At this point, we stop accepting input. To do this, we
1338 * disable the receive line status interrupts.
1339 */
1340 if (port->flags & ASYNC_INITIALIZED) {
1341 unsigned long flags;
1342 spin_lock_irqsave(&uport->lock, flags);
1343 uport->ops->stop_rx(uport);
1344 spin_unlock_irqrestore(&uport->lock, flags);
1345 /*
1346 * Before we drop DTR, make sure the UART transmitter
1347 * has completely drained; this is especially
1348 * important if there is a transmit FIFO!
1349 */
1350 __uart_wait_until_sent(uport, uport->timeout);
1351 }
1352
1353 uart_shutdown(tty, state);
1354 uart_flush_buffer(tty);
1355
1356 tty_ldisc_flush(tty);
1357
1358 tty_port_tty_set(port, NULL);
1359 spin_lock_irqsave(&port->lock, flags);
1360 tty->closing = 0;
1361
1362 if (port->blocked_open) {
1363 spin_unlock_irqrestore(&port->lock, flags);
1364 if (port->close_delay)
1365 msleep_interruptible(port->close_delay);
1366 spin_lock_irqsave(&port->lock, flags);
1367 } else if (!uart_console(uport)) {
1368 spin_unlock_irqrestore(&port->lock, flags);
1369 uart_change_pm(state, 3);
1370 spin_lock_irqsave(&port->lock, flags);
1371 }
1372
1373 /*
1374 * Wake up anyone trying to open this port.
1375 */
1376 clear_bit(ASYNCB_NORMAL_ACTIVE, &port->flags);
1377 spin_unlock_irqrestore(&port->lock, flags);
1378 wake_up_interruptible(&port->open_wait);
1379
1380done:
1381 mutex_unlock(&port->mutex);
1382}
1383
1384static void __uart_wait_until_sent(struct uart_port *port, int timeout)
1385{
1386 unsigned long char_time, expire;
1387
1388 if (port->type == PORT_UNKNOWN || port->fifosize == 0)
1389 return;
1390
1391 /*
1392 * Set the check interval to be 1/5 of the estimated time to
1393 * send a single character, and make it at least 1. The check
1394 * interval should also be less than the timeout.
1395 *
1396 * Note: we have to use pretty tight timings here to satisfy
1397 * the NIST-PCTS.
1398 */
1399 char_time = (port->timeout - HZ/50) / port->fifosize;
1400 char_time = char_time / 5;
1401 if (char_time == 0)
1402 char_time = 1;
1403 if (timeout && timeout < char_time)
1404 char_time = timeout;
1405
1406 /*
1407 * If the transmitter hasn't cleared in twice the approximate
1408 * amount of time to send the entire FIFO, it probably won't
1409 * ever clear. This assumes the UART isn't doing flow
1410 * control, which is currently the case. Hence, if it ever
1411 * takes longer than port->timeout, this is probably due to a
1412 * UART bug of some kind. So, we clamp the timeout parameter at
1413 * 2*port->timeout.
1414 */
1415 if (timeout == 0 || timeout > 2 * port->timeout)
1416 timeout = 2 * port->timeout;
1417
1418 expire = jiffies + timeout;
1419
1420 pr_debug("uart_wait_until_sent(%d), jiffies=%lu, expire=%lu...\n",
1421 port->line, jiffies, expire);
1422
1423 /*
1424 * Check whether the transmitter is empty every 'char_time'.
1425 * 'timeout' / 'expire' give us the maximum amount of time
1426 * we wait.
1427 */
1428 while (!port->ops->tx_empty(port)) {
1429 msleep_interruptible(jiffies_to_msecs(char_time));
1430 if (signal_pending(current))
1431 break;
1432 if (time_after(jiffies, expire))
1433 break;
1434 }
1435 set_current_state(TASK_RUNNING); /* might not be needed */
1436}
1437
1438static void uart_wait_until_sent(struct tty_struct *tty, int timeout)
1439{
1440 struct uart_state *state = tty->driver_data;
1441 struct uart_port *port = state->uart_port;
1442
1443 tty_lock();
1444 __uart_wait_until_sent(port, timeout);
1445 tty_unlock();
1446}
1447
1448/*
1449 * This is called with the BKL held in
1450 * linux/drivers/char/tty_io.c:do_tty_hangup()
1451 * We're called from the eventd thread, so we can sleep for
1452 * a _short_ time only.
1453 */
1454static void uart_hangup(struct tty_struct *tty)
1455{
1456 struct uart_state *state = tty->driver_data;
1457 struct tty_port *port = &state->port;
1458 unsigned long flags;
1459
1460 BUG_ON(!tty_locked());
1461 pr_debug("uart_hangup(%d)\n", state->uart_port->line);
1462
1463 mutex_lock(&port->mutex);
1464 if (port->flags & ASYNC_NORMAL_ACTIVE) {
1465 uart_flush_buffer(tty);
1466 uart_shutdown(tty, state);
1467 spin_lock_irqsave(&port->lock, flags);
1468 port->count = 0;
1469 clear_bit(ASYNCB_NORMAL_ACTIVE, &port->flags);
1470 spin_unlock_irqrestore(&port->lock, flags);
1471 tty_port_tty_set(port, NULL);
1472 wake_up_interruptible(&port->open_wait);
1473 wake_up_interruptible(&port->delta_msr_wait);
1474 }
1475 mutex_unlock(&port->mutex);
1476}
1477
1478/**
1479 * uart_update_termios - update the terminal hw settings
1480 * @tty: tty associated with UART
1481 * @state: UART to update
1482 *
1483 * Copy across the serial console cflag setting into the termios settings
1484 * for the initial open of the port. This allows continuity between the
1485 * kernel settings, and the settings init adopts when it opens the port
1486 * for the first time.
1487 */
1488static void uart_update_termios(struct tty_struct *tty,
1489 struct uart_state *state)
1490{
1491 struct uart_port *port = state->uart_port;
1492
1493 if (uart_console(port) && port->cons->cflag) {
1494 tty->termios->c_cflag = port->cons->cflag;
1495 port->cons->cflag = 0;
1496 }
1497
1498 /*
1499 * If the device failed to grab its irq resources,
1500 * or some other error occurred, don't try to talk
1501 * to the port hardware.
1502 */
1503 if (!(tty->flags & (1 << TTY_IO_ERROR))) {
1504 /*
1505 * Make termios settings take effect.
1506 */
1507 uart_change_speed(tty, state, NULL);
1508
1509 /*
1510 * And finally enable the RTS and DTR signals.
1511 */
1512 if (tty->termios->c_cflag & CBAUD)
1513 uart_set_mctrl(port, TIOCM_DTR | TIOCM_RTS);
1514 }
1515}
1516
1517static int uart_carrier_raised(struct tty_port *port)
1518{
1519 struct uart_state *state = container_of(port, struct uart_state, port);
1520 struct uart_port *uport = state->uart_port;
1521 int mctrl;
1522 spin_lock_irq(&uport->lock);
1523 uport->ops->enable_ms(uport);
1524 mctrl = uport->ops->get_mctrl(uport);
1525 spin_unlock_irq(&uport->lock);
1526 if (mctrl & TIOCM_CAR)
1527 return 1;
1528 return 0;
1529}
1530
1531static void uart_dtr_rts(struct tty_port *port, int onoff)
1532{
1533 struct uart_state *state = container_of(port, struct uart_state, port);
1534 struct uart_port *uport = state->uart_port;
1535
1536 if (onoff) {
1537 uart_set_mctrl(uport, TIOCM_DTR | TIOCM_RTS);
1538
1539 /*
1540 * If this is the first open to succeed,
1541 * adjust things to suit.
1542 */
1543 if (!test_and_set_bit(ASYNCB_NORMAL_ACTIVE, &port->flags))
1544 uart_update_termios(port->tty, state);
1545 }
1546 else
1547 uart_clear_mctrl(uport, TIOCM_DTR | TIOCM_RTS);
1548}
1549
1550static struct uart_state *uart_get(struct uart_driver *drv, int line)
1551{
1552 struct uart_state *state;
1553 struct tty_port *port;
1554 int ret = 0;
1555
1556 state = drv->state + line;
1557 port = &state->port;
1558 if (mutex_lock_interruptible(&port->mutex)) {
1559 ret = -ERESTARTSYS;
1560 goto err;
1561 }
1562
1563 port->count++;
1564 if (!state->uart_port || state->uart_port->flags & UPF_DEAD) {
1565 ret = -ENXIO;
1566 goto err_unlock;
1567 }
1568 return state;
1569
1570 err_unlock:
1571 port->count--;
1572 mutex_unlock(&port->mutex);
1573 err:
1574 return ERR_PTR(ret);
1575}
1576
1577/*
1578 * calls to uart_open are serialised by the BKL in
1579 * fs/char_dev.c:chrdev_open()
1580 * Note that if this fails, then uart_close() _will_ be called.
1581 *
1582 * In time, we want to scrap the "opening nonpresent ports"
1583 * behaviour and implement an alternative way for setserial
1584 * to set base addresses/ports/types. This will allow us to
1585 * get rid of a certain amount of extra tests.
1586 */
1587static int uart_open(struct tty_struct *tty, struct file *filp)
1588{
1589 struct uart_driver *drv = (struct uart_driver *)tty->driver->driver_state;
1590 struct uart_state *state;
1591 struct tty_port *port;
1592 int retval, line = tty->index;
1593
1594 BUG_ON(!tty_locked());
1595 pr_debug("uart_open(%d) called\n", line);
1596
1597 /*
1598 * tty->driver->num won't change, so we won't fail here with
1599 * tty->driver_data set to something non-NULL (and therefore
1600 * we won't get caught by uart_close()).
1601 */
1602 retval = -ENODEV;
1603 if (line >= tty->driver->num)
1604 goto fail;
1605
1606 /*
1607 * We take the semaphore inside uart_get to guarantee that we won't
1608 * be re-entered while allocating the state structure, or while we
1609 * request any IRQs that the driver may need. This also has the nice
1610 * side-effect that it delays the action of uart_hangup, so we can
1611 * guarantee that state->port.tty will always contain something
1612 * reasonable.
1613 */
1614 state = uart_get(drv, line);
1615 if (IS_ERR(state)) {
1616 retval = PTR_ERR(state);
1617 goto fail;
1618 }
1619 port = &state->port;
1620
1621 /*
1622 * Once we set tty->driver_data here, we are guaranteed that
1623 * uart_close() will decrement the driver module use count.
1624 * Any failures from here onwards should not touch the count.
1625 */
1626 tty->driver_data = state;
1627 state->uart_port->state = state;
1628 tty->low_latency = (state->uart_port->flags & UPF_LOW_LATENCY) ? 1 : 0;
1629 tty->alt_speed = 0;
1630 tty_port_tty_set(port, tty);
1631
1632 /*
1633 * If the port is in the middle of closing, bail out now.
1634 */
1635 if (tty_hung_up_p(filp)) {
1636 retval = -EAGAIN;
1637 port->count--;
1638 mutex_unlock(&port->mutex);
1639 goto fail;
1640 }
1641
1642 /*
1643 * Make sure the device is in D0 state.
1644 */
1645 if (port->count == 1)
1646 uart_change_pm(state, 0);
1647
1648 /*
1649 * Start up the serial port.
1650 */
1651 retval = uart_startup(tty, state, 0);
1652
1653 /*
1654 * If we succeeded, wait until the port is ready.
1655 */
1656 mutex_unlock(&port->mutex);
1657 if (retval == 0)
1658 retval = tty_port_block_til_ready(port, tty, filp);
1659
1660fail:
1661 return retval;
1662}
1663
1664static const char *uart_type(struct uart_port *port)
1665{
1666 const char *str = NULL;
1667
1668 if (port->ops->type)
1669 str = port->ops->type(port);
1670
1671 if (!str)
1672 str = "unknown";
1673
1674 return str;
1675}
1676
1677#ifdef CONFIG_PROC_FS
1678
1679static void uart_line_info(struct seq_file *m, struct uart_driver *drv, int i)
1680{
1681 struct uart_state *state = drv->state + i;
1682 struct tty_port *port = &state->port;
1683 int pm_state;
1684 struct uart_port *uport = state->uart_port;
1685 char stat_buf[32];
1686 unsigned int status;
1687 int mmio;
1688
1689 if (!uport)
1690 return;
1691
1692 mmio = uport->iotype >= UPIO_MEM;
1693 seq_printf(m, "%d: uart:%s %s%08llX irq:%d",
1694 uport->line, uart_type(uport),
1695 mmio ? "mmio:0x" : "port:",
1696 mmio ? (unsigned long long)uport->mapbase
1697 : (unsigned long long)uport->iobase,
1698 uport->irq);
1699
1700 if (uport->type == PORT_UNKNOWN) {
1701 seq_putc(m, '\n');
1702 return;
1703 }
1704
1705 if (capable(CAP_SYS_ADMIN)) {
1706 mutex_lock(&port->mutex);
1707 pm_state = state->pm_state;
1708 if (pm_state)
1709 uart_change_pm(state, 0);
1710 spin_lock_irq(&uport->lock);
1711 status = uport->ops->get_mctrl(uport);
1712 spin_unlock_irq(&uport->lock);
1713 if (pm_state)
1714 uart_change_pm(state, pm_state);
1715 mutex_unlock(&port->mutex);
1716
1717 seq_printf(m, " tx:%d rx:%d",
1718 uport->icount.tx, uport->icount.rx);
1719 if (uport->icount.frame)
1720 seq_printf(m, " fe:%d",
1721 uport->icount.frame);
1722 if (uport->icount.parity)
1723 seq_printf(m, " pe:%d",
1724 uport->icount.parity);
1725 if (uport->icount.brk)
1726 seq_printf(m, " brk:%d",
1727 uport->icount.brk);
1728 if (uport->icount.overrun)
1729 seq_printf(m, " oe:%d",
1730 uport->icount.overrun);
1731
1732#define INFOBIT(bit, str) \
1733 if (uport->mctrl & (bit)) \
1734 strncat(stat_buf, (str), sizeof(stat_buf) - \
1735 strlen(stat_buf) - 2)
1736#define STATBIT(bit, str) \
1737 if (status & (bit)) \
1738 strncat(stat_buf, (str), sizeof(stat_buf) - \
1739 strlen(stat_buf) - 2)
1740
1741 stat_buf[0] = '\0';
1742 stat_buf[1] = '\0';
1743 INFOBIT(TIOCM_RTS, "|RTS");
1744 STATBIT(TIOCM_CTS, "|CTS");
1745 INFOBIT(TIOCM_DTR, "|DTR");
1746 STATBIT(TIOCM_DSR, "|DSR");
1747 STATBIT(TIOCM_CAR, "|CD");
1748 STATBIT(TIOCM_RNG, "|RI");
1749 if (stat_buf[0])
1750 stat_buf[0] = ' ';
1751
1752 seq_puts(m, stat_buf);
1753 }
1754 seq_putc(m, '\n');
1755#undef STATBIT
1756#undef INFOBIT
1757}
1758
1759static int uart_proc_show(struct seq_file *m, void *v)
1760{
1761 struct tty_driver *ttydrv = m->private;
1762 struct uart_driver *drv = ttydrv->driver_state;
1763 int i;
1764
1765 seq_printf(m, "serinfo:1.0 driver%s%s revision:%s\n",
1766 "", "", "");
1767 for (i = 0; i < drv->nr; i++)
1768 uart_line_info(m, drv, i);
1769 return 0;
1770}
1771
1772static int uart_proc_open(struct inode *inode, struct file *file)
1773{
1774 return single_open(file, uart_proc_show, PDE(inode)->data);
1775}
1776
1777static const struct file_operations uart_proc_fops = {
1778 .owner = THIS_MODULE,
1779 .open = uart_proc_open,
1780 .read = seq_read,
1781 .llseek = seq_lseek,
1782 .release = single_release,
1783};
1784#endif
1785
1786#if defined(CONFIG_SERIAL_CORE_CONSOLE) || defined(CONFIG_CONSOLE_POLL)
1787/*
1788 * uart_console_write - write a console message to a serial port
1789 * @port: the port to write the message
1790 * @s: array of characters
1791 * @count: number of characters in string to write
1792 * @write: function to write character to port
1793 */
1794void uart_console_write(struct uart_port *port, const char *s,
1795 unsigned int count,
1796 void (*putchar)(struct uart_port *, int))
1797{
1798 unsigned int i;
1799
1800 for (i = 0; i < count; i++, s++) {
1801 if (*s == '\n')
1802 putchar(port, '\r');
1803 putchar(port, *s);
1804 }
1805}
1806EXPORT_SYMBOL_GPL(uart_console_write);
1807
1808/*
1809 * Check whether an invalid uart number has been specified, and
1810 * if so, search for the first available port that does have
1811 * console support.
1812 */
1813struct uart_port * __init
1814uart_get_console(struct uart_port *ports, int nr, struct console *co)
1815{
1816 int idx = co->index;
1817
1818 if (idx < 0 || idx >= nr || (ports[idx].iobase == 0 &&
1819 ports[idx].membase == NULL))
1820 for (idx = 0; idx < nr; idx++)
1821 if (ports[idx].iobase != 0 ||
1822 ports[idx].membase != NULL)
1823 break;
1824
1825 co->index = idx;
1826
1827 return ports + idx;
1828}
1829
1830/**
1831 * uart_parse_options - Parse serial port baud/parity/bits/flow contro.
1832 * @options: pointer to option string
1833 * @baud: pointer to an 'int' variable for the baud rate.
1834 * @parity: pointer to an 'int' variable for the parity.
1835 * @bits: pointer to an 'int' variable for the number of data bits.
1836 * @flow: pointer to an 'int' variable for the flow control character.
1837 *
1838 * uart_parse_options decodes a string containing the serial console
1839 * options. The format of the string is <baud><parity><bits><flow>,
1840 * eg: 115200n8r
1841 */
1842void
1843uart_parse_options(char *options, int *baud, int *parity, int *bits, int *flow)
1844{
1845 char *s = options;
1846
1847 *baud = simple_strtoul(s, NULL, 10);
1848 while (*s >= '0' && *s <= '9')
1849 s++;
1850 if (*s)
1851 *parity = *s++;
1852 if (*s)
1853 *bits = *s++ - '0';
1854 if (*s)
1855 *flow = *s;
1856}
1857EXPORT_SYMBOL_GPL(uart_parse_options);
1858
1859struct baud_rates {
1860 unsigned int rate;
1861 unsigned int cflag;
1862};
1863
1864static const struct baud_rates baud_rates[] = {
1865 { 921600, B921600 },
1866 { 460800, B460800 },
1867 { 230400, B230400 },
1868 { 115200, B115200 },
1869 { 57600, B57600 },
1870 { 38400, B38400 },
1871 { 19200, B19200 },
1872 { 9600, B9600 },
1873 { 4800, B4800 },
1874 { 2400, B2400 },
1875 { 1200, B1200 },
1876 { 0, B38400 }
1877};
1878
1879/**
1880 * uart_set_options - setup the serial console parameters
1881 * @port: pointer to the serial ports uart_port structure
1882 * @co: console pointer
1883 * @baud: baud rate
1884 * @parity: parity character - 'n' (none), 'o' (odd), 'e' (even)
1885 * @bits: number of data bits
1886 * @flow: flow control character - 'r' (rts)
1887 */
1888int
1889uart_set_options(struct uart_port *port, struct console *co,
1890 int baud, int parity, int bits, int flow)
1891{
1892 struct ktermios termios;
1893 static struct ktermios dummy;
1894 int i;
1895
1896 /*
1897 * Ensure that the serial console lock is initialised
1898 * early.
1899 */
1900 spin_lock_init(&port->lock);
1901 lockdep_set_class(&port->lock, &port_lock_key);
1902
1903 memset(&termios, 0, sizeof(struct ktermios));
1904
1905 termios.c_cflag = CREAD | HUPCL | CLOCAL;
1906
1907 /*
1908 * Construct a cflag setting.
1909 */
1910 for (i = 0; baud_rates[i].rate; i++)
1911 if (baud_rates[i].rate <= baud)
1912 break;
1913
1914 termios.c_cflag |= baud_rates[i].cflag;
1915
1916 if (bits == 7)
1917 termios.c_cflag |= CS7;
1918 else
1919 termios.c_cflag |= CS8;
1920
1921 switch (parity) {
1922 case 'o': case 'O':
1923 termios.c_cflag |= PARODD;
1924 /*fall through*/
1925 case 'e': case 'E':
1926 termios.c_cflag |= PARENB;
1927 break;
1928 }
1929
1930 if (flow == 'r')
1931 termios.c_cflag |= CRTSCTS;
1932
1933 /*
1934 * some uarts on other side don't support no flow control.
1935 * So we set * DTR in host uart to make them happy
1936 */
1937 port->mctrl |= TIOCM_DTR;
1938
1939 port->ops->set_termios(port, &termios, &dummy);
1940 /*
1941 * Allow the setting of the UART parameters with a NULL console
1942 * too:
1943 */
1944 if (co)
1945 co->cflag = termios.c_cflag;
1946
1947 return 0;
1948}
1949EXPORT_SYMBOL_GPL(uart_set_options);
1950#endif /* CONFIG_SERIAL_CORE_CONSOLE */
1951
1952static void uart_change_pm(struct uart_state *state, int pm_state)
1953{
1954 struct uart_port *port = state->uart_port;
1955
1956 if (state->pm_state != pm_state) {
1957 if (port->ops->pm)
1958 port->ops->pm(port, pm_state, state->pm_state);
1959 state->pm_state = pm_state;
1960 }
1961}
1962
1963struct uart_match {
1964 struct uart_port *port;
1965 struct uart_driver *driver;
1966};
1967
1968static int serial_match_port(struct device *dev, void *data)
1969{
1970 struct uart_match *match = data;
1971 struct tty_driver *tty_drv = match->driver->tty_driver;
1972 dev_t devt = MKDEV(tty_drv->major, tty_drv->minor_start) +
1973 match->port->line;
1974
1975 return dev->devt == devt; /* Actually, only one tty per port */
1976}
1977
1978int uart_suspend_port(struct uart_driver *drv, struct uart_port *uport)
1979{
1980 struct uart_state *state = drv->state + uport->line;
1981 struct tty_port *port = &state->port;
1982 struct device *tty_dev;
1983 struct uart_match match = {uport, drv};
1984 struct tty_struct *tty;
1985
1986 mutex_lock(&port->mutex);
1987
1988 /* Must be inside the mutex lock until we convert to tty_port */
1989 tty = port->tty;
1990
1991 tty_dev = device_find_child(uport->dev, &match, serial_match_port);
1992 if (device_may_wakeup(tty_dev)) {
1993 enable_irq_wake(uport->irq);
1994 put_device(tty_dev);
1995 mutex_unlock(&port->mutex);
1996 return 0;
1997 }
1998 if (console_suspend_enabled || !uart_console(uport))
1999 uport->suspended = 1;
2000
2001 if (port->flags & ASYNC_INITIALIZED) {
2002 const struct uart_ops *ops = uport->ops;
2003 int tries;
2004
2005 if (console_suspend_enabled || !uart_console(uport)) {
2006 set_bit(ASYNCB_SUSPENDED, &port->flags);
2007 clear_bit(ASYNCB_INITIALIZED, &port->flags);
2008
2009 spin_lock_irq(&uport->lock);
2010 ops->stop_tx(uport);
2011 ops->set_mctrl(uport, 0);
2012 ops->stop_rx(uport);
2013 spin_unlock_irq(&uport->lock);
2014 }
2015
2016 /*
2017 * Wait for the transmitter to empty.
2018 */
2019 for (tries = 3; !ops->tx_empty(uport) && tries; tries--)
2020 msleep(10);
2021 if (!tries)
2022 printk(KERN_ERR "%s%s%s%d: Unable to drain "
2023 "transmitter\n",
2024 uport->dev ? dev_name(uport->dev) : "",
2025 uport->dev ? ": " : "",
2026 drv->dev_name,
2027 drv->tty_driver->name_base + uport->line);
2028
2029 if (console_suspend_enabled || !uart_console(uport))
2030 ops->shutdown(uport);
2031 }
2032
2033 /*
2034 * Disable the console device before suspending.
2035 */
2036 if (console_suspend_enabled && uart_console(uport))
2037 console_stop(uport->cons);
2038
2039 if (console_suspend_enabled || !uart_console(uport))
2040 uart_change_pm(state, 3);
2041
2042 mutex_unlock(&port->mutex);
2043
2044 return 0;
2045}
2046
2047int uart_resume_port(struct uart_driver *drv, struct uart_port *uport)
2048{
2049 struct uart_state *state = drv->state + uport->line;
2050 struct tty_port *port = &state->port;
2051 struct device *tty_dev;
2052 struct uart_match match = {uport, drv};
2053 struct ktermios termios;
2054
2055 mutex_lock(&port->mutex);
2056
2057 tty_dev = device_find_child(uport->dev, &match, serial_match_port);
2058 if (!uport->suspended && device_may_wakeup(tty_dev)) {
2059 disable_irq_wake(uport->irq);
2060 mutex_unlock(&port->mutex);
2061 return 0;
2062 }
2063 uport->suspended = 0;
2064
2065 /*
2066 * Re-enable the console device after suspending.
2067 */
2068 if (uart_console(uport)) {
2069 uart_change_pm(state, 0);
2070 uport->ops->set_termios(uport, &termios, NULL);
2071 console_start(uport->cons);
2072 }
2073
2074 if (port->flags & ASYNC_SUSPENDED) {
2075 const struct uart_ops *ops = uport->ops;
2076 int ret;
2077
2078 uart_change_pm(state, 0);
2079 spin_lock_irq(&uport->lock);
2080 ops->set_mctrl(uport, 0);
2081 spin_unlock_irq(&uport->lock);
2082 if (console_suspend_enabled || !uart_console(uport)) {
2083 /* Protected by port mutex for now */
2084 struct tty_struct *tty = port->tty;
2085 ret = ops->startup(uport);
2086 if (ret == 0) {
2087 if (tty)
2088 uart_change_speed(tty, state, NULL);
2089 spin_lock_irq(&uport->lock);
2090 ops->set_mctrl(uport, uport->mctrl);
2091 ops->start_tx(uport);
2092 spin_unlock_irq(&uport->lock);
2093 set_bit(ASYNCB_INITIALIZED, &port->flags);
2094 } else {
2095 /*
2096 * Failed to resume - maybe hardware went away?
2097 * Clear the "initialized" flag so we won't try
2098 * to call the low level drivers shutdown method.
2099 */
2100 uart_shutdown(tty, state);
2101 }
2102 }
2103
2104 clear_bit(ASYNCB_SUSPENDED, &port->flags);
2105 }
2106
2107 mutex_unlock(&port->mutex);
2108
2109 return 0;
2110}
2111
2112static inline void
2113uart_report_port(struct uart_driver *drv, struct uart_port *port)
2114{
2115 char address[64];
2116
2117 switch (port->iotype) {
2118 case UPIO_PORT:
2119 snprintf(address, sizeof(address), "I/O 0x%lx", port->iobase);
2120 break;
2121 case UPIO_HUB6:
2122 snprintf(address, sizeof(address),
2123 "I/O 0x%lx offset 0x%x", port->iobase, port->hub6);
2124 break;
2125 case UPIO_MEM:
2126 case UPIO_MEM32:
2127 case UPIO_AU:
2128 case UPIO_TSI:
2129 case UPIO_DWAPB:
2130 snprintf(address, sizeof(address),
2131 "MMIO 0x%llx", (unsigned long long)port->mapbase);
2132 break;
2133 default:
2134 strlcpy(address, "*unknown*", sizeof(address));
2135 break;
2136 }
2137
2138 printk(KERN_INFO "%s%s%s%d at %s (irq = %d) is a %s\n",
2139 port->dev ? dev_name(port->dev) : "",
2140 port->dev ? ": " : "",
2141 drv->dev_name,
2142 drv->tty_driver->name_base + port->line,
2143 address, port->irq, uart_type(port));
2144}
2145
2146static void
2147uart_configure_port(struct uart_driver *drv, struct uart_state *state,
2148 struct uart_port *port)
2149{
2150 unsigned int flags;
2151
2152 /*
2153 * If there isn't a port here, don't do anything further.
2154 */
2155 if (!port->iobase && !port->mapbase && !port->membase)
2156 return;
2157
2158 /*
2159 * Now do the auto configuration stuff. Note that config_port
2160 * is expected to claim the resources and map the port for us.
2161 */
2162 flags = 0;
2163 if (port->flags & UPF_AUTO_IRQ)
2164 flags |= UART_CONFIG_IRQ;
2165 if (port->flags & UPF_BOOT_AUTOCONF) {
2166 if (!(port->flags & UPF_FIXED_TYPE)) {
2167 port->type = PORT_UNKNOWN;
2168 flags |= UART_CONFIG_TYPE;
2169 }
2170 port->ops->config_port(port, flags);
2171 }
2172
2173 if (port->type != PORT_UNKNOWN) {
2174 unsigned long flags;
2175
2176 uart_report_port(drv, port);
2177
2178 /* Power up port for set_mctrl() */
2179 uart_change_pm(state, 0);
2180
2181 /*
2182 * Ensure that the modem control lines are de-activated.
2183 * keep the DTR setting that is set in uart_set_options()
2184 * We probably don't need a spinlock around this, but
2185 */
2186 spin_lock_irqsave(&port->lock, flags);
2187 port->ops->set_mctrl(port, port->mctrl & TIOCM_DTR);
2188 spin_unlock_irqrestore(&port->lock, flags);
2189
2190 /*
2191 * If this driver supports console, and it hasn't been
2192 * successfully registered yet, try to re-register it.
2193 * It may be that the port was not available.
2194 */
2195 if (port->cons && !(port->cons->flags & CON_ENABLED))
2196 register_console(port->cons);
2197
2198 /*
2199 * Power down all ports by default, except the
2200 * console if we have one.
2201 */
2202 if (!uart_console(port))
2203 uart_change_pm(state, 3);
2204 }
2205}
2206
2207#ifdef CONFIG_CONSOLE_POLL
2208
2209static int uart_poll_init(struct tty_driver *driver, int line, char *options)
2210{
2211 struct uart_driver *drv = driver->driver_state;
2212 struct uart_state *state = drv->state + line;
2213 struct uart_port *port;
2214 int baud = 9600;
2215 int bits = 8;
2216 int parity = 'n';
2217 int flow = 'n';
2218
2219 if (!state || !state->uart_port)
2220 return -1;
2221
2222 port = state->uart_port;
2223 if (!(port->ops->poll_get_char && port->ops->poll_put_char))
2224 return -1;
2225
2226 if (options) {
2227 uart_parse_options(options, &baud, &parity, &bits, &flow);
2228 return uart_set_options(port, NULL, baud, parity, bits, flow);
2229 }
2230
2231 return 0;
2232}
2233
2234static int uart_poll_get_char(struct tty_driver *driver, int line)
2235{
2236 struct uart_driver *drv = driver->driver_state;
2237 struct uart_state *state = drv->state + line;
2238 struct uart_port *port;
2239
2240 if (!state || !state->uart_port)
2241 return -1;
2242
2243 port = state->uart_port;
2244 return port->ops->poll_get_char(port);
2245}
2246
2247static void uart_poll_put_char(struct tty_driver *driver, int line, char ch)
2248{
2249 struct uart_driver *drv = driver->driver_state;
2250 struct uart_state *state = drv->state + line;
2251 struct uart_port *port;
2252
2253 if (!state || !state->uart_port)
2254 return;
2255
2256 port = state->uart_port;
2257 port->ops->poll_put_char(port, ch);
2258}
2259#endif
2260
2261static const struct tty_operations uart_ops = {
2262 .open = uart_open,
2263 .close = uart_close,
2264 .write = uart_write,
2265 .put_char = uart_put_char,
2266 .flush_chars = uart_flush_chars,
2267 .write_room = uart_write_room,
2268 .chars_in_buffer= uart_chars_in_buffer,
2269 .flush_buffer = uart_flush_buffer,
2270 .ioctl = uart_ioctl,
2271 .throttle = uart_throttle,
2272 .unthrottle = uart_unthrottle,
2273 .send_xchar = uart_send_xchar,
2274 .set_termios = uart_set_termios,
2275 .set_ldisc = uart_set_ldisc,
2276 .stop = uart_stop,
2277 .start = uart_start,
2278 .hangup = uart_hangup,
2279 .break_ctl = uart_break_ctl,
2280 .wait_until_sent= uart_wait_until_sent,
2281#ifdef CONFIG_PROC_FS
2282 .proc_fops = &uart_proc_fops,
2283#endif
2284 .tiocmget = uart_tiocmget,
2285 .tiocmset = uart_tiocmset,
2286#ifdef CONFIG_CONSOLE_POLL
2287 .poll_init = uart_poll_init,
2288 .poll_get_char = uart_poll_get_char,
2289 .poll_put_char = uart_poll_put_char,
2290#endif
2291};
2292
2293static const struct tty_port_operations uart_port_ops = {
2294 .carrier_raised = uart_carrier_raised,
2295 .dtr_rts = uart_dtr_rts,
2296};
2297
2298/**
2299 * uart_register_driver - register a driver with the uart core layer
2300 * @drv: low level driver structure
2301 *
2302 * Register a uart driver with the core driver. We in turn register
2303 * with the tty layer, and initialise the core driver per-port state.
2304 *
2305 * We have a proc file in /proc/tty/driver which is named after the
2306 * normal driver.
2307 *
2308 * drv->port should be NULL, and the per-port structures should be
2309 * registered using uart_add_one_port after this call has succeeded.
2310 */
2311int uart_register_driver(struct uart_driver *drv)
2312{
2313 struct tty_driver *normal;
2314 int i, retval;
2315
2316 BUG_ON(drv->state);
2317
2318 /*
2319 * Maybe we should be using a slab cache for this, especially if
2320 * we have a large number of ports to handle.
2321 */
2322 drv->state = kzalloc(sizeof(struct uart_state) * drv->nr, GFP_KERNEL);
2323 if (!drv->state)
2324 goto out;
2325
2326 normal = alloc_tty_driver(drv->nr);
2327 if (!normal)
2328 goto out_kfree;
2329
2330 drv->tty_driver = normal;
2331
2332 normal->owner = drv->owner;
2333 normal->driver_name = drv->driver_name;
2334 normal->name = drv->dev_name;
2335 normal->major = drv->major;
2336 normal->minor_start = drv->minor;
2337 normal->type = TTY_DRIVER_TYPE_SERIAL;
2338 normal->subtype = SERIAL_TYPE_NORMAL;
2339 normal->init_termios = tty_std_termios;
2340 normal->init_termios.c_cflag = B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2341 normal->init_termios.c_ispeed = normal->init_termios.c_ospeed = 9600;
2342 normal->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
2343 normal->driver_state = drv;
2344 tty_set_operations(normal, &uart_ops);
2345
2346 /*
2347 * Initialise the UART state(s).
2348 */
2349 for (i = 0; i < drv->nr; i++) {
2350 struct uart_state *state = drv->state + i;
2351 struct tty_port *port = &state->port;
2352
2353 tty_port_init(port);
2354 port->ops = &uart_port_ops;
2355 port->close_delay = 500; /* .5 seconds */
2356 port->closing_wait = 30000; /* 30 seconds */
2357 tasklet_init(&state->tlet, uart_tasklet_action,
2358 (unsigned long)state);
2359 }
2360
2361 retval = tty_register_driver(normal);
2362 if (retval >= 0)
2363 return retval;
2364
2365 put_tty_driver(normal);
2366out_kfree:
2367 kfree(drv->state);
2368out:
2369 return -ENOMEM;
2370}
2371
2372/**
2373 * uart_unregister_driver - remove a driver from the uart core layer
2374 * @drv: low level driver structure
2375 *
2376 * Remove all references to a driver from the core driver. The low
2377 * level driver must have removed all its ports via the
2378 * uart_remove_one_port() if it registered them with uart_add_one_port().
2379 * (ie, drv->port == NULL)
2380 */
2381void uart_unregister_driver(struct uart_driver *drv)
2382{
2383 struct tty_driver *p = drv->tty_driver;
2384 tty_unregister_driver(p);
2385 put_tty_driver(p);
2386 kfree(drv->state);
2387 drv->tty_driver = NULL;
2388}
2389
2390struct tty_driver *uart_console_device(struct console *co, int *index)
2391{
2392 struct uart_driver *p = co->data;
2393 *index = co->index;
2394 return p->tty_driver;
2395}
2396
2397/**
2398 * uart_add_one_port - attach a driver-defined port structure
2399 * @drv: pointer to the uart low level driver structure for this port
2400 * @uport: uart port structure to use for this port.
2401 *
2402 * This allows the driver to register its own uart_port structure
2403 * with the core driver. The main purpose is to allow the low
2404 * level uart drivers to expand uart_port, rather than having yet
2405 * more levels of structures.
2406 */
2407int uart_add_one_port(struct uart_driver *drv, struct uart_port *uport)
2408{
2409 struct uart_state *state;
2410 struct tty_port *port;
2411 int ret = 0;
2412 struct device *tty_dev;
2413
2414 BUG_ON(in_interrupt());
2415
2416 if (uport->line >= drv->nr)
2417 return -EINVAL;
2418
2419 state = drv->state + uport->line;
2420 port = &state->port;
2421
2422 mutex_lock(&port_mutex);
2423 mutex_lock(&port->mutex);
2424 if (state->uart_port) {
2425 ret = -EINVAL;
2426 goto out;
2427 }
2428
2429 state->uart_port = uport;
2430 state->pm_state = -1;
2431
2432 uport->cons = drv->cons;
2433 uport->state = state;
2434
2435 /*
2436 * If this port is a console, then the spinlock is already
2437 * initialised.
2438 */
2439 if (!(uart_console(uport) && (uport->cons->flags & CON_ENABLED))) {
2440 spin_lock_init(&uport->lock);
2441 lockdep_set_class(&uport->lock, &port_lock_key);
2442 }
2443
2444 uart_configure_port(drv, state, uport);
2445
2446 /*
2447 * Register the port whether it's detected or not. This allows
2448 * setserial to be used to alter this ports parameters.
2449 */
2450 tty_dev = tty_register_device(drv->tty_driver, uport->line, uport->dev);
2451 if (likely(!IS_ERR(tty_dev))) {
2452 device_init_wakeup(tty_dev, 1);
2453 device_set_wakeup_enable(tty_dev, 0);
2454 } else
2455 printk(KERN_ERR "Cannot register tty device on line %d\n",
2456 uport->line);
2457
2458 /*
2459 * Ensure UPF_DEAD is not set.
2460 */
2461 uport->flags &= ~UPF_DEAD;
2462
2463 out:
2464 mutex_unlock(&port->mutex);
2465 mutex_unlock(&port_mutex);
2466
2467 return ret;
2468}
2469
2470/**
2471 * uart_remove_one_port - detach a driver defined port structure
2472 * @drv: pointer to the uart low level driver structure for this port
2473 * @uport: uart port structure for this port
2474 *
2475 * This unhooks (and hangs up) the specified port structure from the
2476 * core driver. No further calls will be made to the low-level code
2477 * for this port.
2478 */
2479int uart_remove_one_port(struct uart_driver *drv, struct uart_port *uport)
2480{
2481 struct uart_state *state = drv->state + uport->line;
2482 struct tty_port *port = &state->port;
2483
2484 BUG_ON(in_interrupt());
2485
2486 if (state->uart_port != uport)
2487 printk(KERN_ALERT "Removing wrong port: %p != %p\n",
2488 state->uart_port, uport);
2489
2490 mutex_lock(&port_mutex);
2491
2492 /*
2493 * Mark the port "dead" - this prevents any opens from
2494 * succeeding while we shut down the port.
2495 */
2496 mutex_lock(&port->mutex);
2497 uport->flags |= UPF_DEAD;
2498 mutex_unlock(&port->mutex);
2499
2500 /*
2501 * Remove the devices from the tty layer
2502 */
2503 tty_unregister_device(drv->tty_driver, uport->line);
2504
2505 if (port->tty)
2506 tty_vhangup(port->tty);
2507
2508 /*
2509 * Free the port IO and memory resources, if any.
2510 */
2511 if (uport->type != PORT_UNKNOWN)
2512 uport->ops->release_port(uport);
2513
2514 /*
2515 * Indicate that there isn't a port here anymore.
2516 */
2517 uport->type = PORT_UNKNOWN;
2518
2519 /*
2520 * Kill the tasklet, and free resources.
2521 */
2522 tasklet_kill(&state->tlet);
2523
2524 state->uart_port = NULL;
2525 mutex_unlock(&port_mutex);
2526
2527 return 0;
2528}
2529
2530/*
2531 * Are the two ports equivalent?
2532 */
2533int uart_match_port(struct uart_port *port1, struct uart_port *port2)
2534{
2535 if (port1->iotype != port2->iotype)
2536 return 0;
2537
2538 switch (port1->iotype) {
2539 case UPIO_PORT:
2540 return (port1->iobase == port2->iobase);
2541 case UPIO_HUB6:
2542 return (port1->iobase == port2->iobase) &&
2543 (port1->hub6 == port2->hub6);
2544 case UPIO_MEM:
2545 case UPIO_MEM32:
2546 case UPIO_AU:
2547 case UPIO_TSI:
2548 case UPIO_DWAPB:
2549 return (port1->mapbase == port2->mapbase);
2550 }
2551 return 0;
2552}
2553EXPORT_SYMBOL(uart_match_port);
2554
2555EXPORT_SYMBOL(uart_write_wakeup);
2556EXPORT_SYMBOL(uart_register_driver);
2557EXPORT_SYMBOL(uart_unregister_driver);
2558EXPORT_SYMBOL(uart_suspend_port);
2559EXPORT_SYMBOL(uart_resume_port);
2560EXPORT_SYMBOL(uart_add_one_port);
2561EXPORT_SYMBOL(uart_remove_one_port);
2562
2563MODULE_DESCRIPTION("Serial driver core");
2564MODULE_LICENSE("GPL");
diff --git a/drivers/serial/serial_cs.c b/drivers/serial/serial_cs.c
deleted file mode 100644
index 7d475b2a79e8..000000000000
--- a/drivers/serial/serial_cs.c
+++ /dev/null
@@ -1,920 +0,0 @@
1/*======================================================================
2
3 A driver for PCMCIA serial devices
4
5 serial_cs.c 1.134 2002/05/04 05:48:53
6
7 The contents of this file are subject to the Mozilla Public
8 License Version 1.1 (the "License"); you may not use this file
9 except in compliance with the License. You may obtain a copy of
10 the License at http://www.mozilla.org/MPL/
11
12 Software distributed under the License is distributed on an "AS
13 IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
14 implied. See the License for the specific language governing
15 rights and limitations under the License.
16
17 The initial developer of the original code is David A. Hinds
18 <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
19 are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
20
21 Alternatively, the contents of this file may be used under the
22 terms of the GNU General Public License version 2 (the "GPL"), in which
23 case the provisions of the GPL are applicable instead of the
24 above. If you wish to allow the use of your version of this file
25 only under the terms of the GPL and not to allow others to use
26 your version of this file under the MPL, indicate your decision
27 by deleting the provisions above and replace them with the notice
28 and other provisions required by the GPL. If you do not delete
29 the provisions above, a recipient may use your version of this
30 file under either the MPL or the GPL.
31
32======================================================================*/
33
34#include <linux/module.h>
35#include <linux/moduleparam.h>
36#include <linux/kernel.h>
37#include <linux/init.h>
38#include <linux/ptrace.h>
39#include <linux/slab.h>
40#include <linux/string.h>
41#include <linux/timer.h>
42#include <linux/serial_core.h>
43#include <linux/delay.h>
44#include <linux/major.h>
45#include <asm/io.h>
46#include <asm/system.h>
47
48#include <pcmcia/cs.h>
49#include <pcmcia/cistpl.h>
50#include <pcmcia/ciscode.h>
51#include <pcmcia/ds.h>
52#include <pcmcia/cisreg.h>
53
54#include "8250.h"
55
56
57/*====================================================================*/
58
59/* Parameters that can be set with 'insmod' */
60
61/* Enable the speaker? */
62static int do_sound = 1;
63/* Skip strict UART tests? */
64static int buggy_uart;
65
66module_param(do_sound, int, 0444);
67module_param(buggy_uart, int, 0444);
68
69/*====================================================================*/
70
71/* Table of multi-port card ID's */
72
73struct serial_quirk {
74 unsigned int manfid;
75 unsigned int prodid;
76 int multi; /* 1 = multifunction, > 1 = # ports */
77 void (*config)(struct pcmcia_device *);
78 void (*setup)(struct pcmcia_device *, struct uart_port *);
79 void (*wakeup)(struct pcmcia_device *);
80 int (*post)(struct pcmcia_device *);
81};
82
83struct serial_info {
84 struct pcmcia_device *p_dev;
85 int ndev;
86 int multi;
87 int slave;
88 int manfid;
89 int prodid;
90 int c950ctrl;
91 int line[4];
92 const struct serial_quirk *quirk;
93};
94
95struct serial_cfg_mem {
96 tuple_t tuple;
97 cisparse_t parse;
98 u_char buf[256];
99};
100
101/*
102 * vers_1 5.0, "Brain Boxes", "2-Port RS232 card", "r6"
103 * manfid 0x0160, 0x0104
104 * This card appears to have a 14.7456MHz clock.
105 */
106/* Generic Modem: MD55x (GPRS/EDGE) have
107 * Elan VPU16551 UART with 14.7456MHz oscillator
108 * manfid 0x015D, 0x4C45
109 */
110static void quirk_setup_brainboxes_0104(struct pcmcia_device *link, struct uart_port *port)
111{
112 port->uartclk = 14745600;
113}
114
115static int quirk_post_ibm(struct pcmcia_device *link)
116{
117 u8 val;
118 int ret;
119
120 ret = pcmcia_read_config_byte(link, 0x800, &val);
121 if (ret)
122 goto failed;
123
124 ret = pcmcia_write_config_byte(link, 0x800, val | 1);
125 if (ret)
126 goto failed;
127 return 0;
128
129 failed:
130 return -ENODEV;
131}
132
133/*
134 * Nokia cards are not really multiport cards. Shouldn't this
135 * be handled by setting the quirk entry .multi = 0 | 1 ?
136 */
137static void quirk_config_nokia(struct pcmcia_device *link)
138{
139 struct serial_info *info = link->priv;
140
141 if (info->multi > 1)
142 info->multi = 1;
143}
144
145static void quirk_wakeup_oxsemi(struct pcmcia_device *link)
146{
147 struct serial_info *info = link->priv;
148
149 if (info->c950ctrl)
150 outb(12, info->c950ctrl + 1);
151}
152
153/* request_region? oxsemi branch does no request_region too... */
154/*
155 * This sequence is needed to properly initialize MC45 attached to OXCF950.
156 * I tried decreasing these msleep()s, but it worked properly (survived
157 * 1000 stop/start operations) with these timeouts (or bigger).
158 */
159static void quirk_wakeup_possio_gcc(struct pcmcia_device *link)
160{
161 struct serial_info *info = link->priv;
162 unsigned int ctrl = info->c950ctrl;
163
164 outb(0xA, ctrl + 1);
165 msleep(100);
166 outb(0xE, ctrl + 1);
167 msleep(300);
168 outb(0xC, ctrl + 1);
169 msleep(100);
170 outb(0xE, ctrl + 1);
171 msleep(200);
172 outb(0xF, ctrl + 1);
173 msleep(100);
174 outb(0xE, ctrl + 1);
175 msleep(100);
176 outb(0xC, ctrl + 1);
177}
178
179/*
180 * Socket Dual IO: this enables irq's for second port
181 */
182static void quirk_config_socket(struct pcmcia_device *link)
183{
184 struct serial_info *info = link->priv;
185
186 if (info->multi) {
187 link->conf.Present |= PRESENT_EXT_STATUS;
188 link->conf.ExtStatus = ESR_REQ_ATTN_ENA;
189 }
190}
191
192static const struct serial_quirk quirks[] = {
193 {
194 .manfid = 0x0160,
195 .prodid = 0x0104,
196 .multi = -1,
197 .setup = quirk_setup_brainboxes_0104,
198 }, {
199 .manfid = 0x015D,
200 .prodid = 0x4C45,
201 .multi = -1,
202 .setup = quirk_setup_brainboxes_0104,
203 }, {
204 .manfid = MANFID_IBM,
205 .prodid = ~0,
206 .multi = -1,
207 .post = quirk_post_ibm,
208 }, {
209 .manfid = MANFID_INTEL,
210 .prodid = PRODID_INTEL_DUAL_RS232,
211 .multi = 2,
212 }, {
213 .manfid = MANFID_NATINST,
214 .prodid = PRODID_NATINST_QUAD_RS232,
215 .multi = 4,
216 }, {
217 .manfid = MANFID_NOKIA,
218 .prodid = ~0,
219 .multi = -1,
220 .config = quirk_config_nokia,
221 }, {
222 .manfid = MANFID_OMEGA,
223 .prodid = PRODID_OMEGA_QSP_100,
224 .multi = 4,
225 }, {
226 .manfid = MANFID_OXSEMI,
227 .prodid = ~0,
228 .multi = -1,
229 .wakeup = quirk_wakeup_oxsemi,
230 }, {
231 .manfid = MANFID_POSSIO,
232 .prodid = PRODID_POSSIO_GCC,
233 .multi = -1,
234 .wakeup = quirk_wakeup_possio_gcc,
235 }, {
236 .manfid = MANFID_QUATECH,
237 .prodid = PRODID_QUATECH_DUAL_RS232,
238 .multi = 2,
239 }, {
240 .manfid = MANFID_QUATECH,
241 .prodid = PRODID_QUATECH_DUAL_RS232_D1,
242 .multi = 2,
243 }, {
244 .manfid = MANFID_QUATECH,
245 .prodid = PRODID_QUATECH_DUAL_RS232_G,
246 .multi = 2,
247 }, {
248 .manfid = MANFID_QUATECH,
249 .prodid = PRODID_QUATECH_QUAD_RS232,
250 .multi = 4,
251 }, {
252 .manfid = MANFID_SOCKET,
253 .prodid = PRODID_SOCKET_DUAL_RS232,
254 .multi = 2,
255 .config = quirk_config_socket,
256 }, {
257 .manfid = MANFID_SOCKET,
258 .prodid = ~0,
259 .multi = -1,
260 .config = quirk_config_socket,
261 }
262};
263
264
265static int serial_config(struct pcmcia_device * link);
266
267
268/*======================================================================
269
270 After a card is removed, serial_remove() will unregister
271 the serial device(s), and release the PCMCIA configuration.
272
273======================================================================*/
274
275static void serial_remove(struct pcmcia_device *link)
276{
277 struct serial_info *info = link->priv;
278 int i;
279
280 dev_dbg(&link->dev, "serial_release\n");
281
282 /*
283 * Recheck to see if the device is still configured.
284 */
285 for (i = 0; i < info->ndev; i++)
286 serial8250_unregister_port(info->line[i]);
287
288 if (!info->slave)
289 pcmcia_disable_device(link);
290}
291
292static int serial_suspend(struct pcmcia_device *link)
293{
294 struct serial_info *info = link->priv;
295 int i;
296
297 for (i = 0; i < info->ndev; i++)
298 serial8250_suspend_port(info->line[i]);
299
300 return 0;
301}
302
303static int serial_resume(struct pcmcia_device *link)
304{
305 struct serial_info *info = link->priv;
306 int i;
307
308 for (i = 0; i < info->ndev; i++)
309 serial8250_resume_port(info->line[i]);
310
311 if (info->quirk && info->quirk->wakeup)
312 info->quirk->wakeup(link);
313
314 return 0;
315}
316
317/*======================================================================
318
319 serial_attach() creates an "instance" of the driver, allocating
320 local data structures for one device. The device is registered
321 with Card Services.
322
323======================================================================*/
324
325static int serial_probe(struct pcmcia_device *link)
326{
327 struct serial_info *info;
328
329 dev_dbg(&link->dev, "serial_attach()\n");
330
331 /* Create new serial device */
332 info = kzalloc(sizeof (*info), GFP_KERNEL);
333 if (!info)
334 return -ENOMEM;
335 info->p_dev = link;
336 link->priv = info;
337
338 link->conf.Attributes = CONF_ENABLE_IRQ;
339 if (do_sound) {
340 link->conf.Attributes |= CONF_ENABLE_SPKR;
341 link->conf.Status = CCSR_AUDIO_ENA;
342 }
343 link->conf.IntType = INT_MEMORY_AND_IO;
344
345 return serial_config(link);
346}
347
348/*======================================================================
349
350 This deletes a driver "instance". The device is de-registered
351 with Card Services. If it has been released, all local data
352 structures are freed. Otherwise, the structures will be freed
353 when the device is released.
354
355======================================================================*/
356
357static void serial_detach(struct pcmcia_device *link)
358{
359 struct serial_info *info = link->priv;
360
361 dev_dbg(&link->dev, "serial_detach\n");
362
363 /*
364 * Ensure any outstanding scheduled tasks are completed.
365 */
366 flush_scheduled_work();
367
368 /*
369 * Ensure that the ports have been released.
370 */
371 serial_remove(link);
372
373 /* free bits */
374 kfree(info);
375}
376
377/*====================================================================*/
378
379static int setup_serial(struct pcmcia_device *handle, struct serial_info * info,
380 unsigned int iobase, int irq)
381{
382 struct uart_port port;
383 int line;
384
385 memset(&port, 0, sizeof (struct uart_port));
386 port.iobase = iobase;
387 port.irq = irq;
388 port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ;
389 port.uartclk = 1843200;
390 port.dev = &handle->dev;
391 if (buggy_uart)
392 port.flags |= UPF_BUGGY_UART;
393
394 if (info->quirk && info->quirk->setup)
395 info->quirk->setup(handle, &port);
396
397 line = serial8250_register_port(&port);
398 if (line < 0) {
399 printk(KERN_NOTICE "serial_cs: serial8250_register_port() at "
400 "0x%04lx, irq %d failed\n", (u_long)iobase, irq);
401 return -EINVAL;
402 }
403
404 info->line[info->ndev] = line;
405 info->ndev++;
406
407 return 0;
408}
409
410/*====================================================================*/
411
412static int pfc_config(struct pcmcia_device *p_dev)
413{
414 unsigned int port = 0;
415 struct serial_info *info = p_dev->priv;
416
417 if ((p_dev->resource[1]->end != 0) &&
418 (resource_size(p_dev->resource[1]) == 8)) {
419 port = p_dev->resource[1]->start;
420 info->slave = 1;
421 } else if ((info->manfid == MANFID_OSITECH) &&
422 (resource_size(p_dev->resource[0]) == 0x40)) {
423 port = p_dev->resource[0]->start + 0x28;
424 info->slave = 1;
425 }
426 if (info->slave)
427 return setup_serial(p_dev, info, port, p_dev->irq);
428
429 dev_warn(&p_dev->dev, "no usable port range found, giving up\n");
430 return -ENODEV;
431}
432
433static int simple_config_check(struct pcmcia_device *p_dev,
434 cistpl_cftable_entry_t *cf,
435 cistpl_cftable_entry_t *dflt,
436 unsigned int vcc,
437 void *priv_data)
438{
439 static const int size_table[2] = { 8, 16 };
440 int *try = priv_data;
441
442 if (cf->vpp1.present & (1 << CISTPL_POWER_VNOM))
443 p_dev->conf.Vpp =
444 cf->vpp1.param[CISTPL_POWER_VNOM] / 10000;
445
446 p_dev->io_lines = ((*try & 0x1) == 0) ?
447 16 : cf->io.flags & CISTPL_IO_LINES_MASK;
448
449 if ((cf->io.nwin > 0) && (cf->io.win[0].len == size_table[(*try >> 1)])
450 && (cf->io.win[0].base != 0)) {
451 p_dev->resource[0]->start = cf->io.win[0].base;
452 if (!pcmcia_request_io(p_dev))
453 return 0;
454 }
455 return -EINVAL;
456}
457
458static int simple_config_check_notpicky(struct pcmcia_device *p_dev,
459 cistpl_cftable_entry_t *cf,
460 cistpl_cftable_entry_t *dflt,
461 unsigned int vcc,
462 void *priv_data)
463{
464 static const unsigned int base[5] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, 0x0 };
465 int j;
466
467 if ((cf->io.nwin > 0) && ((cf->io.flags & CISTPL_IO_LINES_MASK) <= 3)) {
468 for (j = 0; j < 5; j++) {
469 p_dev->resource[0]->start = base[j];
470 p_dev->io_lines = base[j] ? 16 : 3;
471 if (!pcmcia_request_io(p_dev))
472 return 0;
473 }
474 }
475 return -ENODEV;
476}
477
478static int simple_config(struct pcmcia_device *link)
479{
480 struct serial_info *info = link->priv;
481 int i = -ENODEV, try;
482
483 link->resource[0]->flags |= IO_DATA_PATH_WIDTH_8;
484 link->resource[0]->end = 8;
485
486 /* First pass: look for a config entry that looks normal.
487 * Two tries: without IO aliases, then with aliases */
488 for (try = 0; try < 4; try++)
489 if (!pcmcia_loop_config(link, simple_config_check, &try))
490 goto found_port;
491
492 /* Second pass: try to find an entry that isn't picky about
493 its base address, then try to grab any standard serial port
494 address, and finally try to get any free port. */
495 if (!pcmcia_loop_config(link, simple_config_check_notpicky, NULL))
496 goto found_port;
497
498 dev_warn(&link->dev, "no usable port range found, giving up\n");
499 return -1;
500
501found_port:
502 if (info->multi && (info->manfid == MANFID_3COM))
503 link->conf.ConfigIndex &= ~(0x08);
504
505 /*
506 * Apply any configuration quirks.
507 */
508 if (info->quirk && info->quirk->config)
509 info->quirk->config(link);
510
511 i = pcmcia_request_configuration(link, &link->conf);
512 if (i != 0)
513 return -1;
514 return setup_serial(link, info, link->resource[0]->start, link->irq);
515}
516
517static int multi_config_check(struct pcmcia_device *p_dev,
518 cistpl_cftable_entry_t *cf,
519 cistpl_cftable_entry_t *dflt,
520 unsigned int vcc,
521 void *priv_data)
522{
523 int *base2 = priv_data;
524
525 /* The quad port cards have bad CIS's, so just look for a
526 window larger than 8 ports and assume it will be right */
527 if ((cf->io.nwin == 1) && (cf->io.win[0].len > 8)) {
528 p_dev->resource[0]->start = cf->io.win[0].base;
529 p_dev->io_lines = cf->io.flags & CISTPL_IO_LINES_MASK;
530 if (!pcmcia_request_io(p_dev)) {
531 *base2 = p_dev->resource[0]->start + 8;
532 return 0;
533 }
534 }
535 return -ENODEV;
536}
537
538static int multi_config_check_notpicky(struct pcmcia_device *p_dev,
539 cistpl_cftable_entry_t *cf,
540 cistpl_cftable_entry_t *dflt,
541 unsigned int vcc,
542 void *priv_data)
543{
544 int *base2 = priv_data;
545
546 if (cf->io.nwin == 2) {
547 p_dev->resource[0]->start = cf->io.win[0].base;
548 p_dev->resource[1]->start = cf->io.win[1].base;
549 p_dev->io_lines = cf->io.flags & CISTPL_IO_LINES_MASK;
550 if (!pcmcia_request_io(p_dev)) {
551 *base2 = p_dev->resource[1]->start;
552 return 0;
553 }
554 }
555 return -ENODEV;
556}
557
558static int multi_config(struct pcmcia_device *link)
559{
560 struct serial_info *info = link->priv;
561 int i, base2 = 0;
562
563 /* First, look for a generic full-sized window */
564 link->resource[0]->flags |= IO_DATA_PATH_WIDTH_8;
565 link->resource[0]->end = info->multi * 8;
566 if (pcmcia_loop_config(link, multi_config_check, &base2)) {
567 /* If that didn't work, look for two windows */
568 link->resource[0]->end = link->resource[1]->end = 8;
569 info->multi = 2;
570 if (pcmcia_loop_config(link, multi_config_check_notpicky,
571 &base2)) {
572 dev_warn(&link->dev, "no usable port range "
573 "found, giving up\n");
574 return -ENODEV;
575 }
576 }
577
578 if (!link->irq)
579 dev_warn(&link->dev, "no usable IRQ found, continuing...\n");
580
581 /*
582 * Apply any configuration quirks.
583 */
584 if (info->quirk && info->quirk->config)
585 info->quirk->config(link);
586
587 i = pcmcia_request_configuration(link, &link->conf);
588 if (i != 0)
589 return -ENODEV;
590
591 /* The Oxford Semiconductor OXCF950 cards are in fact single-port:
592 * 8 registers are for the UART, the others are extra registers.
593 * Siemen's MC45 PCMCIA (Possio's GCC) is OXCF950 based too.
594 */
595 if (info->manfid == MANFID_OXSEMI || (info->manfid == MANFID_POSSIO &&
596 info->prodid == PRODID_POSSIO_GCC)) {
597 int err;
598
599 if (link->conf.ConfigIndex == 1 ||
600 link->conf.ConfigIndex == 3) {
601 err = setup_serial(link, info, base2,
602 link->irq);
603 base2 = link->resource[0]->start;;
604 } else {
605 err = setup_serial(link, info, link->resource[0]->start,
606 link->irq);
607 }
608 info->c950ctrl = base2;
609
610 /*
611 * FIXME: We really should wake up the port prior to
612 * handing it over to the serial layer.
613 */
614 if (info->quirk && info->quirk->wakeup)
615 info->quirk->wakeup(link);
616
617 return 0;
618 }
619
620 setup_serial(link, info, link->resource[0]->start, link->irq);
621 for (i = 0; i < info->multi - 1; i++)
622 setup_serial(link, info, base2 + (8 * i),
623 link->irq);
624 return 0;
625}
626
627static int serial_check_for_multi(struct pcmcia_device *p_dev,
628 cistpl_cftable_entry_t *cf,
629 cistpl_cftable_entry_t *dflt,
630 unsigned int vcc,
631 void *priv_data)
632{
633 struct serial_info *info = p_dev->priv;
634
635 if ((cf->io.nwin == 1) && (cf->io.win[0].len % 8 == 0))
636 info->multi = cf->io.win[0].len >> 3;
637
638 if ((cf->io.nwin == 2) && (cf->io.win[0].len == 8) &&
639 (cf->io.win[1].len == 8))
640 info->multi = 2;
641
642 return 0; /* break */
643}
644
645
646/*======================================================================
647
648 serial_config() is scheduled to run after a CARD_INSERTION event
649 is received, to configure the PCMCIA socket, and to make the
650 serial device available to the system.
651
652======================================================================*/
653
654static int serial_config(struct pcmcia_device * link)
655{
656 struct serial_info *info = link->priv;
657 int i;
658
659 dev_dbg(&link->dev, "serial_config\n");
660
661 /* Is this a compliant multifunction card? */
662 info->multi = (link->socket->functions > 1);
663
664 /* Is this a multiport card? */
665 info->manfid = link->manf_id;
666 info->prodid = link->card_id;
667
668 for (i = 0; i < ARRAY_SIZE(quirks); i++)
669 if ((quirks[i].manfid == ~0 ||
670 quirks[i].manfid == info->manfid) &&
671 (quirks[i].prodid == ~0 ||
672 quirks[i].prodid == info->prodid)) {
673 info->quirk = &quirks[i];
674 break;
675 }
676
677 /* Another check for dual-serial cards: look for either serial or
678 multifunction cards that ask for appropriate IO port ranges */
679 if ((info->multi == 0) &&
680 (link->has_func_id) &&
681 (link->socket->pcmcia_pfc == 0) &&
682 ((link->func_id == CISTPL_FUNCID_MULTI) ||
683 (link->func_id == CISTPL_FUNCID_SERIAL)))
684 pcmcia_loop_config(link, serial_check_for_multi, info);
685
686 /*
687 * Apply any multi-port quirk.
688 */
689 if (info->quirk && info->quirk->multi != -1)
690 info->multi = info->quirk->multi;
691
692 dev_info(&link->dev,
693 "trying to set up [0x%04x:0x%04x] (pfc: %d, multi: %d, quirk: %p)\n",
694 link->manf_id, link->card_id,
695 link->socket->pcmcia_pfc, info->multi, info->quirk);
696 if (link->socket->pcmcia_pfc)
697 i = pfc_config(link);
698 else if (info->multi > 1)
699 i = multi_config(link);
700 else
701 i = simple_config(link);
702
703 if (i || info->ndev == 0)
704 goto failed;
705
706 /*
707 * Apply any post-init quirk. FIXME: This should really happen
708 * before we register the port, since it might already be in use.
709 */
710 if (info->quirk && info->quirk->post)
711 if (info->quirk->post(link))
712 goto failed;
713
714 return 0;
715
716failed:
717 dev_warn(&link->dev, "failed to initialize\n");
718 serial_remove(link);
719 return -ENODEV;
720}
721
722static struct pcmcia_device_id serial_ids[] = {
723 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0057, 0x0021),
724 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0089, 0x110a),
725 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0104, 0x000a),
726 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0105, 0x0d0a),
727 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0105, 0x0e0a),
728 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0105, 0xea15),
729 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0109, 0x0501),
730 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0138, 0x110a),
731 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0140, 0x000a),
732 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0143, 0x3341),
733 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0143, 0xc0ab),
734 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x016c, 0x0081),
735 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x021b, 0x0101),
736 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x08a1, 0xc0ab),
737 PCMCIA_PFC_DEVICE_PROD_ID123(1, "MEGAHERTZ", "CC/XJEM3288", "DATA/FAX/CELL ETHERNET MODEM", 0xf510db04, 0x04cd2988, 0x46a52d63),
738 PCMCIA_PFC_DEVICE_PROD_ID123(1, "MEGAHERTZ", "CC/XJEM3336", "DATA/FAX/CELL ETHERNET MODEM", 0xf510db04, 0x0143b773, 0x46a52d63),
739 PCMCIA_PFC_DEVICE_PROD_ID123(1, "MEGAHERTZ", "EM1144T", "PCMCIA MODEM", 0xf510db04, 0x856d66c8, 0xbd6c43ef),
740 PCMCIA_PFC_DEVICE_PROD_ID123(1, "MEGAHERTZ", "XJEM1144/CCEM1144", "PCMCIA MODEM", 0xf510db04, 0x52d21e1e, 0xbd6c43ef),
741 PCMCIA_PFC_DEVICE_PROD_ID13(1, "Xircom", "CEM28", 0x2e3ee845, 0x0ea978ea),
742 PCMCIA_PFC_DEVICE_PROD_ID13(1, "Xircom", "CEM33", 0x2e3ee845, 0x80609023),
743 PCMCIA_PFC_DEVICE_PROD_ID13(1, "Xircom", "CEM56", 0x2e3ee845, 0xa650c32a),
744 PCMCIA_PFC_DEVICE_PROD_ID13(1, "Xircom", "REM10", 0x2e3ee845, 0x76df1d29),
745 PCMCIA_PFC_DEVICE_PROD_ID13(1, "Xircom", "XEM5600", 0x2e3ee845, 0xf1403719),
746 PCMCIA_PFC_DEVICE_PROD_ID12(1, "AnyCom", "Fast Ethernet + 56K COMBO", 0x578ba6e7, 0xb0ac62c4),
747 PCMCIA_PFC_DEVICE_PROD_ID12(1, "ATKK", "LM33-PCM-T", 0xba9eb7e2, 0x077c174e),
748 PCMCIA_PFC_DEVICE_PROD_ID12(1, "D-Link", "DME336T", 0x1a424a1c, 0xb23897ff),
749 PCMCIA_PFC_DEVICE_PROD_ID12(1, "Gateway 2000", "XJEM3336", 0xdd9989be, 0x662c394c),
750 PCMCIA_PFC_DEVICE_PROD_ID12(1, "Grey Cell", "GCS3000", 0x2a151fac, 0x48b932ae),
751 PCMCIA_PFC_DEVICE_PROD_ID12(1, "Linksys", "EtherFast 10&100 + 56K PC Card (PCMLM56)", 0x0733cc81, 0xb3765033),
752 PCMCIA_PFC_DEVICE_PROD_ID12(1, "LINKSYS", "PCMLM336", 0xf7cb0b07, 0x7a821b58),
753 PCMCIA_PFC_DEVICE_PROD_ID12(1, "MEGAHERTZ", "XJEM1144/CCEM1144", 0xf510db04, 0x52d21e1e),
754 PCMCIA_PFC_DEVICE_PROD_ID12(1, "MICRO RESEARCH", "COMBO-L/M-336", 0xb2ced065, 0x3ced0555),
755 PCMCIA_PFC_DEVICE_PROD_ID12(1, "NEC", "PK-UG-J001" ,0x18df0ba0 ,0x831b1064),
756 PCMCIA_PFC_DEVICE_PROD_ID12(1, "Ositech", "Trumpcard:Jack of Diamonds Modem+Ethernet", 0xc2f80cd, 0x656947b9),
757 PCMCIA_PFC_DEVICE_PROD_ID12(1, "Ositech", "Trumpcard:Jack of Hearts Modem+Ethernet", 0xc2f80cd, 0xdc9ba5ed),
758 PCMCIA_PFC_DEVICE_PROD_ID12(1, "PCMCIAs", "ComboCard", 0xdcfe12d3, 0xcd8906cc),
759 PCMCIA_PFC_DEVICE_PROD_ID12(1, "PCMCIAs", "LanModem", 0xdcfe12d3, 0xc67c648f),
760 PCMCIA_PFC_DEVICE_PROD_ID12(1, "TDK", "GlobalNetworker 3410/3412", 0x1eae9475, 0xd9a93bed),
761 PCMCIA_PFC_DEVICE_PROD_ID12(1, "Xircom", "CreditCard Ethernet+Modem II", 0x2e3ee845, 0xeca401bf),
762 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0032, 0x0e01),
763 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0032, 0x0a05),
764 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0032, 0x1101),
765 PCMCIA_MFC_DEVICE_MANF_CARD(0, 0x0104, 0x0070),
766 PCMCIA_MFC_DEVICE_MANF_CARD(1, 0x0101, 0x0562),
767 PCMCIA_MFC_DEVICE_MANF_CARD(1, 0x0104, 0x0070),
768 PCMCIA_MFC_DEVICE_MANF_CARD(1, 0x016c, 0x0020),
769 PCMCIA_MFC_DEVICE_PROD_ID123(1, "APEX DATA", "MULTICARD", "ETHERNET-MODEM", 0x11c2da09, 0x7289dc5d, 0xaad95e1f),
770 PCMCIA_MFC_DEVICE_PROD_ID12(1, "IBM", "Home and Away 28.8 PC Card ", 0xb569a6e5, 0x5bd4ff2c),
771 PCMCIA_MFC_DEVICE_PROD_ID12(1, "IBM", "Home and Away Credit Card Adapter", 0xb569a6e5, 0x4bdf15c3),
772 PCMCIA_MFC_DEVICE_PROD_ID12(1, "IBM", "w95 Home and Away Credit Card ", 0xb569a6e5, 0xae911c15),
773 PCMCIA_MFC_DEVICE_PROD_ID1(1, "Motorola MARQUIS", 0xf03e4e77),
774 PCMCIA_MFC_DEVICE_PROD_ID2(1, "FAX/Modem/Ethernet Combo Card ", 0x1ed59302),
775 PCMCIA_DEVICE_MANF_CARD(0x0089, 0x0301),
776 PCMCIA_DEVICE_MANF_CARD(0x00a4, 0x0276),
777 PCMCIA_DEVICE_MANF_CARD(0x0101, 0x0039),
778 PCMCIA_DEVICE_MANF_CARD(0x0104, 0x0006),
779 PCMCIA_DEVICE_MANF_CARD(0x0105, 0x0101), /* TDK DF2814 */
780 PCMCIA_DEVICE_MANF_CARD(0x0105, 0x100a), /* Xircom CM-56G */
781 PCMCIA_DEVICE_MANF_CARD(0x0105, 0x3e0a), /* TDK DF5660 */
782 PCMCIA_DEVICE_MANF_CARD(0x0105, 0x410a),
783 PCMCIA_DEVICE_MANF_CARD(0x0107, 0x0002), /* USRobotics 14,400 */
784 PCMCIA_DEVICE_MANF_CARD(0x010b, 0x0d50),
785 PCMCIA_DEVICE_MANF_CARD(0x010b, 0x0d51),
786 PCMCIA_DEVICE_MANF_CARD(0x010b, 0x0d52),
787 PCMCIA_DEVICE_MANF_CARD(0x010b, 0x0d53),
788 PCMCIA_DEVICE_MANF_CARD(0x010b, 0xd180),
789 PCMCIA_DEVICE_MANF_CARD(0x0115, 0x3330), /* USRobotics/SUN 14,400 */
790 PCMCIA_DEVICE_MANF_CARD(0x0124, 0x0100), /* Nokia DTP-2 ver II */
791 PCMCIA_DEVICE_MANF_CARD(0x0134, 0x5600), /* LASAT COMMUNICATIONS A/S */
792 PCMCIA_DEVICE_MANF_CARD(0x0137, 0x000e),
793 PCMCIA_DEVICE_MANF_CARD(0x0137, 0x001b),
794 PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0025),
795 PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0045),
796 PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0052),
797 PCMCIA_DEVICE_MANF_CARD(0x016c, 0x0006), /* Psion 56K+Fax */
798 PCMCIA_DEVICE_MANF_CARD(0x0200, 0x0001), /* MultiMobile */
799 PCMCIA_DEVICE_PROD_ID134("ADV", "TECH", "COMpad-32/85", 0x67459937, 0x916d02ba, 0x8fbe92ae),
800 PCMCIA_DEVICE_PROD_ID124("GATEWAY2000", "CC3144", "PCMCIA MODEM", 0x506bccae, 0xcb3685f1, 0xbd6c43ef),
801 PCMCIA_DEVICE_PROD_ID14("MEGAHERTZ", "PCMCIA MODEM", 0xf510db04, 0xbd6c43ef),
802 PCMCIA_DEVICE_PROD_ID124("TOSHIBA", "T144PF", "PCMCIA MODEM", 0xb4585a1a, 0x7271409c, 0xbd6c43ef),
803 PCMCIA_DEVICE_PROD_ID123("FUJITSU", "FC14F ", "MBH10213", 0x6ee5a3d8, 0x30ead12b, 0xb00f05a0),
804 PCMCIA_DEVICE_PROD_ID123("Novatel Wireless", "Merlin UMTS Modem", "U630", 0x32607776, 0xd9e73b13, 0xe87332e),
805 PCMCIA_DEVICE_PROD_ID13("MEGAHERTZ", "V.34 PCMCIA MODEM", 0xf510db04, 0xbb2cce4a),
806 PCMCIA_DEVICE_PROD_ID12("Brain Boxes", "Bluetooth PC Card", 0xee138382, 0xd4ce9b02),
807 PCMCIA_DEVICE_PROD_ID12("CIRRUS LOGIC", "FAX MODEM", 0xe625f451, 0xcecd6dfa),
808 PCMCIA_DEVICE_PROD_ID12("COMPAQ", "PCMCIA 28800 FAX/DATA MODEM", 0xa3a3062c, 0x8cbd7c76),
809 PCMCIA_DEVICE_PROD_ID12("COMPAQ", "PCMCIA 33600 FAX/DATA MODEM", 0xa3a3062c, 0x5a00ce95),
810 PCMCIA_DEVICE_PROD_ID12("Computerboards, Inc.", "PCM-COM422", 0xd0b78f51, 0x7e2d49ed),
811 PCMCIA_DEVICE_PROD_ID12("Dr. Neuhaus", "FURY CARD 14K4", 0x76942813, 0x8b96ce65),
812 PCMCIA_DEVICE_PROD_ID12("IBM", "ISDN/56K/GSM", 0xb569a6e5, 0xfee5297b),
813 PCMCIA_DEVICE_PROD_ID12("Intelligent", "ANGIA FAX/MODEM", 0xb496e65e, 0xf31602a6),
814 PCMCIA_DEVICE_PROD_ID12("Intel", "MODEM 2400+", 0x816cc815, 0x412729fb),
815 PCMCIA_DEVICE_PROD_ID12("Intertex", "IX34-PCMCIA", 0xf8a097e3, 0x97880447),
816 PCMCIA_DEVICE_PROD_ID12("IOTech Inc ", "PCMCIA Dual RS-232 Serial Port Card", 0x3bd2d898, 0x92abc92f),
817 PCMCIA_DEVICE_PROD_ID12("MACRONIX", "FAX/MODEM", 0x668388b3, 0x3f9bdf2f),
818 PCMCIA_DEVICE_PROD_ID12("Multi-Tech", "MT1432LT", 0x5f73be51, 0x0b3e2383),
819 PCMCIA_DEVICE_PROD_ID12("Multi-Tech", "MT2834LT", 0x5f73be51, 0x4cd7c09e),
820 PCMCIA_DEVICE_PROD_ID12("OEM ", "C288MX ", 0xb572d360, 0xd2385b7a),
821 PCMCIA_DEVICE_PROD_ID12("Option International", "V34bis GSM/PSTN Data/Fax Modem", 0x9d7cd6f5, 0x5cb8bf41),
822 PCMCIA_DEVICE_PROD_ID12("PCMCIA ", "C336MX ", 0x99bcafe9, 0xaa25bcab),
823 PCMCIA_DEVICE_PROD_ID12("Quatech Inc", "PCMCIA Dual RS-232 Serial Port Card", 0xc4420b35, 0x92abc92f),
824 PCMCIA_DEVICE_PROD_ID12("Quatech Inc", "Dual RS-232 Serial Port PC Card", 0xc4420b35, 0x031a380d),
825 PCMCIA_DEVICE_PROD_ID12("Telia", "SurfinBird 560P/A+", 0xe2cdd5e, 0xc9314b38),
826 PCMCIA_DEVICE_PROD_ID1("Smart Serial Port", 0x2d8ce292),
827 PCMCIA_PFC_DEVICE_CIS_PROD_ID12(1, "PCMCIA", "EN2218-LAN/MODEM", 0x281f1c5d, 0x570f348e, "cis/PCMLM28.cis"),
828 PCMCIA_PFC_DEVICE_CIS_PROD_ID12(1, "PCMCIA", "UE2218-LAN/MODEM", 0x281f1c5d, 0x6fdcacee, "cis/PCMLM28.cis"),
829 PCMCIA_PFC_DEVICE_CIS_PROD_ID12(1, "Psion Dacom", "Gold Card V34 Ethernet", 0xf5f025c2, 0x338e8155, "cis/PCMLM28.cis"),
830 PCMCIA_PFC_DEVICE_CIS_PROD_ID12(1, "Psion Dacom", "Gold Card V34 Ethernet GSM", 0xf5f025c2, 0x4ae85d35, "cis/PCMLM28.cis"),
831 PCMCIA_PFC_DEVICE_CIS_PROD_ID12(1, "LINKSYS", "PCMLM28", 0xf7cb0b07, 0x66881874, "cis/PCMLM28.cis"),
832 PCMCIA_PFC_DEVICE_CIS_PROD_ID12(1, "TOSHIBA", "Modem/LAN Card", 0xb4585a1a, 0x53f922f8, "cis/PCMLM28.cis"),
833 PCMCIA_MFC_DEVICE_CIS_PROD_ID12(1, "DAYNA COMMUNICATIONS", "LAN AND MODEM MULTIFUNCTION", 0x8fdf8f89, 0xdd5ed9e8, "cis/DP83903.cis"),
834 PCMCIA_MFC_DEVICE_CIS_PROD_ID4(1, "NSC MF LAN/Modem", 0x58fc6056, "cis/DP83903.cis"),
835 PCMCIA_MFC_DEVICE_CIS_MANF_CARD(1, 0x0101, 0x0556, "cis/3CCFEM556.cis"),
836 PCMCIA_MFC_DEVICE_CIS_MANF_CARD(1, 0x0175, 0x0000, "cis/DP83903.cis"),
837 PCMCIA_MFC_DEVICE_CIS_MANF_CARD(1, 0x0101, 0x0035, "cis/3CXEM556.cis"),
838 PCMCIA_MFC_DEVICE_CIS_MANF_CARD(1, 0x0101, 0x003d, "cis/3CXEM556.cis"),
839 PCMCIA_DEVICE_CIS_PROD_ID12("Sierra Wireless", "AC850", 0xd85f6206, 0x42a2c018, "cis/SW_8xx_SER.cis"), /* Sierra Wireless AC850 3G Network Adapter R1 */
840 PCMCIA_DEVICE_CIS_PROD_ID12("Sierra Wireless", "AC860", 0xd85f6206, 0x698f93db, "cis/SW_8xx_SER.cis"), /* Sierra Wireless AC860 3G Network Adapter R1 */
841 PCMCIA_DEVICE_CIS_PROD_ID12("Sierra Wireless", "AC710/AC750", 0xd85f6206, 0x761b11e0, "cis/SW_7xx_SER.cis"), /* Sierra Wireless AC710/AC750 GPRS Network Adapter R1 */
842 PCMCIA_DEVICE_CIS_MANF_CARD(0x0192, 0xa555, "cis/SW_555_SER.cis"), /* Sierra Aircard 555 CDMA 1xrtt Modem -- pre update */
843 PCMCIA_DEVICE_CIS_MANF_CARD(0x013f, 0xa555, "cis/SW_555_SER.cis"), /* Sierra Aircard 555 CDMA 1xrtt Modem -- post update */
844 PCMCIA_DEVICE_CIS_PROD_ID12("MultiTech", "PCMCIA 56K DataFax", 0x842047ee, 0xc2efcf03, "cis/MT5634ZLX.cis"),
845 PCMCIA_DEVICE_CIS_PROD_ID12("ADVANTECH", "COMpad-32/85B-2", 0x96913a85, 0x27ab5437, "cis/COMpad2.cis"),
846 PCMCIA_DEVICE_CIS_PROD_ID12("ADVANTECH", "COMpad-32/85B-4", 0x96913a85, 0xcec8f102, "cis/COMpad4.cis"),
847 PCMCIA_DEVICE_CIS_PROD_ID123("ADVANTECH", "COMpad-32/85", "1.0", 0x96913a85, 0x8fbe92ae, 0x0877b627, "cis/COMpad2.cis"),
848 PCMCIA_DEVICE_CIS_PROD_ID2("RS-COM 2P", 0xad20b156, "cis/RS-COM-2P.cis"),
849 PCMCIA_DEVICE_CIS_MANF_CARD(0x0013, 0x0000, "cis/GLOBETROTTER.cis"),
850 PCMCIA_DEVICE_PROD_ID12("ELAN DIGITAL SYSTEMS LTD, c1997.","SERIAL CARD: SL100 1.00.",0x19ca78af,0xf964f42b),
851 PCMCIA_DEVICE_PROD_ID12("ELAN DIGITAL SYSTEMS LTD, c1997.","SERIAL CARD: SL100",0x19ca78af,0x71d98e83),
852 PCMCIA_DEVICE_PROD_ID12("ELAN DIGITAL SYSTEMS LTD, c1997.","SERIAL CARD: SL232 1.00.",0x19ca78af,0x69fb7490),
853 PCMCIA_DEVICE_PROD_ID12("ELAN DIGITAL SYSTEMS LTD, c1997.","SERIAL CARD: SL232",0x19ca78af,0xb6bc0235),
854 PCMCIA_DEVICE_PROD_ID12("ELAN DIGITAL SYSTEMS LTD, c2000.","SERIAL CARD: CF232",0x63f2e0bd,0xb9e175d3),
855 PCMCIA_DEVICE_PROD_ID12("ELAN DIGITAL SYSTEMS LTD, c2000.","SERIAL CARD: CF232-5",0x63f2e0bd,0xfce33442),
856 PCMCIA_DEVICE_PROD_ID12("Elan","Serial Port: CF232",0x3beb8cf2,0x171e7190),
857 PCMCIA_DEVICE_PROD_ID12("Elan","Serial Port: CF232-5",0x3beb8cf2,0x20da4262),
858 PCMCIA_DEVICE_PROD_ID12("Elan","Serial Port: CF428",0x3beb8cf2,0xea5dd57d),
859 PCMCIA_DEVICE_PROD_ID12("Elan","Serial Port: CF500",0x3beb8cf2,0xd77255fa),
860 PCMCIA_DEVICE_PROD_ID12("Elan","Serial Port: IC232",0x3beb8cf2,0x6a709903),
861 PCMCIA_DEVICE_PROD_ID12("Elan","Serial Port: SL232",0x3beb8cf2,0x18430676),
862 PCMCIA_DEVICE_PROD_ID12("Elan","Serial Port: XL232",0x3beb8cf2,0x6f933767),
863 PCMCIA_MFC_DEVICE_PROD_ID12(0,"Elan","Serial Port: CF332",0x3beb8cf2,0x16dc1ba7),
864 PCMCIA_MFC_DEVICE_PROD_ID12(0,"Elan","Serial Port: SL332",0x3beb8cf2,0x19816c41),
865 PCMCIA_MFC_DEVICE_PROD_ID12(0,"Elan","Serial Port: SL385",0x3beb8cf2,0x64112029),
866 PCMCIA_MFC_DEVICE_PROD_ID12(0,"Elan","Serial Port: SL432",0x3beb8cf2,0x1cce7ac4),
867 PCMCIA_MFC_DEVICE_PROD_ID12(0,"Elan","Serial+Parallel Port: SP230",0x3beb8cf2,0xdb9e58bc),
868 PCMCIA_MFC_DEVICE_PROD_ID12(1,"Elan","Serial Port: CF332",0x3beb8cf2,0x16dc1ba7),
869 PCMCIA_MFC_DEVICE_PROD_ID12(1,"Elan","Serial Port: SL332",0x3beb8cf2,0x19816c41),
870 PCMCIA_MFC_DEVICE_PROD_ID12(1,"Elan","Serial Port: SL385",0x3beb8cf2,0x64112029),
871 PCMCIA_MFC_DEVICE_PROD_ID12(1,"Elan","Serial Port: SL432",0x3beb8cf2,0x1cce7ac4),
872 PCMCIA_MFC_DEVICE_PROD_ID12(2,"Elan","Serial Port: SL432",0x3beb8cf2,0x1cce7ac4),
873 PCMCIA_MFC_DEVICE_PROD_ID12(3,"Elan","Serial Port: SL432",0x3beb8cf2,0x1cce7ac4),
874 PCMCIA_DEVICE_MANF_CARD(0x0279, 0x950b),
875 /* too generic */
876 /* PCMCIA_MFC_DEVICE_MANF_CARD(0, 0x0160, 0x0002), */
877 /* PCMCIA_MFC_DEVICE_MANF_CARD(1, 0x0160, 0x0002), */
878 PCMCIA_DEVICE_FUNC_ID(2),
879 PCMCIA_DEVICE_NULL,
880};
881MODULE_DEVICE_TABLE(pcmcia, serial_ids);
882
883MODULE_FIRMWARE("cis/PCMLM28.cis");
884MODULE_FIRMWARE("cis/DP83903.cis");
885MODULE_FIRMWARE("cis/3CCFEM556.cis");
886MODULE_FIRMWARE("cis/3CXEM556.cis");
887MODULE_FIRMWARE("cis/SW_8xx_SER.cis");
888MODULE_FIRMWARE("cis/SW_7xx_SER.cis");
889MODULE_FIRMWARE("cis/SW_555_SER.cis");
890MODULE_FIRMWARE("cis/MT5634ZLX.cis");
891MODULE_FIRMWARE("cis/COMpad2.cis");
892MODULE_FIRMWARE("cis/COMpad4.cis");
893MODULE_FIRMWARE("cis/RS-COM-2P.cis");
894
895static struct pcmcia_driver serial_cs_driver = {
896 .owner = THIS_MODULE,
897 .drv = {
898 .name = "serial_cs",
899 },
900 .probe = serial_probe,
901 .remove = serial_detach,
902 .id_table = serial_ids,
903 .suspend = serial_suspend,
904 .resume = serial_resume,
905};
906
907static int __init init_serial_cs(void)
908{
909 return pcmcia_register_driver(&serial_cs_driver);
910}
911
912static void __exit exit_serial_cs(void)
913{
914 pcmcia_unregister_driver(&serial_cs_driver);
915}
916
917module_init(init_serial_cs);
918module_exit(exit_serial_cs);
919
920MODULE_LICENSE("GPL");
diff --git a/drivers/serial/serial_ks8695.c b/drivers/serial/serial_ks8695.c
deleted file mode 100644
index b1962025b1aa..000000000000
--- a/drivers/serial/serial_ks8695.c
+++ /dev/null
@@ -1,705 +0,0 @@
1/*
2 * drivers/serial/serial_ks8695.c
3 *
4 * Driver for KS8695 serial ports
5 *
6 * Based on drivers/serial/serial_amba.c, by Kam Lee.
7 *
8 * Copyright 2002-2005 Micrel Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 */
16#include <linux/module.h>
17#include <linux/tty.h>
18#include <linux/ioport.h>
19#include <linux/init.h>
20#include <linux/serial.h>
21#include <linux/console.h>
22#include <linux/sysrq.h>
23#include <linux/device.h>
24
25#include <asm/io.h>
26#include <asm/irq.h>
27#include <asm/mach/irq.h>
28
29#include <mach/regs-uart.h>
30#include <mach/regs-irq.h>
31
32#if defined(CONFIG_SERIAL_KS8695_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
33#define SUPPORT_SYSRQ
34#endif
35
36#include <linux/serial_core.h>
37
38
39#define SERIAL_KS8695_MAJOR 204
40#define SERIAL_KS8695_MINOR 16
41#define SERIAL_KS8695_DEVNAME "ttyAM"
42
43#define SERIAL_KS8695_NR 1
44
45/*
46 * Access macros for the KS8695 UART
47 */
48#define UART_GET_CHAR(p) (__raw_readl((p)->membase + KS8695_URRB) & 0xFF)
49#define UART_PUT_CHAR(p, c) __raw_writel((c), (p)->membase + KS8695_URTH)
50#define UART_GET_FCR(p) __raw_readl((p)->membase + KS8695_URFC)
51#define UART_PUT_FCR(p, c) __raw_writel((c), (p)->membase + KS8695_URFC)
52#define UART_GET_MSR(p) __raw_readl((p)->membase + KS8695_URMS)
53#define UART_GET_LSR(p) __raw_readl((p)->membase + KS8695_URLS)
54#define UART_GET_LCR(p) __raw_readl((p)->membase + KS8695_URLC)
55#define UART_PUT_LCR(p, c) __raw_writel((c), (p)->membase + KS8695_URLC)
56#define UART_GET_MCR(p) __raw_readl((p)->membase + KS8695_URMC)
57#define UART_PUT_MCR(p, c) __raw_writel((c), (p)->membase + KS8695_URMC)
58#define UART_GET_BRDR(p) __raw_readl((p)->membase + KS8695_URBD)
59#define UART_PUT_BRDR(p, c) __raw_writel((c), (p)->membase + KS8695_URBD)
60
61#define KS8695_CLR_TX_INT() __raw_writel(1 << KS8695_IRQ_UART_TX, KS8695_IRQ_VA + KS8695_INTST)
62
63#define UART_DUMMY_LSR_RX 0x100
64#define UART_PORT_SIZE (KS8695_USR - KS8695_URRB + 4)
65
66static inline int tx_enabled(struct uart_port *port)
67{
68 return port->unused[0] & 1;
69}
70
71static inline int rx_enabled(struct uart_port *port)
72{
73 return port->unused[0] & 2;
74}
75
76static inline int ms_enabled(struct uart_port *port)
77{
78 return port->unused[0] & 4;
79}
80
81static inline void ms_enable(struct uart_port *port, int enabled)
82{
83 if(enabled)
84 port->unused[0] |= 4;
85 else
86 port->unused[0] &= ~4;
87}
88
89static inline void rx_enable(struct uart_port *port, int enabled)
90{
91 if(enabled)
92 port->unused[0] |= 2;
93 else
94 port->unused[0] &= ~2;
95}
96
97static inline void tx_enable(struct uart_port *port, int enabled)
98{
99 if(enabled)
100 port->unused[0] |= 1;
101 else
102 port->unused[0] &= ~1;
103}
104
105
106#ifdef SUPPORT_SYSRQ
107static struct console ks8695_console;
108#endif
109
110static void ks8695uart_stop_tx(struct uart_port *port)
111{
112 if (tx_enabled(port)) {
113 /* use disable_irq_nosync() and not disable_irq() to avoid self
114 * imposed deadlock by not waiting for irq handler to end,
115 * since this ks8695uart_stop_tx() is called from interrupt context.
116 */
117 disable_irq_nosync(KS8695_IRQ_UART_TX);
118 tx_enable(port, 0);
119 }
120}
121
122static void ks8695uart_start_tx(struct uart_port *port)
123{
124 if (!tx_enabled(port)) {
125 enable_irq(KS8695_IRQ_UART_TX);
126 tx_enable(port, 1);
127 }
128}
129
130static void ks8695uart_stop_rx(struct uart_port *port)
131{
132 if (rx_enabled(port)) {
133 disable_irq(KS8695_IRQ_UART_RX);
134 rx_enable(port, 0);
135 }
136}
137
138static void ks8695uart_enable_ms(struct uart_port *port)
139{
140 if (!ms_enabled(port)) {
141 enable_irq(KS8695_IRQ_UART_MODEM_STATUS);
142 ms_enable(port,1);
143 }
144}
145
146static void ks8695uart_disable_ms(struct uart_port *port)
147{
148 if (ms_enabled(port)) {
149 disable_irq(KS8695_IRQ_UART_MODEM_STATUS);
150 ms_enable(port,0);
151 }
152}
153
154static irqreturn_t ks8695uart_rx_chars(int irq, void *dev_id)
155{
156 struct uart_port *port = dev_id;
157 struct tty_struct *tty = port->state->port.tty;
158 unsigned int status, ch, lsr, flg, max_count = 256;
159
160 status = UART_GET_LSR(port); /* clears pending LSR interrupts */
161 while ((status & URLS_URDR) && max_count--) {
162 ch = UART_GET_CHAR(port);
163 flg = TTY_NORMAL;
164
165 port->icount.rx++;
166
167 /*
168 * Note that the error handling code is
169 * out of the main execution path
170 */
171 lsr = UART_GET_LSR(port) | UART_DUMMY_LSR_RX;
172 if (unlikely(lsr & (URLS_URBI | URLS_URPE | URLS_URFE | URLS_URROE))) {
173 if (lsr & URLS_URBI) {
174 lsr &= ~(URLS_URFE | URLS_URPE);
175 port->icount.brk++;
176 if (uart_handle_break(port))
177 goto ignore_char;
178 }
179 if (lsr & URLS_URPE)
180 port->icount.parity++;
181 if (lsr & URLS_URFE)
182 port->icount.frame++;
183 if (lsr & URLS_URROE)
184 port->icount.overrun++;
185
186 lsr &= port->read_status_mask;
187
188 if (lsr & URLS_URBI)
189 flg = TTY_BREAK;
190 else if (lsr & URLS_URPE)
191 flg = TTY_PARITY;
192 else if (lsr & URLS_URFE)
193 flg = TTY_FRAME;
194 }
195
196 if (uart_handle_sysrq_char(port, ch))
197 goto ignore_char;
198
199 uart_insert_char(port, lsr, URLS_URROE, ch, flg);
200
201ignore_char:
202 status = UART_GET_LSR(port);
203 }
204 tty_flip_buffer_push(tty);
205
206 return IRQ_HANDLED;
207}
208
209
210static irqreturn_t ks8695uart_tx_chars(int irq, void *dev_id)
211{
212 struct uart_port *port = dev_id;
213 struct circ_buf *xmit = &port->state->xmit;
214 unsigned int count;
215
216 if (port->x_char) {
217 KS8695_CLR_TX_INT();
218 UART_PUT_CHAR(port, port->x_char);
219 port->icount.tx++;
220 port->x_char = 0;
221 return IRQ_HANDLED;
222 }
223
224 if (uart_tx_stopped(port) || uart_circ_empty(xmit)) {
225 ks8695uart_stop_tx(port);
226 return IRQ_HANDLED;
227 }
228
229 count = 16; /* fifo size */
230 while (!uart_circ_empty(xmit) && (count-- > 0)) {
231 KS8695_CLR_TX_INT();
232 UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
233
234 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
235 port->icount.tx++;
236 }
237
238 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
239 uart_write_wakeup(port);
240
241 if (uart_circ_empty(xmit))
242 ks8695uart_stop_tx(port);
243
244 return IRQ_HANDLED;
245}
246
247static irqreturn_t ks8695uart_modem_status(int irq, void *dev_id)
248{
249 struct uart_port *port = dev_id;
250 unsigned int status;
251
252 /*
253 * clear modem interrupt by reading MSR
254 */
255 status = UART_GET_MSR(port);
256
257 if (status & URMS_URDDCD)
258 uart_handle_dcd_change(port, status & URMS_URDDCD);
259
260 if (status & URMS_URDDST)
261 port->icount.dsr++;
262
263 if (status & URMS_URDCTS)
264 uart_handle_cts_change(port, status & URMS_URDCTS);
265
266 if (status & URMS_URTERI)
267 port->icount.rng++;
268
269 wake_up_interruptible(&port->state->port.delta_msr_wait);
270
271 return IRQ_HANDLED;
272}
273
274static unsigned int ks8695uart_tx_empty(struct uart_port *port)
275{
276 return (UART_GET_LSR(port) & URLS_URTE) ? TIOCSER_TEMT : 0;
277}
278
279static unsigned int ks8695uart_get_mctrl(struct uart_port *port)
280{
281 unsigned int result = 0;
282 unsigned int status;
283
284 status = UART_GET_MSR(port);
285 if (status & URMS_URDCD)
286 result |= TIOCM_CAR;
287 if (status & URMS_URDSR)
288 result |= TIOCM_DSR;
289 if (status & URMS_URCTS)
290 result |= TIOCM_CTS;
291 if (status & URMS_URRI)
292 result |= TIOCM_RI;
293
294 return result;
295}
296
297static void ks8695uart_set_mctrl(struct uart_port *port, u_int mctrl)
298{
299 unsigned int mcr;
300
301 mcr = UART_GET_MCR(port);
302 if (mctrl & TIOCM_RTS)
303 mcr |= URMC_URRTS;
304 else
305 mcr &= ~URMC_URRTS;
306
307 if (mctrl & TIOCM_DTR)
308 mcr |= URMC_URDTR;
309 else
310 mcr &= ~URMC_URDTR;
311
312 UART_PUT_MCR(port, mcr);
313}
314
315static void ks8695uart_break_ctl(struct uart_port *port, int break_state)
316{
317 unsigned int lcr;
318
319 lcr = UART_GET_LCR(port);
320
321 if (break_state == -1)
322 lcr |= URLC_URSBC;
323 else
324 lcr &= ~URLC_URSBC;
325
326 UART_PUT_LCR(port, lcr);
327}
328
329static int ks8695uart_startup(struct uart_port *port)
330{
331 int retval;
332
333 set_irq_flags(KS8695_IRQ_UART_TX, IRQF_VALID | IRQF_NOAUTOEN);
334 tx_enable(port, 0);
335 rx_enable(port, 1);
336 ms_enable(port, 1);
337
338 /*
339 * Allocate the IRQ
340 */
341 retval = request_irq(KS8695_IRQ_UART_TX, ks8695uart_tx_chars, IRQF_DISABLED, "UART TX", port);
342 if (retval)
343 goto err_tx;
344
345 retval = request_irq(KS8695_IRQ_UART_RX, ks8695uart_rx_chars, IRQF_DISABLED, "UART RX", port);
346 if (retval)
347 goto err_rx;
348
349 retval = request_irq(KS8695_IRQ_UART_LINE_STATUS, ks8695uart_rx_chars, IRQF_DISABLED, "UART LineStatus", port);
350 if (retval)
351 goto err_ls;
352
353 retval = request_irq(KS8695_IRQ_UART_MODEM_STATUS, ks8695uart_modem_status, IRQF_DISABLED, "UART ModemStatus", port);
354 if (retval)
355 goto err_ms;
356
357 return 0;
358
359err_ms:
360 free_irq(KS8695_IRQ_UART_LINE_STATUS, port);
361err_ls:
362 free_irq(KS8695_IRQ_UART_RX, port);
363err_rx:
364 free_irq(KS8695_IRQ_UART_TX, port);
365err_tx:
366 return retval;
367}
368
369static void ks8695uart_shutdown(struct uart_port *port)
370{
371 /*
372 * Free the interrupt
373 */
374 free_irq(KS8695_IRQ_UART_RX, port);
375 free_irq(KS8695_IRQ_UART_TX, port);
376 free_irq(KS8695_IRQ_UART_MODEM_STATUS, port);
377 free_irq(KS8695_IRQ_UART_LINE_STATUS, port);
378
379 /* disable break condition and fifos */
380 UART_PUT_LCR(port, UART_GET_LCR(port) & ~URLC_URSBC);
381 UART_PUT_FCR(port, UART_GET_FCR(port) & ~URFC_URFE);
382}
383
384static void ks8695uart_set_termios(struct uart_port *port, struct ktermios *termios, struct ktermios *old)
385{
386 unsigned int lcr, fcr = 0;
387 unsigned long flags;
388 unsigned int baud, quot;
389
390 /*
391 * Ask the core to calculate the divisor for us.
392 */
393 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
394 quot = uart_get_divisor(port, baud);
395
396 switch (termios->c_cflag & CSIZE) {
397 case CS5:
398 lcr = URCL_5;
399 break;
400 case CS6:
401 lcr = URCL_6;
402 break;
403 case CS7:
404 lcr = URCL_7;
405 break;
406 default:
407 lcr = URCL_8;
408 break;
409 }
410
411 /* stop bits */
412 if (termios->c_cflag & CSTOPB)
413 lcr |= URLC_URSB;
414
415 /* parity */
416 if (termios->c_cflag & PARENB) {
417 if (termios->c_cflag & CMSPAR) { /* Mark or Space parity */
418 if (termios->c_cflag & PARODD)
419 lcr |= URPE_MARK;
420 else
421 lcr |= URPE_SPACE;
422 }
423 else if (termios->c_cflag & PARODD)
424 lcr |= URPE_ODD;
425 else
426 lcr |= URPE_EVEN;
427 }
428
429 if (port->fifosize > 1)
430 fcr = URFC_URFRT_8 | URFC_URTFR | URFC_URRFR | URFC_URFE;
431
432 spin_lock_irqsave(&port->lock, flags);
433
434 /*
435 * Update the per-port timeout.
436 */
437 uart_update_timeout(port, termios->c_cflag, baud);
438
439 port->read_status_mask = URLS_URROE;
440 if (termios->c_iflag & INPCK)
441 port->read_status_mask |= (URLS_URFE | URLS_URPE);
442 if (termios->c_iflag & (BRKINT | PARMRK))
443 port->read_status_mask |= URLS_URBI;
444
445 /*
446 * Characters to ignore
447 */
448 port->ignore_status_mask = 0;
449 if (termios->c_iflag & IGNPAR)
450 port->ignore_status_mask |= (URLS_URFE | URLS_URPE);
451 if (termios->c_iflag & IGNBRK) {
452 port->ignore_status_mask |= URLS_URBI;
453 /*
454 * If we're ignoring parity and break indicators,
455 * ignore overruns too (for real raw support).
456 */
457 if (termios->c_iflag & IGNPAR)
458 port->ignore_status_mask |= URLS_URROE;
459 }
460
461 /*
462 * Ignore all characters if CREAD is not set.
463 */
464 if ((termios->c_cflag & CREAD) == 0)
465 port->ignore_status_mask |= UART_DUMMY_LSR_RX;
466
467 /* first, disable everything */
468 if (UART_ENABLE_MS(port, termios->c_cflag))
469 ks8695uart_enable_ms(port);
470 else
471 ks8695uart_disable_ms(port);
472
473 /* Set baud rate */
474 UART_PUT_BRDR(port, quot);
475
476 UART_PUT_LCR(port, lcr);
477 UART_PUT_FCR(port, fcr);
478
479 spin_unlock_irqrestore(&port->lock, flags);
480}
481
482static const char *ks8695uart_type(struct uart_port *port)
483{
484 return port->type == PORT_KS8695 ? "KS8695" : NULL;
485}
486
487/*
488 * Release the memory region(s) being used by 'port'
489 */
490static void ks8695uart_release_port(struct uart_port *port)
491{
492 release_mem_region(port->mapbase, UART_PORT_SIZE);
493}
494
495/*
496 * Request the memory region(s) being used by 'port'
497 */
498static int ks8695uart_request_port(struct uart_port *port)
499{
500 return request_mem_region(port->mapbase, UART_PORT_SIZE,
501 "serial_ks8695") != NULL ? 0 : -EBUSY;
502}
503
504/*
505 * Configure/autoconfigure the port.
506 */
507static void ks8695uart_config_port(struct uart_port *port, int flags)
508{
509 if (flags & UART_CONFIG_TYPE) {
510 port->type = PORT_KS8695;
511 ks8695uart_request_port(port);
512 }
513}
514
515/*
516 * verify the new serial_struct (for TIOCSSERIAL).
517 */
518static int ks8695uart_verify_port(struct uart_port *port, struct serial_struct *ser)
519{
520 int ret = 0;
521
522 if (ser->type != PORT_UNKNOWN && ser->type != PORT_KS8695)
523 ret = -EINVAL;
524 if (ser->irq != port->irq)
525 ret = -EINVAL;
526 if (ser->baud_base < 9600)
527 ret = -EINVAL;
528 return ret;
529}
530
531static struct uart_ops ks8695uart_pops = {
532 .tx_empty = ks8695uart_tx_empty,
533 .set_mctrl = ks8695uart_set_mctrl,
534 .get_mctrl = ks8695uart_get_mctrl,
535 .stop_tx = ks8695uart_stop_tx,
536 .start_tx = ks8695uart_start_tx,
537 .stop_rx = ks8695uart_stop_rx,
538 .enable_ms = ks8695uart_enable_ms,
539 .break_ctl = ks8695uart_break_ctl,
540 .startup = ks8695uart_startup,
541 .shutdown = ks8695uart_shutdown,
542 .set_termios = ks8695uart_set_termios,
543 .type = ks8695uart_type,
544 .release_port = ks8695uart_release_port,
545 .request_port = ks8695uart_request_port,
546 .config_port = ks8695uart_config_port,
547 .verify_port = ks8695uart_verify_port,
548};
549
550static struct uart_port ks8695uart_ports[SERIAL_KS8695_NR] = {
551 {
552 .membase = (void *) KS8695_UART_VA,
553 .mapbase = KS8695_UART_VA,
554 .iotype = SERIAL_IO_MEM,
555 .irq = KS8695_IRQ_UART_TX,
556 .uartclk = KS8695_CLOCK_RATE * 16,
557 .fifosize = 16,
558 .ops = &ks8695uart_pops,
559 .flags = ASYNC_BOOT_AUTOCONF,
560 .line = 0,
561 }
562};
563
564#ifdef CONFIG_SERIAL_KS8695_CONSOLE
565static void ks8695_console_putchar(struct uart_port *port, int ch)
566{
567 while (!(UART_GET_LSR(port) & URLS_URTHRE))
568 barrier();
569
570 UART_PUT_CHAR(port, ch);
571}
572
573static void ks8695_console_write(struct console *co, const char *s, u_int count)
574{
575 struct uart_port *port = ks8695uart_ports + co->index;
576
577 uart_console_write(port, s, count, ks8695_console_putchar);
578}
579
580static void __init ks8695_console_get_options(struct uart_port *port, int *baud, int *parity, int *bits)
581{
582 unsigned int lcr;
583
584 lcr = UART_GET_LCR(port);
585
586 switch (lcr & URLC_PARITY) {
587 case URPE_ODD:
588 *parity = 'o';
589 break;
590 case URPE_EVEN:
591 *parity = 'e';
592 break;
593 default:
594 *parity = 'n';
595 }
596
597 switch (lcr & URLC_URCL) {
598 case URCL_5:
599 *bits = 5;
600 break;
601 case URCL_6:
602 *bits = 6;
603 break;
604 case URCL_7:
605 *bits = 7;
606 break;
607 default:
608 *bits = 8;
609 }
610
611 *baud = port->uartclk / (UART_GET_BRDR(port) & 0x0FFF);
612 *baud /= 16;
613 *baud &= 0xFFFFFFF0;
614}
615
616static int __init ks8695_console_setup(struct console *co, char *options)
617{
618 struct uart_port *port;
619 int baud = 115200;
620 int bits = 8;
621 int parity = 'n';
622 int flow = 'n';
623
624 /*
625 * Check whether an invalid uart number has been specified, and
626 * if so, search for the first available port that does have
627 * console support.
628 */
629 port = uart_get_console(ks8695uart_ports, SERIAL_KS8695_NR, co);
630
631 if (options)
632 uart_parse_options(options, &baud, &parity, &bits, &flow);
633 else
634 ks8695_console_get_options(port, &baud, &parity, &bits);
635
636 return uart_set_options(port, co, baud, parity, bits, flow);
637}
638
639static struct uart_driver ks8695_reg;
640
641static struct console ks8695_console = {
642 .name = SERIAL_KS8695_DEVNAME,
643 .write = ks8695_console_write,
644 .device = uart_console_device,
645 .setup = ks8695_console_setup,
646 .flags = CON_PRINTBUFFER,
647 .index = -1,
648 .data = &ks8695_reg,
649};
650
651static int __init ks8695_console_init(void)
652{
653 add_preferred_console(SERIAL_KS8695_DEVNAME, 0, NULL);
654 register_console(&ks8695_console);
655 return 0;
656}
657
658console_initcall(ks8695_console_init);
659
660#define KS8695_CONSOLE &ks8695_console
661#else
662#define KS8695_CONSOLE NULL
663#endif
664
665static struct uart_driver ks8695_reg = {
666 .owner = THIS_MODULE,
667 .driver_name = "serial_ks8695",
668 .dev_name = SERIAL_KS8695_DEVNAME,
669 .major = SERIAL_KS8695_MAJOR,
670 .minor = SERIAL_KS8695_MINOR,
671 .nr = SERIAL_KS8695_NR,
672 .cons = KS8695_CONSOLE,
673};
674
675static int __init ks8695uart_init(void)
676{
677 int i, ret;
678
679 printk(KERN_INFO "Serial: Micrel KS8695 UART driver\n");
680
681 ret = uart_register_driver(&ks8695_reg);
682 if (ret)
683 return ret;
684
685 for (i = 0; i < SERIAL_KS8695_NR; i++)
686 uart_add_one_port(&ks8695_reg, &ks8695uart_ports[0]);
687
688 return 0;
689}
690
691static void __exit ks8695uart_exit(void)
692{
693 int i;
694
695 for (i = 0; i < SERIAL_KS8695_NR; i++)
696 uart_remove_one_port(&ks8695_reg, &ks8695uart_ports[0]);
697 uart_unregister_driver(&ks8695_reg);
698}
699
700module_init(ks8695uart_init);
701module_exit(ks8695uart_exit);
702
703MODULE_DESCRIPTION("KS8695 serial port driver");
704MODULE_AUTHOR("Micrel Inc.");
705MODULE_LICENSE("GPL");
diff --git a/drivers/serial/serial_lh7a40x.c b/drivers/serial/serial_lh7a40x.c
deleted file mode 100644
index ea744707c4d6..000000000000
--- a/drivers/serial/serial_lh7a40x.c
+++ /dev/null
@@ -1,682 +0,0 @@
1/* drivers/serial/serial_lh7a40x.c
2 *
3 * Copyright (C) 2004 Coastal Environmental Systems
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 */
10
11/* Driver for Sharp LH7A40X embedded serial ports
12 *
13 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
14 * Based on drivers/serial/amba.c, by Deep Blue Solutions Ltd.
15 *
16 * ---
17 *
18 * This driver supports the embedded UARTs of the Sharp LH7A40X series
19 * CPUs. While similar to the 16550 and other UART chips, there is
20 * nothing close to register compatibility. Moreover, some of the
21 * modem control lines are not available, either in the chip or they
22 * are lacking in the board-level implementation.
23 *
24 * - Use of SIRDIS
25 * For simplicity, we disable the IR functions of any UART whenever
26 * we enable it.
27 *
28 */
29
30
31#if defined(CONFIG_SERIAL_LH7A40X_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
32#define SUPPORT_SYSRQ
33#endif
34
35#include <linux/module.h>
36#include <linux/ioport.h>
37#include <linux/init.h>
38#include <linux/console.h>
39#include <linux/sysrq.h>
40#include <linux/tty.h>
41#include <linux/tty_flip.h>
42#include <linux/serial_core.h>
43#include <linux/serial.h>
44#include <linux/io.h>
45
46#include <asm/irq.h>
47#include <mach/hardware.h>
48
49#define DEV_MAJOR 204
50#define DEV_MINOR 16
51#define DEV_NR 3
52
53#define ISR_LOOP_LIMIT 256
54
55#define UR(p,o) _UR ((p)->membase, o)
56#define _UR(b,o) (*((volatile unsigned int*)(((unsigned char*) b) + (o))))
57#define BIT_CLR(p,o,m) UR(p,o) = UR(p,o) & (~(unsigned int)m)
58#define BIT_SET(p,o,m) UR(p,o) = UR(p,o) | ( (unsigned int)m)
59
60#define UART_REG_SIZE 32
61
62#define UART_R_DATA (0x00)
63#define UART_R_FCON (0x04)
64#define UART_R_BRCON (0x08)
65#define UART_R_CON (0x0c)
66#define UART_R_STATUS (0x10)
67#define UART_R_RAWISR (0x14)
68#define UART_R_INTEN (0x18)
69#define UART_R_ISR (0x1c)
70
71#define UARTEN (0x01) /* UART enable */
72#define SIRDIS (0x02) /* Serial IR disable (UART1 only) */
73
74#define RxEmpty (0x10)
75#define TxEmpty (0x80)
76#define TxFull (0x20)
77#define nRxRdy RxEmpty
78#define nTxRdy TxFull
79#define TxBusy (0x08)
80
81#define RxBreak (0x0800)
82#define RxOverrunError (0x0400)
83#define RxParityError (0x0200)
84#define RxFramingError (0x0100)
85#define RxError (RxBreak | RxOverrunError | RxParityError | RxFramingError)
86
87#define DCD (0x04)
88#define DSR (0x02)
89#define CTS (0x01)
90
91#define RxInt (0x01)
92#define TxInt (0x02)
93#define ModemInt (0x04)
94#define RxTimeoutInt (0x08)
95
96#define MSEOI (0x10)
97
98#define WLEN_8 (0x60)
99#define WLEN_7 (0x40)
100#define WLEN_6 (0x20)
101#define WLEN_5 (0x00)
102#define WLEN (0x60) /* Mask for all word-length bits */
103#define STP2 (0x08)
104#define PEN (0x02) /* Parity Enable */
105#define EPS (0x04) /* Even Parity Set */
106#define FEN (0x10) /* FIFO Enable */
107#define BRK (0x01) /* Send Break */
108
109
110struct uart_port_lh7a40x {
111 struct uart_port port;
112 unsigned int statusPrev; /* Most recently read modem status */
113};
114
115static void lh7a40xuart_stop_tx (struct uart_port* port)
116{
117 BIT_CLR (port, UART_R_INTEN, TxInt);
118}
119
120static void lh7a40xuart_start_tx (struct uart_port* port)
121{
122 BIT_SET (port, UART_R_INTEN, TxInt);
123
124 /* *** FIXME: do I need to check for startup of the
125 transmitter? The old driver did, but AMBA
126 doesn't . */
127}
128
129static void lh7a40xuart_stop_rx (struct uart_port* port)
130{
131 BIT_SET (port, UART_R_INTEN, RxTimeoutInt | RxInt);
132}
133
134static void lh7a40xuart_enable_ms (struct uart_port* port)
135{
136 BIT_SET (port, UART_R_INTEN, ModemInt);
137}
138
139static void lh7a40xuart_rx_chars (struct uart_port* port)
140{
141 struct tty_struct* tty = port->state->port.tty;
142 int cbRxMax = 256; /* (Gross) limit on receive */
143 unsigned int data; /* Received data and status */
144 unsigned int flag;
145
146 while (!(UR (port, UART_R_STATUS) & nRxRdy) && --cbRxMax) {
147 data = UR (port, UART_R_DATA);
148 flag = TTY_NORMAL;
149 ++port->icount.rx;
150
151 if (unlikely(data & RxError)) {
152 if (data & RxBreak) {
153 data &= ~(RxFramingError | RxParityError);
154 ++port->icount.brk;
155 if (uart_handle_break (port))
156 continue;
157 }
158 else if (data & RxParityError)
159 ++port->icount.parity;
160 else if (data & RxFramingError)
161 ++port->icount.frame;
162 if (data & RxOverrunError)
163 ++port->icount.overrun;
164
165 /* Mask by termios, leave Rx'd byte */
166 data &= port->read_status_mask | 0xff;
167
168 if (data & RxBreak)
169 flag = TTY_BREAK;
170 else if (data & RxParityError)
171 flag = TTY_PARITY;
172 else if (data & RxFramingError)
173 flag = TTY_FRAME;
174 }
175
176 if (uart_handle_sysrq_char (port, (unsigned char) data))
177 continue;
178
179 uart_insert_char(port, data, RxOverrunError, data, flag);
180 }
181 tty_flip_buffer_push (tty);
182 return;
183}
184
185static void lh7a40xuart_tx_chars (struct uart_port* port)
186{
187 struct circ_buf* xmit = &port->state->xmit;
188 int cbTxMax = port->fifosize;
189
190 if (port->x_char) {
191 UR (port, UART_R_DATA) = port->x_char;
192 ++port->icount.tx;
193 port->x_char = 0;
194 return;
195 }
196 if (uart_circ_empty (xmit) || uart_tx_stopped (port)) {
197 lh7a40xuart_stop_tx (port);
198 return;
199 }
200
201 /* Unlike the AMBA UART, the lh7a40x UART does not guarantee
202 that at least half of the FIFO is empty. Instead, we check
203 status for every character. Using the AMBA method causes
204 the transmitter to drop characters. */
205
206 do {
207 UR (port, UART_R_DATA) = xmit->buf[xmit->tail];
208 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
209 ++port->icount.tx;
210 if (uart_circ_empty(xmit))
211 break;
212 } while (!(UR (port, UART_R_STATUS) & nTxRdy)
213 && cbTxMax--);
214
215 if (uart_circ_chars_pending (xmit) < WAKEUP_CHARS)
216 uart_write_wakeup (port);
217
218 if (uart_circ_empty (xmit))
219 lh7a40xuart_stop_tx (port);
220}
221
222static void lh7a40xuart_modem_status (struct uart_port* port)
223{
224 unsigned int status = UR (port, UART_R_STATUS);
225 unsigned int delta
226 = status ^ ((struct uart_port_lh7a40x*) port)->statusPrev;
227
228 BIT_SET (port, UART_R_RAWISR, MSEOI); /* Clear modem status intr */
229
230 if (!delta) /* Only happens if we missed 2 transitions */
231 return;
232
233 ((struct uart_port_lh7a40x*) port)->statusPrev = status;
234
235 if (delta & DCD)
236 uart_handle_dcd_change (port, status & DCD);
237
238 if (delta & DSR)
239 ++port->icount.dsr;
240
241 if (delta & CTS)
242 uart_handle_cts_change (port, status & CTS);
243
244 wake_up_interruptible (&port->state->port.delta_msr_wait);
245}
246
247static irqreturn_t lh7a40xuart_int (int irq, void* dev_id)
248{
249 struct uart_port* port = dev_id;
250 unsigned int cLoopLimit = ISR_LOOP_LIMIT;
251 unsigned int isr = UR (port, UART_R_ISR);
252
253
254 do {
255 if (isr & (RxInt | RxTimeoutInt))
256 lh7a40xuart_rx_chars(port);
257 if (isr & ModemInt)
258 lh7a40xuart_modem_status (port);
259 if (isr & TxInt)
260 lh7a40xuart_tx_chars (port);
261
262 if (--cLoopLimit == 0)
263 break;
264
265 isr = UR (port, UART_R_ISR);
266 } while (isr & (RxInt | TxInt | RxTimeoutInt));
267
268 return IRQ_HANDLED;
269}
270
271static unsigned int lh7a40xuart_tx_empty (struct uart_port* port)
272{
273 return (UR (port, UART_R_STATUS) & TxEmpty) ? TIOCSER_TEMT : 0;
274}
275
276static unsigned int lh7a40xuart_get_mctrl (struct uart_port* port)
277{
278 unsigned int result = 0;
279 unsigned int status = UR (port, UART_R_STATUS);
280
281 if (status & DCD)
282 result |= TIOCM_CAR;
283 if (status & DSR)
284 result |= TIOCM_DSR;
285 if (status & CTS)
286 result |= TIOCM_CTS;
287
288 return result;
289}
290
291static void lh7a40xuart_set_mctrl (struct uart_port* port, unsigned int mctrl)
292{
293 /* None of the ports supports DTR. UART1 supports RTS through GPIO. */
294 /* Note, kernel appears to be setting DTR and RTS on console. */
295
296 /* *** FIXME: this deserves more work. There's some work in
297 tracing all of the IO pins. */
298#if 0
299 if( port->mapbase == UART1_PHYS) {
300 gpioRegs_t *gpio = (gpioRegs_t *)IO_ADDRESS(GPIO_PHYS);
301
302 if (mctrl & TIOCM_RTS)
303 gpio->pbdr &= ~GPIOB_UART1_RTS;
304 else
305 gpio->pbdr |= GPIOB_UART1_RTS;
306 }
307#endif
308}
309
310static void lh7a40xuart_break_ctl (struct uart_port* port, int break_state)
311{
312 unsigned long flags;
313
314 spin_lock_irqsave(&port->lock, flags);
315 if (break_state == -1)
316 BIT_SET (port, UART_R_FCON, BRK); /* Assert break */
317 else
318 BIT_CLR (port, UART_R_FCON, BRK); /* Deassert break */
319 spin_unlock_irqrestore(&port->lock, flags);
320}
321
322static int lh7a40xuart_startup (struct uart_port* port)
323{
324 int retval;
325
326 retval = request_irq (port->irq, lh7a40xuart_int, 0,
327 "serial_lh7a40x", port);
328 if (retval)
329 return retval;
330
331 /* Initial modem control-line settings */
332 ((struct uart_port_lh7a40x*) port)->statusPrev
333 = UR (port, UART_R_STATUS);
334
335 /* There is presently no configuration option to enable IR.
336 Thus, we always disable it. */
337
338 BIT_SET (port, UART_R_CON, UARTEN | SIRDIS);
339 BIT_SET (port, UART_R_INTEN, RxTimeoutInt | RxInt);
340
341 return 0;
342}
343
344static void lh7a40xuart_shutdown (struct uart_port* port)
345{
346 free_irq (port->irq, port);
347 BIT_CLR (port, UART_R_FCON, BRK | FEN);
348 BIT_CLR (port, UART_R_CON, UARTEN);
349}
350
351static void lh7a40xuart_set_termios (struct uart_port* port,
352 struct ktermios* termios,
353 struct ktermios* old)
354{
355 unsigned int con;
356 unsigned int inten;
357 unsigned int fcon;
358 unsigned long flags;
359 unsigned int baud;
360 unsigned int quot;
361
362 baud = uart_get_baud_rate (port, termios, old, 8, port->uartclk/16);
363 quot = uart_get_divisor (port, baud); /* -1 performed elsewhere */
364
365 switch (termios->c_cflag & CSIZE) {
366 case CS5:
367 fcon = WLEN_5;
368 break;
369 case CS6:
370 fcon = WLEN_6;
371 break;
372 case CS7:
373 fcon = WLEN_7;
374 break;
375 case CS8:
376 default:
377 fcon = WLEN_8;
378 break;
379 }
380 if (termios->c_cflag & CSTOPB)
381 fcon |= STP2;
382 if (termios->c_cflag & PARENB) {
383 fcon |= PEN;
384 if (!(termios->c_cflag & PARODD))
385 fcon |= EPS;
386 }
387 if (port->fifosize > 1)
388 fcon |= FEN;
389
390 spin_lock_irqsave (&port->lock, flags);
391
392 uart_update_timeout (port, termios->c_cflag, baud);
393
394 port->read_status_mask = RxOverrunError;
395 if (termios->c_iflag & INPCK)
396 port->read_status_mask |= RxFramingError | RxParityError;
397 if (termios->c_iflag & (BRKINT | PARMRK))
398 port->read_status_mask |= RxBreak;
399
400 /* Figure mask for status we ignore */
401 port->ignore_status_mask = 0;
402 if (termios->c_iflag & IGNPAR)
403 port->ignore_status_mask |= RxFramingError | RxParityError;
404 if (termios->c_iflag & IGNBRK) {
405 port->ignore_status_mask |= RxBreak;
406 /* Ignore overrun when ignorning parity */
407 /* *** FIXME: is this in the right place? */
408 if (termios->c_iflag & IGNPAR)
409 port->ignore_status_mask |= RxOverrunError;
410 }
411
412 /* Ignore all receive errors when receive disabled */
413 if ((termios->c_cflag & CREAD) == 0)
414 port->ignore_status_mask |= RxError;
415
416 con = UR (port, UART_R_CON);
417 inten = (UR (port, UART_R_INTEN) & ~ModemInt);
418
419 if (UART_ENABLE_MS (port, termios->c_cflag))
420 inten |= ModemInt;
421
422 BIT_CLR (port, UART_R_CON, UARTEN); /* Disable UART */
423 UR (port, UART_R_INTEN) = 0; /* Disable interrupts */
424 UR (port, UART_R_BRCON) = quot - 1; /* Set baud rate divisor */
425 UR (port, UART_R_FCON) = fcon; /* Set FIFO and frame ctrl */
426 UR (port, UART_R_INTEN) = inten; /* Enable interrupts */
427 UR (port, UART_R_CON) = con; /* Restore UART mode */
428
429 spin_unlock_irqrestore(&port->lock, flags);
430}
431
432static const char* lh7a40xuart_type (struct uart_port* port)
433{
434 return port->type == PORT_LH7A40X ? "LH7A40X" : NULL;
435}
436
437static void lh7a40xuart_release_port (struct uart_port* port)
438{
439 release_mem_region (port->mapbase, UART_REG_SIZE);
440}
441
442static int lh7a40xuart_request_port (struct uart_port* port)
443{
444 return request_mem_region (port->mapbase, UART_REG_SIZE,
445 "serial_lh7a40x") != NULL
446 ? 0 : -EBUSY;
447}
448
449static void lh7a40xuart_config_port (struct uart_port* port, int flags)
450{
451 if (flags & UART_CONFIG_TYPE) {
452 port->type = PORT_LH7A40X;
453 lh7a40xuart_request_port (port);
454 }
455}
456
457static int lh7a40xuart_verify_port (struct uart_port* port,
458 struct serial_struct* ser)
459{
460 int ret = 0;
461
462 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LH7A40X)
463 ret = -EINVAL;
464 if (ser->irq < 0 || ser->irq >= nr_irqs)
465 ret = -EINVAL;
466 if (ser->baud_base < 9600) /* *** FIXME: is this true? */
467 ret = -EINVAL;
468 return ret;
469}
470
471static struct uart_ops lh7a40x_uart_ops = {
472 .tx_empty = lh7a40xuart_tx_empty,
473 .set_mctrl = lh7a40xuart_set_mctrl,
474 .get_mctrl = lh7a40xuart_get_mctrl,
475 .stop_tx = lh7a40xuart_stop_tx,
476 .start_tx = lh7a40xuart_start_tx,
477 .stop_rx = lh7a40xuart_stop_rx,
478 .enable_ms = lh7a40xuart_enable_ms,
479 .break_ctl = lh7a40xuart_break_ctl,
480 .startup = lh7a40xuart_startup,
481 .shutdown = lh7a40xuart_shutdown,
482 .set_termios = lh7a40xuart_set_termios,
483 .type = lh7a40xuart_type,
484 .release_port = lh7a40xuart_release_port,
485 .request_port = lh7a40xuart_request_port,
486 .config_port = lh7a40xuart_config_port,
487 .verify_port = lh7a40xuart_verify_port,
488};
489
490static struct uart_port_lh7a40x lh7a40x_ports[DEV_NR] = {
491 {
492 .port = {
493 .membase = (void*) io_p2v (UART1_PHYS),
494 .mapbase = UART1_PHYS,
495 .iotype = UPIO_MEM,
496 .irq = IRQ_UART1INTR,
497 .uartclk = 14745600/2,
498 .fifosize = 16,
499 .ops = &lh7a40x_uart_ops,
500 .flags = UPF_BOOT_AUTOCONF,
501 .line = 0,
502 },
503 },
504 {
505 .port = {
506 .membase = (void*) io_p2v (UART2_PHYS),
507 .mapbase = UART2_PHYS,
508 .iotype = UPIO_MEM,
509 .irq = IRQ_UART2INTR,
510 .uartclk = 14745600/2,
511 .fifosize = 16,
512 .ops = &lh7a40x_uart_ops,
513 .flags = UPF_BOOT_AUTOCONF,
514 .line = 1,
515 },
516 },
517 {
518 .port = {
519 .membase = (void*) io_p2v (UART3_PHYS),
520 .mapbase = UART3_PHYS,
521 .iotype = UPIO_MEM,
522 .irq = IRQ_UART3INTR,
523 .uartclk = 14745600/2,
524 .fifosize = 16,
525 .ops = &lh7a40x_uart_ops,
526 .flags = UPF_BOOT_AUTOCONF,
527 .line = 2,
528 },
529 },
530};
531
532#ifndef CONFIG_SERIAL_LH7A40X_CONSOLE
533# define LH7A40X_CONSOLE NULL
534#else
535# define LH7A40X_CONSOLE &lh7a40x_console
536
537static void lh7a40xuart_console_putchar(struct uart_port *port, int ch)
538{
539 while (UR(port, UART_R_STATUS) & nTxRdy)
540 ;
541 UR(port, UART_R_DATA) = ch;
542}
543
544static void lh7a40xuart_console_write (struct console* co,
545 const char* s,
546 unsigned int count)
547{
548 struct uart_port* port = &lh7a40x_ports[co->index].port;
549 unsigned int con = UR (port, UART_R_CON);
550 unsigned int inten = UR (port, UART_R_INTEN);
551
552
553 UR (port, UART_R_INTEN) = 0; /* Disable all interrupts */
554 BIT_SET (port, UART_R_CON, UARTEN | SIRDIS); /* Enable UART */
555
556 uart_console_write(port, s, count, lh7a40xuart_console_putchar);
557
558 /* Wait until all characters are sent */
559 while (UR (port, UART_R_STATUS) & TxBusy)
560 ;
561
562 /* Restore control and interrupt mask */
563 UR (port, UART_R_CON) = con;
564 UR (port, UART_R_INTEN) = inten;
565}
566
567static void __init lh7a40xuart_console_get_options (struct uart_port* port,
568 int* baud,
569 int* parity,
570 int* bits)
571{
572 if (UR (port, UART_R_CON) & UARTEN) {
573 unsigned int fcon = UR (port, UART_R_FCON);
574 unsigned int quot = UR (port, UART_R_BRCON) + 1;
575
576 switch (fcon & (PEN | EPS)) {
577 default: *parity = 'n'; break;
578 case PEN: *parity = 'o'; break;
579 case PEN | EPS: *parity = 'e'; break;
580 }
581
582 switch (fcon & WLEN) {
583 default:
584 case WLEN_8: *bits = 8; break;
585 case WLEN_7: *bits = 7; break;
586 case WLEN_6: *bits = 6; break;
587 case WLEN_5: *bits = 5; break;
588 }
589
590 *baud = port->uartclk/(16*quot);
591 }
592}
593
594static int __init lh7a40xuart_console_setup (struct console* co, char* options)
595{
596 struct uart_port* port;
597 int baud = 38400;
598 int bits = 8;
599 int parity = 'n';
600 int flow = 'n';
601
602 if (co->index >= DEV_NR) /* Bounds check on device number */
603 co->index = 0;
604 port = &lh7a40x_ports[co->index].port;
605
606 if (options)
607 uart_parse_options (options, &baud, &parity, &bits, &flow);
608 else
609 lh7a40xuart_console_get_options (port, &baud, &parity, &bits);
610
611 return uart_set_options (port, co, baud, parity, bits, flow);
612}
613
614static struct uart_driver lh7a40x_reg;
615static struct console lh7a40x_console = {
616 .name = "ttyAM",
617 .write = lh7a40xuart_console_write,
618 .device = uart_console_device,
619 .setup = lh7a40xuart_console_setup,
620 .flags = CON_PRINTBUFFER,
621 .index = -1,
622 .data = &lh7a40x_reg,
623};
624
625static int __init lh7a40xuart_console_init(void)
626{
627 register_console (&lh7a40x_console);
628 return 0;
629}
630
631console_initcall (lh7a40xuart_console_init);
632
633#endif
634
635static struct uart_driver lh7a40x_reg = {
636 .owner = THIS_MODULE,
637 .driver_name = "ttyAM",
638 .dev_name = "ttyAM",
639 .major = DEV_MAJOR,
640 .minor = DEV_MINOR,
641 .nr = DEV_NR,
642 .cons = LH7A40X_CONSOLE,
643};
644
645static int __init lh7a40xuart_init(void)
646{
647 int ret;
648
649 printk (KERN_INFO "serial: LH7A40X serial driver\n");
650
651 ret = uart_register_driver (&lh7a40x_reg);
652
653 if (ret == 0) {
654 int i;
655
656 for (i = 0; i < DEV_NR; i++) {
657 /* UART3, when used, requires GPIO pin reallocation */
658 if (lh7a40x_ports[i].port.mapbase == UART3_PHYS)
659 GPIO_PINMUX |= 1<<3;
660 uart_add_one_port (&lh7a40x_reg,
661 &lh7a40x_ports[i].port);
662 }
663 }
664 return ret;
665}
666
667static void __exit lh7a40xuart_exit(void)
668{
669 int i;
670
671 for (i = 0; i < DEV_NR; i++)
672 uart_remove_one_port (&lh7a40x_reg, &lh7a40x_ports[i].port);
673
674 uart_unregister_driver (&lh7a40x_reg);
675}
676
677module_init (lh7a40xuart_init);
678module_exit (lh7a40xuart_exit);
679
680MODULE_AUTHOR ("Marc Singer");
681MODULE_DESCRIPTION ("Sharp LH7A40X serial port driver");
682MODULE_LICENSE ("GPL");
diff --git a/drivers/serial/serial_txx9.c b/drivers/serial/serial_txx9.c
deleted file mode 100644
index c50e9fbbf743..000000000000
--- a/drivers/serial/serial_txx9.c
+++ /dev/null
@@ -1,1344 +0,0 @@
1/*
2 * drivers/serial/serial_txx9.c
3 *
4 * Derived from many drivers using generic_serial interface,
5 * especially serial_tx3912.c by Steven J. Hill and r39xx_serial.c
6 * (was in Linux/VR tree) by Jim Pick.
7 *
8 * Copyright (C) 1999 Harald Koerfgen
9 * Copyright (C) 2000 Jim Pick <jim@jimpick.com>
10 * Copyright (C) 2001 Steven J. Hill (sjhill@realitydiluted.com)
11 * Copyright (C) 2000-2002 Toshiba Corporation
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 *
17 * Serial driver for TX3927/TX4927/TX4925/TX4938 internal SIO controller
18 */
19
20#if defined(CONFIG_SERIAL_TXX9_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
23
24#include <linux/module.h>
25#include <linux/ioport.h>
26#include <linux/init.h>
27#include <linux/console.h>
28#include <linux/delay.h>
29#include <linux/platform_device.h>
30#include <linux/pci.h>
31#include <linux/serial_core.h>
32#include <linux/serial.h>
33
34#include <asm/io.h>
35
36static char *serial_version = "1.11";
37static char *serial_name = "TX39/49 Serial driver";
38
39#define PASS_LIMIT 256
40
41#if !defined(CONFIG_SERIAL_TXX9_STDSERIAL)
42/* "ttyS" is used for standard serial driver */
43#define TXX9_TTY_NAME "ttyTX"
44#define TXX9_TTY_MINOR_START 196
45#define TXX9_TTY_MAJOR 204
46#else
47/* acts like standard serial driver */
48#define TXX9_TTY_NAME "ttyS"
49#define TXX9_TTY_MINOR_START 64
50#define TXX9_TTY_MAJOR TTY_MAJOR
51#endif
52
53/* flag aliases */
54#define UPF_TXX9_HAVE_CTS_LINE UPF_BUGGY_UART
55#define UPF_TXX9_USE_SCLK UPF_MAGIC_MULTIPLIER
56
57#ifdef CONFIG_PCI
58/* support for Toshiba TC86C001 SIO */
59#define ENABLE_SERIAL_TXX9_PCI
60#endif
61
62/*
63 * Number of serial ports
64 */
65#define UART_NR CONFIG_SERIAL_TXX9_NR_UARTS
66
67struct uart_txx9_port {
68 struct uart_port port;
69 /* No additional info for now */
70};
71
72#define TXX9_REGION_SIZE 0x24
73
74/* TXX9 Serial Registers */
75#define TXX9_SILCR 0x00
76#define TXX9_SIDICR 0x04
77#define TXX9_SIDISR 0x08
78#define TXX9_SICISR 0x0c
79#define TXX9_SIFCR 0x10
80#define TXX9_SIFLCR 0x14
81#define TXX9_SIBGR 0x18
82#define TXX9_SITFIFO 0x1c
83#define TXX9_SIRFIFO 0x20
84
85/* SILCR : Line Control */
86#define TXX9_SILCR_SCS_MASK 0x00000060
87#define TXX9_SILCR_SCS_IMCLK 0x00000000
88#define TXX9_SILCR_SCS_IMCLK_BG 0x00000020
89#define TXX9_SILCR_SCS_SCLK 0x00000040
90#define TXX9_SILCR_SCS_SCLK_BG 0x00000060
91#define TXX9_SILCR_UEPS 0x00000010
92#define TXX9_SILCR_UPEN 0x00000008
93#define TXX9_SILCR_USBL_MASK 0x00000004
94#define TXX9_SILCR_USBL_1BIT 0x00000000
95#define TXX9_SILCR_USBL_2BIT 0x00000004
96#define TXX9_SILCR_UMODE_MASK 0x00000003
97#define TXX9_SILCR_UMODE_8BIT 0x00000000
98#define TXX9_SILCR_UMODE_7BIT 0x00000001
99
100/* SIDICR : DMA/Int. Control */
101#define TXX9_SIDICR_TDE 0x00008000
102#define TXX9_SIDICR_RDE 0x00004000
103#define TXX9_SIDICR_TIE 0x00002000
104#define TXX9_SIDICR_RIE 0x00001000
105#define TXX9_SIDICR_SPIE 0x00000800
106#define TXX9_SIDICR_CTSAC 0x00000600
107#define TXX9_SIDICR_STIE_MASK 0x0000003f
108#define TXX9_SIDICR_STIE_OERS 0x00000020
109#define TXX9_SIDICR_STIE_CTSS 0x00000010
110#define TXX9_SIDICR_STIE_RBRKD 0x00000008
111#define TXX9_SIDICR_STIE_TRDY 0x00000004
112#define TXX9_SIDICR_STIE_TXALS 0x00000002
113#define TXX9_SIDICR_STIE_UBRKD 0x00000001
114
115/* SIDISR : DMA/Int. Status */
116#define TXX9_SIDISR_UBRK 0x00008000
117#define TXX9_SIDISR_UVALID 0x00004000
118#define TXX9_SIDISR_UFER 0x00002000
119#define TXX9_SIDISR_UPER 0x00001000
120#define TXX9_SIDISR_UOER 0x00000800
121#define TXX9_SIDISR_ERI 0x00000400
122#define TXX9_SIDISR_TOUT 0x00000200
123#define TXX9_SIDISR_TDIS 0x00000100
124#define TXX9_SIDISR_RDIS 0x00000080
125#define TXX9_SIDISR_STIS 0x00000040
126#define TXX9_SIDISR_RFDN_MASK 0x0000001f
127
128/* SICISR : Change Int. Status */
129#define TXX9_SICISR_OERS 0x00000020
130#define TXX9_SICISR_CTSS 0x00000010
131#define TXX9_SICISR_RBRKD 0x00000008
132#define TXX9_SICISR_TRDY 0x00000004
133#define TXX9_SICISR_TXALS 0x00000002
134#define TXX9_SICISR_UBRKD 0x00000001
135
136/* SIFCR : FIFO Control */
137#define TXX9_SIFCR_SWRST 0x00008000
138#define TXX9_SIFCR_RDIL_MASK 0x00000180
139#define TXX9_SIFCR_RDIL_1 0x00000000
140#define TXX9_SIFCR_RDIL_4 0x00000080
141#define TXX9_SIFCR_RDIL_8 0x00000100
142#define TXX9_SIFCR_RDIL_12 0x00000180
143#define TXX9_SIFCR_RDIL_MAX 0x00000180
144#define TXX9_SIFCR_TDIL_MASK 0x00000018
145#define TXX9_SIFCR_TDIL_MASK 0x00000018
146#define TXX9_SIFCR_TDIL_1 0x00000000
147#define TXX9_SIFCR_TDIL_4 0x00000001
148#define TXX9_SIFCR_TDIL_8 0x00000010
149#define TXX9_SIFCR_TDIL_MAX 0x00000010
150#define TXX9_SIFCR_TFRST 0x00000004
151#define TXX9_SIFCR_RFRST 0x00000002
152#define TXX9_SIFCR_FRSTE 0x00000001
153#define TXX9_SIO_TX_FIFO 8
154#define TXX9_SIO_RX_FIFO 16
155
156/* SIFLCR : Flow Control */
157#define TXX9_SIFLCR_RCS 0x00001000
158#define TXX9_SIFLCR_TES 0x00000800
159#define TXX9_SIFLCR_RTSSC 0x00000200
160#define TXX9_SIFLCR_RSDE 0x00000100
161#define TXX9_SIFLCR_TSDE 0x00000080
162#define TXX9_SIFLCR_RTSTL_MASK 0x0000001e
163#define TXX9_SIFLCR_RTSTL_MAX 0x0000001e
164#define TXX9_SIFLCR_TBRK 0x00000001
165
166/* SIBGR : Baudrate Control */
167#define TXX9_SIBGR_BCLK_MASK 0x00000300
168#define TXX9_SIBGR_BCLK_T0 0x00000000
169#define TXX9_SIBGR_BCLK_T2 0x00000100
170#define TXX9_SIBGR_BCLK_T4 0x00000200
171#define TXX9_SIBGR_BCLK_T6 0x00000300
172#define TXX9_SIBGR_BRD_MASK 0x000000ff
173
174static inline unsigned int sio_in(struct uart_txx9_port *up, int offset)
175{
176 switch (up->port.iotype) {
177 default:
178 return __raw_readl(up->port.membase + offset);
179 case UPIO_PORT:
180 return inl(up->port.iobase + offset);
181 }
182}
183
184static inline void
185sio_out(struct uart_txx9_port *up, int offset, int value)
186{
187 switch (up->port.iotype) {
188 default:
189 __raw_writel(value, up->port.membase + offset);
190 break;
191 case UPIO_PORT:
192 outl(value, up->port.iobase + offset);
193 break;
194 }
195}
196
197static inline void
198sio_mask(struct uart_txx9_port *up, int offset, unsigned int value)
199{
200 sio_out(up, offset, sio_in(up, offset) & ~value);
201}
202static inline void
203sio_set(struct uart_txx9_port *up, int offset, unsigned int value)
204{
205 sio_out(up, offset, sio_in(up, offset) | value);
206}
207
208static inline void
209sio_quot_set(struct uart_txx9_port *up, int quot)
210{
211 quot >>= 1;
212 if (quot < 256)
213 sio_out(up, TXX9_SIBGR, quot | TXX9_SIBGR_BCLK_T0);
214 else if (quot < (256 << 2))
215 sio_out(up, TXX9_SIBGR, (quot >> 2) | TXX9_SIBGR_BCLK_T2);
216 else if (quot < (256 << 4))
217 sio_out(up, TXX9_SIBGR, (quot >> 4) | TXX9_SIBGR_BCLK_T4);
218 else if (quot < (256 << 6))
219 sio_out(up, TXX9_SIBGR, (quot >> 6) | TXX9_SIBGR_BCLK_T6);
220 else
221 sio_out(up, TXX9_SIBGR, 0xff | TXX9_SIBGR_BCLK_T6);
222}
223
224static struct uart_txx9_port *to_uart_txx9_port(struct uart_port *port)
225{
226 return container_of(port, struct uart_txx9_port, port);
227}
228
229static void serial_txx9_stop_tx(struct uart_port *port)
230{
231 struct uart_txx9_port *up = to_uart_txx9_port(port);
232 sio_mask(up, TXX9_SIDICR, TXX9_SIDICR_TIE);
233}
234
235static void serial_txx9_start_tx(struct uart_port *port)
236{
237 struct uart_txx9_port *up = to_uart_txx9_port(port);
238 sio_set(up, TXX9_SIDICR, TXX9_SIDICR_TIE);
239}
240
241static void serial_txx9_stop_rx(struct uart_port *port)
242{
243 struct uart_txx9_port *up = to_uart_txx9_port(port);
244 up->port.read_status_mask &= ~TXX9_SIDISR_RDIS;
245}
246
247static void serial_txx9_enable_ms(struct uart_port *port)
248{
249 /* TXX9-SIO can not control DTR... */
250}
251
252static void serial_txx9_initialize(struct uart_port *port)
253{
254 struct uart_txx9_port *up = to_uart_txx9_port(port);
255 unsigned int tmout = 10000;
256
257 sio_out(up, TXX9_SIFCR, TXX9_SIFCR_SWRST);
258 /* TX4925 BUG WORKAROUND. Accessing SIOC register
259 * immediately after soft reset causes bus error. */
260 mmiowb();
261 udelay(1);
262 while ((sio_in(up, TXX9_SIFCR) & TXX9_SIFCR_SWRST) && --tmout)
263 udelay(1);
264 /* TX Int by FIFO Empty, RX Int by Receiving 1 char. */
265 sio_set(up, TXX9_SIFCR,
266 TXX9_SIFCR_TDIL_MAX | TXX9_SIFCR_RDIL_1);
267 /* initial settings */
268 sio_out(up, TXX9_SILCR,
269 TXX9_SILCR_UMODE_8BIT | TXX9_SILCR_USBL_1BIT |
270 ((up->port.flags & UPF_TXX9_USE_SCLK) ?
271 TXX9_SILCR_SCS_SCLK_BG : TXX9_SILCR_SCS_IMCLK_BG));
272 sio_quot_set(up, uart_get_divisor(port, 9600));
273 sio_out(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSTL_MAX /* 15 */);
274 sio_out(up, TXX9_SIDICR, 0);
275}
276
277static inline void
278receive_chars(struct uart_txx9_port *up, unsigned int *status)
279{
280 struct tty_struct *tty = up->port.state->port.tty;
281 unsigned char ch;
282 unsigned int disr = *status;
283 int max_count = 256;
284 char flag;
285 unsigned int next_ignore_status_mask;
286
287 do {
288 ch = sio_in(up, TXX9_SIRFIFO);
289 flag = TTY_NORMAL;
290 up->port.icount.rx++;
291
292 /* mask out RFDN_MASK bit added by previous overrun */
293 next_ignore_status_mask =
294 up->port.ignore_status_mask & ~TXX9_SIDISR_RFDN_MASK;
295 if (unlikely(disr & (TXX9_SIDISR_UBRK | TXX9_SIDISR_UPER |
296 TXX9_SIDISR_UFER | TXX9_SIDISR_UOER))) {
297 /*
298 * For statistics only
299 */
300 if (disr & TXX9_SIDISR_UBRK) {
301 disr &= ~(TXX9_SIDISR_UFER | TXX9_SIDISR_UPER);
302 up->port.icount.brk++;
303 /*
304 * We do the SysRQ and SAK checking
305 * here because otherwise the break
306 * may get masked by ignore_status_mask
307 * or read_status_mask.
308 */
309 if (uart_handle_break(&up->port))
310 goto ignore_char;
311 } else if (disr & TXX9_SIDISR_UPER)
312 up->port.icount.parity++;
313 else if (disr & TXX9_SIDISR_UFER)
314 up->port.icount.frame++;
315 if (disr & TXX9_SIDISR_UOER) {
316 up->port.icount.overrun++;
317 /*
318 * The receiver read buffer still hold
319 * a char which caused overrun.
320 * Ignore next char by adding RFDN_MASK
321 * to ignore_status_mask temporarily.
322 */
323 next_ignore_status_mask |=
324 TXX9_SIDISR_RFDN_MASK;
325 }
326
327 /*
328 * Mask off conditions which should be ingored.
329 */
330 disr &= up->port.read_status_mask;
331
332 if (disr & TXX9_SIDISR_UBRK) {
333 flag = TTY_BREAK;
334 } else if (disr & TXX9_SIDISR_UPER)
335 flag = TTY_PARITY;
336 else if (disr & TXX9_SIDISR_UFER)
337 flag = TTY_FRAME;
338 }
339 if (uart_handle_sysrq_char(&up->port, ch))
340 goto ignore_char;
341
342 uart_insert_char(&up->port, disr, TXX9_SIDISR_UOER, ch, flag);
343
344 ignore_char:
345 up->port.ignore_status_mask = next_ignore_status_mask;
346 disr = sio_in(up, TXX9_SIDISR);
347 } while (!(disr & TXX9_SIDISR_UVALID) && (max_count-- > 0));
348 spin_unlock(&up->port.lock);
349 tty_flip_buffer_push(tty);
350 spin_lock(&up->port.lock);
351 *status = disr;
352}
353
354static inline void transmit_chars(struct uart_txx9_port *up)
355{
356 struct circ_buf *xmit = &up->port.state->xmit;
357 int count;
358
359 if (up->port.x_char) {
360 sio_out(up, TXX9_SITFIFO, up->port.x_char);
361 up->port.icount.tx++;
362 up->port.x_char = 0;
363 return;
364 }
365 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
366 serial_txx9_stop_tx(&up->port);
367 return;
368 }
369
370 count = TXX9_SIO_TX_FIFO;
371 do {
372 sio_out(up, TXX9_SITFIFO, xmit->buf[xmit->tail]);
373 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
374 up->port.icount.tx++;
375 if (uart_circ_empty(xmit))
376 break;
377 } while (--count > 0);
378
379 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
380 uart_write_wakeup(&up->port);
381
382 if (uart_circ_empty(xmit))
383 serial_txx9_stop_tx(&up->port);
384}
385
386static irqreturn_t serial_txx9_interrupt(int irq, void *dev_id)
387{
388 int pass_counter = 0;
389 struct uart_txx9_port *up = dev_id;
390 unsigned int status;
391
392 while (1) {
393 spin_lock(&up->port.lock);
394 status = sio_in(up, TXX9_SIDISR);
395 if (!(sio_in(up, TXX9_SIDICR) & TXX9_SIDICR_TIE))
396 status &= ~TXX9_SIDISR_TDIS;
397 if (!(status & (TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS |
398 TXX9_SIDISR_TOUT))) {
399 spin_unlock(&up->port.lock);
400 break;
401 }
402
403 if (status & TXX9_SIDISR_RDIS)
404 receive_chars(up, &status);
405 if (status & TXX9_SIDISR_TDIS)
406 transmit_chars(up);
407 /* Clear TX/RX Int. Status */
408 sio_mask(up, TXX9_SIDISR,
409 TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS |
410 TXX9_SIDISR_TOUT);
411 spin_unlock(&up->port.lock);
412
413 if (pass_counter++ > PASS_LIMIT)
414 break;
415 }
416
417 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
418}
419
420static unsigned int serial_txx9_tx_empty(struct uart_port *port)
421{
422 struct uart_txx9_port *up = to_uart_txx9_port(port);
423 unsigned long flags;
424 unsigned int ret;
425
426 spin_lock_irqsave(&up->port.lock, flags);
427 ret = (sio_in(up, TXX9_SICISR) & TXX9_SICISR_TXALS) ? TIOCSER_TEMT : 0;
428 spin_unlock_irqrestore(&up->port.lock, flags);
429
430 return ret;
431}
432
433static unsigned int serial_txx9_get_mctrl(struct uart_port *port)
434{
435 struct uart_txx9_port *up = to_uart_txx9_port(port);
436 unsigned int ret;
437
438 /* no modem control lines */
439 ret = TIOCM_CAR | TIOCM_DSR;
440 ret |= (sio_in(up, TXX9_SIFLCR) & TXX9_SIFLCR_RTSSC) ? 0 : TIOCM_RTS;
441 ret |= (sio_in(up, TXX9_SICISR) & TXX9_SICISR_CTSS) ? 0 : TIOCM_CTS;
442
443 return ret;
444}
445
446static void serial_txx9_set_mctrl(struct uart_port *port, unsigned int mctrl)
447{
448 struct uart_txx9_port *up = to_uart_txx9_port(port);
449
450 if (mctrl & TIOCM_RTS)
451 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSSC);
452 else
453 sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSSC);
454}
455
456static void serial_txx9_break_ctl(struct uart_port *port, int break_state)
457{
458 struct uart_txx9_port *up = to_uart_txx9_port(port);
459 unsigned long flags;
460
461 spin_lock_irqsave(&up->port.lock, flags);
462 if (break_state == -1)
463 sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK);
464 else
465 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK);
466 spin_unlock_irqrestore(&up->port.lock, flags);
467}
468
469#if defined(CONFIG_SERIAL_TXX9_CONSOLE) || (CONFIG_CONSOLE_POLL)
470/*
471 * Wait for transmitter & holding register to empty
472 */
473static void wait_for_xmitr(struct uart_txx9_port *up)
474{
475 unsigned int tmout = 10000;
476
477 /* Wait up to 10ms for the character(s) to be sent. */
478 while (--tmout &&
479 !(sio_in(up, TXX9_SICISR) & TXX9_SICISR_TXALS))
480 udelay(1);
481
482 /* Wait up to 1s for flow control if necessary */
483 if (up->port.flags & UPF_CONS_FLOW) {
484 tmout = 1000000;
485 while (--tmout &&
486 (sio_in(up, TXX9_SICISR) & TXX9_SICISR_CTSS))
487 udelay(1);
488 }
489}
490#endif
491
492#ifdef CONFIG_CONSOLE_POLL
493/*
494 * Console polling routines for writing and reading from the uart while
495 * in an interrupt or debug context.
496 */
497
498static int serial_txx9_get_poll_char(struct uart_port *port)
499{
500 unsigned int ier;
501 unsigned char c;
502 struct uart_txx9_port *up = to_uart_txx9_port(port);
503
504 /*
505 * First save the IER then disable the interrupts
506 */
507 ier = sio_in(up, TXX9_SIDICR);
508 sio_out(up, TXX9_SIDICR, 0);
509
510 while (sio_in(up, TXX9_SIDISR) & TXX9_SIDISR_UVALID)
511 ;
512
513 c = sio_in(up, TXX9_SIRFIFO);
514
515 /*
516 * Finally, clear RX interrupt status
517 * and restore the IER
518 */
519 sio_mask(up, TXX9_SIDISR, TXX9_SIDISR_RDIS);
520 sio_out(up, TXX9_SIDICR, ier);
521 return c;
522}
523
524
525static void serial_txx9_put_poll_char(struct uart_port *port, unsigned char c)
526{
527 unsigned int ier;
528 struct uart_txx9_port *up = to_uart_txx9_port(port);
529
530 /*
531 * First save the IER then disable the interrupts
532 */
533 ier = sio_in(up, TXX9_SIDICR);
534 sio_out(up, TXX9_SIDICR, 0);
535
536 wait_for_xmitr(up);
537 /*
538 * Send the character out.
539 * If a LF, also do CR...
540 */
541 sio_out(up, TXX9_SITFIFO, c);
542 if (c == 10) {
543 wait_for_xmitr(up);
544 sio_out(up, TXX9_SITFIFO, 13);
545 }
546
547 /*
548 * Finally, wait for transmitter to become empty
549 * and restore the IER
550 */
551 wait_for_xmitr(up);
552 sio_out(up, TXX9_SIDICR, ier);
553}
554
555#endif /* CONFIG_CONSOLE_POLL */
556
557static int serial_txx9_startup(struct uart_port *port)
558{
559 struct uart_txx9_port *up = to_uart_txx9_port(port);
560 unsigned long flags;
561 int retval;
562
563 /*
564 * Clear the FIFO buffers and disable them.
565 * (they will be reenabled in set_termios())
566 */
567 sio_set(up, TXX9_SIFCR,
568 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
569 /* clear reset */
570 sio_mask(up, TXX9_SIFCR,
571 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
572 sio_out(up, TXX9_SIDICR, 0);
573
574 /*
575 * Clear the interrupt registers.
576 */
577 sio_out(up, TXX9_SIDISR, 0);
578
579 retval = request_irq(up->port.irq, serial_txx9_interrupt,
580 IRQF_SHARED, "serial_txx9", up);
581 if (retval)
582 return retval;
583
584 /*
585 * Now, initialize the UART
586 */
587 spin_lock_irqsave(&up->port.lock, flags);
588 serial_txx9_set_mctrl(&up->port, up->port.mctrl);
589 spin_unlock_irqrestore(&up->port.lock, flags);
590
591 /* Enable RX/TX */
592 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_RSDE | TXX9_SIFLCR_TSDE);
593
594 /*
595 * Finally, enable interrupts.
596 */
597 sio_set(up, TXX9_SIDICR, TXX9_SIDICR_RIE);
598
599 return 0;
600}
601
602static void serial_txx9_shutdown(struct uart_port *port)
603{
604 struct uart_txx9_port *up = to_uart_txx9_port(port);
605 unsigned long flags;
606
607 /*
608 * Disable interrupts from this port
609 */
610 sio_out(up, TXX9_SIDICR, 0); /* disable all intrs */
611
612 spin_lock_irqsave(&up->port.lock, flags);
613 serial_txx9_set_mctrl(&up->port, up->port.mctrl);
614 spin_unlock_irqrestore(&up->port.lock, flags);
615
616 /*
617 * Disable break condition
618 */
619 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK);
620
621#ifdef CONFIG_SERIAL_TXX9_CONSOLE
622 if (up->port.cons && up->port.line == up->port.cons->index) {
623 free_irq(up->port.irq, up);
624 return;
625 }
626#endif
627 /* reset FIFOs */
628 sio_set(up, TXX9_SIFCR,
629 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
630 /* clear reset */
631 sio_mask(up, TXX9_SIFCR,
632 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
633
634 /* Disable RX/TX */
635 sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_RSDE | TXX9_SIFLCR_TSDE);
636
637 free_irq(up->port.irq, up);
638}
639
640static void
641serial_txx9_set_termios(struct uart_port *port, struct ktermios *termios,
642 struct ktermios *old)
643{
644 struct uart_txx9_port *up = to_uart_txx9_port(port);
645 unsigned int cval, fcr = 0;
646 unsigned long flags;
647 unsigned int baud, quot;
648
649 /*
650 * We don't support modem control lines.
651 */
652 termios->c_cflag &= ~(HUPCL | CMSPAR);
653 termios->c_cflag |= CLOCAL;
654
655 cval = sio_in(up, TXX9_SILCR);
656 /* byte size and parity */
657 cval &= ~TXX9_SILCR_UMODE_MASK;
658 switch (termios->c_cflag & CSIZE) {
659 case CS7:
660 cval |= TXX9_SILCR_UMODE_7BIT;
661 break;
662 default:
663 case CS5: /* not supported */
664 case CS6: /* not supported */
665 case CS8:
666 cval |= TXX9_SILCR_UMODE_8BIT;
667 break;
668 }
669
670 cval &= ~TXX9_SILCR_USBL_MASK;
671 if (termios->c_cflag & CSTOPB)
672 cval |= TXX9_SILCR_USBL_2BIT;
673 else
674 cval |= TXX9_SILCR_USBL_1BIT;
675 cval &= ~(TXX9_SILCR_UPEN | TXX9_SILCR_UEPS);
676 if (termios->c_cflag & PARENB)
677 cval |= TXX9_SILCR_UPEN;
678 if (!(termios->c_cflag & PARODD))
679 cval |= TXX9_SILCR_UEPS;
680
681 /*
682 * Ask the core to calculate the divisor for us.
683 */
684 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16/2);
685 quot = uart_get_divisor(port, baud);
686
687 /* Set up FIFOs */
688 /* TX Int by FIFO Empty, RX Int by Receiving 1 char. */
689 fcr = TXX9_SIFCR_TDIL_MAX | TXX9_SIFCR_RDIL_1;
690
691 /*
692 * Ok, we're now changing the port state. Do it with
693 * interrupts disabled.
694 */
695 spin_lock_irqsave(&up->port.lock, flags);
696
697 /*
698 * Update the per-port timeout.
699 */
700 uart_update_timeout(port, termios->c_cflag, baud);
701
702 up->port.read_status_mask = TXX9_SIDISR_UOER |
703 TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS;
704 if (termios->c_iflag & INPCK)
705 up->port.read_status_mask |= TXX9_SIDISR_UFER | TXX9_SIDISR_UPER;
706 if (termios->c_iflag & (BRKINT | PARMRK))
707 up->port.read_status_mask |= TXX9_SIDISR_UBRK;
708
709 /*
710 * Characteres to ignore
711 */
712 up->port.ignore_status_mask = 0;
713 if (termios->c_iflag & IGNPAR)
714 up->port.ignore_status_mask |= TXX9_SIDISR_UPER | TXX9_SIDISR_UFER;
715 if (termios->c_iflag & IGNBRK) {
716 up->port.ignore_status_mask |= TXX9_SIDISR_UBRK;
717 /*
718 * If we're ignoring parity and break indicators,
719 * ignore overruns too (for real raw support).
720 */
721 if (termios->c_iflag & IGNPAR)
722 up->port.ignore_status_mask |= TXX9_SIDISR_UOER;
723 }
724
725 /*
726 * ignore all characters if CREAD is not set
727 */
728 if ((termios->c_cflag & CREAD) == 0)
729 up->port.ignore_status_mask |= TXX9_SIDISR_RDIS;
730
731 /* CTS flow control flag */
732 if ((termios->c_cflag & CRTSCTS) &&
733 (up->port.flags & UPF_TXX9_HAVE_CTS_LINE)) {
734 sio_set(up, TXX9_SIFLCR,
735 TXX9_SIFLCR_RCS | TXX9_SIFLCR_TES);
736 } else {
737 sio_mask(up, TXX9_SIFLCR,
738 TXX9_SIFLCR_RCS | TXX9_SIFLCR_TES);
739 }
740
741 sio_out(up, TXX9_SILCR, cval);
742 sio_quot_set(up, quot);
743 sio_out(up, TXX9_SIFCR, fcr);
744
745 serial_txx9_set_mctrl(&up->port, up->port.mctrl);
746 spin_unlock_irqrestore(&up->port.lock, flags);
747}
748
749static void
750serial_txx9_pm(struct uart_port *port, unsigned int state,
751 unsigned int oldstate)
752{
753 /*
754 * If oldstate was -1 this is called from
755 * uart_configure_port(). In this case do not initialize the
756 * port now, because the port was already initialized (for
757 * non-console port) or should not be initialized here (for
758 * console port). If we initialized the port here we lose
759 * serial console settings.
760 */
761 if (state == 0 && oldstate != -1)
762 serial_txx9_initialize(port);
763}
764
765static int serial_txx9_request_resource(struct uart_txx9_port *up)
766{
767 unsigned int size = TXX9_REGION_SIZE;
768 int ret = 0;
769
770 switch (up->port.iotype) {
771 default:
772 if (!up->port.mapbase)
773 break;
774
775 if (!request_mem_region(up->port.mapbase, size, "serial_txx9")) {
776 ret = -EBUSY;
777 break;
778 }
779
780 if (up->port.flags & UPF_IOREMAP) {
781 up->port.membase = ioremap(up->port.mapbase, size);
782 if (!up->port.membase) {
783 release_mem_region(up->port.mapbase, size);
784 ret = -ENOMEM;
785 }
786 }
787 break;
788
789 case UPIO_PORT:
790 if (!request_region(up->port.iobase, size, "serial_txx9"))
791 ret = -EBUSY;
792 break;
793 }
794 return ret;
795}
796
797static void serial_txx9_release_resource(struct uart_txx9_port *up)
798{
799 unsigned int size = TXX9_REGION_SIZE;
800
801 switch (up->port.iotype) {
802 default:
803 if (!up->port.mapbase)
804 break;
805
806 if (up->port.flags & UPF_IOREMAP) {
807 iounmap(up->port.membase);
808 up->port.membase = NULL;
809 }
810
811 release_mem_region(up->port.mapbase, size);
812 break;
813
814 case UPIO_PORT:
815 release_region(up->port.iobase, size);
816 break;
817 }
818}
819
820static void serial_txx9_release_port(struct uart_port *port)
821{
822 struct uart_txx9_port *up = to_uart_txx9_port(port);
823 serial_txx9_release_resource(up);
824}
825
826static int serial_txx9_request_port(struct uart_port *port)
827{
828 struct uart_txx9_port *up = to_uart_txx9_port(port);
829 return serial_txx9_request_resource(up);
830}
831
832static void serial_txx9_config_port(struct uart_port *port, int uflags)
833{
834 struct uart_txx9_port *up = to_uart_txx9_port(port);
835 int ret;
836
837 /*
838 * Find the region that we can probe for. This in turn
839 * tells us whether we can probe for the type of port.
840 */
841 ret = serial_txx9_request_resource(up);
842 if (ret < 0)
843 return;
844 port->type = PORT_TXX9;
845 up->port.fifosize = TXX9_SIO_TX_FIFO;
846
847#ifdef CONFIG_SERIAL_TXX9_CONSOLE
848 if (up->port.line == up->port.cons->index)
849 return;
850#endif
851 serial_txx9_initialize(port);
852}
853
854static const char *
855serial_txx9_type(struct uart_port *port)
856{
857 return "txx9";
858}
859
860static struct uart_ops serial_txx9_pops = {
861 .tx_empty = serial_txx9_tx_empty,
862 .set_mctrl = serial_txx9_set_mctrl,
863 .get_mctrl = serial_txx9_get_mctrl,
864 .stop_tx = serial_txx9_stop_tx,
865 .start_tx = serial_txx9_start_tx,
866 .stop_rx = serial_txx9_stop_rx,
867 .enable_ms = serial_txx9_enable_ms,
868 .break_ctl = serial_txx9_break_ctl,
869 .startup = serial_txx9_startup,
870 .shutdown = serial_txx9_shutdown,
871 .set_termios = serial_txx9_set_termios,
872 .pm = serial_txx9_pm,
873 .type = serial_txx9_type,
874 .release_port = serial_txx9_release_port,
875 .request_port = serial_txx9_request_port,
876 .config_port = serial_txx9_config_port,
877#ifdef CONFIG_CONSOLE_POLL
878 .poll_get_char = serial_txx9_get_poll_char,
879 .poll_put_char = serial_txx9_put_poll_char,
880#endif
881};
882
883static struct uart_txx9_port serial_txx9_ports[UART_NR];
884
885static void __init serial_txx9_register_ports(struct uart_driver *drv,
886 struct device *dev)
887{
888 int i;
889
890 for (i = 0; i < UART_NR; i++) {
891 struct uart_txx9_port *up = &serial_txx9_ports[i];
892
893 up->port.line = i;
894 up->port.ops = &serial_txx9_pops;
895 up->port.dev = dev;
896 if (up->port.iobase || up->port.mapbase)
897 uart_add_one_port(drv, &up->port);
898 }
899}
900
901#ifdef CONFIG_SERIAL_TXX9_CONSOLE
902
903static void serial_txx9_console_putchar(struct uart_port *port, int ch)
904{
905 struct uart_txx9_port *up = to_uart_txx9_port(port);
906
907 wait_for_xmitr(up);
908 sio_out(up, TXX9_SITFIFO, ch);
909}
910
911/*
912 * Print a string to the serial port trying not to disturb
913 * any possible real use of the port...
914 *
915 * The console_lock must be held when we get here.
916 */
917static void
918serial_txx9_console_write(struct console *co, const char *s, unsigned int count)
919{
920 struct uart_txx9_port *up = &serial_txx9_ports[co->index];
921 unsigned int ier, flcr;
922
923 /*
924 * First save the UER then disable the interrupts
925 */
926 ier = sio_in(up, TXX9_SIDICR);
927 sio_out(up, TXX9_SIDICR, 0);
928 /*
929 * Disable flow-control if enabled (and unnecessary)
930 */
931 flcr = sio_in(up, TXX9_SIFLCR);
932 if (!(up->port.flags & UPF_CONS_FLOW) && (flcr & TXX9_SIFLCR_TES))
933 sio_out(up, TXX9_SIFLCR, flcr & ~TXX9_SIFLCR_TES);
934
935 uart_console_write(&up->port, s, count, serial_txx9_console_putchar);
936
937 /*
938 * Finally, wait for transmitter to become empty
939 * and restore the IER
940 */
941 wait_for_xmitr(up);
942 sio_out(up, TXX9_SIFLCR, flcr);
943 sio_out(up, TXX9_SIDICR, ier);
944}
945
946static int __init serial_txx9_console_setup(struct console *co, char *options)
947{
948 struct uart_port *port;
949 struct uart_txx9_port *up;
950 int baud = 9600;
951 int bits = 8;
952 int parity = 'n';
953 int flow = 'n';
954
955 /*
956 * Check whether an invalid uart number has been specified, and
957 * if so, search for the first available port that does have
958 * console support.
959 */
960 if (co->index >= UART_NR)
961 co->index = 0;
962 up = &serial_txx9_ports[co->index];
963 port = &up->port;
964 if (!port->ops)
965 return -ENODEV;
966
967 serial_txx9_initialize(&up->port);
968
969 if (options)
970 uart_parse_options(options, &baud, &parity, &bits, &flow);
971
972 return uart_set_options(port, co, baud, parity, bits, flow);
973}
974
975static struct uart_driver serial_txx9_reg;
976static struct console serial_txx9_console = {
977 .name = TXX9_TTY_NAME,
978 .write = serial_txx9_console_write,
979 .device = uart_console_device,
980 .setup = serial_txx9_console_setup,
981 .flags = CON_PRINTBUFFER,
982 .index = -1,
983 .data = &serial_txx9_reg,
984};
985
986static int __init serial_txx9_console_init(void)
987{
988 register_console(&serial_txx9_console);
989 return 0;
990}
991console_initcall(serial_txx9_console_init);
992
993#define SERIAL_TXX9_CONSOLE &serial_txx9_console
994#else
995#define SERIAL_TXX9_CONSOLE NULL
996#endif
997
998static struct uart_driver serial_txx9_reg = {
999 .owner = THIS_MODULE,
1000 .driver_name = "serial_txx9",
1001 .dev_name = TXX9_TTY_NAME,
1002 .major = TXX9_TTY_MAJOR,
1003 .minor = TXX9_TTY_MINOR_START,
1004 .nr = UART_NR,
1005 .cons = SERIAL_TXX9_CONSOLE,
1006};
1007
1008int __init early_serial_txx9_setup(struct uart_port *port)
1009{
1010 if (port->line >= ARRAY_SIZE(serial_txx9_ports))
1011 return -ENODEV;
1012
1013 serial_txx9_ports[port->line].port = *port;
1014 serial_txx9_ports[port->line].port.ops = &serial_txx9_pops;
1015 serial_txx9_ports[port->line].port.flags |=
1016 UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
1017 return 0;
1018}
1019
1020static DEFINE_MUTEX(serial_txx9_mutex);
1021
1022/**
1023 * serial_txx9_register_port - register a serial port
1024 * @port: serial port template
1025 *
1026 * Configure the serial port specified by the request.
1027 *
1028 * The port is then probed and if necessary the IRQ is autodetected
1029 * If this fails an error is returned.
1030 *
1031 * On success the port is ready to use and the line number is returned.
1032 */
1033static int __devinit serial_txx9_register_port(struct uart_port *port)
1034{
1035 int i;
1036 struct uart_txx9_port *uart;
1037 int ret = -ENOSPC;
1038
1039 mutex_lock(&serial_txx9_mutex);
1040 for (i = 0; i < UART_NR; i++) {
1041 uart = &serial_txx9_ports[i];
1042 if (uart_match_port(&uart->port, port)) {
1043 uart_remove_one_port(&serial_txx9_reg, &uart->port);
1044 break;
1045 }
1046 }
1047 if (i == UART_NR) {
1048 /* Find unused port */
1049 for (i = 0; i < UART_NR; i++) {
1050 uart = &serial_txx9_ports[i];
1051 if (!(uart->port.iobase || uart->port.mapbase))
1052 break;
1053 }
1054 }
1055 if (i < UART_NR) {
1056 uart->port.iobase = port->iobase;
1057 uart->port.membase = port->membase;
1058 uart->port.irq = port->irq;
1059 uart->port.uartclk = port->uartclk;
1060 uart->port.iotype = port->iotype;
1061 uart->port.flags = port->flags
1062 | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
1063 uart->port.mapbase = port->mapbase;
1064 if (port->dev)
1065 uart->port.dev = port->dev;
1066 ret = uart_add_one_port(&serial_txx9_reg, &uart->port);
1067 if (ret == 0)
1068 ret = uart->port.line;
1069 }
1070 mutex_unlock(&serial_txx9_mutex);
1071 return ret;
1072}
1073
1074/**
1075 * serial_txx9_unregister_port - remove a txx9 serial port at runtime
1076 * @line: serial line number
1077 *
1078 * Remove one serial port. This may not be called from interrupt
1079 * context. We hand the port back to the our control.
1080 */
1081static void __devexit serial_txx9_unregister_port(int line)
1082{
1083 struct uart_txx9_port *uart = &serial_txx9_ports[line];
1084
1085 mutex_lock(&serial_txx9_mutex);
1086 uart_remove_one_port(&serial_txx9_reg, &uart->port);
1087 uart->port.flags = 0;
1088 uart->port.type = PORT_UNKNOWN;
1089 uart->port.iobase = 0;
1090 uart->port.mapbase = 0;
1091 uart->port.membase = NULL;
1092 uart->port.dev = NULL;
1093 mutex_unlock(&serial_txx9_mutex);
1094}
1095
1096/*
1097 * Register a set of serial devices attached to a platform device.
1098 */
1099static int __devinit serial_txx9_probe(struct platform_device *dev)
1100{
1101 struct uart_port *p = dev->dev.platform_data;
1102 struct uart_port port;
1103 int ret, i;
1104
1105 memset(&port, 0, sizeof(struct uart_port));
1106 for (i = 0; p && p->uartclk != 0; p++, i++) {
1107 port.iobase = p->iobase;
1108 port.membase = p->membase;
1109 port.irq = p->irq;
1110 port.uartclk = p->uartclk;
1111 port.iotype = p->iotype;
1112 port.flags = p->flags;
1113 port.mapbase = p->mapbase;
1114 port.dev = &dev->dev;
1115 ret = serial_txx9_register_port(&port);
1116 if (ret < 0) {
1117 dev_err(&dev->dev, "unable to register port at index %d "
1118 "(IO%lx MEM%llx IRQ%d): %d\n", i,
1119 p->iobase, (unsigned long long)p->mapbase,
1120 p->irq, ret);
1121 }
1122 }
1123 return 0;
1124}
1125
1126/*
1127 * Remove serial ports registered against a platform device.
1128 */
1129static int __devexit serial_txx9_remove(struct platform_device *dev)
1130{
1131 int i;
1132
1133 for (i = 0; i < UART_NR; i++) {
1134 struct uart_txx9_port *up = &serial_txx9_ports[i];
1135
1136 if (up->port.dev == &dev->dev)
1137 serial_txx9_unregister_port(i);
1138 }
1139 return 0;
1140}
1141
1142#ifdef CONFIG_PM
1143static int serial_txx9_suspend(struct platform_device *dev, pm_message_t state)
1144{
1145 int i;
1146
1147 for (i = 0; i < UART_NR; i++) {
1148 struct uart_txx9_port *up = &serial_txx9_ports[i];
1149
1150 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1151 uart_suspend_port(&serial_txx9_reg, &up->port);
1152 }
1153
1154 return 0;
1155}
1156
1157static int serial_txx9_resume(struct platform_device *dev)
1158{
1159 int i;
1160
1161 for (i = 0; i < UART_NR; i++) {
1162 struct uart_txx9_port *up = &serial_txx9_ports[i];
1163
1164 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1165 uart_resume_port(&serial_txx9_reg, &up->port);
1166 }
1167
1168 return 0;
1169}
1170#endif
1171
1172static struct platform_driver serial_txx9_plat_driver = {
1173 .probe = serial_txx9_probe,
1174 .remove = __devexit_p(serial_txx9_remove),
1175#ifdef CONFIG_PM
1176 .suspend = serial_txx9_suspend,
1177 .resume = serial_txx9_resume,
1178#endif
1179 .driver = {
1180 .name = "serial_txx9",
1181 .owner = THIS_MODULE,
1182 },
1183};
1184
1185#ifdef ENABLE_SERIAL_TXX9_PCI
1186/*
1187 * Probe one serial board. Unfortunately, there is no rhyme nor reason
1188 * to the arrangement of serial ports on a PCI card.
1189 */
1190static int __devinit
1191pciserial_txx9_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1192{
1193 struct uart_port port;
1194 int line;
1195 int rc;
1196
1197 rc = pci_enable_device(dev);
1198 if (rc)
1199 return rc;
1200
1201 memset(&port, 0, sizeof(port));
1202 port.ops = &serial_txx9_pops;
1203 port.flags |= UPF_TXX9_HAVE_CTS_LINE;
1204 port.uartclk = 66670000;
1205 port.irq = dev->irq;
1206 port.iotype = UPIO_PORT;
1207 port.iobase = pci_resource_start(dev, 1);
1208 port.dev = &dev->dev;
1209 line = serial_txx9_register_port(&port);
1210 if (line < 0) {
1211 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), line);
1212 pci_disable_device(dev);
1213 return line;
1214 }
1215 pci_set_drvdata(dev, &serial_txx9_ports[line]);
1216
1217 return 0;
1218}
1219
1220static void __devexit pciserial_txx9_remove_one(struct pci_dev *dev)
1221{
1222 struct uart_txx9_port *up = pci_get_drvdata(dev);
1223
1224 pci_set_drvdata(dev, NULL);
1225
1226 if (up) {
1227 serial_txx9_unregister_port(up->port.line);
1228 pci_disable_device(dev);
1229 }
1230}
1231
1232#ifdef CONFIG_PM
1233static int pciserial_txx9_suspend_one(struct pci_dev *dev, pm_message_t state)
1234{
1235 struct uart_txx9_port *up = pci_get_drvdata(dev);
1236
1237 if (up)
1238 uart_suspend_port(&serial_txx9_reg, &up->port);
1239 pci_save_state(dev);
1240 pci_set_power_state(dev, pci_choose_state(dev, state));
1241 return 0;
1242}
1243
1244static int pciserial_txx9_resume_one(struct pci_dev *dev)
1245{
1246 struct uart_txx9_port *up = pci_get_drvdata(dev);
1247
1248 pci_set_power_state(dev, PCI_D0);
1249 pci_restore_state(dev);
1250 if (up)
1251 uart_resume_port(&serial_txx9_reg, &up->port);
1252 return 0;
1253}
1254#endif
1255
1256static const struct pci_device_id serial_txx9_pci_tbl[] = {
1257 { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC86C001_MISC) },
1258 { 0, }
1259};
1260
1261static struct pci_driver serial_txx9_pci_driver = {
1262 .name = "serial_txx9",
1263 .probe = pciserial_txx9_init_one,
1264 .remove = __devexit_p(pciserial_txx9_remove_one),
1265#ifdef CONFIG_PM
1266 .suspend = pciserial_txx9_suspend_one,
1267 .resume = pciserial_txx9_resume_one,
1268#endif
1269 .id_table = serial_txx9_pci_tbl,
1270};
1271
1272MODULE_DEVICE_TABLE(pci, serial_txx9_pci_tbl);
1273#endif /* ENABLE_SERIAL_TXX9_PCI */
1274
1275static struct platform_device *serial_txx9_plat_devs;
1276
1277static int __init serial_txx9_init(void)
1278{
1279 int ret;
1280
1281 printk(KERN_INFO "%s version %s\n", serial_name, serial_version);
1282
1283 ret = uart_register_driver(&serial_txx9_reg);
1284 if (ret)
1285 goto out;
1286
1287 serial_txx9_plat_devs = platform_device_alloc("serial_txx9", -1);
1288 if (!serial_txx9_plat_devs) {
1289 ret = -ENOMEM;
1290 goto unreg_uart_drv;
1291 }
1292
1293 ret = platform_device_add(serial_txx9_plat_devs);
1294 if (ret)
1295 goto put_dev;
1296
1297 serial_txx9_register_ports(&serial_txx9_reg,
1298 &serial_txx9_plat_devs->dev);
1299
1300 ret = platform_driver_register(&serial_txx9_plat_driver);
1301 if (ret)
1302 goto del_dev;
1303
1304#ifdef ENABLE_SERIAL_TXX9_PCI
1305 ret = pci_register_driver(&serial_txx9_pci_driver);
1306#endif
1307 if (ret == 0)
1308 goto out;
1309
1310 del_dev:
1311 platform_device_del(serial_txx9_plat_devs);
1312 put_dev:
1313 platform_device_put(serial_txx9_plat_devs);
1314 unreg_uart_drv:
1315 uart_unregister_driver(&serial_txx9_reg);
1316 out:
1317 return ret;
1318}
1319
1320static void __exit serial_txx9_exit(void)
1321{
1322 int i;
1323
1324#ifdef ENABLE_SERIAL_TXX9_PCI
1325 pci_unregister_driver(&serial_txx9_pci_driver);
1326#endif
1327 platform_driver_unregister(&serial_txx9_plat_driver);
1328 platform_device_unregister(serial_txx9_plat_devs);
1329 for (i = 0; i < UART_NR; i++) {
1330 struct uart_txx9_port *up = &serial_txx9_ports[i];
1331 if (up->port.iobase || up->port.mapbase)
1332 uart_remove_one_port(&serial_txx9_reg, &up->port);
1333 }
1334
1335 uart_unregister_driver(&serial_txx9_reg);
1336}
1337
1338module_init(serial_txx9_init);
1339module_exit(serial_txx9_exit);
1340
1341MODULE_LICENSE("GPL");
1342MODULE_DESCRIPTION("TX39/49 serial driver");
1343
1344MODULE_ALIAS_CHARDEV_MAJOR(TXX9_TTY_MAJOR);
diff --git a/drivers/serial/sh-sci.c b/drivers/serial/sh-sci.c
deleted file mode 100644
index c291b3add1d2..000000000000
--- a/drivers/serial/sh-sci.c
+++ /dev/null
@@ -1,2027 +0,0 @@
1/*
2 * drivers/serial/sh-sci.c
3 *
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 *
6 * Copyright (C) 2002 - 2008 Paul Mundt
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
17 *
18 * This file is subject to the terms and conditions of the GNU General Public
19 * License. See the file "COPYING" in the main directory of this archive
20 * for more details.
21 */
22#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
23#define SUPPORT_SYSRQ
24#endif
25
26#undef DEBUG
27
28#include <linux/module.h>
29#include <linux/errno.h>
30#include <linux/timer.h>
31#include <linux/interrupt.h>
32#include <linux/tty.h>
33#include <linux/tty_flip.h>
34#include <linux/serial.h>
35#include <linux/major.h>
36#include <linux/string.h>
37#include <linux/sysrq.h>
38#include <linux/ioport.h>
39#include <linux/mm.h>
40#include <linux/init.h>
41#include <linux/delay.h>
42#include <linux/console.h>
43#include <linux/platform_device.h>
44#include <linux/serial_sci.h>
45#include <linux/notifier.h>
46#include <linux/cpufreq.h>
47#include <linux/clk.h>
48#include <linux/ctype.h>
49#include <linux/err.h>
50#include <linux/list.h>
51#include <linux/dmaengine.h>
52#include <linux/scatterlist.h>
53#include <linux/slab.h>
54
55#ifdef CONFIG_SUPERH
56#include <asm/sh_bios.h>
57#endif
58
59#ifdef CONFIG_H8300
60#include <asm/gpio.h>
61#endif
62
63#include "sh-sci.h"
64
65struct sci_port {
66 struct uart_port port;
67
68 /* Port type */
69 unsigned int type;
70
71 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
72 unsigned int irqs[SCIx_NR_IRQS];
73
74 /* Port enable callback */
75 void (*enable)(struct uart_port *port);
76
77 /* Port disable callback */
78 void (*disable)(struct uart_port *port);
79
80 /* Break timer */
81 struct timer_list break_timer;
82 int break_flag;
83
84 /* Interface clock */
85 struct clk *iclk;
86 /* Function clock */
87 struct clk *fclk;
88
89 struct list_head node;
90 struct dma_chan *chan_tx;
91 struct dma_chan *chan_rx;
92#ifdef CONFIG_SERIAL_SH_SCI_DMA
93 struct device *dma_dev;
94 unsigned int slave_tx;
95 unsigned int slave_rx;
96 struct dma_async_tx_descriptor *desc_tx;
97 struct dma_async_tx_descriptor *desc_rx[2];
98 dma_cookie_t cookie_tx;
99 dma_cookie_t cookie_rx[2];
100 dma_cookie_t active_rx;
101 struct scatterlist sg_tx;
102 unsigned int sg_len_tx;
103 struct scatterlist sg_rx[2];
104 size_t buf_len_rx;
105 struct sh_dmae_slave param_tx;
106 struct sh_dmae_slave param_rx;
107 struct work_struct work_tx;
108 struct work_struct work_rx;
109 struct timer_list rx_timer;
110 unsigned int rx_timeout;
111#endif
112};
113
114struct sh_sci_priv {
115 spinlock_t lock;
116 struct list_head ports;
117 struct notifier_block clk_nb;
118};
119
120/* Function prototypes */
121static void sci_stop_tx(struct uart_port *port);
122
123#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
124
125static struct sci_port sci_ports[SCI_NPORTS];
126static struct uart_driver sci_uart_driver;
127
128static inline struct sci_port *
129to_sci_port(struct uart_port *uart)
130{
131 return container_of(uart, struct sci_port, port);
132}
133
134#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
135
136#ifdef CONFIG_CONSOLE_POLL
137static inline void handle_error(struct uart_port *port)
138{
139 /* Clear error flags */
140 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
141}
142
143static int sci_poll_get_char(struct uart_port *port)
144{
145 unsigned short status;
146 int c;
147
148 do {
149 status = sci_in(port, SCxSR);
150 if (status & SCxSR_ERRORS(port)) {
151 handle_error(port);
152 continue;
153 }
154 break;
155 } while (1);
156
157 if (!(status & SCxSR_RDxF(port)))
158 return NO_POLL_CHAR;
159
160 c = sci_in(port, SCxRDR);
161
162 /* Dummy read */
163 sci_in(port, SCxSR);
164 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
165
166 return c;
167}
168#endif
169
170static void sci_poll_put_char(struct uart_port *port, unsigned char c)
171{
172 unsigned short status;
173
174 do {
175 status = sci_in(port, SCxSR);
176 } while (!(status & SCxSR_TDxE(port)));
177
178 sci_out(port, SCxTDR, c);
179 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
180}
181#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
182
183#if defined(__H8300H__) || defined(__H8300S__)
184static void sci_init_pins(struct uart_port *port, unsigned int cflag)
185{
186 int ch = (port->mapbase - SMR0) >> 3;
187
188 /* set DDR regs */
189 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
190 h8300_sci_pins[ch].rx,
191 H8300_GPIO_INPUT);
192 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
193 h8300_sci_pins[ch].tx,
194 H8300_GPIO_OUTPUT);
195
196 /* tx mark output*/
197 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
198}
199#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
200static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
201{
202 if (port->mapbase == 0xA4400000) {
203 __raw_writew(__raw_readw(PACR) & 0xffc0, PACR);
204 __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR);
205 } else if (port->mapbase == 0xA4410000)
206 __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR);
207}
208#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
209static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
210{
211 unsigned short data;
212
213 if (cflag & CRTSCTS) {
214 /* enable RTS/CTS */
215 if (port->mapbase == 0xa4430000) { /* SCIF0 */
216 /* Clear PTCR bit 9-2; enable all scif pins but sck */
217 data = __raw_readw(PORT_PTCR);
218 __raw_writew((data & 0xfc03), PORT_PTCR);
219 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
220 /* Clear PVCR bit 9-2 */
221 data = __raw_readw(PORT_PVCR);
222 __raw_writew((data & 0xfc03), PORT_PVCR);
223 }
224 } else {
225 if (port->mapbase == 0xa4430000) { /* SCIF0 */
226 /* Clear PTCR bit 5-2; enable only tx and rx */
227 data = __raw_readw(PORT_PTCR);
228 __raw_writew((data & 0xffc3), PORT_PTCR);
229 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
230 /* Clear PVCR bit 5-2 */
231 data = __raw_readw(PORT_PVCR);
232 __raw_writew((data & 0xffc3), PORT_PVCR);
233 }
234 }
235}
236#elif defined(CONFIG_CPU_SH3)
237/* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
238static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
239{
240 unsigned short data;
241
242 /* We need to set SCPCR to enable RTS/CTS */
243 data = __raw_readw(SCPCR);
244 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
245 __raw_writew(data & 0x0fcf, SCPCR);
246
247 if (!(cflag & CRTSCTS)) {
248 /* We need to set SCPCR to enable RTS/CTS */
249 data = __raw_readw(SCPCR);
250 /* Clear out SCP7MD1,0, SCP4MD1,0,
251 Set SCP6MD1,0 = {01} (output) */
252 __raw_writew((data & 0x0fcf) | 0x1000, SCPCR);
253
254 data = __raw_readb(SCPDR);
255 /* Set /RTS2 (bit6) = 0 */
256 __raw_writeb(data & 0xbf, SCPDR);
257 }
258}
259#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
260static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
261{
262 unsigned short data;
263
264 if (port->mapbase == 0xffe00000) {
265 data = __raw_readw(PSCR);
266 data &= ~0x03cf;
267 if (!(cflag & CRTSCTS))
268 data |= 0x0340;
269
270 __raw_writew(data, PSCR);
271 }
272}
273#elif defined(CONFIG_CPU_SUBTYPE_SH7757) || \
274 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
275 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
276 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
277 defined(CONFIG_CPU_SUBTYPE_SH7786) || \
278 defined(CONFIG_CPU_SUBTYPE_SHX3)
279static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
280{
281 if (!(cflag & CRTSCTS))
282 __raw_writew(0x0080, SCSPTR0); /* Set RTS = 1 */
283}
284#elif defined(CONFIG_CPU_SH4) && !defined(CONFIG_CPU_SH4A)
285static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
286{
287 if (!(cflag & CRTSCTS))
288 __raw_writew(0x0080, SCSPTR2); /* Set RTS = 1 */
289}
290#else
291static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
292{
293 /* Nothing to do */
294}
295#endif
296
297#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
298 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
299 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
300 defined(CONFIG_CPU_SUBTYPE_SH7786)
301static int scif_txfill(struct uart_port *port)
302{
303 return sci_in(port, SCTFDR) & 0xff;
304}
305
306static int scif_txroom(struct uart_port *port)
307{
308 return SCIF_TXROOM_MAX - scif_txfill(port);
309}
310
311static int scif_rxfill(struct uart_port *port)
312{
313 return sci_in(port, SCRFDR) & 0xff;
314}
315#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
316static int scif_txfill(struct uart_port *port)
317{
318 if (port->mapbase == 0xffe00000 ||
319 port->mapbase == 0xffe08000)
320 /* SCIF0/1*/
321 return sci_in(port, SCTFDR) & 0xff;
322 else
323 /* SCIF2 */
324 return sci_in(port, SCFDR) >> 8;
325}
326
327static int scif_txroom(struct uart_port *port)
328{
329 if (port->mapbase == 0xffe00000 ||
330 port->mapbase == 0xffe08000)
331 /* SCIF0/1*/
332 return SCIF_TXROOM_MAX - scif_txfill(port);
333 else
334 /* SCIF2 */
335 return SCIF2_TXROOM_MAX - scif_txfill(port);
336}
337
338static int scif_rxfill(struct uart_port *port)
339{
340 if ((port->mapbase == 0xffe00000) ||
341 (port->mapbase == 0xffe08000)) {
342 /* SCIF0/1*/
343 return sci_in(port, SCRFDR) & 0xff;
344 } else {
345 /* SCIF2 */
346 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
347 }
348}
349#elif defined(CONFIG_ARCH_SH7372)
350static int scif_txfill(struct uart_port *port)
351{
352 if (port->type == PORT_SCIFA)
353 return sci_in(port, SCFDR) >> 8;
354 else
355 return sci_in(port, SCTFDR);
356}
357
358static int scif_txroom(struct uart_port *port)
359{
360 return port->fifosize - scif_txfill(port);
361}
362
363static int scif_rxfill(struct uart_port *port)
364{
365 if (port->type == PORT_SCIFA)
366 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
367 else
368 return sci_in(port, SCRFDR);
369}
370#else
371static int scif_txfill(struct uart_port *port)
372{
373 return sci_in(port, SCFDR) >> 8;
374}
375
376static int scif_txroom(struct uart_port *port)
377{
378 return SCIF_TXROOM_MAX - scif_txfill(port);
379}
380
381static int scif_rxfill(struct uart_port *port)
382{
383 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
384}
385#endif
386
387static int sci_txfill(struct uart_port *port)
388{
389 return !(sci_in(port, SCxSR) & SCI_TDRE);
390}
391
392static int sci_txroom(struct uart_port *port)
393{
394 return !sci_txfill(port);
395}
396
397static int sci_rxfill(struct uart_port *port)
398{
399 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
400}
401
402/* ********************************************************************** *
403 * the interrupt related routines *
404 * ********************************************************************** */
405
406static void sci_transmit_chars(struct uart_port *port)
407{
408 struct circ_buf *xmit = &port->state->xmit;
409 unsigned int stopped = uart_tx_stopped(port);
410 unsigned short status;
411 unsigned short ctrl;
412 int count;
413
414 status = sci_in(port, SCxSR);
415 if (!(status & SCxSR_TDxE(port))) {
416 ctrl = sci_in(port, SCSCR);
417 if (uart_circ_empty(xmit))
418 ctrl &= ~SCI_CTRL_FLAGS_TIE;
419 else
420 ctrl |= SCI_CTRL_FLAGS_TIE;
421 sci_out(port, SCSCR, ctrl);
422 return;
423 }
424
425 if (port->type == PORT_SCI)
426 count = sci_txroom(port);
427 else
428 count = scif_txroom(port);
429
430 do {
431 unsigned char c;
432
433 if (port->x_char) {
434 c = port->x_char;
435 port->x_char = 0;
436 } else if (!uart_circ_empty(xmit) && !stopped) {
437 c = xmit->buf[xmit->tail];
438 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
439 } else {
440 break;
441 }
442
443 sci_out(port, SCxTDR, c);
444
445 port->icount.tx++;
446 } while (--count > 0);
447
448 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
449
450 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
451 uart_write_wakeup(port);
452 if (uart_circ_empty(xmit)) {
453 sci_stop_tx(port);
454 } else {
455 ctrl = sci_in(port, SCSCR);
456
457 if (port->type != PORT_SCI) {
458 sci_in(port, SCxSR); /* Dummy read */
459 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
460 }
461
462 ctrl |= SCI_CTRL_FLAGS_TIE;
463 sci_out(port, SCSCR, ctrl);
464 }
465}
466
467/* On SH3, SCIF may read end-of-break as a space->mark char */
468#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
469
470static inline void sci_receive_chars(struct uart_port *port)
471{
472 struct sci_port *sci_port = to_sci_port(port);
473 struct tty_struct *tty = port->state->port.tty;
474 int i, count, copied = 0;
475 unsigned short status;
476 unsigned char flag;
477
478 status = sci_in(port, SCxSR);
479 if (!(status & SCxSR_RDxF(port)))
480 return;
481
482 while (1) {
483 if (port->type == PORT_SCI)
484 count = sci_rxfill(port);
485 else
486 count = scif_rxfill(port);
487
488 /* Don't copy more bytes than there is room for in the buffer */
489 count = tty_buffer_request_room(tty, count);
490
491 /* If for any reason we can't copy more data, we're done! */
492 if (count == 0)
493 break;
494
495 if (port->type == PORT_SCI) {
496 char c = sci_in(port, SCxRDR);
497 if (uart_handle_sysrq_char(port, c) ||
498 sci_port->break_flag)
499 count = 0;
500 else
501 tty_insert_flip_char(tty, c, TTY_NORMAL);
502 } else {
503 for (i = 0; i < count; i++) {
504 char c = sci_in(port, SCxRDR);
505 status = sci_in(port, SCxSR);
506#if defined(CONFIG_CPU_SH3)
507 /* Skip "chars" during break */
508 if (sci_port->break_flag) {
509 if ((c == 0) &&
510 (status & SCxSR_FER(port))) {
511 count--; i--;
512 continue;
513 }
514
515 /* Nonzero => end-of-break */
516 dev_dbg(port->dev, "debounce<%02x>\n", c);
517 sci_port->break_flag = 0;
518
519 if (STEPFN(c)) {
520 count--; i--;
521 continue;
522 }
523 }
524#endif /* CONFIG_CPU_SH3 */
525 if (uart_handle_sysrq_char(port, c)) {
526 count--; i--;
527 continue;
528 }
529
530 /* Store data and status */
531 if (status & SCxSR_FER(port)) {
532 flag = TTY_FRAME;
533 dev_notice(port->dev, "frame error\n");
534 } else if (status & SCxSR_PER(port)) {
535 flag = TTY_PARITY;
536 dev_notice(port->dev, "parity error\n");
537 } else
538 flag = TTY_NORMAL;
539
540 tty_insert_flip_char(tty, c, flag);
541 }
542 }
543
544 sci_in(port, SCxSR); /* dummy read */
545 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
546
547 copied += count;
548 port->icount.rx += count;
549 }
550
551 if (copied) {
552 /* Tell the rest of the system the news. New characters! */
553 tty_flip_buffer_push(tty);
554 } else {
555 sci_in(port, SCxSR); /* dummy read */
556 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
557 }
558}
559
560#define SCI_BREAK_JIFFIES (HZ/20)
561/* The sci generates interrupts during the break,
562 * 1 per millisecond or so during the break period, for 9600 baud.
563 * So dont bother disabling interrupts.
564 * But dont want more than 1 break event.
565 * Use a kernel timer to periodically poll the rx line until
566 * the break is finished.
567 */
568static void sci_schedule_break_timer(struct sci_port *port)
569{
570 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
571 add_timer(&port->break_timer);
572}
573/* Ensure that two consecutive samples find the break over. */
574static void sci_break_timer(unsigned long data)
575{
576 struct sci_port *port = (struct sci_port *)data;
577
578 if (sci_rxd_in(&port->port) == 0) {
579 port->break_flag = 1;
580 sci_schedule_break_timer(port);
581 } else if (port->break_flag == 1) {
582 /* break is over. */
583 port->break_flag = 2;
584 sci_schedule_break_timer(port);
585 } else
586 port->break_flag = 0;
587}
588
589static inline int sci_handle_errors(struct uart_port *port)
590{
591 int copied = 0;
592 unsigned short status = sci_in(port, SCxSR);
593 struct tty_struct *tty = port->state->port.tty;
594
595 if (status & SCxSR_ORER(port)) {
596 /* overrun error */
597 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
598 copied++;
599
600 dev_notice(port->dev, "overrun error");
601 }
602
603 if (status & SCxSR_FER(port)) {
604 if (sci_rxd_in(port) == 0) {
605 /* Notify of BREAK */
606 struct sci_port *sci_port = to_sci_port(port);
607
608 if (!sci_port->break_flag) {
609 sci_port->break_flag = 1;
610 sci_schedule_break_timer(sci_port);
611
612 /* Do sysrq handling. */
613 if (uart_handle_break(port))
614 return 0;
615
616 dev_dbg(port->dev, "BREAK detected\n");
617
618 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
619 copied++;
620 }
621
622 } else {
623 /* frame error */
624 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
625 copied++;
626
627 dev_notice(port->dev, "frame error\n");
628 }
629 }
630
631 if (status & SCxSR_PER(port)) {
632 /* parity error */
633 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
634 copied++;
635
636 dev_notice(port->dev, "parity error");
637 }
638
639 if (copied)
640 tty_flip_buffer_push(tty);
641
642 return copied;
643}
644
645static inline int sci_handle_fifo_overrun(struct uart_port *port)
646{
647 struct tty_struct *tty = port->state->port.tty;
648 int copied = 0;
649
650 if (port->type != PORT_SCIF)
651 return 0;
652
653 if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
654 sci_out(port, SCLSR, 0);
655
656 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
657 tty_flip_buffer_push(tty);
658
659 dev_notice(port->dev, "overrun error\n");
660 copied++;
661 }
662
663 return copied;
664}
665
666static inline int sci_handle_breaks(struct uart_port *port)
667{
668 int copied = 0;
669 unsigned short status = sci_in(port, SCxSR);
670 struct tty_struct *tty = port->state->port.tty;
671 struct sci_port *s = to_sci_port(port);
672
673 if (uart_handle_break(port))
674 return 0;
675
676 if (!s->break_flag && status & SCxSR_BRK(port)) {
677#if defined(CONFIG_CPU_SH3)
678 /* Debounce break */
679 s->break_flag = 1;
680#endif
681 /* Notify of BREAK */
682 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
683 copied++;
684
685 dev_dbg(port->dev, "BREAK detected\n");
686 }
687
688 if (copied)
689 tty_flip_buffer_push(tty);
690
691 copied += sci_handle_fifo_overrun(port);
692
693 return copied;
694}
695
696static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
697{
698#ifdef CONFIG_SERIAL_SH_SCI_DMA
699 struct uart_port *port = ptr;
700 struct sci_port *s = to_sci_port(port);
701
702 if (s->chan_rx) {
703 u16 scr = sci_in(port, SCSCR);
704 u16 ssr = sci_in(port, SCxSR);
705
706 /* Disable future Rx interrupts */
707 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
708 disable_irq_nosync(irq);
709 scr |= 0x4000;
710 } else {
711 scr &= ~SCI_CTRL_FLAGS_RIE;
712 }
713 sci_out(port, SCSCR, scr);
714 /* Clear current interrupt */
715 sci_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
716 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
717 jiffies, s->rx_timeout);
718 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
719
720 return IRQ_HANDLED;
721 }
722#endif
723
724 /* I think sci_receive_chars has to be called irrespective
725 * of whether the I_IXOFF is set, otherwise, how is the interrupt
726 * to be disabled?
727 */
728 sci_receive_chars(ptr);
729
730 return IRQ_HANDLED;
731}
732
733static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
734{
735 struct uart_port *port = ptr;
736 unsigned long flags;
737
738 spin_lock_irqsave(&port->lock, flags);
739 sci_transmit_chars(port);
740 spin_unlock_irqrestore(&port->lock, flags);
741
742 return IRQ_HANDLED;
743}
744
745static irqreturn_t sci_er_interrupt(int irq, void *ptr)
746{
747 struct uart_port *port = ptr;
748
749 /* Handle errors */
750 if (port->type == PORT_SCI) {
751 if (sci_handle_errors(port)) {
752 /* discard character in rx buffer */
753 sci_in(port, SCxSR);
754 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
755 }
756 } else {
757 sci_handle_fifo_overrun(port);
758 sci_rx_interrupt(irq, ptr);
759 }
760
761 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
762
763 /* Kick the transmission */
764 sci_tx_interrupt(irq, ptr);
765
766 return IRQ_HANDLED;
767}
768
769static irqreturn_t sci_br_interrupt(int irq, void *ptr)
770{
771 struct uart_port *port = ptr;
772
773 /* Handle BREAKs */
774 sci_handle_breaks(port);
775 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
776
777 return IRQ_HANDLED;
778}
779
780static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
781{
782 unsigned short ssr_status, scr_status, err_enabled;
783 struct uart_port *port = ptr;
784 struct sci_port *s = to_sci_port(port);
785 irqreturn_t ret = IRQ_NONE;
786
787 ssr_status = sci_in(port, SCxSR);
788 scr_status = sci_in(port, SCSCR);
789 err_enabled = scr_status & (SCI_CTRL_FLAGS_REIE | SCI_CTRL_FLAGS_RIE);
790
791 /* Tx Interrupt */
792 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCI_CTRL_FLAGS_TIE) &&
793 !s->chan_tx)
794 ret = sci_tx_interrupt(irq, ptr);
795 /*
796 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
797 * DR flags
798 */
799 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
800 (scr_status & SCI_CTRL_FLAGS_RIE))
801 ret = sci_rx_interrupt(irq, ptr);
802 /* Error Interrupt */
803 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
804 ret = sci_er_interrupt(irq, ptr);
805 /* Break Interrupt */
806 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
807 ret = sci_br_interrupt(irq, ptr);
808
809 return ret;
810}
811
812/*
813 * Here we define a transistion notifier so that we can update all of our
814 * ports' baud rate when the peripheral clock changes.
815 */
816static int sci_notifier(struct notifier_block *self,
817 unsigned long phase, void *p)
818{
819 struct sh_sci_priv *priv = container_of(self,
820 struct sh_sci_priv, clk_nb);
821 struct sci_port *sci_port;
822 unsigned long flags;
823
824 if ((phase == CPUFREQ_POSTCHANGE) ||
825 (phase == CPUFREQ_RESUMECHANGE)) {
826 spin_lock_irqsave(&priv->lock, flags);
827 list_for_each_entry(sci_port, &priv->ports, node)
828 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
829 spin_unlock_irqrestore(&priv->lock, flags);
830 }
831
832 return NOTIFY_OK;
833}
834
835static void sci_clk_enable(struct uart_port *port)
836{
837 struct sci_port *sci_port = to_sci_port(port);
838
839 clk_enable(sci_port->iclk);
840 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
841 clk_enable(sci_port->fclk);
842}
843
844static void sci_clk_disable(struct uart_port *port)
845{
846 struct sci_port *sci_port = to_sci_port(port);
847
848 clk_disable(sci_port->fclk);
849 clk_disable(sci_port->iclk);
850}
851
852static int sci_request_irq(struct sci_port *port)
853{
854 int i;
855 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
856 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
857 sci_br_interrupt,
858 };
859 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
860 "SCI Transmit Data Empty", "SCI Break" };
861
862 if (port->irqs[0] == port->irqs[1]) {
863 if (unlikely(!port->irqs[0]))
864 return -ENODEV;
865
866 if (request_irq(port->irqs[0], sci_mpxed_interrupt,
867 IRQF_DISABLED, "sci", port)) {
868 dev_err(port->port.dev, "Can't allocate IRQ\n");
869 return -ENODEV;
870 }
871 } else {
872 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
873 if (unlikely(!port->irqs[i]))
874 continue;
875
876 if (request_irq(port->irqs[i], handlers[i],
877 IRQF_DISABLED, desc[i], port)) {
878 dev_err(port->port.dev, "Can't allocate IRQ\n");
879 return -ENODEV;
880 }
881 }
882 }
883
884 return 0;
885}
886
887static void sci_free_irq(struct sci_port *port)
888{
889 int i;
890
891 if (port->irqs[0] == port->irqs[1])
892 free_irq(port->irqs[0], port);
893 else {
894 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
895 if (!port->irqs[i])
896 continue;
897
898 free_irq(port->irqs[i], port);
899 }
900 }
901}
902
903static unsigned int sci_tx_empty(struct uart_port *port)
904{
905 unsigned short status = sci_in(port, SCxSR);
906 unsigned short in_tx_fifo = scif_txfill(port);
907
908 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
909}
910
911static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
912{
913 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
914 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
915 /* If you have signals for DTR and DCD, please implement here. */
916}
917
918static unsigned int sci_get_mctrl(struct uart_port *port)
919{
920 /* This routine is used for getting signals of: DTR, DCD, DSR, RI,
921 and CTS/RTS */
922
923 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
924}
925
926#ifdef CONFIG_SERIAL_SH_SCI_DMA
927static void sci_dma_tx_complete(void *arg)
928{
929 struct sci_port *s = arg;
930 struct uart_port *port = &s->port;
931 struct circ_buf *xmit = &port->state->xmit;
932 unsigned long flags;
933
934 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
935
936 spin_lock_irqsave(&port->lock, flags);
937
938 xmit->tail += sg_dma_len(&s->sg_tx);
939 xmit->tail &= UART_XMIT_SIZE - 1;
940
941 port->icount.tx += sg_dma_len(&s->sg_tx);
942
943 async_tx_ack(s->desc_tx);
944 s->cookie_tx = -EINVAL;
945 s->desc_tx = NULL;
946
947 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
948 uart_write_wakeup(port);
949
950 if (!uart_circ_empty(xmit)) {
951 schedule_work(&s->work_tx);
952 } else if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
953 u16 ctrl = sci_in(port, SCSCR);
954 sci_out(port, SCSCR, ctrl & ~SCI_CTRL_FLAGS_TIE);
955 }
956
957 spin_unlock_irqrestore(&port->lock, flags);
958}
959
960/* Locking: called with port lock held */
961static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty,
962 size_t count)
963{
964 struct uart_port *port = &s->port;
965 int i, active, room;
966
967 room = tty_buffer_request_room(tty, count);
968
969 if (s->active_rx == s->cookie_rx[0]) {
970 active = 0;
971 } else if (s->active_rx == s->cookie_rx[1]) {
972 active = 1;
973 } else {
974 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
975 return 0;
976 }
977
978 if (room < count)
979 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
980 count - room);
981 if (!room)
982 return room;
983
984 for (i = 0; i < room; i++)
985 tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
986 TTY_NORMAL);
987
988 port->icount.rx += room;
989
990 return room;
991}
992
993static void sci_dma_rx_complete(void *arg)
994{
995 struct sci_port *s = arg;
996 struct uart_port *port = &s->port;
997 struct tty_struct *tty = port->state->port.tty;
998 unsigned long flags;
999 int count;
1000
1001 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
1002
1003 spin_lock_irqsave(&port->lock, flags);
1004
1005 count = sci_dma_rx_push(s, tty, s->buf_len_rx);
1006
1007 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1008
1009 spin_unlock_irqrestore(&port->lock, flags);
1010
1011 if (count)
1012 tty_flip_buffer_push(tty);
1013
1014 schedule_work(&s->work_rx);
1015}
1016
1017static void sci_start_rx(struct uart_port *port);
1018static void sci_start_tx(struct uart_port *port);
1019
1020static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1021{
1022 struct dma_chan *chan = s->chan_rx;
1023 struct uart_port *port = &s->port;
1024
1025 s->chan_rx = NULL;
1026 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1027 dma_release_channel(chan);
1028 if (sg_dma_address(&s->sg_rx[0]))
1029 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1030 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
1031 if (enable_pio)
1032 sci_start_rx(port);
1033}
1034
1035static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1036{
1037 struct dma_chan *chan = s->chan_tx;
1038 struct uart_port *port = &s->port;
1039
1040 s->chan_tx = NULL;
1041 s->cookie_tx = -EINVAL;
1042 dma_release_channel(chan);
1043 if (enable_pio)
1044 sci_start_tx(port);
1045}
1046
1047static void sci_submit_rx(struct sci_port *s)
1048{
1049 struct dma_chan *chan = s->chan_rx;
1050 int i;
1051
1052 for (i = 0; i < 2; i++) {
1053 struct scatterlist *sg = &s->sg_rx[i];
1054 struct dma_async_tx_descriptor *desc;
1055
1056 desc = chan->device->device_prep_slave_sg(chan,
1057 sg, 1, DMA_FROM_DEVICE, DMA_PREP_INTERRUPT);
1058
1059 if (desc) {
1060 s->desc_rx[i] = desc;
1061 desc->callback = sci_dma_rx_complete;
1062 desc->callback_param = s;
1063 s->cookie_rx[i] = desc->tx_submit(desc);
1064 }
1065
1066 if (!desc || s->cookie_rx[i] < 0) {
1067 if (i) {
1068 async_tx_ack(s->desc_rx[0]);
1069 s->cookie_rx[0] = -EINVAL;
1070 }
1071 if (desc) {
1072 async_tx_ack(desc);
1073 s->cookie_rx[i] = -EINVAL;
1074 }
1075 dev_warn(s->port.dev,
1076 "failed to re-start DMA, using PIO\n");
1077 sci_rx_dma_release(s, true);
1078 return;
1079 }
1080 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1081 s->cookie_rx[i], i);
1082 }
1083
1084 s->active_rx = s->cookie_rx[0];
1085
1086 dma_async_issue_pending(chan);
1087}
1088
1089static void work_fn_rx(struct work_struct *work)
1090{
1091 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1092 struct uart_port *port = &s->port;
1093 struct dma_async_tx_descriptor *desc;
1094 int new;
1095
1096 if (s->active_rx == s->cookie_rx[0]) {
1097 new = 0;
1098 } else if (s->active_rx == s->cookie_rx[1]) {
1099 new = 1;
1100 } else {
1101 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1102 return;
1103 }
1104 desc = s->desc_rx[new];
1105
1106 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1107 DMA_SUCCESS) {
1108 /* Handle incomplete DMA receive */
1109 struct tty_struct *tty = port->state->port.tty;
1110 struct dma_chan *chan = s->chan_rx;
1111 struct sh_desc *sh_desc = container_of(desc, struct sh_desc,
1112 async_tx);
1113 unsigned long flags;
1114 int count;
1115
1116 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
1117 dev_dbg(port->dev, "Read %u bytes with cookie %d\n",
1118 sh_desc->partial, sh_desc->cookie);
1119
1120 spin_lock_irqsave(&port->lock, flags);
1121 count = sci_dma_rx_push(s, tty, sh_desc->partial);
1122 spin_unlock_irqrestore(&port->lock, flags);
1123
1124 if (count)
1125 tty_flip_buffer_push(tty);
1126
1127 sci_submit_rx(s);
1128
1129 return;
1130 }
1131
1132 s->cookie_rx[new] = desc->tx_submit(desc);
1133 if (s->cookie_rx[new] < 0) {
1134 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1135 sci_rx_dma_release(s, true);
1136 return;
1137 }
1138
1139 s->active_rx = s->cookie_rx[!new];
1140
1141 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
1142 s->cookie_rx[new], new, s->active_rx);
1143}
1144
1145static void work_fn_tx(struct work_struct *work)
1146{
1147 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1148 struct dma_async_tx_descriptor *desc;
1149 struct dma_chan *chan = s->chan_tx;
1150 struct uart_port *port = &s->port;
1151 struct circ_buf *xmit = &port->state->xmit;
1152 struct scatterlist *sg = &s->sg_tx;
1153
1154 /*
1155 * DMA is idle now.
1156 * Port xmit buffer is already mapped, and it is one page... Just adjust
1157 * offsets and lengths. Since it is a circular buffer, we have to
1158 * transmit till the end, and then the rest. Take the port lock to get a
1159 * consistent xmit buffer state.
1160 */
1161 spin_lock_irq(&port->lock);
1162 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
1163 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
1164 sg->offset;
1165 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1166 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1167 spin_unlock_irq(&port->lock);
1168
1169 BUG_ON(!sg_dma_len(sg));
1170
1171 desc = chan->device->device_prep_slave_sg(chan,
1172 sg, s->sg_len_tx, DMA_TO_DEVICE,
1173 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1174 if (!desc) {
1175 /* switch to PIO */
1176 sci_tx_dma_release(s, true);
1177 return;
1178 }
1179
1180 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1181
1182 spin_lock_irq(&port->lock);
1183 s->desc_tx = desc;
1184 desc->callback = sci_dma_tx_complete;
1185 desc->callback_param = s;
1186 spin_unlock_irq(&port->lock);
1187 s->cookie_tx = desc->tx_submit(desc);
1188 if (s->cookie_tx < 0) {
1189 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1190 /* switch to PIO */
1191 sci_tx_dma_release(s, true);
1192 return;
1193 }
1194
1195 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1196 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1197
1198 dma_async_issue_pending(chan);
1199}
1200#endif
1201
1202static void sci_start_tx(struct uart_port *port)
1203{
1204 struct sci_port *s = to_sci_port(port);
1205 unsigned short ctrl;
1206
1207#ifdef CONFIG_SERIAL_SH_SCI_DMA
1208 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1209 u16 new, scr = sci_in(port, SCSCR);
1210 if (s->chan_tx)
1211 new = scr | 0x8000;
1212 else
1213 new = scr & ~0x8000;
1214 if (new != scr)
1215 sci_out(port, SCSCR, new);
1216 }
1217 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1218 s->cookie_tx < 0)
1219 schedule_work(&s->work_tx);
1220#endif
1221 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1222 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1223 ctrl = sci_in(port, SCSCR);
1224 sci_out(port, SCSCR, ctrl | SCI_CTRL_FLAGS_TIE);
1225 }
1226}
1227
1228static void sci_stop_tx(struct uart_port *port)
1229{
1230 unsigned short ctrl;
1231
1232 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1233 ctrl = sci_in(port, SCSCR);
1234 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1235 ctrl &= ~0x8000;
1236 ctrl &= ~SCI_CTRL_FLAGS_TIE;
1237 sci_out(port, SCSCR, ctrl);
1238}
1239
1240static void sci_start_rx(struct uart_port *port)
1241{
1242 unsigned short ctrl = SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
1243
1244 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
1245 ctrl |= sci_in(port, SCSCR);
1246 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1247 ctrl &= ~0x4000;
1248 sci_out(port, SCSCR, ctrl);
1249}
1250
1251static void sci_stop_rx(struct uart_port *port)
1252{
1253 unsigned short ctrl;
1254
1255 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
1256 ctrl = sci_in(port, SCSCR);
1257 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1258 ctrl &= ~0x4000;
1259 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
1260 sci_out(port, SCSCR, ctrl);
1261}
1262
1263static void sci_enable_ms(struct uart_port *port)
1264{
1265 /* Nothing here yet .. */
1266}
1267
1268static void sci_break_ctl(struct uart_port *port, int break_state)
1269{
1270 /* Nothing here yet .. */
1271}
1272
1273#ifdef CONFIG_SERIAL_SH_SCI_DMA
1274static bool filter(struct dma_chan *chan, void *slave)
1275{
1276 struct sh_dmae_slave *param = slave;
1277
1278 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
1279 param->slave_id);
1280
1281 if (param->dma_dev == chan->device->dev) {
1282 chan->private = param;
1283 return true;
1284 } else {
1285 return false;
1286 }
1287}
1288
1289static void rx_timer_fn(unsigned long arg)
1290{
1291 struct sci_port *s = (struct sci_port *)arg;
1292 struct uart_port *port = &s->port;
1293 u16 scr = sci_in(port, SCSCR);
1294
1295 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1296 scr &= ~0x4000;
1297 enable_irq(s->irqs[1]);
1298 }
1299 sci_out(port, SCSCR, scr | SCI_CTRL_FLAGS_RIE);
1300 dev_dbg(port->dev, "DMA Rx timed out\n");
1301 schedule_work(&s->work_rx);
1302}
1303
1304static void sci_request_dma(struct uart_port *port)
1305{
1306 struct sci_port *s = to_sci_port(port);
1307 struct sh_dmae_slave *param;
1308 struct dma_chan *chan;
1309 dma_cap_mask_t mask;
1310 int nent;
1311
1312 dev_dbg(port->dev, "%s: port %d DMA %p\n", __func__,
1313 port->line, s->dma_dev);
1314
1315 if (!s->dma_dev)
1316 return;
1317
1318 dma_cap_zero(mask);
1319 dma_cap_set(DMA_SLAVE, mask);
1320
1321 param = &s->param_tx;
1322
1323 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1324 param->slave_id = s->slave_tx;
1325 param->dma_dev = s->dma_dev;
1326
1327 s->cookie_tx = -EINVAL;
1328 chan = dma_request_channel(mask, filter, param);
1329 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1330 if (chan) {
1331 s->chan_tx = chan;
1332 sg_init_table(&s->sg_tx, 1);
1333 /* UART circular tx buffer is an aligned page. */
1334 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
1335 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1336 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK);
1337 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1338 if (!nent)
1339 sci_tx_dma_release(s, false);
1340 else
1341 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1342 sg_dma_len(&s->sg_tx),
1343 port->state->xmit.buf, sg_dma_address(&s->sg_tx));
1344
1345 s->sg_len_tx = nent;
1346
1347 INIT_WORK(&s->work_tx, work_fn_tx);
1348 }
1349
1350 param = &s->param_rx;
1351
1352 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1353 param->slave_id = s->slave_rx;
1354 param->dma_dev = s->dma_dev;
1355
1356 chan = dma_request_channel(mask, filter, param);
1357 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1358 if (chan) {
1359 dma_addr_t dma[2];
1360 void *buf[2];
1361 int i;
1362
1363 s->chan_rx = chan;
1364
1365 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1366 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1367 &dma[0], GFP_KERNEL);
1368
1369 if (!buf[0]) {
1370 dev_warn(port->dev,
1371 "failed to allocate dma buffer, using PIO\n");
1372 sci_rx_dma_release(s, true);
1373 return;
1374 }
1375
1376 buf[1] = buf[0] + s->buf_len_rx;
1377 dma[1] = dma[0] + s->buf_len_rx;
1378
1379 for (i = 0; i < 2; i++) {
1380 struct scatterlist *sg = &s->sg_rx[i];
1381
1382 sg_init_table(sg, 1);
1383 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1384 (int)buf[i] & ~PAGE_MASK);
1385 sg_dma_address(sg) = dma[i];
1386 }
1387
1388 INIT_WORK(&s->work_rx, work_fn_rx);
1389 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1390
1391 sci_submit_rx(s);
1392 }
1393}
1394
1395static void sci_free_dma(struct uart_port *port)
1396{
1397 struct sci_port *s = to_sci_port(port);
1398
1399 if (!s->dma_dev)
1400 return;
1401
1402 if (s->chan_tx)
1403 sci_tx_dma_release(s, false);
1404 if (s->chan_rx)
1405 sci_rx_dma_release(s, false);
1406}
1407#endif
1408
1409static int sci_startup(struct uart_port *port)
1410{
1411 struct sci_port *s = to_sci_port(port);
1412
1413 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1414
1415 if (s->enable)
1416 s->enable(port);
1417
1418 sci_request_irq(s);
1419#ifdef CONFIG_SERIAL_SH_SCI_DMA
1420 sci_request_dma(port);
1421#endif
1422 sci_start_tx(port);
1423 sci_start_rx(port);
1424
1425 return 0;
1426}
1427
1428static void sci_shutdown(struct uart_port *port)
1429{
1430 struct sci_port *s = to_sci_port(port);
1431
1432 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1433
1434 sci_stop_rx(port);
1435 sci_stop_tx(port);
1436#ifdef CONFIG_SERIAL_SH_SCI_DMA
1437 sci_free_dma(port);
1438#endif
1439 sci_free_irq(s);
1440
1441 if (s->disable)
1442 s->disable(port);
1443}
1444
1445static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1446 struct ktermios *old)
1447{
1448#ifdef CONFIG_SERIAL_SH_SCI_DMA
1449 struct sci_port *s = to_sci_port(port);
1450#endif
1451 unsigned int status, baud, smr_val, max_baud;
1452 int t = -1;
1453 u16 scfcr = 0;
1454
1455 /*
1456 * earlyprintk comes here early on with port->uartclk set to zero.
1457 * the clock framework is not up and running at this point so here
1458 * we assume that 115200 is the maximum baud rate. please note that
1459 * the baud rate is not programmed during earlyprintk - it is assumed
1460 * that the previous boot loader has enabled required clocks and
1461 * setup the baud rate generator hardware for us already.
1462 */
1463 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1464
1465 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1466 if (likely(baud && port->uartclk))
1467 t = SCBRR_VALUE(baud, port->uartclk);
1468
1469 do {
1470 status = sci_in(port, SCxSR);
1471 } while (!(status & SCxSR_TEND(port)));
1472
1473 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1474
1475 if (port->type != PORT_SCI)
1476 sci_out(port, SCFCR, scfcr | SCFCR_RFRST | SCFCR_TFRST);
1477
1478 smr_val = sci_in(port, SCSMR) & 3;
1479 if ((termios->c_cflag & CSIZE) == CS7)
1480 smr_val |= 0x40;
1481 if (termios->c_cflag & PARENB)
1482 smr_val |= 0x20;
1483 if (termios->c_cflag & PARODD)
1484 smr_val |= 0x30;
1485 if (termios->c_cflag & CSTOPB)
1486 smr_val |= 0x08;
1487
1488 uart_update_timeout(port, termios->c_cflag, baud);
1489
1490 sci_out(port, SCSMR, smr_val);
1491
1492 dev_dbg(port->dev, "%s: SMR %x, t %x, SCSCR %x\n", __func__, smr_val, t,
1493 SCSCR_INIT(port));
1494
1495 if (t > 0) {
1496 if (t >= 256) {
1497 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1498 t >>= 2;
1499 } else
1500 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
1501
1502 sci_out(port, SCBRR, t);
1503 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1504 }
1505
1506 sci_init_pins(port, termios->c_cflag);
1507 sci_out(port, SCFCR, scfcr | ((termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0));
1508
1509 sci_out(port, SCSCR, SCSCR_INIT(port));
1510
1511#ifdef CONFIG_SERIAL_SH_SCI_DMA
1512 /*
1513 * Calculate delay for 1.5 DMA buffers: see
1514 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1515 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1516 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1517 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1518 * sizes), but it has been found out experimentally, that this is not
1519 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1520 * as a minimum seem to work perfectly.
1521 */
1522 if (s->chan_rx) {
1523 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1524 port->fifosize / 2;
1525 dev_dbg(port->dev,
1526 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1527 s->rx_timeout * 1000 / HZ, port->timeout);
1528 if (s->rx_timeout < msecs_to_jiffies(20))
1529 s->rx_timeout = msecs_to_jiffies(20);
1530 }
1531#endif
1532
1533 if ((termios->c_cflag & CREAD) != 0)
1534 sci_start_rx(port);
1535}
1536
1537static const char *sci_type(struct uart_port *port)
1538{
1539 switch (port->type) {
1540 case PORT_IRDA:
1541 return "irda";
1542 case PORT_SCI:
1543 return "sci";
1544 case PORT_SCIF:
1545 return "scif";
1546 case PORT_SCIFA:
1547 return "scifa";
1548 case PORT_SCIFB:
1549 return "scifb";
1550 }
1551
1552 return NULL;
1553}
1554
1555static void sci_release_port(struct uart_port *port)
1556{
1557 /* Nothing here yet .. */
1558}
1559
1560static int sci_request_port(struct uart_port *port)
1561{
1562 /* Nothing here yet .. */
1563 return 0;
1564}
1565
1566static void sci_config_port(struct uart_port *port, int flags)
1567{
1568 struct sci_port *s = to_sci_port(port);
1569
1570 port->type = s->type;
1571
1572 if (port->membase)
1573 return;
1574
1575 if (port->flags & UPF_IOREMAP) {
1576 port->membase = ioremap_nocache(port->mapbase, 0x40);
1577
1578 if (IS_ERR(port->membase))
1579 dev_err(port->dev, "can't remap port#%d\n", port->line);
1580 } else {
1581 /*
1582 * For the simple (and majority of) cases where we don't
1583 * need to do any remapping, just cast the cookie
1584 * directly.
1585 */
1586 port->membase = (void __iomem *)port->mapbase;
1587 }
1588}
1589
1590static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1591{
1592 struct sci_port *s = to_sci_port(port);
1593
1594 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1595 return -EINVAL;
1596 if (ser->baud_base < 2400)
1597 /* No paper tape reader for Mitch.. */
1598 return -EINVAL;
1599
1600 return 0;
1601}
1602
1603static struct uart_ops sci_uart_ops = {
1604 .tx_empty = sci_tx_empty,
1605 .set_mctrl = sci_set_mctrl,
1606 .get_mctrl = sci_get_mctrl,
1607 .start_tx = sci_start_tx,
1608 .stop_tx = sci_stop_tx,
1609 .stop_rx = sci_stop_rx,
1610 .enable_ms = sci_enable_ms,
1611 .break_ctl = sci_break_ctl,
1612 .startup = sci_startup,
1613 .shutdown = sci_shutdown,
1614 .set_termios = sci_set_termios,
1615 .type = sci_type,
1616 .release_port = sci_release_port,
1617 .request_port = sci_request_port,
1618 .config_port = sci_config_port,
1619 .verify_port = sci_verify_port,
1620#ifdef CONFIG_CONSOLE_POLL
1621 .poll_get_char = sci_poll_get_char,
1622 .poll_put_char = sci_poll_put_char,
1623#endif
1624};
1625
1626static int __devinit sci_init_single(struct platform_device *dev,
1627 struct sci_port *sci_port,
1628 unsigned int index,
1629 struct plat_sci_port *p)
1630{
1631 struct uart_port *port = &sci_port->port;
1632
1633 port->ops = &sci_uart_ops;
1634 port->iotype = UPIO_MEM;
1635 port->line = index;
1636
1637 switch (p->type) {
1638 case PORT_SCIFB:
1639 port->fifosize = 256;
1640 break;
1641 case PORT_SCIFA:
1642 port->fifosize = 64;
1643 break;
1644 case PORT_SCIF:
1645 port->fifosize = 16;
1646 break;
1647 default:
1648 port->fifosize = 1;
1649 break;
1650 }
1651
1652 if (dev) {
1653 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
1654 if (IS_ERR(sci_port->iclk)) {
1655 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
1656 if (IS_ERR(sci_port->iclk)) {
1657 dev_err(&dev->dev, "can't get iclk\n");
1658 return PTR_ERR(sci_port->iclk);
1659 }
1660 }
1661
1662 /*
1663 * The function clock is optional, ignore it if we can't
1664 * find it.
1665 */
1666 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
1667 if (IS_ERR(sci_port->fclk))
1668 sci_port->fclk = NULL;
1669
1670 sci_port->enable = sci_clk_enable;
1671 sci_port->disable = sci_clk_disable;
1672 port->dev = &dev->dev;
1673 }
1674
1675 sci_port->break_timer.data = (unsigned long)sci_port;
1676 sci_port->break_timer.function = sci_break_timer;
1677 init_timer(&sci_port->break_timer);
1678
1679 port->mapbase = p->mapbase;
1680 port->membase = p->membase;
1681
1682 port->irq = p->irqs[SCIx_TXI_IRQ];
1683 port->flags = p->flags;
1684 sci_port->type = port->type = p->type;
1685
1686#ifdef CONFIG_SERIAL_SH_SCI_DMA
1687 sci_port->dma_dev = p->dma_dev;
1688 sci_port->slave_tx = p->dma_slave_tx;
1689 sci_port->slave_rx = p->dma_slave_rx;
1690
1691 dev_dbg(port->dev, "%s: DMA device %p, tx %d, rx %d\n", __func__,
1692 p->dma_dev, p->dma_slave_tx, p->dma_slave_rx);
1693#endif
1694
1695 memcpy(&sci_port->irqs, &p->irqs, sizeof(p->irqs));
1696 return 0;
1697}
1698
1699#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1700static struct tty_driver *serial_console_device(struct console *co, int *index)
1701{
1702 struct uart_driver *p = &sci_uart_driver;
1703 *index = co->index;
1704 return p->tty_driver;
1705}
1706
1707static void serial_console_putchar(struct uart_port *port, int ch)
1708{
1709 sci_poll_put_char(port, ch);
1710}
1711
1712/*
1713 * Print a string to the serial port trying not to disturb
1714 * any possible real use of the port...
1715 */
1716static void serial_console_write(struct console *co, const char *s,
1717 unsigned count)
1718{
1719 struct uart_port *port = co->data;
1720 struct sci_port *sci_port = to_sci_port(port);
1721 unsigned short bits;
1722
1723 if (sci_port->enable)
1724 sci_port->enable(port);
1725
1726 uart_console_write(port, s, count, serial_console_putchar);
1727
1728 /* wait until fifo is empty and last bit has been transmitted */
1729 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
1730 while ((sci_in(port, SCxSR) & bits) != bits)
1731 cpu_relax();
1732
1733 if (sci_port->disable)
1734 sci_port->disable(port);
1735}
1736
1737static int __devinit serial_console_setup(struct console *co, char *options)
1738{
1739 struct sci_port *sci_port;
1740 struct uart_port *port;
1741 int baud = 115200;
1742 int bits = 8;
1743 int parity = 'n';
1744 int flow = 'n';
1745 int ret;
1746
1747 /*
1748 * Check whether an invalid uart number has been specified, and
1749 * if so, search for the first available port that does have
1750 * console support.
1751 */
1752 if (co->index >= SCI_NPORTS)
1753 co->index = 0;
1754
1755 if (co->data) {
1756 port = co->data;
1757 sci_port = to_sci_port(port);
1758 } else {
1759 sci_port = &sci_ports[co->index];
1760 port = &sci_port->port;
1761 co->data = port;
1762 }
1763
1764 /*
1765 * Also need to check port->type, we don't actually have any
1766 * UPIO_PORT ports, but uart_report_port() handily misreports
1767 * it anyways if we don't have a port available by the time this is
1768 * called.
1769 */
1770 if (!port->type)
1771 return -ENODEV;
1772
1773 sci_config_port(port, 0);
1774
1775 if (sci_port->enable)
1776 sci_port->enable(port);
1777
1778 if (options)
1779 uart_parse_options(options, &baud, &parity, &bits, &flow);
1780
1781 ret = uart_set_options(port, co, baud, parity, bits, flow);
1782#if defined(__H8300H__) || defined(__H8300S__)
1783 /* disable rx interrupt */
1784 if (ret == 0)
1785 sci_stop_rx(port);
1786#endif
1787 /* TODO: disable clock */
1788 return ret;
1789}
1790
1791static struct console serial_console = {
1792 .name = "ttySC",
1793 .device = serial_console_device,
1794 .write = serial_console_write,
1795 .setup = serial_console_setup,
1796 .flags = CON_PRINTBUFFER,
1797 .index = -1,
1798};
1799
1800static int __init sci_console_init(void)
1801{
1802 register_console(&serial_console);
1803 return 0;
1804}
1805console_initcall(sci_console_init);
1806
1807static struct sci_port early_serial_port;
1808static struct console early_serial_console = {
1809 .name = "early_ttySC",
1810 .write = serial_console_write,
1811 .flags = CON_PRINTBUFFER,
1812};
1813static char early_serial_buf[32];
1814
1815#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1816
1817#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1818#define SCI_CONSOLE (&serial_console)
1819#else
1820#define SCI_CONSOLE 0
1821#endif
1822
1823static char banner[] __initdata =
1824 KERN_INFO "SuperH SCI(F) driver initialized\n";
1825
1826static struct uart_driver sci_uart_driver = {
1827 .owner = THIS_MODULE,
1828 .driver_name = "sci",
1829 .dev_name = "ttySC",
1830 .major = SCI_MAJOR,
1831 .minor = SCI_MINOR_START,
1832 .nr = SCI_NPORTS,
1833 .cons = SCI_CONSOLE,
1834};
1835
1836
1837static int sci_remove(struct platform_device *dev)
1838{
1839 struct sh_sci_priv *priv = platform_get_drvdata(dev);
1840 struct sci_port *p;
1841 unsigned long flags;
1842
1843 cpufreq_unregister_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER);
1844
1845 spin_lock_irqsave(&priv->lock, flags);
1846 list_for_each_entry(p, &priv->ports, node) {
1847 uart_remove_one_port(&sci_uart_driver, &p->port);
1848 clk_put(p->iclk);
1849 clk_put(p->fclk);
1850 }
1851 spin_unlock_irqrestore(&priv->lock, flags);
1852
1853 kfree(priv);
1854 return 0;
1855}
1856
1857static int __devinit sci_probe_single(struct platform_device *dev,
1858 unsigned int index,
1859 struct plat_sci_port *p,
1860 struct sci_port *sciport)
1861{
1862 struct sh_sci_priv *priv = platform_get_drvdata(dev);
1863 unsigned long flags;
1864 int ret;
1865
1866 /* Sanity check */
1867 if (unlikely(index >= SCI_NPORTS)) {
1868 dev_notice(&dev->dev, "Attempting to register port "
1869 "%d when only %d are available.\n",
1870 index+1, SCI_NPORTS);
1871 dev_notice(&dev->dev, "Consider bumping "
1872 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
1873 return 0;
1874 }
1875
1876 ret = sci_init_single(dev, sciport, index, p);
1877 if (ret)
1878 return ret;
1879
1880 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
1881 if (ret)
1882 return ret;
1883
1884 INIT_LIST_HEAD(&sciport->node);
1885
1886 spin_lock_irqsave(&priv->lock, flags);
1887 list_add(&sciport->node, &priv->ports);
1888 spin_unlock_irqrestore(&priv->lock, flags);
1889
1890 return 0;
1891}
1892
1893/*
1894 * Register a set of serial devices attached to a platform device. The
1895 * list is terminated with a zero flags entry, which means we expect
1896 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
1897 * remapping (such as sh64) should also set UPF_IOREMAP.
1898 */
1899static int __devinit sci_probe(struct platform_device *dev)
1900{
1901 struct plat_sci_port *p = dev->dev.platform_data;
1902 struct sh_sci_priv *priv;
1903 int i, ret = -EINVAL;
1904
1905#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1906 if (is_early_platform_device(dev)) {
1907 if (dev->id == -1)
1908 return -ENOTSUPP;
1909 early_serial_console.index = dev->id;
1910 early_serial_console.data = &early_serial_port.port;
1911 sci_init_single(NULL, &early_serial_port, dev->id, p);
1912 serial_console_setup(&early_serial_console, early_serial_buf);
1913 if (!strstr(early_serial_buf, "keep"))
1914 early_serial_console.flags |= CON_BOOT;
1915 register_console(&early_serial_console);
1916 return 0;
1917 }
1918#endif
1919
1920 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1921 if (!priv)
1922 return -ENOMEM;
1923
1924 INIT_LIST_HEAD(&priv->ports);
1925 spin_lock_init(&priv->lock);
1926 platform_set_drvdata(dev, priv);
1927
1928 priv->clk_nb.notifier_call = sci_notifier;
1929 cpufreq_register_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER);
1930
1931 if (dev->id != -1) {
1932 ret = sci_probe_single(dev, dev->id, p, &sci_ports[dev->id]);
1933 if (ret)
1934 goto err_unreg;
1935 } else {
1936 for (i = 0; p && p->flags != 0; p++, i++) {
1937 ret = sci_probe_single(dev, i, p, &sci_ports[i]);
1938 if (ret)
1939 goto err_unreg;
1940 }
1941 }
1942
1943#ifdef CONFIG_SH_STANDARD_BIOS
1944 sh_bios_gdb_detach();
1945#endif
1946
1947 return 0;
1948
1949err_unreg:
1950 sci_remove(dev);
1951 return ret;
1952}
1953
1954static int sci_suspend(struct device *dev)
1955{
1956 struct sh_sci_priv *priv = dev_get_drvdata(dev);
1957 struct sci_port *p;
1958 unsigned long flags;
1959
1960 spin_lock_irqsave(&priv->lock, flags);
1961 list_for_each_entry(p, &priv->ports, node)
1962 uart_suspend_port(&sci_uart_driver, &p->port);
1963 spin_unlock_irqrestore(&priv->lock, flags);
1964
1965 return 0;
1966}
1967
1968static int sci_resume(struct device *dev)
1969{
1970 struct sh_sci_priv *priv = dev_get_drvdata(dev);
1971 struct sci_port *p;
1972 unsigned long flags;
1973
1974 spin_lock_irqsave(&priv->lock, flags);
1975 list_for_each_entry(p, &priv->ports, node)
1976 uart_resume_port(&sci_uart_driver, &p->port);
1977 spin_unlock_irqrestore(&priv->lock, flags);
1978
1979 return 0;
1980}
1981
1982static const struct dev_pm_ops sci_dev_pm_ops = {
1983 .suspend = sci_suspend,
1984 .resume = sci_resume,
1985};
1986
1987static struct platform_driver sci_driver = {
1988 .probe = sci_probe,
1989 .remove = sci_remove,
1990 .driver = {
1991 .name = "sh-sci",
1992 .owner = THIS_MODULE,
1993 .pm = &sci_dev_pm_ops,
1994 },
1995};
1996
1997static int __init sci_init(void)
1998{
1999 int ret;
2000
2001 printk(banner);
2002
2003 ret = uart_register_driver(&sci_uart_driver);
2004 if (likely(ret == 0)) {
2005 ret = platform_driver_register(&sci_driver);
2006 if (unlikely(ret))
2007 uart_unregister_driver(&sci_uart_driver);
2008 }
2009
2010 return ret;
2011}
2012
2013static void __exit sci_exit(void)
2014{
2015 platform_driver_unregister(&sci_driver);
2016 uart_unregister_driver(&sci_uart_driver);
2017}
2018
2019#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2020early_platform_init_buffer("earlyprintk", &sci_driver,
2021 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2022#endif
2023module_init(sci_init);
2024module_exit(sci_exit);
2025
2026MODULE_LICENSE("GPL");
2027MODULE_ALIAS("platform:sh-sci");
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
deleted file mode 100644
index 9b52f77a9305..000000000000
--- a/drivers/serial/sh-sci.h
+++ /dev/null
@@ -1,644 +0,0 @@
1#include <linux/serial_core.h>
2#include <linux/io.h>
3#include <linux/gpio.h>
4
5#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
6#include <asm/regs306x.h>
7#endif
8#if defined(CONFIG_H8S2678)
9#include <asm/regs267x.h>
10#endif
11
12#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
13 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
14 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
15 defined(CONFIG_CPU_SUBTYPE_SH7709)
16# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
17# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
18# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
19#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
20# define SCIF0 0xA4400000
21# define SCIF2 0xA4410000
22# define SCSMR_Ir 0xA44A0000
23# define IRDA_SCIF SCIF0
24# define SCPCR 0xA4000116
25# define SCPDR 0xA4000136
26
27/* Set the clock source,
28 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
29 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
30 */
31# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
32#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
33 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
34 defined(CONFIG_ARCH_SH7367) || \
35 defined(CONFIG_ARCH_SH7377) || \
36 defined(CONFIG_ARCH_SH7372)
37# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
38# define PORT_PTCR 0xA405011EUL
39# define PORT_PVCR 0xA4050122UL
40# define SCIF_ORER 0x0200 /* overrun error bit */
41#elif defined(CONFIG_SH_RTS7751R2D)
42# define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
43# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
44# define SCIF_ORER 0x0001 /* overrun error bit */
45# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
46#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
47 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
48 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
49 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
50 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
51 defined(CONFIG_CPU_SUBTYPE_SH7751R)
52# define SCSPTR1 0xffe0001c /* 8 bit SCI */
53# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
54# define SCIF_ORER 0x0001 /* overrun error bit */
55# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
56 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
57 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
58#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
59# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
60# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
61# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
62# define SCIF_ORER 0x0001 /* overrun error bit */
63# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
64#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
65# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
66# define SCIF_ORER 0x0001 /* overrun error bit */
67# define PACR 0xa4050100
68# define PBCR 0xa4050102
69# define SCSCR_INIT(port) 0x3B
70#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
71# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
72# define SCSPTR1 0xffe10010 /* 16 bit SCIF */
73# define SCSPTR2 0xffe20010 /* 16 bit SCIF */
74# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
75# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
76#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
77# define PADR 0xA4050120
78# define PSDR 0xA405013e
79# define PWDR 0xA4050166
80# define PSCR 0xA405011E
81# define SCIF_ORER 0x0001 /* overrun error bit */
82# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
83#elif defined(CONFIG_CPU_SUBTYPE_SH7366)
84# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
85# define SCSPTR0 SCPDR0
86# define SCIF_ORER 0x0001 /* overrun error bit */
87# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
88#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
89# define SCSPTR0 0xa4050160
90# define SCSPTR1 0xa405013e
91# define SCSPTR2 0xa4050160
92# define SCSPTR3 0xa405013e
93# define SCSPTR4 0xa4050128
94# define SCSPTR5 0xa4050128
95# define SCIF_ORER 0x0001 /* overrun error bit */
96# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
97#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
98# define SCIF_ORER 0x0001 /* overrun error bit */
99# define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \
100 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
101 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
102#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
103# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
104# define SCIF_ORER 0x0001 /* overrun error bit */
105# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
106#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
107# define SCIF_BASE_ADDR 0x01030000
108# define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
109# define SCIF_PTR2_OFFS 0x0000020
110# define SCIF_LSR2_OFFS 0x0000024
111# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
112# define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
113# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
114#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
115# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
116# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
117#elif defined(CONFIG_H8S2678)
118# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
119# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
120#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
121# define SCSPTR0 0xfe4b0020
122# define SCSPTR1 0xfe4b0020
123# define SCSPTR2 0xfe4b0020
124# define SCIF_ORER 0x0001
125# define SCSCR_INIT(port) 0x38
126# define SCIF_ONLY
127#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
128# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
129# define SCSPTR1 0xffe08024 /* 16 bit SCIF */
130# define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
131# define SCIF_ORER 0x0001 /* overrun error bit */
132# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
133#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
134# define SCSPTR0 0xff923020 /* 16 bit SCIF */
135# define SCSPTR1 0xff924020 /* 16 bit SCIF */
136# define SCSPTR2 0xff925020 /* 16 bit SCIF */
137# define SCIF_ORER 0x0001 /* overrun error bit */
138# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
139#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
140# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
141# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
142# define SCIF_ORER 0x0001 /* Overrun error bit */
143# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
144#elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \
145 defined(CONFIG_CPU_SUBTYPE_SH7786)
146# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
147# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
148# define SCSPTR2 0xffec0024 /* 16 bit SCIF */
149# define SCSPTR3 0xffed0024 /* 16 bit SCIF */
150# define SCSPTR4 0xffee0024 /* 16 bit SCIF */
151# define SCSPTR5 0xffef0024 /* 16 bit SCIF */
152# define SCIF_ORER 0x0001 /* Overrun error bit */
153# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
154#elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \
155 defined(CONFIG_CPU_SUBTYPE_SH7203) || \
156 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
157 defined(CONFIG_CPU_SUBTYPE_SH7263)
158# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
159# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
160# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
161# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
162# if defined(CONFIG_CPU_SUBTYPE_SH7201)
163# define SCSPTR4 0xfffeA020 /* 16 bit SCIF */
164# define SCSPTR5 0xfffeA820 /* 16 bit SCIF */
165# define SCSPTR6 0xfffeB020 /* 16 bit SCIF */
166# define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
167# endif
168# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
169#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
170# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
171# define SCSPTR1 0xf8410020 /* 16 bit SCIF */
172# define SCSPTR2 0xf8420020 /* 16 bit SCIF */
173# define SCIF_ORER 0x0001 /* overrun error bit */
174# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
175#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
176# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
177# define SCSPTR1 0xffc40020 /* 16 bit SCIF */
178# define SCSPTR2 0xffc50020 /* 16 bit SCIF */
179# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
180# define SCIF_ORER 0x0001 /* Overrun error bit */
181# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
182#else
183# error CPU subtype not defined
184#endif
185
186/* SCSCR */
187#define SCI_CTRL_FLAGS_TIE 0x80 /* all */
188#define SCI_CTRL_FLAGS_RIE 0x40 /* all */
189#define SCI_CTRL_FLAGS_TE 0x20 /* all */
190#define SCI_CTRL_FLAGS_RE 0x10 /* all */
191#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
192 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
193 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
194 defined(CONFIG_CPU_SUBTYPE_SH7722) || \
195 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
196 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
197 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
198 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
199 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
200 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
201 defined(CONFIG_CPU_SUBTYPE_SH7786) || \
202 defined(CONFIG_CPU_SUBTYPE_SHX3)
203#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
204#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
205#define SCI_CTRL_FLAGS_REIE ((port)->type == PORT_SCIFA ? 0 : 8)
206#else
207#define SCI_CTRL_FLAGS_REIE 0
208#endif
209/* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
210/* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
211/* SCI_CTRL_FLAGS_CKE1 0x02 * all */
212/* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
213
214/* SCxSR SCI */
215#define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
216#define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
217#define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
218#define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
219#define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
220#define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
221/* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
222/* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
223
224#define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
225
226/* SCxSR SCIF */
227#define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
228#define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
229#define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
230#define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
231#define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
232#define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
233#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
234#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
235
236#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
237 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
238 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
239 defined(CONFIG_ARCH_SH7367) || \
240 defined(CONFIG_ARCH_SH7377) || \
241 defined(CONFIG_ARCH_SH7372)
242# define SCIF_ORER 0x0200
243# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
244# define SCIF_RFDC_MASK 0x007f
245# define SCIF_TXROOM_MAX 64
246#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
247# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK )
248# define SCIF_RFDC_MASK 0x007f
249# define SCIF_TXROOM_MAX 64
250/* SH7763 SCIF2 support */
251# define SCIF2_RFDC_MASK 0x001f
252# define SCIF2_TXROOM_MAX 16
253#else
254# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
255# define SCIF_RFDC_MASK 0x001f
256# define SCIF_TXROOM_MAX 16
257#endif
258
259#ifndef SCIF_ORER
260#define SCIF_ORER 0x0000
261#endif
262
263#define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
264#define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
265#define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
266#define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
267#define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
268#define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
269#define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
270#define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
271
272#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
273 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
274 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
275 defined(CONFIG_ARCH_SH7367) || \
276 defined(CONFIG_ARCH_SH7377) || \
277 defined(CONFIG_ARCH_SH7372)
278# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
279# define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
280# define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf)
281# define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3)
282#else
283# define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
284# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
285# define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
286# define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
287#endif
288
289/* SCFCR */
290#define SCFCR_RFRST 0x0002
291#define SCFCR_TFRST 0x0004
292#define SCFCR_TCRST 0x4000
293#define SCFCR_MCE 0x0008
294
295#define SCI_MAJOR 204
296#define SCI_MINOR_START 8
297
298/* Generic serial flags */
299#define SCI_RX_THROTTLE 0x0000001
300
301#define SCI_MAGIC 0xbabeface
302
303/*
304 * Events are used to schedule things to happen at timer-interrupt
305 * time, instead of at rs interrupt time.
306 */
307#define SCI_EVENT_WRITE_WAKEUP 0
308
309#define SCI_IN(size, offset) \
310 if ((size) == 8) { \
311 return ioread8(port->membase + (offset)); \
312 } else { \
313 return ioread16(port->membase + (offset)); \
314 }
315#define SCI_OUT(size, offset, value) \
316 if ((size) == 8) { \
317 iowrite8(value, port->membase + (offset)); \
318 } else if ((size) == 16) { \
319 iowrite16(value, port->membase + (offset)); \
320 }
321
322#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
323 static inline unsigned int sci_##name##_in(struct uart_port *port) \
324 { \
325 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) { \
326 SCI_IN(scif_size, scif_offset) \
327 } else { /* PORT_SCI or PORT_SCIFA */ \
328 SCI_IN(sci_size, sci_offset); \
329 } \
330 } \
331 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
332 { \
333 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) { \
334 SCI_OUT(scif_size, scif_offset, value) \
335 } else { /* PORT_SCI or PORT_SCIFA */ \
336 SCI_OUT(sci_size, sci_offset, value); \
337 } \
338 }
339
340#ifdef CONFIG_H8300
341/* h8300 don't have SCIF */
342#define CPU_SCIF_FNS(name) \
343 static inline unsigned int sci_##name##_in(struct uart_port *port) \
344 { \
345 return 0; \
346 } \
347 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
348 { \
349 }
350#else
351#define CPU_SCIF_FNS(name, scif_offset, scif_size) \
352 static inline unsigned int sci_##name##_in(struct uart_port *port) \
353 { \
354 SCI_IN(scif_size, scif_offset); \
355 } \
356 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
357 { \
358 SCI_OUT(scif_size, scif_offset, value); \
359 }
360#endif
361
362#define CPU_SCI_FNS(name, sci_offset, sci_size) \
363 static inline unsigned int sci_##name##_in(struct uart_port* port) \
364 { \
365 SCI_IN(sci_size, sci_offset); \
366 } \
367 static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
368 { \
369 SCI_OUT(sci_size, sci_offset, value); \
370 }
371
372#if defined(CONFIG_CPU_SH3) || \
373 defined(CONFIG_ARCH_SH7367) || \
374 defined(CONFIG_ARCH_SH7377) || \
375 defined(CONFIG_ARCH_SH7372)
376#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
377#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
378 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
379 h8_sci_offset, h8_sci_size) \
380 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
381#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
382 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
383#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
384 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
385 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
386 defined(CONFIG_ARCH_SH7367) || \
387 defined(CONFIG_ARCH_SH7377)
388#define SCIF_FNS(name, scif_offset, scif_size) \
389 CPU_SCIF_FNS(name, scif_offset, scif_size)
390#elif defined(CONFIG_ARCH_SH7372)
391#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scifb_offset, sh4_scifb_size) \
392 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scifb_offset, sh4_scifb_size)
393#define SCIF_FNS(name, scif_offset, scif_size) \
394 CPU_SCIF_FNS(name, scif_offset, scif_size)
395#else
396#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
397 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
398 h8_sci_offset, h8_sci_size) \
399 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
400#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
401 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
402#endif
403#elif defined(__H8300H__) || defined(__H8300S__)
404#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
405 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
406 h8_sci_offset, h8_sci_size) \
407 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
408#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
409 CPU_SCIF_FNS(name)
410#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
411 defined(CONFIG_CPU_SUBTYPE_SH7724)
412 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \
413 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size)
414 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
415 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
416#else
417#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
418 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
419 h8_sci_offset, h8_sci_size) \
420 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
421#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
422 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
423#endif
424
425#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
426 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
427 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
428 defined(CONFIG_ARCH_SH7367) || \
429 defined(CONFIG_ARCH_SH7377)
430
431SCIF_FNS(SCSMR, 0x00, 16)
432SCIF_FNS(SCBRR, 0x04, 8)
433SCIF_FNS(SCSCR, 0x08, 16)
434SCIF_FNS(SCTDSR, 0x0c, 8)
435SCIF_FNS(SCFER, 0x10, 16)
436SCIF_FNS(SCxSR, 0x14, 16)
437SCIF_FNS(SCFCR, 0x18, 16)
438SCIF_FNS(SCFDR, 0x1c, 16)
439SCIF_FNS(SCxTDR, 0x20, 8)
440SCIF_FNS(SCxRDR, 0x24, 8)
441SCIF_FNS(SCLSR, 0x00, 0)
442#elif defined(CONFIG_ARCH_SH7372)
443SCIF_FNS(SCSMR, 0x00, 16)
444SCIF_FNS(SCBRR, 0x04, 8)
445SCIF_FNS(SCSCR, 0x08, 16)
446SCIF_FNS(SCTDSR, 0x0c, 16)
447SCIF_FNS(SCFER, 0x10, 16)
448SCIF_FNS(SCxSR, 0x14, 16)
449SCIF_FNS(SCFCR, 0x18, 16)
450SCIF_FNS(SCFDR, 0x1c, 16)
451SCIF_FNS(SCTFDR, 0x38, 16)
452SCIF_FNS(SCRFDR, 0x3c, 16)
453SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8)
454SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8)
455SCIF_FNS(SCLSR, 0x00, 0)
456#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
457 defined(CONFIG_CPU_SUBTYPE_SH7724)
458SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
459SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
460SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
461SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
462SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
463SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
464SCIx_FNS(SCSPTR, 0, 0, 0, 0)
465SCIF_FNS(SCTDSR, 0x0c, 8)
466SCIF_FNS(SCFER, 0x10, 16)
467SCIF_FNS(SCFCR, 0x18, 16)
468SCIF_FNS(SCFDR, 0x1c, 16)
469SCIF_FNS(SCLSR, 0x24, 16)
470#else
471/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
472/* name off sz off sz off sz off sz off sz*/
473SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
474SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
475SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
476SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
477SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
478SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
479SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
480#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
481 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
482 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
483 defined(CONFIG_CPU_SUBTYPE_SH7786)
484SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
485SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
486SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
487SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
488SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
489#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
490SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
491SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16)
492SCIF_FNS(SCLSR2, 0, 0, 0x24, 16)
493SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
494SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
495SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
496SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
497#else
498SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
499#if defined(CONFIG_CPU_SUBTYPE_SH7722)
500SCIF_FNS(SCSPTR, 0, 0, 0, 0)
501#else
502SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
503#endif
504SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
505#endif
506#endif
507#define sci_in(port, reg) sci_##reg##_in(port)
508#define sci_out(port, reg, value) sci_##reg##_out(port, value)
509
510/* H8/300 series SCI pins assignment */
511#if defined(__H8300H__) || defined(__H8300S__)
512static const struct __attribute__((packed)) {
513 int port; /* GPIO port no */
514 unsigned short rx,tx; /* GPIO bit no */
515} h8300_sci_pins[] = {
516#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
517 { /* SCI0 */
518 .port = H8300_GPIO_P9,
519 .rx = H8300_GPIO_B2,
520 .tx = H8300_GPIO_B0,
521 },
522 { /* SCI1 */
523 .port = H8300_GPIO_P9,
524 .rx = H8300_GPIO_B3,
525 .tx = H8300_GPIO_B1,
526 },
527 { /* SCI2 */
528 .port = H8300_GPIO_PB,
529 .rx = H8300_GPIO_B7,
530 .tx = H8300_GPIO_B6,
531 }
532#elif defined(CONFIG_H8S2678)
533 { /* SCI0 */
534 .port = H8300_GPIO_P3,
535 .rx = H8300_GPIO_B2,
536 .tx = H8300_GPIO_B0,
537 },
538 { /* SCI1 */
539 .port = H8300_GPIO_P3,
540 .rx = H8300_GPIO_B3,
541 .tx = H8300_GPIO_B1,
542 },
543 { /* SCI2 */
544 .port = H8300_GPIO_P5,
545 .rx = H8300_GPIO_B1,
546 .tx = H8300_GPIO_B0,
547 }
548#endif
549};
550#endif
551
552#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
553 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
554 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
555 defined(CONFIG_CPU_SUBTYPE_SH7709)
556static inline int sci_rxd_in(struct uart_port *port)
557{
558 if (port->mapbase == 0xfffffe80)
559 return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */
560 return 1;
561}
562#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
563 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
564 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
565 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
566 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
567 defined(CONFIG_CPU_SUBTYPE_SH7091)
568static inline int sci_rxd_in(struct uart_port *port)
569{
570 if (port->mapbase == 0xffe00000)
571 return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
572 return 1;
573}
574#elif defined(__H8300H__) || defined(__H8300S__)
575static inline int sci_rxd_in(struct uart_port *port)
576{
577 int ch = (port->mapbase - SMR0) >> 3;
578 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
579}
580#else /* default case for non-SCI processors */
581static inline int sci_rxd_in(struct uart_port *port)
582{
583 return 1;
584}
585#endif
586
587/*
588 * Values for the BitRate Register (SCBRR)
589 *
590 * The values are actually divisors for a frequency which can
591 * be internal to the SH3 (14.7456MHz) or derived from an external
592 * clock source. This driver assumes the internal clock is used;
593 * to support using an external clock source, config options or
594 * possibly command-line options would need to be added.
595 *
596 * Also, to support speeds below 2400 (why?) the lower 2 bits of
597 * the SCSMR register would also need to be set to non-zero values.
598 *
599 * -- Greg Banks 27Feb2000
600 *
601 * Answer: The SCBRR register is only eight bits, and the value in
602 * it gets larger with lower baud rates. At around 2400 (depending on
603 * the peripherial module clock) you run out of bits. However the
604 * lower two bits of SCSMR allow the module clock to be divided down,
605 * scaling the value which is needed in SCBRR.
606 *
607 * -- Stuart Menefy - 23 May 2000
608 *
609 * I meant, why would anyone bother with bitrates below 2400.
610 *
611 * -- Greg Banks - 7Jul2000
612 *
613 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
614 * tape reader as a console!
615 *
616 * -- Mitch Davis - 15 Jul 2000
617 */
618
619#if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
620 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
621 defined(CONFIG_CPU_SUBTYPE_SH7786)
622#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
623#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
624 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
625 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
626 defined(CONFIG_ARCH_SH7367) || \
627 defined(CONFIG_ARCH_SH7377) || \
628 defined(CONFIG_ARCH_SH7372)
629#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
630#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
631 defined(CONFIG_CPU_SUBTYPE_SH7724)
632static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
633{
634 if (port->type == PORT_SCIF)
635 return (clk+16*bps)/(32*bps)-1;
636 else
637 return ((clk*2)+16*bps)/(16*bps)-1;
638}
639#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
640#elif defined(__H8300H__) || defined(__H8300S__)
641#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
642#else /* Generic SH */
643#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
644#endif
diff --git a/drivers/serial/sn_console.c b/drivers/serial/sn_console.c
deleted file mode 100644
index cff9a306660f..000000000000
--- a/drivers/serial/sn_console.c
+++ /dev/null
@@ -1,1085 +0,0 @@
1/*
2 * C-Brick Serial Port (and console) driver for SGI Altix machines.
3 *
4 * This driver is NOT suitable for talking to the l1-controller for
5 * anything other than 'console activities' --- please use the l1
6 * driver for that.
7 *
8 *
9 * Copyright (c) 2004-2006 Silicon Graphics, Inc. All Rights Reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of version 2 of the GNU General Public License
13 * as published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it would be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
18 *
19 * Further, this software is distributed without any warranty that it is
20 * free of the rightful claim of any third person regarding infringement
21 * or the like. Any license provided herein, whether implied or
22 * otherwise, applies only to this software file. Patent licenses, if
23 * any, provided herein do not apply to combinations of this program with
24 * other software, or any other product whatsoever.
25 *
26 * You should have received a copy of the GNU General Public
27 * License along with this program; if not, write the Free Software
28 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
29 *
30 * Contact information: Silicon Graphics, Inc., 1500 Crittenden Lane,
31 * Mountain View, CA 94043, or:
32 *
33 * http://www.sgi.com
34 *
35 * For further information regarding this notice, see:
36 *
37 * http://oss.sgi.com/projects/GenInfo/NoticeExplan
38 */
39
40#include <linux/interrupt.h>
41#include <linux/tty.h>
42#include <linux/serial.h>
43#include <linux/console.h>
44#include <linux/module.h>
45#include <linux/sysrq.h>
46#include <linux/circ_buf.h>
47#include <linux/serial_reg.h>
48#include <linux/delay.h> /* for mdelay */
49#include <linux/miscdevice.h>
50#include <linux/serial_core.h>
51
52#include <asm/io.h>
53#include <asm/sn/simulator.h>
54#include <asm/sn/sn_sal.h>
55
56/* number of characters we can transmit to the SAL console at a time */
57#define SN_SAL_MAX_CHARS 120
58
59/* 64K, when we're asynch, it must be at least printk's LOG_BUF_LEN to
60 * avoid losing chars, (always has to be a power of 2) */
61#define SN_SAL_BUFFER_SIZE (64 * (1 << 10))
62
63#define SN_SAL_UART_FIFO_DEPTH 16
64#define SN_SAL_UART_FIFO_SPEED_CPS (9600/10)
65
66/* sn_transmit_chars() calling args */
67#define TRANSMIT_BUFFERED 0
68#define TRANSMIT_RAW 1
69
70/* To use dynamic numbers only and not use the assigned major and minor,
71 * define the following.. */
72 /* #define USE_DYNAMIC_MINOR 1 *//* use dynamic minor number */
73#define USE_DYNAMIC_MINOR 0 /* Don't rely on misc_register dynamic minor */
74
75/* Device name we're using */
76#define DEVICE_NAME "ttySG"
77#define DEVICE_NAME_DYNAMIC "ttySG0" /* need full name for misc_register */
78/* The major/minor we are using, ignored for USE_DYNAMIC_MINOR */
79#define DEVICE_MAJOR 204
80#define DEVICE_MINOR 40
81
82#ifdef CONFIG_MAGIC_SYSRQ
83static char sysrq_serial_str[] = "\eSYS";
84static char *sysrq_serial_ptr = sysrq_serial_str;
85static unsigned long sysrq_requested;
86#endif /* CONFIG_MAGIC_SYSRQ */
87
88/*
89 * Port definition - this kinda drives it all
90 */
91struct sn_cons_port {
92 struct timer_list sc_timer;
93 struct uart_port sc_port;
94 struct sn_sal_ops {
95 int (*sal_puts_raw) (const char *s, int len);
96 int (*sal_puts) (const char *s, int len);
97 int (*sal_getc) (void);
98 int (*sal_input_pending) (void);
99 void (*sal_wakeup_transmit) (struct sn_cons_port *, int);
100 } *sc_ops;
101 unsigned long sc_interrupt_timeout;
102 int sc_is_asynch;
103};
104
105static struct sn_cons_port sal_console_port;
106static int sn_process_input;
107
108/* Only used if USE_DYNAMIC_MINOR is set to 1 */
109static struct miscdevice misc; /* used with misc_register for dynamic */
110
111extern void early_sn_setup(void);
112
113#undef DEBUG
114#ifdef DEBUG
115static int sn_debug_printf(const char *fmt, ...);
116#define DPRINTF(x...) sn_debug_printf(x)
117#else
118#define DPRINTF(x...) do { } while (0)
119#endif
120
121/* Prototypes */
122static int snt_hw_puts_raw(const char *, int);
123static int snt_hw_puts_buffered(const char *, int);
124static int snt_poll_getc(void);
125static int snt_poll_input_pending(void);
126static int snt_intr_getc(void);
127static int snt_intr_input_pending(void);
128static void sn_transmit_chars(struct sn_cons_port *, int);
129
130/* A table for polling:
131 */
132static struct sn_sal_ops poll_ops = {
133 .sal_puts_raw = snt_hw_puts_raw,
134 .sal_puts = snt_hw_puts_raw,
135 .sal_getc = snt_poll_getc,
136 .sal_input_pending = snt_poll_input_pending
137};
138
139/* A table for interrupts enabled */
140static struct sn_sal_ops intr_ops = {
141 .sal_puts_raw = snt_hw_puts_raw,
142 .sal_puts = snt_hw_puts_buffered,
143 .sal_getc = snt_intr_getc,
144 .sal_input_pending = snt_intr_input_pending,
145 .sal_wakeup_transmit = sn_transmit_chars
146};
147
148/* the console does output in two distinctly different ways:
149 * synchronous (raw) and asynchronous (buffered). initally, early_printk
150 * does synchronous output. any data written goes directly to the SAL
151 * to be output (incidentally, it is internally buffered by the SAL)
152 * after interrupts and timers are initialized and available for use,
153 * the console init code switches to asynchronous output. this is
154 * also the earliest opportunity to begin polling for console input.
155 * after console initialization, console output and tty (serial port)
156 * output is buffered and sent to the SAL asynchronously (either by
157 * timer callback or by UART interrupt) */
158
159/* routines for running the console in polling mode */
160
161/**
162 * snt_poll_getc - Get a character from the console in polling mode
163 *
164 */
165static int snt_poll_getc(void)
166{
167 int ch;
168
169 ia64_sn_console_getc(&ch);
170 return ch;
171}
172
173/**
174 * snt_poll_input_pending - Check if any input is waiting - polling mode.
175 *
176 */
177static int snt_poll_input_pending(void)
178{
179 int status, input;
180
181 status = ia64_sn_console_check(&input);
182 return !status && input;
183}
184
185/* routines for an interrupt driven console (normal) */
186
187/**
188 * snt_intr_getc - Get a character from the console, interrupt mode
189 *
190 */
191static int snt_intr_getc(void)
192{
193 return ia64_sn_console_readc();
194}
195
196/**
197 * snt_intr_input_pending - Check if input is pending, interrupt mode
198 *
199 */
200static int snt_intr_input_pending(void)
201{
202 return ia64_sn_console_intr_status() & SAL_CONSOLE_INTR_RECV;
203}
204
205/* these functions are polled and interrupt */
206
207/**
208 * snt_hw_puts_raw - Send raw string to the console, polled or interrupt mode
209 * @s: String
210 * @len: Length
211 *
212 */
213static int snt_hw_puts_raw(const char *s, int len)
214{
215 /* this will call the PROM and not return until this is done */
216 return ia64_sn_console_putb(s, len);
217}
218
219/**
220 * snt_hw_puts_buffered - Send string to console, polled or interrupt mode
221 * @s: String
222 * @len: Length
223 *
224 */
225static int snt_hw_puts_buffered(const char *s, int len)
226{
227 /* queue data to the PROM */
228 return ia64_sn_console_xmit_chars((char *)s, len);
229}
230
231/* uart interface structs
232 * These functions are associated with the uart_port that the serial core
233 * infrastructure calls.
234 *
235 * Note: Due to how the console works, many routines are no-ops.
236 */
237
238/**
239 * snp_type - What type of console are we?
240 * @port: Port to operate with (we ignore since we only have one port)
241 *
242 */
243static const char *snp_type(struct uart_port *port)
244{
245 return ("SGI SN L1");
246}
247
248/**
249 * snp_tx_empty - Is the transmitter empty? We pretend we're always empty
250 * @port: Port to operate on (we ignore since we only have one port)
251 *
252 */
253static unsigned int snp_tx_empty(struct uart_port *port)
254{
255 return 1;
256}
257
258/**
259 * snp_stop_tx - stop the transmitter - no-op for us
260 * @port: Port to operat eon - we ignore - no-op function
261 *
262 */
263static void snp_stop_tx(struct uart_port *port)
264{
265}
266
267/**
268 * snp_release_port - Free i/o and resources for port - no-op for us
269 * @port: Port to operate on - we ignore - no-op function
270 *
271 */
272static void snp_release_port(struct uart_port *port)
273{
274}
275
276/**
277 * snp_enable_ms - Force modem status interrupts on - no-op for us
278 * @port: Port to operate on - we ignore - no-op function
279 *
280 */
281static void snp_enable_ms(struct uart_port *port)
282{
283}
284
285/**
286 * snp_shutdown - shut down the port - free irq and disable - no-op for us
287 * @port: Port to shut down - we ignore
288 *
289 */
290static void snp_shutdown(struct uart_port *port)
291{
292}
293
294/**
295 * snp_set_mctrl - set control lines (dtr, rts, etc) - no-op for our console
296 * @port: Port to operate on - we ignore
297 * @mctrl: Lines to set/unset - we ignore
298 *
299 */
300static void snp_set_mctrl(struct uart_port *port, unsigned int mctrl)
301{
302}
303
304/**
305 * snp_get_mctrl - get contorl line info, we just return a static value
306 * @port: port to operate on - we only have one port so we ignore this
307 *
308 */
309static unsigned int snp_get_mctrl(struct uart_port *port)
310{
311 return TIOCM_CAR | TIOCM_RNG | TIOCM_DSR | TIOCM_CTS;
312}
313
314/**
315 * snp_stop_rx - Stop the receiver - we ignor ethis
316 * @port: Port to operate on - we ignore
317 *
318 */
319static void snp_stop_rx(struct uart_port *port)
320{
321}
322
323/**
324 * snp_start_tx - Start transmitter
325 * @port: Port to operate on
326 *
327 */
328static void snp_start_tx(struct uart_port *port)
329{
330 if (sal_console_port.sc_ops->sal_wakeup_transmit)
331 sal_console_port.sc_ops->sal_wakeup_transmit(&sal_console_port,
332 TRANSMIT_BUFFERED);
333
334}
335
336/**
337 * snp_break_ctl - handle breaks - ignored by us
338 * @port: Port to operate on
339 * @break_state: Break state
340 *
341 */
342static void snp_break_ctl(struct uart_port *port, int break_state)
343{
344}
345
346/**
347 * snp_startup - Start up the serial port - always return 0 (We're always on)
348 * @port: Port to operate on
349 *
350 */
351static int snp_startup(struct uart_port *port)
352{
353 return 0;
354}
355
356/**
357 * snp_set_termios - set termios stuff - we ignore these
358 * @port: port to operate on
359 * @termios: New settings
360 * @termios: Old
361 *
362 */
363static void
364snp_set_termios(struct uart_port *port, struct ktermios *termios,
365 struct ktermios *old)
366{
367}
368
369/**
370 * snp_request_port - allocate resources for port - ignored by us
371 * @port: port to operate on
372 *
373 */
374static int snp_request_port(struct uart_port *port)
375{
376 return 0;
377}
378
379/**
380 * snp_config_port - allocate resources, set up - we ignore, we're always on
381 * @port: Port to operate on
382 * @flags: flags used for port setup
383 *
384 */
385static void snp_config_port(struct uart_port *port, int flags)
386{
387}
388
389/* Associate the uart functions above - given to serial core */
390
391static struct uart_ops sn_console_ops = {
392 .tx_empty = snp_tx_empty,
393 .set_mctrl = snp_set_mctrl,
394 .get_mctrl = snp_get_mctrl,
395 .stop_tx = snp_stop_tx,
396 .start_tx = snp_start_tx,
397 .stop_rx = snp_stop_rx,
398 .enable_ms = snp_enable_ms,
399 .break_ctl = snp_break_ctl,
400 .startup = snp_startup,
401 .shutdown = snp_shutdown,
402 .set_termios = snp_set_termios,
403 .pm = NULL,
404 .type = snp_type,
405 .release_port = snp_release_port,
406 .request_port = snp_request_port,
407 .config_port = snp_config_port,
408 .verify_port = NULL,
409};
410
411/* End of uart struct functions and defines */
412
413#ifdef DEBUG
414
415/**
416 * sn_debug_printf - close to hardware debugging printf
417 * @fmt: printf format
418 *
419 * This is as "close to the metal" as we can get, used when the driver
420 * itself may be broken.
421 *
422 */
423static int sn_debug_printf(const char *fmt, ...)
424{
425 static char printk_buf[1024];
426 int printed_len;
427 va_list args;
428
429 va_start(args, fmt);
430 printed_len = vsnprintf(printk_buf, sizeof(printk_buf), fmt, args);
431
432 if (!sal_console_port.sc_ops) {
433 sal_console_port.sc_ops = &poll_ops;
434 early_sn_setup();
435 }
436 sal_console_port.sc_ops->sal_puts_raw(printk_buf, printed_len);
437
438 va_end(args);
439 return printed_len;
440}
441#endif /* DEBUG */
442
443/*
444 * Interrupt handling routines.
445 */
446
447/**
448 * sn_receive_chars - Grab characters, pass them to tty layer
449 * @port: Port to operate on
450 * @flags: irq flags
451 *
452 * Note: If we're not registered with the serial core infrastructure yet,
453 * we don't try to send characters to it...
454 *
455 */
456static void
457sn_receive_chars(struct sn_cons_port *port, unsigned long flags)
458{
459 int ch;
460 struct tty_struct *tty;
461
462 if (!port) {
463 printk(KERN_ERR "sn_receive_chars - port NULL so can't receieve\n");
464 return;
465 }
466
467 if (!port->sc_ops) {
468 printk(KERN_ERR "sn_receive_chars - port->sc_ops NULL so can't receieve\n");
469 return;
470 }
471
472 if (port->sc_port.state) {
473 /* The serial_core stuffs are initialized, use them */
474 tty = port->sc_port.state->port.tty;
475 }
476 else {
477 /* Not registered yet - can't pass to tty layer. */
478 tty = NULL;
479 }
480
481 while (port->sc_ops->sal_input_pending()) {
482 ch = port->sc_ops->sal_getc();
483 if (ch < 0) {
484 printk(KERN_ERR "sn_console: An error occured while "
485 "obtaining data from the console (0x%0x)\n", ch);
486 break;
487 }
488#ifdef CONFIG_MAGIC_SYSRQ
489 if (sysrq_requested) {
490 unsigned long sysrq_timeout = sysrq_requested + HZ*5;
491
492 sysrq_requested = 0;
493 if (ch && time_before(jiffies, sysrq_timeout)) {
494 spin_unlock_irqrestore(&port->sc_port.lock, flags);
495 handle_sysrq(ch);
496 spin_lock_irqsave(&port->sc_port.lock, flags);
497 /* ignore actual sysrq command char */
498 continue;
499 }
500 }
501 if (ch == *sysrq_serial_ptr) {
502 if (!(*++sysrq_serial_ptr)) {
503 sysrq_requested = jiffies;
504 sysrq_serial_ptr = sysrq_serial_str;
505 }
506 /*
507 * ignore the whole sysrq string except for the
508 * leading escape
509 */
510 if (ch != '\e')
511 continue;
512 }
513 else
514 sysrq_serial_ptr = sysrq_serial_str;
515#endif /* CONFIG_MAGIC_SYSRQ */
516
517 /* record the character to pass up to the tty layer */
518 if (tty) {
519 if(tty_insert_flip_char(tty, ch, TTY_NORMAL) == 0)
520 break;
521 }
522 port->sc_port.icount.rx++;
523 }
524
525 if (tty)
526 tty_flip_buffer_push(tty);
527}
528
529/**
530 * sn_transmit_chars - grab characters from serial core, send off
531 * @port: Port to operate on
532 * @raw: Transmit raw or buffered
533 *
534 * Note: If we're early, before we're registered with serial core, the
535 * writes are going through sn_sal_console_write because that's how
536 * register_console has been set up. We currently could have asynch
537 * polls calling this function due to sn_sal_switch_to_asynch but we can
538 * ignore them until we register with the serial core stuffs.
539 *
540 */
541static void sn_transmit_chars(struct sn_cons_port *port, int raw)
542{
543 int xmit_count, tail, head, loops, ii;
544 int result;
545 char *start;
546 struct circ_buf *xmit;
547
548 if (!port)
549 return;
550
551 BUG_ON(!port->sc_is_asynch);
552
553 if (port->sc_port.state) {
554 /* We're initialized, using serial core infrastructure */
555 xmit = &port->sc_port.state->xmit;
556 } else {
557 /* Probably sn_sal_switch_to_asynch has been run but serial core isn't
558 * initialized yet. Just return. Writes are going through
559 * sn_sal_console_write (due to register_console) at this time.
560 */
561 return;
562 }
563
564 if (uart_circ_empty(xmit) || uart_tx_stopped(&port->sc_port)) {
565 /* Nothing to do. */
566 ia64_sn_console_intr_disable(SAL_CONSOLE_INTR_XMIT);
567 return;
568 }
569
570 head = xmit->head;
571 tail = xmit->tail;
572 start = &xmit->buf[tail];
573
574 /* twice around gets the tail to the end of the buffer and
575 * then to the head, if needed */
576 loops = (head < tail) ? 2 : 1;
577
578 for (ii = 0; ii < loops; ii++) {
579 xmit_count = (head < tail) ?
580 (UART_XMIT_SIZE - tail) : (head - tail);
581
582 if (xmit_count > 0) {
583 if (raw == TRANSMIT_RAW)
584 result =
585 port->sc_ops->sal_puts_raw(start,
586 xmit_count);
587 else
588 result =
589 port->sc_ops->sal_puts(start, xmit_count);
590#ifdef DEBUG
591 if (!result)
592 DPRINTF("`");
593#endif
594 if (result > 0) {
595 xmit_count -= result;
596 port->sc_port.icount.tx += result;
597 tail += result;
598 tail &= UART_XMIT_SIZE - 1;
599 xmit->tail = tail;
600 start = &xmit->buf[tail];
601 }
602 }
603 }
604
605 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
606 uart_write_wakeup(&port->sc_port);
607
608 if (uart_circ_empty(xmit))
609 snp_stop_tx(&port->sc_port); /* no-op for us */
610}
611
612/**
613 * sn_sal_interrupt - Handle console interrupts
614 * @irq: irq #, useful for debug statements
615 * @dev_id: our pointer to our port (sn_cons_port which contains the uart port)
616 *
617 */
618static irqreturn_t sn_sal_interrupt(int irq, void *dev_id)
619{
620 struct sn_cons_port *port = (struct sn_cons_port *)dev_id;
621 unsigned long flags;
622 int status = ia64_sn_console_intr_status();
623
624 if (!port)
625 return IRQ_NONE;
626
627 spin_lock_irqsave(&port->sc_port.lock, flags);
628 if (status & SAL_CONSOLE_INTR_RECV) {
629 sn_receive_chars(port, flags);
630 }
631 if (status & SAL_CONSOLE_INTR_XMIT) {
632 sn_transmit_chars(port, TRANSMIT_BUFFERED);
633 }
634 spin_unlock_irqrestore(&port->sc_port.lock, flags);
635 return IRQ_HANDLED;
636}
637
638/**
639 * sn_sal_timer_poll - this function handles polled console mode
640 * @data: A pointer to our sn_cons_port (which contains the uart port)
641 *
642 * data is the pointer that init_timer will store for us. This function is
643 * associated with init_timer to see if there is any console traffic.
644 * Obviously not used in interrupt mode
645 *
646 */
647static void sn_sal_timer_poll(unsigned long data)
648{
649 struct sn_cons_port *port = (struct sn_cons_port *)data;
650 unsigned long flags;
651
652 if (!port)
653 return;
654
655 if (!port->sc_port.irq) {
656 spin_lock_irqsave(&port->sc_port.lock, flags);
657 if (sn_process_input)
658 sn_receive_chars(port, flags);
659 sn_transmit_chars(port, TRANSMIT_RAW);
660 spin_unlock_irqrestore(&port->sc_port.lock, flags);
661 mod_timer(&port->sc_timer,
662 jiffies + port->sc_interrupt_timeout);
663 }
664}
665
666/*
667 * Boot-time initialization code
668 */
669
670/**
671 * sn_sal_switch_to_asynch - Switch to async mode (as opposed to synch)
672 * @port: Our sn_cons_port (which contains the uart port)
673 *
674 * So this is used by sn_sal_serial_console_init (early on, before we're
675 * registered with serial core). It's also used by sn_sal_module_init
676 * right after we've registered with serial core. The later only happens
677 * if we didn't already come through here via sn_sal_serial_console_init.
678 *
679 */
680static void __init sn_sal_switch_to_asynch(struct sn_cons_port *port)
681{
682 unsigned long flags;
683
684 if (!port)
685 return;
686
687 DPRINTF("sn_console: about to switch to asynchronous console\n");
688
689 /* without early_printk, we may be invoked late enough to race
690 * with other cpus doing console IO at this point, however
691 * console interrupts will never be enabled */
692 spin_lock_irqsave(&port->sc_port.lock, flags);
693
694 /* early_printk invocation may have done this for us */
695 if (!port->sc_ops)
696 port->sc_ops = &poll_ops;
697
698 /* we can't turn on the console interrupt (as request_irq
699 * calls kmalloc, which isn't set up yet), so we rely on a
700 * timer to poll for input and push data from the console
701 * buffer.
702 */
703 init_timer(&port->sc_timer);
704 port->sc_timer.function = sn_sal_timer_poll;
705 port->sc_timer.data = (unsigned long)port;
706
707 if (IS_RUNNING_ON_SIMULATOR())
708 port->sc_interrupt_timeout = 6;
709 else {
710 /* 960cps / 16 char FIFO = 60HZ
711 * HZ / (SN_SAL_FIFO_SPEED_CPS / SN_SAL_FIFO_DEPTH) */
712 port->sc_interrupt_timeout =
713 HZ * SN_SAL_UART_FIFO_DEPTH / SN_SAL_UART_FIFO_SPEED_CPS;
714 }
715 mod_timer(&port->sc_timer, jiffies + port->sc_interrupt_timeout);
716
717 port->sc_is_asynch = 1;
718 spin_unlock_irqrestore(&port->sc_port.lock, flags);
719}
720
721/**
722 * sn_sal_switch_to_interrupts - Switch to interrupt driven mode
723 * @port: Our sn_cons_port (which contains the uart port)
724 *
725 * In sn_sal_module_init, after we're registered with serial core and
726 * the port is added, this function is called to switch us to interrupt
727 * mode. We were previously in asynch/polling mode (using init_timer).
728 *
729 * We attempt to switch to interrupt mode here by calling
730 * request_irq. If that works out, we enable receive interrupts.
731 */
732static void __init sn_sal_switch_to_interrupts(struct sn_cons_port *port)
733{
734 unsigned long flags;
735
736 if (port) {
737 DPRINTF("sn_console: switching to interrupt driven console\n");
738
739 if (request_irq(SGI_UART_VECTOR, sn_sal_interrupt,
740 IRQF_DISABLED | IRQF_SHARED,
741 "SAL console driver", port) >= 0) {
742 spin_lock_irqsave(&port->sc_port.lock, flags);
743 port->sc_port.irq = SGI_UART_VECTOR;
744 port->sc_ops = &intr_ops;
745
746 /* turn on receive interrupts */
747 ia64_sn_console_intr_enable(SAL_CONSOLE_INTR_RECV);
748 spin_unlock_irqrestore(&port->sc_port.lock, flags);
749 }
750 else {
751 printk(KERN_INFO
752 "sn_console: console proceeding in polled mode\n");
753 }
754 }
755}
756
757/*
758 * Kernel console definitions
759 */
760
761static void sn_sal_console_write(struct console *, const char *, unsigned);
762static int sn_sal_console_setup(struct console *, char *);
763static struct uart_driver sal_console_uart;
764extern struct tty_driver *uart_console_device(struct console *, int *);
765
766static struct console sal_console = {
767 .name = DEVICE_NAME,
768 .write = sn_sal_console_write,
769 .device = uart_console_device,
770 .setup = sn_sal_console_setup,
771 .index = -1, /* unspecified */
772 .data = &sal_console_uart,
773};
774
775#define SAL_CONSOLE &sal_console
776
777static struct uart_driver sal_console_uart = {
778 .owner = THIS_MODULE,
779 .driver_name = "sn_console",
780 .dev_name = DEVICE_NAME,
781 .major = 0, /* major/minor set at registration time per USE_DYNAMIC_MINOR */
782 .minor = 0,
783 .nr = 1, /* one port */
784 .cons = SAL_CONSOLE,
785};
786
787/**
788 * sn_sal_module_init - When the kernel loads us, get us rolling w/ serial core
789 *
790 * Before this is called, we've been printing kernel messages in a special
791 * early mode not making use of the serial core infrastructure. When our
792 * driver is loaded for real, we register the driver and port with serial
793 * core and try to enable interrupt driven mode.
794 *
795 */
796static int __init sn_sal_module_init(void)
797{
798 int retval;
799
800 if (!ia64_platform_is("sn2"))
801 return 0;
802
803 printk(KERN_INFO "sn_console: Console driver init\n");
804
805 if (USE_DYNAMIC_MINOR == 1) {
806 misc.minor = MISC_DYNAMIC_MINOR;
807 misc.name = DEVICE_NAME_DYNAMIC;
808 retval = misc_register(&misc);
809 if (retval != 0) {
810 printk(KERN_WARNING "Failed to register console "
811 "device using misc_register.\n");
812 return -ENODEV;
813 }
814 sal_console_uart.major = MISC_MAJOR;
815 sal_console_uart.minor = misc.minor;
816 } else {
817 sal_console_uart.major = DEVICE_MAJOR;
818 sal_console_uart.minor = DEVICE_MINOR;
819 }
820
821 /* We register the driver and the port before switching to interrupts
822 * or async above so the proper uart structures are populated */
823
824 if (uart_register_driver(&sal_console_uart) < 0) {
825 printk
826 ("ERROR sn_sal_module_init failed uart_register_driver, line %d\n",
827 __LINE__);
828 return -ENODEV;
829 }
830
831 spin_lock_init(&sal_console_port.sc_port.lock);
832
833 /* Setup the port struct with the minimum needed */
834 sal_console_port.sc_port.membase = (char *)1; /* just needs to be non-zero */
835 sal_console_port.sc_port.type = PORT_16550A;
836 sal_console_port.sc_port.fifosize = SN_SAL_MAX_CHARS;
837 sal_console_port.sc_port.ops = &sn_console_ops;
838 sal_console_port.sc_port.line = 0;
839
840 if (uart_add_one_port(&sal_console_uart, &sal_console_port.sc_port) < 0) {
841 /* error - not sure what I'd do - so I'll do nothing */
842 printk(KERN_ERR "%s: unable to add port\n", __func__);
843 }
844
845 /* when this driver is compiled in, the console initialization
846 * will have already switched us into asynchronous operation
847 * before we get here through the module initcalls */
848 if (!sal_console_port.sc_is_asynch) {
849 sn_sal_switch_to_asynch(&sal_console_port);
850 }
851
852 /* at this point (module_init) we can try to turn on interrupts */
853 if (!IS_RUNNING_ON_SIMULATOR()) {
854 sn_sal_switch_to_interrupts(&sal_console_port);
855 }
856 sn_process_input = 1;
857 return 0;
858}
859
860/**
861 * sn_sal_module_exit - When we're unloaded, remove the driver/port
862 *
863 */
864static void __exit sn_sal_module_exit(void)
865{
866 del_timer_sync(&sal_console_port.sc_timer);
867 uart_remove_one_port(&sal_console_uart, &sal_console_port.sc_port);
868 uart_unregister_driver(&sal_console_uart);
869 misc_deregister(&misc);
870}
871
872module_init(sn_sal_module_init);
873module_exit(sn_sal_module_exit);
874
875/**
876 * puts_raw_fixed - sn_sal_console_write helper for adding \r's as required
877 * @puts_raw : puts function to do the writing
878 * @s: input string
879 * @count: length
880 *
881 * We need a \r ahead of every \n for direct writes through
882 * ia64_sn_console_putb (what sal_puts_raw below actually does).
883 *
884 */
885
886static void puts_raw_fixed(int (*puts_raw) (const char *s, int len),
887 const char *s, int count)
888{
889 const char *s1;
890
891 /* Output '\r' before each '\n' */
892 while ((s1 = memchr(s, '\n', count)) != NULL) {
893 puts_raw(s, s1 - s);
894 puts_raw("\r\n", 2);
895 count -= s1 + 1 - s;
896 s = s1 + 1;
897 }
898 puts_raw(s, count);
899}
900
901/**
902 * sn_sal_console_write - Print statements before serial core available
903 * @console: Console to operate on - we ignore since we have just one
904 * @s: String to send
905 * @count: length
906 *
907 * This is referenced in the console struct. It is used for early
908 * console printing before we register with serial core and for things
909 * such as kdb. The console_lock must be held when we get here.
910 *
911 * This function has some code for trying to print output even if the lock
912 * is held. We try to cover the case where a lock holder could have died.
913 * We don't use this special case code if we're not registered with serial
914 * core yet. After we're registered with serial core, the only time this
915 * function would be used is for high level kernel output like magic sys req,
916 * kdb, and printk's.
917 */
918static void
919sn_sal_console_write(struct console *co, const char *s, unsigned count)
920{
921 unsigned long flags = 0;
922 struct sn_cons_port *port = &sal_console_port;
923 static int stole_lock = 0;
924
925 BUG_ON(!port->sc_is_asynch);
926
927 /* We can't look at the xmit buffer if we're not registered with serial core
928 * yet. So only do the fancy recovery after registering
929 */
930 if (!port->sc_port.state) {
931 /* Not yet registered with serial core - simple case */
932 puts_raw_fixed(port->sc_ops->sal_puts_raw, s, count);
933 return;
934 }
935
936 /* somebody really wants this output, might be an
937 * oops, kdb, panic, etc. make sure they get it. */
938 if (spin_is_locked(&port->sc_port.lock)) {
939 int lhead = port->sc_port.state->xmit.head;
940 int ltail = port->sc_port.state->xmit.tail;
941 int counter, got_lock = 0;
942
943 /*
944 * We attempt to determine if someone has died with the
945 * lock. We wait ~20 secs after the head and tail ptrs
946 * stop moving and assume the lock holder is not functional
947 * and plow ahead. If the lock is freed within the time out
948 * period we re-get the lock and go ahead normally. We also
949 * remember if we have plowed ahead so that we don't have
950 * to wait out the time out period again - the asumption
951 * is that we will time out again.
952 */
953
954 for (counter = 0; counter < 150; mdelay(125), counter++) {
955 if (!spin_is_locked(&port->sc_port.lock)
956 || stole_lock) {
957 if (!stole_lock) {
958 spin_lock_irqsave(&port->sc_port.lock,
959 flags);
960 got_lock = 1;
961 }
962 break;
963 } else {
964 /* still locked */
965 if ((lhead != port->sc_port.state->xmit.head)
966 || (ltail !=
967 port->sc_port.state->xmit.tail)) {
968 lhead =
969 port->sc_port.state->xmit.head;
970 ltail =
971 port->sc_port.state->xmit.tail;
972 counter = 0;
973 }
974 }
975 }
976 /* flush anything in the serial core xmit buffer, raw */
977 sn_transmit_chars(port, 1);
978 if (got_lock) {
979 spin_unlock_irqrestore(&port->sc_port.lock, flags);
980 stole_lock = 0;
981 } else {
982 /* fell thru */
983 stole_lock = 1;
984 }
985 puts_raw_fixed(port->sc_ops->sal_puts_raw, s, count);
986 } else {
987 stole_lock = 0;
988 spin_lock_irqsave(&port->sc_port.lock, flags);
989 sn_transmit_chars(port, 1);
990 spin_unlock_irqrestore(&port->sc_port.lock, flags);
991
992 puts_raw_fixed(port->sc_ops->sal_puts_raw, s, count);
993 }
994}
995
996
997/**
998 * sn_sal_console_setup - Set up console for early printing
999 * @co: Console to work with
1000 * @options: Options to set
1001 *
1002 * Altix console doesn't do anything with baud rates, etc, anyway.
1003 *
1004 * This isn't required since not providing the setup function in the
1005 * console struct is ok. However, other patches like KDB plop something
1006 * here so providing it is easier.
1007 *
1008 */
1009static int sn_sal_console_setup(struct console *co, char *options)
1010{
1011 return 0;
1012}
1013
1014/**
1015 * sn_sal_console_write_early - simple early output routine
1016 * @co - console struct
1017 * @s - string to print
1018 * @count - count
1019 *
1020 * Simple function to provide early output, before even
1021 * sn_sal_serial_console_init is called. Referenced in the
1022 * console struct registerd in sn_serial_console_early_setup.
1023 *
1024 */
1025static void __init
1026sn_sal_console_write_early(struct console *co, const char *s, unsigned count)
1027{
1028 puts_raw_fixed(sal_console_port.sc_ops->sal_puts_raw, s, count);
1029}
1030
1031/* Used for very early console printing - again, before
1032 * sn_sal_serial_console_init is run */
1033static struct console sal_console_early __initdata = {
1034 .name = "sn_sal",
1035 .write = sn_sal_console_write_early,
1036 .flags = CON_PRINTBUFFER,
1037 .index = -1,
1038};
1039
1040/**
1041 * sn_serial_console_early_setup - Sets up early console output support
1042 *
1043 * Register a console early on... This is for output before even
1044 * sn_sal_serial_cosnole_init is called. This function is called from
1045 * setup.c. This allows us to do really early polled writes. When
1046 * sn_sal_serial_console_init is called, this console is unregistered
1047 * and a new one registered.
1048 */
1049int __init sn_serial_console_early_setup(void)
1050{
1051 if (!ia64_platform_is("sn2"))
1052 return -1;
1053
1054 sal_console_port.sc_ops = &poll_ops;
1055 spin_lock_init(&sal_console_port.sc_port.lock);
1056 early_sn_setup(); /* Find SAL entry points */
1057 register_console(&sal_console_early);
1058
1059 return 0;
1060}
1061
1062/**
1063 * sn_sal_serial_console_init - Early console output - set up for register
1064 *
1065 * This function is called when regular console init happens. Because we
1066 * support even earlier console output with sn_serial_console_early_setup
1067 * (called from setup.c directly), this function unregisters the really
1068 * early console.
1069 *
1070 * Note: Even if setup.c doesn't register sal_console_early, unregistering
1071 * it here doesn't hurt anything.
1072 *
1073 */
1074static int __init sn_sal_serial_console_init(void)
1075{
1076 if (ia64_platform_is("sn2")) {
1077 sn_sal_switch_to_asynch(&sal_console_port);
1078 DPRINTF("sn_sal_serial_console_init : register console\n");
1079 register_console(&sal_console);
1080 unregister_console(&sal_console_early);
1081 }
1082 return 0;
1083}
1084
1085console_initcall(sn_sal_serial_console_init);
diff --git a/drivers/serial/suncore.c b/drivers/serial/suncore.c
deleted file mode 100644
index 6381a0282ee7..000000000000
--- a/drivers/serial/suncore.c
+++ /dev/null
@@ -1,247 +0,0 @@
1/* suncore.c
2 *
3 * Common SUN serial routines. Based entirely
4 * upon drivers/sbus/char/sunserial.c which is:
5 *
6 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
7 *
8 * Adaptation to new UART layer is:
9 *
10 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
11 */
12
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/console.h>
16#include <linux/tty.h>
17#include <linux/errno.h>
18#include <linux/string.h>
19#include <linux/serial_core.h>
20#include <linux/init.h>
21
22#include <asm/prom.h>
23
24#include "suncore.h"
25
26static int sunserial_current_minor = 64;
27
28int sunserial_register_minors(struct uart_driver *drv, int count)
29{
30 int err = 0;
31
32 drv->minor = sunserial_current_minor;
33 drv->nr += count;
34 /* Register the driver on the first call */
35 if (drv->nr == count)
36 err = uart_register_driver(drv);
37 if (err == 0) {
38 sunserial_current_minor += count;
39 drv->tty_driver->name_base = drv->minor - 64;
40 }
41 return err;
42}
43EXPORT_SYMBOL(sunserial_register_minors);
44
45void sunserial_unregister_minors(struct uart_driver *drv, int count)
46{
47 drv->nr -= count;
48 sunserial_current_minor -= count;
49
50 if (drv->nr == 0)
51 uart_unregister_driver(drv);
52}
53EXPORT_SYMBOL(sunserial_unregister_minors);
54
55int sunserial_console_match(struct console *con, struct device_node *dp,
56 struct uart_driver *drv, int line, bool ignore_line)
57{
58 if (!con)
59 return 0;
60
61 drv->cons = con;
62
63 if (of_console_device != dp)
64 return 0;
65
66 if (!ignore_line) {
67 int off = 0;
68
69 if (of_console_options &&
70 *of_console_options == 'b')
71 off = 1;
72
73 if ((line & 1) != off)
74 return 0;
75 }
76
77 if (!console_set_on_cmdline) {
78 con->index = line;
79 add_preferred_console(con->name, line, NULL);
80 }
81 return 1;
82}
83EXPORT_SYMBOL(sunserial_console_match);
84
85void sunserial_console_termios(struct console *con, struct device_node *uart_dp)
86{
87 const char *mode, *s;
88 char mode_prop[] = "ttyX-mode";
89 int baud, bits, stop, cflag;
90 char parity;
91
92 if (!strcmp(uart_dp->name, "rsc") ||
93 !strcmp(uart_dp->name, "rsc-console") ||
94 !strcmp(uart_dp->name, "rsc-control")) {
95 mode = of_get_property(uart_dp,
96 "ssp-console-modes", NULL);
97 if (!mode)
98 mode = "115200,8,n,1,-";
99 } else if (!strcmp(uart_dp->name, "lom-console")) {
100 mode = "9600,8,n,1,-";
101 } else {
102 struct device_node *dp;
103 char c;
104
105 c = 'a';
106 if (of_console_options)
107 c = *of_console_options;
108
109 mode_prop[3] = c;
110
111 dp = of_find_node_by_path("/options");
112 mode = of_get_property(dp, mode_prop, NULL);
113 if (!mode)
114 mode = "9600,8,n,1,-";
115 }
116
117 cflag = CREAD | HUPCL | CLOCAL;
118
119 s = mode;
120 baud = simple_strtoul(s, NULL, 0);
121 s = strchr(s, ',');
122 bits = simple_strtoul(++s, NULL, 0);
123 s = strchr(s, ',');
124 parity = *(++s);
125 s = strchr(s, ',');
126 stop = simple_strtoul(++s, NULL, 0);
127 s = strchr(s, ',');
128 /* XXX handshake is not handled here. */
129
130 switch (baud) {
131 case 150: cflag |= B150; break;
132 case 300: cflag |= B300; break;
133 case 600: cflag |= B600; break;
134 case 1200: cflag |= B1200; break;
135 case 2400: cflag |= B2400; break;
136 case 4800: cflag |= B4800; break;
137 case 9600: cflag |= B9600; break;
138 case 19200: cflag |= B19200; break;
139 case 38400: cflag |= B38400; break;
140 case 57600: cflag |= B57600; break;
141 case 115200: cflag |= B115200; break;
142 case 230400: cflag |= B230400; break;
143 case 460800: cflag |= B460800; break;
144 default: baud = 9600; cflag |= B9600; break;
145 }
146
147 switch (bits) {
148 case 5: cflag |= CS5; break;
149 case 6: cflag |= CS6; break;
150 case 7: cflag |= CS7; break;
151 case 8: cflag |= CS8; break;
152 default: cflag |= CS8; break;
153 }
154
155 switch (parity) {
156 case 'o': cflag |= (PARENB | PARODD); break;
157 case 'e': cflag |= PARENB; break;
158 case 'n': default: break;
159 }
160
161 switch (stop) {
162 case 2: cflag |= CSTOPB; break;
163 case 1: default: break;
164 }
165
166 con->cflag = cflag;
167}
168
169/* Sun serial MOUSE auto baud rate detection. */
170static struct mouse_baud_cflag {
171 int baud;
172 unsigned int cflag;
173} mouse_baud_table[] = {
174 { 1200, B1200 },
175 { 2400, B2400 },
176 { 4800, B4800 },
177 { 9600, B9600 },
178 { -1, ~0 },
179 { -1, ~0 },
180};
181
182unsigned int suncore_mouse_baud_cflag_next(unsigned int cflag, int *new_baud)
183{
184 int i;
185
186 for (i = 0; mouse_baud_table[i].baud != -1; i++)
187 if (mouse_baud_table[i].cflag == (cflag & CBAUD))
188 break;
189
190 i += 1;
191 if (mouse_baud_table[i].baud == -1)
192 i = 0;
193
194 *new_baud = mouse_baud_table[i].baud;
195 return mouse_baud_table[i].cflag;
196}
197
198EXPORT_SYMBOL(suncore_mouse_baud_cflag_next);
199
200/* Basically, when the baud rate is wrong the mouse spits out
201 * breaks to us.
202 */
203int suncore_mouse_baud_detection(unsigned char ch, int is_break)
204{
205 static int mouse_got_break = 0;
206 static int ctr = 0;
207
208 if (is_break) {
209 /* Let a few normal bytes go by before we jump the gun
210 * and say we need to try another baud rate.
211 */
212 if (mouse_got_break && ctr < 8)
213 return 1;
214
215 /* Ok, we need to try another baud. */
216 ctr = 0;
217 mouse_got_break = 1;
218 return 2;
219 }
220 if (mouse_got_break) {
221 ctr++;
222 if (ch == 0x87) {
223 /* Correct baud rate determined. */
224 mouse_got_break = 0;
225 }
226 return 1;
227 }
228 return 0;
229}
230
231EXPORT_SYMBOL(suncore_mouse_baud_detection);
232
233static int __init suncore_init(void)
234{
235 return 0;
236}
237
238static void __exit suncore_exit(void)
239{
240}
241
242module_init(suncore_init);
243module_exit(suncore_exit);
244
245MODULE_AUTHOR("Eddie C. Dost, David S. Miller");
246MODULE_DESCRIPTION("Sun serial common layer");
247MODULE_LICENSE("GPL");
diff --git a/drivers/serial/suncore.h b/drivers/serial/suncore.h
deleted file mode 100644
index db2057936c31..000000000000
--- a/drivers/serial/suncore.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/* suncore.h
2 *
3 * Generic SUN serial/kbd/ms layer. Based entirely
4 * upon drivers/sbus/char/sunserial.h which is:
5 *
6 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
7 *
8 * Port to new UART layer is:
9 *
10 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
11 */
12
13#ifndef _SERIAL_SUN_H
14#define _SERIAL_SUN_H
15
16/* Serial keyboard defines for L1-A processing... */
17#define SUNKBD_RESET 0xff
18#define SUNKBD_L1 0x01
19#define SUNKBD_UP 0x80
20#define SUNKBD_A 0x4d
21
22extern unsigned int suncore_mouse_baud_cflag_next(unsigned int, int *);
23extern int suncore_mouse_baud_detection(unsigned char, int);
24
25extern int sunserial_register_minors(struct uart_driver *, int);
26extern void sunserial_unregister_minors(struct uart_driver *, int);
27
28extern int sunserial_console_match(struct console *, struct device_node *,
29 struct uart_driver *, int, bool);
30extern void sunserial_console_termios(struct console *,
31 struct device_node *);
32
33#endif /* !(_SERIAL_SUN_H) */
diff --git a/drivers/serial/sunhv.c b/drivers/serial/sunhv.c
deleted file mode 100644
index c9014868297d..000000000000
--- a/drivers/serial/sunhv.c
+++ /dev/null
@@ -1,661 +0,0 @@
1/* sunhv.c: Serial driver for SUN4V hypervisor console.
2 *
3 * Copyright (C) 2006, 2007 David S. Miller (davem@davemloft.net)
4 */
5
6#include <linux/module.h>
7#include <linux/kernel.h>
8#include <linux/errno.h>
9#include <linux/tty.h>
10#include <linux/tty_flip.h>
11#include <linux/major.h>
12#include <linux/circ_buf.h>
13#include <linux/serial.h>
14#include <linux/sysrq.h>
15#include <linux/console.h>
16#include <linux/spinlock.h>
17#include <linux/slab.h>
18#include <linux/delay.h>
19#include <linux/init.h>
20#include <linux/of_device.h>
21
22#include <asm/hypervisor.h>
23#include <asm/spitfire.h>
24#include <asm/prom.h>
25#include <asm/irq.h>
26
27#if defined(CONFIG_MAGIC_SYSRQ)
28#define SUPPORT_SYSRQ
29#endif
30
31#include <linux/serial_core.h>
32
33#include "suncore.h"
34
35#define CON_BREAK ((long)-1)
36#define CON_HUP ((long)-2)
37
38#define IGNORE_BREAK 0x1
39#define IGNORE_ALL 0x2
40
41static char *con_write_page;
42static char *con_read_page;
43
44static int hung_up = 0;
45
46static void transmit_chars_putchar(struct uart_port *port, struct circ_buf *xmit)
47{
48 while (!uart_circ_empty(xmit)) {
49 long status = sun4v_con_putchar(xmit->buf[xmit->tail]);
50
51 if (status != HV_EOK)
52 break;
53
54 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
55 port->icount.tx++;
56 }
57}
58
59static void transmit_chars_write(struct uart_port *port, struct circ_buf *xmit)
60{
61 while (!uart_circ_empty(xmit)) {
62 unsigned long ra = __pa(xmit->buf + xmit->tail);
63 unsigned long len, status, sent;
64
65 len = CIRC_CNT_TO_END(xmit->head, xmit->tail,
66 UART_XMIT_SIZE);
67 status = sun4v_con_write(ra, len, &sent);
68 if (status != HV_EOK)
69 break;
70 xmit->tail = (xmit->tail + sent) & (UART_XMIT_SIZE - 1);
71 port->icount.tx += sent;
72 }
73}
74
75static int receive_chars_getchar(struct uart_port *port, struct tty_struct *tty)
76{
77 int saw_console_brk = 0;
78 int limit = 10000;
79
80 while (limit-- > 0) {
81 long status;
82 long c = sun4v_con_getchar(&status);
83
84 if (status == HV_EWOULDBLOCK)
85 break;
86
87 if (c == CON_BREAK) {
88 if (uart_handle_break(port))
89 continue;
90 saw_console_brk = 1;
91 c = 0;
92 }
93
94 if (c == CON_HUP) {
95 hung_up = 1;
96 uart_handle_dcd_change(port, 0);
97 } else if (hung_up) {
98 hung_up = 0;
99 uart_handle_dcd_change(port, 1);
100 }
101
102 if (tty == NULL) {
103 uart_handle_sysrq_char(port, c);
104 continue;
105 }
106
107 port->icount.rx++;
108
109 if (uart_handle_sysrq_char(port, c))
110 continue;
111
112 tty_insert_flip_char(tty, c, TTY_NORMAL);
113 }
114
115 return saw_console_brk;
116}
117
118static int receive_chars_read(struct uart_port *port, struct tty_struct *tty)
119{
120 int saw_console_brk = 0;
121 int limit = 10000;
122
123 while (limit-- > 0) {
124 unsigned long ra = __pa(con_read_page);
125 unsigned long bytes_read, i;
126 long stat = sun4v_con_read(ra, PAGE_SIZE, &bytes_read);
127
128 if (stat != HV_EOK) {
129 bytes_read = 0;
130
131 if (stat == CON_BREAK) {
132 if (uart_handle_break(port))
133 continue;
134 saw_console_brk = 1;
135 *con_read_page = 0;
136 bytes_read = 1;
137 } else if (stat == CON_HUP) {
138 hung_up = 1;
139 uart_handle_dcd_change(port, 0);
140 continue;
141 } else {
142 /* HV_EWOULDBLOCK, etc. */
143 break;
144 }
145 }
146
147 if (hung_up) {
148 hung_up = 0;
149 uart_handle_dcd_change(port, 1);
150 }
151
152 for (i = 0; i < bytes_read; i++)
153 uart_handle_sysrq_char(port, con_read_page[i]);
154
155 if (tty == NULL)
156 continue;
157
158 port->icount.rx += bytes_read;
159
160 tty_insert_flip_string(tty, con_read_page, bytes_read);
161 }
162
163 return saw_console_brk;
164}
165
166struct sunhv_ops {
167 void (*transmit_chars)(struct uart_port *port, struct circ_buf *xmit);
168 int (*receive_chars)(struct uart_port *port, struct tty_struct *tty);
169};
170
171static struct sunhv_ops bychar_ops = {
172 .transmit_chars = transmit_chars_putchar,
173 .receive_chars = receive_chars_getchar,
174};
175
176static struct sunhv_ops bywrite_ops = {
177 .transmit_chars = transmit_chars_write,
178 .receive_chars = receive_chars_read,
179};
180
181static struct sunhv_ops *sunhv_ops = &bychar_ops;
182
183static struct tty_struct *receive_chars(struct uart_port *port)
184{
185 struct tty_struct *tty = NULL;
186
187 if (port->state != NULL) /* Unopened serial console */
188 tty = port->state->port.tty;
189
190 if (sunhv_ops->receive_chars(port, tty))
191 sun_do_break();
192
193 return tty;
194}
195
196static void transmit_chars(struct uart_port *port)
197{
198 struct circ_buf *xmit;
199
200 if (!port->state)
201 return;
202
203 xmit = &port->state->xmit;
204 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
205 return;
206
207 sunhv_ops->transmit_chars(port, xmit);
208
209 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
210 uart_write_wakeup(port);
211}
212
213static irqreturn_t sunhv_interrupt(int irq, void *dev_id)
214{
215 struct uart_port *port = dev_id;
216 struct tty_struct *tty;
217 unsigned long flags;
218
219 spin_lock_irqsave(&port->lock, flags);
220 tty = receive_chars(port);
221 transmit_chars(port);
222 spin_unlock_irqrestore(&port->lock, flags);
223
224 if (tty)
225 tty_flip_buffer_push(tty);
226
227 return IRQ_HANDLED;
228}
229
230/* port->lock is not held. */
231static unsigned int sunhv_tx_empty(struct uart_port *port)
232{
233 /* Transmitter is always empty for us. If the circ buffer
234 * is non-empty or there is an x_char pending, our caller
235 * will do the right thing and ignore what we return here.
236 */
237 return TIOCSER_TEMT;
238}
239
240/* port->lock held by caller. */
241static void sunhv_set_mctrl(struct uart_port *port, unsigned int mctrl)
242{
243 return;
244}
245
246/* port->lock is held by caller and interrupts are disabled. */
247static unsigned int sunhv_get_mctrl(struct uart_port *port)
248{
249 return TIOCM_DSR | TIOCM_CAR | TIOCM_CTS;
250}
251
252/* port->lock held by caller. */
253static void sunhv_stop_tx(struct uart_port *port)
254{
255 return;
256}
257
258/* port->lock held by caller. */
259static void sunhv_start_tx(struct uart_port *port)
260{
261 transmit_chars(port);
262}
263
264/* port->lock is not held. */
265static void sunhv_send_xchar(struct uart_port *port, char ch)
266{
267 unsigned long flags;
268 int limit = 10000;
269
270 spin_lock_irqsave(&port->lock, flags);
271
272 while (limit-- > 0) {
273 long status = sun4v_con_putchar(ch);
274 if (status == HV_EOK)
275 break;
276 udelay(1);
277 }
278
279 spin_unlock_irqrestore(&port->lock, flags);
280}
281
282/* port->lock held by caller. */
283static void sunhv_stop_rx(struct uart_port *port)
284{
285}
286
287/* port->lock held by caller. */
288static void sunhv_enable_ms(struct uart_port *port)
289{
290}
291
292/* port->lock is not held. */
293static void sunhv_break_ctl(struct uart_port *port, int break_state)
294{
295 if (break_state) {
296 unsigned long flags;
297 int limit = 10000;
298
299 spin_lock_irqsave(&port->lock, flags);
300
301 while (limit-- > 0) {
302 long status = sun4v_con_putchar(CON_BREAK);
303 if (status == HV_EOK)
304 break;
305 udelay(1);
306 }
307
308 spin_unlock_irqrestore(&port->lock, flags);
309 }
310}
311
312/* port->lock is not held. */
313static int sunhv_startup(struct uart_port *port)
314{
315 return 0;
316}
317
318/* port->lock is not held. */
319static void sunhv_shutdown(struct uart_port *port)
320{
321}
322
323/* port->lock is not held. */
324static void sunhv_set_termios(struct uart_port *port, struct ktermios *termios,
325 struct ktermios *old)
326{
327 unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
328 unsigned int quot = uart_get_divisor(port, baud);
329 unsigned int iflag, cflag;
330 unsigned long flags;
331
332 spin_lock_irqsave(&port->lock, flags);
333
334 iflag = termios->c_iflag;
335 cflag = termios->c_cflag;
336
337 port->ignore_status_mask = 0;
338 if (iflag & IGNBRK)
339 port->ignore_status_mask |= IGNORE_BREAK;
340 if ((cflag & CREAD) == 0)
341 port->ignore_status_mask |= IGNORE_ALL;
342
343 /* XXX */
344 uart_update_timeout(port, cflag,
345 (port->uartclk / (16 * quot)));
346
347 spin_unlock_irqrestore(&port->lock, flags);
348}
349
350static const char *sunhv_type(struct uart_port *port)
351{
352 return "SUN4V HCONS";
353}
354
355static void sunhv_release_port(struct uart_port *port)
356{
357}
358
359static int sunhv_request_port(struct uart_port *port)
360{
361 return 0;
362}
363
364static void sunhv_config_port(struct uart_port *port, int flags)
365{
366}
367
368static int sunhv_verify_port(struct uart_port *port, struct serial_struct *ser)
369{
370 return -EINVAL;
371}
372
373static struct uart_ops sunhv_pops = {
374 .tx_empty = sunhv_tx_empty,
375 .set_mctrl = sunhv_set_mctrl,
376 .get_mctrl = sunhv_get_mctrl,
377 .stop_tx = sunhv_stop_tx,
378 .start_tx = sunhv_start_tx,
379 .send_xchar = sunhv_send_xchar,
380 .stop_rx = sunhv_stop_rx,
381 .enable_ms = sunhv_enable_ms,
382 .break_ctl = sunhv_break_ctl,
383 .startup = sunhv_startup,
384 .shutdown = sunhv_shutdown,
385 .set_termios = sunhv_set_termios,
386 .type = sunhv_type,
387 .release_port = sunhv_release_port,
388 .request_port = sunhv_request_port,
389 .config_port = sunhv_config_port,
390 .verify_port = sunhv_verify_port,
391};
392
393static struct uart_driver sunhv_reg = {
394 .owner = THIS_MODULE,
395 .driver_name = "sunhv",
396 .dev_name = "ttyS",
397 .major = TTY_MAJOR,
398};
399
400static struct uart_port *sunhv_port;
401
402/* Copy 's' into the con_write_page, decoding "\n" into
403 * "\r\n" along the way. We have to return two lengths
404 * because the caller needs to know how much to advance
405 * 's' and also how many bytes to output via con_write_page.
406 */
407static int fill_con_write_page(const char *s, unsigned int n,
408 unsigned long *page_bytes)
409{
410 const char *orig_s = s;
411 char *p = con_write_page;
412 int left = PAGE_SIZE;
413
414 while (n--) {
415 if (*s == '\n') {
416 if (left < 2)
417 break;
418 *p++ = '\r';
419 left--;
420 } else if (left < 1)
421 break;
422 *p++ = *s++;
423 left--;
424 }
425 *page_bytes = p - con_write_page;
426 return s - orig_s;
427}
428
429static void sunhv_console_write_paged(struct console *con, const char *s, unsigned n)
430{
431 struct uart_port *port = sunhv_port;
432 unsigned long flags;
433 int locked = 1;
434
435 local_irq_save(flags);
436 if (port->sysrq) {
437 locked = 0;
438 } else if (oops_in_progress) {
439 locked = spin_trylock(&port->lock);
440 } else
441 spin_lock(&port->lock);
442
443 while (n > 0) {
444 unsigned long ra = __pa(con_write_page);
445 unsigned long page_bytes;
446 unsigned int cpy = fill_con_write_page(s, n,
447 &page_bytes);
448
449 n -= cpy;
450 s += cpy;
451 while (page_bytes > 0) {
452 unsigned long written;
453 int limit = 1000000;
454
455 while (limit--) {
456 unsigned long stat;
457
458 stat = sun4v_con_write(ra, page_bytes,
459 &written);
460 if (stat == HV_EOK)
461 break;
462 udelay(1);
463 }
464 if (limit < 0)
465 break;
466 page_bytes -= written;
467 ra += written;
468 }
469 }
470
471 if (locked)
472 spin_unlock(&port->lock);
473 local_irq_restore(flags);
474}
475
476static inline void sunhv_console_putchar(struct uart_port *port, char c)
477{
478 int limit = 1000000;
479
480 while (limit-- > 0) {
481 long status = sun4v_con_putchar(c);
482 if (status == HV_EOK)
483 break;
484 udelay(1);
485 }
486}
487
488static void sunhv_console_write_bychar(struct console *con, const char *s, unsigned n)
489{
490 struct uart_port *port = sunhv_port;
491 unsigned long flags;
492 int i, locked = 1;
493
494 local_irq_save(flags);
495 if (port->sysrq) {
496 locked = 0;
497 } else if (oops_in_progress) {
498 locked = spin_trylock(&port->lock);
499 } else
500 spin_lock(&port->lock);
501
502 for (i = 0; i < n; i++) {
503 if (*s == '\n')
504 sunhv_console_putchar(port, '\r');
505 sunhv_console_putchar(port, *s++);
506 }
507
508 if (locked)
509 spin_unlock(&port->lock);
510 local_irq_restore(flags);
511}
512
513static struct console sunhv_console = {
514 .name = "ttyHV",
515 .write = sunhv_console_write_bychar,
516 .device = uart_console_device,
517 .flags = CON_PRINTBUFFER,
518 .index = -1,
519 .data = &sunhv_reg,
520};
521
522static int __devinit hv_probe(struct platform_device *op, const struct of_device_id *match)
523{
524 struct uart_port *port;
525 unsigned long minor;
526 int err;
527
528 if (op->archdata.irqs[0] == 0xffffffff)
529 return -ENODEV;
530
531 port = kzalloc(sizeof(struct uart_port), GFP_KERNEL);
532 if (unlikely(!port))
533 return -ENOMEM;
534
535 minor = 1;
536 if (sun4v_hvapi_register(HV_GRP_CORE, 1, &minor) == 0 &&
537 minor >= 1) {
538 err = -ENOMEM;
539 con_write_page = kzalloc(PAGE_SIZE, GFP_KERNEL);
540 if (!con_write_page)
541 goto out_free_port;
542
543 con_read_page = kzalloc(PAGE_SIZE, GFP_KERNEL);
544 if (!con_read_page)
545 goto out_free_con_write_page;
546
547 sunhv_console.write = sunhv_console_write_paged;
548 sunhv_ops = &bywrite_ops;
549 }
550
551 sunhv_port = port;
552
553 port->line = 0;
554 port->ops = &sunhv_pops;
555 port->type = PORT_SUNHV;
556 port->uartclk = ( 29491200 / 16 ); /* arbitrary */
557
558 port->membase = (unsigned char __iomem *) __pa(port);
559
560 port->irq = op->archdata.irqs[0];
561
562 port->dev = &op->dev;
563
564 err = sunserial_register_minors(&sunhv_reg, 1);
565 if (err)
566 goto out_free_con_read_page;
567
568 sunserial_console_match(&sunhv_console, op->dev.of_node,
569 &sunhv_reg, port->line, false);
570
571 err = uart_add_one_port(&sunhv_reg, port);
572 if (err)
573 goto out_unregister_driver;
574
575 err = request_irq(port->irq, sunhv_interrupt, 0, "hvcons", port);
576 if (err)
577 goto out_remove_port;
578
579 dev_set_drvdata(&op->dev, port);
580
581 return 0;
582
583out_remove_port:
584 uart_remove_one_port(&sunhv_reg, port);
585
586out_unregister_driver:
587 sunserial_unregister_minors(&sunhv_reg, 1);
588
589out_free_con_read_page:
590 kfree(con_read_page);
591
592out_free_con_write_page:
593 kfree(con_write_page);
594
595out_free_port:
596 kfree(port);
597 sunhv_port = NULL;
598 return err;
599}
600
601static int __devexit hv_remove(struct platform_device *dev)
602{
603 struct uart_port *port = dev_get_drvdata(&dev->dev);
604
605 free_irq(port->irq, port);
606
607 uart_remove_one_port(&sunhv_reg, port);
608
609 sunserial_unregister_minors(&sunhv_reg, 1);
610
611 kfree(port);
612 sunhv_port = NULL;
613
614 dev_set_drvdata(&dev->dev, NULL);
615
616 return 0;
617}
618
619static const struct of_device_id hv_match[] = {
620 {
621 .name = "console",
622 .compatible = "qcn",
623 },
624 {
625 .name = "console",
626 .compatible = "SUNW,sun4v-console",
627 },
628 {},
629};
630MODULE_DEVICE_TABLE(of, hv_match);
631
632static struct of_platform_driver hv_driver = {
633 .driver = {
634 .name = "hv",
635 .owner = THIS_MODULE,
636 .of_match_table = hv_match,
637 },
638 .probe = hv_probe,
639 .remove = __devexit_p(hv_remove),
640};
641
642static int __init sunhv_init(void)
643{
644 if (tlb_type != hypervisor)
645 return -ENODEV;
646
647 return of_register_platform_driver(&hv_driver);
648}
649
650static void __exit sunhv_exit(void)
651{
652 of_unregister_platform_driver(&hv_driver);
653}
654
655module_init(sunhv_init);
656module_exit(sunhv_exit);
657
658MODULE_AUTHOR("David S. Miller");
659MODULE_DESCRIPTION("SUN4V Hypervisor console driver");
660MODULE_VERSION("2.0");
661MODULE_LICENSE("GPL");
diff --git a/drivers/serial/sunsab.c b/drivers/serial/sunsab.c
deleted file mode 100644
index 5b246b18f42f..000000000000
--- a/drivers/serial/sunsab.c
+++ /dev/null
@@ -1,1152 +0,0 @@
1/* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC.
2 *
3 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
4 * Copyright (C) 2002, 2006 David S. Miller (davem@davemloft.net)
5 *
6 * Rewrote buffer handling to use CIRC(Circular Buffer) macros.
7 * Maxim Krasnyanskiy <maxk@qualcomm.com>
8 *
9 * Fixed to use tty_get_baud_rate, and to allow for arbitrary baud
10 * rates to be programmed into the UART. Also eliminated a lot of
11 * duplicated code in the console setup.
12 * Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
13 *
14 * Ported to new 2.5.x UART layer.
15 * David S. Miller <davem@davemloft.net>
16 */
17
18#include <linux/module.h>
19#include <linux/kernel.h>
20#include <linux/errno.h>
21#include <linux/tty.h>
22#include <linux/tty_flip.h>
23#include <linux/major.h>
24#include <linux/string.h>
25#include <linux/ptrace.h>
26#include <linux/ioport.h>
27#include <linux/circ_buf.h>
28#include <linux/serial.h>
29#include <linux/sysrq.h>
30#include <linux/console.h>
31#include <linux/spinlock.h>
32#include <linux/slab.h>
33#include <linux/delay.h>
34#include <linux/init.h>
35#include <linux/of_device.h>
36
37#include <asm/io.h>
38#include <asm/irq.h>
39#include <asm/prom.h>
40
41#if defined(CONFIG_SERIAL_SUNSAB_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
42#define SUPPORT_SYSRQ
43#endif
44
45#include <linux/serial_core.h>
46
47#include "suncore.h"
48#include "sunsab.h"
49
50struct uart_sunsab_port {
51 struct uart_port port; /* Generic UART port */
52 union sab82532_async_regs __iomem *regs; /* Chip registers */
53 unsigned long irqflags; /* IRQ state flags */
54 int dsr; /* Current DSR state */
55 unsigned int cec_timeout; /* Chip poll timeout... */
56 unsigned int tec_timeout; /* likewise */
57 unsigned char interrupt_mask0;/* ISR0 masking */
58 unsigned char interrupt_mask1;/* ISR1 masking */
59 unsigned char pvr_dtr_bit; /* Which PVR bit is DTR */
60 unsigned char pvr_dsr_bit; /* Which PVR bit is DSR */
61 unsigned int gis_shift;
62 int type; /* SAB82532 version */
63
64 /* Setting configuration bits while the transmitter is active
65 * can cause garbage characters to get emitted by the chip.
66 * Therefore, we cache such writes here and do the real register
67 * write the next time the transmitter becomes idle.
68 */
69 unsigned int cached_ebrg;
70 unsigned char cached_mode;
71 unsigned char cached_pvr;
72 unsigned char cached_dafo;
73};
74
75/*
76 * This assumes you have a 29.4912 MHz clock for your UART.
77 */
78#define SAB_BASE_BAUD ( 29491200 / 16 )
79
80static char *sab82532_version[16] = {
81 "V1.0", "V2.0", "V3.2", "V(0x03)",
82 "V(0x04)", "V(0x05)", "V(0x06)", "V(0x07)",
83 "V(0x08)", "V(0x09)", "V(0x0a)", "V(0x0b)",
84 "V(0x0c)", "V(0x0d)", "V(0x0e)", "V(0x0f)"
85};
86
87#define SAB82532_MAX_TEC_TIMEOUT 200000 /* 1 character time (at 50 baud) */
88#define SAB82532_MAX_CEC_TIMEOUT 50000 /* 2.5 TX CLKs (at 50 baud) */
89
90#define SAB82532_RECV_FIFO_SIZE 32 /* Standard async fifo sizes */
91#define SAB82532_XMIT_FIFO_SIZE 32
92
93static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up)
94{
95 int timeout = up->tec_timeout;
96
97 while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout)
98 udelay(1);
99}
100
101static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up)
102{
103 int timeout = up->cec_timeout;
104
105 while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout)
106 udelay(1);
107}
108
109static struct tty_struct *
110receive_chars(struct uart_sunsab_port *up,
111 union sab82532_irq_status *stat)
112{
113 struct tty_struct *tty = NULL;
114 unsigned char buf[32];
115 int saw_console_brk = 0;
116 int free_fifo = 0;
117 int count = 0;
118 int i;
119
120 if (up->port.state != NULL) /* Unopened serial console */
121 tty = up->port.state->port.tty;
122
123 /* Read number of BYTES (Character + Status) available. */
124 if (stat->sreg.isr0 & SAB82532_ISR0_RPF) {
125 count = SAB82532_RECV_FIFO_SIZE;
126 free_fifo++;
127 }
128
129 if (stat->sreg.isr0 & SAB82532_ISR0_TCD) {
130 count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1);
131 free_fifo++;
132 }
133
134 /* Issue a FIFO read command in case we where idle. */
135 if (stat->sreg.isr0 & SAB82532_ISR0_TIME) {
136 sunsab_cec_wait(up);
137 writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr);
138 return tty;
139 }
140
141 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
142 free_fifo++;
143
144 /* Read the FIFO. */
145 for (i = 0; i < count; i++)
146 buf[i] = readb(&up->regs->r.rfifo[i]);
147
148 /* Issue Receive Message Complete command. */
149 if (free_fifo) {
150 sunsab_cec_wait(up);
151 writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr);
152 }
153
154 /* Count may be zero for BRK, so we check for it here */
155 if ((stat->sreg.isr1 & SAB82532_ISR1_BRK) &&
156 (up->port.line == up->port.cons->index))
157 saw_console_brk = 1;
158
159 for (i = 0; i < count; i++) {
160 unsigned char ch = buf[i], flag;
161
162 if (tty == NULL) {
163 uart_handle_sysrq_char(&up->port, ch);
164 continue;
165 }
166
167 flag = TTY_NORMAL;
168 up->port.icount.rx++;
169
170 if (unlikely(stat->sreg.isr0 & (SAB82532_ISR0_PERR |
171 SAB82532_ISR0_FERR |
172 SAB82532_ISR0_RFO)) ||
173 unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
174 /*
175 * For statistics only
176 */
177 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
178 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
179 SAB82532_ISR0_FERR);
180 up->port.icount.brk++;
181 /*
182 * We do the SysRQ and SAK checking
183 * here because otherwise the break
184 * may get masked by ignore_status_mask
185 * or read_status_mask.
186 */
187 if (uart_handle_break(&up->port))
188 continue;
189 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
190 up->port.icount.parity++;
191 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
192 up->port.icount.frame++;
193 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
194 up->port.icount.overrun++;
195
196 /*
197 * Mask off conditions which should be ingored.
198 */
199 stat->sreg.isr0 &= (up->port.read_status_mask & 0xff);
200 stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff);
201
202 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
203 flag = TTY_BREAK;
204 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
205 flag = TTY_PARITY;
206 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
207 flag = TTY_FRAME;
208 }
209
210 if (uart_handle_sysrq_char(&up->port, ch))
211 continue;
212
213 if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 &&
214 (stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0)
215 tty_insert_flip_char(tty, ch, flag);
216 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
217 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
218 }
219
220 if (saw_console_brk)
221 sun_do_break();
222
223 return tty;
224}
225
226static void sunsab_stop_tx(struct uart_port *);
227static void sunsab_tx_idle(struct uart_sunsab_port *);
228
229static void transmit_chars(struct uart_sunsab_port *up,
230 union sab82532_irq_status *stat)
231{
232 struct circ_buf *xmit = &up->port.state->xmit;
233 int i;
234
235 if (stat->sreg.isr1 & SAB82532_ISR1_ALLS) {
236 up->interrupt_mask1 |= SAB82532_IMR1_ALLS;
237 writeb(up->interrupt_mask1, &up->regs->w.imr1);
238 set_bit(SAB82532_ALLS, &up->irqflags);
239 }
240
241#if 0 /* bde@nwlink.com says this check causes problems */
242 if (!(stat->sreg.isr1 & SAB82532_ISR1_XPR))
243 return;
244#endif
245
246 if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW))
247 return;
248
249 set_bit(SAB82532_XPR, &up->irqflags);
250 sunsab_tx_idle(up);
251
252 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
253 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
254 writeb(up->interrupt_mask1, &up->regs->w.imr1);
255 return;
256 }
257
258 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
259 writeb(up->interrupt_mask1, &up->regs->w.imr1);
260 clear_bit(SAB82532_ALLS, &up->irqflags);
261
262 /* Stuff 32 bytes into Transmit FIFO. */
263 clear_bit(SAB82532_XPR, &up->irqflags);
264 for (i = 0; i < up->port.fifosize; i++) {
265 writeb(xmit->buf[xmit->tail],
266 &up->regs->w.xfifo[i]);
267 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
268 up->port.icount.tx++;
269 if (uart_circ_empty(xmit))
270 break;
271 }
272
273 /* Issue a Transmit Frame command. */
274 sunsab_cec_wait(up);
275 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
276
277 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
278 uart_write_wakeup(&up->port);
279
280 if (uart_circ_empty(xmit))
281 sunsab_stop_tx(&up->port);
282}
283
284static void check_status(struct uart_sunsab_port *up,
285 union sab82532_irq_status *stat)
286{
287 if (stat->sreg.isr0 & SAB82532_ISR0_CDSC)
288 uart_handle_dcd_change(&up->port,
289 !(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD));
290
291 if (stat->sreg.isr1 & SAB82532_ISR1_CSC)
292 uart_handle_cts_change(&up->port,
293 (readb(&up->regs->r.star) & SAB82532_STAR_CTS));
294
295 if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) {
296 up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1;
297 up->port.icount.dsr++;
298 }
299
300 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
301}
302
303static irqreturn_t sunsab_interrupt(int irq, void *dev_id)
304{
305 struct uart_sunsab_port *up = dev_id;
306 struct tty_struct *tty;
307 union sab82532_irq_status status;
308 unsigned long flags;
309 unsigned char gis;
310
311 spin_lock_irqsave(&up->port.lock, flags);
312
313 status.stat = 0;
314 gis = readb(&up->regs->r.gis) >> up->gis_shift;
315 if (gis & 1)
316 status.sreg.isr0 = readb(&up->regs->r.isr0);
317 if (gis & 2)
318 status.sreg.isr1 = readb(&up->regs->r.isr1);
319
320 tty = NULL;
321 if (status.stat) {
322 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
323 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
324 (status.sreg.isr1 & SAB82532_ISR1_BRK))
325 tty = receive_chars(up, &status);
326 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
327 (status.sreg.isr1 & SAB82532_ISR1_CSC))
328 check_status(up, &status);
329 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
330 transmit_chars(up, &status);
331 }
332
333 spin_unlock_irqrestore(&up->port.lock, flags);
334
335 if (tty)
336 tty_flip_buffer_push(tty);
337
338 return IRQ_HANDLED;
339}
340
341/* port->lock is not held. */
342static unsigned int sunsab_tx_empty(struct uart_port *port)
343{
344 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
345 int ret;
346
347 /* Do not need a lock for a state test like this. */
348 if (test_bit(SAB82532_ALLS, &up->irqflags))
349 ret = TIOCSER_TEMT;
350 else
351 ret = 0;
352
353 return ret;
354}
355
356/* port->lock held by caller. */
357static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl)
358{
359 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
360
361 if (mctrl & TIOCM_RTS) {
362 up->cached_mode &= ~SAB82532_MODE_FRTS;
363 up->cached_mode |= SAB82532_MODE_RTS;
364 } else {
365 up->cached_mode |= (SAB82532_MODE_FRTS |
366 SAB82532_MODE_RTS);
367 }
368 if (mctrl & TIOCM_DTR) {
369 up->cached_pvr &= ~(up->pvr_dtr_bit);
370 } else {
371 up->cached_pvr |= up->pvr_dtr_bit;
372 }
373
374 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
375 if (test_bit(SAB82532_XPR, &up->irqflags))
376 sunsab_tx_idle(up);
377}
378
379/* port->lock is held by caller and interrupts are disabled. */
380static unsigned int sunsab_get_mctrl(struct uart_port *port)
381{
382 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
383 unsigned char val;
384 unsigned int result;
385
386 result = 0;
387
388 val = readb(&up->regs->r.pvr);
389 result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR;
390
391 val = readb(&up->regs->r.vstr);
392 result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR;
393
394 val = readb(&up->regs->r.star);
395 result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0;
396
397 return result;
398}
399
400/* port->lock held by caller. */
401static void sunsab_stop_tx(struct uart_port *port)
402{
403 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
404
405 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
406 writeb(up->interrupt_mask1, &up->regs->w.imr1);
407}
408
409/* port->lock held by caller. */
410static void sunsab_tx_idle(struct uart_sunsab_port *up)
411{
412 if (test_bit(SAB82532_REGS_PENDING, &up->irqflags)) {
413 u8 tmp;
414
415 clear_bit(SAB82532_REGS_PENDING, &up->irqflags);
416 writeb(up->cached_mode, &up->regs->rw.mode);
417 writeb(up->cached_pvr, &up->regs->rw.pvr);
418 writeb(up->cached_dafo, &up->regs->w.dafo);
419
420 writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr);
421 tmp = readb(&up->regs->rw.ccr2);
422 tmp &= ~0xc0;
423 tmp |= (up->cached_ebrg >> 2) & 0xc0;
424 writeb(tmp, &up->regs->rw.ccr2);
425 }
426}
427
428/* port->lock held by caller. */
429static void sunsab_start_tx(struct uart_port *port)
430{
431 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
432 struct circ_buf *xmit = &up->port.state->xmit;
433 int i;
434
435 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
436 writeb(up->interrupt_mask1, &up->regs->w.imr1);
437
438 if (!test_bit(SAB82532_XPR, &up->irqflags))
439 return;
440
441 clear_bit(SAB82532_ALLS, &up->irqflags);
442 clear_bit(SAB82532_XPR, &up->irqflags);
443
444 for (i = 0; i < up->port.fifosize; i++) {
445 writeb(xmit->buf[xmit->tail],
446 &up->regs->w.xfifo[i]);
447 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
448 up->port.icount.tx++;
449 if (uart_circ_empty(xmit))
450 break;
451 }
452
453 /* Issue a Transmit Frame command. */
454 sunsab_cec_wait(up);
455 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
456}
457
458/* port->lock is not held. */
459static void sunsab_send_xchar(struct uart_port *port, char ch)
460{
461 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
462 unsigned long flags;
463
464 spin_lock_irqsave(&up->port.lock, flags);
465
466 sunsab_tec_wait(up);
467 writeb(ch, &up->regs->w.tic);
468
469 spin_unlock_irqrestore(&up->port.lock, flags);
470}
471
472/* port->lock held by caller. */
473static void sunsab_stop_rx(struct uart_port *port)
474{
475 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
476
477 up->interrupt_mask0 |= SAB82532_IMR0_TCD;
478 writeb(up->interrupt_mask1, &up->regs->w.imr0);
479}
480
481/* port->lock held by caller. */
482static void sunsab_enable_ms(struct uart_port *port)
483{
484 /* For now we always receive these interrupts. */
485}
486
487/* port->lock is not held. */
488static void sunsab_break_ctl(struct uart_port *port, int break_state)
489{
490 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
491 unsigned long flags;
492 unsigned char val;
493
494 spin_lock_irqsave(&up->port.lock, flags);
495
496 val = up->cached_dafo;
497 if (break_state)
498 val |= SAB82532_DAFO_XBRK;
499 else
500 val &= ~SAB82532_DAFO_XBRK;
501 up->cached_dafo = val;
502
503 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
504 if (test_bit(SAB82532_XPR, &up->irqflags))
505 sunsab_tx_idle(up);
506
507 spin_unlock_irqrestore(&up->port.lock, flags);
508}
509
510/* port->lock is not held. */
511static int sunsab_startup(struct uart_port *port)
512{
513 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
514 unsigned long flags;
515 unsigned char tmp;
516 int err = request_irq(up->port.irq, sunsab_interrupt,
517 IRQF_SHARED, "sab", up);
518 if (err)
519 return err;
520
521 spin_lock_irqsave(&up->port.lock, flags);
522
523 /*
524 * Wait for any commands or immediate characters
525 */
526 sunsab_cec_wait(up);
527 sunsab_tec_wait(up);
528
529 /*
530 * Clear the FIFO buffers.
531 */
532 writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr);
533 sunsab_cec_wait(up);
534 writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr);
535
536 /*
537 * Clear the interrupt registers.
538 */
539 (void) readb(&up->regs->r.isr0);
540 (void) readb(&up->regs->r.isr1);
541
542 /*
543 * Now, initialize the UART
544 */
545 writeb(0, &up->regs->w.ccr0); /* power-down */
546 writeb(SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ |
547 SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0);
548 writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1);
549 writeb(SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL |
550 SAB82532_CCR2_TOE, &up->regs->w.ccr2);
551 writeb(0, &up->regs->w.ccr3);
552 writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4);
553 up->cached_mode = (SAB82532_MODE_RTS | SAB82532_MODE_FCTS |
554 SAB82532_MODE_RAC);
555 writeb(up->cached_mode, &up->regs->w.mode);
556 writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc);
557
558 tmp = readb(&up->regs->rw.ccr0);
559 tmp |= SAB82532_CCR0_PU; /* power-up */
560 writeb(tmp, &up->regs->rw.ccr0);
561
562 /*
563 * Finally, enable interrupts
564 */
565 up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
566 SAB82532_IMR0_PLLA);
567 writeb(up->interrupt_mask0, &up->regs->w.imr0);
568 up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
569 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
570 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
571 SAB82532_IMR1_XPR);
572 writeb(up->interrupt_mask1, &up->regs->w.imr1);
573 set_bit(SAB82532_ALLS, &up->irqflags);
574 set_bit(SAB82532_XPR, &up->irqflags);
575
576 spin_unlock_irqrestore(&up->port.lock, flags);
577
578 return 0;
579}
580
581/* port->lock is not held. */
582static void sunsab_shutdown(struct uart_port *port)
583{
584 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
585 unsigned long flags;
586
587 spin_lock_irqsave(&up->port.lock, flags);
588
589 /* Disable Interrupts */
590 up->interrupt_mask0 = 0xff;
591 writeb(up->interrupt_mask0, &up->regs->w.imr0);
592 up->interrupt_mask1 = 0xff;
593 writeb(up->interrupt_mask1, &up->regs->w.imr1);
594
595 /* Disable break condition */
596 up->cached_dafo = readb(&up->regs->rw.dafo);
597 up->cached_dafo &= ~SAB82532_DAFO_XBRK;
598 writeb(up->cached_dafo, &up->regs->rw.dafo);
599
600 /* Disable Receiver */
601 up->cached_mode &= ~SAB82532_MODE_RAC;
602 writeb(up->cached_mode, &up->regs->rw.mode);
603
604 /*
605 * XXX FIXME
606 *
607 * If the chip is powered down here the system hangs/crashes during
608 * reboot or shutdown. This needs to be investigated further,
609 * similar behaviour occurs in 2.4 when the driver is configured
610 * as a module only. One hint may be that data is sometimes
611 * transmitted at 9600 baud during shutdown (regardless of the
612 * speed the chip was configured for when the port was open).
613 */
614#if 0
615 /* Power Down */
616 tmp = readb(&up->regs->rw.ccr0);
617 tmp &= ~SAB82532_CCR0_PU;
618 writeb(tmp, &up->regs->rw.ccr0);
619#endif
620
621 spin_unlock_irqrestore(&up->port.lock, flags);
622 free_irq(up->port.irq, up);
623}
624
625/*
626 * This is used to figure out the divisor speeds.
627 *
628 * The formula is: Baud = SAB_BASE_BAUD / ((N + 1) * (1 << M)),
629 *
630 * with 0 <= N < 64 and 0 <= M < 16
631 */
632
633static void calc_ebrg(int baud, int *n_ret, int *m_ret)
634{
635 int n, m;
636
637 if (baud == 0) {
638 *n_ret = 0;
639 *m_ret = 0;
640 return;
641 }
642
643 /*
644 * We scale numbers by 10 so that we get better accuracy
645 * without having to use floating point. Here we increment m
646 * until n is within the valid range.
647 */
648 n = (SAB_BASE_BAUD * 10) / baud;
649 m = 0;
650 while (n >= 640) {
651 n = n / 2;
652 m++;
653 }
654 n = (n+5) / 10;
655 /*
656 * We try very hard to avoid speeds with M == 0 since they may
657 * not work correctly for XTAL frequences above 10 MHz.
658 */
659 if ((m == 0) && ((n & 1) == 0)) {
660 n = n / 2;
661 m++;
662 }
663 *n_ret = n - 1;
664 *m_ret = m;
665}
666
667/* Internal routine, port->lock is held and local interrupts are disabled. */
668static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag,
669 unsigned int iflag, unsigned int baud,
670 unsigned int quot)
671{
672 unsigned char dafo;
673 int bits, n, m;
674
675 /* Byte size and parity */
676 switch (cflag & CSIZE) {
677 case CS5: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
678 case CS6: dafo = SAB82532_DAFO_CHL6; bits = 8; break;
679 case CS7: dafo = SAB82532_DAFO_CHL7; bits = 9; break;
680 case CS8: dafo = SAB82532_DAFO_CHL8; bits = 10; break;
681 /* Never happens, but GCC is too dumb to figure it out */
682 default: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
683 }
684
685 if (cflag & CSTOPB) {
686 dafo |= SAB82532_DAFO_STOP;
687 bits++;
688 }
689
690 if (cflag & PARENB) {
691 dafo |= SAB82532_DAFO_PARE;
692 bits++;
693 }
694
695 if (cflag & PARODD) {
696 dafo |= SAB82532_DAFO_PAR_ODD;
697 } else {
698 dafo |= SAB82532_DAFO_PAR_EVEN;
699 }
700 up->cached_dafo = dafo;
701
702 calc_ebrg(baud, &n, &m);
703
704 up->cached_ebrg = n | (m << 6);
705
706 up->tec_timeout = (10 * 1000000) / baud;
707 up->cec_timeout = up->tec_timeout >> 2;
708
709 /* CTS flow control flags */
710 /* We encode read_status_mask and ignore_status_mask like so:
711 *
712 * ---------------------
713 * | ... | ISR1 | ISR0 |
714 * ---------------------
715 * .. 15 8 7 0
716 */
717
718 up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
719 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF |
720 SAB82532_ISR0_CDSC);
721 up->port.read_status_mask |= (SAB82532_ISR1_CSC |
722 SAB82532_ISR1_ALLS |
723 SAB82532_ISR1_XPR) << 8;
724 if (iflag & INPCK)
725 up->port.read_status_mask |= (SAB82532_ISR0_PERR |
726 SAB82532_ISR0_FERR);
727 if (iflag & (BRKINT | PARMRK))
728 up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8);
729
730 /*
731 * Characteres to ignore
732 */
733 up->port.ignore_status_mask = 0;
734 if (iflag & IGNPAR)
735 up->port.ignore_status_mask |= (SAB82532_ISR0_PERR |
736 SAB82532_ISR0_FERR);
737 if (iflag & IGNBRK) {
738 up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8);
739 /*
740 * If we're ignoring parity and break indicators,
741 * ignore overruns too (for real raw support).
742 */
743 if (iflag & IGNPAR)
744 up->port.ignore_status_mask |= SAB82532_ISR0_RFO;
745 }
746
747 /*
748 * ignore all characters if CREAD is not set
749 */
750 if ((cflag & CREAD) == 0)
751 up->port.ignore_status_mask |= (SAB82532_ISR0_RPF |
752 SAB82532_ISR0_TCD);
753
754 uart_update_timeout(&up->port, cflag,
755 (up->port.uartclk / (16 * quot)));
756
757 /* Now schedule a register update when the chip's
758 * transmitter is idle.
759 */
760 up->cached_mode |= SAB82532_MODE_RAC;
761 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
762 if (test_bit(SAB82532_XPR, &up->irqflags))
763 sunsab_tx_idle(up);
764}
765
766/* port->lock is not held. */
767static void sunsab_set_termios(struct uart_port *port, struct ktermios *termios,
768 struct ktermios *old)
769{
770 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
771 unsigned long flags;
772 unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
773 unsigned int quot = uart_get_divisor(port, baud);
774
775 spin_lock_irqsave(&up->port.lock, flags);
776 sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot);
777 spin_unlock_irqrestore(&up->port.lock, flags);
778}
779
780static const char *sunsab_type(struct uart_port *port)
781{
782 struct uart_sunsab_port *up = (void *)port;
783 static char buf[36];
784
785 sprintf(buf, "SAB82532 %s", sab82532_version[up->type]);
786 return buf;
787}
788
789static void sunsab_release_port(struct uart_port *port)
790{
791}
792
793static int sunsab_request_port(struct uart_port *port)
794{
795 return 0;
796}
797
798static void sunsab_config_port(struct uart_port *port, int flags)
799{
800}
801
802static int sunsab_verify_port(struct uart_port *port, struct serial_struct *ser)
803{
804 return -EINVAL;
805}
806
807static struct uart_ops sunsab_pops = {
808 .tx_empty = sunsab_tx_empty,
809 .set_mctrl = sunsab_set_mctrl,
810 .get_mctrl = sunsab_get_mctrl,
811 .stop_tx = sunsab_stop_tx,
812 .start_tx = sunsab_start_tx,
813 .send_xchar = sunsab_send_xchar,
814 .stop_rx = sunsab_stop_rx,
815 .enable_ms = sunsab_enable_ms,
816 .break_ctl = sunsab_break_ctl,
817 .startup = sunsab_startup,
818 .shutdown = sunsab_shutdown,
819 .set_termios = sunsab_set_termios,
820 .type = sunsab_type,
821 .release_port = sunsab_release_port,
822 .request_port = sunsab_request_port,
823 .config_port = sunsab_config_port,
824 .verify_port = sunsab_verify_port,
825};
826
827static struct uart_driver sunsab_reg = {
828 .owner = THIS_MODULE,
829 .driver_name = "sunsab",
830 .dev_name = "ttyS",
831 .major = TTY_MAJOR,
832};
833
834static struct uart_sunsab_port *sunsab_ports;
835
836#ifdef CONFIG_SERIAL_SUNSAB_CONSOLE
837
838static void sunsab_console_putchar(struct uart_port *port, int c)
839{
840 struct uart_sunsab_port *up = (struct uart_sunsab_port *)port;
841
842 sunsab_tec_wait(up);
843 writeb(c, &up->regs->w.tic);
844}
845
846static void sunsab_console_write(struct console *con, const char *s, unsigned n)
847{
848 struct uart_sunsab_port *up = &sunsab_ports[con->index];
849 unsigned long flags;
850 int locked = 1;
851
852 local_irq_save(flags);
853 if (up->port.sysrq) {
854 locked = 0;
855 } else if (oops_in_progress) {
856 locked = spin_trylock(&up->port.lock);
857 } else
858 spin_lock(&up->port.lock);
859
860 uart_console_write(&up->port, s, n, sunsab_console_putchar);
861 sunsab_tec_wait(up);
862
863 if (locked)
864 spin_unlock(&up->port.lock);
865 local_irq_restore(flags);
866}
867
868static int sunsab_console_setup(struct console *con, char *options)
869{
870 struct uart_sunsab_port *up = &sunsab_ports[con->index];
871 unsigned long flags;
872 unsigned int baud, quot;
873
874 /*
875 * The console framework calls us for each and every port
876 * registered. Defer the console setup until the requested
877 * port has been properly discovered. A bit of a hack,
878 * though...
879 */
880 if (up->port.type != PORT_SUNSAB)
881 return -1;
882
883 printk("Console: ttyS%d (SAB82532)\n",
884 (sunsab_reg.minor - 64) + con->index);
885
886 sunserial_console_termios(con, up->port.dev->of_node);
887
888 switch (con->cflag & CBAUD) {
889 case B150: baud = 150; break;
890 case B300: baud = 300; break;
891 case B600: baud = 600; break;
892 case B1200: baud = 1200; break;
893 case B2400: baud = 2400; break;
894 case B4800: baud = 4800; break;
895 default: case B9600: baud = 9600; break;
896 case B19200: baud = 19200; break;
897 case B38400: baud = 38400; break;
898 case B57600: baud = 57600; break;
899 case B115200: baud = 115200; break;
900 case B230400: baud = 230400; break;
901 case B460800: baud = 460800; break;
902 };
903
904 /*
905 * Temporary fix.
906 */
907 spin_lock_init(&up->port.lock);
908
909 /*
910 * Initialize the hardware
911 */
912 sunsab_startup(&up->port);
913
914 spin_lock_irqsave(&up->port.lock, flags);
915
916 /*
917 * Finally, enable interrupts
918 */
919 up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
920 SAB82532_IMR0_PLLA | SAB82532_IMR0_CDSC;
921 writeb(up->interrupt_mask0, &up->regs->w.imr0);
922 up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
923 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
924 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
925 SAB82532_IMR1_XPR;
926 writeb(up->interrupt_mask1, &up->regs->w.imr1);
927
928 quot = uart_get_divisor(&up->port, baud);
929 sunsab_convert_to_sab(up, con->cflag, 0, baud, quot);
930 sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
931
932 spin_unlock_irqrestore(&up->port.lock, flags);
933
934 return 0;
935}
936
937static struct console sunsab_console = {
938 .name = "ttyS",
939 .write = sunsab_console_write,
940 .device = uart_console_device,
941 .setup = sunsab_console_setup,
942 .flags = CON_PRINTBUFFER,
943 .index = -1,
944 .data = &sunsab_reg,
945};
946
947static inline struct console *SUNSAB_CONSOLE(void)
948{
949 return &sunsab_console;
950}
951#else
952#define SUNSAB_CONSOLE() (NULL)
953#define sunsab_console_init() do { } while (0)
954#endif
955
956static int __devinit sunsab_init_one(struct uart_sunsab_port *up,
957 struct platform_device *op,
958 unsigned long offset,
959 int line)
960{
961 up->port.line = line;
962 up->port.dev = &op->dev;
963
964 up->port.mapbase = op->resource[0].start + offset;
965 up->port.membase = of_ioremap(&op->resource[0], offset,
966 sizeof(union sab82532_async_regs),
967 "sab");
968 if (!up->port.membase)
969 return -ENOMEM;
970 up->regs = (union sab82532_async_regs __iomem *) up->port.membase;
971
972 up->port.irq = op->archdata.irqs[0];
973
974 up->port.fifosize = SAB82532_XMIT_FIFO_SIZE;
975 up->port.iotype = UPIO_MEM;
976
977 writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc);
978
979 up->port.ops = &sunsab_pops;
980 up->port.type = PORT_SUNSAB;
981 up->port.uartclk = SAB_BASE_BAUD;
982
983 up->type = readb(&up->regs->r.vstr) & 0x0f;
984 writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr);
985 writeb(0xff, &up->regs->w.pim);
986 if ((up->port.line & 0x1) == 0) {
987 up->pvr_dsr_bit = (1 << 0);
988 up->pvr_dtr_bit = (1 << 1);
989 up->gis_shift = 2;
990 } else {
991 up->pvr_dsr_bit = (1 << 3);
992 up->pvr_dtr_bit = (1 << 2);
993 up->gis_shift = 0;
994 }
995 up->cached_pvr = (1 << 1) | (1 << 2) | (1 << 4);
996 writeb(up->cached_pvr, &up->regs->w.pvr);
997 up->cached_mode = readb(&up->regs->rw.mode);
998 up->cached_mode |= SAB82532_MODE_FRTS;
999 writeb(up->cached_mode, &up->regs->rw.mode);
1000 up->cached_mode |= SAB82532_MODE_RTS;
1001 writeb(up->cached_mode, &up->regs->rw.mode);
1002
1003 up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT;
1004 up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT;
1005
1006 return 0;
1007}
1008
1009static int __devinit sab_probe(struct platform_device *op, const struct of_device_id *match)
1010{
1011 static int inst;
1012 struct uart_sunsab_port *up;
1013 int err;
1014
1015 up = &sunsab_ports[inst * 2];
1016
1017 err = sunsab_init_one(&up[0], op,
1018 0,
1019 (inst * 2) + 0);
1020 if (err)
1021 goto out;
1022
1023 err = sunsab_init_one(&up[1], op,
1024 sizeof(union sab82532_async_regs),
1025 (inst * 2) + 1);
1026 if (err)
1027 goto out1;
1028
1029 sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,
1030 &sunsab_reg, up[0].port.line,
1031 false);
1032
1033 sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,
1034 &sunsab_reg, up[1].port.line,
1035 false);
1036
1037 err = uart_add_one_port(&sunsab_reg, &up[0].port);
1038 if (err)
1039 goto out2;
1040
1041 err = uart_add_one_port(&sunsab_reg, &up[1].port);
1042 if (err)
1043 goto out3;
1044
1045 dev_set_drvdata(&op->dev, &up[0]);
1046
1047 inst++;
1048
1049 return 0;
1050
1051out3:
1052 uart_remove_one_port(&sunsab_reg, &up[0].port);
1053out2:
1054 of_iounmap(&op->resource[0],
1055 up[1].port.membase,
1056 sizeof(union sab82532_async_regs));
1057out1:
1058 of_iounmap(&op->resource[0],
1059 up[0].port.membase,
1060 sizeof(union sab82532_async_regs));
1061out:
1062 return err;
1063}
1064
1065static int __devexit sab_remove(struct platform_device *op)
1066{
1067 struct uart_sunsab_port *up = dev_get_drvdata(&op->dev);
1068
1069 uart_remove_one_port(&sunsab_reg, &up[1].port);
1070 uart_remove_one_port(&sunsab_reg, &up[0].port);
1071 of_iounmap(&op->resource[0],
1072 up[1].port.membase,
1073 sizeof(union sab82532_async_regs));
1074 of_iounmap(&op->resource[0],
1075 up[0].port.membase,
1076 sizeof(union sab82532_async_regs));
1077
1078 dev_set_drvdata(&op->dev, NULL);
1079
1080 return 0;
1081}
1082
1083static const struct of_device_id sab_match[] = {
1084 {
1085 .name = "se",
1086 },
1087 {
1088 .name = "serial",
1089 .compatible = "sab82532",
1090 },
1091 {},
1092};
1093MODULE_DEVICE_TABLE(of, sab_match);
1094
1095static struct of_platform_driver sab_driver = {
1096 .driver = {
1097 .name = "sab",
1098 .owner = THIS_MODULE,
1099 .of_match_table = sab_match,
1100 },
1101 .probe = sab_probe,
1102 .remove = __devexit_p(sab_remove),
1103};
1104
1105static int __init sunsab_init(void)
1106{
1107 struct device_node *dp;
1108 int err;
1109 int num_channels = 0;
1110
1111 for_each_node_by_name(dp, "se")
1112 num_channels += 2;
1113 for_each_node_by_name(dp, "serial") {
1114 if (of_device_is_compatible(dp, "sab82532"))
1115 num_channels += 2;
1116 }
1117
1118 if (num_channels) {
1119 sunsab_ports = kzalloc(sizeof(struct uart_sunsab_port) *
1120 num_channels, GFP_KERNEL);
1121 if (!sunsab_ports)
1122 return -ENOMEM;
1123
1124 err = sunserial_register_minors(&sunsab_reg, num_channels);
1125 if (err) {
1126 kfree(sunsab_ports);
1127 sunsab_ports = NULL;
1128
1129 return err;
1130 }
1131 }
1132
1133 return of_register_platform_driver(&sab_driver);
1134}
1135
1136static void __exit sunsab_exit(void)
1137{
1138 of_unregister_platform_driver(&sab_driver);
1139 if (sunsab_reg.nr) {
1140 sunserial_unregister_minors(&sunsab_reg, sunsab_reg.nr);
1141 }
1142
1143 kfree(sunsab_ports);
1144 sunsab_ports = NULL;
1145}
1146
1147module_init(sunsab_init);
1148module_exit(sunsab_exit);
1149
1150MODULE_AUTHOR("Eddie C. Dost and David S. Miller");
1151MODULE_DESCRIPTION("Sun SAB82532 serial port driver");
1152MODULE_LICENSE("GPL");
diff --git a/drivers/serial/sunsab.h b/drivers/serial/sunsab.h
deleted file mode 100644
index b78e1f7b8050..000000000000
--- a/drivers/serial/sunsab.h
+++ /dev/null
@@ -1,322 +0,0 @@
1/* sunsab.h: Register Definitions for the Siemens SAB82532 DUSCC
2 *
3 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
4 */
5
6#ifndef _SUNSAB_H
7#define _SUNSAB_H
8
9struct sab82532_async_rd_regs {
10 u8 rfifo[0x20]; /* Receive FIFO */
11 u8 star; /* Status Register */
12 u8 __pad1;
13 u8 mode; /* Mode Register */
14 u8 timr; /* Timer Register */
15 u8 xon; /* XON Character */
16 u8 xoff; /* XOFF Character */
17 u8 tcr; /* Termination Character Register */
18 u8 dafo; /* Data Format */
19 u8 rfc; /* RFIFO Control Register */
20 u8 __pad2;
21 u8 rbcl; /* Receive Byte Count Low */
22 u8 rbch; /* Receive Byte Count High */
23 u8 ccr0; /* Channel Configuration Register 0 */
24 u8 ccr1; /* Channel Configuration Register 1 */
25 u8 ccr2; /* Channel Configuration Register 2 */
26 u8 ccr3; /* Channel Configuration Register 3 */
27 u8 __pad3[4];
28 u8 vstr; /* Version Status Register */
29 u8 __pad4[3];
30 u8 gis; /* Global Interrupt Status */
31 u8 ipc; /* Interrupt Port Configuration */
32 u8 isr0; /* Interrupt Status 0 */
33 u8 isr1; /* Interrupt Status 1 */
34 u8 pvr; /* Port Value Register */
35 u8 pis; /* Port Interrupt Status */
36 u8 pcr; /* Port Configuration Register */
37 u8 ccr4; /* Channel Configuration Register 4 */
38};
39
40struct sab82532_async_wr_regs {
41 u8 xfifo[0x20]; /* Transmit FIFO */
42 u8 cmdr; /* Command Register */
43 u8 __pad1;
44 u8 mode;
45 u8 timr;
46 u8 xon;
47 u8 xoff;
48 u8 tcr;
49 u8 dafo;
50 u8 rfc;
51 u8 __pad2;
52 u8 xbcl; /* Transmit Byte Count Low */
53 u8 xbch; /* Transmit Byte Count High */
54 u8 ccr0;
55 u8 ccr1;
56 u8 ccr2;
57 u8 ccr3;
58 u8 tsax; /* Time-Slot Assignment Reg. Transmit */
59 u8 tsar; /* Time-Slot Assignment Reg. Receive */
60 u8 xccr; /* Transmit Channel Capacity Register */
61 u8 rccr; /* Receive Channel Capacity Register */
62 u8 bgr; /* Baud Rate Generator Register */
63 u8 tic; /* Transmit Immediate Character */
64 u8 mxn; /* Mask XON Character */
65 u8 mxf; /* Mask XOFF Character */
66 u8 iva; /* Interrupt Vector Address */
67 u8 ipc;
68 u8 imr0; /* Interrupt Mask Register 0 */
69 u8 imr1; /* Interrupt Mask Register 1 */
70 u8 pvr;
71 u8 pim; /* Port Interrupt Mask */
72 u8 pcr;
73 u8 ccr4;
74};
75
76struct sab82532_async_rw_regs { /* Read/Write registers */
77 u8 __pad1[0x20];
78 u8 __pad2;
79 u8 __pad3;
80 u8 mode;
81 u8 timr;
82 u8 xon;
83 u8 xoff;
84 u8 tcr;
85 u8 dafo;
86 u8 rfc;
87 u8 __pad4;
88 u8 __pad5;
89 u8 __pad6;
90 u8 ccr0;
91 u8 ccr1;
92 u8 ccr2;
93 u8 ccr3;
94 u8 __pad7;
95 u8 __pad8;
96 u8 __pad9;
97 u8 __pad10;
98 u8 __pad11;
99 u8 __pad12;
100 u8 __pad13;
101 u8 __pad14;
102 u8 __pad15;
103 u8 ipc;
104 u8 __pad16;
105 u8 __pad17;
106 u8 pvr;
107 u8 __pad18;
108 u8 pcr;
109 u8 ccr4;
110};
111
112union sab82532_async_regs {
113 __volatile__ struct sab82532_async_rd_regs r;
114 __volatile__ struct sab82532_async_wr_regs w;
115 __volatile__ struct sab82532_async_rw_regs rw;
116};
117
118union sab82532_irq_status {
119 unsigned short stat;
120 struct {
121 unsigned char isr0;
122 unsigned char isr1;
123 } sreg;
124};
125
126/* irqflags bits */
127#define SAB82532_ALLS 0x00000001
128#define SAB82532_XPR 0x00000002
129#define SAB82532_REGS_PENDING 0x00000004
130
131/* RFIFO Status Byte */
132#define SAB82532_RSTAT_PE 0x80
133#define SAB82532_RSTAT_FE 0x40
134#define SAB82532_RSTAT_PARITY 0x01
135
136/* Status Register (STAR) */
137#define SAB82532_STAR_XDOV 0x80
138#define SAB82532_STAR_XFW 0x40
139#define SAB82532_STAR_RFNE 0x20
140#define SAB82532_STAR_FCS 0x10
141#define SAB82532_STAR_TEC 0x08
142#define SAB82532_STAR_CEC 0x04
143#define SAB82532_STAR_CTS 0x02
144
145/* Command Register (CMDR) */
146#define SAB82532_CMDR_RMC 0x80
147#define SAB82532_CMDR_RRES 0x40
148#define SAB82532_CMDR_RFRD 0x20
149#define SAB82532_CMDR_STI 0x10
150#define SAB82532_CMDR_XF 0x08
151#define SAB82532_CMDR_XRES 0x01
152
153/* Mode Register (MODE) */
154#define SAB82532_MODE_FRTS 0x40
155#define SAB82532_MODE_FCTS 0x20
156#define SAB82532_MODE_FLON 0x10
157#define SAB82532_MODE_RAC 0x08
158#define SAB82532_MODE_RTS 0x04
159#define SAB82532_MODE_TRS 0x02
160#define SAB82532_MODE_TLP 0x01
161
162/* Timer Register (TIMR) */
163#define SAB82532_TIMR_CNT_MASK 0xe0
164#define SAB82532_TIMR_VALUE_MASK 0x1f
165
166/* Data Format (DAFO) */
167#define SAB82532_DAFO_XBRK 0x40
168#define SAB82532_DAFO_STOP 0x20
169#define SAB82532_DAFO_PAR_SPACE 0x00
170#define SAB82532_DAFO_PAR_ODD 0x08
171#define SAB82532_DAFO_PAR_EVEN 0x10
172#define SAB82532_DAFO_PAR_MARK 0x18
173#define SAB82532_DAFO_PARE 0x04
174#define SAB82532_DAFO_CHL8 0x00
175#define SAB82532_DAFO_CHL7 0x01
176#define SAB82532_DAFO_CHL6 0x02
177#define SAB82532_DAFO_CHL5 0x03
178
179/* RFIFO Control Register (RFC) */
180#define SAB82532_RFC_DPS 0x40
181#define SAB82532_RFC_DXS 0x20
182#define SAB82532_RFC_RFDF 0x10
183#define SAB82532_RFC_RFTH_1 0x00
184#define SAB82532_RFC_RFTH_4 0x04
185#define SAB82532_RFC_RFTH_16 0x08
186#define SAB82532_RFC_RFTH_32 0x0c
187#define SAB82532_RFC_TCDE 0x01
188
189/* Received Byte Count High (RBCH) */
190#define SAB82532_RBCH_DMA 0x80
191#define SAB82532_RBCH_CAS 0x20
192
193/* Transmit Byte Count High (XBCH) */
194#define SAB82532_XBCH_DMA 0x80
195#define SAB82532_XBCH_CAS 0x20
196#define SAB82532_XBCH_XC 0x10
197
198/* Channel Configuration Register 0 (CCR0) */
199#define SAB82532_CCR0_PU 0x80
200#define SAB82532_CCR0_MCE 0x40
201#define SAB82532_CCR0_SC_NRZ 0x00
202#define SAB82532_CCR0_SC_NRZI 0x08
203#define SAB82532_CCR0_SC_FM0 0x10
204#define SAB82532_CCR0_SC_FM1 0x14
205#define SAB82532_CCR0_SC_MANCH 0x18
206#define SAB82532_CCR0_SM_HDLC 0x00
207#define SAB82532_CCR0_SM_SDLC_LOOP 0x01
208#define SAB82532_CCR0_SM_BISYNC 0x02
209#define SAB82532_CCR0_SM_ASYNC 0x03
210
211/* Channel Configuration Register 1 (CCR1) */
212#define SAB82532_CCR1_ODS 0x10
213#define SAB82532_CCR1_BCR 0x08
214#define SAB82532_CCR1_CM_MASK 0x07
215
216/* Channel Configuration Register 2 (CCR2) */
217#define SAB82532_CCR2_SOC1 0x80
218#define SAB82532_CCR2_SOC0 0x40
219#define SAB82532_CCR2_BR9 0x80
220#define SAB82532_CCR2_BR8 0x40
221#define SAB82532_CCR2_BDF 0x20
222#define SAB82532_CCR2_SSEL 0x10
223#define SAB82532_CCR2_XCS0 0x20
224#define SAB82532_CCR2_RCS0 0x10
225#define SAB82532_CCR2_TOE 0x08
226#define SAB82532_CCR2_RWX 0x04
227#define SAB82532_CCR2_DIV 0x01
228
229/* Channel Configuration Register 3 (CCR3) */
230#define SAB82532_CCR3_PSD 0x01
231
232/* Time Slot Assignment Register Transmit (TSAX) */
233#define SAB82532_TSAX_TSNX_MASK 0xfc
234#define SAB82532_TSAX_XCS2 0x02 /* see also CCR2 */
235#define SAB82532_TSAX_XCS1 0x01
236
237/* Time Slot Assignment Register Receive (TSAR) */
238#define SAB82532_TSAR_TSNR_MASK 0xfc
239#define SAB82532_TSAR_RCS2 0x02 /* see also CCR2 */
240#define SAB82532_TSAR_RCS1 0x01
241
242/* Version Status Register (VSTR) */
243#define SAB82532_VSTR_CD 0x80
244#define SAB82532_VSTR_DPLA 0x40
245#define SAB82532_VSTR_VN_MASK 0x0f
246#define SAB82532_VSTR_VN_1 0x00
247#define SAB82532_VSTR_VN_2 0x01
248#define SAB82532_VSTR_VN_3_2 0x02
249
250/* Global Interrupt Status Register (GIS) */
251#define SAB82532_GIS_PI 0x80
252#define SAB82532_GIS_ISA1 0x08
253#define SAB82532_GIS_ISA0 0x04
254#define SAB82532_GIS_ISB1 0x02
255#define SAB82532_GIS_ISB0 0x01
256
257/* Interrupt Vector Address (IVA) */
258#define SAB82532_IVA_MASK 0xf1
259
260/* Interrupt Port Configuration (IPC) */
261#define SAB82532_IPC_VIS 0x80
262#define SAB82532_IPC_SLA1 0x10
263#define SAB82532_IPC_SLA0 0x08
264#define SAB82532_IPC_CASM 0x04
265#define SAB82532_IPC_IC_OPEN_DRAIN 0x00
266#define SAB82532_IPC_IC_ACT_LOW 0x01
267#define SAB82532_IPC_IC_ACT_HIGH 0x03
268
269/* Interrupt Status Register 0 (ISR0) */
270#define SAB82532_ISR0_TCD 0x80
271#define SAB82532_ISR0_TIME 0x40
272#define SAB82532_ISR0_PERR 0x20
273#define SAB82532_ISR0_FERR 0x10
274#define SAB82532_ISR0_PLLA 0x08
275#define SAB82532_ISR0_CDSC 0x04
276#define SAB82532_ISR0_RFO 0x02
277#define SAB82532_ISR0_RPF 0x01
278
279/* Interrupt Status Register 1 (ISR1) */
280#define SAB82532_ISR1_BRK 0x80
281#define SAB82532_ISR1_BRKT 0x40
282#define SAB82532_ISR1_ALLS 0x20
283#define SAB82532_ISR1_XOFF 0x10
284#define SAB82532_ISR1_TIN 0x08
285#define SAB82532_ISR1_CSC 0x04
286#define SAB82532_ISR1_XON 0x02
287#define SAB82532_ISR1_XPR 0x01
288
289/* Interrupt Mask Register 0 (IMR0) */
290#define SAB82532_IMR0_TCD 0x80
291#define SAB82532_IMR0_TIME 0x40
292#define SAB82532_IMR0_PERR 0x20
293#define SAB82532_IMR0_FERR 0x10
294#define SAB82532_IMR0_PLLA 0x08
295#define SAB82532_IMR0_CDSC 0x04
296#define SAB82532_IMR0_RFO 0x02
297#define SAB82532_IMR0_RPF 0x01
298
299/* Interrupt Mask Register 1 (IMR1) */
300#define SAB82532_IMR1_BRK 0x80
301#define SAB82532_IMR1_BRKT 0x40
302#define SAB82532_IMR1_ALLS 0x20
303#define SAB82532_IMR1_XOFF 0x10
304#define SAB82532_IMR1_TIN 0x08
305#define SAB82532_IMR1_CSC 0x04
306#define SAB82532_IMR1_XON 0x02
307#define SAB82532_IMR1_XPR 0x01
308
309/* Port Interrupt Status Register (PIS) */
310#define SAB82532_PIS_SYNC_B 0x08
311#define SAB82532_PIS_DTR_B 0x04
312#define SAB82532_PIS_DTR_A 0x02
313#define SAB82532_PIS_SYNC_A 0x01
314
315/* Channel Configuration Register 4 (CCR4) */
316#define SAB82532_CCR4_MCK4 0x80
317#define SAB82532_CCR4_EBRG 0x40
318#define SAB82532_CCR4_TST1 0x20
319#define SAB82532_CCR4_ICD 0x10
320
321
322#endif /* !(_SUNSAB_H) */
diff --git a/drivers/serial/sunsu.c b/drivers/serial/sunsu.c
deleted file mode 100644
index 551ebfe3ccbb..000000000000
--- a/drivers/serial/sunsu.c
+++ /dev/null
@@ -1,1608 +0,0 @@
1/*
2 * su.c: Small serial driver for keyboard/mouse interface on sparc32/PCI
3 *
4 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1998-1999 Pete Zaitcev (zaitcev@yahoo.com)
6 *
7 * This is mainly a variation of 8250.c, credits go to authors mentioned
8 * therein. In fact this driver should be merged into the generic 8250.c
9 * infrastructure perhaps using a 8250_sparc.c module.
10 *
11 * Fixed to use tty_get_baud_rate().
12 * Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
13 *
14 * Converted to new 2.5.x UART layer.
15 * David S. Miller (davem@davemloft.net), 2002-Jul-29
16 */
17
18#include <linux/module.h>
19#include <linux/kernel.h>
20#include <linux/spinlock.h>
21#include <linux/errno.h>
22#include <linux/tty.h>
23#include <linux/tty_flip.h>
24#include <linux/major.h>
25#include <linux/string.h>
26#include <linux/ptrace.h>
27#include <linux/ioport.h>
28#include <linux/circ_buf.h>
29#include <linux/serial.h>
30#include <linux/sysrq.h>
31#include <linux/console.h>
32#include <linux/slab.h>
33#ifdef CONFIG_SERIO
34#include <linux/serio.h>
35#endif
36#include <linux/serial_reg.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/of_device.h>
40
41#include <asm/io.h>
42#include <asm/irq.h>
43#include <asm/prom.h>
44
45#if defined(CONFIG_SERIAL_SUNSU_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
46#define SUPPORT_SYSRQ
47#endif
48
49#include <linux/serial_core.h>
50
51#include "suncore.h"
52
53/* We are on a NS PC87303 clocked with 24.0 MHz, which results
54 * in a UART clock of 1.8462 MHz.
55 */
56#define SU_BASE_BAUD (1846200 / 16)
57
58enum su_type { SU_PORT_NONE, SU_PORT_MS, SU_PORT_KBD, SU_PORT_PORT };
59static char *su_typev[] = { "su(???)", "su(mouse)", "su(kbd)", "su(serial)" };
60
61/*
62 * Here we define the default xmit fifo size used for each type of UART.
63 */
64static const struct serial_uart_config uart_config[PORT_MAX_8250+1] = {
65 { "unknown", 1, 0 },
66 { "8250", 1, 0 },
67 { "16450", 1, 0 },
68 { "16550", 1, 0 },
69 { "16550A", 16, UART_CLEAR_FIFO | UART_USE_FIFO },
70 { "Cirrus", 1, 0 },
71 { "ST16650", 1, UART_CLEAR_FIFO | UART_STARTECH },
72 { "ST16650V2", 32, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH },
73 { "TI16750", 64, UART_CLEAR_FIFO | UART_USE_FIFO },
74 { "Startech", 1, 0 },
75 { "16C950/954", 128, UART_CLEAR_FIFO | UART_USE_FIFO },
76 { "ST16654", 64, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH },
77 { "XR16850", 128, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH },
78 { "RSA", 2048, UART_CLEAR_FIFO | UART_USE_FIFO }
79};
80
81struct uart_sunsu_port {
82 struct uart_port port;
83 unsigned char acr;
84 unsigned char ier;
85 unsigned short rev;
86 unsigned char lcr;
87 unsigned int lsr_break_flag;
88 unsigned int cflag;
89
90 /* Probing information. */
91 enum su_type su_type;
92 unsigned int type_probed; /* XXX Stupid */
93 unsigned long reg_size;
94
95#ifdef CONFIG_SERIO
96 struct serio serio;
97 int serio_open;
98#endif
99};
100
101static unsigned int serial_in(struct uart_sunsu_port *up, int offset)
102{
103 offset <<= up->port.regshift;
104
105 switch (up->port.iotype) {
106 case UPIO_HUB6:
107 outb(up->port.hub6 - 1 + offset, up->port.iobase);
108 return inb(up->port.iobase + 1);
109
110 case UPIO_MEM:
111 return readb(up->port.membase + offset);
112
113 default:
114 return inb(up->port.iobase + offset);
115 }
116}
117
118static void serial_out(struct uart_sunsu_port *up, int offset, int value)
119{
120#ifndef CONFIG_SPARC64
121 /*
122 * MrCoffee has weird schematics: IRQ4 & P10(?) pins of SuperIO are
123 * connected with a gate then go to SlavIO. When IRQ4 goes tristated
124 * gate outputs a logical one. Since we use level triggered interrupts
125 * we have lockup and watchdog reset. We cannot mask IRQ because
126 * keyboard shares IRQ with us (Word has it as Bob Smelik's design).
127 * This problem is similar to what Alpha people suffer, see serial.c.
128 */
129 if (offset == UART_MCR)
130 value |= UART_MCR_OUT2;
131#endif
132 offset <<= up->port.regshift;
133
134 switch (up->port.iotype) {
135 case UPIO_HUB6:
136 outb(up->port.hub6 - 1 + offset, up->port.iobase);
137 outb(value, up->port.iobase + 1);
138 break;
139
140 case UPIO_MEM:
141 writeb(value, up->port.membase + offset);
142 break;
143
144 default:
145 outb(value, up->port.iobase + offset);
146 }
147}
148
149/*
150 * We used to support using pause I/O for certain machines. We
151 * haven't supported this for a while, but just in case it's badly
152 * needed for certain old 386 machines, I've left these #define's
153 * in....
154 */
155#define serial_inp(up, offset) serial_in(up, offset)
156#define serial_outp(up, offset, value) serial_out(up, offset, value)
157
158
159/*
160 * For the 16C950
161 */
162static void serial_icr_write(struct uart_sunsu_port *up, int offset, int value)
163{
164 serial_out(up, UART_SCR, offset);
165 serial_out(up, UART_ICR, value);
166}
167
168#if 0 /* Unused currently */
169static unsigned int serial_icr_read(struct uart_sunsu_port *up, int offset)
170{
171 unsigned int value;
172
173 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
174 serial_out(up, UART_SCR, offset);
175 value = serial_in(up, UART_ICR);
176 serial_icr_write(up, UART_ACR, up->acr);
177
178 return value;
179}
180#endif
181
182#ifdef CONFIG_SERIAL_8250_RSA
183/*
184 * Attempts to turn on the RSA FIFO. Returns zero on failure.
185 * We set the port uart clock rate if we succeed.
186 */
187static int __enable_rsa(struct uart_sunsu_port *up)
188{
189 unsigned char mode;
190 int result;
191
192 mode = serial_inp(up, UART_RSA_MSR);
193 result = mode & UART_RSA_MSR_FIFO;
194
195 if (!result) {
196 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
197 mode = serial_inp(up, UART_RSA_MSR);
198 result = mode & UART_RSA_MSR_FIFO;
199 }
200
201 if (result)
202 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
203
204 return result;
205}
206
207static void enable_rsa(struct uart_sunsu_port *up)
208{
209 if (up->port.type == PORT_RSA) {
210 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
211 spin_lock_irq(&up->port.lock);
212 __enable_rsa(up);
213 spin_unlock_irq(&up->port.lock);
214 }
215 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
216 serial_outp(up, UART_RSA_FRR, 0);
217 }
218}
219
220/*
221 * Attempts to turn off the RSA FIFO. Returns zero on failure.
222 * It is unknown why interrupts were disabled in here. However,
223 * the caller is expected to preserve this behaviour by grabbing
224 * the spinlock before calling this function.
225 */
226static void disable_rsa(struct uart_sunsu_port *up)
227{
228 unsigned char mode;
229 int result;
230
231 if (up->port.type == PORT_RSA &&
232 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
233 spin_lock_irq(&up->port.lock);
234
235 mode = serial_inp(up, UART_RSA_MSR);
236 result = !(mode & UART_RSA_MSR_FIFO);
237
238 if (!result) {
239 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
240 mode = serial_inp(up, UART_RSA_MSR);
241 result = !(mode & UART_RSA_MSR_FIFO);
242 }
243
244 if (result)
245 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
246 spin_unlock_irq(&up->port.lock);
247 }
248}
249#endif /* CONFIG_SERIAL_8250_RSA */
250
251static inline void __stop_tx(struct uart_sunsu_port *p)
252{
253 if (p->ier & UART_IER_THRI) {
254 p->ier &= ~UART_IER_THRI;
255 serial_out(p, UART_IER, p->ier);
256 }
257}
258
259static void sunsu_stop_tx(struct uart_port *port)
260{
261 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
262
263 __stop_tx(up);
264
265 /*
266 * We really want to stop the transmitter from sending.
267 */
268 if (up->port.type == PORT_16C950) {
269 up->acr |= UART_ACR_TXDIS;
270 serial_icr_write(up, UART_ACR, up->acr);
271 }
272}
273
274static void sunsu_start_tx(struct uart_port *port)
275{
276 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
277
278 if (!(up->ier & UART_IER_THRI)) {
279 up->ier |= UART_IER_THRI;
280 serial_out(up, UART_IER, up->ier);
281 }
282
283 /*
284 * Re-enable the transmitter if we disabled it.
285 */
286 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
287 up->acr &= ~UART_ACR_TXDIS;
288 serial_icr_write(up, UART_ACR, up->acr);
289 }
290}
291
292static void sunsu_stop_rx(struct uart_port *port)
293{
294 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
295
296 up->ier &= ~UART_IER_RLSI;
297 up->port.read_status_mask &= ~UART_LSR_DR;
298 serial_out(up, UART_IER, up->ier);
299}
300
301static void sunsu_enable_ms(struct uart_port *port)
302{
303 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
304 unsigned long flags;
305
306 spin_lock_irqsave(&up->port.lock, flags);
307 up->ier |= UART_IER_MSI;
308 serial_out(up, UART_IER, up->ier);
309 spin_unlock_irqrestore(&up->port.lock, flags);
310}
311
312static struct tty_struct *
313receive_chars(struct uart_sunsu_port *up, unsigned char *status)
314{
315 struct tty_struct *tty = up->port.state->port.tty;
316 unsigned char ch, flag;
317 int max_count = 256;
318 int saw_console_brk = 0;
319
320 do {
321 ch = serial_inp(up, UART_RX);
322 flag = TTY_NORMAL;
323 up->port.icount.rx++;
324
325 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
326 UART_LSR_FE | UART_LSR_OE))) {
327 /*
328 * For statistics only
329 */
330 if (*status & UART_LSR_BI) {
331 *status &= ~(UART_LSR_FE | UART_LSR_PE);
332 up->port.icount.brk++;
333 if (up->port.cons != NULL &&
334 up->port.line == up->port.cons->index)
335 saw_console_brk = 1;
336 /*
337 * We do the SysRQ and SAK checking
338 * here because otherwise the break
339 * may get masked by ignore_status_mask
340 * or read_status_mask.
341 */
342 if (uart_handle_break(&up->port))
343 goto ignore_char;
344 } else if (*status & UART_LSR_PE)
345 up->port.icount.parity++;
346 else if (*status & UART_LSR_FE)
347 up->port.icount.frame++;
348 if (*status & UART_LSR_OE)
349 up->port.icount.overrun++;
350
351 /*
352 * Mask off conditions which should be ingored.
353 */
354 *status &= up->port.read_status_mask;
355
356 if (up->port.cons != NULL &&
357 up->port.line == up->port.cons->index) {
358 /* Recover the break flag from console xmit */
359 *status |= up->lsr_break_flag;
360 up->lsr_break_flag = 0;
361 }
362
363 if (*status & UART_LSR_BI) {
364 flag = TTY_BREAK;
365 } else if (*status & UART_LSR_PE)
366 flag = TTY_PARITY;
367 else if (*status & UART_LSR_FE)
368 flag = TTY_FRAME;
369 }
370 if (uart_handle_sysrq_char(&up->port, ch))
371 goto ignore_char;
372 if ((*status & up->port.ignore_status_mask) == 0)
373 tty_insert_flip_char(tty, ch, flag);
374 if (*status & UART_LSR_OE)
375 /*
376 * Overrun is special, since it's reported
377 * immediately, and doesn't affect the current
378 * character.
379 */
380 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
381 ignore_char:
382 *status = serial_inp(up, UART_LSR);
383 } while ((*status & UART_LSR_DR) && (max_count-- > 0));
384
385 if (saw_console_brk)
386 sun_do_break();
387
388 return tty;
389}
390
391static void transmit_chars(struct uart_sunsu_port *up)
392{
393 struct circ_buf *xmit = &up->port.state->xmit;
394 int count;
395
396 if (up->port.x_char) {
397 serial_outp(up, UART_TX, up->port.x_char);
398 up->port.icount.tx++;
399 up->port.x_char = 0;
400 return;
401 }
402 if (uart_tx_stopped(&up->port)) {
403 sunsu_stop_tx(&up->port);
404 return;
405 }
406 if (uart_circ_empty(xmit)) {
407 __stop_tx(up);
408 return;
409 }
410
411 count = up->port.fifosize;
412 do {
413 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
414 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
415 up->port.icount.tx++;
416 if (uart_circ_empty(xmit))
417 break;
418 } while (--count > 0);
419
420 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
421 uart_write_wakeup(&up->port);
422
423 if (uart_circ_empty(xmit))
424 __stop_tx(up);
425}
426
427static void check_modem_status(struct uart_sunsu_port *up)
428{
429 int status;
430
431 status = serial_in(up, UART_MSR);
432
433 if ((status & UART_MSR_ANY_DELTA) == 0)
434 return;
435
436 if (status & UART_MSR_TERI)
437 up->port.icount.rng++;
438 if (status & UART_MSR_DDSR)
439 up->port.icount.dsr++;
440 if (status & UART_MSR_DDCD)
441 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
442 if (status & UART_MSR_DCTS)
443 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
444
445 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
446}
447
448static irqreturn_t sunsu_serial_interrupt(int irq, void *dev_id)
449{
450 struct uart_sunsu_port *up = dev_id;
451 unsigned long flags;
452 unsigned char status;
453
454 spin_lock_irqsave(&up->port.lock, flags);
455
456 do {
457 struct tty_struct *tty;
458
459 status = serial_inp(up, UART_LSR);
460 tty = NULL;
461 if (status & UART_LSR_DR)
462 tty = receive_chars(up, &status);
463 check_modem_status(up);
464 if (status & UART_LSR_THRE)
465 transmit_chars(up);
466
467 spin_unlock_irqrestore(&up->port.lock, flags);
468
469 if (tty)
470 tty_flip_buffer_push(tty);
471
472 spin_lock_irqsave(&up->port.lock, flags);
473
474 } while (!(serial_in(up, UART_IIR) & UART_IIR_NO_INT));
475
476 spin_unlock_irqrestore(&up->port.lock, flags);
477
478 return IRQ_HANDLED;
479}
480
481/* Separate interrupt handling path for keyboard/mouse ports. */
482
483static void
484sunsu_change_speed(struct uart_port *port, unsigned int cflag,
485 unsigned int iflag, unsigned int quot);
486
487static void sunsu_change_mouse_baud(struct uart_sunsu_port *up)
488{
489 unsigned int cur_cflag = up->cflag;
490 int quot, new_baud;
491
492 up->cflag &= ~CBAUD;
493 up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud);
494
495 quot = up->port.uartclk / (16 * new_baud);
496
497 sunsu_change_speed(&up->port, up->cflag, 0, quot);
498}
499
500static void receive_kbd_ms_chars(struct uart_sunsu_port *up, int is_break)
501{
502 do {
503 unsigned char ch = serial_inp(up, UART_RX);
504
505 /* Stop-A is handled by drivers/char/keyboard.c now. */
506 if (up->su_type == SU_PORT_KBD) {
507#ifdef CONFIG_SERIO
508 serio_interrupt(&up->serio, ch, 0);
509#endif
510 } else if (up->su_type == SU_PORT_MS) {
511 int ret = suncore_mouse_baud_detection(ch, is_break);
512
513 switch (ret) {
514 case 2:
515 sunsu_change_mouse_baud(up);
516 /* fallthru */
517 case 1:
518 break;
519
520 case 0:
521#ifdef CONFIG_SERIO
522 serio_interrupt(&up->serio, ch, 0);
523#endif
524 break;
525 };
526 }
527 } while (serial_in(up, UART_LSR) & UART_LSR_DR);
528}
529
530static irqreturn_t sunsu_kbd_ms_interrupt(int irq, void *dev_id)
531{
532 struct uart_sunsu_port *up = dev_id;
533
534 if (!(serial_in(up, UART_IIR) & UART_IIR_NO_INT)) {
535 unsigned char status = serial_inp(up, UART_LSR);
536
537 if ((status & UART_LSR_DR) || (status & UART_LSR_BI))
538 receive_kbd_ms_chars(up, (status & UART_LSR_BI) != 0);
539 }
540
541 return IRQ_HANDLED;
542}
543
544static unsigned int sunsu_tx_empty(struct uart_port *port)
545{
546 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
547 unsigned long flags;
548 unsigned int ret;
549
550 spin_lock_irqsave(&up->port.lock, flags);
551 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
552 spin_unlock_irqrestore(&up->port.lock, flags);
553
554 return ret;
555}
556
557static unsigned int sunsu_get_mctrl(struct uart_port *port)
558{
559 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
560 unsigned char status;
561 unsigned int ret;
562
563 status = serial_in(up, UART_MSR);
564
565 ret = 0;
566 if (status & UART_MSR_DCD)
567 ret |= TIOCM_CAR;
568 if (status & UART_MSR_RI)
569 ret |= TIOCM_RNG;
570 if (status & UART_MSR_DSR)
571 ret |= TIOCM_DSR;
572 if (status & UART_MSR_CTS)
573 ret |= TIOCM_CTS;
574 return ret;
575}
576
577static void sunsu_set_mctrl(struct uart_port *port, unsigned int mctrl)
578{
579 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
580 unsigned char mcr = 0;
581
582 if (mctrl & TIOCM_RTS)
583 mcr |= UART_MCR_RTS;
584 if (mctrl & TIOCM_DTR)
585 mcr |= UART_MCR_DTR;
586 if (mctrl & TIOCM_OUT1)
587 mcr |= UART_MCR_OUT1;
588 if (mctrl & TIOCM_OUT2)
589 mcr |= UART_MCR_OUT2;
590 if (mctrl & TIOCM_LOOP)
591 mcr |= UART_MCR_LOOP;
592
593 serial_out(up, UART_MCR, mcr);
594}
595
596static void sunsu_break_ctl(struct uart_port *port, int break_state)
597{
598 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
599 unsigned long flags;
600
601 spin_lock_irqsave(&up->port.lock, flags);
602 if (break_state == -1)
603 up->lcr |= UART_LCR_SBC;
604 else
605 up->lcr &= ~UART_LCR_SBC;
606 serial_out(up, UART_LCR, up->lcr);
607 spin_unlock_irqrestore(&up->port.lock, flags);
608}
609
610static int sunsu_startup(struct uart_port *port)
611{
612 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
613 unsigned long flags;
614 int retval;
615
616 if (up->port.type == PORT_16C950) {
617 /* Wake up and initialize UART */
618 up->acr = 0;
619 serial_outp(up, UART_LCR, 0xBF);
620 serial_outp(up, UART_EFR, UART_EFR_ECB);
621 serial_outp(up, UART_IER, 0);
622 serial_outp(up, UART_LCR, 0);
623 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
624 serial_outp(up, UART_LCR, 0xBF);
625 serial_outp(up, UART_EFR, UART_EFR_ECB);
626 serial_outp(up, UART_LCR, 0);
627 }
628
629#ifdef CONFIG_SERIAL_8250_RSA
630 /*
631 * If this is an RSA port, see if we can kick it up to the
632 * higher speed clock.
633 */
634 enable_rsa(up);
635#endif
636
637 /*
638 * Clear the FIFO buffers and disable them.
639 * (they will be reenabled in set_termios())
640 */
641 if (uart_config[up->port.type].flags & UART_CLEAR_FIFO) {
642 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
643 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
644 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
645 serial_outp(up, UART_FCR, 0);
646 }
647
648 /*
649 * Clear the interrupt registers.
650 */
651 (void) serial_inp(up, UART_LSR);
652 (void) serial_inp(up, UART_RX);
653 (void) serial_inp(up, UART_IIR);
654 (void) serial_inp(up, UART_MSR);
655
656 /*
657 * At this point, there's no way the LSR could still be 0xff;
658 * if it is, then bail out, because there's likely no UART
659 * here.
660 */
661 if (!(up->port.flags & UPF_BUGGY_UART) &&
662 (serial_inp(up, UART_LSR) == 0xff)) {
663 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
664 return -ENODEV;
665 }
666
667 if (up->su_type != SU_PORT_PORT) {
668 retval = request_irq(up->port.irq, sunsu_kbd_ms_interrupt,
669 IRQF_SHARED, su_typev[up->su_type], up);
670 } else {
671 retval = request_irq(up->port.irq, sunsu_serial_interrupt,
672 IRQF_SHARED, su_typev[up->su_type], up);
673 }
674 if (retval) {
675 printk("su: Cannot register IRQ %d\n", up->port.irq);
676 return retval;
677 }
678
679 /*
680 * Now, initialize the UART
681 */
682 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
683
684 spin_lock_irqsave(&up->port.lock, flags);
685
686 up->port.mctrl |= TIOCM_OUT2;
687
688 sunsu_set_mctrl(&up->port, up->port.mctrl);
689 spin_unlock_irqrestore(&up->port.lock, flags);
690
691 /*
692 * Finally, enable interrupts. Note: Modem status interrupts
693 * are set via set_termios(), which will be occurring imminently
694 * anyway, so we don't enable them here.
695 */
696 up->ier = UART_IER_RLSI | UART_IER_RDI;
697 serial_outp(up, UART_IER, up->ier);
698
699 if (up->port.flags & UPF_FOURPORT) {
700 unsigned int icp;
701 /*
702 * Enable interrupts on the AST Fourport board
703 */
704 icp = (up->port.iobase & 0xfe0) | 0x01f;
705 outb_p(0x80, icp);
706 (void) inb_p(icp);
707 }
708
709 /*
710 * And clear the interrupt registers again for luck.
711 */
712 (void) serial_inp(up, UART_LSR);
713 (void) serial_inp(up, UART_RX);
714 (void) serial_inp(up, UART_IIR);
715 (void) serial_inp(up, UART_MSR);
716
717 return 0;
718}
719
720static void sunsu_shutdown(struct uart_port *port)
721{
722 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
723 unsigned long flags;
724
725 /*
726 * Disable interrupts from this port
727 */
728 up->ier = 0;
729 serial_outp(up, UART_IER, 0);
730
731 spin_lock_irqsave(&up->port.lock, flags);
732 if (up->port.flags & UPF_FOURPORT) {
733 /* reset interrupts on the AST Fourport board */
734 inb((up->port.iobase & 0xfe0) | 0x1f);
735 up->port.mctrl |= TIOCM_OUT1;
736 } else
737 up->port.mctrl &= ~TIOCM_OUT2;
738
739 sunsu_set_mctrl(&up->port, up->port.mctrl);
740 spin_unlock_irqrestore(&up->port.lock, flags);
741
742 /*
743 * Disable break condition and FIFOs
744 */
745 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
746 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
747 UART_FCR_CLEAR_RCVR |
748 UART_FCR_CLEAR_XMIT);
749 serial_outp(up, UART_FCR, 0);
750
751#ifdef CONFIG_SERIAL_8250_RSA
752 /*
753 * Reset the RSA board back to 115kbps compat mode.
754 */
755 disable_rsa(up);
756#endif
757
758 /*
759 * Read data port to reset things.
760 */
761 (void) serial_in(up, UART_RX);
762
763 free_irq(up->port.irq, up);
764}
765
766static void
767sunsu_change_speed(struct uart_port *port, unsigned int cflag,
768 unsigned int iflag, unsigned int quot)
769{
770 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
771 unsigned char cval, fcr = 0;
772 unsigned long flags;
773
774 switch (cflag & CSIZE) {
775 case CS5:
776 cval = 0x00;
777 break;
778 case CS6:
779 cval = 0x01;
780 break;
781 case CS7:
782 cval = 0x02;
783 break;
784 default:
785 case CS8:
786 cval = 0x03;
787 break;
788 }
789
790 if (cflag & CSTOPB)
791 cval |= 0x04;
792 if (cflag & PARENB)
793 cval |= UART_LCR_PARITY;
794 if (!(cflag & PARODD))
795 cval |= UART_LCR_EPAR;
796#ifdef CMSPAR
797 if (cflag & CMSPAR)
798 cval |= UART_LCR_SPAR;
799#endif
800
801 /*
802 * Work around a bug in the Oxford Semiconductor 952 rev B
803 * chip which causes it to seriously miscalculate baud rates
804 * when DLL is 0.
805 */
806 if ((quot & 0xff) == 0 && up->port.type == PORT_16C950 &&
807 up->rev == 0x5201)
808 quot ++;
809
810 if (uart_config[up->port.type].flags & UART_USE_FIFO) {
811 if ((up->port.uartclk / quot) < (2400 * 16))
812 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
813#ifdef CONFIG_SERIAL_8250_RSA
814 else if (up->port.type == PORT_RSA)
815 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_14;
816#endif
817 else
818 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_8;
819 }
820 if (up->port.type == PORT_16750)
821 fcr |= UART_FCR7_64BYTE;
822
823 /*
824 * Ok, we're now changing the port state. Do it with
825 * interrupts disabled.
826 */
827 spin_lock_irqsave(&up->port.lock, flags);
828
829 /*
830 * Update the per-port timeout.
831 */
832 uart_update_timeout(port, cflag, (port->uartclk / (16 * quot)));
833
834 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
835 if (iflag & INPCK)
836 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
837 if (iflag & (BRKINT | PARMRK))
838 up->port.read_status_mask |= UART_LSR_BI;
839
840 /*
841 * Characteres to ignore
842 */
843 up->port.ignore_status_mask = 0;
844 if (iflag & IGNPAR)
845 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
846 if (iflag & IGNBRK) {
847 up->port.ignore_status_mask |= UART_LSR_BI;
848 /*
849 * If we're ignoring parity and break indicators,
850 * ignore overruns too (for real raw support).
851 */
852 if (iflag & IGNPAR)
853 up->port.ignore_status_mask |= UART_LSR_OE;
854 }
855
856 /*
857 * ignore all characters if CREAD is not set
858 */
859 if ((cflag & CREAD) == 0)
860 up->port.ignore_status_mask |= UART_LSR_DR;
861
862 /*
863 * CTS flow control flag and modem status interrupts
864 */
865 up->ier &= ~UART_IER_MSI;
866 if (UART_ENABLE_MS(&up->port, cflag))
867 up->ier |= UART_IER_MSI;
868
869 serial_out(up, UART_IER, up->ier);
870
871 if (uart_config[up->port.type].flags & UART_STARTECH) {
872 serial_outp(up, UART_LCR, 0xBF);
873 serial_outp(up, UART_EFR, cflag & CRTSCTS ? UART_EFR_CTS :0);
874 }
875 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
876 serial_outp(up, UART_DLL, quot & 0xff); /* LS of divisor */
877 serial_outp(up, UART_DLM, quot >> 8); /* MS of divisor */
878 if (up->port.type == PORT_16750)
879 serial_outp(up, UART_FCR, fcr); /* set fcr */
880 serial_outp(up, UART_LCR, cval); /* reset DLAB */
881 up->lcr = cval; /* Save LCR */
882 if (up->port.type != PORT_16750) {
883 if (fcr & UART_FCR_ENABLE_FIFO) {
884 /* emulated UARTs (Lucent Venus 167x) need two steps */
885 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
886 }
887 serial_outp(up, UART_FCR, fcr); /* set fcr */
888 }
889
890 up->cflag = cflag;
891
892 spin_unlock_irqrestore(&up->port.lock, flags);
893}
894
895static void
896sunsu_set_termios(struct uart_port *port, struct ktermios *termios,
897 struct ktermios *old)
898{
899 unsigned int baud, quot;
900
901 /*
902 * Ask the core to calculate the divisor for us.
903 */
904 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
905 quot = uart_get_divisor(port, baud);
906
907 sunsu_change_speed(port, termios->c_cflag, termios->c_iflag, quot);
908}
909
910static void sunsu_release_port(struct uart_port *port)
911{
912}
913
914static int sunsu_request_port(struct uart_port *port)
915{
916 return 0;
917}
918
919static void sunsu_config_port(struct uart_port *port, int flags)
920{
921 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
922
923 if (flags & UART_CONFIG_TYPE) {
924 /*
925 * We are supposed to call autoconfig here, but this requires
926 * splitting all the OBP probing crap from the UART probing.
927 * We'll do it when we kill sunsu.c altogether.
928 */
929 port->type = up->type_probed; /* XXX */
930 }
931}
932
933static int
934sunsu_verify_port(struct uart_port *port, struct serial_struct *ser)
935{
936 return -EINVAL;
937}
938
939static const char *
940sunsu_type(struct uart_port *port)
941{
942 int type = port->type;
943
944 if (type >= ARRAY_SIZE(uart_config))
945 type = 0;
946 return uart_config[type].name;
947}
948
949static struct uart_ops sunsu_pops = {
950 .tx_empty = sunsu_tx_empty,
951 .set_mctrl = sunsu_set_mctrl,
952 .get_mctrl = sunsu_get_mctrl,
953 .stop_tx = sunsu_stop_tx,
954 .start_tx = sunsu_start_tx,
955 .stop_rx = sunsu_stop_rx,
956 .enable_ms = sunsu_enable_ms,
957 .break_ctl = sunsu_break_ctl,
958 .startup = sunsu_startup,
959 .shutdown = sunsu_shutdown,
960 .set_termios = sunsu_set_termios,
961 .type = sunsu_type,
962 .release_port = sunsu_release_port,
963 .request_port = sunsu_request_port,
964 .config_port = sunsu_config_port,
965 .verify_port = sunsu_verify_port,
966};
967
968#define UART_NR 4
969
970static struct uart_sunsu_port sunsu_ports[UART_NR];
971
972#ifdef CONFIG_SERIO
973
974static DEFINE_SPINLOCK(sunsu_serio_lock);
975
976static int sunsu_serio_write(struct serio *serio, unsigned char ch)
977{
978 struct uart_sunsu_port *up = serio->port_data;
979 unsigned long flags;
980 int lsr;
981
982 spin_lock_irqsave(&sunsu_serio_lock, flags);
983
984 do {
985 lsr = serial_in(up, UART_LSR);
986 } while (!(lsr & UART_LSR_THRE));
987
988 /* Send the character out. */
989 serial_out(up, UART_TX, ch);
990
991 spin_unlock_irqrestore(&sunsu_serio_lock, flags);
992
993 return 0;
994}
995
996static int sunsu_serio_open(struct serio *serio)
997{
998 struct uart_sunsu_port *up = serio->port_data;
999 unsigned long flags;
1000 int ret;
1001
1002 spin_lock_irqsave(&sunsu_serio_lock, flags);
1003 if (!up->serio_open) {
1004 up->serio_open = 1;
1005 ret = 0;
1006 } else
1007 ret = -EBUSY;
1008 spin_unlock_irqrestore(&sunsu_serio_lock, flags);
1009
1010 return ret;
1011}
1012
1013static void sunsu_serio_close(struct serio *serio)
1014{
1015 struct uart_sunsu_port *up = serio->port_data;
1016 unsigned long flags;
1017
1018 spin_lock_irqsave(&sunsu_serio_lock, flags);
1019 up->serio_open = 0;
1020 spin_unlock_irqrestore(&sunsu_serio_lock, flags);
1021}
1022
1023#endif /* CONFIG_SERIO */
1024
1025static void sunsu_autoconfig(struct uart_sunsu_port *up)
1026{
1027 unsigned char status1, status2, scratch, scratch2, scratch3;
1028 unsigned char save_lcr, save_mcr;
1029 unsigned long flags;
1030
1031 if (up->su_type == SU_PORT_NONE)
1032 return;
1033
1034 up->type_probed = PORT_UNKNOWN;
1035 up->port.iotype = UPIO_MEM;
1036
1037 spin_lock_irqsave(&up->port.lock, flags);
1038
1039 if (!(up->port.flags & UPF_BUGGY_UART)) {
1040 /*
1041 * Do a simple existence test first; if we fail this, there's
1042 * no point trying anything else.
1043 *
1044 * 0x80 is used as a nonsense port to prevent against false
1045 * positives due to ISA bus float. The assumption is that
1046 * 0x80 is a non-existent port; which should be safe since
1047 * include/asm/io.h also makes this assumption.
1048 */
1049 scratch = serial_inp(up, UART_IER);
1050 serial_outp(up, UART_IER, 0);
1051#ifdef __i386__
1052 outb(0xff, 0x080);
1053#endif
1054 scratch2 = serial_inp(up, UART_IER);
1055 serial_outp(up, UART_IER, 0x0f);
1056#ifdef __i386__
1057 outb(0, 0x080);
1058#endif
1059 scratch3 = serial_inp(up, UART_IER);
1060 serial_outp(up, UART_IER, scratch);
1061 if (scratch2 != 0 || scratch3 != 0x0F)
1062 goto out; /* We failed; there's nothing here */
1063 }
1064
1065 save_mcr = serial_in(up, UART_MCR);
1066 save_lcr = serial_in(up, UART_LCR);
1067
1068 /*
1069 * Check to see if a UART is really there. Certain broken
1070 * internal modems based on the Rockwell chipset fail this
1071 * test, because they apparently don't implement the loopback
1072 * test mode. So this test is skipped on the COM 1 through
1073 * COM 4 ports. This *should* be safe, since no board
1074 * manufacturer would be stupid enough to design a board
1075 * that conflicts with COM 1-4 --- we hope!
1076 */
1077 if (!(up->port.flags & UPF_SKIP_TEST)) {
1078 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1079 status1 = serial_inp(up, UART_MSR) & 0xF0;
1080 serial_outp(up, UART_MCR, save_mcr);
1081 if (status1 != 0x90)
1082 goto out; /* We failed loopback test */
1083 }
1084 serial_outp(up, UART_LCR, 0xBF); /* set up for StarTech test */
1085 serial_outp(up, UART_EFR, 0); /* EFR is the same as FCR */
1086 serial_outp(up, UART_LCR, 0);
1087 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1088 scratch = serial_in(up, UART_IIR) >> 6;
1089 switch (scratch) {
1090 case 0:
1091 up->port.type = PORT_16450;
1092 break;
1093 case 1:
1094 up->port.type = PORT_UNKNOWN;
1095 break;
1096 case 2:
1097 up->port.type = PORT_16550;
1098 break;
1099 case 3:
1100 up->port.type = PORT_16550A;
1101 break;
1102 }
1103 if (up->port.type == PORT_16550A) {
1104 /* Check for Startech UART's */
1105 serial_outp(up, UART_LCR, UART_LCR_DLAB);
1106 if (serial_in(up, UART_EFR) == 0) {
1107 up->port.type = PORT_16650;
1108 } else {
1109 serial_outp(up, UART_LCR, 0xBF);
1110 if (serial_in(up, UART_EFR) == 0)
1111 up->port.type = PORT_16650V2;
1112 }
1113 }
1114 if (up->port.type == PORT_16550A) {
1115 /* Check for TI 16750 */
1116 serial_outp(up, UART_LCR, save_lcr | UART_LCR_DLAB);
1117 serial_outp(up, UART_FCR,
1118 UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1119 scratch = serial_in(up, UART_IIR) >> 5;
1120 if (scratch == 7) {
1121 /*
1122 * If this is a 16750, and not a cheap UART
1123 * clone, then it should only go into 64 byte
1124 * mode if the UART_FCR7_64BYTE bit was set
1125 * while UART_LCR_DLAB was latched.
1126 */
1127 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1128 serial_outp(up, UART_LCR, 0);
1129 serial_outp(up, UART_FCR,
1130 UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1131 scratch = serial_in(up, UART_IIR) >> 5;
1132 if (scratch == 6)
1133 up->port.type = PORT_16750;
1134 }
1135 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1136 }
1137 serial_outp(up, UART_LCR, save_lcr);
1138 if (up->port.type == PORT_16450) {
1139 scratch = serial_in(up, UART_SCR);
1140 serial_outp(up, UART_SCR, 0xa5);
1141 status1 = serial_in(up, UART_SCR);
1142 serial_outp(up, UART_SCR, 0x5a);
1143 status2 = serial_in(up, UART_SCR);
1144 serial_outp(up, UART_SCR, scratch);
1145
1146 if ((status1 != 0xa5) || (status2 != 0x5a))
1147 up->port.type = PORT_8250;
1148 }
1149
1150 up->port.fifosize = uart_config[up->port.type].dfl_xmit_fifo_size;
1151
1152 if (up->port.type == PORT_UNKNOWN)
1153 goto out;
1154 up->type_probed = up->port.type; /* XXX */
1155
1156 /*
1157 * Reset the UART.
1158 */
1159#ifdef CONFIG_SERIAL_8250_RSA
1160 if (up->port.type == PORT_RSA)
1161 serial_outp(up, UART_RSA_FRR, 0);
1162#endif
1163 serial_outp(up, UART_MCR, save_mcr);
1164 serial_outp(up, UART_FCR, (UART_FCR_ENABLE_FIFO |
1165 UART_FCR_CLEAR_RCVR |
1166 UART_FCR_CLEAR_XMIT));
1167 serial_outp(up, UART_FCR, 0);
1168 (void)serial_in(up, UART_RX);
1169 serial_outp(up, UART_IER, 0);
1170
1171out:
1172 spin_unlock_irqrestore(&up->port.lock, flags);
1173}
1174
1175static struct uart_driver sunsu_reg = {
1176 .owner = THIS_MODULE,
1177 .driver_name = "sunsu",
1178 .dev_name = "ttyS",
1179 .major = TTY_MAJOR,
1180};
1181
1182static int __devinit sunsu_kbd_ms_init(struct uart_sunsu_port *up)
1183{
1184 int quot, baud;
1185#ifdef CONFIG_SERIO
1186 struct serio *serio;
1187#endif
1188
1189 if (up->su_type == SU_PORT_KBD) {
1190 up->cflag = B1200 | CS8 | CLOCAL | CREAD;
1191 baud = 1200;
1192 } else {
1193 up->cflag = B4800 | CS8 | CLOCAL | CREAD;
1194 baud = 4800;
1195 }
1196 quot = up->port.uartclk / (16 * baud);
1197
1198 sunsu_autoconfig(up);
1199 if (up->port.type == PORT_UNKNOWN)
1200 return -ENODEV;
1201
1202 printk("%s: %s port at %llx, irq %u\n",
1203 up->port.dev->of_node->full_name,
1204 (up->su_type == SU_PORT_KBD) ? "Keyboard" : "Mouse",
1205 (unsigned long long) up->port.mapbase,
1206 up->port.irq);
1207
1208#ifdef CONFIG_SERIO
1209 serio = &up->serio;
1210 serio->port_data = up;
1211
1212 serio->id.type = SERIO_RS232;
1213 if (up->su_type == SU_PORT_KBD) {
1214 serio->id.proto = SERIO_SUNKBD;
1215 strlcpy(serio->name, "sukbd", sizeof(serio->name));
1216 } else {
1217 serio->id.proto = SERIO_SUN;
1218 serio->id.extra = 1;
1219 strlcpy(serio->name, "sums", sizeof(serio->name));
1220 }
1221 strlcpy(serio->phys,
1222 (!(up->port.line & 1) ? "su/serio0" : "su/serio1"),
1223 sizeof(serio->phys));
1224
1225 serio->write = sunsu_serio_write;
1226 serio->open = sunsu_serio_open;
1227 serio->close = sunsu_serio_close;
1228 serio->dev.parent = up->port.dev;
1229
1230 serio_register_port(serio);
1231#endif
1232
1233 sunsu_change_speed(&up->port, up->cflag, 0, quot);
1234
1235 sunsu_startup(&up->port);
1236 return 0;
1237}
1238
1239/*
1240 * ------------------------------------------------------------
1241 * Serial console driver
1242 * ------------------------------------------------------------
1243 */
1244
1245#ifdef CONFIG_SERIAL_SUNSU_CONSOLE
1246
1247#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1248
1249/*
1250 * Wait for transmitter & holding register to empty
1251 */
1252static __inline__ void wait_for_xmitr(struct uart_sunsu_port *up)
1253{
1254 unsigned int status, tmout = 10000;
1255
1256 /* Wait up to 10ms for the character(s) to be sent. */
1257 do {
1258 status = serial_in(up, UART_LSR);
1259
1260 if (status & UART_LSR_BI)
1261 up->lsr_break_flag = UART_LSR_BI;
1262
1263 if (--tmout == 0)
1264 break;
1265 udelay(1);
1266 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1267
1268 /* Wait up to 1s for flow control if necessary */
1269 if (up->port.flags & UPF_CONS_FLOW) {
1270 tmout = 1000000;
1271 while (--tmout &&
1272 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
1273 udelay(1);
1274 }
1275}
1276
1277static void sunsu_console_putchar(struct uart_port *port, int ch)
1278{
1279 struct uart_sunsu_port *up = (struct uart_sunsu_port *)port;
1280
1281 wait_for_xmitr(up);
1282 serial_out(up, UART_TX, ch);
1283}
1284
1285/*
1286 * Print a string to the serial port trying not to disturb
1287 * any possible real use of the port...
1288 */
1289static void sunsu_console_write(struct console *co, const char *s,
1290 unsigned int count)
1291{
1292 struct uart_sunsu_port *up = &sunsu_ports[co->index];
1293 unsigned long flags;
1294 unsigned int ier;
1295 int locked = 1;
1296
1297 local_irq_save(flags);
1298 if (up->port.sysrq) {
1299 locked = 0;
1300 } else if (oops_in_progress) {
1301 locked = spin_trylock(&up->port.lock);
1302 } else
1303 spin_lock(&up->port.lock);
1304
1305 /*
1306 * First save the UER then disable the interrupts
1307 */
1308 ier = serial_in(up, UART_IER);
1309 serial_out(up, UART_IER, 0);
1310
1311 uart_console_write(&up->port, s, count, sunsu_console_putchar);
1312
1313 /*
1314 * Finally, wait for transmitter to become empty
1315 * and restore the IER
1316 */
1317 wait_for_xmitr(up);
1318 serial_out(up, UART_IER, ier);
1319
1320 if (locked)
1321 spin_unlock(&up->port.lock);
1322 local_irq_restore(flags);
1323}
1324
1325/*
1326 * Setup initial baud/bits/parity. We do two things here:
1327 * - construct a cflag setting for the first su_open()
1328 * - initialize the serial port
1329 * Return non-zero if we didn't find a serial port.
1330 */
1331static int __init sunsu_console_setup(struct console *co, char *options)
1332{
1333 static struct ktermios dummy;
1334 struct ktermios termios;
1335 struct uart_port *port;
1336
1337 printk("Console: ttyS%d (SU)\n",
1338 (sunsu_reg.minor - 64) + co->index);
1339
1340 /*
1341 * Check whether an invalid uart number has been specified, and
1342 * if so, search for the first available port that does have
1343 * console support.
1344 */
1345 if (co->index >= UART_NR)
1346 co->index = 0;
1347 port = &sunsu_ports[co->index].port;
1348
1349 /*
1350 * Temporary fix.
1351 */
1352 spin_lock_init(&port->lock);
1353
1354 /* Get firmware console settings. */
1355 sunserial_console_termios(co, port->dev->of_node);
1356
1357 memset(&termios, 0, sizeof(struct ktermios));
1358 termios.c_cflag = co->cflag;
1359 port->mctrl |= TIOCM_DTR;
1360 port->ops->set_termios(port, &termios, &dummy);
1361
1362 return 0;
1363}
1364
1365static struct console sunsu_console = {
1366 .name = "ttyS",
1367 .write = sunsu_console_write,
1368 .device = uart_console_device,
1369 .setup = sunsu_console_setup,
1370 .flags = CON_PRINTBUFFER,
1371 .index = -1,
1372 .data = &sunsu_reg,
1373};
1374
1375/*
1376 * Register console.
1377 */
1378
1379static inline struct console *SUNSU_CONSOLE(void)
1380{
1381 return &sunsu_console;
1382}
1383#else
1384#define SUNSU_CONSOLE() (NULL)
1385#define sunsu_serial_console_init() do { } while (0)
1386#endif
1387
1388static enum su_type __devinit su_get_type(struct device_node *dp)
1389{
1390 struct device_node *ap = of_find_node_by_path("/aliases");
1391
1392 if (ap) {
1393 const char *keyb = of_get_property(ap, "keyboard", NULL);
1394 const char *ms = of_get_property(ap, "mouse", NULL);
1395
1396 if (keyb) {
1397 if (dp == of_find_node_by_path(keyb))
1398 return SU_PORT_KBD;
1399 }
1400 if (ms) {
1401 if (dp == of_find_node_by_path(ms))
1402 return SU_PORT_MS;
1403 }
1404 }
1405
1406 return SU_PORT_PORT;
1407}
1408
1409static int __devinit su_probe(struct platform_device *op, const struct of_device_id *match)
1410{
1411 static int inst;
1412 struct device_node *dp = op->dev.of_node;
1413 struct uart_sunsu_port *up;
1414 struct resource *rp;
1415 enum su_type type;
1416 bool ignore_line;
1417 int err;
1418
1419 type = su_get_type(dp);
1420 if (type == SU_PORT_PORT) {
1421 if (inst >= UART_NR)
1422 return -EINVAL;
1423 up = &sunsu_ports[inst];
1424 } else {
1425 up = kzalloc(sizeof(*up), GFP_KERNEL);
1426 if (!up)
1427 return -ENOMEM;
1428 }
1429
1430 up->port.line = inst;
1431
1432 spin_lock_init(&up->port.lock);
1433
1434 up->su_type = type;
1435
1436 rp = &op->resource[0];
1437 up->port.mapbase = rp->start;
1438 up->reg_size = (rp->end - rp->start) + 1;
1439 up->port.membase = of_ioremap(rp, 0, up->reg_size, "su");
1440 if (!up->port.membase) {
1441 if (type != SU_PORT_PORT)
1442 kfree(up);
1443 return -ENOMEM;
1444 }
1445
1446 up->port.irq = op->archdata.irqs[0];
1447
1448 up->port.dev = &op->dev;
1449
1450 up->port.type = PORT_UNKNOWN;
1451 up->port.uartclk = (SU_BASE_BAUD * 16);
1452
1453 err = 0;
1454 if (up->su_type == SU_PORT_KBD || up->su_type == SU_PORT_MS) {
1455 err = sunsu_kbd_ms_init(up);
1456 if (err) {
1457 of_iounmap(&op->resource[0],
1458 up->port.membase, up->reg_size);
1459 kfree(up);
1460 return err;
1461 }
1462 dev_set_drvdata(&op->dev, up);
1463
1464 return 0;
1465 }
1466
1467 up->port.flags |= UPF_BOOT_AUTOCONF;
1468
1469 sunsu_autoconfig(up);
1470
1471 err = -ENODEV;
1472 if (up->port.type == PORT_UNKNOWN)
1473 goto out_unmap;
1474
1475 up->port.ops = &sunsu_pops;
1476
1477 ignore_line = false;
1478 if (!strcmp(dp->name, "rsc-console") ||
1479 !strcmp(dp->name, "lom-console"))
1480 ignore_line = true;
1481
1482 sunserial_console_match(SUNSU_CONSOLE(), dp,
1483 &sunsu_reg, up->port.line,
1484 ignore_line);
1485 err = uart_add_one_port(&sunsu_reg, &up->port);
1486 if (err)
1487 goto out_unmap;
1488
1489 dev_set_drvdata(&op->dev, up);
1490
1491 inst++;
1492
1493 return 0;
1494
1495out_unmap:
1496 of_iounmap(&op->resource[0], up->port.membase, up->reg_size);
1497 return err;
1498}
1499
1500static int __devexit su_remove(struct platform_device *op)
1501{
1502 struct uart_sunsu_port *up = dev_get_drvdata(&op->dev);
1503 bool kbdms = false;
1504
1505 if (up->su_type == SU_PORT_MS ||
1506 up->su_type == SU_PORT_KBD)
1507 kbdms = true;
1508
1509 if (kbdms) {
1510#ifdef CONFIG_SERIO
1511 serio_unregister_port(&up->serio);
1512#endif
1513 } else if (up->port.type != PORT_UNKNOWN)
1514 uart_remove_one_port(&sunsu_reg, &up->port);
1515
1516 if (up->port.membase)
1517 of_iounmap(&op->resource[0], up->port.membase, up->reg_size);
1518
1519 if (kbdms)
1520 kfree(up);
1521
1522 dev_set_drvdata(&op->dev, NULL);
1523
1524 return 0;
1525}
1526
1527static const struct of_device_id su_match[] = {
1528 {
1529 .name = "su",
1530 },
1531 {
1532 .name = "su_pnp",
1533 },
1534 {
1535 .name = "serial",
1536 .compatible = "su",
1537 },
1538 {
1539 .type = "serial",
1540 .compatible = "su",
1541 },
1542 {},
1543};
1544MODULE_DEVICE_TABLE(of, su_match);
1545
1546static struct of_platform_driver su_driver = {
1547 .driver = {
1548 .name = "su",
1549 .owner = THIS_MODULE,
1550 .of_match_table = su_match,
1551 },
1552 .probe = su_probe,
1553 .remove = __devexit_p(su_remove),
1554};
1555
1556static int __init sunsu_init(void)
1557{
1558 struct device_node *dp;
1559 int err;
1560 int num_uart = 0;
1561
1562 for_each_node_by_name(dp, "su") {
1563 if (su_get_type(dp) == SU_PORT_PORT)
1564 num_uart++;
1565 }
1566 for_each_node_by_name(dp, "su_pnp") {
1567 if (su_get_type(dp) == SU_PORT_PORT)
1568 num_uart++;
1569 }
1570 for_each_node_by_name(dp, "serial") {
1571 if (of_device_is_compatible(dp, "su")) {
1572 if (su_get_type(dp) == SU_PORT_PORT)
1573 num_uart++;
1574 }
1575 }
1576 for_each_node_by_type(dp, "serial") {
1577 if (of_device_is_compatible(dp, "su")) {
1578 if (su_get_type(dp) == SU_PORT_PORT)
1579 num_uart++;
1580 }
1581 }
1582
1583 if (num_uart) {
1584 err = sunserial_register_minors(&sunsu_reg, num_uart);
1585 if (err)
1586 return err;
1587 }
1588
1589 err = of_register_platform_driver(&su_driver);
1590 if (err && num_uart)
1591 sunserial_unregister_minors(&sunsu_reg, num_uart);
1592
1593 return err;
1594}
1595
1596static void __exit sunsu_exit(void)
1597{
1598 if (sunsu_reg.nr)
1599 sunserial_unregister_minors(&sunsu_reg, sunsu_reg.nr);
1600}
1601
1602module_init(sunsu_init);
1603module_exit(sunsu_exit);
1604
1605MODULE_AUTHOR("Eddie C. Dost, Peter Zaitcev, and David S. Miller");
1606MODULE_DESCRIPTION("Sun SU serial port driver");
1607MODULE_VERSION("2.0");
1608MODULE_LICENSE("GPL");
diff --git a/drivers/serial/sunzilog.c b/drivers/serial/sunzilog.c
deleted file mode 100644
index c1967ac1c07f..000000000000
--- a/drivers/serial/sunzilog.c
+++ /dev/null
@@ -1,1655 +0,0 @@
1/* sunzilog.c: Zilog serial driver for Sparc systems.
2 *
3 * Driver for Zilog serial chips found on Sun workstations and
4 * servers. This driver could actually be made more generic.
5 *
6 * This is based on the old drivers/sbus/char/zs.c code. A lot
7 * of code has been simply moved over directly from there but
8 * much has been rewritten. Credits therefore go out to Eddie
9 * C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell for their
10 * work there.
11 *
12 * Copyright (C) 2002, 2006, 2007 David S. Miller (davem@davemloft.net)
13 */
14
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/errno.h>
18#include <linux/delay.h>
19#include <linux/tty.h>
20#include <linux/tty_flip.h>
21#include <linux/major.h>
22#include <linux/string.h>
23#include <linux/ptrace.h>
24#include <linux/ioport.h>
25#include <linux/slab.h>
26#include <linux/circ_buf.h>
27#include <linux/serial.h>
28#include <linux/sysrq.h>
29#include <linux/console.h>
30#include <linux/spinlock.h>
31#ifdef CONFIG_SERIO
32#include <linux/serio.h>
33#endif
34#include <linux/init.h>
35#include <linux/of_device.h>
36
37#include <asm/io.h>
38#include <asm/irq.h>
39#include <asm/prom.h>
40
41#if defined(CONFIG_SERIAL_SUNZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
42#define SUPPORT_SYSRQ
43#endif
44
45#include <linux/serial_core.h>
46
47#include "suncore.h"
48#include "sunzilog.h"
49
50/* On 32-bit sparcs we need to delay after register accesses
51 * to accommodate sun4 systems, but we do not need to flush writes.
52 * On 64-bit sparc we only need to flush single writes to ensure
53 * completion.
54 */
55#ifndef CONFIG_SPARC64
56#define ZSDELAY() udelay(5)
57#define ZSDELAY_LONG() udelay(20)
58#define ZS_WSYNC(channel) do { } while (0)
59#else
60#define ZSDELAY()
61#define ZSDELAY_LONG()
62#define ZS_WSYNC(__channel) \
63 readb(&((__channel)->control))
64#endif
65
66#define ZS_CLOCK 4915200 /* Zilog input clock rate. */
67#define ZS_CLOCK_DIVISOR 16 /* Divisor this driver uses. */
68
69/*
70 * We wrap our port structure around the generic uart_port.
71 */
72struct uart_sunzilog_port {
73 struct uart_port port;
74
75 /* IRQ servicing chain. */
76 struct uart_sunzilog_port *next;
77
78 /* Current values of Zilog write registers. */
79 unsigned char curregs[NUM_ZSREGS];
80
81 unsigned int flags;
82#define SUNZILOG_FLAG_CONS_KEYB 0x00000001
83#define SUNZILOG_FLAG_CONS_MOUSE 0x00000002
84#define SUNZILOG_FLAG_IS_CONS 0x00000004
85#define SUNZILOG_FLAG_IS_KGDB 0x00000008
86#define SUNZILOG_FLAG_MODEM_STATUS 0x00000010
87#define SUNZILOG_FLAG_IS_CHANNEL_A 0x00000020
88#define SUNZILOG_FLAG_REGS_HELD 0x00000040
89#define SUNZILOG_FLAG_TX_STOPPED 0x00000080
90#define SUNZILOG_FLAG_TX_ACTIVE 0x00000100
91#define SUNZILOG_FLAG_ESCC 0x00000200
92#define SUNZILOG_FLAG_ISR_HANDLER 0x00000400
93
94 unsigned int cflag;
95
96 unsigned char parity_mask;
97 unsigned char prev_status;
98
99#ifdef CONFIG_SERIO
100 struct serio serio;
101 int serio_open;
102#endif
103};
104
105static void sunzilog_putchar(struct uart_port *port, int ch);
106
107#define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel __iomem *)((PORT)->membase))
108#define UART_ZILOG(PORT) ((struct uart_sunzilog_port *)(PORT))
109
110#define ZS_IS_KEYB(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_KEYB)
111#define ZS_IS_MOUSE(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_MOUSE)
112#define ZS_IS_CONS(UP) ((UP)->flags & SUNZILOG_FLAG_IS_CONS)
113#define ZS_IS_KGDB(UP) ((UP)->flags & SUNZILOG_FLAG_IS_KGDB)
114#define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & SUNZILOG_FLAG_MODEM_STATUS)
115#define ZS_IS_CHANNEL_A(UP) ((UP)->flags & SUNZILOG_FLAG_IS_CHANNEL_A)
116#define ZS_REGS_HELD(UP) ((UP)->flags & SUNZILOG_FLAG_REGS_HELD)
117#define ZS_TX_STOPPED(UP) ((UP)->flags & SUNZILOG_FLAG_TX_STOPPED)
118#define ZS_TX_ACTIVE(UP) ((UP)->flags & SUNZILOG_FLAG_TX_ACTIVE)
119
120/* Reading and writing Zilog8530 registers. The delays are to make this
121 * driver work on the Sun4 which needs a settling delay after each chip
122 * register access, other machines handle this in hardware via auxiliary
123 * flip-flops which implement the settle time we do in software.
124 *
125 * The port lock must be held and local IRQs must be disabled
126 * when {read,write}_zsreg is invoked.
127 */
128static unsigned char read_zsreg(struct zilog_channel __iomem *channel,
129 unsigned char reg)
130{
131 unsigned char retval;
132
133 writeb(reg, &channel->control);
134 ZSDELAY();
135 retval = readb(&channel->control);
136 ZSDELAY();
137
138 return retval;
139}
140
141static void write_zsreg(struct zilog_channel __iomem *channel,
142 unsigned char reg, unsigned char value)
143{
144 writeb(reg, &channel->control);
145 ZSDELAY();
146 writeb(value, &channel->control);
147 ZSDELAY();
148}
149
150static void sunzilog_clear_fifo(struct zilog_channel __iomem *channel)
151{
152 int i;
153
154 for (i = 0; i < 32; i++) {
155 unsigned char regval;
156
157 regval = readb(&channel->control);
158 ZSDELAY();
159 if (regval & Rx_CH_AV)
160 break;
161
162 regval = read_zsreg(channel, R1);
163 readb(&channel->data);
164 ZSDELAY();
165
166 if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) {
167 writeb(ERR_RES, &channel->control);
168 ZSDELAY();
169 ZS_WSYNC(channel);
170 }
171 }
172}
173
174/* This function must only be called when the TX is not busy. The UART
175 * port lock must be held and local interrupts disabled.
176 */
177static int __load_zsregs(struct zilog_channel __iomem *channel, unsigned char *regs)
178{
179 int i;
180 int escc;
181 unsigned char r15;
182
183 /* Let pending transmits finish. */
184 for (i = 0; i < 1000; i++) {
185 unsigned char stat = read_zsreg(channel, R1);
186 if (stat & ALL_SNT)
187 break;
188 udelay(100);
189 }
190
191 writeb(ERR_RES, &channel->control);
192 ZSDELAY();
193 ZS_WSYNC(channel);
194
195 sunzilog_clear_fifo(channel);
196
197 /* Disable all interrupts. */
198 write_zsreg(channel, R1,
199 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
200
201 /* Set parity, sync config, stop bits, and clock divisor. */
202 write_zsreg(channel, R4, regs[R4]);
203
204 /* Set misc. TX/RX control bits. */
205 write_zsreg(channel, R10, regs[R10]);
206
207 /* Set TX/RX controls sans the enable bits. */
208 write_zsreg(channel, R3, regs[R3] & ~RxENAB);
209 write_zsreg(channel, R5, regs[R5] & ~TxENAB);
210
211 /* Synchronous mode config. */
212 write_zsreg(channel, R6, regs[R6]);
213 write_zsreg(channel, R7, regs[R7]);
214
215 /* Don't mess with the interrupt vector (R2, unused by us) and
216 * master interrupt control (R9). We make sure this is setup
217 * properly at probe time then never touch it again.
218 */
219
220 /* Disable baud generator. */
221 write_zsreg(channel, R14, regs[R14] & ~BRENAB);
222
223 /* Clock mode control. */
224 write_zsreg(channel, R11, regs[R11]);
225
226 /* Lower and upper byte of baud rate generator divisor. */
227 write_zsreg(channel, R12, regs[R12]);
228 write_zsreg(channel, R13, regs[R13]);
229
230 /* Now rewrite R14, with BRENAB (if set). */
231 write_zsreg(channel, R14, regs[R14]);
232
233 /* External status interrupt control. */
234 write_zsreg(channel, R15, (regs[R15] | WR7pEN) & ~FIFOEN);
235
236 /* ESCC Extension Register */
237 r15 = read_zsreg(channel, R15);
238 if (r15 & 0x01) {
239 write_zsreg(channel, R7, regs[R7p]);
240
241 /* External status interrupt and FIFO control. */
242 write_zsreg(channel, R15, regs[R15] & ~WR7pEN);
243 escc = 1;
244 } else {
245 /* Clear FIFO bit case it is an issue */
246 regs[R15] &= ~FIFOEN;
247 escc = 0;
248 }
249
250 /* Reset external status interrupts. */
251 write_zsreg(channel, R0, RES_EXT_INT); /* First Latch */
252 write_zsreg(channel, R0, RES_EXT_INT); /* Second Latch */
253
254 /* Rewrite R3/R5, this time without enables masked. */
255 write_zsreg(channel, R3, regs[R3]);
256 write_zsreg(channel, R5, regs[R5]);
257
258 /* Rewrite R1, this time without IRQ enabled masked. */
259 write_zsreg(channel, R1, regs[R1]);
260
261 return escc;
262}
263
264/* Reprogram the Zilog channel HW registers with the copies found in the
265 * software state struct. If the transmitter is busy, we defer this update
266 * until the next TX complete interrupt. Else, we do it right now.
267 *
268 * The UART port lock must be held and local interrupts disabled.
269 */
270static void sunzilog_maybe_update_regs(struct uart_sunzilog_port *up,
271 struct zilog_channel __iomem *channel)
272{
273 if (!ZS_REGS_HELD(up)) {
274 if (ZS_TX_ACTIVE(up)) {
275 up->flags |= SUNZILOG_FLAG_REGS_HELD;
276 } else {
277 __load_zsregs(channel, up->curregs);
278 }
279 }
280}
281
282static void sunzilog_change_mouse_baud(struct uart_sunzilog_port *up)
283{
284 unsigned int cur_cflag = up->cflag;
285 int brg, new_baud;
286
287 up->cflag &= ~CBAUD;
288 up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud);
289
290 brg = BPS_TO_BRG(new_baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
291 up->curregs[R12] = (brg & 0xff);
292 up->curregs[R13] = (brg >> 8) & 0xff;
293 sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(&up->port));
294}
295
296static void sunzilog_kbdms_receive_chars(struct uart_sunzilog_port *up,
297 unsigned char ch, int is_break)
298{
299 if (ZS_IS_KEYB(up)) {
300 /* Stop-A is handled by drivers/char/keyboard.c now. */
301#ifdef CONFIG_SERIO
302 if (up->serio_open)
303 serio_interrupt(&up->serio, ch, 0);
304#endif
305 } else if (ZS_IS_MOUSE(up)) {
306 int ret = suncore_mouse_baud_detection(ch, is_break);
307
308 switch (ret) {
309 case 2:
310 sunzilog_change_mouse_baud(up);
311 /* fallthru */
312 case 1:
313 break;
314
315 case 0:
316#ifdef CONFIG_SERIO
317 if (up->serio_open)
318 serio_interrupt(&up->serio, ch, 0);
319#endif
320 break;
321 };
322 }
323}
324
325static struct tty_struct *
326sunzilog_receive_chars(struct uart_sunzilog_port *up,
327 struct zilog_channel __iomem *channel)
328{
329 struct tty_struct *tty;
330 unsigned char ch, r1, flag;
331
332 tty = NULL;
333 if (up->port.state != NULL && /* Unopened serial console */
334 up->port.state->port.tty != NULL) /* Keyboard || mouse */
335 tty = up->port.state->port.tty;
336
337 for (;;) {
338
339 r1 = read_zsreg(channel, R1);
340 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
341 writeb(ERR_RES, &channel->control);
342 ZSDELAY();
343 ZS_WSYNC(channel);
344 }
345
346 ch = readb(&channel->control);
347 ZSDELAY();
348
349 /* This funny hack depends upon BRK_ABRT not interfering
350 * with the other bits we care about in R1.
351 */
352 if (ch & BRK_ABRT)
353 r1 |= BRK_ABRT;
354
355 if (!(ch & Rx_CH_AV))
356 break;
357
358 ch = readb(&channel->data);
359 ZSDELAY();
360
361 ch &= up->parity_mask;
362
363 if (unlikely(ZS_IS_KEYB(up)) || unlikely(ZS_IS_MOUSE(up))) {
364 sunzilog_kbdms_receive_chars(up, ch, 0);
365 continue;
366 }
367
368 if (tty == NULL) {
369 uart_handle_sysrq_char(&up->port, ch);
370 continue;
371 }
372
373 /* A real serial line, record the character and status. */
374 flag = TTY_NORMAL;
375 up->port.icount.rx++;
376 if (r1 & (BRK_ABRT | PAR_ERR | Rx_OVR | CRC_ERR)) {
377 if (r1 & BRK_ABRT) {
378 r1 &= ~(PAR_ERR | CRC_ERR);
379 up->port.icount.brk++;
380 if (uart_handle_break(&up->port))
381 continue;
382 }
383 else if (r1 & PAR_ERR)
384 up->port.icount.parity++;
385 else if (r1 & CRC_ERR)
386 up->port.icount.frame++;
387 if (r1 & Rx_OVR)
388 up->port.icount.overrun++;
389 r1 &= up->port.read_status_mask;
390 if (r1 & BRK_ABRT)
391 flag = TTY_BREAK;
392 else if (r1 & PAR_ERR)
393 flag = TTY_PARITY;
394 else if (r1 & CRC_ERR)
395 flag = TTY_FRAME;
396 }
397 if (uart_handle_sysrq_char(&up->port, ch))
398 continue;
399
400 if (up->port.ignore_status_mask == 0xff ||
401 (r1 & up->port.ignore_status_mask) == 0) {
402 tty_insert_flip_char(tty, ch, flag);
403 }
404 if (r1 & Rx_OVR)
405 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
406 }
407
408 return tty;
409}
410
411static void sunzilog_status_handle(struct uart_sunzilog_port *up,
412 struct zilog_channel __iomem *channel)
413{
414 unsigned char status;
415
416 status = readb(&channel->control);
417 ZSDELAY();
418
419 writeb(RES_EXT_INT, &channel->control);
420 ZSDELAY();
421 ZS_WSYNC(channel);
422
423 if (status & BRK_ABRT) {
424 if (ZS_IS_MOUSE(up))
425 sunzilog_kbdms_receive_chars(up, 0, 1);
426 if (ZS_IS_CONS(up)) {
427 /* Wait for BREAK to deassert to avoid potentially
428 * confusing the PROM.
429 */
430 while (1) {
431 status = readb(&channel->control);
432 ZSDELAY();
433 if (!(status & BRK_ABRT))
434 break;
435 }
436 sun_do_break();
437 return;
438 }
439 }
440
441 if (ZS_WANTS_MODEM_STATUS(up)) {
442 if (status & SYNC)
443 up->port.icount.dsr++;
444
445 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
446 * But it does not tell us which bit has changed, we have to keep
447 * track of this ourselves.
448 */
449 if ((status ^ up->prev_status) ^ DCD)
450 uart_handle_dcd_change(&up->port,
451 (status & DCD));
452 if ((status ^ up->prev_status) ^ CTS)
453 uart_handle_cts_change(&up->port,
454 (status & CTS));
455
456 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
457 }
458
459 up->prev_status = status;
460}
461
462static void sunzilog_transmit_chars(struct uart_sunzilog_port *up,
463 struct zilog_channel __iomem *channel)
464{
465 struct circ_buf *xmit;
466
467 if (ZS_IS_CONS(up)) {
468 unsigned char status = readb(&channel->control);
469 ZSDELAY();
470
471 /* TX still busy? Just wait for the next TX done interrupt.
472 *
473 * It can occur because of how we do serial console writes. It would
474 * be nice to transmit console writes just like we normally would for
475 * a TTY line. (ie. buffered and TX interrupt driven). That is not
476 * easy because console writes cannot sleep. One solution might be
477 * to poll on enough port->xmit space becomming free. -DaveM
478 */
479 if (!(status & Tx_BUF_EMP))
480 return;
481 }
482
483 up->flags &= ~SUNZILOG_FLAG_TX_ACTIVE;
484
485 if (ZS_REGS_HELD(up)) {
486 __load_zsregs(channel, up->curregs);
487 up->flags &= ~SUNZILOG_FLAG_REGS_HELD;
488 }
489
490 if (ZS_TX_STOPPED(up)) {
491 up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
492 goto ack_tx_int;
493 }
494
495 if (up->port.x_char) {
496 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
497 writeb(up->port.x_char, &channel->data);
498 ZSDELAY();
499 ZS_WSYNC(channel);
500
501 up->port.icount.tx++;
502 up->port.x_char = 0;
503 return;
504 }
505
506 if (up->port.state == NULL)
507 goto ack_tx_int;
508 xmit = &up->port.state->xmit;
509 if (uart_circ_empty(xmit))
510 goto ack_tx_int;
511
512 if (uart_tx_stopped(&up->port))
513 goto ack_tx_int;
514
515 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
516 writeb(xmit->buf[xmit->tail], &channel->data);
517 ZSDELAY();
518 ZS_WSYNC(channel);
519
520 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
521 up->port.icount.tx++;
522
523 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
524 uart_write_wakeup(&up->port);
525
526 return;
527
528ack_tx_int:
529 writeb(RES_Tx_P, &channel->control);
530 ZSDELAY();
531 ZS_WSYNC(channel);
532}
533
534static irqreturn_t sunzilog_interrupt(int irq, void *dev_id)
535{
536 struct uart_sunzilog_port *up = dev_id;
537
538 while (up) {
539 struct zilog_channel __iomem *channel
540 = ZILOG_CHANNEL_FROM_PORT(&up->port);
541 struct tty_struct *tty;
542 unsigned char r3;
543
544 spin_lock(&up->port.lock);
545 r3 = read_zsreg(channel, R3);
546
547 /* Channel A */
548 tty = NULL;
549 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
550 writeb(RES_H_IUS, &channel->control);
551 ZSDELAY();
552 ZS_WSYNC(channel);
553
554 if (r3 & CHARxIP)
555 tty = sunzilog_receive_chars(up, channel);
556 if (r3 & CHAEXT)
557 sunzilog_status_handle(up, channel);
558 if (r3 & CHATxIP)
559 sunzilog_transmit_chars(up, channel);
560 }
561 spin_unlock(&up->port.lock);
562
563 if (tty)
564 tty_flip_buffer_push(tty);
565
566 /* Channel B */
567 up = up->next;
568 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
569
570 spin_lock(&up->port.lock);
571 tty = NULL;
572 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
573 writeb(RES_H_IUS, &channel->control);
574 ZSDELAY();
575 ZS_WSYNC(channel);
576
577 if (r3 & CHBRxIP)
578 tty = sunzilog_receive_chars(up, channel);
579 if (r3 & CHBEXT)
580 sunzilog_status_handle(up, channel);
581 if (r3 & CHBTxIP)
582 sunzilog_transmit_chars(up, channel);
583 }
584 spin_unlock(&up->port.lock);
585
586 if (tty)
587 tty_flip_buffer_push(tty);
588
589 up = up->next;
590 }
591
592 return IRQ_HANDLED;
593}
594
595/* A convenient way to quickly get R0 status. The caller must _not_ hold the
596 * port lock, it is acquired here.
597 */
598static __inline__ unsigned char sunzilog_read_channel_status(struct uart_port *port)
599{
600 struct zilog_channel __iomem *channel;
601 unsigned char status;
602
603 channel = ZILOG_CHANNEL_FROM_PORT(port);
604 status = readb(&channel->control);
605 ZSDELAY();
606
607 return status;
608}
609
610/* The port lock is not held. */
611static unsigned int sunzilog_tx_empty(struct uart_port *port)
612{
613 unsigned long flags;
614 unsigned char status;
615 unsigned int ret;
616
617 spin_lock_irqsave(&port->lock, flags);
618
619 status = sunzilog_read_channel_status(port);
620
621 spin_unlock_irqrestore(&port->lock, flags);
622
623 if (status & Tx_BUF_EMP)
624 ret = TIOCSER_TEMT;
625 else
626 ret = 0;
627
628 return ret;
629}
630
631/* The port lock is held and interrupts are disabled. */
632static unsigned int sunzilog_get_mctrl(struct uart_port *port)
633{
634 unsigned char status;
635 unsigned int ret;
636
637 status = sunzilog_read_channel_status(port);
638
639 ret = 0;
640 if (status & DCD)
641 ret |= TIOCM_CAR;
642 if (status & SYNC)
643 ret |= TIOCM_DSR;
644 if (status & CTS)
645 ret |= TIOCM_CTS;
646
647 return ret;
648}
649
650/* The port lock is held and interrupts are disabled. */
651static void sunzilog_set_mctrl(struct uart_port *port, unsigned int mctrl)
652{
653 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
654 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
655 unsigned char set_bits, clear_bits;
656
657 set_bits = clear_bits = 0;
658
659 if (mctrl & TIOCM_RTS)
660 set_bits |= RTS;
661 else
662 clear_bits |= RTS;
663 if (mctrl & TIOCM_DTR)
664 set_bits |= DTR;
665 else
666 clear_bits |= DTR;
667
668 /* NOTE: Not subject to 'transmitter active' rule. */
669 up->curregs[R5] |= set_bits;
670 up->curregs[R5] &= ~clear_bits;
671 write_zsreg(channel, R5, up->curregs[R5]);
672}
673
674/* The port lock is held and interrupts are disabled. */
675static void sunzilog_stop_tx(struct uart_port *port)
676{
677 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
678
679 up->flags |= SUNZILOG_FLAG_TX_STOPPED;
680}
681
682/* The port lock is held and interrupts are disabled. */
683static void sunzilog_start_tx(struct uart_port *port)
684{
685 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
686 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
687 unsigned char status;
688
689 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
690 up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
691
692 status = readb(&channel->control);
693 ZSDELAY();
694
695 /* TX busy? Just wait for the TX done interrupt. */
696 if (!(status & Tx_BUF_EMP))
697 return;
698
699 /* Send the first character to jump-start the TX done
700 * IRQ sending engine.
701 */
702 if (port->x_char) {
703 writeb(port->x_char, &channel->data);
704 ZSDELAY();
705 ZS_WSYNC(channel);
706
707 port->icount.tx++;
708 port->x_char = 0;
709 } else {
710 struct circ_buf *xmit = &port->state->xmit;
711
712 writeb(xmit->buf[xmit->tail], &channel->data);
713 ZSDELAY();
714 ZS_WSYNC(channel);
715
716 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
717 port->icount.tx++;
718
719 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
720 uart_write_wakeup(&up->port);
721 }
722}
723
724/* The port lock is held. */
725static void sunzilog_stop_rx(struct uart_port *port)
726{
727 struct uart_sunzilog_port *up = UART_ZILOG(port);
728 struct zilog_channel __iomem *channel;
729
730 if (ZS_IS_CONS(up))
731 return;
732
733 channel = ZILOG_CHANNEL_FROM_PORT(port);
734
735 /* Disable all RX interrupts. */
736 up->curregs[R1] &= ~RxINT_MASK;
737 sunzilog_maybe_update_regs(up, channel);
738}
739
740/* The port lock is held. */
741static void sunzilog_enable_ms(struct uart_port *port)
742{
743 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
744 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
745 unsigned char new_reg;
746
747 new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
748 if (new_reg != up->curregs[R15]) {
749 up->curregs[R15] = new_reg;
750
751 /* NOTE: Not subject to 'transmitter active' rule. */
752 write_zsreg(channel, R15, up->curregs[R15] & ~WR7pEN);
753 }
754}
755
756/* The port lock is not held. */
757static void sunzilog_break_ctl(struct uart_port *port, int break_state)
758{
759 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
760 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
761 unsigned char set_bits, clear_bits, new_reg;
762 unsigned long flags;
763
764 set_bits = clear_bits = 0;
765
766 if (break_state)
767 set_bits |= SND_BRK;
768 else
769 clear_bits |= SND_BRK;
770
771 spin_lock_irqsave(&port->lock, flags);
772
773 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
774 if (new_reg != up->curregs[R5]) {
775 up->curregs[R5] = new_reg;
776
777 /* NOTE: Not subject to 'transmitter active' rule. */
778 write_zsreg(channel, R5, up->curregs[R5]);
779 }
780
781 spin_unlock_irqrestore(&port->lock, flags);
782}
783
784static void __sunzilog_startup(struct uart_sunzilog_port *up)
785{
786 struct zilog_channel __iomem *channel;
787
788 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
789 up->prev_status = readb(&channel->control);
790
791 /* Enable receiver and transmitter. */
792 up->curregs[R3] |= RxENAB;
793 up->curregs[R5] |= TxENAB;
794
795 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
796 sunzilog_maybe_update_regs(up, channel);
797}
798
799static int sunzilog_startup(struct uart_port *port)
800{
801 struct uart_sunzilog_port *up = UART_ZILOG(port);
802 unsigned long flags;
803
804 if (ZS_IS_CONS(up))
805 return 0;
806
807 spin_lock_irqsave(&port->lock, flags);
808 __sunzilog_startup(up);
809 spin_unlock_irqrestore(&port->lock, flags);
810 return 0;
811}
812
813/*
814 * The test for ZS_IS_CONS is explained by the following e-mail:
815 *****
816 * From: Russell King <rmk@arm.linux.org.uk>
817 * Date: Sun, 8 Dec 2002 10:18:38 +0000
818 *
819 * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote:
820 * > I boot my 2.5 boxes using "console=ttyS0,9600" argument,
821 * > and I noticed that something is not right with reference
822 * > counting in this case. It seems that when the console
823 * > is open by kernel initially, this is not accounted
824 * > as an open, and uart_startup is not called.
825 *
826 * That is correct. We are unable to call uart_startup when the serial
827 * console is initialised because it may need to allocate memory (as
828 * request_irq does) and the memory allocators may not have been
829 * initialised.
830 *
831 * 1. initialise the port into a state where it can send characters in the
832 * console write method.
833 *
834 * 2. don't do the actual hardware shutdown in your shutdown() method (but
835 * do the normal software shutdown - ie, free irqs etc)
836 *****
837 */
838static void sunzilog_shutdown(struct uart_port *port)
839{
840 struct uart_sunzilog_port *up = UART_ZILOG(port);
841 struct zilog_channel __iomem *channel;
842 unsigned long flags;
843
844 if (ZS_IS_CONS(up))
845 return;
846
847 spin_lock_irqsave(&port->lock, flags);
848
849 channel = ZILOG_CHANNEL_FROM_PORT(port);
850
851 /* Disable receiver and transmitter. */
852 up->curregs[R3] &= ~RxENAB;
853 up->curregs[R5] &= ~TxENAB;
854
855 /* Disable all interrupts and BRK assertion. */
856 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
857 up->curregs[R5] &= ~SND_BRK;
858 sunzilog_maybe_update_regs(up, channel);
859
860 spin_unlock_irqrestore(&port->lock, flags);
861}
862
863/* Shared by TTY driver and serial console setup. The port lock is held
864 * and local interrupts are disabled.
865 */
866static void
867sunzilog_convert_to_zs(struct uart_sunzilog_port *up, unsigned int cflag,
868 unsigned int iflag, int brg)
869{
870
871 up->curregs[R10] = NRZ;
872 up->curregs[R11] = TCBR | RCBR;
873
874 /* Program BAUD and clock source. */
875 up->curregs[R4] &= ~XCLK_MASK;
876 up->curregs[R4] |= X16CLK;
877 up->curregs[R12] = brg & 0xff;
878 up->curregs[R13] = (brg >> 8) & 0xff;
879 up->curregs[R14] = BRSRC | BRENAB;
880
881 /* Character size, stop bits, and parity. */
882 up->curregs[R3] &= ~RxN_MASK;
883 up->curregs[R5] &= ~TxN_MASK;
884 switch (cflag & CSIZE) {
885 case CS5:
886 up->curregs[R3] |= Rx5;
887 up->curregs[R5] |= Tx5;
888 up->parity_mask = 0x1f;
889 break;
890 case CS6:
891 up->curregs[R3] |= Rx6;
892 up->curregs[R5] |= Tx6;
893 up->parity_mask = 0x3f;
894 break;
895 case CS7:
896 up->curregs[R3] |= Rx7;
897 up->curregs[R5] |= Tx7;
898 up->parity_mask = 0x7f;
899 break;
900 case CS8:
901 default:
902 up->curregs[R3] |= Rx8;
903 up->curregs[R5] |= Tx8;
904 up->parity_mask = 0xff;
905 break;
906 };
907 up->curregs[R4] &= ~0x0c;
908 if (cflag & CSTOPB)
909 up->curregs[R4] |= SB2;
910 else
911 up->curregs[R4] |= SB1;
912 if (cflag & PARENB)
913 up->curregs[R4] |= PAR_ENAB;
914 else
915 up->curregs[R4] &= ~PAR_ENAB;
916 if (!(cflag & PARODD))
917 up->curregs[R4] |= PAR_EVEN;
918 else
919 up->curregs[R4] &= ~PAR_EVEN;
920
921 up->port.read_status_mask = Rx_OVR;
922 if (iflag & INPCK)
923 up->port.read_status_mask |= CRC_ERR | PAR_ERR;
924 if (iflag & (BRKINT | PARMRK))
925 up->port.read_status_mask |= BRK_ABRT;
926
927 up->port.ignore_status_mask = 0;
928 if (iflag & IGNPAR)
929 up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
930 if (iflag & IGNBRK) {
931 up->port.ignore_status_mask |= BRK_ABRT;
932 if (iflag & IGNPAR)
933 up->port.ignore_status_mask |= Rx_OVR;
934 }
935
936 if ((cflag & CREAD) == 0)
937 up->port.ignore_status_mask = 0xff;
938}
939
940/* The port lock is not held. */
941static void
942sunzilog_set_termios(struct uart_port *port, struct ktermios *termios,
943 struct ktermios *old)
944{
945 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
946 unsigned long flags;
947 int baud, brg;
948
949 baud = uart_get_baud_rate(port, termios, old, 1200, 76800);
950
951 spin_lock_irqsave(&up->port.lock, flags);
952
953 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
954
955 sunzilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
956
957 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
958 up->flags |= SUNZILOG_FLAG_MODEM_STATUS;
959 else
960 up->flags &= ~SUNZILOG_FLAG_MODEM_STATUS;
961
962 up->cflag = termios->c_cflag;
963
964 sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
965
966 uart_update_timeout(port, termios->c_cflag, baud);
967
968 spin_unlock_irqrestore(&up->port.lock, flags);
969}
970
971static const char *sunzilog_type(struct uart_port *port)
972{
973 struct uart_sunzilog_port *up = UART_ZILOG(port);
974
975 return (up->flags & SUNZILOG_FLAG_ESCC) ? "zs (ESCC)" : "zs";
976}
977
978/* We do not request/release mappings of the registers here, this
979 * happens at early serial probe time.
980 */
981static void sunzilog_release_port(struct uart_port *port)
982{
983}
984
985static int sunzilog_request_port(struct uart_port *port)
986{
987 return 0;
988}
989
990/* These do not need to do anything interesting either. */
991static void sunzilog_config_port(struct uart_port *port, int flags)
992{
993}
994
995/* We do not support letting the user mess with the divisor, IRQ, etc. */
996static int sunzilog_verify_port(struct uart_port *port, struct serial_struct *ser)
997{
998 return -EINVAL;
999}
1000
1001#ifdef CONFIG_CONSOLE_POLL
1002static int sunzilog_get_poll_char(struct uart_port *port)
1003{
1004 unsigned char ch, r1;
1005 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
1006 struct zilog_channel __iomem *channel
1007 = ZILOG_CHANNEL_FROM_PORT(&up->port);
1008
1009
1010 r1 = read_zsreg(channel, R1);
1011 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
1012 writeb(ERR_RES, &channel->control);
1013 ZSDELAY();
1014 ZS_WSYNC(channel);
1015 }
1016
1017 ch = readb(&channel->control);
1018 ZSDELAY();
1019
1020 /* This funny hack depends upon BRK_ABRT not interfering
1021 * with the other bits we care about in R1.
1022 */
1023 if (ch & BRK_ABRT)
1024 r1 |= BRK_ABRT;
1025
1026 if (!(ch & Rx_CH_AV))
1027 return NO_POLL_CHAR;
1028
1029 ch = readb(&channel->data);
1030 ZSDELAY();
1031
1032 ch &= up->parity_mask;
1033 return ch;
1034}
1035
1036static void sunzilog_put_poll_char(struct uart_port *port,
1037 unsigned char ch)
1038{
1039 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *)port;
1040
1041 sunzilog_putchar(&up->port, ch);
1042}
1043#endif /* CONFIG_CONSOLE_POLL */
1044
1045static struct uart_ops sunzilog_pops = {
1046 .tx_empty = sunzilog_tx_empty,
1047 .set_mctrl = sunzilog_set_mctrl,
1048 .get_mctrl = sunzilog_get_mctrl,
1049 .stop_tx = sunzilog_stop_tx,
1050 .start_tx = sunzilog_start_tx,
1051 .stop_rx = sunzilog_stop_rx,
1052 .enable_ms = sunzilog_enable_ms,
1053 .break_ctl = sunzilog_break_ctl,
1054 .startup = sunzilog_startup,
1055 .shutdown = sunzilog_shutdown,
1056 .set_termios = sunzilog_set_termios,
1057 .type = sunzilog_type,
1058 .release_port = sunzilog_release_port,
1059 .request_port = sunzilog_request_port,
1060 .config_port = sunzilog_config_port,
1061 .verify_port = sunzilog_verify_port,
1062#ifdef CONFIG_CONSOLE_POLL
1063 .poll_get_char = sunzilog_get_poll_char,
1064 .poll_put_char = sunzilog_put_poll_char,
1065#endif
1066};
1067
1068static int uart_chip_count;
1069static struct uart_sunzilog_port *sunzilog_port_table;
1070static struct zilog_layout __iomem **sunzilog_chip_regs;
1071
1072static struct uart_sunzilog_port *sunzilog_irq_chain;
1073
1074static struct uart_driver sunzilog_reg = {
1075 .owner = THIS_MODULE,
1076 .driver_name = "sunzilog",
1077 .dev_name = "ttyS",
1078 .major = TTY_MAJOR,
1079};
1080
1081static int __init sunzilog_alloc_tables(int num_sunzilog)
1082{
1083 struct uart_sunzilog_port *up;
1084 unsigned long size;
1085 int num_channels = num_sunzilog * 2;
1086 int i;
1087
1088 size = num_channels * sizeof(struct uart_sunzilog_port);
1089 sunzilog_port_table = kzalloc(size, GFP_KERNEL);
1090 if (!sunzilog_port_table)
1091 return -ENOMEM;
1092
1093 for (i = 0; i < num_channels; i++) {
1094 up = &sunzilog_port_table[i];
1095
1096 spin_lock_init(&up->port.lock);
1097
1098 if (i == 0)
1099 sunzilog_irq_chain = up;
1100
1101 if (i < num_channels - 1)
1102 up->next = up + 1;
1103 else
1104 up->next = NULL;
1105 }
1106
1107 size = num_sunzilog * sizeof(struct zilog_layout __iomem *);
1108 sunzilog_chip_regs = kzalloc(size, GFP_KERNEL);
1109 if (!sunzilog_chip_regs) {
1110 kfree(sunzilog_port_table);
1111 sunzilog_irq_chain = NULL;
1112 return -ENOMEM;
1113 }
1114
1115 return 0;
1116}
1117
1118static void sunzilog_free_tables(void)
1119{
1120 kfree(sunzilog_port_table);
1121 sunzilog_irq_chain = NULL;
1122 kfree(sunzilog_chip_regs);
1123}
1124
1125#define ZS_PUT_CHAR_MAX_DELAY 2000 /* 10 ms */
1126
1127static void sunzilog_putchar(struct uart_port *port, int ch)
1128{
1129 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
1130 int loops = ZS_PUT_CHAR_MAX_DELAY;
1131
1132 /* This is a timed polling loop so do not switch the explicit
1133 * udelay with ZSDELAY as that is a NOP on some platforms. -DaveM
1134 */
1135 do {
1136 unsigned char val = readb(&channel->control);
1137 if (val & Tx_BUF_EMP) {
1138 ZSDELAY();
1139 break;
1140 }
1141 udelay(5);
1142 } while (--loops);
1143
1144 writeb(ch, &channel->data);
1145 ZSDELAY();
1146 ZS_WSYNC(channel);
1147}
1148
1149#ifdef CONFIG_SERIO
1150
1151static DEFINE_SPINLOCK(sunzilog_serio_lock);
1152
1153static int sunzilog_serio_write(struct serio *serio, unsigned char ch)
1154{
1155 struct uart_sunzilog_port *up = serio->port_data;
1156 unsigned long flags;
1157
1158 spin_lock_irqsave(&sunzilog_serio_lock, flags);
1159
1160 sunzilog_putchar(&up->port, ch);
1161
1162 spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1163
1164 return 0;
1165}
1166
1167static int sunzilog_serio_open(struct serio *serio)
1168{
1169 struct uart_sunzilog_port *up = serio->port_data;
1170 unsigned long flags;
1171 int ret;
1172
1173 spin_lock_irqsave(&sunzilog_serio_lock, flags);
1174 if (!up->serio_open) {
1175 up->serio_open = 1;
1176 ret = 0;
1177 } else
1178 ret = -EBUSY;
1179 spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1180
1181 return ret;
1182}
1183
1184static void sunzilog_serio_close(struct serio *serio)
1185{
1186 struct uart_sunzilog_port *up = serio->port_data;
1187 unsigned long flags;
1188
1189 spin_lock_irqsave(&sunzilog_serio_lock, flags);
1190 up->serio_open = 0;
1191 spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1192}
1193
1194#endif /* CONFIG_SERIO */
1195
1196#ifdef CONFIG_SERIAL_SUNZILOG_CONSOLE
1197static void
1198sunzilog_console_write(struct console *con, const char *s, unsigned int count)
1199{
1200 struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1201 unsigned long flags;
1202 int locked = 1;
1203
1204 local_irq_save(flags);
1205 if (up->port.sysrq) {
1206 locked = 0;
1207 } else if (oops_in_progress) {
1208 locked = spin_trylock(&up->port.lock);
1209 } else
1210 spin_lock(&up->port.lock);
1211
1212 uart_console_write(&up->port, s, count, sunzilog_putchar);
1213 udelay(2);
1214
1215 if (locked)
1216 spin_unlock(&up->port.lock);
1217 local_irq_restore(flags);
1218}
1219
1220static int __init sunzilog_console_setup(struct console *con, char *options)
1221{
1222 struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1223 unsigned long flags;
1224 int baud, brg;
1225
1226 if (up->port.type != PORT_SUNZILOG)
1227 return -1;
1228
1229 printk(KERN_INFO "Console: ttyS%d (SunZilog zs%d)\n",
1230 (sunzilog_reg.minor - 64) + con->index, con->index);
1231
1232 /* Get firmware console settings. */
1233 sunserial_console_termios(con, up->port.dev->of_node);
1234
1235 /* Firmware console speed is limited to 150-->38400 baud so
1236 * this hackish cflag thing is OK.
1237 */
1238 switch (con->cflag & CBAUD) {
1239 case B150: baud = 150; break;
1240 case B300: baud = 300; break;
1241 case B600: baud = 600; break;
1242 case B1200: baud = 1200; break;
1243 case B2400: baud = 2400; break;
1244 case B4800: baud = 4800; break;
1245 default: case B9600: baud = 9600; break;
1246 case B19200: baud = 19200; break;
1247 case B38400: baud = 38400; break;
1248 };
1249
1250 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1251
1252 spin_lock_irqsave(&up->port.lock, flags);
1253
1254 up->curregs[R15] |= BRKIE;
1255 sunzilog_convert_to_zs(up, con->cflag, 0, brg);
1256
1257 sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1258 __sunzilog_startup(up);
1259
1260 spin_unlock_irqrestore(&up->port.lock, flags);
1261
1262 return 0;
1263}
1264
1265static struct console sunzilog_console_ops = {
1266 .name = "ttyS",
1267 .write = sunzilog_console_write,
1268 .device = uart_console_device,
1269 .setup = sunzilog_console_setup,
1270 .flags = CON_PRINTBUFFER,
1271 .index = -1,
1272 .data = &sunzilog_reg,
1273};
1274
1275static inline struct console *SUNZILOG_CONSOLE(void)
1276{
1277 return &sunzilog_console_ops;
1278}
1279
1280#else
1281#define SUNZILOG_CONSOLE() (NULL)
1282#endif
1283
1284static void __devinit sunzilog_init_kbdms(struct uart_sunzilog_port *up)
1285{
1286 int baud, brg;
1287
1288 if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
1289 up->cflag = B1200 | CS8 | CLOCAL | CREAD;
1290 baud = 1200;
1291 } else {
1292 up->cflag = B4800 | CS8 | CLOCAL | CREAD;
1293 baud = 4800;
1294 }
1295
1296 up->curregs[R15] |= BRKIE;
1297 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1298 sunzilog_convert_to_zs(up, up->cflag, 0, brg);
1299 sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1300 __sunzilog_startup(up);
1301}
1302
1303#ifdef CONFIG_SERIO
1304static void __devinit sunzilog_register_serio(struct uart_sunzilog_port *up)
1305{
1306 struct serio *serio = &up->serio;
1307
1308 serio->port_data = up;
1309
1310 serio->id.type = SERIO_RS232;
1311 if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
1312 serio->id.proto = SERIO_SUNKBD;
1313 strlcpy(serio->name, "zskbd", sizeof(serio->name));
1314 } else {
1315 serio->id.proto = SERIO_SUN;
1316 serio->id.extra = 1;
1317 strlcpy(serio->name, "zsms", sizeof(serio->name));
1318 }
1319 strlcpy(serio->phys,
1320 ((up->flags & SUNZILOG_FLAG_CONS_KEYB) ?
1321 "zs/serio0" : "zs/serio1"),
1322 sizeof(serio->phys));
1323
1324 serio->write = sunzilog_serio_write;
1325 serio->open = sunzilog_serio_open;
1326 serio->close = sunzilog_serio_close;
1327 serio->dev.parent = up->port.dev;
1328
1329 serio_register_port(serio);
1330}
1331#endif
1332
1333static void __devinit sunzilog_init_hw(struct uart_sunzilog_port *up)
1334{
1335 struct zilog_channel __iomem *channel;
1336 unsigned long flags;
1337 int baud, brg;
1338
1339 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1340
1341 spin_lock_irqsave(&up->port.lock, flags);
1342 if (ZS_IS_CHANNEL_A(up)) {
1343 write_zsreg(channel, R9, FHWRES);
1344 ZSDELAY_LONG();
1345 (void) read_zsreg(channel, R0);
1346 }
1347
1348 if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
1349 SUNZILOG_FLAG_CONS_MOUSE)) {
1350 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1351 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1352 up->curregs[R3] = RxENAB | Rx8;
1353 up->curregs[R5] = TxENAB | Tx8;
1354 up->curregs[R6] = 0x00; /* SDLC Address */
1355 up->curregs[R7] = 0x7E; /* SDLC Flag */
1356 up->curregs[R9] = NV;
1357 up->curregs[R7p] = 0x00;
1358 sunzilog_init_kbdms(up);
1359 /* Only enable interrupts if an ISR handler available */
1360 if (up->flags & SUNZILOG_FLAG_ISR_HANDLER)
1361 up->curregs[R9] |= MIE;
1362 write_zsreg(channel, R9, up->curregs[R9]);
1363 } else {
1364 /* Normal serial TTY. */
1365 up->parity_mask = 0xff;
1366 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1367 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1368 up->curregs[R3] = RxENAB | Rx8;
1369 up->curregs[R5] = TxENAB | Tx8;
1370 up->curregs[R6] = 0x00; /* SDLC Address */
1371 up->curregs[R7] = 0x7E; /* SDLC Flag */
1372 up->curregs[R9] = NV;
1373 up->curregs[R10] = NRZ;
1374 up->curregs[R11] = TCBR | RCBR;
1375 baud = 9600;
1376 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1377 up->curregs[R12] = (brg & 0xff);
1378 up->curregs[R13] = (brg >> 8) & 0xff;
1379 up->curregs[R14] = BRSRC | BRENAB;
1380 up->curregs[R15] = FIFOEN; /* Use FIFO if on ESCC */
1381 up->curregs[R7p] = TxFIFO_LVL | RxFIFO_LVL;
1382 if (__load_zsregs(channel, up->curregs)) {
1383 up->flags |= SUNZILOG_FLAG_ESCC;
1384 }
1385 /* Only enable interrupts if an ISR handler available */
1386 if (up->flags & SUNZILOG_FLAG_ISR_HANDLER)
1387 up->curregs[R9] |= MIE;
1388 write_zsreg(channel, R9, up->curregs[R9]);
1389 }
1390
1391 spin_unlock_irqrestore(&up->port.lock, flags);
1392
1393#ifdef CONFIG_SERIO
1394 if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
1395 SUNZILOG_FLAG_CONS_MOUSE))
1396 sunzilog_register_serio(up);
1397#endif
1398}
1399
1400static int zilog_irq = -1;
1401
1402static int __devinit zs_probe(struct platform_device *op, const struct of_device_id *match)
1403{
1404 static int kbm_inst, uart_inst;
1405 int inst;
1406 struct uart_sunzilog_port *up;
1407 struct zilog_layout __iomem *rp;
1408 int keyboard_mouse = 0;
1409 int err;
1410
1411 if (of_find_property(op->dev.of_node, "keyboard", NULL))
1412 keyboard_mouse = 1;
1413
1414 /* uarts must come before keyboards/mice */
1415 if (keyboard_mouse)
1416 inst = uart_chip_count + kbm_inst;
1417 else
1418 inst = uart_inst;
1419
1420 sunzilog_chip_regs[inst] = of_ioremap(&op->resource[0], 0,
1421 sizeof(struct zilog_layout),
1422 "zs");
1423 if (!sunzilog_chip_regs[inst])
1424 return -ENOMEM;
1425
1426 rp = sunzilog_chip_regs[inst];
1427
1428 if (zilog_irq == -1)
1429 zilog_irq = op->archdata.irqs[0];
1430
1431 up = &sunzilog_port_table[inst * 2];
1432
1433 /* Channel A */
1434 up[0].port.mapbase = op->resource[0].start + 0x00;
1435 up[0].port.membase = (void __iomem *) &rp->channelA;
1436 up[0].port.iotype = UPIO_MEM;
1437 up[0].port.irq = op->archdata.irqs[0];
1438 up[0].port.uartclk = ZS_CLOCK;
1439 up[0].port.fifosize = 1;
1440 up[0].port.ops = &sunzilog_pops;
1441 up[0].port.type = PORT_SUNZILOG;
1442 up[0].port.flags = 0;
1443 up[0].port.line = (inst * 2) + 0;
1444 up[0].port.dev = &op->dev;
1445 up[0].flags |= SUNZILOG_FLAG_IS_CHANNEL_A;
1446 if (keyboard_mouse)
1447 up[0].flags |= SUNZILOG_FLAG_CONS_KEYB;
1448 sunzilog_init_hw(&up[0]);
1449
1450 /* Channel B */
1451 up[1].port.mapbase = op->resource[0].start + 0x04;
1452 up[1].port.membase = (void __iomem *) &rp->channelB;
1453 up[1].port.iotype = UPIO_MEM;
1454 up[1].port.irq = op->archdata.irqs[0];
1455 up[1].port.uartclk = ZS_CLOCK;
1456 up[1].port.fifosize = 1;
1457 up[1].port.ops = &sunzilog_pops;
1458 up[1].port.type = PORT_SUNZILOG;
1459 up[1].port.flags = 0;
1460 up[1].port.line = (inst * 2) + 1;
1461 up[1].port.dev = &op->dev;
1462 up[1].flags |= 0;
1463 if (keyboard_mouse)
1464 up[1].flags |= SUNZILOG_FLAG_CONS_MOUSE;
1465 sunzilog_init_hw(&up[1]);
1466
1467 if (!keyboard_mouse) {
1468 if (sunserial_console_match(SUNZILOG_CONSOLE(), op->dev.of_node,
1469 &sunzilog_reg, up[0].port.line,
1470 false))
1471 up->flags |= SUNZILOG_FLAG_IS_CONS;
1472 err = uart_add_one_port(&sunzilog_reg, &up[0].port);
1473 if (err) {
1474 of_iounmap(&op->resource[0],
1475 rp, sizeof(struct zilog_layout));
1476 return err;
1477 }
1478 if (sunserial_console_match(SUNZILOG_CONSOLE(), op->dev.of_node,
1479 &sunzilog_reg, up[1].port.line,
1480 false))
1481 up->flags |= SUNZILOG_FLAG_IS_CONS;
1482 err = uart_add_one_port(&sunzilog_reg, &up[1].port);
1483 if (err) {
1484 uart_remove_one_port(&sunzilog_reg, &up[0].port);
1485 of_iounmap(&op->resource[0],
1486 rp, sizeof(struct zilog_layout));
1487 return err;
1488 }
1489 uart_inst++;
1490 } else {
1491 printk(KERN_INFO "%s: Keyboard at MMIO 0x%llx (irq = %d) "
1492 "is a %s\n",
1493 dev_name(&op->dev),
1494 (unsigned long long) up[0].port.mapbase,
1495 op->archdata.irqs[0], sunzilog_type(&up[0].port));
1496 printk(KERN_INFO "%s: Mouse at MMIO 0x%llx (irq = %d) "
1497 "is a %s\n",
1498 dev_name(&op->dev),
1499 (unsigned long long) up[1].port.mapbase,
1500 op->archdata.irqs[0], sunzilog_type(&up[1].port));
1501 kbm_inst++;
1502 }
1503
1504 dev_set_drvdata(&op->dev, &up[0]);
1505
1506 return 0;
1507}
1508
1509static void __devexit zs_remove_one(struct uart_sunzilog_port *up)
1510{
1511 if (ZS_IS_KEYB(up) || ZS_IS_MOUSE(up)) {
1512#ifdef CONFIG_SERIO
1513 serio_unregister_port(&up->serio);
1514#endif
1515 } else
1516 uart_remove_one_port(&sunzilog_reg, &up->port);
1517}
1518
1519static int __devexit zs_remove(struct platform_device *op)
1520{
1521 struct uart_sunzilog_port *up = dev_get_drvdata(&op->dev);
1522 struct zilog_layout __iomem *regs;
1523
1524 zs_remove_one(&up[0]);
1525 zs_remove_one(&up[1]);
1526
1527 regs = sunzilog_chip_regs[up[0].port.line / 2];
1528 of_iounmap(&op->resource[0], regs, sizeof(struct zilog_layout));
1529
1530 dev_set_drvdata(&op->dev, NULL);
1531
1532 return 0;
1533}
1534
1535static const struct of_device_id zs_match[] = {
1536 {
1537 .name = "zs",
1538 },
1539 {},
1540};
1541MODULE_DEVICE_TABLE(of, zs_match);
1542
1543static struct of_platform_driver zs_driver = {
1544 .driver = {
1545 .name = "zs",
1546 .owner = THIS_MODULE,
1547 .of_match_table = zs_match,
1548 },
1549 .probe = zs_probe,
1550 .remove = __devexit_p(zs_remove),
1551};
1552
1553static int __init sunzilog_init(void)
1554{
1555 struct device_node *dp;
1556 int err;
1557 int num_keybms = 0;
1558 int num_sunzilog = 0;
1559
1560 for_each_node_by_name(dp, "zs") {
1561 num_sunzilog++;
1562 if (of_find_property(dp, "keyboard", NULL))
1563 num_keybms++;
1564 }
1565
1566 if (num_sunzilog) {
1567 err = sunzilog_alloc_tables(num_sunzilog);
1568 if (err)
1569 goto out;
1570
1571 uart_chip_count = num_sunzilog - num_keybms;
1572
1573 err = sunserial_register_minors(&sunzilog_reg,
1574 uart_chip_count * 2);
1575 if (err)
1576 goto out_free_tables;
1577 }
1578
1579 err = of_register_platform_driver(&zs_driver);
1580 if (err)
1581 goto out_unregister_uart;
1582
1583 if (zilog_irq != -1) {
1584 struct uart_sunzilog_port *up = sunzilog_irq_chain;
1585 err = request_irq(zilog_irq, sunzilog_interrupt, IRQF_SHARED,
1586 "zs", sunzilog_irq_chain);
1587 if (err)
1588 goto out_unregister_driver;
1589
1590 /* Enable Interrupts */
1591 while (up) {
1592 struct zilog_channel __iomem *channel;
1593
1594 /* printk (KERN_INFO "Enable IRQ for ZILOG Hardware %p\n", up); */
1595 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1596 up->flags |= SUNZILOG_FLAG_ISR_HANDLER;
1597 up->curregs[R9] |= MIE;
1598 write_zsreg(channel, R9, up->curregs[R9]);
1599 up = up->next;
1600 }
1601 }
1602
1603out:
1604 return err;
1605
1606out_unregister_driver:
1607 of_unregister_platform_driver(&zs_driver);
1608
1609out_unregister_uart:
1610 if (num_sunzilog) {
1611 sunserial_unregister_minors(&sunzilog_reg, num_sunzilog);
1612 sunzilog_reg.cons = NULL;
1613 }
1614
1615out_free_tables:
1616 sunzilog_free_tables();
1617 goto out;
1618}
1619
1620static void __exit sunzilog_exit(void)
1621{
1622 of_unregister_platform_driver(&zs_driver);
1623
1624 if (zilog_irq != -1) {
1625 struct uart_sunzilog_port *up = sunzilog_irq_chain;
1626
1627 /* Disable Interrupts */
1628 while (up) {
1629 struct zilog_channel __iomem *channel;
1630
1631 /* printk (KERN_INFO "Disable IRQ for ZILOG Hardware %p\n", up); */
1632 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1633 up->flags &= ~SUNZILOG_FLAG_ISR_HANDLER;
1634 up->curregs[R9] &= ~MIE;
1635 write_zsreg(channel, R9, up->curregs[R9]);
1636 up = up->next;
1637 }
1638
1639 free_irq(zilog_irq, sunzilog_irq_chain);
1640 zilog_irq = -1;
1641 }
1642
1643 if (sunzilog_reg.nr) {
1644 sunserial_unregister_minors(&sunzilog_reg, sunzilog_reg.nr);
1645 sunzilog_free_tables();
1646 }
1647}
1648
1649module_init(sunzilog_init);
1650module_exit(sunzilog_exit);
1651
1652MODULE_AUTHOR("David S. Miller");
1653MODULE_DESCRIPTION("Sun Zilog serial port driver");
1654MODULE_VERSION("2.0");
1655MODULE_LICENSE("GPL");
diff --git a/drivers/serial/sunzilog.h b/drivers/serial/sunzilog.h
deleted file mode 100644
index 5dec7b47cc38..000000000000
--- a/drivers/serial/sunzilog.h
+++ /dev/null
@@ -1,289 +0,0 @@
1#ifndef _SUNZILOG_H
2#define _SUNZILOG_H
3
4struct zilog_channel {
5 volatile unsigned char control;
6 volatile unsigned char __pad1;
7 volatile unsigned char data;
8 volatile unsigned char __pad2;
9};
10
11struct zilog_layout {
12 struct zilog_channel channelB;
13 struct zilog_channel channelA;
14};
15
16#define NUM_ZSREGS 17
17#define R7p 16 /* Written as R7 with P15 bit 0 set */
18
19/* Conversion routines to/from brg time constants from/to bits
20 * per second.
21 */
22#define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
23#define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
24
25/* The Zilog register set */
26
27#define FLAG 0x7e
28
29/* Write Register 0 */
30#define R0 0 /* Register selects */
31#define R1 1
32#define R2 2
33#define R3 3
34#define R4 4
35#define R5 5
36#define R6 6
37#define R7 7
38#define R8 8
39#define R9 9
40#define R10 10
41#define R11 11
42#define R12 12
43#define R13 13
44#define R14 14
45#define R15 15
46
47#define NULLCODE 0 /* Null Code */
48#define POINT_HIGH 0x8 /* Select upper half of registers */
49#define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
50#define SEND_ABORT 0x18 /* HDLC Abort */
51#define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
52#define RES_Tx_P 0x28 /* Reset TxINT Pending */
53#define ERR_RES 0x30 /* Error Reset */
54#define RES_H_IUS 0x38 /* Reset highest IUS */
55
56#define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
57#define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
58#define RES_EOM_L 0xC0 /* Reset EOM latch */
59
60/* Write Register 1 */
61
62#define EXT_INT_ENAB 0x1 /* Ext Int Enable */
63#define TxINT_ENAB 0x2 /* Tx Int Enable */
64#define PAR_SPEC 0x4 /* Parity is special condition */
65
66#define RxINT_DISAB 0 /* Rx Int Disable */
67#define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
68#define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */
69#define INT_ERR_Rx 0x18 /* Int on error only */
70#define RxINT_MASK 0x18
71
72#define WT_RDY_RT 0x20 /* Wait/Ready on R/T */
73#define WT_FN_RDYFN 0x40 /* Wait/FN/Ready FN */
74#define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
75
76/* Write Register #2 (Interrupt Vector) */
77
78/* Write Register 3 */
79
80#define RxENAB 0x1 /* Rx Enable */
81#define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
82#define ADD_SM 0x4 /* Address Search Mode (SDLC) */
83#define RxCRC_ENAB 0x8 /* Rx CRC Enable */
84#define ENT_HM 0x10 /* Enter Hunt Mode */
85#define AUTO_ENAB 0x20 /* Auto Enables */
86#define Rx5 0x0 /* Rx 5 Bits/Character */
87#define Rx7 0x40 /* Rx 7 Bits/Character */
88#define Rx6 0x80 /* Rx 6 Bits/Character */
89#define Rx8 0xc0 /* Rx 8 Bits/Character */
90#define RxN_MASK 0xc0
91
92/* Write Register 4 */
93
94#define PAR_ENAB 0x1 /* Parity Enable */
95#define PAR_EVEN 0x2 /* Parity Even/Odd* */
96
97#define SYNC_ENAB 0 /* Sync Modes Enable */
98#define SB1 0x4 /* 1 stop bit/char */
99#define SB15 0x8 /* 1.5 stop bits/char */
100#define SB2 0xc /* 2 stop bits/char */
101
102#define MONSYNC 0 /* 8 Bit Sync character */
103#define BISYNC 0x10 /* 16 bit sync character */
104#define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
105#define EXTSYNC 0x30 /* External Sync Mode */
106
107#define X1CLK 0x0 /* x1 clock mode */
108#define X16CLK 0x40 /* x16 clock mode */
109#define X32CLK 0x80 /* x32 clock mode */
110#define X64CLK 0xC0 /* x64 clock mode */
111#define XCLK_MASK 0xC0
112
113/* Write Register 5 */
114
115#define TxCRC_ENAB 0x1 /* Tx CRC Enable */
116#define RTS 0x2 /* RTS */
117#define SDLC_CRC 0x4 /* SDLC/CRC-16 */
118#define TxENAB 0x8 /* Tx Enable */
119#define SND_BRK 0x10 /* Send Break */
120#define Tx5 0x0 /* Tx 5 bits (or less)/character */
121#define Tx7 0x20 /* Tx 7 bits/character */
122#define Tx6 0x40 /* Tx 6 bits/character */
123#define Tx8 0x60 /* Tx 8 bits/character */
124#define TxN_MASK 0x60
125#define DTR 0x80 /* DTR */
126
127/* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
128
129/* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
130
131/* Write Register 7' (ESCC Only) */
132#define AUTO_TxFLAG 1 /* Automatic Tx SDLC Flag */
133#define AUTO_EOM_RST 2 /* Automatic EOM Reset */
134#define AUTOnRTS 4 /* Automatic /RTS pin deactivation */
135#define RxFIFO_LVL 8 /* Receive FIFO interrupt level */
136#define nDTRnREQ 0x10 /* /DTR/REQ timing */
137#define TxFIFO_LVL 0x20 /* Transmit FIFO interrupt level */
138#define EXT_RD_EN 0x40 /* Extended read register enable */
139
140/* Write Register 8 (transmit buffer) */
141
142/* Write Register 9 (Master interrupt control) */
143#define VIS 1 /* Vector Includes Status */
144#define NV 2 /* No Vector */
145#define DLC 4 /* Disable Lower Chain */
146#define MIE 8 /* Master Interrupt Enable */
147#define STATHI 0x10 /* Status high */
148#define SWIACK 0x20 /* Software Interrupt Ack (not on NMOS) */
149#define NORESET 0 /* No reset on write to R9 */
150#define CHRB 0x40 /* Reset channel B */
151#define CHRA 0x80 /* Reset channel A */
152#define FHWRES 0xc0 /* Force hardware reset */
153
154/* Write Register 10 (misc control bits) */
155#define BIT6 1 /* 6 bit/8bit sync */
156#define LOOPMODE 2 /* SDLC Loop mode */
157#define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */
158#define MARKIDLE 8 /* Mark/flag on idle */
159#define GAOP 0x10 /* Go active on poll */
160#define NRZ 0 /* NRZ mode */
161#define NRZI 0x20 /* NRZI mode */
162#define FM1 0x40 /* FM1 (transition = 1) */
163#define FM0 0x60 /* FM0 (transition = 0) */
164#define CRCPS 0x80 /* CRC Preset I/O */
165
166/* Write Register 11 (Clock Mode control) */
167#define TRxCXT 0 /* TRxC = Xtal output */
168#define TRxCTC 1 /* TRxC = Transmit clock */
169#define TRxCBR 2 /* TRxC = BR Generator Output */
170#define TRxCDP 3 /* TRxC = DPLL output */
171#define TRxCOI 4 /* TRxC O/I */
172#define TCRTxCP 0 /* Transmit clock = RTxC pin */
173#define TCTRxCP 8 /* Transmit clock = TRxC pin */
174#define TCBR 0x10 /* Transmit clock = BR Generator output */
175#define TCDPLL 0x18 /* Transmit clock = DPLL output */
176#define RCRTxCP 0 /* Receive clock = RTxC pin */
177#define RCTRxCP 0x20 /* Receive clock = TRxC pin */
178#define RCBR 0x40 /* Receive clock = BR Generator output */
179#define RCDPLL 0x60 /* Receive clock = DPLL output */
180#define RTxCX 0x80 /* RTxC Xtal/No Xtal */
181
182/* Write Register 12 (lower byte of baud rate generator time constant) */
183
184/* Write Register 13 (upper byte of baud rate generator time constant) */
185
186/* Write Register 14 (Misc control bits) */
187#define BRENAB 1 /* Baud rate generator enable */
188#define BRSRC 2 /* Baud rate generator source */
189#define DTRREQ 4 /* DTR/Request function */
190#define AUTOECHO 8 /* Auto Echo */
191#define LOOPBAK 0x10 /* Local loopback */
192#define SEARCH 0x20 /* Enter search mode */
193#define RMC 0x40 /* Reset missing clock */
194#define DISDPLL 0x60 /* Disable DPLL */
195#define SSBR 0x80 /* Set DPLL source = BR generator */
196#define SSRTxC 0xa0 /* Set DPLL source = RTxC */
197#define SFMM 0xc0 /* Set FM mode */
198#define SNRZI 0xe0 /* Set NRZI mode */
199
200/* Write Register 15 (external/status interrupt control) */
201#define WR7pEN 1 /* WR7' Enable (ESCC only) */
202#define ZCIE 2 /* Zero count IE */
203#define FIFOEN 4 /* FIFO Enable (ESCC only) */
204#define DCDIE 8 /* DCD IE */
205#define SYNCIE 0x10 /* Sync/hunt IE */
206#define CTSIE 0x20 /* CTS IE */
207#define TxUIE 0x40 /* Tx Underrun/EOM IE */
208#define BRKIE 0x80 /* Break/Abort IE */
209
210
211/* Read Register 0 */
212#define Rx_CH_AV 0x1 /* Rx Character Available */
213#define ZCOUNT 0x2 /* Zero count */
214#define Tx_BUF_EMP 0x4 /* Tx Buffer empty */
215#define DCD 0x8 /* DCD */
216#define SYNC 0x10 /* Sync/hunt */
217#define CTS 0x20 /* CTS */
218#define TxEOM 0x40 /* Tx underrun */
219#define BRK_ABRT 0x80 /* Break/Abort */
220
221/* Read Register 1 */
222#define ALL_SNT 0x1 /* All sent */
223/* Residue Data for 8 Rx bits/char programmed */
224#define RES3 0x8 /* 0/3 */
225#define RES4 0x4 /* 0/4 */
226#define RES5 0xc /* 0/5 */
227#define RES6 0x2 /* 0/6 */
228#define RES7 0xa /* 0/7 */
229#define RES8 0x6 /* 0/8 */
230#define RES18 0xe /* 1/8 */
231#define RES28 0x0 /* 2/8 */
232/* Special Rx Condition Interrupts */
233#define PAR_ERR 0x10 /* Parity error */
234#define Rx_OVR 0x20 /* Rx Overrun Error */
235#define CRC_ERR 0x40 /* CRC/Framing Error */
236#define END_FR 0x80 /* End of Frame (SDLC) */
237
238/* Read Register 2 (channel b only) - Interrupt vector */
239#define CHB_Tx_EMPTY 0x00
240#define CHB_EXT_STAT 0x02
241#define CHB_Rx_AVAIL 0x04
242#define CHB_SPECIAL 0x06
243#define CHA_Tx_EMPTY 0x08
244#define CHA_EXT_STAT 0x0a
245#define CHA_Rx_AVAIL 0x0c
246#define CHA_SPECIAL 0x0e
247#define STATUS_MASK 0x0e
248
249/* Read Register 3 (interrupt pending register) ch a only */
250#define CHBEXT 0x1 /* Channel B Ext/Stat IP */
251#define CHBTxIP 0x2 /* Channel B Tx IP */
252#define CHBRxIP 0x4 /* Channel B Rx IP */
253#define CHAEXT 0x8 /* Channel A Ext/Stat IP */
254#define CHATxIP 0x10 /* Channel A Tx IP */
255#define CHARxIP 0x20 /* Channel A Rx IP */
256
257/* Read Register 6 (LSB frame byte count [Not on NMOS]) */
258
259/* Read Register 7 (MSB frame byte count and FIFO status [Not on NMOS]) */
260
261/* Read Register 8 (receive data register) */
262
263/* Read Register 10 (misc status bits) */
264#define ONLOOP 2 /* On loop */
265#define LOOPSEND 0x10 /* Loop sending */
266#define CLK2MIS 0x40 /* Two clocks missing */
267#define CLK1MIS 0x80 /* One clock missing */
268
269/* Read Register 12 (lower byte of baud rate generator constant) */
270
271/* Read Register 13 (upper byte of baud rate generator constant) */
272
273/* Read Register 15 (value of WR 15) */
274
275/* Misc macros */
276#define ZS_CLEARERR(channel) do { sbus_writeb(ERR_RES, &channel->control); \
277 udelay(5); } while(0)
278
279#define ZS_CLEARSTAT(channel) do { sbus_writeb(RES_EXT_INT, &channel->control); \
280 udelay(5); } while(0)
281
282#define ZS_CLEARFIFO(channel) do { sbus_readb(&channel->data); \
283 udelay(2); \
284 sbus_readb(&channel->data); \
285 udelay(2); \
286 sbus_readb(&channel->data); \
287 udelay(2); } while(0)
288
289#endif /* _SUNZILOG_H */
diff --git a/drivers/serial/timbuart.c b/drivers/serial/timbuart.c
deleted file mode 100644
index 1f36b7eb7351..000000000000
--- a/drivers/serial/timbuart.c
+++ /dev/null
@@ -1,531 +0,0 @@
1/*
2 * timbuart.c timberdale FPGA UART driver
3 * Copyright (c) 2009 Intel Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19/* Supports:
20 * Timberdale FPGA UART
21 */
22
23#include <linux/pci.h>
24#include <linux/interrupt.h>
25#include <linux/serial_core.h>
26#include <linux/kernel.h>
27#include <linux/platform_device.h>
28#include <linux/ioport.h>
29#include <linux/slab.h>
30
31#include "timbuart.h"
32
33struct timbuart_port {
34 struct uart_port port;
35 struct tasklet_struct tasklet;
36 int usedma;
37 u32 last_ier;
38 struct platform_device *dev;
39};
40
41static int baudrates[] = {9600, 19200, 38400, 57600, 115200, 230400, 460800,
42 921600, 1843200, 3250000};
43
44static void timbuart_mctrl_check(struct uart_port *port, u32 isr, u32 *ier);
45
46static irqreturn_t timbuart_handleinterrupt(int irq, void *devid);
47
48static void timbuart_stop_rx(struct uart_port *port)
49{
50 /* spin lock held by upper layer, disable all RX interrupts */
51 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~RXFLAGS;
52 iowrite32(ier, port->membase + TIMBUART_IER);
53}
54
55static void timbuart_stop_tx(struct uart_port *port)
56{
57 /* spinlock held by upper layer, disable TX interrupt */
58 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~TXBAE;
59 iowrite32(ier, port->membase + TIMBUART_IER);
60}
61
62static void timbuart_start_tx(struct uart_port *port)
63{
64 struct timbuart_port *uart =
65 container_of(port, struct timbuart_port, port);
66
67 /* do not transfer anything here -> fire off the tasklet */
68 tasklet_schedule(&uart->tasklet);
69}
70
71static unsigned int timbuart_tx_empty(struct uart_port *port)
72{
73 u32 isr = ioread32(port->membase + TIMBUART_ISR);
74
75 return (isr & TXBE) ? TIOCSER_TEMT : 0;
76}
77
78static void timbuart_flush_buffer(struct uart_port *port)
79{
80 if (!timbuart_tx_empty(port)) {
81 u8 ctl = ioread8(port->membase + TIMBUART_CTRL) |
82 TIMBUART_CTRL_FLSHTX;
83
84 iowrite8(ctl, port->membase + TIMBUART_CTRL);
85 iowrite32(TXBF, port->membase + TIMBUART_ISR);
86 }
87}
88
89static void timbuart_rx_chars(struct uart_port *port)
90{
91 struct tty_struct *tty = port->state->port.tty;
92
93 while (ioread32(port->membase + TIMBUART_ISR) & RXDP) {
94 u8 ch = ioread8(port->membase + TIMBUART_RXFIFO);
95 port->icount.rx++;
96 tty_insert_flip_char(tty, ch, TTY_NORMAL);
97 }
98
99 spin_unlock(&port->lock);
100 tty_flip_buffer_push(port->state->port.tty);
101 spin_lock(&port->lock);
102
103 dev_dbg(port->dev, "%s - total read %d bytes\n",
104 __func__, port->icount.rx);
105}
106
107static void timbuart_tx_chars(struct uart_port *port)
108{
109 struct circ_buf *xmit = &port->state->xmit;
110
111 while (!(ioread32(port->membase + TIMBUART_ISR) & TXBF) &&
112 !uart_circ_empty(xmit)) {
113 iowrite8(xmit->buf[xmit->tail],
114 port->membase + TIMBUART_TXFIFO);
115 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
116 port->icount.tx++;
117 }
118
119 dev_dbg(port->dev,
120 "%s - total written %d bytes, CTL: %x, RTS: %x, baud: %x\n",
121 __func__,
122 port->icount.tx,
123 ioread8(port->membase + TIMBUART_CTRL),
124 port->mctrl & TIOCM_RTS,
125 ioread8(port->membase + TIMBUART_BAUDRATE));
126}
127
128static void timbuart_handle_tx_port(struct uart_port *port, u32 isr, u32 *ier)
129{
130 struct timbuart_port *uart =
131 container_of(port, struct timbuart_port, port);
132 struct circ_buf *xmit = &port->state->xmit;
133
134 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
135 return;
136
137 if (port->x_char)
138 return;
139
140 if (isr & TXFLAGS) {
141 timbuart_tx_chars(port);
142 /* clear all TX interrupts */
143 iowrite32(TXFLAGS, port->membase + TIMBUART_ISR);
144
145 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
146 uart_write_wakeup(port);
147 } else
148 /* Re-enable any tx interrupt */
149 *ier |= uart->last_ier & TXFLAGS;
150
151 /* enable interrupts if there are chars in the transmit buffer,
152 * Or if we delivered some bytes and want the almost empty interrupt
153 * we wake up the upper layer later when we got the interrupt
154 * to give it some time to go out...
155 */
156 if (!uart_circ_empty(xmit))
157 *ier |= TXBAE;
158
159 dev_dbg(port->dev, "%s - leaving\n", __func__);
160}
161
162void timbuart_handle_rx_port(struct uart_port *port, u32 isr, u32 *ier)
163{
164 if (isr & RXFLAGS) {
165 /* Some RX status is set */
166 if (isr & RXBF) {
167 u8 ctl = ioread8(port->membase + TIMBUART_CTRL) |
168 TIMBUART_CTRL_FLSHRX;
169 iowrite8(ctl, port->membase + TIMBUART_CTRL);
170 port->icount.overrun++;
171 } else if (isr & (RXDP))
172 timbuart_rx_chars(port);
173
174 /* ack all RX interrupts */
175 iowrite32(RXFLAGS, port->membase + TIMBUART_ISR);
176 }
177
178 /* always have the RX interrupts enabled */
179 *ier |= RXBAF | RXBF | RXTT;
180
181 dev_dbg(port->dev, "%s - leaving\n", __func__);
182}
183
184void timbuart_tasklet(unsigned long arg)
185{
186 struct timbuart_port *uart = (struct timbuart_port *)arg;
187 u32 isr, ier = 0;
188
189 spin_lock(&uart->port.lock);
190
191 isr = ioread32(uart->port.membase + TIMBUART_ISR);
192 dev_dbg(uart->port.dev, "%s ISR: %x\n", __func__, isr);
193
194 if (!uart->usedma)
195 timbuart_handle_tx_port(&uart->port, isr, &ier);
196
197 timbuart_mctrl_check(&uart->port, isr, &ier);
198
199 if (!uart->usedma)
200 timbuart_handle_rx_port(&uart->port, isr, &ier);
201
202 iowrite32(ier, uart->port.membase + TIMBUART_IER);
203
204 spin_unlock(&uart->port.lock);
205 dev_dbg(uart->port.dev, "%s leaving\n", __func__);
206}
207
208static unsigned int timbuart_get_mctrl(struct uart_port *port)
209{
210 u8 cts = ioread8(port->membase + TIMBUART_CTRL);
211 dev_dbg(port->dev, "%s - cts %x\n", __func__, cts);
212
213 if (cts & TIMBUART_CTRL_CTS)
214 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
215 else
216 return TIOCM_DSR | TIOCM_CAR;
217}
218
219static void timbuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
220{
221 dev_dbg(port->dev, "%s - %x\n", __func__, mctrl);
222
223 if (mctrl & TIOCM_RTS)
224 iowrite8(TIMBUART_CTRL_RTS, port->membase + TIMBUART_CTRL);
225 else
226 iowrite8(0, port->membase + TIMBUART_CTRL);
227}
228
229static void timbuart_mctrl_check(struct uart_port *port, u32 isr, u32 *ier)
230{
231 unsigned int cts;
232
233 if (isr & CTS_DELTA) {
234 /* ack */
235 iowrite32(CTS_DELTA, port->membase + TIMBUART_ISR);
236 cts = timbuart_get_mctrl(port);
237 uart_handle_cts_change(port, cts & TIOCM_CTS);
238 wake_up_interruptible(&port->state->port.delta_msr_wait);
239 }
240
241 *ier |= CTS_DELTA;
242}
243
244static void timbuart_enable_ms(struct uart_port *port)
245{
246 /* N/A */
247}
248
249static void timbuart_break_ctl(struct uart_port *port, int ctl)
250{
251 /* N/A */
252}
253
254static int timbuart_startup(struct uart_port *port)
255{
256 struct timbuart_port *uart =
257 container_of(port, struct timbuart_port, port);
258
259 dev_dbg(port->dev, "%s\n", __func__);
260
261 iowrite8(TIMBUART_CTRL_FLSHRX, port->membase + TIMBUART_CTRL);
262 iowrite32(0x1ff, port->membase + TIMBUART_ISR);
263 /* Enable all but TX interrupts */
264 iowrite32(RXBAF | RXBF | RXTT | CTS_DELTA,
265 port->membase + TIMBUART_IER);
266
267 return request_irq(port->irq, timbuart_handleinterrupt, IRQF_SHARED,
268 "timb-uart", uart);
269}
270
271static void timbuart_shutdown(struct uart_port *port)
272{
273 struct timbuart_port *uart =
274 container_of(port, struct timbuart_port, port);
275 dev_dbg(port->dev, "%s\n", __func__);
276 free_irq(port->irq, uart);
277 iowrite32(0, port->membase + TIMBUART_IER);
278}
279
280static int get_bindex(int baud)
281{
282 int i;
283
284 for (i = 0; i < ARRAY_SIZE(baudrates); i++)
285 if (baud <= baudrates[i])
286 return i;
287
288 return -1;
289}
290
291static void timbuart_set_termios(struct uart_port *port,
292 struct ktermios *termios,
293 struct ktermios *old)
294{
295 unsigned int baud;
296 short bindex;
297 unsigned long flags;
298
299 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
300 bindex = get_bindex(baud);
301 dev_dbg(port->dev, "%s - bindex %d\n", __func__, bindex);
302
303 if (bindex < 0)
304 bindex = 0;
305 baud = baudrates[bindex];
306
307 /* The serial layer calls into this once with old = NULL when setting
308 up initially */
309 if (old)
310 tty_termios_copy_hw(termios, old);
311 tty_termios_encode_baud_rate(termios, baud, baud);
312
313 spin_lock_irqsave(&port->lock, flags);
314 iowrite8((u8)bindex, port->membase + TIMBUART_BAUDRATE);
315 uart_update_timeout(port, termios->c_cflag, baud);
316 spin_unlock_irqrestore(&port->lock, flags);
317}
318
319static const char *timbuart_type(struct uart_port *port)
320{
321 return port->type == PORT_UNKNOWN ? "timbuart" : NULL;
322}
323
324/* We do not request/release mappings of the registers here,
325 * currently it's done in the proble function.
326 */
327static void timbuart_release_port(struct uart_port *port)
328{
329 struct platform_device *pdev = to_platform_device(port->dev);
330 int size =
331 resource_size(platform_get_resource(pdev, IORESOURCE_MEM, 0));
332
333 if (port->flags & UPF_IOREMAP) {
334 iounmap(port->membase);
335 port->membase = NULL;
336 }
337
338 release_mem_region(port->mapbase, size);
339}
340
341static int timbuart_request_port(struct uart_port *port)
342{
343 struct platform_device *pdev = to_platform_device(port->dev);
344 int size =
345 resource_size(platform_get_resource(pdev, IORESOURCE_MEM, 0));
346
347 if (!request_mem_region(port->mapbase, size, "timb-uart"))
348 return -EBUSY;
349
350 if (port->flags & UPF_IOREMAP) {
351 port->membase = ioremap(port->mapbase, size);
352 if (port->membase == NULL) {
353 release_mem_region(port->mapbase, size);
354 return -ENOMEM;
355 }
356 }
357
358 return 0;
359}
360
361static irqreturn_t timbuart_handleinterrupt(int irq, void *devid)
362{
363 struct timbuart_port *uart = (struct timbuart_port *)devid;
364
365 if (ioread8(uart->port.membase + TIMBUART_IPR)) {
366 uart->last_ier = ioread32(uart->port.membase + TIMBUART_IER);
367
368 /* disable interrupts, the tasklet enables them again */
369 iowrite32(0, uart->port.membase + TIMBUART_IER);
370
371 /* fire off bottom half */
372 tasklet_schedule(&uart->tasklet);
373
374 return IRQ_HANDLED;
375 } else
376 return IRQ_NONE;
377}
378
379/*
380 * Configure/autoconfigure the port.
381 */
382static void timbuart_config_port(struct uart_port *port, int flags)
383{
384 if (flags & UART_CONFIG_TYPE) {
385 port->type = PORT_TIMBUART;
386 timbuart_request_port(port);
387 }
388}
389
390static int timbuart_verify_port(struct uart_port *port,
391 struct serial_struct *ser)
392{
393 /* we don't want the core code to modify any port params */
394 return -EINVAL;
395}
396
397static struct uart_ops timbuart_ops = {
398 .tx_empty = timbuart_tx_empty,
399 .set_mctrl = timbuart_set_mctrl,
400 .get_mctrl = timbuart_get_mctrl,
401 .stop_tx = timbuart_stop_tx,
402 .start_tx = timbuart_start_tx,
403 .flush_buffer = timbuart_flush_buffer,
404 .stop_rx = timbuart_stop_rx,
405 .enable_ms = timbuart_enable_ms,
406 .break_ctl = timbuart_break_ctl,
407 .startup = timbuart_startup,
408 .shutdown = timbuart_shutdown,
409 .set_termios = timbuart_set_termios,
410 .type = timbuart_type,
411 .release_port = timbuart_release_port,
412 .request_port = timbuart_request_port,
413 .config_port = timbuart_config_port,
414 .verify_port = timbuart_verify_port
415};
416
417static struct uart_driver timbuart_driver = {
418 .owner = THIS_MODULE,
419 .driver_name = "timberdale_uart",
420 .dev_name = "ttyTU",
421 .major = TIMBUART_MAJOR,
422 .minor = TIMBUART_MINOR,
423 .nr = 1
424};
425
426static int __devinit timbuart_probe(struct platform_device *dev)
427{
428 int err, irq;
429 struct timbuart_port *uart;
430 struct resource *iomem;
431
432 dev_dbg(&dev->dev, "%s\n", __func__);
433
434 uart = kzalloc(sizeof(*uart), GFP_KERNEL);
435 if (!uart) {
436 err = -EINVAL;
437 goto err_mem;
438 }
439
440 uart->usedma = 0;
441
442 uart->port.uartclk = 3250000 * 16;
443 uart->port.fifosize = TIMBUART_FIFO_SIZE;
444 uart->port.regshift = 2;
445 uart->port.iotype = UPIO_MEM;
446 uart->port.ops = &timbuart_ops;
447 uart->port.irq = 0;
448 uart->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
449 uart->port.line = 0;
450 uart->port.dev = &dev->dev;
451
452 iomem = platform_get_resource(dev, IORESOURCE_MEM, 0);
453 if (!iomem) {
454 err = -ENOMEM;
455 goto err_register;
456 }
457 uart->port.mapbase = iomem->start;
458 uart->port.membase = NULL;
459
460 irq = platform_get_irq(dev, 0);
461 if (irq < 0) {
462 err = -EINVAL;
463 goto err_register;
464 }
465 uart->port.irq = irq;
466
467 tasklet_init(&uart->tasklet, timbuart_tasklet, (unsigned long)uart);
468
469 err = uart_register_driver(&timbuart_driver);
470 if (err)
471 goto err_register;
472
473 err = uart_add_one_port(&timbuart_driver, &uart->port);
474 if (err)
475 goto err_add_port;
476
477 platform_set_drvdata(dev, uart);
478
479 return 0;
480
481err_add_port:
482 uart_unregister_driver(&timbuart_driver);
483err_register:
484 kfree(uart);
485err_mem:
486 printk(KERN_ERR "timberdale: Failed to register Timberdale UART: %d\n",
487 err);
488
489 return err;
490}
491
492static int __devexit timbuart_remove(struct platform_device *dev)
493{
494 struct timbuart_port *uart = platform_get_drvdata(dev);
495
496 tasklet_kill(&uart->tasklet);
497 uart_remove_one_port(&timbuart_driver, &uart->port);
498 uart_unregister_driver(&timbuart_driver);
499 kfree(uart);
500
501 return 0;
502}
503
504static struct platform_driver timbuart_platform_driver = {
505 .driver = {
506 .name = "timb-uart",
507 .owner = THIS_MODULE,
508 },
509 .probe = timbuart_probe,
510 .remove = __devexit_p(timbuart_remove),
511};
512
513/*--------------------------------------------------------------------------*/
514
515static int __init timbuart_init(void)
516{
517 return platform_driver_register(&timbuart_platform_driver);
518}
519
520static void __exit timbuart_exit(void)
521{
522 platform_driver_unregister(&timbuart_platform_driver);
523}
524
525module_init(timbuart_init);
526module_exit(timbuart_exit);
527
528MODULE_DESCRIPTION("Timberdale UART driver");
529MODULE_LICENSE("GPL v2");
530MODULE_ALIAS("platform:timb-uart");
531
diff --git a/drivers/serial/timbuart.h b/drivers/serial/timbuart.h
deleted file mode 100644
index 7e566766bc43..000000000000
--- a/drivers/serial/timbuart.h
+++ /dev/null
@@ -1,58 +0,0 @@
1/*
2 * timbuart.c timberdale FPGA GPIO driver
3 * Copyright (c) 2009 Intel Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19/* Supports:
20 * Timberdale FPGA UART
21 */
22
23#ifndef _TIMBUART_H
24#define _TIMBUART_H
25
26#define TIMBUART_FIFO_SIZE 2048
27
28#define TIMBUART_RXFIFO 0x08
29#define TIMBUART_TXFIFO 0x0c
30#define TIMBUART_IER 0x10
31#define TIMBUART_IPR 0x14
32#define TIMBUART_ISR 0x18
33#define TIMBUART_CTRL 0x1c
34#define TIMBUART_BAUDRATE 0x20
35
36#define TIMBUART_CTRL_RTS 0x01
37#define TIMBUART_CTRL_CTS 0x02
38#define TIMBUART_CTRL_FLSHTX 0x40
39#define TIMBUART_CTRL_FLSHRX 0x80
40
41#define TXBF 0x01
42#define TXBAE 0x02
43#define CTS_DELTA 0x04
44#define RXDP 0x08
45#define RXBAF 0x10
46#define RXBF 0x20
47#define RXTT 0x40
48#define RXBNAE 0x80
49#define TXBE 0x100
50
51#define RXFLAGS (RXDP | RXBAF | RXBF | RXTT | RXBNAE)
52#define TXFLAGS (TXBF | TXBAE)
53
54#define TIMBUART_MAJOR 204
55#define TIMBUART_MINOR 192
56
57#endif /* _TIMBUART_H */
58
diff --git a/drivers/serial/uartlite.c b/drivers/serial/uartlite.c
deleted file mode 100644
index 9b03d7b3e456..000000000000
--- a/drivers/serial/uartlite.c
+++ /dev/null
@@ -1,685 +0,0 @@
1/*
2 * uartlite.c: Serial driver for Xilinx uartlite serial controller
3 *
4 * Copyright (C) 2006 Peter Korsgaard <jacmet@sunsite.dk>
5 * Copyright (C) 2007 Secret Lab Technologies Ltd.
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12#include <linux/platform_device.h>
13#include <linux/module.h>
14#include <linux/console.h>
15#include <linux/serial.h>
16#include <linux/serial_core.h>
17#include <linux/tty.h>
18#include <linux/delay.h>
19#include <linux/interrupt.h>
20#include <linux/init.h>
21#include <asm/io.h>
22#if defined(CONFIG_OF) && (defined(CONFIG_PPC32) || defined(CONFIG_MICROBLAZE))
23#include <linux/of.h>
24#include <linux/of_address.h>
25#include <linux/of_device.h>
26#include <linux/of_platform.h>
27
28/* Match table for of_platform binding */
29static struct of_device_id ulite_of_match[] __devinitdata = {
30 { .compatible = "xlnx,opb-uartlite-1.00.b", },
31 { .compatible = "xlnx,xps-uartlite-1.00.a", },
32 {}
33};
34MODULE_DEVICE_TABLE(of, ulite_of_match);
35
36#endif
37
38#define ULITE_NAME "ttyUL"
39#define ULITE_MAJOR 204
40#define ULITE_MINOR 187
41#define ULITE_NR_UARTS 4
42
43/* ---------------------------------------------------------------------
44 * Register definitions
45 *
46 * For register details see datasheet:
47 * http://www.xilinx.com/bvdocs/ipcenter/data_sheet/opb_uartlite.pdf
48 */
49
50#define ULITE_RX 0x00
51#define ULITE_TX 0x04
52#define ULITE_STATUS 0x08
53#define ULITE_CONTROL 0x0c
54
55#define ULITE_REGION 16
56
57#define ULITE_STATUS_RXVALID 0x01
58#define ULITE_STATUS_RXFULL 0x02
59#define ULITE_STATUS_TXEMPTY 0x04
60#define ULITE_STATUS_TXFULL 0x08
61#define ULITE_STATUS_IE 0x10
62#define ULITE_STATUS_OVERRUN 0x20
63#define ULITE_STATUS_FRAME 0x40
64#define ULITE_STATUS_PARITY 0x80
65
66#define ULITE_CONTROL_RST_TX 0x01
67#define ULITE_CONTROL_RST_RX 0x02
68#define ULITE_CONTROL_IE 0x10
69
70
71static struct uart_port ulite_ports[ULITE_NR_UARTS];
72
73/* ---------------------------------------------------------------------
74 * Core UART driver operations
75 */
76
77static int ulite_receive(struct uart_port *port, int stat)
78{
79 struct tty_struct *tty = port->state->port.tty;
80 unsigned char ch = 0;
81 char flag = TTY_NORMAL;
82
83 if ((stat & (ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
84 | ULITE_STATUS_FRAME)) == 0)
85 return 0;
86
87 /* stats */
88 if (stat & ULITE_STATUS_RXVALID) {
89 port->icount.rx++;
90 ch = ioread32be(port->membase + ULITE_RX);
91
92 if (stat & ULITE_STATUS_PARITY)
93 port->icount.parity++;
94 }
95
96 if (stat & ULITE_STATUS_OVERRUN)
97 port->icount.overrun++;
98
99 if (stat & ULITE_STATUS_FRAME)
100 port->icount.frame++;
101
102
103 /* drop byte with parity error if IGNPAR specificed */
104 if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY)
105 stat &= ~ULITE_STATUS_RXVALID;
106
107 stat &= port->read_status_mask;
108
109 if (stat & ULITE_STATUS_PARITY)
110 flag = TTY_PARITY;
111
112
113 stat &= ~port->ignore_status_mask;
114
115 if (stat & ULITE_STATUS_RXVALID)
116 tty_insert_flip_char(tty, ch, flag);
117
118 if (stat & ULITE_STATUS_FRAME)
119 tty_insert_flip_char(tty, 0, TTY_FRAME);
120
121 if (stat & ULITE_STATUS_OVERRUN)
122 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
123
124 return 1;
125}
126
127static int ulite_transmit(struct uart_port *port, int stat)
128{
129 struct circ_buf *xmit = &port->state->xmit;
130
131 if (stat & ULITE_STATUS_TXFULL)
132 return 0;
133
134 if (port->x_char) {
135 iowrite32be(port->x_char, port->membase + ULITE_TX);
136 port->x_char = 0;
137 port->icount.tx++;
138 return 1;
139 }
140
141 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
142 return 0;
143
144 iowrite32be(xmit->buf[xmit->tail], port->membase + ULITE_TX);
145 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1);
146 port->icount.tx++;
147
148 /* wake up */
149 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
150 uart_write_wakeup(port);
151
152 return 1;
153}
154
155static irqreturn_t ulite_isr(int irq, void *dev_id)
156{
157 struct uart_port *port = dev_id;
158 int busy, n = 0;
159
160 do {
161 int stat = ioread32be(port->membase + ULITE_STATUS);
162 busy = ulite_receive(port, stat);
163 busy |= ulite_transmit(port, stat);
164 n++;
165 } while (busy);
166
167 /* work done? */
168 if (n > 1) {
169 tty_flip_buffer_push(port->state->port.tty);
170 return IRQ_HANDLED;
171 } else {
172 return IRQ_NONE;
173 }
174}
175
176static unsigned int ulite_tx_empty(struct uart_port *port)
177{
178 unsigned long flags;
179 unsigned int ret;
180
181 spin_lock_irqsave(&port->lock, flags);
182 ret = ioread32be(port->membase + ULITE_STATUS);
183 spin_unlock_irqrestore(&port->lock, flags);
184
185 return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0;
186}
187
188static unsigned int ulite_get_mctrl(struct uart_port *port)
189{
190 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
191}
192
193static void ulite_set_mctrl(struct uart_port *port, unsigned int mctrl)
194{
195 /* N/A */
196}
197
198static void ulite_stop_tx(struct uart_port *port)
199{
200 /* N/A */
201}
202
203static void ulite_start_tx(struct uart_port *port)
204{
205 ulite_transmit(port, ioread32be(port->membase + ULITE_STATUS));
206}
207
208static void ulite_stop_rx(struct uart_port *port)
209{
210 /* don't forward any more data (like !CREAD) */
211 port->ignore_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
212 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
213}
214
215static void ulite_enable_ms(struct uart_port *port)
216{
217 /* N/A */
218}
219
220static void ulite_break_ctl(struct uart_port *port, int ctl)
221{
222 /* N/A */
223}
224
225static int ulite_startup(struct uart_port *port)
226{
227 int ret;
228
229 ret = request_irq(port->irq, ulite_isr,
230 IRQF_SHARED | IRQF_SAMPLE_RANDOM, "uartlite", port);
231 if (ret)
232 return ret;
233
234 iowrite32be(ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX,
235 port->membase + ULITE_CONTROL);
236 iowrite32be(ULITE_CONTROL_IE, port->membase + ULITE_CONTROL);
237
238 return 0;
239}
240
241static void ulite_shutdown(struct uart_port *port)
242{
243 iowrite32be(0, port->membase + ULITE_CONTROL);
244 ioread32be(port->membase + ULITE_CONTROL); /* dummy */
245 free_irq(port->irq, port);
246}
247
248static void ulite_set_termios(struct uart_port *port, struct ktermios *termios,
249 struct ktermios *old)
250{
251 unsigned long flags;
252 unsigned int baud;
253
254 spin_lock_irqsave(&port->lock, flags);
255
256 port->read_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
257 | ULITE_STATUS_TXFULL;
258
259 if (termios->c_iflag & INPCK)
260 port->read_status_mask |=
261 ULITE_STATUS_PARITY | ULITE_STATUS_FRAME;
262
263 port->ignore_status_mask = 0;
264 if (termios->c_iflag & IGNPAR)
265 port->ignore_status_mask |= ULITE_STATUS_PARITY
266 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
267
268 /* ignore all characters if CREAD is not set */
269 if ((termios->c_cflag & CREAD) == 0)
270 port->ignore_status_mask |=
271 ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
272 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
273
274 /* update timeout */
275 baud = uart_get_baud_rate(port, termios, old, 0, 460800);
276 uart_update_timeout(port, termios->c_cflag, baud);
277
278 spin_unlock_irqrestore(&port->lock, flags);
279}
280
281static const char *ulite_type(struct uart_port *port)
282{
283 return port->type == PORT_UARTLITE ? "uartlite" : NULL;
284}
285
286static void ulite_release_port(struct uart_port *port)
287{
288 release_mem_region(port->mapbase, ULITE_REGION);
289 iounmap(port->membase);
290 port->membase = NULL;
291}
292
293static int ulite_request_port(struct uart_port *port)
294{
295 pr_debug("ulite console: port=%p; port->mapbase=%llx\n",
296 port, (unsigned long long) port->mapbase);
297
298 if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) {
299 dev_err(port->dev, "Memory region busy\n");
300 return -EBUSY;
301 }
302
303 port->membase = ioremap(port->mapbase, ULITE_REGION);
304 if (!port->membase) {
305 dev_err(port->dev, "Unable to map registers\n");
306 release_mem_region(port->mapbase, ULITE_REGION);
307 return -EBUSY;
308 }
309
310 return 0;
311}
312
313static void ulite_config_port(struct uart_port *port, int flags)
314{
315 if (!ulite_request_port(port))
316 port->type = PORT_UARTLITE;
317}
318
319static int ulite_verify_port(struct uart_port *port, struct serial_struct *ser)
320{
321 /* we don't want the core code to modify any port params */
322 return -EINVAL;
323}
324
325static struct uart_ops ulite_ops = {
326 .tx_empty = ulite_tx_empty,
327 .set_mctrl = ulite_set_mctrl,
328 .get_mctrl = ulite_get_mctrl,
329 .stop_tx = ulite_stop_tx,
330 .start_tx = ulite_start_tx,
331 .stop_rx = ulite_stop_rx,
332 .enable_ms = ulite_enable_ms,
333 .break_ctl = ulite_break_ctl,
334 .startup = ulite_startup,
335 .shutdown = ulite_shutdown,
336 .set_termios = ulite_set_termios,
337 .type = ulite_type,
338 .release_port = ulite_release_port,
339 .request_port = ulite_request_port,
340 .config_port = ulite_config_port,
341 .verify_port = ulite_verify_port
342};
343
344/* ---------------------------------------------------------------------
345 * Console driver operations
346 */
347
348#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
349static void ulite_console_wait_tx(struct uart_port *port)
350{
351 int i;
352 u8 val;
353
354 /* Spin waiting for TX fifo to have space available */
355 for (i = 0; i < 100000; i++) {
356 val = ioread32be(port->membase + ULITE_STATUS);
357 if ((val & ULITE_STATUS_TXFULL) == 0)
358 break;
359 cpu_relax();
360 }
361}
362
363static void ulite_console_putchar(struct uart_port *port, int ch)
364{
365 ulite_console_wait_tx(port);
366 iowrite32be(ch, port->membase + ULITE_TX);
367}
368
369static void ulite_console_write(struct console *co, const char *s,
370 unsigned int count)
371{
372 struct uart_port *port = &ulite_ports[co->index];
373 unsigned long flags;
374 unsigned int ier;
375 int locked = 1;
376
377 if (oops_in_progress) {
378 locked = spin_trylock_irqsave(&port->lock, flags);
379 } else
380 spin_lock_irqsave(&port->lock, flags);
381
382 /* save and disable interrupt */
383 ier = ioread32be(port->membase + ULITE_STATUS) & ULITE_STATUS_IE;
384 iowrite32be(0, port->membase + ULITE_CONTROL);
385
386 uart_console_write(port, s, count, ulite_console_putchar);
387
388 ulite_console_wait_tx(port);
389
390 /* restore interrupt state */
391 if (ier)
392 iowrite32be(ULITE_CONTROL_IE, port->membase + ULITE_CONTROL);
393
394 if (locked)
395 spin_unlock_irqrestore(&port->lock, flags);
396}
397
398static int __devinit ulite_console_setup(struct console *co, char *options)
399{
400 struct uart_port *port;
401 int baud = 9600;
402 int bits = 8;
403 int parity = 'n';
404 int flow = 'n';
405
406 if (co->index < 0 || co->index >= ULITE_NR_UARTS)
407 return -EINVAL;
408
409 port = &ulite_ports[co->index];
410
411 /* Has the device been initialized yet? */
412 if (!port->mapbase) {
413 pr_debug("console on ttyUL%i not present\n", co->index);
414 return -ENODEV;
415 }
416
417 /* not initialized yet? */
418 if (!port->membase) {
419 if (ulite_request_port(port))
420 return -ENODEV;
421 }
422
423 if (options)
424 uart_parse_options(options, &baud, &parity, &bits, &flow);
425
426 return uart_set_options(port, co, baud, parity, bits, flow);
427}
428
429static struct uart_driver ulite_uart_driver;
430
431static struct console ulite_console = {
432 .name = ULITE_NAME,
433 .write = ulite_console_write,
434 .device = uart_console_device,
435 .setup = ulite_console_setup,
436 .flags = CON_PRINTBUFFER,
437 .index = -1, /* Specified on the cmdline (e.g. console=ttyUL0 ) */
438 .data = &ulite_uart_driver,
439};
440
441static int __init ulite_console_init(void)
442{
443 register_console(&ulite_console);
444 return 0;
445}
446
447console_initcall(ulite_console_init);
448
449#endif /* CONFIG_SERIAL_UARTLITE_CONSOLE */
450
451static struct uart_driver ulite_uart_driver = {
452 .owner = THIS_MODULE,
453 .driver_name = "uartlite",
454 .dev_name = ULITE_NAME,
455 .major = ULITE_MAJOR,
456 .minor = ULITE_MINOR,
457 .nr = ULITE_NR_UARTS,
458#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
459 .cons = &ulite_console,
460#endif
461};
462
463/* ---------------------------------------------------------------------
464 * Port assignment functions (mapping devices to uart_port structures)
465 */
466
467/** ulite_assign: register a uartlite device with the driver
468 *
469 * @dev: pointer to device structure
470 * @id: requested id number. Pass -1 for automatic port assignment
471 * @base: base address of uartlite registers
472 * @irq: irq number for uartlite
473 *
474 * Returns: 0 on success, <0 otherwise
475 */
476static int __devinit ulite_assign(struct device *dev, int id, u32 base, int irq)
477{
478 struct uart_port *port;
479 int rc;
480
481 /* if id = -1; then scan for a free id and use that */
482 if (id < 0) {
483 for (id = 0; id < ULITE_NR_UARTS; id++)
484 if (ulite_ports[id].mapbase == 0)
485 break;
486 }
487 if (id < 0 || id >= ULITE_NR_UARTS) {
488 dev_err(dev, "%s%i too large\n", ULITE_NAME, id);
489 return -EINVAL;
490 }
491
492 if ((ulite_ports[id].mapbase) && (ulite_ports[id].mapbase != base)) {
493 dev_err(dev, "cannot assign to %s%i; it is already in use\n",
494 ULITE_NAME, id);
495 return -EBUSY;
496 }
497
498 port = &ulite_ports[id];
499
500 spin_lock_init(&port->lock);
501 port->fifosize = 16;
502 port->regshift = 2;
503 port->iotype = UPIO_MEM;
504 port->iobase = 1; /* mark port in use */
505 port->mapbase = base;
506 port->membase = NULL;
507 port->ops = &ulite_ops;
508 port->irq = irq;
509 port->flags = UPF_BOOT_AUTOCONF;
510 port->dev = dev;
511 port->type = PORT_UNKNOWN;
512 port->line = id;
513
514 dev_set_drvdata(dev, port);
515
516 /* Register the port */
517 rc = uart_add_one_port(&ulite_uart_driver, port);
518 if (rc) {
519 dev_err(dev, "uart_add_one_port() failed; err=%i\n", rc);
520 port->mapbase = 0;
521 dev_set_drvdata(dev, NULL);
522 return rc;
523 }
524
525 return 0;
526}
527
528/** ulite_release: register a uartlite device with the driver
529 *
530 * @dev: pointer to device structure
531 */
532static int __devexit ulite_release(struct device *dev)
533{
534 struct uart_port *port = dev_get_drvdata(dev);
535 int rc = 0;
536
537 if (port) {
538 rc = uart_remove_one_port(&ulite_uart_driver, port);
539 dev_set_drvdata(dev, NULL);
540 port->mapbase = 0;
541 }
542
543 return rc;
544}
545
546/* ---------------------------------------------------------------------
547 * Platform bus binding
548 */
549
550static int __devinit ulite_probe(struct platform_device *pdev)
551{
552 struct resource *res, *res2;
553
554 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
555 if (!res)
556 return -ENODEV;
557
558 res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
559 if (!res2)
560 return -ENODEV;
561
562 return ulite_assign(&pdev->dev, pdev->id, res->start, res2->start);
563}
564
565static int __devexit ulite_remove(struct platform_device *pdev)
566{
567 return ulite_release(&pdev->dev);
568}
569
570/* work with hotplug and coldplug */
571MODULE_ALIAS("platform:uartlite");
572
573static struct platform_driver ulite_platform_driver = {
574 .probe = ulite_probe,
575 .remove = __devexit_p(ulite_remove),
576 .driver = {
577 .owner = THIS_MODULE,
578 .name = "uartlite",
579 },
580};
581
582/* ---------------------------------------------------------------------
583 * OF bus bindings
584 */
585#if defined(CONFIG_OF) && (defined(CONFIG_PPC32) || defined(CONFIG_MICROBLAZE))
586static int __devinit
587ulite_of_probe(struct platform_device *op, const struct of_device_id *match)
588{
589 struct resource res;
590 const unsigned int *id;
591 int irq, rc;
592
593 dev_dbg(&op->dev, "%s(%p, %p)\n", __func__, op, match);
594
595 rc = of_address_to_resource(op->dev.of_node, 0, &res);
596 if (rc) {
597 dev_err(&op->dev, "invalid address\n");
598 return rc;
599 }
600
601 irq = irq_of_parse_and_map(op->dev.of_node, 0);
602
603 id = of_get_property(op->dev.of_node, "port-number", NULL);
604
605 return ulite_assign(&op->dev, id ? *id : -1, res.start, irq);
606}
607
608static int __devexit ulite_of_remove(struct platform_device *op)
609{
610 return ulite_release(&op->dev);
611}
612
613static struct of_platform_driver ulite_of_driver = {
614 .probe = ulite_of_probe,
615 .remove = __devexit_p(ulite_of_remove),
616 .driver = {
617 .name = "uartlite",
618 .owner = THIS_MODULE,
619 .of_match_table = ulite_of_match,
620 },
621};
622
623/* Registration helpers to keep the number of #ifdefs to a minimum */
624static inline int __init ulite_of_register(void)
625{
626 pr_debug("uartlite: calling of_register_platform_driver()\n");
627 return of_register_platform_driver(&ulite_of_driver);
628}
629
630static inline void __exit ulite_of_unregister(void)
631{
632 of_unregister_platform_driver(&ulite_of_driver);
633}
634#else /* CONFIG_OF && (CONFIG_PPC32 || CONFIG_MICROBLAZE) */
635/* Appropriate config not enabled; do nothing helpers */
636static inline int __init ulite_of_register(void) { return 0; }
637static inline void __exit ulite_of_unregister(void) { }
638#endif /* CONFIG_OF && (CONFIG_PPC32 || CONFIG_MICROBLAZE) */
639
640/* ---------------------------------------------------------------------
641 * Module setup/teardown
642 */
643
644int __init ulite_init(void)
645{
646 int ret;
647
648 pr_debug("uartlite: calling uart_register_driver()\n");
649 ret = uart_register_driver(&ulite_uart_driver);
650 if (ret)
651 goto err_uart;
652
653 ret = ulite_of_register();
654 if (ret)
655 goto err_of;
656
657 pr_debug("uartlite: calling platform_driver_register()\n");
658 ret = platform_driver_register(&ulite_platform_driver);
659 if (ret)
660 goto err_plat;
661
662 return 0;
663
664err_plat:
665 ulite_of_unregister();
666err_of:
667 uart_unregister_driver(&ulite_uart_driver);
668err_uart:
669 printk(KERN_ERR "registering uartlite driver failed: err=%i", ret);
670 return ret;
671}
672
673void __exit ulite_exit(void)
674{
675 platform_driver_unregister(&ulite_platform_driver);
676 ulite_of_unregister();
677 uart_unregister_driver(&ulite_uart_driver);
678}
679
680module_init(ulite_init);
681module_exit(ulite_exit);
682
683MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
684MODULE_DESCRIPTION("Xilinx uartlite serial driver");
685MODULE_LICENSE("GPL");
diff --git a/drivers/serial/ucc_uart.c b/drivers/serial/ucc_uart.c
deleted file mode 100644
index 3f4848e2174a..000000000000
--- a/drivers/serial/ucc_uart.c
+++ /dev/null
@@ -1,1537 +0,0 @@
1/*
2 * Freescale QUICC Engine UART device driver
3 *
4 * Author: Timur Tabi <timur@freescale.com>
5 *
6 * Copyright 2007 Freescale Semiconductor, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 *
11 * This driver adds support for UART devices via Freescale's QUICC Engine
12 * found on some Freescale SOCs.
13 *
14 * If Soft-UART support is needed but not already present, then this driver
15 * will request and upload the "Soft-UART" microcode upon probe. The
16 * filename of the microcode should be fsl_qe_ucode_uart_X_YZ.bin, where "X"
17 * is the name of the SOC (e.g. 8323), and YZ is the revision of the SOC,
18 * (e.g. "11" for 1.1).
19 */
20
21#include <linux/module.h>
22#include <linux/serial.h>
23#include <linux/slab.h>
24#include <linux/serial_core.h>
25#include <linux/io.h>
26#include <linux/of_platform.h>
27#include <linux/dma-mapping.h>
28
29#include <linux/fs_uart_pd.h>
30#include <asm/ucc_slow.h>
31
32#include <linux/firmware.h>
33#include <asm/reg.h>
34
35/*
36 * The GUMR flag for Soft UART. This would normally be defined in qe.h,
37 * but Soft-UART is a hack and we want to keep everything related to it in
38 * this file.
39 */
40#define UCC_SLOW_GUMR_H_SUART 0x00004000 /* Soft-UART */
41
42/*
43 * soft_uart is 1 if we need to use Soft-UART mode
44 */
45static int soft_uart;
46/*
47 * firmware_loaded is 1 if the firmware has been loaded, 0 otherwise.
48 */
49static int firmware_loaded;
50
51/* Enable this macro to configure all serial ports in internal loopback
52 mode */
53/* #define LOOPBACK */
54
55/* The major and minor device numbers are defined in
56 * http://www.lanana.org/docs/device-list/devices-2.6+.txt. For the QE
57 * UART, we have major number 204 and minor numbers 46 - 49, which are the
58 * same as for the CPM2. This decision was made because no Freescale part
59 * has both a CPM and a QE.
60 */
61#define SERIAL_QE_MAJOR 204
62#define SERIAL_QE_MINOR 46
63
64/* Since we only have minor numbers 46 - 49, there is a hard limit of 4 ports */
65#define UCC_MAX_UART 4
66
67/* The number of buffer descriptors for receiving characters. */
68#define RX_NUM_FIFO 4
69
70/* The number of buffer descriptors for transmitting characters. */
71#define TX_NUM_FIFO 4
72
73/* The maximum size of the character buffer for a single RX BD. */
74#define RX_BUF_SIZE 32
75
76/* The maximum size of the character buffer for a single TX BD. */
77#define TX_BUF_SIZE 32
78
79/*
80 * The number of jiffies to wait after receiving a close command before the
81 * device is actually closed. This allows the last few characters to be
82 * sent over the wire.
83 */
84#define UCC_WAIT_CLOSING 100
85
86struct ucc_uart_pram {
87 struct ucc_slow_pram common;
88 u8 res1[8]; /* reserved */
89 __be16 maxidl; /* Maximum idle chars */
90 __be16 idlc; /* temp idle counter */
91 __be16 brkcr; /* Break count register */
92 __be16 parec; /* receive parity error counter */
93 __be16 frmec; /* receive framing error counter */
94 __be16 nosec; /* receive noise counter */
95 __be16 brkec; /* receive break condition counter */
96 __be16 brkln; /* last received break length */
97 __be16 uaddr[2]; /* UART address character 1 & 2 */
98 __be16 rtemp; /* Temp storage */
99 __be16 toseq; /* Transmit out of sequence char */
100 __be16 cchars[8]; /* control characters 1-8 */
101 __be16 rccm; /* receive control character mask */
102 __be16 rccr; /* receive control character register */
103 __be16 rlbc; /* receive last break character */
104 __be16 res2; /* reserved */
105 __be32 res3; /* reserved, should be cleared */
106 u8 res4; /* reserved, should be cleared */
107 u8 res5[3]; /* reserved, should be cleared */
108 __be32 res6; /* reserved, should be cleared */
109 __be32 res7; /* reserved, should be cleared */
110 __be32 res8; /* reserved, should be cleared */
111 __be32 res9; /* reserved, should be cleared */
112 __be32 res10; /* reserved, should be cleared */
113 __be32 res11; /* reserved, should be cleared */
114 __be32 res12; /* reserved, should be cleared */
115 __be32 res13; /* reserved, should be cleared */
116/* The rest is for Soft-UART only */
117 __be16 supsmr; /* 0x90, Shadow UPSMR */
118 __be16 res92; /* 0x92, reserved, initialize to 0 */
119 __be32 rx_state; /* 0x94, RX state, initialize to 0 */
120 __be32 rx_cnt; /* 0x98, RX count, initialize to 0 */
121 u8 rx_length; /* 0x9C, Char length, set to 1+CL+PEN+1+SL */
122 u8 rx_bitmark; /* 0x9D, reserved, initialize to 0 */
123 u8 rx_temp_dlst_qe; /* 0x9E, reserved, initialize to 0 */
124 u8 res14[0xBC - 0x9F]; /* reserved */
125 __be32 dump_ptr; /* 0xBC, Dump pointer */
126 __be32 rx_frame_rem; /* 0xC0, reserved, initialize to 0 */
127 u8 rx_frame_rem_size; /* 0xC4, reserved, initialize to 0 */
128 u8 tx_mode; /* 0xC5, mode, 0=AHDLC, 1=UART */
129 __be16 tx_state; /* 0xC6, TX state */
130 u8 res15[0xD0 - 0xC8]; /* reserved */
131 __be32 resD0; /* 0xD0, reserved, initialize to 0 */
132 u8 resD4; /* 0xD4, reserved, initialize to 0 */
133 __be16 resD5; /* 0xD5, reserved, initialize to 0 */
134} __attribute__ ((packed));
135
136/* SUPSMR definitions, for Soft-UART only */
137#define UCC_UART_SUPSMR_SL 0x8000
138#define UCC_UART_SUPSMR_RPM_MASK 0x6000
139#define UCC_UART_SUPSMR_RPM_ODD 0x0000
140#define UCC_UART_SUPSMR_RPM_LOW 0x2000
141#define UCC_UART_SUPSMR_RPM_EVEN 0x4000
142#define UCC_UART_SUPSMR_RPM_HIGH 0x6000
143#define UCC_UART_SUPSMR_PEN 0x1000
144#define UCC_UART_SUPSMR_TPM_MASK 0x0C00
145#define UCC_UART_SUPSMR_TPM_ODD 0x0000
146#define UCC_UART_SUPSMR_TPM_LOW 0x0400
147#define UCC_UART_SUPSMR_TPM_EVEN 0x0800
148#define UCC_UART_SUPSMR_TPM_HIGH 0x0C00
149#define UCC_UART_SUPSMR_FRZ 0x0100
150#define UCC_UART_SUPSMR_UM_MASK 0x00c0
151#define UCC_UART_SUPSMR_UM_NORMAL 0x0000
152#define UCC_UART_SUPSMR_UM_MAN_MULTI 0x0040
153#define UCC_UART_SUPSMR_UM_AUTO_MULTI 0x00c0
154#define UCC_UART_SUPSMR_CL_MASK 0x0030
155#define UCC_UART_SUPSMR_CL_8 0x0030
156#define UCC_UART_SUPSMR_CL_7 0x0020
157#define UCC_UART_SUPSMR_CL_6 0x0010
158#define UCC_UART_SUPSMR_CL_5 0x0000
159
160#define UCC_UART_TX_STATE_AHDLC 0x00
161#define UCC_UART_TX_STATE_UART 0x01
162#define UCC_UART_TX_STATE_X1 0x00
163#define UCC_UART_TX_STATE_X16 0x80
164
165#define UCC_UART_PRAM_ALIGNMENT 0x100
166
167#define UCC_UART_SIZE_OF_BD UCC_SLOW_SIZE_OF_BD
168#define NUM_CONTROL_CHARS 8
169
170/* Private per-port data structure */
171struct uart_qe_port {
172 struct uart_port port;
173 struct ucc_slow __iomem *uccp;
174 struct ucc_uart_pram __iomem *uccup;
175 struct ucc_slow_info us_info;
176 struct ucc_slow_private *us_private;
177 struct device_node *np;
178 unsigned int ucc_num; /* First ucc is 0, not 1 */
179
180 u16 rx_nrfifos;
181 u16 rx_fifosize;
182 u16 tx_nrfifos;
183 u16 tx_fifosize;
184 int wait_closing;
185 u32 flags;
186 struct qe_bd *rx_bd_base;
187 struct qe_bd *rx_cur;
188 struct qe_bd *tx_bd_base;
189 struct qe_bd *tx_cur;
190 unsigned char *tx_buf;
191 unsigned char *rx_buf;
192 void *bd_virt; /* virtual address of the BD buffers */
193 dma_addr_t bd_dma_addr; /* bus address of the BD buffers */
194 unsigned int bd_size; /* size of BD buffer space */
195};
196
197static struct uart_driver ucc_uart_driver = {
198 .owner = THIS_MODULE,
199 .driver_name = "ucc_uart",
200 .dev_name = "ttyQE",
201 .major = SERIAL_QE_MAJOR,
202 .minor = SERIAL_QE_MINOR,
203 .nr = UCC_MAX_UART,
204};
205
206/*
207 * Virtual to physical address translation.
208 *
209 * Given the virtual address for a character buffer, this function returns
210 * the physical (DMA) equivalent.
211 */
212static inline dma_addr_t cpu2qe_addr(void *addr, struct uart_qe_port *qe_port)
213{
214 if (likely((addr >= qe_port->bd_virt)) &&
215 (addr < (qe_port->bd_virt + qe_port->bd_size)))
216 return qe_port->bd_dma_addr + (addr - qe_port->bd_virt);
217
218 /* something nasty happened */
219 printk(KERN_ERR "%s: addr=%p\n", __func__, addr);
220 BUG();
221 return 0;
222}
223
224/*
225 * Physical to virtual address translation.
226 *
227 * Given the physical (DMA) address for a character buffer, this function
228 * returns the virtual equivalent.
229 */
230static inline void *qe2cpu_addr(dma_addr_t addr, struct uart_qe_port *qe_port)
231{
232 /* sanity check */
233 if (likely((addr >= qe_port->bd_dma_addr) &&
234 (addr < (qe_port->bd_dma_addr + qe_port->bd_size))))
235 return qe_port->bd_virt + (addr - qe_port->bd_dma_addr);
236
237 /* something nasty happened */
238 printk(KERN_ERR "%s: addr=%x\n", __func__, addr);
239 BUG();
240 return NULL;
241}
242
243/*
244 * Return 1 if the QE is done transmitting all buffers for this port
245 *
246 * This function scans each BD in sequence. If we find a BD that is not
247 * ready (READY=1), then we return 0 indicating that the QE is still sending
248 * data. If we reach the last BD (WRAP=1), then we know we've scanned
249 * the entire list, and all BDs are done.
250 */
251static unsigned int qe_uart_tx_empty(struct uart_port *port)
252{
253 struct uart_qe_port *qe_port =
254 container_of(port, struct uart_qe_port, port);
255 struct qe_bd *bdp = qe_port->tx_bd_base;
256
257 while (1) {
258 if (in_be16(&bdp->status) & BD_SC_READY)
259 /* This BD is not done, so return "not done" */
260 return 0;
261
262 if (in_be16(&bdp->status) & BD_SC_WRAP)
263 /*
264 * This BD is done and it's the last one, so return
265 * "done"
266 */
267 return 1;
268
269 bdp++;
270 };
271}
272
273/*
274 * Set the modem control lines
275 *
276 * Although the QE can control the modem control lines (e.g. CTS), we
277 * don't need that support. This function must exist, however, otherwise
278 * the kernel will panic.
279 */
280void qe_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
281{
282}
283
284/*
285 * Get the current modem control line status
286 *
287 * Although the QE can control the modem control lines (e.g. CTS), this
288 * driver currently doesn't support that, so we always return Carrier
289 * Detect, Data Set Ready, and Clear To Send.
290 */
291static unsigned int qe_uart_get_mctrl(struct uart_port *port)
292{
293 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
294}
295
296/*
297 * Disable the transmit interrupt.
298 *
299 * Although this function is called "stop_tx", it does not actually stop
300 * transmission of data. Instead, it tells the QE to not generate an
301 * interrupt when the UCC is finished sending characters.
302 */
303static void qe_uart_stop_tx(struct uart_port *port)
304{
305 struct uart_qe_port *qe_port =
306 container_of(port, struct uart_qe_port, port);
307
308 clrbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
309}
310
311/*
312 * Transmit as many characters to the HW as possible.
313 *
314 * This function will attempt to stuff of all the characters from the
315 * kernel's transmit buffer into TX BDs.
316 *
317 * A return value of non-zero indicates that it successfully stuffed all
318 * characters from the kernel buffer.
319 *
320 * A return value of zero indicates that there are still characters in the
321 * kernel's buffer that have not been transmitted, but there are no more BDs
322 * available. This function should be called again after a BD has been made
323 * available.
324 */
325static int qe_uart_tx_pump(struct uart_qe_port *qe_port)
326{
327 struct qe_bd *bdp;
328 unsigned char *p;
329 unsigned int count;
330 struct uart_port *port = &qe_port->port;
331 struct circ_buf *xmit = &port->state->xmit;
332
333 bdp = qe_port->rx_cur;
334
335 /* Handle xon/xoff */
336 if (port->x_char) {
337 /* Pick next descriptor and fill from buffer */
338 bdp = qe_port->tx_cur;
339
340 p = qe2cpu_addr(bdp->buf, qe_port);
341
342 *p++ = port->x_char;
343 out_be16(&bdp->length, 1);
344 setbits16(&bdp->status, BD_SC_READY);
345 /* Get next BD. */
346 if (in_be16(&bdp->status) & BD_SC_WRAP)
347 bdp = qe_port->tx_bd_base;
348 else
349 bdp++;
350 qe_port->tx_cur = bdp;
351
352 port->icount.tx++;
353 port->x_char = 0;
354 return 1;
355 }
356
357 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
358 qe_uart_stop_tx(port);
359 return 0;
360 }
361
362 /* Pick next descriptor and fill from buffer */
363 bdp = qe_port->tx_cur;
364
365 while (!(in_be16(&bdp->status) & BD_SC_READY) &&
366 (xmit->tail != xmit->head)) {
367 count = 0;
368 p = qe2cpu_addr(bdp->buf, qe_port);
369 while (count < qe_port->tx_fifosize) {
370 *p++ = xmit->buf[xmit->tail];
371 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
372 port->icount.tx++;
373 count++;
374 if (xmit->head == xmit->tail)
375 break;
376 }
377
378 out_be16(&bdp->length, count);
379 setbits16(&bdp->status, BD_SC_READY);
380
381 /* Get next BD. */
382 if (in_be16(&bdp->status) & BD_SC_WRAP)
383 bdp = qe_port->tx_bd_base;
384 else
385 bdp++;
386 }
387 qe_port->tx_cur = bdp;
388
389 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
390 uart_write_wakeup(port);
391
392 if (uart_circ_empty(xmit)) {
393 /* The kernel buffer is empty, so turn off TX interrupts. We
394 don't need to be told when the QE is finished transmitting
395 the data. */
396 qe_uart_stop_tx(port);
397 return 0;
398 }
399
400 return 1;
401}
402
403/*
404 * Start transmitting data
405 *
406 * This function will start transmitting any available data, if the port
407 * isn't already transmitting data.
408 */
409static void qe_uart_start_tx(struct uart_port *port)
410{
411 struct uart_qe_port *qe_port =
412 container_of(port, struct uart_qe_port, port);
413
414 /* If we currently are transmitting, then just return */
415 if (in_be16(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX)
416 return;
417
418 /* Otherwise, pump the port and start transmission */
419 if (qe_uart_tx_pump(qe_port))
420 setbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
421}
422
423/*
424 * Stop transmitting data
425 */
426static void qe_uart_stop_rx(struct uart_port *port)
427{
428 struct uart_qe_port *qe_port =
429 container_of(port, struct uart_qe_port, port);
430
431 clrbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
432}
433
434/*
435 * Enable status change interrupts
436 *
437 * We don't support status change interrupts, but we need to define this
438 * function otherwise the kernel will panic.
439 */
440static void qe_uart_enable_ms(struct uart_port *port)
441{
442}
443
444/* Start or stop sending break signal
445 *
446 * This function controls the sending of a break signal. If break_state=1,
447 * then we start sending a break signal. If break_state=0, then we stop
448 * sending the break signal.
449 */
450static void qe_uart_break_ctl(struct uart_port *port, int break_state)
451{
452 struct uart_qe_port *qe_port =
453 container_of(port, struct uart_qe_port, port);
454
455 if (break_state)
456 ucc_slow_stop_tx(qe_port->us_private);
457 else
458 ucc_slow_restart_tx(qe_port->us_private);
459}
460
461/* ISR helper function for receiving character.
462 *
463 * This function is called by the ISR to handling receiving characters
464 */
465static void qe_uart_int_rx(struct uart_qe_port *qe_port)
466{
467 int i;
468 unsigned char ch, *cp;
469 struct uart_port *port = &qe_port->port;
470 struct tty_struct *tty = port->state->port.tty;
471 struct qe_bd *bdp;
472 u16 status;
473 unsigned int flg;
474
475 /* Just loop through the closed BDs and copy the characters into
476 * the buffer.
477 */
478 bdp = qe_port->rx_cur;
479 while (1) {
480 status = in_be16(&bdp->status);
481
482 /* If this one is empty, then we assume we've read them all */
483 if (status & BD_SC_EMPTY)
484 break;
485
486 /* get number of characters, and check space in RX buffer */
487 i = in_be16(&bdp->length);
488
489 /* If we don't have enough room in RX buffer for the entire BD,
490 * then we try later, which will be the next RX interrupt.
491 */
492 if (tty_buffer_request_room(tty, i) < i) {
493 dev_dbg(port->dev, "ucc-uart: no room in RX buffer\n");
494 return;
495 }
496
497 /* get pointer */
498 cp = qe2cpu_addr(bdp->buf, qe_port);
499
500 /* loop through the buffer */
501 while (i-- > 0) {
502 ch = *cp++;
503 port->icount.rx++;
504 flg = TTY_NORMAL;
505
506 if (!i && status &
507 (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV))
508 goto handle_error;
509 if (uart_handle_sysrq_char(port, ch))
510 continue;
511
512error_return:
513 tty_insert_flip_char(tty, ch, flg);
514
515 }
516
517 /* This BD is ready to be used again. Clear status. get next */
518 clrsetbits_be16(&bdp->status, BD_SC_BR | BD_SC_FR | BD_SC_PR |
519 BD_SC_OV | BD_SC_ID, BD_SC_EMPTY);
520 if (in_be16(&bdp->status) & BD_SC_WRAP)
521 bdp = qe_port->rx_bd_base;
522 else
523 bdp++;
524
525 }
526
527 /* Write back buffer pointer */
528 qe_port->rx_cur = bdp;
529
530 /* Activate BH processing */
531 tty_flip_buffer_push(tty);
532
533 return;
534
535 /* Error processing */
536
537handle_error:
538 /* Statistics */
539 if (status & BD_SC_BR)
540 port->icount.brk++;
541 if (status & BD_SC_PR)
542 port->icount.parity++;
543 if (status & BD_SC_FR)
544 port->icount.frame++;
545 if (status & BD_SC_OV)
546 port->icount.overrun++;
547
548 /* Mask out ignored conditions */
549 status &= port->read_status_mask;
550
551 /* Handle the remaining ones */
552 if (status & BD_SC_BR)
553 flg = TTY_BREAK;
554 else if (status & BD_SC_PR)
555 flg = TTY_PARITY;
556 else if (status & BD_SC_FR)
557 flg = TTY_FRAME;
558
559 /* Overrun does not affect the current character ! */
560 if (status & BD_SC_OV)
561 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
562#ifdef SUPPORT_SYSRQ
563 port->sysrq = 0;
564#endif
565 goto error_return;
566}
567
568/* Interrupt handler
569 *
570 * This interrupt handler is called after a BD is processed.
571 */
572static irqreturn_t qe_uart_int(int irq, void *data)
573{
574 struct uart_qe_port *qe_port = (struct uart_qe_port *) data;
575 struct ucc_slow __iomem *uccp = qe_port->uccp;
576 u16 events;
577
578 /* Clear the interrupts */
579 events = in_be16(&uccp->ucce);
580 out_be16(&uccp->ucce, events);
581
582 if (events & UCC_UART_UCCE_BRKE)
583 uart_handle_break(&qe_port->port);
584
585 if (events & UCC_UART_UCCE_RX)
586 qe_uart_int_rx(qe_port);
587
588 if (events & UCC_UART_UCCE_TX)
589 qe_uart_tx_pump(qe_port);
590
591 return events ? IRQ_HANDLED : IRQ_NONE;
592}
593
594/* Initialize buffer descriptors
595 *
596 * This function initializes all of the RX and TX buffer descriptors.
597 */
598static void qe_uart_initbd(struct uart_qe_port *qe_port)
599{
600 int i;
601 void *bd_virt;
602 struct qe_bd *bdp;
603
604 /* Set the physical address of the host memory buffers in the buffer
605 * descriptors, and the virtual address for us to work with.
606 */
607 bd_virt = qe_port->bd_virt;
608 bdp = qe_port->rx_bd_base;
609 qe_port->rx_cur = qe_port->rx_bd_base;
610 for (i = 0; i < (qe_port->rx_nrfifos - 1); i++) {
611 out_be16(&bdp->status, BD_SC_EMPTY | BD_SC_INTRPT);
612 out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
613 out_be16(&bdp->length, 0);
614 bd_virt += qe_port->rx_fifosize;
615 bdp++;
616 }
617
618 /* */
619 out_be16(&bdp->status, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT);
620 out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
621 out_be16(&bdp->length, 0);
622
623 /* Set the physical address of the host memory
624 * buffers in the buffer descriptors, and the
625 * virtual address for us to work with.
626 */
627 bd_virt = qe_port->bd_virt +
628 L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize);
629 qe_port->tx_cur = qe_port->tx_bd_base;
630 bdp = qe_port->tx_bd_base;
631 for (i = 0; i < (qe_port->tx_nrfifos - 1); i++) {
632 out_be16(&bdp->status, BD_SC_INTRPT);
633 out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
634 out_be16(&bdp->length, 0);
635 bd_virt += qe_port->tx_fifosize;
636 bdp++;
637 }
638
639 /* Loopback requires the preamble bit to be set on the first TX BD */
640#ifdef LOOPBACK
641 setbits16(&qe_port->tx_cur->status, BD_SC_P);
642#endif
643
644 out_be16(&bdp->status, BD_SC_WRAP | BD_SC_INTRPT);
645 out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
646 out_be16(&bdp->length, 0);
647}
648
649/*
650 * Initialize a UCC for UART.
651 *
652 * This function configures a given UCC to be used as a UART device. Basic
653 * UCC initialization is handled in qe_uart_request_port(). This function
654 * does all the UART-specific stuff.
655 */
656static void qe_uart_init_ucc(struct uart_qe_port *qe_port)
657{
658 u32 cecr_subblock;
659 struct ucc_slow __iomem *uccp = qe_port->uccp;
660 struct ucc_uart_pram *uccup = qe_port->uccup;
661
662 unsigned int i;
663
664 /* First, disable TX and RX in the UCC */
665 ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
666
667 /* Program the UCC UART parameter RAM */
668 out_8(&uccup->common.rbmr, UCC_BMR_GBL | UCC_BMR_BO_BE);
669 out_8(&uccup->common.tbmr, UCC_BMR_GBL | UCC_BMR_BO_BE);
670 out_be16(&uccup->common.mrblr, qe_port->rx_fifosize);
671 out_be16(&uccup->maxidl, 0x10);
672 out_be16(&uccup->brkcr, 1);
673 out_be16(&uccup->parec, 0);
674 out_be16(&uccup->frmec, 0);
675 out_be16(&uccup->nosec, 0);
676 out_be16(&uccup->brkec, 0);
677 out_be16(&uccup->uaddr[0], 0);
678 out_be16(&uccup->uaddr[1], 0);
679 out_be16(&uccup->toseq, 0);
680 for (i = 0; i < 8; i++)
681 out_be16(&uccup->cchars[i], 0xC000);
682 out_be16(&uccup->rccm, 0xc0ff);
683
684 /* Configure the GUMR registers for UART */
685 if (soft_uart) {
686 /* Soft-UART requires a 1X multiplier for TX */
687 clrsetbits_be32(&uccp->gumr_l,
688 UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
689 UCC_SLOW_GUMR_L_RDCR_MASK,
690 UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_1 |
691 UCC_SLOW_GUMR_L_RDCR_16);
692
693 clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW,
694 UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX);
695 } else {
696 clrsetbits_be32(&uccp->gumr_l,
697 UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
698 UCC_SLOW_GUMR_L_RDCR_MASK,
699 UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_16 |
700 UCC_SLOW_GUMR_L_RDCR_16);
701
702 clrsetbits_be32(&uccp->gumr_h,
703 UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX,
704 UCC_SLOW_GUMR_H_RFW);
705 }
706
707#ifdef LOOPBACK
708 clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
709 UCC_SLOW_GUMR_L_DIAG_LOOP);
710 clrsetbits_be32(&uccp->gumr_h,
711 UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_RSYN,
712 UCC_SLOW_GUMR_H_CDS);
713#endif
714
715 /* Disable rx interrupts and clear all pending events. */
716 out_be16(&uccp->uccm, 0);
717 out_be16(&uccp->ucce, 0xffff);
718 out_be16(&uccp->udsr, 0x7e7e);
719
720 /* Initialize UPSMR */
721 out_be16(&uccp->upsmr, 0);
722
723 if (soft_uart) {
724 out_be16(&uccup->supsmr, 0x30);
725 out_be16(&uccup->res92, 0);
726 out_be32(&uccup->rx_state, 0);
727 out_be32(&uccup->rx_cnt, 0);
728 out_8(&uccup->rx_bitmark, 0);
729 out_8(&uccup->rx_length, 10);
730 out_be32(&uccup->dump_ptr, 0x4000);
731 out_8(&uccup->rx_temp_dlst_qe, 0);
732 out_be32(&uccup->rx_frame_rem, 0);
733 out_8(&uccup->rx_frame_rem_size, 0);
734 /* Soft-UART requires TX to be 1X */
735 out_8(&uccup->tx_mode,
736 UCC_UART_TX_STATE_UART | UCC_UART_TX_STATE_X1);
737 out_be16(&uccup->tx_state, 0);
738 out_8(&uccup->resD4, 0);
739 out_be16(&uccup->resD5, 0);
740
741 /* Set UART mode.
742 * Enable receive and transmit.
743 */
744
745 /* From the microcode errata:
746 * 1.GUMR_L register, set mode=0010 (QMC).
747 * 2.Set GUMR_H[17] bit. (UART/AHDLC mode).
748 * 3.Set GUMR_H[19:20] (Transparent mode)
749 * 4.Clear GUMR_H[26] (RFW)
750 * ...
751 * 6.Receiver must use 16x over sampling
752 */
753 clrsetbits_be32(&uccp->gumr_l,
754 UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
755 UCC_SLOW_GUMR_L_RDCR_MASK,
756 UCC_SLOW_GUMR_L_MODE_QMC | UCC_SLOW_GUMR_L_TDCR_16 |
757 UCC_SLOW_GUMR_L_RDCR_16);
758
759 clrsetbits_be32(&uccp->gumr_h,
760 UCC_SLOW_GUMR_H_RFW | UCC_SLOW_GUMR_H_RSYN,
761 UCC_SLOW_GUMR_H_SUART | UCC_SLOW_GUMR_H_TRX |
762 UCC_SLOW_GUMR_H_TTX | UCC_SLOW_GUMR_H_TFL);
763
764#ifdef LOOPBACK
765 clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
766 UCC_SLOW_GUMR_L_DIAG_LOOP);
767 clrbits32(&uccp->gumr_h, UCC_SLOW_GUMR_H_CTSP |
768 UCC_SLOW_GUMR_H_CDS);
769#endif
770
771 cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
772 qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
773 QE_CR_PROTOCOL_UNSPECIFIED, 0);
774 } else {
775 cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
776 qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
777 QE_CR_PROTOCOL_UART, 0);
778 }
779}
780
781/*
782 * Initialize the port.
783 */
784static int qe_uart_startup(struct uart_port *port)
785{
786 struct uart_qe_port *qe_port =
787 container_of(port, struct uart_qe_port, port);
788 int ret;
789
790 /*
791 * If we're using Soft-UART mode, then we need to make sure the
792 * firmware has been uploaded first.
793 */
794 if (soft_uart && !firmware_loaded) {
795 dev_err(port->dev, "Soft-UART firmware not uploaded\n");
796 return -ENODEV;
797 }
798
799 qe_uart_initbd(qe_port);
800 qe_uart_init_ucc(qe_port);
801
802 /* Install interrupt handler. */
803 ret = request_irq(port->irq, qe_uart_int, IRQF_SHARED, "ucc-uart",
804 qe_port);
805 if (ret) {
806 dev_err(port->dev, "could not claim IRQ %u\n", port->irq);
807 return ret;
808 }
809
810 /* Startup rx-int */
811 setbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
812 ucc_slow_enable(qe_port->us_private, COMM_DIR_RX_AND_TX);
813
814 return 0;
815}
816
817/*
818 * Shutdown the port.
819 */
820static void qe_uart_shutdown(struct uart_port *port)
821{
822 struct uart_qe_port *qe_port =
823 container_of(port, struct uart_qe_port, port);
824 struct ucc_slow __iomem *uccp = qe_port->uccp;
825 unsigned int timeout = 20;
826
827 /* Disable RX and TX */
828
829 /* Wait for all the BDs marked sent */
830 while (!qe_uart_tx_empty(port)) {
831 if (!--timeout) {
832 dev_warn(port->dev, "shutdown timeout\n");
833 break;
834 }
835 set_current_state(TASK_UNINTERRUPTIBLE);
836 schedule_timeout(2);
837 }
838
839 if (qe_port->wait_closing) {
840 /* Wait a bit longer */
841 set_current_state(TASK_UNINTERRUPTIBLE);
842 schedule_timeout(qe_port->wait_closing);
843 }
844
845 /* Stop uarts */
846 ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
847 clrbits16(&uccp->uccm, UCC_UART_UCCE_TX | UCC_UART_UCCE_RX);
848
849 /* Shut them really down and reinit buffer descriptors */
850 ucc_slow_graceful_stop_tx(qe_port->us_private);
851 qe_uart_initbd(qe_port);
852
853 free_irq(port->irq, qe_port);
854}
855
856/*
857 * Set the serial port parameters.
858 */
859static void qe_uart_set_termios(struct uart_port *port,
860 struct ktermios *termios, struct ktermios *old)
861{
862 struct uart_qe_port *qe_port =
863 container_of(port, struct uart_qe_port, port);
864 struct ucc_slow __iomem *uccp = qe_port->uccp;
865 unsigned int baud;
866 unsigned long flags;
867 u16 upsmr = in_be16(&uccp->upsmr);
868 struct ucc_uart_pram __iomem *uccup = qe_port->uccup;
869 u16 supsmr = in_be16(&uccup->supsmr);
870 u8 char_length = 2; /* 1 + CL + PEN + 1 + SL */
871
872 /* Character length programmed into the mode register is the
873 * sum of: 1 start bit, number of data bits, 0 or 1 parity bit,
874 * 1 or 2 stop bits, minus 1.
875 * The value 'bits' counts this for us.
876 */
877
878 /* byte size */
879 upsmr &= UCC_UART_UPSMR_CL_MASK;
880 supsmr &= UCC_UART_SUPSMR_CL_MASK;
881
882 switch (termios->c_cflag & CSIZE) {
883 case CS5:
884 upsmr |= UCC_UART_UPSMR_CL_5;
885 supsmr |= UCC_UART_SUPSMR_CL_5;
886 char_length += 5;
887 break;
888 case CS6:
889 upsmr |= UCC_UART_UPSMR_CL_6;
890 supsmr |= UCC_UART_SUPSMR_CL_6;
891 char_length += 6;
892 break;
893 case CS7:
894 upsmr |= UCC_UART_UPSMR_CL_7;
895 supsmr |= UCC_UART_SUPSMR_CL_7;
896 char_length += 7;
897 break;
898 default: /* case CS8 */
899 upsmr |= UCC_UART_UPSMR_CL_8;
900 supsmr |= UCC_UART_SUPSMR_CL_8;
901 char_length += 8;
902 break;
903 }
904
905 /* If CSTOPB is set, we want two stop bits */
906 if (termios->c_cflag & CSTOPB) {
907 upsmr |= UCC_UART_UPSMR_SL;
908 supsmr |= UCC_UART_SUPSMR_SL;
909 char_length++; /* + SL */
910 }
911
912 if (termios->c_cflag & PARENB) {
913 upsmr |= UCC_UART_UPSMR_PEN;
914 supsmr |= UCC_UART_SUPSMR_PEN;
915 char_length++; /* + PEN */
916
917 if (!(termios->c_cflag & PARODD)) {
918 upsmr &= ~(UCC_UART_UPSMR_RPM_MASK |
919 UCC_UART_UPSMR_TPM_MASK);
920 upsmr |= UCC_UART_UPSMR_RPM_EVEN |
921 UCC_UART_UPSMR_TPM_EVEN;
922 supsmr &= ~(UCC_UART_SUPSMR_RPM_MASK |
923 UCC_UART_SUPSMR_TPM_MASK);
924 supsmr |= UCC_UART_SUPSMR_RPM_EVEN |
925 UCC_UART_SUPSMR_TPM_EVEN;
926 }
927 }
928
929 /*
930 * Set up parity check flag
931 */
932 port->read_status_mask = BD_SC_EMPTY | BD_SC_OV;
933 if (termios->c_iflag & INPCK)
934 port->read_status_mask |= BD_SC_FR | BD_SC_PR;
935 if (termios->c_iflag & (BRKINT | PARMRK))
936 port->read_status_mask |= BD_SC_BR;
937
938 /*
939 * Characters to ignore
940 */
941 port->ignore_status_mask = 0;
942 if (termios->c_iflag & IGNPAR)
943 port->ignore_status_mask |= BD_SC_PR | BD_SC_FR;
944 if (termios->c_iflag & IGNBRK) {
945 port->ignore_status_mask |= BD_SC_BR;
946 /*
947 * If we're ignore parity and break indicators, ignore
948 * overruns too. (For real raw support).
949 */
950 if (termios->c_iflag & IGNPAR)
951 port->ignore_status_mask |= BD_SC_OV;
952 }
953 /*
954 * !!! ignore all characters if CREAD is not set
955 */
956 if ((termios->c_cflag & CREAD) == 0)
957 port->read_status_mask &= ~BD_SC_EMPTY;
958
959 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
960
961 /* Do we really need a spinlock here? */
962 spin_lock_irqsave(&port->lock, flags);
963
964 out_be16(&uccp->upsmr, upsmr);
965 if (soft_uart) {
966 out_be16(&uccup->supsmr, supsmr);
967 out_8(&uccup->rx_length, char_length);
968
969 /* Soft-UART requires a 1X multiplier for TX */
970 qe_setbrg(qe_port->us_info.rx_clock, baud, 16);
971 qe_setbrg(qe_port->us_info.tx_clock, baud, 1);
972 } else {
973 qe_setbrg(qe_port->us_info.rx_clock, baud, 16);
974 qe_setbrg(qe_port->us_info.tx_clock, baud, 16);
975 }
976
977 spin_unlock_irqrestore(&port->lock, flags);
978}
979
980/*
981 * Return a pointer to a string that describes what kind of port this is.
982 */
983static const char *qe_uart_type(struct uart_port *port)
984{
985 return "QE";
986}
987
988/*
989 * Allocate any memory and I/O resources required by the port.
990 */
991static int qe_uart_request_port(struct uart_port *port)
992{
993 int ret;
994 struct uart_qe_port *qe_port =
995 container_of(port, struct uart_qe_port, port);
996 struct ucc_slow_info *us_info = &qe_port->us_info;
997 struct ucc_slow_private *uccs;
998 unsigned int rx_size, tx_size;
999 void *bd_virt;
1000 dma_addr_t bd_dma_addr = 0;
1001
1002 ret = ucc_slow_init(us_info, &uccs);
1003 if (ret) {
1004 dev_err(port->dev, "could not initialize UCC%u\n",
1005 qe_port->ucc_num);
1006 return ret;
1007 }
1008
1009 qe_port->us_private = uccs;
1010 qe_port->uccp = uccs->us_regs;
1011 qe_port->uccup = (struct ucc_uart_pram *) uccs->us_pram;
1012 qe_port->rx_bd_base = uccs->rx_bd;
1013 qe_port->tx_bd_base = uccs->tx_bd;
1014
1015 /*
1016 * Allocate the transmit and receive data buffers.
1017 */
1018
1019 rx_size = L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize);
1020 tx_size = L1_CACHE_ALIGN(qe_port->tx_nrfifos * qe_port->tx_fifosize);
1021
1022 bd_virt = dma_alloc_coherent(port->dev, rx_size + tx_size, &bd_dma_addr,
1023 GFP_KERNEL);
1024 if (!bd_virt) {
1025 dev_err(port->dev, "could not allocate buffer descriptors\n");
1026 return -ENOMEM;
1027 }
1028
1029 qe_port->bd_virt = bd_virt;
1030 qe_port->bd_dma_addr = bd_dma_addr;
1031 qe_port->bd_size = rx_size + tx_size;
1032
1033 qe_port->rx_buf = bd_virt;
1034 qe_port->tx_buf = qe_port->rx_buf + rx_size;
1035
1036 return 0;
1037}
1038
1039/*
1040 * Configure the port.
1041 *
1042 * We say we're a CPM-type port because that's mostly true. Once the device
1043 * is configured, this driver operates almost identically to the CPM serial
1044 * driver.
1045 */
1046static void qe_uart_config_port(struct uart_port *port, int flags)
1047{
1048 if (flags & UART_CONFIG_TYPE) {
1049 port->type = PORT_CPM;
1050 qe_uart_request_port(port);
1051 }
1052}
1053
1054/*
1055 * Release any memory and I/O resources that were allocated in
1056 * qe_uart_request_port().
1057 */
1058static void qe_uart_release_port(struct uart_port *port)
1059{
1060 struct uart_qe_port *qe_port =
1061 container_of(port, struct uart_qe_port, port);
1062 struct ucc_slow_private *uccs = qe_port->us_private;
1063
1064 dma_free_coherent(port->dev, qe_port->bd_size, qe_port->bd_virt,
1065 qe_port->bd_dma_addr);
1066
1067 ucc_slow_free(uccs);
1068}
1069
1070/*
1071 * Verify that the data in serial_struct is suitable for this device.
1072 */
1073static int qe_uart_verify_port(struct uart_port *port,
1074 struct serial_struct *ser)
1075{
1076 if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM)
1077 return -EINVAL;
1078
1079 if (ser->irq < 0 || ser->irq >= nr_irqs)
1080 return -EINVAL;
1081
1082 if (ser->baud_base < 9600)
1083 return -EINVAL;
1084
1085 return 0;
1086}
1087/* UART operations
1088 *
1089 * Details on these functions can be found in Documentation/serial/driver
1090 */
1091static struct uart_ops qe_uart_pops = {
1092 .tx_empty = qe_uart_tx_empty,
1093 .set_mctrl = qe_uart_set_mctrl,
1094 .get_mctrl = qe_uart_get_mctrl,
1095 .stop_tx = qe_uart_stop_tx,
1096 .start_tx = qe_uart_start_tx,
1097 .stop_rx = qe_uart_stop_rx,
1098 .enable_ms = qe_uart_enable_ms,
1099 .break_ctl = qe_uart_break_ctl,
1100 .startup = qe_uart_startup,
1101 .shutdown = qe_uart_shutdown,
1102 .set_termios = qe_uart_set_termios,
1103 .type = qe_uart_type,
1104 .release_port = qe_uart_release_port,
1105 .request_port = qe_uart_request_port,
1106 .config_port = qe_uart_config_port,
1107 .verify_port = qe_uart_verify_port,
1108};
1109
1110/*
1111 * Obtain the SOC model number and revision level
1112 *
1113 * This function parses the device tree to obtain the SOC model. It then
1114 * reads the SVR register to the revision.
1115 *
1116 * The device tree stores the SOC model two different ways.
1117 *
1118 * The new way is:
1119 *
1120 * cpu@0 {
1121 * compatible = "PowerPC,8323";
1122 * device_type = "cpu";
1123 * ...
1124 *
1125 *
1126 * The old way is:
1127 * PowerPC,8323@0 {
1128 * device_type = "cpu";
1129 * ...
1130 *
1131 * This code first checks the new way, and then the old way.
1132 */
1133static unsigned int soc_info(unsigned int *rev_h, unsigned int *rev_l)
1134{
1135 struct device_node *np;
1136 const char *soc_string;
1137 unsigned int svr;
1138 unsigned int soc;
1139
1140 /* Find the CPU node */
1141 np = of_find_node_by_type(NULL, "cpu");
1142 if (!np)
1143 return 0;
1144 /* Find the compatible property */
1145 soc_string = of_get_property(np, "compatible", NULL);
1146 if (!soc_string)
1147 /* No compatible property, so try the name. */
1148 soc_string = np->name;
1149
1150 /* Extract the SOC number from the "PowerPC," string */
1151 if ((sscanf(soc_string, "PowerPC,%u", &soc) != 1) || !soc)
1152 return 0;
1153
1154 /* Get the revision from the SVR */
1155 svr = mfspr(SPRN_SVR);
1156 *rev_h = (svr >> 4) & 0xf;
1157 *rev_l = svr & 0xf;
1158
1159 return soc;
1160}
1161
1162/*
1163 * requst_firmware_nowait() callback function
1164 *
1165 * This function is called by the kernel when a firmware is made available,
1166 * or if it times out waiting for the firmware.
1167 */
1168static void uart_firmware_cont(const struct firmware *fw, void *context)
1169{
1170 struct qe_firmware *firmware;
1171 struct device *dev = context;
1172 int ret;
1173
1174 if (!fw) {
1175 dev_err(dev, "firmware not found\n");
1176 return;
1177 }
1178
1179 firmware = (struct qe_firmware *) fw->data;
1180
1181 if (firmware->header.length != fw->size) {
1182 dev_err(dev, "invalid firmware\n");
1183 goto out;
1184 }
1185
1186 ret = qe_upload_firmware(firmware);
1187 if (ret) {
1188 dev_err(dev, "could not load firmware\n");
1189 goto out;
1190 }
1191
1192 firmware_loaded = 1;
1193 out:
1194 release_firmware(fw);
1195}
1196
1197static int ucc_uart_probe(struct platform_device *ofdev,
1198 const struct of_device_id *match)
1199{
1200 struct device_node *np = ofdev->dev.of_node;
1201 const unsigned int *iprop; /* Integer OF properties */
1202 const char *sprop; /* String OF properties */
1203 struct uart_qe_port *qe_port = NULL;
1204 struct resource res;
1205 int ret;
1206
1207 /*
1208 * Determine if we need Soft-UART mode
1209 */
1210 if (of_find_property(np, "soft-uart", NULL)) {
1211 dev_dbg(&ofdev->dev, "using Soft-UART mode\n");
1212 soft_uart = 1;
1213 }
1214
1215 /*
1216 * If we are using Soft-UART, determine if we need to upload the
1217 * firmware, too.
1218 */
1219 if (soft_uart) {
1220 struct qe_firmware_info *qe_fw_info;
1221
1222 qe_fw_info = qe_get_firmware_info();
1223
1224 /* Check if the firmware has been uploaded. */
1225 if (qe_fw_info && strstr(qe_fw_info->id, "Soft-UART")) {
1226 firmware_loaded = 1;
1227 } else {
1228 char filename[32];
1229 unsigned int soc;
1230 unsigned int rev_h;
1231 unsigned int rev_l;
1232
1233 soc = soc_info(&rev_h, &rev_l);
1234 if (!soc) {
1235 dev_err(&ofdev->dev, "unknown CPU model\n");
1236 return -ENXIO;
1237 }
1238 sprintf(filename, "fsl_qe_ucode_uart_%u_%u%u.bin",
1239 soc, rev_h, rev_l);
1240
1241 dev_info(&ofdev->dev, "waiting for firmware %s\n",
1242 filename);
1243
1244 /*
1245 * We call request_firmware_nowait instead of
1246 * request_firmware so that the driver can load and
1247 * initialize the ports without holding up the rest of
1248 * the kernel. If hotplug support is enabled in the
1249 * kernel, then we use it.
1250 */
1251 ret = request_firmware_nowait(THIS_MODULE,
1252 FW_ACTION_HOTPLUG, filename, &ofdev->dev,
1253 GFP_KERNEL, &ofdev->dev, uart_firmware_cont);
1254 if (ret) {
1255 dev_err(&ofdev->dev,
1256 "could not load firmware %s\n",
1257 filename);
1258 return ret;
1259 }
1260 }
1261 }
1262
1263 qe_port = kzalloc(sizeof(struct uart_qe_port), GFP_KERNEL);
1264 if (!qe_port) {
1265 dev_err(&ofdev->dev, "can't allocate QE port structure\n");
1266 return -ENOMEM;
1267 }
1268
1269 /* Search for IRQ and mapbase */
1270 ret = of_address_to_resource(np, 0, &res);
1271 if (ret) {
1272 dev_err(&ofdev->dev, "missing 'reg' property in device tree\n");
1273 kfree(qe_port);
1274 return ret;
1275 }
1276 if (!res.start) {
1277 dev_err(&ofdev->dev, "invalid 'reg' property in device tree\n");
1278 kfree(qe_port);
1279 return -EINVAL;
1280 }
1281 qe_port->port.mapbase = res.start;
1282
1283 /* Get the UCC number (device ID) */
1284 /* UCCs are numbered 1-7 */
1285 iprop = of_get_property(np, "cell-index", NULL);
1286 if (!iprop) {
1287 iprop = of_get_property(np, "device-id", NULL);
1288 if (!iprop) {
1289 kfree(qe_port);
1290 dev_err(&ofdev->dev, "UCC is unspecified in "
1291 "device tree\n");
1292 return -EINVAL;
1293 }
1294 }
1295
1296 if ((*iprop < 1) || (*iprop > UCC_MAX_NUM)) {
1297 dev_err(&ofdev->dev, "no support for UCC%u\n", *iprop);
1298 kfree(qe_port);
1299 return -ENODEV;
1300 }
1301 qe_port->ucc_num = *iprop - 1;
1302
1303 /*
1304 * In the future, we should not require the BRG to be specified in the
1305 * device tree. If no clock-source is specified, then just pick a BRG
1306 * to use. This requires a new QE library function that manages BRG
1307 * assignments.
1308 */
1309
1310 sprop = of_get_property(np, "rx-clock-name", NULL);
1311 if (!sprop) {
1312 dev_err(&ofdev->dev, "missing rx-clock-name in device tree\n");
1313 kfree(qe_port);
1314 return -ENODEV;
1315 }
1316
1317 qe_port->us_info.rx_clock = qe_clock_source(sprop);
1318 if ((qe_port->us_info.rx_clock < QE_BRG1) ||
1319 (qe_port->us_info.rx_clock > QE_BRG16)) {
1320 dev_err(&ofdev->dev, "rx-clock-name must be a BRG for UART\n");
1321 kfree(qe_port);
1322 return -ENODEV;
1323 }
1324
1325#ifdef LOOPBACK
1326 /* In internal loopback mode, TX and RX must use the same clock */
1327 qe_port->us_info.tx_clock = qe_port->us_info.rx_clock;
1328#else
1329 sprop = of_get_property(np, "tx-clock-name", NULL);
1330 if (!sprop) {
1331 dev_err(&ofdev->dev, "missing tx-clock-name in device tree\n");
1332 kfree(qe_port);
1333 return -ENODEV;
1334 }
1335 qe_port->us_info.tx_clock = qe_clock_source(sprop);
1336#endif
1337 if ((qe_port->us_info.tx_clock < QE_BRG1) ||
1338 (qe_port->us_info.tx_clock > QE_BRG16)) {
1339 dev_err(&ofdev->dev, "tx-clock-name must be a BRG for UART\n");
1340 kfree(qe_port);
1341 return -ENODEV;
1342 }
1343
1344 /* Get the port number, numbered 0-3 */
1345 iprop = of_get_property(np, "port-number", NULL);
1346 if (!iprop) {
1347 dev_err(&ofdev->dev, "missing port-number in device tree\n");
1348 kfree(qe_port);
1349 return -EINVAL;
1350 }
1351 qe_port->port.line = *iprop;
1352 if (qe_port->port.line >= UCC_MAX_UART) {
1353 dev_err(&ofdev->dev, "port-number must be 0-%u\n",
1354 UCC_MAX_UART - 1);
1355 kfree(qe_port);
1356 return -EINVAL;
1357 }
1358
1359 qe_port->port.irq = irq_of_parse_and_map(np, 0);
1360 if (qe_port->port.irq == NO_IRQ) {
1361 dev_err(&ofdev->dev, "could not map IRQ for UCC%u\n",
1362 qe_port->ucc_num + 1);
1363 kfree(qe_port);
1364 return -EINVAL;
1365 }
1366
1367 /*
1368 * Newer device trees have an "fsl,qe" compatible property for the QE
1369 * node, but we still need to support older device trees.
1370 */
1371 np = of_find_compatible_node(NULL, NULL, "fsl,qe");
1372 if (!np) {
1373 np = of_find_node_by_type(NULL, "qe");
1374 if (!np) {
1375 dev_err(&ofdev->dev, "could not find 'qe' node\n");
1376 kfree(qe_port);
1377 return -EINVAL;
1378 }
1379 }
1380
1381 iprop = of_get_property(np, "brg-frequency", NULL);
1382 if (!iprop) {
1383 dev_err(&ofdev->dev,
1384 "missing brg-frequency in device tree\n");
1385 kfree(qe_port);
1386 return -EINVAL;
1387 }
1388
1389 if (*iprop)
1390 qe_port->port.uartclk = *iprop;
1391 else {
1392 /*
1393 * Older versions of U-Boot do not initialize the brg-frequency
1394 * property, so in this case we assume the BRG frequency is
1395 * half the QE bus frequency.
1396 */
1397 iprop = of_get_property(np, "bus-frequency", NULL);
1398 if (!iprop) {
1399 dev_err(&ofdev->dev,
1400 "missing QE bus-frequency in device tree\n");
1401 kfree(qe_port);
1402 return -EINVAL;
1403 }
1404 if (*iprop)
1405 qe_port->port.uartclk = *iprop / 2;
1406 else {
1407 dev_err(&ofdev->dev,
1408 "invalid QE bus-frequency in device tree\n");
1409 kfree(qe_port);
1410 return -EINVAL;
1411 }
1412 }
1413
1414 spin_lock_init(&qe_port->port.lock);
1415 qe_port->np = np;
1416 qe_port->port.dev = &ofdev->dev;
1417 qe_port->port.ops = &qe_uart_pops;
1418 qe_port->port.iotype = UPIO_MEM;
1419
1420 qe_port->tx_nrfifos = TX_NUM_FIFO;
1421 qe_port->tx_fifosize = TX_BUF_SIZE;
1422 qe_port->rx_nrfifos = RX_NUM_FIFO;
1423 qe_port->rx_fifosize = RX_BUF_SIZE;
1424
1425 qe_port->wait_closing = UCC_WAIT_CLOSING;
1426 qe_port->port.fifosize = 512;
1427 qe_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
1428
1429 qe_port->us_info.ucc_num = qe_port->ucc_num;
1430 qe_port->us_info.regs = (phys_addr_t) res.start;
1431 qe_port->us_info.irq = qe_port->port.irq;
1432
1433 qe_port->us_info.rx_bd_ring_len = qe_port->rx_nrfifos;
1434 qe_port->us_info.tx_bd_ring_len = qe_port->tx_nrfifos;
1435
1436 /* Make sure ucc_slow_init() initializes both TX and RX */
1437 qe_port->us_info.init_tx = 1;
1438 qe_port->us_info.init_rx = 1;
1439
1440 /* Add the port to the uart sub-system. This will cause
1441 * qe_uart_config_port() to be called, so the us_info structure must
1442 * be initialized.
1443 */
1444 ret = uart_add_one_port(&ucc_uart_driver, &qe_port->port);
1445 if (ret) {
1446 dev_err(&ofdev->dev, "could not add /dev/ttyQE%u\n",
1447 qe_port->port.line);
1448 kfree(qe_port);
1449 return ret;
1450 }
1451
1452 dev_set_drvdata(&ofdev->dev, qe_port);
1453
1454 dev_info(&ofdev->dev, "UCC%u assigned to /dev/ttyQE%u\n",
1455 qe_port->ucc_num + 1, qe_port->port.line);
1456
1457 /* Display the mknod command for this device */
1458 dev_dbg(&ofdev->dev, "mknod command is 'mknod /dev/ttyQE%u c %u %u'\n",
1459 qe_port->port.line, SERIAL_QE_MAJOR,
1460 SERIAL_QE_MINOR + qe_port->port.line);
1461
1462 return 0;
1463}
1464
1465static int ucc_uart_remove(struct platform_device *ofdev)
1466{
1467 struct uart_qe_port *qe_port = dev_get_drvdata(&ofdev->dev);
1468
1469 dev_info(&ofdev->dev, "removing /dev/ttyQE%u\n", qe_port->port.line);
1470
1471 uart_remove_one_port(&ucc_uart_driver, &qe_port->port);
1472
1473 dev_set_drvdata(&ofdev->dev, NULL);
1474 kfree(qe_port);
1475
1476 return 0;
1477}
1478
1479static struct of_device_id ucc_uart_match[] = {
1480 {
1481 .type = "serial",
1482 .compatible = "ucc_uart",
1483 },
1484 {},
1485};
1486MODULE_DEVICE_TABLE(of, ucc_uart_match);
1487
1488static struct of_platform_driver ucc_uart_of_driver = {
1489 .driver = {
1490 .name = "ucc_uart",
1491 .owner = THIS_MODULE,
1492 .of_match_table = ucc_uart_match,
1493 },
1494 .probe = ucc_uart_probe,
1495 .remove = ucc_uart_remove,
1496};
1497
1498static int __init ucc_uart_init(void)
1499{
1500 int ret;
1501
1502 printk(KERN_INFO "Freescale QUICC Engine UART device driver\n");
1503#ifdef LOOPBACK
1504 printk(KERN_INFO "ucc-uart: Using loopback mode\n");
1505#endif
1506
1507 ret = uart_register_driver(&ucc_uart_driver);
1508 if (ret) {
1509 printk(KERN_ERR "ucc-uart: could not register UART driver\n");
1510 return ret;
1511 }
1512
1513 ret = of_register_platform_driver(&ucc_uart_of_driver);
1514 if (ret)
1515 printk(KERN_ERR
1516 "ucc-uart: could not register platform driver\n");
1517
1518 return ret;
1519}
1520
1521static void __exit ucc_uart_exit(void)
1522{
1523 printk(KERN_INFO
1524 "Freescale QUICC Engine UART device driver unloading\n");
1525
1526 of_unregister_platform_driver(&ucc_uart_of_driver);
1527 uart_unregister_driver(&ucc_uart_driver);
1528}
1529
1530module_init(ucc_uart_init);
1531module_exit(ucc_uart_exit);
1532
1533MODULE_DESCRIPTION("Freescale QUICC Engine (QE) UART");
1534MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1535MODULE_LICENSE("GPL v2");
1536MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_QE_MAJOR);
1537
diff --git a/drivers/serial/vr41xx_siu.c b/drivers/serial/vr41xx_siu.c
deleted file mode 100644
index 3beb6ab4fa68..000000000000
--- a/drivers/serial/vr41xx_siu.c
+++ /dev/null
@@ -1,978 +0,0 @@
1/*
2 * Driver for NEC VR4100 series Serial Interface Unit.
3 *
4 * Copyright (C) 2004-2008 Yoichi Yuasa <yuasa@linux-mips.org>
5 *
6 * Based on drivers/serial/8250.c, by Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#if defined(CONFIG_SERIAL_VR41XX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
24#define SUPPORT_SYSRQ
25#endif
26
27#include <linux/console.h>
28#include <linux/errno.h>
29#include <linux/init.h>
30#include <linux/interrupt.h>
31#include <linux/ioport.h>
32#include <linux/module.h>
33#include <linux/platform_device.h>
34#include <linux/serial.h>
35#include <linux/serial_core.h>
36#include <linux/serial_reg.h>
37#include <linux/tty.h>
38#include <linux/tty_flip.h>
39
40#include <asm/io.h>
41#include <asm/vr41xx/siu.h>
42#include <asm/vr41xx/vr41xx.h>
43
44#define SIU_BAUD_BASE 1152000
45#define SIU_MAJOR 204
46#define SIU_MINOR_BASE 82
47
48#define RX_MAX_COUNT 256
49#define TX_MAX_COUNT 15
50
51#define SIUIRSEL 0x08
52 #define TMICMODE 0x20
53 #define TMICTX 0x10
54 #define IRMSEL 0x0c
55 #define IRMSEL_HP 0x08
56 #define IRMSEL_TEMIC 0x04
57 #define IRMSEL_SHARP 0x00
58 #define IRUSESEL 0x02
59 #define SIRSEL 0x01
60
61static struct uart_port siu_uart_ports[SIU_PORTS_MAX] = {
62 [0 ... SIU_PORTS_MAX-1] = {
63 .lock = __SPIN_LOCK_UNLOCKED(siu_uart_ports->lock),
64 .irq = -1,
65 },
66};
67
68#ifdef CONFIG_SERIAL_VR41XX_CONSOLE
69static uint8_t lsr_break_flag[SIU_PORTS_MAX];
70#endif
71
72#define siu_read(port, offset) readb((port)->membase + (offset))
73#define siu_write(port, offset, value) writeb((value), (port)->membase + (offset))
74
75void vr41xx_select_siu_interface(siu_interface_t interface)
76{
77 struct uart_port *port;
78 unsigned long flags;
79 uint8_t irsel;
80
81 port = &siu_uart_ports[0];
82
83 spin_lock_irqsave(&port->lock, flags);
84
85 irsel = siu_read(port, SIUIRSEL);
86 if (interface == SIU_INTERFACE_IRDA)
87 irsel |= SIRSEL;
88 else
89 irsel &= ~SIRSEL;
90 siu_write(port, SIUIRSEL, irsel);
91
92 spin_unlock_irqrestore(&port->lock, flags);
93}
94EXPORT_SYMBOL_GPL(vr41xx_select_siu_interface);
95
96void vr41xx_use_irda(irda_use_t use)
97{
98 struct uart_port *port;
99 unsigned long flags;
100 uint8_t irsel;
101
102 port = &siu_uart_ports[0];
103
104 spin_lock_irqsave(&port->lock, flags);
105
106 irsel = siu_read(port, SIUIRSEL);
107 if (use == FIR_USE_IRDA)
108 irsel |= IRUSESEL;
109 else
110 irsel &= ~IRUSESEL;
111 siu_write(port, SIUIRSEL, irsel);
112
113 spin_unlock_irqrestore(&port->lock, flags);
114}
115EXPORT_SYMBOL_GPL(vr41xx_use_irda);
116
117void vr41xx_select_irda_module(irda_module_t module, irda_speed_t speed)
118{
119 struct uart_port *port;
120 unsigned long flags;
121 uint8_t irsel;
122
123 port = &siu_uart_ports[0];
124
125 spin_lock_irqsave(&port->lock, flags);
126
127 irsel = siu_read(port, SIUIRSEL);
128 irsel &= ~(IRMSEL | TMICTX | TMICMODE);
129 switch (module) {
130 case SHARP_IRDA:
131 irsel |= IRMSEL_SHARP;
132 break;
133 case TEMIC_IRDA:
134 irsel |= IRMSEL_TEMIC | TMICMODE;
135 if (speed == IRDA_TX_4MBPS)
136 irsel |= TMICTX;
137 break;
138 case HP_IRDA:
139 irsel |= IRMSEL_HP;
140 break;
141 default:
142 break;
143 }
144 siu_write(port, SIUIRSEL, irsel);
145
146 spin_unlock_irqrestore(&port->lock, flags);
147}
148EXPORT_SYMBOL_GPL(vr41xx_select_irda_module);
149
150static inline void siu_clear_fifo(struct uart_port *port)
151{
152 siu_write(port, UART_FCR, UART_FCR_ENABLE_FIFO);
153 siu_write(port, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR |
154 UART_FCR_CLEAR_XMIT);
155 siu_write(port, UART_FCR, 0);
156}
157
158static inline unsigned long siu_port_size(struct uart_port *port)
159{
160 switch (port->type) {
161 case PORT_VR41XX_SIU:
162 return 11UL;
163 case PORT_VR41XX_DSIU:
164 return 8UL;
165 }
166
167 return 0;
168}
169
170static inline unsigned int siu_check_type(struct uart_port *port)
171{
172 if (port->line == 0)
173 return PORT_VR41XX_SIU;
174 if (port->line == 1 && port->irq != -1)
175 return PORT_VR41XX_DSIU;
176
177 return PORT_UNKNOWN;
178}
179
180static inline const char *siu_type_name(struct uart_port *port)
181{
182 switch (port->type) {
183 case PORT_VR41XX_SIU:
184 return "SIU";
185 case PORT_VR41XX_DSIU:
186 return "DSIU";
187 }
188
189 return NULL;
190}
191
192static unsigned int siu_tx_empty(struct uart_port *port)
193{
194 uint8_t lsr;
195
196 lsr = siu_read(port, UART_LSR);
197 if (lsr & UART_LSR_TEMT)
198 return TIOCSER_TEMT;
199
200 return 0;
201}
202
203static void siu_set_mctrl(struct uart_port *port, unsigned int mctrl)
204{
205 uint8_t mcr = 0;
206
207 if (mctrl & TIOCM_DTR)
208 mcr |= UART_MCR_DTR;
209 if (mctrl & TIOCM_RTS)
210 mcr |= UART_MCR_RTS;
211 if (mctrl & TIOCM_OUT1)
212 mcr |= UART_MCR_OUT1;
213 if (mctrl & TIOCM_OUT2)
214 mcr |= UART_MCR_OUT2;
215 if (mctrl & TIOCM_LOOP)
216 mcr |= UART_MCR_LOOP;
217
218 siu_write(port, UART_MCR, mcr);
219}
220
221static unsigned int siu_get_mctrl(struct uart_port *port)
222{
223 uint8_t msr;
224 unsigned int mctrl = 0;
225
226 msr = siu_read(port, UART_MSR);
227 if (msr & UART_MSR_DCD)
228 mctrl |= TIOCM_CAR;
229 if (msr & UART_MSR_RI)
230 mctrl |= TIOCM_RNG;
231 if (msr & UART_MSR_DSR)
232 mctrl |= TIOCM_DSR;
233 if (msr & UART_MSR_CTS)
234 mctrl |= TIOCM_CTS;
235
236 return mctrl;
237}
238
239static void siu_stop_tx(struct uart_port *port)
240{
241 unsigned long flags;
242 uint8_t ier;
243
244 spin_lock_irqsave(&port->lock, flags);
245
246 ier = siu_read(port, UART_IER);
247 ier &= ~UART_IER_THRI;
248 siu_write(port, UART_IER, ier);
249
250 spin_unlock_irqrestore(&port->lock, flags);
251}
252
253static void siu_start_tx(struct uart_port *port)
254{
255 unsigned long flags;
256 uint8_t ier;
257
258 spin_lock_irqsave(&port->lock, flags);
259
260 ier = siu_read(port, UART_IER);
261 ier |= UART_IER_THRI;
262 siu_write(port, UART_IER, ier);
263
264 spin_unlock_irqrestore(&port->lock, flags);
265}
266
267static void siu_stop_rx(struct uart_port *port)
268{
269 unsigned long flags;
270 uint8_t ier;
271
272 spin_lock_irqsave(&port->lock, flags);
273
274 ier = siu_read(port, UART_IER);
275 ier &= ~UART_IER_RLSI;
276 siu_write(port, UART_IER, ier);
277
278 port->read_status_mask &= ~UART_LSR_DR;
279
280 spin_unlock_irqrestore(&port->lock, flags);
281}
282
283static void siu_enable_ms(struct uart_port *port)
284{
285 unsigned long flags;
286 uint8_t ier;
287
288 spin_lock_irqsave(&port->lock, flags);
289
290 ier = siu_read(port, UART_IER);
291 ier |= UART_IER_MSI;
292 siu_write(port, UART_IER, ier);
293
294 spin_unlock_irqrestore(&port->lock, flags);
295}
296
297static void siu_break_ctl(struct uart_port *port, int ctl)
298{
299 unsigned long flags;
300 uint8_t lcr;
301
302 spin_lock_irqsave(&port->lock, flags);
303
304 lcr = siu_read(port, UART_LCR);
305 if (ctl == -1)
306 lcr |= UART_LCR_SBC;
307 else
308 lcr &= ~UART_LCR_SBC;
309 siu_write(port, UART_LCR, lcr);
310
311 spin_unlock_irqrestore(&port->lock, flags);
312}
313
314static inline void receive_chars(struct uart_port *port, uint8_t *status)
315{
316 struct tty_struct *tty;
317 uint8_t lsr, ch;
318 char flag;
319 int max_count = RX_MAX_COUNT;
320
321 tty = port->state->port.tty;
322 lsr = *status;
323
324 do {
325 ch = siu_read(port, UART_RX);
326 port->icount.rx++;
327 flag = TTY_NORMAL;
328
329#ifdef CONFIG_SERIAL_VR41XX_CONSOLE
330 lsr |= lsr_break_flag[port->line];
331 lsr_break_flag[port->line] = 0;
332#endif
333 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_FE |
334 UART_LSR_PE | UART_LSR_OE))) {
335 if (lsr & UART_LSR_BI) {
336 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
337 port->icount.brk++;
338
339 if (uart_handle_break(port))
340 goto ignore_char;
341 }
342
343 if (lsr & UART_LSR_FE)
344 port->icount.frame++;
345 if (lsr & UART_LSR_PE)
346 port->icount.parity++;
347 if (lsr & UART_LSR_OE)
348 port->icount.overrun++;
349
350 lsr &= port->read_status_mask;
351 if (lsr & UART_LSR_BI)
352 flag = TTY_BREAK;
353 if (lsr & UART_LSR_FE)
354 flag = TTY_FRAME;
355 if (lsr & UART_LSR_PE)
356 flag = TTY_PARITY;
357 }
358
359 if (uart_handle_sysrq_char(port, ch))
360 goto ignore_char;
361
362 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
363
364 ignore_char:
365 lsr = siu_read(port, UART_LSR);
366 } while ((lsr & UART_LSR_DR) && (max_count-- > 0));
367
368 tty_flip_buffer_push(tty);
369
370 *status = lsr;
371}
372
373static inline void check_modem_status(struct uart_port *port)
374{
375 uint8_t msr;
376
377 msr = siu_read(port, UART_MSR);
378 if ((msr & UART_MSR_ANY_DELTA) == 0)
379 return;
380 if (msr & UART_MSR_DDCD)
381 uart_handle_dcd_change(port, msr & UART_MSR_DCD);
382 if (msr & UART_MSR_TERI)
383 port->icount.rng++;
384 if (msr & UART_MSR_DDSR)
385 port->icount.dsr++;
386 if (msr & UART_MSR_DCTS)
387 uart_handle_cts_change(port, msr & UART_MSR_CTS);
388
389 wake_up_interruptible(&port->state->port.delta_msr_wait);
390}
391
392static inline void transmit_chars(struct uart_port *port)
393{
394 struct circ_buf *xmit;
395 int max_count = TX_MAX_COUNT;
396
397 xmit = &port->state->xmit;
398
399 if (port->x_char) {
400 siu_write(port, UART_TX, port->x_char);
401 port->icount.tx++;
402 port->x_char = 0;
403 return;
404 }
405
406 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
407 siu_stop_tx(port);
408 return;
409 }
410
411 do {
412 siu_write(port, UART_TX, xmit->buf[xmit->tail]);
413 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
414 port->icount.tx++;
415 if (uart_circ_empty(xmit))
416 break;
417 } while (max_count-- > 0);
418
419 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
420 uart_write_wakeup(port);
421
422 if (uart_circ_empty(xmit))
423 siu_stop_tx(port);
424}
425
426static irqreturn_t siu_interrupt(int irq, void *dev_id)
427{
428 struct uart_port *port;
429 uint8_t iir, lsr;
430
431 port = (struct uart_port *)dev_id;
432
433 iir = siu_read(port, UART_IIR);
434 if (iir & UART_IIR_NO_INT)
435 return IRQ_NONE;
436
437 lsr = siu_read(port, UART_LSR);
438 if (lsr & UART_LSR_DR)
439 receive_chars(port, &lsr);
440
441 check_modem_status(port);
442
443 if (lsr & UART_LSR_THRE)
444 transmit_chars(port);
445
446 return IRQ_HANDLED;
447}
448
449static int siu_startup(struct uart_port *port)
450{
451 int retval;
452
453 if (port->membase == NULL)
454 return -ENODEV;
455
456 siu_clear_fifo(port);
457
458 (void)siu_read(port, UART_LSR);
459 (void)siu_read(port, UART_RX);
460 (void)siu_read(port, UART_IIR);
461 (void)siu_read(port, UART_MSR);
462
463 if (siu_read(port, UART_LSR) == 0xff)
464 return -ENODEV;
465
466 retval = request_irq(port->irq, siu_interrupt, 0, siu_type_name(port), port);
467 if (retval)
468 return retval;
469
470 if (port->type == PORT_VR41XX_DSIU)
471 vr41xx_enable_dsiuint(DSIUINT_ALL);
472
473 siu_write(port, UART_LCR, UART_LCR_WLEN8);
474
475 spin_lock_irq(&port->lock);
476 siu_set_mctrl(port, port->mctrl);
477 spin_unlock_irq(&port->lock);
478
479 siu_write(port, UART_IER, UART_IER_RLSI | UART_IER_RDI);
480
481 (void)siu_read(port, UART_LSR);
482 (void)siu_read(port, UART_RX);
483 (void)siu_read(port, UART_IIR);
484 (void)siu_read(port, UART_MSR);
485
486 return 0;
487}
488
489static void siu_shutdown(struct uart_port *port)
490{
491 unsigned long flags;
492 uint8_t lcr;
493
494 siu_write(port, UART_IER, 0);
495
496 spin_lock_irqsave(&port->lock, flags);
497
498 port->mctrl &= ~TIOCM_OUT2;
499 siu_set_mctrl(port, port->mctrl);
500
501 spin_unlock_irqrestore(&port->lock, flags);
502
503 lcr = siu_read(port, UART_LCR);
504 lcr &= ~UART_LCR_SBC;
505 siu_write(port, UART_LCR, lcr);
506
507 siu_clear_fifo(port);
508
509 (void)siu_read(port, UART_RX);
510
511 if (port->type == PORT_VR41XX_DSIU)
512 vr41xx_disable_dsiuint(DSIUINT_ALL);
513
514 free_irq(port->irq, port);
515}
516
517static void siu_set_termios(struct uart_port *port, struct ktermios *new,
518 struct ktermios *old)
519{
520 tcflag_t c_cflag, c_iflag;
521 uint8_t lcr, fcr, ier;
522 unsigned int baud, quot;
523 unsigned long flags;
524
525 c_cflag = new->c_cflag;
526 switch (c_cflag & CSIZE) {
527 case CS5:
528 lcr = UART_LCR_WLEN5;
529 break;
530 case CS6:
531 lcr = UART_LCR_WLEN6;
532 break;
533 case CS7:
534 lcr = UART_LCR_WLEN7;
535 break;
536 default:
537 lcr = UART_LCR_WLEN8;
538 break;
539 }
540
541 if (c_cflag & CSTOPB)
542 lcr |= UART_LCR_STOP;
543 if (c_cflag & PARENB)
544 lcr |= UART_LCR_PARITY;
545 if ((c_cflag & PARODD) != PARODD)
546 lcr |= UART_LCR_EPAR;
547 if (c_cflag & CMSPAR)
548 lcr |= UART_LCR_SPAR;
549
550 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk/16);
551 quot = uart_get_divisor(port, baud);
552
553 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10;
554
555 spin_lock_irqsave(&port->lock, flags);
556
557 uart_update_timeout(port, c_cflag, baud);
558
559 c_iflag = new->c_iflag;
560
561 port->read_status_mask = UART_LSR_THRE | UART_LSR_OE | UART_LSR_DR;
562 if (c_iflag & INPCK)
563 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
564 if (c_iflag & (BRKINT | PARMRK))
565 port->read_status_mask |= UART_LSR_BI;
566
567 port->ignore_status_mask = 0;
568 if (c_iflag & IGNPAR)
569 port->ignore_status_mask |= UART_LSR_FE | UART_LSR_PE;
570 if (c_iflag & IGNBRK) {
571 port->ignore_status_mask |= UART_LSR_BI;
572 if (c_iflag & IGNPAR)
573 port->ignore_status_mask |= UART_LSR_OE;
574 }
575
576 if ((c_cflag & CREAD) == 0)
577 port->ignore_status_mask |= UART_LSR_DR;
578
579 ier = siu_read(port, UART_IER);
580 ier &= ~UART_IER_MSI;
581 if (UART_ENABLE_MS(port, c_cflag))
582 ier |= UART_IER_MSI;
583 siu_write(port, UART_IER, ier);
584
585 siu_write(port, UART_LCR, lcr | UART_LCR_DLAB);
586
587 siu_write(port, UART_DLL, (uint8_t)quot);
588 siu_write(port, UART_DLM, (uint8_t)(quot >> 8));
589
590 siu_write(port, UART_LCR, lcr);
591
592 siu_write(port, UART_FCR, fcr);
593
594 siu_set_mctrl(port, port->mctrl);
595
596 spin_unlock_irqrestore(&port->lock, flags);
597}
598
599static void siu_pm(struct uart_port *port, unsigned int state, unsigned int oldstate)
600{
601 switch (state) {
602 case 0:
603 switch (port->type) {
604 case PORT_VR41XX_SIU:
605 vr41xx_supply_clock(SIU_CLOCK);
606 break;
607 case PORT_VR41XX_DSIU:
608 vr41xx_supply_clock(DSIU_CLOCK);
609 break;
610 }
611 break;
612 case 3:
613 switch (port->type) {
614 case PORT_VR41XX_SIU:
615 vr41xx_mask_clock(SIU_CLOCK);
616 break;
617 case PORT_VR41XX_DSIU:
618 vr41xx_mask_clock(DSIU_CLOCK);
619 break;
620 }
621 break;
622 }
623}
624
625static const char *siu_type(struct uart_port *port)
626{
627 return siu_type_name(port);
628}
629
630static void siu_release_port(struct uart_port *port)
631{
632 unsigned long size;
633
634 if (port->flags & UPF_IOREMAP) {
635 iounmap(port->membase);
636 port->membase = NULL;
637 }
638
639 size = siu_port_size(port);
640 release_mem_region(port->mapbase, size);
641}
642
643static int siu_request_port(struct uart_port *port)
644{
645 unsigned long size;
646 struct resource *res;
647
648 size = siu_port_size(port);
649 res = request_mem_region(port->mapbase, size, siu_type_name(port));
650 if (res == NULL)
651 return -EBUSY;
652
653 if (port->flags & UPF_IOREMAP) {
654 port->membase = ioremap(port->mapbase, size);
655 if (port->membase == NULL) {
656 release_resource(res);
657 return -ENOMEM;
658 }
659 }
660
661 return 0;
662}
663
664static void siu_config_port(struct uart_port *port, int flags)
665{
666 if (flags & UART_CONFIG_TYPE) {
667 port->type = siu_check_type(port);
668 (void)siu_request_port(port);
669 }
670}
671
672static int siu_verify_port(struct uart_port *port, struct serial_struct *serial)
673{
674 if (port->type != PORT_VR41XX_SIU && port->type != PORT_VR41XX_DSIU)
675 return -EINVAL;
676 if (port->irq != serial->irq)
677 return -EINVAL;
678 if (port->iotype != serial->io_type)
679 return -EINVAL;
680 if (port->mapbase != (unsigned long)serial->iomem_base)
681 return -EINVAL;
682
683 return 0;
684}
685
686static struct uart_ops siu_uart_ops = {
687 .tx_empty = siu_tx_empty,
688 .set_mctrl = siu_set_mctrl,
689 .get_mctrl = siu_get_mctrl,
690 .stop_tx = siu_stop_tx,
691 .start_tx = siu_start_tx,
692 .stop_rx = siu_stop_rx,
693 .enable_ms = siu_enable_ms,
694 .break_ctl = siu_break_ctl,
695 .startup = siu_startup,
696 .shutdown = siu_shutdown,
697 .set_termios = siu_set_termios,
698 .pm = siu_pm,
699 .type = siu_type,
700 .release_port = siu_release_port,
701 .request_port = siu_request_port,
702 .config_port = siu_config_port,
703 .verify_port = siu_verify_port,
704};
705
706static int siu_init_ports(struct platform_device *pdev)
707{
708 struct uart_port *port;
709 struct resource *res;
710 int *type = pdev->dev.platform_data;
711 int i;
712
713 if (!type)
714 return 0;
715
716 port = siu_uart_ports;
717 for (i = 0; i < SIU_PORTS_MAX; i++) {
718 port->type = type[i];
719 if (port->type == PORT_UNKNOWN)
720 continue;
721 port->irq = platform_get_irq(pdev, i);
722 port->uartclk = SIU_BAUD_BASE * 16;
723 port->fifosize = 16;
724 port->regshift = 0;
725 port->iotype = UPIO_MEM;
726 port->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
727 port->line = i;
728 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
729 port->mapbase = res->start;
730 port++;
731 }
732
733 return i;
734}
735
736#ifdef CONFIG_SERIAL_VR41XX_CONSOLE
737
738#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
739
740static void wait_for_xmitr(struct uart_port *port)
741{
742 int timeout = 10000;
743 uint8_t lsr, msr;
744
745 do {
746 lsr = siu_read(port, UART_LSR);
747 if (lsr & UART_LSR_BI)
748 lsr_break_flag[port->line] = UART_LSR_BI;
749
750 if ((lsr & BOTH_EMPTY) == BOTH_EMPTY)
751 break;
752 } while (timeout-- > 0);
753
754 if (port->flags & UPF_CONS_FLOW) {
755 timeout = 1000000;
756
757 do {
758 msr = siu_read(port, UART_MSR);
759 if ((msr & UART_MSR_CTS) != 0)
760 break;
761 } while (timeout-- > 0);
762 }
763}
764
765static void siu_console_putchar(struct uart_port *port, int ch)
766{
767 wait_for_xmitr(port);
768 siu_write(port, UART_TX, ch);
769}
770
771static void siu_console_write(struct console *con, const char *s, unsigned count)
772{
773 struct uart_port *port;
774 uint8_t ier;
775
776 port = &siu_uart_ports[con->index];
777
778 ier = siu_read(port, UART_IER);
779 siu_write(port, UART_IER, 0);
780
781 uart_console_write(port, s, count, siu_console_putchar);
782
783 wait_for_xmitr(port);
784 siu_write(port, UART_IER, ier);
785}
786
787static int __init siu_console_setup(struct console *con, char *options)
788{
789 struct uart_port *port;
790 int baud = 9600;
791 int parity = 'n';
792 int bits = 8;
793 int flow = 'n';
794
795 if (con->index >= SIU_PORTS_MAX)
796 con->index = 0;
797
798 port = &siu_uart_ports[con->index];
799 if (port->membase == NULL) {
800 if (port->mapbase == 0)
801 return -ENODEV;
802 port->membase = ioremap(port->mapbase, siu_port_size(port));
803 }
804
805 if (port->type == PORT_VR41XX_SIU)
806 vr41xx_select_siu_interface(SIU_INTERFACE_RS232C);
807
808 if (options != NULL)
809 uart_parse_options(options, &baud, &parity, &bits, &flow);
810
811 return uart_set_options(port, con, baud, parity, bits, flow);
812}
813
814static struct uart_driver siu_uart_driver;
815
816static struct console siu_console = {
817 .name = "ttyVR",
818 .write = siu_console_write,
819 .device = uart_console_device,
820 .setup = siu_console_setup,
821 .flags = CON_PRINTBUFFER,
822 .index = -1,
823 .data = &siu_uart_driver,
824};
825
826static int __devinit siu_console_init(void)
827{
828 struct uart_port *port;
829 int i;
830
831 for (i = 0; i < SIU_PORTS_MAX; i++) {
832 port = &siu_uart_ports[i];
833 port->ops = &siu_uart_ops;
834 }
835
836 register_console(&siu_console);
837
838 return 0;
839}
840
841console_initcall(siu_console_init);
842
843void __init vr41xx_siu_early_setup(struct uart_port *port)
844{
845 if (port->type == PORT_UNKNOWN)
846 return;
847
848 siu_uart_ports[port->line].line = port->line;
849 siu_uart_ports[port->line].type = port->type;
850 siu_uart_ports[port->line].uartclk = SIU_BAUD_BASE * 16;
851 siu_uart_ports[port->line].mapbase = port->mapbase;
852 siu_uart_ports[port->line].mapbase = port->mapbase;
853 siu_uart_ports[port->line].ops = &siu_uart_ops;
854}
855
856#define SERIAL_VR41XX_CONSOLE &siu_console
857#else
858#define SERIAL_VR41XX_CONSOLE NULL
859#endif
860
861static struct uart_driver siu_uart_driver = {
862 .owner = THIS_MODULE,
863 .driver_name = "SIU",
864 .dev_name = "ttyVR",
865 .major = SIU_MAJOR,
866 .minor = SIU_MINOR_BASE,
867 .cons = SERIAL_VR41XX_CONSOLE,
868};
869
870static int __devinit siu_probe(struct platform_device *dev)
871{
872 struct uart_port *port;
873 int num, i, retval;
874
875 num = siu_init_ports(dev);
876 if (num <= 0)
877 return -ENODEV;
878
879 siu_uart_driver.nr = num;
880 retval = uart_register_driver(&siu_uart_driver);
881 if (retval)
882 return retval;
883
884 for (i = 0; i < num; i++) {
885 port = &siu_uart_ports[i];
886 port->ops = &siu_uart_ops;
887 port->dev = &dev->dev;
888
889 retval = uart_add_one_port(&siu_uart_driver, port);
890 if (retval < 0) {
891 port->dev = NULL;
892 break;
893 }
894 }
895
896 if (i == 0 && retval < 0) {
897 uart_unregister_driver(&siu_uart_driver);
898 return retval;
899 }
900
901 return 0;
902}
903
904static int __devexit siu_remove(struct platform_device *dev)
905{
906 struct uart_port *port;
907 int i;
908
909 for (i = 0; i < siu_uart_driver.nr; i++) {
910 port = &siu_uart_ports[i];
911 if (port->dev == &dev->dev) {
912 uart_remove_one_port(&siu_uart_driver, port);
913 port->dev = NULL;
914 }
915 }
916
917 uart_unregister_driver(&siu_uart_driver);
918
919 return 0;
920}
921
922static int siu_suspend(struct platform_device *dev, pm_message_t state)
923{
924 struct uart_port *port;
925 int i;
926
927 for (i = 0; i < siu_uart_driver.nr; i++) {
928 port = &siu_uart_ports[i];
929 if ((port->type == PORT_VR41XX_SIU ||
930 port->type == PORT_VR41XX_DSIU) && port->dev == &dev->dev)
931 uart_suspend_port(&siu_uart_driver, port);
932
933 }
934
935 return 0;
936}
937
938static int siu_resume(struct platform_device *dev)
939{
940 struct uart_port *port;
941 int i;
942
943 for (i = 0; i < siu_uart_driver.nr; i++) {
944 port = &siu_uart_ports[i];
945 if ((port->type == PORT_VR41XX_SIU ||
946 port->type == PORT_VR41XX_DSIU) && port->dev == &dev->dev)
947 uart_resume_port(&siu_uart_driver, port);
948 }
949
950 return 0;
951}
952
953static struct platform_driver siu_device_driver = {
954 .probe = siu_probe,
955 .remove = __devexit_p(siu_remove),
956 .suspend = siu_suspend,
957 .resume = siu_resume,
958 .driver = {
959 .name = "SIU",
960 .owner = THIS_MODULE,
961 },
962};
963
964static int __init vr41xx_siu_init(void)
965{
966 return platform_driver_register(&siu_device_driver);
967}
968
969static void __exit vr41xx_siu_exit(void)
970{
971 platform_driver_unregister(&siu_device_driver);
972}
973
974module_init(vr41xx_siu_init);
975module_exit(vr41xx_siu_exit);
976
977MODULE_LICENSE("GPL");
978MODULE_ALIAS("platform:SIU");
diff --git a/drivers/serial/zs.c b/drivers/serial/zs.c
deleted file mode 100644
index 1a7fd3e70315..000000000000
--- a/drivers/serial/zs.c
+++ /dev/null
@@ -1,1304 +0,0 @@
1/*
2 * zs.c: Serial port driver for IOASIC DECstations.
3 *
4 * Derived from drivers/sbus/char/sunserial.c by Paul Mackerras.
5 * Derived from drivers/macintosh/macserial.c by Harald Koerfgen.
6 *
7 * DECstation changes
8 * Copyright (C) 1998-2000 Harald Koerfgen
9 * Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
10 *
11 * For the rest of the code the original Copyright applies:
12 * Copyright (C) 1996 Paul Mackerras (Paul.Mackerras@cs.anu.edu.au)
13 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
14 *
15 *
16 * Note: for IOASIC systems the wiring is as follows:
17 *
18 * mouse/keyboard:
19 * DIN-7 MJ-4 signal SCC
20 * 2 1 TxD <- A.TxD
21 * 3 4 RxD -> A.RxD
22 *
23 * EIA-232/EIA-423:
24 * DB-25 MMJ-6 signal SCC
25 * 2 2 TxD <- B.TxD
26 * 3 5 RxD -> B.RxD
27 * 4 RTS <- ~A.RTS
28 * 5 CTS -> ~B.CTS
29 * 6 6 DSR -> ~A.SYNC
30 * 8 CD -> ~B.DCD
31 * 12 DSRS(DCE) -> ~A.CTS (*)
32 * 15 TxC -> B.TxC
33 * 17 RxC -> B.RxC
34 * 20 1 DTR <- ~A.DTR
35 * 22 RI -> ~A.DCD
36 * 23 DSRS(DTE) <- ~B.RTS
37 *
38 * (*) EIA-232 defines the signal at this pin to be SCD, while DSRS(DCE)
39 * is shared with DSRS(DTE) at pin 23.
40 *
41 * As you can immediately notice the wiring of the RTS, DTR and DSR signals
42 * is a bit odd. This makes the handling of port B unnecessarily
43 * complicated and prevents the use of some automatic modes of operation.
44 */
45
46#if defined(CONFIG_SERIAL_ZS_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
47#define SUPPORT_SYSRQ
48#endif
49
50#include <linux/bug.h>
51#include <linux/console.h>
52#include <linux/delay.h>
53#include <linux/errno.h>
54#include <linux/init.h>
55#include <linux/interrupt.h>
56#include <linux/io.h>
57#include <linux/ioport.h>
58#include <linux/irqflags.h>
59#include <linux/kernel.h>
60#include <linux/major.h>
61#include <linux/serial.h>
62#include <linux/serial_core.h>
63#include <linux/spinlock.h>
64#include <linux/sysrq.h>
65#include <linux/tty.h>
66#include <linux/types.h>
67
68#include <asm/atomic.h>
69#include <asm/system.h>
70
71#include <asm/dec/interrupts.h>
72#include <asm/dec/ioasic_addrs.h>
73#include <asm/dec/system.h>
74
75#include "zs.h"
76
77
78MODULE_AUTHOR("Maciej W. Rozycki <macro@linux-mips.org>");
79MODULE_DESCRIPTION("DECstation Z85C30 serial driver");
80MODULE_LICENSE("GPL");
81
82
83static char zs_name[] __initdata = "DECstation Z85C30 serial driver version ";
84static char zs_version[] __initdata = "0.10";
85
86/*
87 * It would be nice to dynamically allocate everything that
88 * depends on ZS_NUM_SCCS, so we could support any number of
89 * Z85C30s, but for now...
90 */
91#define ZS_NUM_SCCS 2 /* Max # of ZS chips supported. */
92#define ZS_NUM_CHAN 2 /* 2 channels per chip. */
93#define ZS_CHAN_A 0 /* Index of the channel A. */
94#define ZS_CHAN_B 1 /* Index of the channel B. */
95#define ZS_CHAN_IO_SIZE 8 /* IOMEM space size. */
96#define ZS_CHAN_IO_STRIDE 4 /* Register alignment. */
97#define ZS_CHAN_IO_OFFSET 1 /* The SCC resides on the high byte
98 of the 16-bit IOBUS. */
99#define ZS_CLOCK 7372800 /* Z85C30 PCLK input clock rate. */
100
101#define to_zport(uport) container_of(uport, struct zs_port, port)
102
103struct zs_parms {
104 resource_size_t scc[ZS_NUM_SCCS];
105 int irq[ZS_NUM_SCCS];
106};
107
108static struct zs_scc zs_sccs[ZS_NUM_SCCS];
109
110static u8 zs_init_regs[ZS_NUM_REGS] __initdata = {
111 0, /* write 0 */
112 PAR_SPEC, /* write 1 */
113 0, /* write 2 */
114 0, /* write 3 */
115 X16CLK | SB1, /* write 4 */
116 0, /* write 5 */
117 0, 0, 0, /* write 6, 7, 8 */
118 MIE | DLC | NV, /* write 9 */
119 NRZ, /* write 10 */
120 TCBR | RCBR, /* write 11 */
121 0, 0, /* BRG time constant, write 12 + 13 */
122 BRSRC | BRENABL, /* write 14 */
123 0, /* write 15 */
124};
125
126/*
127 * Debugging.
128 */
129#undef ZS_DEBUG_REGS
130
131
132/*
133 * Reading and writing Z85C30 registers.
134 */
135static void recovery_delay(void)
136{
137 udelay(2);
138}
139
140static u8 read_zsreg(struct zs_port *zport, int reg)
141{
142 void __iomem *control = zport->port.membase + ZS_CHAN_IO_OFFSET;
143 u8 retval;
144
145 if (reg != 0) {
146 writeb(reg & 0xf, control);
147 fast_iob();
148 recovery_delay();
149 }
150 retval = readb(control);
151 recovery_delay();
152 return retval;
153}
154
155static void write_zsreg(struct zs_port *zport, int reg, u8 value)
156{
157 void __iomem *control = zport->port.membase + ZS_CHAN_IO_OFFSET;
158
159 if (reg != 0) {
160 writeb(reg & 0xf, control);
161 fast_iob(); recovery_delay();
162 }
163 writeb(value, control);
164 fast_iob();
165 recovery_delay();
166 return;
167}
168
169static u8 read_zsdata(struct zs_port *zport)
170{
171 void __iomem *data = zport->port.membase +
172 ZS_CHAN_IO_STRIDE + ZS_CHAN_IO_OFFSET;
173 u8 retval;
174
175 retval = readb(data);
176 recovery_delay();
177 return retval;
178}
179
180static void write_zsdata(struct zs_port *zport, u8 value)
181{
182 void __iomem *data = zport->port.membase +
183 ZS_CHAN_IO_STRIDE + ZS_CHAN_IO_OFFSET;
184
185 writeb(value, data);
186 fast_iob();
187 recovery_delay();
188 return;
189}
190
191#ifdef ZS_DEBUG_REGS
192void zs_dump(void)
193{
194 struct zs_port *zport;
195 int i, j;
196
197 for (i = 0; i < ZS_NUM_SCCS * ZS_NUM_CHAN; i++) {
198 zport = &zs_sccs[i / ZS_NUM_CHAN].zport[i % ZS_NUM_CHAN];
199
200 if (!zport->scc)
201 continue;
202
203 for (j = 0; j < 16; j++)
204 printk("W%-2d = 0x%02x\t", j, zport->regs[j]);
205 printk("\n");
206 for (j = 0; j < 16; j++)
207 printk("R%-2d = 0x%02x\t", j, read_zsreg(zport, j));
208 printk("\n\n");
209 }
210}
211#endif
212
213
214static void zs_spin_lock_cond_irq(spinlock_t *lock, int irq)
215{
216 if (irq)
217 spin_lock_irq(lock);
218 else
219 spin_lock(lock);
220}
221
222static void zs_spin_unlock_cond_irq(spinlock_t *lock, int irq)
223{
224 if (irq)
225 spin_unlock_irq(lock);
226 else
227 spin_unlock(lock);
228}
229
230static int zs_receive_drain(struct zs_port *zport)
231{
232 int loops = 10000;
233
234 while ((read_zsreg(zport, R0) & Rx_CH_AV) && --loops)
235 read_zsdata(zport);
236 return loops;
237}
238
239static int zs_transmit_drain(struct zs_port *zport, int irq)
240{
241 struct zs_scc *scc = zport->scc;
242 int loops = 10000;
243
244 while (!(read_zsreg(zport, R0) & Tx_BUF_EMP) && --loops) {
245 zs_spin_unlock_cond_irq(&scc->zlock, irq);
246 udelay(2);
247 zs_spin_lock_cond_irq(&scc->zlock, irq);
248 }
249 return loops;
250}
251
252static int zs_line_drain(struct zs_port *zport, int irq)
253{
254 struct zs_scc *scc = zport->scc;
255 int loops = 10000;
256
257 while (!(read_zsreg(zport, R1) & ALL_SNT) && --loops) {
258 zs_spin_unlock_cond_irq(&scc->zlock, irq);
259 udelay(2);
260 zs_spin_lock_cond_irq(&scc->zlock, irq);
261 }
262 return loops;
263}
264
265
266static void load_zsregs(struct zs_port *zport, u8 *regs, int irq)
267{
268 /* Let the current transmission finish. */
269 zs_line_drain(zport, irq);
270 /* Load 'em up. */
271 write_zsreg(zport, R3, regs[3] & ~RxENABLE);
272 write_zsreg(zport, R5, regs[5] & ~TxENAB);
273 write_zsreg(zport, R4, regs[4]);
274 write_zsreg(zport, R9, regs[9]);
275 write_zsreg(zport, R1, regs[1]);
276 write_zsreg(zport, R2, regs[2]);
277 write_zsreg(zport, R10, regs[10]);
278 write_zsreg(zport, R14, regs[14] & ~BRENABL);
279 write_zsreg(zport, R11, regs[11]);
280 write_zsreg(zport, R12, regs[12]);
281 write_zsreg(zport, R13, regs[13]);
282 write_zsreg(zport, R14, regs[14]);
283 write_zsreg(zport, R15, regs[15]);
284 if (regs[3] & RxENABLE)
285 write_zsreg(zport, R3, regs[3]);
286 if (regs[5] & TxENAB)
287 write_zsreg(zport, R5, regs[5]);
288 return;
289}
290
291
292/*
293 * Status handling routines.
294 */
295
296/*
297 * zs_tx_empty() -- get the transmitter empty status
298 *
299 * Purpose: Let user call ioctl() to get info when the UART physically
300 * is emptied. On bus types like RS485, the transmitter must
301 * release the bus after transmitting. This must be done when
302 * the transmit shift register is empty, not be done when the
303 * transmit holding register is empty. This functionality
304 * allows an RS485 driver to be written in user space.
305 */
306static unsigned int zs_tx_empty(struct uart_port *uport)
307{
308 struct zs_port *zport = to_zport(uport);
309 struct zs_scc *scc = zport->scc;
310 unsigned long flags;
311 u8 status;
312
313 spin_lock_irqsave(&scc->zlock, flags);
314 status = read_zsreg(zport, R1);
315 spin_unlock_irqrestore(&scc->zlock, flags);
316
317 return status & ALL_SNT ? TIOCSER_TEMT : 0;
318}
319
320static unsigned int zs_raw_get_ab_mctrl(struct zs_port *zport_a,
321 struct zs_port *zport_b)
322{
323 u8 status_a, status_b;
324 unsigned int mctrl;
325
326 status_a = read_zsreg(zport_a, R0);
327 status_b = read_zsreg(zport_b, R0);
328
329 mctrl = ((status_b & CTS) ? TIOCM_CTS : 0) |
330 ((status_b & DCD) ? TIOCM_CAR : 0) |
331 ((status_a & DCD) ? TIOCM_RNG : 0) |
332 ((status_a & SYNC_HUNT) ? TIOCM_DSR : 0);
333
334 return mctrl;
335}
336
337static unsigned int zs_raw_get_mctrl(struct zs_port *zport)
338{
339 struct zs_port *zport_a = &zport->scc->zport[ZS_CHAN_A];
340
341 return zport != zport_a ? zs_raw_get_ab_mctrl(zport_a, zport) : 0;
342}
343
344static unsigned int zs_raw_xor_mctrl(struct zs_port *zport)
345{
346 struct zs_port *zport_a = &zport->scc->zport[ZS_CHAN_A];
347 unsigned int mmask, mctrl, delta;
348 u8 mask_a, mask_b;
349
350 if (zport == zport_a)
351 return 0;
352
353 mask_a = zport_a->regs[15];
354 mask_b = zport->regs[15];
355
356 mmask = ((mask_b & CTSIE) ? TIOCM_CTS : 0) |
357 ((mask_b & DCDIE) ? TIOCM_CAR : 0) |
358 ((mask_a & DCDIE) ? TIOCM_RNG : 0) |
359 ((mask_a & SYNCIE) ? TIOCM_DSR : 0);
360
361 mctrl = zport->mctrl;
362 if (mmask) {
363 mctrl &= ~mmask;
364 mctrl |= zs_raw_get_ab_mctrl(zport_a, zport) & mmask;
365 }
366
367 delta = mctrl ^ zport->mctrl;
368 if (delta)
369 zport->mctrl = mctrl;
370
371 return delta;
372}
373
374static unsigned int zs_get_mctrl(struct uart_port *uport)
375{
376 struct zs_port *zport = to_zport(uport);
377 struct zs_scc *scc = zport->scc;
378 unsigned int mctrl;
379
380 spin_lock(&scc->zlock);
381 mctrl = zs_raw_get_mctrl(zport);
382 spin_unlock(&scc->zlock);
383
384 return mctrl;
385}
386
387static void zs_set_mctrl(struct uart_port *uport, unsigned int mctrl)
388{
389 struct zs_port *zport = to_zport(uport);
390 struct zs_scc *scc = zport->scc;
391 struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
392 u8 oldloop, newloop;
393
394 spin_lock(&scc->zlock);
395 if (zport != zport_a) {
396 if (mctrl & TIOCM_DTR)
397 zport_a->regs[5] |= DTR;
398 else
399 zport_a->regs[5] &= ~DTR;
400 if (mctrl & TIOCM_RTS)
401 zport_a->regs[5] |= RTS;
402 else
403 zport_a->regs[5] &= ~RTS;
404 write_zsreg(zport_a, R5, zport_a->regs[5]);
405 }
406
407 /* Rarely modified, so don't poke at hardware unless necessary. */
408 oldloop = zport->regs[14];
409 newloop = oldloop;
410 if (mctrl & TIOCM_LOOP)
411 newloop |= LOOPBAK;
412 else
413 newloop &= ~LOOPBAK;
414 if (newloop != oldloop) {
415 zport->regs[14] = newloop;
416 write_zsreg(zport, R14, zport->regs[14]);
417 }
418 spin_unlock(&scc->zlock);
419}
420
421static void zs_raw_stop_tx(struct zs_port *zport)
422{
423 write_zsreg(zport, R0, RES_Tx_P);
424 zport->tx_stopped = 1;
425}
426
427static void zs_stop_tx(struct uart_port *uport)
428{
429 struct zs_port *zport = to_zport(uport);
430 struct zs_scc *scc = zport->scc;
431
432 spin_lock(&scc->zlock);
433 zs_raw_stop_tx(zport);
434 spin_unlock(&scc->zlock);
435}
436
437static void zs_raw_transmit_chars(struct zs_port *);
438
439static void zs_start_tx(struct uart_port *uport)
440{
441 struct zs_port *zport = to_zport(uport);
442 struct zs_scc *scc = zport->scc;
443
444 spin_lock(&scc->zlock);
445 if (zport->tx_stopped) {
446 zs_transmit_drain(zport, 0);
447 zport->tx_stopped = 0;
448 zs_raw_transmit_chars(zport);
449 }
450 spin_unlock(&scc->zlock);
451}
452
453static void zs_stop_rx(struct uart_port *uport)
454{
455 struct zs_port *zport = to_zport(uport);
456 struct zs_scc *scc = zport->scc;
457 struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
458
459 spin_lock(&scc->zlock);
460 zport->regs[15] &= ~BRKIE;
461 zport->regs[1] &= ~(RxINT_MASK | TxINT_ENAB);
462 zport->regs[1] |= RxINT_DISAB;
463
464 if (zport != zport_a) {
465 /* A-side DCD tracks RI and SYNC tracks DSR. */
466 zport_a->regs[15] &= ~(DCDIE | SYNCIE);
467 write_zsreg(zport_a, R15, zport_a->regs[15]);
468 if (!(zport_a->regs[15] & BRKIE)) {
469 zport_a->regs[1] &= ~EXT_INT_ENAB;
470 write_zsreg(zport_a, R1, zport_a->regs[1]);
471 }
472
473 /* This-side DCD tracks DCD and CTS tracks CTS. */
474 zport->regs[15] &= ~(DCDIE | CTSIE);
475 zport->regs[1] &= ~EXT_INT_ENAB;
476 } else {
477 /* DCD tracks RI and SYNC tracks DSR for the B side. */
478 if (!(zport->regs[15] & (DCDIE | SYNCIE)))
479 zport->regs[1] &= ~EXT_INT_ENAB;
480 }
481
482 write_zsreg(zport, R15, zport->regs[15]);
483 write_zsreg(zport, R1, zport->regs[1]);
484 spin_unlock(&scc->zlock);
485}
486
487static void zs_enable_ms(struct uart_port *uport)
488{
489 struct zs_port *zport = to_zport(uport);
490 struct zs_scc *scc = zport->scc;
491 struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
492
493 if (zport == zport_a)
494 return;
495
496 spin_lock(&scc->zlock);
497
498 /* Clear Ext interrupts if not being handled already. */
499 if (!(zport_a->regs[1] & EXT_INT_ENAB))
500 write_zsreg(zport_a, R0, RES_EXT_INT);
501
502 /* A-side DCD tracks RI and SYNC tracks DSR. */
503 zport_a->regs[1] |= EXT_INT_ENAB;
504 zport_a->regs[15] |= DCDIE | SYNCIE;
505
506 /* This-side DCD tracks DCD and CTS tracks CTS. */
507 zport->regs[15] |= DCDIE | CTSIE;
508
509 zs_raw_xor_mctrl(zport);
510
511 write_zsreg(zport_a, R1, zport_a->regs[1]);
512 write_zsreg(zport_a, R15, zport_a->regs[15]);
513 write_zsreg(zport, R15, zport->regs[15]);
514 spin_unlock(&scc->zlock);
515}
516
517static void zs_break_ctl(struct uart_port *uport, int break_state)
518{
519 struct zs_port *zport = to_zport(uport);
520 struct zs_scc *scc = zport->scc;
521 unsigned long flags;
522
523 spin_lock_irqsave(&scc->zlock, flags);
524 if (break_state == -1)
525 zport->regs[5] |= SND_BRK;
526 else
527 zport->regs[5] &= ~SND_BRK;
528 write_zsreg(zport, R5, zport->regs[5]);
529 spin_unlock_irqrestore(&scc->zlock, flags);
530}
531
532
533/*
534 * Interrupt handling routines.
535 */
536#define Rx_BRK 0x0100 /* BREAK event software flag. */
537#define Rx_SYS 0x0200 /* SysRq event software flag. */
538
539static void zs_receive_chars(struct zs_port *zport)
540{
541 struct uart_port *uport = &zport->port;
542 struct zs_scc *scc = zport->scc;
543 struct uart_icount *icount;
544 unsigned int avail, status, ch, flag;
545 int count;
546
547 for (count = 16; count; count--) {
548 spin_lock(&scc->zlock);
549 avail = read_zsreg(zport, R0) & Rx_CH_AV;
550 spin_unlock(&scc->zlock);
551 if (!avail)
552 break;
553
554 spin_lock(&scc->zlock);
555 status = read_zsreg(zport, R1) & (Rx_OVR | FRM_ERR | PAR_ERR);
556 ch = read_zsdata(zport);
557 spin_unlock(&scc->zlock);
558
559 flag = TTY_NORMAL;
560
561 icount = &uport->icount;
562 icount->rx++;
563
564 /* Handle the null char got when BREAK is removed. */
565 if (!ch)
566 status |= zport->tty_break;
567 if (unlikely(status &
568 (Rx_OVR | FRM_ERR | PAR_ERR | Rx_SYS | Rx_BRK))) {
569 zport->tty_break = 0;
570
571 /* Reset the error indication. */
572 if (status & (Rx_OVR | FRM_ERR | PAR_ERR)) {
573 spin_lock(&scc->zlock);
574 write_zsreg(zport, R0, ERR_RES);
575 spin_unlock(&scc->zlock);
576 }
577
578 if (status & (Rx_SYS | Rx_BRK)) {
579 icount->brk++;
580 /* SysRq discards the null char. */
581 if (status & Rx_SYS)
582 continue;
583 } else if (status & FRM_ERR)
584 icount->frame++;
585 else if (status & PAR_ERR)
586 icount->parity++;
587 if (status & Rx_OVR)
588 icount->overrun++;
589
590 status &= uport->read_status_mask;
591 if (status & Rx_BRK)
592 flag = TTY_BREAK;
593 else if (status & FRM_ERR)
594 flag = TTY_FRAME;
595 else if (status & PAR_ERR)
596 flag = TTY_PARITY;
597 }
598
599 if (uart_handle_sysrq_char(uport, ch))
600 continue;
601
602 uart_insert_char(uport, status, Rx_OVR, ch, flag);
603 }
604
605 tty_flip_buffer_push(uport->state->port.tty);
606}
607
608static void zs_raw_transmit_chars(struct zs_port *zport)
609{
610 struct circ_buf *xmit = &zport->port.state->xmit;
611
612 /* XON/XOFF chars. */
613 if (zport->port.x_char) {
614 write_zsdata(zport, zport->port.x_char);
615 zport->port.icount.tx++;
616 zport->port.x_char = 0;
617 return;
618 }
619
620 /* If nothing to do or stopped or hardware stopped. */
621 if (uart_circ_empty(xmit) || uart_tx_stopped(&zport->port)) {
622 zs_raw_stop_tx(zport);
623 return;
624 }
625
626 /* Send char. */
627 write_zsdata(zport, xmit->buf[xmit->tail]);
628 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
629 zport->port.icount.tx++;
630
631 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
632 uart_write_wakeup(&zport->port);
633
634 /* Are we are done? */
635 if (uart_circ_empty(xmit))
636 zs_raw_stop_tx(zport);
637}
638
639static void zs_transmit_chars(struct zs_port *zport)
640{
641 struct zs_scc *scc = zport->scc;
642
643 spin_lock(&scc->zlock);
644 zs_raw_transmit_chars(zport);
645 spin_unlock(&scc->zlock);
646}
647
648static void zs_status_handle(struct zs_port *zport, struct zs_port *zport_a)
649{
650 struct uart_port *uport = &zport->port;
651 struct zs_scc *scc = zport->scc;
652 unsigned int delta;
653 u8 status, brk;
654
655 spin_lock(&scc->zlock);
656
657 /* Get status from Read Register 0. */
658 status = read_zsreg(zport, R0);
659
660 if (zport->regs[15] & BRKIE) {
661 brk = status & BRK_ABRT;
662 if (brk && !zport->brk) {
663 spin_unlock(&scc->zlock);
664 if (uart_handle_break(uport))
665 zport->tty_break = Rx_SYS;
666 else
667 zport->tty_break = Rx_BRK;
668 spin_lock(&scc->zlock);
669 }
670 zport->brk = brk;
671 }
672
673 if (zport != zport_a) {
674 delta = zs_raw_xor_mctrl(zport);
675 spin_unlock(&scc->zlock);
676
677 if (delta & TIOCM_CTS)
678 uart_handle_cts_change(uport,
679 zport->mctrl & TIOCM_CTS);
680 if (delta & TIOCM_CAR)
681 uart_handle_dcd_change(uport,
682 zport->mctrl & TIOCM_CAR);
683 if (delta & TIOCM_RNG)
684 uport->icount.dsr++;
685 if (delta & TIOCM_DSR)
686 uport->icount.rng++;
687
688 if (delta)
689 wake_up_interruptible(&uport->state->port.delta_msr_wait);
690
691 spin_lock(&scc->zlock);
692 }
693
694 /* Clear the status condition... */
695 write_zsreg(zport, R0, RES_EXT_INT);
696
697 spin_unlock(&scc->zlock);
698}
699
700/*
701 * This is the Z85C30 driver's generic interrupt routine.
702 */
703static irqreturn_t zs_interrupt(int irq, void *dev_id)
704{
705 struct zs_scc *scc = dev_id;
706 struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
707 struct zs_port *zport_b = &scc->zport[ZS_CHAN_B];
708 irqreturn_t status = IRQ_NONE;
709 u8 zs_intreg;
710 int count;
711
712 /*
713 * NOTE: The read register 3, which holds the irq status,
714 * does so for both channels on each chip. Although
715 * the status value itself must be read from the A
716 * channel and is only valid when read from channel A.
717 * Yes... broken hardware...
718 */
719 for (count = 16; count; count--) {
720 spin_lock(&scc->zlock);
721 zs_intreg = read_zsreg(zport_a, R3);
722 spin_unlock(&scc->zlock);
723 if (!zs_intreg)
724 break;
725
726 /*
727 * We do not like losing characters, so we prioritise
728 * interrupt sources a little bit differently than
729 * the SCC would, was it allowed to.
730 */
731 if (zs_intreg & CHBRxIP)
732 zs_receive_chars(zport_b);
733 if (zs_intreg & CHARxIP)
734 zs_receive_chars(zport_a);
735 if (zs_intreg & CHBEXT)
736 zs_status_handle(zport_b, zport_a);
737 if (zs_intreg & CHAEXT)
738 zs_status_handle(zport_a, zport_a);
739 if (zs_intreg & CHBTxIP)
740 zs_transmit_chars(zport_b);
741 if (zs_intreg & CHATxIP)
742 zs_transmit_chars(zport_a);
743
744 status = IRQ_HANDLED;
745 }
746
747 return status;
748}
749
750
751/*
752 * Finally, routines used to initialize the serial port.
753 */
754static int zs_startup(struct uart_port *uport)
755{
756 struct zs_port *zport = to_zport(uport);
757 struct zs_scc *scc = zport->scc;
758 unsigned long flags;
759 int irq_guard;
760 int ret;
761
762 irq_guard = atomic_add_return(1, &scc->irq_guard);
763 if (irq_guard == 1) {
764 ret = request_irq(zport->port.irq, zs_interrupt,
765 IRQF_SHARED, "scc", scc);
766 if (ret) {
767 atomic_add(-1, &scc->irq_guard);
768 printk(KERN_ERR "zs: can't get irq %d\n",
769 zport->port.irq);
770 return ret;
771 }
772 }
773
774 spin_lock_irqsave(&scc->zlock, flags);
775
776 /* Clear the receive FIFO. */
777 zs_receive_drain(zport);
778
779 /* Clear the interrupt registers. */
780 write_zsreg(zport, R0, ERR_RES);
781 write_zsreg(zport, R0, RES_Tx_P);
782 /* But Ext only if not being handled already. */
783 if (!(zport->regs[1] & EXT_INT_ENAB))
784 write_zsreg(zport, R0, RES_EXT_INT);
785
786 /* Finally, enable sequencing and interrupts. */
787 zport->regs[1] &= ~RxINT_MASK;
788 zport->regs[1] |= RxINT_ALL | TxINT_ENAB | EXT_INT_ENAB;
789 zport->regs[3] |= RxENABLE;
790 zport->regs[15] |= BRKIE;
791 write_zsreg(zport, R1, zport->regs[1]);
792 write_zsreg(zport, R3, zport->regs[3]);
793 write_zsreg(zport, R5, zport->regs[5]);
794 write_zsreg(zport, R15, zport->regs[15]);
795
796 /* Record the current state of RR0. */
797 zport->mctrl = zs_raw_get_mctrl(zport);
798 zport->brk = read_zsreg(zport, R0) & BRK_ABRT;
799
800 zport->tx_stopped = 1;
801
802 spin_unlock_irqrestore(&scc->zlock, flags);
803
804 return 0;
805}
806
807static void zs_shutdown(struct uart_port *uport)
808{
809 struct zs_port *zport = to_zport(uport);
810 struct zs_scc *scc = zport->scc;
811 unsigned long flags;
812 int irq_guard;
813
814 spin_lock_irqsave(&scc->zlock, flags);
815
816 zport->regs[3] &= ~RxENABLE;
817 write_zsreg(zport, R5, zport->regs[5]);
818 write_zsreg(zport, R3, zport->regs[3]);
819
820 spin_unlock_irqrestore(&scc->zlock, flags);
821
822 irq_guard = atomic_add_return(-1, &scc->irq_guard);
823 if (!irq_guard)
824 free_irq(zport->port.irq, scc);
825}
826
827
828static void zs_reset(struct zs_port *zport)
829{
830 struct zs_scc *scc = zport->scc;
831 int irq;
832 unsigned long flags;
833
834 spin_lock_irqsave(&scc->zlock, flags);
835 irq = !irqs_disabled_flags(flags);
836 if (!scc->initialised) {
837 /* Reset the pointer first, just in case... */
838 read_zsreg(zport, R0);
839 /* And let the current transmission finish. */
840 zs_line_drain(zport, irq);
841 write_zsreg(zport, R9, FHWRES);
842 udelay(10);
843 write_zsreg(zport, R9, 0);
844 scc->initialised = 1;
845 }
846 load_zsregs(zport, zport->regs, irq);
847 spin_unlock_irqrestore(&scc->zlock, flags);
848}
849
850static void zs_set_termios(struct uart_port *uport, struct ktermios *termios,
851 struct ktermios *old_termios)
852{
853 struct zs_port *zport = to_zport(uport);
854 struct zs_scc *scc = zport->scc;
855 struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
856 int irq;
857 unsigned int baud, brg;
858 unsigned long flags;
859
860 spin_lock_irqsave(&scc->zlock, flags);
861 irq = !irqs_disabled_flags(flags);
862
863 /* Byte size. */
864 zport->regs[3] &= ~RxNBITS_MASK;
865 zport->regs[5] &= ~TxNBITS_MASK;
866 switch (termios->c_cflag & CSIZE) {
867 case CS5:
868 zport->regs[3] |= Rx5;
869 zport->regs[5] |= Tx5;
870 break;
871 case CS6:
872 zport->regs[3] |= Rx6;
873 zport->regs[5] |= Tx6;
874 break;
875 case CS7:
876 zport->regs[3] |= Rx7;
877 zport->regs[5] |= Tx7;
878 break;
879 case CS8:
880 default:
881 zport->regs[3] |= Rx8;
882 zport->regs[5] |= Tx8;
883 break;
884 }
885
886 /* Parity and stop bits. */
887 zport->regs[4] &= ~(XCLK_MASK | SB_MASK | PAR_ENA | PAR_EVEN);
888 if (termios->c_cflag & CSTOPB)
889 zport->regs[4] |= SB2;
890 else
891 zport->regs[4] |= SB1;
892 if (termios->c_cflag & PARENB)
893 zport->regs[4] |= PAR_ENA;
894 if (!(termios->c_cflag & PARODD))
895 zport->regs[4] |= PAR_EVEN;
896 switch (zport->clk_mode) {
897 case 64:
898 zport->regs[4] |= X64CLK;
899 break;
900 case 32:
901 zport->regs[4] |= X32CLK;
902 break;
903 case 16:
904 zport->regs[4] |= X16CLK;
905 break;
906 case 1:
907 zport->regs[4] |= X1CLK;
908 break;
909 default:
910 BUG();
911 }
912
913 baud = uart_get_baud_rate(uport, termios, old_termios, 0,
914 uport->uartclk / zport->clk_mode / 4);
915
916 brg = ZS_BPS_TO_BRG(baud, uport->uartclk / zport->clk_mode);
917 zport->regs[12] = brg & 0xff;
918 zport->regs[13] = (brg >> 8) & 0xff;
919
920 uart_update_timeout(uport, termios->c_cflag, baud);
921
922 uport->read_status_mask = Rx_OVR;
923 if (termios->c_iflag & INPCK)
924 uport->read_status_mask |= FRM_ERR | PAR_ERR;
925 if (termios->c_iflag & (BRKINT | PARMRK))
926 uport->read_status_mask |= Rx_BRK;
927
928 uport->ignore_status_mask = 0;
929 if (termios->c_iflag & IGNPAR)
930 uport->ignore_status_mask |= FRM_ERR | PAR_ERR;
931 if (termios->c_iflag & IGNBRK) {
932 uport->ignore_status_mask |= Rx_BRK;
933 if (termios->c_iflag & IGNPAR)
934 uport->ignore_status_mask |= Rx_OVR;
935 }
936
937 if (termios->c_cflag & CREAD)
938 zport->regs[3] |= RxENABLE;
939 else
940 zport->regs[3] &= ~RxENABLE;
941
942 if (zport != zport_a) {
943 if (!(termios->c_cflag & CLOCAL)) {
944 zport->regs[15] |= DCDIE;
945 } else
946 zport->regs[15] &= ~DCDIE;
947 if (termios->c_cflag & CRTSCTS) {
948 zport->regs[15] |= CTSIE;
949 } else
950 zport->regs[15] &= ~CTSIE;
951 zs_raw_xor_mctrl(zport);
952 }
953
954 /* Load up the new values. */
955 load_zsregs(zport, zport->regs, irq);
956
957 spin_unlock_irqrestore(&scc->zlock, flags);
958}
959
960/*
961 * Hack alert!
962 * Required solely so that the initial PROM-based console
963 * works undisturbed in parallel with this one.
964 */
965static void zs_pm(struct uart_port *uport, unsigned int state,
966 unsigned int oldstate)
967{
968 struct zs_port *zport = to_zport(uport);
969
970 if (state < 3)
971 zport->regs[5] |= TxENAB;
972 else
973 zport->regs[5] &= ~TxENAB;
974 write_zsreg(zport, R5, zport->regs[5]);
975}
976
977
978static const char *zs_type(struct uart_port *uport)
979{
980 return "Z85C30 SCC";
981}
982
983static void zs_release_port(struct uart_port *uport)
984{
985 iounmap(uport->membase);
986 uport->membase = 0;
987 release_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE);
988}
989
990static int zs_map_port(struct uart_port *uport)
991{
992 if (!uport->membase)
993 uport->membase = ioremap_nocache(uport->mapbase,
994 ZS_CHAN_IO_SIZE);
995 if (!uport->membase) {
996 printk(KERN_ERR "zs: Cannot map MMIO\n");
997 return -ENOMEM;
998 }
999 return 0;
1000}
1001
1002static int zs_request_port(struct uart_port *uport)
1003{
1004 int ret;
1005
1006 if (!request_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE, "scc")) {
1007 printk(KERN_ERR "zs: Unable to reserve MMIO resource\n");
1008 return -EBUSY;
1009 }
1010 ret = zs_map_port(uport);
1011 if (ret) {
1012 release_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE);
1013 return ret;
1014 }
1015 return 0;
1016}
1017
1018static void zs_config_port(struct uart_port *uport, int flags)
1019{
1020 struct zs_port *zport = to_zport(uport);
1021
1022 if (flags & UART_CONFIG_TYPE) {
1023 if (zs_request_port(uport))
1024 return;
1025
1026 uport->type = PORT_ZS;
1027
1028 zs_reset(zport);
1029 }
1030}
1031
1032static int zs_verify_port(struct uart_port *uport, struct serial_struct *ser)
1033{
1034 struct zs_port *zport = to_zport(uport);
1035 int ret = 0;
1036
1037 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ZS)
1038 ret = -EINVAL;
1039 if (ser->irq != uport->irq)
1040 ret = -EINVAL;
1041 if (ser->baud_base != uport->uartclk / zport->clk_mode / 4)
1042 ret = -EINVAL;
1043 return ret;
1044}
1045
1046
1047static struct uart_ops zs_ops = {
1048 .tx_empty = zs_tx_empty,
1049 .set_mctrl = zs_set_mctrl,
1050 .get_mctrl = zs_get_mctrl,
1051 .stop_tx = zs_stop_tx,
1052 .start_tx = zs_start_tx,
1053 .stop_rx = zs_stop_rx,
1054 .enable_ms = zs_enable_ms,
1055 .break_ctl = zs_break_ctl,
1056 .startup = zs_startup,
1057 .shutdown = zs_shutdown,
1058 .set_termios = zs_set_termios,
1059 .pm = zs_pm,
1060 .type = zs_type,
1061 .release_port = zs_release_port,
1062 .request_port = zs_request_port,
1063 .config_port = zs_config_port,
1064 .verify_port = zs_verify_port,
1065};
1066
1067/*
1068 * Initialize Z85C30 port structures.
1069 */
1070static int __init zs_probe_sccs(void)
1071{
1072 static int probed;
1073 struct zs_parms zs_parms;
1074 int chip, side, irq;
1075 int n_chips = 0;
1076 int i;
1077
1078 if (probed)
1079 return 0;
1080
1081 irq = dec_interrupt[DEC_IRQ_SCC0];
1082 if (irq >= 0) {
1083 zs_parms.scc[n_chips] = IOASIC_SCC0;
1084 zs_parms.irq[n_chips] = dec_interrupt[DEC_IRQ_SCC0];
1085 n_chips++;
1086 }
1087 irq = dec_interrupt[DEC_IRQ_SCC1];
1088 if (irq >= 0) {
1089 zs_parms.scc[n_chips] = IOASIC_SCC1;
1090 zs_parms.irq[n_chips] = dec_interrupt[DEC_IRQ_SCC1];
1091 n_chips++;
1092 }
1093 if (!n_chips)
1094 return -ENXIO;
1095
1096 probed = 1;
1097
1098 for (chip = 0; chip < n_chips; chip++) {
1099 spin_lock_init(&zs_sccs[chip].zlock);
1100 for (side = 0; side < ZS_NUM_CHAN; side++) {
1101 struct zs_port *zport = &zs_sccs[chip].zport[side];
1102 struct uart_port *uport = &zport->port;
1103
1104 zport->scc = &zs_sccs[chip];
1105 zport->clk_mode = 16;
1106
1107 uport->irq = zs_parms.irq[chip];
1108 uport->uartclk = ZS_CLOCK;
1109 uport->fifosize = 1;
1110 uport->iotype = UPIO_MEM;
1111 uport->flags = UPF_BOOT_AUTOCONF;
1112 uport->ops = &zs_ops;
1113 uport->line = chip * ZS_NUM_CHAN + side;
1114 uport->mapbase = dec_kn_slot_base +
1115 zs_parms.scc[chip] +
1116 (side ^ ZS_CHAN_B) * ZS_CHAN_IO_SIZE;
1117
1118 for (i = 0; i < ZS_NUM_REGS; i++)
1119 zport->regs[i] = zs_init_regs[i];
1120 }
1121 }
1122
1123 return 0;
1124}
1125
1126
1127#ifdef CONFIG_SERIAL_ZS_CONSOLE
1128static void zs_console_putchar(struct uart_port *uport, int ch)
1129{
1130 struct zs_port *zport = to_zport(uport);
1131 struct zs_scc *scc = zport->scc;
1132 int irq;
1133 unsigned long flags;
1134
1135 spin_lock_irqsave(&scc->zlock, flags);
1136 irq = !irqs_disabled_flags(flags);
1137 if (zs_transmit_drain(zport, irq))
1138 write_zsdata(zport, ch);
1139 spin_unlock_irqrestore(&scc->zlock, flags);
1140}
1141
1142/*
1143 * Print a string to the serial port trying not to disturb
1144 * any possible real use of the port...
1145 */
1146static void zs_console_write(struct console *co, const char *s,
1147 unsigned int count)
1148{
1149 int chip = co->index / ZS_NUM_CHAN, side = co->index % ZS_NUM_CHAN;
1150 struct zs_port *zport = &zs_sccs[chip].zport[side];
1151 struct zs_scc *scc = zport->scc;
1152 unsigned long flags;
1153 u8 txint, txenb;
1154 int irq;
1155
1156 /* Disable transmit interrupts and enable the transmitter. */
1157 spin_lock_irqsave(&scc->zlock, flags);
1158 txint = zport->regs[1];
1159 txenb = zport->regs[5];
1160 if (txint & TxINT_ENAB) {
1161 zport->regs[1] = txint & ~TxINT_ENAB;
1162 write_zsreg(zport, R1, zport->regs[1]);
1163 }
1164 if (!(txenb & TxENAB)) {
1165 zport->regs[5] = txenb | TxENAB;
1166 write_zsreg(zport, R5, zport->regs[5]);
1167 }
1168 spin_unlock_irqrestore(&scc->zlock, flags);
1169
1170 uart_console_write(&zport->port, s, count, zs_console_putchar);
1171
1172 /* Restore transmit interrupts and the transmitter enable. */
1173 spin_lock_irqsave(&scc->zlock, flags);
1174 irq = !irqs_disabled_flags(flags);
1175 zs_line_drain(zport, irq);
1176 if (!(txenb & TxENAB)) {
1177 zport->regs[5] &= ~TxENAB;
1178 write_zsreg(zport, R5, zport->regs[5]);
1179 }
1180 if (txint & TxINT_ENAB) {
1181 zport->regs[1] |= TxINT_ENAB;
1182 write_zsreg(zport, R1, zport->regs[1]);
1183 }
1184 spin_unlock_irqrestore(&scc->zlock, flags);
1185}
1186
1187/*
1188 * Setup serial console baud/bits/parity. We do two things here:
1189 * - construct a cflag setting for the first uart_open()
1190 * - initialise the serial port
1191 * Return non-zero if we didn't find a serial port.
1192 */
1193static int __init zs_console_setup(struct console *co, char *options)
1194{
1195 int chip = co->index / ZS_NUM_CHAN, side = co->index % ZS_NUM_CHAN;
1196 struct zs_port *zport = &zs_sccs[chip].zport[side];
1197 struct uart_port *uport = &zport->port;
1198 int baud = 9600;
1199 int bits = 8;
1200 int parity = 'n';
1201 int flow = 'n';
1202 int ret;
1203
1204 ret = zs_map_port(uport);
1205 if (ret)
1206 return ret;
1207
1208 zs_reset(zport);
1209 zs_pm(uport, 0, -1);
1210
1211 if (options)
1212 uart_parse_options(options, &baud, &parity, &bits, &flow);
1213 return uart_set_options(uport, co, baud, parity, bits, flow);
1214}
1215
1216static struct uart_driver zs_reg;
1217static struct console zs_console = {
1218 .name = "ttyS",
1219 .write = zs_console_write,
1220 .device = uart_console_device,
1221 .setup = zs_console_setup,
1222 .flags = CON_PRINTBUFFER,
1223 .index = -1,
1224 .data = &zs_reg,
1225};
1226
1227/*
1228 * Register console.
1229 */
1230static int __init zs_serial_console_init(void)
1231{
1232 int ret;
1233
1234 ret = zs_probe_sccs();
1235 if (ret)
1236 return ret;
1237 register_console(&zs_console);
1238
1239 return 0;
1240}
1241
1242console_initcall(zs_serial_console_init);
1243
1244#define SERIAL_ZS_CONSOLE &zs_console
1245#else
1246#define SERIAL_ZS_CONSOLE NULL
1247#endif /* CONFIG_SERIAL_ZS_CONSOLE */
1248
1249static struct uart_driver zs_reg = {
1250 .owner = THIS_MODULE,
1251 .driver_name = "serial",
1252 .dev_name = "ttyS",
1253 .major = TTY_MAJOR,
1254 .minor = 64,
1255 .nr = ZS_NUM_SCCS * ZS_NUM_CHAN,
1256 .cons = SERIAL_ZS_CONSOLE,
1257};
1258
1259/* zs_init inits the driver. */
1260static int __init zs_init(void)
1261{
1262 int i, ret;
1263
1264 pr_info("%s%s\n", zs_name, zs_version);
1265
1266 /* Find out how many Z85C30 SCCs we have. */
1267 ret = zs_probe_sccs();
1268 if (ret)
1269 return ret;
1270
1271 ret = uart_register_driver(&zs_reg);
1272 if (ret)
1273 return ret;
1274
1275 for (i = 0; i < ZS_NUM_SCCS * ZS_NUM_CHAN; i++) {
1276 struct zs_scc *scc = &zs_sccs[i / ZS_NUM_CHAN];
1277 struct zs_port *zport = &scc->zport[i % ZS_NUM_CHAN];
1278 struct uart_port *uport = &zport->port;
1279
1280 if (zport->scc)
1281 uart_add_one_port(&zs_reg, uport);
1282 }
1283
1284 return 0;
1285}
1286
1287static void __exit zs_exit(void)
1288{
1289 int i;
1290
1291 for (i = ZS_NUM_SCCS * ZS_NUM_CHAN - 1; i >= 0; i--) {
1292 struct zs_scc *scc = &zs_sccs[i / ZS_NUM_CHAN];
1293 struct zs_port *zport = &scc->zport[i % ZS_NUM_CHAN];
1294 struct uart_port *uport = &zport->port;
1295
1296 if (zport->scc)
1297 uart_remove_one_port(&zs_reg, uport);
1298 }
1299
1300 uart_unregister_driver(&zs_reg);
1301}
1302
1303module_init(zs_init);
1304module_exit(zs_exit);
diff --git a/drivers/serial/zs.h b/drivers/serial/zs.h
deleted file mode 100644
index aa921b57d827..000000000000
--- a/drivers/serial/zs.h
+++ /dev/null
@@ -1,284 +0,0 @@
1/*
2 * zs.h: Definitions for the DECstation Z85C30 serial driver.
3 *
4 * Adapted from drivers/sbus/char/sunserial.h by Paul Mackerras.
5 * Adapted from drivers/macintosh/macserial.h by Harald Koerfgen.
6 *
7 * Copyright (C) 1996 Paul Mackerras (Paul.Mackerras@cs.anu.edu.au)
8 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
9 * Copyright (C) 2004, 2005, 2007 Maciej W. Rozycki
10 */
11#ifndef _SERIAL_ZS_H
12#define _SERIAL_ZS_H
13
14#ifdef __KERNEL__
15
16#define ZS_NUM_REGS 16
17
18/*
19 * This is our internal structure for each serial port's state.
20 */
21struct zs_port {
22 struct zs_scc *scc; /* Containing SCC. */
23 struct uart_port port; /* Underlying UART. */
24
25 int clk_mode; /* May be 1, 16, 32, or 64. */
26
27 unsigned int tty_break; /* Set on BREAK condition. */
28 int tx_stopped; /* Output is suspended. */
29
30 unsigned int mctrl; /* State of modem lines. */
31 u8 brk; /* BREAK state from RR0. */
32
33 u8 regs[ZS_NUM_REGS]; /* Channel write registers. */
34};
35
36/*
37 * Per-SCC state for locking and the interrupt handler.
38 */
39struct zs_scc {
40 struct zs_port zport[2];
41 spinlock_t zlock;
42 atomic_t irq_guard;
43 int initialised;
44};
45
46#endif /* __KERNEL__ */
47
48/*
49 * Conversion routines to/from brg time constants from/to bits per second.
50 */
51#define ZS_BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
52#define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
53
54/*
55 * The Zilog register set.
56 */
57
58/* Write Register 0 (Command) */
59#define R0 0 /* Register selects */
60#define R1 1
61#define R2 2
62#define R3 3
63#define R4 4
64#define R5 5
65#define R6 6
66#define R7 7
67#define R8 8
68#define R9 9
69#define R10 10
70#define R11 11
71#define R12 12
72#define R13 13
73#define R14 14
74#define R15 15
75
76#define NULLCODE 0 /* Null Code */
77#define POINT_HIGH 0x8 /* Select upper half of registers */
78#define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
79#define SEND_ABORT 0x18 /* HDLC Abort */
80#define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
81#define RES_Tx_P 0x28 /* Reset TxINT Pending */
82#define ERR_RES 0x30 /* Error Reset */
83#define RES_H_IUS 0x38 /* Reset highest IUS */
84
85#define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
86#define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
87#define RES_EOM_L 0xC0 /* Reset EOM latch */
88
89/* Write Register 1 (Tx/Rx/Ext Int Enable and WAIT/DMA Commands) */
90#define EXT_INT_ENAB 0x1 /* Ext Int Enable */
91#define TxINT_ENAB 0x2 /* Tx Int Enable */
92#define PAR_SPEC 0x4 /* Parity is special condition */
93
94#define RxINT_DISAB 0 /* Rx Int Disable */
95#define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
96#define RxINT_ALL 0x10 /* Int on all Rx Characters or error */
97#define RxINT_ERR 0x18 /* Int on error only */
98#define RxINT_MASK 0x18
99
100#define WT_RDY_RT 0x20 /* Wait/Ready on R/T */
101#define WT_FN_RDYFN 0x40 /* Wait/FN/Ready FN */
102#define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
103
104/* Write Register 2 (Interrupt Vector) */
105
106/* Write Register 3 (Receive Parameters and Control) */
107#define RxENABLE 0x1 /* Rx Enable */
108#define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
109#define ADD_SM 0x4 /* Address Search Mode (SDLC) */
110#define RxCRC_ENAB 0x8 /* Rx CRC Enable */
111#define ENT_HM 0x10 /* Enter Hunt Mode */
112#define AUTO_ENAB 0x20 /* Auto Enables */
113#define Rx5 0x0 /* Rx 5 Bits/Character */
114#define Rx7 0x40 /* Rx 7 Bits/Character */
115#define Rx6 0x80 /* Rx 6 Bits/Character */
116#define Rx8 0xc0 /* Rx 8 Bits/Character */
117#define RxNBITS_MASK 0xc0
118
119/* Write Register 4 (Transmit/Receive Miscellaneous Parameters and Modes) */
120#define PAR_ENA 0x1 /* Parity Enable */
121#define PAR_EVEN 0x2 /* Parity Even/Odd* */
122
123#define SYNC_ENAB 0 /* Sync Modes Enable */
124#define SB1 0x4 /* 1 stop bit/char */
125#define SB15 0x8 /* 1.5 stop bits/char */
126#define SB2 0xc /* 2 stop bits/char */
127#define SB_MASK 0xc
128
129#define MONSYNC 0 /* 8 Bit Sync character */
130#define BISYNC 0x10 /* 16 bit sync character */
131#define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
132#define EXTSYNC 0x30 /* External Sync Mode */
133
134#define X1CLK 0x0 /* x1 clock mode */
135#define X16CLK 0x40 /* x16 clock mode */
136#define X32CLK 0x80 /* x32 clock mode */
137#define X64CLK 0xc0 /* x64 clock mode */
138#define XCLK_MASK 0xc0
139
140/* Write Register 5 (Transmit Parameters and Controls) */
141#define TxCRC_ENAB 0x1 /* Tx CRC Enable */
142#define RTS 0x2 /* RTS */
143#define SDLC_CRC 0x4 /* SDLC/CRC-16 */
144#define TxENAB 0x8 /* Tx Enable */
145#define SND_BRK 0x10 /* Send Break */
146#define Tx5 0x0 /* Tx 5 bits (or less)/character */
147#define Tx7 0x20 /* Tx 7 bits/character */
148#define Tx6 0x40 /* Tx 6 bits/character */
149#define Tx8 0x60 /* Tx 8 bits/character */
150#define TxNBITS_MASK 0x60
151#define DTR 0x80 /* DTR */
152
153/* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
154
155/* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
156
157/* Write Register 8 (Transmit Buffer) */
158
159/* Write Register 9 (Master Interrupt Control) */
160#define VIS 1 /* Vector Includes Status */
161#define NV 2 /* No Vector */
162#define DLC 4 /* Disable Lower Chain */
163#define MIE 8 /* Master Interrupt Enable */
164#define STATHI 0x10 /* Status high */
165#define SOFTACK 0x20 /* Software Interrupt Acknowledge */
166#define NORESET 0 /* No reset on write to R9 */
167#define CHRB 0x40 /* Reset channel B */
168#define CHRA 0x80 /* Reset channel A */
169#define FHWRES 0xc0 /* Force hardware reset */
170
171/* Write Register 10 (Miscellaneous Transmitter/Receiver Control Bits) */
172#define BIT6 1 /* 6 bit/8bit sync */
173#define LOOPMODE 2 /* SDLC Loop mode */
174#define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */
175#define MARKIDLE 8 /* Mark/flag on idle */
176#define GAOP 0x10 /* Go active on poll */
177#define NRZ 0 /* NRZ mode */
178#define NRZI 0x20 /* NRZI mode */
179#define FM1 0x40 /* FM1 (transition = 1) */
180#define FM0 0x60 /* FM0 (transition = 0) */
181#define CRCPS 0x80 /* CRC Preset I/O */
182
183/* Write Register 11 (Clock Mode Control) */
184#define TRxCXT 0 /* TRxC = Xtal output */
185#define TRxCTC 1 /* TRxC = Transmit clock */
186#define TRxCBR 2 /* TRxC = BR Generator Output */
187#define TRxCDP 3 /* TRxC = DPLL output */
188#define TRxCOI 4 /* TRxC O/I */
189#define TCRTxCP 0 /* Transmit clock = RTxC pin */
190#define TCTRxCP 8 /* Transmit clock = TRxC pin */
191#define TCBR 0x10 /* Transmit clock = BR Generator output */
192#define TCDPLL 0x18 /* Transmit clock = DPLL output */
193#define RCRTxCP 0 /* Receive clock = RTxC pin */
194#define RCTRxCP 0x20 /* Receive clock = TRxC pin */
195#define RCBR 0x40 /* Receive clock = BR Generator output */
196#define RCDPLL 0x60 /* Receive clock = DPLL output */
197#define RTxCX 0x80 /* RTxC Xtal/No Xtal */
198
199/* Write Register 12 (Lower Byte of Baud Rate Generator Time Constant) */
200
201/* Write Register 13 (Upper Byte of Baud Rate Generator Time Constant) */
202
203/* Write Register 14 (Miscellaneous Control Bits) */
204#define BRENABL 1 /* Baud rate generator enable */
205#define BRSRC 2 /* Baud rate generator source */
206#define DTRREQ 4 /* DTR/Request function */
207#define AUTOECHO 8 /* Auto Echo */
208#define LOOPBAK 0x10 /* Local loopback */
209#define SEARCH 0x20 /* Enter search mode */
210#define RMC 0x40 /* Reset missing clock */
211#define DISDPLL 0x60 /* Disable DPLL */
212#define SSBR 0x80 /* Set DPLL source = BR generator */
213#define SSRTxC 0xa0 /* Set DPLL source = RTxC */
214#define SFMM 0xc0 /* Set FM mode */
215#define SNRZI 0xe0 /* Set NRZI mode */
216
217/* Write Register 15 (External/Status Interrupt Control) */
218#define WR7P_EN 1 /* WR7 Prime SDLC Feature Enable */
219#define ZCIE 2 /* Zero count IE */
220#define DCDIE 8 /* DCD IE */
221#define SYNCIE 0x10 /* Sync/hunt IE */
222#define CTSIE 0x20 /* CTS IE */
223#define TxUIE 0x40 /* Tx Underrun/EOM IE */
224#define BRKIE 0x80 /* Break/Abort IE */
225
226
227/* Read Register 0 (Transmit/Receive Buffer Status and External Status) */
228#define Rx_CH_AV 0x1 /* Rx Character Available */
229#define ZCOUNT 0x2 /* Zero count */
230#define Tx_BUF_EMP 0x4 /* Tx Buffer empty */
231#define DCD 0x8 /* DCD */
232#define SYNC_HUNT 0x10 /* Sync/hunt */
233#define CTS 0x20 /* CTS */
234#define TxEOM 0x40 /* Tx underrun */
235#define BRK_ABRT 0x80 /* Break/Abort */
236
237/* Read Register 1 (Special Receive Condition Status) */
238#define ALL_SNT 0x1 /* All sent */
239/* Residue Data for 8 Rx bits/char programmed */
240#define RES3 0x8 /* 0/3 */
241#define RES4 0x4 /* 0/4 */
242#define RES5 0xc /* 0/5 */
243#define RES6 0x2 /* 0/6 */
244#define RES7 0xa /* 0/7 */
245#define RES8 0x6 /* 0/8 */
246#define RES18 0xe /* 1/8 */
247#define RES28 0x0 /* 2/8 */
248/* Special Rx Condition Interrupts */
249#define PAR_ERR 0x10 /* Parity Error */
250#define Rx_OVR 0x20 /* Rx Overrun Error */
251#define FRM_ERR 0x40 /* CRC/Framing Error */
252#define END_FR 0x80 /* End of Frame (SDLC) */
253
254/* Read Register 2 (Interrupt Vector (WR2) -- channel A). */
255
256/* Read Register 2 (Modified Interrupt Vector -- channel B). */
257
258/* Read Register 3 (Interrupt Pending Bits -- channel A only). */
259#define CHBEXT 0x1 /* Channel B Ext/Stat IP */
260#define CHBTxIP 0x2 /* Channel B Tx IP */
261#define CHBRxIP 0x4 /* Channel B Rx IP */
262#define CHAEXT 0x8 /* Channel A Ext/Stat IP */
263#define CHATxIP 0x10 /* Channel A Tx IP */
264#define CHARxIP 0x20 /* Channel A Rx IP */
265
266/* Read Register 6 (SDLC FIFO Status and Byte Count LSB) */
267
268/* Read Register 7 (SDLC FIFO Status and Byte Count MSB) */
269
270/* Read Register 8 (Receive Data) */
271
272/* Read Register 10 (Miscellaneous Status Bits) */
273#define ONLOOP 2 /* On loop */
274#define LOOPSEND 0x10 /* Loop sending */
275#define CLK2MIS 0x40 /* Two clocks missing */
276#define CLK1MIS 0x80 /* One clock missing */
277
278/* Read Register 12 (Lower Byte of Baud Rate Generator Constant (WR12)) */
279
280/* Read Register 13 (Upper Byte of Baud Rate Generator Constant (WR13) */
281
282/* Read Register 15 (External/Status Interrupt Control (WR15)) */
283
284#endif /* _SERIAL_ZS_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-24 00:57:46 -0400