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-rw-r--r--drivers/serial/8250.c3309
1 files changed, 0 insertions, 3309 deletions
diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c
deleted file mode 100644
index 24110f6f61e0..000000000000
--- a/drivers/serial/8250.c
+++ /dev/null
@@ -1,3309 +0,0 @@
1/*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * A note about mapbase / membase
16 *
17 * mapbase is the physical address of the IO port.
18 * membase is an 'ioremapped' cookie.
19 */
20
21#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22#define SUPPORT_SYSRQ
23#endif
24
25#include <linux/module.h>
26#include <linux/moduleparam.h>
27#include <linux/ioport.h>
28#include <linux/init.h>
29#include <linux/console.h>
30#include <linux/sysrq.h>
31#include <linux/delay.h>
32#include <linux/platform_device.h>
33#include <linux/tty.h>
34#include <linux/tty_flip.h>
35#include <linux/serial_reg.h>
36#include <linux/serial_core.h>
37#include <linux/serial.h>
38#include <linux/serial_8250.h>
39#include <linux/nmi.h>
40#include <linux/mutex.h>
41#include <linux/slab.h>
42
43#include <asm/io.h>
44#include <asm/irq.h>
45
46#include "8250.h"
47
48#ifdef CONFIG_SPARC
49#include "suncore.h"
50#endif
51
52/*
53 * Configuration:
54 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
55 * is unsafe when used on edge-triggered interrupts.
56 */
57static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
58
59static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
60
61static struct uart_driver serial8250_reg;
62
63static int serial_index(struct uart_port *port)
64{
65 return (serial8250_reg.minor - 64) + port->line;
66}
67
68static unsigned int skip_txen_test; /* force skip of txen test at init time */
69
70/*
71 * Debugging.
72 */
73#if 0
74#define DEBUG_AUTOCONF(fmt...) printk(fmt)
75#else
76#define DEBUG_AUTOCONF(fmt...) do { } while (0)
77#endif
78
79#if 0
80#define DEBUG_INTR(fmt...) printk(fmt)
81#else
82#define DEBUG_INTR(fmt...) do { } while (0)
83#endif
84
85#define PASS_LIMIT 256
86
87#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
88
89
90/*
91 * We default to IRQ0 for the "no irq" hack. Some
92 * machine types want others as well - they're free
93 * to redefine this in their header file.
94 */
95#define is_real_interrupt(irq) ((irq) != 0)
96
97#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
98#define CONFIG_SERIAL_DETECT_IRQ 1
99#endif
100#ifdef CONFIG_SERIAL_8250_MANY_PORTS
101#define CONFIG_SERIAL_MANY_PORTS 1
102#endif
103
104/*
105 * HUB6 is always on. This will be removed once the header
106 * files have been cleaned.
107 */
108#define CONFIG_HUB6 1
109
110#include <asm/serial.h>
111/*
112 * SERIAL_PORT_DFNS tells us about built-in ports that have no
113 * standard enumeration mechanism. Platforms that can find all
114 * serial ports via mechanisms like ACPI or PCI need not supply it.
115 */
116#ifndef SERIAL_PORT_DFNS
117#define SERIAL_PORT_DFNS
118#endif
119
120static const struct old_serial_port old_serial_port[] = {
121 SERIAL_PORT_DFNS /* defined in asm/serial.h */
122};
123
124#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
125
126#ifdef CONFIG_SERIAL_8250_RSA
127
128#define PORT_RSA_MAX 4
129static unsigned long probe_rsa[PORT_RSA_MAX];
130static unsigned int probe_rsa_count;
131#endif /* CONFIG_SERIAL_8250_RSA */
132
133struct uart_8250_port {
134 struct uart_port port;
135 struct timer_list timer; /* "no irq" timer */
136 struct list_head list; /* ports on this IRQ */
137 unsigned short capabilities; /* port capabilities */
138 unsigned short bugs; /* port bugs */
139 unsigned int tx_loadsz; /* transmit fifo load size */
140 unsigned char acr;
141 unsigned char ier;
142 unsigned char lcr;
143 unsigned char mcr;
144 unsigned char mcr_mask; /* mask of user bits */
145 unsigned char mcr_force; /* mask of forced bits */
146 unsigned char cur_iotype; /* Running I/O type */
147
148 /*
149 * Some bits in registers are cleared on a read, so they must
150 * be saved whenever the register is read but the bits will not
151 * be immediately processed.
152 */
153#define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
154 unsigned char lsr_saved_flags;
155#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
156 unsigned char msr_saved_flags;
157
158 /*
159 * We provide a per-port pm hook.
160 */
161 void (*pm)(struct uart_port *port,
162 unsigned int state, unsigned int old);
163};
164
165struct irq_info {
166 struct hlist_node node;
167 int irq;
168 spinlock_t lock; /* Protects list not the hash */
169 struct list_head *head;
170};
171
172#define NR_IRQ_HASH 32 /* Can be adjusted later */
173static struct hlist_head irq_lists[NR_IRQ_HASH];
174static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
175
176/*
177 * Here we define the default xmit fifo size used for each type of UART.
178 */
179static const struct serial8250_config uart_config[] = {
180 [PORT_UNKNOWN] = {
181 .name = "unknown",
182 .fifo_size = 1,
183 .tx_loadsz = 1,
184 },
185 [PORT_8250] = {
186 .name = "8250",
187 .fifo_size = 1,
188 .tx_loadsz = 1,
189 },
190 [PORT_16450] = {
191 .name = "16450",
192 .fifo_size = 1,
193 .tx_loadsz = 1,
194 },
195 [PORT_16550] = {
196 .name = "16550",
197 .fifo_size = 1,
198 .tx_loadsz = 1,
199 },
200 [PORT_16550A] = {
201 .name = "16550A",
202 .fifo_size = 16,
203 .tx_loadsz = 16,
204 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
205 .flags = UART_CAP_FIFO,
206 },
207 [PORT_CIRRUS] = {
208 .name = "Cirrus",
209 .fifo_size = 1,
210 .tx_loadsz = 1,
211 },
212 [PORT_16650] = {
213 .name = "ST16650",
214 .fifo_size = 1,
215 .tx_loadsz = 1,
216 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
217 },
218 [PORT_16650V2] = {
219 .name = "ST16650V2",
220 .fifo_size = 32,
221 .tx_loadsz = 16,
222 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
223 UART_FCR_T_TRIG_00,
224 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
225 },
226 [PORT_16750] = {
227 .name = "TI16750",
228 .fifo_size = 64,
229 .tx_loadsz = 64,
230 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
231 UART_FCR7_64BYTE,
232 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
233 },
234 [PORT_STARTECH] = {
235 .name = "Startech",
236 .fifo_size = 1,
237 .tx_loadsz = 1,
238 },
239 [PORT_16C950] = {
240 .name = "16C950/954",
241 .fifo_size = 128,
242 .tx_loadsz = 128,
243 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
244 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
245 },
246 [PORT_16654] = {
247 .name = "ST16654",
248 .fifo_size = 64,
249 .tx_loadsz = 32,
250 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
251 UART_FCR_T_TRIG_10,
252 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
253 },
254 [PORT_16850] = {
255 .name = "XR16850",
256 .fifo_size = 128,
257 .tx_loadsz = 128,
258 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
259 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
260 },
261 [PORT_RSA] = {
262 .name = "RSA",
263 .fifo_size = 2048,
264 .tx_loadsz = 2048,
265 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
266 .flags = UART_CAP_FIFO,
267 },
268 [PORT_NS16550A] = {
269 .name = "NS16550A",
270 .fifo_size = 16,
271 .tx_loadsz = 16,
272 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
273 .flags = UART_CAP_FIFO | UART_NATSEMI,
274 },
275 [PORT_XSCALE] = {
276 .name = "XScale",
277 .fifo_size = 32,
278 .tx_loadsz = 32,
279 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
280 .flags = UART_CAP_FIFO | UART_CAP_UUE,
281 },
282 [PORT_RM9000] = {
283 .name = "RM9000",
284 .fifo_size = 16,
285 .tx_loadsz = 16,
286 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
287 .flags = UART_CAP_FIFO,
288 },
289 [PORT_OCTEON] = {
290 .name = "OCTEON",
291 .fifo_size = 64,
292 .tx_loadsz = 64,
293 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
294 .flags = UART_CAP_FIFO,
295 },
296 [PORT_AR7] = {
297 .name = "AR7",
298 .fifo_size = 16,
299 .tx_loadsz = 16,
300 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
301 .flags = UART_CAP_FIFO | UART_CAP_AFE,
302 },
303 [PORT_U6_16550A] = {
304 .name = "U6_16550A",
305 .fifo_size = 64,
306 .tx_loadsz = 64,
307 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
308 .flags = UART_CAP_FIFO | UART_CAP_AFE,
309 },
310};
311
312#if defined(CONFIG_MIPS_ALCHEMY)
313
314/* Au1x00 UART hardware has a weird register layout */
315static const u8 au_io_in_map[] = {
316 [UART_RX] = 0,
317 [UART_IER] = 2,
318 [UART_IIR] = 3,
319 [UART_LCR] = 5,
320 [UART_MCR] = 6,
321 [UART_LSR] = 7,
322 [UART_MSR] = 8,
323};
324
325static const u8 au_io_out_map[] = {
326 [UART_TX] = 1,
327 [UART_IER] = 2,
328 [UART_FCR] = 4,
329 [UART_LCR] = 5,
330 [UART_MCR] = 6,
331};
332
333/* sane hardware needs no mapping */
334static inline int map_8250_in_reg(struct uart_port *p, int offset)
335{
336 if (p->iotype != UPIO_AU)
337 return offset;
338 return au_io_in_map[offset];
339}
340
341static inline int map_8250_out_reg(struct uart_port *p, int offset)
342{
343 if (p->iotype != UPIO_AU)
344 return offset;
345 return au_io_out_map[offset];
346}
347
348#elif defined(CONFIG_SERIAL_8250_RM9K)
349
350static const u8
351 regmap_in[8] = {
352 [UART_RX] = 0x00,
353 [UART_IER] = 0x0c,
354 [UART_IIR] = 0x14,
355 [UART_LCR] = 0x1c,
356 [UART_MCR] = 0x20,
357 [UART_LSR] = 0x24,
358 [UART_MSR] = 0x28,
359 [UART_SCR] = 0x2c
360 },
361 regmap_out[8] = {
362 [UART_TX] = 0x04,
363 [UART_IER] = 0x0c,
364 [UART_FCR] = 0x18,
365 [UART_LCR] = 0x1c,
366 [UART_MCR] = 0x20,
367 [UART_LSR] = 0x24,
368 [UART_MSR] = 0x28,
369 [UART_SCR] = 0x2c
370 };
371
372static inline int map_8250_in_reg(struct uart_port *p, int offset)
373{
374 if (p->iotype != UPIO_RM9000)
375 return offset;
376 return regmap_in[offset];
377}
378
379static inline int map_8250_out_reg(struct uart_port *p, int offset)
380{
381 if (p->iotype != UPIO_RM9000)
382 return offset;
383 return regmap_out[offset];
384}
385
386#else
387
388/* sane hardware needs no mapping */
389#define map_8250_in_reg(up, offset) (offset)
390#define map_8250_out_reg(up, offset) (offset)
391
392#endif
393
394static unsigned int hub6_serial_in(struct uart_port *p, int offset)
395{
396 offset = map_8250_in_reg(p, offset) << p->regshift;
397 outb(p->hub6 - 1 + offset, p->iobase);
398 return inb(p->iobase + 1);
399}
400
401static void hub6_serial_out(struct uart_port *p, int offset, int value)
402{
403 offset = map_8250_out_reg(p, offset) << p->regshift;
404 outb(p->hub6 - 1 + offset, p->iobase);
405 outb(value, p->iobase + 1);
406}
407
408static unsigned int mem_serial_in(struct uart_port *p, int offset)
409{
410 offset = map_8250_in_reg(p, offset) << p->regshift;
411 return readb(p->membase + offset);
412}
413
414static void mem_serial_out(struct uart_port *p, int offset, int value)
415{
416 offset = map_8250_out_reg(p, offset) << p->regshift;
417 writeb(value, p->membase + offset);
418}
419
420static void mem32_serial_out(struct uart_port *p, int offset, int value)
421{
422 offset = map_8250_out_reg(p, offset) << p->regshift;
423 writel(value, p->membase + offset);
424}
425
426static unsigned int mem32_serial_in(struct uart_port *p, int offset)
427{
428 offset = map_8250_in_reg(p, offset) << p->regshift;
429 return readl(p->membase + offset);
430}
431
432static unsigned int au_serial_in(struct uart_port *p, int offset)
433{
434 offset = map_8250_in_reg(p, offset) << p->regshift;
435 return __raw_readl(p->membase + offset);
436}
437
438static void au_serial_out(struct uart_port *p, int offset, int value)
439{
440 offset = map_8250_out_reg(p, offset) << p->regshift;
441 __raw_writel(value, p->membase + offset);
442}
443
444static unsigned int tsi_serial_in(struct uart_port *p, int offset)
445{
446 unsigned int tmp;
447 offset = map_8250_in_reg(p, offset) << p->regshift;
448 if (offset == UART_IIR) {
449 tmp = readl(p->membase + (UART_IIR & ~3));
450 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
451 } else
452 return readb(p->membase + offset);
453}
454
455static void tsi_serial_out(struct uart_port *p, int offset, int value)
456{
457 offset = map_8250_out_reg(p, offset) << p->regshift;
458 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
459 writeb(value, p->membase + offset);
460}
461
462static void dwapb_serial_out(struct uart_port *p, int offset, int value)
463{
464 int save_offset = offset;
465 offset = map_8250_out_reg(p, offset) << p->regshift;
466 /* Save the LCR value so it can be re-written when a
467 * Busy Detect interrupt occurs. */
468 if (save_offset == UART_LCR) {
469 struct uart_8250_port *up = (struct uart_8250_port *)p;
470 up->lcr = value;
471 }
472 writeb(value, p->membase + offset);
473 /* Read the IER to ensure any interrupt is cleared before
474 * returning from ISR. */
475 if (save_offset == UART_TX || save_offset == UART_IER)
476 value = p->serial_in(p, UART_IER);
477}
478
479static unsigned int io_serial_in(struct uart_port *p, int offset)
480{
481 offset = map_8250_in_reg(p, offset) << p->regshift;
482 return inb(p->iobase + offset);
483}
484
485static void io_serial_out(struct uart_port *p, int offset, int value)
486{
487 offset = map_8250_out_reg(p, offset) << p->regshift;
488 outb(value, p->iobase + offset);
489}
490
491static void set_io_from_upio(struct uart_port *p)
492{
493 struct uart_8250_port *up = (struct uart_8250_port *)p;
494 switch (p->iotype) {
495 case UPIO_HUB6:
496 p->serial_in = hub6_serial_in;
497 p->serial_out = hub6_serial_out;
498 break;
499
500 case UPIO_MEM:
501 p->serial_in = mem_serial_in;
502 p->serial_out = mem_serial_out;
503 break;
504
505 case UPIO_RM9000:
506 case UPIO_MEM32:
507 p->serial_in = mem32_serial_in;
508 p->serial_out = mem32_serial_out;
509 break;
510
511 case UPIO_AU:
512 p->serial_in = au_serial_in;
513 p->serial_out = au_serial_out;
514 break;
515
516 case UPIO_TSI:
517 p->serial_in = tsi_serial_in;
518 p->serial_out = tsi_serial_out;
519 break;
520
521 case UPIO_DWAPB:
522 p->serial_in = mem_serial_in;
523 p->serial_out = dwapb_serial_out;
524 break;
525
526 default:
527 p->serial_in = io_serial_in;
528 p->serial_out = io_serial_out;
529 break;
530 }
531 /* Remember loaded iotype */
532 up->cur_iotype = p->iotype;
533}
534
535static void
536serial_out_sync(struct uart_8250_port *up, int offset, int value)
537{
538 struct uart_port *p = &up->port;
539 switch (p->iotype) {
540 case UPIO_MEM:
541 case UPIO_MEM32:
542 case UPIO_AU:
543 case UPIO_DWAPB:
544 p->serial_out(p, offset, value);
545 p->serial_in(p, UART_LCR); /* safe, no side-effects */
546 break;
547 default:
548 p->serial_out(p, offset, value);
549 }
550}
551
552#define serial_in(up, offset) \
553 (up->port.serial_in(&(up)->port, (offset)))
554#define serial_out(up, offset, value) \
555 (up->port.serial_out(&(up)->port, (offset), (value)))
556/*
557 * We used to support using pause I/O for certain machines. We
558 * haven't supported this for a while, but just in case it's badly
559 * needed for certain old 386 machines, I've left these #define's
560 * in....
561 */
562#define serial_inp(up, offset) serial_in(up, offset)
563#define serial_outp(up, offset, value) serial_out(up, offset, value)
564
565/* Uart divisor latch read */
566static inline int _serial_dl_read(struct uart_8250_port *up)
567{
568 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
569}
570
571/* Uart divisor latch write */
572static inline void _serial_dl_write(struct uart_8250_port *up, int value)
573{
574 serial_outp(up, UART_DLL, value & 0xff);
575 serial_outp(up, UART_DLM, value >> 8 & 0xff);
576}
577
578#if defined(CONFIG_MIPS_ALCHEMY)
579/* Au1x00 haven't got a standard divisor latch */
580static int serial_dl_read(struct uart_8250_port *up)
581{
582 if (up->port.iotype == UPIO_AU)
583 return __raw_readl(up->port.membase + 0x28);
584 else
585 return _serial_dl_read(up);
586}
587
588static void serial_dl_write(struct uart_8250_port *up, int value)
589{
590 if (up->port.iotype == UPIO_AU)
591 __raw_writel(value, up->port.membase + 0x28);
592 else
593 _serial_dl_write(up, value);
594}
595#elif defined(CONFIG_SERIAL_8250_RM9K)
596static int serial_dl_read(struct uart_8250_port *up)
597{
598 return (up->port.iotype == UPIO_RM9000) ?
599 (((__raw_readl(up->port.membase + 0x10) << 8) |
600 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
601 _serial_dl_read(up);
602}
603
604static void serial_dl_write(struct uart_8250_port *up, int value)
605{
606 if (up->port.iotype == UPIO_RM9000) {
607 __raw_writel(value, up->port.membase + 0x08);
608 __raw_writel(value >> 8, up->port.membase + 0x10);
609 } else {
610 _serial_dl_write(up, value);
611 }
612}
613#else
614#define serial_dl_read(up) _serial_dl_read(up)
615#define serial_dl_write(up, value) _serial_dl_write(up, value)
616#endif
617
618/*
619 * For the 16C950
620 */
621static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
622{
623 serial_out(up, UART_SCR, offset);
624 serial_out(up, UART_ICR, value);
625}
626
627static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
628{
629 unsigned int value;
630
631 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
632 serial_out(up, UART_SCR, offset);
633 value = serial_in(up, UART_ICR);
634 serial_icr_write(up, UART_ACR, up->acr);
635
636 return value;
637}
638
639/*
640 * FIFO support.
641 */
642static void serial8250_clear_fifos(struct uart_8250_port *p)
643{
644 if (p->capabilities & UART_CAP_FIFO) {
645 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
646 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
647 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
648 serial_outp(p, UART_FCR, 0);
649 }
650}
651
652/*
653 * IER sleep support. UARTs which have EFRs need the "extended
654 * capability" bit enabled. Note that on XR16C850s, we need to
655 * reset LCR to write to IER.
656 */
657static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
658{
659 if (p->capabilities & UART_CAP_SLEEP) {
660 if (p->capabilities & UART_CAP_EFR) {
661 serial_outp(p, UART_LCR, 0xBF);
662 serial_outp(p, UART_EFR, UART_EFR_ECB);
663 serial_outp(p, UART_LCR, 0);
664 }
665 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
666 if (p->capabilities & UART_CAP_EFR) {
667 serial_outp(p, UART_LCR, 0xBF);
668 serial_outp(p, UART_EFR, 0);
669 serial_outp(p, UART_LCR, 0);
670 }
671 }
672}
673
674#ifdef CONFIG_SERIAL_8250_RSA
675/*
676 * Attempts to turn on the RSA FIFO. Returns zero on failure.
677 * We set the port uart clock rate if we succeed.
678 */
679static int __enable_rsa(struct uart_8250_port *up)
680{
681 unsigned char mode;
682 int result;
683
684 mode = serial_inp(up, UART_RSA_MSR);
685 result = mode & UART_RSA_MSR_FIFO;
686
687 if (!result) {
688 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
689 mode = serial_inp(up, UART_RSA_MSR);
690 result = mode & UART_RSA_MSR_FIFO;
691 }
692
693 if (result)
694 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
695
696 return result;
697}
698
699static void enable_rsa(struct uart_8250_port *up)
700{
701 if (up->port.type == PORT_RSA) {
702 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
703 spin_lock_irq(&up->port.lock);
704 __enable_rsa(up);
705 spin_unlock_irq(&up->port.lock);
706 }
707 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
708 serial_outp(up, UART_RSA_FRR, 0);
709 }
710}
711
712/*
713 * Attempts to turn off the RSA FIFO. Returns zero on failure.
714 * It is unknown why interrupts were disabled in here. However,
715 * the caller is expected to preserve this behaviour by grabbing
716 * the spinlock before calling this function.
717 */
718static void disable_rsa(struct uart_8250_port *up)
719{
720 unsigned char mode;
721 int result;
722
723 if (up->port.type == PORT_RSA &&
724 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
725 spin_lock_irq(&up->port.lock);
726
727 mode = serial_inp(up, UART_RSA_MSR);
728 result = !(mode & UART_RSA_MSR_FIFO);
729
730 if (!result) {
731 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
732 mode = serial_inp(up, UART_RSA_MSR);
733 result = !(mode & UART_RSA_MSR_FIFO);
734 }
735
736 if (result)
737 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
738 spin_unlock_irq(&up->port.lock);
739 }
740}
741#endif /* CONFIG_SERIAL_8250_RSA */
742
743/*
744 * This is a quickie test to see how big the FIFO is.
745 * It doesn't work at all the time, more's the pity.
746 */
747static int size_fifo(struct uart_8250_port *up)
748{
749 unsigned char old_fcr, old_mcr, old_lcr;
750 unsigned short old_dl;
751 int count;
752
753 old_lcr = serial_inp(up, UART_LCR);
754 serial_outp(up, UART_LCR, 0);
755 old_fcr = serial_inp(up, UART_FCR);
756 old_mcr = serial_inp(up, UART_MCR);
757 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
758 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
759 serial_outp(up, UART_MCR, UART_MCR_LOOP);
760 serial_outp(up, UART_LCR, UART_LCR_DLAB);
761 old_dl = serial_dl_read(up);
762 serial_dl_write(up, 0x0001);
763 serial_outp(up, UART_LCR, 0x03);
764 for (count = 0; count < 256; count++)
765 serial_outp(up, UART_TX, count);
766 mdelay(20);/* FIXME - schedule_timeout */
767 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
768 (count < 256); count++)
769 serial_inp(up, UART_RX);
770 serial_outp(up, UART_FCR, old_fcr);
771 serial_outp(up, UART_MCR, old_mcr);
772 serial_outp(up, UART_LCR, UART_LCR_DLAB);
773 serial_dl_write(up, old_dl);
774 serial_outp(up, UART_LCR, old_lcr);
775
776 return count;
777}
778
779/*
780 * Read UART ID using the divisor method - set DLL and DLM to zero
781 * and the revision will be in DLL and device type in DLM. We
782 * preserve the device state across this.
783 */
784static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
785{
786 unsigned char old_dll, old_dlm, old_lcr;
787 unsigned int id;
788
789 old_lcr = serial_inp(p, UART_LCR);
790 serial_outp(p, UART_LCR, UART_LCR_DLAB);
791
792 old_dll = serial_inp(p, UART_DLL);
793 old_dlm = serial_inp(p, UART_DLM);
794
795 serial_outp(p, UART_DLL, 0);
796 serial_outp(p, UART_DLM, 0);
797
798 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
799
800 serial_outp(p, UART_DLL, old_dll);
801 serial_outp(p, UART_DLM, old_dlm);
802 serial_outp(p, UART_LCR, old_lcr);
803
804 return id;
805}
806
807/*
808 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
809 * When this function is called we know it is at least a StarTech
810 * 16650 V2, but it might be one of several StarTech UARTs, or one of
811 * its clones. (We treat the broken original StarTech 16650 V1 as a
812 * 16550, and why not? Startech doesn't seem to even acknowledge its
813 * existence.)
814 *
815 * What evil have men's minds wrought...
816 */
817static void autoconfig_has_efr(struct uart_8250_port *up)
818{
819 unsigned int id1, id2, id3, rev;
820
821 /*
822 * Everything with an EFR has SLEEP
823 */
824 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
825
826 /*
827 * First we check to see if it's an Oxford Semiconductor UART.
828 *
829 * If we have to do this here because some non-National
830 * Semiconductor clone chips lock up if you try writing to the
831 * LSR register (which serial_icr_read does)
832 */
833
834 /*
835 * Check for Oxford Semiconductor 16C950.
836 *
837 * EFR [4] must be set else this test fails.
838 *
839 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
840 * claims that it's needed for 952 dual UART's (which are not
841 * recommended for new designs).
842 */
843 up->acr = 0;
844 serial_out(up, UART_LCR, 0xBF);
845 serial_out(up, UART_EFR, UART_EFR_ECB);
846 serial_out(up, UART_LCR, 0x00);
847 id1 = serial_icr_read(up, UART_ID1);
848 id2 = serial_icr_read(up, UART_ID2);
849 id3 = serial_icr_read(up, UART_ID3);
850 rev = serial_icr_read(up, UART_REV);
851
852 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
853
854 if (id1 == 0x16 && id2 == 0xC9 &&
855 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
856 up->port.type = PORT_16C950;
857
858 /*
859 * Enable work around for the Oxford Semiconductor 952 rev B
860 * chip which causes it to seriously miscalculate baud rates
861 * when DLL is 0.
862 */
863 if (id3 == 0x52 && rev == 0x01)
864 up->bugs |= UART_BUG_QUOT;
865 return;
866 }
867
868 /*
869 * We check for a XR16C850 by setting DLL and DLM to 0, and then
870 * reading back DLL and DLM. The chip type depends on the DLM
871 * value read back:
872 * 0x10 - XR16C850 and the DLL contains the chip revision.
873 * 0x12 - XR16C2850.
874 * 0x14 - XR16C854.
875 */
876 id1 = autoconfig_read_divisor_id(up);
877 DEBUG_AUTOCONF("850id=%04x ", id1);
878
879 id2 = id1 >> 8;
880 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
881 up->port.type = PORT_16850;
882 return;
883 }
884
885 /*
886 * It wasn't an XR16C850.
887 *
888 * We distinguish between the '654 and the '650 by counting
889 * how many bytes are in the FIFO. I'm using this for now,
890 * since that's the technique that was sent to me in the
891 * serial driver update, but I'm not convinced this works.
892 * I've had problems doing this in the past. -TYT
893 */
894 if (size_fifo(up) == 64)
895 up->port.type = PORT_16654;
896 else
897 up->port.type = PORT_16650V2;
898}
899
900/*
901 * We detected a chip without a FIFO. Only two fall into
902 * this category - the original 8250 and the 16450. The
903 * 16450 has a scratch register (accessible with LCR=0)
904 */
905static void autoconfig_8250(struct uart_8250_port *up)
906{
907 unsigned char scratch, status1, status2;
908
909 up->port.type = PORT_8250;
910
911 scratch = serial_in(up, UART_SCR);
912 serial_outp(up, UART_SCR, 0xa5);
913 status1 = serial_in(up, UART_SCR);
914 serial_outp(up, UART_SCR, 0x5a);
915 status2 = serial_in(up, UART_SCR);
916 serial_outp(up, UART_SCR, scratch);
917
918 if (status1 == 0xa5 && status2 == 0x5a)
919 up->port.type = PORT_16450;
920}
921
922static int broken_efr(struct uart_8250_port *up)
923{
924 /*
925 * Exar ST16C2550 "A2" devices incorrectly detect as
926 * having an EFR, and report an ID of 0x0201. See
927 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
928 */
929 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
930 return 1;
931
932 return 0;
933}
934
935/*
936 * We know that the chip has FIFOs. Does it have an EFR? The
937 * EFR is located in the same register position as the IIR and
938 * we know the top two bits of the IIR are currently set. The
939 * EFR should contain zero. Try to read the EFR.
940 */
941static void autoconfig_16550a(struct uart_8250_port *up)
942{
943 unsigned char status1, status2;
944 unsigned int iersave;
945
946 up->port.type = PORT_16550A;
947 up->capabilities |= UART_CAP_FIFO;
948
949 /*
950 * Check for presence of the EFR when DLAB is set.
951 * Only ST16C650V1 UARTs pass this test.
952 */
953 serial_outp(up, UART_LCR, UART_LCR_DLAB);
954 if (serial_in(up, UART_EFR) == 0) {
955 serial_outp(up, UART_EFR, 0xA8);
956 if (serial_in(up, UART_EFR) != 0) {
957 DEBUG_AUTOCONF("EFRv1 ");
958 up->port.type = PORT_16650;
959 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
960 } else {
961 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
962 }
963 serial_outp(up, UART_EFR, 0);
964 return;
965 }
966
967 /*
968 * Maybe it requires 0xbf to be written to the LCR.
969 * (other ST16C650V2 UARTs, TI16C752A, etc)
970 */
971 serial_outp(up, UART_LCR, 0xBF);
972 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
973 DEBUG_AUTOCONF("EFRv2 ");
974 autoconfig_has_efr(up);
975 return;
976 }
977
978 /*
979 * Check for a National Semiconductor SuperIO chip.
980 * Attempt to switch to bank 2, read the value of the LOOP bit
981 * from EXCR1. Switch back to bank 0, change it in MCR. Then
982 * switch back to bank 2, read it from EXCR1 again and check
983 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
984 */
985 serial_outp(up, UART_LCR, 0);
986 status1 = serial_in(up, UART_MCR);
987 serial_outp(up, UART_LCR, 0xE0);
988 status2 = serial_in(up, 0x02); /* EXCR1 */
989
990 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
991 serial_outp(up, UART_LCR, 0);
992 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
993 serial_outp(up, UART_LCR, 0xE0);
994 status2 = serial_in(up, 0x02); /* EXCR1 */
995 serial_outp(up, UART_LCR, 0);
996 serial_outp(up, UART_MCR, status1);
997
998 if ((status2 ^ status1) & UART_MCR_LOOP) {
999 unsigned short quot;
1000
1001 serial_outp(up, UART_LCR, 0xE0);
1002
1003 quot = serial_dl_read(up);
1004 quot <<= 3;
1005
1006 status1 = serial_in(up, 0x04); /* EXCR2 */
1007 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
1008 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
1009 serial_outp(up, 0x04, status1);
1010
1011 serial_dl_write(up, quot);
1012
1013 serial_outp(up, UART_LCR, 0);
1014
1015 up->port.uartclk = 921600*16;
1016 up->port.type = PORT_NS16550A;
1017 up->capabilities |= UART_NATSEMI;
1018 return;
1019 }
1020 }
1021
1022 /*
1023 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1024 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1025 * Try setting it with and without DLAB set. Cheap clones
1026 * set bit 5 without DLAB set.
1027 */
1028 serial_outp(up, UART_LCR, 0);
1029 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1030 status1 = serial_in(up, UART_IIR) >> 5;
1031 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1032 serial_outp(up, UART_LCR, UART_LCR_DLAB);
1033 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1034 status2 = serial_in(up, UART_IIR) >> 5;
1035 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1036 serial_outp(up, UART_LCR, 0);
1037
1038 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1039
1040 if (status1 == 6 && status2 == 7) {
1041 up->port.type = PORT_16750;
1042 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1043 return;
1044 }
1045
1046 /*
1047 * Try writing and reading the UART_IER_UUE bit (b6).
1048 * If it works, this is probably one of the Xscale platform's
1049 * internal UARTs.
1050 * We're going to explicitly set the UUE bit to 0 before
1051 * trying to write and read a 1 just to make sure it's not
1052 * already a 1 and maybe locked there before we even start start.
1053 */
1054 iersave = serial_in(up, UART_IER);
1055 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1056 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1057 /*
1058 * OK it's in a known zero state, try writing and reading
1059 * without disturbing the current state of the other bits.
1060 */
1061 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1062 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1063 /*
1064 * It's an Xscale.
1065 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1066 */
1067 DEBUG_AUTOCONF("Xscale ");
1068 up->port.type = PORT_XSCALE;
1069 up->capabilities |= UART_CAP_UUE;
1070 return;
1071 }
1072 } else {
1073 /*
1074 * If we got here we couldn't force the IER_UUE bit to 0.
1075 * Log it and continue.
1076 */
1077 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1078 }
1079 serial_outp(up, UART_IER, iersave);
1080
1081 /*
1082 * We distinguish between 16550A and U6 16550A by counting
1083 * how many bytes are in the FIFO.
1084 */
1085 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1086 up->port.type = PORT_U6_16550A;
1087 up->capabilities |= UART_CAP_AFE;
1088 }
1089}
1090
1091/*
1092 * This routine is called by rs_init() to initialize a specific serial
1093 * port. It determines what type of UART chip this serial port is
1094 * using: 8250, 16450, 16550, 16550A. The important question is
1095 * whether or not this UART is a 16550A or not, since this will
1096 * determine whether or not we can use its FIFO features or not.
1097 */
1098static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1099{
1100 unsigned char status1, scratch, scratch2, scratch3;
1101 unsigned char save_lcr, save_mcr;
1102 unsigned long flags;
1103
1104 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1105 return;
1106
1107 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1108 serial_index(&up->port), up->port.iobase, up->port.membase);
1109
1110 /*
1111 * We really do need global IRQs disabled here - we're going to
1112 * be frobbing the chips IRQ enable register to see if it exists.
1113 */
1114 spin_lock_irqsave(&up->port.lock, flags);
1115
1116 up->capabilities = 0;
1117 up->bugs = 0;
1118
1119 if (!(up->port.flags & UPF_BUGGY_UART)) {
1120 /*
1121 * Do a simple existence test first; if we fail this,
1122 * there's no point trying anything else.
1123 *
1124 * 0x80 is used as a nonsense port to prevent against
1125 * false positives due to ISA bus float. The
1126 * assumption is that 0x80 is a non-existent port;
1127 * which should be safe since include/asm/io.h also
1128 * makes this assumption.
1129 *
1130 * Note: this is safe as long as MCR bit 4 is clear
1131 * and the device is in "PC" mode.
1132 */
1133 scratch = serial_inp(up, UART_IER);
1134 serial_outp(up, UART_IER, 0);
1135#ifdef __i386__
1136 outb(0xff, 0x080);
1137#endif
1138 /*
1139 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1140 * 16C754B) allow only to modify them if an EFR bit is set.
1141 */
1142 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1143 serial_outp(up, UART_IER, 0x0F);
1144#ifdef __i386__
1145 outb(0, 0x080);
1146#endif
1147 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1148 serial_outp(up, UART_IER, scratch);
1149 if (scratch2 != 0 || scratch3 != 0x0F) {
1150 /*
1151 * We failed; there's nothing here
1152 */
1153 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1154 scratch2, scratch3);
1155 goto out;
1156 }
1157 }
1158
1159 save_mcr = serial_in(up, UART_MCR);
1160 save_lcr = serial_in(up, UART_LCR);
1161
1162 /*
1163 * Check to see if a UART is really there. Certain broken
1164 * internal modems based on the Rockwell chipset fail this
1165 * test, because they apparently don't implement the loopback
1166 * test mode. So this test is skipped on the COM 1 through
1167 * COM 4 ports. This *should* be safe, since no board
1168 * manufacturer would be stupid enough to design a board
1169 * that conflicts with COM 1-4 --- we hope!
1170 */
1171 if (!(up->port.flags & UPF_SKIP_TEST)) {
1172 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1173 status1 = serial_inp(up, UART_MSR) & 0xF0;
1174 serial_outp(up, UART_MCR, save_mcr);
1175 if (status1 != 0x90) {
1176 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1177 status1);
1178 goto out;
1179 }
1180 }
1181
1182 /*
1183 * We're pretty sure there's a port here. Lets find out what
1184 * type of port it is. The IIR top two bits allows us to find
1185 * out if it's 8250 or 16450, 16550, 16550A or later. This
1186 * determines what we test for next.
1187 *
1188 * We also initialise the EFR (if any) to zero for later. The
1189 * EFR occupies the same register location as the FCR and IIR.
1190 */
1191 serial_outp(up, UART_LCR, 0xBF);
1192 serial_outp(up, UART_EFR, 0);
1193 serial_outp(up, UART_LCR, 0);
1194
1195 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1196 scratch = serial_in(up, UART_IIR) >> 6;
1197
1198 DEBUG_AUTOCONF("iir=%d ", scratch);
1199
1200 switch (scratch) {
1201 case 0:
1202 autoconfig_8250(up);
1203 break;
1204 case 1:
1205 up->port.type = PORT_UNKNOWN;
1206 break;
1207 case 2:
1208 up->port.type = PORT_16550;
1209 break;
1210 case 3:
1211 autoconfig_16550a(up);
1212 break;
1213 }
1214
1215#ifdef CONFIG_SERIAL_8250_RSA
1216 /*
1217 * Only probe for RSA ports if we got the region.
1218 */
1219 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1220 int i;
1221
1222 for (i = 0 ; i < probe_rsa_count; ++i) {
1223 if (probe_rsa[i] == up->port.iobase &&
1224 __enable_rsa(up)) {
1225 up->port.type = PORT_RSA;
1226 break;
1227 }
1228 }
1229 }
1230#endif
1231
1232 serial_outp(up, UART_LCR, save_lcr);
1233
1234 if (up->capabilities != uart_config[up->port.type].flags) {
1235 printk(KERN_WARNING
1236 "ttyS%d: detected caps %08x should be %08x\n",
1237 serial_index(&up->port), up->capabilities,
1238 uart_config[up->port.type].flags);
1239 }
1240
1241 up->port.fifosize = uart_config[up->port.type].fifo_size;
1242 up->capabilities = uart_config[up->port.type].flags;
1243 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1244
1245 if (up->port.type == PORT_UNKNOWN)
1246 goto out;
1247
1248 /*
1249 * Reset the UART.
1250 */
1251#ifdef CONFIG_SERIAL_8250_RSA
1252 if (up->port.type == PORT_RSA)
1253 serial_outp(up, UART_RSA_FRR, 0);
1254#endif
1255 serial_outp(up, UART_MCR, save_mcr);
1256 serial8250_clear_fifos(up);
1257 serial_in(up, UART_RX);
1258 if (up->capabilities & UART_CAP_UUE)
1259 serial_outp(up, UART_IER, UART_IER_UUE);
1260 else
1261 serial_outp(up, UART_IER, 0);
1262
1263 out:
1264 spin_unlock_irqrestore(&up->port.lock, flags);
1265 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1266}
1267
1268static void autoconfig_irq(struct uart_8250_port *up)
1269{
1270 unsigned char save_mcr, save_ier;
1271 unsigned char save_ICP = 0;
1272 unsigned int ICP = 0;
1273 unsigned long irqs;
1274 int irq;
1275
1276 if (up->port.flags & UPF_FOURPORT) {
1277 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1278 save_ICP = inb_p(ICP);
1279 outb_p(0x80, ICP);
1280 (void) inb_p(ICP);
1281 }
1282
1283 /* forget possible initially masked and pending IRQ */
1284 probe_irq_off(probe_irq_on());
1285 save_mcr = serial_inp(up, UART_MCR);
1286 save_ier = serial_inp(up, UART_IER);
1287 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1288
1289 irqs = probe_irq_on();
1290 serial_outp(up, UART_MCR, 0);
1291 udelay(10);
1292 if (up->port.flags & UPF_FOURPORT) {
1293 serial_outp(up, UART_MCR,
1294 UART_MCR_DTR | UART_MCR_RTS);
1295 } else {
1296 serial_outp(up, UART_MCR,
1297 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1298 }
1299 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1300 (void)serial_inp(up, UART_LSR);
1301 (void)serial_inp(up, UART_RX);
1302 (void)serial_inp(up, UART_IIR);
1303 (void)serial_inp(up, UART_MSR);
1304 serial_outp(up, UART_TX, 0xFF);
1305 udelay(20);
1306 irq = probe_irq_off(irqs);
1307
1308 serial_outp(up, UART_MCR, save_mcr);
1309 serial_outp(up, UART_IER, save_ier);
1310
1311 if (up->port.flags & UPF_FOURPORT)
1312 outb_p(save_ICP, ICP);
1313
1314 up->port.irq = (irq > 0) ? irq : 0;
1315}
1316
1317static inline void __stop_tx(struct uart_8250_port *p)
1318{
1319 if (p->ier & UART_IER_THRI) {
1320 p->ier &= ~UART_IER_THRI;
1321 serial_out(p, UART_IER, p->ier);
1322 }
1323}
1324
1325static void serial8250_stop_tx(struct uart_port *port)
1326{
1327 struct uart_8250_port *up = (struct uart_8250_port *)port;
1328
1329 __stop_tx(up);
1330
1331 /*
1332 * We really want to stop the transmitter from sending.
1333 */
1334 if (up->port.type == PORT_16C950) {
1335 up->acr |= UART_ACR_TXDIS;
1336 serial_icr_write(up, UART_ACR, up->acr);
1337 }
1338}
1339
1340static void transmit_chars(struct uart_8250_port *up);
1341
1342static void serial8250_start_tx(struct uart_port *port)
1343{
1344 struct uart_8250_port *up = (struct uart_8250_port *)port;
1345
1346 if (!(up->ier & UART_IER_THRI)) {
1347 up->ier |= UART_IER_THRI;
1348 serial_out(up, UART_IER, up->ier);
1349
1350 if (up->bugs & UART_BUG_TXEN) {
1351 unsigned char lsr;
1352 lsr = serial_in(up, UART_LSR);
1353 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1354 if ((up->port.type == PORT_RM9000) ?
1355 (lsr & UART_LSR_THRE) :
1356 (lsr & UART_LSR_TEMT))
1357 transmit_chars(up);
1358 }
1359 }
1360
1361 /*
1362 * Re-enable the transmitter if we disabled it.
1363 */
1364 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1365 up->acr &= ~UART_ACR_TXDIS;
1366 serial_icr_write(up, UART_ACR, up->acr);
1367 }
1368}
1369
1370static void serial8250_stop_rx(struct uart_port *port)
1371{
1372 struct uart_8250_port *up = (struct uart_8250_port *)port;
1373
1374 up->ier &= ~UART_IER_RLSI;
1375 up->port.read_status_mask &= ~UART_LSR_DR;
1376 serial_out(up, UART_IER, up->ier);
1377}
1378
1379static void serial8250_enable_ms(struct uart_port *port)
1380{
1381 struct uart_8250_port *up = (struct uart_8250_port *)port;
1382
1383 /* no MSR capabilities */
1384 if (up->bugs & UART_BUG_NOMSR)
1385 return;
1386
1387 up->ier |= UART_IER_MSI;
1388 serial_out(up, UART_IER, up->ier);
1389}
1390
1391static void
1392receive_chars(struct uart_8250_port *up, unsigned int *status)
1393{
1394 struct tty_struct *tty = up->port.state->port.tty;
1395 unsigned char ch, lsr = *status;
1396 int max_count = 256;
1397 char flag;
1398
1399 do {
1400 if (likely(lsr & UART_LSR_DR))
1401 ch = serial_inp(up, UART_RX);
1402 else
1403 /*
1404 * Intel 82571 has a Serial Over Lan device that will
1405 * set UART_LSR_BI without setting UART_LSR_DR when
1406 * it receives a break. To avoid reading from the
1407 * receive buffer without UART_LSR_DR bit set, we
1408 * just force the read character to be 0
1409 */
1410 ch = 0;
1411
1412 flag = TTY_NORMAL;
1413 up->port.icount.rx++;
1414
1415 lsr |= up->lsr_saved_flags;
1416 up->lsr_saved_flags = 0;
1417
1418 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1419 /*
1420 * For statistics only
1421 */
1422 if (lsr & UART_LSR_BI) {
1423 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1424 up->port.icount.brk++;
1425 /*
1426 * We do the SysRQ and SAK checking
1427 * here because otherwise the break
1428 * may get masked by ignore_status_mask
1429 * or read_status_mask.
1430 */
1431 if (uart_handle_break(&up->port))
1432 goto ignore_char;
1433 } else if (lsr & UART_LSR_PE)
1434 up->port.icount.parity++;
1435 else if (lsr & UART_LSR_FE)
1436 up->port.icount.frame++;
1437 if (lsr & UART_LSR_OE)
1438 up->port.icount.overrun++;
1439
1440 /*
1441 * Mask off conditions which should be ignored.
1442 */
1443 lsr &= up->port.read_status_mask;
1444
1445 if (lsr & UART_LSR_BI) {
1446 DEBUG_INTR("handling break....");
1447 flag = TTY_BREAK;
1448 } else if (lsr & UART_LSR_PE)
1449 flag = TTY_PARITY;
1450 else if (lsr & UART_LSR_FE)
1451 flag = TTY_FRAME;
1452 }
1453 if (uart_handle_sysrq_char(&up->port, ch))
1454 goto ignore_char;
1455
1456 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1457
1458ignore_char:
1459 lsr = serial_inp(up, UART_LSR);
1460 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1461 spin_unlock(&up->port.lock);
1462 tty_flip_buffer_push(tty);
1463 spin_lock(&up->port.lock);
1464 *status = lsr;
1465}
1466
1467static void transmit_chars(struct uart_8250_port *up)
1468{
1469 struct circ_buf *xmit = &up->port.state->xmit;
1470 int count;
1471
1472 if (up->port.x_char) {
1473 serial_outp(up, UART_TX, up->port.x_char);
1474 up->port.icount.tx++;
1475 up->port.x_char = 0;
1476 return;
1477 }
1478 if (uart_tx_stopped(&up->port)) {
1479 serial8250_stop_tx(&up->port);
1480 return;
1481 }
1482 if (uart_circ_empty(xmit)) {
1483 __stop_tx(up);
1484 return;
1485 }
1486
1487 count = up->tx_loadsz;
1488 do {
1489 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1490 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1491 up->port.icount.tx++;
1492 if (uart_circ_empty(xmit))
1493 break;
1494 } while (--count > 0);
1495
1496 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1497 uart_write_wakeup(&up->port);
1498
1499 DEBUG_INTR("THRE...");
1500
1501 if (uart_circ_empty(xmit))
1502 __stop_tx(up);
1503}
1504
1505static unsigned int check_modem_status(struct uart_8250_port *up)
1506{
1507 unsigned int status = serial_in(up, UART_MSR);
1508
1509 status |= up->msr_saved_flags;
1510 up->msr_saved_flags = 0;
1511 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1512 up->port.state != NULL) {
1513 if (status & UART_MSR_TERI)
1514 up->port.icount.rng++;
1515 if (status & UART_MSR_DDSR)
1516 up->port.icount.dsr++;
1517 if (status & UART_MSR_DDCD)
1518 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1519 if (status & UART_MSR_DCTS)
1520 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1521
1522 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
1523 }
1524
1525 return status;
1526}
1527
1528/*
1529 * This handles the interrupt from one port.
1530 */
1531static void serial8250_handle_port(struct uart_8250_port *up)
1532{
1533 unsigned int status;
1534 unsigned long flags;
1535
1536 spin_lock_irqsave(&up->port.lock, flags);
1537
1538 status = serial_inp(up, UART_LSR);
1539
1540 DEBUG_INTR("status = %x...", status);
1541
1542 if (status & (UART_LSR_DR | UART_LSR_BI))
1543 receive_chars(up, &status);
1544 check_modem_status(up);
1545 if (status & UART_LSR_THRE)
1546 transmit_chars(up);
1547
1548 spin_unlock_irqrestore(&up->port.lock, flags);
1549}
1550
1551/*
1552 * This is the serial driver's interrupt routine.
1553 *
1554 * Arjan thinks the old way was overly complex, so it got simplified.
1555 * Alan disagrees, saying that need the complexity to handle the weird
1556 * nature of ISA shared interrupts. (This is a special exception.)
1557 *
1558 * In order to handle ISA shared interrupts properly, we need to check
1559 * that all ports have been serviced, and therefore the ISA interrupt
1560 * line has been de-asserted.
1561 *
1562 * This means we need to loop through all ports. checking that they
1563 * don't have an interrupt pending.
1564 */
1565static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1566{
1567 struct irq_info *i = dev_id;
1568 struct list_head *l, *end = NULL;
1569 int pass_counter = 0, handled = 0;
1570
1571 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1572
1573 spin_lock(&i->lock);
1574
1575 l = i->head;
1576 do {
1577 struct uart_8250_port *up;
1578 unsigned int iir;
1579
1580 up = list_entry(l, struct uart_8250_port, list);
1581
1582 iir = serial_in(up, UART_IIR);
1583 if (!(iir & UART_IIR_NO_INT)) {
1584 serial8250_handle_port(up);
1585
1586 handled = 1;
1587
1588 end = NULL;
1589 } else if (up->port.iotype == UPIO_DWAPB &&
1590 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1591 /* The DesignWare APB UART has an Busy Detect (0x07)
1592 * interrupt meaning an LCR write attempt occured while the
1593 * UART was busy. The interrupt must be cleared by reading
1594 * the UART status register (USR) and the LCR re-written. */
1595 unsigned int status;
1596 status = *(volatile u32 *)up->port.private_data;
1597 serial_out(up, UART_LCR, up->lcr);
1598
1599 handled = 1;
1600
1601 end = NULL;
1602 } else if (end == NULL)
1603 end = l;
1604
1605 l = l->next;
1606
1607 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1608 /* If we hit this, we're dead. */
1609 printk(KERN_ERR "serial8250: too much work for "
1610 "irq%d\n", irq);
1611 break;
1612 }
1613 } while (l != end);
1614
1615 spin_unlock(&i->lock);
1616
1617 DEBUG_INTR("end.\n");
1618
1619 return IRQ_RETVAL(handled);
1620}
1621
1622/*
1623 * To support ISA shared interrupts, we need to have one interrupt
1624 * handler that ensures that the IRQ line has been deasserted
1625 * before returning. Failing to do this will result in the IRQ
1626 * line being stuck active, and, since ISA irqs are edge triggered,
1627 * no more IRQs will be seen.
1628 */
1629static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1630{
1631 spin_lock_irq(&i->lock);
1632
1633 if (!list_empty(i->head)) {
1634 if (i->head == &up->list)
1635 i->head = i->head->next;
1636 list_del(&up->list);
1637 } else {
1638 BUG_ON(i->head != &up->list);
1639 i->head = NULL;
1640 }
1641 spin_unlock_irq(&i->lock);
1642 /* List empty so throw away the hash node */
1643 if (i->head == NULL) {
1644 hlist_del(&i->node);
1645 kfree(i);
1646 }
1647}
1648
1649static int serial_link_irq_chain(struct uart_8250_port *up)
1650{
1651 struct hlist_head *h;
1652 struct hlist_node *n;
1653 struct irq_info *i;
1654 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1655
1656 mutex_lock(&hash_mutex);
1657
1658 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1659
1660 hlist_for_each(n, h) {
1661 i = hlist_entry(n, struct irq_info, node);
1662 if (i->irq == up->port.irq)
1663 break;
1664 }
1665
1666 if (n == NULL) {
1667 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1668 if (i == NULL) {
1669 mutex_unlock(&hash_mutex);
1670 return -ENOMEM;
1671 }
1672 spin_lock_init(&i->lock);
1673 i->irq = up->port.irq;
1674 hlist_add_head(&i->node, h);
1675 }
1676 mutex_unlock(&hash_mutex);
1677
1678 spin_lock_irq(&i->lock);
1679
1680 if (i->head) {
1681 list_add(&up->list, i->head);
1682 spin_unlock_irq(&i->lock);
1683
1684 ret = 0;
1685 } else {
1686 INIT_LIST_HEAD(&up->list);
1687 i->head = &up->list;
1688 spin_unlock_irq(&i->lock);
1689 irq_flags |= up->port.irqflags;
1690 ret = request_irq(up->port.irq, serial8250_interrupt,
1691 irq_flags, "serial", i);
1692 if (ret < 0)
1693 serial_do_unlink(i, up);
1694 }
1695
1696 return ret;
1697}
1698
1699static void serial_unlink_irq_chain(struct uart_8250_port *up)
1700{
1701 struct irq_info *i;
1702 struct hlist_node *n;
1703 struct hlist_head *h;
1704
1705 mutex_lock(&hash_mutex);
1706
1707 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1708
1709 hlist_for_each(n, h) {
1710 i = hlist_entry(n, struct irq_info, node);
1711 if (i->irq == up->port.irq)
1712 break;
1713 }
1714
1715 BUG_ON(n == NULL);
1716 BUG_ON(i->head == NULL);
1717
1718 if (list_empty(i->head))
1719 free_irq(up->port.irq, i);
1720
1721 serial_do_unlink(i, up);
1722 mutex_unlock(&hash_mutex);
1723}
1724
1725/* Base timer interval for polling */
1726static inline int poll_timeout(int timeout)
1727{
1728 return timeout > 6 ? (timeout / 2 - 2) : 1;
1729}
1730
1731/*
1732 * This function is used to handle ports that do not have an
1733 * interrupt. This doesn't work very well for 16450's, but gives
1734 * barely passable results for a 16550A. (Although at the expense
1735 * of much CPU overhead).
1736 */
1737static void serial8250_timeout(unsigned long data)
1738{
1739 struct uart_8250_port *up = (struct uart_8250_port *)data;
1740 unsigned int iir;
1741
1742 iir = serial_in(up, UART_IIR);
1743 if (!(iir & UART_IIR_NO_INT))
1744 serial8250_handle_port(up);
1745 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1746}
1747
1748static void serial8250_backup_timeout(unsigned long data)
1749{
1750 struct uart_8250_port *up = (struct uart_8250_port *)data;
1751 unsigned int iir, ier = 0, lsr;
1752 unsigned long flags;
1753
1754 /*
1755 * Must disable interrupts or else we risk racing with the interrupt
1756 * based handler.
1757 */
1758 if (is_real_interrupt(up->port.irq)) {
1759 ier = serial_in(up, UART_IER);
1760 serial_out(up, UART_IER, 0);
1761 }
1762
1763 iir = serial_in(up, UART_IIR);
1764
1765 /*
1766 * This should be a safe test for anyone who doesn't trust the
1767 * IIR bits on their UART, but it's specifically designed for
1768 * the "Diva" UART used on the management processor on many HP
1769 * ia64 and parisc boxes.
1770 */
1771 spin_lock_irqsave(&up->port.lock, flags);
1772 lsr = serial_in(up, UART_LSR);
1773 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1774 spin_unlock_irqrestore(&up->port.lock, flags);
1775 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1776 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1777 (lsr & UART_LSR_THRE)) {
1778 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1779 iir |= UART_IIR_THRI;
1780 }
1781
1782 if (!(iir & UART_IIR_NO_INT))
1783 serial8250_handle_port(up);
1784
1785 if (is_real_interrupt(up->port.irq))
1786 serial_out(up, UART_IER, ier);
1787
1788 /* Standard timer interval plus 0.2s to keep the port running */
1789 mod_timer(&up->timer,
1790 jiffies + poll_timeout(up->port.timeout) + HZ / 5);
1791}
1792
1793static unsigned int serial8250_tx_empty(struct uart_port *port)
1794{
1795 struct uart_8250_port *up = (struct uart_8250_port *)port;
1796 unsigned long flags;
1797 unsigned int lsr;
1798
1799 spin_lock_irqsave(&up->port.lock, flags);
1800 lsr = serial_in(up, UART_LSR);
1801 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1802 spin_unlock_irqrestore(&up->port.lock, flags);
1803
1804 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1805}
1806
1807static unsigned int serial8250_get_mctrl(struct uart_port *port)
1808{
1809 struct uart_8250_port *up = (struct uart_8250_port *)port;
1810 unsigned int status;
1811 unsigned int ret;
1812
1813 status = check_modem_status(up);
1814
1815 ret = 0;
1816 if (status & UART_MSR_DCD)
1817 ret |= TIOCM_CAR;
1818 if (status & UART_MSR_RI)
1819 ret |= TIOCM_RNG;
1820 if (status & UART_MSR_DSR)
1821 ret |= TIOCM_DSR;
1822 if (status & UART_MSR_CTS)
1823 ret |= TIOCM_CTS;
1824 return ret;
1825}
1826
1827static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1828{
1829 struct uart_8250_port *up = (struct uart_8250_port *)port;
1830 unsigned char mcr = 0;
1831
1832 if (mctrl & TIOCM_RTS)
1833 mcr |= UART_MCR_RTS;
1834 if (mctrl & TIOCM_DTR)
1835 mcr |= UART_MCR_DTR;
1836 if (mctrl & TIOCM_OUT1)
1837 mcr |= UART_MCR_OUT1;
1838 if (mctrl & TIOCM_OUT2)
1839 mcr |= UART_MCR_OUT2;
1840 if (mctrl & TIOCM_LOOP)
1841 mcr |= UART_MCR_LOOP;
1842
1843 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1844
1845 serial_out(up, UART_MCR, mcr);
1846}
1847
1848static void serial8250_break_ctl(struct uart_port *port, int break_state)
1849{
1850 struct uart_8250_port *up = (struct uart_8250_port *)port;
1851 unsigned long flags;
1852
1853 spin_lock_irqsave(&up->port.lock, flags);
1854 if (break_state == -1)
1855 up->lcr |= UART_LCR_SBC;
1856 else
1857 up->lcr &= ~UART_LCR_SBC;
1858 serial_out(up, UART_LCR, up->lcr);
1859 spin_unlock_irqrestore(&up->port.lock, flags);
1860}
1861
1862/*
1863 * Wait for transmitter & holding register to empty
1864 */
1865static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1866{
1867 unsigned int status, tmout = 10000;
1868
1869 /* Wait up to 10ms for the character(s) to be sent. */
1870 do {
1871 status = serial_in(up, UART_LSR);
1872
1873 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1874
1875 if (--tmout == 0)
1876 break;
1877 udelay(1);
1878 } while ((status & bits) != bits);
1879
1880 /* Wait up to 1s for flow control if necessary */
1881 if (up->port.flags & UPF_CONS_FLOW) {
1882 unsigned int tmout;
1883 for (tmout = 1000000; tmout; tmout--) {
1884 unsigned int msr = serial_in(up, UART_MSR);
1885 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1886 if (msr & UART_MSR_CTS)
1887 break;
1888 udelay(1);
1889 touch_nmi_watchdog();
1890 }
1891 }
1892}
1893
1894#ifdef CONFIG_CONSOLE_POLL
1895/*
1896 * Console polling routines for writing and reading from the uart while
1897 * in an interrupt or debug context.
1898 */
1899
1900static int serial8250_get_poll_char(struct uart_port *port)
1901{
1902 struct uart_8250_port *up = (struct uart_8250_port *)port;
1903 unsigned char lsr = serial_inp(up, UART_LSR);
1904
1905 if (!(lsr & UART_LSR_DR))
1906 return NO_POLL_CHAR;
1907
1908 return serial_inp(up, UART_RX);
1909}
1910
1911
1912static void serial8250_put_poll_char(struct uart_port *port,
1913 unsigned char c)
1914{
1915 unsigned int ier;
1916 struct uart_8250_port *up = (struct uart_8250_port *)port;
1917
1918 /*
1919 * First save the IER then disable the interrupts
1920 */
1921 ier = serial_in(up, UART_IER);
1922 if (up->capabilities & UART_CAP_UUE)
1923 serial_out(up, UART_IER, UART_IER_UUE);
1924 else
1925 serial_out(up, UART_IER, 0);
1926
1927 wait_for_xmitr(up, BOTH_EMPTY);
1928 /*
1929 * Send the character out.
1930 * If a LF, also do CR...
1931 */
1932 serial_out(up, UART_TX, c);
1933 if (c == 10) {
1934 wait_for_xmitr(up, BOTH_EMPTY);
1935 serial_out(up, UART_TX, 13);
1936 }
1937
1938 /*
1939 * Finally, wait for transmitter to become empty
1940 * and restore the IER
1941 */
1942 wait_for_xmitr(up, BOTH_EMPTY);
1943 serial_out(up, UART_IER, ier);
1944}
1945
1946#endif /* CONFIG_CONSOLE_POLL */
1947
1948static int serial8250_startup(struct uart_port *port)
1949{
1950 struct uart_8250_port *up = (struct uart_8250_port *)port;
1951 unsigned long flags;
1952 unsigned char lsr, iir;
1953 int retval;
1954
1955 up->capabilities = uart_config[up->port.type].flags;
1956 up->mcr = 0;
1957
1958 if (up->port.iotype != up->cur_iotype)
1959 set_io_from_upio(port);
1960
1961 if (up->port.type == PORT_16C950) {
1962 /* Wake up and initialize UART */
1963 up->acr = 0;
1964 serial_outp(up, UART_LCR, 0xBF);
1965 serial_outp(up, UART_EFR, UART_EFR_ECB);
1966 serial_outp(up, UART_IER, 0);
1967 serial_outp(up, UART_LCR, 0);
1968 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1969 serial_outp(up, UART_LCR, 0xBF);
1970 serial_outp(up, UART_EFR, UART_EFR_ECB);
1971 serial_outp(up, UART_LCR, 0);
1972 }
1973
1974#ifdef CONFIG_SERIAL_8250_RSA
1975 /*
1976 * If this is an RSA port, see if we can kick it up to the
1977 * higher speed clock.
1978 */
1979 enable_rsa(up);
1980#endif
1981
1982 /*
1983 * Clear the FIFO buffers and disable them.
1984 * (they will be reenabled in set_termios())
1985 */
1986 serial8250_clear_fifos(up);
1987
1988 /*
1989 * Clear the interrupt registers.
1990 */
1991 (void) serial_inp(up, UART_LSR);
1992 (void) serial_inp(up, UART_RX);
1993 (void) serial_inp(up, UART_IIR);
1994 (void) serial_inp(up, UART_MSR);
1995
1996 /*
1997 * At this point, there's no way the LSR could still be 0xff;
1998 * if it is, then bail out, because there's likely no UART
1999 * here.
2000 */
2001 if (!(up->port.flags & UPF_BUGGY_UART) &&
2002 (serial_inp(up, UART_LSR) == 0xff)) {
2003 printk(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2004 serial_index(&up->port));
2005 return -ENODEV;
2006 }
2007
2008 /*
2009 * For a XR16C850, we need to set the trigger levels
2010 */
2011 if (up->port.type == PORT_16850) {
2012 unsigned char fctr;
2013
2014 serial_outp(up, UART_LCR, 0xbf);
2015
2016 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2017 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2018 serial_outp(up, UART_TRG, UART_TRG_96);
2019 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2020 serial_outp(up, UART_TRG, UART_TRG_96);
2021
2022 serial_outp(up, UART_LCR, 0);
2023 }
2024
2025 if (is_real_interrupt(up->port.irq)) {
2026 unsigned char iir1;
2027 /*
2028 * Test for UARTs that do not reassert THRE when the
2029 * transmitter is idle and the interrupt has already
2030 * been cleared. Real 16550s should always reassert
2031 * this interrupt whenever the transmitter is idle and
2032 * the interrupt is enabled. Delays are necessary to
2033 * allow register changes to become visible.
2034 */
2035 spin_lock_irqsave(&up->port.lock, flags);
2036 if (up->port.irqflags & IRQF_SHARED)
2037 disable_irq_nosync(up->port.irq);
2038
2039 wait_for_xmitr(up, UART_LSR_THRE);
2040 serial_out_sync(up, UART_IER, UART_IER_THRI);
2041 udelay(1); /* allow THRE to set */
2042 iir1 = serial_in(up, UART_IIR);
2043 serial_out(up, UART_IER, 0);
2044 serial_out_sync(up, UART_IER, UART_IER_THRI);
2045 udelay(1); /* allow a working UART time to re-assert THRE */
2046 iir = serial_in(up, UART_IIR);
2047 serial_out(up, UART_IER, 0);
2048
2049 if (up->port.irqflags & IRQF_SHARED)
2050 enable_irq(up->port.irq);
2051 spin_unlock_irqrestore(&up->port.lock, flags);
2052
2053 /*
2054 * If the interrupt is not reasserted, setup a timer to
2055 * kick the UART on a regular basis.
2056 */
2057 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
2058 up->bugs |= UART_BUG_THRE;
2059 pr_debug("ttyS%d - using backup timer\n",
2060 serial_index(port));
2061 }
2062 }
2063
2064 /*
2065 * The above check will only give an accurate result the first time
2066 * the port is opened so this value needs to be preserved.
2067 */
2068 if (up->bugs & UART_BUG_THRE) {
2069 up->timer.function = serial8250_backup_timeout;
2070 up->timer.data = (unsigned long)up;
2071 mod_timer(&up->timer, jiffies +
2072 poll_timeout(up->port.timeout) + HZ / 5);
2073 }
2074
2075 /*
2076 * If the "interrupt" for this port doesn't correspond with any
2077 * hardware interrupt, we use a timer-based system. The original
2078 * driver used to do this with IRQ0.
2079 */
2080 if (!is_real_interrupt(up->port.irq)) {
2081 up->timer.data = (unsigned long)up;
2082 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
2083 } else {
2084 retval = serial_link_irq_chain(up);
2085 if (retval)
2086 return retval;
2087 }
2088
2089 /*
2090 * Now, initialize the UART
2091 */
2092 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2093
2094 spin_lock_irqsave(&up->port.lock, flags);
2095 if (up->port.flags & UPF_FOURPORT) {
2096 if (!is_real_interrupt(up->port.irq))
2097 up->port.mctrl |= TIOCM_OUT1;
2098 } else
2099 /*
2100 * Most PC uarts need OUT2 raised to enable interrupts.
2101 */
2102 if (is_real_interrupt(up->port.irq))
2103 up->port.mctrl |= TIOCM_OUT2;
2104
2105 serial8250_set_mctrl(&up->port, up->port.mctrl);
2106
2107 /* Serial over Lan (SoL) hack:
2108 Intel 8257x Gigabit ethernet chips have a
2109 16550 emulation, to be used for Serial Over Lan.
2110 Those chips take a longer time than a normal
2111 serial device to signalize that a transmission
2112 data was queued. Due to that, the above test generally
2113 fails. One solution would be to delay the reading of
2114 iir. However, this is not reliable, since the timeout
2115 is variable. So, let's just don't test if we receive
2116 TX irq. This way, we'll never enable UART_BUG_TXEN.
2117 */
2118 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2119 goto dont_test_tx_en;
2120
2121 /*
2122 * Do a quick test to see if we receive an
2123 * interrupt when we enable the TX irq.
2124 */
2125 serial_outp(up, UART_IER, UART_IER_THRI);
2126 lsr = serial_in(up, UART_LSR);
2127 iir = serial_in(up, UART_IIR);
2128 serial_outp(up, UART_IER, 0);
2129
2130 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2131 if (!(up->bugs & UART_BUG_TXEN)) {
2132 up->bugs |= UART_BUG_TXEN;
2133 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2134 serial_index(port));
2135 }
2136 } else {
2137 up->bugs &= ~UART_BUG_TXEN;
2138 }
2139
2140dont_test_tx_en:
2141 spin_unlock_irqrestore(&up->port.lock, flags);
2142
2143 /*
2144 * Clear the interrupt registers again for luck, and clear the
2145 * saved flags to avoid getting false values from polling
2146 * routines or the previous session.
2147 */
2148 serial_inp(up, UART_LSR);
2149 serial_inp(up, UART_RX);
2150 serial_inp(up, UART_IIR);
2151 serial_inp(up, UART_MSR);
2152 up->lsr_saved_flags = 0;
2153 up->msr_saved_flags = 0;
2154
2155 /*
2156 * Finally, enable interrupts. Note: Modem status interrupts
2157 * are set via set_termios(), which will be occurring imminently
2158 * anyway, so we don't enable them here.
2159 */
2160 up->ier = UART_IER_RLSI | UART_IER_RDI;
2161 serial_outp(up, UART_IER, up->ier);
2162
2163 if (up->port.flags & UPF_FOURPORT) {
2164 unsigned int icp;
2165 /*
2166 * Enable interrupts on the AST Fourport board
2167 */
2168 icp = (up->port.iobase & 0xfe0) | 0x01f;
2169 outb_p(0x80, icp);
2170 (void) inb_p(icp);
2171 }
2172
2173 return 0;
2174}
2175
2176static void serial8250_shutdown(struct uart_port *port)
2177{
2178 struct uart_8250_port *up = (struct uart_8250_port *)port;
2179 unsigned long flags;
2180
2181 /*
2182 * Disable interrupts from this port
2183 */
2184 up->ier = 0;
2185 serial_outp(up, UART_IER, 0);
2186
2187 spin_lock_irqsave(&up->port.lock, flags);
2188 if (up->port.flags & UPF_FOURPORT) {
2189 /* reset interrupts on the AST Fourport board */
2190 inb((up->port.iobase & 0xfe0) | 0x1f);
2191 up->port.mctrl |= TIOCM_OUT1;
2192 } else
2193 up->port.mctrl &= ~TIOCM_OUT2;
2194
2195 serial8250_set_mctrl(&up->port, up->port.mctrl);
2196 spin_unlock_irqrestore(&up->port.lock, flags);
2197
2198 /*
2199 * Disable break condition and FIFOs
2200 */
2201 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2202 serial8250_clear_fifos(up);
2203
2204#ifdef CONFIG_SERIAL_8250_RSA
2205 /*
2206 * Reset the RSA board back to 115kbps compat mode.
2207 */
2208 disable_rsa(up);
2209#endif
2210
2211 /*
2212 * Read data port to reset things, and then unlink from
2213 * the IRQ chain.
2214 */
2215 (void) serial_in(up, UART_RX);
2216
2217 del_timer_sync(&up->timer);
2218 up->timer.function = serial8250_timeout;
2219 if (is_real_interrupt(up->port.irq))
2220 serial_unlink_irq_chain(up);
2221}
2222
2223static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2224{
2225 unsigned int quot;
2226
2227 /*
2228 * Handle magic divisors for baud rates above baud_base on
2229 * SMSC SuperIO chips.
2230 */
2231 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2232 baud == (port->uartclk/4))
2233 quot = 0x8001;
2234 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2235 baud == (port->uartclk/8))
2236 quot = 0x8002;
2237 else
2238 quot = uart_get_divisor(port, baud);
2239
2240 return quot;
2241}
2242
2243void
2244serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2245 struct ktermios *old)
2246{
2247 struct uart_8250_port *up = (struct uart_8250_port *)port;
2248 unsigned char cval, fcr = 0;
2249 unsigned long flags;
2250 unsigned int baud, quot;
2251
2252 switch (termios->c_cflag & CSIZE) {
2253 case CS5:
2254 cval = UART_LCR_WLEN5;
2255 break;
2256 case CS6:
2257 cval = UART_LCR_WLEN6;
2258 break;
2259 case CS7:
2260 cval = UART_LCR_WLEN7;
2261 break;
2262 default:
2263 case CS8:
2264 cval = UART_LCR_WLEN8;
2265 break;
2266 }
2267
2268 if (termios->c_cflag & CSTOPB)
2269 cval |= UART_LCR_STOP;
2270 if (termios->c_cflag & PARENB)
2271 cval |= UART_LCR_PARITY;
2272 if (!(termios->c_cflag & PARODD))
2273 cval |= UART_LCR_EPAR;
2274#ifdef CMSPAR
2275 if (termios->c_cflag & CMSPAR)
2276 cval |= UART_LCR_SPAR;
2277#endif
2278
2279 /*
2280 * Ask the core to calculate the divisor for us.
2281 */
2282 baud = uart_get_baud_rate(port, termios, old,
2283 port->uartclk / 16 / 0xffff,
2284 port->uartclk / 16);
2285 quot = serial8250_get_divisor(port, baud);
2286
2287 /*
2288 * Oxford Semi 952 rev B workaround
2289 */
2290 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2291 quot++;
2292
2293 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2294 if (baud < 2400)
2295 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2296 else
2297 fcr = uart_config[up->port.type].fcr;
2298 }
2299
2300 /*
2301 * MCR-based auto flow control. When AFE is enabled, RTS will be
2302 * deasserted when the receive FIFO contains more characters than
2303 * the trigger, or the MCR RTS bit is cleared. In the case where
2304 * the remote UART is not using CTS auto flow control, we must
2305 * have sufficient FIFO entries for the latency of the remote
2306 * UART to respond. IOW, at least 32 bytes of FIFO.
2307 */
2308 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2309 up->mcr &= ~UART_MCR_AFE;
2310 if (termios->c_cflag & CRTSCTS)
2311 up->mcr |= UART_MCR_AFE;
2312 }
2313
2314 /*
2315 * Ok, we're now changing the port state. Do it with
2316 * interrupts disabled.
2317 */
2318 spin_lock_irqsave(&up->port.lock, flags);
2319
2320 /*
2321 * Update the per-port timeout.
2322 */
2323 uart_update_timeout(port, termios->c_cflag, baud);
2324
2325 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2326 if (termios->c_iflag & INPCK)
2327 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2328 if (termios->c_iflag & (BRKINT | PARMRK))
2329 up->port.read_status_mask |= UART_LSR_BI;
2330
2331 /*
2332 * Characteres to ignore
2333 */
2334 up->port.ignore_status_mask = 0;
2335 if (termios->c_iflag & IGNPAR)
2336 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2337 if (termios->c_iflag & IGNBRK) {
2338 up->port.ignore_status_mask |= UART_LSR_BI;
2339 /*
2340 * If we're ignoring parity and break indicators,
2341 * ignore overruns too (for real raw support).
2342 */
2343 if (termios->c_iflag & IGNPAR)
2344 up->port.ignore_status_mask |= UART_LSR_OE;
2345 }
2346
2347 /*
2348 * ignore all characters if CREAD is not set
2349 */
2350 if ((termios->c_cflag & CREAD) == 0)
2351 up->port.ignore_status_mask |= UART_LSR_DR;
2352
2353 /*
2354 * CTS flow control flag and modem status interrupts
2355 */
2356 up->ier &= ~UART_IER_MSI;
2357 if (!(up->bugs & UART_BUG_NOMSR) &&
2358 UART_ENABLE_MS(&up->port, termios->c_cflag))
2359 up->ier |= UART_IER_MSI;
2360 if (up->capabilities & UART_CAP_UUE)
2361 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
2362
2363 serial_out(up, UART_IER, up->ier);
2364
2365 if (up->capabilities & UART_CAP_EFR) {
2366 unsigned char efr = 0;
2367 /*
2368 * TI16C752/Startech hardware flow control. FIXME:
2369 * - TI16C752 requires control thresholds to be set.
2370 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2371 */
2372 if (termios->c_cflag & CRTSCTS)
2373 efr |= UART_EFR_CTS;
2374
2375 serial_outp(up, UART_LCR, 0xBF);
2376 serial_outp(up, UART_EFR, efr);
2377 }
2378
2379#ifdef CONFIG_ARCH_OMAP
2380 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2381 if (cpu_is_omap1510() && is_omap_port(up)) {
2382 if (baud == 115200) {
2383 quot = 1;
2384 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2385 } else
2386 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2387 }
2388#endif
2389
2390 if (up->capabilities & UART_NATSEMI) {
2391 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2392 serial_outp(up, UART_LCR, 0xe0);
2393 } else {
2394 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2395 }
2396
2397 serial_dl_write(up, quot);
2398
2399 /*
2400 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2401 * is written without DLAB set, this mode will be disabled.
2402 */
2403 if (up->port.type == PORT_16750)
2404 serial_outp(up, UART_FCR, fcr);
2405
2406 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2407 up->lcr = cval; /* Save LCR */
2408 if (up->port.type != PORT_16750) {
2409 if (fcr & UART_FCR_ENABLE_FIFO) {
2410 /* emulated UARTs (Lucent Venus 167x) need two steps */
2411 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2412 }
2413 serial_outp(up, UART_FCR, fcr); /* set fcr */
2414 }
2415 serial8250_set_mctrl(&up->port, up->port.mctrl);
2416 spin_unlock_irqrestore(&up->port.lock, flags);
2417 /* Don't rewrite B0 */
2418 if (tty_termios_baud_rate(termios))
2419 tty_termios_encode_baud_rate(termios, baud, baud);
2420}
2421EXPORT_SYMBOL(serial8250_do_set_termios);
2422
2423static void
2424serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2425 struct ktermios *old)
2426{
2427 if (port->set_termios)
2428 port->set_termios(port, termios, old);
2429 else
2430 serial8250_do_set_termios(port, termios, old);
2431}
2432
2433static void
2434serial8250_set_ldisc(struct uart_port *port, int new)
2435{
2436 if (new == N_PPS) {
2437 port->flags |= UPF_HARDPPS_CD;
2438 serial8250_enable_ms(port);
2439 } else
2440 port->flags &= ~UPF_HARDPPS_CD;
2441}
2442
2443static void
2444serial8250_pm(struct uart_port *port, unsigned int state,
2445 unsigned int oldstate)
2446{
2447 struct uart_8250_port *p = (struct uart_8250_port *)port;
2448
2449 serial8250_set_sleep(p, state != 0);
2450
2451 if (p->pm)
2452 p->pm(port, state, oldstate);
2453}
2454
2455static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2456{
2457 if (pt->port.iotype == UPIO_AU)
2458 return 0x1000;
2459#ifdef CONFIG_ARCH_OMAP
2460 if (is_omap_port(pt))
2461 return 0x16 << pt->port.regshift;
2462#endif
2463 return 8 << pt->port.regshift;
2464}
2465
2466/*
2467 * Resource handling.
2468 */
2469static int serial8250_request_std_resource(struct uart_8250_port *up)
2470{
2471 unsigned int size = serial8250_port_size(up);
2472 int ret = 0;
2473
2474 switch (up->port.iotype) {
2475 case UPIO_AU:
2476 case UPIO_TSI:
2477 case UPIO_MEM32:
2478 case UPIO_MEM:
2479 case UPIO_DWAPB:
2480 if (!up->port.mapbase)
2481 break;
2482
2483 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2484 ret = -EBUSY;
2485 break;
2486 }
2487
2488 if (up->port.flags & UPF_IOREMAP) {
2489 up->port.membase = ioremap_nocache(up->port.mapbase,
2490 size);
2491 if (!up->port.membase) {
2492 release_mem_region(up->port.mapbase, size);
2493 ret = -ENOMEM;
2494 }
2495 }
2496 break;
2497
2498 case UPIO_HUB6:
2499 case UPIO_PORT:
2500 if (!request_region(up->port.iobase, size, "serial"))
2501 ret = -EBUSY;
2502 break;
2503 }
2504 return ret;
2505}
2506
2507static void serial8250_release_std_resource(struct uart_8250_port *up)
2508{
2509 unsigned int size = serial8250_port_size(up);
2510
2511 switch (up->port.iotype) {
2512 case UPIO_AU:
2513 case UPIO_TSI:
2514 case UPIO_MEM32:
2515 case UPIO_MEM:
2516 case UPIO_DWAPB:
2517 if (!up->port.mapbase)
2518 break;
2519
2520 if (up->port.flags & UPF_IOREMAP) {
2521 iounmap(up->port.membase);
2522 up->port.membase = NULL;
2523 }
2524
2525 release_mem_region(up->port.mapbase, size);
2526 break;
2527
2528 case UPIO_HUB6:
2529 case UPIO_PORT:
2530 release_region(up->port.iobase, size);
2531 break;
2532 }
2533}
2534
2535static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2536{
2537 unsigned long start = UART_RSA_BASE << up->port.regshift;
2538 unsigned int size = 8 << up->port.regshift;
2539 int ret = -EINVAL;
2540
2541 switch (up->port.iotype) {
2542 case UPIO_HUB6:
2543 case UPIO_PORT:
2544 start += up->port.iobase;
2545 if (request_region(start, size, "serial-rsa"))
2546 ret = 0;
2547 else
2548 ret = -EBUSY;
2549 break;
2550 }
2551
2552 return ret;
2553}
2554
2555static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2556{
2557 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2558 unsigned int size = 8 << up->port.regshift;
2559
2560 switch (up->port.iotype) {
2561 case UPIO_HUB6:
2562 case UPIO_PORT:
2563 release_region(up->port.iobase + offset, size);
2564 break;
2565 }
2566}
2567
2568static void serial8250_release_port(struct uart_port *port)
2569{
2570 struct uart_8250_port *up = (struct uart_8250_port *)port;
2571
2572 serial8250_release_std_resource(up);
2573 if (up->port.type == PORT_RSA)
2574 serial8250_release_rsa_resource(up);
2575}
2576
2577static int serial8250_request_port(struct uart_port *port)
2578{
2579 struct uart_8250_port *up = (struct uart_8250_port *)port;
2580 int ret = 0;
2581
2582 ret = serial8250_request_std_resource(up);
2583 if (ret == 0 && up->port.type == PORT_RSA) {
2584 ret = serial8250_request_rsa_resource(up);
2585 if (ret < 0)
2586 serial8250_release_std_resource(up);
2587 }
2588
2589 return ret;
2590}
2591
2592static void serial8250_config_port(struct uart_port *port, int flags)
2593{
2594 struct uart_8250_port *up = (struct uart_8250_port *)port;
2595 int probeflags = PROBE_ANY;
2596 int ret;
2597
2598 /*
2599 * Find the region that we can probe for. This in turn
2600 * tells us whether we can probe for the type of port.
2601 */
2602 ret = serial8250_request_std_resource(up);
2603 if (ret < 0)
2604 return;
2605
2606 ret = serial8250_request_rsa_resource(up);
2607 if (ret < 0)
2608 probeflags &= ~PROBE_RSA;
2609
2610 if (up->port.iotype != up->cur_iotype)
2611 set_io_from_upio(port);
2612
2613 if (flags & UART_CONFIG_TYPE)
2614 autoconfig(up, probeflags);
2615
2616 /* if access method is AU, it is a 16550 with a quirk */
2617 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
2618 up->bugs |= UART_BUG_NOMSR;
2619
2620 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2621 autoconfig_irq(up);
2622
2623 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2624 serial8250_release_rsa_resource(up);
2625 if (up->port.type == PORT_UNKNOWN)
2626 serial8250_release_std_resource(up);
2627}
2628
2629static int
2630serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2631{
2632 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2633 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2634 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2635 ser->type == PORT_STARTECH)
2636 return -EINVAL;
2637 return 0;
2638}
2639
2640static const char *
2641serial8250_type(struct uart_port *port)
2642{
2643 int type = port->type;
2644
2645 if (type >= ARRAY_SIZE(uart_config))
2646 type = 0;
2647 return uart_config[type].name;
2648}
2649
2650static struct uart_ops serial8250_pops = {
2651 .tx_empty = serial8250_tx_empty,
2652 .set_mctrl = serial8250_set_mctrl,
2653 .get_mctrl = serial8250_get_mctrl,
2654 .stop_tx = serial8250_stop_tx,
2655 .start_tx = serial8250_start_tx,
2656 .stop_rx = serial8250_stop_rx,
2657 .enable_ms = serial8250_enable_ms,
2658 .break_ctl = serial8250_break_ctl,
2659 .startup = serial8250_startup,
2660 .shutdown = serial8250_shutdown,
2661 .set_termios = serial8250_set_termios,
2662 .set_ldisc = serial8250_set_ldisc,
2663 .pm = serial8250_pm,
2664 .type = serial8250_type,
2665 .release_port = serial8250_release_port,
2666 .request_port = serial8250_request_port,
2667 .config_port = serial8250_config_port,
2668 .verify_port = serial8250_verify_port,
2669#ifdef CONFIG_CONSOLE_POLL
2670 .poll_get_char = serial8250_get_poll_char,
2671 .poll_put_char = serial8250_put_poll_char,
2672#endif
2673};
2674
2675static struct uart_8250_port serial8250_ports[UART_NR];
2676
2677static void __init serial8250_isa_init_ports(void)
2678{
2679 struct uart_8250_port *up;
2680 static int first = 1;
2681 int i, irqflag = 0;
2682
2683 if (!first)
2684 return;
2685 first = 0;
2686
2687 for (i = 0; i < nr_uarts; i++) {
2688 struct uart_8250_port *up = &serial8250_ports[i];
2689
2690 up->port.line = i;
2691 spin_lock_init(&up->port.lock);
2692
2693 init_timer(&up->timer);
2694 up->timer.function = serial8250_timeout;
2695
2696 /*
2697 * ALPHA_KLUDGE_MCR needs to be killed.
2698 */
2699 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2700 up->mcr_force = ALPHA_KLUDGE_MCR;
2701
2702 up->port.ops = &serial8250_pops;
2703 }
2704
2705 if (share_irqs)
2706 irqflag = IRQF_SHARED;
2707
2708 for (i = 0, up = serial8250_ports;
2709 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2710 i++, up++) {
2711 up->port.iobase = old_serial_port[i].port;
2712 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2713 up->port.irqflags = old_serial_port[i].irqflags;
2714 up->port.uartclk = old_serial_port[i].baud_base * 16;
2715 up->port.flags = old_serial_port[i].flags;
2716 up->port.hub6 = old_serial_port[i].hub6;
2717 up->port.membase = old_serial_port[i].iomem_base;
2718 up->port.iotype = old_serial_port[i].io_type;
2719 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2720 set_io_from_upio(&up->port);
2721 up->port.irqflags |= irqflag;
2722 }
2723}
2724
2725static void
2726serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2727{
2728 up->port.type = type;
2729 up->port.fifosize = uart_config[type].fifo_size;
2730 up->capabilities = uart_config[type].flags;
2731 up->tx_loadsz = uart_config[type].tx_loadsz;
2732}
2733
2734static void __init
2735serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2736{
2737 int i;
2738
2739 for (i = 0; i < nr_uarts; i++) {
2740 struct uart_8250_port *up = &serial8250_ports[i];
2741 up->cur_iotype = 0xFF;
2742 }
2743
2744 serial8250_isa_init_ports();
2745
2746 for (i = 0; i < nr_uarts; i++) {
2747 struct uart_8250_port *up = &serial8250_ports[i];
2748
2749 up->port.dev = dev;
2750
2751 if (up->port.flags & UPF_FIXED_TYPE)
2752 serial8250_init_fixed_type_port(up, up->port.type);
2753
2754 uart_add_one_port(drv, &up->port);
2755 }
2756}
2757
2758#ifdef CONFIG_SERIAL_8250_CONSOLE
2759
2760static void serial8250_console_putchar(struct uart_port *port, int ch)
2761{
2762 struct uart_8250_port *up = (struct uart_8250_port *)port;
2763
2764 wait_for_xmitr(up, UART_LSR_THRE);
2765 serial_out(up, UART_TX, ch);
2766}
2767
2768/*
2769 * Print a string to the serial port trying not to disturb
2770 * any possible real use of the port...
2771 *
2772 * The console_lock must be held when we get here.
2773 */
2774static void
2775serial8250_console_write(struct console *co, const char *s, unsigned int count)
2776{
2777 struct uart_8250_port *up = &serial8250_ports[co->index];
2778 unsigned long flags;
2779 unsigned int ier;
2780 int locked = 1;
2781
2782 touch_nmi_watchdog();
2783
2784 local_irq_save(flags);
2785 if (up->port.sysrq) {
2786 /* serial8250_handle_port() already took the lock */
2787 locked = 0;
2788 } else if (oops_in_progress) {
2789 locked = spin_trylock(&up->port.lock);
2790 } else
2791 spin_lock(&up->port.lock);
2792
2793 /*
2794 * First save the IER then disable the interrupts
2795 */
2796 ier = serial_in(up, UART_IER);
2797
2798 if (up->capabilities & UART_CAP_UUE)
2799 serial_out(up, UART_IER, UART_IER_UUE);
2800 else
2801 serial_out(up, UART_IER, 0);
2802
2803 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2804
2805 /*
2806 * Finally, wait for transmitter to become empty
2807 * and restore the IER
2808 */
2809 wait_for_xmitr(up, BOTH_EMPTY);
2810 serial_out(up, UART_IER, ier);
2811
2812 /*
2813 * The receive handling will happen properly because the
2814 * receive ready bit will still be set; it is not cleared
2815 * on read. However, modem control will not, we must
2816 * call it if we have saved something in the saved flags
2817 * while processing with interrupts off.
2818 */
2819 if (up->msr_saved_flags)
2820 check_modem_status(up);
2821
2822 if (locked)
2823 spin_unlock(&up->port.lock);
2824 local_irq_restore(flags);
2825}
2826
2827static int __init serial8250_console_setup(struct console *co, char *options)
2828{
2829 struct uart_port *port;
2830 int baud = 9600;
2831 int bits = 8;
2832 int parity = 'n';
2833 int flow = 'n';
2834
2835 /*
2836 * Check whether an invalid uart number has been specified, and
2837 * if so, search for the first available port that does have
2838 * console support.
2839 */
2840 if (co->index >= nr_uarts)
2841 co->index = 0;
2842 port = &serial8250_ports[co->index].port;
2843 if (!port->iobase && !port->membase)
2844 return -ENODEV;
2845
2846 if (options)
2847 uart_parse_options(options, &baud, &parity, &bits, &flow);
2848
2849 return uart_set_options(port, co, baud, parity, bits, flow);
2850}
2851
2852static int serial8250_console_early_setup(void)
2853{
2854 return serial8250_find_port_for_earlycon();
2855}
2856
2857static struct console serial8250_console = {
2858 .name = "ttyS",
2859 .write = serial8250_console_write,
2860 .device = uart_console_device,
2861 .setup = serial8250_console_setup,
2862 .early_setup = serial8250_console_early_setup,
2863 .flags = CON_PRINTBUFFER,
2864 .index = -1,
2865 .data = &serial8250_reg,
2866};
2867
2868static int __init serial8250_console_init(void)
2869{
2870 if (nr_uarts > UART_NR)
2871 nr_uarts = UART_NR;
2872
2873 serial8250_isa_init_ports();
2874 register_console(&serial8250_console);
2875 return 0;
2876}
2877console_initcall(serial8250_console_init);
2878
2879int serial8250_find_port(struct uart_port *p)
2880{
2881 int line;
2882 struct uart_port *port;
2883
2884 for (line = 0; line < nr_uarts; line++) {
2885 port = &serial8250_ports[line].port;
2886 if (uart_match_port(p, port))
2887 return line;
2888 }
2889 return -ENODEV;
2890}
2891
2892#define SERIAL8250_CONSOLE &serial8250_console
2893#else
2894#define SERIAL8250_CONSOLE NULL
2895#endif
2896
2897static struct uart_driver serial8250_reg = {
2898 .owner = THIS_MODULE,
2899 .driver_name = "serial",
2900 .dev_name = "ttyS",
2901 .major = TTY_MAJOR,
2902 .minor = 64,
2903 .cons = SERIAL8250_CONSOLE,
2904};
2905
2906/*
2907 * early_serial_setup - early registration for 8250 ports
2908 *
2909 * Setup an 8250 port structure prior to console initialisation. Use
2910 * after console initialisation will cause undefined behaviour.
2911 */
2912int __init early_serial_setup(struct uart_port *port)
2913{
2914 struct uart_port *p;
2915
2916 if (port->line >= ARRAY_SIZE(serial8250_ports))
2917 return -ENODEV;
2918
2919 serial8250_isa_init_ports();
2920 p = &serial8250_ports[port->line].port;
2921 p->iobase = port->iobase;
2922 p->membase = port->membase;
2923 p->irq = port->irq;
2924 p->irqflags = port->irqflags;
2925 p->uartclk = port->uartclk;
2926 p->fifosize = port->fifosize;
2927 p->regshift = port->regshift;
2928 p->iotype = port->iotype;
2929 p->flags = port->flags;
2930 p->mapbase = port->mapbase;
2931 p->private_data = port->private_data;
2932 p->type = port->type;
2933 p->line = port->line;
2934
2935 set_io_from_upio(p);
2936 if (port->serial_in)
2937 p->serial_in = port->serial_in;
2938 if (port->serial_out)
2939 p->serial_out = port->serial_out;
2940
2941 return 0;
2942}
2943
2944/**
2945 * serial8250_suspend_port - suspend one serial port
2946 * @line: serial line number
2947 *
2948 * Suspend one serial port.
2949 */
2950void serial8250_suspend_port(int line)
2951{
2952 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2953}
2954
2955/**
2956 * serial8250_resume_port - resume one serial port
2957 * @line: serial line number
2958 *
2959 * Resume one serial port.
2960 */
2961void serial8250_resume_port(int line)
2962{
2963 struct uart_8250_port *up = &serial8250_ports[line];
2964
2965 if (up->capabilities & UART_NATSEMI) {
2966 unsigned char tmp;
2967
2968 /* Ensure it's still in high speed mode */
2969 serial_outp(up, UART_LCR, 0xE0);
2970
2971 tmp = serial_in(up, 0x04); /* EXCR2 */
2972 tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
2973 tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
2974 serial_outp(up, 0x04, tmp);
2975
2976 serial_outp(up, UART_LCR, 0);
2977 }
2978 uart_resume_port(&serial8250_reg, &up->port);
2979}
2980
2981/*
2982 * Register a set of serial devices attached to a platform device. The
2983 * list is terminated with a zero flags entry, which means we expect
2984 * all entries to have at least UPF_BOOT_AUTOCONF set.
2985 */
2986static int __devinit serial8250_probe(struct platform_device *dev)
2987{
2988 struct plat_serial8250_port *p = dev->dev.platform_data;
2989 struct uart_port port;
2990 int ret, i, irqflag = 0;
2991
2992 memset(&port, 0, sizeof(struct uart_port));
2993
2994 if (share_irqs)
2995 irqflag = IRQF_SHARED;
2996
2997 for (i = 0; p && p->flags != 0; p++, i++) {
2998 port.iobase = p->iobase;
2999 port.membase = p->membase;
3000 port.irq = p->irq;
3001 port.irqflags = p->irqflags;
3002 port.uartclk = p->uartclk;
3003 port.regshift = p->regshift;
3004 port.iotype = p->iotype;
3005 port.flags = p->flags;
3006 port.mapbase = p->mapbase;
3007 port.hub6 = p->hub6;
3008 port.private_data = p->private_data;
3009 port.type = p->type;
3010 port.serial_in = p->serial_in;
3011 port.serial_out = p->serial_out;
3012 port.set_termios = p->set_termios;
3013 port.dev = &dev->dev;
3014 port.irqflags |= irqflag;
3015 ret = serial8250_register_port(&port);
3016 if (ret < 0) {
3017 dev_err(&dev->dev, "unable to register port at index %d "
3018 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3019 p->iobase, (unsigned long long)p->mapbase,
3020 p->irq, ret);
3021 }
3022 }
3023 return 0;
3024}
3025
3026/*
3027 * Remove serial ports registered against a platform device.
3028 */
3029static int __devexit serial8250_remove(struct platform_device *dev)
3030{
3031 int i;
3032
3033 for (i = 0; i < nr_uarts; i++) {
3034 struct uart_8250_port *up = &serial8250_ports[i];
3035
3036 if (up->port.dev == &dev->dev)
3037 serial8250_unregister_port(i);
3038 }
3039 return 0;
3040}
3041
3042static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3043{
3044 int i;
3045
3046 for (i = 0; i < UART_NR; i++) {
3047 struct uart_8250_port *up = &serial8250_ports[i];
3048
3049 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3050 uart_suspend_port(&serial8250_reg, &up->port);
3051 }
3052
3053 return 0;
3054}
3055
3056static int serial8250_resume(struct platform_device *dev)
3057{
3058 int i;
3059
3060 for (i = 0; i < UART_NR; i++) {
3061 struct uart_8250_port *up = &serial8250_ports[i];
3062
3063 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3064 serial8250_resume_port(i);
3065 }
3066
3067 return 0;
3068}
3069
3070static struct platform_driver serial8250_isa_driver = {
3071 .probe = serial8250_probe,
3072 .remove = __devexit_p(serial8250_remove),
3073 .suspend = serial8250_suspend,
3074 .resume = serial8250_resume,
3075 .driver = {
3076 .name = "serial8250",
3077 .owner = THIS_MODULE,
3078 },
3079};
3080
3081/*
3082 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3083 * in the table in include/asm/serial.h
3084 */
3085static struct platform_device *serial8250_isa_devs;
3086
3087/*
3088 * serial8250_register_port and serial8250_unregister_port allows for
3089 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3090 * modems and PCI multiport cards.
3091 */
3092static DEFINE_MUTEX(serial_mutex);
3093
3094static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3095{
3096 int i;
3097
3098 /*
3099 * First, find a port entry which matches.
3100 */
3101 for (i = 0; i < nr_uarts; i++)
3102 if (uart_match_port(&serial8250_ports[i].port, port))
3103 return &serial8250_ports[i];
3104
3105 /*
3106 * We didn't find a matching entry, so look for the first
3107 * free entry. We look for one which hasn't been previously
3108 * used (indicated by zero iobase).
3109 */
3110 for (i = 0; i < nr_uarts; i++)
3111 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3112 serial8250_ports[i].port.iobase == 0)
3113 return &serial8250_ports[i];
3114
3115 /*
3116 * That also failed. Last resort is to find any entry which
3117 * doesn't have a real port associated with it.
3118 */
3119 for (i = 0; i < nr_uarts; i++)
3120 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3121 return &serial8250_ports[i];
3122
3123 return NULL;
3124}
3125
3126/**
3127 * serial8250_register_port - register a serial port
3128 * @port: serial port template
3129 *
3130 * Configure the serial port specified by the request. If the
3131 * port exists and is in use, it is hung up and unregistered
3132 * first.
3133 *
3134 * The port is then probed and if necessary the IRQ is autodetected
3135 * If this fails an error is returned.
3136 *
3137 * On success the port is ready to use and the line number is returned.
3138 */
3139int serial8250_register_port(struct uart_port *port)
3140{
3141 struct uart_8250_port *uart;
3142 int ret = -ENOSPC;
3143
3144 if (port->uartclk == 0)
3145 return -EINVAL;
3146
3147 mutex_lock(&serial_mutex);
3148
3149 uart = serial8250_find_match_or_unused(port);
3150 if (uart) {
3151 uart_remove_one_port(&serial8250_reg, &uart->port);
3152
3153 uart->port.iobase = port->iobase;
3154 uart->port.membase = port->membase;
3155 uart->port.irq = port->irq;
3156 uart->port.irqflags = port->irqflags;
3157 uart->port.uartclk = port->uartclk;
3158 uart->port.fifosize = port->fifosize;
3159 uart->port.regshift = port->regshift;
3160 uart->port.iotype = port->iotype;
3161 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3162 uart->port.mapbase = port->mapbase;
3163 uart->port.private_data = port->private_data;
3164 if (port->dev)
3165 uart->port.dev = port->dev;
3166
3167 if (port->flags & UPF_FIXED_TYPE)
3168 serial8250_init_fixed_type_port(uart, port->type);
3169
3170 set_io_from_upio(&uart->port);
3171 /* Possibly override default I/O functions. */
3172 if (port->serial_in)
3173 uart->port.serial_in = port->serial_in;
3174 if (port->serial_out)
3175 uart->port.serial_out = port->serial_out;
3176 /* Possibly override set_termios call */
3177 if (port->set_termios)
3178 uart->port.set_termios = port->set_termios;
3179
3180 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3181 if (ret == 0)
3182 ret = uart->port.line;
3183 }
3184 mutex_unlock(&serial_mutex);
3185
3186 return ret;
3187}
3188EXPORT_SYMBOL(serial8250_register_port);
3189
3190/**
3191 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3192 * @line: serial line number
3193 *
3194 * Remove one serial port. This may not be called from interrupt
3195 * context. We hand the port back to the our control.
3196 */
3197void serial8250_unregister_port(int line)
3198{
3199 struct uart_8250_port *uart = &serial8250_ports[line];
3200
3201 mutex_lock(&serial_mutex);
3202 uart_remove_one_port(&serial8250_reg, &uart->port);
3203 if (serial8250_isa_devs) {
3204 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3205 uart->port.type = PORT_UNKNOWN;
3206 uart->port.dev = &serial8250_isa_devs->dev;
3207 uart_add_one_port(&serial8250_reg, &uart->port);
3208 } else {
3209 uart->port.dev = NULL;
3210 }
3211 mutex_unlock(&serial_mutex);
3212}
3213EXPORT_SYMBOL(serial8250_unregister_port);
3214
3215static int __init serial8250_init(void)
3216{
3217 int ret;
3218
3219 if (nr_uarts > UART_NR)
3220 nr_uarts = UART_NR;
3221
3222 printk(KERN_INFO "Serial: 8250/16550 driver, "
3223 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3224 share_irqs ? "en" : "dis");
3225
3226#ifdef CONFIG_SPARC
3227 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3228#else
3229 serial8250_reg.nr = UART_NR;
3230 ret = uart_register_driver(&serial8250_reg);
3231#endif
3232 if (ret)
3233 goto out;
3234
3235 serial8250_isa_devs = platform_device_alloc("serial8250",
3236 PLAT8250_DEV_LEGACY);
3237 if (!serial8250_isa_devs) {
3238 ret = -ENOMEM;
3239 goto unreg_uart_drv;
3240 }
3241
3242 ret = platform_device_add(serial8250_isa_devs);
3243 if (ret)
3244 goto put_dev;
3245
3246 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3247
3248 ret = platform_driver_register(&serial8250_isa_driver);
3249 if (ret == 0)
3250 goto out;
3251
3252 platform_device_del(serial8250_isa_devs);
3253put_dev:
3254 platform_device_put(serial8250_isa_devs);
3255unreg_uart_drv:
3256#ifdef CONFIG_SPARC
3257 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3258#else
3259 uart_unregister_driver(&serial8250_reg);
3260#endif
3261out:
3262 return ret;
3263}
3264
3265static void __exit serial8250_exit(void)
3266{
3267 struct platform_device *isa_dev = serial8250_isa_devs;
3268
3269 /*
3270 * This tells serial8250_unregister_port() not to re-register
3271 * the ports (thereby making serial8250_isa_driver permanently
3272 * in use.)
3273 */
3274 serial8250_isa_devs = NULL;
3275
3276 platform_driver_unregister(&serial8250_isa_driver);
3277 platform_device_unregister(isa_dev);
3278
3279#ifdef CONFIG_SPARC
3280 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3281#else
3282 uart_unregister_driver(&serial8250_reg);
3283#endif
3284}
3285
3286module_init(serial8250_init);
3287module_exit(serial8250_exit);
3288
3289EXPORT_SYMBOL(serial8250_suspend_port);
3290EXPORT_SYMBOL(serial8250_resume_port);
3291
3292MODULE_LICENSE("GPL");
3293MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3294
3295module_param(share_irqs, uint, 0644);
3296MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3297 " (unsafe)");
3298
3299module_param(nr_uarts, uint, 0644);
3300MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3301
3302module_param(skip_txen_test, uint, 0644);
3303MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3304
3305#ifdef CONFIG_SERIAL_8250_RSA
3306module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3307MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3308#endif
3309MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-25 12:27:00 -0400