aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/serial/bfin_sport_uart.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/serial/bfin_sport_uart.c')
-rw-r--r--drivers/serial/bfin_sport_uart.c702
1 files changed, 470 insertions, 232 deletions
diff --git a/drivers/serial/bfin_sport_uart.c b/drivers/serial/bfin_sport_uart.c
index 088bb35475f1..c88f8ad3ff82 100644
--- a/drivers/serial/bfin_sport_uart.c
+++ b/drivers/serial/bfin_sport_uart.c
@@ -1,27 +1,11 @@
1/* 1/*
2 * File: linux/drivers/serial/bfin_sport_uart.c 2 * Blackfin On-Chip Sport Emulated UART Driver
3 * 3 *
4 * Based on: drivers/serial/bfin_5xx.c by Aubrey Li. 4 * Copyright 2006-2009 Analog Devices Inc.
5 * Author: Roy Huang <roy.huang@analog.com>
6 * 5 *
7 * Created: Nov 22, 2006 6 * Enter bugs at http://blackfin.uclinux.org/
8 * Copyright: (c) 2006-2007 Analog Devices Inc.
9 * Description: this driver enable SPORTs on Blackfin emulate UART.
10 * 7 *
11 * This program is free software; you can redistribute it and/or modify 8 * Licensed under the GPL-2 or later.
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see the file COPYING, or write
23 * to the Free Software Foundation, Inc.,
24 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 */ 9 */
26 10
27/* 11/*
@@ -29,42 +13,22 @@
29 * http://www.analog.com/UploadedFiles/Application_Notes/399447663EE191.pdf 13 * http://www.analog.com/UploadedFiles/Application_Notes/399447663EE191.pdf
30 * This application note describe how to implement a UART on a Sharc DSP, 14 * This application note describe how to implement a UART on a Sharc DSP,
31 * but this driver is implemented on Blackfin Processor. 15 * but this driver is implemented on Blackfin Processor.
16 * Transmit Frame Sync is not used by this driver to transfer data out.
32 */ 17 */
33 18
34/* After reset, there is a prelude of low level pulse when transmit data first 19/* #define DEBUG */
35 * time. No addtional pulse in following transmit.
36 * According to document:
37 * The SPORTs are ready to start transmitting or receiving data no later than
38 * three serial clock cycles after they are enabled in the SPORTx_TCR1 or
39 * SPORTx_RCR1 register. No serial clock cycles are lost from this point on.
40 * The first internal frame sync will occur one frame sync delay after the
41 * SPORTs are ready. External frame syncs can occur as soon as the SPORT is
42 * ready.
43 */
44 20
45/* Thanks to Axel Alatalo <axel@rubico.se> for fixing sport rx bug. Sometimes 21#define DRV_NAME "bfin-sport-uart"
46 * sport receives data incorrectly. The following is Axel's words. 22#define DEVICE_NAME "ttySS"
47 * As EE-191, sport rx samples 3 times of the UART baudrate and takes the 23#define pr_fmt(fmt) DRV_NAME ": " fmt
48 * middle smaple of every 3 samples as the data bit. For a 8-N-1 UART setting,
49 * 30 samples will be required for a byte. If transmitter sends a 1/3 bit short
50 * byte due to buadrate drift, then the 30th sample of a byte, this sample is
51 * also the third sample of the stop bit, will happens on the immediately
52 * following start bit which will be thrown away and missed. Thus since parts
53 * of the startbit will be missed and the receiver will begin to drift, the
54 * effect accumulates over time until synchronization is lost.
55 * If only require 2 samples of the stopbit (by sampling in total 29 samples),
56 * then a to short byte as in the case above will be tolerated. Then the 1/3
57 * early startbit will trigger a framesync since the last read is complete
58 * after only 2/3 stopbit and framesync is active during the last 1/3 looking
59 * for a possible early startbit. */
60
61//#define DEBUG
62 24
63#include <linux/module.h> 25#include <linux/module.h>
64#include <linux/ioport.h> 26#include <linux/ioport.h>
27#include <linux/io.h>
65#include <linux/init.h> 28#include <linux/init.h>
66#include <linux/console.h> 29#include <linux/console.h>
67#include <linux/sysrq.h> 30#include <linux/sysrq.h>
31#include <linux/slab.h>
68#include <linux/platform_device.h> 32#include <linux/platform_device.h>
69#include <linux/tty.h> 33#include <linux/tty.h>
70#include <linux/tty_flip.h> 34#include <linux/tty_flip.h>
@@ -75,23 +39,36 @@
75 39
76#include "bfin_sport_uart.h" 40#include "bfin_sport_uart.h"
77 41
42#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
78unsigned short bfin_uart_pin_req_sport0[] = 43unsigned short bfin_uart_pin_req_sport0[] =
79 {P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, \ 44 {P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, \
80 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0}; 45 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0};
81 46#endif
47#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
82unsigned short bfin_uart_pin_req_sport1[] = 48unsigned short bfin_uart_pin_req_sport1[] =
83 {P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, \ 49 {P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, \
84 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0}; 50 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0};
85 51#endif
86#define DRV_NAME "bfin-sport-uart" 52#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
53unsigned short bfin_uart_pin_req_sport2[] =
54 {P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS, \
55 P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0};
56#endif
57#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
58unsigned short bfin_uart_pin_req_sport3[] =
59 {P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS, \
60 P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0};
61#endif
87 62
88struct sport_uart_port { 63struct sport_uart_port {
89 struct uart_port port; 64 struct uart_port port;
90 char *name;
91
92 int tx_irq;
93 int rx_irq;
94 int err_irq; 65 int err_irq;
66 unsigned short csize;
67 unsigned short rxmask;
68 unsigned short txmask1;
69 unsigned short txmask2;
70 unsigned char stopb;
71/* unsigned char parib; */
95}; 72};
96 73
97static void sport_uart_tx_chars(struct sport_uart_port *up); 74static void sport_uart_tx_chars(struct sport_uart_port *up);
@@ -99,36 +76,42 @@ static void sport_stop_tx(struct uart_port *port);
99 76
100static inline void tx_one_byte(struct sport_uart_port *up, unsigned int value) 77static inline void tx_one_byte(struct sport_uart_port *up, unsigned int value)
101{ 78{
102 pr_debug("%s value:%x\n", __func__, value); 79 pr_debug("%s value:%x, mask1=0x%x, mask2=0x%x\n", __func__, value,
103 /* Place a Start and Stop bit */ 80 up->txmask1, up->txmask2);
81
82 /* Place Start and Stop bits */
104 __asm__ __volatile__ ( 83 __asm__ __volatile__ (
105 "R2 = b#01111111100;" 84 "%[val] <<= 1;"
106 "R3 = b#10000000001;" 85 "%[val] = %[val] & %[mask1];"
107 "%0 <<= 2;" 86 "%[val] = %[val] | %[mask2];"
108 "%0 = %0 & R2;" 87 : [val]"+d"(value)
109 "%0 = %0 | R3;" 88 : [mask1]"d"(up->txmask1), [mask2]"d"(up->txmask2)
110 : "=d"(value) 89 : "ASTAT"
111 : "d"(value)
112 : "ASTAT", "R2", "R3"
113 ); 90 );
114 pr_debug("%s value:%x\n", __func__, value); 91 pr_debug("%s value:%x\n", __func__, value);
115 92
116 SPORT_PUT_TX(up, value); 93 SPORT_PUT_TX(up, value);
117} 94}
118 95
119static inline unsigned int rx_one_byte(struct sport_uart_port *up) 96static inline unsigned char rx_one_byte(struct sport_uart_port *up)
120{ 97{
121 unsigned int value, extract; 98 unsigned int value;
99 unsigned char extract;
122 u32 tmp_mask1, tmp_mask2, tmp_shift, tmp; 100 u32 tmp_mask1, tmp_mask2, tmp_shift, tmp;
123 101
124 value = SPORT_GET_RX32(up); 102 if ((up->csize + up->stopb) > 7)
125 pr_debug("%s value:%x\n", __func__, value); 103 value = SPORT_GET_RX32(up);
104 else
105 value = SPORT_GET_RX(up);
106
107 pr_debug("%s value:%x, cs=%d, mask=0x%x\n", __func__, value,
108 up->csize, up->rxmask);
126 109
127 /* Extract 8 bits data */ 110 /* Extract data */
128 __asm__ __volatile__ ( 111 __asm__ __volatile__ (
129 "%[extr] = 0;" 112 "%[extr] = 0;"
130 "%[mask1] = 0x1801(Z);" 113 "%[mask1] = %[rxmask];"
131 "%[mask2] = 0x0300(Z);" 114 "%[mask2] = 0x0200(Z);"
132 "%[shift] = 0;" 115 "%[shift] = 0;"
133 "LSETUP(.Lloop_s, .Lloop_e) LC0 = %[lc];" 116 "LSETUP(.Lloop_s, .Lloop_e) LC0 = %[lc];"
134 ".Lloop_s:" 117 ".Lloop_s:"
@@ -138,9 +121,9 @@ static inline unsigned int rx_one_byte(struct sport_uart_port *up)
138 "%[mask1] = %[mask1] - %[mask2];" 121 "%[mask1] = %[mask1] - %[mask2];"
139 ".Lloop_e:" 122 ".Lloop_e:"
140 "%[shift] += 1;" 123 "%[shift] += 1;"
141 : [val]"=d"(value), [extr]"=d"(extract), [shift]"=d"(tmp_shift), [tmp]"=d"(tmp), 124 : [extr]"=&d"(extract), [shift]"=&d"(tmp_shift), [tmp]"=&d"(tmp),
142 [mask1]"=d"(tmp_mask1), [mask2]"=d"(tmp_mask2) 125 [mask1]"=&d"(tmp_mask1), [mask2]"=&d"(tmp_mask2)
143 : "d"(value), [lc]"a"(8) 126 : [val]"d"(value), [rxmask]"d"(up->rxmask), [lc]"a"(up->csize)
144 : "ASTAT", "LB0", "LC0", "LT0" 127 : "ASTAT", "LB0", "LC0", "LT0"
145 ); 128 );
146 129
@@ -148,29 +131,28 @@ static inline unsigned int rx_one_byte(struct sport_uart_port *up)
148 return extract; 131 return extract;
149} 132}
150 133
151static int sport_uart_setup(struct sport_uart_port *up, int sclk, int baud_rate) 134static int sport_uart_setup(struct sport_uart_port *up, int size, int baud_rate)
152{ 135{
153 int tclkdiv, tfsdiv, rclkdiv; 136 int tclkdiv, rclkdiv;
137 unsigned int sclk = get_sclk();
154 138
155 /* Set TCR1 and TCR2 */ 139 /* Set TCR1 and TCR2, TFSR is not enabled for uart */
156 SPORT_PUT_TCR1(up, (LATFS | ITFS | TFSR | TLSBIT | ITCLK)); 140 SPORT_PUT_TCR1(up, (ITFS | TLSBIT | ITCLK));
157 SPORT_PUT_TCR2(up, 10); 141 SPORT_PUT_TCR2(up, size + 1);
158 pr_debug("%s TCR1:%x, TCR2:%x\n", __func__, SPORT_GET_TCR1(up), SPORT_GET_TCR2(up)); 142 pr_debug("%s TCR1:%x, TCR2:%x\n", __func__, SPORT_GET_TCR1(up), SPORT_GET_TCR2(up));
159 143
160 /* Set RCR1 and RCR2 */ 144 /* Set RCR1 and RCR2 */
161 SPORT_PUT_RCR1(up, (RCKFE | LARFS | LRFS | RFSR | IRCLK)); 145 SPORT_PUT_RCR1(up, (RCKFE | LARFS | LRFS | RFSR | IRCLK));
162 SPORT_PUT_RCR2(up, 28); 146 SPORT_PUT_RCR2(up, (size + 1) * 2 - 1);
163 pr_debug("%s RCR1:%x, RCR2:%x\n", __func__, SPORT_GET_RCR1(up), SPORT_GET_RCR2(up)); 147 pr_debug("%s RCR1:%x, RCR2:%x\n", __func__, SPORT_GET_RCR1(up), SPORT_GET_RCR2(up));
164 148
165 tclkdiv = sclk/(2 * baud_rate) - 1; 149 tclkdiv = sclk / (2 * baud_rate) - 1;
166 tfsdiv = 12; 150 rclkdiv = sclk / (2 * baud_rate * 2) - 1;
167 rclkdiv = sclk/(2 * baud_rate * 3) - 1;
168 SPORT_PUT_TCLKDIV(up, tclkdiv); 151 SPORT_PUT_TCLKDIV(up, tclkdiv);
169 SPORT_PUT_TFSDIV(up, tfsdiv);
170 SPORT_PUT_RCLKDIV(up, rclkdiv); 152 SPORT_PUT_RCLKDIV(up, rclkdiv);
171 SSYNC(); 153 SSYNC();
172 pr_debug("%s sclk:%d, baud_rate:%d, tclkdiv:%d, tfsdiv:%d, rclkdiv:%d\n", 154 pr_debug("%s sclk:%d, baud_rate:%d, tclkdiv:%d, rclkdiv:%d\n",
173 __func__, sclk, baud_rate, tclkdiv, tfsdiv, rclkdiv); 155 __func__, sclk, baud_rate, tclkdiv, rclkdiv);
174 156
175 return 0; 157 return 0;
176} 158}
@@ -181,23 +163,29 @@ static irqreturn_t sport_uart_rx_irq(int irq, void *dev_id)
181 struct tty_struct *tty = up->port.state->port.tty; 163 struct tty_struct *tty = up->port.state->port.tty;
182 unsigned int ch; 164 unsigned int ch;
183 165
184 do { 166 spin_lock(&up->port.lock);
167
168 while (SPORT_GET_STAT(up) & RXNE) {
185 ch = rx_one_byte(up); 169 ch = rx_one_byte(up);
186 up->port.icount.rx++; 170 up->port.icount.rx++;
187 171
188 if (uart_handle_sysrq_char(&up->port, ch)) 172 if (!uart_handle_sysrq_char(&up->port, ch))
189 ;
190 else
191 tty_insert_flip_char(tty, ch, TTY_NORMAL); 173 tty_insert_flip_char(tty, ch, TTY_NORMAL);
192 } while (SPORT_GET_STAT(up) & RXNE); 174 }
193 tty_flip_buffer_push(tty); 175 tty_flip_buffer_push(tty);
194 176
177 spin_unlock(&up->port.lock);
178
195 return IRQ_HANDLED; 179 return IRQ_HANDLED;
196} 180}
197 181
198static irqreturn_t sport_uart_tx_irq(int irq, void *dev_id) 182static irqreturn_t sport_uart_tx_irq(int irq, void *dev_id)
199{ 183{
200 sport_uart_tx_chars(dev_id); 184 struct sport_uart_port *up = dev_id;
185
186 spin_lock(&up->port.lock);
187 sport_uart_tx_chars(up);
188 spin_unlock(&up->port.lock);
201 189
202 return IRQ_HANDLED; 190 return IRQ_HANDLED;
203} 191}
@@ -208,6 +196,8 @@ static irqreturn_t sport_uart_err_irq(int irq, void *dev_id)
208 struct tty_struct *tty = up->port.state->port.tty; 196 struct tty_struct *tty = up->port.state->port.tty;
209 unsigned int stat = SPORT_GET_STAT(up); 197 unsigned int stat = SPORT_GET_STAT(up);
210 198
199 spin_lock(&up->port.lock);
200
211 /* Overflow in RX FIFO */ 201 /* Overflow in RX FIFO */
212 if (stat & ROVF) { 202 if (stat & ROVF) {
213 up->port.icount.overrun++; 203 up->port.icount.overrun++;
@@ -216,15 +206,16 @@ static irqreturn_t sport_uart_err_irq(int irq, void *dev_id)
216 } 206 }
217 /* These should not happen */ 207 /* These should not happen */
218 if (stat & (TOVF | TUVF | RUVF)) { 208 if (stat & (TOVF | TUVF | RUVF)) {
219 printk(KERN_ERR "SPORT Error:%s %s %s\n", 209 pr_err("SPORT Error:%s %s %s\n",
220 (stat & TOVF)?"TX overflow":"", 210 (stat & TOVF) ? "TX overflow" : "",
221 (stat & TUVF)?"TX underflow":"", 211 (stat & TUVF) ? "TX underflow" : "",
222 (stat & RUVF)?"RX underflow":""); 212 (stat & RUVF) ? "RX underflow" : "");
223 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN); 213 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
224 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN); 214 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
225 } 215 }
226 SSYNC(); 216 SSYNC();
227 217
218 spin_unlock(&up->port.lock);
228 return IRQ_HANDLED; 219 return IRQ_HANDLED;
229} 220}
230 221
@@ -232,60 +223,37 @@ static irqreturn_t sport_uart_err_irq(int irq, void *dev_id)
232static int sport_startup(struct uart_port *port) 223static int sport_startup(struct uart_port *port)
233{ 224{
234 struct sport_uart_port *up = (struct sport_uart_port *)port; 225 struct sport_uart_port *up = (struct sport_uart_port *)port;
235 char buffer[20]; 226 int ret;
236 int retval;
237 227
238 pr_debug("%s enter\n", __func__); 228 pr_debug("%s enter\n", __func__);
239 snprintf(buffer, 20, "%s rx", up->name); 229 ret = request_irq(up->port.irq, sport_uart_rx_irq, 0,
240 retval = request_irq(up->rx_irq, sport_uart_rx_irq, IRQF_SAMPLE_RANDOM, buffer, up); 230 "SPORT_UART_RX", up);
241 if (retval) { 231 if (ret) {
242 printk(KERN_ERR "Unable to request interrupt %s\n", buffer); 232 dev_err(port->dev, "unable to request SPORT RX interrupt\n");
243 return retval; 233 return ret;
244 } 234 }
245 235
246 snprintf(buffer, 20, "%s tx", up->name); 236 ret = request_irq(up->port.irq+1, sport_uart_tx_irq, 0,
247 retval = request_irq(up->tx_irq, sport_uart_tx_irq, IRQF_SAMPLE_RANDOM, buffer, up); 237 "SPORT_UART_TX", up);
248 if (retval) { 238 if (ret) {
249 printk(KERN_ERR "Unable to request interrupt %s\n", buffer); 239 dev_err(port->dev, "unable to request SPORT TX interrupt\n");
250 goto fail1; 240 goto fail1;
251 } 241 }
252 242
253 snprintf(buffer, 20, "%s err", up->name); 243 ret = request_irq(up->err_irq, sport_uart_err_irq, 0,
254 retval = request_irq(up->err_irq, sport_uart_err_irq, IRQF_SAMPLE_RANDOM, buffer, up); 244 "SPORT_UART_STATUS", up);
255 if (retval) { 245 if (ret) {
256 printk(KERN_ERR "Unable to request interrupt %s\n", buffer); 246 dev_err(port->dev, "unable to request SPORT status interrupt\n");
257 goto fail2; 247 goto fail2;
258 } 248 }
259 249
260 if (port->line) {
261 if (peripheral_request_list(bfin_uart_pin_req_sport1, DRV_NAME))
262 goto fail3;
263 } else {
264 if (peripheral_request_list(bfin_uart_pin_req_sport0, DRV_NAME))
265 goto fail3;
266 }
267
268 sport_uart_setup(up, get_sclk(), port->uartclk);
269
270 /* Enable receive interrupt */
271 SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) | RSPEN));
272 SSYNC();
273
274 return 0; 250 return 0;
251 fail2:
252 free_irq(up->port.irq+1, up);
253 fail1:
254 free_irq(up->port.irq, up);
275 255
276 256 return ret;
277fail3:
278 printk(KERN_ERR DRV_NAME
279 ": Requesting Peripherals failed\n");
280
281 free_irq(up->err_irq, up);
282fail2:
283 free_irq(up->tx_irq, up);
284fail1:
285 free_irq(up->rx_irq, up);
286
287 return retval;
288
289} 257}
290 258
291static void sport_uart_tx_chars(struct sport_uart_port *up) 259static void sport_uart_tx_chars(struct sport_uart_port *up)
@@ -344,20 +312,17 @@ static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl)
344static void sport_stop_tx(struct uart_port *port) 312static void sport_stop_tx(struct uart_port *port)
345{ 313{
346 struct sport_uart_port *up = (struct sport_uart_port *)port; 314 struct sport_uart_port *up = (struct sport_uart_port *)port;
347 unsigned int stat;
348 315
349 pr_debug("%s enter\n", __func__); 316 pr_debug("%s enter\n", __func__);
350 317
351 stat = SPORT_GET_STAT(up);
352 while(!(stat & TXHRE)) {
353 udelay(1);
354 stat = SPORT_GET_STAT(up);
355 }
356 /* Although the hold register is empty, last byte is still in shift 318 /* Although the hold register is empty, last byte is still in shift
357 * register and not sent out yet. If baud rate is lower than default, 319 * register and not sent out yet. So, put a dummy data into TX FIFO.
358 * delay should be longer. For example, if the baud rate is 9600, 320 * Then, sport tx stops when last byte is shift out and the dummy
359 * the delay must be at least 2ms by experience */ 321 * data is moved into the shift register.
360 udelay(500); 322 */
323 SPORT_PUT_TX(up, 0xffff);
324 while (!(SPORT_GET_STAT(up) & TXHRE))
325 cpu_relax();
361 326
362 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN)); 327 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
363 SSYNC(); 328 SSYNC();
@@ -370,6 +335,7 @@ static void sport_start_tx(struct uart_port *port)
370 struct sport_uart_port *up = (struct sport_uart_port *)port; 335 struct sport_uart_port *up = (struct sport_uart_port *)port;
371 336
372 pr_debug("%s enter\n", __func__); 337 pr_debug("%s enter\n", __func__);
338
373 /* Write data into SPORT FIFO before enable SPROT to transmit */ 339 /* Write data into SPORT FIFO before enable SPROT to transmit */
374 sport_uart_tx_chars(up); 340 sport_uart_tx_chars(up);
375 341
@@ -403,37 +369,24 @@ static void sport_shutdown(struct uart_port *port)
403{ 369{
404 struct sport_uart_port *up = (struct sport_uart_port *)port; 370 struct sport_uart_port *up = (struct sport_uart_port *)port;
405 371
406 pr_debug("%s enter\n", __func__); 372 dev_dbg(port->dev, "%s enter\n", __func__);
407 373
408 /* Disable sport */ 374 /* Disable sport */
409 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN)); 375 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
410 SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN)); 376 SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
411 SSYNC(); 377 SSYNC();
412 378
413 if (port->line) { 379 free_irq(up->port.irq, up);
414 peripheral_free_list(bfin_uart_pin_req_sport1); 380 free_irq(up->port.irq+1, up);
415 } else {
416 peripheral_free_list(bfin_uart_pin_req_sport0);
417 }
418
419 free_irq(up->rx_irq, up);
420 free_irq(up->tx_irq, up);
421 free_irq(up->err_irq, up); 381 free_irq(up->err_irq, up);
422} 382}
423 383
424static void sport_set_termios(struct uart_port *port,
425 struct ktermios *termios, struct ktermios *old)
426{
427 pr_debug("%s enter, c_cflag:%08x\n", __func__, termios->c_cflag);
428 uart_update_timeout(port, CS8 ,port->uartclk);
429}
430
431static const char *sport_type(struct uart_port *port) 384static const char *sport_type(struct uart_port *port)
432{ 385{
433 struct sport_uart_port *up = (struct sport_uart_port *)port; 386 struct sport_uart_port *up = (struct sport_uart_port *)port;
434 387
435 pr_debug("%s enter\n", __func__); 388 pr_debug("%s enter\n", __func__);
436 return up->name; 389 return up->port.type == PORT_BFIN_SPORT ? "BFIN-SPORT-UART" : NULL;
437} 390}
438 391
439static void sport_release_port(struct uart_port *port) 392static void sport_release_port(struct uart_port *port)
@@ -461,6 +414,110 @@ static int sport_verify_port(struct uart_port *port, struct serial_struct *ser)
461 return 0; 414 return 0;
462} 415}
463 416
417static void sport_set_termios(struct uart_port *port,
418 struct ktermios *termios, struct ktermios *old)
419{
420 struct sport_uart_port *up = (struct sport_uart_port *)port;
421 unsigned long flags;
422 int i;
423
424 pr_debug("%s enter, c_cflag:%08x\n", __func__, termios->c_cflag);
425
426 switch (termios->c_cflag & CSIZE) {
427 case CS8:
428 up->csize = 8;
429 break;
430 case CS7:
431 up->csize = 7;
432 break;
433 case CS6:
434 up->csize = 6;
435 break;
436 case CS5:
437 up->csize = 5;
438 break;
439 default:
440 pr_warning("requested word length not supported\n");
441 }
442
443 if (termios->c_cflag & CSTOPB) {
444 up->stopb = 1;
445 }
446 if (termios->c_cflag & PARENB) {
447 pr_warning("PAREN bits is not supported yet\n");
448 /* up->parib = 1; */
449 }
450
451 port->read_status_mask = OE;
452 if (termios->c_iflag & INPCK)
453 port->read_status_mask |= (FE | PE);
454 if (termios->c_iflag & (BRKINT | PARMRK))
455 port->read_status_mask |= BI;
456
457 /*
458 * Characters to ignore
459 */
460 port->ignore_status_mask = 0;
461 if (termios->c_iflag & IGNPAR)
462 port->ignore_status_mask |= FE | PE;
463 if (termios->c_iflag & IGNBRK) {
464 port->ignore_status_mask |= BI;
465 /*
466 * If we're ignoring parity and break indicators,
467 * ignore overruns too (for real raw support).
468 */
469 if (termios->c_iflag & IGNPAR)
470 port->ignore_status_mask |= OE;
471 }
472
473 /* RX extract mask */
474 up->rxmask = 0x01 | (((up->csize + up->stopb) * 2 - 1) << 0x8);
475 /* TX masks, 8 bit data and 1 bit stop for example:
476 * mask1 = b#0111111110
477 * mask2 = b#1000000000
478 */
479 for (i = 0, up->txmask1 = 0; i < up->csize; i++)
480 up->txmask1 |= (1<<i);
481 up->txmask2 = (1<<i);
482 if (up->stopb) {
483 ++i;
484 up->txmask2 |= (1<<i);
485 }
486 up->txmask1 <<= 1;
487 up->txmask2 <<= 1;
488 /* uart baud rate */
489 port->uartclk = uart_get_baud_rate(port, termios, old, 0, get_sclk()/16);
490
491 spin_lock_irqsave(&up->port.lock, flags);
492
493 /* Disable UART */
494 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
495 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
496
497 sport_uart_setup(up, up->csize + up->stopb, port->uartclk);
498
499 /* driver TX line high after config, one dummy data is
500 * necessary to stop sport after shift one byte
501 */
502 SPORT_PUT_TX(up, 0xffff);
503 SPORT_PUT_TX(up, 0xffff);
504 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
505 SSYNC();
506 while (!(SPORT_GET_STAT(up) & TXHRE))
507 cpu_relax();
508 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
509 SSYNC();
510
511 /* Port speed changed, update the per-port timeout. */
512 uart_update_timeout(port, termios->c_cflag, port->uartclk);
513
514 /* Enable sport rx */
515 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) | RSPEN);
516 SSYNC();
517
518 spin_unlock_irqrestore(&up->port.lock, flags);
519}
520
464struct uart_ops sport_uart_ops = { 521struct uart_ops sport_uart_ops = {
465 .tx_empty = sport_tx_empty, 522 .tx_empty = sport_tx_empty,
466 .set_mctrl = sport_set_mctrl, 523 .set_mctrl = sport_set_mctrl,
@@ -480,138 +537,319 @@ struct uart_ops sport_uart_ops = {
480 .verify_port = sport_verify_port, 537 .verify_port = sport_verify_port,
481}; 538};
482 539
483static struct sport_uart_port sport_uart_ports[] = { 540#define BFIN_SPORT_UART_MAX_PORTS 4
484 { /* SPORT 0 */ 541
485 .name = "SPORT0", 542static struct sport_uart_port *bfin_sport_uart_ports[BFIN_SPORT_UART_MAX_PORTS];
486 .tx_irq = IRQ_SPORT0_TX, 543
487 .rx_irq = IRQ_SPORT0_RX, 544#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
488 .err_irq= IRQ_SPORT0_ERROR, 545static int __init
489 .port = { 546sport_uart_console_setup(struct console *co, char *options)
490 .type = PORT_BFIN_SPORT, 547{
491 .iotype = UPIO_MEM, 548 struct sport_uart_port *up;
492 .membase = (void __iomem *)SPORT0_TCR1, 549 int baud = 57600;
493 .mapbase = SPORT0_TCR1, 550 int bits = 8;
494 .irq = IRQ_SPORT0_RX, 551 int parity = 'n';
495 .uartclk = CONFIG_SPORT_BAUD_RATE, 552 int flow = 'n';
496 .fifosize = 8, 553
497 .ops = &sport_uart_ops, 554 /* Check whether an invalid uart number has been specified */
498 .line = 0, 555 if (co->index < 0 || co->index >= BFIN_SPORT_UART_MAX_PORTS)
499 }, 556 return -ENODEV;
500 }, { /* SPORT 1 */ 557
501 .name = "SPORT1", 558 up = bfin_sport_uart_ports[co->index];
502 .tx_irq = IRQ_SPORT1_TX, 559 if (!up)
503 .rx_irq = IRQ_SPORT1_RX, 560 return -ENODEV;
504 .err_irq= IRQ_SPORT1_ERROR, 561
505 .port = { 562 if (options)
506 .type = PORT_BFIN_SPORT, 563 uart_parse_options(options, &baud, &parity, &bits, &flow);
507 .iotype = UPIO_MEM, 564
508 .membase = (void __iomem *)SPORT1_TCR1, 565 return uart_set_options(&up->port, co, baud, parity, bits, flow);
509 .mapbase = SPORT1_TCR1, 566}
510 .irq = IRQ_SPORT1_RX, 567
511 .uartclk = CONFIG_SPORT_BAUD_RATE, 568static void sport_uart_console_putchar(struct uart_port *port, int ch)
512 .fifosize = 8, 569{
513 .ops = &sport_uart_ops, 570 struct sport_uart_port *up = (struct sport_uart_port *)port;
514 .line = 1, 571
515 }, 572 while (SPORT_GET_STAT(up) & TXF)
573 barrier();
574
575 tx_one_byte(up, ch);
576}
577
578/*
579 * Interrupts are disabled on entering
580 */
581static void
582sport_uart_console_write(struct console *co, const char *s, unsigned int count)
583{
584 struct sport_uart_port *up = bfin_sport_uart_ports[co->index];
585 unsigned long flags;
586
587 spin_lock_irqsave(&up->port.lock, flags);
588
589 if (SPORT_GET_TCR1(up) & TSPEN)
590 uart_console_write(&up->port, s, count, sport_uart_console_putchar);
591 else {
592 /* dummy data to start sport */
593 while (SPORT_GET_STAT(up) & TXF)
594 barrier();
595 SPORT_PUT_TX(up, 0xffff);
596 /* Enable transmit, then an interrupt will generated */
597 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
598 SSYNC();
599
600 uart_console_write(&up->port, s, count, sport_uart_console_putchar);
601
602 /* Although the hold register is empty, last byte is still in shift
603 * register and not sent out yet. So, put a dummy data into TX FIFO.
604 * Then, sport tx stops when last byte is shift out and the dummy
605 * data is moved into the shift register.
606 */
607 while (SPORT_GET_STAT(up) & TXF)
608 barrier();
609 SPORT_PUT_TX(up, 0xffff);
610 while (!(SPORT_GET_STAT(up) & TXHRE))
611 barrier();
612
613 /* Stop sport tx transfer */
614 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
615 SSYNC();
516 } 616 }
617
618 spin_unlock_irqrestore(&up->port.lock, flags);
619}
620
621static struct uart_driver sport_uart_reg;
622
623static struct console sport_uart_console = {
624 .name = DEVICE_NAME,
625 .write = sport_uart_console_write,
626 .device = uart_console_device,
627 .setup = sport_uart_console_setup,
628 .flags = CON_PRINTBUFFER,
629 .index = -1,
630 .data = &sport_uart_reg,
517}; 631};
518 632
633#define SPORT_UART_CONSOLE (&sport_uart_console)
634#else
635#define SPORT_UART_CONSOLE NULL
636#endif /* CONFIG_SERIAL_BFIN_SPORT_CONSOLE */
637
638
519static struct uart_driver sport_uart_reg = { 639static struct uart_driver sport_uart_reg = {
520 .owner = THIS_MODULE, 640 .owner = THIS_MODULE,
521 .driver_name = "SPORT-UART", 641 .driver_name = DRV_NAME,
522 .dev_name = "ttySS", 642 .dev_name = DEVICE_NAME,
523 .major = 204, 643 .major = 204,
524 .minor = 84, 644 .minor = 84,
525 .nr = ARRAY_SIZE(sport_uart_ports), 645 .nr = BFIN_SPORT_UART_MAX_PORTS,
526 .cons = NULL, 646 .cons = SPORT_UART_CONSOLE,
527}; 647};
528 648
529static int sport_uart_suspend(struct platform_device *dev, pm_message_t state) 649#ifdef CONFIG_PM
650static int sport_uart_suspend(struct device *dev)
530{ 651{
531 struct sport_uart_port *sport = platform_get_drvdata(dev); 652 struct sport_uart_port *sport = dev_get_drvdata(dev);
532 653
533 pr_debug("%s enter\n", __func__); 654 dev_dbg(dev, "%s enter\n", __func__);
534 if (sport) 655 if (sport)
535 uart_suspend_port(&sport_uart_reg, &sport->port); 656 uart_suspend_port(&sport_uart_reg, &sport->port);
536 657
537 return 0; 658 return 0;
538} 659}
539 660
540static int sport_uart_resume(struct platform_device *dev) 661static int sport_uart_resume(struct device *dev)
541{ 662{
542 struct sport_uart_port *sport = platform_get_drvdata(dev); 663 struct sport_uart_port *sport = dev_get_drvdata(dev);
543 664
544 pr_debug("%s enter\n", __func__); 665 dev_dbg(dev, "%s enter\n", __func__);
545 if (sport) 666 if (sport)
546 uart_resume_port(&sport_uart_reg, &sport->port); 667 uart_resume_port(&sport_uart_reg, &sport->port);
547 668
548 return 0; 669 return 0;
549} 670}
550 671
551static int sport_uart_probe(struct platform_device *dev) 672static struct dev_pm_ops bfin_sport_uart_dev_pm_ops = {
673 .suspend = sport_uart_suspend,
674 .resume = sport_uart_resume,
675};
676#endif
677
678static int __devinit sport_uart_probe(struct platform_device *pdev)
552{ 679{
553 pr_debug("%s enter\n", __func__); 680 struct resource *res;
554 sport_uart_ports[dev->id].port.dev = &dev->dev; 681 struct sport_uart_port *sport;
555 uart_add_one_port(&sport_uart_reg, &sport_uart_ports[dev->id].port); 682 int ret = 0;
556 platform_set_drvdata(dev, &sport_uart_ports[dev->id]);
557 683
558 return 0; 684 dev_dbg(&pdev->dev, "%s enter\n", __func__);
685
686 if (pdev->id < 0 || pdev->id >= BFIN_SPORT_UART_MAX_PORTS) {
687 dev_err(&pdev->dev, "Wrong sport uart platform device id.\n");
688 return -ENOENT;
689 }
690
691 if (bfin_sport_uart_ports[pdev->id] == NULL) {
692 bfin_sport_uart_ports[pdev->id] =
693 kmalloc(sizeof(struct sport_uart_port), GFP_KERNEL);
694 sport = bfin_sport_uart_ports[pdev->id];
695 if (!sport) {
696 dev_err(&pdev->dev,
697 "Fail to kmalloc sport_uart_port\n");
698 return -ENOMEM;
699 }
700
701 ret = peripheral_request_list(
702 (unsigned short *)pdev->dev.platform_data, DRV_NAME);
703 if (ret) {
704 dev_err(&pdev->dev,
705 "Fail to request SPORT peripherals\n");
706 goto out_error_free_mem;
707 }
708
709 spin_lock_init(&sport->port.lock);
710 sport->port.fifosize = SPORT_TX_FIFO_SIZE,
711 sport->port.ops = &sport_uart_ops;
712 sport->port.line = pdev->id;
713 sport->port.iotype = UPIO_MEM;
714 sport->port.flags = UPF_BOOT_AUTOCONF;
715
716 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
717 if (res == NULL) {
718 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
719 ret = -ENOENT;
720 goto out_error_free_peripherals;
721 }
722
723 sport->port.membase = ioremap(res->start,
724 res->end - res->start);
725 if (!sport->port.membase) {
726 dev_err(&pdev->dev, "Cannot map sport IO\n");
727 ret = -ENXIO;
728 goto out_error_free_peripherals;
729 }
730
731 sport->port.irq = platform_get_irq(pdev, 0);
732 if (sport->port.irq < 0) {
733 dev_err(&pdev->dev, "No sport RX/TX IRQ specified\n");
734 ret = -ENOENT;
735 goto out_error_unmap;
736 }
737
738 sport->err_irq = platform_get_irq(pdev, 1);
739 if (sport->err_irq < 0) {
740 dev_err(&pdev->dev, "No sport status IRQ specified\n");
741 ret = -ENOENT;
742 goto out_error_unmap;
743 }
744 }
745
746#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
747 if (!is_early_platform_device(pdev)) {
748#endif
749 sport = bfin_sport_uart_ports[pdev->id];
750 sport->port.dev = &pdev->dev;
751 dev_set_drvdata(&pdev->dev, sport);
752 ret = uart_add_one_port(&sport_uart_reg, &sport->port);
753#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
754 }
755#endif
756 if (!ret)
757 return 0;
758
759 if (sport) {
760out_error_unmap:
761 iounmap(sport->port.membase);
762out_error_free_peripherals:
763 peripheral_free_list(
764 (unsigned short *)pdev->dev.platform_data);
765out_error_free_mem:
766 kfree(sport);
767 bfin_sport_uart_ports[pdev->id] = NULL;
768 }
769
770 return ret;
559} 771}
560 772
561static int sport_uart_remove(struct platform_device *dev) 773static int __devexit sport_uart_remove(struct platform_device *pdev)
562{ 774{
563 struct sport_uart_port *sport = platform_get_drvdata(dev); 775 struct sport_uart_port *sport = platform_get_drvdata(pdev);
564 776
565 pr_debug("%s enter\n", __func__); 777 dev_dbg(&pdev->dev, "%s enter\n", __func__);
566 platform_set_drvdata(dev, NULL); 778 dev_set_drvdata(&pdev->dev, NULL);
567 779
568 if (sport) 780 if (sport) {
569 uart_remove_one_port(&sport_uart_reg, &sport->port); 781 uart_remove_one_port(&sport_uart_reg, &sport->port);
782 iounmap(sport->port.membase);
783 peripheral_free_list(
784 (unsigned short *)pdev->dev.platform_data);
785 kfree(sport);
786 bfin_sport_uart_ports[pdev->id] = NULL;
787 }
570 788
571 return 0; 789 return 0;
572} 790}
573 791
574static struct platform_driver sport_uart_driver = { 792static struct platform_driver sport_uart_driver = {
575 .probe = sport_uart_probe, 793 .probe = sport_uart_probe,
576 .remove = sport_uart_remove, 794 .remove = __devexit_p(sport_uart_remove),
577 .suspend = sport_uart_suspend,
578 .resume = sport_uart_resume,
579 .driver = { 795 .driver = {
580 .name = DRV_NAME, 796 .name = DRV_NAME,
797#ifdef CONFIG_PM
798 .pm = &bfin_sport_uart_dev_pm_ops,
799#endif
581 }, 800 },
582}; 801};
583 802
803#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
804static __initdata struct early_platform_driver early_sport_uart_driver = {
805 .class_str = DRV_NAME,
806 .pdrv = &sport_uart_driver,
807 .requested_id = EARLY_PLATFORM_ID_UNSET,
808};
809
810static int __init sport_uart_rs_console_init(void)
811{
812 early_platform_driver_register(&early_sport_uart_driver, DRV_NAME);
813
814 early_platform_driver_probe(DRV_NAME, BFIN_SPORT_UART_MAX_PORTS, 0);
815
816 register_console(&sport_uart_console);
817
818 return 0;
819}
820console_initcall(sport_uart_rs_console_init);
821#endif
822
584static int __init sport_uart_init(void) 823static int __init sport_uart_init(void)
585{ 824{
586 int ret; 825 int ret;
587 826
588 pr_debug("%s enter\n", __func__); 827 pr_info("Serial: Blackfin uart over sport driver\n");
828
589 ret = uart_register_driver(&sport_uart_reg); 829 ret = uart_register_driver(&sport_uart_reg);
590 if (ret != 0) { 830 if (ret) {
591 printk(KERN_ERR "Failed to register %s:%d\n", 831 pr_err("failed to register %s:%d\n",
592 sport_uart_reg.driver_name, ret); 832 sport_uart_reg.driver_name, ret);
593 return ret; 833 return ret;
594 } 834 }
595 835
596 ret = platform_driver_register(&sport_uart_driver); 836 ret = platform_driver_register(&sport_uart_driver);
597 if (ret != 0) { 837 if (ret) {
598 printk(KERN_ERR "Failed to register sport uart driver:%d\n", ret); 838 pr_err("failed to register sport uart driver:%d\n", ret);
599 uart_unregister_driver(&sport_uart_reg); 839 uart_unregister_driver(&sport_uart_reg);
600 } 840 }
601 841
602
603 pr_debug("%s exit\n", __func__);
604 return ret; 842 return ret;
605} 843}
844module_init(sport_uart_init);
606 845
607static void __exit sport_uart_exit(void) 846static void __exit sport_uart_exit(void)
608{ 847{
609 pr_debug("%s enter\n", __func__);
610 platform_driver_unregister(&sport_uart_driver); 848 platform_driver_unregister(&sport_uart_driver);
611 uart_unregister_driver(&sport_uart_reg); 849 uart_unregister_driver(&sport_uart_reg);
612} 850}
613
614module_init(sport_uart_init);
615module_exit(sport_uart_exit); 851module_exit(sport_uart_exit);
616 852
853MODULE_AUTHOR("Sonic Zhang, Roy Huang");
854MODULE_DESCRIPTION("Blackfin serial over SPORT driver");
617MODULE_LICENSE("GPL"); 855MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-19 23:07:29 -0400