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-rw-r--r--drivers/net/wireless/rtlwifi/Kconfig15
-rw-r--r--drivers/net/wireless/rtlwifi/Makefile1
-rw-r--r--drivers/net/wireless/rtlwifi/pci.c23
-rw-r--r--drivers/net/wireless/rtlwifi/pci.h11
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/reg.h2
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/sw.c20
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/Makefile14
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/def.h269
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/dm.c1355
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/dm.h212
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/fw.c790
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/fw.h155
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/hw.c2326
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/hw.h66
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/led.c159
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/led.h38
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/phy.c3837
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/phy.h178
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/reg.h1313
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/rf.c628
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/rf.h44
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/sw.c423
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/sw.h37
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/table.c1690
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/table.h57
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/trx.c959
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/trx.h756
-rw-r--r--drivers/net/wireless/rtlwifi/wifi.h3
28 files changed, 15359 insertions, 22 deletions
diff --git a/drivers/net/wireless/rtlwifi/Kconfig b/drivers/net/wireless/rtlwifi/Kconfig
index 5aee8b22d74e..45e14760c16e 100644
--- a/drivers/net/wireless/rtlwifi/Kconfig
+++ b/drivers/net/wireless/rtlwifi/Kconfig
@@ -21,6 +21,17 @@ config RTL8192SE
21 21
22 If you choose to build it as a module, it will be called rtl8192se 22 If you choose to build it as a module, it will be called rtl8192se
23 23
24config RTL8192DE
25 tristate "Realtek RTL8192DE/RTL8188DE PCIe Wireless Network Adapter"
26 depends on MAC80211 && EXPERIMENTAL
27 select FW_LOADER
28 select RTLWIFI
29 ---help---
30 This is the driver for Realtek RTL8192DE/RTL8188DE 802.11n PCIe
31 wireless network adapters.
32
33 If you choose to build it as a module, it will be called rtl8192de
34
24config RTL8192CU 35config RTL8192CU
25 tristate "Realtek RTL8192CU/RTL8188CU USB Wireless Network Adapter" 36 tristate "Realtek RTL8192CU/RTL8188CU USB Wireless Network Adapter"
26 depends on MAC80211 && USB && EXPERIMENTAL 37 depends on MAC80211 && USB && EXPERIMENTAL
@@ -35,10 +46,10 @@ config RTL8192CU
35 46
36config RTLWIFI 47config RTLWIFI
37 tristate 48 tristate
38 depends on RTL8192CE || RTL8192CU || RTL8192SE 49 depends on RTL8192CE || RTL8192CU || RTL8192SE || RTL8192DE
39 default m 50 default m
40 51
41config RTL8192C_COMMON 52config RTL8192C_COMMON
42 tristate 53 tristate
43 depends on RTL8192CE || RTL8192CU || RTL8192SE 54 depends on RTL8192CE || RTL8192CU
44 default m 55 default m
diff --git a/drivers/net/wireless/rtlwifi/Makefile b/drivers/net/wireless/rtlwifi/Makefile
index 7acce83c3785..97935c565bab 100644
--- a/drivers/net/wireless/rtlwifi/Makefile
+++ b/drivers/net/wireless/rtlwifi/Makefile
@@ -23,5 +23,6 @@ obj-$(CONFIG_RTL8192C_COMMON) += rtl8192c/
23obj-$(CONFIG_RTL8192CE) += rtl8192ce/ 23obj-$(CONFIG_RTL8192CE) += rtl8192ce/
24obj-$(CONFIG_RTL8192CU) += rtl8192cu/ 24obj-$(CONFIG_RTL8192CU) += rtl8192cu/
25obj-$(CONFIG_RTL8192SE) += rtl8192se/ 25obj-$(CONFIG_RTL8192SE) += rtl8192se/
26obj-$(CONFIG_RTL8192DE) += rtl8192de/
26 27
27ccflags-y += -D__CHECK_ENDIAN__ 28ccflags-y += -D__CHECK_ENDIAN__
diff --git a/drivers/net/wireless/rtlwifi/pci.c b/drivers/net/wireless/rtlwifi/pci.c
index ad39af462f87..532c7d38dae2 100644
--- a/drivers/net/wireless/rtlwifi/pci.c
+++ b/drivers/net/wireless/rtlwifi/pci.c
@@ -35,10 +35,10 @@
35#include "efuse.h" 35#include "efuse.h"
36 36
37static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = { 37static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
38 INTEL_VENDOR_ID, 38 PCI_VENDOR_ID_INTEL,
39 ATI_VENDOR_ID, 39 PCI_VENDOR_ID_ATI,
40 AMD_VENDOR_ID, 40 PCI_VENDOR_ID_AMD,
41 SIS_VENDOR_ID 41 PCI_VENDOR_ID_SI
42}; 42};
43 43
44static const u8 ac_to_hwq[] = { 44static const u8 ac_to_hwq[] = {
@@ -390,7 +390,7 @@ static void rtl_pci_parse_configuration(struct pci_dev *pdev,
390 u8 linkctrl_reg; 390 u8 linkctrl_reg;
391 391
392 /*Link Control Register */ 392 /*Link Control Register */
393 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); 393 pos = pci_pcie_cap(pdev);
394 pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &linkctrl_reg); 394 pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &linkctrl_reg);
395 pcipriv->ndis_adapter.linkctrl_reg = linkctrl_reg; 395 pcipriv->ndis_adapter.linkctrl_reg = linkctrl_reg;
396 396
@@ -1615,6 +1615,16 @@ static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1615 pci_read_config_byte(pdev, 0x8, &revisionid); 1615 pci_read_config_byte(pdev, 0x8, &revisionid);
1616 pci_read_config_word(pdev, 0x3C, &irqline); 1616 pci_read_config_word(pdev, 0x3C, &irqline);
1617 1617
1618 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses
1619 * r8192e_pci, and RTL8192SE, which uses this driver. If the
1620 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then
1621 * the correct driver is r8192e_pci, thus this routine should
1622 * return false.
1623 */
1624 if (deviceid == RTL_PCI_8192SE_DID &&
1625 revisionid == RTL_PCI_REVISION_ID_8192PCIE)
1626 return false;
1627
1618 if (deviceid == RTL_PCI_8192_DID || 1628 if (deviceid == RTL_PCI_8192_DID ||
1619 deviceid == RTL_PCI_0044_DID || 1629 deviceid == RTL_PCI_0044_DID ||
1620 deviceid == RTL_PCI_0047_DID || 1630 deviceid == RTL_PCI_0047_DID ||
@@ -1847,7 +1857,8 @@ int __devinit rtl_pci_probe(struct pci_dev *pdev,
1847 pci_write_config_byte(pdev, 0x04, 0x07); 1857 pci_write_config_byte(pdev, 0x04, 0x07);
1848 1858
1849 /* find adapter */ 1859 /* find adapter */
1850 _rtl_pci_find_adapter(pdev, hw); 1860 if (!_rtl_pci_find_adapter(pdev, hw))
1861 goto fail3;
1851 1862
1852 /* Init IO handler */ 1863 /* Init IO handler */
1853 _rtl_pci_io_handler_init(&pdev->dev, hw); 1864 _rtl_pci_io_handler_init(&pdev->dev, hw);
diff --git a/drivers/net/wireless/rtlwifi/pci.h b/drivers/net/wireless/rtlwifi/pci.h
index 671b1f5aa0cf..a50e5513256e 100644
--- a/drivers/net/wireless/rtlwifi/pci.h
+++ b/drivers/net/wireless/rtlwifi/pci.h
@@ -62,12 +62,6 @@
62 .subdevice = PCI_ANY_ID,\ 62 .subdevice = PCI_ANY_ID,\
63 .driver_data = (kernel_ulong_t)&(cfg) 63 .driver_data = (kernel_ulong_t)&(cfg)
64 64
65#define INTEL_VENDOR_ID 0x8086
66#define SIS_VENDOR_ID 0x1039
67#define ATI_VENDOR_ID 0x1002
68#define ATI_DEVICE_ID 0x7914
69#define AMD_VENDOR_ID 0x1022
70
71#define PCI_MAX_BRIDGE_NUMBER 255 65#define PCI_MAX_BRIDGE_NUMBER 255
72#define PCI_MAX_DEVICES 32 66#define PCI_MAX_DEVICES 32
73#define PCI_MAX_FUNCTION 8 67#define PCI_MAX_FUNCTION 8
@@ -75,11 +69,6 @@
75#define PCI_CONF_ADDRESS 0x0CF8 /*PCI Configuration Space Address */ 69#define PCI_CONF_ADDRESS 0x0CF8 /*PCI Configuration Space Address */
76#define PCI_CONF_DATA 0x0CFC /*PCI Configuration Space Data */ 70#define PCI_CONF_DATA 0x0CFC /*PCI Configuration Space Data */
77 71
78#define PCI_CLASS_BRIDGE_DEV 0x06
79#define PCI_SUBCLASS_BR_PCI_TO_PCI 0x04
80#define PCI_CAPABILITY_ID_PCI_EXPRESS 0x10
81#define PCI_CAP_ID_EXP 0x10
82
83#define U1DONTCARE 0xFF 72#define U1DONTCARE 0xFF
84#define U2DONTCARE 0xFFFF 73#define U2DONTCARE 0xFFFF
85#define U4DONTCARE 0xFFFFFFFF 74#define U4DONTCARE 0xFFFFFFFF
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/reg.h b/drivers/net/wireless/rtlwifi/rtl8192ce/reg.h
index 598cecc63f41..72a3d5497547 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192ce/reg.h
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/reg.h
@@ -1203,7 +1203,9 @@
1203#define EPROM_CMD_CONFIG 0x3 1203#define EPROM_CMD_CONFIG 0x3
1204#define EPROM_CMD_LOAD 1 1204#define EPROM_CMD_LOAD 1
1205 1205
1206#define HWSET_MAX_SIZE 128
1206#define HWSET_MAX_SIZE_92S HWSET_MAX_SIZE 1207#define HWSET_MAX_SIZE_92S HWSET_MAX_SIZE
1208#define EFUSE_MAX_SECTION 16
1207 1209
1208#define WL_HWPDN_EN BIT(0) 1210#define WL_HWPDN_EN BIT(0)
1209 1211
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c b/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c
index bee7c1480f63..092e342c19df 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c
@@ -53,6 +53,8 @@ MODULE_FIRMWARE("rtlwifi/rtl8192cufw.bin");
53static int rtl92cu_init_sw_vars(struct ieee80211_hw *hw) 53static int rtl92cu_init_sw_vars(struct ieee80211_hw *hw)
54{ 54{
55 struct rtl_priv *rtlpriv = rtl_priv(hw); 55 struct rtl_priv *rtlpriv = rtl_priv(hw);
56 const struct firmware *firmware;
57 int err;
56 58
57 rtlpriv->dm.dm_initialgain_enable = 1; 59 rtlpriv->dm.dm_initialgain_enable = 1;
58 rtlpriv->dm.dm_flag = 0; 60 rtlpriv->dm.dm_flag = 0;
@@ -64,6 +66,24 @@ static int rtl92cu_init_sw_vars(struct ieee80211_hw *hw)
64 ("Can't alloc buffer for fw.\n")); 66 ("Can't alloc buffer for fw.\n"));
65 return 1; 67 return 1;
66 } 68 }
69 /* request fw */
70 err = request_firmware(&firmware, rtlpriv->cfg->fw_name,
71 rtlpriv->io.dev);
72 if (err) {
73 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
74 ("Failed to request firmware!\n"));
75 return 1;
76 }
77 if (firmware->size > 0x4000) {
78 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
79 ("Firmware is too big!\n"));
80 release_firmware(firmware);
81 return 1;
82 }
83 memcpy(rtlpriv->rtlhal.pfirmware, firmware->data, firmware->size);
84 rtlpriv->rtlhal.fwsize = firmware->size;
85 release_firmware(firmware);
86
67 return 0; 87 return 0;
68} 88}
69 89
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/Makefile b/drivers/net/wireless/rtlwifi/rtl8192de/Makefile
new file mode 100644
index 000000000000..e3213c8264b6
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/Makefile
@@ -0,0 +1,14 @@
1rtl8192de-objs := \
2 dm.o \
3 fw.o \
4 hw.o \
5 led.o \
6 phy.o \
7 rf.o \
8 sw.o \
9 table.o \
10 trx.o
11
12obj-$(CONFIG_RTL8192DE) += rtl8192de.o
13
14ccflags-y += -D__CHECK_ENDIAN__
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/def.h b/drivers/net/wireless/rtlwifi/rtl8192de/def.h
new file mode 100644
index 000000000000..f0f5f9bfbb7b
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/def.h
@@ -0,0 +1,269 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92D_DEF_H__
31#define __RTL92D_DEF_H__
32
33/* Min Spacing related settings. */
34#define MAX_MSS_DENSITY_2T 0x13
35#define MAX_MSS_DENSITY_1T 0x0A
36
37#define RF6052_MAX_TX_PWR 0x3F
38#define RF6052_MAX_REG 0x3F
39#define RF6052_MAX_PATH 2
40
41#define HAL_RETRY_LIMIT_INFRA 48
42#define HAL_RETRY_LIMIT_AP_ADHOC 7
43
44#define PHY_RSSI_SLID_WIN_MAX 100
45#define PHY_LINKQUALITY_SLID_WIN_MAX 20
46#define PHY_BEACON_RSSI_SLID_WIN_MAX 10
47
48#define RESET_DELAY_8185 20
49
50#define RT_IBSS_INT_MASKS (IMR_BCNINT | IMR_TBDOK | IMR_TBDER)
51#define RT_AC_INT_MASKS (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
52
53#define NUM_OF_FIRMWARE_QUEUE 10
54#define NUM_OF_PAGES_IN_FW 0x100
55#define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x07
56#define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x07
57#define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x07
58#define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x07
59#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0x0
60#define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x0
61#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x02
62#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0x02
63#define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x2
64#define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0xA1
65
66#define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM 0x026
67#define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM 0x048
68#define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM 0x048
69#define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM 0x026
70#define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM 0x00
71
72#define MAX_LINES_HWCONFIG_TXT 1000
73#define MAX_BYTES_LINE_HWCONFIG_TXT 256
74
75#define SW_THREE_WIRE 0
76#define HW_THREE_WIRE 2
77
78#define BT_DEMO_BOARD 0
79#define BT_QA_BOARD 1
80#define BT_FPGA 2
81
82#define RX_SMOOTH_FACTOR 20
83
84#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
85#define HAL_PRIME_CHNL_OFFSET_LOWER 1
86#define HAL_PRIME_CHNL_OFFSET_UPPER 2
87
88#define MAX_H2C_QUEUE_NUM 10
89
90#define RX_MPDU_QUEUE 0
91#define RX_CMD_QUEUE 1
92#define RX_MAX_QUEUE 2
93
94#define C2H_RX_CMD_HDR_LEN 8
95#define GET_C2H_CMD_CMD_LEN(__prxhdr) \
96 LE_BITS_TO_4BYTE((__prxhdr), 0, 16)
97#define GET_C2H_CMD_ELEMENT_ID(__prxhdr) \
98 LE_BITS_TO_4BYTE((__prxhdr), 16, 8)
99#define GET_C2H_CMD_CMD_SEQ(__prxhdr) \
100 LE_BITS_TO_4BYTE((__prxhdr), 24, 7)
101#define GET_C2H_CMD_CONTINUE(__prxhdr) \
102 LE_BITS_TO_4BYTE((__prxhdr), 31, 1)
103#define GET_C2H_CMD_CONTENT(__prxhdr) \
104 ((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN)
105
106#define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr) \
107 LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8)
108#define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr) \
109 LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8)
110#define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr) \
111 LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16)
112#define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr) \
113 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5)
114#define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr) \
115 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1)
116#define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr) \
117 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5)
118#define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr) \
119 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1)
120#define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr) \
121 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4)
122#define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr) \
123 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)
124
125/*
126 * 92D chip ver:
127 * BIT8: IS 92D
128 * BIT9: single phy
129 * BIT10: C-cut
130 * BIT11: D-cut
131 */
132
133/* Chip specific */
134#define CHIP_92C BIT(0)
135#define CHIP_92C_1T2R BIT(1)
136#define CHIP_8723 BIT(2) /* RTL8723 With BT feature */
137#define CHIP_8723_DRV_REV BIT(3) /* RTL8723 Driver Revised */
138#define NORMAL_CHIP BIT(4)
139#define CHIP_VENDOR_UMC BIT(5)
140#define CHIP_VENDOR_UMC_B_CUT BIT(6) /* Chip version for ECO */
141
142/* for 92D */
143#define CHIP_92D BIT(8)
144#define CHIP_92D_SINGLEPHY BIT(9)
145#define CHIP_92D_C_CUT BIT(10)
146#define CHIP_92D_D_CUT BIT(11)
147
148enum version_8192d {
149 VERSION_TEST_CHIP_88C = 0x00,
150 VERSION_TEST_CHIP_92C = 0x01,
151 VERSION_NORMAL_TSMC_CHIP_88C = 0x10,
152 VERSION_NORMAL_TSMC_CHIP_92C = 0x11,
153 VERSION_NORMAL_TSMC_CHIP_92C_1T2R = 0x13,
154 VERSION_NORMAL_UMC_CHIP_88C_A_CUT = 0x30,
155 VERSION_NORMAL_UMC_CHIP_92C_A_CUT = 0x31,
156 VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT = 0x33,
157 VERSION_NORMA_UMC_CHIP_8723_1T1R_A_CUT = 0x34,
158 VERSION_NORMA_UMC_CHIP_8723_1T1R_B_CUT = 0x3c,
159 VERSION_NORMAL_UMC_CHIP_88C_B_CUT = 0x70,
160 VERSION_NORMAL_UMC_CHIP_92C_B_CUT = 0x71,
161 VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT = 0x73,
162 VERSION_TEST_CHIP_92D_SINGLEPHY = 0x300,
163 VERSION_TEST_CHIP_92D_DUALPHY = 0x100,
164 VERSION_NORMAL_CHIP_92D_SINGLEPHY = 0x310,
165 VERSION_NORMAL_CHIP_92D_DUALPHY = 0x110,
166 VERSION_NORMAL_CHIP_92D_C_CUT_SINGLEPHY = 0x710,
167 VERSION_NORMAL_CHIP_92D_C_CUT_DUALPHY = 0x510,
168 VERSION_NORMAL_CHIP_92D_D_CUT_SINGLEPHY = 0xB10,
169 VERSION_NORMAL_CHIP_92D_D_CUT_DUALPHY = 0x910,
170};
171
172#define IS_92D_SINGLEPHY(version) \
173 ((version & CHIP_92D_SINGLEPHY) ? true : false)
174#define IS_92D_C_CUT(version) \
175 ((version & CHIP_92D_C_CUT) ? true : false)
176#define IS_92D_D_CUT(version) \
177 ((version & CHIP_92D_D_CUT) ? true : false)
178
179enum rf_optype {
180 RF_OP_BY_SW_3WIRE = 0,
181 RF_OP_BY_FW,
182 RF_OP_MAX
183};
184
185enum rtl_desc_qsel {
186 QSLT_BK = 0x2,
187 QSLT_BE = 0x0,
188 QSLT_VI = 0x5,
189 QSLT_VO = 0x7,
190 QSLT_BEACON = 0x10,
191 QSLT_HIGH = 0x11,
192 QSLT_MGNT = 0x12,
193 QSLT_CMD = 0x13,
194};
195
196enum rtl_desc92d_rate {
197 DESC92D_RATE1M = 0x00,
198 DESC92D_RATE2M = 0x01,
199 DESC92D_RATE5_5M = 0x02,
200 DESC92D_RATE11M = 0x03,
201
202 DESC92D_RATE6M = 0x04,
203 DESC92D_RATE9M = 0x05,
204 DESC92D_RATE12M = 0x06,
205 DESC92D_RATE18M = 0x07,
206 DESC92D_RATE24M = 0x08,
207 DESC92D_RATE36M = 0x09,
208 DESC92D_RATE48M = 0x0a,
209 DESC92D_RATE54M = 0x0b,
210
211 DESC92D_RATEMCS0 = 0x0c,
212 DESC92D_RATEMCS1 = 0x0d,
213 DESC92D_RATEMCS2 = 0x0e,
214 DESC92D_RATEMCS3 = 0x0f,
215 DESC92D_RATEMCS4 = 0x10,
216 DESC92D_RATEMCS5 = 0x11,
217 DESC92D_RATEMCS6 = 0x12,
218 DESC92D_RATEMCS7 = 0x13,
219 DESC92D_RATEMCS8 = 0x14,
220 DESC92D_RATEMCS9 = 0x15,
221 DESC92D_RATEMCS10 = 0x16,
222 DESC92D_RATEMCS11 = 0x17,
223 DESC92D_RATEMCS12 = 0x18,
224 DESC92D_RATEMCS13 = 0x19,
225 DESC92D_RATEMCS14 = 0x1a,
226 DESC92D_RATEMCS15 = 0x1b,
227 DESC92D_RATEMCS15_SG = 0x1c,
228 DESC92D_RATEMCS32 = 0x20,
229};
230
231enum channel_plan {
232 CHPL_FCC = 0,
233 CHPL_IC = 1,
234 CHPL_ETSI = 2,
235 CHPL_SPAIN = 3,
236 CHPL_FRANCE = 4,
237 CHPL_MKK = 5,
238 CHPL_MKK1 = 6,
239 CHPL_ISRAEL = 7,
240 CHPL_TELEC = 8,
241 CHPL_GLOBAL = 9,
242 CHPL_WORLD = 10,
243};
244
245struct phy_sts_cck_8192d {
246 u8 adc_pwdb_X[4];
247 u8 sq_rpt;
248 u8 cck_agc_rpt;
249};
250
251struct h2c_cmd_8192c {
252 u8 element_id;
253 u32 cmd_len;
254 u8 *p_cmdbuffer;
255};
256
257struct txpower_info {
258 u8 cck_index[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
259 u8 ht40_1sindex[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
260 u8 ht40_2sindexdiff[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
261 u8 ht20indexdiff[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
262 u8 ofdmindexdiff[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
263 u8 ht40maxoffset[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
264 u8 ht20maxoffset[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
265 u8 tssi_a[3]; /* 5GL/5GM/5GH */
266 u8 tssi_b[3];
267};
268
269#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/dm.c b/drivers/net/wireless/rtlwifi/rtl8192de/dm.c
new file mode 100644
index 000000000000..3cd0736fe8e1
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/dm.c
@@ -0,0 +1,1355 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../base.h"
32#include "reg.h"
33#include "def.h"
34#include "phy.h"
35#include "dm.h"
36#include "fw.h"
37
38#define UNDEC_SM_PWDB entry_min_undecoratedsmoothed_pwdb
39
40struct dig_t de_digtable;
41
42static const u32 ofdmswing_table[OFDM_TABLE_SIZE_92D] = {
43 0x7f8001fe, /* 0, +6.0dB */
44 0x788001e2, /* 1, +5.5dB */
45 0x71c001c7, /* 2, +5.0dB */
46 0x6b8001ae, /* 3, +4.5dB */
47 0x65400195, /* 4, +4.0dB */
48 0x5fc0017f, /* 5, +3.5dB */
49 0x5a400169, /* 6, +3.0dB */
50 0x55400155, /* 7, +2.5dB */
51 0x50800142, /* 8, +2.0dB */
52 0x4c000130, /* 9, +1.5dB */
53 0x47c0011f, /* 10, +1.0dB */
54 0x43c0010f, /* 11, +0.5dB */
55 0x40000100, /* 12, +0dB */
56 0x3c8000f2, /* 13, -0.5dB */
57 0x390000e4, /* 14, -1.0dB */
58 0x35c000d7, /* 15, -1.5dB */
59 0x32c000cb, /* 16, -2.0dB */
60 0x300000c0, /* 17, -2.5dB */
61 0x2d4000b5, /* 18, -3.0dB */
62 0x2ac000ab, /* 19, -3.5dB */
63 0x288000a2, /* 20, -4.0dB */
64 0x26000098, /* 21, -4.5dB */
65 0x24000090, /* 22, -5.0dB */
66 0x22000088, /* 23, -5.5dB */
67 0x20000080, /* 24, -6.0dB */
68 0x1e400079, /* 25, -6.5dB */
69 0x1c800072, /* 26, -7.0dB */
70 0x1b00006c, /* 27. -7.5dB */
71 0x19800066, /* 28, -8.0dB */
72 0x18000060, /* 29, -8.5dB */
73 0x16c0005b, /* 30, -9.0dB */
74 0x15800056, /* 31, -9.5dB */
75 0x14400051, /* 32, -10.0dB */
76 0x1300004c, /* 33, -10.5dB */
77 0x12000048, /* 34, -11.0dB */
78 0x11000044, /* 35, -11.5dB */
79 0x10000040, /* 36, -12.0dB */
80 0x0f00003c, /* 37, -12.5dB */
81 0x0e400039, /* 38, -13.0dB */
82 0x0d800036, /* 39, -13.5dB */
83 0x0cc00033, /* 40, -14.0dB */
84 0x0c000030, /* 41, -14.5dB */
85 0x0b40002d, /* 42, -15.0dB */
86};
87
88static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = {
89 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */
90 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */
91 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */
92 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */
93 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */
94 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */
95 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */
96 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */
97 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */
98 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */
99 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */
100 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */
101 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB */
102 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */
103 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */
104 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */
105 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
106 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */
107 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */
108 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */
109 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */
110 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */
111 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */
112 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */
113 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */
114 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */
115 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */
116 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */
117 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */
118 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */
119 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */
120 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */
121 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */
122};
123
124static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = {
125 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */
126 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */
127 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */
128 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */
129 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */
130 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */
131 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */
132 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */
133 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */
134 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */
135 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */
136 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */
137 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB */
138 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */
139 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */
140 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */
141 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
142 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */
143 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */
144 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */
145 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */
146 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */
147 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */
148 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */
149 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */
150 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */
151 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */
152 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */
153 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */
154 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */
155 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */
156 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */
157 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */
158};
159
160static void rtl92d_dm_diginit(struct ieee80211_hw *hw)
161{
162 de_digtable.dig_enable_flag = true;
163 de_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
164 de_digtable.cur_igvalue = 0x20;
165 de_digtable.pre_igvalue = 0x0;
166 de_digtable.cursta_connectctate = DIG_STA_DISCONNECT;
167 de_digtable.presta_connectstate = DIG_STA_DISCONNECT;
168 de_digtable.curmultista_connectstate = DIG_MULTISTA_DISCONNECT;
169 de_digtable.rssi_lowthresh = DM_DIG_THRESH_LOW;
170 de_digtable.rssi_highthresh = DM_DIG_THRESH_HIGH;
171 de_digtable.fa_lowthresh = DM_FALSEALARM_THRESH_LOW;
172 de_digtable.fa_highthresh = DM_FALSEALARM_THRESH_HIGH;
173 de_digtable.rx_gain_range_max = DM_DIG_FA_UPPER;
174 de_digtable.rx_gain_range_min = DM_DIG_FA_LOWER;
175 de_digtable.backoff_val = DM_DIG_BACKOFF_DEFAULT;
176 de_digtable.backoff_val_range_max = DM_DIG_BACKOFF_MAX;
177 de_digtable.backoff_val_range_min = DM_DIG_BACKOFF_MIN;
178 de_digtable.pre_cck_pd_state = CCK_PD_STAGE_LOWRSSI;
179 de_digtable.cur_cck_pd_state = CCK_PD_STAGE_MAX;
180 de_digtable.large_fa_hit = 0;
181 de_digtable.recover_cnt = 0;
182 de_digtable.forbidden_igi = DM_DIG_FA_LOWER;
183}
184
185static void rtl92d_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
186{
187 u32 ret_value;
188 struct rtl_priv *rtlpriv = rtl_priv(hw);
189 struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
190 unsigned long flag = 0;
191
192 /* hold ofdm counter */
193 rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 1); /* hold page C counter */
194 rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 1); /*hold page D counter */
195
196 ret_value = rtl_get_bbreg(hw, ROFDM0_FRAMESYNC, BMASKDWORD);
197 falsealm_cnt->cnt_fast_fsync_fail = (ret_value & 0xffff);
198 falsealm_cnt->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16);
199 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, BMASKDWORD);
200 falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
201 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, BMASKDWORD);
202 falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
203 falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
204 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, BMASKDWORD);
205 falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
206 falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
207 falsealm_cnt->cnt_rate_illegal +
208 falsealm_cnt->cnt_crc8_fail +
209 falsealm_cnt->cnt_mcs_fail +
210 falsealm_cnt->cnt_fast_fsync_fail +
211 falsealm_cnt->cnt_sb_search_fail;
212
213 if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G) {
214 /* hold cck counter */
215 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
216 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, BMASKBYTE0);
217 falsealm_cnt->cnt_cck_fail = ret_value;
218 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, BMASKBYTE3);
219 falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
220 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
221 } else {
222 falsealm_cnt->cnt_cck_fail = 0;
223 }
224
225 /* reset false alarm counter registers */
226 falsealm_cnt->cnt_all = falsealm_cnt->cnt_fast_fsync_fail +
227 falsealm_cnt->cnt_sb_search_fail +
228 falsealm_cnt->cnt_parity_fail +
229 falsealm_cnt->cnt_rate_illegal +
230 falsealm_cnt->cnt_crc8_fail +
231 falsealm_cnt->cnt_mcs_fail +
232 falsealm_cnt->cnt_cck_fail;
233
234 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1);
235 /* update ofdm counter */
236 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0);
237 /* update page C counter */
238 rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 0);
239 /* update page D counter */
240 rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 0);
241 if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G) {
242 /* reset cck counter */
243 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
244 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0);
245 /* enable cck counter */
246 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2);
247 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
248 }
249 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, ("Cnt_Fast_Fsync_fail = %x, "
250 "Cnt_SB_Search_fail = %x\n",
251 falsealm_cnt->cnt_fast_fsync_fail,
252 falsealm_cnt->cnt_sb_search_fail));
253 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, ("Cnt_Parity_Fail = %x, "
254 "Cnt_Rate_Illegal = %x, Cnt_Crc8_fail = %x, "
255 "Cnt_Mcs_fail = %x\n",
256 falsealm_cnt->cnt_parity_fail,
257 falsealm_cnt->cnt_rate_illegal,
258 falsealm_cnt->cnt_crc8_fail,
259 falsealm_cnt->cnt_mcs_fail));
260 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
261 ("Cnt_Ofdm_fail = %x, " "Cnt_Cck_fail = %x, "
262 "Cnt_all = %x\n",
263 falsealm_cnt->cnt_ofdm_fail,
264 falsealm_cnt->cnt_cck_fail,
265 falsealm_cnt->cnt_all));
266}
267
268static void rtl92d_dm_find_minimum_rssi(struct ieee80211_hw *hw)
269{
270 struct rtl_priv *rtlpriv = rtl_priv(hw);
271 struct rtl_mac *mac = rtl_mac(rtlpriv);
272
273 /* Determine the minimum RSSI */
274 if ((mac->link_state < MAC80211_LINKED) &&
275 (rtlpriv->dm.UNDEC_SM_PWDB == 0)) {
276 de_digtable.min_undecorated_pwdb_for_dm = 0;
277 RT_TRACE(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
278 ("Not connected to any\n"));
279 }
280 if (mac->link_state >= MAC80211_LINKED) {
281 if (mac->opmode == NL80211_IFTYPE_AP ||
282 mac->opmode == NL80211_IFTYPE_ADHOC) {
283 de_digtable.min_undecorated_pwdb_for_dm =
284 rtlpriv->dm.UNDEC_SM_PWDB;
285 RT_TRACE(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
286 ("AP Client PWDB = 0x%lx\n",
287 rtlpriv->dm.UNDEC_SM_PWDB));
288 } else {
289 de_digtable.min_undecorated_pwdb_for_dm =
290 rtlpriv->dm.undecorated_smoothed_pwdb;
291 RT_TRACE(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
292 ("STA Default Port PWDB = 0x%x\n",
293 de_digtable.min_undecorated_pwdb_for_dm));
294 }
295 } else {
296 de_digtable.min_undecorated_pwdb_for_dm =
297 rtlpriv->dm.UNDEC_SM_PWDB;
298 RT_TRACE(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
299 ("AP Ext Port or disconnet PWDB = 0x%x\n",
300 de_digtable.min_undecorated_pwdb_for_dm));
301 }
302
303 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, ("MinUndecoratedPWDBForDM =%d\n",
304 de_digtable.min_undecorated_pwdb_for_dm));
305}
306
307static void rtl92d_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
308{
309 struct rtl_priv *rtlpriv = rtl_priv(hw);
310 unsigned long flag = 0;
311
312 if (de_digtable.cursta_connectctate == DIG_STA_CONNECT) {
313 if (de_digtable.pre_cck_pd_state == CCK_PD_STAGE_LOWRSSI) {
314 if (de_digtable.min_undecorated_pwdb_for_dm <= 25)
315 de_digtable.cur_cck_pd_state =
316 CCK_PD_STAGE_LOWRSSI;
317 else
318 de_digtable.cur_cck_pd_state =
319 CCK_PD_STAGE_HIGHRSSI;
320 } else {
321 if (de_digtable.min_undecorated_pwdb_for_dm <= 20)
322 de_digtable.cur_cck_pd_state =
323 CCK_PD_STAGE_LOWRSSI;
324 else
325 de_digtable.cur_cck_pd_state =
326 CCK_PD_STAGE_HIGHRSSI;
327 }
328 } else {
329 de_digtable.cur_cck_pd_state = CCK_PD_STAGE_LOWRSSI;
330 }
331 if (de_digtable.pre_cck_pd_state != de_digtable.cur_cck_pd_state) {
332 if (de_digtable.cur_cck_pd_state == CCK_PD_STAGE_LOWRSSI) {
333 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
334 rtl_set_bbreg(hw, RCCK0_CCA, BMASKBYTE2, 0x83);
335 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
336 } else {
337 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
338 rtl_set_bbreg(hw, RCCK0_CCA, BMASKBYTE2, 0xcd);
339 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
340 }
341 de_digtable.pre_cck_pd_state = de_digtable.cur_cck_pd_state;
342 }
343 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, ("CurSTAConnectState=%s\n",
344 (de_digtable.cursta_connectctate == DIG_STA_CONNECT ?
345 "DIG_STA_CONNECT " : "DIG_STA_DISCONNECT")));
346 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, ("CCKPDStage=%s\n",
347 (de_digtable.cur_cck_pd_state == CCK_PD_STAGE_LOWRSSI ?
348 "Low RSSI " : "High RSSI ")));
349 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, ("is92d single phy =%x\n",
350 IS_92D_SINGLEPHY(rtlpriv->rtlhal.version)));
351
352}
353
354void rtl92d_dm_write_dig(struct ieee80211_hw *hw)
355{
356 struct rtl_priv *rtlpriv = rtl_priv(hw);
357
358 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, ("cur_igvalue = 0x%x, "
359 "pre_igvalue = 0x%x, backoff_val = %d\n",
360 de_digtable.cur_igvalue, de_digtable.pre_igvalue,
361 de_digtable.backoff_val));
362 if (de_digtable.dig_enable_flag == false) {
363 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, ("DIG is disabled\n"));
364 de_digtable.pre_igvalue = 0x17;
365 return;
366 }
367 if (de_digtable.pre_igvalue != de_digtable.cur_igvalue) {
368 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f,
369 de_digtable.cur_igvalue);
370 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f,
371 de_digtable.cur_igvalue);
372 de_digtable.pre_igvalue = de_digtable.cur_igvalue;
373 }
374}
375
376static void rtl92d_early_mode_enabled(struct rtl_priv *rtlpriv)
377{
378 if ((rtlpriv->mac80211.link_state >= MAC80211_LINKED) &&
379 (rtlpriv->mac80211.vendor == PEER_CISCO)) {
380 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
381 ("IOT_PEER = CISCO\n"));
382 if (de_digtable.last_min_undecorated_pwdb_for_dm >= 50
383 && de_digtable.min_undecorated_pwdb_for_dm < 50) {
384 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, 0x00);
385 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
386 ("Early Mode Off\n"));
387 } else if (de_digtable.last_min_undecorated_pwdb_for_dm <= 55 &&
388 de_digtable.min_undecorated_pwdb_for_dm > 55) {
389 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, 0x0f);
390 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
391 ("Early Mode On\n"));
392 }
393 } else if (!(rtl_read_byte(rtlpriv, REG_EARLY_MODE_CONTROL) & 0xf)) {
394 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, 0x0f);
395 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, ("Early Mode On\n"));
396 }
397}
398
399static void rtl92d_dm_dig(struct ieee80211_hw *hw)
400{
401 struct rtl_priv *rtlpriv = rtl_priv(hw);
402 u8 value_igi = de_digtable.cur_igvalue;
403 struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
404
405 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, ("==>\n"));
406 if (rtlpriv->rtlhal.earlymode_enable) {
407 rtl92d_early_mode_enabled(rtlpriv);
408 de_digtable.last_min_undecorated_pwdb_for_dm =
409 de_digtable.min_undecorated_pwdb_for_dm;
410 }
411 if (rtlpriv->dm.dm_initialgain_enable == false)
412 return;
413
414 /* because we will send data pkt when scanning
415 * this will cause some ap like gear-3700 wep TP
416 * lower if we retrun here, this is the diff of
417 * mac80211 driver vs ieee80211 driver */
418 /* if (rtlpriv->mac80211.act_scanning)
419 * return; */
420
421 /* Not STA mode return tmp */
422 if (rtlpriv->mac80211.opmode != NL80211_IFTYPE_STATION)
423 return;
424 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, ("progress\n"));
425 /* Decide the current status and if modify initial gain or not */
426 if (rtlpriv->mac80211.link_state >= MAC80211_LINKED)
427 de_digtable.cursta_connectctate = DIG_STA_CONNECT;
428 else
429 de_digtable.cursta_connectctate = DIG_STA_DISCONNECT;
430
431 /* adjust initial gain according to false alarm counter */
432 if (falsealm_cnt->cnt_all < DM_DIG_FA_TH0)
433 value_igi--;
434 else if (falsealm_cnt->cnt_all < DM_DIG_FA_TH1)
435 value_igi += 0;
436 else if (falsealm_cnt->cnt_all < DM_DIG_FA_TH2)
437 value_igi++;
438 else if (falsealm_cnt->cnt_all >= DM_DIG_FA_TH2)
439 value_igi += 2;
440 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
441 ("dm_DIG() Before: large_fa_hit=%d, forbidden_igi=%x\n",
442 de_digtable.large_fa_hit, de_digtable.forbidden_igi));
443 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
444 ("dm_DIG() Before: Recover_cnt=%d, rx_gain_range_min=%x\n",
445 de_digtable.recover_cnt, de_digtable.rx_gain_range_min));
446
447 /* deal with abnorally large false alarm */
448 if (falsealm_cnt->cnt_all > 10000) {
449 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
450 ("dm_DIG(): Abnornally false alarm case.\n"));
451
452 de_digtable.large_fa_hit++;
453 if (de_digtable.forbidden_igi < de_digtable.cur_igvalue) {
454 de_digtable.forbidden_igi = de_digtable.cur_igvalue;
455 de_digtable.large_fa_hit = 1;
456 }
457 if (de_digtable.large_fa_hit >= 3) {
458 if ((de_digtable.forbidden_igi + 1) > DM_DIG_MAX)
459 de_digtable.rx_gain_range_min = DM_DIG_MAX;
460 else
461 de_digtable.rx_gain_range_min =
462 (de_digtable.forbidden_igi + 1);
463 de_digtable.recover_cnt = 3600; /* 3600=2hr */
464 }
465 } else {
466 /* Recovery mechanism for IGI lower bound */
467 if (de_digtable.recover_cnt != 0) {
468 de_digtable.recover_cnt--;
469 } else {
470 if (de_digtable.large_fa_hit == 0) {
471 if ((de_digtable.forbidden_igi - 1) <
472 DM_DIG_FA_LOWER) {
473 de_digtable.forbidden_igi =
474 DM_DIG_FA_LOWER;
475 de_digtable.rx_gain_range_min =
476 DM_DIG_FA_LOWER;
477
478 } else {
479 de_digtable.forbidden_igi--;
480 de_digtable.rx_gain_range_min =
481 (de_digtable.forbidden_igi + 1);
482 }
483 } else if (de_digtable.large_fa_hit == 3) {
484 de_digtable.large_fa_hit = 0;
485 }
486 }
487 }
488 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
489 ("dm_DIG() After: large_fa_hit=%d, forbidden_igi=%x\n",
490 de_digtable.large_fa_hit, de_digtable.forbidden_igi));
491 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
492 ("dm_DIG() After: recover_cnt=%d, rx_gain_range_min=%x\n",
493 de_digtable.recover_cnt, de_digtable.rx_gain_range_min));
494
495 if (value_igi > DM_DIG_MAX)
496 value_igi = DM_DIG_MAX;
497 else if (value_igi < de_digtable.rx_gain_range_min)
498 value_igi = de_digtable.rx_gain_range_min;
499 de_digtable.cur_igvalue = value_igi;
500 rtl92d_dm_write_dig(hw);
501 if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G)
502 rtl92d_dm_cck_packet_detection_thresh(hw);
503 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, ("<<==\n"));
504}
505
506static void rtl92d_dm_init_dynamic_txpower(struct ieee80211_hw *hw)
507{
508 struct rtl_priv *rtlpriv = rtl_priv(hw);
509
510 rtlpriv->dm.dynamic_txpower_enable = true;
511 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
512 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
513}
514
515static void rtl92d_dm_dynamic_txpower(struct ieee80211_hw *hw)
516{
517 struct rtl_priv *rtlpriv = rtl_priv(hw);
518 struct rtl_phy *rtlphy = &(rtlpriv->phy);
519 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
520 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
521 long undecorated_smoothed_pwdb;
522
523 if ((!rtlpriv->dm.dynamic_txpower_enable)
524 || rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
525 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
526 return;
527 }
528 if ((mac->link_state < MAC80211_LINKED) &&
529 (rtlpriv->dm.UNDEC_SM_PWDB == 0)) {
530 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
531 ("Not connected to any\n"));
532 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
533 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
534 return;
535 }
536 if (mac->link_state >= MAC80211_LINKED) {
537 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
538 undecorated_smoothed_pwdb =
539 rtlpriv->dm.UNDEC_SM_PWDB;
540 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
541 ("IBSS Client PWDB = 0x%lx\n",
542 undecorated_smoothed_pwdb));
543 } else {
544 undecorated_smoothed_pwdb =
545 rtlpriv->dm.undecorated_smoothed_pwdb;
546 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
547 ("STA Default Port PWDB = 0x%lx\n",
548 undecorated_smoothed_pwdb));
549 }
550 } else {
551 undecorated_smoothed_pwdb =
552 rtlpriv->dm.UNDEC_SM_PWDB;
553
554 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
555 ("AP Ext Port PWDB = 0x%lx\n",
556 undecorated_smoothed_pwdb));
557 }
558 if (rtlhal->current_bandtype == BAND_ON_5G) {
559 if (undecorated_smoothed_pwdb >= 0x33) {
560 rtlpriv->dm.dynamic_txhighpower_lvl =
561 TXHIGHPWRLEVEL_LEVEL2;
562 RT_TRACE(rtlpriv, COMP_HIPWR, DBG_LOUD,
563 ("5G:TxHighPwrLevel_Level2 (TxPwr=0x0)\n"));
564 } else if ((undecorated_smoothed_pwdb < 0x33)
565 && (undecorated_smoothed_pwdb >= 0x2b)) {
566 rtlpriv->dm.dynamic_txhighpower_lvl =
567 TXHIGHPWRLEVEL_LEVEL1;
568 RT_TRACE(rtlpriv, COMP_HIPWR, DBG_LOUD,
569 ("5G:TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
570 } else if (undecorated_smoothed_pwdb < 0x2b) {
571 rtlpriv->dm.dynamic_txhighpower_lvl =
572 TXHIGHPWRLEVEL_NORMAL;
573 RT_TRACE(rtlpriv, COMP_HIPWR, DBG_LOUD,
574 ("5G:TxHighPwrLevel_Normal\n"));
575 }
576 } else {
577 if (undecorated_smoothed_pwdb >=
578 TX_POWER_NEAR_FIELD_THRESH_LVL2) {
579 rtlpriv->dm.dynamic_txhighpower_lvl =
580 TXHIGHPWRLEVEL_LEVEL2;
581 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
582 ("TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n"));
583 } else
584 if ((undecorated_smoothed_pwdb <
585 (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3))
586 && (undecorated_smoothed_pwdb >=
587 TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
588
589 rtlpriv->dm.dynamic_txhighpower_lvl =
590 TXHIGHPWRLEVEL_LEVEL1;
591 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
592 ("TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x10)\n"));
593 } else if (undecorated_smoothed_pwdb <
594 (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
595 rtlpriv->dm.dynamic_txhighpower_lvl =
596 TXHIGHPWRLEVEL_NORMAL;
597 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
598 ("TXHIGHPWRLEVEL_NORMAL\n"));
599 }
600 }
601 if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl)) {
602 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
603 ("PHY_SetTxPowerLevel8192S() Channel = %d\n",
604 rtlphy->current_channel));
605 rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel);
606 }
607 rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
608}
609
610static void rtl92d_dm_pwdb_monitor(struct ieee80211_hw *hw)
611{
612 struct rtl_priv *rtlpriv = rtl_priv(hw);
613
614 /* AP & ADHOC & MESH will return tmp */
615 if (rtlpriv->mac80211.opmode != NL80211_IFTYPE_STATION)
616 return;
617 /* Indicate Rx signal strength to FW. */
618 if (rtlpriv->dm.useramask) {
619 u32 temp = rtlpriv->dm.undecorated_smoothed_pwdb;
620
621 temp <<= 16;
622 temp |= 0x100;
623 /* fw v12 cmdid 5:use max macid ,for nic ,
624 * default macid is 0 ,max macid is 1 */
625 rtl92d_fill_h2c_cmd(hw, H2C_RSSI_REPORT, 3, (u8 *) (&temp));
626 } else {
627 rtl_write_byte(rtlpriv, 0x4fe,
628 (u8) rtlpriv->dm.undecorated_smoothed_pwdb);
629 }
630}
631
632void rtl92d_dm_init_edca_turbo(struct ieee80211_hw *hw)
633{
634 struct rtl_priv *rtlpriv = rtl_priv(hw);
635
636 rtlpriv->dm.current_turbo_edca = false;
637 rtlpriv->dm.is_any_nonbepkts = false;
638 rtlpriv->dm.is_cur_rdlstate = false;
639}
640
641static void rtl92d_dm_check_edca_turbo(struct ieee80211_hw *hw)
642{
643 struct rtl_priv *rtlpriv = rtl_priv(hw);
644 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
645 static u64 last_txok_cnt;
646 static u64 last_rxok_cnt;
647 u64 cur_txok_cnt;
648 u64 cur_rxok_cnt;
649 u32 edca_be_ul = 0x5ea42b;
650 u32 edca_be_dl = 0x5ea42b;
651
652 if (mac->link_state != MAC80211_LINKED) {
653 rtlpriv->dm.current_turbo_edca = false;
654 goto exit;
655 }
656
657 /* Enable BEQ TxOP limit configuration in wireless G-mode. */
658 /* To check whether we shall force turn on TXOP configuration. */
659 if ((!rtlpriv->dm.disable_framebursting) &&
660 (rtlpriv->sec.pairwise_enc_algorithm == WEP40_ENCRYPTION ||
661 rtlpriv->sec.pairwise_enc_algorithm == WEP104_ENCRYPTION ||
662 rtlpriv->sec.pairwise_enc_algorithm == TKIP_ENCRYPTION)) {
663 /* Force TxOP limit to 0x005e for UL. */
664 if (!(edca_be_ul & 0xffff0000))
665 edca_be_ul |= 0x005e0000;
666 /* Force TxOP limit to 0x005e for DL. */
667 if (!(edca_be_dl & 0xffff0000))
668 edca_be_dl |= 0x005e0000;
669 }
670
671 if ((!rtlpriv->dm.is_any_nonbepkts) &&
672 (!rtlpriv->dm.disable_framebursting)) {
673 cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
674 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
675 if (cur_rxok_cnt > 4 * cur_txok_cnt) {
676 if (!rtlpriv->dm.is_cur_rdlstate ||
677 !rtlpriv->dm.current_turbo_edca) {
678 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM,
679 edca_be_dl);
680 rtlpriv->dm.is_cur_rdlstate = true;
681 }
682 } else {
683 if (rtlpriv->dm.is_cur_rdlstate ||
684 !rtlpriv->dm.current_turbo_edca) {
685 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM,
686 edca_be_ul);
687 rtlpriv->dm.is_cur_rdlstate = false;
688 }
689 }
690 rtlpriv->dm.current_turbo_edca = true;
691 } else {
692 if (rtlpriv->dm.current_turbo_edca) {
693 u8 tmp = AC0_BE;
694 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
695 (u8 *) (&tmp));
696 rtlpriv->dm.current_turbo_edca = false;
697 }
698 }
699
700exit:
701 rtlpriv->dm.is_any_nonbepkts = false;
702 last_txok_cnt = rtlpriv->stats.txbytesunicast;
703 last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
704}
705
706static void rtl92d_dm_rxgain_tracking_thermalmeter(struct ieee80211_hw *hw)
707{
708 struct rtl_priv *rtlpriv = rtl_priv(hw);
709 u8 index_mapping[RX_INDEX_MAPPING_NUM] = {
710 0x0f, 0x0f, 0x0d, 0x0c, 0x0b,
711 0x0a, 0x09, 0x08, 0x07, 0x06,
712 0x05, 0x04, 0x04, 0x03, 0x02
713 };
714 int i;
715 u32 u4tmp;
716
717 u4tmp = (index_mapping[(rtlpriv->efuse.eeprom_thermalmeter -
718 rtlpriv->dm.thermalvalue_rxgain)]) << 12;
719 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
720 ("===> Rx Gain %x\n", u4tmp));
721 for (i = RF90_PATH_A; i < rtlpriv->phy.num_total_rfpath; i++)
722 rtl_set_rfreg(hw, i, 0x3C, BRFREGOFFSETMASK,
723 (rtlpriv->phy.reg_rf3c[i] & (~(0xF000))) | u4tmp);
724}
725
726static void rtl92d_bandtype_2_4G(struct ieee80211_hw *hw, long *temp_cckg,
727 u8 *cck_index_old)
728{
729 struct rtl_priv *rtlpriv = rtl_priv(hw);
730 int i;
731 unsigned long flag = 0;
732 long temp_cck;
733
734 /* Query CCK default setting From 0xa24 */
735 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
736 temp_cck = rtl_get_bbreg(hw, RCCK0_TXFILTER2,
737 BMASKDWORD) & BMASKCCK;
738 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
739 for (i = 0; i < CCK_TABLE_LENGTH; i++) {
740 if (rtlpriv->dm.cck_inch14) {
741 if (!memcmp((void *)&temp_cck,
742 (void *)&cckswing_table_ch14[i][2], 4)) {
743 *cck_index_old = (u8) i;
744 RT_TRACE(rtlpriv,
745 COMP_POWER_TRACKING,
746 DBG_LOUD,
747 ("Initial reg0x%x = 0x%lx, "
748 "cck_index=0x%x, ch 14 %d\n",
749 RCCK0_TXFILTER2,
750 temp_cck, *cck_index_old,
751 rtlpriv->dm.cck_inch14));
752 break;
753 }
754 } else {
755 if (!memcmp((void *) &temp_cck,
756 &cckswing_table_ch1ch13[i][2], 4)) {
757 *cck_index_old = (u8) i;
758 RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
759 DBG_LOUD,
760 ("Initial reg0x%x = 0x%lx, "
761 "cck_index = 0x%x, ch14 %d\n",
762 RCCK0_TXFILTER2,
763 temp_cck, *cck_index_old,
764 rtlpriv->dm.cck_inch14));
765 break;
766 }
767 }
768 }
769 *temp_cckg = temp_cck;
770}
771
772static void rtl92d_bandtype_5G(struct rtl_hal *rtlhal, u8 *ofdm_index,
773 bool *internal_pa, u8 thermalvalue, u8 delta,
774 u8 rf, struct rtl_efuse *rtlefuse,
775 struct rtl_priv *rtlpriv, struct rtl_phy *rtlphy,
776 u8 index_mapping[5][INDEX_MAPPING_NUM],
777 u8 index_mapping_pa[8][INDEX_MAPPING_NUM])
778{
779 int i;
780 u8 index;
781 u8 offset = 0;
782
783 for (i = 0; i < rf; i++) {
784 if (rtlhal->macphymode == DUALMAC_DUALPHY &&
785 rtlhal->interfaceindex == 1) /* MAC 1 5G */
786 *internal_pa = rtlefuse->internal_pa_5g[1];
787 else
788 *internal_pa = rtlefuse->internal_pa_5g[i];
789 if (*internal_pa) {
790 if (rtlhal->interfaceindex == 1 || i == rf)
791 offset = 4;
792 else
793 offset = 0;
794 if (rtlphy->current_channel >= 100 &&
795 rtlphy->current_channel <= 165)
796 offset += 2;
797 } else {
798 if (rtlhal->interfaceindex == 1 || i == rf)
799 offset = 2;
800 else
801 offset = 0;
802 }
803 if (thermalvalue > rtlefuse->eeprom_thermalmeter)
804 offset++;
805 if (*internal_pa) {
806 if (delta > INDEX_MAPPING_NUM - 1)
807 index = index_mapping_pa[offset]
808 [INDEX_MAPPING_NUM - 1];
809 else
810 index =
811 index_mapping_pa[offset][delta];
812 } else {
813 if (delta > INDEX_MAPPING_NUM - 1)
814 index =
815 index_mapping[offset][INDEX_MAPPING_NUM - 1];
816 else
817 index = index_mapping[offset][delta];
818 }
819 if (thermalvalue > rtlefuse->eeprom_thermalmeter) {
820 if (*internal_pa && thermalvalue > 0x12) {
821 ofdm_index[i] = rtlpriv->dm.ofdm_index[i] -
822 ((delta / 2) * 3 + (delta % 2));
823 } else {
824 ofdm_index[i] -= index;
825 }
826 } else {
827 ofdm_index[i] += index;
828 }
829 }
830}
831
832static void rtl92d_dm_txpower_tracking_callback_thermalmeter(
833 struct ieee80211_hw *hw)
834{
835 struct rtl_priv *rtlpriv = rtl_priv(hw);
836 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
837 struct rtl_phy *rtlphy = &(rtlpriv->phy);
838 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
839 u8 thermalvalue, delta, delta_lck, delta_iqk, delta_rxgain;
840 u8 offset, thermalvalue_avg_count = 0;
841 u32 thermalvalue_avg = 0;
842 bool internal_pa = false;
843 long ele_a = 0, ele_d, temp_cck, val_x, value32;
844 long val_y, ele_c = 0;
845 u8 ofdm_index[2];
846 u8 cck_index = 0;
847 u8 ofdm_index_old[2];
848 u8 cck_index_old = 0;
849 u8 index;
850 int i;
851 bool is2t = IS_92D_SINGLEPHY(rtlhal->version);
852 u8 ofdm_min_index = 6, ofdm_min_index_internal_pa = 3, rf;
853 u8 indexforchannel =
854 rtl92d_get_rightchnlplace_for_iqk(rtlphy->current_channel);
855 u8 index_mapping[5][INDEX_MAPPING_NUM] = {
856 /* 5G, path A/MAC 0, decrease power */
857 {0, 1, 3, 6, 8, 9, 11, 13, 14, 16, 17, 18, 18},
858 /* 5G, path A/MAC 0, increase power */
859 {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18},
860 /* 5G, path B/MAC 1, decrease power */
861 {0, 2, 3, 6, 8, 9, 11, 13, 14, 16, 17, 18, 18},
862 /* 5G, path B/MAC 1, increase power */
863 {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18},
864 /* 2.4G, for decreas power */
865 {0, 1, 2, 3, 4, 5, 6, 7, 7, 8, 9, 10, 10},
866 };
867 u8 index_mapping_internal_pa[8][INDEX_MAPPING_NUM] = {
868 /* 5G, path A/MAC 0, ch36-64, decrease power */
869 {0, 1, 2, 4, 6, 7, 9, 11, 12, 14, 15, 16, 16},
870 /* 5G, path A/MAC 0, ch36-64, increase power */
871 {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18},
872 /* 5G, path A/MAC 0, ch100-165, decrease power */
873 {0, 1, 2, 3, 5, 6, 8, 10, 11, 13, 14, 15, 15},
874 /* 5G, path A/MAC 0, ch100-165, increase power */
875 {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18},
876 /* 5G, path B/MAC 1, ch36-64, decrease power */
877 {0, 1, 2, 4, 6, 7, 9, 11, 12, 14, 15, 16, 16},
878 /* 5G, path B/MAC 1, ch36-64, increase power */
879 {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18},
880 /* 5G, path B/MAC 1, ch100-165, decrease power */
881 {0, 1, 2, 3, 5, 6, 8, 9, 10, 12, 13, 14, 14},
882 /* 5G, path B/MAC 1, ch100-165, increase power */
883 {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18},
884 };
885
886 rtlpriv->dm.txpower_trackinginit = true;
887 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, ("\n"));
888 thermalvalue = (u8) rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0xf800);
889 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
890 ("Readback Thermal Meter = 0x%x pre thermal meter 0x%x "
891 "eeprom_thermalmeter 0x%x\n", thermalvalue,
892 rtlpriv->dm.thermalvalue, rtlefuse->eeprom_thermalmeter));
893 rtl92d_phy_ap_calibrate(hw, (thermalvalue -
894 rtlefuse->eeprom_thermalmeter));
895 if (is2t)
896 rf = 2;
897 else
898 rf = 1;
899 if (thermalvalue) {
900 ele_d = rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
901 BMASKDWORD) & BMASKOFDM_D;
902 for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) {
903 if (ele_d == (ofdmswing_table[i] & BMASKOFDM_D)) {
904 ofdm_index_old[0] = (u8) i;
905
906 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
907 ("Initial pathA ele_d reg0x%x = 0x%lx,"
908 " ofdm_index=0x%x\n",
909 ROFDM0_XATxIQIMBALANCE,
910 ele_d, ofdm_index_old[0]));
911 break;
912 }
913 }
914 if (is2t) {
915 ele_d = rtl_get_bbreg(hw, ROFDM0_XBTxIQIMBALANCE,
916 BMASKDWORD) & BMASKOFDM_D;
917 for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) {
918 if (ele_d ==
919 (ofdmswing_table[i] & BMASKOFDM_D)) {
920 ofdm_index_old[1] = (u8) i;
921 RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
922 DBG_LOUD,
923 ("Initial pathB ele_d reg "
924 "0x%x = 0x%lx, ofdm_index "
925 "= 0x%x\n",
926 ROFDM0_XBTxIQIMBALANCE, ele_d,
927 ofdm_index_old[1]));
928 break;
929 }
930 }
931 }
932 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
933 rtl92d_bandtype_2_4G(hw, &temp_cck, &cck_index_old);
934 } else {
935 temp_cck = 0x090e1317;
936 cck_index_old = 12;
937 }
938
939 if (!rtlpriv->dm.thermalvalue) {
940 rtlpriv->dm.thermalvalue =
941 rtlefuse->eeprom_thermalmeter;
942 rtlpriv->dm.thermalvalue_lck = thermalvalue;
943 rtlpriv->dm.thermalvalue_iqk = thermalvalue;
944 rtlpriv->dm.thermalvalue_rxgain =
945 rtlefuse->eeprom_thermalmeter;
946 for (i = 0; i < rf; i++)
947 rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i];
948 rtlpriv->dm.cck_index = cck_index_old;
949 }
950 if (rtlhal->reloadtxpowerindex) {
951 for (i = 0; i < rf; i++)
952 rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i];
953 rtlpriv->dm.cck_index = cck_index_old;
954 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
955 ("reload ofdm index for band switch\n"));
956 }
957 rtlpriv->dm.thermalvalue_avg
958 [rtlpriv->dm.thermalvalue_avg_index] = thermalvalue;
959 rtlpriv->dm.thermalvalue_avg_index++;
960 if (rtlpriv->dm.thermalvalue_avg_index == AVG_THERMAL_NUM)
961 rtlpriv->dm.thermalvalue_avg_index = 0;
962 for (i = 0; i < AVG_THERMAL_NUM; i++) {
963 if (rtlpriv->dm.thermalvalue_avg[i]) {
964 thermalvalue_avg +=
965 rtlpriv->dm.thermalvalue_avg[i];
966 thermalvalue_avg_count++;
967 }
968 }
969 if (thermalvalue_avg_count)
970 thermalvalue = (u8) (thermalvalue_avg /
971 thermalvalue_avg_count);
972 if (rtlhal->reloadtxpowerindex) {
973 delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ?
974 (thermalvalue - rtlefuse->eeprom_thermalmeter) :
975 (rtlefuse->eeprom_thermalmeter - thermalvalue);
976 rtlhal->reloadtxpowerindex = false;
977 rtlpriv->dm.done_txpower = false;
978 } else if (rtlpriv->dm.done_txpower) {
979 delta = (thermalvalue > rtlpriv->dm.thermalvalue) ?
980 (thermalvalue - rtlpriv->dm.thermalvalue) :
981 (rtlpriv->dm.thermalvalue - thermalvalue);
982 } else {
983 delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ?
984 (thermalvalue - rtlefuse->eeprom_thermalmeter) :
985 (rtlefuse->eeprom_thermalmeter - thermalvalue);
986 }
987 delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ?
988 (thermalvalue - rtlpriv->dm.thermalvalue_lck) :
989 (rtlpriv->dm.thermalvalue_lck - thermalvalue);
990 delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ?
991 (thermalvalue - rtlpriv->dm.thermalvalue_iqk) :
992 (rtlpriv->dm.thermalvalue_iqk - thermalvalue);
993 delta_rxgain =
994 (thermalvalue > rtlpriv->dm.thermalvalue_rxgain) ?
995 (thermalvalue - rtlpriv->dm.thermalvalue_rxgain) :
996 (rtlpriv->dm.thermalvalue_rxgain - thermalvalue);
997 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
998 ("Readback Thermal Meter = 0x%x pre thermal meter 0x%x"
999 " eeprom_thermalmeter 0x%x delta 0x%x "
1000 "delta_lck 0x%x delta_iqk 0x%x\n",
1001 thermalvalue, rtlpriv->dm.thermalvalue,
1002 rtlefuse->eeprom_thermalmeter, delta, delta_lck,
1003 delta_iqk));
1004 if ((delta_lck > rtlefuse->delta_lck) &&
1005 (rtlefuse->delta_lck != 0)) {
1006 rtlpriv->dm.thermalvalue_lck = thermalvalue;
1007 rtl92d_phy_lc_calibrate(hw);
1008 }
1009 if (delta > 0 && rtlpriv->dm.txpower_track_control) {
1010 rtlpriv->dm.done_txpower = true;
1011 delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ?
1012 (thermalvalue - rtlefuse->eeprom_thermalmeter) :
1013 (rtlefuse->eeprom_thermalmeter - thermalvalue);
1014 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1015 offset = 4;
1016 if (delta > INDEX_MAPPING_NUM - 1)
1017 index = index_mapping[offset]
1018 [INDEX_MAPPING_NUM - 1];
1019 else
1020 index = index_mapping[offset][delta];
1021 if (thermalvalue > rtlpriv->dm.thermalvalue) {
1022 for (i = 0; i < rf; i++)
1023 ofdm_index[i] -= delta;
1024 cck_index -= delta;
1025 } else {
1026 for (i = 0; i < rf; i++)
1027 ofdm_index[i] += index;
1028 cck_index += index;
1029 }
1030 } else if (rtlhal->current_bandtype == BAND_ON_5G) {
1031 rtl92d_bandtype_5G(rtlhal, ofdm_index,
1032 &internal_pa, thermalvalue,
1033 delta, rf, rtlefuse, rtlpriv,
1034 rtlphy, index_mapping,
1035 index_mapping_internal_pa);
1036 }
1037 if (is2t) {
1038 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1039 ("temp OFDM_A_index=0x%x, OFDM_B_index"
1040 " = 0x%x,cck_index=0x%x\n",
1041 rtlpriv->dm.ofdm_index[0],
1042 rtlpriv->dm.ofdm_index[1],
1043 rtlpriv->dm.cck_index));
1044 } else {
1045 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1046 ("temp OFDM_A_index=0x%x,cck_index = "
1047 "0x%x\n",
1048 rtlpriv->dm.ofdm_index[0],
1049 rtlpriv->dm.cck_index));
1050 }
1051 for (i = 0; i < rf; i++) {
1052 if (ofdm_index[i] > OFDM_TABLE_SIZE_92D - 1)
1053 ofdm_index[i] = OFDM_TABLE_SIZE_92D - 1;
1054 else if (ofdm_index[i] < ofdm_min_index)
1055 ofdm_index[i] = ofdm_min_index;
1056 }
1057 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1058 if (cck_index > CCK_TABLE_SIZE - 1) {
1059 cck_index = CCK_TABLE_SIZE - 1;
1060 } else if (internal_pa ||
1061 rtlhal->current_bandtype ==
1062 BAND_ON_2_4G) {
1063 if (ofdm_index[i] <
1064 ofdm_min_index_internal_pa)
1065 ofdm_index[i] =
1066 ofdm_min_index_internal_pa;
1067 } else if (cck_index < 0) {
1068 cck_index = 0;
1069 }
1070 }
1071 if (is2t) {
1072 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1073 ("new OFDM_A_index=0x%x, OFDM_B_index "
1074 "= 0x%x, cck_index=0x%x\n",
1075 ofdm_index[0], ofdm_index[1],
1076 cck_index));
1077 } else {
1078 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1079 ("new OFDM_A_index=0x%x,cck_index = "
1080 "0x%x\n",
1081 ofdm_index[0], cck_index));
1082 }
1083 ele_d = (ofdmswing_table[(u8) ofdm_index[0]] &
1084 0xFFC00000) >> 22;
1085 val_x = rtlphy->iqk_matrix_regsetting
1086 [indexforchannel].value[0][0];
1087 val_y = rtlphy->iqk_matrix_regsetting
1088 [indexforchannel].value[0][1];
1089 if (val_x != 0) {
1090 if ((val_x & 0x00000200) != 0)
1091 val_x = val_x | 0xFFFFFC00;
1092 ele_a =
1093 ((val_x * ele_d) >> 8) & 0x000003FF;
1094
1095 /* new element C = element D x Y */
1096 if ((val_y & 0x00000200) != 0)
1097 val_y = val_y | 0xFFFFFC00;
1098 ele_c = ((val_y * ele_d) >> 8) & 0x000003FF;
1099
1100 /* wirte new elements A, C, D to regC80 and
1101 * regC94, element B is always 0 */
1102 value32 = (ele_d << 22) | ((ele_c & 0x3F) <<
1103 16) | ele_a;
1104 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
1105 BMASKDWORD, value32);
1106
1107 value32 = (ele_c & 0x000003C0) >> 6;
1108 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, BMASKH4BITS,
1109 value32);
1110
1111 value32 = ((val_x * ele_d) >> 7) & 0x01;
1112 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24),
1113 value32);
1114
1115 } else {
1116 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
1117 BMASKDWORD,
1118 ofdmswing_table
1119 [(u8)ofdm_index[0]]);
1120 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, BMASKH4BITS,
1121 0x00);
1122 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1123 BIT(24), 0x00);
1124 }
1125
1126 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1127 ("TxPwrTracking for interface %d path A: X ="
1128 " 0x%lx, Y = 0x%lx ele_A = 0x%lx ele_C = "
1129 "0x%lx ele_D = 0x%lx 0xe94 = 0x%lx 0xe9c = "
1130 "0x%lx\n", rtlhal->interfaceindex,
1131 val_x, val_y, ele_a, ele_c, ele_d,
1132 val_x, val_y));
1133
1134 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1135 /* Adjust CCK according to IQK result */
1136 if (!rtlpriv->dm.cck_inch14) {
1137 rtl_write_byte(rtlpriv, 0xa22,
1138 cckswing_table_ch1ch13
1139 [(u8)cck_index][0]);
1140 rtl_write_byte(rtlpriv, 0xa23,
1141 cckswing_table_ch1ch13
1142 [(u8)cck_index][1]);
1143 rtl_write_byte(rtlpriv, 0xa24,
1144 cckswing_table_ch1ch13
1145 [(u8)cck_index][2]);
1146 rtl_write_byte(rtlpriv, 0xa25,
1147 cckswing_table_ch1ch13
1148 [(u8)cck_index][3]);
1149 rtl_write_byte(rtlpriv, 0xa26,
1150 cckswing_table_ch1ch13
1151 [(u8)cck_index][4]);
1152 rtl_write_byte(rtlpriv, 0xa27,
1153 cckswing_table_ch1ch13
1154 [(u8)cck_index][5]);
1155 rtl_write_byte(rtlpriv, 0xa28,
1156 cckswing_table_ch1ch13
1157 [(u8)cck_index][6]);
1158 rtl_write_byte(rtlpriv, 0xa29,
1159 cckswing_table_ch1ch13
1160 [(u8)cck_index][7]);
1161 } else {
1162 rtl_write_byte(rtlpriv, 0xa22,
1163 cckswing_table_ch14
1164 [(u8)cck_index][0]);
1165 rtl_write_byte(rtlpriv, 0xa23,
1166 cckswing_table_ch14
1167 [(u8)cck_index][1]);
1168 rtl_write_byte(rtlpriv, 0xa24,
1169 cckswing_table_ch14
1170 [(u8)cck_index][2]);
1171 rtl_write_byte(rtlpriv, 0xa25,
1172 cckswing_table_ch14
1173 [(u8)cck_index][3]);
1174 rtl_write_byte(rtlpriv, 0xa26,
1175 cckswing_table_ch14
1176 [(u8)cck_index][4]);
1177 rtl_write_byte(rtlpriv, 0xa27,
1178 cckswing_table_ch14
1179 [(u8)cck_index][5]);
1180 rtl_write_byte(rtlpriv, 0xa28,
1181 cckswing_table_ch14
1182 [(u8)cck_index][6]);
1183 rtl_write_byte(rtlpriv, 0xa29,
1184 cckswing_table_ch14
1185 [(u8)cck_index][7]);
1186 }
1187 }
1188 if (is2t) {
1189 ele_d = (ofdmswing_table[(u8) ofdm_index[1]] &
1190 0xFFC00000) >> 22;
1191 val_x = rtlphy->iqk_matrix_regsetting
1192 [indexforchannel].value[0][4];
1193 val_y = rtlphy->iqk_matrix_regsetting
1194 [indexforchannel].value[0][5];
1195 if (val_x != 0) {
1196 if ((val_x & 0x00000200) != 0)
1197 /* consider minus */
1198 val_x = val_x | 0xFFFFFC00;
1199 ele_a = ((val_x * ele_d) >> 8) &
1200 0x000003FF;
1201 /* new element C = element D x Y */
1202 if ((val_y & 0x00000200) != 0)
1203 val_y =
1204 val_y | 0xFFFFFC00;
1205 ele_c =
1206 ((val_y *
1207 ele_d) >> 8) & 0x00003FF;
1208 /* write new elements A, C, D to regC88
1209 * and regC9C, element B is always 0
1210 */
1211 value32 = (ele_d << 22) |
1212 ((ele_c & 0x3F) << 16) |
1213 ele_a;
1214 rtl_set_bbreg(hw,
1215 ROFDM0_XBTxIQIMBALANCE,
1216 BMASKDWORD, value32);
1217 value32 = (ele_c & 0x000003C0) >> 6;
1218 rtl_set_bbreg(hw, ROFDM0_XDTxAFE,
1219 BMASKH4BITS, value32);
1220 value32 = ((val_x * ele_d) >> 7) & 0x01;
1221 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1222 BIT(28), value32);
1223 } else {
1224 rtl_set_bbreg(hw,
1225 ROFDM0_XBTxIQIMBALANCE,
1226 BMASKDWORD,
1227 ofdmswing_table
1228 [(u8) ofdm_index[1]]);
1229 rtl_set_bbreg(hw, ROFDM0_XDTxAFE,
1230 BMASKH4BITS, 0x00);
1231 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1232 BIT(28), 0x00);
1233 }
1234 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1235 ("TxPwrTracking path B: X = 0x%lx, "
1236 "Y = 0x%lx ele_A = 0x%lx ele_C = 0x"
1237 "%lx ele_D = 0x%lx 0xeb4 = 0x%lx "
1238 "0xebc = 0x%lx\n",
1239 val_x, val_y, ele_a, ele_c,
1240 ele_d, val_x, val_y));
1241 }
1242 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1243 ("TxPwrTracking 0xc80 = 0x%x, 0xc94 = "
1244 "0x%x RF 0x24 = 0x%x\n",
1245 rtl_get_bbreg(hw, 0xc80, BMASKDWORD),
1246 rtl_get_bbreg(hw, 0xc94, BMASKDWORD),
1247 rtl_get_rfreg(hw, RF90_PATH_A, 0x24,
1248 BRFREGOFFSETMASK)));
1249 }
1250 if ((delta_iqk > rtlefuse->delta_iqk) &&
1251 (rtlefuse->delta_iqk != 0)) {
1252 rtl92d_phy_reset_iqk_result(hw);
1253 rtlpriv->dm.thermalvalue_iqk = thermalvalue;
1254 rtl92d_phy_iq_calibrate(hw);
1255 }
1256 if (delta_rxgain > 0 && rtlhal->current_bandtype == BAND_ON_5G
1257 && thermalvalue <= rtlefuse->eeprom_thermalmeter) {
1258 rtlpriv->dm.thermalvalue_rxgain = thermalvalue;
1259 rtl92d_dm_rxgain_tracking_thermalmeter(hw);
1260 }
1261 if (rtlpriv->dm.txpower_track_control)
1262 rtlpriv->dm.thermalvalue = thermalvalue;
1263 }
1264
1265 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, ("<===\n"));
1266}
1267
1268static void rtl92d_dm_initialize_txpower_tracking(struct ieee80211_hw *hw)
1269{
1270 struct rtl_priv *rtlpriv = rtl_priv(hw);
1271
1272 rtlpriv->dm.txpower_tracking = true;
1273 rtlpriv->dm.txpower_trackinginit = false;
1274 rtlpriv->dm.txpower_track_control = true;
1275 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1276 ("pMgntInfo->txpower_tracking = %d\n",
1277 rtlpriv->dm.txpower_tracking));
1278}
1279
1280void rtl92d_dm_check_txpower_tracking_thermal_meter(struct ieee80211_hw *hw)
1281{
1282 struct rtl_priv *rtlpriv = rtl_priv(hw);
1283 static u8 tm_trigger;
1284
1285 if (!rtlpriv->dm.txpower_tracking)
1286 return;
1287
1288 if (!tm_trigger) {
1289 rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, BIT(17) |
1290 BIT(16), 0x03);
1291 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1292 ("Trigger 92S Thermal Meter!!\n"));
1293 tm_trigger = 1;
1294 return;
1295 } else {
1296 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1297 ("Schedule TxPowerTracking direct call!!\n"));
1298 rtl92d_dm_txpower_tracking_callback_thermalmeter(hw);
1299 tm_trigger = 0;
1300 }
1301}
1302
1303void rtl92d_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
1304{
1305 struct rtl_priv *rtlpriv = rtl_priv(hw);
1306 struct rate_adaptive *ra = &(rtlpriv->ra);
1307
1308 ra->ratr_state = DM_RATR_STA_INIT;
1309 ra->pre_ratr_state = DM_RATR_STA_INIT;
1310 if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
1311 rtlpriv->dm.useramask = true;
1312 else
1313 rtlpriv->dm.useramask = false;
1314}
1315
1316void rtl92d_dm_init(struct ieee80211_hw *hw)
1317{
1318 struct rtl_priv *rtlpriv = rtl_priv(hw);
1319
1320 rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
1321 rtl92d_dm_diginit(hw);
1322 rtl92d_dm_init_dynamic_txpower(hw);
1323 rtl92d_dm_init_edca_turbo(hw);
1324 rtl92d_dm_init_rate_adaptive_mask(hw);
1325 rtl92d_dm_initialize_txpower_tracking(hw);
1326}
1327
1328void rtl92d_dm_watchdog(struct ieee80211_hw *hw)
1329{
1330 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1331 bool fw_current_inpsmode = false;
1332 bool fwps_awake = true;
1333
1334 /* 1. RF is OFF. (No need to do DM.)
1335 * 2. Fw is under power saving mode for FwLPS.
1336 * (Prevent from SW/FW I/O racing.)
1337 * 3. IPS workitem is scheduled. (Prevent from IPS sequence
1338 * to be swapped with DM.
1339 * 4. RFChangeInProgress is TRUE.
1340 * (Prevent from broken by IPS/HW/SW Rf off.) */
1341
1342 if ((ppsc->rfpwr_state == ERFON) && ((!fw_current_inpsmode) &&
1343 fwps_awake) && (!ppsc->rfchange_inprogress)) {
1344 rtl92d_dm_pwdb_monitor(hw);
1345 rtl92d_dm_false_alarm_counter_statistics(hw);
1346 rtl92d_dm_find_minimum_rssi(hw);
1347 rtl92d_dm_dig(hw);
1348 /* rtl92d_dm_dynamic_bb_powersaving(hw); */
1349 rtl92d_dm_dynamic_txpower(hw);
1350 /* rtl92d_dm_check_txpower_tracking_thermal_meter(hw); */
1351 /* rtl92d_dm_refresh_rate_adaptive_mask(hw); */
1352 /* rtl92d_dm_interrupt_migration(hw); */
1353 rtl92d_dm_check_edca_turbo(hw);
1354 }
1355}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/dm.h b/drivers/net/wireless/rtlwifi/rtl8192de/dm.h
new file mode 100644
index 000000000000..69354657f0f5
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/dm.h
@@ -0,0 +1,212 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92C_DM_H__
31#define __RTL92C_DM_H__
32
33#define HAL_DM_DIG_DISABLE BIT(0)
34#define HAL_DM_HIPWR_DISABLE BIT(1)
35
36#define OFDM_TABLE_LENGTH 37
37#define OFDM_TABLE_SIZE_92D 43
38#define CCK_TABLE_LENGTH 33
39
40#define CCK_TABLE_SIZE 33
41
42#define BW_AUTO_SWITCH_HIGH_LOW 25
43#define BW_AUTO_SWITCH_LOW_HIGH 30
44
45#define DM_DIG_THRESH_HIGH 40
46#define DM_DIG_THRESH_LOW 35
47
48#define DM_FALSEALARM_THRESH_LOW 400
49#define DM_FALSEALARM_THRESH_HIGH 1000
50
51#define DM_DIG_MAX 0x3e
52#define DM_DIG_MIN 0x1c
53
54#define DM_DIG_FA_UPPER 0x32
55#define DM_DIG_FA_LOWER 0x20
56#define DM_DIG_FA_TH0 0x100
57#define DM_DIG_FA_TH1 0x400
58#define DM_DIG_FA_TH2 0x600
59
60#define DM_DIG_BACKOFF_MAX 12
61#define DM_DIG_BACKOFF_MIN -4
62#define DM_DIG_BACKOFF_DEFAULT 10
63
64#define RXPATHSELECTION_SS_TH_lOW 30
65#define RXPATHSELECTION_DIFF_TH 18
66
67#define DM_RATR_STA_INIT 0
68#define DM_RATR_STA_HIGH 1
69#define DM_RATR_STA_MIDDLE 2
70#define DM_RATR_STA_LOW 3
71
72#define CTS2SELF_THVAL 30
73#define REGC38_TH 20
74
75#define WAIOTTHVAL 25
76
77#define TXHIGHPWRLEVEL_NORMAL 0
78#define TXHIGHPWRLEVEL_LEVEL1 1
79#define TXHIGHPWRLEVEL_LEVEL2 2
80#define TXHIGHPWRLEVEL_BT1 3
81#define TXHIGHPWRLEVEL_BT2 4
82
83#define DM_TYPE_BYFW 0
84#define DM_TYPE_BYDRIVER 1
85
86#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
87#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
88#define INDEX_MAPPING_NUM 13
89
90struct ps_t {
91 u8 pre_ccastate;
92 u8 cur_ccasate;
93
94 u8 pre_rfstate;
95 u8 cur_rfstate;
96
97 long rssi_val_min;
98};
99
100struct dig_t {
101 u8 dig_enable_flag;
102 u8 dig_ext_port_stage;
103
104 u32 rssi_lowthresh;
105 u32 rssi_highthresh;
106
107 u32 fa_lowthresh;
108 u32 fa_highthresh;
109
110 u8 cursta_connectctate;
111 u8 presta_connectstate;
112 u8 curmultista_connectstate;
113
114 u8 pre_igvalue;
115 u8 cur_igvalue;
116
117 char backoff_val;
118 char backoff_val_range_max;
119 char backoff_val_range_min;
120 u8 rx_gain_range_max;
121 u8 rx_gain_range_min;
122 u8 min_undecorated_pwdb_for_dm;
123 long last_min_undecorated_pwdb_for_dm;
124
125 u8 pre_cck_pd_state;
126 u8 cur_cck_pd_state;
127
128 u8 pre_cck_fa_state;
129 u8 cur_cck_fa_state;
130
131 u8 pre_ccastate;
132 u8 cur_ccasate;
133
134 u8 large_fa_hit;
135 u8 forbidden_igi;
136 u32 recover_cnt;
137};
138
139struct swat {
140 u8 failure_cnt;
141 u8 try_flag;
142 u8 stop_trying;
143 long pre_rssi;
144 long trying_threshold;
145 u8 cur_antenna;
146 u8 pre_antenna;
147};
148
149enum tag_dynamic_init_gain_operation_type_definition {
150 DIG_TYPE_THRESH_HIGH = 0,
151 DIG_TYPE_THRESH_LOW = 1,
152 DIG_TYPE_BACKOFF = 2,
153 DIG_TYPE_RX_GAIN_MIN = 3,
154 DIG_TYPE_RX_GAIN_MAX = 4,
155 DIG_TYPE_ENABLE = 5,
156 DIG_TYPE_DISABLE = 6,
157 DIG_OP_TYPE_MAX
158};
159
160enum tag_cck_packet_detection_threshold_type_definition {
161 CCK_PD_STAGE_LOWRSSI = 0,
162 CCK_PD_STAGE_HIGHRSSI = 1,
163 CCK_FA_STAGE_LOW = 2,
164 CCK_FA_STAGE_HIGH = 3,
165 CCK_PD_STAGE_MAX = 4,
166};
167
168enum dm_1r_cca {
169 CCA_1R = 0,
170 CCA_2R = 1,
171 CCA_MAX = 2,
172};
173
174enum dm_rf {
175 RF_SAVE = 0,
176 RF_NORMAL = 1,
177 RF_MAX = 2,
178};
179
180enum dm_sw_ant_switch {
181 ANS_ANTENNA_B = 1,
182 ANS_ANTENNA_A = 2,
183 ANS_ANTENNA_MAX = 3,
184};
185
186enum dm_dig_ext_port_alg {
187 DIG_EXT_PORT_STAGE_0 = 0,
188 DIG_EXT_PORT_STAGE_1 = 1,
189 DIG_EXT_PORT_STAGE_2 = 2,
190 DIG_EXT_PORT_STAGE_3 = 3,
191 DIG_EXT_PORT_STAGE_MAX = 4,
192};
193
194enum dm_dig_connect {
195 DIG_STA_DISCONNECT = 0,
196 DIG_STA_CONNECT = 1,
197 DIG_STA_BEFORE_CONNECT = 2,
198 DIG_MULTISTA_DISCONNECT = 3,
199 DIG_MULTISTA_CONNECT = 4,
200 DIG_CONNECT_MAX
201};
202
203extern struct dig_t de_digtable;
204
205void rtl92d_dm_init(struct ieee80211_hw *hw);
206void rtl92d_dm_watchdog(struct ieee80211_hw *hw);
207void rtl92d_dm_init_edca_turbo(struct ieee80211_hw *hw);
208void rtl92d_dm_write_dig(struct ieee80211_hw *hw);
209void rtl92d_dm_check_txpower_tracking_thermal_meter(struct ieee80211_hw *hw);
210void rtl92d_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);
211
212#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/fw.c b/drivers/net/wireless/rtlwifi/rtl8192de/fw.c
new file mode 100644
index 000000000000..82f060bdbc0b
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/fw.c
@@ -0,0 +1,790 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../pci.h"
32#include "../base.h"
33#include "reg.h"
34#include "def.h"
35#include "fw.h"
36#include "sw.h"
37
38static bool _rtl92d_is_fw_downloaded(struct rtl_priv *rtlpriv)
39{
40 return (rtl_read_dword(rtlpriv, REG_MCUFWDL) & MCUFWDL_RDY) ?
41 true : false;
42}
43
44static void _rtl92d_enable_fw_download(struct ieee80211_hw *hw, bool enable)
45{
46 struct rtl_priv *rtlpriv = rtl_priv(hw);
47 u8 tmp;
48
49 if (enable) {
50 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
51 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp | 0x04);
52 tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
53 rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp | 0x01);
54 tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL + 2);
55 rtl_write_byte(rtlpriv, REG_MCUFWDL + 2, tmp & 0xf7);
56 } else {
57 tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
58 rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp & 0xfe);
59 /* Reserved for fw extension.
60 * 0x81[7] is used for mac0 status ,
61 * so don't write this reg here
62 * rtl_write_byte(rtlpriv, REG_MCUFWDL + 1, 0x00);*/
63 }
64}
65
66static void _rtl92d_fw_block_write(struct ieee80211_hw *hw,
67 const u8 *buffer, u32 size)
68{
69 struct rtl_priv *rtlpriv = rtl_priv(hw);
70 u32 blocksize = sizeof(u32);
71 u8 *bufferptr = (u8 *) buffer;
72 u32 *pu4BytePtr = (u32 *) buffer;
73 u32 i, offset, blockCount, remainSize;
74
75 blockCount = size / blocksize;
76 remainSize = size % blocksize;
77 for (i = 0; i < blockCount; i++) {
78 offset = i * blocksize;
79 rtl_write_dword(rtlpriv, (FW_8192D_START_ADDRESS + offset),
80 *(pu4BytePtr + i));
81 }
82 if (remainSize) {
83 offset = blockCount * blocksize;
84 bufferptr += offset;
85 for (i = 0; i < remainSize; i++) {
86 rtl_write_byte(rtlpriv, (FW_8192D_START_ADDRESS +
87 offset + i), *(bufferptr + i));
88 }
89 }
90}
91
92static void _rtl92d_fw_page_write(struct ieee80211_hw *hw,
93 u32 page, const u8 *buffer, u32 size)
94{
95 struct rtl_priv *rtlpriv = rtl_priv(hw);
96 u8 value8;
97 u8 u8page = (u8) (page & 0x07);
98
99 value8 = (rtl_read_byte(rtlpriv, REG_MCUFWDL + 2) & 0xF8) | u8page;
100 rtl_write_byte(rtlpriv, (REG_MCUFWDL + 2), value8);
101 _rtl92d_fw_block_write(hw, buffer, size);
102}
103
104static void _rtl92d_fill_dummy(u8 *pfwbuf, u32 *pfwlen)
105{
106 u32 fwlen = *pfwlen;
107 u8 remain = (u8) (fwlen % 4);
108
109 remain = (remain == 0) ? 0 : (4 - remain);
110 while (remain > 0) {
111 pfwbuf[fwlen] = 0;
112 fwlen++;
113 remain--;
114 }
115 *pfwlen = fwlen;
116}
117
118static void _rtl92d_write_fw(struct ieee80211_hw *hw,
119 enum version_8192d version, u8 *buffer, u32 size)
120{
121 struct rtl_priv *rtlpriv = rtl_priv(hw);
122 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
123 u8 *bufferPtr = (u8 *) buffer;
124 u32 pagenums, remainSize;
125 u32 page, offset;
126
127 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE, ("FW size is %d bytes,\n", size));
128 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE)
129 _rtl92d_fill_dummy(bufferPtr, &size);
130 pagenums = size / FW_8192D_PAGE_SIZE;
131 remainSize = size % FW_8192D_PAGE_SIZE;
132 if (pagenums > 8) {
133 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
134 ("Page numbers should not greater then 8\n"));
135 }
136 for (page = 0; page < pagenums; page++) {
137 offset = page * FW_8192D_PAGE_SIZE;
138 _rtl92d_fw_page_write(hw, page, (bufferPtr + offset),
139 FW_8192D_PAGE_SIZE);
140 }
141 if (remainSize) {
142 offset = pagenums * FW_8192D_PAGE_SIZE;
143 page = pagenums;
144 _rtl92d_fw_page_write(hw, page, (bufferPtr + offset),
145 remainSize);
146 }
147}
148
149static int _rtl92d_fw_free_to_go(struct ieee80211_hw *hw)
150{
151 struct rtl_priv *rtlpriv = rtl_priv(hw);
152 u32 counter = 0;
153 u32 value32;
154
155 do {
156 value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
157 } while ((counter++ < FW_8192D_POLLING_TIMEOUT_COUNT) &&
158 (!(value32 & FWDL_ChkSum_rpt)));
159 if (counter >= FW_8192D_POLLING_TIMEOUT_COUNT) {
160 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
161 ("chksum report faill ! REG_MCUFWDL:0x%08x .\n",
162 value32));
163 return -EIO;
164 }
165 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
166 ("Checksum report OK ! REG_MCUFWDL:0x%08x .\n", value32));
167 value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
168 value32 |= MCUFWDL_RDY;
169 rtl_write_dword(rtlpriv, REG_MCUFWDL, value32);
170 return 0;
171}
172
173void rtl92d_firmware_selfreset(struct ieee80211_hw *hw)
174{
175 struct rtl_priv *rtlpriv = rtl_priv(hw);
176 u8 u1b_tmp;
177 u8 delay = 100;
178
179 /* Set (REG_HMETFR + 3) to 0x20 is reset 8051 */
180 rtl_write_byte(rtlpriv, REG_HMETFR + 3, 0x20);
181 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
182 while (u1b_tmp & BIT(2)) {
183 delay--;
184 if (delay == 0)
185 break;
186 udelay(50);
187 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
188 }
189 RT_ASSERT((delay > 0), ("8051 reset failed!\n"));
190 RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
191 ("=====> 8051 reset success (%d) .\n", delay));
192}
193
194static int _rtl92d_fw_init(struct ieee80211_hw *hw)
195{
196 struct rtl_priv *rtlpriv = rtl_priv(hw);
197 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
198 u32 counter;
199
200 RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG, ("FW already have download\n"));
201 /* polling for FW ready */
202 counter = 0;
203 do {
204 if (rtlhal->interfaceindex == 0) {
205 if (rtl_read_byte(rtlpriv, FW_MAC0_READY) &
206 MAC0_READY) {
207 RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
208 ("Polling FW ready success!! "
209 "REG_MCUFWDL: 0x%x .\n",
210 rtl_read_byte(rtlpriv,
211 FW_MAC0_READY)));
212 return 0;
213 }
214 udelay(5);
215 } else {
216 if (rtl_read_byte(rtlpriv, FW_MAC1_READY) &
217 MAC1_READY) {
218 RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
219 ("Polling FW ready success!! "
220 "REG_MCUFWDL: 0x%x .\n",
221 rtl_read_byte(rtlpriv,
222 FW_MAC1_READY)));
223 return 0;
224 }
225 udelay(5);
226 }
227 } while (counter++ < POLLING_READY_TIMEOUT_COUNT);
228
229 if (rtlhal->interfaceindex == 0) {
230 RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
231 ("Polling FW ready fail!! MAC0 FW init not ready: "
232 "0x%x .\n",
233 rtl_read_byte(rtlpriv, FW_MAC0_READY)));
234 } else {
235 RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
236 ("Polling FW ready fail!! MAC1 FW init not ready: "
237 "0x%x .\n",
238 rtl_read_byte(rtlpriv, FW_MAC1_READY)));
239 }
240 RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
241 ("Polling FW ready fail!! REG_MCUFWDL:0x%08ul .\n",
242 rtl_read_dword(rtlpriv, REG_MCUFWDL)));
243 return -1;
244}
245
246int rtl92d_download_fw(struct ieee80211_hw *hw)
247{
248 struct rtl_priv *rtlpriv = rtl_priv(hw);
249 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
250 u8 *pfwheader;
251 u8 *pfwdata;
252 u32 fwsize;
253 int err;
254 enum version_8192d version = rtlhal->version;
255 u8 value;
256 u32 count;
257 bool fw_downloaded = false, fwdl_in_process = false;
258 unsigned long flags;
259
260 if (!rtlhal->pfirmware)
261 return 1;
262 fwsize = rtlhal->fwsize;
263 pfwheader = (u8 *) rtlhal->pfirmware;
264 pfwdata = (u8 *) rtlhal->pfirmware;
265 rtlhal->fw_version = (u16) GET_FIRMWARE_HDR_VERSION(pfwheader);
266 rtlhal->fw_subversion = (u16) GET_FIRMWARE_HDR_SUB_VER(pfwheader);
267 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, (" FirmwareVersion(%d),"
268 "FirmwareSubVersion(%d), Signature(%#x)\n",
269 rtlhal->fw_version, rtlhal->fw_subversion,
270 GET_FIRMWARE_HDR_SIGNATURE(pfwheader)));
271 if (IS_FW_HEADER_EXIST(pfwheader)) {
272 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
273 ("Shift 32 bytes for FW header!!\n"));
274 pfwdata = pfwdata + 32;
275 fwsize = fwsize - 32;
276 }
277
278 spin_lock_irqsave(&globalmutex_for_fwdownload, flags);
279 fw_downloaded = _rtl92d_is_fw_downloaded(rtlpriv);
280 if ((rtl_read_byte(rtlpriv, 0x1f) & BIT(5)) == BIT(5))
281 fwdl_in_process = true;
282 else
283 fwdl_in_process = false;
284 if (fw_downloaded) {
285 spin_unlock_irqrestore(&globalmutex_for_fwdownload, flags);
286 goto exit;
287 } else if (fwdl_in_process) {
288 spin_unlock_irqrestore(&globalmutex_for_fwdownload, flags);
289 for (count = 0; count < 5000; count++) {
290 udelay(500);
291 spin_lock_irqsave(&globalmutex_for_fwdownload, flags);
292 fw_downloaded = _rtl92d_is_fw_downloaded(rtlpriv);
293 if ((rtl_read_byte(rtlpriv, 0x1f) & BIT(5)) == BIT(5))
294 fwdl_in_process = true;
295 else
296 fwdl_in_process = false;
297 spin_unlock_irqrestore(&globalmutex_for_fwdownload,
298 flags);
299 if (fw_downloaded)
300 goto exit;
301 else if (!fwdl_in_process)
302 break;
303 else
304 RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
305 ("Wait for another mac "
306 "download fw\n"));
307 }
308 spin_lock_irqsave(&globalmutex_for_fwdownload, flags);
309 value = rtl_read_byte(rtlpriv, 0x1f);
310 value |= BIT(5);
311 rtl_write_byte(rtlpriv, 0x1f, value);
312 spin_unlock_irqrestore(&globalmutex_for_fwdownload, flags);
313 } else {
314 value = rtl_read_byte(rtlpriv, 0x1f);
315 value |= BIT(5);
316 rtl_write_byte(rtlpriv, 0x1f, value);
317 spin_unlock_irqrestore(&globalmutex_for_fwdownload, flags);
318 }
319
320 /* If 8051 is running in RAM code, driver should
321 * inform Fw to reset by itself, or it will cause
322 * download Fw fail.*/
323 /* 8051 RAM code */
324 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) {
325 rtl92d_firmware_selfreset(hw);
326 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
327 }
328 _rtl92d_enable_fw_download(hw, true);
329 _rtl92d_write_fw(hw, version, pfwdata, fwsize);
330 _rtl92d_enable_fw_download(hw, false);
331 spin_lock_irqsave(&globalmutex_for_fwdownload, flags);
332 err = _rtl92d_fw_free_to_go(hw);
333 /* download fw over,clear 0x1f[5] */
334 value = rtl_read_byte(rtlpriv, 0x1f);
335 value &= (~BIT(5));
336 rtl_write_byte(rtlpriv, 0x1f, value);
337 spin_unlock_irqrestore(&globalmutex_for_fwdownload, flags);
338 if (err) {
339 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
340 ("fw is not ready to run!\n"));
341 goto exit;
342 } else {
343 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
344 ("fw is ready to run!\n"));
345 }
346exit:
347 err = _rtl92d_fw_init(hw);
348 return err;
349}
350
351static bool _rtl92d_check_fw_read_last_h2c(struct ieee80211_hw *hw, u8 boxnum)
352{
353 struct rtl_priv *rtlpriv = rtl_priv(hw);
354 u8 val_hmetfr;
355 bool result = false;
356
357 val_hmetfr = rtl_read_byte(rtlpriv, REG_HMETFR);
358 if (((val_hmetfr >> boxnum) & BIT(0)) == 0)
359 result = true;
360 return result;
361}
362
363static void _rtl92d_fill_h2c_command(struct ieee80211_hw *hw,
364 u8 element_id, u32 cmd_len, u8 *cmdbuffer)
365{
366 struct rtl_priv *rtlpriv = rtl_priv(hw);
367 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
368 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
369 u8 boxnum;
370 u16 box_reg = 0, box_extreg = 0;
371 u8 u1b_tmp;
372 bool isfw_read = false;
373 u8 buf_index = 0;
374 bool bwrite_sucess = false;
375 u8 wait_h2c_limmit = 100;
376 u8 wait_writeh2c_limmit = 100;
377 u8 boxcontent[4], boxextcontent[2];
378 u32 h2c_waitcounter = 0;
379 unsigned long flag;
380 u8 idx;
381
382 if (ppsc->rfpwr_state == ERFOFF || ppsc->inactive_pwrstate == ERFOFF) {
383 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
384 ("Return as RF is off!!!\n"));
385 return;
386 }
387 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("come in\n"));
388 while (true) {
389 spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
390 if (rtlhal->h2c_setinprogress) {
391 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
392 ("H2C set in progress! Wait to set.."
393 "element_id(%d).\n", element_id));
394
395 while (rtlhal->h2c_setinprogress) {
396 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock,
397 flag);
398 h2c_waitcounter++;
399 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
400 ("Wait 100 us (%d times)...\n",
401 h2c_waitcounter));
402 udelay(100);
403
404 if (h2c_waitcounter > 1000)
405 return;
406
407 spin_lock_irqsave(&rtlpriv->locks.h2c_lock,
408 flag);
409 }
410 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
411 } else {
412 rtlhal->h2c_setinprogress = true;
413 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
414 break;
415 }
416 }
417 while (!bwrite_sucess) {
418 wait_writeh2c_limmit--;
419 if (wait_writeh2c_limmit == 0) {
420 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
421 ("Write H2C fail because no trigger "
422 "for FW INT!\n"));
423 break;
424 }
425 boxnum = rtlhal->last_hmeboxnum;
426 switch (boxnum) {
427 case 0:
428 box_reg = REG_HMEBOX_0;
429 box_extreg = REG_HMEBOX_EXT_0;
430 break;
431 case 1:
432 box_reg = REG_HMEBOX_1;
433 box_extreg = REG_HMEBOX_EXT_1;
434 break;
435 case 2:
436 box_reg = REG_HMEBOX_2;
437 box_extreg = REG_HMEBOX_EXT_2;
438 break;
439 case 3:
440 box_reg = REG_HMEBOX_3;
441 box_extreg = REG_HMEBOX_EXT_3;
442 break;
443 default:
444 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
445 ("switch case not process\n"));
446 break;
447 }
448 isfw_read = _rtl92d_check_fw_read_last_h2c(hw, boxnum);
449 while (!isfw_read) {
450 wait_h2c_limmit--;
451 if (wait_h2c_limmit == 0) {
452 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
453 ("Wating too long for FW read "
454 "clear HMEBox(%d)!\n", boxnum));
455 break;
456 }
457 udelay(10);
458 isfw_read = _rtl92d_check_fw_read_last_h2c(hw, boxnum);
459 u1b_tmp = rtl_read_byte(rtlpriv, 0x1BF);
460 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
461 ("Wating for FW read clear HMEBox(%d)!!! "
462 "0x1BF = %2x\n", boxnum, u1b_tmp));
463 }
464 if (!isfw_read) {
465 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
466 ("Write H2C register BOX[%d] fail!!!!! "
467 "Fw do not read.\n", boxnum));
468 break;
469 }
470 memset(boxcontent, 0, sizeof(boxcontent));
471 memset(boxextcontent, 0, sizeof(boxextcontent));
472 boxcontent[0] = element_id;
473 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
474 ("Write element_id box_reg(%4x) = %2x\n",
475 box_reg, element_id));
476 switch (cmd_len) {
477 case 1:
478 boxcontent[0] &= ~(BIT(7));
479 memcpy(boxcontent + 1, cmdbuffer + buf_index, 1);
480 for (idx = 0; idx < 4; idx++)
481 rtl_write_byte(rtlpriv, box_reg + idx,
482 boxcontent[idx]);
483 break;
484 case 2:
485 boxcontent[0] &= ~(BIT(7));
486 memcpy(boxcontent + 1, cmdbuffer + buf_index, 2);
487 for (idx = 0; idx < 4; idx++)
488 rtl_write_byte(rtlpriv, box_reg + idx,
489 boxcontent[idx]);
490 break;
491 case 3:
492 boxcontent[0] &= ~(BIT(7));
493 memcpy(boxcontent + 1, cmdbuffer + buf_index, 3);
494 for (idx = 0; idx < 4; idx++)
495 rtl_write_byte(rtlpriv, box_reg + idx,
496 boxcontent[idx]);
497 break;
498 case 4:
499 boxcontent[0] |= (BIT(7));
500 memcpy(boxextcontent, cmdbuffer + buf_index, 2);
501 memcpy(boxcontent + 1, cmdbuffer + buf_index + 2, 2);
502 for (idx = 0; idx < 2; idx++)
503 rtl_write_byte(rtlpriv, box_extreg + idx,
504 boxextcontent[idx]);
505 for (idx = 0; idx < 4; idx++)
506 rtl_write_byte(rtlpriv, box_reg + idx,
507 boxcontent[idx]);
508 break;
509 case 5:
510 boxcontent[0] |= (BIT(7));
511 memcpy(boxextcontent, cmdbuffer + buf_index, 2);
512 memcpy(boxcontent + 1, cmdbuffer + buf_index + 2, 3);
513 for (idx = 0; idx < 2; idx++)
514 rtl_write_byte(rtlpriv, box_extreg + idx,
515 boxextcontent[idx]);
516 for (idx = 0; idx < 4; idx++)
517 rtl_write_byte(rtlpriv, box_reg + idx,
518 boxcontent[idx]);
519 break;
520 default:
521 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
522 ("switch case not process\n"));
523 break;
524 }
525 bwrite_sucess = true;
526 rtlhal->last_hmeboxnum = boxnum + 1;
527 if (rtlhal->last_hmeboxnum == 4)
528 rtlhal->last_hmeboxnum = 0;
529 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
530 ("pHalData->last_hmeboxnum = %d\n",
531 rtlhal->last_hmeboxnum));
532 }
533 spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
534 rtlhal->h2c_setinprogress = false;
535 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
536 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("go out\n"));
537}
538
539void rtl92d_fill_h2c_cmd(struct ieee80211_hw *hw,
540 u8 element_id, u32 cmd_len, u8 *cmdbuffer)
541{
542 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
543 u32 tmp_cmdbuf[2];
544
545 if (rtlhal->fw_ready == false) {
546 RT_ASSERT(false, ("return H2C cmd because of Fw "
547 "download fail!!!\n"));
548 return;
549 }
550 memset(tmp_cmdbuf, 0, 8);
551 memcpy(tmp_cmdbuf, cmdbuffer, cmd_len);
552 _rtl92d_fill_h2c_command(hw, element_id, cmd_len, (u8 *)&tmp_cmdbuf);
553 return;
554}
555
556void rtl92d_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode)
557{
558 struct rtl_priv *rtlpriv = rtl_priv(hw);
559 u8 u1_h2c_set_pwrmode[3] = { 0 };
560 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
561
562 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, ("FW LPS mode = %d\n", mode));
563 SET_H2CCMD_PWRMODE_PARM_MODE(u1_h2c_set_pwrmode, mode);
564 SET_H2CCMD_PWRMODE_PARM_SMART_PS(u1_h2c_set_pwrmode, 1);
565 SET_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(u1_h2c_set_pwrmode,
566 ppsc->reg_max_lps_awakeintvl);
567 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
568 "rtl92d_set_fw_rsvdpagepkt(): u1_h2c_set_pwrmode\n",
569 u1_h2c_set_pwrmode, 3);
570 rtl92d_fill_h2c_cmd(hw, H2C_SETPWRMODE, 3, u1_h2c_set_pwrmode);
571}
572
573static bool _rtl92d_cmd_send_packet(struct ieee80211_hw *hw,
574 struct sk_buff *skb)
575{
576 struct rtl_priv *rtlpriv = rtl_priv(hw);
577 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
578 struct rtl8192_tx_ring *ring;
579 struct rtl_tx_desc *pdesc;
580 u8 idx = 0;
581 unsigned long flags;
582 struct sk_buff *pskb;
583
584 ring = &rtlpci->tx_ring[BEACON_QUEUE];
585 pskb = __skb_dequeue(&ring->queue);
586 if (pskb)
587 kfree_skb(pskb);
588 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
589 pdesc = &ring->desc[idx];
590 /* discard output from call below */
591 rtlpriv->cfg->ops->get_desc((u8 *) pdesc, true, HW_DESC_OWN);
592 rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *) pdesc, 1, 1, skb);
593 __skb_queue_tail(&ring->queue, skb);
594 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
595 rtlpriv->cfg->ops->tx_polling(hw, BEACON_QUEUE);
596 return true;
597}
598
599#define BEACON_PG 0 /*->1 */
600#define PSPOLL_PG 2
601#define NULL_PG 3
602#define PROBERSP_PG 4 /*->5 */
603#define TOTAL_RESERVED_PKT_LEN 768
604
605static u8 reserved_page_packet[TOTAL_RESERVED_PKT_LEN] = {
606 /* page 0 beacon */
607 0x80, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
608 0xFF, 0xFF, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
609 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x50, 0x08,
610 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
611 0x64, 0x00, 0x00, 0x04, 0x00, 0x0C, 0x6C, 0x69,
612 0x6E, 0x6B, 0x73, 0x79, 0x73, 0x5F, 0x77, 0x6C,
613 0x61, 0x6E, 0x01, 0x04, 0x82, 0x84, 0x8B, 0x96,
614 0x03, 0x01, 0x01, 0x06, 0x02, 0x00, 0x00, 0x2A,
615 0x01, 0x00, 0x32, 0x08, 0x24, 0x30, 0x48, 0x6C,
616 0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C, 0x18,
617 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
618 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
619 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
620 0x3D, 0x00, 0xDD, 0x06, 0x00, 0xE0, 0x4C, 0x02,
621 0x01, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
622 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
623
624 /* page 1 beacon */
625 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
626 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
627 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
628 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
629 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
630 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
631 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
632 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
633 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
634 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
635 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
636 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
637 0x10, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x10, 0x00,
638 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
639 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
640 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
641
642 /* page 2 ps-poll */
643 0xA4, 0x10, 0x01, 0xC0, 0x00, 0x40, 0x10, 0x10,
644 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
645 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
646 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
647 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
648 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
649 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
650 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
651 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
652 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
653 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
654 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
655 0x18, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x00, 0x00,
656 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
657 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
658 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
659
660 /* page 3 null */
661 0x48, 0x01, 0x00, 0x00, 0x00, 0x40, 0x10, 0x10,
662 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
663 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x00, 0x00,
664 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
665 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
666 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
667 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
668 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
669 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
670 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
671 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
672 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
673 0x72, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x00, 0x00,
674 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
675 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
676 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
677
678 /* page 4 probe_resp */
679 0x50, 0x00, 0x00, 0x00, 0x00, 0x40, 0x10, 0x10,
680 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
681 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x00, 0x00,
682 0x9E, 0x46, 0x15, 0x32, 0x27, 0xF2, 0x2D, 0x00,
683 0x64, 0x00, 0x00, 0x04, 0x00, 0x0C, 0x6C, 0x69,
684 0x6E, 0x6B, 0x73, 0x79, 0x73, 0x5F, 0x77, 0x6C,
685 0x61, 0x6E, 0x01, 0x04, 0x82, 0x84, 0x8B, 0x96,
686 0x03, 0x01, 0x01, 0x06, 0x02, 0x00, 0x00, 0x2A,
687 0x01, 0x00, 0x32, 0x08, 0x24, 0x30, 0x48, 0x6C,
688 0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C, 0x18,
689 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
690 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
691 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
692 0x3D, 0x00, 0xDD, 0x06, 0x00, 0xE0, 0x4C, 0x02,
693 0x01, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
694 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
695
696 /* page 5 probe_resp */
697 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
698 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
699 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
700 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
701 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
702 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
703 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
704 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
705 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
706 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
707 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
708 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
709 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
710 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
711 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
712 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
713};
714
715void rtl92d_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool dl_finished)
716{
717 struct rtl_priv *rtlpriv = rtl_priv(hw);
718 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
719 struct sk_buff *skb = NULL;
720 u32 totalpacketlen;
721 bool rtstatus;
722 u8 u1RsvdPageLoc[3] = { 0 };
723 bool dlok = false;
724 u8 *beacon;
725 u8 *p_pspoll;
726 u8 *nullfunc;
727 u8 *p_probersp;
728 /*---------------------------------------------------------
729 (1) beacon
730 ---------------------------------------------------------*/
731 beacon = &reserved_page_packet[BEACON_PG * 128];
732 SET_80211_HDR_ADDRESS2(beacon, mac->mac_addr);
733 SET_80211_HDR_ADDRESS3(beacon, mac->bssid);
734 /*-------------------------------------------------------
735 (2) ps-poll
736 --------------------------------------------------------*/
737 p_pspoll = &reserved_page_packet[PSPOLL_PG * 128];
738 SET_80211_PS_POLL_AID(p_pspoll, (mac->assoc_id | 0xc000));
739 SET_80211_PS_POLL_BSSID(p_pspoll, mac->bssid);
740 SET_80211_PS_POLL_TA(p_pspoll, mac->mac_addr);
741 SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1RsvdPageLoc, PSPOLL_PG);
742 /*--------------------------------------------------------
743 (3) null data
744 ---------------------------------------------------------*/
745 nullfunc = &reserved_page_packet[NULL_PG * 128];
746 SET_80211_HDR_ADDRESS1(nullfunc, mac->bssid);
747 SET_80211_HDR_ADDRESS2(nullfunc, mac->mac_addr);
748 SET_80211_HDR_ADDRESS3(nullfunc, mac->bssid);
749 SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1RsvdPageLoc, NULL_PG);
750 /*---------------------------------------------------------
751 (4) probe response
752 ----------------------------------------------------------*/
753 p_probersp = &reserved_page_packet[PROBERSP_PG * 128];
754 SET_80211_HDR_ADDRESS1(p_probersp, mac->bssid);
755 SET_80211_HDR_ADDRESS2(p_probersp, mac->mac_addr);
756 SET_80211_HDR_ADDRESS3(p_probersp, mac->bssid);
757 SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1RsvdPageLoc, PROBERSP_PG);
758 totalpacketlen = TOTAL_RESERVED_PKT_LEN;
759 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
760 "rtl92d_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
761 &reserved_page_packet[0], totalpacketlen);
762 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
763 "rtl92d_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
764 u1RsvdPageLoc, 3);
765 skb = dev_alloc_skb(totalpacketlen);
766 memcpy((u8 *) skb_put(skb, totalpacketlen), &reserved_page_packet,
767 totalpacketlen);
768 rtstatus = _rtl92d_cmd_send_packet(hw, skb);
769
770 if (rtstatus)
771 dlok = true;
772 if (dlok) {
773 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
774 ("Set RSVD page location to Fw.\n"));
775 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
776 "H2C_RSVDPAGE:\n", u1RsvdPageLoc, 3);
777 rtl92d_fill_h2c_cmd(hw, H2C_RSVDPAGE,
778 sizeof(u1RsvdPageLoc), u1RsvdPageLoc);
779 } else
780 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
781 ("Set RSVD page location to Fw FAIL!!!!!!.\n"));
782}
783
784void rtl92d_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus)
785{
786 u8 u1_joinbssrpt_parm[1] = {0};
787
788 SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(u1_joinbssrpt_parm, mstatus);
789 rtl92d_fill_h2c_cmd(hw, H2C_JOINBSSRPT, 1, u1_joinbssrpt_parm);
790}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/fw.h b/drivers/net/wireless/rtlwifi/rtl8192de/fw.h
new file mode 100644
index 000000000000..0c4d489eaa48
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/fw.h
@@ -0,0 +1,155 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92D__FW__H__
31#define __RTL92D__FW__H__
32
33#define FW_8192D_START_ADDRESS 0x1000
34#define FW_8192D_PAGE_SIZE 4096
35#define FW_8192D_POLLING_TIMEOUT_COUNT 1000
36
37#define IS_FW_HEADER_EXIST(_pfwhdr) \
38 ((GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFF0) == 0x92C0 || \
39 (GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFF0) == 0x88C0 || \
40 (GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFFF) == 0x92D0 || \
41 (GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFFF) == 0x92D1 || \
42 (GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFFF) == 0x92D2 || \
43 (GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFFF) == 0x92D3)
44
45/* Define a macro that takes an le32 word, converts it to host ordering,
46 * right shifts by a specified count, creates a mask of the specified
47 * bit count, and extracts that number of bits.
48 */
49
50#define SHIFT_AND_MASK_LE(__pdesc, __shift, __mask) \
51 ((le32_to_cpu(*(((__le32 *)(__pdesc)))) >> (__shift)) & \
52 BIT_LEN_MASK_32(__mask))
53
54/* Firmware Header(8-byte alinment required) */
55/* --- LONG WORD 0 ---- */
56#define GET_FIRMWARE_HDR_SIGNATURE(__fwhdr) \
57 SHIFT_AND_MASK_LE(__fwhdr, 0, 16)
58#define GET_FIRMWARE_HDR_CATEGORY(__fwhdr) \
59 SHIFT_AND_MASK_LE(__fwhdr, 16, 8)
60#define GET_FIRMWARE_HDR_FUNCTION(__fwhdr) \
61 SHIFT_AND_MASK_LE(__fwhdr, 24, 8)
62#define GET_FIRMWARE_HDR_VERSION(__fwhdr) \
63 SHIFT_AND_MASK_LE(__fwhdr + 4, 0, 16)
64#define GET_FIRMWARE_HDR_SUB_VER(__fwhdr) \
65 SHIFT_AND_MASK_LE(__fwhdr + 4, 16, 8)
66#define GET_FIRMWARE_HDR_RSVD1(__fwhdr) \
67 SHIFT_AND_MASK_LE(__fwhdr + 4, 24, 8)
68
69/* --- LONG WORD 1 ---- */
70#define GET_FIRMWARE_HDR_MONTH(__fwhdr) \
71 SHIFT_AND_MASK_LE(__fwhdr + 8, 0, 8)
72#define GET_FIRMWARE_HDR_DATE(__fwhdr) \
73 SHIFT_AND_MASK_LE(__fwhdr + 8, 8, 8)
74#define GET_FIRMWARE_HDR_HOUR(__fwhdr) \
75 SHIFT_AND_MASK_LE(__fwhdr + 8, 16, 8)
76#define GET_FIRMWARE_HDR_MINUTE(__fwhdr) \
77 SHIFT_AND_MASK_LE(__fwhdr + 8, 24, 8)
78#define GET_FIRMWARE_HDR_ROMCODE_SIZE(__fwhdr) \
79 SHIFT_AND_MASK_LE(__fwhdr + 12, 0, 16)
80#define GET_FIRMWARE_HDR_RSVD2(__fwhdr) \
81 SHIFT_AND_MASK_LE(__fwhdr + 12, 16, 16)
82
83/* --- LONG WORD 2 ---- */
84#define GET_FIRMWARE_HDR_SVN_IDX(__fwhdr) \
85 SHIFT_AND_MASK_LE(__fwhdr + 16, 0, 32)
86#define GET_FIRMWARE_HDR_RSVD3(__fwhdr) \
87 SHIFT_AND_MASK_LE(__fwhdr + 20, 0, 32)
88
89/* --- LONG WORD 3 ---- */
90#define GET_FIRMWARE_HDR_RSVD4(__fwhdr) \
91 SHIFT_AND_MASK_LE(__fwhdr + 24, 0, 32)
92#define GET_FIRMWARE_HDR_RSVD5(__fwhdr) \
93 SHIFT_AND_MASK_LE(__fwhdr + 28, 0, 32)
94
95#define pagenum_128(_len) \
96 (u32)(((_len) >> 7) + ((_len) & 0x7F ? 1 : 0))
97
98#define SET_H2CCMD_PWRMODE_PARM_MODE(__ph2ccmd, __val) \
99 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
100#define SET_H2CCMD_PWRMODE_PARM_SMART_PS(__ph2ccmd, __val) \
101 SET_BITS_TO_LE_1BYTE((__ph2ccmd) + 1, 0, 8, __val)
102#define SET_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__ph2ccmd, __val) \
103 SET_BITS_TO_LE_1BYTE((__ph2ccmd) + 2, 0, 8, __val)
104#define SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(__ph2ccmd, __val) \
105 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
106#define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__ph2ccmd, __val) \
107 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
108#define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__ph2ccmd, __val) \
109 SET_BITS_TO_LE_1BYTE((__ph2ccmd) + 1, 0, 8, __val)
110#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__ph2ccmd, __val) \
111 SET_BITS_TO_LE_1BYTE((__ph2ccmd) + 2, 0, 8, __val)
112
113struct rtl92d_firmware_header {
114 u16 signature;
115 u8 category;
116 u8 function;
117 u16 version;
118 u8 subversion;
119 u8 rsvd1;
120
121 u8 month;
122 u8 date;
123 u8 hour;
124 u8 minute;
125 u16 ramcodeSize;
126 u16 rsvd2;
127
128 u32 svnindex;
129 u32 rsvd3;
130
131 u32 rsvd4;
132 u32 rsvd5;
133};
134
135enum rtl8192d_h2c_cmd {
136 H2C_AP_OFFLOAD = 0,
137 H2C_SETPWRMODE = 1,
138 H2C_JOINBSSRPT = 2,
139 H2C_RSVDPAGE = 3,
140 H2C_RSSI_REPORT = 5,
141 H2C_RA_MASK = 6,
142 H2C_MAC_MODE_SEL = 9,
143 H2C_PWRM = 15,
144 MAX_H2CCMD
145};
146
147int rtl92d_download_fw(struct ieee80211_hw *hw);
148void rtl92d_fill_h2c_cmd(struct ieee80211_hw *hw, u8 element_id,
149 u32 cmd_len, u8 *p_cmdbuffer);
150void rtl92d_firmware_selfreset(struct ieee80211_hw *hw);
151void rtl92d_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode);
152void rtl92d_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished);
153void rtl92d_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus);
154
155#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/hw.c b/drivers/net/wireless/rtlwifi/rtl8192de/hw.c
new file mode 100644
index 000000000000..e833bbf92c55
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/hw.c
@@ -0,0 +1,2326 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../efuse.h"
32#include "../base.h"
33#include "../regd.h"
34#include "../cam.h"
35#include "../ps.h"
36#include "../pci.h"
37#include "reg.h"
38#include "def.h"
39#include "phy.h"
40#include "dm.h"
41#include "fw.h"
42#include "led.h"
43#include "sw.h"
44#include "hw.h"
45
46u32 rtl92de_read_dword_dbi(struct ieee80211_hw *hw, u16 offset, u8 direct)
47{
48 struct rtl_priv *rtlpriv = rtl_priv(hw);
49 u32 value;
50
51 rtl_write_word(rtlpriv, REG_DBI_CTRL, (offset & 0xFFC));
52 rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(1) | direct);
53 udelay(10);
54 value = rtl_read_dword(rtlpriv, REG_DBI_RDATA);
55 return value;
56}
57
58void rtl92de_write_dword_dbi(struct ieee80211_hw *hw,
59 u16 offset, u32 value, u8 direct)
60{
61 struct rtl_priv *rtlpriv = rtl_priv(hw);
62
63 rtl_write_word(rtlpriv, REG_DBI_CTRL, ((offset & 0xFFC) | 0xF000));
64 rtl_write_dword(rtlpriv, REG_DBI_WDATA, value);
65 rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(0) | direct);
66}
67
68static void _rtl92de_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
69 u8 set_bits, u8 clear_bits)
70{
71 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
72 struct rtl_priv *rtlpriv = rtl_priv(hw);
73
74 rtlpci->reg_bcn_ctrl_val |= set_bits;
75 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
76 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
77}
78
79static void _rtl92de_stop_tx_beacon(struct ieee80211_hw *hw)
80{
81 struct rtl_priv *rtlpriv = rtl_priv(hw);
82 u8 tmp1byte;
83
84 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
85 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
86 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
87 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
88 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
89 tmp1byte &= ~(BIT(0));
90 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
91}
92
93static void _rtl92de_resume_tx_beacon(struct ieee80211_hw *hw)
94{
95 struct rtl_priv *rtlpriv = rtl_priv(hw);
96 u8 tmp1byte;
97
98 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
99 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
100 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a);
101 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
102 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
103 tmp1byte |= BIT(0);
104 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
105}
106
107static void _rtl92de_enable_bcn_sub_func(struct ieee80211_hw *hw)
108{
109 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(1));
110}
111
112static void _rtl92de_disable_bcn_sub_func(struct ieee80211_hw *hw)
113{
114 _rtl92de_set_bcn_ctrl_reg(hw, BIT(1), 0);
115}
116
117void rtl92de_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
118{
119 struct rtl_priv *rtlpriv = rtl_priv(hw);
120 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
121 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
122
123 switch (variable) {
124 case HW_VAR_RCR:
125 *((u32 *) (val)) = rtlpci->receive_config;
126 break;
127 case HW_VAR_RF_STATE:
128 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
129 break;
130 case HW_VAR_FWLPS_RF_ON:{
131 enum rf_pwrstate rfState;
132 u32 val_rcr;
133
134 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
135 (u8 *) (&rfState));
136 if (rfState == ERFOFF) {
137 *((bool *) (val)) = true;
138 } else {
139 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
140 val_rcr &= 0x00070000;
141 if (val_rcr)
142 *((bool *) (val)) = false;
143 else
144 *((bool *) (val)) = true;
145 }
146 break;
147 }
148 case HW_VAR_FW_PSMODE_STATUS:
149 *((bool *) (val)) = ppsc->fw_current_inpsmode;
150 break;
151 case HW_VAR_CORRECT_TSF:{
152 u64 tsf;
153 u32 *ptsf_low = (u32 *)&tsf;
154 u32 *ptsf_high = ((u32 *)&tsf) + 1;
155
156 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
157 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
158 *((u64 *) (val)) = tsf;
159 break;
160 }
161 case HW_VAR_INT_MIGRATION:
162 *((bool *)(val)) = rtlpriv->dm.interrupt_migration;
163 break;
164 case HW_VAR_INT_AC:
165 *((bool *)(val)) = rtlpriv->dm.disable_tx_int;
166 break;
167 default:
168 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
169 ("switch case not process\n"));
170 break;
171 }
172}
173
174void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
175{
176 struct rtl_priv *rtlpriv = rtl_priv(hw);
177 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
178 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
179 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
180 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
181 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
182 u8 idx;
183
184 switch (variable) {
185 case HW_VAR_ETHER_ADDR:
186 for (idx = 0; idx < ETH_ALEN; idx++) {
187 rtl_write_byte(rtlpriv, (REG_MACID + idx),
188 val[idx]);
189 }
190 break;
191 case HW_VAR_BASIC_RATE: {
192 u16 rate_cfg = ((u16 *) val)[0];
193 u8 rate_index = 0;
194
195 rate_cfg = rate_cfg & 0x15f;
196 if (mac->vendor == PEER_CISCO &&
197 ((rate_cfg & 0x150) == 0))
198 rate_cfg |= 0x01;
199 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
200 rtl_write_byte(rtlpriv, REG_RRSR + 1,
201 (rate_cfg >> 8) & 0xff);
202 while (rate_cfg > 0x1) {
203 rate_cfg = (rate_cfg >> 1);
204 rate_index++;
205 }
206 if (rtlhal->fw_version > 0xe)
207 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
208 rate_index);
209 break;
210 }
211 case HW_VAR_BSSID:
212 for (idx = 0; idx < ETH_ALEN; idx++) {
213 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
214 val[idx]);
215 }
216 break;
217 case HW_VAR_SIFS:
218 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
219 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
220 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
221 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
222 if (!mac->ht_enable)
223 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
224 0x0e0e);
225 else
226 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
227 *((u16 *) val));
228 break;
229 case HW_VAR_SLOT_TIME: {
230 u8 e_aci;
231
232 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
233 ("HW_VAR_SLOT_TIME %x\n", val[0]));
234 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
235 for (e_aci = 0; e_aci < AC_MAX; e_aci++)
236 rtlpriv->cfg->ops->set_hw_reg(hw,
237 HW_VAR_AC_PARAM,
238 (u8 *) (&e_aci));
239 break;
240 }
241 case HW_VAR_ACK_PREAMBLE: {
242 u8 reg_tmp;
243 u8 short_preamble = (bool) (*(u8 *) val);
244
245 reg_tmp = (mac->cur_40_prime_sc) << 5;
246 if (short_preamble)
247 reg_tmp |= 0x80;
248 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
249 break;
250 }
251 case HW_VAR_AMPDU_MIN_SPACE: {
252 u8 min_spacing_to_set;
253 u8 sec_min_space;
254
255 min_spacing_to_set = *((u8 *) val);
256 if (min_spacing_to_set <= 7) {
257 sec_min_space = 0;
258 if (min_spacing_to_set < sec_min_space)
259 min_spacing_to_set = sec_min_space;
260 mac->min_space_cfg = ((mac->min_space_cfg & 0xf8) |
261 min_spacing_to_set);
262 *val = min_spacing_to_set;
263 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
264 ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
265 mac->min_space_cfg));
266 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
267 mac->min_space_cfg);
268 }
269 break;
270 }
271 case HW_VAR_SHORTGI_DENSITY: {
272 u8 density_to_set;
273
274 density_to_set = *((u8 *) val);
275 mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg;
276 mac->min_space_cfg |= (density_to_set << 3);
277 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
278 ("Set HW_VAR_SHORTGI_DENSITY: %#x\n",
279 mac->min_space_cfg));
280 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
281 mac->min_space_cfg);
282 break;
283 }
284 case HW_VAR_AMPDU_FACTOR: {
285 u8 factor_toset;
286 u32 regtoSet;
287 u8 *ptmp_byte = NULL;
288 u8 index;
289
290 if (rtlhal->macphymode == DUALMAC_DUALPHY)
291 regtoSet = 0xb9726641;
292 else if (rtlhal->macphymode == DUALMAC_SINGLEPHY)
293 regtoSet = 0x66626641;
294 else
295 regtoSet = 0xb972a841;
296 factor_toset = *((u8 *) val);
297 if (factor_toset <= 3) {
298 factor_toset = (1 << (factor_toset + 2));
299 if (factor_toset > 0xf)
300 factor_toset = 0xf;
301 for (index = 0; index < 4; index++) {
302 ptmp_byte = (u8 *) (&regtoSet) + index;
303 if ((*ptmp_byte & 0xf0) >
304 (factor_toset << 4))
305 *ptmp_byte = (*ptmp_byte & 0x0f)
306 | (factor_toset << 4);
307 if ((*ptmp_byte & 0x0f) > factor_toset)
308 *ptmp_byte = (*ptmp_byte & 0xf0)
309 | (factor_toset);
310 }
311 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, regtoSet);
312 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
313 ("Set HW_VAR_AMPDU_FACTOR: %#x\n",
314 factor_toset));
315 }
316 break;
317 }
318 case HW_VAR_AC_PARAM: {
319 u8 e_aci = *((u8 *) val);
320 rtl92d_dm_init_edca_turbo(hw);
321 if (rtlpci->acm_method != eAcmWay2_SW)
322 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL,
323 (u8 *) (&e_aci));
324 break;
325 }
326 case HW_VAR_ACM_CTRL: {
327 u8 e_aci = *((u8 *) val);
328 union aci_aifsn *p_aci_aifsn =
329 (union aci_aifsn *)(&(mac->ac[0].aifs));
330 u8 acm = p_aci_aifsn->f.acm;
331 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
332
333 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
334 if (acm) {
335 switch (e_aci) {
336 case AC0_BE:
337 acm_ctrl |= ACMHW_BEQEN;
338 break;
339 case AC2_VI:
340 acm_ctrl |= ACMHW_VIQEN;
341 break;
342 case AC3_VO:
343 acm_ctrl |= ACMHW_VOQEN;
344 break;
345 default:
346 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
347 ("HW_VAR_ACM_CTRL acm set "
348 "failed: eACI is %d\n", acm));
349 break;
350 }
351 } else {
352 switch (e_aci) {
353 case AC0_BE:
354 acm_ctrl &= (~ACMHW_BEQEN);
355 break;
356 case AC2_VI:
357 acm_ctrl &= (~ACMHW_VIQEN);
358 break;
359 case AC3_VO:
360 acm_ctrl &= (~ACMHW_VOQEN);
361 break;
362 default:
363 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
364 ("switch case not process\n"));
365 break;
366 }
367 }
368 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
369 ("SetHwReg8190pci(): [HW_VAR_ACM_CTRL] "
370 "Write 0x%X\n", acm_ctrl));
371 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
372 break;
373 }
374 case HW_VAR_RCR:
375 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
376 rtlpci->receive_config = ((u32 *) (val))[0];
377 break;
378 case HW_VAR_RETRY_LIMIT: {
379 u8 retry_limit = ((u8 *) (val))[0];
380
381 rtl_write_word(rtlpriv, REG_RL,
382 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
383 retry_limit << RETRY_LIMIT_LONG_SHIFT);
384 break;
385 }
386 case HW_VAR_DUAL_TSF_RST:
387 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
388 break;
389 case HW_VAR_EFUSE_BYTES:
390 rtlefuse->efuse_usedbytes = *((u16 *) val);
391 break;
392 case HW_VAR_EFUSE_USAGE:
393 rtlefuse->efuse_usedpercentage = *((u8 *) val);
394 break;
395 case HW_VAR_IO_CMD:
396 rtl92d_phy_set_io_cmd(hw, (*(enum io_type *)val));
397 break;
398 case HW_VAR_WPA_CONFIG:
399 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *) val));
400 break;
401 case HW_VAR_SET_RPWM:
402 rtl92d_fill_h2c_cmd(hw, H2C_PWRM, 1, (u8 *) (val));
403 break;
404 case HW_VAR_H2C_FW_PWRMODE:
405 break;
406 case HW_VAR_FW_PSMODE_STATUS:
407 ppsc->fw_current_inpsmode = *((bool *) val);
408 break;
409 case HW_VAR_H2C_FW_JOINBSSRPT: {
410 u8 mstatus = (*(u8 *) val);
411 u8 tmp_regcr, tmp_reg422;
412 bool recover = false;
413
414 if (mstatus == RT_MEDIA_CONNECT) {
415 rtlpriv->cfg->ops->set_hw_reg(hw,
416 HW_VAR_AID, NULL);
417 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
418 rtl_write_byte(rtlpriv, REG_CR + 1,
419 (tmp_regcr | BIT(0)));
420 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3));
421 _rtl92de_set_bcn_ctrl_reg(hw, BIT(4), 0);
422 tmp_reg422 = rtl_read_byte(rtlpriv,
423 REG_FWHW_TXQ_CTRL + 2);
424 if (tmp_reg422 & BIT(6))
425 recover = true;
426 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
427 tmp_reg422 & (~BIT(6)));
428 rtl92d_set_fw_rsvdpagepkt(hw, 0);
429 _rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0);
430 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(4));
431 if (recover)
432 rtl_write_byte(rtlpriv,
433 REG_FWHW_TXQ_CTRL + 2,
434 tmp_reg422);
435 rtl_write_byte(rtlpriv, REG_CR + 1,
436 (tmp_regcr & ~(BIT(0))));
437 }
438 rtl92d_set_fw_joinbss_report_cmd(hw, (*(u8 *) val));
439 break;
440 }
441 case HW_VAR_AID: {
442 u16 u2btmp;
443 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
444 u2btmp &= 0xC000;
445 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
446 mac->assoc_id));
447 break;
448 }
449 case HW_VAR_CORRECT_TSF: {
450 u8 btype_ibss = ((u8 *) (val))[0];
451
452 if (btype_ibss == true)
453 _rtl92de_stop_tx_beacon(hw);
454 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3));
455 rtl_write_dword(rtlpriv, REG_TSFTR,
456 (u32) (mac->tsf & 0xffffffff));
457 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
458 (u32) ((mac->tsf >> 32) & 0xffffffff));
459 _rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0);
460 if (btype_ibss == true)
461 _rtl92de_resume_tx_beacon(hw);
462
463 break;
464 }
465 case HW_VAR_INT_MIGRATION: {
466 bool int_migration = *(bool *) (val);
467
468 if (int_migration) {
469 /* Set interrrupt migration timer and
470 * corresponging Tx/Rx counter.
471 * timer 25ns*0xfa0=100us for 0xf packets.
472 * 0x306:Rx, 0x307:Tx */
473 rtl_write_dword(rtlpriv, REG_INT_MIG, 0xfe000fa0);
474 rtlpriv->dm.interrupt_migration = int_migration;
475 } else {
476 /* Reset all interrupt migration settings. */
477 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
478 rtlpriv->dm.interrupt_migration = int_migration;
479 }
480 break;
481 }
482 case HW_VAR_INT_AC: {
483 bool disable_ac_int = *((bool *) val);
484
485 /* Disable four ACs interrupts. */
486 if (disable_ac_int) {
487 /* Disable VO, VI, BE and BK four AC interrupts
488 * to gain more efficient CPU utilization.
489 * When extremely highly Rx OK occurs,
490 * we will disable Tx interrupts.
491 */
492 rtlpriv->cfg->ops->update_interrupt_mask(hw, 0,
493 RT_AC_INT_MASKS);
494 rtlpriv->dm.disable_tx_int = disable_ac_int;
495 /* Enable four ACs interrupts. */
496 } else {
497 rtlpriv->cfg->ops->update_interrupt_mask(hw,
498 RT_AC_INT_MASKS, 0);
499 rtlpriv->dm.disable_tx_int = disable_ac_int;
500 }
501 break;
502 }
503 default:
504 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
505 ("switch case not process\n"));
506 break;
507 }
508}
509
510static bool _rtl92de_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
511{
512 struct rtl_priv *rtlpriv = rtl_priv(hw);
513 bool status = true;
514 long count = 0;
515 u32 value = _LLT_INIT_ADDR(address) |
516 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
517
518 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
519 do {
520 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
521 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
522 break;
523 if (count > POLLING_LLT_THRESHOLD) {
524 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
525 ("Failed to polling write LLT done at "
526 "address %d!\n", address));
527 status = false;
528 break;
529 }
530 } while (++count);
531 return status;
532}
533
534static bool _rtl92de_llt_table_init(struct ieee80211_hw *hw)
535{
536 struct rtl_priv *rtlpriv = rtl_priv(hw);
537 unsigned short i;
538 u8 txpktbuf_bndy;
539 u8 maxPage;
540 bool status;
541 u32 value32; /* High+low page number */
542 u8 value8; /* normal page number */
543
544 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) {
545 maxPage = 255;
546 txpktbuf_bndy = 246;
547 value8 = 0;
548 value32 = 0x80bf0d29;
549 } else if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) {
550 maxPage = 127;
551 txpktbuf_bndy = 123;
552 value8 = 0;
553 value32 = 0x80750005;
554 }
555
556 /* Set reserved page for each queue */
557 /* 11. RQPN 0x200[31:0] = 0x80BD1C1C */
558 /* load RQPN */
559 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
560 rtl_write_dword(rtlpriv, REG_RQPN, value32);
561
562 /* 12. TXRKTBUG_PG_BNDY 0x114[31:0] = 0x27FF00F6 */
563 /* TXRKTBUG_PG_BNDY */
564 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY,
565 (rtl_read_word(rtlpriv, REG_TRXFF_BNDY + 2) << 16 |
566 txpktbuf_bndy));
567
568 /* 13. TDECTRL[15:8] 0x209[7:0] = 0xF6 */
569 /* Beacon Head for TXDMA */
570 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
571
572 /* 14. BCNQ_PGBNDY 0x424[7:0] = 0xF6 */
573 /* BCNQ_PGBNDY */
574 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
575 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
576
577 /* 15. WMAC_LBK_BF_HD 0x45D[7:0] = 0xF6 */
578 /* WMAC_LBK_BF_HD */
579 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
580
581 /* Set Tx/Rx page size (Tx must be 128 Bytes, */
582 /* Rx can be 64,128,256,512,1024 bytes) */
583 /* 16. PBP [7:0] = 0x11 */
584 /* TRX page size */
585 rtl_write_byte(rtlpriv, REG_PBP, 0x11);
586
587 /* 17. DRV_INFO_SZ = 0x04 */
588 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
589
590 /* 18. LLT_table_init(Adapter); */
591 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
592 status = _rtl92de_llt_write(hw, i, i + 1);
593 if (true != status)
594 return status;
595 }
596
597 /* end of list */
598 status = _rtl92de_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
599 if (true != status)
600 return status;
601
602 /* Make the other pages as ring buffer */
603 /* This ring buffer is used as beacon buffer if we */
604 /* config this MAC as two MAC transfer. */
605 /* Otherwise used as local loopback buffer. */
606 for (i = txpktbuf_bndy; i < maxPage; i++) {
607 status = _rtl92de_llt_write(hw, i, (i + 1));
608 if (true != status)
609 return status;
610 }
611
612 /* Let last entry point to the start entry of ring buffer */
613 status = _rtl92de_llt_write(hw, maxPage, txpktbuf_bndy);
614 if (true != status)
615 return status;
616
617 return true;
618}
619
620static void _rtl92de_gen_refresh_led_state(struct ieee80211_hw *hw)
621{
622 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
623 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
624 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
625 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
626
627 if (rtlpci->up_first_time)
628 return;
629 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
630 rtl92de_sw_led_on(hw, pLed0);
631 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
632 rtl92de_sw_led_on(hw, pLed0);
633 else
634 rtl92de_sw_led_off(hw, pLed0);
635}
636
637static bool _rtl92de_init_mac(struct ieee80211_hw *hw)
638{
639 struct rtl_priv *rtlpriv = rtl_priv(hw);
640 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
641 unsigned char bytetmp;
642 unsigned short wordtmp;
643 u16 retry;
644
645 rtl92d_phy_set_poweron(hw);
646 /* Add for resume sequence of power domain according
647 * to power document V11. Chapter V.11.... */
648 /* 0. RSV_CTRL 0x1C[7:0] = 0x00 */
649 /* unlock ISO/CLK/Power control register */
650 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
651 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x05);
652
653 /* 1. AFE_XTAL_CTRL [7:0] = 0x0F enable XTAL */
654 /* 2. SPS0_CTRL 0x11[7:0] = 0x2b enable SPS into PWM mode */
655 /* 3. delay (1ms) this is not necessary when initially power on */
656
657 /* C. Resume Sequence */
658 /* a. SPS0_CTRL 0x11[7:0] = 0x2b */
659 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
660
661 /* b. AFE_XTAL_CTRL [7:0] = 0x0F */
662 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F);
663
664 /* c. DRV runs power on init flow */
665
666 /* auto enable WLAN */
667 /* 4. APS_FSMCO 0x04[8] = 1; wait till 0x04[8] = 0 */
668 /* Power On Reset for MAC Block */
669 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0);
670 udelay(2);
671 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
672 udelay(2);
673
674 /* 5. Wait while 0x04[8] == 0 goto 2, otherwise goto 1 */
675 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
676 udelay(50);
677 retry = 0;
678 while ((bytetmp & BIT(0)) && retry < 1000) {
679 retry++;
680 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
681 udelay(50);
682 }
683
684 /* Enable Radio off, GPIO, and LED function */
685 /* 6. APS_FSMCO 0x04[15:0] = 0x0012 when enable HWPDN */
686 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012);
687
688 /* release RF digital isolation */
689 /* 7. SYS_ISO_CTRL 0x01[1] = 0x0; */
690 /*Set REG_SYS_ISO_CTRL 0x1=0x82 to prevent wake# problem. */
691 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82);
692 udelay(2);
693
694 /* make sure that BB reset OK. */
695 /* rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); */
696
697 /* Disable REG_CR before enable it to assure reset */
698 rtl_write_word(rtlpriv, REG_CR, 0x0);
699
700 /* Release MAC IO register reset */
701 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
702
703 /* clear stopping tx/rx dma */
704 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x0);
705
706 /* rtl_write_word(rtlpriv,REG_CR+2, 0x2); */
707
708 /* System init */
709 /* 18. LLT_table_init(Adapter); */
710 if (_rtl92de_llt_table_init(hw) == false)
711 return false;
712
713 /* Clear interrupt and enable interrupt */
714 /* 19. HISR 0x124[31:0] = 0xffffffff; */
715 /* HISRE 0x12C[7:0] = 0xFF */
716 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
717 rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
718
719 /* 20. HIMR 0x120[31:0] |= [enable INT mask bit map]; */
720 /* 21. HIMRE 0x128[7:0] = [enable INT mask bit map] */
721 /* The IMR should be enabled later after all init sequence
722 * is finished. */
723
724 /* 22. PCIE configuration space configuration */
725 /* 23. Ensure PCIe Device 0x80[15:0] = 0x0143 (ASPM+CLKREQ), */
726 /* and PCIe gated clock function is enabled. */
727 /* PCIE configuration space will be written after
728 * all init sequence.(Or by BIOS) */
729
730 rtl92d_phy_config_maccoexist_rfpage(hw);
731
732 /* THe below section is not related to power document Vxx . */
733 /* This is only useful for driver and OS setting. */
734 /* -------------------Software Relative Setting---------------------- */
735 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
736 wordtmp &= 0xf;
737 wordtmp |= 0xF771;
738 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
739
740 /* Reported Tx status from HW for rate adaptive. */
741 /* This should be realtive to power on step 14. But in document V11 */
742 /* still not contain the description.!!! */
743 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
744
745 /* Set Tx/Rx page size (Tx must be 128 Bytes,
746 * Rx can be 64,128,256,512,1024 bytes) */
747 /* rtl_write_byte(rtlpriv,REG_PBP, 0x11); */
748
749 /* Set RCR register */
750 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
751 /* rtl_write_byte(rtlpriv,REG_RX_DRVINFO_SZ, 4); */
752
753 /* Set TCR register */
754 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
755
756 /* disable earlymode */
757 rtl_write_byte(rtlpriv, 0x4d0, 0x0);
758
759 /* Set TX/RX descriptor physical address(from OS API). */
760 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
761 rtlpci->tx_ring[BEACON_QUEUE].dma);
762 rtl_write_dword(rtlpriv, REG_MGQ_DESA, rtlpci->tx_ring[MGNT_QUEUE].dma);
763 rtl_write_dword(rtlpriv, REG_VOQ_DESA, rtlpci->tx_ring[VO_QUEUE].dma);
764 rtl_write_dword(rtlpriv, REG_VIQ_DESA, rtlpci->tx_ring[VI_QUEUE].dma);
765 rtl_write_dword(rtlpriv, REG_BEQ_DESA, rtlpci->tx_ring[BE_QUEUE].dma);
766 rtl_write_dword(rtlpriv, REG_BKQ_DESA, rtlpci->tx_ring[BK_QUEUE].dma);
767 rtl_write_dword(rtlpriv, REG_HQ_DESA, rtlpci->tx_ring[HIGH_QUEUE].dma);
768 /* Set RX Desc Address */
769 rtl_write_dword(rtlpriv, REG_RX_DESA,
770 rtlpci->rx_ring[RX_MPDU_QUEUE].dma);
771
772 /* if we want to support 64 bit DMA, we should set it here,
773 * but now we do not support 64 bit DMA*/
774
775 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x33);
776
777 /* Reset interrupt migration setting when initialization */
778 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
779
780 /* Reconsider when to do this operation after asking HWSD. */
781 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
782 rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
783 do {
784 retry++;
785 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
786 } while ((retry < 200) && !(bytetmp & BIT(7)));
787
788 /* After MACIO reset,we must refresh LED state. */
789 _rtl92de_gen_refresh_led_state(hw);
790
791 /* Reset H2C protection register */
792 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
793
794 return true;
795}
796
797static void _rtl92de_hw_configure(struct ieee80211_hw *hw)
798{
799 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
800 struct rtl_priv *rtlpriv = rtl_priv(hw);
801 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
802 u8 reg_bw_opmode = BW_OPMODE_20MHZ;
803 u32 reg_rrsr;
804
805 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
806 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
807 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
808 rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
809 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
810 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
811 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
812 rtl_write_word(rtlpriv, REG_RL, 0x0707);
813 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
814 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
815 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
816 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
817 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
818 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
819 /* Aggregation threshold */
820 if (rtlhal->macphymode == DUALMAC_DUALPHY)
821 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb9726641);
822 else if (rtlhal->macphymode == DUALMAC_SINGLEPHY)
823 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x66626641);
824 else
825 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
826 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
827 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a);
828 rtlpci->reg_bcn_ctrl_val = 0x1f;
829 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
830 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
831 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
832 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
833 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
834 /* For throughput */
835 rtl_write_word(rtlpriv, REG_FAST_EDCA_CTRL, 0x6666);
836 /* ACKTO for IOT issue. */
837 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
838 /* Set Spec SIFS (used in NAV) */
839 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
840 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
841 /* Set SIFS for CCK */
842 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
843 /* Set SIFS for OFDM */
844 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
845 /* Set Multicast Address. */
846 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
847 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
848 switch (rtlpriv->phy.rf_type) {
849 case RF_1T2R:
850 case RF_1T1R:
851 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3);
852 break;
853 case RF_2T2R:
854 case RF_2T2R_GREEN:
855 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3);
856 break;
857 }
858}
859
860static void _rtl92de_enable_aspm_back_door(struct ieee80211_hw *hw)
861{
862 struct rtl_priv *rtlpriv = rtl_priv(hw);
863 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
864
865 rtl_write_byte(rtlpriv, 0x34b, 0x93);
866 rtl_write_word(rtlpriv, 0x350, 0x870c);
867 rtl_write_byte(rtlpriv, 0x352, 0x1);
868 if (ppsc->support_backdoor)
869 rtl_write_byte(rtlpriv, 0x349, 0x1b);
870 else
871 rtl_write_byte(rtlpriv, 0x349, 0x03);
872 rtl_write_word(rtlpriv, 0x350, 0x2718);
873 rtl_write_byte(rtlpriv, 0x352, 0x1);
874}
875
876void rtl92de_enable_hw_security_config(struct ieee80211_hw *hw)
877{
878 struct rtl_priv *rtlpriv = rtl_priv(hw);
879 u8 sec_reg_value;
880
881 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
882 ("PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
883 rtlpriv->sec.pairwise_enc_algorithm,
884 rtlpriv->sec.group_enc_algorithm));
885 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
886 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
887 ("not open hw encryption\n"));
888 return;
889 }
890 sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE;
891 if (rtlpriv->sec.use_defaultkey) {
892 sec_reg_value |= SCR_TXUSEDK;
893 sec_reg_value |= SCR_RXUSEDK;
894 }
895 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
896 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
897 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
898 ("The SECR-value %x\n", sec_reg_value));
899 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
900}
901
902int rtl92de_hw_init(struct ieee80211_hw *hw)
903{
904 struct rtl_priv *rtlpriv = rtl_priv(hw);
905 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
906 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
907 struct rtl_phy *rtlphy = &(rtlpriv->phy);
908 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
909 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
910 bool rtstatus = true;
911 u8 tmp_u1b;
912 int i;
913 int err;
914 unsigned long flags;
915
916 rtlpci->being_init_adapter = true;
917 rtlpci->init_ready = false;
918 spin_lock_irqsave(&globalmutex_for_power_and_efuse, flags);
919 /* we should do iqk after disable/enable */
920 rtl92d_phy_reset_iqk_result(hw);
921 /* rtlpriv->intf_ops->disable_aspm(hw); */
922 rtstatus = _rtl92de_init_mac(hw);
923 if (rtstatus != true) {
924 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Init MAC failed\n"));
925 err = 1;
926 spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags);
927 return err;
928 }
929 err = rtl92d_download_fw(hw);
930 spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags);
931 if (err) {
932 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
933 ("Failed to download FW. Init HW "
934 "without FW..\n"));
935 err = 1;
936 rtlhal->fw_ready = false;
937 } else {
938 rtlhal->fw_ready = true;
939 }
940 rtlhal->last_hmeboxnum = 0;
941 rtlpriv->psc.fw_current_inpsmode = false;
942
943 tmp_u1b = rtl_read_byte(rtlpriv, 0x605);
944 tmp_u1b = tmp_u1b | 0x30;
945 rtl_write_byte(rtlpriv, 0x605, tmp_u1b);
946
947 if (rtlhal->earlymode_enable) {
948 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
949 ("EarlyMode Enabled!!!\n"));
950
951 tmp_u1b = rtl_read_byte(rtlpriv, 0x4d0);
952 tmp_u1b = tmp_u1b | 0x1f;
953 rtl_write_byte(rtlpriv, 0x4d0, tmp_u1b);
954
955 rtl_write_byte(rtlpriv, 0x4d3, 0x80);
956
957 tmp_u1b = rtl_read_byte(rtlpriv, 0x605);
958 tmp_u1b = tmp_u1b | 0x40;
959 rtl_write_byte(rtlpriv, 0x605, tmp_u1b);
960 }
961
962 if (mac->rdg_en) {
963 rtl_write_byte(rtlpriv, REG_RD_CTRL, 0xff);
964 rtl_write_word(rtlpriv, REG_RD_NAV_NXT, 0x200);
965 rtl_write_byte(rtlpriv, REG_RD_RESP_PKT_TH, 0x05);
966 }
967
968 rtl92d_phy_mac_config(hw);
969 /* because last function modify RCR, so we update
970 * rcr var here, or TP will unstable for receive_config
971 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
972 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252*/
973 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
974 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
975
976 rtl92d_phy_bb_config(hw);
977
978 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
979 /* set before initialize RF */
980 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
981
982 /* config RF */
983 rtl92d_phy_rf_config(hw);
984
985 /* After read predefined TXT, we must set BB/MAC/RF
986 * register as our requirement */
987 /* After load BB,RF params,we need do more for 92D. */
988 rtl92d_update_bbrf_configuration(hw);
989 /* set default value after initialize RF, */
990 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0);
991 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
992 RF_CHNLBW, BRFREGOFFSETMASK);
993 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
994 RF_CHNLBW, BRFREGOFFSETMASK);
995
996 /*---- Set CCK and OFDM Block "ON"----*/
997 if (rtlhal->current_bandtype == BAND_ON_2_4G)
998 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
999 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1000 if (rtlhal->interfaceindex == 0) {
1001 /* RFPGA0_ANALOGPARAMETER2: cck clock select,
1002 * set to 20MHz by default */
1003 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
1004 BIT(11), 3);
1005 } else {
1006 /* Mac1 */
1007 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(11) |
1008 BIT(10), 3);
1009 }
1010
1011 _rtl92de_hw_configure(hw);
1012
1013 /* reset hw sec */
1014 rtl_cam_reset_all_entry(hw);
1015 rtl92de_enable_hw_security_config(hw);
1016
1017 /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */
1018 /* TX power index for different rate set. */
1019 rtl92d_phy_get_hw_reg_originalvalue(hw);
1020 rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel);
1021
1022 ppsc->rfpwr_state = ERFON;
1023
1024 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1025
1026 _rtl92de_enable_aspm_back_door(hw);
1027 /* rtlpriv->intf_ops->enable_aspm(hw); */
1028
1029 rtl92d_dm_init(hw);
1030 rtlpci->being_init_adapter = false;
1031
1032 if (ppsc->rfpwr_state == ERFON) {
1033 rtl92d_phy_lc_calibrate(hw);
1034 /* 5G and 2.4G must wait sometime to let RF LO ready */
1035 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
1036 u32 tmp_rega;
1037 for (i = 0; i < 10000; i++) {
1038 udelay(MAX_STALL_TIME);
1039
1040 tmp_rega = rtl_get_rfreg(hw,
1041 (enum radio_path)RF90_PATH_A,
1042 0x2a, BMASKDWORD);
1043
1044 if (((tmp_rega & BIT(11)) == BIT(11)))
1045 break;
1046 }
1047 }
1048 }
1049 rtlpci->init_ready = true;
1050 return err;
1051}
1052
1053static enum version_8192d _rtl92de_read_chip_version(struct ieee80211_hw *hw)
1054{
1055 struct rtl_priv *rtlpriv = rtl_priv(hw);
1056 enum version_8192d version = VERSION_NORMAL_CHIP_92D_SINGLEPHY;
1057 u32 value32;
1058
1059 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1060 if (!(value32 & 0x000f0000)) {
1061 version = VERSION_TEST_CHIP_92D_SINGLEPHY;
1062 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("TEST CHIP!!!\n"));
1063 } else {
1064 version = VERSION_NORMAL_CHIP_92D_SINGLEPHY;
1065 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Normal CHIP!!!\n"));
1066 }
1067 return version;
1068}
1069
1070static int _rtl92de_set_media_status(struct ieee80211_hw *hw,
1071 enum nl80211_iftype type)
1072{
1073 struct rtl_priv *rtlpriv = rtl_priv(hw);
1074 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1075 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1076 u8 bcnfunc_enable;
1077
1078 bt_msr &= 0xfc;
1079
1080 if (type == NL80211_IFTYPE_UNSPECIFIED ||
1081 type == NL80211_IFTYPE_STATION) {
1082 _rtl92de_stop_tx_beacon(hw);
1083 _rtl92de_enable_bcn_sub_func(hw);
1084 } else if (type == NL80211_IFTYPE_ADHOC ||
1085 type == NL80211_IFTYPE_AP) {
1086 _rtl92de_resume_tx_beacon(hw);
1087 _rtl92de_disable_bcn_sub_func(hw);
1088 } else {
1089 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1090 ("Set HW_VAR_MEDIA_STATUS: No such media "
1091 "status(%x).\n", type));
1092 }
1093 bcnfunc_enable = rtl_read_byte(rtlpriv, REG_BCN_CTRL);
1094 switch (type) {
1095 case NL80211_IFTYPE_UNSPECIFIED:
1096 bt_msr |= MSR_NOLINK;
1097 ledaction = LED_CTL_LINK;
1098 bcnfunc_enable &= 0xF7;
1099 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1100 ("Set Network type to NO LINK!\n"));
1101 break;
1102 case NL80211_IFTYPE_ADHOC:
1103 bt_msr |= MSR_ADHOC;
1104 bcnfunc_enable |= 0x08;
1105 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1106 ("Set Network type to Ad Hoc!\n"));
1107 break;
1108 case NL80211_IFTYPE_STATION:
1109 bt_msr |= MSR_INFRA;
1110 ledaction = LED_CTL_LINK;
1111 bcnfunc_enable &= 0xF7;
1112 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1113 ("Set Network type to STA!\n"));
1114 break;
1115 case NL80211_IFTYPE_AP:
1116 bt_msr |= MSR_AP;
1117 bcnfunc_enable |= 0x08;
1118 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1119 ("Set Network type to AP!\n"));
1120 break;
1121 default:
1122 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1123 ("Network type %d not support!\n", type));
1124 return 1;
1125 break;
1126
1127 }
1128 rtl_write_byte(rtlpriv, REG_CR + 2, bt_msr);
1129 rtlpriv->cfg->ops->led_control(hw, ledaction);
1130 if ((bt_msr & 0xfc) == MSR_AP)
1131 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1132 else
1133 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1134 return 0;
1135}
1136
1137void rtl92de_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1138{
1139 struct rtl_priv *rtlpriv = rtl_priv(hw);
1140 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1141 u32 reg_rcr = rtlpci->receive_config;
1142
1143 if (rtlpriv->psc.rfpwr_state != ERFON)
1144 return;
1145 if (check_bssid == true) {
1146 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1147 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1148 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(4));
1149 } else if (check_bssid == false) {
1150 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1151 _rtl92de_set_bcn_ctrl_reg(hw, BIT(4), 0);
1152 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1153 }
1154}
1155
1156int rtl92de_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1157{
1158 struct rtl_priv *rtlpriv = rtl_priv(hw);
1159
1160 if (_rtl92de_set_media_status(hw, type))
1161 return -EOPNOTSUPP;
1162
1163 /* check bssid */
1164 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1165 if (type != NL80211_IFTYPE_AP)
1166 rtl92de_set_check_bssid(hw, true);
1167 } else {
1168 rtl92de_set_check_bssid(hw, false);
1169 }
1170 return 0;
1171}
1172
1173/* do iqk or reload iqk */
1174/* windows just rtl92d_phy_reload_iqk_setting in set channel,
1175 * but it's very strict for time sequence so we add
1176 * rtl92d_phy_reload_iqk_setting here */
1177void rtl92d_linked_set_reg(struct ieee80211_hw *hw)
1178{
1179 struct rtl_priv *rtlpriv = rtl_priv(hw);
1180 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1181 u8 indexforchannel;
1182 u8 channel = rtlphy->current_channel;
1183
1184 indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel);
1185 if (!rtlphy->iqk_matrix_regsetting[indexforchannel].iqk_done) {
1186 RT_TRACE(rtlpriv, COMP_SCAN | COMP_INIT, DBG_DMESG,
1187 ("Do IQK for channel:%d.\n", channel));
1188 rtl92d_phy_iq_calibrate(hw);
1189 }
1190}
1191
1192/* don't set REG_EDCA_BE_PARAM here because
1193 * mac80211 will send pkt when scan */
1194void rtl92de_set_qos(struct ieee80211_hw *hw, int aci)
1195{
1196 struct rtl_priv *rtlpriv = rtl_priv(hw);
1197 rtl92d_dm_init_edca_turbo(hw);
1198 return;
1199 switch (aci) {
1200 case AC1_BK:
1201 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1202 break;
1203 case AC0_BE:
1204 break;
1205 case AC2_VI:
1206 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1207 break;
1208 case AC3_VO:
1209 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1210 break;
1211 default:
1212 RT_ASSERT(false, ("invalid aci: %d !\n", aci));
1213 break;
1214 }
1215}
1216
1217void rtl92de_enable_interrupt(struct ieee80211_hw *hw)
1218{
1219 struct rtl_priv *rtlpriv = rtl_priv(hw);
1220 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1221
1222 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1223 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1224 rtlpci->irq_enabled = true;
1225}
1226
1227void rtl92de_disable_interrupt(struct ieee80211_hw *hw)
1228{
1229 struct rtl_priv *rtlpriv = rtl_priv(hw);
1230 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1231
1232 rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
1233 rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
1234 rtlpci->irq_enabled = false;
1235 synchronize_irq(rtlpci->pdev->irq);
1236}
1237
1238static void _rtl92de_poweroff_adapter(struct ieee80211_hw *hw)
1239{
1240 struct rtl_priv *rtlpriv = rtl_priv(hw);
1241 u8 u1b_tmp;
1242 unsigned long flags;
1243
1244 rtlpriv->intf_ops->enable_aspm(hw);
1245 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1246 rtl_set_bbreg(hw, RFPGA0_XCD_RFPARAMETER, BIT(3), 0);
1247 rtl_set_bbreg(hw, RFPGA0_XCD_RFPARAMETER, BIT(15), 0);
1248
1249 /* 0x20:value 05-->04 */
1250 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04);
1251
1252 /* ==== Reset digital sequence ====== */
1253 rtl92d_firmware_selfreset(hw);
1254
1255 /* f. SYS_FUNC_EN 0x03[7:0]=0x51 reset MCU, MAC register, DCORE */
1256 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51);
1257
1258 /* g. MCUFWDL 0x80[1:0]=0 reset MCU ready status */
1259 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1260
1261 /* ==== Pull GPIO PIN to balance level and LED control ====== */
1262
1263 /* h. GPIO_PIN_CTRL 0x44[31:0]=0x000 */
1264 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000);
1265
1266 /* i. Value = GPIO_PIN_CTRL[7:0] */
1267 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL);
1268
1269 /* j. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); */
1270 /* write external PIN level */
1271 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL,
1272 0x00FF0000 | (u1b_tmp << 8));
1273
1274 /* k. GPIO_MUXCFG 0x42 [15:0] = 0x0780 */
1275 rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790);
1276
1277 /* l. LEDCFG 0x4C[15:0] = 0x8080 */
1278 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1279
1280 /* ==== Disable analog sequence === */
1281
1282 /* m. AFE_PLL_CTRL[7:0] = 0x80 disable PLL */
1283 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1284
1285 /* n. SPS0_CTRL 0x11[7:0] = 0x22 enter PFM mode */
1286 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1287
1288 /* o. AFE_XTAL_CTRL 0x24[7:0] = 0x0E disable XTAL, if No BT COEX */
1289 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e);
1290
1291 /* p. RSV_CTRL 0x1C[7:0] = 0x0E lock ISO/CLK/Power control register */
1292 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1293
1294 /* ==== interface into suspend === */
1295
1296 /* q. APS_FSMCO[15:8] = 0x58 PCIe suspend mode */
1297 /* According to power document V11, we need to set this */
1298 /* value as 0x18. Otherwise, we may not L0s sometimes. */
1299 /* This indluences power consumption. Bases on SD1's test, */
1300 /* set as 0x00 do not affect power current. And if it */
1301 /* is set as 0x18, they had ever met auto load fail problem. */
1302 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10);
1303
1304 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1305 ("In PowerOff,reg0x%x=%X\n", REG_SPS0_CTRL,
1306 rtl_read_byte(rtlpriv, REG_SPS0_CTRL)));
1307 /* r. Note: for PCIe interface, PON will not turn */
1308 /* off m-bias and BandGap in PCIe suspend mode. */
1309
1310 /* 0x17[7] 1b': power off in process 0b' : power off over */
1311 if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) {
1312 spin_lock_irqsave(&globalmutex_power, flags);
1313 u1b_tmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
1314 u1b_tmp &= (~BIT(7));
1315 rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1b_tmp);
1316 spin_unlock_irqrestore(&globalmutex_power, flags);
1317 }
1318
1319 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("<=======\n"));
1320}
1321
1322void rtl92de_card_disable(struct ieee80211_hw *hw)
1323{
1324 struct rtl_priv *rtlpriv = rtl_priv(hw);
1325 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1326 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1327 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1328 enum nl80211_iftype opmode;
1329
1330 mac->link_state = MAC80211_NOLINK;
1331 opmode = NL80211_IFTYPE_UNSPECIFIED;
1332 _rtl92de_set_media_status(hw, opmode);
1333
1334 if (rtlpci->driver_is_goingto_unload ||
1335 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1336 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1337 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1338 /* Power sequence for each MAC. */
1339 /* a. stop tx DMA */
1340 /* b. close RF */
1341 /* c. clear rx buf */
1342 /* d. stop rx DMA */
1343 /* e. reset MAC */
1344
1345 /* a. stop tx DMA */
1346 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1347 udelay(50);
1348
1349 /* b. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */
1350
1351 /* c. ========RF OFF sequence========== */
1352 /* 0x88c[23:20] = 0xf. */
1353 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
1354 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, BRFREGOFFSETMASK, 0x00);
1355
1356 /* APSD_CTRL 0x600[7:0] = 0x40 */
1357 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1358
1359 /* Close antenna 0,0xc04,0xd04 */
1360 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKBYTE0, 0);
1361 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0);
1362
1363 /* SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB state machine */
1364 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1365
1366 /* Mac0 can not do Global reset. Mac1 can do. */
1367 /* SYS_FUNC_EN 0x02[7:0] = 0xE0 reset BB state machine */
1368 if (rtlpriv->rtlhal.interfaceindex == 1)
1369 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0);
1370 udelay(50);
1371
1372 /* d. stop tx/rx dma before disable REG_CR (0x100) to fix */
1373 /* dma hang issue when disable/enable device. */
1374 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff);
1375 udelay(50);
1376 rtl_write_byte(rtlpriv, REG_CR, 0x0);
1377 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("==> Do power off.......\n"));
1378 if (rtl92d_phy_check_poweroff(hw))
1379 _rtl92de_poweroff_adapter(hw);
1380 return;
1381}
1382
1383void rtl92de_interrupt_recognized(struct ieee80211_hw *hw,
1384 u32 *p_inta, u32 *p_intb)
1385{
1386 struct rtl_priv *rtlpriv = rtl_priv(hw);
1387 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1388
1389 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1390 rtl_write_dword(rtlpriv, ISR, *p_inta);
1391
1392 /*
1393 * *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1394 * rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1395 */
1396}
1397
1398void rtl92de_set_beacon_related_registers(struct ieee80211_hw *hw)
1399{
1400 struct rtl_priv *rtlpriv = rtl_priv(hw);
1401 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1402 u16 bcn_interval, atim_window;
1403
1404 bcn_interval = mac->beacon_interval;
1405 atim_window = 2;
1406 /*rtl92de_disable_interrupt(hw); */
1407 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1408 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1409 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1410 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x20);
1411 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G)
1412 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x30);
1413 else
1414 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x20);
1415 rtl_write_byte(rtlpriv, 0x606, 0x30);
1416}
1417
1418void rtl92de_set_beacon_interval(struct ieee80211_hw *hw)
1419{
1420 struct rtl_priv *rtlpriv = rtl_priv(hw);
1421 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1422 u16 bcn_interval = mac->beacon_interval;
1423
1424 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1425 ("beacon_interval:%d\n", bcn_interval));
1426 /* rtl92de_disable_interrupt(hw); */
1427 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1428 /* rtl92de_enable_interrupt(hw); */
1429}
1430
1431void rtl92de_update_interrupt_mask(struct ieee80211_hw *hw,
1432 u32 add_msr, u32 rm_msr)
1433{
1434 struct rtl_priv *rtlpriv = rtl_priv(hw);
1435 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1436
1437 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1438 ("add_msr:%x, rm_msr:%x\n", add_msr, rm_msr));
1439 if (add_msr)
1440 rtlpci->irq_mask[0] |= add_msr;
1441 if (rm_msr)
1442 rtlpci->irq_mask[0] &= (~rm_msr);
1443 rtl92de_disable_interrupt(hw);
1444 rtl92de_enable_interrupt(hw);
1445}
1446
1447static void _rtl92de_readpowervalue_fromprom(struct txpower_info *pwrinfo,
1448 u8 *rom_content, bool autoLoadfail)
1449{
1450 u32 rfpath, eeaddr, group, offset1, offset2;
1451 u8 i;
1452
1453 memset(pwrinfo, 0, sizeof(struct txpower_info));
1454 if (autoLoadfail) {
1455 for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
1456 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1457 if (group < CHANNEL_GROUP_MAX_2G) {
1458 pwrinfo->cck_index[rfpath][group] =
1459 EEPROM_DEFAULT_TXPOWERLEVEL_2G;
1460 pwrinfo->ht40_1sindex[rfpath][group] =
1461 EEPROM_DEFAULT_TXPOWERLEVEL_2G;
1462 } else {
1463 pwrinfo->ht40_1sindex[rfpath][group] =
1464 EEPROM_DEFAULT_TXPOWERLEVEL_5G;
1465 }
1466 pwrinfo->ht40_2sindexdiff[rfpath][group] =
1467 EEPROM_DEFAULT_HT40_2SDIFF;
1468 pwrinfo->ht20indexdiff[rfpath][group] =
1469 EEPROM_DEFAULT_HT20_DIFF;
1470 pwrinfo->ofdmindexdiff[rfpath][group] =
1471 EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1472 pwrinfo->ht40maxoffset[rfpath][group] =
1473 EEPROM_DEFAULT_HT40_PWRMAXOFFSET;
1474 pwrinfo->ht20maxoffset[rfpath][group] =
1475 EEPROM_DEFAULT_HT20_PWRMAXOFFSET;
1476 }
1477 }
1478 for (i = 0; i < 3; i++) {
1479 pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI;
1480 pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI;
1481 }
1482 return;
1483 }
1484
1485 /* Maybe autoload OK,buf the tx power index value is not filled.
1486 * If we find it, we set it to default value. */
1487 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1488 for (group = 0; group < CHANNEL_GROUP_MAX_2G; group++) {
1489 eeaddr = EEPROM_CCK_TX_PWR_INX_2G + (rfpath * 3)
1490 + group;
1491 pwrinfo->cck_index[rfpath][group] =
1492 (rom_content[eeaddr] == 0xFF) ?
1493 (eeaddr > 0x7B ?
1494 EEPROM_DEFAULT_TXPOWERLEVEL_5G :
1495 EEPROM_DEFAULT_TXPOWERLEVEL_2G) :
1496 rom_content[eeaddr];
1497 }
1498 }
1499 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1500 for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
1501 offset1 = group / 3;
1502 offset2 = group % 3;
1503 eeaddr = EEPROM_HT40_1S_TX_PWR_INX_2G + (rfpath * 3) +
1504 offset2 + offset1 * 21;
1505 pwrinfo->ht40_1sindex[rfpath][group] =
1506 (rom_content[eeaddr] == 0xFF) ? (eeaddr > 0x7B ?
1507 EEPROM_DEFAULT_TXPOWERLEVEL_5G :
1508 EEPROM_DEFAULT_TXPOWERLEVEL_2G) :
1509 rom_content[eeaddr];
1510 }
1511 }
1512 /* These just for 92D efuse offset. */
1513 for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
1514 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1515 int base1 = EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G;
1516
1517 offset1 = group / 3;
1518 offset2 = group % 3;
1519
1520 if (rom_content[base1 + offset2 + offset1 * 21] != 0xFF)
1521 pwrinfo->ht40_2sindexdiff[rfpath][group] =
1522 (rom_content[base1 +
1523 offset2 + offset1 * 21] >> (rfpath * 4))
1524 & 0xF;
1525 else
1526 pwrinfo->ht40_2sindexdiff[rfpath][group] =
1527 EEPROM_DEFAULT_HT40_2SDIFF;
1528 if (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G + offset2
1529 + offset1 * 21] != 0xFF)
1530 pwrinfo->ht20indexdiff[rfpath][group] =
1531 (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G
1532 + offset2 + offset1 * 21] >> (rfpath * 4))
1533 & 0xF;
1534 else
1535 pwrinfo->ht20indexdiff[rfpath][group] =
1536 EEPROM_DEFAULT_HT20_DIFF;
1537 if (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G + offset2
1538 + offset1 * 21] != 0xFF)
1539 pwrinfo->ofdmindexdiff[rfpath][group] =
1540 (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G
1541 + offset2 + offset1 * 21] >> (rfpath * 4))
1542 & 0xF;
1543 else
1544 pwrinfo->ofdmindexdiff[rfpath][group] =
1545 EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1546 if (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G + offset2
1547 + offset1 * 21] != 0xFF)
1548 pwrinfo->ht40maxoffset[rfpath][group] =
1549 (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G
1550 + offset2 + offset1 * 21] >> (rfpath * 4))
1551 & 0xF;
1552 else
1553 pwrinfo->ht40maxoffset[rfpath][group] =
1554 EEPROM_DEFAULT_HT40_PWRMAXOFFSET;
1555 if (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G + offset2
1556 + offset1 * 21] != 0xFF)
1557 pwrinfo->ht20maxoffset[rfpath][group] =
1558 (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G +
1559 offset2 + offset1 * 21] >> (rfpath * 4)) &
1560 0xF;
1561 else
1562 pwrinfo->ht20maxoffset[rfpath][group] =
1563 EEPROM_DEFAULT_HT20_PWRMAXOFFSET;
1564 }
1565 }
1566 if (rom_content[EEPROM_TSSI_A_5G] != 0xFF) {
1567 /* 5GL */
1568 pwrinfo->tssi_a[0] = rom_content[EEPROM_TSSI_A_5G] & 0x3F;
1569 pwrinfo->tssi_b[0] = rom_content[EEPROM_TSSI_B_5G] & 0x3F;
1570 /* 5GM */
1571 pwrinfo->tssi_a[1] = rom_content[EEPROM_TSSI_AB_5G] & 0x3F;
1572 pwrinfo->tssi_b[1] =
1573 (rom_content[EEPROM_TSSI_AB_5G] & 0xC0) >> 6 |
1574 (rom_content[EEPROM_TSSI_AB_5G + 1] & 0x0F) << 2;
1575 /* 5GH */
1576 pwrinfo->tssi_a[2] = (rom_content[EEPROM_TSSI_AB_5G + 1] &
1577 0xF0) >> 4 |
1578 (rom_content[EEPROM_TSSI_AB_5G + 2] & 0x03) << 4;
1579 pwrinfo->tssi_b[2] = (rom_content[EEPROM_TSSI_AB_5G + 2] &
1580 0xFC) >> 2;
1581 } else {
1582 for (i = 0; i < 3; i++) {
1583 pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI;
1584 pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI;
1585 }
1586 }
1587}
1588
1589static void _rtl92de_read_txpower_info(struct ieee80211_hw *hw,
1590 bool autoload_fail, u8 *hwinfo)
1591{
1592 struct rtl_priv *rtlpriv = rtl_priv(hw);
1593 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1594 struct txpower_info pwrinfo;
1595 u8 tempval[2], i, pwr, diff;
1596 u32 ch, rfPath, group;
1597
1598 _rtl92de_readpowervalue_fromprom(&pwrinfo, hwinfo, autoload_fail);
1599 if (!autoload_fail) {
1600 /* bit0~2 */
1601 rtlefuse->eeprom_regulatory = (hwinfo[EEPROM_RF_OPT1] & 0x7);
1602 rtlefuse->eeprom_thermalmeter =
1603 hwinfo[EEPROM_THERMAL_METER] & 0x1f;
1604 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_K];
1605 tempval[0] = hwinfo[EEPROM_IQK_DELTA] & 0x03;
1606 tempval[1] = (hwinfo[EEPROM_LCK_DELTA] & 0x0C) >> 2;
1607 rtlefuse->txpwr_fromeprom = true;
1608 if (IS_92D_D_CUT(rtlpriv->rtlhal.version)) {
1609 rtlefuse->internal_pa_5g[0] =
1610 !((hwinfo[EEPROM_TSSI_A_5G] &
1611 BIT(6)) >> 6);
1612 rtlefuse->internal_pa_5g[1] =
1613 !((hwinfo[EEPROM_TSSI_B_5G] &
1614 BIT(6)) >> 6);
1615 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1616 ("Is D cut,Internal PA0 %d Internal PA1 %d\n",
1617 rtlefuse->internal_pa_5g[0],
1618 rtlefuse->internal_pa_5g[1]))
1619 }
1620 rtlefuse->eeprom_c9 = hwinfo[EEPROM_RF_OPT6];
1621 rtlefuse->eeprom_cc = hwinfo[EEPROM_RF_OPT7];
1622 } else {
1623 rtlefuse->eeprom_regulatory = 0;
1624 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1625 rtlefuse->crystalcap = EEPROM_DEFAULT_CRYSTALCAP;
1626 tempval[0] = tempval[1] = 3;
1627 }
1628
1629 /* Use default value to fill parameters if
1630 * efuse is not filled on some place. */
1631
1632 /* ThermalMeter from EEPROM */
1633 if (rtlefuse->eeprom_thermalmeter < 0x06 ||
1634 rtlefuse->eeprom_thermalmeter > 0x1c)
1635 rtlefuse->eeprom_thermalmeter = 0x12;
1636 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1637
1638 /* check XTAL_K */
1639 if (rtlefuse->crystalcap == 0xFF)
1640 rtlefuse->crystalcap = 0;
1641 if (rtlefuse->eeprom_regulatory > 3)
1642 rtlefuse->eeprom_regulatory = 0;
1643
1644 for (i = 0; i < 2; i++) {
1645 switch (tempval[i]) {
1646 case 0:
1647 tempval[i] = 5;
1648 break;
1649 case 1:
1650 tempval[i] = 4;
1651 break;
1652 case 2:
1653 tempval[i] = 3;
1654 break;
1655 case 3:
1656 default:
1657 tempval[i] = 0;
1658 break;
1659 }
1660 }
1661
1662 rtlefuse->delta_iqk = tempval[0];
1663 if (tempval[1] > 0)
1664 rtlefuse->delta_lck = tempval[1] - 1;
1665 if (rtlefuse->eeprom_c9 == 0xFF)
1666 rtlefuse->eeprom_c9 = 0x00;
1667 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1668 ("EEPROMRegulatory = 0x%x\n", rtlefuse->eeprom_regulatory));
1669 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1670 ("ThermalMeter = 0x%x\n", rtlefuse->eeprom_thermalmeter));
1671 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1672 ("CrystalCap = 0x%x\n", rtlefuse->crystalcap));
1673 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1674 ("Delta_IQK = 0x%x Delta_LCK = 0x%x\n", rtlefuse->delta_iqk,
1675 rtlefuse->delta_lck));
1676
1677 for (rfPath = 0; rfPath < RF6052_MAX_PATH; rfPath++) {
1678 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
1679 group = rtl92d_get_chnlgroup_fromarray((u8) ch);
1680 if (ch < CHANNEL_MAX_NUMBER_2G)
1681 rtlefuse->txpwrlevel_cck[rfPath][ch] =
1682 pwrinfo.cck_index[rfPath][group];
1683 rtlefuse->txpwrlevel_ht40_1s[rfPath][ch] =
1684 pwrinfo.ht40_1sindex[rfPath][group];
1685 rtlefuse->txpwr_ht20diff[rfPath][ch] =
1686 pwrinfo.ht20indexdiff[rfPath][group];
1687 rtlefuse->txpwr_legacyhtdiff[rfPath][ch] =
1688 pwrinfo.ofdmindexdiff[rfPath][group];
1689 rtlefuse->pwrgroup_ht20[rfPath][ch] =
1690 pwrinfo.ht20maxoffset[rfPath][group];
1691 rtlefuse->pwrgroup_ht40[rfPath][ch] =
1692 pwrinfo.ht40maxoffset[rfPath][group];
1693 pwr = pwrinfo.ht40_1sindex[rfPath][group];
1694 diff = pwrinfo.ht40_2sindexdiff[rfPath][group];
1695 rtlefuse->txpwrlevel_ht40_2s[rfPath][ch] =
1696 (pwr > diff) ? (pwr - diff) : 0;
1697 }
1698 }
1699}
1700
1701static void _rtl92de_read_macphymode_from_prom(struct ieee80211_hw *hw,
1702 u8 *content)
1703{
1704 struct rtl_priv *rtlpriv = rtl_priv(hw);
1705 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1706 u8 macphy_crvalue = content[EEPROM_MAC_FUNCTION];
1707
1708 if (macphy_crvalue & BIT(3)) {
1709 rtlhal->macphymode = SINGLEMAC_SINGLEPHY;
1710 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1711 ("MacPhyMode SINGLEMAC_SINGLEPHY\n"));
1712 } else {
1713 rtlhal->macphymode = DUALMAC_DUALPHY;
1714 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1715 ("MacPhyMode DUALMAC_DUALPHY\n"));
1716 }
1717}
1718
1719static void _rtl92de_read_macphymode_and_bandtype(struct ieee80211_hw *hw,
1720 u8 *content)
1721{
1722 _rtl92de_read_macphymode_from_prom(hw, content);
1723 rtl92d_phy_config_macphymode(hw);
1724 rtl92d_phy_config_macphymode_info(hw);
1725}
1726
1727static void _rtl92de_efuse_update_chip_version(struct ieee80211_hw *hw)
1728{
1729 struct rtl_priv *rtlpriv = rtl_priv(hw);
1730 enum version_8192d chipver = rtlpriv->rtlhal.version;
1731 u8 cutvalue[2];
1732 u16 chipvalue;
1733
1734 rtlpriv->intf_ops->read_efuse_byte(hw, EEPROME_CHIP_VERSION_H,
1735 &cutvalue[1]);
1736 rtlpriv->intf_ops->read_efuse_byte(hw, EEPROME_CHIP_VERSION_L,
1737 &cutvalue[0]);
1738 chipvalue = (cutvalue[1] << 8) | cutvalue[0];
1739 switch (chipvalue) {
1740 case 0xAA55:
1741 chipver |= CHIP_92D_C_CUT;
1742 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("C-CUT!!!\n"));
1743 break;
1744 case 0x9966:
1745 chipver |= CHIP_92D_D_CUT;
1746 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("D-CUT!!!\n"));
1747 break;
1748 default:
1749 chipver |= CHIP_92D_D_CUT;
1750 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, ("Unkown CUT!\n"));
1751 break;
1752 }
1753 rtlpriv->rtlhal.version = chipver;
1754}
1755
1756static void _rtl92de_read_adapter_info(struct ieee80211_hw *hw)
1757{
1758 struct rtl_priv *rtlpriv = rtl_priv(hw);
1759 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1760 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1761 u16 i, usvalue;
1762 u8 hwinfo[HWSET_MAX_SIZE];
1763 u16 eeprom_id;
1764 unsigned long flags;
1765
1766 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1767 spin_lock_irqsave(&globalmutex_for_power_and_efuse, flags);
1768 rtl_efuse_shadow_map_update(hw);
1769 _rtl92de_efuse_update_chip_version(hw);
1770 spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags);
1771 memcpy((void *)hwinfo, (void *)&rtlefuse->efuse_map
1772 [EFUSE_INIT_MAP][0],
1773 HWSET_MAX_SIZE);
1774 } else if (rtlefuse->epromtype == EEPROM_93C46) {
1775 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1776 ("RTL819X Not boot from eeprom, check it !!"));
1777 }
1778 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, ("MAP\n"),
1779 hwinfo, HWSET_MAX_SIZE);
1780
1781 eeprom_id = *((u16 *)&hwinfo[0]);
1782 if (eeprom_id != RTL8190_EEPROM_ID) {
1783 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1784 ("EEPROM ID(%#x) is invalid!!\n", eeprom_id));
1785 rtlefuse->autoload_failflag = true;
1786 } else {
1787 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
1788 rtlefuse->autoload_failflag = false;
1789 }
1790 if (rtlefuse->autoload_failflag == true) {
1791 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1792 ("RTL819X Not boot from eeprom, check it !!"));
1793 return;
1794 }
1795 rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
1796 _rtl92de_read_macphymode_and_bandtype(hw, hwinfo);
1797
1798 /* VID, DID SE 0xA-D */
1799 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
1800 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
1801 rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
1802 rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
1803 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1804 ("EEPROMId = 0x%4x\n", eeprom_id));
1805 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1806 ("EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid));
1807 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1808 ("EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did));
1809 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1810 ("EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid));
1811 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1812 ("EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid));
1813
1814 /* Read Permanent MAC address */
1815 if (rtlhal->interfaceindex == 0) {
1816 for (i = 0; i < 6; i += 2) {
1817 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR_MAC0_92D + i];
1818 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1819 }
1820 } else {
1821 for (i = 0; i < 6; i += 2) {
1822 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR_MAC1_92D + i];
1823 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1824 }
1825 }
1826 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR,
1827 rtlefuse->dev_addr);
1828 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1829 (MAC_FMT "\n", MAC_ARG(rtlefuse->dev_addr)));
1830 _rtl92de_read_txpower_info(hw, rtlefuse->autoload_failflag, hwinfo);
1831
1832 /* Read Channel Plan */
1833 switch (rtlhal->bandset) {
1834 case BAND_ON_2_4G:
1835 rtlefuse->channel_plan = COUNTRY_CODE_TELEC;
1836 break;
1837 case BAND_ON_5G:
1838 rtlefuse->channel_plan = COUNTRY_CODE_FCC;
1839 break;
1840 case BAND_ON_BOTH:
1841 rtlefuse->channel_plan = COUNTRY_CODE_FCC;
1842 break;
1843 default:
1844 rtlefuse->channel_plan = COUNTRY_CODE_FCC;
1845 break;
1846 }
1847 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1848 rtlefuse->txpwr_fromeprom = true;
1849 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1850 ("EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid));
1851}
1852
1853void rtl92de_read_eeprom_info(struct ieee80211_hw *hw)
1854{
1855 struct rtl_priv *rtlpriv = rtl_priv(hw);
1856 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1857 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1858 u8 tmp_u1b;
1859
1860 rtlhal->version = _rtl92de_read_chip_version(hw);
1861 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1862 rtlefuse->autoload_status = tmp_u1b;
1863 if (tmp_u1b & BIT(4)) {
1864 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from EEPROM\n"));
1865 rtlefuse->epromtype = EEPROM_93C46;
1866 } else {
1867 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from EFUSE\n"));
1868 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1869 }
1870 if (tmp_u1b & BIT(5)) {
1871 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
1872
1873 rtlefuse->autoload_failflag = false;
1874 _rtl92de_read_adapter_info(hw);
1875 } else {
1876 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Autoload ERR!!\n"));
1877 }
1878 return;
1879}
1880
1881static void rtl92de_update_hal_rate_table(struct ieee80211_hw *hw,
1882 struct ieee80211_sta *sta)
1883{
1884 struct rtl_priv *rtlpriv = rtl_priv(hw);
1885 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1886 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1887 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1888 u32 ratr_value;
1889 u8 ratr_index = 0;
1890 u8 nmode = mac->ht_enable;
1891 u8 mimo_ps = IEEE80211_SMPS_OFF;
1892 u16 shortgi_rate;
1893 u32 tmp_ratr_value;
1894 u8 curtxbw_40mhz = mac->bw_40;
1895 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1896 1 : 0;
1897 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1898 1 : 0;
1899 enum wireless_mode wirelessmode = mac->mode;
1900
1901 if (rtlhal->current_bandtype == BAND_ON_5G)
1902 ratr_value = sta->supp_rates[1] << 4;
1903 else
1904 ratr_value = sta->supp_rates[0];
1905 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1906 sta->ht_cap.mcs.rx_mask[0] << 12);
1907 switch (wirelessmode) {
1908 case WIRELESS_MODE_A:
1909 ratr_value &= 0x00000FF0;
1910 break;
1911 case WIRELESS_MODE_B:
1912 if (ratr_value & 0x0000000c)
1913 ratr_value &= 0x0000000d;
1914 else
1915 ratr_value &= 0x0000000f;
1916 break;
1917 case WIRELESS_MODE_G:
1918 ratr_value &= 0x00000FF5;
1919 break;
1920 case WIRELESS_MODE_N_24G:
1921 case WIRELESS_MODE_N_5G:
1922 nmode = 1;
1923 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1924 ratr_value &= 0x0007F005;
1925 } else {
1926 u32 ratr_mask;
1927
1928 if (get_rf_type(rtlphy) == RF_1T2R ||
1929 get_rf_type(rtlphy) == RF_1T1R) {
1930 ratr_mask = 0x000ff005;
1931 } else {
1932 ratr_mask = 0x0f0ff005;
1933 }
1934
1935 ratr_value &= ratr_mask;
1936 }
1937 break;
1938 default:
1939 if (rtlphy->rf_type == RF_1T2R)
1940 ratr_value &= 0x000ff0ff;
1941 else
1942 ratr_value &= 0x0f0ff0ff;
1943
1944 break;
1945 }
1946 ratr_value &= 0x0FFFFFFF;
1947 if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) ||
1948 (!curtxbw_40mhz && curshortgi_20mhz))) {
1949 ratr_value |= 0x10000000;
1950 tmp_ratr_value = (ratr_value >> 12);
1951 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1952 if ((1 << shortgi_rate) & tmp_ratr_value)
1953 break;
1954 }
1955 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1956 (shortgi_rate << 4) | (shortgi_rate);
1957 }
1958 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1959 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1960 ("%x\n", rtl_read_dword(rtlpriv, REG_ARFR0)));
1961}
1962
1963static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw,
1964 struct ieee80211_sta *sta, u8 rssi_level)
1965{
1966 struct rtl_priv *rtlpriv = rtl_priv(hw);
1967 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1968 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1969 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1970 struct rtl_sta_info *sta_entry = NULL;
1971 u32 ratr_bitmap;
1972 u8 ratr_index;
1973 u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
1974 ? 1 : 0;
1975 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1976 1 : 0;
1977 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1978 1 : 0;
1979 enum wireless_mode wirelessmode = 0;
1980 bool shortgi = false;
1981 u32 value[2];
1982 u8 macid = 0;
1983 u8 mimo_ps = IEEE80211_SMPS_OFF;
1984
1985 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
1986 mimo_ps = sta_entry->mimo_ps;
1987 wirelessmode = sta_entry->wireless_mode;
1988 if (mac->opmode == NL80211_IFTYPE_STATION)
1989 curtxbw_40mhz = mac->bw_40;
1990 else if (mac->opmode == NL80211_IFTYPE_AP ||
1991 mac->opmode == NL80211_IFTYPE_ADHOC)
1992 macid = sta->aid + 1;
1993
1994 if (rtlhal->current_bandtype == BAND_ON_5G)
1995 ratr_bitmap = sta->supp_rates[1] << 4;
1996 else
1997 ratr_bitmap = sta->supp_rates[0];
1998 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1999 sta->ht_cap.mcs.rx_mask[0] << 12);
2000 switch (wirelessmode) {
2001 case WIRELESS_MODE_B:
2002 ratr_index = RATR_INX_WIRELESS_B;
2003 if (ratr_bitmap & 0x0000000c)
2004 ratr_bitmap &= 0x0000000d;
2005 else
2006 ratr_bitmap &= 0x0000000f;
2007 break;
2008 case WIRELESS_MODE_G:
2009 ratr_index = RATR_INX_WIRELESS_GB;
2010
2011 if (rssi_level == 1)
2012 ratr_bitmap &= 0x00000f00;
2013 else if (rssi_level == 2)
2014 ratr_bitmap &= 0x00000ff0;
2015 else
2016 ratr_bitmap &= 0x00000ff5;
2017 break;
2018 case WIRELESS_MODE_A:
2019 ratr_index = RATR_INX_WIRELESS_G;
2020 ratr_bitmap &= 0x00000ff0;
2021 break;
2022 case WIRELESS_MODE_N_24G:
2023 case WIRELESS_MODE_N_5G:
2024 if (wirelessmode == WIRELESS_MODE_N_24G)
2025 ratr_index = RATR_INX_WIRELESS_NGB;
2026 else
2027 ratr_index = RATR_INX_WIRELESS_NG;
2028 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2029 if (rssi_level == 1)
2030 ratr_bitmap &= 0x00070000;
2031 else if (rssi_level == 2)
2032 ratr_bitmap &= 0x0007f000;
2033 else
2034 ratr_bitmap &= 0x0007f005;
2035 } else {
2036 if (rtlphy->rf_type == RF_1T2R ||
2037 rtlphy->rf_type == RF_1T1R) {
2038 if (curtxbw_40mhz) {
2039 if (rssi_level == 1)
2040 ratr_bitmap &= 0x000f0000;
2041 else if (rssi_level == 2)
2042 ratr_bitmap &= 0x000ff000;
2043 else
2044 ratr_bitmap &= 0x000ff015;
2045 } else {
2046 if (rssi_level == 1)
2047 ratr_bitmap &= 0x000f0000;
2048 else if (rssi_level == 2)
2049 ratr_bitmap &= 0x000ff000;
2050 else
2051 ratr_bitmap &= 0x000ff005;
2052 }
2053 } else {
2054 if (curtxbw_40mhz) {
2055 if (rssi_level == 1)
2056 ratr_bitmap &= 0x0f0f0000;
2057 else if (rssi_level == 2)
2058 ratr_bitmap &= 0x0f0ff000;
2059 else
2060 ratr_bitmap &= 0x0f0ff015;
2061 } else {
2062 if (rssi_level == 1)
2063 ratr_bitmap &= 0x0f0f0000;
2064 else if (rssi_level == 2)
2065 ratr_bitmap &= 0x0f0ff000;
2066 else
2067 ratr_bitmap &= 0x0f0ff005;
2068 }
2069 }
2070 }
2071 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2072 (!curtxbw_40mhz && curshortgi_20mhz)) {
2073
2074 if (macid == 0)
2075 shortgi = true;
2076 else if (macid == 1)
2077 shortgi = false;
2078 }
2079 break;
2080 default:
2081 ratr_index = RATR_INX_WIRELESS_NGB;
2082
2083 if (rtlphy->rf_type == RF_1T2R)
2084 ratr_bitmap &= 0x000ff0ff;
2085 else
2086 ratr_bitmap &= 0x0f0ff0ff;
2087 break;
2088 }
2089
2090 value[0] = (ratr_bitmap & 0x0fffffff) | (ratr_index << 28);
2091 value[1] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2092 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2093 ("ratr_bitmap :%x value0:%x value1:%x\n",
2094 ratr_bitmap, value[0], value[1]));
2095 rtl92d_fill_h2c_cmd(hw, H2C_RA_MASK, 5, (u8 *) value);
2096 if (macid != 0)
2097 sta_entry->ratr_index = ratr_index;
2098}
2099
2100void rtl92de_update_hal_rate_tbl(struct ieee80211_hw *hw,
2101 struct ieee80211_sta *sta, u8 rssi_level)
2102{
2103 struct rtl_priv *rtlpriv = rtl_priv(hw);
2104
2105 if (rtlpriv->dm.useramask)
2106 rtl92de_update_hal_rate_mask(hw, sta, rssi_level);
2107 else
2108 rtl92de_update_hal_rate_table(hw, sta);
2109}
2110
2111void rtl92de_update_channel_access_setting(struct ieee80211_hw *hw)
2112{
2113 struct rtl_priv *rtlpriv = rtl_priv(hw);
2114 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2115 u16 sifs_timer;
2116
2117 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2118 (u8 *)&mac->slot_time);
2119 if (!mac->ht_enable)
2120 sifs_timer = 0x0a0a;
2121 else
2122 sifs_timer = 0x1010;
2123 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2124}
2125
2126bool rtl92de_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2127{
2128 struct rtl_priv *rtlpriv = rtl_priv(hw);
2129 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2130 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2131 enum rf_pwrstate e_rfpowerstate_toset;
2132 u8 u1tmp;
2133 bool actuallyset = false;
2134 unsigned long flag;
2135
2136 if (rtlpci->being_init_adapter)
2137 return false;
2138 if (ppsc->swrf_processing)
2139 return false;
2140 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2141 if (ppsc->rfchange_inprogress) {
2142 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2143 return false;
2144 } else {
2145 ppsc->rfchange_inprogress = true;
2146 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2147 }
2148 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv,
2149 REG_MAC_PINMUX_CFG) & ~(BIT(3)));
2150 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2151 e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF;
2152 if ((ppsc->hwradiooff == true) && (e_rfpowerstate_toset == ERFON)) {
2153 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2154 ("GPIOChangeRF - HW Radio ON, RF ON\n"));
2155 e_rfpowerstate_toset = ERFON;
2156 ppsc->hwradiooff = false;
2157 actuallyset = true;
2158 } else if ((ppsc->hwradiooff == false)
2159 && (e_rfpowerstate_toset == ERFOFF)) {
2160 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2161 ("GPIOChangeRF - HW Radio OFF, RF OFF\n"));
2162 e_rfpowerstate_toset = ERFOFF;
2163 ppsc->hwradiooff = true;
2164 actuallyset = true;
2165 }
2166 if (actuallyset) {
2167 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2168 ppsc->rfchange_inprogress = false;
2169 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2170 } else {
2171 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2172 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2173 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2174 ppsc->rfchange_inprogress = false;
2175 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2176 }
2177 *valid = 1;
2178 return !ppsc->hwradiooff;
2179}
2180
2181void rtl92de_set_key(struct ieee80211_hw *hw, u32 key_index,
2182 u8 *p_macaddr, bool is_group, u8 enc_algo,
2183 bool is_wepkey, bool clear_all)
2184{
2185 struct rtl_priv *rtlpriv = rtl_priv(hw);
2186 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2187 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2188 u8 *macaddr = p_macaddr;
2189 u32 entry_id;
2190 bool is_pairwise = false;
2191 static u8 cam_const_addr[4][6] = {
2192 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2193 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2194 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2195 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2196 };
2197 static u8 cam_const_broad[] = {
2198 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2199 };
2200
2201 if (clear_all) {
2202 u8 idx;
2203 u8 cam_offset = 0;
2204 u8 clear_number = 5;
2205 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, ("clear_all\n"));
2206 for (idx = 0; idx < clear_number; idx++) {
2207 rtl_cam_mark_invalid(hw, cam_offset + idx);
2208 rtl_cam_empty_entry(hw, cam_offset + idx);
2209
2210 if (idx < 5) {
2211 memset(rtlpriv->sec.key_buf[idx], 0,
2212 MAX_KEY_LEN);
2213 rtlpriv->sec.key_len[idx] = 0;
2214 }
2215 }
2216 } else {
2217 switch (enc_algo) {
2218 case WEP40_ENCRYPTION:
2219 enc_algo = CAM_WEP40;
2220 break;
2221 case WEP104_ENCRYPTION:
2222 enc_algo = CAM_WEP104;
2223 break;
2224 case TKIP_ENCRYPTION:
2225 enc_algo = CAM_TKIP;
2226 break;
2227 case AESCCMP_ENCRYPTION:
2228 enc_algo = CAM_AES;
2229 break;
2230 default:
2231 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("switch case "
2232 "not process\n"));
2233 enc_algo = CAM_TKIP;
2234 break;
2235 }
2236 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2237 macaddr = cam_const_addr[key_index];
2238 entry_id = key_index;
2239 } else {
2240 if (is_group) {
2241 macaddr = cam_const_broad;
2242 entry_id = key_index;
2243 } else {
2244 if (mac->opmode == NL80211_IFTYPE_AP) {
2245 entry_id = rtl_cam_get_free_entry(hw,
2246 p_macaddr);
2247 if (entry_id >= TOTAL_CAM_ENTRY) {
2248 RT_TRACE(rtlpriv, COMP_SEC,
2249 DBG_EMERG, ("Can not "
2250 "find free hw security"
2251 " cam entry\n"));
2252 return;
2253 }
2254 } else {
2255 entry_id = CAM_PAIRWISE_KEY_POSITION;
2256 }
2257 key_index = PAIRWISE_KEYIDX;
2258 is_pairwise = true;
2259 }
2260 }
2261 if (rtlpriv->sec.key_len[key_index] == 0) {
2262 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2263 ("delete one entry, entry_id is %d\n",
2264 entry_id));
2265 if (mac->opmode == NL80211_IFTYPE_AP)
2266 rtl_cam_del_entry(hw, p_macaddr);
2267 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2268 } else {
2269 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2270 ("The insert KEY length is %d\n",
2271 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]));
2272 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2273 ("The insert KEY is %x %x\n",
2274 rtlpriv->sec.key_buf[0][0],
2275 rtlpriv->sec.key_buf[0][1]));
2276 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2277 ("add one entry\n"));
2278 if (is_pairwise) {
2279 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2280 "Pairwiase Key content :",
2281 rtlpriv->sec.pairwise_key,
2282 rtlpriv->
2283 sec.key_len[PAIRWISE_KEYIDX]);
2284 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2285 ("set Pairwiase key\n"));
2286 rtl_cam_add_one_entry(hw, macaddr, key_index,
2287 entry_id, enc_algo,
2288 CAM_CONFIG_NO_USEDK,
2289 rtlpriv->
2290 sec.key_buf[key_index]);
2291 } else {
2292 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2293 ("set group key\n"));
2294 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2295 rtl_cam_add_one_entry(hw,
2296 rtlefuse->dev_addr,
2297 PAIRWISE_KEYIDX,
2298 CAM_PAIRWISE_KEY_POSITION,
2299 enc_algo, CAM_CONFIG_NO_USEDK,
2300 rtlpriv->sec.key_buf[entry_id]);
2301 }
2302 rtl_cam_add_one_entry(hw, macaddr, key_index,
2303 entry_id, enc_algo,
2304 CAM_CONFIG_NO_USEDK,
2305 rtlpriv->sec.key_buf
2306 [entry_id]);
2307 }
2308 }
2309 }
2310}
2311
2312void rtl92de_suspend(struct ieee80211_hw *hw)
2313{
2314 struct rtl_priv *rtlpriv = rtl_priv(hw);
2315
2316 rtlpriv->rtlhal.macphyctl_reg = rtl_read_byte(rtlpriv,
2317 REG_MAC_PHY_CTRL_NORMAL);
2318}
2319
2320void rtl92de_resume(struct ieee80211_hw *hw)
2321{
2322 struct rtl_priv *rtlpriv = rtl_priv(hw);
2323
2324 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL,
2325 rtlpriv->rtlhal.macphyctl_reg);
2326}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/hw.h b/drivers/net/wireless/rtlwifi/rtl8192de/hw.h
new file mode 100644
index 000000000000..ad44ffa520e6
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/hw.h
@@ -0,0 +1,66 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92DE_HW_H__
31#define __RTL92DE_HW_H__
32
33void rtl92de_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
34void rtl92de_read_eeprom_info(struct ieee80211_hw *hw);
35void rtl92de_interrupt_recognized(struct ieee80211_hw *hw,
36 u32 *p_inta, u32 *p_intb);
37int rtl92de_hw_init(struct ieee80211_hw *hw);
38void rtl92de_card_disable(struct ieee80211_hw *hw);
39void rtl92de_enable_interrupt(struct ieee80211_hw *hw);
40void rtl92de_disable_interrupt(struct ieee80211_hw *hw);
41int rtl92de_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type);
42void rtl92de_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid);
43void rtl92de_set_qos(struct ieee80211_hw *hw, int aci);
44void rtl92de_set_beacon_related_registers(struct ieee80211_hw *hw);
45void rtl92de_set_beacon_interval(struct ieee80211_hw *hw);
46void rtl92de_update_interrupt_mask(struct ieee80211_hw *hw,
47 u32 add_msr, u32 rm_msr);
48void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
49void rtl92de_update_hal_rate_tbl(struct ieee80211_hw *hw,
50 struct ieee80211_sta *sta, u8 rssi_level);
51void rtl92de_update_channel_access_setting(struct ieee80211_hw *hw);
52bool rtl92de_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid);
53void rtl92de_enable_hw_security_config(struct ieee80211_hw *hw);
54void rtl92de_set_key(struct ieee80211_hw *hw, u32 key_index,
55 u8 *p_macaddr, bool is_group, u8 enc_algo,
56 bool is_wepkey, bool clear_all);
57
58extern void rtl92de_write_dword_dbi(struct ieee80211_hw *hw, u16 offset,
59 u32 value, u8 direct);
60extern u32 rtl92de_read_dword_dbi(struct ieee80211_hw *hw, u16 offset,
61 u8 direct);
62void rtl92de_suspend(struct ieee80211_hw *hw);
63void rtl92de_resume(struct ieee80211_hw *hw);
64void rtl92d_linked_set_reg(struct ieee80211_hw *hw);
65
66#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/led.c b/drivers/net/wireless/rtlwifi/rtl8192de/led.c
new file mode 100644
index 000000000000..719972c16fcc
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/led.c
@@ -0,0 +1,159 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../pci.h"
32#include "reg.h"
33#include "led.h"
34
35static void _rtl92ce_init_led(struct ieee80211_hw *hw,
36 struct rtl_led *pled, enum rtl_led_pin ledpin)
37{
38 pled->hw = hw;
39 pled->ledpin = ledpin;
40 pled->ledon = false;
41}
42
43void rtl92de_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
44{
45 u8 ledcfg;
46 struct rtl_priv *rtlpriv = rtl_priv(hw);
47
48 RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD,
49 ("LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin));
50
51 switch (pled->ledpin) {
52 case LED_PIN_GPIO0:
53 break;
54 case LED_PIN_LED0:
55 ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
56
57 if ((rtlpriv->efuse.eeprom_did == 0x8176) ||
58 (rtlpriv->efuse.eeprom_did == 0x8193))
59 /* BIT7 of REG_LEDCFG2 should be set to
60 * make sure we could emit the led2. */
61 rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg & 0xf0) |
62 BIT(7) | BIT(5) | BIT(6));
63 else
64 rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg & 0xf0) |
65 BIT(7) | BIT(5));
66 break;
67 case LED_PIN_LED1:
68 ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG1);
69
70 rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg & 0x0f) | BIT(5));
71 break;
72 default:
73 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
74 ("switch case not process\n"));
75 break;
76 }
77 pled->ledon = true;
78}
79
80void rtl92de_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
81{
82 struct rtl_priv *rtlpriv = rtl_priv(hw);
83 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
84 u8 ledcfg;
85
86 RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD,
87 ("LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin));
88
89 ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
90
91 switch (pled->ledpin) {
92 case LED_PIN_GPIO0:
93 break;
94 case LED_PIN_LED0:
95 ledcfg &= 0xf0;
96 if (pcipriv->ledctl.led_opendrain == true)
97 rtl_write_byte(rtlpriv, REG_LEDCFG2,
98 (ledcfg | BIT(1) | BIT(5) | BIT(6)));
99 else
100 rtl_write_byte(rtlpriv, REG_LEDCFG2,
101 (ledcfg | BIT(3) | BIT(5) | BIT(6)));
102 break;
103 case LED_PIN_LED1:
104 ledcfg &= 0x0f;
105 rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg | BIT(3)));
106 break;
107 default:
108 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
109 ("switch case not process\n"));
110 break;
111 }
112 pled->ledon = false;
113}
114
115void rtl92de_init_sw_leds(struct ieee80211_hw *hw)
116{
117 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
118 _rtl92ce_init_led(hw, &(pcipriv->ledctl.sw_led0), LED_PIN_LED0);
119 _rtl92ce_init_led(hw, &(pcipriv->ledctl.sw_led1), LED_PIN_LED1);
120}
121
122static void _rtl92ce_sw_led_control(struct ieee80211_hw *hw,
123 enum led_ctl_mode ledaction)
124{
125 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
126 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
127 switch (ledaction) {
128 case LED_CTL_POWER_ON:
129 case LED_CTL_LINK:
130 case LED_CTL_NO_LINK:
131 rtl92de_sw_led_on(hw, pLed0);
132 break;
133 case LED_CTL_POWER_OFF:
134 rtl92de_sw_led_off(hw, pLed0);
135 break;
136 default:
137 break;
138 }
139}
140
141void rtl92de_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction)
142{
143 struct rtl_priv *rtlpriv = rtl_priv(hw);
144 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
145
146 if ((ppsc->rfoff_reason > RF_CHANGE_BY_PS) &&
147 (ledaction == LED_CTL_TX ||
148 ledaction == LED_CTL_RX ||
149 ledaction == LED_CTL_SITE_SURVEY ||
150 ledaction == LED_CTL_LINK ||
151 ledaction == LED_CTL_NO_LINK ||
152 ledaction == LED_CTL_START_TO_LINK ||
153 ledaction == LED_CTL_POWER_ON)) {
154 return;
155 }
156 RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD, ("ledaction %d,\n", ledaction));
157
158 _rtl92ce_sw_led_control(hw, ledaction);
159}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/led.h b/drivers/net/wireless/rtlwifi/rtl8192de/led.h
new file mode 100644
index 000000000000..57f4a3c583d4
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/led.h
@@ -0,0 +1,38 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92CE_LED_H__
31#define __RTL92CE_LED_H__
32
33void rtl92de_init_sw_leds(struct ieee80211_hw *hw);
34void rtl92de_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled);
35void rtl92de_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled);
36void rtl92de_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction);
37
38#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/phy.c b/drivers/net/wireless/rtlwifi/rtl8192de/phy.c
new file mode 100644
index 000000000000..97fb6ca39d73
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/phy.c
@@ -0,0 +1,3837 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../pci.h"
32#include "../ps.h"
33#include "reg.h"
34#include "def.h"
35#include "phy.h"
36#include "rf.h"
37#include "dm.h"
38#include "table.h"
39#include "sw.h"
40#include "hw.h"
41
42#define MAX_RF_IMR_INDEX 12
43#define MAX_RF_IMR_INDEX_NORMAL 13
44#define RF_REG_NUM_FOR_C_CUT_5G 6
45#define RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA 7
46#define RF_REG_NUM_FOR_C_CUT_2G 5
47#define RF_CHNL_NUM_5G 19
48#define RF_CHNL_NUM_5G_40M 17
49#define TARGET_CHNL_NUM_5G 221
50#define TARGET_CHNL_NUM_2G 14
51#define CV_CURVE_CNT 64
52
53static u32 rf_reg_for_5g_swchnl_normal[MAX_RF_IMR_INDEX_NORMAL] = {
54 0, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x0
55};
56
57static u8 rf_reg_for_c_cut_5g[RF_REG_NUM_FOR_C_CUT_5G] = {
58 RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G4, RF_SYN_G5, RF_SYN_G6
59};
60
61static u8 rf_reg_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = {
62 RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G7, RF_SYN_G8
63};
64
65static u8 rf_for_c_cut_5g_internal_pa[RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = {
66 0x0B, 0x48, 0x49, 0x4B, 0x03, 0x04, 0x0E
67};
68
69static u32 rf_reg_mask_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = {
70 BIT(19) | BIT(18) | BIT(17) | BIT(14) | BIT(1),
71 BIT(10) | BIT(9),
72 BIT(18) | BIT(17) | BIT(16) | BIT(1),
73 BIT(2) | BIT(1),
74 BIT(15) | BIT(14) | BIT(13) | BIT(12) | BIT(11)
75};
76
77static u8 rf_chnl_5g[RF_CHNL_NUM_5G] = {
78 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108,
79 112, 116, 120, 124, 128, 132, 136, 140
80};
81
82static u8 rf_chnl_5g_40m[RF_CHNL_NUM_5G_40M] = {
83 38, 42, 46, 50, 54, 58, 62, 102, 106, 110, 114,
84 118, 122, 126, 130, 134, 138
85};
86static u32 rf_reg_pram_c_5g[5][RF_REG_NUM_FOR_C_CUT_5G] = {
87 {0xE43BE, 0xFC638, 0x77C0A, 0xDE471, 0xd7110, 0x8EB04},
88 {0xE43BE, 0xFC078, 0xF7C1A, 0xE0C71, 0xD7550, 0xAEB04},
89 {0xE43BF, 0xFF038, 0xF7C0A, 0xDE471, 0xE5550, 0xAEB04},
90 {0xE43BF, 0xFF079, 0xF7C1A, 0xDE471, 0xE5550, 0xAEB04},
91 {0xE43BF, 0xFF038, 0xF7C1A, 0xDE471, 0xd7550, 0xAEB04}
92};
93
94static u32 rf_reg_param_for_c_cut_2g[3][RF_REG_NUM_FOR_C_CUT_2G] = {
95 {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840},
96 {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840},
97 {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41}
98};
99
100static u32 rf_syn_g4_for_c_cut_2g = 0xD1C31 & 0x7FF;
101
102static u32 rf_pram_c_5g_int_pa[3][RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = {
103 {0x01a00, 0x40443, 0x00eb5, 0x89bec, 0x94a12, 0x94a12, 0x94a12},
104 {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a52, 0x94a52, 0x94a52},
105 {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a12, 0x94a12, 0x94a12}
106};
107
108/* [mode][patha+b][reg] */
109static u32 rf_imr_param_normal[1][3][MAX_RF_IMR_INDEX_NORMAL] = {
110 {
111 /* channel 1-14. */
112 {
113 0x70000, 0x00ff0, 0x4400f, 0x00ff0, 0x0, 0x0, 0x0,
114 0x0, 0x0, 0x64888, 0xe266c, 0x00090, 0x22fff
115 },
116 /* path 36-64 */
117 {
118 0x70000, 0x22880, 0x4470f, 0x55880, 0x00070, 0x88000,
119 0x0, 0x88080, 0x70000, 0x64a82, 0xe466c, 0x00090,
120 0x32c9a
121 },
122 /* 100 -165 */
123 {
124 0x70000, 0x44880, 0x4477f, 0x77880, 0x00070, 0x88000,
125 0x0, 0x880b0, 0x0, 0x64b82, 0xe466c, 0x00090, 0x32c9a
126 }
127 }
128};
129
130static u32 curveindex_5g[TARGET_CHNL_NUM_5G] = {0};
131
132static u32 curveindex_2g[TARGET_CHNL_NUM_2G] = {0};
133
134static u32 targetchnl_5g[TARGET_CHNL_NUM_5G] = {
135 25141, 25116, 25091, 25066, 25041,
136 25016, 24991, 24966, 24941, 24917,
137 24892, 24867, 24843, 24818, 24794,
138 24770, 24765, 24721, 24697, 24672,
139 24648, 24624, 24600, 24576, 24552,
140 24528, 24504, 24480, 24457, 24433,
141 24409, 24385, 24362, 24338, 24315,
142 24291, 24268, 24245, 24221, 24198,
143 24175, 24151, 24128, 24105, 24082,
144 24059, 24036, 24013, 23990, 23967,
145 23945, 23922, 23899, 23876, 23854,
146 23831, 23809, 23786, 23764, 23741,
147 23719, 23697, 23674, 23652, 23630,
148 23608, 23586, 23564, 23541, 23519,
149 23498, 23476, 23454, 23432, 23410,
150 23388, 23367, 23345, 23323, 23302,
151 23280, 23259, 23237, 23216, 23194,
152 23173, 23152, 23130, 23109, 23088,
153 23067, 23046, 23025, 23003, 22982,
154 22962, 22941, 22920, 22899, 22878,
155 22857, 22837, 22816, 22795, 22775,
156 22754, 22733, 22713, 22692, 22672,
157 22652, 22631, 22611, 22591, 22570,
158 22550, 22530, 22510, 22490, 22469,
159 22449, 22429, 22409, 22390, 22370,
160 22350, 22336, 22310, 22290, 22271,
161 22251, 22231, 22212, 22192, 22173,
162 22153, 22134, 22114, 22095, 22075,
163 22056, 22037, 22017, 21998, 21979,
164 21960, 21941, 21921, 21902, 21883,
165 21864, 21845, 21826, 21807, 21789,
166 21770, 21751, 21732, 21713, 21695,
167 21676, 21657, 21639, 21620, 21602,
168 21583, 21565, 21546, 21528, 21509,
169 21491, 21473, 21454, 21436, 21418,
170 21400, 21381, 21363, 21345, 21327,
171 21309, 21291, 21273, 21255, 21237,
172 21219, 21201, 21183, 21166, 21148,
173 21130, 21112, 21095, 21077, 21059,
174 21042, 21024, 21007, 20989, 20972,
175 25679, 25653, 25627, 25601, 25575,
176 25549, 25523, 25497, 25471, 25446,
177 25420, 25394, 25369, 25343, 25318,
178 25292, 25267, 25242, 25216, 25191,
179 25166
180};
181
182/* channel 1~14 */
183static u32 targetchnl_2g[TARGET_CHNL_NUM_2G] = {
184 26084, 26030, 25976, 25923, 25869, 25816, 25764,
185 25711, 25658, 25606, 25554, 25502, 25451, 25328
186};
187
188static u32 _rtl92d_phy_calculate_bit_shift(u32 bitmask)
189{
190 u32 i;
191
192 for (i = 0; i <= 31; i++) {
193 if (((bitmask >> i) & 0x1) == 1)
194 break;
195 }
196
197 return i;
198}
199
200u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
201{
202 struct rtl_priv *rtlpriv = rtl_priv(hw);
203 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
204 u32 returnvalue, originalvalue, bitshift;
205 u8 dbi_direct;
206
207 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
208 "bitmask(%#x)\n", regaddr, bitmask));
209 if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob) {
210 /* mac1 use phy0 read radio_b. */
211 /* mac0 use phy1 read radio_b. */
212 if (rtlhal->during_mac1init_radioa)
213 dbi_direct = BIT(3);
214 else if (rtlhal->during_mac0init_radiob)
215 dbi_direct = BIT(3) | BIT(2);
216 originalvalue = rtl92de_read_dword_dbi(hw, (u16)regaddr,
217 dbi_direct);
218 } else {
219 originalvalue = rtl_read_dword(rtlpriv, regaddr);
220 }
221 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
222 returnvalue = (originalvalue & bitmask) >> bitshift;
223 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("BBR MASK=0x%x "
224 "Addr[0x%x]=0x%x\n", bitmask, regaddr, originalvalue));
225 return returnvalue;
226}
227
228void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw,
229 u32 regaddr, u32 bitmask, u32 data)
230{
231 struct rtl_priv *rtlpriv = rtl_priv(hw);
232 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
233 u8 dbi_direct = 0;
234 u32 originalvalue, bitshift;
235
236 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x),"
237 " data(%#x)\n", regaddr, bitmask, data));
238 if (rtlhal->during_mac1init_radioa)
239 dbi_direct = BIT(3);
240 else if (rtlhal->during_mac0init_radiob)
241 /* mac0 use phy1 write radio_b. */
242 dbi_direct = BIT(3) | BIT(2);
243 if (bitmask != BMASKDWORD) {
244 if (rtlhal->during_mac1init_radioa ||
245 rtlhal->during_mac0init_radiob)
246 originalvalue = rtl92de_read_dword_dbi(hw,
247 (u16) regaddr,
248 dbi_direct);
249 else
250 originalvalue = rtl_read_dword(rtlpriv, regaddr);
251 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
252 data = ((originalvalue & (~bitmask)) | (data << bitshift));
253 }
254 if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob)
255 rtl92de_write_dword_dbi(hw, (u16) regaddr, data, dbi_direct);
256 else
257 rtl_write_dword(rtlpriv, regaddr, data);
258 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x),"
259 " data(%#x)\n", regaddr, bitmask, data));
260}
261
262static u32 _rtl92d_phy_rf_serial_read(struct ieee80211_hw *hw,
263 enum radio_path rfpath, u32 offset)
264{
265
266 struct rtl_priv *rtlpriv = rtl_priv(hw);
267 struct rtl_phy *rtlphy = &(rtlpriv->phy);
268 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
269 u32 newoffset;
270 u32 tmplong, tmplong2;
271 u8 rfpi_enable = 0;
272 u32 retvalue;
273
274 newoffset = offset;
275 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, BMASKDWORD);
276 if (rfpath == RF90_PATH_A)
277 tmplong2 = tmplong;
278 else
279 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, BMASKDWORD);
280 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
281 (newoffset << 23) | BLSSIREADEDGE;
282 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, BMASKDWORD,
283 tmplong & (~BLSSIREADEDGE));
284 udelay(10);
285 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, BMASKDWORD, tmplong2);
286 udelay(50);
287 udelay(50);
288 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, BMASKDWORD,
289 tmplong | BLSSIREADEDGE);
290 udelay(10);
291 if (rfpath == RF90_PATH_A)
292 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
293 BIT(8));
294 else if (rfpath == RF90_PATH_B)
295 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
296 BIT(8));
297 if (rfpi_enable)
298 retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readbackpi,
299 BLSSIREADBACKDATA);
300 else
301 retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readback,
302 BLSSIREADBACKDATA);
303 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("RFR-%d Addr[0x%x] = 0x%x\n",
304 rfpath, pphyreg->rflssi_readback, retvalue));
305 return retvalue;
306}
307
308static void _rtl92d_phy_rf_serial_write(struct ieee80211_hw *hw,
309 enum radio_path rfpath,
310 u32 offset, u32 data)
311{
312 u32 data_and_addr;
313 u32 newoffset;
314 struct rtl_priv *rtlpriv = rtl_priv(hw);
315 struct rtl_phy *rtlphy = &(rtlpriv->phy);
316 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
317
318 newoffset = offset;
319 /* T65 RF */
320 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
321 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, BMASKDWORD, data_and_addr);
322 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("RFW-%d Addr[0x%x]=0x%x\n",
323 rfpath, pphyreg->rf3wire_offset, data_and_addr));
324}
325
326u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw,
327 enum radio_path rfpath, u32 regaddr, u32 bitmask)
328{
329 struct rtl_priv *rtlpriv = rtl_priv(hw);
330 u32 original_value, readback_value, bitshift;
331 unsigned long flags;
332
333 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
334 "rfpath(%#x), bitmask(%#x)\n",
335 regaddr, rfpath, bitmask));
336 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
337 original_value = _rtl92d_phy_rf_serial_read(hw, rfpath, regaddr);
338 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
339 readback_value = (original_value & bitmask) >> bitshift;
340 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
341 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), rfpath(%#x), "
342 "bitmask(%#x), original_value(%#x)\n",
343 regaddr, rfpath, bitmask, original_value));
344 return readback_value;
345}
346
347void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
348 u32 regaddr, u32 bitmask, u32 data)
349{
350 struct rtl_priv *rtlpriv = rtl_priv(hw);
351 struct rtl_phy *rtlphy = &(rtlpriv->phy);
352 u32 original_value, bitshift;
353 unsigned long flags;
354
355 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
356 ("regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
357 regaddr, bitmask, data, rfpath));
358 if (bitmask == 0)
359 return;
360 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
361 if (rtlphy->rf_mode != RF_OP_BY_FW) {
362 if (bitmask != BRFREGOFFSETMASK) {
363 original_value = _rtl92d_phy_rf_serial_read(hw,
364 rfpath, regaddr);
365 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
366 data = ((original_value & (~bitmask)) |
367 (data << bitshift));
368 }
369 _rtl92d_phy_rf_serial_write(hw, rfpath, regaddr, data);
370 }
371 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
372 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
373 "bitmask(%#x), data(%#x), rfpath(%#x)\n",
374 regaddr, bitmask, data, rfpath));
375}
376
377bool rtl92d_phy_mac_config(struct ieee80211_hw *hw)
378{
379 struct rtl_priv *rtlpriv = rtl_priv(hw);
380 u32 i;
381 u32 arraylength;
382 u32 *ptrarray;
383
384 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Read Rtl819XMACPHY_Array\n"));
385 arraylength = MAC_2T_ARRAYLENGTH;
386 ptrarray = rtl8192de_mac_2tarray;
387 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Img:Rtl819XMAC_Array\n"));
388 for (i = 0; i < arraylength; i = i + 2)
389 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
390 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) {
391 /* improve 2-stream TX EVM */
392 /* rtl_write_byte(rtlpriv, 0x14,0x71); */
393 /* AMPDU aggregation number 9 */
394 /* rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, MAX_AGGR_NUM); */
395 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x0B);
396 } else {
397 /* 92D need to test to decide the num. */
398 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x07);
399 }
400 return true;
401}
402
403static void _rtl92d_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
404{
405 struct rtl_priv *rtlpriv = rtl_priv(hw);
406 struct rtl_phy *rtlphy = &(rtlpriv->phy);
407
408 /* RF Interface Sowrtware Control */
409 /* 16 LSBs if read 32-bit from 0x870 */
410 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
411 /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
412 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
413 /* 16 LSBs if read 32-bit from 0x874 */
414 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
415 /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */
416
417 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
418 /* RF Interface Readback Value */
419 /* 16 LSBs if read 32-bit from 0x8E0 */
420 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
421 /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */
422 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
423 /* 16 LSBs if read 32-bit from 0x8E4 */
424 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
425 /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */
426 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
427
428 /* RF Interface Output (and Enable) */
429 /* 16 LSBs if read 32-bit from 0x860 */
430 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
431 /* 16 LSBs if read 32-bit from 0x864 */
432 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
433
434 /* RF Interface (Output and) Enable */
435 /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
436 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
437 /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
438 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
439
440 /* Addr of LSSI. Wirte RF register by driver */
441 /* LSSI Parameter */
442 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
443 RFPGA0_XA_LSSIPARAMETER;
444 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
445 RFPGA0_XB_LSSIPARAMETER;
446
447 /* RF parameter */
448 /* BB Band Select */
449 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
450 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
451 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
452 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
453
454 /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
455 /* Tx gain stage */
456 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
457 /* Tx gain stage */
458 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
459 /* Tx gain stage */
460 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
461 /* Tx gain stage */
462 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
463
464 /* Tranceiver A~D HSSI Parameter-1 */
465 /* wire control parameter1 */
466 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
467 /* wire control parameter1 */
468 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
469
470 /* Tranceiver A~D HSSI Parameter-2 */
471 /* wire control parameter2 */
472 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
473 /* wire control parameter2 */
474 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
475
476 /* RF switch Control */
477 /* TR/Ant switch control */
478 rtlphy->phyreg_def[RF90_PATH_A].rfswitch_control =
479 RFPGA0_XAB_SWITCHCONTROL;
480 rtlphy->phyreg_def[RF90_PATH_B].rfswitch_control =
481 RFPGA0_XAB_SWITCHCONTROL;
482 rtlphy->phyreg_def[RF90_PATH_C].rfswitch_control =
483 RFPGA0_XCD_SWITCHCONTROL;
484 rtlphy->phyreg_def[RF90_PATH_D].rfswitch_control =
485 RFPGA0_XCD_SWITCHCONTROL;
486
487 /* AGC control 1 */
488 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
489 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
490 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
491 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
492
493 /* AGC control 2 */
494 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
495 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
496 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
497 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
498
499 /* RX AFE control 1 */
500 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbalance =
501 ROFDM0_XARXIQIMBALANCE;
502 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbalance =
503 ROFDM0_XBRXIQIMBALANCE;
504 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbalance =
505 ROFDM0_XCRXIQIMBALANCE;
506 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbalance =
507 ROFDM0_XDRXIQIMBALANCE;
508
509 /*RX AFE control 1 */
510 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
511 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
512 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
513 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
514
515 /* Tx AFE control 1 */
516 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbalance =
517 ROFDM0_XATxIQIMBALANCE;
518 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbalance =
519 ROFDM0_XBTxIQIMBALANCE;
520 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbalance =
521 ROFDM0_XCTxIQIMBALANCE;
522 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbalance =
523 ROFDM0_XDTxIQIMBALANCE;
524
525 /* Tx AFE control 2 */
526 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATxAFE;
527 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTxAFE;
528 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTxAFE;
529 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTxAFE;
530
531 /* Tranceiver LSSI Readback SI mode */
532 rtlphy->phyreg_def[RF90_PATH_A].rflssi_readback =
533 RFPGA0_XA_LSSIREADBACK;
534 rtlphy->phyreg_def[RF90_PATH_B].rflssi_readback =
535 RFPGA0_XB_LSSIREADBACK;
536 rtlphy->phyreg_def[RF90_PATH_C].rflssi_readback =
537 RFPGA0_XC_LSSIREADBACK;
538 rtlphy->phyreg_def[RF90_PATH_D].rflssi_readback =
539 RFPGA0_XD_LSSIREADBACK;
540
541 /* Tranceiver LSSI Readback PI mode */
542 rtlphy->phyreg_def[RF90_PATH_A].rflssi_readbackpi =
543 TRANSCEIVERA_HSPI_READBACK;
544 rtlphy->phyreg_def[RF90_PATH_B].rflssi_readbackpi =
545 TRANSCEIVERB_HSPI_READBACK;
546}
547
548static bool _rtl92d_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
549 u8 configtype)
550{
551 int i;
552 u32 *phy_regarray_table;
553 u32 *agctab_array_table = NULL;
554 u32 *agctab_5garray_table;
555 u16 phy_reg_arraylen, agctab_arraylen = 0, agctab_5garraylen;
556 struct rtl_priv *rtlpriv = rtl_priv(hw);
557 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
558
559 /* Normal chip,Mac0 use AGC_TAB.txt for 2G and 5G band. */
560 if (rtlhal->interfaceindex == 0) {
561 agctab_arraylen = AGCTAB_ARRAYLENGTH;
562 agctab_array_table = rtl8192de_agctab_array;
563 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
564 (" ===> phy:MAC0, Rtl819XAGCTAB_Array\n"));
565 } else {
566 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
567 agctab_arraylen = AGCTAB_2G_ARRAYLENGTH;
568 agctab_array_table = rtl8192de_agctab_2garray;
569 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
570 (" ===> phy:MAC1, Rtl819XAGCTAB_2GArray\n"));
571 } else {
572 agctab_5garraylen = AGCTAB_5G_ARRAYLENGTH;
573 agctab_5garray_table = rtl8192de_agctab_5garray;
574 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
575 (" ===> phy:MAC1, Rtl819XAGCTAB_5GArray\n"));
576
577 }
578 }
579 phy_reg_arraylen = PHY_REG_2T_ARRAYLENGTH;
580 phy_regarray_table = rtl8192de_phy_reg_2tarray;
581 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
582 (" ===> phy:Rtl819XPHY_REG_Array_PG\n"));
583 if (configtype == BASEBAND_CONFIG_PHY_REG) {
584 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
585 if (phy_regarray_table[i] == 0xfe)
586 mdelay(50);
587 else if (phy_regarray_table[i] == 0xfd)
588 mdelay(5);
589 else if (phy_regarray_table[i] == 0xfc)
590 mdelay(1);
591 else if (phy_regarray_table[i] == 0xfb)
592 udelay(50);
593 else if (phy_regarray_table[i] == 0xfa)
594 udelay(5);
595 else if (phy_regarray_table[i] == 0xf9)
596 udelay(1);
597 rtl_set_bbreg(hw, phy_regarray_table[i], BMASKDWORD,
598 phy_regarray_table[i + 1]);
599 udelay(1);
600 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
601 ("The phy_regarray_table[0] is %x"
602 " Rtl819XPHY_REGArray[1] is %x\n",
603 phy_regarray_table[i],
604 phy_regarray_table[i + 1]));
605 }
606 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
607 if (rtlhal->interfaceindex == 0) {
608 for (i = 0; i < agctab_arraylen; i = i + 2) {
609 rtl_set_bbreg(hw, agctab_array_table[i],
610 BMASKDWORD,
611 agctab_array_table[i + 1]);
612 /* Add 1us delay between BB/RF register
613 * setting. */
614 udelay(1);
615 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
616 ("The Rtl819XAGCTAB_Array_"
617 "Table[0] is %ul "
618 "Rtl819XPHY_REGArray[1] is %ul\n",
619 agctab_array_table[i],
620 agctab_array_table[i + 1]));
621 }
622 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
623 ("Normal Chip, MAC0, load "
624 "Rtl819XAGCTAB_Array\n"));
625 } else {
626 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
627 for (i = 0; i < agctab_arraylen; i = i + 2) {
628 rtl_set_bbreg(hw, agctab_array_table[i],
629 BMASKDWORD,
630 agctab_array_table[i + 1]);
631 /* Add 1us delay between BB/RF register
632 * setting. */
633 udelay(1);
634 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
635 ("The Rtl819XAGCTAB_Array_"
636 "Table[0] is %ul Rtl819XPHY_"
637 "REGArray[1] is %ul\n",
638 agctab_array_table[i],
639 agctab_array_table[i + 1]));
640 }
641 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
642 ("Load Rtl819XAGCTAB_2GArray\n"));
643 } else {
644 for (i = 0; i < agctab_5garraylen; i = i + 2) {
645 rtl_set_bbreg(hw,
646 agctab_5garray_table[i],
647 BMASKDWORD,
648 agctab_5garray_table[i + 1]);
649 /* Add 1us delay between BB/RF registeri
650 * setting. */
651 udelay(1);
652 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
653 ("The Rtl819XAGCTAB_5GArray_"
654 "Table[0] is %ul Rtl819XPHY_"
655 "REGArray[1] is %ul\n",
656 agctab_5garray_table[i],
657 agctab_5garray_table[i + 1]));
658 }
659 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
660 ("Load Rtl819XAGCTAB_5GArray\n"));
661 }
662 }
663 }
664 return true;
665}
666
667static void _rtl92d_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,
668 u32 regaddr, u32 bitmask,
669 u32 data)
670{
671 struct rtl_priv *rtlpriv = rtl_priv(hw);
672 struct rtl_phy *rtlphy = &(rtlpriv->phy);
673
674 if (regaddr == RTXAGC_A_RATE18_06) {
675 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][0] =
676 data;
677 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
678 ("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%ulx\n",
679 rtlphy->pwrgroup_cnt,
680 rtlphy->mcs_txpwrlevel_origoffset
681 [rtlphy->pwrgroup_cnt][0]));
682 }
683 if (regaddr == RTXAGC_A_RATE54_24) {
684 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][1] =
685 data;
686 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
687 ("MCSTxPowerLevelOriginalOffset[%d][1] = 0x%ulx\n",
688 rtlphy->pwrgroup_cnt,
689 rtlphy->mcs_txpwrlevel_origoffset
690 [rtlphy->pwrgroup_cnt][1]));
691 }
692 if (regaddr == RTXAGC_A_CCK1_MCS32) {
693 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][6] =
694 data;
695 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
696 ("MCSTxPowerLevelOriginalOffset[%d][6] = 0x%ulx\n",
697 rtlphy->pwrgroup_cnt,
698 rtlphy->mcs_txpwrlevel_origoffset
699 [rtlphy->pwrgroup_cnt][6]));
700 }
701 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) {
702 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][7] =
703 data;
704 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
705 ("MCSTxPowerLevelOriginalOffset[%d][7] = 0x%ulx\n",
706 rtlphy->pwrgroup_cnt,
707 rtlphy->mcs_txpwrlevel_origoffset
708 [rtlphy->pwrgroup_cnt][7]));
709 }
710 if (regaddr == RTXAGC_A_MCS03_MCS00) {
711 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][2] =
712 data;
713 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
714 ("MCSTxPowerLevelOriginalOffset[%d][2] = 0x%ulx\n",
715 rtlphy->pwrgroup_cnt,
716 rtlphy->mcs_txpwrlevel_origoffset
717 [rtlphy->pwrgroup_cnt][2]));
718 }
719 if (regaddr == RTXAGC_A_MCS07_MCS04) {
720 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][3] =
721 data;
722 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
723 ("MCSTxPowerLevelOriginalOffset[%d][3] = 0x%ulx\n",
724 rtlphy->pwrgroup_cnt,
725 rtlphy->mcs_txpwrlevel_origoffset
726 [rtlphy->pwrgroup_cnt][3]));
727 }
728 if (regaddr == RTXAGC_A_MCS11_MCS08) {
729 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][4] =
730 data;
731 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
732 ("MCSTxPowerLevelOriginalOffset[%d][4] = 0x%ulx\n",
733 rtlphy->pwrgroup_cnt,
734 rtlphy->mcs_txpwrlevel_origoffset
735 [rtlphy->pwrgroup_cnt][4]));
736 }
737 if (regaddr == RTXAGC_A_MCS15_MCS12) {
738 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][5] =
739 data;
740 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
741 ("MCSTxPowerLevelOriginalOffset[%d][5] = 0x%ulx\n",
742 rtlphy->pwrgroup_cnt,
743 rtlphy->mcs_txpwrlevel_origoffset
744 [rtlphy->pwrgroup_cnt][5]));
745 }
746 if (regaddr == RTXAGC_B_RATE18_06) {
747 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][8] =
748 data;
749 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
750 ("MCSTxPowerLevelOriginalOffset[%d][8] = 0x%ulx\n",
751 rtlphy->pwrgroup_cnt,
752 rtlphy->mcs_txpwrlevel_origoffset
753 [rtlphy->pwrgroup_cnt][8]));
754 }
755 if (regaddr == RTXAGC_B_RATE54_24) {
756 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][9] =
757 data;
758 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
759 ("MCSTxPowerLevelOriginalOffset[%d][9] = 0x%ulx\n",
760 rtlphy->pwrgroup_cnt,
761 rtlphy->mcs_txpwrlevel_origoffset
762 [rtlphy->pwrgroup_cnt][9]));
763 }
764 if (regaddr == RTXAGC_B_CCK1_55_MCS32) {
765 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][14] =
766 data;
767 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
768 ("MCSTxPowerLevelOriginalOffset[%d][14] = 0x%ulx\n",
769 rtlphy->pwrgroup_cnt,
770 rtlphy->mcs_txpwrlevel_origoffset
771 [rtlphy->pwrgroup_cnt][14]));
772 }
773 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) {
774 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][15] =
775 data;
776 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
777 ("MCSTxPowerLevelOriginalOffset[%d][15] = 0x%ulx\n",
778 rtlphy->pwrgroup_cnt,
779 rtlphy->mcs_txpwrlevel_origoffset
780 [rtlphy->pwrgroup_cnt][15]));
781 }
782 if (regaddr == RTXAGC_B_MCS03_MCS00) {
783 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][10] =
784 data;
785 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
786 ("MCSTxPowerLevelOriginalOffset[%d][10] = 0x%ulx\n",
787 rtlphy->pwrgroup_cnt,
788 rtlphy->mcs_txpwrlevel_origoffset
789 [rtlphy->pwrgroup_cnt][10]));
790 }
791 if (regaddr == RTXAGC_B_MCS07_MCS04) {
792 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][11] =
793 data;
794 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
795 ("MCSTxPowerLevelOriginalOffset[%d][11] = 0x%ulx\n",
796 rtlphy->pwrgroup_cnt,
797 rtlphy->mcs_txpwrlevel_origoffset
798 [rtlphy->pwrgroup_cnt][11]));
799 }
800 if (regaddr == RTXAGC_B_MCS11_MCS08) {
801 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][12] =
802 data;
803 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
804 ("MCSTxPowerLevelOriginalOffset[%d][12] = 0x%ulx\n",
805 rtlphy->pwrgroup_cnt,
806 rtlphy->mcs_txpwrlevel_origoffset
807 [rtlphy->pwrgroup_cnt][12]));
808 }
809 if (regaddr == RTXAGC_B_MCS15_MCS12) {
810 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][13] =
811 data;
812 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
813 ("MCSTxPowerLevelOriginalOffset[%d][13] = 0x%ulx\n",
814 rtlphy->pwrgroup_cnt,
815 rtlphy->mcs_txpwrlevel_origoffset
816 [rtlphy->pwrgroup_cnt][13]));
817 rtlphy->pwrgroup_cnt++;
818 }
819}
820
821static bool _rtl92d_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
822 u8 configtype)
823{
824 struct rtl_priv *rtlpriv = rtl_priv(hw);
825 int i;
826 u32 *phy_regarray_table_pg;
827 u16 phy_regarray_pg_len;
828
829 phy_regarray_pg_len = PHY_REG_ARRAY_PG_LENGTH;
830 phy_regarray_table_pg = rtl8192de_phy_reg_array_pg;
831 if (configtype == BASEBAND_CONFIG_PHY_REG) {
832 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
833 if (phy_regarray_table_pg[i] == 0xfe)
834 mdelay(50);
835 else if (phy_regarray_table_pg[i] == 0xfd)
836 mdelay(5);
837 else if (phy_regarray_table_pg[i] == 0xfc)
838 mdelay(1);
839 else if (phy_regarray_table_pg[i] == 0xfb)
840 udelay(50);
841 else if (phy_regarray_table_pg[i] == 0xfa)
842 udelay(5);
843 else if (phy_regarray_table_pg[i] == 0xf9)
844 udelay(1);
845 _rtl92d_store_pwrindex_diffrate_offset(hw,
846 phy_regarray_table_pg[i],
847 phy_regarray_table_pg[i + 1],
848 phy_regarray_table_pg[i + 2]);
849 }
850 } else {
851 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
852 ("configtype != BaseBand_Config_PHY_REG\n"));
853 }
854 return true;
855}
856
857static bool _rtl92d_phy_bb_config(struct ieee80211_hw *hw)
858{
859 struct rtl_priv *rtlpriv = rtl_priv(hw);
860 struct rtl_phy *rtlphy = &(rtlpriv->phy);
861 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
862 bool rtstatus = true;
863
864 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("==>\n"));
865 rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw,
866 BASEBAND_CONFIG_PHY_REG);
867 if (rtstatus != true) {
868 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Write BB Reg Fail!!"));
869 return false;
870 }
871
872 /* if (rtlphy->rf_type == RF_1T2R) {
873 * _rtl92c_phy_bb_config_1t(hw);
874 * RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Config to 1T!!\n"));
875 *} */
876
877 if (rtlefuse->autoload_failflag == false) {
878 rtlphy->pwrgroup_cnt = 0;
879 rtstatus = _rtl92d_phy_config_bb_with_pgheaderfile(hw,
880 BASEBAND_CONFIG_PHY_REG);
881 }
882 if (rtstatus != true) {
883 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("BB_PG Reg Fail!!"));
884 return false;
885 }
886 rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw,
887 BASEBAND_CONFIG_AGC_TAB);
888 if (rtstatus != true) {
889 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("AGC Table Fail\n"));
890 return false;
891 }
892 rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw,
893 RFPGA0_XA_HSSIPARAMETER2, 0x200));
894
895 return true;
896}
897
898bool rtl92d_phy_bb_config(struct ieee80211_hw *hw)
899{
900 struct rtl_priv *rtlpriv = rtl_priv(hw);
901 u16 regval;
902 u32 regvaldw;
903 u8 value;
904
905 _rtl92d_phy_init_bb_rf_register_definition(hw);
906 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
907 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
908 regval | BIT(13) | BIT(0) | BIT(1));
909 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
910 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
911 /* 0x1f bit7 bit6 represent for mac0/mac1 driver ready */
912 value = rtl_read_byte(rtlpriv, REG_RF_CTRL);
913 rtl_write_byte(rtlpriv, REG_RF_CTRL, value | RF_EN | RF_RSTB |
914 RF_SDMRSTB);
915 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_PPLL | FEN_PCIEA |
916 FEN_DIO_PCIE | FEN_BB_GLB_RSTn | FEN_BBRSTB);
917 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
918 if (!(IS_92D_SINGLEPHY(rtlpriv->rtlhal.version))) {
919 regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0);
920 rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23));
921 }
922
923 return _rtl92d_phy_bb_config(hw);
924}
925
926bool rtl92d_phy_rf_config(struct ieee80211_hw *hw)
927{
928 return rtl92d_phy_rf6052_config(hw);
929}
930
931bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
932 enum rf_content content,
933 enum radio_path rfpath)
934{
935 int i, j;
936 u32 *radioa_array_table;
937 u32 *radiob_array_table;
938 u16 radioa_arraylen, radiob_arraylen;
939 struct rtl_priv *rtlpriv = rtl_priv(hw);
940
941 radioa_arraylen = RADIOA_2T_ARRAYLENGTH;
942 radioa_array_table = rtl8192de_radioa_2tarray;
943 radiob_arraylen = RADIOB_2T_ARRAYLENGTH;
944 radiob_array_table = rtl8192de_radiob_2tarray;
945 if (rtlpriv->efuse.internal_pa_5g[0]) {
946 radioa_arraylen = RADIOA_2T_INT_PA_ARRAYLENGTH;
947 radioa_array_table = rtl8192de_radioa_2t_int_paarray;
948 }
949 if (rtlpriv->efuse.internal_pa_5g[1]) {
950 radiob_arraylen = RADIOB_2T_INT_PA_ARRAYLENGTH;
951 radiob_array_table = rtl8192de_radiob_2t_int_paarray;
952 }
953 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
954 ("PHY_ConfigRFWithHeaderFile() "
955 "Radio_A:Rtl819XRadioA_1TArray\n"));
956 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
957 ("PHY_ConfigRFWithHeaderFile() "
958 "Radio_B:Rtl819XRadioB_1TArray\n"));
959 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Radio No %x\n", rfpath));
960
961 /* this only happens when DMDP, mac0 start on 2.4G,
962 * mac1 start on 5G, mac 0 has to set phy0&phy1
963 * pathA or mac1 has to set phy0&phy1 pathA */
964 if ((content == radiob_txt) && (rfpath == RF90_PATH_A)) {
965 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
966 (" ===> althougth Path A, we load radiob.txt\n"));
967 radioa_arraylen = radiob_arraylen;
968 radioa_array_table = radiob_array_table;
969 }
970 switch (rfpath) {
971 case RF90_PATH_A:
972 for (i = 0; i < radioa_arraylen; i = i + 2) {
973 if (radioa_array_table[i] == 0xfe) {
974 mdelay(50);
975 } else if (radioa_array_table[i] == 0xfd) {
976 /* delay_ms(5); */
977 for (j = 0; j < 100; j++)
978 udelay(MAX_STALL_TIME);
979 } else if (radioa_array_table[i] == 0xfc) {
980 /* delay_ms(1); */
981 for (j = 0; j < 20; j++)
982 udelay(MAX_STALL_TIME);
983
984 } else if (radioa_array_table[i] == 0xfb) {
985 udelay(50);
986 } else if (radioa_array_table[i] == 0xfa) {
987 udelay(5);
988 } else if (radioa_array_table[i] == 0xf9) {
989 udelay(1);
990 } else {
991 rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
992 BRFREGOFFSETMASK,
993 radioa_array_table[i + 1]);
994 /* Add 1us delay between BB/RF register set. */
995 udelay(1);
996 }
997 }
998 break;
999 case RF90_PATH_B:
1000 for (i = 0; i < radiob_arraylen; i = i + 2) {
1001 if (radiob_array_table[i] == 0xfe) {
1002 /* Delay specific ms. Only RF configuration
1003 * requires delay. */
1004 mdelay(50);
1005 } else if (radiob_array_table[i] == 0xfd) {
1006 /* delay_ms(5); */
1007 for (j = 0; j < 100; j++)
1008 udelay(MAX_STALL_TIME);
1009 } else if (radiob_array_table[i] == 0xfc) {
1010 /* delay_ms(1); */
1011 for (j = 0; j < 20; j++)
1012 udelay(MAX_STALL_TIME);
1013 } else if (radiob_array_table[i] == 0xfb) {
1014 udelay(50);
1015 } else if (radiob_array_table[i] == 0xfa) {
1016 udelay(5);
1017 } else if (radiob_array_table[i] == 0xf9) {
1018 udelay(1);
1019 } else {
1020 rtl_set_rfreg(hw, rfpath, radiob_array_table[i],
1021 BRFREGOFFSETMASK,
1022 radiob_array_table[i + 1]);
1023 /* Add 1us delay between BB/RF register set. */
1024 udelay(1);
1025 }
1026 }
1027 break;
1028 case RF90_PATH_C:
1029 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1030 ("switch case not process\n"));
1031 break;
1032 case RF90_PATH_D:
1033 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1034 ("switch case not process\n"));
1035 break;
1036 }
1037 return true;
1038}
1039
1040void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
1041{
1042 struct rtl_priv *rtlpriv = rtl_priv(hw);
1043 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1044
1045 rtlphy->default_initialgain[0] =
1046 (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, BMASKBYTE0);
1047 rtlphy->default_initialgain[1] =
1048 (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, BMASKBYTE0);
1049 rtlphy->default_initialgain[2] =
1050 (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, BMASKBYTE0);
1051 rtlphy->default_initialgain[3] =
1052 (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, BMASKBYTE0);
1053 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1054 ("Default initial gain (c50=0x%x, "
1055 "c58=0x%x, c60=0x%x, c68=0x%x\n",
1056 rtlphy->default_initialgain[0],
1057 rtlphy->default_initialgain[1],
1058 rtlphy->default_initialgain[2],
1059 rtlphy->default_initialgain[3]));
1060 rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3,
1061 BMASKBYTE0);
1062 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
1063 BMASKDWORD);
1064 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1065 ("Default framesync (0x%x) = 0x%x\n",
1066 ROFDM0_RXDETECTOR3, rtlphy->framesync));
1067}
1068
1069static void _rtl92d_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
1070 u8 *cckpowerlevel, u8 *ofdmpowerlevel)
1071{
1072 struct rtl_priv *rtlpriv = rtl_priv(hw);
1073 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1074 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
1075 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1076 u8 index = (channel - 1);
1077
1078 /* 1. CCK */
1079 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1080 /* RF-A */
1081 cckpowerlevel[RF90_PATH_A] =
1082 rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];
1083 /* RF-B */
1084 cckpowerlevel[RF90_PATH_B] =
1085 rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];
1086 } else {
1087 cckpowerlevel[RF90_PATH_A] = 0;
1088 cckpowerlevel[RF90_PATH_B] = 0;
1089 }
1090 /* 2. OFDM for 1S or 2S */
1091 if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) {
1092 /* Read HT 40 OFDM TX power */
1093 ofdmpowerlevel[RF90_PATH_A] =
1094 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];
1095 ofdmpowerlevel[RF90_PATH_B] =
1096 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];
1097 } else if (rtlphy->rf_type == RF_2T2R) {
1098 /* Read HT 40 OFDM TX power */
1099 ofdmpowerlevel[RF90_PATH_A] =
1100 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index];
1101 ofdmpowerlevel[RF90_PATH_B] =
1102 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index];
1103 }
1104}
1105
1106static void _rtl92d_ccxpower_index_check(struct ieee80211_hw *hw,
1107 u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel)
1108{
1109 struct rtl_priv *rtlpriv = rtl_priv(hw);
1110 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1111
1112 rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
1113 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
1114}
1115
1116static u8 _rtl92c_phy_get_rightchnlplace(u8 chnl)
1117{
1118 u8 channel_5g[59] = {
1119 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
1120 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
1121 60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
1122 114, 116, 118, 120, 122, 124, 126, 128,
1123 130, 132, 134, 136, 138, 140, 149, 151,
1124 153, 155, 157, 159, 161, 163, 165
1125 };
1126 u8 place = chnl;
1127
1128 if (chnl > 14) {
1129 for (place = 14; place < sizeof(channel_5g); place++) {
1130 if (channel_5g[place] == chnl) {
1131 place++;
1132 break;
1133 }
1134 }
1135 }
1136 return place;
1137}
1138
1139void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
1140{
1141 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1142 struct rtl_priv *rtlpriv = rtl_priv(hw);
1143 u8 cckpowerlevel[2], ofdmpowerlevel[2];
1144
1145 if (rtlefuse->txpwr_fromeprom == false)
1146 return;
1147 channel = _rtl92c_phy_get_rightchnlplace(channel);
1148 _rtl92d_get_txpower_index(hw, channel, &cckpowerlevel[0],
1149 &ofdmpowerlevel[0]);
1150 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)
1151 _rtl92d_ccxpower_index_check(hw, channel, &cckpowerlevel[0],
1152 &ofdmpowerlevel[0]);
1153 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)
1154 rtl92d_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
1155 rtl92d_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel);
1156}
1157
1158void rtl92d_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
1159{
1160 struct rtl_priv *rtlpriv = rtl_priv(hw);
1161 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1162 enum io_type iotype;
1163
1164 if (!is_hal_stop(rtlhal)) {
1165 switch (operation) {
1166 case SCAN_OPT_BACKUP:
1167 rtlhal->current_bandtypebackup =
1168 rtlhal->current_bandtype;
1169 iotype = IO_CMD_PAUSE_DM_BY_SCAN;
1170 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_IO_CMD,
1171 (u8 *)&iotype);
1172 break;
1173 case SCAN_OPT_RESTORE:
1174 iotype = IO_CMD_RESUME_DM_BY_SCAN;
1175 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_IO_CMD,
1176 (u8 *)&iotype);
1177 break;
1178 default:
1179 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1180 ("Unknown Scan Backup operation.\n"));
1181 break;
1182 }
1183 }
1184}
1185
1186void rtl92d_phy_set_bw_mode(struct ieee80211_hw *hw,
1187 enum nl80211_channel_type ch_type)
1188{
1189 struct rtl_priv *rtlpriv = rtl_priv(hw);
1190 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1191 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1192 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1193 unsigned long flag = 0;
1194 u8 reg_prsr_rsc;
1195 u8 reg_bw_opmode;
1196
1197 if (rtlphy->set_bwmode_inprogress)
1198 return;
1199 if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
1200 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1201 ("FALSE driver sleep or unload\n"));
1202 return;
1203 }
1204 rtlphy->set_bwmode_inprogress = true;
1205 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
1206 ("Switch to %s bandwidth\n",
1207 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
1208 "20MHz" : "40MHz"));
1209 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
1210 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
1211 switch (rtlphy->current_chan_bw) {
1212 case HT_CHANNEL_WIDTH_20:
1213 reg_bw_opmode |= BW_OPMODE_20MHZ;
1214 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
1215 break;
1216 case HT_CHANNEL_WIDTH_20_40:
1217 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
1218 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
1219
1220 reg_prsr_rsc = (reg_prsr_rsc & 0x90) |
1221 (mac->cur_40_prime_sc << 5);
1222 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
1223 break;
1224 default:
1225 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1226 ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
1227 break;
1228 }
1229 switch (rtlphy->current_chan_bw) {
1230 case HT_CHANNEL_WIDTH_20:
1231 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
1232 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
1233 /* SET BIT10 BIT11 for receive cck */
1234 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
1235 BIT(11), 3);
1236 break;
1237 case HT_CHANNEL_WIDTH_20_40:
1238 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
1239 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
1240 /* Set Control channel to upper or lower.
1241 * These settings are required only for 40MHz */
1242 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1243 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
1244 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCKSIDEBAND,
1245 (mac->cur_40_prime_sc >> 1));
1246 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
1247 }
1248 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
1249 /* SET BIT10 BIT11 for receive cck */
1250 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
1251 BIT(11), 0);
1252 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
1253 (mac->cur_40_prime_sc ==
1254 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
1255 break;
1256 default:
1257 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1258 ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
1259 break;
1260
1261 }
1262 rtl92d_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
1263 rtlphy->set_bwmode_inprogress = false;
1264 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("<==\n"));
1265}
1266
1267static void _rtl92d_phy_stop_trx_before_changeband(struct ieee80211_hw *hw)
1268{
1269 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0);
1270 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0);
1271 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKBYTE0, 0x00);
1272 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0);
1273}
1274
1275static void rtl92d_phy_switch_wirelessband(struct ieee80211_hw *hw, u8 band)
1276{
1277 struct rtl_priv *rtlpriv = rtl_priv(hw);
1278 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1279 u8 i, value8;
1280
1281 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("==>\n"));
1282 rtlhal->bandset = band;
1283 rtlhal->current_bandtype = band;
1284 if (IS_92D_SINGLEPHY(rtlhal->version))
1285 rtlhal->bandset = BAND_ON_BOTH;
1286 /* stop RX/Tx */
1287 _rtl92d_phy_stop_trx_before_changeband(hw);
1288 /* reconfig BB/RF according to wireless mode */
1289 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1290 /* BB & RF Config */
1291 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, ("====>2.4G\n"));
1292 if (rtlhal->interfaceindex == 1)
1293 _rtl92d_phy_config_bb_with_headerfile(hw,
1294 BASEBAND_CONFIG_AGC_TAB);
1295 } else {
1296 /* 5G band */
1297 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, ("====>5G\n"));
1298 if (rtlhal->interfaceindex == 1)
1299 _rtl92d_phy_config_bb_with_headerfile(hw,
1300 BASEBAND_CONFIG_AGC_TAB);
1301 }
1302 rtl92d_update_bbrf_configuration(hw);
1303 if (rtlhal->current_bandtype == BAND_ON_2_4G)
1304 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1305 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1306
1307 /* 20M BW. */
1308 /* rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); */
1309 rtlhal->reloadtxpowerindex = true;
1310 /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */
1311 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1312 value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex ==
1313 0 ? REG_MAC0 : REG_MAC1));
1314 value8 |= BIT(1);
1315 rtl_write_byte(rtlpriv, (rtlhal->interfaceindex ==
1316 0 ? REG_MAC0 : REG_MAC1), value8);
1317 } else {
1318 value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex ==
1319 0 ? REG_MAC0 : REG_MAC1));
1320 value8 &= (~BIT(1));
1321 rtl_write_byte(rtlpriv, (rtlhal->interfaceindex ==
1322 0 ? REG_MAC0 : REG_MAC1), value8);
1323 }
1324 for (i = 0; i < 20; i++)
1325 udelay(MAX_STALL_TIME);
1326 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("<==Switch Band OK.\n"));
1327}
1328
1329static void _rtl92d_phy_reload_imr_setting(struct ieee80211_hw *hw,
1330 u8 channel, u8 rfpath)
1331{
1332 struct rtl_priv *rtlpriv = rtl_priv(hw);
1333 u32 imr_num = MAX_RF_IMR_INDEX;
1334 u32 rfmask = BRFREGOFFSETMASK;
1335 u8 group, i;
1336 unsigned long flag = 0;
1337
1338 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("====>path %d\n", rfpath));
1339 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {
1340 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("====>5G\n"));
1341 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0);
1342 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
1343 /* fc area 0xd2c */
1344 if (channel > 99)
1345 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) |
1346 BIT(14), 2);
1347 else
1348 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) |
1349 BIT(14), 1);
1350 /* leave 0 for channel1-14. */
1351 group = channel <= 64 ? 1 : 2;
1352 imr_num = MAX_RF_IMR_INDEX_NORMAL;
1353 for (i = 0; i < imr_num; i++)
1354 rtl_set_rfreg(hw, (enum radio_path)rfpath,
1355 rf_reg_for_5g_swchnl_normal[i], rfmask,
1356 rf_imr_param_normal[0][group][i]);
1357 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0);
1358 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 1);
1359 } else {
1360 /* G band. */
1361 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
1362 ("Load RF IMR parameters for G band. IMR already "
1363 "setting %d\n",
1364 rtlpriv->rtlhal.load_imrandiqk_setting_for2g));
1365 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("====>2.4G\n"));
1366 if (!rtlpriv->rtlhal.load_imrandiqk_setting_for2g) {
1367 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
1368 ("Load RF IMR parameters "
1369 "for G band. %d\n", rfpath));
1370 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
1371 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0);
1372 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4,
1373 0x00f00000, 0xf);
1374 imr_num = MAX_RF_IMR_INDEX_NORMAL;
1375 for (i = 0; i < imr_num; i++) {
1376 rtl_set_rfreg(hw, (enum radio_path)rfpath,
1377 rf_reg_for_5g_swchnl_normal[i],
1378 BRFREGOFFSETMASK,
1379 rf_imr_param_normal[0][0][i]);
1380 }
1381 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4,
1382 0x00f00000, 0);
1383 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN | BCCKEN, 3);
1384 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
1385 }
1386 }
1387 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("<====\n"));
1388}
1389
1390static void _rtl92d_phy_enable_rf_env(struct ieee80211_hw *hw,
1391 u8 rfpath, u32 *pu4_regval)
1392{
1393 struct rtl_priv *rtlpriv = rtl_priv(hw);
1394 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1395 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
1396
1397 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, ("====>\n"));
1398 /*----Store original RFENV control type----*/
1399 switch (rfpath) {
1400 case RF90_PATH_A:
1401 case RF90_PATH_C:
1402 *pu4_regval = rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV);
1403 break;
1404 case RF90_PATH_B:
1405 case RF90_PATH_D:
1406 *pu4_regval =
1407 rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16);
1408 break;
1409 }
1410 /*----Set RF_ENV enable----*/
1411 rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
1412 udelay(1);
1413 /*----Set RF_ENV output high----*/
1414 rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
1415 udelay(1);
1416 /* Set bit number of Address and Data for RF register */
1417 /* Set 1 to 4 bits for 8255 */
1418 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREADDRESSLENGTH, 0x0);
1419 udelay(1);
1420 /*Set 0 to 12 bits for 8255 */
1421 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
1422 udelay(1);
1423 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, ("<====\n"));
1424}
1425
1426static void _rtl92d_phy_restore_rf_env(struct ieee80211_hw *hw, u8 rfpath,
1427 u32 *pu4_regval)
1428{
1429 struct rtl_priv *rtlpriv = rtl_priv(hw);
1430 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1431 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
1432
1433 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, ("=====>\n"));
1434 /*----Restore RFENV control type----*/ ;
1435 switch (rfpath) {
1436 case RF90_PATH_A:
1437 case RF90_PATH_C:
1438 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV, *pu4_regval);
1439 break;
1440 case RF90_PATH_B:
1441 case RF90_PATH_D:
1442 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16,
1443 *pu4_regval);
1444 break;
1445 }
1446 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, ("<=====\n"));
1447}
1448
1449static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel)
1450{
1451 struct rtl_priv *rtlpriv = rtl_priv(hw);
1452 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1453 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
1454 u8 path = rtlhal->current_bandtype ==
1455 BAND_ON_5G ? RF90_PATH_A : RF90_PATH_B;
1456 u8 index = 0, i = 0, rfpath = RF90_PATH_A;
1457 bool need_pwr_down = false, internal_pa = false;
1458 u32 u4regvalue, mask = 0x1C000, value = 0, u4tmp, u4tmp2;
1459
1460 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("====>\n"));
1461 /* config path A for 5G */
1462 if (rtlhal->current_bandtype == BAND_ON_5G) {
1463 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("====>5G\n"));
1464 u4tmp = curveindex_5g[channel - 1];
1465 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("ver 1 set RF-A, 5G, "
1466 "0x28 = 0x%x !!\n", u4tmp));
1467 for (i = 0; i < RF_CHNL_NUM_5G; i++) {
1468 if (channel == rf_chnl_5g[i] && channel <= 140)
1469 index = 0;
1470 }
1471 for (i = 0; i < RF_CHNL_NUM_5G_40M; i++) {
1472 if (channel == rf_chnl_5g_40m[i] && channel <= 140)
1473 index = 1;
1474 }
1475 if (channel == 149 || channel == 155 || channel == 161)
1476 index = 2;
1477 else if (channel == 151 || channel == 153 || channel == 163
1478 || channel == 165)
1479 index = 3;
1480 else if (channel == 157 || channel == 159)
1481 index = 4;
1482
1483 if (rtlhal->macphymode == DUALMAC_DUALPHY
1484 && rtlhal->interfaceindex == 1) {
1485 need_pwr_down = rtl92d_phy_enable_anotherphy(hw, false);
1486 rtlhal->during_mac1init_radioa = true;
1487 /* asume no this case */
1488 if (need_pwr_down)
1489 _rtl92d_phy_enable_rf_env(hw, path,
1490 &u4regvalue);
1491 }
1492 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_5G; i++) {
1493 if (i == 0 && (rtlhal->macphymode == DUALMAC_DUALPHY)) {
1494 rtl_set_rfreg(hw, (enum radio_path)path,
1495 rf_reg_for_c_cut_5g[i],
1496 BRFREGOFFSETMASK, 0xE439D);
1497 } else if (rf_reg_for_c_cut_5g[i] == RF_SYN_G4) {
1498 u4tmp2 = (rf_reg_pram_c_5g[index][i] &
1499 0x7FF) | (u4tmp << 11);
1500 if (channel == 36)
1501 u4tmp2 &= ~(BIT(7) | BIT(6));
1502 rtl_set_rfreg(hw, (enum radio_path)path,
1503 rf_reg_for_c_cut_5g[i],
1504 BRFREGOFFSETMASK, u4tmp2);
1505 } else {
1506 rtl_set_rfreg(hw, (enum radio_path)path,
1507 rf_reg_for_c_cut_5g[i],
1508 BRFREGOFFSETMASK,
1509 rf_reg_pram_c_5g[index][i]);
1510 }
1511 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
1512 ("offset 0x%x value 0x%x "
1513 "path %d index %d readback 0x%x\n",
1514 rf_reg_for_c_cut_5g[i],
1515 rf_reg_pram_c_5g[index][i], path,
1516 index, rtl_get_rfreg(hw, (enum radio_path)path,
1517 rf_reg_for_c_cut_5g[i], BRFREGOFFSETMASK)));
1518 }
1519 if (need_pwr_down)
1520 _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue);
1521 if (rtlhal->during_mac1init_radioa)
1522 rtl92d_phy_powerdown_anotherphy(hw, false);
1523 if (channel < 149)
1524 value = 0x07;
1525 else if (channel >= 149)
1526 value = 0x02;
1527 if (channel >= 36 && channel <= 64)
1528 index = 0;
1529 else if (channel >= 100 && channel <= 140)
1530 index = 1;
1531 else
1532 index = 2;
1533 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
1534 rfpath++) {
1535 if (rtlhal->macphymode == DUALMAC_DUALPHY &&
1536 rtlhal->interfaceindex == 1) /* MAC 1 5G */
1537 internal_pa = rtlpriv->efuse.internal_pa_5g[1];
1538 else
1539 internal_pa =
1540 rtlpriv->efuse.internal_pa_5g[rfpath];
1541 if (internal_pa) {
1542 for (i = 0;
1543 i < RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA;
1544 i++) {
1545 rtl_set_rfreg(hw, rfpath,
1546 rf_for_c_cut_5g_internal_pa[i],
1547 BRFREGOFFSETMASK,
1548 rf_pram_c_5g_int_pa[index][i]);
1549 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
1550 ("offset 0x%x value 0x%x "
1551 "path %d index %d\n",
1552 rf_for_c_cut_5g_internal_pa[i],
1553 rf_pram_c_5g_int_pa[index][i],
1554 rfpath, index));
1555 }
1556 } else {
1557 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B,
1558 mask, value);
1559 }
1560 }
1561 } else if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1562 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("====>2.4G\n"));
1563 u4tmp = curveindex_2g[channel - 1];
1564 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("ver 3 set RF-B, 2G, "
1565 "0x28 = 0x%x !!\n", u4tmp));
1566 if (channel == 1 || channel == 2 || channel == 4 || channel == 9
1567 || channel == 10 || channel == 11 || channel == 12)
1568 index = 0;
1569 else if (channel == 3 || channel == 13 || channel == 14)
1570 index = 1;
1571 else if (channel >= 5 && channel <= 8)
1572 index = 2;
1573 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
1574 path = RF90_PATH_A;
1575 if (rtlhal->interfaceindex == 0) {
1576 need_pwr_down =
1577 rtl92d_phy_enable_anotherphy(hw, true);
1578 rtlhal->during_mac0init_radiob = true;
1579
1580 if (need_pwr_down)
1581 _rtl92d_phy_enable_rf_env(hw, path,
1582 &u4regvalue);
1583 }
1584 }
1585 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_2G; i++) {
1586 if (rf_reg_for_c_cut_2g[i] == RF_SYN_G7)
1587 rtl_set_rfreg(hw, (enum radio_path)path,
1588 rf_reg_for_c_cut_2g[i],
1589 BRFREGOFFSETMASK,
1590 (rf_reg_param_for_c_cut_2g[index][i] |
1591 BIT(17)));
1592 else
1593 rtl_set_rfreg(hw, (enum radio_path)path,
1594 rf_reg_for_c_cut_2g[i],
1595 BRFREGOFFSETMASK,
1596 rf_reg_param_for_c_cut_2g
1597 [index][i]);
1598 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
1599 ("offset 0x%x value 0x%x mak 0x%x path %d "
1600 "index %d readback 0x%x\n",
1601 rf_reg_for_c_cut_2g[i],
1602 rf_reg_param_for_c_cut_2g[index][i],
1603 rf_reg_mask_for_c_cut_2g[i], path, index,
1604 rtl_get_rfreg(hw, (enum radio_path)path,
1605 rf_reg_for_c_cut_2g[i],
1606 BRFREGOFFSETMASK)));
1607 }
1608 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1609 ("cosa ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n",
1610 rf_syn_g4_for_c_cut_2g | (u4tmp << 11)));
1611
1612 rtl_set_rfreg(hw, (enum radio_path)path, RF_SYN_G4,
1613 BRFREGOFFSETMASK,
1614 rf_syn_g4_for_c_cut_2g | (u4tmp << 11));
1615 if (need_pwr_down)
1616 _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue);
1617 if (rtlhal->during_mac0init_radiob)
1618 rtl92d_phy_powerdown_anotherphy(hw, true);
1619 }
1620 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("<====\n"));
1621}
1622
1623u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl)
1624{
1625 u8 channel_all[59] = {
1626 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
1627 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
1628 60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
1629 114, 116, 118, 120, 122, 124, 126, 128, 130,
1630 132, 134, 136, 138, 140, 149, 151, 153, 155,
1631 157, 159, 161, 163, 165
1632 };
1633 u8 place = chnl;
1634
1635 if (chnl > 14) {
1636 for (place = 14; place < sizeof(channel_all); place++) {
1637 if (channel_all[place] == chnl)
1638 return place - 13;
1639 }
1640 }
1641
1642 return 0;
1643}
1644
1645#define MAX_TOLERANCE 5
1646#define IQK_DELAY_TIME 1 /* ms */
1647#define MAX_TOLERANCE_92D 3
1648
1649/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1650static u8 _rtl92d_phy_patha_iqk(struct ieee80211_hw *hw, bool configpathb)
1651{
1652 struct rtl_priv *rtlpriv = rtl_priv(hw);
1653 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1654 u32 regeac, rege94, rege9c, regea4;
1655 u8 result = 0;
1656
1657 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path A IQK!\n"));
1658 /* path-A IQK setting */
1659 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path-A IQK setting!\n"));
1660 if (rtlhal->interfaceindex == 0) {
1661 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x10008c1f);
1662 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x10008c1f);
1663 } else {
1664 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x10008c22);
1665 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x10008c22);
1666 }
1667 rtl_set_bbreg(hw, 0xe38, BMASKDWORD, 0x82140102);
1668 rtl_set_bbreg(hw, 0xe3c, BMASKDWORD, 0x28160206);
1669 /* path-B IQK setting */
1670 if (configpathb) {
1671 rtl_set_bbreg(hw, 0xe50, BMASKDWORD, 0x10008c22);
1672 rtl_set_bbreg(hw, 0xe54, BMASKDWORD, 0x10008c22);
1673 rtl_set_bbreg(hw, 0xe58, BMASKDWORD, 0x82140102);
1674 rtl_set_bbreg(hw, 0xe5c, BMASKDWORD, 0x28160206);
1675 }
1676 /* LO calibration setting */
1677 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("LO calibration setting!\n"));
1678 rtl_set_bbreg(hw, 0xe4c, BMASKDWORD, 0x00462911);
1679 /* One shot, path A LOK & IQK */
1680 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n"));
1681 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf9000000);
1682 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf8000000);
1683 /* delay x ms */
1684 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1685 ("Delay %d ms for One shot, path A LOK & IQK.\n",
1686 IQK_DELAY_TIME));
1687 udelay(IQK_DELAY_TIME * 1000);
1688 /* Check failed */
1689 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD);
1690 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xeac = 0x%x\n", regeac));
1691 rege94 = rtl_get_bbreg(hw, 0xe94, BMASKDWORD);
1692 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xe94 = 0x%x\n", rege94));
1693 rege9c = rtl_get_bbreg(hw, 0xe9c, BMASKDWORD);
1694 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xe9c = 0x%x\n", rege9c));
1695 regea4 = rtl_get_bbreg(hw, 0xea4, BMASKDWORD);
1696 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xea4 = 0x%x\n", regea4));
1697 if (!(regeac & BIT(28)) && (((rege94 & 0x03FF0000) >> 16) != 0x142) &&
1698 (((rege9c & 0x03FF0000) >> 16) != 0x42))
1699 result |= 0x01;
1700 else /* if Tx not OK, ignore Rx */
1701 return result;
1702 /* if Tx is OK, check whether Rx is OK */
1703 if (!(regeac & BIT(27)) && (((regea4 & 0x03FF0000) >> 16) != 0x132) &&
1704 (((regeac & 0x03FF0000) >> 16) != 0x36))
1705 result |= 0x02;
1706 else
1707 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n"));
1708 return result;
1709}
1710
1711/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1712static u8 _rtl92d_phy_patha_iqk_5g_normal(struct ieee80211_hw *hw,
1713 bool configpathb)
1714{
1715 struct rtl_priv *rtlpriv = rtl_priv(hw);
1716 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1717 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1718 u32 regeac, rege94, rege9c, regea4;
1719 u8 result = 0;
1720 u8 i;
1721 u8 retrycount = 2;
1722 u32 TxOKBit = BIT(28), RxOKBit = BIT(27);
1723
1724 if (rtlhal->interfaceindex == 1) { /* PHY1 */
1725 TxOKBit = BIT(31);
1726 RxOKBit = BIT(30);
1727 }
1728 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path A IQK!\n"));
1729 /* path-A IQK setting */
1730 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path-A IQK setting!\n"));
1731 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x18008c1f);
1732 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x18008c1f);
1733 rtl_set_bbreg(hw, 0xe38, BMASKDWORD, 0x82140307);
1734 rtl_set_bbreg(hw, 0xe3c, BMASKDWORD, 0x68160960);
1735 /* path-B IQK setting */
1736 if (configpathb) {
1737 rtl_set_bbreg(hw, 0xe50, BMASKDWORD, 0x18008c2f);
1738 rtl_set_bbreg(hw, 0xe54, BMASKDWORD, 0x18008c2f);
1739 rtl_set_bbreg(hw, 0xe58, BMASKDWORD, 0x82110000);
1740 rtl_set_bbreg(hw, 0xe5c, BMASKDWORD, 0x68110000);
1741 }
1742 /* LO calibration setting */
1743 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("LO calibration setting!\n"));
1744 rtl_set_bbreg(hw, 0xe4c, BMASKDWORD, 0x00462911);
1745 /* path-A PA on */
1746 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD, 0x07000f60);
1747 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BMASKDWORD, 0x66e60e30);
1748 for (i = 0; i < retrycount; i++) {
1749 /* One shot, path A LOK & IQK */
1750 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1751 ("One shot, path A LOK & IQK!\n"));
1752 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf9000000);
1753 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf8000000);
1754 /* delay x ms */
1755 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1756 ("Delay %d ms for One shot, path A LOK & IQK.\n",
1757 IQK_DELAY_TIME));
1758 udelay(IQK_DELAY_TIME * 1000 * 10);
1759 /* Check failed */
1760 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD);
1761 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xeac = 0x%x\n", regeac));
1762 rege94 = rtl_get_bbreg(hw, 0xe94, BMASKDWORD);
1763 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xe94 = 0x%x\n", rege94));
1764 rege9c = rtl_get_bbreg(hw, 0xe9c, BMASKDWORD);
1765 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xe9c = 0x%x\n", rege9c));
1766 regea4 = rtl_get_bbreg(hw, 0xea4, BMASKDWORD);
1767 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xea4 = 0x%x\n", regea4));
1768 if (!(regeac & TxOKBit) &&
1769 (((rege94 & 0x03FF0000) >> 16) != 0x142)) {
1770 result |= 0x01;
1771 } else { /* if Tx not OK, ignore Rx */
1772 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1773 ("Path A Tx IQK fail!!\n"));
1774 continue;
1775 }
1776
1777 /* if Tx is OK, check whether Rx is OK */
1778 if (!(regeac & RxOKBit) &&
1779 (((regea4 & 0x03FF0000) >> 16) != 0x132)) {
1780 result |= 0x02;
1781 break;
1782 } else {
1783 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1784 ("Path A Rx IQK fail!!\n"));
1785 }
1786 }
1787 /* path A PA off */
1788 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD,
1789 rtlphy->iqk_bb_backup[0]);
1790 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BMASKDWORD,
1791 rtlphy->iqk_bb_backup[1]);
1792 return result;
1793}
1794
1795/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1796static u8 _rtl92d_phy_pathb_iqk(struct ieee80211_hw *hw)
1797{
1798 struct rtl_priv *rtlpriv = rtl_priv(hw);
1799 u32 regeac, regeb4, regebc, regec4, regecc;
1800 u8 result = 0;
1801
1802 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path B IQK!\n"));
1803 /* One shot, path B LOK & IQK */
1804 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n"));
1805 rtl_set_bbreg(hw, 0xe60, BMASKDWORD, 0x00000002);
1806 rtl_set_bbreg(hw, 0xe60, BMASKDWORD, 0x00000000);
1807 /* delay x ms */
1808 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1809 ("Delay %d ms for One shot, path B LOK & IQK.\n",
1810 IQK_DELAY_TIME));
1811 udelay(IQK_DELAY_TIME * 1000);
1812 /* Check failed */
1813 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD);
1814 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xeac = 0x%x\n", regeac));
1815 regeb4 = rtl_get_bbreg(hw, 0xeb4, BMASKDWORD);
1816 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xeb4 = 0x%x\n", regeb4));
1817 regebc = rtl_get_bbreg(hw, 0xebc, BMASKDWORD);
1818 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xebc = 0x%x\n", regebc));
1819 regec4 = rtl_get_bbreg(hw, 0xec4, BMASKDWORD);
1820 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xec4 = 0x%x\n", regec4));
1821 regecc = rtl_get_bbreg(hw, 0xecc, BMASKDWORD);
1822 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xecc = 0x%x\n", regecc));
1823 if (!(regeac & BIT(31)) && (((regeb4 & 0x03FF0000) >> 16) != 0x142) &&
1824 (((regebc & 0x03FF0000) >> 16) != 0x42))
1825 result |= 0x01;
1826 else
1827 return result;
1828 if (!(regeac & BIT(30)) && (((regec4 & 0x03FF0000) >> 16) != 0x132) &&
1829 (((regecc & 0x03FF0000) >> 16) != 0x36))
1830 result |= 0x02;
1831 else
1832 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path B Rx IQK fail!!\n"));
1833 return result;
1834}
1835
1836/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1837static u8 _rtl92d_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw)
1838{
1839 struct rtl_priv *rtlpriv = rtl_priv(hw);
1840 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1841 u32 regeac, regeb4, regebc, regec4, regecc;
1842 u8 result = 0;
1843 u8 i;
1844 u8 retrycount = 2;
1845
1846 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path B IQK!\n"));
1847 /* path-A IQK setting */
1848 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path-A IQK setting!\n"));
1849 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x18008c1f);
1850 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x18008c1f);
1851 rtl_set_bbreg(hw, 0xe38, BMASKDWORD, 0x82110000);
1852 rtl_set_bbreg(hw, 0xe3c, BMASKDWORD, 0x68110000);
1853
1854 /* path-B IQK setting */
1855 rtl_set_bbreg(hw, 0xe50, BMASKDWORD, 0x18008c2f);
1856 rtl_set_bbreg(hw, 0xe54, BMASKDWORD, 0x18008c2f);
1857 rtl_set_bbreg(hw, 0xe58, BMASKDWORD, 0x82140307);
1858 rtl_set_bbreg(hw, 0xe5c, BMASKDWORD, 0x68160960);
1859
1860 /* LO calibration setting */
1861 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("LO calibration setting!\n"));
1862 rtl_set_bbreg(hw, 0xe4c, BMASKDWORD, 0x00462911);
1863
1864 /* path-B PA on */
1865 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD, 0x0f600700);
1866 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BMASKDWORD, 0x061f0d30);
1867
1868 for (i = 0; i < retrycount; i++) {
1869 /* One shot, path B LOK & IQK */
1870 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1871 ("One shot, path A LOK & IQK!\n"));
1872 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xfa000000);
1873 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf8000000);
1874
1875 /* delay x ms */
1876 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1877 ("Delay %d ms for One shot, path B LOK & IQK.\n", 10));
1878 udelay(IQK_DELAY_TIME * 1000 * 10);
1879
1880 /* Check failed */
1881 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD);
1882 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xeac = 0x%x\n", regeac));
1883 regeb4 = rtl_get_bbreg(hw, 0xeb4, BMASKDWORD);
1884 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xeb4 = 0x%x\n", regeb4));
1885 regebc = rtl_get_bbreg(hw, 0xebc, BMASKDWORD);
1886 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xebc = 0x%x\n", regebc));
1887 regec4 = rtl_get_bbreg(hw, 0xec4, BMASKDWORD);
1888 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xec4 = 0x%x\n", regec4));
1889 regecc = rtl_get_bbreg(hw, 0xecc, BMASKDWORD);
1890 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xecc = 0x%x\n", regecc));
1891 if (!(regeac & BIT(31)) &&
1892 (((regeb4 & 0x03FF0000) >> 16) != 0x142))
1893 result |= 0x01;
1894 else
1895 continue;
1896 if (!(regeac & BIT(30)) &&
1897 (((regec4 & 0x03FF0000) >> 16) != 0x132)) {
1898 result |= 0x02;
1899 break;
1900 } else {
1901 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1902 ("Path B Rx IQK fail!!\n"));
1903 }
1904 }
1905
1906 /* path B PA off */
1907 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD,
1908 rtlphy->iqk_bb_backup[0]);
1909 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BMASKDWORD,
1910 rtlphy->iqk_bb_backup[2]);
1911 return result;
1912}
1913
1914static void _rtl92d_phy_save_adda_registers(struct ieee80211_hw *hw,
1915 u32 *adda_reg, u32 *adda_backup,
1916 u32 regnum)
1917{
1918 struct rtl_priv *rtlpriv = rtl_priv(hw);
1919 u32 i;
1920
1921 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Save ADDA parameters.\n"));
1922 for (i = 0; i < regnum; i++)
1923 adda_backup[i] = rtl_get_bbreg(hw, adda_reg[i], BMASKDWORD);
1924}
1925
1926static void _rtl92d_phy_save_mac_registers(struct ieee80211_hw *hw,
1927 u32 *macreg, u32 *macbackup)
1928{
1929 struct rtl_priv *rtlpriv = rtl_priv(hw);
1930 u32 i;
1931
1932 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Save MAC parameters.\n"));
1933 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1934 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
1935 macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
1936}
1937
1938static void _rtl92d_phy_reload_adda_registers(struct ieee80211_hw *hw,
1939 u32 *adda_reg, u32 *adda_backup,
1940 u32 regnum)
1941{
1942 struct rtl_priv *rtlpriv = rtl_priv(hw);
1943 u32 i;
1944
1945 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1946 ("Reload ADDA power saving parameters !\n"));
1947 for (i = 0; i < regnum; i++)
1948 rtl_set_bbreg(hw, adda_reg[i], BMASKDWORD, adda_backup[i]);
1949}
1950
1951static void _rtl92d_phy_reload_mac_registers(struct ieee80211_hw *hw,
1952 u32 *macreg, u32 *macbackup)
1953{
1954 struct rtl_priv *rtlpriv = rtl_priv(hw);
1955 u32 i;
1956
1957 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Reload MAC parameters !\n"));
1958 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1959 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
1960 rtl_write_byte(rtlpriv, macreg[i], macbackup[i]);
1961}
1962
1963static void _rtl92d_phy_path_adda_on(struct ieee80211_hw *hw,
1964 u32 *adda_reg, bool patha_on, bool is2t)
1965{
1966 struct rtl_priv *rtlpriv = rtl_priv(hw);
1967 u32 pathon;
1968 u32 i;
1969
1970 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("ADDA ON.\n"));
1971 pathon = patha_on ? 0x04db25a4 : 0x0b1b25a4;
1972 if (patha_on)
1973 pathon = rtlpriv->rtlhal.interfaceindex == 0 ?
1974 0x04db25a4 : 0x0b1b25a4;
1975 for (i = 0; i < IQK_ADDA_REG_NUM; i++)
1976 rtl_set_bbreg(hw, adda_reg[i], BMASKDWORD, pathon);
1977}
1978
1979static void _rtl92d_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1980 u32 *macreg, u32 *macbackup)
1981{
1982 struct rtl_priv *rtlpriv = rtl_priv(hw);
1983 u32 i;
1984
1985 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("MAC settings for Calibration.\n"));
1986 rtl_write_byte(rtlpriv, macreg[0], 0x3F);
1987
1988 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1989 rtl_write_byte(rtlpriv, macreg[i], (u8)(macbackup[i] &
1990 (~BIT(3))));
1991 rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5))));
1992}
1993
1994static void _rtl92d_phy_patha_standby(struct ieee80211_hw *hw)
1995{
1996 struct rtl_priv *rtlpriv = rtl_priv(hw);
1997 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path-A standby mode!\n"));
1998
1999 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x0);
2000 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, BMASKDWORD, 0x00010000);
2001 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x80800000);
2002}
2003
2004static void _rtl92d_phy_pimode_switch(struct ieee80211_hw *hw, bool pi_mode)
2005{
2006 struct rtl_priv *rtlpriv = rtl_priv(hw);
2007 u32 mode;
2008
2009 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2010 ("BB Switch to %s mode!\n", (pi_mode ? "PI" : "SI")));
2011 mode = pi_mode ? 0x01000100 : 0x01000000;
2012 rtl_set_bbreg(hw, 0x820, BMASKDWORD, mode);
2013 rtl_set_bbreg(hw, 0x828, BMASKDWORD, mode);
2014}
2015
2016static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
2017 u8 t, bool is2t)
2018{
2019 struct rtl_priv *rtlpriv = rtl_priv(hw);
2020 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2021 u32 i;
2022 u8 patha_ok, pathb_ok;
2023 static u32 adda_reg[IQK_ADDA_REG_NUM] = {
2024 RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74,
2025 0xe78, 0xe7c, 0xe80, 0xe84,
2026 0xe88, 0xe8c, 0xed0, 0xed4,
2027 0xed8, 0xedc, 0xee0, 0xeec
2028 };
2029 static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
2030 0x522, 0x550, 0x551, 0x040
2031 };
2032 static u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
2033 RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE,
2034 RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR,
2035 RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
2036 RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4,
2037 ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1
2038 };
2039 const u32 retrycount = 2;
2040 u32 bbvalue;
2041
2042 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("IQK for 2.4G :Start!!!\n"));
2043 if (t == 0) {
2044 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, BMASKDWORD);
2045 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("==>0x%08x\n", bbvalue));
2046 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("IQ Calibration for %s\n",
2047 (is2t ? "2T2R" : "1T1R")));
2048
2049 /* Save ADDA parameters, turn Path A ADDA on */
2050 _rtl92d_phy_save_adda_registers(hw, adda_reg,
2051 rtlphy->adda_backup, IQK_ADDA_REG_NUM);
2052 _rtl92d_phy_save_mac_registers(hw, iqk_mac_reg,
2053 rtlphy->iqk_mac_backup);
2054 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
2055 rtlphy->iqk_bb_backup, IQK_BB_REG_NUM);
2056 }
2057 _rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t);
2058 if (t == 0)
2059 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
2060 RFPGA0_XA_HSSIPARAMETER1, BIT(8));
2061
2062 /* Switch BB to PI mode to do IQ Calibration. */
2063 if (!rtlphy->rfpi_enable)
2064 _rtl92d_phy_pimode_switch(hw, true);
2065
2066 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
2067 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKDWORD, 0x03a05600);
2068 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, BMASKDWORD, 0x000800e4);
2069 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, BMASKDWORD, 0x22204000);
2070 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f);
2071 if (is2t) {
2072 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, BMASKDWORD,
2073 0x00010000);
2074 rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, BMASKDWORD,
2075 0x00010000);
2076 }
2077 /* MAC settings */
2078 _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg,
2079 rtlphy->iqk_mac_backup);
2080 /* Page B init */
2081 rtl_set_bbreg(hw, 0xb68, BMASKDWORD, 0x0f600000);
2082 if (is2t)
2083 rtl_set_bbreg(hw, 0xb6c, BMASKDWORD, 0x0f600000);
2084 /* IQ calibration setting */
2085 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("IQK setting!\n"));
2086 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x80800000);
2087 rtl_set_bbreg(hw, 0xe40, BMASKDWORD, 0x01007c00);
2088 rtl_set_bbreg(hw, 0xe44, BMASKDWORD, 0x01004800);
2089 for (i = 0; i < retrycount; i++) {
2090 patha_ok = _rtl92d_phy_patha_iqk(hw, is2t);
2091 if (patha_ok == 0x03) {
2092 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2093 ("Path A IQK Success!!\n"));
2094 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) &
2095 0x3FF0000) >> 16;
2096 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) &
2097 0x3FF0000) >> 16;
2098 result[t][2] = (rtl_get_bbreg(hw, 0xea4, BMASKDWORD) &
2099 0x3FF0000) >> 16;
2100 result[t][3] = (rtl_get_bbreg(hw, 0xeac, BMASKDWORD) &
2101 0x3FF0000) >> 16;
2102 break;
2103 } else if (i == (retrycount - 1) && patha_ok == 0x01) {
2104 /* Tx IQK OK */
2105 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2106 ("Path A IQK Only Tx Success!!\n"));
2107
2108 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) &
2109 0x3FF0000) >> 16;
2110 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) &
2111 0x3FF0000) >> 16;
2112 }
2113 }
2114 if (0x00 == patha_ok)
2115 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path A IQK failed!!\n"));
2116 if (is2t) {
2117 _rtl92d_phy_patha_standby(hw);
2118 /* Turn Path B ADDA on */
2119 _rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t);
2120 for (i = 0; i < retrycount; i++) {
2121 pathb_ok = _rtl92d_phy_pathb_iqk(hw);
2122 if (pathb_ok == 0x03) {
2123 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2124 ("Path B IQK Success!!\n"));
2125 result[t][4] = (rtl_get_bbreg(hw, 0xeb4,
2126 BMASKDWORD) & 0x3FF0000) >> 16;
2127 result[t][5] = (rtl_get_bbreg(hw, 0xebc,
2128 BMASKDWORD) & 0x3FF0000) >> 16;
2129 result[t][6] = (rtl_get_bbreg(hw, 0xec4,
2130 BMASKDWORD) & 0x3FF0000) >> 16;
2131 result[t][7] = (rtl_get_bbreg(hw, 0xecc,
2132 BMASKDWORD) & 0x3FF0000) >> 16;
2133 break;
2134 } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
2135 /* Tx IQK OK */
2136 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2137 ("Path B Only Tx IQK Success!!\n"));
2138 result[t][4] = (rtl_get_bbreg(hw, 0xeb4,
2139 BMASKDWORD) & 0x3FF0000) >> 16;
2140 result[t][5] = (rtl_get_bbreg(hw, 0xebc,
2141 BMASKDWORD) & 0x3FF0000) >> 16;
2142 }
2143 }
2144 if (0x00 == pathb_ok)
2145 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2146 ("Path B IQK failed!!\n"));
2147 }
2148
2149 /* Back to BB mode, load original value */
2150 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2151 ("IQK:Back to BB mode, load original value!\n"));
2152
2153 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0);
2154 if (t != 0) {
2155 /* Switch back BB to SI mode after finish IQ Calibration. */
2156 if (!rtlphy->rfpi_enable)
2157 _rtl92d_phy_pimode_switch(hw, false);
2158 /* Reload ADDA power saving parameters */
2159 _rtl92d_phy_reload_adda_registers(hw, adda_reg,
2160 rtlphy->adda_backup, IQK_ADDA_REG_NUM);
2161 /* Reload MAC parameters */
2162 _rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg,
2163 rtlphy->iqk_mac_backup);
2164 if (is2t)
2165 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2166 rtlphy->iqk_bb_backup,
2167 IQK_BB_REG_NUM);
2168 else
2169 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2170 rtlphy->iqk_bb_backup,
2171 IQK_BB_REG_NUM - 1);
2172 /* load 0xe30 IQC default value */
2173 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x01008c00);
2174 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x01008c00);
2175 }
2176 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("<==\n"));
2177}
2178
2179static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw,
2180 long result[][8], u8 t)
2181{
2182 struct rtl_priv *rtlpriv = rtl_priv(hw);
2183 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2184 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2185 u8 patha_ok, pathb_ok;
2186 static u32 adda_reg[IQK_ADDA_REG_NUM] = {
2187 RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74,
2188 0xe78, 0xe7c, 0xe80, 0xe84,
2189 0xe88, 0xe8c, 0xed0, 0xed4,
2190 0xed8, 0xedc, 0xee0, 0xeec
2191 };
2192 static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
2193 0x522, 0x550, 0x551, 0x040
2194 };
2195 static u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
2196 RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE,
2197 RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR,
2198 RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
2199 RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4,
2200 ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1
2201 };
2202 u32 bbvalue;
2203 bool is2t = IS_92D_SINGLEPHY(rtlhal->version);
2204
2205 /* Note: IQ calibration must be performed after loading
2206 * PHY_REG.txt , and radio_a, radio_b.txt */
2207
2208 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("IQK for 5G NORMAL:Start!!!\n"));
2209 udelay(IQK_DELAY_TIME * 1000 * 20);
2210 if (t == 0) {
2211 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, BMASKDWORD);
2212 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("==>0x%08x\n", bbvalue));
2213 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("IQ Calibration for %s\n",
2214 (is2t ? "2T2R" : "1T1R")));
2215 /* Save ADDA parameters, turn Path A ADDA on */
2216 _rtl92d_phy_save_adda_registers(hw, adda_reg,
2217 rtlphy->adda_backup,
2218 IQK_ADDA_REG_NUM);
2219 _rtl92d_phy_save_mac_registers(hw, iqk_mac_reg,
2220 rtlphy->iqk_mac_backup);
2221 if (is2t)
2222 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
2223 rtlphy->iqk_bb_backup,
2224 IQK_BB_REG_NUM);
2225 else
2226 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
2227 rtlphy->iqk_bb_backup,
2228 IQK_BB_REG_NUM - 1);
2229 }
2230 _rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t);
2231 /* MAC settings */
2232 _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg,
2233 rtlphy->iqk_mac_backup);
2234 if (t == 0)
2235 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
2236 RFPGA0_XA_HSSIPARAMETER1, BIT(8));
2237 /* Switch BB to PI mode to do IQ Calibration. */
2238 if (!rtlphy->rfpi_enable)
2239 _rtl92d_phy_pimode_switch(hw, true);
2240 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
2241 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKDWORD, 0x03a05600);
2242 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, BMASKDWORD, 0x000800e4);
2243 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, BMASKDWORD, 0x22208000);
2244 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f);
2245
2246 /* Page B init */
2247 rtl_set_bbreg(hw, 0xb68, BMASKDWORD, 0x0f600000);
2248 if (is2t)
2249 rtl_set_bbreg(hw, 0xb6c, BMASKDWORD, 0x0f600000);
2250 /* IQ calibration setting */
2251 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("IQK setting!\n"));
2252 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x80800000);
2253 rtl_set_bbreg(hw, 0xe40, BMASKDWORD, 0x10007c00);
2254 rtl_set_bbreg(hw, 0xe44, BMASKDWORD, 0x01004800);
2255 patha_ok = _rtl92d_phy_patha_iqk_5g_normal(hw, is2t);
2256 if (patha_ok == 0x03) {
2257 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path A IQK Success!!\n"));
2258 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) &
2259 0x3FF0000) >> 16;
2260 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) &
2261 0x3FF0000) >> 16;
2262 result[t][2] = (rtl_get_bbreg(hw, 0xea4, BMASKDWORD) &
2263 0x3FF0000) >> 16;
2264 result[t][3] = (rtl_get_bbreg(hw, 0xeac, BMASKDWORD) &
2265 0x3FF0000) >> 16;
2266 } else if (patha_ok == 0x01) { /* Tx IQK OK */
2267 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2268 ("Path A IQK Only Tx Success!!\n"));
2269
2270 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) &
2271 0x3FF0000) >> 16;
2272 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) &
2273 0x3FF0000) >> 16;
2274 } else {
2275 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path A IQK Fail!!\n"));
2276 }
2277 if (is2t) {
2278 /* _rtl92d_phy_patha_standby(hw); */
2279 /* Turn Path B ADDA on */
2280 _rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t);
2281 pathb_ok = _rtl92d_phy_pathb_iqk_5g_normal(hw);
2282 if (pathb_ok == 0x03) {
2283 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2284 ("Path B IQK Success!!\n"));
2285 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, BMASKDWORD) &
2286 0x3FF0000) >> 16;
2287 result[t][5] = (rtl_get_bbreg(hw, 0xebc, BMASKDWORD) &
2288 0x3FF0000) >> 16;
2289 result[t][6] = (rtl_get_bbreg(hw, 0xec4, BMASKDWORD) &
2290 0x3FF0000) >> 16;
2291 result[t][7] = (rtl_get_bbreg(hw, 0xecc, BMASKDWORD) &
2292 0x3FF0000) >> 16;
2293 } else if (pathb_ok == 0x01) { /* Tx IQK OK */
2294 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2295 ("Path B Only Tx IQK Success!!\n"));
2296 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, BMASKDWORD) &
2297 0x3FF0000) >> 16;
2298 result[t][5] = (rtl_get_bbreg(hw, 0xebc, BMASKDWORD) &
2299 0x3FF0000) >> 16;
2300 } else {
2301 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2302 ("Path B IQK failed!!\n"));
2303 }
2304 }
2305
2306 /* Back to BB mode, load original value */
2307 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2308 ("IQK:Back to BB mode, load original value!\n"));
2309 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0);
2310 if (t != 0) {
2311 if (is2t)
2312 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2313 rtlphy->iqk_bb_backup,
2314 IQK_BB_REG_NUM);
2315 else
2316 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2317 rtlphy->iqk_bb_backup,
2318 IQK_BB_REG_NUM - 1);
2319 /* Reload MAC parameters */
2320 _rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg,
2321 rtlphy->iqk_mac_backup);
2322 /* Switch back BB to SI mode after finish IQ Calibration. */
2323 if (!rtlphy->rfpi_enable)
2324 _rtl92d_phy_pimode_switch(hw, false);
2325 /* Reload ADDA power saving parameters */
2326 _rtl92d_phy_reload_adda_registers(hw, adda_reg,
2327 rtlphy->adda_backup,
2328 IQK_ADDA_REG_NUM);
2329 }
2330 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("<==\n"));
2331}
2332
2333static bool _rtl92d_phy_simularity_compare(struct ieee80211_hw *hw,
2334 long result[][8], u8 c1, u8 c2)
2335{
2336 struct rtl_priv *rtlpriv = rtl_priv(hw);
2337 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2338 u32 i, j, diff, sim_bitmap, bound;
2339 u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */
2340 bool bresult = true;
2341 bool is2t = IS_92D_SINGLEPHY(rtlhal->version);
2342
2343 if (is2t)
2344 bound = 8;
2345 else
2346 bound = 4;
2347 sim_bitmap = 0;
2348 for (i = 0; i < bound; i++) {
2349 diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] -
2350 result[c2][i]) : (result[c2][i] - result[c1][i]);
2351 if (diff > MAX_TOLERANCE_92D) {
2352 if ((i == 2 || i == 6) && !sim_bitmap) {
2353 if (result[c1][i] + result[c1][i + 1] == 0)
2354 final_candidate[(i / 4)] = c2;
2355 else if (result[c2][i] + result[c2][i + 1] == 0)
2356 final_candidate[(i / 4)] = c1;
2357 else
2358 sim_bitmap = sim_bitmap | (1 << i);
2359 } else {
2360 sim_bitmap = sim_bitmap | (1 << i);
2361 }
2362 }
2363 }
2364 if (sim_bitmap == 0) {
2365 for (i = 0; i < (bound / 4); i++) {
2366 if (final_candidate[i] != 0xFF) {
2367 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2368 result[3][j] =
2369 result[final_candidate[i]][j];
2370 bresult = false;
2371 }
2372 }
2373 return bresult;
2374 }
2375 if (!(sim_bitmap & 0x0F)) { /* path A OK */
2376 for (i = 0; i < 4; i++)
2377 result[3][i] = result[c1][i];
2378 } else if (!(sim_bitmap & 0x03)) { /* path A, Tx OK */
2379 for (i = 0; i < 2; i++)
2380 result[3][i] = result[c1][i];
2381 }
2382 if (!(sim_bitmap & 0xF0) && is2t) { /* path B OK */
2383 for (i = 4; i < 8; i++)
2384 result[3][i] = result[c1][i];
2385 } else if (!(sim_bitmap & 0x30)) { /* path B, Tx OK */
2386 for (i = 4; i < 6; i++)
2387 result[3][i] = result[c1][i];
2388 }
2389 return false;
2390}
2391
2392static void _rtl92d_phy_patha_fill_iqk_matrix(struct ieee80211_hw *hw,
2393 bool iqk_ok, long result[][8],
2394 u8 final_candidate, bool txonly)
2395{
2396 struct rtl_priv *rtlpriv = rtl_priv(hw);
2397 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2398 u32 oldval_0, val_x, tx0_a, reg;
2399 long val_y, tx0_c;
2400 bool is2t = IS_92D_SINGLEPHY(rtlhal->version) ||
2401 rtlhal->macphymode == DUALMAC_DUALPHY;
2402
2403 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2404 ("Path A IQ Calibration %s !\n",
2405 (iqk_ok) ? "Success" : "Failed"));
2406 if (final_candidate == 0xFF) {
2407 return;
2408 } else if (iqk_ok) {
2409 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
2410 BMASKDWORD) >> 22) & 0x3FF; /* OFDM0_D */
2411 val_x = result[final_candidate][0];
2412 if ((val_x & 0x00000200) != 0)
2413 val_x = val_x | 0xFFFFFC00;
2414 tx0_a = (val_x * oldval_0) >> 8;
2415 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("X = 0x%x, tx0_a = 0x%x,"
2416 " oldval_0 0x%x\n", val_x, tx0_a, oldval_0));
2417 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 0x3FF, tx0_a);
2418 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24),
2419 ((val_x * oldval_0 >> 7) & 0x1));
2420 val_y = result[final_candidate][1];
2421 if ((val_y & 0x00000200) != 0)
2422 val_y = val_y | 0xFFFFFC00;
2423 /* path B IQK result + 3 */
2424 if (rtlhal->interfaceindex == 1 &&
2425 rtlhal->current_bandtype == BAND_ON_5G)
2426 val_y += 3;
2427 tx0_c = (val_y * oldval_0) >> 8;
2428 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Y = 0x%lx, tx0_c = 0x%lx\n",
2429 val_y, tx0_c));
2430 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000,
2431 ((tx0_c & 0x3C0) >> 6));
2432 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 0x003F0000,
2433 (tx0_c & 0x3F));
2434 if (is2t)
2435 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26),
2436 ((val_y * oldval_0 >> 7) & 0x1));
2437 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xC80 = 0x%x\n",
2438 rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
2439 BMASKDWORD)));
2440 if (txonly) {
2441 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("only Tx OK\n"));
2442 return;
2443 }
2444 reg = result[final_candidate][2];
2445 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
2446 reg = result[final_candidate][3] & 0x3F;
2447 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
2448 reg = (result[final_candidate][3] >> 6) & 0xF;
2449 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
2450 }
2451}
2452
2453static void _rtl92d_phy_pathb_fill_iqk_matrix(struct ieee80211_hw *hw,
2454 bool iqk_ok, long result[][8], u8 final_candidate, bool txonly)
2455{
2456 struct rtl_priv *rtlpriv = rtl_priv(hw);
2457 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2458 u32 oldval_1, val_x, tx1_a, reg;
2459 long val_y, tx1_c;
2460
2461 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path B IQ Calibration %s !\n",
2462 (iqk_ok) ? "Success" : "Failed"));
2463 if (final_candidate == 0xFF) {
2464 return;
2465 } else if (iqk_ok) {
2466 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTxIQIMBALANCE,
2467 BMASKDWORD) >> 22) & 0x3FF;
2468 val_x = result[final_candidate][4];
2469 if ((val_x & 0x00000200) != 0)
2470 val_x = val_x | 0xFFFFFC00;
2471 tx1_a = (val_x * oldval_1) >> 8;
2472 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("X = 0x%x, tx1_a = 0x%x\n",
2473 val_x, tx1_a));
2474 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 0x3FF, tx1_a);
2475 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28),
2476 ((val_x * oldval_1 >> 7) & 0x1));
2477 val_y = result[final_candidate][5];
2478 if ((val_y & 0x00000200) != 0)
2479 val_y = val_y | 0xFFFFFC00;
2480 if (rtlhal->current_bandtype == BAND_ON_5G)
2481 val_y += 3;
2482 tx1_c = (val_y * oldval_1) >> 8;
2483 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Y = 0x%lx, tx1_c = 0x%lx\n",
2484 val_y, tx1_c));
2485 rtl_set_bbreg(hw, ROFDM0_XDTxAFE, 0xF0000000,
2486 ((tx1_c & 0x3C0) >> 6));
2487 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 0x003F0000,
2488 (tx1_c & 0x3F));
2489 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30),
2490 ((val_y * oldval_1 >> 7) & 0x1));
2491 if (txonly)
2492 return;
2493 reg = result[final_candidate][6];
2494 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
2495 reg = result[final_candidate][7] & 0x3F;
2496 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg);
2497 reg = (result[final_candidate][7] >> 6) & 0xF;
2498 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg);
2499 }
2500}
2501
2502void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw)
2503{
2504 struct rtl_priv *rtlpriv = rtl_priv(hw);
2505 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2506 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2507 long result[4][8];
2508 u8 i, final_candidate, indexforchannel;
2509 bool patha_ok, pathb_ok;
2510 long rege94, rege9c, regea4, regeac, regeb4;
2511 long regebc, regec4, regecc, regtmp = 0;
2512 bool is12simular, is13simular, is23simular;
2513 unsigned long flag = 0;
2514
2515 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2516 ("IQK:Start!!!channel %d\n", rtlphy->current_channel));
2517 for (i = 0; i < 8; i++) {
2518 result[0][i] = 0;
2519 result[1][i] = 0;
2520 result[2][i] = 0;
2521 result[3][i] = 0;
2522 }
2523 final_candidate = 0xff;
2524 patha_ok = false;
2525 pathb_ok = false;
2526 is12simular = false;
2527 is23simular = false;
2528 is13simular = false;
2529 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2530 ("IQK !!!currentband %d\n", rtlhal->current_bandtype));
2531 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
2532 for (i = 0; i < 3; i++) {
2533 if (rtlhal->current_bandtype == BAND_ON_5G) {
2534 _rtl92d_phy_iq_calibrate_5g_normal(hw, result, i);
2535 } else if (rtlhal->current_bandtype == BAND_ON_2_4G) {
2536 if (IS_92D_SINGLEPHY(rtlhal->version))
2537 _rtl92d_phy_iq_calibrate(hw, result, i, true);
2538 else
2539 _rtl92d_phy_iq_calibrate(hw, result, i, false);
2540 }
2541 if (i == 1) {
2542 is12simular = _rtl92d_phy_simularity_compare(hw, result,
2543 0, 1);
2544 if (is12simular) {
2545 final_candidate = 0;
2546 break;
2547 }
2548 }
2549 if (i == 2) {
2550 is13simular = _rtl92d_phy_simularity_compare(hw, result,
2551 0, 2);
2552 if (is13simular) {
2553 final_candidate = 0;
2554 break;
2555 }
2556 is23simular = _rtl92d_phy_simularity_compare(hw, result,
2557 1, 2);
2558 if (is23simular) {
2559 final_candidate = 1;
2560 } else {
2561 for (i = 0; i < 8; i++)
2562 regtmp += result[3][i];
2563
2564 if (regtmp != 0)
2565 final_candidate = 3;
2566 else
2567 final_candidate = 0xFF;
2568 }
2569 }
2570 }
2571 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
2572 for (i = 0; i < 4; i++) {
2573 rege94 = result[i][0];
2574 rege9c = result[i][1];
2575 regea4 = result[i][2];
2576 regeac = result[i][3];
2577 regeb4 = result[i][4];
2578 regebc = result[i][5];
2579 regec4 = result[i][6];
2580 regecc = result[i][7];
2581 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2582 ("IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx "
2583 "regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n ",
2584 rege94, rege9c, regea4, regeac, regeb4, regebc, regec4,
2585 regecc));
2586 }
2587 if (final_candidate != 0xff) {
2588 rtlphy->reg_e94 = rege94 = result[final_candidate][0];
2589 rtlphy->reg_e9c = rege9c = result[final_candidate][1];
2590 regea4 = result[final_candidate][2];
2591 regeac = result[final_candidate][3];
2592 rtlphy->reg_eb4 = regeb4 = result[final_candidate][4];
2593 rtlphy->reg_ebc = regebc = result[final_candidate][5];
2594 regec4 = result[final_candidate][6];
2595 regecc = result[final_candidate][7];
2596 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2597 ("IQK: final_candidate is %x\n", final_candidate));
2598 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2599 ("IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx "
2600 "regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n ",
2601 rege94, rege9c, regea4, regeac, regeb4, regebc, regec4,
2602 regecc));
2603 patha_ok = pathb_ok = true;
2604 } else {
2605 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100; /* X default value */
2606 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0; /* Y default value */
2607 }
2608 if ((rege94 != 0) /*&&(regea4 != 0) */)
2609 _rtl92d_phy_patha_fill_iqk_matrix(hw, patha_ok, result,
2610 final_candidate, (regea4 == 0));
2611 if (IS_92D_SINGLEPHY(rtlhal->version)) {
2612 if ((regeb4 != 0) /*&&(regec4 != 0) */)
2613 _rtl92d_phy_pathb_fill_iqk_matrix(hw, pathb_ok, result,
2614 final_candidate, (regec4 == 0));
2615 }
2616 if (final_candidate != 0xFF) {
2617 indexforchannel = rtl92d_get_rightchnlplace_for_iqk(
2618 rtlphy->current_channel);
2619
2620 for (i = 0; i < IQK_MATRIX_REG_NUM; i++)
2621 rtlphy->iqk_matrix_regsetting[indexforchannel].
2622 value[0][i] = result[final_candidate][i];
2623 rtlphy->iqk_matrix_regsetting[indexforchannel].iqk_done =
2624 true;
2625
2626 RT_TRACE(rtlpriv, COMP_SCAN | COMP_MLME, DBG_LOUD,
2627 ("\nIQK OK indexforchannel %d.\n", indexforchannel));
2628 }
2629}
2630
2631void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel)
2632{
2633 struct rtl_priv *rtlpriv = rtl_priv(hw);
2634 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2635 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2636 u8 indexforchannel;
2637
2638 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("channel %d\n", channel));
2639 /*------Do IQK for normal chip and test chip 5G band------- */
2640 indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel);
2641 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
2642 ("indexforchannel %d done %d\n", indexforchannel,
2643 rtlphy->iqk_matrix_regsetting[indexforchannel].iqk_done));
2644 if (0 && !rtlphy->iqk_matrix_regsetting[indexforchannel].iqk_done &&
2645 rtlphy->need_iqk) {
2646 /* Re Do IQK. */
2647 RT_TRACE(rtlpriv, COMP_SCAN | COMP_INIT, DBG_LOUD,
2648 ("Do IQK Matrix reg for channel:%d....\n", channel));
2649 rtl92d_phy_iq_calibrate(hw);
2650 } else {
2651 /* Just load the value. */
2652 /* 2G band just load once. */
2653 if (((!rtlhal->load_imrandiqk_setting_for2g) &&
2654 indexforchannel == 0) || indexforchannel > 0) {
2655 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
2656 ("Just Read IQK Matrix reg for channel:%d"
2657 "....\n", channel));
2658 if ((rtlphy->iqk_matrix_regsetting[indexforchannel].
2659 value[0] != NULL)
2660 /*&&(regea4 != 0) */)
2661 _rtl92d_phy_patha_fill_iqk_matrix(hw, true,
2662 rtlphy->iqk_matrix_regsetting[
2663 indexforchannel].value, 0,
2664 (rtlphy->iqk_matrix_regsetting[
2665 indexforchannel].value[0][2] == 0));
2666 if (IS_92D_SINGLEPHY(rtlhal->version)) {
2667 if ((rtlphy->iqk_matrix_regsetting[
2668 indexforchannel].value[0][4] != 0)
2669 /*&&(regec4 != 0) */)
2670 _rtl92d_phy_pathb_fill_iqk_matrix(hw,
2671 true,
2672 rtlphy->iqk_matrix_regsetting[
2673 indexforchannel].value, 0,
2674 (rtlphy->iqk_matrix_regsetting[
2675 indexforchannel].value[0][6]
2676 == 0));
2677 }
2678 }
2679 }
2680 rtlphy->need_iqk = false;
2681 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("<====\n"));
2682}
2683
2684static u32 _rtl92d_phy_get_abs(u32 val1, u32 val2)
2685{
2686 u32 ret;
2687
2688 if (val1 >= val2)
2689 ret = val1 - val2;
2690 else
2691 ret = val2 - val1;
2692 return ret;
2693}
2694
2695static bool _rtl92d_is_legal_5g_channel(struct ieee80211_hw *hw, u8 channel)
2696{
2697
2698 int i;
2699 u8 channel_5g[45] = {
2700 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
2701 60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
2702 114, 116, 118, 120, 122, 124, 126, 128, 130, 132,
2703 134, 136, 138, 140, 149, 151, 153, 155, 157, 159,
2704 161, 163, 165
2705 };
2706
2707 for (i = 0; i < sizeof(channel_5g); i++)
2708 if (channel == channel_5g[i])
2709 return true;
2710 return false;
2711}
2712
2713static void _rtl92d_phy_calc_curvindex(struct ieee80211_hw *hw,
2714 u32 *targetchnl, u32 * curvecount_val,
2715 bool is5g, u32 *curveindex)
2716{
2717 struct rtl_priv *rtlpriv = rtl_priv(hw);
2718 u32 smallest_abs_val = 0xffffffff, u4tmp;
2719 u8 i, j;
2720 u8 chnl_num = is5g ? TARGET_CHNL_NUM_5G : TARGET_CHNL_NUM_2G;
2721
2722 for (i = 0; i < chnl_num; i++) {
2723 if (is5g && !_rtl92d_is_legal_5g_channel(hw, i + 1))
2724 continue;
2725 curveindex[i] = 0;
2726 for (j = 0; j < (CV_CURVE_CNT * 2); j++) {
2727 u4tmp = _rtl92d_phy_get_abs(targetchnl[i],
2728 curvecount_val[j]);
2729
2730 if (u4tmp < smallest_abs_val) {
2731 curveindex[i] = j;
2732 smallest_abs_val = u4tmp;
2733 }
2734 }
2735 smallest_abs_val = 0xffffffff;
2736 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("curveindex[%d] = %x\n", i,
2737 curveindex[i]));
2738 }
2739}
2740
2741static void _rtl92d_phy_reload_lck_setting(struct ieee80211_hw *hw,
2742 u8 channel)
2743{
2744 struct rtl_priv *rtlpriv = rtl_priv(hw);
2745 u8 erfpath = rtlpriv->rtlhal.current_bandtype ==
2746 BAND_ON_5G ? RF90_PATH_A :
2747 IS_92D_SINGLEPHY(rtlpriv->rtlhal.version) ?
2748 RF90_PATH_B : RF90_PATH_A;
2749 u32 u4tmp = 0, u4regvalue = 0;
2750 bool bneed_powerdown_radio = false;
2751
2752 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("path %d\n", erfpath));
2753 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("band type = %d\n",
2754 rtlpriv->rtlhal.current_bandtype));
2755 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("channel = %d\n", channel));
2756 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {/* Path-A for 5G */
2757 u4tmp = curveindex_5g[channel-1];
2758 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2759 ("ver 1 set RF-A, 5G, 0x28 = 0x%ulx !!\n", u4tmp));
2760 if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY &&
2761 rtlpriv->rtlhal.interfaceindex == 1) {
2762 bneed_powerdown_radio =
2763 rtl92d_phy_enable_anotherphy(hw, false);
2764 rtlpriv->rtlhal.during_mac1init_radioa = true;
2765 /* asume no this case */
2766 if (bneed_powerdown_radio)
2767 _rtl92d_phy_enable_rf_env(hw, erfpath,
2768 &u4regvalue);
2769 }
2770 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp);
2771 if (bneed_powerdown_radio)
2772 _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue);
2773 if (rtlpriv->rtlhal.during_mac1init_radioa)
2774 rtl92d_phy_powerdown_anotherphy(hw, false);
2775 } else if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) {
2776 u4tmp = curveindex_2g[channel-1];
2777 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2778 ("ver 3 set RF-B, 2G, 0x28 = 0x%ulx !!\n", u4tmp));
2779 if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY &&
2780 rtlpriv->rtlhal.interfaceindex == 0) {
2781 bneed_powerdown_radio =
2782 rtl92d_phy_enable_anotherphy(hw, true);
2783 rtlpriv->rtlhal.during_mac0init_radiob = true;
2784 if (bneed_powerdown_radio)
2785 _rtl92d_phy_enable_rf_env(hw, erfpath,
2786 &u4regvalue);
2787 }
2788 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp);
2789 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2790 ("ver 3 set RF-B, 2G, 0x28 = 0x%ulx !!\n",
2791 rtl_get_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800)));
2792 if (bneed_powerdown_radio)
2793 _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue);
2794 if (rtlpriv->rtlhal.during_mac0init_radiob)
2795 rtl92d_phy_powerdown_anotherphy(hw, true);
2796 }
2797 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("<====\n"));
2798}
2799
2800static void _rtl92d_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t)
2801{
2802 struct rtl_priv *rtlpriv = rtl_priv(hw);
2803 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2804 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2805 u8 tmpreg, index, rf_mode[2];
2806 u8 path = is2t ? 2 : 1;
2807 u8 i;
2808 u32 u4tmp, offset;
2809 u32 curvecount_val[CV_CURVE_CNT * 2] = {0};
2810 u16 timeout = 800, timecount = 0;
2811
2812 /* Check continuous TX and Packet TX */
2813 tmpreg = rtl_read_byte(rtlpriv, 0xd03);
2814 /* if Deal with contisuous TX case, disable all continuous TX */
2815 /* if Deal with Packet TX case, block all queues */
2816 if ((tmpreg & 0x70) != 0)
2817 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
2818 else
2819 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
2820 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x0F);
2821 for (index = 0; index < path; index++) {
2822 /* 1. Read original RF mode */
2823 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1;
2824 rf_mode[index] = rtl_read_byte(rtlpriv, offset);
2825 /* 2. Set RF mode = standby mode */
2826 rtl_set_rfreg(hw, (enum radio_path)index, RF_AC,
2827 BRFREGOFFSETMASK, 0x010000);
2828 if (rtlpci->init_ready) {
2829 /* switch CV-curve control by LC-calibration */
2830 rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7,
2831 BIT(17), 0x0);
2832 /* 4. Set LC calibration begin */
2833 rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW,
2834 0x08000, 0x01);
2835 }
2836 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, RF_SYN_G6,
2837 BRFREGOFFSETMASK);
2838 while ((!(u4tmp & BIT(11))) && timecount <= timeout) {
2839 mdelay(50);
2840 timecount += 50;
2841 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index,
2842 RF_SYN_G6, BRFREGOFFSETMASK);
2843 }
2844 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2845 ("PHY_LCK finish delay for %d ms=2\n", timecount));
2846 u4tmp = rtl_get_rfreg(hw, index, RF_SYN_G4, BRFREGOFFSETMASK);
2847 if (index == 0 && rtlhal->interfaceindex == 0) {
2848 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2849 ("path-A / 5G LCK\n"));
2850 } else {
2851 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2852 ("path-B / 2.4G LCK\n"));
2853 }
2854 memset(&curvecount_val[0], 0, CV_CURVE_CNT * 2);
2855 /* Set LC calibration off */
2856 rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW,
2857 0x08000, 0x0);
2858 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("set RF 0x18[15] = 0\n"));
2859 /* save Curve-counting number */
2860 for (i = 0; i < CV_CURVE_CNT; i++) {
2861 u32 readval = 0, readval2 = 0;
2862 rtl_set_rfreg(hw, (enum radio_path)index, 0x3F,
2863 0x7f, i);
2864
2865 rtl_set_rfreg(hw, (enum radio_path)index, 0x4D,
2866 BRFREGOFFSETMASK, 0x0);
2867 readval = rtl_get_rfreg(hw, (enum radio_path)index,
2868 0x4F, BRFREGOFFSETMASK);
2869 curvecount_val[2 * i + 1] = (readval & 0xfffe0) >> 5;
2870 /* reg 0x4f [4:0] */
2871 /* reg 0x50 [19:10] */
2872 readval2 = rtl_get_rfreg(hw, (enum radio_path)index,
2873 0x50, 0xffc00);
2874 curvecount_val[2 * i] = (((readval & 0x1F) << 10) |
2875 readval2);
2876 }
2877 if (index == 0 && rtlhal->interfaceindex == 0)
2878 _rtl92d_phy_calc_curvindex(hw, targetchnl_5g,
2879 curvecount_val,
2880 true, curveindex_5g);
2881 else
2882 _rtl92d_phy_calc_curvindex(hw, targetchnl_2g,
2883 curvecount_val,
2884 false, curveindex_2g);
2885 /* switch CV-curve control mode */
2886 rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7,
2887 BIT(17), 0x1);
2888 }
2889
2890 /* Restore original situation */
2891 for (index = 0; index < path; index++) {
2892 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1;
2893 rtl_write_byte(rtlpriv, offset, 0x50);
2894 rtl_write_byte(rtlpriv, offset, rf_mode[index]);
2895 }
2896 if ((tmpreg & 0x70) != 0)
2897 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
2898 else /*Deal with Packet TX case */
2899 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2900 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x00);
2901 _rtl92d_phy_reload_lck_setting(hw, rtlpriv->phy.current_channel);
2902}
2903
2904static void _rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
2905{
2906 struct rtl_priv *rtlpriv = rtl_priv(hw);
2907
2908 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("cosa PHY_LCK ver=2\n"));
2909 _rtl92d_phy_lc_calibrate_sw(hw, is2t);
2910}
2911
2912void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw)
2913{
2914 struct rtl_priv *rtlpriv = rtl_priv(hw);
2915 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2916 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2917 u32 timeout = 2000, timecount = 0;
2918
2919 while (rtlpriv->mac80211.act_scanning && timecount < timeout) {
2920 udelay(50);
2921 timecount += 50;
2922 }
2923
2924 rtlphy->lck_inprogress = true;
2925 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2926 ("LCK:Start!!! currentband %x delay %d ms\n",
2927 rtlhal->current_bandtype, timecount));
2928 if (IS_92D_SINGLEPHY(rtlhal->version)) {
2929 _rtl92d_phy_lc_calibrate(hw, true);
2930 } else {
2931 /* For 1T1R */
2932 _rtl92d_phy_lc_calibrate(hw, false);
2933 }
2934 rtlphy->lck_inprogress = false;
2935 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("LCK:Finish!!!\n"));
2936}
2937
2938void rtl92d_phy_ap_calibrate(struct ieee80211_hw *hw, char delta)
2939{
2940 return;
2941}
2942
2943static bool _rtl92d_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
2944 u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid,
2945 u32 para1, u32 para2, u32 msdelay)
2946{
2947 struct swchnlcmd *pcmd;
2948
2949 if (cmdtable == NULL) {
2950 RT_ASSERT(false, ("cmdtable cannot be NULL.\n"));
2951 return false;
2952 }
2953 if (cmdtableidx >= cmdtablesz)
2954 return false;
2955
2956 pcmd = cmdtable + cmdtableidx;
2957 pcmd->cmdid = cmdid;
2958 pcmd->para1 = para1;
2959 pcmd->para2 = para2;
2960 pcmd->msdelay = msdelay;
2961 return true;
2962}
2963
2964void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw)
2965{
2966 struct rtl_priv *rtlpriv = rtl_priv(hw);
2967 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2968 u8 i;
2969
2970 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2971 ("settings regs %d default regs %d\n",
2972 (int)(sizeof(rtlphy->iqk_matrix_regsetting) /
2973 sizeof(struct iqk_matrix_regs)),
2974 IQK_MATRIX_REG_NUM));
2975 /* 0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc */
2976 for (i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) {
2977 rtlphy->iqk_matrix_regsetting[i].value[0][0] = 0x100;
2978 rtlphy->iqk_matrix_regsetting[i].value[0][2] = 0x100;
2979 rtlphy->iqk_matrix_regsetting[i].value[0][4] = 0x100;
2980 rtlphy->iqk_matrix_regsetting[i].value[0][6] = 0x100;
2981 rtlphy->iqk_matrix_regsetting[i].value[0][1] = 0x0;
2982 rtlphy->iqk_matrix_regsetting[i].value[0][3] = 0x0;
2983 rtlphy->iqk_matrix_regsetting[i].value[0][5] = 0x0;
2984 rtlphy->iqk_matrix_regsetting[i].value[0][7] = 0x0;
2985 rtlphy->iqk_matrix_regsetting[i].iqk_done = false;
2986 }
2987}
2988
2989static bool _rtl92d_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
2990 u8 channel, u8 *stage, u8 *step,
2991 u32 *delay)
2992{
2993 struct rtl_priv *rtlpriv = rtl_priv(hw);
2994 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2995 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
2996 u32 precommoncmdcnt;
2997 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
2998 u32 postcommoncmdcnt;
2999 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
3000 u32 rfdependcmdcnt;
3001 struct swchnlcmd *currentcmd = NULL;
3002 u8 rfpath;
3003 u8 num_total_rfpath = rtlphy->num_total_rfpath;
3004
3005 precommoncmdcnt = 0;
3006 _rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
3007 MAX_PRECMD_CNT,
3008 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
3009 _rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
3010 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
3011 postcommoncmdcnt = 0;
3012 _rtl92d_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
3013 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
3014 rfdependcmdcnt = 0;
3015 _rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
3016 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
3017 RF_CHNLBW, channel, 0);
3018 _rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
3019 MAX_RFDEPENDCMD_CNT, CMDID_END,
3020 0, 0, 0);
3021
3022 do {
3023 switch (*stage) {
3024 case 0:
3025 currentcmd = &precommoncmd[*step];
3026 break;
3027 case 1:
3028 currentcmd = &rfdependcmd[*step];
3029 break;
3030 case 2:
3031 currentcmd = &postcommoncmd[*step];
3032 break;
3033 }
3034 if (currentcmd->cmdid == CMDID_END) {
3035 if ((*stage) == 2) {
3036 return true;
3037 } else {
3038 (*stage)++;
3039 (*step) = 0;
3040 continue;
3041 }
3042 }
3043 switch (currentcmd->cmdid) {
3044 case CMDID_SET_TXPOWEROWER_LEVEL:
3045 rtl92d_phy_set_txpower_level(hw, channel);
3046 break;
3047 case CMDID_WRITEPORT_ULONG:
3048 rtl_write_dword(rtlpriv, currentcmd->para1,
3049 currentcmd->para2);
3050 break;
3051 case CMDID_WRITEPORT_USHORT:
3052 rtl_write_word(rtlpriv, currentcmd->para1,
3053 (u16)currentcmd->para2);
3054 break;
3055 case CMDID_WRITEPORT_UCHAR:
3056 rtl_write_byte(rtlpriv, currentcmd->para1,
3057 (u8)currentcmd->para2);
3058 break;
3059 case CMDID_RF_WRITEREG:
3060 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
3061 rtlphy->rfreg_chnlval[rfpath] =
3062 ((rtlphy->rfreg_chnlval[rfpath] &
3063 0xffffff00) | currentcmd->para2);
3064 if (rtlpriv->rtlhal.current_bandtype ==
3065 BAND_ON_5G) {
3066 if (currentcmd->para2 > 99)
3067 rtlphy->rfreg_chnlval[rfpath] =
3068 rtlphy->rfreg_chnlval
3069 [rfpath] | (BIT(18));
3070 else
3071 rtlphy->rfreg_chnlval[rfpath] =
3072 rtlphy->rfreg_chnlval
3073 [rfpath] & (~BIT(18));
3074 rtlphy->rfreg_chnlval[rfpath] |=
3075 (BIT(16) | BIT(8));
3076 } else {
3077 rtlphy->rfreg_chnlval[rfpath] &=
3078 ~(BIT(8) | BIT(16) | BIT(18));
3079 }
3080 rtl_set_rfreg(hw, (enum radio_path)rfpath,
3081 currentcmd->para1,
3082 BRFREGOFFSETMASK,
3083 rtlphy->rfreg_chnlval[rfpath]);
3084 _rtl92d_phy_reload_imr_setting(hw, channel,
3085 rfpath);
3086 }
3087 _rtl92d_phy_switch_rf_setting(hw, channel);
3088 /* do IQK when all parameters are ready */
3089 rtl92d_phy_reload_iqk_setting(hw, channel);
3090 break;
3091 default:
3092 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3093 ("switch case not process\n"));
3094 break;
3095 }
3096 break;
3097 } while (true);
3098 (*delay) = currentcmd->msdelay;
3099 (*step)++;
3100 return false;
3101}
3102
3103u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw)
3104{
3105 struct rtl_priv *rtlpriv = rtl_priv(hw);
3106 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3107 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3108 u32 delay;
3109 u32 timeout = 1000, timecount = 0;
3110 u8 channel = rtlphy->current_channel;
3111 u32 ret_value;
3112
3113 if (rtlphy->sw_chnl_inprogress)
3114 return 0;
3115 if (rtlphy->set_bwmode_inprogress)
3116 return 0;
3117
3118 if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
3119 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
3120 ("sw_chnl_inprogress false driver sleep or unload\n"));
3121 return 0;
3122 }
3123 while (rtlphy->lck_inprogress && timecount < timeout) {
3124 mdelay(50);
3125 timecount += 50;
3126 }
3127 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY &&
3128 rtlhal->bandset == BAND_ON_BOTH) {
3129 ret_value = rtl_get_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
3130 BMASKDWORD);
3131 if (rtlphy->current_channel > 14 && !(ret_value & BIT(0)))
3132 rtl92d_phy_switch_wirelessband(hw, BAND_ON_5G);
3133 else if (rtlphy->current_channel <= 14 && (ret_value & BIT(0)))
3134 rtl92d_phy_switch_wirelessband(hw, BAND_ON_2_4G);
3135 }
3136 switch (rtlhal->current_bandtype) {
3137 case BAND_ON_5G:
3138 /* Get first channel error when change between
3139 * 5G and 2.4G band. */
3140 if (channel <= 14)
3141 return 0;
3142 RT_ASSERT((channel > 14), ("5G but channel<=14"));
3143 break;
3144 case BAND_ON_2_4G:
3145 /* Get first channel error when change between
3146 * 5G and 2.4G band. */
3147 if (channel > 14)
3148 return 0;
3149 RT_ASSERT((channel <= 14), ("2G but channel>14"));
3150 break;
3151 default:
3152 RT_ASSERT(false,
3153 ("Invalid WirelessMode(%#x)!!\n",
3154 rtlpriv->mac80211.mode));
3155 break;
3156 }
3157 rtlphy->sw_chnl_inprogress = true;
3158 if (channel == 0)
3159 channel = 1;
3160 rtlphy->sw_chnl_stage = 0;
3161 rtlphy->sw_chnl_step = 0;
3162 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
3163 ("switch to channel%d\n", rtlphy->current_channel));
3164
3165 do {
3166 if (!rtlphy->sw_chnl_inprogress)
3167 break;
3168 if (!_rtl92d_phy_sw_chnl_step_by_step(hw,
3169 rtlphy->current_channel,
3170 &rtlphy->sw_chnl_stage, &rtlphy->sw_chnl_step, &delay)) {
3171 if (delay > 0)
3172 mdelay(delay);
3173 else
3174 continue;
3175 } else {
3176 rtlphy->sw_chnl_inprogress = false;
3177 }
3178 break;
3179 } while (true);
3180 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("<==\n"));
3181 rtlphy->sw_chnl_inprogress = false;
3182 return 1;
3183}
3184
3185static void rtl92d_phy_set_io(struct ieee80211_hw *hw)
3186{
3187 struct rtl_priv *rtlpriv = rtl_priv(hw);
3188 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3189
3190 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
3191 ("--->Cmd(%#x), set_io_inprogress(%d)\n",
3192 rtlphy->current_io_type, rtlphy->set_io_inprogress));
3193 switch (rtlphy->current_io_type) {
3194 case IO_CMD_RESUME_DM_BY_SCAN:
3195 de_digtable.cur_igvalue = rtlphy->initgain_backup.xaagccore1;
3196 rtl92d_dm_write_dig(hw);
3197 rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel);
3198 break;
3199 case IO_CMD_PAUSE_DM_BY_SCAN:
3200 rtlphy->initgain_backup.xaagccore1 = de_digtable.cur_igvalue;
3201 de_digtable.cur_igvalue = 0x17;
3202 rtl92d_dm_write_dig(hw);
3203 break;
3204 default:
3205 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3206 ("switch case not process\n"));
3207 break;
3208 }
3209 rtlphy->set_io_inprogress = false;
3210 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
3211 ("<---(%#x)\n", rtlphy->current_io_type));
3212}
3213
3214bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
3215{
3216 struct rtl_priv *rtlpriv = rtl_priv(hw);
3217 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3218 bool postprocessing = false;
3219
3220 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
3221 ("-->IO Cmd(%#x), set_io_inprogress(%d)\n",
3222 iotype, rtlphy->set_io_inprogress));
3223 do {
3224 switch (iotype) {
3225 case IO_CMD_RESUME_DM_BY_SCAN:
3226 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
3227 ("[IO CMD] Resume DM after scan.\n"));
3228 postprocessing = true;
3229 break;
3230 case IO_CMD_PAUSE_DM_BY_SCAN:
3231 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
3232 ("[IO CMD] Pause DM before scan.\n"));
3233 postprocessing = true;
3234 break;
3235 default:
3236 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3237 ("switch case not process\n"));
3238 break;
3239 }
3240 } while (false);
3241 if (postprocessing && !rtlphy->set_io_inprogress) {
3242 rtlphy->set_io_inprogress = true;
3243 rtlphy->current_io_type = iotype;
3244 } else {
3245 return false;
3246 }
3247 rtl92d_phy_set_io(hw);
3248 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, ("<--IO Type(%#x)\n", iotype));
3249 return true;
3250}
3251
3252static void _rtl92d_phy_set_rfon(struct ieee80211_hw *hw)
3253{
3254 struct rtl_priv *rtlpriv = rtl_priv(hw);
3255
3256 /* a. SYS_CLKR 0x08[11] = 1 restore MAC clock */
3257 /* b. SPS_CTRL 0x11[7:0] = 0x2b */
3258 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY)
3259 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
3260 /* c. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function */
3261 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3262 /* RF_ON_EXCEP(d~g): */
3263 /* d. APSD_CTRL 0x600[7:0] = 0x00 */
3264 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
3265 /* e. SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function again */
3266 /* f. SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function*/
3267 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3268 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3269 /* g. txpause 0x522[7:0] = 0x00 enable mac tx queue */
3270 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
3271}
3272
3273static void _rtl92d_phy_set_rfsleep(struct ieee80211_hw *hw)
3274{
3275 struct rtl_priv *rtlpriv = rtl_priv(hw);
3276 u32 u4btmp;
3277 u8 delay = 5;
3278
3279 /* a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */
3280 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
3281 /* b. RF path 0 offset 0x00 = 0x00 disable RF */
3282 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, BRFREGOFFSETMASK, 0x00);
3283 /* c. APSD_CTRL 0x600[7:0] = 0x40 */
3284 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
3285 /* d. APSD_CTRL 0x600[7:0] = 0x00
3286 * APSD_CTRL 0x600[7:0] = 0x00
3287 * RF path 0 offset 0x00 = 0x00
3288 * APSD_CTRL 0x600[7:0] = 0x40
3289 * */
3290 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, BRFREGOFFSETMASK);
3291 while (u4btmp != 0 && delay > 0) {
3292 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
3293 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, BRFREGOFFSETMASK, 0x00);
3294 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
3295 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, BRFREGOFFSETMASK);
3296 delay--;
3297 }
3298 if (delay == 0) {
3299 /* Jump out the LPS turn off sequence to RF_ON_EXCEP */
3300 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
3301
3302 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3303 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3304 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
3305 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
3306 ("Fail !!! Switch RF timeout.\n"));
3307 return;
3308 }
3309 /* e. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function */
3310 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3311 /* f. SPS_CTRL 0x11[7:0] = 0x22 */
3312 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY)
3313 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
3314 /* g. SYS_CLKR 0x08[11] = 0 gated MAC clock */
3315}
3316
3317bool rtl92d_phy_set_rf_power_state(struct ieee80211_hw *hw,
3318 enum rf_pwrstate rfpwr_state)
3319{
3320
3321 bool bresult = true;
3322 struct rtl_priv *rtlpriv = rtl_priv(hw);
3323 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3324 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3325 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3326 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
3327 u8 i, queue_id;
3328 struct rtl8192_tx_ring *ring = NULL;
3329
3330 if (rfpwr_state == ppsc->rfpwr_state)
3331 return false;
3332 switch (rfpwr_state) {
3333 case ERFON:
3334 if ((ppsc->rfpwr_state == ERFOFF) &&
3335 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
3336 bool rtstatus;
3337 u32 InitializeCount = 0;
3338 do {
3339 InitializeCount++;
3340 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3341 ("IPS Set eRf nic enable\n"));
3342 rtstatus = rtl_ps_enable_nic(hw);
3343 } while ((rtstatus != true) &&
3344 (InitializeCount < 10));
3345
3346 RT_CLEAR_PS_LEVEL(ppsc,
3347 RT_RF_OFF_LEVL_HALT_NIC);
3348 } else {
3349 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
3350 ("awake, sleeped:%d ms state_"
3351 "inap:%x\n",
3352 jiffies_to_msecs(jiffies -
3353 ppsc->last_sleep_jiffies),
3354 rtlpriv->psc.state_inap));
3355 ppsc->last_awake_jiffies = jiffies;
3356 _rtl92d_phy_set_rfon(hw);
3357 }
3358
3359 if (mac->link_state == MAC80211_LINKED)
3360 rtlpriv->cfg->ops->led_control(hw,
3361 LED_CTL_LINK);
3362 else
3363 rtlpriv->cfg->ops->led_control(hw,
3364 LED_CTL_NO_LINK);
3365 break;
3366 case ERFOFF:
3367 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
3368 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3369 ("IPS Set eRf nic disable\n"));
3370 rtl_ps_disable_nic(hw);
3371 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3372 } else {
3373 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
3374 rtlpriv->cfg->ops->led_control(hw,
3375 LED_CTL_NO_LINK);
3376 else
3377 rtlpriv->cfg->ops->led_control(hw,
3378 LED_CTL_POWER_OFF);
3379 }
3380 break;
3381 case ERFSLEEP:
3382 if (ppsc->rfpwr_state == ERFOFF)
3383 break;
3384
3385 for (queue_id = 0, i = 0;
3386 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
3387 ring = &pcipriv->dev.tx_ring[queue_id];
3388 if (skb_queue_len(&ring->queue) == 0 ||
3389 queue_id == BEACON_QUEUE) {
3390 queue_id++;
3391 continue;
3392 } else if (rtlpci->pdev->current_state != PCI_D0) {
3393 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
3394 ("eRf Off/Sleep: %d times TcbBusyQueu"
3395 "e[%d] !=0 but lower power state!\n",
3396 (i + 1), queue_id));
3397 break;
3398 } else {
3399 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
3400 ("eRf Off/Sleep: %d times TcbBusyQueu"
3401 "e[%d] =%d "
3402 "before doze!\n", (i + 1), queue_id,
3403 skb_queue_len(&ring->queue)));
3404 udelay(10);
3405 i++;
3406 }
3407
3408 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
3409 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
3410 ("\nERFOFF: %d times TcbBusyQueue[%d] "
3411 "= %d !\n",
3412 MAX_DOZE_WAITING_TIMES_9x, queue_id,
3413 skb_queue_len(&ring->queue)));
3414 break;
3415 }
3416 }
3417 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
3418 ("Set rfsleep awaked:%d ms\n",
3419 jiffies_to_msecs(jiffies - ppsc->last_awake_jiffies)));
3420 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, ("sleep awaked:%d ms "
3421 "state_inap:%x\n", jiffies_to_msecs(jiffies -
3422 ppsc->last_awake_jiffies), rtlpriv->psc.state_inap));
3423 ppsc->last_sleep_jiffies = jiffies;
3424 _rtl92d_phy_set_rfsleep(hw);
3425 break;
3426 default:
3427 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3428 ("switch case not process\n"));
3429 bresult = false;
3430 break;
3431 }
3432 if (bresult)
3433 ppsc->rfpwr_state = rfpwr_state;
3434 return bresult;
3435}
3436
3437void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw)
3438{
3439 struct rtl_priv *rtlpriv = rtl_priv(hw);
3440 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3441 u8 offset = REG_MAC_PHY_CTRL_NORMAL;
3442
3443 switch (rtlhal->macphymode) {
3444 case DUALMAC_DUALPHY:
3445 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3446 ("MacPhyMode: DUALMAC_DUALPHY\n"));
3447 rtl_write_byte(rtlpriv, offset, 0xF3);
3448 break;
3449 case SINGLEMAC_SINGLEPHY:
3450 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3451 ("MacPhyMode: SINGLEMAC_SINGLEPHY\n"));
3452 rtl_write_byte(rtlpriv, offset, 0xF4);
3453 break;
3454 case DUALMAC_SINGLEPHY:
3455 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3456 ("MacPhyMode: DUALMAC_SINGLEPHY\n"));
3457 rtl_write_byte(rtlpriv, offset, 0xF1);
3458 break;
3459 }
3460}
3461
3462void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw)
3463{
3464 struct rtl_priv *rtlpriv = rtl_priv(hw);
3465 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3466 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3467
3468 switch (rtlhal->macphymode) {
3469 case DUALMAC_SINGLEPHY:
3470 rtlphy->rf_type = RF_2T2R;
3471 rtlhal->version |= CHIP_92D_SINGLEPHY;
3472 rtlhal->bandset = BAND_ON_BOTH;
3473 rtlhal->current_bandtype = BAND_ON_2_4G;
3474 break;
3475
3476 case SINGLEMAC_SINGLEPHY:
3477 rtlphy->rf_type = RF_2T2R;
3478 rtlhal->version |= CHIP_92D_SINGLEPHY;
3479 rtlhal->bandset = BAND_ON_BOTH;
3480 rtlhal->current_bandtype = BAND_ON_2_4G;
3481 break;
3482
3483 case DUALMAC_DUALPHY:
3484 rtlphy->rf_type = RF_1T1R;
3485 rtlhal->version &= (~CHIP_92D_SINGLEPHY);
3486 /* Now we let MAC0 run on 5G band. */
3487 if (rtlhal->interfaceindex == 0) {
3488 rtlhal->bandset = BAND_ON_5G;
3489 rtlhal->current_bandtype = BAND_ON_5G;
3490 } else {
3491 rtlhal->bandset = BAND_ON_2_4G;
3492 rtlhal->current_bandtype = BAND_ON_2_4G;
3493 }
3494 break;
3495 default:
3496 break;
3497 }
3498}
3499
3500u8 rtl92d_get_chnlgroup_fromarray(u8 chnl)
3501{
3502 u8 group;
3503 u8 channel_info[59] = {
3504 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
3505 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56,
3506 58, 60, 62, 64, 100, 102, 104, 106, 108,
3507 110, 112, 114, 116, 118, 120, 122, 124,
3508 126, 128, 130, 132, 134, 136, 138, 140,
3509 149, 151, 153, 155, 157, 159, 161, 163,
3510 165
3511 };
3512
3513 if (channel_info[chnl] <= 3)
3514 group = 0;
3515 else if (channel_info[chnl] <= 9)
3516 group = 1;
3517 else if (channel_info[chnl] <= 14)
3518 group = 2;
3519 else if (channel_info[chnl] <= 44)
3520 group = 3;
3521 else if (channel_info[chnl] <= 54)
3522 group = 4;
3523 else if (channel_info[chnl] <= 64)
3524 group = 5;
3525 else if (channel_info[chnl] <= 112)
3526 group = 6;
3527 else if (channel_info[chnl] <= 126)
3528 group = 7;
3529 else if (channel_info[chnl] <= 140)
3530 group = 8;
3531 else if (channel_info[chnl] <= 153)
3532 group = 9;
3533 else if (channel_info[chnl] <= 159)
3534 group = 10;
3535 else
3536 group = 11;
3537 return group;
3538}
3539
3540void rtl92d_phy_set_poweron(struct ieee80211_hw *hw)
3541{
3542 struct rtl_priv *rtlpriv = rtl_priv(hw);
3543 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3544 unsigned long flags;
3545 u8 value8;
3546 u16 i;
3547 u32 mac_reg = (rtlhal->interfaceindex == 0 ? REG_MAC0 : REG_MAC1);
3548
3549 /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */
3550 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3551 value8 = rtl_read_byte(rtlpriv, mac_reg);
3552 value8 |= BIT(1);
3553 rtl_write_byte(rtlpriv, mac_reg, value8);
3554 } else {
3555 value8 = rtl_read_byte(rtlpriv, mac_reg);
3556 value8 &= (~BIT(1));
3557 rtl_write_byte(rtlpriv, mac_reg, value8);
3558 }
3559
3560 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) {
3561 value8 = rtl_read_byte(rtlpriv, REG_MAC0);
3562 rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON);
3563 } else {
3564 spin_lock_irqsave(&globalmutex_power, flags);
3565 if (rtlhal->interfaceindex == 0) {
3566 value8 = rtl_read_byte(rtlpriv, REG_MAC0);
3567 rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON);
3568 } else {
3569 value8 = rtl_read_byte(rtlpriv, REG_MAC1);
3570 rtl_write_byte(rtlpriv, REG_MAC1, value8 | MAC1_ON);
3571 }
3572 value8 = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
3573 spin_unlock_irqrestore(&globalmutex_power, flags);
3574 for (i = 0; i < 200; i++) {
3575 if ((value8 & BIT(7)) == 0) {
3576 break;
3577 } else {
3578 udelay(500);
3579 spin_lock_irqsave(&globalmutex_power, flags);
3580 value8 = rtl_read_byte(rtlpriv,
3581 REG_POWER_OFF_IN_PROCESS);
3582 spin_unlock_irqrestore(&globalmutex_power,
3583 flags);
3584 }
3585 }
3586 if (i == 200)
3587 RT_ASSERT(false, ("Another mac power off over time\n"));
3588 }
3589}
3590
3591void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw)
3592{
3593 struct rtl_priv *rtlpriv = rtl_priv(hw);
3594
3595 switch (rtlpriv->rtlhal.macphymode) {
3596 case DUALMAC_DUALPHY:
3597 rtl_write_byte(rtlpriv, REG_DMC, 0x0);
3598 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08);
3599 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff);
3600 break;
3601 case DUALMAC_SINGLEPHY:
3602 rtl_write_byte(rtlpriv, REG_DMC, 0xf8);
3603 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08);
3604 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff);
3605 break;
3606 case SINGLEMAC_SINGLEPHY:
3607 rtl_write_byte(rtlpriv, REG_DMC, 0x0);
3608 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x10);
3609 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF);
3610 break;
3611 default:
3612 break;
3613 }
3614}
3615
3616void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw)
3617{
3618 struct rtl_priv *rtlpriv = rtl_priv(hw);
3619 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3620 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3621 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3622 u8 rfpath, i;
3623
3624 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("==>\n"));
3625 /* r_select_5G for path_A/B 0 for 2.4G, 1 for 5G */
3626 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3627 /* r_select_5G for path_A/B,0x878 */
3628 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x0);
3629 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x0);
3630 if (rtlhal->macphymode != DUALMAC_DUALPHY) {
3631 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x0);
3632 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x0);
3633 }
3634 /* rssi_table_select:index 0 for 2.4G.1~3 for 5G,0xc78 */
3635 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x0);
3636 /* fc_area 0xd2c */
3637 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x0);
3638 /* 5G LAN ON */
3639 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa);
3640 /* TX BB gain shift*1,Just for testchip,0xc80,0xc88 */
3641 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, BMASKDWORD,
3642 0x40000100);
3643 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, BMASKDWORD,
3644 0x40000100);
3645 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
3646 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3647 BIT(10) | BIT(6) | BIT(5),
3648 ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) |
3649 (rtlefuse->eeprom_c9 & BIT(1)) |
3650 ((rtlefuse->eeprom_cc & BIT(1)) << 4));
3651 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
3652 BIT(10) | BIT(6) | BIT(5),
3653 ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) |
3654 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) |
3655 ((rtlefuse->eeprom_cc & BIT(0)) << 5));
3656 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0);
3657 } else {
3658 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3659 BIT(26) | BIT(22) | BIT(21) | BIT(10) |
3660 BIT(6) | BIT(5),
3661 ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) |
3662 (rtlefuse->eeprom_c9 & BIT(1)) |
3663 ((rtlefuse->eeprom_cc & BIT(1)) << 4) |
3664 ((rtlefuse->eeprom_c9 & BIT(7)) << 9) |
3665 ((rtlefuse->eeprom_c9 & BIT(5)) << 12) |
3666 ((rtlefuse->eeprom_cc & BIT(3)) << 18));
3667 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
3668 BIT(10) | BIT(6) | BIT(5),
3669 ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) |
3670 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) |
3671 ((rtlefuse->eeprom_cc & BIT(0)) << 5));
3672 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
3673 BIT(10) | BIT(6) | BIT(5),
3674 ((rtlefuse->eeprom_c9 & BIT(6)) >> 6) |
3675 ((rtlefuse->eeprom_c9 & BIT(4)) >> 3) |
3676 ((rtlefuse->eeprom_cc & BIT(2)) << 3));
3677 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
3678 BIT(31) | BIT(15), 0);
3679 }
3680 /* 1.5V_LDO */
3681 } else {
3682 /* r_select_5G for path_A/B */
3683 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x1);
3684 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x1);
3685 if (rtlhal->macphymode != DUALMAC_DUALPHY) {
3686 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x1);
3687 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x1);
3688 }
3689 /* rssi_table_select:index 0 for 2.4G.1~3 for 5G */
3690 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x1);
3691 /* fc_area */
3692 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x1);
3693 /* 5G LAN ON */
3694 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0);
3695 /* TX BB gain shift,Just for testchip,0xc80,0xc88 */
3696 if (rtlefuse->internal_pa_5g[0])
3697 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, BMASKDWORD,
3698 0x2d4000b5);
3699 else
3700 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, BMASKDWORD,
3701 0x20000080);
3702 if (rtlefuse->internal_pa_5g[1])
3703 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, BMASKDWORD,
3704 0x2d4000b5);
3705 else
3706 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, BMASKDWORD,
3707 0x20000080);
3708 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
3709 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3710 BIT(10) | BIT(6) | BIT(5),
3711 (rtlefuse->eeprom_cc & BIT(5)));
3712 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10),
3713 ((rtlefuse->eeprom_cc & BIT(4)) >> 4));
3714 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15),
3715 (rtlefuse->eeprom_cc & BIT(4)) >> 4);
3716 } else {
3717 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3718 BIT(26) | BIT(22) | BIT(21) | BIT(10) |
3719 BIT(6) | BIT(5),
3720 (rtlefuse->eeprom_cc & BIT(5)) |
3721 ((rtlefuse->eeprom_cc & BIT(7)) << 14));
3722 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10),
3723 ((rtlefuse->eeprom_cc & BIT(4)) >> 4));
3724 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10),
3725 ((rtlefuse->eeprom_cc & BIT(6)) >> 6));
3726 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
3727 BIT(31) | BIT(15),
3728 ((rtlefuse->eeprom_cc & BIT(4)) >> 4) |
3729 ((rtlefuse->eeprom_cc & BIT(6)) << 10));
3730 }
3731 }
3732 /* update IQK related settings */
3733 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, BMASKDWORD, 0x40000100);
3734 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, BMASKDWORD, 0x40000100);
3735 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000, 0x00);
3736 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30) | BIT(28) |
3737 BIT(26) | BIT(24), 0x00);
3738 rtl_set_bbreg(hw, ROFDM0_XDTxAFE, 0xF0000000, 0x00);
3739 rtl_set_bbreg(hw, 0xca0, 0xF0000000, 0x00);
3740 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, 0x00);
3741
3742 /* Update RF */
3743 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
3744 rfpath++) {
3745 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3746 /* MOD_AG for RF paht_A 0x18 BIT8,BIT16 */
3747 rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) | BIT(16) |
3748 BIT(18), 0);
3749 /* RF0x0b[16:14] =3b'111 */
3750 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B,
3751 0x1c000, 0x07);
3752 } else {
3753 /* MOD_AG for RF paht_A 0x18 BIT8,BIT16 */
3754 rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) |
3755 BIT(16) | BIT(18),
3756 (BIT(16) | BIT(8)) >> 8);
3757 }
3758 }
3759 /* Update for all band. */
3760 /* DMDP */
3761 if (rtlphy->rf_type == RF_1T1R) {
3762 /* Use antenna 0,0xc04,0xd04 */
3763 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKBYTE0, 0x11);
3764 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1);
3765
3766 /* enable ad/da clock1 for dual-phy reg0x888 */
3767 if (rtlhal->interfaceindex == 0) {
3768 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) |
3769 BIT(13), 0x3);
3770 } else {
3771 rtl92d_phy_enable_anotherphy(hw, false);
3772 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3773 ("MAC1 use DBI to update 0x888"));
3774 /* 0x888 */
3775 rtl92de_write_dword_dbi(hw, RFPGA0_ADDALLOCKEN,
3776 rtl92de_read_dword_dbi(hw,
3777 RFPGA0_ADDALLOCKEN,
3778 BIT(3)) | BIT(12) | BIT(13),
3779 BIT(3));
3780 rtl92d_phy_powerdown_anotherphy(hw, false);
3781 }
3782 } else {
3783 /* Single PHY */
3784 /* Use antenna 0 & 1,0xc04,0xd04 */
3785 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKBYTE0, 0x33);
3786 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3);
3787 /* disable ad/da clock1,0x888 */
3788 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0);
3789 }
3790 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
3791 rfpath++) {
3792 rtlphy->rfreg_chnlval[rfpath] = rtl_get_rfreg(hw, rfpath,
3793 RF_CHNLBW, BRFREGOFFSETMASK);
3794 rtlphy->reg_rf3c[rfpath] = rtl_get_rfreg(hw, rfpath, 0x3C,
3795 BRFREGOFFSETMASK);
3796 }
3797 for (i = 0; i < 2; i++)
3798 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, ("RF 0x18 = 0x%x\n",
3799 rtlphy->rfreg_chnlval[i]));
3800 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("<==\n"));
3801
3802}
3803
3804bool rtl92d_phy_check_poweroff(struct ieee80211_hw *hw)
3805{
3806 struct rtl_priv *rtlpriv = rtl_priv(hw);
3807 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3808 u8 u1btmp;
3809 unsigned long flags;
3810
3811 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) {
3812 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3813 rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON));
3814 return true;
3815 }
3816 spin_lock_irqsave(&globalmutex_power, flags);
3817 if (rtlhal->interfaceindex == 0) {
3818 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3819 rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON));
3820 u1btmp = rtl_read_byte(rtlpriv, REG_MAC1);
3821 u1btmp &= MAC1_ON;
3822 } else {
3823 u1btmp = rtl_read_byte(rtlpriv, REG_MAC1);
3824 rtl_write_byte(rtlpriv, REG_MAC1, u1btmp & (~MAC1_ON));
3825 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3826 u1btmp &= MAC0_ON;
3827 }
3828 if (u1btmp) {
3829 spin_unlock_irqrestore(&globalmutex_power, flags);
3830 return false;
3831 }
3832 u1btmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
3833 u1btmp |= BIT(7);
3834 rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1btmp);
3835 spin_unlock_irqrestore(&globalmutex_power, flags);
3836 return true;
3837}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/phy.h b/drivers/net/wireless/rtlwifi/rtl8192de/phy.h
new file mode 100644
index 000000000000..a52c824b41e3
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/phy.h
@@ -0,0 +1,178 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92D_PHY_H__
31#define __RTL92D_PHY_H__
32
33#define MAX_PRECMD_CNT 16
34#define MAX_RFDEPENDCMD_CNT 16
35#define MAX_POSTCMD_CNT 16
36
37#define MAX_DOZE_WAITING_TIMES_9x 64
38
39#define RT_CANNOT_IO(hw) false
40#define HIGHPOWER_RADIOA_ARRAYLEN 22
41
42#define IQK_ADDA_REG_NUM 16
43#define MAX_TOLERANCE 5
44#define IQK_DELAY_TIME 1
45
46#define APK_BB_REG_NUM 5
47#define APK_AFE_REG_NUM 16
48#define APK_CURVE_REG_NUM 4
49#define PATH_NUM 2
50
51#define LOOP_LIMIT 5
52#define MAX_STALL_TIME 50
53#define ANTENNA_DIVERSITY_VALUE 0x80
54#define MAX_TXPWR_IDX_NMODE_92S 63
55#define RESET_CNT_LIMIT 3
56
57#define IQK_ADDA_REG_NUM 16
58#define IQK_BB_REG_NUM 10
59#define IQK_BB_REG_NUM_test 6
60#define IQK_MAC_REG_NUM 4
61#define RX_INDEX_MAPPING_NUM 15
62
63#define IQK_DELAY_TIME 1
64
65#define CT_OFFSET_MAC_ADDR 0X16
66
67#define CT_OFFSET_CCK_TX_PWR_IDX 0x5A
68#define CT_OFFSET_HT401S_TX_PWR_IDX 0x60
69#define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF 0x66
70#define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x69
71#define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C
72
73#define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F
74#define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x72
75
76#define CT_OFFSET_CHANNEL_PLAH 0x75
77#define CT_OFFSET_THERMAL_METER 0x78
78#define CT_OFFSET_RF_OPTION 0x79
79#define CT_OFFSET_VERSION 0x7E
80#define CT_OFFSET_CUSTOMER_ID 0x7F
81
82enum swchnlcmd_id {
83 CMDID_END,
84 CMDID_SET_TXPOWEROWER_LEVEL,
85 CMDID_BBREGWRITE10,
86 CMDID_WRITEPORT_ULONG,
87 CMDID_WRITEPORT_USHORT,
88 CMDID_WRITEPORT_UCHAR,
89 CMDID_RF_WRITEREG,
90};
91
92struct swchnlcmd {
93 enum swchnlcmd_id cmdid;
94 u32 para1;
95 u32 para2;
96 u32 msdelay;
97};
98
99enum baseband_config_type {
100 BASEBAND_CONFIG_PHY_REG = 0,
101 BASEBAND_CONFIG_AGC_TAB = 1,
102};
103
104enum rf_content {
105 radioa_txt = 0,
106 radiob_txt = 1,
107 radioc_txt = 2,
108 radiod_txt = 3
109};
110
111static inline void rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
112 unsigned long *flag)
113{
114 struct rtl_priv *rtlpriv = rtl_priv(hw);
115
116 if (rtlpriv->rtlhal.interfaceindex == 1)
117 spin_lock_irqsave(&rtlpriv->locks.cck_and_rw_pagea_lock, *flag);
118}
119
120static inline void rtl92d_release_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
121 unsigned long *flag)
122{
123 struct rtl_priv *rtlpriv = rtl_priv(hw);
124
125 if (rtlpriv->rtlhal.interfaceindex == 1)
126 spin_unlock_irqrestore(&rtlpriv->locks.cck_and_rw_pagea_lock,
127 *flag);
128}
129
130extern u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw,
131 u32 regaddr, u32 bitmask);
132extern void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw,
133 u32 regaddr, u32 bitmask, u32 data);
134extern u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw,
135 enum radio_path rfpath, u32 regaddr,
136 u32 bitmask);
137extern void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw,
138 enum radio_path rfpath, u32 regaddr,
139 u32 bitmask, u32 data);
140extern bool rtl92d_phy_mac_config(struct ieee80211_hw *hw);
141extern bool rtl92d_phy_bb_config(struct ieee80211_hw *hw);
142extern bool rtl92d_phy_rf_config(struct ieee80211_hw *hw);
143extern bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw *hw,
144 enum radio_path rfpath);
145extern void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
146extern void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
147extern void rtl92d_phy_scan_operation_backup(struct ieee80211_hw *hw,
148 u8 operation);
149extern void rtl92d_phy_set_bw_mode(struct ieee80211_hw *hw,
150 enum nl80211_channel_type ch_type);
151extern u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw);
152bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
153 enum rf_content content,
154 enum radio_path rfpath);
155bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
156extern bool rtl92d_phy_set_rf_power_state(struct ieee80211_hw *hw,
157 enum rf_pwrstate rfpwr_state);
158
159void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw);
160void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw);
161u8 rtl92d_get_chnlgroup_fromarray(u8 chnl);
162void rtl92d_phy_set_poweron(struct ieee80211_hw *hw);
163void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw);
164bool rtl92d_phy_check_poweroff(struct ieee80211_hw *hw);
165void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw);
166void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw);
167void rtl92d_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
168void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw);
169void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw);
170void rtl92d_release_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
171 unsigned long *flag);
172void rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
173 unsigned long *flag);
174u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl);
175void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel);
176void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw);
177
178#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/reg.h b/drivers/net/wireless/rtlwifi/rtl8192de/reg.h
new file mode 100644
index 000000000000..131acc306fcc
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/reg.h
@@ -0,0 +1,1313 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92D_REG_H__
31#define __RTL92D_REG_H__
32
33/* ----------------------------------------------------- */
34/* 0x0000h ~ 0x00FFh System Configuration */
35/* ----------------------------------------------------- */
36#define REG_SYS_ISO_CTRL 0x0000
37#define REG_SYS_FUNC_EN 0x0002
38#define REG_APS_FSMCO 0x0004
39#define REG_SYS_CLKR 0x0008
40#define REG_9346CR 0x000A
41#define REG_EE_VPD 0x000C
42#define REG_AFE_MISC 0x0010
43#define REG_SPS0_CTRL 0x0011
44#define REG_POWER_OFF_IN_PROCESS 0x0017
45#define REG_SPS_OCP_CFG 0x0018
46#define REG_RSV_CTRL 0x001C
47#define REG_RF_CTRL 0x001F
48#define REG_LDOA15_CTRL 0x0020
49#define REG_LDOV12D_CTRL 0x0021
50#define REG_LDOHCI12_CTRL 0x0022
51#define REG_LPLDO_CTRL 0x0023
52#define REG_AFE_XTAL_CTRL 0x0024
53#define REG_AFE_PLL_CTRL 0x0028
54/* for 92d, DMDP,SMSP,DMSP contrl */
55#define REG_MAC_PHY_CTRL 0x002c
56#define REG_EFUSE_CTRL 0x0030
57#define REG_EFUSE_TEST 0x0034
58#define REG_PWR_DATA 0x0038
59#define REG_CAL_TIMER 0x003C
60#define REG_ACLK_MON 0x003E
61#define REG_GPIO_MUXCFG 0x0040
62#define REG_GPIO_IO_SEL 0x0042
63#define REG_MAC_PINMUX_CFG 0x0043
64#define REG_GPIO_PIN_CTRL 0x0044
65#define REG_GPIO_INTM 0x0048
66#define REG_LEDCFG0 0x004C
67#define REG_LEDCFG1 0x004D
68#define REG_LEDCFG2 0x004E
69#define REG_LEDCFG3 0x004F
70#define REG_FSIMR 0x0050
71#define REG_FSISR 0x0054
72
73#define REG_MCUFWDL 0x0080
74
75#define REG_HMEBOX_EXT_0 0x0088
76#define REG_HMEBOX_EXT_1 0x008A
77#define REG_HMEBOX_EXT_2 0x008C
78#define REG_HMEBOX_EXT_3 0x008E
79
80#define REG_BIST_SCAN 0x00D0
81#define REG_BIST_RPT 0x00D4
82#define REG_BIST_ROM_RPT 0x00D8
83#define REG_USB_SIE_INTF 0x00E0
84#define REG_PCIE_MIO_INTF 0x00E4
85#define REG_PCIE_MIO_INTD 0x00E8
86#define REG_HPON_FSM 0x00EC
87#define REG_SYS_CFG 0x00F0
88#define REG_MAC_PHY_CTRL_NORMAL 0x00f8
89
90#define REG_MAC0 0x0081
91#define REG_MAC1 0x0053
92#define FW_MAC0_READY 0x18
93#define FW_MAC1_READY 0x1A
94#define MAC0_ON BIT(7)
95#define MAC1_ON BIT(0)
96#define MAC0_READY BIT(0)
97#define MAC1_READY BIT(0)
98
99/* ----------------------------------------------------- */
100/* 0x0100h ~ 0x01FFh MACTOP General Configuration */
101/* ----------------------------------------------------- */
102#define REG_CR 0x0100
103#define REG_PBP 0x0104
104#define REG_TRXDMA_CTRL 0x010C
105#define REG_TRXFF_BNDY 0x0114
106#define REG_TRXFF_STATUS 0x0118
107#define REG_RXFF_PTR 0x011C
108#define REG_HIMR 0x0120
109#define REG_HISR 0x0124
110#define REG_HIMRE 0x0128
111#define REG_HISRE 0x012C
112#define REG_CPWM 0x012F
113#define REG_FWIMR 0x0130
114#define REG_FWISR 0x0134
115#define REG_PKTBUF_DBG_CTRL 0x0140
116#define REG_PKTBUF_DBG_DATA_L 0x0144
117#define REG_PKTBUF_DBG_DATA_H 0x0148
118
119#define REG_TC0_CTRL 0x0150
120#define REG_TC1_CTRL 0x0154
121#define REG_TC2_CTRL 0x0158
122#define REG_TC3_CTRL 0x015C
123#define REG_TC4_CTRL 0x0160
124#define REG_TCUNIT_BASE 0x0164
125#define REG_MBIST_START 0x0174
126#define REG_MBIST_DONE 0x0178
127#define REG_MBIST_FAIL 0x017C
128#define REG_C2HEVT_MSG_NORMAL 0x01A0
129#define REG_C2HEVT_MSG_TEST 0x01B8
130#define REG_C2HEVT_CLEAR 0x01BF
131#define REG_MCUTST_1 0x01c0
132#define REG_FMETHR 0x01C8
133#define REG_HMETFR 0x01CC
134#define REG_HMEBOX_0 0x01D0
135#define REG_HMEBOX_1 0x01D4
136#define REG_HMEBOX_2 0x01D8
137#define REG_HMEBOX_3 0x01DC
138
139#define REG_LLT_INIT 0x01E0
140#define REG_BB_ACCEESS_CTRL 0x01E8
141#define REG_BB_ACCESS_DATA 0x01EC
142
143
144/* ----------------------------------------------------- */
145/* 0x0200h ~ 0x027Fh TXDMA Configuration */
146/* ----------------------------------------------------- */
147#define REG_RQPN 0x0200
148#define REG_FIFOPAGE 0x0204
149#define REG_TDECTRL 0x0208
150#define REG_TXDMA_OFFSET_CHK 0x020C
151#define REG_TXDMA_STATUS 0x0210
152#define REG_RQPN_NPQ 0x0214
153
154/* ----------------------------------------------------- */
155/* 0x0280h ~ 0x02FFh RXDMA Configuration */
156/* ----------------------------------------------------- */
157#define REG_RXDMA_AGG_PG_TH 0x0280
158#define REG_RXPKT_NUM 0x0284
159#define REG_RXDMA_STATUS 0x0288
160
161/* ----------------------------------------------------- */
162/* 0x0300h ~ 0x03FFh PCIe */
163/* ----------------------------------------------------- */
164#define REG_PCIE_CTRL_REG 0x0300
165#define REG_INT_MIG 0x0304
166#define REG_BCNQ_DESA 0x0308
167#define REG_HQ_DESA 0x0310
168#define REG_MGQ_DESA 0x0318
169#define REG_VOQ_DESA 0x0320
170#define REG_VIQ_DESA 0x0328
171#define REG_BEQ_DESA 0x0330
172#define REG_BKQ_DESA 0x0338
173#define REG_RX_DESA 0x0340
174#define REG_DBI 0x0348
175#define REG_DBI_WDATA 0x0348
176#define REG_DBI_RDATA 0x034C
177#define REG_DBI_CTRL 0x0350
178#define REG_DBI_FLAG 0x0352
179#define REG_MDIO 0x0354
180#define REG_DBG_SEL 0x0360
181#define REG_PCIE_HRPWM 0x0361
182#define REG_PCIE_HCPWM 0x0363
183#define REG_UART_CTRL 0x0364
184#define REG_UART_TX_DESA 0x0370
185#define REG_UART_RX_DESA 0x0378
186
187/* ----------------------------------------------------- */
188/* 0x0400h ~ 0x047Fh Protocol Configuration */
189/* ----------------------------------------------------- */
190#define REG_VOQ_INFORMATION 0x0400
191#define REG_VIQ_INFORMATION 0x0404
192#define REG_BEQ_INFORMATION 0x0408
193#define REG_BKQ_INFORMATION 0x040C
194#define REG_MGQ_INFORMATION 0x0410
195#define REG_HGQ_INFORMATION 0x0414
196#define REG_BCNQ_INFORMATION 0x0418
197
198
199#define REG_CPU_MGQ_INFORMATION 0x041C
200#define REG_FWHW_TXQ_CTRL 0x0420
201#define REG_HWSEQ_CTRL 0x0423
202#define REG_TXPKTBUF_BCNQ_BDNY 0x0424
203#define REG_TXPKTBUF_MGQ_BDNY 0x0425
204#define REG_MULTI_BCNQ_EN 0x0426
205#define REG_MULTI_BCNQ_OFFSET 0x0427
206#define REG_SPEC_SIFS 0x0428
207#define REG_RL 0x042A
208#define REG_DARFRC 0x0430
209#define REG_RARFRC 0x0438
210#define REG_RRSR 0x0440
211#define REG_ARFR0 0x0444
212#define REG_ARFR1 0x0448
213#define REG_ARFR2 0x044C
214#define REG_ARFR3 0x0450
215#define REG_AGGLEN_LMT 0x0458
216#define REG_AMPDU_MIN_SPACE 0x045C
217#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D
218#define REG_FAST_EDCA_CTRL 0x0460
219#define REG_RD_RESP_PKT_TH 0x0463
220#define REG_INIRTS_RATE_SEL 0x0480
221#define REG_INIDATA_RATE_SEL 0x0484
222#define REG_POWER_STATUS 0x04A4
223#define REG_POWER_STAGE1 0x04B4
224#define REG_POWER_STAGE2 0x04B8
225#define REG_PKT_LIFE_TIME 0x04C0
226#define REG_STBC_SETTING 0x04C4
227#define REG_PROT_MODE_CTRL 0x04C8
228#define REG_MAX_AGGR_NUM 0x04CA
229#define REG_RTS_MAX_AGGR_NUM 0x04CB
230#define REG_BAR_MODE_CTRL 0x04CC
231#define REG_RA_TRY_RATE_AGG_LMT 0x04CF
232#define REG_EARLY_MODE_CONTROL 0x4D0
233#define REG_NQOS_SEQ 0x04DC
234#define REG_QOS_SEQ 0x04DE
235#define REG_NEED_CPU_HANDLE 0x04E0
236#define REG_PKT_LOSE_RPT 0x04E1
237#define REG_PTCL_ERR_STATUS 0x04E2
238#define REG_DUMMY 0x04FC
239
240/* ----------------------------------------------------- */
241/* 0x0500h ~ 0x05FFh EDCA Configuration */
242/* ----------------------------------------------------- */
243#define REG_EDCA_VO_PARAM 0x0500
244#define REG_EDCA_VI_PARAM 0x0504
245#define REG_EDCA_BE_PARAM 0x0508
246#define REG_EDCA_BK_PARAM 0x050C
247#define REG_BCNTCFG 0x0510
248#define REG_PIFS 0x0512
249#define REG_RDG_PIFS 0x0513
250#define REG_SIFS_CTX 0x0514
251#define REG_SIFS_TRX 0x0516
252#define REG_AGGR_BREAK_TIME 0x051A
253#define REG_SLOT 0x051B
254#define REG_TX_PTCL_CTRL 0x0520
255#define REG_TXPAUSE 0x0522
256#define REG_DIS_TXREQ_CLR 0x0523
257#define REG_RD_CTRL 0x0524
258#define REG_TBTT_PROHIBIT 0x0540
259#define REG_RD_NAV_NXT 0x0544
260#define REG_NAV_PROT_LEN 0x0546
261#define REG_BCN_CTRL 0x0550
262#define REG_USTIME_TSF 0x0551
263#define REG_MBID_NUM 0x0552
264#define REG_DUAL_TSF_RST 0x0553
265#define REG_BCN_INTERVAL 0x0554
266#define REG_MBSSID_BCN_SPACE 0x0554
267#define REG_DRVERLYINT 0x0558
268#define REG_BCNDMATIM 0x0559
269#define REG_ATIMWND 0x055A
270#define REG_BCN_MAX_ERR 0x055D
271#define REG_RXTSF_OFFSET_CCK 0x055E
272#define REG_RXTSF_OFFSET_OFDM 0x055F
273#define REG_TSFTR 0x0560
274#define REG_INIT_TSFTR 0x0564
275#define REG_PSTIMER 0x0580
276#define REG_TIMER0 0x0584
277#define REG_TIMER1 0x0588
278#define REG_ACMHWCTRL 0x05C0
279#define REG_ACMRSTCTRL 0x05C1
280#define REG_ACMAVG 0x05C2
281#define REG_VO_ADMTIME 0x05C4
282#define REG_VI_ADMTIME 0x05C6
283#define REG_BE_ADMTIME 0x05C8
284#define REG_EDCA_RANDOM_GEN 0x05CC
285#define REG_SCH_TXCMD 0x05D0
286
287/* Dual MAC Co-Existence Register */
288#define REG_DMC 0x05F0
289
290/* ----------------------------------------------------- */
291/* 0x0600h ~ 0x07FFh WMAC Configuration */
292/* ----------------------------------------------------- */
293#define REG_APSD_CTRL 0x0600
294#define REG_BWOPMODE 0x0603
295#define REG_TCR 0x0604
296#define REG_RCR 0x0608
297#define REG_RX_PKT_LIMIT 0x060C
298#define REG_RX_DLK_TIME 0x060D
299#define REG_RX_DRVINFO_SZ 0x060F
300
301#define REG_MACID 0x0610
302#define REG_BSSID 0x0618
303#define REG_MAR 0x0620
304#define REG_MBIDCAMCFG 0x0628
305
306#define REG_USTIME_EDCA 0x0638
307#define REG_MAC_SPEC_SIFS 0x063A
308#define REG_RESP_SIFS_CCK 0x063C
309#define REG_RESP_SIFS_OFDM 0x063E
310#define REG_ACKTO 0x0640
311#define REG_CTS2TO 0x0641
312#define REG_EIFS 0x0642
313
314
315/* WMA, BA, CCX */
316#define REG_NAV_CTRL 0x0650
317#define REG_BACAMCMD 0x0654
318#define REG_BACAMCONTENT 0x0658
319#define REG_LBDLY 0x0660
320#define REG_FWDLY 0x0661
321#define REG_RXERR_RPT 0x0664
322#define REG_WMAC_TRXPTCL_CTL 0x0668
323
324
325/* Security */
326#define REG_CAMCMD 0x0670
327#define REG_CAMWRITE 0x0674
328#define REG_CAMREAD 0x0678
329#define REG_CAMDBG 0x067C
330#define REG_SECCFG 0x0680
331
332/* Power */
333#define REG_WOW_CTRL 0x0690
334#define REG_PSSTATUS 0x0691
335#define REG_PS_RX_INFO 0x0692
336#define REG_LPNAV_CTRL 0x0694
337#define REG_WKFMCAM_CMD 0x0698
338#define REG_WKFMCAM_RWD 0x069C
339#define REG_RXFLTMAP0 0x06A0
340#define REG_RXFLTMAP1 0x06A2
341#define REG_RXFLTMAP2 0x06A4
342#define REG_BCN_PSR_RPT 0x06A8
343#define REG_CALB32K_CTRL 0x06AC
344#define REG_PKT_MON_CTRL 0x06B4
345#define REG_BT_COEX_TABLE 0x06C0
346#define REG_WMAC_RESP_TXINFO 0x06D8
347
348
349/* ----------------------------------------------------- */
350/* Redifine 8192C register definition for compatibility */
351/* ----------------------------------------------------- */
352#define CR9346 REG_9346CR
353#define MSR (REG_CR + 2)
354#define ISR REG_HISR
355#define TSFR REG_TSFTR
356
357#define MACIDR0 REG_MACID
358#define MACIDR4 (REG_MACID + 4)
359
360#define PBP REG_PBP
361
362#define IDR0 MACIDR0
363#define IDR4 MACIDR4
364
365/* ----------------------------------------------------- */
366/* 8192C (MSR) Media Status Register(Offset 0x4C, 8 bits)*/
367/* ----------------------------------------------------- */
368#define MSR_NOLINK 0x00
369#define MSR_ADHOC 0x01
370#define MSR_INFRA 0x02
371#define MSR_AP 0x03
372
373/* 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) */
374/* ----------------------------------------------------- */
375/* 8192C Response Rate Set Register(offset 0x181, 24bits)*/
376/* ----------------------------------------------------- */
377#define RRSR_RSC_OFFSET 21
378#define RRSR_SHORT_OFFSET 23
379#define RRSR_RSC_BW_40M 0x600000
380#define RRSR_RSC_UPSUBCHNL 0x400000
381#define RRSR_RSC_LOWSUBCHNL 0x200000
382#define RRSR_SHORT 0x800000
383#define RRSR_1M BIT0
384#define RRSR_2M BIT1
385#define RRSR_5_5M BIT2
386#define RRSR_11M BIT3
387#define RRSR_6M BIT4
388#define RRSR_9M BIT5
389#define RRSR_12M BIT6
390#define RRSR_18M BIT7
391#define RRSR_24M BIT8
392#define RRSR_36M BIT9
393#define RRSR_48M BIT10
394#define RRSR_54M BIT11
395#define RRSR_MCS0 BIT12
396#define RRSR_MCS1 BIT13
397#define RRSR_MCS2 BIT14
398#define RRSR_MCS3 BIT15
399#define RRSR_MCS4 BIT16
400#define RRSR_MCS5 BIT17
401#define RRSR_MCS6 BIT18
402#define RRSR_MCS7 BIT19
403#define BRSR_ACKSHORTPMB BIT23
404
405/* ----------------------------------------------------- */
406/* 8192C Rate Definition */
407/* ----------------------------------------------------- */
408/* CCK */
409#define RATR_1M 0x00000001
410#define RATR_2M 0x00000002
411#define RATR_55M 0x00000004
412#define RATR_11M 0x00000008
413/* OFDM */
414#define RATR_6M 0x00000010
415#define RATR_9M 0x00000020
416#define RATR_12M 0x00000040
417#define RATR_18M 0x00000080
418#define RATR_24M 0x00000100
419#define RATR_36M 0x00000200
420#define RATR_48M 0x00000400
421#define RATR_54M 0x00000800
422/* MCS 1 Spatial Stream */
423#define RATR_MCS0 0x00001000
424#define RATR_MCS1 0x00002000
425#define RATR_MCS2 0x00004000
426#define RATR_MCS3 0x00008000
427#define RATR_MCS4 0x00010000
428#define RATR_MCS5 0x00020000
429#define RATR_MCS6 0x00040000
430#define RATR_MCS7 0x00080000
431/* MCS 2 Spatial Stream */
432#define RATR_MCS8 0x00100000
433#define RATR_MCS9 0x00200000
434#define RATR_MCS10 0x00400000
435#define RATR_MCS11 0x00800000
436#define RATR_MCS12 0x01000000
437#define RATR_MCS13 0x02000000
438#define RATR_MCS14 0x04000000
439#define RATR_MCS15 0x08000000
440
441/* CCK */
442#define RATE_1M BIT(0)
443#define RATE_2M BIT(1)
444#define RATE_5_5M BIT(2)
445#define RATE_11M BIT(3)
446/* OFDM */
447#define RATE_6M BIT(4)
448#define RATE_9M BIT(5)
449#define RATE_12M BIT(6)
450#define RATE_18M BIT(7)
451#define RATE_24M BIT(8)
452#define RATE_36M BIT(9)
453#define RATE_48M BIT(10)
454#define RATE_54M BIT(11)
455/* MCS 1 Spatial Stream */
456#define RATE_MCS0 BIT(12)
457#define RATE_MCS1 BIT(13)
458#define RATE_MCS2 BIT(14)
459#define RATE_MCS3 BIT(15)
460#define RATE_MCS4 BIT(16)
461#define RATE_MCS5 BIT(17)
462#define RATE_MCS6 BIT(18)
463#define RATE_MCS7 BIT(19)
464/* MCS 2 Spatial Stream */
465#define RATE_MCS8 BIT(20)
466#define RATE_MCS9 BIT(21)
467#define RATE_MCS10 BIT(22)
468#define RATE_MCS11 BIT(23)
469#define RATE_MCS12 BIT(24)
470#define RATE_MCS13 BIT(25)
471#define RATE_MCS14 BIT(26)
472#define RATE_MCS15 BIT(27)
473
474/* ALL CCK Rate */
475#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | \
476 RATR_11M)
477#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | \
478 RATR_18M | RATR_24M | \
479 RATR_36M | RATR_48M | RATR_54M)
480#define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 | \
481 RATR_MCS3 | RATR_MCS4 | RATR_MCS5 | \
482 RATR_MCS6 | RATR_MCS7)
483#define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 | \
484 RATR_MCS11 | RATR_MCS12 | RATR_MCS13 | \
485 RATR_MCS14 | RATR_MCS15)
486
487/* ----------------------------------------------------- */
488/* 8192C BW_OPMODE bits (Offset 0x203, 8bit) */
489/* ----------------------------------------------------- */
490#define BW_OPMODE_20MHZ BIT(2)
491#define BW_OPMODE_5G BIT(1)
492#define BW_OPMODE_11J BIT(0)
493
494
495/* ----------------------------------------------------- */
496/* 8192C CAM Config Setting (offset 0x250, 1 byte) */
497/* ----------------------------------------------------- */
498#define CAM_VALID BIT(15)
499#define CAM_NOTVALID 0x0000
500#define CAM_USEDK BIT(5)
501
502#define CAM_NONE 0x0
503#define CAM_WEP40 0x01
504#define CAM_TKIP 0x02
505#define CAM_AES 0x04
506#define CAM_WEP104 0x05
507#define CAM_SMS4 0x6
508
509
510#define TOTAL_CAM_ENTRY 32
511#define HALF_CAM_ENTRY 16
512
513#define CAM_WRITE BIT(16)
514#define CAM_READ 0x00000000
515#define CAM_POLLINIG BIT(31)
516
517/* 10. Power Save Control Registers (Offset: 0x0260 - 0x02DF) */
518#define WOW_PMEN BIT0 /* Power management Enable. */
519#define WOW_WOMEN BIT1 /* WoW function on or off. */
520#define WOW_MAGIC BIT2 /* Magic packet */
521#define WOW_UWF BIT3 /* Unicast Wakeup frame. */
522
523/* 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F) */
524/* ----------------------------------------------------- */
525/* 8190 IMR/ISR bits (offset 0xfd, 8bits) */
526/* ----------------------------------------------------- */
527#define IMR8190_DISABLED 0x0
528#define IMR_BCNDMAINT6 BIT(31)
529#define IMR_BCNDMAINT5 BIT(30)
530#define IMR_BCNDMAINT4 BIT(29)
531#define IMR_BCNDMAINT3 BIT(28)
532#define IMR_BCNDMAINT2 BIT(27)
533#define IMR_BCNDMAINT1 BIT(26)
534#define IMR_BCNDOK8 BIT(25)
535#define IMR_BCNDOK7 BIT(24)
536#define IMR_BCNDOK6 BIT(23)
537#define IMR_BCNDOK5 BIT(22)
538#define IMR_BCNDOK4 BIT(21)
539#define IMR_BCNDOK3 BIT(20)
540#define IMR_BCNDOK2 BIT(19)
541#define IMR_BCNDOK1 BIT(18)
542#define IMR_TIMEOUT2 BIT(17)
543#define IMR_TIMEOUT1 BIT(16)
544#define IMR_TXFOVW BIT(15)
545#define IMR_PSTIMEOUT BIT(14)
546#define IMR_BcnInt BIT(13)
547#define IMR_RXFOVW BIT(12)
548#define IMR_RDU BIT(11)
549#define IMR_ATIMEND BIT(10)
550#define IMR_BDOK BIT(9)
551#define IMR_HIGHDOK BIT(8)
552#define IMR_TBDOK BIT(7)
553#define IMR_MGNTDOK BIT(6)
554#define IMR_TBDER BIT(5)
555#define IMR_BKDOK BIT(4)
556#define IMR_BEDOK BIT(3)
557#define IMR_VIDOK BIT(2)
558#define IMR_VODOK BIT(1)
559#define IMR_ROK BIT(0)
560
561#define IMR_TXERR BIT(11)
562#define IMR_RXERR BIT(10)
563#define IMR_C2HCMD BIT(9)
564#define IMR_CPWM BIT(8)
565#define IMR_OCPINT BIT(1)
566#define IMR_WLANOFF BIT(0)
567
568/* ----------------------------------------------------- */
569/* 8192C EFUSE */
570/* ----------------------------------------------------- */
571#define HWSET_MAX_SIZE 256
572#define EFUSE_MAX_SECTION 32
573#define EFUSE_REAL_CONTENT_LEN 512
574
575/* ----------------------------------------------------- */
576/* 8192C EEPROM/EFUSE share register definition. */
577/* ----------------------------------------------------- */
578#define EEPROM_DEFAULT_TSSI 0x0
579#define EEPROM_DEFAULT_CRYSTALCAP 0x0
580#define EEPROM_DEFAULT_THERMALMETER 0x12
581
582#define EEPROM_DEFAULT_TXPOWERLEVEL_2G 0x2C
583#define EEPROM_DEFAULT_TXPOWERLEVEL_5G 0x22
584
585#define EEPROM_DEFAULT_HT40_2SDIFF 0x0
586/* HT20<->40 default Tx Power Index Difference */
587#define EEPROM_DEFAULT_HT20_DIFF 2
588/* OFDM Tx Power index diff */
589#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x4
590#define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0
591#define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0
592
593#define EEPROM_CHANNEL_PLAN_FCC 0x0
594#define EEPROM_CHANNEL_PLAN_IC 0x1
595#define EEPROM_CHANNEL_PLAN_ETSI 0x2
596#define EEPROM_CHANNEL_PLAN_SPAIN 0x3
597#define EEPROM_CHANNEL_PLAN_FRANCE 0x4
598#define EEPROM_CHANNEL_PLAN_MKK 0x5
599#define EEPROM_CHANNEL_PLAN_MKK1 0x6
600#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
601#define EEPROM_CHANNEL_PLAN_TELEC 0x8
602#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9
603#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
604#define EEPROM_CHANNEL_PLAN_NCC 0xB
605#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
606
607#define EEPROM_CID_DEFAULT 0x0
608#define EEPROM_CID_TOSHIBA 0x4
609#define EEPROM_CID_CCX 0x10
610#define EEPROM_CID_QMI 0x0D
611#define EEPROM_CID_WHQL 0xFE
612
613
614#define RTL8192_EEPROM_ID 0x8129
615#define EEPROM_WAPI_SUPPORT 0x78
616
617
618#define RTL8190_EEPROM_ID 0x8129 /* 0-1 */
619#define EEPROM_HPON 0x02 /* LDO settings.2-5 */
620#define EEPROM_CLK 0x06 /* Clock settings.6-7 */
621#define EEPROM_MAC_FUNCTION 0x08 /* SE Test mode.8 */
622
623#define EEPROM_VID 0x28 /* SE Vendor ID.A-B */
624#define EEPROM_DID 0x2A /* SE Device ID. C-D */
625#define EEPROM_SVID 0x2C /* SE Vendor ID.E-F */
626#define EEPROM_SMID 0x2E /* SE PCI Subsystem ID. 10-11 */
627
628#define EEPROM_MAC_ADDR 0x16 /* SEMAC Address. 12-17 */
629#define EEPROM_MAC_ADDR_MAC0_92D 0x55
630#define EEPROM_MAC_ADDR_MAC1_92D 0x5B
631
632/* 2.4G band Tx power index setting */
633#define EEPROM_CCK_TX_PWR_INX_2G 0x61
634#define EEPROM_HT40_1S_TX_PWR_INX_2G 0x67
635#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G 0x6D
636#define EEPROM_HT20_TX_PWR_INX_DIFF_2G 0x70
637#define EEPROM_OFDM_TX_PWR_INX_DIFF_2G 0x73
638#define EEPROM_HT40_MAX_PWR_OFFSET_2G 0x76
639#define EEPROM_HT20_MAX_PWR_OFFSET_2G 0x79
640
641/*5GL channel 32-64 */
642#define EEPROM_HT40_1S_TX_PWR_INX_5GL 0x7C
643#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GL 0x82
644#define EEPROM_HT20_TX_PWR_INX_DIFF_5GL 0x85
645#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GL 0x88
646#define EEPROM_HT40_MAX_PWR_OFFSET_5GL 0x8B
647#define EEPROM_HT20_MAX_PWR_OFFSET_5GL 0x8E
648
649/* 5GM channel 100-140 */
650#define EEPROM_HT40_1S_TX_PWR_INX_5GM 0x91
651#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GM 0x97
652#define EEPROM_HT20_TX_PWR_INX_DIFF_5GM 0x9A
653#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GM 0x9D
654#define EEPROM_HT40_MAX_PWR_OFFSET_5GM 0xA0
655#define EEPROM_HT20_MAX_PWR_OFFSET_5GM 0xA3
656
657/* 5GH channel 149-165 */
658#define EEPROM_HT40_1S_TX_PWR_INX_5GH 0xA6
659#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GH 0xAC
660#define EEPROM_HT20_TX_PWR_INX_DIFF_5GH 0xAF
661#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GH 0xB2
662#define EEPROM_HT40_MAX_PWR_OFFSET_5GH 0xB5
663#define EEPROM_HT20_MAX_PWR_OFFSET_5GH 0xB8
664
665/* Map of supported channels. */
666#define EEPROM_CHANNEL_PLAN 0xBB
667#define EEPROM_IQK_DELTA 0xBC
668#define EEPROM_LCK_DELTA 0xBC
669#define EEPROM_XTAL_K 0xBD /* [7:5] */
670#define EEPROM_TSSI_A_5G 0xBE
671#define EEPROM_TSSI_B_5G 0xBF
672#define EEPROM_TSSI_AB_5G 0xC0
673#define EEPROM_THERMAL_METER 0xC3 /* [4:0] */
674#define EEPROM_RF_OPT1 0xC4
675#define EEPROM_RF_OPT2 0xC5
676#define EEPROM_RF_OPT3 0xC6
677#define EEPROM_RF_OPT4 0xC7
678#define EEPROM_RF_OPT5 0xC8
679#define EEPROM_RF_OPT6 0xC9
680#define EEPROM_VERSION 0xCA
681#define EEPROM_CUSTOMER_ID 0xCB
682#define EEPROM_RF_OPT7 0xCC
683
684#define EEPROM_DEF_PART_NO 0x3FD /* Byte */
685#define EEPROME_CHIP_VERSION_L 0x3FF
686#define EEPROME_CHIP_VERSION_H 0x3FE
687
688/*
689 * Current IOREG MAP
690 * 0x0000h ~ 0x00FFh System Configuration (256 Bytes)
691 * 0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes)
692 * 0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes)
693 * 0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes)
694 * 0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes)
695 * 0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes)
696 * 0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes)
697 * 0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes)
698 * 0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes)
699 */
700
701/* ----------------------------------------------------- */
702/* 8192C (RCR) (Offset 0x608, 32 bits) */
703/* ----------------------------------------------------- */
704#define RCR_APPFCS BIT(31)
705#define RCR_APP_MIC BIT(30)
706#define RCR_APP_ICV BIT(29)
707#define RCR_APP_PHYST_RXFF BIT(28)
708#define RCR_APP_BA_SSN BIT(27)
709#define RCR_ENMBID BIT(24)
710#define RCR_LSIGEN BIT(23)
711#define RCR_MFBEN BIT(22)
712#define RCR_HTC_LOC_CTRL BIT(14)
713#define RCR_AMF BIT(13)
714#define RCR_ACF BIT(12)
715#define RCR_ADF BIT(11)
716#define RCR_AICV BIT(9)
717#define RCR_ACRC32 BIT(8)
718#define RCR_CBSSID_BCN BIT(7)
719#define RCR_CBSSID_DATA BIT(6)
720#define RCR_APWRMGT BIT(5)
721#define RCR_ADD3 BIT(4)
722#define RCR_AB BIT(3)
723#define RCR_AM BIT(2)
724#define RCR_APM BIT(1)
725#define RCR_AAP BIT(0)
726#define RCR_MXDMA_OFFSET 8
727#define RCR_FIFO_OFFSET 13
728
729/* ----------------------------------------------------- */
730/* 8192C Regsiter Bit and Content definition */
731/* ----------------------------------------------------- */
732/* ----------------------------------------------------- */
733/* 0x0000h ~ 0x00FFh System Configuration */
734/* ----------------------------------------------------- */
735
736/* SPS0_CTRL */
737#define SW18_FPWM BIT(3)
738
739
740/* SYS_ISO_CTRL */
741#define ISO_MD2PP BIT(0)
742#define ISO_UA2USB BIT(1)
743#define ISO_UD2CORE BIT(2)
744#define ISO_PA2PCIE BIT(3)
745#define ISO_PD2CORE BIT(4)
746#define ISO_IP2MAC BIT(5)
747#define ISO_DIOP BIT(6)
748#define ISO_DIOE BIT(7)
749#define ISO_EB2CORE BIT(8)
750#define ISO_DIOR BIT(9)
751
752#define PWC_EV25V BIT(14)
753#define PWC_EV12V BIT(15)
754
755
756/* SYS_FUNC_EN */
757#define FEN_BBRSTB BIT(0)
758#define FEN_BB_GLB_RSTn BIT(1)
759#define FEN_USBA BIT(2)
760#define FEN_UPLL BIT(3)
761#define FEN_USBD BIT(4)
762#define FEN_DIO_PCIE BIT(5)
763#define FEN_PCIEA BIT(6)
764#define FEN_PPLL BIT(7)
765#define FEN_PCIED BIT(8)
766#define FEN_DIOE BIT(9)
767#define FEN_CPUEN BIT(10)
768#define FEN_DCORE BIT(11)
769#define FEN_ELDR BIT(12)
770#define FEN_DIO_RF BIT(13)
771#define FEN_HWPDN BIT(14)
772#define FEN_MREGEN BIT(15)
773
774/* APS_FSMCO */
775#define PFM_LDALL BIT(0)
776#define PFM_ALDN BIT(1)
777#define PFM_LDKP BIT(2)
778#define PFM_WOWL BIT(3)
779#define EnPDN BIT(4)
780#define PDN_PL BIT(5)
781#define APFM_ONMAC BIT(8)
782#define APFM_OFF BIT(9)
783#define APFM_RSM BIT(10)
784#define AFSM_HSUS BIT(11)
785#define AFSM_PCIE BIT(12)
786#define APDM_MAC BIT(13)
787#define APDM_HOST BIT(14)
788#define APDM_HPDN BIT(15)
789#define RDY_MACON BIT(16)
790#define SUS_HOST BIT(17)
791#define ROP_ALD BIT(20)
792#define ROP_PWR BIT(21)
793#define ROP_SPS BIT(22)
794#define SOP_MRST BIT(25)
795#define SOP_FUSE BIT(26)
796#define SOP_ABG BIT(27)
797#define SOP_AMB BIT(28)
798#define SOP_RCK BIT(29)
799#define SOP_A8M BIT(30)
800#define XOP_BTCK BIT(31)
801
802/* SYS_CLKR */
803#define ANAD16V_EN BIT(0)
804#define ANA8M BIT(1)
805#define MACSLP BIT(4)
806#define LOADER_CLK_EN BIT(5)
807#define _80M_SSC_DIS BIT(7)
808#define _80M_SSC_EN_HO BIT(8)
809#define PHY_SSC_RSTB BIT(9)
810#define SEC_CLK_EN BIT(10)
811#define MAC_CLK_EN BIT(11)
812#define SYS_CLK_EN BIT(12)
813#define RING_CLK_EN BIT(13)
814
815
816/* 9346CR */
817#define BOOT_FROM_EEPROM BIT(4)
818#define EEPROM_EN BIT(5)
819
820/* AFE_MISC */
821#define AFE_BGEN BIT(0)
822#define AFE_MBEN BIT(1)
823#define MAC_ID_EN BIT(7)
824
825/* RSV_CTRL */
826#define WLOCK_ALL BIT(0)
827#define WLOCK_00 BIT(1)
828#define WLOCK_04 BIT(2)
829#define WLOCK_08 BIT(3)
830#define WLOCK_40 BIT(4)
831#define R_DIS_PRST_0 BIT(5)
832#define R_DIS_PRST_1 BIT(6)
833#define LOCK_ALL_EN BIT(7)
834
835/* RF_CTRL */
836#define RF_EN BIT(0)
837#define RF_RSTB BIT(1)
838#define RF_SDMRSTB BIT(2)
839
840
841
842/* LDOA15_CTRL */
843#define LDA15_EN BIT(0)
844#define LDA15_STBY BIT(1)
845#define LDA15_OBUF BIT(2)
846#define LDA15_REG_VOS BIT(3)
847#define _LDA15_VOADJ(x) (((x) & 0x7) << 4)
848
849
850
851/* LDOV12D_CTRL */
852#define LDV12_EN BIT(0)
853#define LDV12_SDBY BIT(1)
854#define LPLDO_HSM BIT(2)
855#define LPLDO_LSM_DIS BIT(3)
856#define _LDV12_VADJ(x) (((x) & 0xF) << 4)
857
858
859/* AFE_XTAL_CTRL */
860#define XTAL_EN BIT(0)
861#define XTAL_BSEL BIT(1)
862#define _XTAL_BOSC(x) (((x) & 0x3) << 2)
863#define _XTAL_CADJ(x) (((x) & 0xF) << 4)
864#define XTAL_GATE_USB BIT(8)
865#define _XTAL_USB_DRV(x) (((x) & 0x3) << 9)
866#define XTAL_GATE_AFE BIT(11)
867#define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12)
868#define XTAL_RF_GATE BIT(14)
869#define _XTAL_RF_DRV(x) (((x) & 0x3) << 15)
870#define XTAL_GATE_DIG BIT(17)
871#define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18)
872#define XTAL_BT_GATE BIT(20)
873#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21)
874#define _XTAL_GPIO(x) (((x) & 0x7) << 23)
875
876
877#define CKDLY_AFE BIT(26)
878#define CKDLY_USB BIT(27)
879#define CKDLY_DIG BIT(28)
880#define CKDLY_BT BIT(29)
881
882
883/* AFE_PLL_CTRL */
884#define APLL_EN BIT(0)
885#define APLL_320_EN BIT(1)
886#define APLL_FREF_SEL BIT(2)
887#define APLL_EDGE_SEL BIT(3)
888#define APLL_WDOGB BIT(4)
889#define APLL_LPFEN BIT(5)
890
891#define APLL_REF_CLK_13MHZ 0x1
892#define APLL_REF_CLK_19_2MHZ 0x2
893#define APLL_REF_CLK_20MHZ 0x3
894#define APLL_REF_CLK_25MHZ 0x4
895#define APLL_REF_CLK_26MHZ 0x5
896#define APLL_REF_CLK_38_4MHZ 0x6
897#define APLL_REF_CLK_40MHZ 0x7
898
899#define APLL_320EN BIT(14)
900#define APLL_80EN BIT(15)
901#define APLL_1MEN BIT(24)
902
903
904/* EFUSE_CTRL */
905#define ALD_EN BIT(18)
906#define EF_PD BIT(19)
907#define EF_FLAG BIT(31)
908
909/* EFUSE_TEST */
910#define EF_TRPT BIT(7)
911#define LDOE25_EN BIT(31)
912
913/* MCUFWDL */
914#define MCUFWDL_EN BIT(0)
915#define MCUFWDL_RDY BIT(1)
916#define FWDL_ChkSum_rpt BIT(2)
917#define MACINI_RDY BIT(3)
918#define BBINI_RDY BIT(4)
919#define RFINI_RDY BIT(5)
920#define WINTINI_RDY BIT(6)
921#define MAC1_WINTINI_RDY BIT(11)
922#define CPRST BIT(23)
923
924/* REG_SYS_CFG */
925#define XCLK_VLD BIT(0)
926#define ACLK_VLD BIT(1)
927#define UCLK_VLD BIT(2)
928#define PCLK_VLD BIT(3)
929#define PCIRSTB BIT(4)
930#define V15_VLD BIT(5)
931#define TRP_B15V_EN BIT(7)
932#define SIC_IDLE BIT(8)
933#define BD_MAC2 BIT(9)
934#define BD_MAC1 BIT(10)
935#define IC_MACPHY_MODE BIT(11)
936#define PAD_HWPD_IDN BIT(22)
937#define TRP_VAUX_EN BIT(23)
938#define TRP_BT_EN BIT(24)
939#define BD_PKG_SEL BIT(25)
940#define BD_HCI_SEL BIT(26)
941#define TYPE_ID BIT(27)
942
943/* LLT_INIT */
944#define _LLT_NO_ACTIVE 0x0
945#define _LLT_WRITE_ACCESS 0x1
946#define _LLT_READ_ACCESS 0x2
947
948#define _LLT_INIT_DATA(x) ((x) & 0xFF)
949#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8)
950#define _LLT_OP(x) (((x) & 0x3) << 30)
951#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3)
952
953
954/* ----------------------------------------------------- */
955/* 0x0400h ~ 0x047Fh Protocol Configuration */
956/* ----------------------------------------------------- */
957#define RETRY_LIMIT_SHORT_SHIFT 8
958#define RETRY_LIMIT_LONG_SHIFT 0
959
960
961/* ----------------------------------------------------- */
962/* 0x0500h ~ 0x05FFh EDCA Configuration */
963/* ----------------------------------------------------- */
964/* EDCA setting */
965#define AC_PARAM_TXOP_LIMIT_OFFSET 16
966#define AC_PARAM_ECW_MAX_OFFSET 12
967#define AC_PARAM_ECW_MIN_OFFSET 8
968#define AC_PARAM_AIFS_OFFSET 0
969
970/* ACMHWCTRL */
971#define ACMHW_HWEN BIT(0)
972#define ACMHW_BEQEN BIT(1)
973#define ACMHW_VIQEN BIT(2)
974#define ACMHW_VOQEN BIT(3)
975
976/* ----------------------------------------------------- */
977/* 0x0600h ~ 0x07FFh WMAC Configuration */
978/* ----------------------------------------------------- */
979
980/* TCR */
981#define TSFRST BIT(0)
982#define DIS_GCLK BIT(1)
983#define PAD_SEL BIT(2)
984#define PWR_ST BIT(6)
985#define PWRBIT_OW_EN BIT(7)
986#define ACRC BIT(8)
987#define CFENDFORM BIT(9)
988#define ICV BIT(10)
989
990/* SECCFG */
991#define SCR_TXUSEDK BIT(0)
992#define SCR_RXUSEDK BIT(1)
993#define SCR_TXENCENABLE BIT(2)
994#define SCR_RXENCENABLE BIT(3)
995#define SCR_SKBYA2 BIT(4)
996#define SCR_NOSKMC BIT(5)
997#define SCR_TXBCUSEDK BIT(6)
998#define SCR_RXBCUSEDK BIT(7)
999
1000/* General definitions */
1001#define MAC_ADDR_LEN 6
1002#define LAST_ENTRY_OF_TX_PKT_BUFFER 255
1003#define LAST_ENTRY_OF_TX_PKT_BUFFER_DUAL_MAC 127
1004
1005#define POLLING_LLT_THRESHOLD 20
1006#define POLLING_READY_TIMEOUT_COUNT 1000
1007
1008/* Min Spacing related settings. */
1009#define MAX_MSS_DENSITY_2T 0x13
1010#define MAX_MSS_DENSITY_1T 0x0A
1011
1012
1013/* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
1014/* 1. PMAC duplicate register due to connection: */
1015/* RF_Mode, TRxRN, NumOf L-STF */
1016/* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */
1017/* 3. RF register 0x00-2E */
1018/* 4. Bit Mask for BB/RF register */
1019/* 5. Other defintion for BB/RF R/W */
1020
1021/* 3. Page8(0x800) */
1022#define RFPGA0_RFMOD 0x800
1023
1024#define RFPGA0_TXINFO 0x804
1025#define RFPGA0_PSDFUNCTION 0x808
1026
1027#define RFPGA0_TXGAINSTAGE 0x80c
1028
1029#define RFPGA0_RFTIMING1 0x810
1030#define RFPGA0_RFTIMING2 0x814
1031
1032#define RFPGA0_XA_HSSIPARAMETER1 0x820
1033#define RFPGA0_XA_HSSIPARAMETER2 0x824
1034#define RFPGA0_XB_HSSIPARAMETER1 0x828
1035#define RFPGA0_XB_HSSIPARAMETER2 0x82c
1036
1037#define RFPGA0_XA_LSSIPARAMETER 0x840
1038#define RFPGA0_XB_LSSIPARAMETER 0x844
1039
1040#define RFPGA0_RFWAkEUPPARAMETER 0x850
1041#define RFPGA0_RFSLEEPUPPARAMETER 0x854
1042
1043#define RFPGA0_XAB_SWITCHCONTROL 0x858
1044#define RFPGA0_XCD_SWITCHCONTROL 0x85c
1045
1046#define RFPGA0_XA_RFINTERFACEOE 0x860
1047#define RFPGA0_XB_RFINTERFACEOE 0x864
1048
1049#define RFPGA0_XAB_RFINTERFACESW 0x870
1050#define RFPGA0_XCD_RFINTERFACESW 0x874
1051
1052#define RFPGA0_XAB_RFPARAMETER 0x878
1053#define RFPGA0_XCD_RFPARAMETER 0x87c
1054
1055#define RFPGA0_ANALOGPARAMETER1 0x880
1056#define RFPGA0_ANALOGPARAMETER2 0x884
1057#define RFPGA0_ANALOGPARAMETER3 0x888
1058#define RFPGA0_ADDALLOCKEN 0x888
1059#define RFPGA0_ANALOGPARAMETER4 0x88c
1060
1061#define RFPGA0_XA_LSSIREADBACK 0x8a0
1062#define RFPGA0_XB_LSSIREADBACK 0x8a4
1063#define RFPGA0_XC_LSSIREADBACK 0x8a8
1064#define RFPGA0_XD_LSSIREADBACK 0x8ac
1065
1066#define RFPGA0_PSDREPORT 0x8b4
1067#define TRANSCEIVERA_HSPI_READBACK 0x8b8
1068#define TRANSCEIVERB_HSPI_READBACK 0x8bc
1069#define RFPGA0_XAB_RFINTERFACERB 0x8e0
1070#define RFPGA0_XCD_RFINTERFACERB 0x8e4
1071
1072/* 4. Page9(0x900) */
1073#define RFPGA1_RFMOD 0x900
1074
1075#define RFPGA1_TXBLOCK 0x904
1076#define RFPGA1_DEBUGSELECT 0x908
1077#define RFPGA1_TXINFO 0x90c
1078
1079/* 5. PageA(0xA00) */
1080#define RCCK0_SYSTEM 0xa00
1081
1082#define RCCK0_AFESSTTING 0xa04
1083#define RCCK0_CCA 0xa08
1084
1085#define RCCK0_RXAGC1 0xa0c
1086#define RCCK0_RXAGC2 0xa10
1087
1088#define RCCK0_RXHP 0xa14
1089
1090#define RCCK0_DSPPARAMETER1 0xa18
1091#define RCCK0_DSPPARAMETER2 0xa1c
1092
1093#define RCCK0_TXFILTER1 0xa20
1094#define RCCK0_TXFILTER2 0xa24
1095#define RCCK0_DEBUGPORT 0xa28
1096#define RCCK0_FALSEALARMREPORT 0xa2c
1097#define RCCK0_TRSSIREPORT 0xa50
1098#define RCCK0_RXREPORT 0xa54
1099#define RCCK0_FACOUNTERLOWER 0xa5c
1100#define RCCK0_FACOUNTERUPPER 0xa58
1101
1102/* 6. PageC(0xC00) */
1103#define ROFDM0_LSTF 0xc00
1104
1105#define ROFDM0_TRXPATHENABLE 0xc04
1106#define ROFDM0_TRMUXPAR 0xc08
1107#define ROFDM0_TRSWISOLATION 0xc0c
1108
1109#define ROFDM0_XARXAFE 0xc10
1110#define ROFDM0_XARXIQIMBALANCE 0xc14
1111#define ROFDM0_XBRXAFE 0xc18
1112#define ROFDM0_XBRXIQIMBALANCE 0xc1c
1113#define ROFDM0_XCRXAFE 0xc20
1114#define ROFDM0_XCRXIQIMBALANCE 0xc24
1115#define ROFDM0_XDRXAFE 0xc28
1116#define ROFDM0_XDRXIQIMBALANCE 0xc2c
1117
1118#define ROFDM0_RXDETECTOR1 0xc30
1119#define ROFDM0_RXDETECTOR2 0xc34
1120#define ROFDM0_RXDETECTOR3 0xc38
1121#define ROFDM0_RXDETECTOR4 0xc3c
1122
1123#define ROFDM0_RXDSP 0xc40
1124#define ROFDM0_CFOANDDAGC 0xc44
1125#define ROFDM0_CCADROPTHRESHOLD 0xc48
1126#define ROFDM0_ECCATHRESHOLD 0xc4c
1127
1128#define ROFDM0_XAAGCCORE1 0xc50
1129#define ROFDM0_XAAGCCORE2 0xc54
1130#define ROFDM0_XBAGCCORE1 0xc58
1131#define ROFDM0_XBAGCCORE2 0xc5c
1132#define ROFDM0_XCAGCCORE1 0xc60
1133#define ROFDM0_XCAGCCORE2 0xc64
1134#define ROFDM0_XDAGCCORE1 0xc68
1135#define ROFDM0_XDAGCCORE2 0xc6c
1136
1137#define ROFDM0_AGCPARAMETER1 0xc70
1138#define ROFDM0_AGCPARAMETER2 0xc74
1139#define ROFDM0_AGCRSSITABLE 0xc78
1140#define ROFDM0_HTSTFAGC 0xc7c
1141
1142#define ROFDM0_XATxIQIMBALANCE 0xc80
1143#define ROFDM0_XATxAFE 0xc84
1144#define ROFDM0_XBTxIQIMBALANCE 0xc88
1145#define ROFDM0_XBTxAFE 0xc8c
1146#define ROFDM0_XCTxIQIMBALANCE 0xc90
1147#define ROFDM0_XCTxAFE 0xc94
1148#define ROFDM0_XDTxIQIMBALANCE 0xc98
1149#define ROFDM0_XDTxAFE 0xc9c
1150
1151#define ROFDM0_RXHPPARAMETER 0xce0
1152#define ROFDM0_TXPSEUDONOISEWGT 0xce4
1153#define ROFDM0_FRAMESYNC 0xcf0
1154#define ROFDM0_DFSREPORT 0xcf4
1155#define ROFDM0_TXCOEFF1 0xca4
1156#define ROFDM0_TXCOEFF2 0xca8
1157#define ROFDM0_TXCOEFF3 0xcac
1158#define ROFDM0_TXCOEFF4 0xcb0
1159#define ROFDM0_TXCOEFF5 0xcb4
1160#define ROFDM0_TXCOEFF6 0xcb8
1161
1162/* 7. PageD(0xD00) */
1163#define ROFDM1_LSTF 0xd00
1164#define ROFDM1_TRXPATHENABLE 0xd04
1165
1166#define ROFDM1_CFO 0xd08
1167#define ROFDM1_CSI1 0xd10
1168#define ROFDM1_SBD 0xd14
1169#define ROFDM1_CSI2 0xd18
1170#define ROFDM1_CFOTRACKING 0xd2c
1171#define ROFDM1_TRXMESAURE1 0xd34
1172#define ROFDM1_INTFDET 0xd3c
1173#define ROFDM1_PSEUDONOISESTATEAB 0xd50
1174#define ROFDM1_PSEUDONOISESTATECD 0xd54
1175#define ROFDM1_RXPSEUDONOISEWGT 0xd58
1176
1177#define ROFDM_PHYCOUNTER1 0xda0
1178#define ROFDM_PHYCOUNTER2 0xda4
1179#define ROFDM_PHYCOUNTER3 0xda8
1180
1181#define ROFDM_SHORTCFOAB 0xdac
1182#define ROFDM_SHORTCFOCD 0xdb0
1183#define ROFDM_LONGCFOAB 0xdb4
1184#define ROFDM_LONGCFOCD 0xdb8
1185#define ROFDM_TAILCFOAB 0xdbc
1186#define ROFDM_TAILCFOCD 0xdc0
1187#define ROFDM_PWMEASURE1 0xdc4
1188#define ROFDM_PWMEASURE2 0xdc8
1189#define ROFDM_BWREPORT 0xdcc
1190#define ROFDM_AGCREPORT 0xdd0
1191#define ROFDM_RXSNR 0xdd4
1192#define ROFDM_RXEVMCSI 0xdd8
1193#define ROFDM_SIGReport 0xddc
1194
1195/* 8. PageE(0xE00) */
1196#define RTXAGC_A_RATE18_06 0xe00
1197#define RTXAGC_A_RATE54_24 0xe04
1198#define RTXAGC_A_CCK1_MCS32 0xe08
1199#define RTXAGC_A_MCS03_MCS00 0xe10
1200#define RTXAGC_A_MCS07_MCS04 0xe14
1201#define RTXAGC_A_MCS11_MCS08 0xe18
1202#define RTXAGC_A_MCS15_MCS12 0xe1c
1203
1204#define RTXAGC_B_RATE18_06 0x830
1205#define RTXAGC_B_RATE54_24 0x834
1206#define RTXAGC_B_CCK1_55_MCS32 0x838
1207#define RTXAGC_B_MCS03_MCS00 0x83c
1208#define RTXAGC_B_MCS07_MCS04 0x848
1209#define RTXAGC_B_MCS11_MCS08 0x84c
1210#define RTXAGC_B_MCS15_MCS12 0x868
1211#define RTXAGC_B_CCK11_A_CCK2_11 0x86c
1212
1213/* RL6052 Register definition */
1214#define RF_AC 0x00
1215
1216#define RF_IQADJ_G1 0x01
1217#define RF_IQADJ_G2 0x02
1218#define RF_POW_TRSW 0x05
1219
1220#define RF_GAIN_RX 0x06
1221#define RF_GAIN_TX 0x07
1222
1223#define RF_TXM_IDAC 0x08
1224#define RF_BS_IQGEN 0x0F
1225
1226#define RF_MODE1 0x10
1227#define RF_MODE2 0x11
1228
1229#define RF_RX_AGC_HP 0x12
1230#define RF_TX_AGC 0x13
1231#define RF_BIAS 0x14
1232#define RF_IPA 0x15
1233#define RF_POW_ABILITY 0x17
1234#define RF_MODE_AG 0x18
1235#define rRfChannel 0x18
1236#define RF_CHNLBW 0x18
1237#define RF_TOP 0x19
1238
1239#define RF_RX_G1 0x1A
1240#define RF_RX_G2 0x1B
1241
1242#define RF_RX_BB2 0x1C
1243#define RF_RX_BB1 0x1D
1244
1245#define RF_RCK1 0x1E
1246#define RF_RCK2 0x1F
1247
1248#define RF_TX_G1 0x20
1249#define RF_TX_G2 0x21
1250#define RF_TX_G3 0x22
1251
1252#define RF_TX_BB1 0x23
1253
1254#define RF_T_METER 0x42
1255
1256#define RF_SYN_G1 0x25
1257#define RF_SYN_G2 0x26
1258#define RF_SYN_G3 0x27
1259#define RF_SYN_G4 0x28
1260#define RF_SYN_G5 0x29
1261#define RF_SYN_G6 0x2A
1262#define RF_SYN_G7 0x2B
1263#define RF_SYN_G8 0x2C
1264
1265#define RF_RCK_OS 0x30
1266
1267#define RF_TXPA_G1 0x31
1268#define RF_TXPA_G2 0x32
1269#define RF_TXPA_G3 0x33
1270
1271/* Bit Mask */
1272
1273/* 2. Page8(0x800) */
1274#define BRFMOD 0x1
1275#define BCCKTXSC 0x30
1276#define BCCKEN 0x1000000
1277#define BOFDMEN 0x2000000
1278
1279#define B3WIREDATALENGTH 0x800
1280#define B3WIREADDRESSLENGTH 0x400
1281
1282#define BRFSI_RFENV 0x10
1283
1284#define BLSSIREADADDRESS 0x7f800000
1285#define BLSSIREADEDGE 0x80000000
1286#define BLSSIREADBACKDATA 0xfffff
1287/* 4. PageA(0xA00) */
1288#define BCCKSIDEBAND 0x10
1289
1290/* Other Definition */
1291#define BBYTE0 0x1
1292#define BBYTE1 0x2
1293#define BBYTE2 0x4
1294#define BBYTE3 0x8
1295#define BWORD0 0x3
1296#define BWORD1 0xc
1297#define BDWORD 0xf
1298
1299#define BMASKBYTE0 0xff
1300#define BMASKBYTE1 0xff00
1301#define BMASKBYTE2 0xff0000
1302#define BMASKBYTE3 0xff000000
1303#define BMASKHWORD 0xffff0000
1304#define BMASKLWORD 0x0000ffff
1305#define BMASKDWORD 0xffffffff
1306#define BMASK12BITS 0xfff
1307#define BMASKH4BITS 0xf0000000
1308#define BMASKOFDM_D 0xffc00000
1309#define BMASKCCK 0x3f3f3f3f
1310
1311#define BRFREGOFFSETMASK 0xfffff
1312
1313#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/rf.c b/drivers/net/wireless/rtlwifi/rtl8192de/rf.c
new file mode 100644
index 000000000000..c326372220f3
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/rf.c
@@ -0,0 +1,628 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "reg.h"
32#include "def.h"
33#include "phy.h"
34#include "rf.h"
35#include "dm.h"
36#include "hw.h"
37
38void rtl92d_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
39{
40 struct rtl_priv *rtlpriv = rtl_priv(hw);
41 struct rtl_phy *rtlphy = &(rtlpriv->phy);
42 u8 rfpath;
43
44 switch (bandwidth) {
45 case HT_CHANNEL_WIDTH_20:
46 for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
47 rtlphy->rfreg_chnlval[rfpath] = ((rtlphy->rfreg_chnlval
48 [rfpath] & 0xfffff3ff) | 0x0400);
49 rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(10) |
50 BIT(11), 0x01);
51
52 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
53 ("20M RF 0x18 = 0x%x\n",
54 rtlphy->rfreg_chnlval[rfpath]));
55 }
56
57 break;
58 case HT_CHANNEL_WIDTH_20_40:
59 for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
60 rtlphy->rfreg_chnlval[rfpath] =
61 ((rtlphy->rfreg_chnlval[rfpath] & 0xfffff3ff));
62 rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(10) | BIT(11),
63 0x00);
64 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
65 ("40M RF 0x18 = 0x%x\n",
66 rtlphy->rfreg_chnlval[rfpath]));
67 }
68 break;
69 default:
70 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
71 ("unknown bandwidth: %#X\n", bandwidth));
72 break;
73 }
74}
75
76void rtl92d_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
77 u8 *ppowerlevel)
78{
79 struct rtl_priv *rtlpriv = rtl_priv(hw);
80 struct rtl_phy *rtlphy = &(rtlpriv->phy);
81 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
82 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
83 u32 tx_agc[2] = {0, 0}, tmpval;
84 bool turbo_scanoff = false;
85 u8 idx1, idx2;
86 u8 *ptr;
87
88 if (rtlefuse->eeprom_regulatory != 0)
89 turbo_scanoff = true;
90 if (mac->act_scanning == true) {
91 tx_agc[RF90_PATH_A] = 0x3f3f3f3f;
92 tx_agc[RF90_PATH_B] = 0x3f3f3f3f;
93 if (turbo_scanoff) {
94 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
95 tx_agc[idx1] = ppowerlevel[idx1] |
96 (ppowerlevel[idx1] << 8) |
97 (ppowerlevel[idx1] << 16) |
98 (ppowerlevel[idx1] << 24);
99 }
100 }
101 } else {
102 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
103 tx_agc[idx1] = ppowerlevel[idx1] |
104 (ppowerlevel[idx1] << 8) |
105 (ppowerlevel[idx1] << 16) |
106 (ppowerlevel[idx1] << 24);
107 }
108 if (rtlefuse->eeprom_regulatory == 0) {
109 tmpval = (rtlphy->mcs_txpwrlevel_origoffset[0][6]) +
110 (rtlphy->mcs_txpwrlevel_origoffset[0][7] << 8);
111 tx_agc[RF90_PATH_A] += tmpval;
112 tmpval = (rtlphy->mcs_txpwrlevel_origoffset[0][14]) +
113 (rtlphy->mcs_txpwrlevel_origoffset[0][15] << 24);
114 tx_agc[RF90_PATH_B] += tmpval;
115 }
116 }
117
118 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
119 ptr = (u8 *) (&(tx_agc[idx1]));
120 for (idx2 = 0; idx2 < 4; idx2++) {
121 if (*ptr > RF6052_MAX_TX_PWR)
122 *ptr = RF6052_MAX_TX_PWR;
123 ptr++;
124 }
125 }
126
127 tmpval = tx_agc[RF90_PATH_A] & 0xff;
128 rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, BMASKBYTE1, tmpval);
129 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
130 ("CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
131 RTXAGC_A_CCK1_MCS32));
132 tmpval = tx_agc[RF90_PATH_A] >> 8;
133 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
134 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
135 ("CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
136 RTXAGC_B_CCK11_A_CCK2_11));
137 tmpval = tx_agc[RF90_PATH_B] >> 24;
138 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, BMASKBYTE0, tmpval);
139 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
140 ("CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
141 RTXAGC_B_CCK11_A_CCK2_11));
142 tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff;
143 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval);
144 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
145 ("CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
146 RTXAGC_B_CCK1_55_MCS32));
147}
148
149static void _rtl92d_phy_get_power_base(struct ieee80211_hw *hw,
150 u8 *ppowerlevel, u8 channel,
151 u32 *ofdmbase, u32 *mcsbase)
152{
153 struct rtl_priv *rtlpriv = rtl_priv(hw);
154 struct rtl_phy *rtlphy = &(rtlpriv->phy);
155 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
156 u32 powerbase0, powerbase1;
157 u8 legacy_pwrdiff, ht20_pwrdiff;
158 u8 i, powerlevel[2];
159
160 for (i = 0; i < 2; i++) {
161 powerlevel[i] = ppowerlevel[i];
162 legacy_pwrdiff = rtlefuse->txpwr_legacyhtdiff[i][channel - 1];
163 powerbase0 = powerlevel[i] + legacy_pwrdiff;
164 powerbase0 = (powerbase0 << 24) | (powerbase0 << 16) |
165 (powerbase0 << 8) | powerbase0;
166 *(ofdmbase + i) = powerbase0;
167 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
168 (" [OFDM power base index rf(%c) = 0x%x]\n",
169 ((i == 0) ? 'A' : 'B'), *(ofdmbase + i)));
170 }
171
172 for (i = 0; i < 2; i++) {
173 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) {
174 ht20_pwrdiff = rtlefuse->txpwr_ht20diff[i][channel - 1];
175 powerlevel[i] += ht20_pwrdiff;
176 }
177 powerbase1 = powerlevel[i];
178 powerbase1 = (powerbase1 << 24) | (powerbase1 << 16) |
179 (powerbase1 << 8) | powerbase1;
180 *(mcsbase + i) = powerbase1;
181 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
182 (" [MCS power base index rf(%c) = 0x%x]\n",
183 ((i == 0) ? 'A' : 'B'), *(mcsbase + i)));
184 }
185}
186
187static u8 _rtl92d_phy_get_chnlgroup_bypg(u8 chnlindex)
188{
189 u8 group;
190 u8 channel_info[59] = {
191 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
192 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
193 60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
194 114, 116, 118, 120, 122, 124, 126, 128, 130, 132,
195 134, 136, 138, 140, 149, 151, 153, 155, 157, 159,
196 161, 163, 165
197 };
198
199 if (channel_info[chnlindex] <= 3) /* Chanel 1-3 */
200 group = 0;
201 else if (channel_info[chnlindex] <= 9) /* Channel 4-9 */
202 group = 1;
203 else if (channel_info[chnlindex] <= 14) /* Channel 10-14 */
204 group = 2;
205 else if (channel_info[chnlindex] <= 64)
206 group = 6;
207 else if (channel_info[chnlindex] <= 140)
208 group = 7;
209 else
210 group = 8;
211 return group;
212}
213
214static void _rtl92d_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw,
215 u8 channel, u8 index,
216 u32 *powerbase0,
217 u32 *powerbase1,
218 u32 *p_outwriteval)
219{
220 struct rtl_priv *rtlpriv = rtl_priv(hw);
221 struct rtl_phy *rtlphy = &(rtlpriv->phy);
222 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
223 u8 i, chnlgroup = 0, pwr_diff_limit[4];
224 u32 writeval = 0, customer_limit, rf;
225
226 for (rf = 0; rf < 2; rf++) {
227 switch (rtlefuse->eeprom_regulatory) {
228 case 0:
229 chnlgroup = 0;
230 writeval = rtlphy->mcs_txpwrlevel_origoffset
231 [chnlgroup][index +
232 (rf ? 8 : 0)] + ((index < 2) ?
233 powerbase0[rf] :
234 powerbase1[rf]);
235 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, ("RTK better "
236 "performance, writeval(%c) = 0x%x\n",
237 ((rf == 0) ? 'A' : 'B'), writeval));
238 break;
239 case 1:
240 if (rtlphy->pwrgroup_cnt == 1)
241 chnlgroup = 0;
242 if (rtlphy->pwrgroup_cnt >= MAX_PG_GROUP) {
243 chnlgroup = _rtl92d_phy_get_chnlgroup_bypg(
244 channel - 1);
245 if (rtlphy->current_chan_bw ==
246 HT_CHANNEL_WIDTH_20)
247 chnlgroup++;
248 else
249 chnlgroup += 4;
250 writeval = rtlphy->mcs_txpwrlevel_origoffset
251 [chnlgroup][index +
252 (rf ? 8 : 0)] + ((index < 2) ?
253 powerbase0[rf] :
254 powerbase1[rf]);
255 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
256 ("Realtek regulatory, "
257 "20MHz, writeval(%c) = 0x%x\n",
258 ((rf == 0) ? 'A' : 'B'),
259 writeval));
260 }
261 break;
262 case 2:
263 writeval = ((index < 2) ? powerbase0[rf] :
264 powerbase1[rf]);
265 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, ("Better regulatory, "
266 "writeval(%c) = 0x%x\n",
267 ((rf == 0) ? 'A' : 'B'), writeval));
268 break;
269 case 3:
270 chnlgroup = 0;
271 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
272 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
273 ("customer's limit, 40MHz rf(%c) = "
274 "0x%x\n", ((rf == 0) ? 'A' : 'B'),
275 rtlefuse->pwrgroup_ht40[rf]
276 [channel - 1]));
277 } else {
278 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
279 ("customer's limit, 20MHz rf(%c) = "
280 "0x%x\n", ((rf == 0) ? 'A' : 'B'),
281 rtlefuse->pwrgroup_ht20[rf]
282 [channel - 1]));
283 }
284 for (i = 0; i < 4; i++) {
285 pwr_diff_limit[i] =
286 (u8)((rtlphy->mcs_txpwrlevel_origoffset
287 [chnlgroup][index + (rf ? 8 : 0)] &
288 (0x7f << (i * 8))) >> (i * 8));
289 if (rtlphy->current_chan_bw ==
290 HT_CHANNEL_WIDTH_20_40) {
291 if (pwr_diff_limit[i] >
292 rtlefuse->pwrgroup_ht40[rf]
293 [channel - 1])
294 pwr_diff_limit[i] =
295 rtlefuse->pwrgroup_ht40
296 [rf][channel - 1];
297 } else {
298 if (pwr_diff_limit[i] >
299 rtlefuse->pwrgroup_ht20[rf][
300 channel - 1])
301 pwr_diff_limit[i] =
302 rtlefuse->pwrgroup_ht20[rf]
303 [channel - 1];
304 }
305 }
306 customer_limit = (pwr_diff_limit[3] << 24) |
307 (pwr_diff_limit[2] << 16) |
308 (pwr_diff_limit[1] << 8) |
309 (pwr_diff_limit[0]);
310 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
311 ("Customer's limit rf(%c) = 0x%x\n",
312 ((rf == 0) ? 'A' : 'B'), customer_limit));
313 writeval = customer_limit + ((index < 2) ?
314 powerbase0[rf] : powerbase1[rf]);
315 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
316 ("Customer, writeval rf(%c)= 0x%x\n",
317 ((rf == 0) ? 'A' : 'B'), writeval));
318 break;
319 default:
320 chnlgroup = 0;
321 writeval = rtlphy->mcs_txpwrlevel_origoffset
322 [chnlgroup][index +
323 (rf ? 8 : 0)] + ((index < 2) ?
324 powerbase0[rf] : powerbase1[rf]);
325 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
326 ("RTK better performance, writeval "
327 "rf(%c) = 0x%x\n",
328 ((rf == 0) ? 'A' : 'B'), writeval));
329 break;
330 }
331 *(p_outwriteval + rf) = writeval;
332 }
333}
334
335static void _rtl92d_write_ofdm_power_reg(struct ieee80211_hw *hw,
336 u8 index, u32 *pvalue)
337{
338 struct rtl_priv *rtlpriv = rtl_priv(hw);
339 struct rtl_phy *rtlphy = &(rtlpriv->phy);
340 static u16 regoffset_a[6] = {
341 RTXAGC_A_RATE18_06, RTXAGC_A_RATE54_24,
342 RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04,
343 RTXAGC_A_MCS11_MCS08, RTXAGC_A_MCS15_MCS12
344 };
345 static u16 regoffset_b[6] = {
346 RTXAGC_B_RATE18_06, RTXAGC_B_RATE54_24,
347 RTXAGC_B_MCS03_MCS00, RTXAGC_B_MCS07_MCS04,
348 RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12
349 };
350 u8 i, rf, pwr_val[4];
351 u32 writeval;
352 u16 regoffset;
353
354 for (rf = 0; rf < 2; rf++) {
355 writeval = pvalue[rf];
356 for (i = 0; i < 4; i++) {
357 pwr_val[i] = (u8) ((writeval & (0x7f <<
358 (i * 8))) >> (i * 8));
359 if (pwr_val[i] > RF6052_MAX_TX_PWR)
360 pwr_val[i] = RF6052_MAX_TX_PWR;
361 }
362 writeval = (pwr_val[3] << 24) | (pwr_val[2] << 16) |
363 (pwr_val[1] << 8) | pwr_val[0];
364 if (rf == 0)
365 regoffset = regoffset_a[index];
366 else
367 regoffset = regoffset_b[index];
368 rtl_set_bbreg(hw, regoffset, BMASKDWORD, writeval);
369 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
370 ("Set 0x%x = %08x\n", regoffset, writeval));
371 if (((get_rf_type(rtlphy) == RF_2T2R) &&
372 (regoffset == RTXAGC_A_MCS15_MCS12 ||
373 regoffset == RTXAGC_B_MCS15_MCS12)) ||
374 ((get_rf_type(rtlphy) != RF_2T2R) &&
375 (regoffset == RTXAGC_A_MCS07_MCS04 ||
376 regoffset == RTXAGC_B_MCS07_MCS04))) {
377 writeval = pwr_val[3];
378 if (regoffset == RTXAGC_A_MCS15_MCS12 ||
379 regoffset == RTXAGC_A_MCS07_MCS04)
380 regoffset = 0xc90;
381 if (regoffset == RTXAGC_B_MCS15_MCS12 ||
382 regoffset == RTXAGC_B_MCS07_MCS04)
383 regoffset = 0xc98;
384 for (i = 0; i < 3; i++) {
385 if (i != 2)
386 writeval = (writeval > 8) ?
387 (writeval - 8) : 0;
388 else
389 writeval = (writeval > 6) ?
390 (writeval - 6) : 0;
391 rtl_write_byte(rtlpriv, (u32) (regoffset + i),
392 (u8) writeval);
393 }
394 }
395 }
396}
397
398void rtl92d_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
399 u8 *ppowerlevel, u8 channel)
400{
401 u32 writeval[2], powerbase0[2], powerbase1[2];
402 u8 index;
403
404 _rtl92d_phy_get_power_base(hw, ppowerlevel, channel,
405 &powerbase0[0], &powerbase1[0]);
406 for (index = 0; index < 6; index++) {
407 _rtl92d_get_txpower_writeval_by_regulatory(hw,
408 channel, index, &powerbase0[0],
409 &powerbase1[0], &writeval[0]);
410 _rtl92d_write_ofdm_power_reg(hw, index, &writeval[0]);
411 }
412}
413
414bool rtl92d_phy_enable_anotherphy(struct ieee80211_hw *hw, bool bmac0)
415{
416 struct rtl_priv *rtlpriv = rtl_priv(hw);
417 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
418 u8 u1btmp;
419 u8 direct = bmac0 == true ? BIT(3) | BIT(2) : BIT(3);
420 u8 mac_reg = bmac0 == true ? REG_MAC1 : REG_MAC0;
421 u8 mac_on_bit = bmac0 == true ? MAC1_ON : MAC0_ON;
422 bool bresult = true; /* true: need to enable BB/RF power */
423
424 rtlhal->during_mac0init_radiob = false;
425 rtlhal->during_mac1init_radioa = false;
426 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, ("===>\n"));
427 /* MAC0 Need PHY1 load radio_b.txt . Driver use DBI to write. */
428 u1btmp = rtl_read_byte(rtlpriv, mac_reg);
429 if (!(u1btmp & mac_on_bit)) {
430 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("enable BB & RF\n"));
431 /* Enable BB and RF power */
432 rtl92de_write_dword_dbi(hw, REG_SYS_ISO_CTRL,
433 rtl92de_read_dword_dbi(hw, REG_SYS_ISO_CTRL, direct) |
434 BIT(29) | BIT(16) | BIT(17), direct);
435 } else {
436 /* We think if MAC1 is ON,then radio_a.txt
437 * and radio_b.txt has been load. */
438 bresult = false;
439 }
440 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, ("<===\n"));
441 return bresult;
442
443}
444
445void rtl92d_phy_powerdown_anotherphy(struct ieee80211_hw *hw, bool bmac0)
446{
447 struct rtl_priv *rtlpriv = rtl_priv(hw);
448 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
449 u8 u1btmp;
450 u8 direct = bmac0 == true ? BIT(3) | BIT(2) : BIT(3);
451 u8 mac_reg = bmac0 == true ? REG_MAC1 : REG_MAC0;
452 u8 mac_on_bit = bmac0 == true ? MAC1_ON : MAC0_ON;
453
454 rtlhal->during_mac0init_radiob = false;
455 rtlhal->during_mac1init_radioa = false;
456 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, ("====>\n"));
457 /* check MAC0 enable or not again now, if
458 * enabled, not power down radio A. */
459 u1btmp = rtl_read_byte(rtlpriv, mac_reg);
460 if (!(u1btmp & mac_on_bit)) {
461 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("power down\n"));
462 /* power down RF radio A according to YuNan's advice. */
463 rtl92de_write_dword_dbi(hw, RFPGA0_XA_LSSIPARAMETER,
464 0x00000000, direct);
465 }
466 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, ("<====\n"));
467}
468
469bool rtl92d_phy_rf6052_config(struct ieee80211_hw *hw)
470{
471 struct rtl_priv *rtlpriv = rtl_priv(hw);
472 struct rtl_phy *rtlphy = &(rtlpriv->phy);
473 bool rtstatus = true;
474 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
475 u32 u4_regvalue = 0;
476 u8 rfpath;
477 struct bb_reg_def *pphyreg;
478 bool mac1_initradioa_first = false, mac0_initradiob_first = false;
479 bool need_pwrdown_radioa = false, need_pwrdown_radiob = false;
480 bool true_bpath = false;
481
482 if (rtlphy->rf_type == RF_1T1R)
483 rtlphy->num_total_rfpath = 1;
484 else
485 rtlphy->num_total_rfpath = 2;
486
487 /* Single phy mode: use radio_a radio_b config path_A path_B */
488 /* seperately by MAC0, and MAC1 needn't configure RF; */
489 /* Dual PHY mode:MAC0 use radio_a config 1st phy path_A, */
490 /* MAC1 use radio_b config 2nd PHY path_A. */
491 /* DMDP,MAC0 on G band,MAC1 on A band. */
492 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
493 if (rtlhal->current_bandtype == BAND_ON_2_4G &&
494 rtlhal->interfaceindex == 0) {
495 /* MAC0 needs PHY1 load radio_b.txt.
496 * Driver use DBI to write. */
497 if (rtl92d_phy_enable_anotherphy(hw, true)) {
498 rtlphy->num_total_rfpath = 2;
499 mac0_initradiob_first = true;
500 } else {
501 /* We think if MAC1 is ON,then radio_a.txt and
502 * radio_b.txt has been load. */
503 return rtstatus;
504 }
505 } else if (rtlhal->current_bandtype == BAND_ON_5G &&
506 rtlhal->interfaceindex == 1) {
507 /* MAC1 needs PHY0 load radio_a.txt.
508 * Driver use DBI to write. */
509 if (rtl92d_phy_enable_anotherphy(hw, false)) {
510 rtlphy->num_total_rfpath = 2;
511 mac1_initradioa_first = true;
512 } else {
513 /* We think if MAC0 is ON,then radio_a.txt and
514 * radio_b.txt has been load. */
515 return rtstatus;
516 }
517 } else if (rtlhal->interfaceindex == 1) {
518 /* MAC0 enabled, only init radia B. */
519 true_bpath = true;
520 }
521 }
522
523 for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
524 /* Mac1 use PHY0 write */
525 if (mac1_initradioa_first) {
526 if (rfpath == RF90_PATH_A) {
527 rtlhal->during_mac1init_radioa = true;
528 need_pwrdown_radioa = true;
529 } else if (rfpath == RF90_PATH_B) {
530 rtlhal->during_mac1init_radioa = false;
531 mac1_initradioa_first = false;
532 rfpath = RF90_PATH_A;
533 true_bpath = true;
534 rtlphy->num_total_rfpath = 1;
535 }
536 } else if (mac0_initradiob_first) {
537 /* Mac0 use PHY1 write */
538 if (rfpath == RF90_PATH_A)
539 rtlhal->during_mac0init_radiob = false;
540 if (rfpath == RF90_PATH_B) {
541 rtlhal->during_mac0init_radiob = true;
542 mac0_initradiob_first = false;
543 need_pwrdown_radiob = true;
544 rfpath = RF90_PATH_A;
545 true_bpath = true;
546 rtlphy->num_total_rfpath = 1;
547 }
548 }
549 pphyreg = &rtlphy->phyreg_def[rfpath];
550 switch (rfpath) {
551 case RF90_PATH_A:
552 case RF90_PATH_C:
553 u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
554 BRFSI_RFENV);
555 break;
556 case RF90_PATH_B:
557 case RF90_PATH_D:
558 u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
559 BRFSI_RFENV << 16);
560 break;
561 }
562 rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
563 udelay(1);
564 rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
565 udelay(1);
566 /* Set bit number of Address and Data for RF register */
567 /* Set 1 to 4 bits for 8255 */
568 rtl_set_bbreg(hw, pphyreg->rfhssi_para2,
569 B3WIREADDRESSLENGTH, 0x0);
570 udelay(1);
571 /* Set 0 to 12 bits for 8255 */
572 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
573 udelay(1);
574 switch (rfpath) {
575 case RF90_PATH_A:
576 if (true_bpath == true)
577 rtstatus = rtl92d_phy_config_rf_with_headerfile(
578 hw, radiob_txt,
579 (enum radio_path)rfpath);
580 else
581 rtstatus = rtl92d_phy_config_rf_with_headerfile(
582 hw, radioa_txt,
583 (enum radio_path)rfpath);
584 break;
585 case RF90_PATH_B:
586 rtstatus =
587 rtl92d_phy_config_rf_with_headerfile(hw, radiob_txt,
588 (enum radio_path) rfpath);
589 break;
590 case RF90_PATH_C:
591 break;
592 case RF90_PATH_D:
593 break;
594 }
595 switch (rfpath) {
596 case RF90_PATH_A:
597 case RF90_PATH_C:
598 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV,
599 u4_regvalue);
600 break;
601 case RF90_PATH_B:
602 case RF90_PATH_D:
603 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16,
604 u4_regvalue);
605 break;
606 }
607 if (rtstatus != true) {
608 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
609 ("Radio[%d] Fail!!", rfpath));
610 goto phy_rf_cfg_fail;
611 }
612
613 }
614
615 /* check MAC0 enable or not again, if enabled,
616 * not power down radio A. */
617 /* check MAC1 enable or not again, if enabled,
618 * not power down radio B. */
619 if (need_pwrdown_radioa)
620 rtl92d_phy_powerdown_anotherphy(hw, false);
621 else if (need_pwrdown_radiob)
622 rtl92d_phy_powerdown_anotherphy(hw, true);
623 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("<---\n"));
624 return rtstatus;
625
626phy_rf_cfg_fail:
627 return rtstatus;
628}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/rf.h b/drivers/net/wireless/rtlwifi/rtl8192de/rf.h
new file mode 100644
index 000000000000..74b9cfc39a83
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/rf.h
@@ -0,0 +1,44 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92D_RF_H__
31#define __RTL92D_RF_H__
32
33extern void rtl92d_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw,
34 u8 bandwidth);
35extern void rtl92d_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
36 u8 *ppowerlevel);
37extern void rtl92d_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
38 u8 *ppowerlevel, u8 channel);
39extern bool rtl92d_phy_rf6052_config(struct ieee80211_hw *hw);
40extern bool rtl92d_phy_enable_anotherphy(struct ieee80211_hw *hw, bool bmac0);
41extern void rtl92d_phy_powerdown_anotherphy(struct ieee80211_hw *hw,
42 bool bmac0);
43
44#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/sw.c b/drivers/net/wireless/rtlwifi/rtl8192de/sw.c
new file mode 100644
index 000000000000..08837744f6f1
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/sw.c
@@ -0,0 +1,423 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include <linux/vmalloc.h>
31
32#include "../wifi.h"
33#include "../core.h"
34#include "../pci.h"
35#include "reg.h"
36#include "def.h"
37#include "phy.h"
38#include "dm.h"
39#include "hw.h"
40#include "sw.h"
41#include "trx.h"
42#include "led.h"
43
44static void rtl92d_init_aspm_vars(struct ieee80211_hw *hw)
45{
46 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
47
48 /*close ASPM for AMD defaultly */
49 rtlpci->const_amdpci_aspm = 0;
50
51 /*
52 * ASPM PS mode.
53 * 0 - Disable ASPM,
54 * 1 - Enable ASPM without Clock Req,
55 * 2 - Enable ASPM with Clock Req,
56 * 3 - Alwyas Enable ASPM with Clock Req,
57 * 4 - Always Enable ASPM without Clock Req.
58 * set defult to RTL8192CE:3 RTL8192E:2
59 * */
60 rtlpci->const_pci_aspm = 3;
61
62 /*Setting for PCI-E device */
63 rtlpci->const_devicepci_aspm_setting = 0x03;
64
65 /*Setting for PCI-E bridge */
66 rtlpci->const_hostpci_aspm_setting = 0x02;
67
68 /*
69 * In Hw/Sw Radio Off situation.
70 * 0 - Default,
71 * 1 - From ASPM setting without low Mac Pwr,
72 * 2 - From ASPM setting with low Mac Pwr,
73 * 3 - Bus D3
74 * set default to RTL8192CE:0 RTL8192SE:2
75 */
76 rtlpci->const_hwsw_rfoff_d3 = 0;
77
78 /*
79 * This setting works for those device with
80 * backdoor ASPM setting such as EPHY setting.
81 * 0 - Not support ASPM,
82 * 1 - Support ASPM,
83 * 2 - According to chipset.
84 */
85 rtlpci->const_support_pciaspm = 1;
86}
87
88static int rtl92d_init_sw_vars(struct ieee80211_hw *hw)
89{
90 int err;
91 u8 tid;
92 struct rtl_priv *rtlpriv = rtl_priv(hw);
93 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
94 const struct firmware *firmware;
95 static int header_print;
96
97 rtlpriv->dm.dm_initialgain_enable = true;
98 rtlpriv->dm.dm_flag = 0;
99 rtlpriv->dm.disable_framebursting = 0;
100 rtlpriv->dm.thermalvalue = 0;
101 rtlpriv->dm.useramask = 1;
102
103 /* dual mac */
104 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G)
105 rtlpriv->phy.current_channel = 36;
106 else
107 rtlpriv->phy.current_channel = 1;
108
109 if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) {
110 rtlpriv->rtlhal.disable_amsdu_8k = true;
111 /* No long RX - reduce fragmentation */
112 rtlpci->rxbuffersize = 4096;
113 }
114
115 rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13);
116
117 rtlpci->receive_config = (
118 RCR_APPFCS
119 | RCR_AMF
120 | RCR_ADF
121 | RCR_APP_MIC
122 | RCR_APP_ICV
123 | RCR_AICV
124 | RCR_ACRC32
125 | RCR_AB
126 | RCR_AM
127 | RCR_APM
128 | RCR_APP_PHYST_RXFF
129 | RCR_HTC_LOC_CTRL
130 );
131
132 rtlpci->irq_mask[0] = (u32) (
133 IMR_ROK
134 | IMR_VODOK
135 | IMR_VIDOK
136 | IMR_BEDOK
137 | IMR_BKDOK
138 | IMR_MGNTDOK
139 | IMR_HIGHDOK
140 | IMR_BDOK
141 | IMR_RDU
142 | IMR_RXFOVW
143 );
144
145 rtlpci->irq_mask[1] = (u32) (IMR_CPWM | IMR_C2HCMD);
146
147 /* for LPS & IPS */
148 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
149 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
150 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
151 rtlpriv->psc.reg_fwctrl_lps = 3;
152 rtlpriv->psc.reg_max_lps_awakeintvl = 5;
153 /* for ASPM, you can close aspm through
154 * set const_support_pciaspm = 0 */
155 rtl92d_init_aspm_vars(hw);
156
157 if (rtlpriv->psc.reg_fwctrl_lps == 1)
158 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
159 else if (rtlpriv->psc.reg_fwctrl_lps == 2)
160 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
161 else if (rtlpriv->psc.reg_fwctrl_lps == 3)
162 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
163
164 /* for firmware buf */
165 rtlpriv->rtlhal.pfirmware = vzalloc(0x8000);
166 if (!rtlpriv->rtlhal.pfirmware) {
167 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
168 ("Can't alloc buffer for fw.\n"));
169 return 1;
170 }
171
172 if (!header_print) {
173 printk(KERN_INFO "rtl8192de: Driver for Realtek RTL8192DE"
174 " WLAN interface");
175 printk(KERN_INFO "rtl8192de: Loading firmware file %s\n",
176 rtlpriv->cfg->fw_name);
177 header_print++;
178 }
179 /* request fw */
180 err = request_firmware(&firmware, rtlpriv->cfg->fw_name,
181 rtlpriv->io.dev);
182 if (err) {
183 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
184 ("Failed to request firmware!\n"));
185 return 1;
186 }
187 if (firmware->size > 0x8000) {
188 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
189 ("Firmware is too big!\n"));
190 release_firmware(firmware);
191 return 1;
192 }
193 memcpy(rtlpriv->rtlhal.pfirmware, firmware->data, firmware->size);
194 rtlpriv->rtlhal.fwsize = firmware->size;
195 release_firmware(firmware);
196
197 /* for early mode */
198 rtlpriv->rtlhal.earlymode_enable = true;
199 for (tid = 0; tid < 8; tid++)
200 skb_queue_head_init(&rtlpriv->mac80211.skb_waitq[tid]);
201 return 0;
202}
203
204static void rtl92d_deinit_sw_vars(struct ieee80211_hw *hw)
205{
206 struct rtl_priv *rtlpriv = rtl_priv(hw);
207 u8 tid;
208
209 if (rtlpriv->rtlhal.pfirmware) {
210 vfree(rtlpriv->rtlhal.pfirmware);
211 rtlpriv->rtlhal.pfirmware = NULL;
212 }
213 for (tid = 0; tid < 8; tid++)
214 skb_queue_purge(&rtlpriv->mac80211.skb_waitq[tid]);
215}
216
217static struct rtl_hal_ops rtl8192de_hal_ops = {
218 .init_sw_vars = rtl92d_init_sw_vars,
219 .deinit_sw_vars = rtl92d_deinit_sw_vars,
220 .read_eeprom_info = rtl92de_read_eeprom_info,
221 .interrupt_recognized = rtl92de_interrupt_recognized,
222 .hw_init = rtl92de_hw_init,
223 .hw_disable = rtl92de_card_disable,
224 .hw_suspend = rtl92de_suspend,
225 .hw_resume = rtl92de_resume,
226 .enable_interrupt = rtl92de_enable_interrupt,
227 .disable_interrupt = rtl92de_disable_interrupt,
228 .set_network_type = rtl92de_set_network_type,
229 .set_chk_bssid = rtl92de_set_check_bssid,
230 .set_qos = rtl92de_set_qos,
231 .set_bcn_reg = rtl92de_set_beacon_related_registers,
232 .set_bcn_intv = rtl92de_set_beacon_interval,
233 .update_interrupt_mask = rtl92de_update_interrupt_mask,
234 .get_hw_reg = rtl92de_get_hw_reg,
235 .set_hw_reg = rtl92de_set_hw_reg,
236 .update_rate_tbl = rtl92de_update_hal_rate_tbl,
237 .fill_tx_desc = rtl92de_tx_fill_desc,
238 .fill_tx_cmddesc = rtl92de_tx_fill_cmddesc,
239 .query_rx_desc = rtl92de_rx_query_desc,
240 .set_channel_access = rtl92de_update_channel_access_setting,
241 .radio_onoff_checking = rtl92de_gpio_radio_on_off_checking,
242 .set_bw_mode = rtl92d_phy_set_bw_mode,
243 .switch_channel = rtl92d_phy_sw_chnl,
244 .dm_watchdog = rtl92d_dm_watchdog,
245 .scan_operation_backup = rtl92d_phy_scan_operation_backup,
246 .set_rf_power_state = rtl92d_phy_set_rf_power_state,
247 .led_control = rtl92de_led_control,
248 .set_desc = rtl92de_set_desc,
249 .get_desc = rtl92de_get_desc,
250 .tx_polling = rtl92de_tx_polling,
251 .enable_hw_sec = rtl92de_enable_hw_security_config,
252 .set_key = rtl92de_set_key,
253 .init_sw_leds = rtl92de_init_sw_leds,
254 .get_bbreg = rtl92d_phy_query_bb_reg,
255 .set_bbreg = rtl92d_phy_set_bb_reg,
256 .get_rfreg = rtl92d_phy_query_rf_reg,
257 .set_rfreg = rtl92d_phy_set_rf_reg,
258 .linked_set_reg = rtl92d_linked_set_reg,
259};
260
261static struct rtl_mod_params rtl92de_mod_params = {
262 .sw_crypto = false,
263 .inactiveps = true,
264 .swctrl_lps = true,
265 .fwctrl_lps = false,
266};
267
268static struct rtl_hal_cfg rtl92de_hal_cfg = {
269 .bar_id = 2,
270 .write_readback = true,
271 .name = "rtl8192de",
272 .fw_name = "rtlwifi/rtl8192defw.bin",
273 .ops = &rtl8192de_hal_ops,
274 .mod_params = &rtl92de_mod_params,
275
276 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
277 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
278 .maps[SYS_CLK] = REG_SYS_CLKR,
279 .maps[MAC_RCR_AM] = RCR_AM,
280 .maps[MAC_RCR_AB] = RCR_AB,
281 .maps[MAC_RCR_ACRC32] = RCR_ACRC32,
282 .maps[MAC_RCR_ACF] = RCR_ACF,
283 .maps[MAC_RCR_AAP] = RCR_AAP,
284
285 .maps[EFUSE_TEST] = REG_EFUSE_TEST,
286 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
287 .maps[EFUSE_CLK] = 0, /* just for 92se */
288 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
289 .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
290 .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
291 .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
292 .maps[EFUSE_ANA8M] = 0, /* just for 92se */
293 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
294 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
295 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
296
297 .maps[RWCAM] = REG_CAMCMD,
298 .maps[WCAMI] = REG_CAMWRITE,
299 .maps[RCAMO] = REG_CAMREAD,
300 .maps[CAMDBG] = REG_CAMDBG,
301 .maps[SECR] = REG_SECCFG,
302 .maps[SEC_CAM_NONE] = CAM_NONE,
303 .maps[SEC_CAM_WEP40] = CAM_WEP40,
304 .maps[SEC_CAM_TKIP] = CAM_TKIP,
305 .maps[SEC_CAM_AES] = CAM_AES,
306 .maps[SEC_CAM_WEP104] = CAM_WEP104,
307
308 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
309 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
310 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
311 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
312 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
313 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
314 .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
315 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
316 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
317 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
318 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
319 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
320 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
321 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
322 .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
323 .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
324
325 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
326 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
327 .maps[RTL_IMR_BcnInt] = IMR_BcnInt,
328 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
329 .maps[RTL_IMR_RDU] = IMR_RDU,
330 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
331 .maps[RTL_IMR_BDOK] = IMR_BDOK,
332 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
333 .maps[RTL_IMR_TBDER] = IMR_TBDER,
334 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
335 .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
336 .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
337 .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
338 .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
339 .maps[RTL_IMR_VODOK] = IMR_VODOK,
340 .maps[RTL_IMR_ROK] = IMR_ROK,
341 .maps[RTL_IBSS_INT_MASKS] = (IMR_BcnInt | IMR_TBDOK | IMR_TBDER),
342
343 .maps[RTL_RC_CCK_RATE1M] = DESC92D_RATE1M,
344 .maps[RTL_RC_CCK_RATE2M] = DESC92D_RATE2M,
345 .maps[RTL_RC_CCK_RATE5_5M] = DESC92D_RATE5_5M,
346 .maps[RTL_RC_CCK_RATE11M] = DESC92D_RATE11M,
347 .maps[RTL_RC_OFDM_RATE6M] = DESC92D_RATE6M,
348 .maps[RTL_RC_OFDM_RATE9M] = DESC92D_RATE9M,
349 .maps[RTL_RC_OFDM_RATE12M] = DESC92D_RATE12M,
350 .maps[RTL_RC_OFDM_RATE18M] = DESC92D_RATE18M,
351 .maps[RTL_RC_OFDM_RATE24M] = DESC92D_RATE24M,
352 .maps[RTL_RC_OFDM_RATE36M] = DESC92D_RATE36M,
353 .maps[RTL_RC_OFDM_RATE48M] = DESC92D_RATE48M,
354 .maps[RTL_RC_OFDM_RATE54M] = DESC92D_RATE54M,
355
356 .maps[RTL_RC_HT_RATEMCS7] = DESC92D_RATEMCS7,
357 .maps[RTL_RC_HT_RATEMCS15] = DESC92D_RATEMCS15,
358};
359
360static struct pci_device_id rtl92de_pci_ids[] __devinitdata = {
361 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8193, rtl92de_hal_cfg)},
362 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x002B, rtl92de_hal_cfg)},
363 {},
364};
365
366MODULE_DEVICE_TABLE(pci, rtl92de_pci_ids);
367
368MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
369MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
370MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
371MODULE_LICENSE("GPL");
372MODULE_DESCRIPTION("Realtek 8192DE 802.11n Dual Mac PCI wireless");
373MODULE_FIRMWARE("rtlwifi/rtl8192defw.bin");
374
375module_param_named(swenc, rtl92de_mod_params.sw_crypto, bool, 0444);
376module_param_named(ips, rtl92de_mod_params.inactiveps, bool, 0444);
377module_param_named(swlps, rtl92de_mod_params.swctrl_lps, bool, 0444);
378module_param_named(fwlps, rtl92de_mod_params.fwctrl_lps, bool, 0444);
379MODULE_PARM_DESC(swenc, "using hardware crypto (default 0 [hardware])\n");
380MODULE_PARM_DESC(ips, "using no link power save (default 1 is open)\n");
381MODULE_PARM_DESC(swlps, "using linked sw control power save (default 1"
382 " is open)\n");
383
384static struct pci_driver rtl92de_driver = {
385 .name = KBUILD_MODNAME,
386 .id_table = rtl92de_pci_ids,
387 .probe = rtl_pci_probe,
388 .remove = rtl_pci_disconnect,
389
390#ifdef CONFIG_PM
391 .suspend = rtl_pci_suspend,
392 .resume = rtl_pci_resume,
393#endif
394
395};
396
397/* add global spin lock to solve the problem that
398 * Dul mac register operation on the same time */
399spinlock_t globalmutex_power;
400spinlock_t globalmutex_for_fwdownload;
401spinlock_t globalmutex_for_power_and_efuse;
402
403static int __init rtl92de_module_init(void)
404{
405 int ret = 0;
406
407 spin_lock_init(&globalmutex_power);
408 spin_lock_init(&globalmutex_for_fwdownload);
409 spin_lock_init(&globalmutex_for_power_and_efuse);
410
411 ret = pci_register_driver(&rtl92de_driver);
412 if (ret)
413 RT_ASSERT(false, (": No device found\n"));
414 return ret;
415}
416
417static void __exit rtl92de_module_exit(void)
418{
419 pci_unregister_driver(&rtl92de_driver);
420}
421
422module_init(rtl92de_module_init);
423module_exit(rtl92de_module_exit);
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/sw.h b/drivers/net/wireless/rtlwifi/rtl8192de/sw.h
new file mode 100644
index 000000000000..c95e47de1346
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/sw.h
@@ -0,0 +1,37 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92DE_SW_H__
31#define __RTL92DE_SW_H__
32
33extern spinlock_t globalmutex_power;
34extern spinlock_t globalmutex_for_fwdownload;
35extern spinlock_t globalmutex_for_power_and_efuse;
36
37#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/table.c b/drivers/net/wireless/rtlwifi/rtl8192de/table.c
new file mode 100644
index 000000000000..bad7f9449ecf
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/table.c
@@ -0,0 +1,1690 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 * Created on 2010/12/23, 6:38
29 *****************************************************************************/
30
31#include <linux/types.h>
32
33#include "table.h"
34
35u32 rtl8192de_phy_reg_2tarray[PHY_REG_2T_ARRAYLENGTH] = {
36 0x024, 0x0011800d,
37 0x028, 0x00ffdb83,
38 0x014, 0x088ba955,
39 0x010, 0x49022b03,
40 0x800, 0x80040002,
41 0x804, 0x00000003,
42 0x808, 0x0000fc00,
43 0x80c, 0x0000000a,
44 0x810, 0x80706388,
45 0x814, 0x020c3d10,
46 0x818, 0x02200385,
47 0x81c, 0x00000000,
48 0x820, 0x01000100,
49 0x824, 0x00390004,
50 0x828, 0x01000100,
51 0x82c, 0x00390004,
52 0x830, 0x27272727,
53 0x834, 0x27272727,
54 0x838, 0x27272727,
55 0x83c, 0x27272727,
56 0x840, 0x00010000,
57 0x844, 0x00010000,
58 0x848, 0x27272727,
59 0x84c, 0x27272727,
60 0x850, 0x00000000,
61 0x854, 0x00000000,
62 0x858, 0x569a569a,
63 0x85c, 0x0c1b25a4,
64 0x860, 0x66e60230,
65 0x864, 0x061f0130,
66 0x868, 0x27272727,
67 0x86c, 0x272b2b2b,
68 0x870, 0x07000700,
69 0x874, 0x22188000,
70 0x878, 0x08080808,
71 0x87c, 0x00007ff8,
72 0x880, 0xc0083070,
73 0x884, 0x00000cd5,
74 0x888, 0x00000000,
75 0x88c, 0xcc0000c0,
76 0x890, 0x00000800,
77 0x894, 0xfffffffe,
78 0x898, 0x40302010,
79 0x89c, 0x00706050,
80 0x900, 0x00000000,
81 0x904, 0x00000023,
82 0x908, 0x00000000,
83 0x90c, 0x81121313,
84 0xa00, 0x00d047c8,
85 0xa04, 0x80ff000c,
86 0xa08, 0x8c838300,
87 0xa0c, 0x2e68120f,
88 0xa10, 0x9500bb78,
89 0xa14, 0x11144028,
90 0xa18, 0x00881117,
91 0xa1c, 0x89140f00,
92 0xa20, 0x1a1b0000,
93 0xa24, 0x090e1317,
94 0xa28, 0x00000204,
95 0xa2c, 0x00d30000,
96 0xa70, 0x101fbf00,
97 0xa74, 0x00000007,
98 0xc00, 0x40071d40,
99 0xc04, 0x03a05633,
100 0xc08, 0x001000e4,
101 0xc0c, 0x6c6c6c6c,
102 0xc10, 0x08800000,
103 0xc14, 0x40000100,
104 0xc18, 0x08800000,
105 0xc1c, 0x40000100,
106 0xc20, 0x00000000,
107 0xc24, 0x00000000,
108 0xc28, 0x00000000,
109 0xc2c, 0x00000000,
110 0xc30, 0x69e9ac44,
111 0xc34, 0x469652cf,
112 0xc38, 0x49795994,
113 0xc3c, 0x0a979718,
114 0xc40, 0x1f7c403f,
115 0xc44, 0x000100b7,
116 0xc48, 0xec020107,
117 0xc4c, 0x007f037f,
118 0xc50, 0x69543420,
119 0xc54, 0x43bc009e,
120 0xc58, 0x69543420,
121 0xc5c, 0x433c00a8,
122 0xc60, 0x00000000,
123 0xc64, 0x5116848b,
124 0xc68, 0x47c00bff,
125 0xc6c, 0x00000036,
126 0xc70, 0x2c7f000d,
127 0xc74, 0x058610db,
128 0xc78, 0x0000001f,
129 0xc7c, 0x40b95612,
130 0xc80, 0x40000100,
131 0xc84, 0x20f60000,
132 0xc88, 0x40000100,
133 0xc8c, 0x20e00000,
134 0xc90, 0x00121820,
135 0xc94, 0x00000007,
136 0xc98, 0x00121820,
137 0xc9c, 0x00007f7f,
138 0xca0, 0x00000000,
139 0xca4, 0x00000080,
140 0xca8, 0x00000000,
141 0xcac, 0x00000000,
142 0xcb0, 0x00000000,
143 0xcb4, 0x00000000,
144 0xcb8, 0x00000000,
145 0xcbc, 0x28000000,
146 0xcc0, 0x00000000,
147 0xcc4, 0x00000000,
148 0xcc8, 0x00000000,
149 0xccc, 0x00000000,
150 0xcd0, 0x00000000,
151 0xcd4, 0x00000000,
152 0xcd8, 0x64b11e20,
153 0xcdc, 0xe8767533,
154 0xce0, 0x00222222,
155 0xce4, 0x00000000,
156 0xce8, 0x37644302,
157 0xcec, 0x2f97d40c,
158 0xd00, 0x00080740,
159 0xd04, 0x00020403,
160 0xd08, 0x0000907f,
161 0xd0c, 0x20010201,
162 0xd10, 0xa0633333,
163 0xd14, 0x3333bc43,
164 0xd18, 0x7a8f5b6b,
165 0xd2c, 0xcc979975,
166 0xd30, 0x00000000,
167 0xd34, 0x80608404,
168 0xd38, 0x00000000,
169 0xd3c, 0x00027293,
170 0xd40, 0x00000000,
171 0xd44, 0x00000000,
172 0xd48, 0x00000000,
173 0xd4c, 0x00000000,
174 0xd50, 0x6437140a,
175 0xd54, 0x00000000,
176 0xd58, 0x00000000,
177 0xd5c, 0x30032064,
178 0xd60, 0x4653de68,
179 0xd64, 0x04518a3c,
180 0xd68, 0x00002101,
181 0xd6c, 0x2a201c16,
182 0xd70, 0x1812362e,
183 0xd74, 0x322c2220,
184 0xd78, 0x000e3c24,
185 0xe00, 0x2a2a2a2a,
186 0xe04, 0x2a2a2a2a,
187 0xe08, 0x03902a2a,
188 0xe10, 0x2a2a2a2a,
189 0xe14, 0x2a2a2a2a,
190 0xe18, 0x2a2a2a2a,
191 0xe1c, 0x2a2a2a2a,
192 0xe28, 0x00000000,
193 0xe30, 0x1000dc1f,
194 0xe34, 0x10008c1f,
195 0xe38, 0x02140102,
196 0xe3c, 0x681604c2,
197 0xe40, 0x01007c00,
198 0xe44, 0x01004800,
199 0xe48, 0xfb000000,
200 0xe4c, 0x000028d1,
201 0xe50, 0x1000dc1f,
202 0xe54, 0x10008c1f,
203 0xe58, 0x02140102,
204 0xe5c, 0x28160d05,
205 0xe60, 0x00000010,
206 0xe68, 0x001b25a4,
207 0xe6c, 0x63db25a4,
208 0xe70, 0x63db25a4,
209 0xe74, 0x0c126da4,
210 0xe78, 0x0c126da4,
211 0xe7c, 0x0c126da4,
212 0xe80, 0x0c126da4,
213 0xe84, 0x63db25a4,
214 0xe88, 0x0c126da4,
215 0xe8c, 0x63db25a4,
216 0xed0, 0x63db25a4,
217 0xed4, 0x63db25a4,
218 0xed8, 0x63db25a4,
219 0xedc, 0x001b25a4,
220 0xee0, 0x001b25a4,
221 0xeec, 0x6fdb25a4,
222 0xf14, 0x00000003,
223 0xf1c, 0x00000064,
224 0xf4c, 0x00000004,
225 0xf00, 0x00000300,
226};
227
228u32 rtl8192de_phy_reg_array_pg[PHY_REG_ARRAY_PG_LENGTH] = {
229 0xe00, 0xffffffff, 0x07090c0c,
230 0xe04, 0xffffffff, 0x01020405,
231 0xe08, 0x0000ff00, 0x00000000,
232 0x86c, 0xffffff00, 0x00000000,
233 0xe10, 0xffffffff, 0x0b0c0c0e,
234 0xe14, 0xffffffff, 0x01030506,
235 0xe18, 0xffffffff, 0x0b0c0d0e,
236 0xe1c, 0xffffffff, 0x01030509,
237 0x830, 0xffffffff, 0x07090c0c,
238 0x834, 0xffffffff, 0x01020405,
239 0x838, 0xffffff00, 0x00000000,
240 0x86c, 0x000000ff, 0x00000000,
241 0x83c, 0xffffffff, 0x0b0c0c0e,
242 0x848, 0xffffffff, 0x01030506,
243 0x84c, 0xffffffff, 0x0b0c0d0e,
244 0x868, 0xffffffff, 0x01030509,
245 0xe00, 0xffffffff, 0x00000000,
246 0xe04, 0xffffffff, 0x00000000,
247 0xe08, 0x0000ff00, 0x00000000,
248 0x86c, 0xffffff00, 0x00000000,
249 0xe10, 0xffffffff, 0x00000000,
250 0xe14, 0xffffffff, 0x00000000,
251 0xe18, 0xffffffff, 0x00000000,
252 0xe1c, 0xffffffff, 0x00000000,
253 0x830, 0xffffffff, 0x00000000,
254 0x834, 0xffffffff, 0x00000000,
255 0x838, 0xffffff00, 0x00000000,
256 0x86c, 0x000000ff, 0x00000000,
257 0x83c, 0xffffffff, 0x00000000,
258 0x848, 0xffffffff, 0x00000000,
259 0x84c, 0xffffffff, 0x00000000,
260 0x868, 0xffffffff, 0x00000000,
261 0xe00, 0xffffffff, 0x04040404,
262 0xe04, 0xffffffff, 0x00020204,
263 0xe08, 0x0000ff00, 0x00000000,
264 0x86c, 0xffffff00, 0x00000000,
265 0xe10, 0xffffffff, 0x06060606,
266 0xe14, 0xffffffff, 0x00020406,
267 0xe18, 0xffffffff, 0x00000000,
268 0xe1c, 0xffffffff, 0x00000000,
269 0x830, 0xffffffff, 0x04040404,
270 0x834, 0xffffffff, 0x00020204,
271 0x838, 0xffffff00, 0x00000000,
272 0x86c, 0x000000ff, 0x00000000,
273 0x83c, 0xffffffff, 0x06060606,
274 0x848, 0xffffffff, 0x00020406,
275 0x84c, 0xffffffff, 0x00000000,
276 0x868, 0xffffffff, 0x00000000,
277 0xe00, 0xffffffff, 0x00000000,
278 0xe04, 0xffffffff, 0x00000000,
279 0xe08, 0x0000ff00, 0x00000000,
280 0x86c, 0xffffff00, 0x00000000,
281 0xe10, 0xffffffff, 0x00000000,
282 0xe14, 0xffffffff, 0x00000000,
283 0xe18, 0xffffffff, 0x00000000,
284 0xe1c, 0xffffffff, 0x00000000,
285 0x830, 0xffffffff, 0x00000000,
286 0x834, 0xffffffff, 0x00000000,
287 0x838, 0xffffff00, 0x00000000,
288 0x86c, 0x000000ff, 0x00000000,
289 0x83c, 0xffffffff, 0x00000000,
290 0x848, 0xffffffff, 0x00000000,
291 0x84c, 0xffffffff, 0x00000000,
292 0x868, 0xffffffff, 0x00000000,
293 0xe00, 0xffffffff, 0x00000000,
294 0xe04, 0xffffffff, 0x00000000,
295 0xe08, 0x0000ff00, 0x00000000,
296 0x86c, 0xffffff00, 0x00000000,
297 0xe10, 0xffffffff, 0x00000000,
298 0xe14, 0xffffffff, 0x00000000,
299 0xe18, 0xffffffff, 0x00000000,
300 0xe1c, 0xffffffff, 0x00000000,
301 0x830, 0xffffffff, 0x00000000,
302 0x834, 0xffffffff, 0x00000000,
303 0x838, 0xffffff00, 0x00000000,
304 0x86c, 0x000000ff, 0x00000000,
305 0x83c, 0xffffffff, 0x00000000,
306 0x848, 0xffffffff, 0x00000000,
307 0x84c, 0xffffffff, 0x00000000,
308 0x868, 0xffffffff, 0x00000000,
309 0xe00, 0xffffffff, 0x04040404,
310 0xe04, 0xffffffff, 0x00020204,
311 0xe08, 0x0000ff00, 0x00000000,
312 0x86c, 0xffffff00, 0x00000000,
313 0xe10, 0xffffffff, 0x00000000,
314 0xe14, 0xffffffff, 0x00000000,
315 0xe18, 0xffffffff, 0x00000000,
316 0xe1c, 0xffffffff, 0x00000000,
317 0x830, 0xffffffff, 0x04040404,
318 0x834, 0xffffffff, 0x00020204,
319 0x838, 0xffffff00, 0x00000000,
320 0x86c, 0x000000ff, 0x00000000,
321 0x83c, 0xffffffff, 0x00000000,
322 0x848, 0xffffffff, 0x00000000,
323 0x84c, 0xffffffff, 0x00000000,
324 0x868, 0xffffffff, 0x00000000,
325 0xe00, 0xffffffff, 0x00000000,
326 0xe04, 0xffffffff, 0x00000000,
327 0xe08, 0x0000ff00, 0x00000000,
328 0x86c, 0xffffff00, 0x00000000,
329 0xe10, 0xffffffff, 0x00000000,
330 0xe14, 0xffffffff, 0x00000000,
331 0xe18, 0xffffffff, 0x00000000,
332 0xe1c, 0xffffffff, 0x00000000,
333 0x830, 0xffffffff, 0x00000000,
334 0x834, 0xffffffff, 0x00000000,
335 0x838, 0xffffff00, 0x00000000,
336 0x86c, 0x000000ff, 0x00000000,
337 0x83c, 0xffffffff, 0x00000000,
338 0x848, 0xffffffff, 0x00000000,
339 0x84c, 0xffffffff, 0x00000000,
340 0x868, 0xffffffff, 0x00000000,
341 0xe00, 0xffffffff, 0x04040404,
342 0xe04, 0xffffffff, 0x00020204,
343 0xe08, 0x0000ff00, 0x00000000,
344 0x86c, 0xffffff00, 0x00000000,
345 0xe10, 0xffffffff, 0x08080808,
346 0xe14, 0xffffffff, 0x00040408,
347 0xe18, 0xffffffff, 0x00000000,
348 0xe1c, 0xffffffff, 0x00000000,
349 0x830, 0xffffffff, 0x04040404,
350 0x834, 0xffffffff, 0x00020204,
351 0x838, 0xffffff00, 0x00000000,
352 0x86c, 0x000000ff, 0x00000000,
353 0x83c, 0xffffffff, 0x08080808,
354 0x848, 0xffffffff, 0x00040408,
355 0x84c, 0xffffffff, 0x00000000,
356 0x868, 0xffffffff, 0x00000000,
357 0xe00, 0xffffffff, 0x04040404,
358 0xe04, 0xffffffff, 0x00020204,
359 0xe08, 0x0000ff00, 0x00000000,
360 0x86c, 0xffffff00, 0x00000000,
361 0xe10, 0xffffffff, 0x08080808,
362 0xe14, 0xffffffff, 0x00040408,
363 0xe18, 0xffffffff, 0x00000000,
364 0xe1c, 0xffffffff, 0x00000000,
365 0x830, 0xffffffff, 0x04040404,
366 0x834, 0xffffffff, 0x00020204,
367 0x838, 0xffffff00, 0x00000000,
368 0x86c, 0x000000ff, 0x00000000,
369 0x83c, 0xffffffff, 0x08080808,
370 0x848, 0xffffffff, 0x00040408,
371 0x84c, 0xffffffff, 0x00000000,
372 0x868, 0xffffffff, 0x00000000,
373 0xe00, 0xffffffff, 0x04040404,
374 0xe04, 0xffffffff, 0x00020204,
375 0xe08, 0x0000ff00, 0x00000000,
376 0x86c, 0xffffff00, 0x00000000,
377 0xe10, 0xffffffff, 0x08080808,
378 0xe14, 0xffffffff, 0x00040408,
379 0xe18, 0xffffffff, 0x00000000,
380 0xe1c, 0xffffffff, 0x00000000,
381 0x830, 0xffffffff, 0x04040404,
382 0x834, 0xffffffff, 0x00020204,
383 0x838, 0xffffff00, 0x00000000,
384 0x86c, 0x000000ff, 0x00000000,
385 0x83c, 0xffffffff, 0x08080808,
386 0x848, 0xffffffff, 0x00040408,
387 0x84c, 0xffffffff, 0x00000000,
388 0x868, 0xffffffff, 0x00000000,
389 0xe00, 0xffffffff, 0x04040404,
390 0xe04, 0xffffffff, 0x00020204,
391 0xe08, 0x0000ff00, 0x00000000,
392 0x86c, 0xffffff00, 0x00000000,
393 0xe10, 0xffffffff, 0x08080808,
394 0xe14, 0xffffffff, 0x00040408,
395 0xe18, 0xffffffff, 0x00000000,
396 0xe1c, 0xffffffff, 0x00000000,
397 0x830, 0xffffffff, 0x04040404,
398 0x834, 0xffffffff, 0x00020204,
399 0x838, 0xffffff00, 0x00000000,
400 0x86c, 0x000000ff, 0x00000000,
401 0x83c, 0xffffffff, 0x08080808,
402 0x848, 0xffffffff, 0x00040408,
403 0x84c, 0xffffffff, 0x00000000,
404 0x868, 0xffffffff, 0x00000000,
405 0xe00, 0xffffffff, 0x04040404,
406 0xe04, 0xffffffff, 0x00020204,
407 0xe08, 0x0000ff00, 0x00000000,
408 0x86c, 0xffffff00, 0x00000000,
409 0xe10, 0xffffffff, 0x08080808,
410 0xe14, 0xffffffff, 0x00040408,
411 0xe18, 0xffffffff, 0x00000000,
412 0xe1c, 0xffffffff, 0x00000000,
413 0x830, 0xffffffff, 0x04040404,
414 0x834, 0xffffffff, 0x00020204,
415 0x838, 0xffffff00, 0x00000000,
416 0x86c, 0x000000ff, 0x00000000,
417 0x83c, 0xffffffff, 0x08080808,
418 0x848, 0xffffffff, 0x00040408,
419 0x84c, 0xffffffff, 0x00000000,
420 0x868, 0xffffffff, 0x00000000,
421 0xe00, 0xffffffff, 0x04040404,
422 0xe04, 0xffffffff, 0x00020204,
423 0xe08, 0x0000ff00, 0x00000000,
424 0x86c, 0xffffff00, 0x00000000,
425 0xe10, 0xffffffff, 0x08080808,
426 0xe14, 0xffffffff, 0x00040408,
427 0xe18, 0xffffffff, 0x00000000,
428 0xe1c, 0xffffffff, 0x00000000,
429 0x830, 0xffffffff, 0x04040404,
430 0x834, 0xffffffff, 0x00020204,
431 0x838, 0xffffff00, 0x00000000,
432 0x86c, 0x000000ff, 0x00000000,
433 0x83c, 0xffffffff, 0x08080808,
434 0x848, 0xffffffff, 0x00040408,
435 0x84c, 0xffffffff, 0x00000000,
436 0x868, 0xffffffff, 0x00000000,
437};
438
439u32 rtl8192de_radioa_2tarray[RADIOA_2T_ARRAYLENGTH] = {
440 0x000, 0x00030000,
441 0x001, 0x00030000,
442 0x002, 0x00000000,
443 0x003, 0x00018c63,
444 0x004, 0x00018c63,
445 0x008, 0x00084000,
446 0x00b, 0x0001c000,
447 0x00e, 0x00018c67,
448 0x00f, 0x00000851,
449 0x014, 0x00021440,
450 0x018, 0x00017524,
451 0x019, 0x00000000,
452 0x01d, 0x000a1290,
453 0x023, 0x00001558,
454 0x01a, 0x00030a99,
455 0x01b, 0x00040b00,
456 0x01c, 0x000fc339,
457 0x03a, 0x000a57eb,
458 0x03b, 0x00020000,
459 0x03c, 0x000ff454,
460 0x020, 0x0000aa52,
461 0x021, 0x00054000,
462 0x040, 0x0000aa52,
463 0x041, 0x00014000,
464 0x025, 0x000803be,
465 0x026, 0x000fc638,
466 0x027, 0x00077c18,
467 0x028, 0x000de471,
468 0x029, 0x000d7110,
469 0x02a, 0x0008cb04,
470 0x02b, 0x0004128b,
471 0x02c, 0x00001840,
472 0x043, 0x0002444f,
473 0x044, 0x0001adb0,
474 0x045, 0x00056467,
475 0x046, 0x0008992c,
476 0x047, 0x0000452c,
477 0x048, 0x000f9c43,
478 0x049, 0x00002e0c,
479 0x04a, 0x000546eb,
480 0x04b, 0x0008966c,
481 0x04c, 0x0000dde9,
482 0x018, 0x00007401,
483 0x000, 0x00070000,
484 0x012, 0x000dc000,
485 0x012, 0x00090000,
486 0x012, 0x00051000,
487 0x012, 0x00012000,
488 0x013, 0x000287b7,
489 0x013, 0x000247ab,
490 0x013, 0x0002079f,
491 0x013, 0x0001c793,
492 0x013, 0x0001839b,
493 0x013, 0x00014392,
494 0x013, 0x0001019a,
495 0x013, 0x0000c191,
496 0x013, 0x00008194,
497 0x013, 0x000040a0,
498 0x013, 0x00000018,
499 0x015, 0x0000f424,
500 0x015, 0x0004f424,
501 0x015, 0x0008f424,
502 0x016, 0x000e1330,
503 0x016, 0x000a1330,
504 0x016, 0x00061330,
505 0x016, 0x00021330,
506 0x018, 0x00017524,
507 0x000, 0x00070000,
508 0x012, 0x000cf000,
509 0x012, 0x000bc000,
510 0x012, 0x00078000,
511 0x012, 0x00000000,
512 0x013, 0x000287bc,
513 0x013, 0x000247b0,
514 0x013, 0x000203b4,
515 0x013, 0x0001c3a8,
516 0x013, 0x000181b4,
517 0x013, 0x000141a8,
518 0x013, 0x000100b0,
519 0x013, 0x0000c0a4,
520 0x013, 0x0000b02c,
521 0x013, 0x00004020,
522 0x013, 0x00000014,
523 0x015, 0x0000f4c3,
524 0x015, 0x0004f4c3,
525 0x015, 0x0008f4c3,
526 0x016, 0x000e085f,
527 0x016, 0x000a085f,
528 0x016, 0x0006085f,
529 0x016, 0x0002085f,
530 0x018, 0x00037524,
531 0x000, 0x00070000,
532 0x012, 0x000cf000,
533 0x012, 0x000bc000,
534 0x012, 0x00078000,
535 0x012, 0x00000000,
536 0x013, 0x000287bc,
537 0x013, 0x000247b0,
538 0x013, 0x000203b4,
539 0x013, 0x0001c3a8,
540 0x013, 0x000181b4,
541 0x013, 0x000141a8,
542 0x013, 0x000100b0,
543 0x013, 0x0000c0a4,
544 0x013, 0x0000b02c,
545 0x013, 0x00004020,
546 0x013, 0x00000014,
547 0x015, 0x0000f4c3,
548 0x015, 0x0004f4c3,
549 0x015, 0x0008f4c3,
550 0x016, 0x000e085f,
551 0x016, 0x000a085f,
552 0x016, 0x0006085f,
553 0x016, 0x0002085f,
554 0x018, 0x00057568,
555 0x000, 0x00070000,
556 0x012, 0x000cf000,
557 0x012, 0x000bc000,
558 0x012, 0x00078000,
559 0x012, 0x00000000,
560 0x013, 0x000287bc,
561 0x013, 0x000247b0,
562 0x013, 0x000203b4,
563 0x013, 0x0001c3a8,
564 0x013, 0x000181b4,
565 0x013, 0x000141a8,
566 0x013, 0x000100b0,
567 0x013, 0x0000c0a4,
568 0x013, 0x0000b02c,
569 0x013, 0x00004020,
570 0x013, 0x00000014,
571 0x015, 0x0000f4c3,
572 0x015, 0x0004f4c3,
573 0x015, 0x0008f4c3,
574 0x016, 0x000e085f,
575 0x016, 0x000a085f,
576 0x016, 0x0006085f,
577 0x016, 0x0002085f,
578 0x030, 0x0004470f,
579 0x031, 0x00044ff0,
580 0x032, 0x00000070,
581 0x033, 0x000dd480,
582 0x034, 0x000ffac0,
583 0x035, 0x000b80c0,
584 0x036, 0x00077000,
585 0x037, 0x00064ff2,
586 0x038, 0x000e7661,
587 0x039, 0x00000e90,
588 0x000, 0x00030000,
589 0x018, 0x0000f401,
590 0x0fe, 0x00000000,
591 0x0fe, 0x00000000,
592 0x01e, 0x00088009,
593 0x01f, 0x00080003,
594 0x0fe, 0x00000000,
595 0x01e, 0x00088001,
596 0x01f, 0x00080000,
597 0x0fe, 0x00000000,
598 0x018, 0x00097524,
599 0x0fe, 0x00000000,
600 0x0fe, 0x00000000,
601 0x0fe, 0x00000000,
602 0x0fe, 0x00000000,
603 0x02b, 0x00041289,
604 0x0fe, 0x00000000,
605 0x02d, 0x0006aaaa,
606 0x02e, 0x000b4d01,
607 0x02d, 0x00080000,
608 0x02e, 0x00004d02,
609 0x02d, 0x00095555,
610 0x02e, 0x00054d03,
611 0x02d, 0x000aaaaa,
612 0x02e, 0x000b4d04,
613 0x02d, 0x000c0000,
614 0x02e, 0x00004d05,
615 0x02d, 0x000d5555,
616 0x02e, 0x00054d06,
617 0x02d, 0x000eaaaa,
618 0x02e, 0x000b4d07,
619 0x02d, 0x00000000,
620 0x02e, 0x00005108,
621 0x02d, 0x00015555,
622 0x02e, 0x00055109,
623 0x02d, 0x0002aaaa,
624 0x02e, 0x000b510a,
625 0x02d, 0x00040000,
626 0x02e, 0x0000510b,
627 0x02d, 0x00055555,
628 0x02e, 0x0005510c,
629};
630
631u32 rtl8192de_radiob_2tarray[RADIOB_2T_ARRAYLENGTH] = {
632 0x000, 0x00030000,
633 0x001, 0x00030000,
634 0x002, 0x00000000,
635 0x003, 0x00018c63,
636 0x004, 0x00018c63,
637 0x008, 0x00084000,
638 0x00b, 0x0001c000,
639 0x00e, 0x00018c67,
640 0x00f, 0x00000851,
641 0x014, 0x00021440,
642 0x018, 0x00007401,
643 0x019, 0x00000060,
644 0x01d, 0x000a1290,
645 0x023, 0x00001558,
646 0x01a, 0x00030a99,
647 0x01b, 0x00040b00,
648 0x01c, 0x000fc339,
649 0x03a, 0x000a57eb,
650 0x03b, 0x00020000,
651 0x03c, 0x000ff454,
652 0x020, 0x0000aa52,
653 0x021, 0x00054000,
654 0x040, 0x0000aa52,
655 0x041, 0x00014000,
656 0x025, 0x000803be,
657 0x026, 0x000fc638,
658 0x027, 0x00077c18,
659 0x028, 0x000d1c31,
660 0x029, 0x000d7110,
661 0x02a, 0x000aeb04,
662 0x02b, 0x0004128b,
663 0x02c, 0x00001840,
664 0x043, 0x0002444f,
665 0x044, 0x0001adb0,
666 0x045, 0x00056467,
667 0x046, 0x0008992c,
668 0x047, 0x0000452c,
669 0x048, 0x000f9c43,
670 0x049, 0x00002e0c,
671 0x04a, 0x000546eb,
672 0x04b, 0x0008966c,
673 0x04c, 0x0000dde9,
674 0x018, 0x00007401,
675 0x000, 0x00070000,
676 0x012, 0x000dc000,
677 0x012, 0x00090000,
678 0x012, 0x00051000,
679 0x012, 0x00012000,
680 0x013, 0x000287b7,
681 0x013, 0x000247ab,
682 0x013, 0x0002079f,
683 0x013, 0x0001c793,
684 0x013, 0x0001839b,
685 0x013, 0x00014392,
686 0x013, 0x0001019a,
687 0x013, 0x0000c191,
688 0x013, 0x00008194,
689 0x013, 0x000040a0,
690 0x013, 0x00000018,
691 0x015, 0x0000f424,
692 0x015, 0x0004f424,
693 0x015, 0x0008f424,
694 0x016, 0x000e1330,
695 0x016, 0x000a1330,
696 0x016, 0x00061330,
697 0x016, 0x00021330,
698 0x018, 0x00017524,
699 0x000, 0x00070000,
700 0x012, 0x000cf000,
701 0x012, 0x000bc000,
702 0x012, 0x00078000,
703 0x012, 0x00000000,
704 0x013, 0x000287bc,
705 0x013, 0x000247b0,
706 0x013, 0x000203b4,
707 0x013, 0x0001c3a8,
708 0x013, 0x000181b4,
709 0x013, 0x000141a8,
710 0x013, 0x000100b0,
711 0x013, 0x0000c0a4,
712 0x013, 0x0000b02c,
713 0x013, 0x00004020,
714 0x013, 0x00000014,
715 0x015, 0x0000f4c3,
716 0x015, 0x0004f4c3,
717 0x015, 0x0008f4c3,
718 0x016, 0x000e085f,
719 0x016, 0x000a085f,
720 0x016, 0x0006085f,
721 0x016, 0x0002085f,
722 0x018, 0x00037524,
723 0x000, 0x00070000,
724 0x012, 0x000cf000,
725 0x012, 0x000bc000,
726 0x012, 0x00078000,
727 0x012, 0x00000000,
728 0x013, 0x000287bc,
729 0x013, 0x000247b0,
730 0x013, 0x000203b4,
731 0x013, 0x0001c3a8,
732 0x013, 0x000181b4,
733 0x013, 0x000141a8,
734 0x013, 0x000100b0,
735 0x013, 0x0000c0a4,
736 0x013, 0x0000b02c,
737 0x013, 0x00004020,
738 0x013, 0x00000014,
739 0x015, 0x0000f4c3,
740 0x015, 0x0004f4c3,
741 0x015, 0x0008f4c3,
742 0x016, 0x000e085f,
743 0x016, 0x000a085f,
744 0x016, 0x0006085f,
745 0x016, 0x0002085f,
746 0x018, 0x00057524,
747 0x000, 0x00070000,
748 0x012, 0x000cf000,
749 0x012, 0x000bc000,
750 0x012, 0x00078000,
751 0x012, 0x00000000,
752 0x013, 0x000287bc,
753 0x013, 0x000247b0,
754 0x013, 0x000203b4,
755 0x013, 0x0001c3a8,
756 0x013, 0x000181b4,
757 0x013, 0x000141a8,
758 0x013, 0x000100b0,
759 0x013, 0x0000c0a4,
760 0x013, 0x0000b02c,
761 0x013, 0x00004020,
762 0x013, 0x00000014,
763 0x015, 0x0000f4c3,
764 0x015, 0x0004f4c3,
765 0x015, 0x0008f4c3,
766 0x016, 0x000e085f,
767 0x016, 0x000a085f,
768 0x016, 0x0006085f,
769 0x016, 0x0002085f,
770 0x030, 0x0004470f,
771 0x031, 0x00044ff0,
772 0x032, 0x00000070,
773 0x033, 0x000dd480,
774 0x034, 0x000ffac0,
775 0x035, 0x000b80c0,
776 0x036, 0x00077000,
777 0x037, 0x00064ff2,
778 0x038, 0x000e7661,
779 0x039, 0x00000e90,
780 0x000, 0x00030000,
781 0x018, 0x0000f401,
782 0x0fe, 0x00000000,
783 0x0fe, 0x00000000,
784 0x01e, 0x00088009,
785 0x01f, 0x00080003,
786 0x0fe, 0x00000000,
787 0x01e, 0x00088001,
788 0x01f, 0x00080000,
789 0x0fe, 0x00000000,
790 0x018, 0x00087401,
791 0x0fe, 0x00000000,
792 0x0fe, 0x00000000,
793 0x0fe, 0x00000000,
794 0x02b, 0x00041289,
795 0x0fe, 0x00000000,
796 0x02d, 0x00066666,
797 0x02e, 0x00064001,
798 0x02d, 0x00091111,
799 0x02e, 0x00014002,
800 0x02d, 0x000bbbbb,
801 0x02e, 0x000b4003,
802 0x02d, 0x000e6666,
803 0x02e, 0x00064004,
804 0x02d, 0x00088888,
805 0x02e, 0x00084005,
806 0x02d, 0x0009dddd,
807 0x02e, 0x000d4006,
808 0x02d, 0x000b3333,
809 0x02e, 0x00034007,
810 0x02d, 0x00048888,
811 0x02e, 0x00084408,
812 0x02d, 0x000bbbbb,
813 0x02e, 0x000b4409,
814 0x02d, 0x000e6666,
815 0x02e, 0x0006440a,
816 0x02d, 0x00011111,
817 0x02e, 0x0001480b,
818 0x02d, 0x0003bbbb,
819 0x02e, 0x000b480c,
820 0x02d, 0x00066666,
821 0x02e, 0x0006480d,
822 0x02d, 0x000ccccc,
823 0x02e, 0x000c480e,
824};
825
826u32 rtl8192de_radioa_2t_int_paarray[RADIOA_2T_INT_PA_ARRAYLENGTH] = {
827 0x000, 0x00030000,
828 0x001, 0x00030000,
829 0x002, 0x00000000,
830 0x003, 0x00018c63,
831 0x004, 0x00018c63,
832 0x008, 0x00084000,
833 0x00b, 0x0001c000,
834 0x00e, 0x00018c67,
835 0x00f, 0x00000851,
836 0x014, 0x00021440,
837 0x018, 0x00017524,
838 0x019, 0x00000000,
839 0x01d, 0x000a1290,
840 0x023, 0x00001558,
841 0x01a, 0x00030a99,
842 0x01b, 0x00040b00,
843 0x01c, 0x000fc339,
844 0x03a, 0x000a57eb,
845 0x03b, 0x00020000,
846 0x03c, 0x000ff454,
847 0x020, 0x0000aa52,
848 0x021, 0x00054000,
849 0x040, 0x0000aa52,
850 0x041, 0x00014000,
851 0x025, 0x000803be,
852 0x026, 0x000fc638,
853 0x027, 0x00077c18,
854 0x028, 0x000de471,
855 0x029, 0x000d7110,
856 0x02a, 0x0008eb04,
857 0x02b, 0x0004128b,
858 0x02c, 0x00001840,
859 0x043, 0x0002444f,
860 0x044, 0x0001adb0,
861 0x045, 0x00056467,
862 0x046, 0x0008992c,
863 0x047, 0x0000452c,
864 0x048, 0x000c0443,
865 0x049, 0x00000730,
866 0x04a, 0x00050f0f,
867 0x04b, 0x000896ee,
868 0x04c, 0x0000ddee,
869 0x018, 0x00007401,
870 0x000, 0x00070000,
871 0x012, 0x000dc000,
872 0x012, 0x00090000,
873 0x012, 0x00051000,
874 0x012, 0x00012000,
875 0x013, 0x000287b7,
876 0x013, 0x000247ab,
877 0x013, 0x0002079f,
878 0x013, 0x0001c793,
879 0x013, 0x0001839b,
880 0x013, 0x00014392,
881 0x013, 0x0001019a,
882 0x013, 0x0000c191,
883 0x013, 0x00008194,
884 0x013, 0x000040a0,
885 0x013, 0x00000018,
886 0x015, 0x0000f424,
887 0x015, 0x0004f424,
888 0x015, 0x0008f424,
889 0x016, 0x000e1330,
890 0x016, 0x000a1330,
891 0x016, 0x00061330,
892 0x016, 0x00021330,
893 0x018, 0x00017524,
894 0x000, 0x00070000,
895 0x012, 0x000cf000,
896 0x012, 0x000bc000,
897 0x012, 0x00078000,
898 0x012, 0x00000000,
899 0x013, 0x000287bf,
900 0x013, 0x000247b3,
901 0x013, 0x000207a7,
902 0x013, 0x0001c79b,
903 0x013, 0x0001839f,
904 0x013, 0x00014393,
905 0x013, 0x00010399,
906 0x013, 0x0000c38d,
907 0x013, 0x00008199,
908 0x013, 0x0000418d,
909 0x013, 0x00000099,
910 0x015, 0x0000f495,
911 0x015, 0x0004f495,
912 0x015, 0x0008f495,
913 0x016, 0x000e1874,
914 0x016, 0x000a1874,
915 0x016, 0x00061874,
916 0x016, 0x00021874,
917 0x018, 0x00037564,
918 0x000, 0x00070000,
919 0x012, 0x000cf000,
920 0x012, 0x000bc000,
921 0x012, 0x00078000,
922 0x012, 0x00000000,
923 0x013, 0x000287bf,
924 0x013, 0x000247b3,
925 0x013, 0x000207a7,
926 0x013, 0x0001c79b,
927 0x013, 0x0001839f,
928 0x013, 0x00014393,
929 0x013, 0x00010399,
930 0x013, 0x0000c38d,
931 0x013, 0x00008199,
932 0x013, 0x0000418d,
933 0x013, 0x00000099,
934 0x015, 0x0000f495,
935 0x015, 0x0004f495,
936 0x015, 0x0008f495,
937 0x016, 0x000e1874,
938 0x016, 0x000a1874,
939 0x016, 0x00061874,
940 0x016, 0x00021874,
941 0x018, 0x00057595,
942 0x000, 0x00070000,
943 0x012, 0x000cf000,
944 0x012, 0x000bc000,
945 0x012, 0x00078000,
946 0x012, 0x00000000,
947 0x013, 0x000287bf,
948 0x013, 0x000247b3,
949 0x013, 0x000207a7,
950 0x013, 0x0001c79b,
951 0x013, 0x0001839f,
952 0x013, 0x00014393,
953 0x013, 0x00010399,
954 0x013, 0x0000c38d,
955 0x013, 0x00008199,
956 0x013, 0x0000418d,
957 0x013, 0x00000099,
958 0x015, 0x0000f495,
959 0x015, 0x0004f495,
960 0x015, 0x0008f495,
961 0x016, 0x000e1874,
962 0x016, 0x000a1874,
963 0x016, 0x00061874,
964 0x016, 0x00021874,
965 0x030, 0x0004470f,
966 0x031, 0x00044ff0,
967 0x032, 0x00000070,
968 0x033, 0x000dd480,
969 0x034, 0x000ffac0,
970 0x035, 0x000b80c0,
971 0x036, 0x00077000,
972 0x037, 0x00064ff2,
973 0x038, 0x000e7661,
974 0x039, 0x00000e90,
975 0x000, 0x00030000,
976 0x018, 0x0000f401,
977 0x0fe, 0x00000000,
978 0x0fe, 0x00000000,
979 0x01e, 0x00088009,
980 0x01f, 0x00080003,
981 0x0fe, 0x00000000,
982 0x01e, 0x00088001,
983 0x01f, 0x00080000,
984 0x0fe, 0x00000000,
985 0x018, 0x00097524,
986 0x0fe, 0x00000000,
987 0x0fe, 0x00000000,
988 0x0fe, 0x00000000,
989 0x0fe, 0x00000000,
990 0x02b, 0x00041289,
991 0x0fe, 0x00000000,
992 0x02d, 0x0006aaaa,
993 0x02e, 0x000b4d01,
994 0x02d, 0x00080000,
995 0x02e, 0x00004d02,
996 0x02d, 0x00095555,
997 0x02e, 0x00054d03,
998 0x02d, 0x000aaaaa,
999 0x02e, 0x000b4d04,
1000 0x02d, 0x000c0000,
1001 0x02e, 0x00004d05,
1002 0x02d, 0x000d5555,
1003 0x02e, 0x00054d06,
1004 0x02d, 0x000eaaaa,
1005 0x02e, 0x000b4d07,
1006 0x02d, 0x00000000,
1007 0x02e, 0x00005108,
1008 0x02d, 0x00015555,
1009 0x02e, 0x00055109,
1010 0x02d, 0x0002aaaa,
1011 0x02e, 0x000b510a,
1012 0x02d, 0x00040000,
1013 0x02e, 0x0000510b,
1014 0x02d, 0x00055555,
1015 0x02e, 0x0005510c,
1016};
1017
1018u32 rtl8192de_radiob_2t_int_paarray[RADIOB_2T_INT_PA_ARRAYLENGTH] = {
1019 0x000, 0x00030000,
1020 0x001, 0x00030000,
1021 0x002, 0x00000000,
1022 0x003, 0x00018c63,
1023 0x004, 0x00018c63,
1024 0x008, 0x00084000,
1025 0x00b, 0x0001c000,
1026 0x00e, 0x00018c67,
1027 0x00f, 0x00000851,
1028 0x014, 0x00021440,
1029 0x018, 0x00007401,
1030 0x019, 0x00000060,
1031 0x01d, 0x000a1290,
1032 0x023, 0x00001558,
1033 0x01a, 0x00030a99,
1034 0x01b, 0x00040b00,
1035 0x01c, 0x000fc339,
1036 0x03a, 0x000a57eb,
1037 0x03b, 0x00020000,
1038 0x03c, 0x000ff454,
1039 0x020, 0x0000aa52,
1040 0x021, 0x00054000,
1041 0x040, 0x0000aa52,
1042 0x041, 0x00014000,
1043 0x025, 0x000803be,
1044 0x026, 0x000fc638,
1045 0x027, 0x00077c18,
1046 0x028, 0x000d1c31,
1047 0x029, 0x000d7110,
1048 0x02a, 0x000aeb04,
1049 0x02b, 0x0004128b,
1050 0x02c, 0x00001840,
1051 0x043, 0x0002444f,
1052 0x044, 0x0001adb0,
1053 0x045, 0x00056467,
1054 0x046, 0x0008992c,
1055 0x047, 0x0000452c,
1056 0x048, 0x000c0443,
1057 0x049, 0x00000730,
1058 0x04a, 0x00050f0f,
1059 0x04b, 0x000896ee,
1060 0x04c, 0x0000ddee,
1061 0x018, 0x00007401,
1062 0x000, 0x00070000,
1063 0x012, 0x000dc000,
1064 0x012, 0x00090000,
1065 0x012, 0x00051000,
1066 0x012, 0x00012000,
1067 0x013, 0x000287b7,
1068 0x013, 0x000247ab,
1069 0x013, 0x0002079f,
1070 0x013, 0x0001c793,
1071 0x013, 0x0001839b,
1072 0x013, 0x00014392,
1073 0x013, 0x0001019a,
1074 0x013, 0x0000c191,
1075 0x013, 0x00008194,
1076 0x013, 0x000040a0,
1077 0x013, 0x00000018,
1078 0x015, 0x0000f424,
1079 0x015, 0x0004f424,
1080 0x015, 0x0008f424,
1081 0x016, 0x000e1330,
1082 0x016, 0x000a1330,
1083 0x016, 0x00061330,
1084 0x016, 0x00021330,
1085 0x018, 0x00017524,
1086 0x000, 0x00070000,
1087 0x012, 0x000cf000,
1088 0x012, 0x000bc000,
1089 0x012, 0x00078000,
1090 0x012, 0x00000000,
1091 0x013, 0x000287bf,
1092 0x013, 0x000247b3,
1093 0x013, 0x000207a7,
1094 0x013, 0x0001c79b,
1095 0x013, 0x0001839f,
1096 0x013, 0x00014393,
1097 0x013, 0x00010399,
1098 0x013, 0x0000c38d,
1099 0x013, 0x00008199,
1100 0x013, 0x0000418d,
1101 0x013, 0x00000099,
1102 0x015, 0x0000f495,
1103 0x015, 0x0004f495,
1104 0x015, 0x0008f495,
1105 0x016, 0x000e1874,
1106 0x016, 0x000a1874,
1107 0x016, 0x00061874,
1108 0x016, 0x00021874,
1109 0x018, 0x00037564,
1110 0x000, 0x00070000,
1111 0x012, 0x000cf000,
1112 0x012, 0x000bc000,
1113 0x012, 0x00078000,
1114 0x012, 0x00000000,
1115 0x013, 0x000287bf,
1116 0x013, 0x000247b3,
1117 0x013, 0x000207a7,
1118 0x013, 0x0001c79b,
1119 0x013, 0x0001839f,
1120 0x013, 0x00014393,
1121 0x013, 0x00010399,
1122 0x013, 0x0000c38d,
1123 0x013, 0x00008199,
1124 0x013, 0x0000418d,
1125 0x013, 0x00000099,
1126 0x015, 0x0000f495,
1127 0x015, 0x0004f495,
1128 0x015, 0x0008f495,
1129 0x016, 0x000e1874,
1130 0x016, 0x000a1874,
1131 0x016, 0x00061874,
1132 0x016, 0x00021874,
1133 0x018, 0x00057595,
1134 0x000, 0x00070000,
1135 0x012, 0x000cf000,
1136 0x012, 0x000bc000,
1137 0x012, 0x00078000,
1138 0x012, 0x00000000,
1139 0x013, 0x000287bf,
1140 0x013, 0x000247b3,
1141 0x013, 0x000207a7,
1142 0x013, 0x0001c79b,
1143 0x013, 0x0001839f,
1144 0x013, 0x00014393,
1145 0x013, 0x00010399,
1146 0x013, 0x0000c38d,
1147 0x013, 0x00008199,
1148 0x013, 0x0000418d,
1149 0x013, 0x00000099,
1150 0x015, 0x0000f495,
1151 0x015, 0x0004f495,
1152 0x015, 0x0008f495,
1153 0x016, 0x000e1874,
1154 0x016, 0x000a1874,
1155 0x016, 0x00061874,
1156 0x016, 0x00021874,
1157 0x030, 0x0004470f,
1158 0x031, 0x00044ff0,
1159 0x032, 0x00000070,
1160 0x033, 0x000dd480,
1161 0x034, 0x000ffac0,
1162 0x035, 0x000b80c0,
1163 0x036, 0x00077000,
1164 0x037, 0x00064ff2,
1165 0x038, 0x000e7661,
1166 0x039, 0x00000e90,
1167 0x000, 0x00030000,
1168 0x018, 0x0000f401,
1169 0x0fe, 0x00000000,
1170 0x0fe, 0x00000000,
1171 0x01e, 0x00088009,
1172 0x01f, 0x00080003,
1173 0x0fe, 0x00000000,
1174 0x01e, 0x00088001,
1175 0x01f, 0x00080000,
1176 0x0fe, 0x00000000,
1177 0x018, 0x00087401,
1178 0x0fe, 0x00000000,
1179 0x0fe, 0x00000000,
1180 0x0fe, 0x00000000,
1181 0x02b, 0x00041289,
1182 0x0fe, 0x00000000,
1183 0x02d, 0x00066666,
1184 0x02e, 0x00064001,
1185 0x02d, 0x00091111,
1186 0x02e, 0x00014002,
1187 0x02d, 0x000bbbbb,
1188 0x02e, 0x000b4003,
1189 0x02d, 0x000e6666,
1190 0x02e, 0x00064004,
1191 0x02d, 0x00088888,
1192 0x02e, 0x00084005,
1193 0x02d, 0x0009dddd,
1194 0x02e, 0x000d4006,
1195 0x02d, 0x000b3333,
1196 0x02e, 0x00034007,
1197 0x02d, 0x00048888,
1198 0x02e, 0x00084408,
1199 0x02d, 0x000bbbbb,
1200 0x02e, 0x000b4409,
1201 0x02d, 0x000e6666,
1202 0x02e, 0x0006440a,
1203 0x02d, 0x00011111,
1204 0x02e, 0x0001480b,
1205 0x02d, 0x0003bbbb,
1206 0x02e, 0x000b480c,
1207 0x02d, 0x00066666,
1208 0x02e, 0x0006480d,
1209 0x02d, 0x000ccccc,
1210 0x02e, 0x000c480e,
1211};
1212
1213u32 rtl8192de_mac_2tarray[MAC_2T_ARRAYLENGTH] = {
1214 0x420, 0x00000080,
1215 0x423, 0x00000000,
1216 0x430, 0x00000000,
1217 0x431, 0x00000000,
1218 0x432, 0x00000000,
1219 0x433, 0x00000001,
1220 0x434, 0x00000004,
1221 0x435, 0x00000005,
1222 0x436, 0x00000006,
1223 0x437, 0x00000007,
1224 0x438, 0x00000000,
1225 0x439, 0x00000000,
1226 0x43a, 0x00000000,
1227 0x43b, 0x00000001,
1228 0x43c, 0x00000004,
1229 0x43d, 0x00000005,
1230 0x43e, 0x00000006,
1231 0x43f, 0x00000007,
1232 0x440, 0x00000050,
1233 0x441, 0x00000001,
1234 0x442, 0x00000000,
1235 0x444, 0x00000015,
1236 0x445, 0x000000f0,
1237 0x446, 0x0000000f,
1238 0x447, 0x00000000,
1239 0x462, 0x00000008,
1240 0x463, 0x00000003,
1241 0x4c8, 0x000000ff,
1242 0x4c9, 0x00000008,
1243 0x4cc, 0x000000ff,
1244 0x4cd, 0x000000ff,
1245 0x4ce, 0x00000001,
1246 0x500, 0x00000026,
1247 0x501, 0x000000a2,
1248 0x502, 0x0000002f,
1249 0x503, 0x00000000,
1250 0x504, 0x00000028,
1251 0x505, 0x000000a3,
1252 0x506, 0x0000005e,
1253 0x507, 0x00000000,
1254 0x508, 0x0000002b,
1255 0x509, 0x000000a4,
1256 0x50a, 0x0000005e,
1257 0x50b, 0x00000000,
1258 0x50c, 0x0000004f,
1259 0x50d, 0x000000a4,
1260 0x50e, 0x00000000,
1261 0x50f, 0x00000000,
1262 0x512, 0x0000001c,
1263 0x514, 0x0000000a,
1264 0x515, 0x00000010,
1265 0x516, 0x0000000a,
1266 0x517, 0x00000010,
1267 0x51a, 0x00000016,
1268 0x524, 0x0000000f,
1269 0x525, 0x0000004f,
1270 0x546, 0x00000040,
1271 0x547, 0x00000000,
1272 0x550, 0x00000010,
1273 0x551, 0x00000010,
1274 0x559, 0x00000002,
1275 0x55a, 0x00000002,
1276 0x55d, 0x000000ff,
1277 0x605, 0x00000030,
1278 0x608, 0x0000000e,
1279 0x609, 0x0000002a,
1280 0x652, 0x00000020,
1281 0x63c, 0x0000000a,
1282 0x63d, 0x0000000a,
1283 0x63e, 0x0000000e,
1284 0x63f, 0x0000000e,
1285 0x66e, 0x00000005,
1286 0x700, 0x00000021,
1287 0x701, 0x00000043,
1288 0x702, 0x00000065,
1289 0x703, 0x00000087,
1290 0x708, 0x00000021,
1291 0x709, 0x00000043,
1292 0x70a, 0x00000065,
1293 0x70b, 0x00000087,
1294};
1295
1296u32 rtl8192de_agctab_array[AGCTAB_ARRAYLENGTH] = {
1297 0xc78, 0x7b000001,
1298 0xc78, 0x7b010001,
1299 0xc78, 0x7b020001,
1300 0xc78, 0x7b030001,
1301 0xc78, 0x7b040001,
1302 0xc78, 0x7b050001,
1303 0xc78, 0x7b060001,
1304 0xc78, 0x7a070001,
1305 0xc78, 0x79080001,
1306 0xc78, 0x78090001,
1307 0xc78, 0x770a0001,
1308 0xc78, 0x760b0001,
1309 0xc78, 0x750c0001,
1310 0xc78, 0x740d0001,
1311 0xc78, 0x730e0001,
1312 0xc78, 0x720f0001,
1313 0xc78, 0x71100001,
1314 0xc78, 0x70110001,
1315 0xc78, 0x6f120001,
1316 0xc78, 0x6e130001,
1317 0xc78, 0x6d140001,
1318 0xc78, 0x6c150001,
1319 0xc78, 0x6b160001,
1320 0xc78, 0x6a170001,
1321 0xc78, 0x69180001,
1322 0xc78, 0x68190001,
1323 0xc78, 0x671a0001,
1324 0xc78, 0x661b0001,
1325 0xc78, 0x651c0001,
1326 0xc78, 0x641d0001,
1327 0xc78, 0x631e0001,
1328 0xc78, 0x621f0001,
1329 0xc78, 0x61200001,
1330 0xc78, 0x60210001,
1331 0xc78, 0x49220001,
1332 0xc78, 0x48230001,
1333 0xc78, 0x47240001,
1334 0xc78, 0x46250001,
1335 0xc78, 0x45260001,
1336 0xc78, 0x44270001,
1337 0xc78, 0x43280001,
1338 0xc78, 0x42290001,
1339 0xc78, 0x412a0001,
1340 0xc78, 0x402b0001,
1341 0xc78, 0x262c0001,
1342 0xc78, 0x252d0001,
1343 0xc78, 0x242e0001,
1344 0xc78, 0x232f0001,
1345 0xc78, 0x22300001,
1346 0xc78, 0x21310001,
1347 0xc78, 0x20320001,
1348 0xc78, 0x06330001,
1349 0xc78, 0x05340001,
1350 0xc78, 0x04350001,
1351 0xc78, 0x03360001,
1352 0xc78, 0x02370001,
1353 0xc78, 0x01380001,
1354 0xc78, 0x00390001,
1355 0xc78, 0x003a0001,
1356 0xc78, 0x003b0001,
1357 0xc78, 0x003c0001,
1358 0xc78, 0x003d0001,
1359 0xc78, 0x003e0001,
1360 0xc78, 0x003f0001,
1361 0xc78, 0x7b400001,
1362 0xc78, 0x7b410001,
1363 0xc78, 0x7a420001,
1364 0xc78, 0x79430001,
1365 0xc78, 0x78440001,
1366 0xc78, 0x77450001,
1367 0xc78, 0x76460001,
1368 0xc78, 0x75470001,
1369 0xc78, 0x74480001,
1370 0xc78, 0x73490001,
1371 0xc78, 0x724a0001,
1372 0xc78, 0x714b0001,
1373 0xc78, 0x704c0001,
1374 0xc78, 0x6f4d0001,
1375 0xc78, 0x6e4e0001,
1376 0xc78, 0x6d4f0001,
1377 0xc78, 0x6c500001,
1378 0xc78, 0x6b510001,
1379 0xc78, 0x6a520001,
1380 0xc78, 0x69530001,
1381 0xc78, 0x68540001,
1382 0xc78, 0x67550001,
1383 0xc78, 0x66560001,
1384 0xc78, 0x65570001,
1385 0xc78, 0x64580001,
1386 0xc78, 0x63590001,
1387 0xc78, 0x625a0001,
1388 0xc78, 0x615b0001,
1389 0xc78, 0x605c0001,
1390 0xc78, 0x485d0001,
1391 0xc78, 0x475e0001,
1392 0xc78, 0x465f0001,
1393 0xc78, 0x45600001,
1394 0xc78, 0x44610001,
1395 0xc78, 0x43620001,
1396 0xc78, 0x42630001,
1397 0xc78, 0x41640001,
1398 0xc78, 0x40650001,
1399 0xc78, 0x27660001,
1400 0xc78, 0x26670001,
1401 0xc78, 0x25680001,
1402 0xc78, 0x24690001,
1403 0xc78, 0x236a0001,
1404 0xc78, 0x226b0001,
1405 0xc78, 0x216c0001,
1406 0xc78, 0x206d0001,
1407 0xc78, 0x206e0001,
1408 0xc78, 0x206f0001,
1409 0xc78, 0x20700001,
1410 0xc78, 0x20710001,
1411 0xc78, 0x20720001,
1412 0xc78, 0x20730001,
1413 0xc78, 0x20740001,
1414 0xc78, 0x20750001,
1415 0xc78, 0x20760001,
1416 0xc78, 0x20770001,
1417 0xc78, 0x20780001,
1418 0xc78, 0x20790001,
1419 0xc78, 0x207a0001,
1420 0xc78, 0x207b0001,
1421 0xc78, 0x207c0001,
1422 0xc78, 0x207d0001,
1423 0xc78, 0x207e0001,
1424 0xc78, 0x207f0001,
1425 0xc78, 0x38000002,
1426 0xc78, 0x38010002,
1427 0xc78, 0x38020002,
1428 0xc78, 0x38030002,
1429 0xc78, 0x38040002,
1430 0xc78, 0x38050002,
1431 0xc78, 0x38060002,
1432 0xc78, 0x38070002,
1433 0xc78, 0x38080002,
1434 0xc78, 0x3c090002,
1435 0xc78, 0x3e0a0002,
1436 0xc78, 0x400b0002,
1437 0xc78, 0x440c0002,
1438 0xc78, 0x480d0002,
1439 0xc78, 0x4c0e0002,
1440 0xc78, 0x500f0002,
1441 0xc78, 0x52100002,
1442 0xc78, 0x56110002,
1443 0xc78, 0x5a120002,
1444 0xc78, 0x5e130002,
1445 0xc78, 0x60140002,
1446 0xc78, 0x60150002,
1447 0xc78, 0x60160002,
1448 0xc78, 0x62170002,
1449 0xc78, 0x62180002,
1450 0xc78, 0x62190002,
1451 0xc78, 0x621a0002,
1452 0xc78, 0x621b0002,
1453 0xc78, 0x621c0002,
1454 0xc78, 0x621d0002,
1455 0xc78, 0x621e0002,
1456 0xc78, 0x621f0002,
1457 0xc78, 0x32000044,
1458 0xc78, 0x32010044,
1459 0xc78, 0x32020044,
1460 0xc78, 0x32030044,
1461 0xc78, 0x32040044,
1462 0xc78, 0x32050044,
1463 0xc78, 0x32060044,
1464 0xc78, 0x32070044,
1465 0xc78, 0x32080044,
1466 0xc78, 0x34090044,
1467 0xc78, 0x350a0044,
1468 0xc78, 0x360b0044,
1469 0xc78, 0x370c0044,
1470 0xc78, 0x380d0044,
1471 0xc78, 0x390e0044,
1472 0xc78, 0x3a0f0044,
1473 0xc78, 0x3e100044,
1474 0xc78, 0x42110044,
1475 0xc78, 0x44120044,
1476 0xc78, 0x46130044,
1477 0xc78, 0x4a140044,
1478 0xc78, 0x4e150044,
1479 0xc78, 0x50160044,
1480 0xc78, 0x55170044,
1481 0xc78, 0x5a180044,
1482 0xc78, 0x5e190044,
1483 0xc78, 0x641a0044,
1484 0xc78, 0x6e1b0044,
1485 0xc78, 0x6e1c0044,
1486 0xc78, 0x6e1d0044,
1487 0xc78, 0x6e1e0044,
1488 0xc78, 0x6e1f0044,
1489 0xc78, 0x6e1f0000,
1490};
1491
1492u32 rtl8192de_agctab_5garray[AGCTAB_5G_ARRAYLENGTH] = {
1493 0xc78, 0x7b000001,
1494 0xc78, 0x7b010001,
1495 0xc78, 0x7a020001,
1496 0xc78, 0x79030001,
1497 0xc78, 0x78040001,
1498 0xc78, 0x77050001,
1499 0xc78, 0x76060001,
1500 0xc78, 0x75070001,
1501 0xc78, 0x74080001,
1502 0xc78, 0x73090001,
1503 0xc78, 0x720a0001,
1504 0xc78, 0x710b0001,
1505 0xc78, 0x700c0001,
1506 0xc78, 0x6f0d0001,
1507 0xc78, 0x6e0e0001,
1508 0xc78, 0x6d0f0001,
1509 0xc78, 0x6c100001,
1510 0xc78, 0x6b110001,
1511 0xc78, 0x6a120001,
1512 0xc78, 0x69130001,
1513 0xc78, 0x68140001,
1514 0xc78, 0x67150001,
1515 0xc78, 0x66160001,
1516 0xc78, 0x65170001,
1517 0xc78, 0x64180001,
1518 0xc78, 0x63190001,
1519 0xc78, 0x621a0001,
1520 0xc78, 0x611b0001,
1521 0xc78, 0x601c0001,
1522 0xc78, 0x481d0001,
1523 0xc78, 0x471e0001,
1524 0xc78, 0x461f0001,
1525 0xc78, 0x45200001,
1526 0xc78, 0x44210001,
1527 0xc78, 0x43220001,
1528 0xc78, 0x42230001,
1529 0xc78, 0x41240001,
1530 0xc78, 0x40250001,
1531 0xc78, 0x27260001,
1532 0xc78, 0x26270001,
1533 0xc78, 0x25280001,
1534 0xc78, 0x24290001,
1535 0xc78, 0x232a0001,
1536 0xc78, 0x222b0001,
1537 0xc78, 0x212c0001,
1538 0xc78, 0x202d0001,
1539 0xc78, 0x202e0001,
1540 0xc78, 0x202f0001,
1541 0xc78, 0x20300001,
1542 0xc78, 0x20310001,
1543 0xc78, 0x20320001,
1544 0xc78, 0x20330001,
1545 0xc78, 0x20340001,
1546 0xc78, 0x20350001,
1547 0xc78, 0x20360001,
1548 0xc78, 0x20370001,
1549 0xc78, 0x20380001,
1550 0xc78, 0x20390001,
1551 0xc78, 0x203a0001,
1552 0xc78, 0x203b0001,
1553 0xc78, 0x203c0001,
1554 0xc78, 0x203d0001,
1555 0xc78, 0x203e0001,
1556 0xc78, 0x203f0001,
1557 0xc78, 0x32000044,
1558 0xc78, 0x32010044,
1559 0xc78, 0x32020044,
1560 0xc78, 0x32030044,
1561 0xc78, 0x32040044,
1562 0xc78, 0x32050044,
1563 0xc78, 0x32060044,
1564 0xc78, 0x32070044,
1565 0xc78, 0x32080044,
1566 0xc78, 0x34090044,
1567 0xc78, 0x350a0044,
1568 0xc78, 0x360b0044,
1569 0xc78, 0x370c0044,
1570 0xc78, 0x380d0044,
1571 0xc78, 0x390e0044,
1572 0xc78, 0x3a0f0044,
1573 0xc78, 0x3e100044,
1574 0xc78, 0x42110044,
1575 0xc78, 0x44120044,
1576 0xc78, 0x46130044,
1577 0xc78, 0x4a140044,
1578 0xc78, 0x4e150044,
1579 0xc78, 0x50160044,
1580 0xc78, 0x55170044,
1581 0xc78, 0x5a180044,
1582 0xc78, 0x5e190044,
1583 0xc78, 0x641a0044,
1584 0xc78, 0x6e1b0044,
1585 0xc78, 0x6e1c0044,
1586 0xc78, 0x6e1d0044,
1587 0xc78, 0x6e1e0044,
1588 0xc78, 0x6e1f0044,
1589 0xc78, 0x6e1f0000,
1590};
1591
1592u32 rtl8192de_agctab_2garray[AGCTAB_2G_ARRAYLENGTH] = {
1593 0xc78, 0x7b000001,
1594 0xc78, 0x7b010001,
1595 0xc78, 0x7b020001,
1596 0xc78, 0x7b030001,
1597 0xc78, 0x7b040001,
1598 0xc78, 0x7b050001,
1599 0xc78, 0x7b060001,
1600 0xc78, 0x7a070001,
1601 0xc78, 0x79080001,
1602 0xc78, 0x78090001,
1603 0xc78, 0x770a0001,
1604 0xc78, 0x760b0001,
1605 0xc78, 0x750c0001,
1606 0xc78, 0x740d0001,
1607 0xc78, 0x730e0001,
1608 0xc78, 0x720f0001,
1609 0xc78, 0x71100001,
1610 0xc78, 0x70110001,
1611 0xc78, 0x6f120001,
1612 0xc78, 0x6e130001,
1613 0xc78, 0x6d140001,
1614 0xc78, 0x6c150001,
1615 0xc78, 0x6b160001,
1616 0xc78, 0x6a170001,
1617 0xc78, 0x69180001,
1618 0xc78, 0x68190001,
1619 0xc78, 0x671a0001,
1620 0xc78, 0x661b0001,
1621 0xc78, 0x651c0001,
1622 0xc78, 0x641d0001,
1623 0xc78, 0x631e0001,
1624 0xc78, 0x621f0001,
1625 0xc78, 0x61200001,
1626 0xc78, 0x60210001,
1627 0xc78, 0x49220001,
1628 0xc78, 0x48230001,
1629 0xc78, 0x47240001,
1630 0xc78, 0x46250001,
1631 0xc78, 0x45260001,
1632 0xc78, 0x44270001,
1633 0xc78, 0x43280001,
1634 0xc78, 0x42290001,
1635 0xc78, 0x412a0001,
1636 0xc78, 0x402b0001,
1637 0xc78, 0x262c0001,
1638 0xc78, 0x252d0001,
1639 0xc78, 0x242e0001,
1640 0xc78, 0x232f0001,
1641 0xc78, 0x22300001,
1642 0xc78, 0x21310001,
1643 0xc78, 0x20320001,
1644 0xc78, 0x06330001,
1645 0xc78, 0x05340001,
1646 0xc78, 0x04350001,
1647 0xc78, 0x03360001,
1648 0xc78, 0x02370001,
1649 0xc78, 0x01380001,
1650 0xc78, 0x00390001,
1651 0xc78, 0x003a0001,
1652 0xc78, 0x003b0001,
1653 0xc78, 0x003c0001,
1654 0xc78, 0x003d0001,
1655 0xc78, 0x003e0001,
1656 0xc78, 0x003f0001,
1657 0xc78, 0x38000002,
1658 0xc78, 0x38010002,
1659 0xc78, 0x38020002,
1660 0xc78, 0x38030002,
1661 0xc78, 0x38040002,
1662 0xc78, 0x38050002,
1663 0xc78, 0x38060002,
1664 0xc78, 0x38070002,
1665 0xc78, 0x38080002,
1666 0xc78, 0x3c090002,
1667 0xc78, 0x3e0a0002,
1668 0xc78, 0x400b0002,
1669 0xc78, 0x440c0002,
1670 0xc78, 0x480d0002,
1671 0xc78, 0x4c0e0002,
1672 0xc78, 0x500f0002,
1673 0xc78, 0x52100002,
1674 0xc78, 0x56110002,
1675 0xc78, 0x5a120002,
1676 0xc78, 0x5e130002,
1677 0xc78, 0x60140002,
1678 0xc78, 0x60150002,
1679 0xc78, 0x60160002,
1680 0xc78, 0x62170002,
1681 0xc78, 0x62180002,
1682 0xc78, 0x62190002,
1683 0xc78, 0x621a0002,
1684 0xc78, 0x621b0002,
1685 0xc78, 0x621c0002,
1686 0xc78, 0x621d0002,
1687 0xc78, 0x621e0002,
1688 0xc78, 0x621f0002,
1689 0xc78, 0x6e1f0000,
1690};
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/table.h b/drivers/net/wireless/rtlwifi/rtl8192de/table.h
new file mode 100644
index 000000000000..93f30ca62d8f
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/table.h
@@ -0,0 +1,57 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 * Created on 2010/ 5/18, 1:41
29 *****************************************************************************/
30
31#ifndef __RTL92DE_TABLE__H_
32#define __RTL92DE_TABLE__H_
33
34/*Created on 2011/ 1/14, 1:35*/
35
36#define PHY_REG_2T_ARRAYLENGTH 380
37extern u32 rtl8192de_phy_reg_2tarray[PHY_REG_2T_ARRAYLENGTH];
38#define PHY_REG_ARRAY_PG_LENGTH 624
39extern u32 rtl8192de_phy_reg_array_pg[PHY_REG_ARRAY_PG_LENGTH];
40#define RADIOA_2T_ARRAYLENGTH 378
41extern u32 rtl8192de_radioa_2tarray[RADIOA_2T_ARRAYLENGTH];
42#define RADIOB_2T_ARRAYLENGTH 384
43extern u32 rtl8192de_radiob_2tarray[RADIOB_2T_ARRAYLENGTH];
44#define RADIOA_2T_INT_PA_ARRAYLENGTH 378
45extern u32 rtl8192de_radioa_2t_int_paarray[RADIOA_2T_INT_PA_ARRAYLENGTH];
46#define RADIOB_2T_INT_PA_ARRAYLENGTH 384
47extern u32 rtl8192de_radiob_2t_int_paarray[RADIOB_2T_INT_PA_ARRAYLENGTH];
48#define MAC_2T_ARRAYLENGTH 160
49extern u32 rtl8192de_mac_2tarray[MAC_2T_ARRAYLENGTH];
50#define AGCTAB_ARRAYLENGTH 386
51extern u32 rtl8192de_agctab_array[AGCTAB_ARRAYLENGTH];
52#define AGCTAB_5G_ARRAYLENGTH 194
53extern u32 rtl8192de_agctab_5garray[AGCTAB_5G_ARRAYLENGTH];
54#define AGCTAB_2G_ARRAYLENGTH 194
55extern u32 rtl8192de_agctab_2garray[AGCTAB_2G_ARRAYLENGTH];
56
57#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/trx.c b/drivers/net/wireless/rtlwifi/rtl8192de/trx.c
new file mode 100644
index 000000000000..bf1462f69b52
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/trx.c
@@ -0,0 +1,959 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../pci.h"
32#include "../base.h"
33#include "reg.h"
34#include "def.h"
35#include "phy.h"
36#include "trx.h"
37#include "led.h"
38
39static u8 _rtl92de_map_hwqueue_to_fwqueue(struct sk_buff *skb, u8 hw_queue)
40{
41 __le16 fc = rtl_get_fc(skb);
42
43 if (unlikely(ieee80211_is_beacon(fc)))
44 return QSLT_BEACON;
45 if (ieee80211_is_mgmt(fc))
46 return QSLT_MGNT;
47
48 return skb->priority;
49}
50
51static int _rtl92de_rate_mapping(bool isht, u8 desc_rate)
52{
53 int rate_idx;
54
55 if (false == isht) {
56 switch (desc_rate) {
57 case DESC92D_RATE1M:
58 rate_idx = 0;
59 break;
60 case DESC92D_RATE2M:
61 rate_idx = 1;
62 break;
63 case DESC92D_RATE5_5M:
64 rate_idx = 2;
65 break;
66 case DESC92D_RATE11M:
67 rate_idx = 3;
68 break;
69 case DESC92D_RATE6M:
70 rate_idx = 4;
71 break;
72 case DESC92D_RATE9M:
73 rate_idx = 5;
74 break;
75 case DESC92D_RATE12M:
76 rate_idx = 6;
77 break;
78 case DESC92D_RATE18M:
79 rate_idx = 7;
80 break;
81 case DESC92D_RATE24M:
82 rate_idx = 8;
83 break;
84 case DESC92D_RATE36M:
85 rate_idx = 9;
86 break;
87 case DESC92D_RATE48M:
88 rate_idx = 10;
89 break;
90 case DESC92D_RATE54M:
91 rate_idx = 11;
92 break;
93 default:
94 rate_idx = 0;
95 break;
96 }
97 return rate_idx;
98 } else {
99 switch (desc_rate) {
100 case DESC92D_RATE1M:
101 rate_idx = 0;
102 break;
103 case DESC92D_RATE2M:
104 rate_idx = 1;
105 break;
106 case DESC92D_RATE5_5M:
107 rate_idx = 2;
108 break;
109 case DESC92D_RATE11M:
110 rate_idx = 3;
111 break;
112 case DESC92D_RATE6M:
113 rate_idx = 4;
114 break;
115 case DESC92D_RATE9M:
116 rate_idx = 5;
117 break;
118 case DESC92D_RATE12M:
119 rate_idx = 6;
120 break;
121 case DESC92D_RATE18M:
122 rate_idx = 7;
123 break;
124 case DESC92D_RATE24M:
125 rate_idx = 8;
126 break;
127 case DESC92D_RATE36M:
128 rate_idx = 9;
129 break;
130 case DESC92D_RATE48M:
131 rate_idx = 10;
132 break;
133 case DESC92D_RATE54M:
134 rate_idx = 11;
135 break;
136 default:
137 rate_idx = 11;
138 break;
139 }
140 return rate_idx;
141 }
142}
143
144static u8 _rtl92d_query_rxpwrpercentage(char antpower)
145{
146 if ((antpower <= -100) || (antpower >= 20))
147 return 0;
148 else if (antpower >= 0)
149 return 100;
150 else
151 return 100 + antpower;
152}
153
154static u8 _rtl92d_evm_db_to_percentage(char value)
155{
156 char ret_val = value;
157
158 if (ret_val >= 0)
159 ret_val = 0;
160 if (ret_val <= -33)
161 ret_val = -33;
162 ret_val = 0 - ret_val;
163 ret_val *= 3;
164 if (ret_val == 99)
165 ret_val = 100;
166 return ret_val;
167}
168
169static long _rtl92de_translate_todbm(struct ieee80211_hw *hw,
170 u8 signal_strength_index)
171{
172 long signal_power;
173
174 signal_power = (long)((signal_strength_index + 1) >> 1);
175 signal_power -= 95;
176 return signal_power;
177}
178
179static long _rtl92de_signal_scale_mapping(struct ieee80211_hw *hw, long currsig)
180{
181 long retsig;
182
183 if (currsig >= 61 && currsig <= 100)
184 retsig = 90 + ((currsig - 60) / 4);
185 else if (currsig >= 41 && currsig <= 60)
186 retsig = 78 + ((currsig - 40) / 2);
187 else if (currsig >= 31 && currsig <= 40)
188 retsig = 66 + (currsig - 30);
189 else if (currsig >= 21 && currsig <= 30)
190 retsig = 54 + (currsig - 20);
191 else if (currsig >= 5 && currsig <= 20)
192 retsig = 42 + (((currsig - 5) * 2) / 3);
193 else if (currsig == 4)
194 retsig = 36;
195 else if (currsig == 3)
196 retsig = 27;
197 else if (currsig == 2)
198 retsig = 18;
199 else if (currsig == 1)
200 retsig = 9;
201 else
202 retsig = currsig;
203 return retsig;
204}
205
206static void _rtl92de_query_rxphystatus(struct ieee80211_hw *hw,
207 struct rtl_stats *pstats,
208 struct rx_desc_92d *pdesc,
209 struct rx_fwinfo_92d *p_drvinfo,
210 bool packet_match_bssid,
211 bool packet_toself,
212 bool packet_beacon)
213{
214 struct rtl_priv *rtlpriv = rtl_priv(hw);
215 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
216 struct phy_sts_cck_8192d *cck_buf;
217 s8 rx_pwr_all, rx_pwr[4];
218 u8 rf_rx_num = 0, evm, pwdb_all;
219 u8 i, max_spatial_stream;
220 u32 rssi, total_rssi = 0;
221 bool is_cck_rate;
222
223 is_cck_rate = RX_HAL_IS_CCK_RATE(pdesc);
224 pstats->packet_matchbssid = packet_match_bssid;
225 pstats->packet_toself = packet_toself;
226 pstats->packet_beacon = packet_beacon;
227 pstats->is_cck = is_cck_rate;
228 pstats->rx_mimo_signalquality[0] = -1;
229 pstats->rx_mimo_signalquality[1] = -1;
230
231 if (is_cck_rate) {
232 u8 report, cck_highpwr;
233 cck_buf = (struct phy_sts_cck_8192d *)p_drvinfo;
234 if (ppsc->rfpwr_state == ERFON)
235 cck_highpwr = (u8) rtl_get_bbreg(hw,
236 RFPGA0_XA_HSSIPARAMETER2,
237 BIT(9));
238 else
239 cck_highpwr = false;
240 if (!cck_highpwr) {
241 u8 cck_agc_rpt = cck_buf->cck_agc_rpt;
242 report = cck_buf->cck_agc_rpt & 0xc0;
243 report = report >> 6;
244 switch (report) {
245 case 0x3:
246 rx_pwr_all = -46 - (cck_agc_rpt & 0x3e);
247 break;
248 case 0x2:
249 rx_pwr_all = -26 - (cck_agc_rpt & 0x3e);
250 break;
251 case 0x1:
252 rx_pwr_all = -12 - (cck_agc_rpt & 0x3e);
253 break;
254 case 0x0:
255 rx_pwr_all = 16 - (cck_agc_rpt & 0x3e);
256 break;
257 }
258 } else {
259 u8 cck_agc_rpt = cck_buf->cck_agc_rpt;
260 report = p_drvinfo->cfosho[0] & 0x60;
261 report = report >> 5;
262 switch (report) {
263 case 0x3:
264 rx_pwr_all = -46 - ((cck_agc_rpt & 0x1f) << 1);
265 break;
266 case 0x2:
267 rx_pwr_all = -26 - ((cck_agc_rpt & 0x1f) << 1);
268 break;
269 case 0x1:
270 rx_pwr_all = -12 - ((cck_agc_rpt & 0x1f) << 1);
271 break;
272 case 0x0:
273 rx_pwr_all = 16 - ((cck_agc_rpt & 0x1f) << 1);
274 break;
275 }
276 }
277 pwdb_all = _rtl92d_query_rxpwrpercentage(rx_pwr_all);
278 /* CCK gain is smaller than OFDM/MCS gain, */
279 /* so we add gain diff by experiences, the val is 6 */
280 pwdb_all += 6;
281 if (pwdb_all > 100)
282 pwdb_all = 100;
283 /* modify the offset to make the same gain index with OFDM. */
284 if (pwdb_all > 34 && pwdb_all <= 42)
285 pwdb_all -= 2;
286 else if (pwdb_all > 26 && pwdb_all <= 34)
287 pwdb_all -= 6;
288 else if (pwdb_all > 14 && pwdb_all <= 26)
289 pwdb_all -= 8;
290 else if (pwdb_all > 4 && pwdb_all <= 14)
291 pwdb_all -= 4;
292 pstats->rx_pwdb_all = pwdb_all;
293 pstats->recvsignalpower = rx_pwr_all;
294 if (packet_match_bssid) {
295 u8 sq;
296 if (pstats->rx_pwdb_all > 40) {
297 sq = 100;
298 } else {
299 sq = cck_buf->sq_rpt;
300 if (sq > 64)
301 sq = 0;
302 else if (sq < 20)
303 sq = 100;
304 else
305 sq = ((64 - sq) * 100) / 44;
306 }
307 pstats->signalquality = sq;
308 pstats->rx_mimo_signalquality[0] = sq;
309 pstats->rx_mimo_signalquality[1] = -1;
310 }
311 } else {
312 rtlpriv->dm.rfpath_rxenable[0] = true;
313 rtlpriv->dm.rfpath_rxenable[1] = true;
314 for (i = RF90_PATH_A; i < RF6052_MAX_PATH; i++) {
315 if (rtlpriv->dm.rfpath_rxenable[i])
316 rf_rx_num++;
317 rx_pwr[i] = ((p_drvinfo->gain_trsw[i] & 0x3f) * 2)
318 - 110;
319 rssi = _rtl92d_query_rxpwrpercentage(rx_pwr[i]);
320 total_rssi += rssi;
321 rtlpriv->stats.rx_snr_db[i] =
322 (long)(p_drvinfo->rxsnr[i] / 2);
323 if (packet_match_bssid)
324 pstats->rx_mimo_signalstrength[i] = (u8) rssi;
325 }
326 rx_pwr_all = ((p_drvinfo->pwdb_all >> 1) & 0x7f) - 106;
327 pwdb_all = _rtl92d_query_rxpwrpercentage(rx_pwr_all);
328 pstats->rx_pwdb_all = pwdb_all;
329 pstats->rxpower = rx_pwr_all;
330 pstats->recvsignalpower = rx_pwr_all;
331 if (pdesc->rxht && pdesc->rxmcs >= DESC92D_RATEMCS8 &&
332 pdesc->rxmcs <= DESC92D_RATEMCS15)
333 max_spatial_stream = 2;
334 else
335 max_spatial_stream = 1;
336 for (i = 0; i < max_spatial_stream; i++) {
337 evm = _rtl92d_evm_db_to_percentage(p_drvinfo->rxevm[i]);
338 if (packet_match_bssid) {
339 if (i == 0)
340 pstats->signalquality =
341 (u8)(evm & 0xff);
342 pstats->rx_mimo_signalquality[i] =
343 (u8)(evm & 0xff);
344 }
345 }
346 }
347 if (is_cck_rate)
348 pstats->signalstrength = (u8)(_rtl92de_signal_scale_mapping(hw,
349 pwdb_all));
350 else if (rf_rx_num != 0)
351 pstats->signalstrength = (u8)(_rtl92de_signal_scale_mapping(hw,
352 total_rssi /= rf_rx_num));
353}
354
355static void rtl92d_loop_over_paths(struct ieee80211_hw *hw,
356 struct rtl_stats *pstats)
357{
358 struct rtl_priv *rtlpriv = rtl_priv(hw);
359 struct rtl_phy *rtlphy = &(rtlpriv->phy);
360 u8 rfpath;
361
362 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
363 rfpath++) {
364 if (rtlpriv->stats.rx_rssi_percentage[rfpath] == 0) {
365 rtlpriv->stats.rx_rssi_percentage[rfpath] =
366 pstats->rx_mimo_signalstrength[rfpath];
367
368 }
369 if (pstats->rx_mimo_signalstrength[rfpath] >
370 rtlpriv->stats.rx_rssi_percentage[rfpath]) {
371 rtlpriv->stats.rx_rssi_percentage[rfpath] =
372 ((rtlpriv->stats.rx_rssi_percentage[rfpath] *
373 (RX_SMOOTH_FACTOR - 1)) +
374 (pstats->rx_mimo_signalstrength[rfpath])) /
375 (RX_SMOOTH_FACTOR);
376 rtlpriv->stats.rx_rssi_percentage[rfpath] =
377 rtlpriv->stats.rx_rssi_percentage[rfpath] + 1;
378 } else {
379 rtlpriv->stats.rx_rssi_percentage[rfpath] =
380 ((rtlpriv->stats.rx_rssi_percentage[rfpath] *
381 (RX_SMOOTH_FACTOR - 1)) +
382 (pstats->rx_mimo_signalstrength[rfpath])) /
383 (RX_SMOOTH_FACTOR);
384 }
385 }
386}
387
388static void _rtl92de_process_ui_rssi(struct ieee80211_hw *hw,
389 struct rtl_stats *pstats)
390{
391 struct rtl_priv *rtlpriv = rtl_priv(hw);
392 u32 last_rssi, tmpval;
393
394 if (pstats->packet_toself || pstats->packet_beacon) {
395 rtlpriv->stats.rssi_calculate_cnt++;
396 if (rtlpriv->stats.ui_rssi.total_num++ >=
397 PHY_RSSI_SLID_WIN_MAX) {
398 rtlpriv->stats.ui_rssi.total_num =
399 PHY_RSSI_SLID_WIN_MAX;
400 last_rssi = rtlpriv->stats.ui_rssi.elements[
401 rtlpriv->stats.ui_rssi.index];
402 rtlpriv->stats.ui_rssi.total_val -= last_rssi;
403 }
404 rtlpriv->stats.ui_rssi.total_val += pstats->signalstrength;
405 rtlpriv->stats.ui_rssi.elements
406 [rtlpriv->stats.ui_rssi.index++] =
407 pstats->signalstrength;
408 if (rtlpriv->stats.ui_rssi.index >= PHY_RSSI_SLID_WIN_MAX)
409 rtlpriv->stats.ui_rssi.index = 0;
410 tmpval = rtlpriv->stats.ui_rssi.total_val /
411 rtlpriv->stats.ui_rssi.total_num;
412 rtlpriv->stats.signal_strength = _rtl92de_translate_todbm(hw,
413 (u8) tmpval);
414 pstats->rssi = rtlpriv->stats.signal_strength;
415 }
416 if (!pstats->is_cck && pstats->packet_toself)
417 rtl92d_loop_over_paths(hw, pstats);
418}
419
420static void _rtl92de_update_rxsignalstatistics(struct ieee80211_hw *hw,
421 struct rtl_stats *pstats)
422{
423 struct rtl_priv *rtlpriv = rtl_priv(hw);
424 int weighting = 0;
425
426 if (rtlpriv->stats.recv_signal_power == 0)
427 rtlpriv->stats.recv_signal_power = pstats->recvsignalpower;
428 if (pstats->recvsignalpower > rtlpriv->stats.recv_signal_power)
429 weighting = 5;
430 else if (pstats->recvsignalpower < rtlpriv->stats.recv_signal_power)
431 weighting = (-5);
432 rtlpriv->stats.recv_signal_power = (rtlpriv->stats.recv_signal_power *
433 5 + pstats->recvsignalpower + weighting) / 6;
434}
435
436static void _rtl92de_process_pwdb(struct ieee80211_hw *hw,
437 struct rtl_stats *pstats)
438{
439 struct rtl_priv *rtlpriv = rtl_priv(hw);
440 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
441 long undecorated_smoothed_pwdb;
442
443 if (mac->opmode == NL80211_IFTYPE_ADHOC ||
444 mac->opmode == NL80211_IFTYPE_AP)
445 return;
446 else
447 undecorated_smoothed_pwdb =
448 rtlpriv->dm.undecorated_smoothed_pwdb;
449
450 if (pstats->packet_toself || pstats->packet_beacon) {
451 if (undecorated_smoothed_pwdb < 0)
452 undecorated_smoothed_pwdb = pstats->rx_pwdb_all;
453 if (pstats->rx_pwdb_all > (u32) undecorated_smoothed_pwdb) {
454 undecorated_smoothed_pwdb =
455 (((undecorated_smoothed_pwdb) *
456 (RX_SMOOTH_FACTOR - 1)) +
457 (pstats->rx_pwdb_all)) / (RX_SMOOTH_FACTOR);
458 undecorated_smoothed_pwdb =
459 undecorated_smoothed_pwdb + 1;
460 } else {
461 undecorated_smoothed_pwdb =
462 (((undecorated_smoothed_pwdb) *
463 (RX_SMOOTH_FACTOR - 1)) +
464 (pstats->rx_pwdb_all)) / (RX_SMOOTH_FACTOR);
465 }
466 rtlpriv->dm.undecorated_smoothed_pwdb =
467 undecorated_smoothed_pwdb;
468 _rtl92de_update_rxsignalstatistics(hw, pstats);
469 }
470}
471
472static void rtl92d_loop_over_streams(struct ieee80211_hw *hw,
473 struct rtl_stats *pstats)
474{
475 struct rtl_priv *rtlpriv = rtl_priv(hw);
476 int stream;
477
478 for (stream = 0; stream < 2; stream++) {
479 if (pstats->rx_mimo_signalquality[stream] != -1) {
480 if (rtlpriv->stats.rx_evm_percentage[stream] == 0) {
481 rtlpriv->stats.rx_evm_percentage[stream] =
482 pstats->rx_mimo_signalquality[stream];
483 }
484 rtlpriv->stats.rx_evm_percentage[stream] =
485 ((rtlpriv->stats.rx_evm_percentage[stream]
486 * (RX_SMOOTH_FACTOR - 1)) +
487 (pstats->rx_mimo_signalquality[stream] * 1)) /
488 (RX_SMOOTH_FACTOR);
489 }
490 }
491}
492
493static void _rtl92de_process_ui_link_quality(struct ieee80211_hw *hw,
494 struct rtl_stats *pstats)
495{
496 struct rtl_priv *rtlpriv = rtl_priv(hw);
497 u32 last_evm, tmpval;
498
499 if (pstats->signalquality == 0)
500 return;
501 if (pstats->packet_toself || pstats->packet_beacon) {
502 if (rtlpriv->stats.ui_link_quality.total_num++ >=
503 PHY_LINKQUALITY_SLID_WIN_MAX) {
504 rtlpriv->stats.ui_link_quality.total_num =
505 PHY_LINKQUALITY_SLID_WIN_MAX;
506 last_evm = rtlpriv->stats.ui_link_quality.elements[
507 rtlpriv->stats.ui_link_quality.index];
508 rtlpriv->stats.ui_link_quality.total_val -= last_evm;
509 }
510 rtlpriv->stats.ui_link_quality.total_val +=
511 pstats->signalquality;
512 rtlpriv->stats.ui_link_quality.elements[
513 rtlpriv->stats.ui_link_quality.index++] =
514 pstats->signalquality;
515 if (rtlpriv->stats.ui_link_quality.index >=
516 PHY_LINKQUALITY_SLID_WIN_MAX)
517 rtlpriv->stats.ui_link_quality.index = 0;
518 tmpval = rtlpriv->stats.ui_link_quality.total_val /
519 rtlpriv->stats.ui_link_quality.total_num;
520 rtlpriv->stats.signal_quality = tmpval;
521 rtlpriv->stats.last_sigstrength_inpercent = tmpval;
522 rtl92d_loop_over_streams(hw, pstats);
523 }
524}
525
526static void _rtl92de_process_phyinfo(struct ieee80211_hw *hw,
527 u8 *buffer,
528 struct rtl_stats *pcurrent_stats)
529{
530
531 if (!pcurrent_stats->packet_matchbssid &&
532 !pcurrent_stats->packet_beacon)
533 return;
534
535 _rtl92de_process_ui_rssi(hw, pcurrent_stats);
536 _rtl92de_process_pwdb(hw, pcurrent_stats);
537 _rtl92de_process_ui_link_quality(hw, pcurrent_stats);
538}
539
540static void _rtl92de_translate_rx_signal_stuff(struct ieee80211_hw *hw,
541 struct sk_buff *skb,
542 struct rtl_stats *pstats,
543 struct rx_desc_92d *pdesc,
544 struct rx_fwinfo_92d *p_drvinfo)
545{
546 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
547 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
548 struct ieee80211_hdr *hdr;
549 u8 *tmp_buf;
550 u8 *praddr;
551 u16 type, cfc;
552 __le16 fc;
553 bool packet_matchbssid, packet_toself, packet_beacon;
554
555 tmp_buf = skb->data + pstats->rx_drvinfo_size + pstats->rx_bufshift;
556 hdr = (struct ieee80211_hdr *)tmp_buf;
557 fc = hdr->frame_control;
558 cfc = le16_to_cpu(fc);
559 type = WLAN_FC_GET_TYPE(fc);
560 praddr = hdr->addr1;
561 packet_matchbssid = ((IEEE80211_FTYPE_CTL != type) &&
562 (!compare_ether_addr(mac->bssid, (cfc & IEEE80211_FCTL_TODS) ?
563 hdr->addr1 : (cfc & IEEE80211_FCTL_FROMDS) ?
564 hdr->addr2 : hdr->addr3)) && (!pstats->hwerror) &&
565 (!pstats->crc) && (!pstats->icv));
566 packet_toself = packet_matchbssid &&
567 (!compare_ether_addr(praddr, rtlefuse->dev_addr));
568 if (ieee80211_is_beacon(fc))
569 packet_beacon = true;
570 _rtl92de_query_rxphystatus(hw, pstats, pdesc, p_drvinfo,
571 packet_matchbssid, packet_toself,
572 packet_beacon);
573 _rtl92de_process_phyinfo(hw, tmp_buf, pstats);
574}
575
576bool rtl92de_rx_query_desc(struct ieee80211_hw *hw, struct rtl_stats *stats,
577 struct ieee80211_rx_status *rx_status,
578 u8 *p_desc, struct sk_buff *skb)
579{
580 struct rx_fwinfo_92d *p_drvinfo;
581 struct rx_desc_92d *pdesc = (struct rx_desc_92d *)p_desc;
582 u32 phystatus = GET_RX_DESC_PHYST(pdesc);
583
584 stats->length = (u16) GET_RX_DESC_PKT_LEN(pdesc);
585 stats->rx_drvinfo_size = (u8) GET_RX_DESC_DRV_INFO_SIZE(pdesc) *
586 RX_DRV_INFO_SIZE_UNIT;
587 stats->rx_bufshift = (u8) (GET_RX_DESC_SHIFT(pdesc) & 0x03);
588 stats->icv = (u16) GET_RX_DESC_ICV(pdesc);
589 stats->crc = (u16) GET_RX_DESC_CRC32(pdesc);
590 stats->hwerror = (stats->crc | stats->icv);
591 stats->decrypted = !GET_RX_DESC_SWDEC(pdesc);
592 stats->rate = (u8) GET_RX_DESC_RXMCS(pdesc);
593 stats->shortpreamble = (u16) GET_RX_DESC_SPLCP(pdesc);
594 stats->isampdu = (bool) (GET_RX_DESC_PAGGR(pdesc) == 1);
595 stats->isfirst_ampdu = (bool) ((GET_RX_DESC_PAGGR(pdesc) == 1)
596 && (GET_RX_DESC_FAGGR(pdesc) == 1));
597 stats->timestamp_low = GET_RX_DESC_TSFL(pdesc);
598 stats->rx_is40Mhzpacket = (bool) GET_RX_DESC_BW(pdesc);
599 rx_status->freq = hw->conf.channel->center_freq;
600 rx_status->band = hw->conf.channel->band;
601 if (GET_RX_DESC_CRC32(pdesc))
602 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
603 if (!GET_RX_DESC_SWDEC(pdesc))
604 rx_status->flag |= RX_FLAG_DECRYPTED;
605 if (GET_RX_DESC_BW(pdesc))
606 rx_status->flag |= RX_FLAG_40MHZ;
607 if (GET_RX_DESC_RXHT(pdesc))
608 rx_status->flag |= RX_FLAG_HT;
609 rx_status->flag |= RX_FLAG_MACTIME_MPDU;
610 if (stats->decrypted)
611 rx_status->flag |= RX_FLAG_DECRYPTED;
612 rx_status->rate_idx = _rtl92de_rate_mapping((bool)
613 GET_RX_DESC_RXHT(pdesc),
614 (u8)
615 GET_RX_DESC_RXMCS(pdesc));
616 rx_status->mactime = GET_RX_DESC_TSFL(pdesc);
617 if (phystatus == true) {
618 p_drvinfo = (struct rx_fwinfo_92d *)(skb->data +
619 stats->rx_bufshift);
620 _rtl92de_translate_rx_signal_stuff(hw,
621 skb, stats, pdesc,
622 p_drvinfo);
623 }
624 /*rx_status->qual = stats->signal; */
625 rx_status->signal = stats->rssi + 10;
626 /*rx_status->noise = -stats->noise; */
627 return true;
628}
629
630static void _rtl92de_insert_emcontent(struct rtl_tcb_desc *ptcb_desc,
631 u8 *virtualaddress)
632{
633 memset(virtualaddress, 0, 8);
634
635 SET_EARLYMODE_PKTNUM(virtualaddress, ptcb_desc->empkt_num);
636 SET_EARLYMODE_LEN0(virtualaddress, ptcb_desc->empkt_len[0]);
637 SET_EARLYMODE_LEN1(virtualaddress, ptcb_desc->empkt_len[1]);
638 SET_EARLYMODE_LEN2_1(virtualaddress, ptcb_desc->empkt_len[2] & 0xF);
639 SET_EARLYMODE_LEN2_2(virtualaddress, ptcb_desc->empkt_len[2] >> 4);
640 SET_EARLYMODE_LEN3(virtualaddress, ptcb_desc->empkt_len[3]);
641 SET_EARLYMODE_LEN4(virtualaddress, ptcb_desc->empkt_len[4]);
642}
643
644void rtl92de_tx_fill_desc(struct ieee80211_hw *hw,
645 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
646 struct ieee80211_tx_info *info, struct sk_buff *skb,
647 u8 hw_queue, struct rtl_tcb_desc *ptcb_desc)
648{
649 struct rtl_priv *rtlpriv = rtl_priv(hw);
650 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
651 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
652 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
653 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
654 struct ieee80211_sta *sta = info->control.sta;
655 u8 *pdesc = (u8 *) pdesc_tx;
656 u16 seq_number;
657 __le16 fc = hdr->frame_control;
658 unsigned int buf_len = 0;
659 unsigned int skb_len = skb->len;
660 u8 fw_qsel = _rtl92de_map_hwqueue_to_fwqueue(skb, hw_queue);
661 bool firstseg = ((hdr->seq_ctrl &
662 cpu_to_le16(IEEE80211_SCTL_FRAG)) == 0);
663 bool lastseg = ((hdr->frame_control &
664 cpu_to_le16(IEEE80211_FCTL_MOREFRAGS)) == 0);
665 dma_addr_t mapping;
666 u8 bw_40 = 0;
667
668 if (mac->opmode == NL80211_IFTYPE_STATION) {
669 bw_40 = mac->bw_40;
670 } else if (mac->opmode == NL80211_IFTYPE_AP ||
671 mac->opmode == NL80211_IFTYPE_ADHOC) {
672 if (sta)
673 bw_40 = sta->ht_cap.cap &
674 IEEE80211_HT_CAP_SUP_WIDTH_20_40;
675 }
676 seq_number = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
677 rtl_get_tcb_desc(hw, info, sta, skb, ptcb_desc);
678 /* reserve 8 byte for AMPDU early mode */
679 if (rtlhal->earlymode_enable) {
680 skb_push(skb, EM_HDR_LEN);
681 memset(skb->data, 0, EM_HDR_LEN);
682 }
683 buf_len = skb->len;
684 mapping = pci_map_single(rtlpci->pdev, skb->data, skb->len,
685 PCI_DMA_TODEVICE);
686 CLEAR_PCI_TX_DESC_CONTENT(pdesc, sizeof(struct tx_desc_92d));
687 if (ieee80211_is_nullfunc(fc) || ieee80211_is_ctl(fc)) {
688 firstseg = true;
689 lastseg = true;
690 }
691 if (firstseg) {
692 if (rtlhal->earlymode_enable) {
693 SET_TX_DESC_PKT_OFFSET(pdesc, 1);
694 SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN +
695 EM_HDR_LEN);
696 if (ptcb_desc->empkt_num) {
697 RT_TRACE(rtlpriv, COMP_SEND, DBG_LOUD,
698 ("Insert 8 byte.pTcb->EMPktNum:%d\n",
699 ptcb_desc->empkt_num));
700 _rtl92de_insert_emcontent(ptcb_desc,
701 (u8 *)(skb->data));
702 }
703 } else {
704 SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN);
705 }
706 /* 5G have no CCK rate */
707 if (rtlhal->current_bandtype == BAND_ON_5G)
708 if (ptcb_desc->hw_rate < DESC92D_RATE6M)
709 ptcb_desc->hw_rate = DESC92D_RATE6M;
710 SET_TX_DESC_TX_RATE(pdesc, ptcb_desc->hw_rate);
711 if (ptcb_desc->use_shortgi || ptcb_desc->use_shortpreamble)
712 SET_TX_DESC_DATA_SHORTGI(pdesc, 1);
713
714 if (rtlhal->macphymode == DUALMAC_DUALPHY &&
715 ptcb_desc->hw_rate == DESC92D_RATEMCS7)
716 SET_TX_DESC_DATA_SHORTGI(pdesc, 1);
717
718 if (info->flags & IEEE80211_TX_CTL_AMPDU) {
719 SET_TX_DESC_AGG_ENABLE(pdesc, 1);
720 SET_TX_DESC_MAX_AGG_NUM(pdesc, 0x14);
721 }
722 SET_TX_DESC_SEQ(pdesc, seq_number);
723 SET_TX_DESC_RTS_ENABLE(pdesc, ((ptcb_desc->rts_enable &&
724 !ptcb_desc->cts_enable) ? 1 : 0));
725 SET_TX_DESC_HW_RTS_ENABLE(pdesc, ((ptcb_desc->rts_enable
726 || ptcb_desc->cts_enable) ? 1 : 0));
727 SET_TX_DESC_CTS2SELF(pdesc, ((ptcb_desc->cts_enable) ? 1 : 0));
728 SET_TX_DESC_RTS_STBC(pdesc, ((ptcb_desc->rts_stbc) ? 1 : 0));
729 /* 5G have no CCK rate */
730 if (rtlhal->current_bandtype == BAND_ON_5G)
731 if (ptcb_desc->rts_rate < DESC92D_RATE6M)
732 ptcb_desc->rts_rate = DESC92D_RATE6M;
733 SET_TX_DESC_RTS_RATE(pdesc, ptcb_desc->rts_rate);
734 SET_TX_DESC_RTS_BW(pdesc, 0);
735 SET_TX_DESC_RTS_SC(pdesc, ptcb_desc->rts_sc);
736 SET_TX_DESC_RTS_SHORT(pdesc, ((ptcb_desc->rts_rate <=
737 DESC92D_RATE54M) ?
738 (ptcb_desc->rts_use_shortpreamble ? 1 : 0) :
739 (ptcb_desc->rts_use_shortgi ? 1 : 0)));
740 if (bw_40) {
741 if (ptcb_desc->packet_bw) {
742 SET_TX_DESC_DATA_BW(pdesc, 1);
743 SET_TX_DESC_TX_SUB_CARRIER(pdesc, 3);
744 } else {
745 SET_TX_DESC_DATA_BW(pdesc, 0);
746 SET_TX_DESC_TX_SUB_CARRIER(pdesc,
747 mac->cur_40_prime_sc);
748 }
749 } else {
750 SET_TX_DESC_DATA_BW(pdesc, 0);
751 SET_TX_DESC_TX_SUB_CARRIER(pdesc, 0);
752 }
753 SET_TX_DESC_LINIP(pdesc, 0);
754 SET_TX_DESC_PKT_SIZE(pdesc, (u16) skb_len);
755 if (sta) {
756 u8 ampdu_density = sta->ht_cap.ampdu_density;
757 SET_TX_DESC_AMPDU_DENSITY(pdesc, ampdu_density);
758 }
759 if (info->control.hw_key) {
760 struct ieee80211_key_conf *keyconf;
761
762 keyconf = info->control.hw_key;
763 switch (keyconf->cipher) {
764 case WLAN_CIPHER_SUITE_WEP40:
765 case WLAN_CIPHER_SUITE_WEP104:
766 case WLAN_CIPHER_SUITE_TKIP:
767 SET_TX_DESC_SEC_TYPE(pdesc, 0x1);
768 break;
769 case WLAN_CIPHER_SUITE_CCMP:
770 SET_TX_DESC_SEC_TYPE(pdesc, 0x3);
771 break;
772 default:
773 SET_TX_DESC_SEC_TYPE(pdesc, 0x0);
774 break;
775
776 }
777 }
778 SET_TX_DESC_PKT_ID(pdesc, 0);
779 SET_TX_DESC_QUEUE_SEL(pdesc, fw_qsel);
780 SET_TX_DESC_DATA_RATE_FB_LIMIT(pdesc, 0x1F);
781 SET_TX_DESC_RTS_RATE_FB_LIMIT(pdesc, 0xF);
782 SET_TX_DESC_DISABLE_FB(pdesc, ptcb_desc->disable_ratefallback ?
783 1 : 0);
784 SET_TX_DESC_USE_RATE(pdesc, ptcb_desc->use_driver_rate ? 1 : 0);
785
786 /* Set TxRate and RTSRate in TxDesc */
787 /* This prevent Tx initial rate of new-coming packets */
788 /* from being overwritten by retried packet rate.*/
789 if (!ptcb_desc->use_driver_rate) {
790 SET_TX_DESC_RTS_RATE(pdesc, 0x08);
791 /* SET_TX_DESC_TX_RATE(pdesc, 0x0b); */
792 }
793 if (ieee80211_is_data_qos(fc)) {
794 if (mac->rdg_en) {
795 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
796 ("Enable RDG function.\n"));
797 SET_TX_DESC_RDG_ENABLE(pdesc, 1);
798 SET_TX_DESC_HTC(pdesc, 1);
799 }
800 }
801 }
802
803 SET_TX_DESC_FIRST_SEG(pdesc, (firstseg ? 1 : 0));
804 SET_TX_DESC_LAST_SEG(pdesc, (lastseg ? 1 : 0));
805 SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16) buf_len);
806 SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping);
807 if (rtlpriv->dm.useramask) {
808 SET_TX_DESC_RATE_ID(pdesc, ptcb_desc->ratr_index);
809 SET_TX_DESC_MACID(pdesc, ptcb_desc->mac_id);
810 } else {
811 SET_TX_DESC_RATE_ID(pdesc, 0xC + ptcb_desc->ratr_index);
812 SET_TX_DESC_MACID(pdesc, ptcb_desc->ratr_index);
813 }
814 if (ieee80211_is_data_qos(fc))
815 SET_TX_DESC_QOS(pdesc, 1);
816
817 if ((!ieee80211_is_data_qos(fc)) && ppsc->fwctrl_lps) {
818 SET_TX_DESC_HWSEQ_EN(pdesc, 1);
819 SET_TX_DESC_PKT_ID(pdesc, 8);
820 }
821 SET_TX_DESC_MORE_FRAG(pdesc, (lastseg ? 0 : 1));
822 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, ("\n"));
823}
824
825void rtl92de_tx_fill_cmddesc(struct ieee80211_hw *hw,
826 u8 *pdesc, bool firstseg,
827 bool lastseg, struct sk_buff *skb)
828{
829 struct rtl_priv *rtlpriv = rtl_priv(hw);
830 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
831 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
832 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
833 u8 fw_queue = QSLT_BEACON;
834 dma_addr_t mapping = pci_map_single(rtlpci->pdev,
835 skb->data, skb->len, PCI_DMA_TODEVICE);
836 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
837 __le16 fc = hdr->frame_control;
838
839 CLEAR_PCI_TX_DESC_CONTENT(pdesc, TX_DESC_SIZE);
840 if (firstseg)
841 SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN);
842 /* 5G have no CCK rate
843 * Caution: The macros below are multi-line expansions.
844 * The braces are needed no matter what checkpatch says
845 */
846 if (rtlhal->current_bandtype == BAND_ON_5G) {
847 SET_TX_DESC_TX_RATE(pdesc, DESC92D_RATE6M);
848 } else {
849 SET_TX_DESC_TX_RATE(pdesc, DESC92D_RATE1M);
850 }
851 SET_TX_DESC_SEQ(pdesc, 0);
852 SET_TX_DESC_LINIP(pdesc, 0);
853 SET_TX_DESC_QUEUE_SEL(pdesc, fw_queue);
854 SET_TX_DESC_FIRST_SEG(pdesc, 1);
855 SET_TX_DESC_LAST_SEG(pdesc, 1);
856 SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16) (skb->len));
857 SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping);
858 SET_TX_DESC_RATE_ID(pdesc, 7);
859 SET_TX_DESC_MACID(pdesc, 0);
860 SET_TX_DESC_PKT_SIZE((u8 *) pdesc, (u16) (skb->len));
861 SET_TX_DESC_FIRST_SEG(pdesc, 1);
862 SET_TX_DESC_LAST_SEG(pdesc, 1);
863 SET_TX_DESC_OFFSET(pdesc, 0x20);
864 SET_TX_DESC_USE_RATE(pdesc, 1);
865
866 if (!ieee80211_is_data_qos(fc) && ppsc->fwctrl_lps) {
867 SET_TX_DESC_HWSEQ_EN(pdesc, 1);
868 SET_TX_DESC_PKT_ID(pdesc, 8);
869 }
870
871 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
872 "H2C Tx Cmd Content\n", pdesc, TX_DESC_SIZE);
873 wmb();
874 SET_TX_DESC_OWN(pdesc, 1);
875}
876
877void rtl92de_set_desc(u8 *pdesc, bool istx, u8 desc_name, u8 *val)
878{
879 if (istx == true) {
880 switch (desc_name) {
881 case HW_DESC_OWN:
882 wmb();
883 SET_TX_DESC_OWN(pdesc, 1);
884 break;
885 case HW_DESC_TX_NEXTDESC_ADDR:
886 SET_TX_DESC_NEXT_DESC_ADDRESS(pdesc, *(u32 *) val);
887 break;
888 default:
889 RT_ASSERT(false, ("ERR txdesc :%d"
890 " not process\n", desc_name));
891 break;
892 }
893 } else {
894 switch (desc_name) {
895 case HW_DESC_RXOWN:
896 wmb();
897 SET_RX_DESC_OWN(pdesc, 1);
898 break;
899 case HW_DESC_RXBUFF_ADDR:
900 SET_RX_DESC_BUFF_ADDR(pdesc, *(u32 *) val);
901 break;
902 case HW_DESC_RXPKT_LEN:
903 SET_RX_DESC_PKT_LEN(pdesc, *(u32 *) val);
904 break;
905 case HW_DESC_RXERO:
906 SET_RX_DESC_EOR(pdesc, 1);
907 break;
908 default:
909 RT_ASSERT(false, ("ERR rxdesc :%d "
910 "not process\n", desc_name));
911 break;
912 }
913 }
914}
915
916u32 rtl92de_get_desc(u8 *p_desc, bool istx, u8 desc_name)
917{
918 u32 ret = 0;
919
920 if (istx == true) {
921 switch (desc_name) {
922 case HW_DESC_OWN:
923 ret = GET_TX_DESC_OWN(p_desc);
924 break;
925 case HW_DESC_TXBUFF_ADDR:
926 ret = GET_TX_DESC_TX_BUFFER_ADDRESS(p_desc);
927 break;
928 default:
929 RT_ASSERT(false, ("ERR txdesc :%d "
930 "not process\n", desc_name));
931 break;
932 }
933 } else {
934 struct rx_desc_92c *pdesc = (struct rx_desc_92c *)p_desc;
935 switch (desc_name) {
936 case HW_DESC_OWN:
937 ret = GET_RX_DESC_OWN(pdesc);
938 break;
939 case HW_DESC_RXPKT_LEN:
940 ret = GET_RX_DESC_PKT_LEN(pdesc);
941 break;
942 default:
943 RT_ASSERT(false, ("ERR rxdesc :%d "
944 "not process\n", desc_name));
945 break;
946 }
947 }
948 return ret;
949}
950
951void rtl92de_tx_polling(struct ieee80211_hw *hw, u8 hw_queue)
952{
953 struct rtl_priv *rtlpriv = rtl_priv(hw);
954 if (hw_queue == BEACON_QUEUE)
955 rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG, BIT(4));
956 else
957 rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG,
958 BIT(0) << (hw_queue));
959}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/trx.h b/drivers/net/wireless/rtlwifi/rtl8192de/trx.h
new file mode 100644
index 000000000000..992d6766e667
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/trx.h
@@ -0,0 +1,756 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92DE_TRX_H__
31#define __RTL92DE_TRX_H__
32
33#define TX_DESC_SIZE 64
34#define TX_DESC_AGGR_SUBFRAME_SIZE 32
35
36#define RX_DESC_SIZE 32
37#define RX_DRV_INFO_SIZE_UNIT 8
38
39#define TX_DESC_NEXT_DESC_OFFSET 40
40#define USB_HWDESC_HEADER_LEN 32
41#define CRCLENGTH 4
42
43/* Define a macro that takes a le32 word, converts it to host ordering,
44 * right shifts by a specified count, creates a mask of the specified
45 * bit count, and extracts that number of bits.
46 */
47
48#define SHIFT_AND_MASK_LE(__pdesc, __shift, __mask) \
49 ((le32_to_cpu(*(((__le32 *)(__pdesc)))) >> (__shift)) & \
50 BIT_LEN_MASK_32(__mask))
51
52/* Define a macro that clears a bit field in an le32 word and
53 * sets the specified value into that bit field. The resulting
54 * value remains in le32 ordering; however, it is properly converted
55 * to host ordering for the clear and set operations before conversion
56 * back to le32.
57 */
58
59#define SET_BITS_OFFSET_LE(__pdesc, __shift, __len, __val) \
60 (*(__le32 *)(__pdesc) = \
61 (cpu_to_le32((le32_to_cpu(*((__le32 *)(__pdesc))) & \
62 (~(BIT_OFFSET_LEN_MASK_32((__shift), __len)))) | \
63 (((u32)(__val) & BIT_LEN_MASK_32(__len)) << (__shift)))));
64
65/* macros to read/write various fields in RX or TX descriptors */
66
67#define SET_TX_DESC_PKT_SIZE(__pdesc, __val) \
68 SET_BITS_OFFSET_LE(__pdesc, 0, 16, __val)
69#define SET_TX_DESC_OFFSET(__pdesc, __val) \
70 SET_BITS_OFFSET_LE(__pdesc, 16, 8, __val)
71#define SET_TX_DESC_BMC(__pdesc, __val) \
72 SET_BITS_OFFSET_LE(__pdesc, 24, 1, __val)
73#define SET_TX_DESC_HTC(__pdesc, __val) \
74 SET_BITS_OFFSET_LE(__pdesc, 25, 1, __val)
75#define SET_TX_DESC_LAST_SEG(__pdesc, __val) \
76 SET_BITS_OFFSET_LE(__pdesc, 26, 1, __val)
77#define SET_TX_DESC_FIRST_SEG(__pdesc, __val) \
78 SET_BITS_OFFSET_LE(__pdesc, 27, 1, __val)
79#define SET_TX_DESC_LINIP(__pdesc, __val) \
80 SET_BITS_OFFSET_LE(__pdesc, 28, 1, __val)
81#define SET_TX_DESC_NO_ACM(__pdesc, __val) \
82 SET_BITS_OFFSET_LE(__pdesc, 29, 1, __val)
83#define SET_TX_DESC_GF(__pdesc, __val) \
84 SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val)
85#define SET_TX_DESC_OWN(__pdesc, __val) \
86 SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
87
88#define GET_TX_DESC_PKT_SIZE(__pdesc) \
89 SHIFT_AND_MASK_LE(__pdesc, 0, 16)
90#define GET_TX_DESC_OFFSET(__pdesc) \
91 SHIFT_AND_MASK_LE(__pdesc, 16, 8)
92#define GET_TX_DESC_BMC(__pdesc) \
93 SHIFT_AND_MASK_LE(__pdesc, 24, 1)
94#define GET_TX_DESC_HTC(__pdesc) \
95 SHIFT_AND_MASK_LE(__pdesc, 25, 1)
96#define GET_TX_DESC_LAST_SEG(__pdesc) \
97 SHIFT_AND_MASK_LE(__pdesc, 26, 1)
98#define GET_TX_DESC_FIRST_SEG(__pdesc) \
99 SHIFT_AND_MASK_LE(__pdesc, 27, 1)
100#define GET_TX_DESC_LINIP(__pdesc) \
101 SHIFT_AND_MASK_LE(__pdesc, 28, 1)
102#define GET_TX_DESC_NO_ACM(__pdesc) \
103 SHIFT_AND_MASK_LE(__pdesc, 29, 1)
104#define GET_TX_DESC_GF(__pdesc) \
105 SHIFT_AND_MASK_LE(__pdesc, 30, 1)
106#define GET_TX_DESC_OWN(__pdesc) \
107 SHIFT_AND_MASK_LE(__pdesc, 31, 1)
108
109#define SET_TX_DESC_MACID(__pdesc, __val) \
110 SET_BITS_OFFSET_LE(__pdesc+4, 0, 5, __val)
111#define SET_TX_DESC_AGG_ENABLE(__pdesc, __val) \
112 SET_BITS_OFFSET_LE(__pdesc+4, 5, 1, __val)
113#define SET_TX_DESC_BK(__pdesc, __val) \
114 SET_BITS_OFFSET_LE(__pdesc+4, 6, 1, __val)
115#define SET_TX_DESC_RDG_ENABLE(__pdesc, __val) \
116 SET_BITS_OFFSET_LE(__pdesc+4, 7, 1, __val)
117#define SET_TX_DESC_QUEUE_SEL(__pdesc, __val) \
118 SET_BITS_OFFSET_LE(__pdesc+4, 8, 5, __val)
119#define SET_TX_DESC_RDG_NAV_EXT(__pdesc, __val) \
120 SET_BITS_OFFSET_LE(__pdesc+4, 13, 1, __val)
121#define SET_TX_DESC_LSIG_TXOP_EN(__pdesc, __val) \
122 SET_BITS_OFFSET_LE(__pdesc+4, 14, 1, __val)
123#define SET_TX_DESC_PIFS(__pdesc, __val) \
124 SET_BITS_OFFSET_LE(__pdesc+4, 15, 1, __val)
125#define SET_TX_DESC_RATE_ID(__pdesc, __val) \
126 SET_BITS_OFFSET_LE(__pdesc+4, 16, 4, __val)
127#define SET_TX_DESC_NAV_USE_HDR(__pdesc, __val) \
128 SET_BITS_OFFSET_LE(__pdesc+4, 20, 1, __val)
129#define SET_TX_DESC_EN_DESC_ID(__pdesc, __val) \
130 SET_BITS_OFFSET_LE(__pdesc+4, 21, 1, __val)
131#define SET_TX_DESC_SEC_TYPE(__pdesc, __val) \
132 SET_BITS_OFFSET_LE(__pdesc+4, 22, 2, __val)
133#define SET_TX_DESC_PKT_OFFSET(__pdesc, __val) \
134 SET_BITS_OFFSET_LE(__pdesc+4, 26, 8, __val)
135
136#define GET_TX_DESC_MACID(__pdesc) \
137 SHIFT_AND_MASK_LE(__pdesc+4, 0, 5)
138#define GET_TX_DESC_AGG_ENABLE(__pdesc) \
139 SHIFT_AND_MASK_LE(__pdesc+4, 5, 1)
140#define GET_TX_DESC_AGG_BREAK(__pdesc) \
141 SHIFT_AND_MASK_LE(__pdesc+4, 6, 1)
142#define GET_TX_DESC_RDG_ENABLE(__pdesc) \
143 SHIFT_AND_MASK_LE(__pdesc+4, 7, 1)
144#define GET_TX_DESC_QUEUE_SEL(__pdesc) \
145 SHIFT_AND_MASK_LE(__pdesc+4, 8, 5)
146#define GET_TX_DESC_RDG_NAV_EXT(__pdesc) \
147 SHIFT_AND_MASK_LE(__pdesc+4, 13, 1)
148#define GET_TX_DESC_LSIG_TXOP_EN(__pdesc) \
149 SHIFT_AND_MASK_LE(__pdesc+4, 14, 1)
150#define GET_TX_DESC_PIFS(__pdesc) \
151 SHIFT_AND_MASK_LE(__pdesc+4, 15, 1)
152#define GET_TX_DESC_RATE_ID(__pdesc) \
153 SHIFT_AND_MASK_LE(__pdesc+4, 16, 4)
154#define GET_TX_DESC_NAV_USE_HDR(__pdesc) \
155 SHIFT_AND_MASK_LE(__pdesc+4, 20, 1)
156#define GET_TX_DESC_EN_DESC_ID(__pdesc) \
157 SHIFT_AND_MASK_LE(__pdesc+4, 21, 1)
158#define GET_TX_DESC_SEC_TYPE(__pdesc) \
159 SHIFT_AND_MASK_LE(__pdesc+4, 22, 2)
160#define GET_TX_DESC_PKT_OFFSET(__pdesc) \
161 SHIFT_AND_MASK_LE(__pdesc+4, 24, 8)
162
163#define SET_TX_DESC_RTS_RC(__pdesc, __val) \
164 SET_BITS_OFFSET_LE(__pdesc+8, 0, 6, __val)
165#define SET_TX_DESC_DATA_RC(__pdesc, __val) \
166 SET_BITS_OFFSET_LE(__pdesc+8, 6, 6, __val)
167#define SET_TX_DESC_BAR_RTY_TH(__pdesc, __val) \
168 SET_BITS_OFFSET_LE(__pdesc+8, 14, 2, __val)
169#define SET_TX_DESC_MORE_FRAG(__pdesc, __val) \
170 SET_BITS_OFFSET_LE(__pdesc+8, 17, 1, __val)
171#define SET_TX_DESC_RAW(__pdesc, __val) \
172 SET_BITS_OFFSET_LE(__pdesc+8, 18, 1, __val)
173#define SET_TX_DESC_CCX(__pdesc, __val) \
174 SET_BITS_OFFSET_LE(__pdesc+8, 19, 1, __val)
175#define SET_TX_DESC_AMPDU_DENSITY(__pdesc, __val) \
176 SET_BITS_OFFSET_LE(__pdesc+8, 20, 3, __val)
177#define SET_TX_DESC_ANTSEL_A(__pdesc, __val) \
178 SET_BITS_OFFSET_LE(__pdesc+8, 24, 1, __val)
179#define SET_TX_DESC_ANTSEL_B(__pdesc, __val) \
180 SET_BITS_OFFSET_LE(__pdesc+8, 25, 1, __val)
181#define SET_TX_DESC_TX_ANT_CCK(__pdesc, __val) \
182 SET_BITS_OFFSET_LE(__pdesc+8, 26, 2, __val)
183#define SET_TX_DESC_TX_ANTL(__pdesc, __val) \
184 SET_BITS_OFFSET_LE(__pdesc+8, 28, 2, __val)
185#define SET_TX_DESC_TX_ANT_HT(__pdesc, __val) \
186 SET_BITS_OFFSET_LE(__pdesc+8, 30, 2, __val)
187
188#define GET_TX_DESC_RTS_RC(__pdesc) \
189 SHIFT_AND_MASK_LE(__pdesc+8, 0, 6)
190#define GET_TX_DESC_DATA_RC(__pdesc) \
191 SHIFT_AND_MASK_LE(__pdesc+8, 6, 6)
192#define GET_TX_DESC_BAR_RTY_TH(__pdesc) \
193 SHIFT_AND_MASK_LE(__pdesc+8, 14, 2)
194#define GET_TX_DESC_MORE_FRAG(__pdesc) \
195 SHIFT_AND_MASK_LE(__pdesc+8, 17, 1)
196#define GET_TX_DESC_RAW(__pdesc) \
197 SHIFT_AND_MASK_LE(__pdesc+8, 18, 1)
198#define GET_TX_DESC_CCX(__pdesc) \
199 SHIFT_AND_MASK_LE(__pdesc+8, 19, 1)
200#define GET_TX_DESC_AMPDU_DENSITY(__pdesc) \
201 SHIFT_AND_MASK_LE(__pdesc+8, 20, 3)
202#define GET_TX_DESC_ANTSEL_A(__pdesc) \
203 SHIFT_AND_MASK_LE(__pdesc+8, 24, 1)
204#define GET_TX_DESC_ANTSEL_B(__pdesc) \
205 SHIFT_AND_MASK_LE(__pdesc+8, 25, 1)
206#define GET_TX_DESC_TX_ANT_CCK(__pdesc) \
207 SHIFT_AND_MASK_LE(__pdesc+8, 26, 2)
208#define GET_TX_DESC_TX_ANTL(__pdesc) \
209 SHIFT_AND_MASK_LE(__pdesc+8, 28, 2)
210#define GET_TX_DESC_TX_ANT_HT(__pdesc) \
211 SHIFT_AND_MASK_LE(__pdesc+8, 30, 2)
212
213#define SET_TX_DESC_NEXT_HEAP_PAGE(__pdesc, __val) \
214 SET_BITS_OFFSET_LE(__pdesc+12, 0, 8, __val)
215#define SET_TX_DESC_TAIL_PAGE(__pdesc, __val) \
216 SET_BITS_OFFSET_LE(__pdesc+12, 8, 8, __val)
217#define SET_TX_DESC_SEQ(__pdesc, __val) \
218 SET_BITS_OFFSET_LE(__pdesc+12, 16, 12, __val)
219#define SET_TX_DESC_PKT_ID(__pdesc, __val) \
220 SET_BITS_OFFSET_LE(__pdesc+12, 28, 4, __val)
221
222#define GET_TX_DESC_NEXT_HEAP_PAGE(__pdesc) \
223 SHIFT_AND_MASK_LE(__pdesc+12, 0, 8)
224#define GET_TX_DESC_TAIL_PAGE(__pdesc) \
225 SHIFT_AND_MASK_LE(__pdesc+12, 8, 8)
226#define GET_TX_DESC_SEQ(__pdesc) \
227 SHIFT_AND_MASK_LE(__pdesc+12, 16, 12)
228#define GET_TX_DESC_PKT_ID(__pdesc) \
229 SHIFT_AND_MASK_LE(__pdesc+12, 28, 4)
230
231#define SET_TX_DESC_RTS_RATE(__pdesc, __val) \
232 SET_BITS_OFFSET_LE(__pdesc+16, 0, 5, __val)
233#define SET_TX_DESC_AP_DCFE(__pdesc, __val) \
234 SET_BITS_OFFSET_LE(__pdesc+16, 5, 1, __val)
235#define SET_TX_DESC_QOS(__pdesc, __val) \
236 SET_BITS_OFFSET_LE(__pdesc+16, 6, 1, __val)
237#define SET_TX_DESC_HWSEQ_EN(__pdesc, __val) \
238 SET_BITS_OFFSET_LE(__pdesc+16, 7, 1, __val)
239#define SET_TX_DESC_USE_RATE(__pdesc, __val) \
240 SET_BITS_OFFSET_LE(__pdesc+16, 8, 1, __val)
241#define SET_TX_DESC_DISABLE_RTS_FB(__pdesc, __val) \
242 SET_BITS_OFFSET_LE(__pdesc+16, 9, 1, __val)
243#define SET_TX_DESC_DISABLE_FB(__pdesc, __val) \
244 SET_BITS_OFFSET_LE(__pdesc+16, 10, 1, __val)
245#define SET_TX_DESC_CTS2SELF(__pdesc, __val) \
246 SET_BITS_OFFSET_LE(__pdesc+16, 11, 1, __val)
247#define SET_TX_DESC_RTS_ENABLE(__pdesc, __val) \
248 SET_BITS_OFFSET_LE(__pdesc+16, 12, 1, __val)
249#define SET_TX_DESC_HW_RTS_ENABLE(__pdesc, __val) \
250 SET_BITS_OFFSET_LE(__pdesc+16, 13, 1, __val)
251#define SET_TX_DESC_PORT_ID(__pdesc, __val) \
252 SET_BITS_OFFSET_LE(__pdesc+16, 14, 1, __val)
253#define SET_TX_DESC_WAIT_DCTS(__pdesc, __val) \
254 SET_BITS_OFFSET_LE(__pdesc+16, 18, 1, __val)
255#define SET_TX_DESC_CTS2AP_EN(__pdesc, __val) \
256 SET_BITS_OFFSET_LE(__pdesc+16, 19, 1, __val)
257#define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val) \
258 SET_BITS_OFFSET_LE(__pdesc+16, 20, 2, __val)
259#define SET_TX_DESC_TX_STBC(__pdesc, __val) \
260 SET_BITS_OFFSET_LE(__pdesc+16, 22, 2, __val)
261#define SET_TX_DESC_DATA_SHORT(__pdesc, __val) \
262 SET_BITS_OFFSET_LE(__pdesc+16, 24, 1, __val)
263#define SET_TX_DESC_DATA_BW(__pdesc, __val) \
264 SET_BITS_OFFSET_LE(__pdesc+16, 25, 1, __val)
265#define SET_TX_DESC_RTS_SHORT(__pdesc, __val) \
266 SET_BITS_OFFSET_LE(__pdesc+16, 26, 1, __val)
267#define SET_TX_DESC_RTS_BW(__pdesc, __val) \
268 SET_BITS_OFFSET_LE(__pdesc+16, 27, 1, __val)
269#define SET_TX_DESC_RTS_SC(__pdesc, __val) \
270 SET_BITS_OFFSET_LE(__pdesc+16, 28, 2, __val)
271#define SET_TX_DESC_RTS_STBC(__pdesc, __val) \
272 SET_BITS_OFFSET_LE(__pdesc+16, 30, 2, __val)
273
274#define GET_TX_DESC_RTS_RATE(__pdesc) \
275 SHIFT_AND_MASK_LE(__pdesc+16, 0, 5)
276#define GET_TX_DESC_AP_DCFE(__pdesc) \
277 SHIFT_AND_MASK_LE(__pdesc+16, 5, 1)
278#define GET_TX_DESC_QOS(__pdesc) \
279 SHIFT_AND_MASK_LE(__pdesc+16, 6, 1)
280#define GET_TX_DESC_HWSEQ_EN(__pdesc) \
281 SHIFT_AND_MASK_LE(__pdesc+16, 7, 1)
282#define GET_TX_DESC_USE_RATE(__pdesc) \
283 SHIFT_AND_MASK_LE(__pdesc+16, 8, 1)
284#define GET_TX_DESC_DISABLE_RTS_FB(__pdesc) \
285 SHIFT_AND_MASK_LE(__pdesc+16, 9, 1)
286#define GET_TX_DESC_DISABLE_FB(__pdesc) \
287 SHIFT_AND_MASK_LE(__pdesc+16, 10, 1)
288#define GET_TX_DESC_CTS2SELF(__pdesc) \
289 SHIFT_AND_MASK_LE(__pdesc+16, 11, 1)
290#define GET_TX_DESC_RTS_ENABLE(__pdesc) \
291 SHIFT_AND_MASK_LE(__pdesc+16, 12, 1)
292#define GET_TX_DESC_HW_RTS_ENABLE(__pdesc) \
293 SHIFT_AND_MASK_LE(__pdesc+16, 13, 1)
294#define GET_TX_DESC_PORT_ID(__pdesc) \
295 SHIFT_AND_MASK_LE(__pdesc+16, 14, 1)
296#define GET_TX_DESC_WAIT_DCTS(__pdesc) \
297 SHIFT_AND_MASK_LE(__pdesc+16, 18, 1)
298#define GET_TX_DESC_CTS2AP_EN(__pdesc) \
299 SHIFT_AND_MASK_LE(__pdesc+16, 19, 1)
300#define GET_TX_DESC_TX_SUB_CARRIER(__pdesc) \
301 SHIFT_AND_MASK_LE(__pdesc+16, 20, 2)
302#define GET_TX_DESC_TX_STBC(__pdesc) \
303 SHIFT_AND_MASK_LE(__pdesc+16, 22, 2)
304#define GET_TX_DESC_DATA_SHORT(__pdesc) \
305 SHIFT_AND_MASK_LE(__pdesc+16, 24, 1)
306#define GET_TX_DESC_DATA_BW(__pdesc) \
307 SHIFT_AND_MASK_LE(__pdesc+16, 25, 1)
308#define GET_TX_DESC_RTS_SHORT(__pdesc) \
309 SHIFT_AND_MASK_LE(__pdesc+16, 26, 1)
310#define GET_TX_DESC_RTS_BW(__pdesc) \
311 SHIFT_AND_MASK_LE(__pdesc+16, 27, 1)
312#define GET_TX_DESC_RTS_SC(__pdesc) \
313 SHIFT_AND_MASK_LE(__pdesc+16, 28, 2)
314#define GET_TX_DESC_RTS_STBC(__pdesc) \
315 SHIFT_AND_MASK_LE(__pdesc+16, 30, 2)
316
317#define SET_TX_DESC_TX_RATE(__pdesc, __val) \
318 SET_BITS_OFFSET_LE(__pdesc+20, 0, 6, __val)
319#define SET_TX_DESC_DATA_SHORTGI(__pdesc, __val) \
320 SET_BITS_OFFSET_LE(__pdesc+20, 6, 1, __val)
321#define SET_TX_DESC_CCX_TAG(__pdesc, __val) \
322 SET_BITS_OFFSET_LE(__pdesc+20, 7, 1, __val)
323#define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val) \
324 SET_BITS_OFFSET_LE(__pdesc+20, 8, 5, __val)
325#define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val) \
326 SET_BITS_OFFSET_LE(__pdesc+20, 13, 4, __val)
327#define SET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc, __val) \
328 SET_BITS_OFFSET_LE(__pdesc+20, 17, 1, __val)
329#define SET_TX_DESC_DATA_RETRY_LIMIT(__pdesc, __val) \
330 SET_BITS_OFFSET_LE(__pdesc+20, 18, 6, __val)
331#define SET_TX_DESC_USB_TXAGG_NUM(__pdesc, __val) \
332 SET_BITS_OFFSET_LE(__pdesc+20, 24, 8, __val)
333
334#define GET_TX_DESC_TX_RATE(__pdesc) \
335 SHIFT_AND_MASK_LE(__pdesc+20, 0, 6)
336#define GET_TX_DESC_DATA_SHORTGI(__pdesc) \
337 SHIFT_AND_MASK_LE(__pdesc+20, 6, 1)
338#define GET_TX_DESC_CCX_TAG(__pdesc) \
339 SHIFT_AND_MASK_LE(__pdesc+20, 7, 1)
340#define GET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc) \
341 SHIFT_AND_MASK_LE(__pdesc+20, 8, 5)
342#define GET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc) \
343 SHIFT_AND_MASK_LE(__pdesc+20, 13, 4)
344#define GET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc) \
345 SHIFT_AND_MASK_LE(__pdesc+20, 17, 1)
346#define GET_TX_DESC_DATA_RETRY_LIMIT(__pdesc) \
347 SHIFT_AND_MASK_LE(__pdesc+20, 18, 6)
348#define GET_TX_DESC_USB_TXAGG_NUM(__pdesc) \
349 SHIFT_AND_MASK_LE(__pdesc+20, 24, 8)
350
351#define SET_TX_DESC_TXAGC_A(__pdesc, __val) \
352 SET_BITS_OFFSET_LE(__pdesc+24, 0, 5, __val)
353#define SET_TX_DESC_TXAGC_B(__pdesc, __val) \
354 SET_BITS_OFFSET_LE(__pdesc+24, 5, 5, __val)
355#define SET_TX_DESC_USE_MAX_LEN(__pdesc, __val) \
356 SET_BITS_OFFSET_LE(__pdesc+24, 10, 1, __val)
357#define SET_TX_DESC_MAX_AGG_NUM(__pdesc, __val) \
358 SET_BITS_OFFSET_LE(__pdesc+24, 11, 5, __val)
359#define SET_TX_DESC_MCSG1_MAX_LEN(__pdesc, __val) \
360 SET_BITS_OFFSET_LE(__pdesc+24, 16, 4, __val)
361#define SET_TX_DESC_MCSG2_MAX_LEN(__pdesc, __val) \
362 SET_BITS_OFFSET_LE(__pdesc+24, 20, 4, __val)
363#define SET_TX_DESC_MCSG3_MAX_LEN(__pdesc, __val) \
364 SET_BITS_OFFSET_LE(__pdesc+24, 24, 4, __val)
365#define SET_TX_DESC_MCS7_SGI_MAX_LEN(__pdesc, __val) \
366 SET_BITS_OFFSET_LE(__pdesc+24, 28, 4, __val)
367
368#define GET_TX_DESC_TXAGC_A(__pdesc) \
369 SHIFT_AND_MASK_LE(__pdesc+24, 0, 5)
370#define GET_TX_DESC_TXAGC_B(__pdesc) \
371 SHIFT_AND_MASK_LE(__pdesc+24, 5, 5)
372#define GET_TX_DESC_USE_MAX_LEN(__pdesc) \
373 SHIFT_AND_MASK_LE(__pdesc+24, 10, 1)
374#define GET_TX_DESC_MAX_AGG_NUM(__pdesc) \
375 SHIFT_AND_MASK_LE(__pdesc+24, 11, 5)
376#define GET_TX_DESC_MCSG1_MAX_LEN(__pdesc) \
377 SHIFT_AND_MASK_LE(__pdesc+24, 16, 4)
378#define GET_TX_DESC_MCSG2_MAX_LEN(__pdesc) \
379 SHIFT_AND_MASK_LE(__pdesc+24, 20, 4)
380#define GET_TX_DESC_MCSG3_MAX_LEN(__pdesc) \
381 SHIFT_AND_MASK_LE(__pdesc+24, 24, 4)
382#define GET_TX_DESC_MCS7_SGI_MAX_LEN(__pdesc) \
383 SHIFT_AND_MASK_LE(__pdesc+24, 28, 4)
384
385#define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val) \
386 SET_BITS_OFFSET_LE(__pdesc+28, 0, 16, __val)
387#define SET_TX_DESC_MCSG4_MAX_LEN(__pdesc, __val) \
388 SET_BITS_OFFSET_LE(__pdesc+28, 16, 4, __val)
389#define SET_TX_DESC_MCSG5_MAX_LEN(__pdesc, __val) \
390 SET_BITS_OFFSET_LE(__pdesc+28, 20, 4, __val)
391#define SET_TX_DESC_MCSG6_MAX_LEN(__pdesc, __val) \
392 SET_BITS_OFFSET_LE(__pdesc+28, 24, 4, __val)
393#define SET_TX_DESC_MCS15_SGI_MAX_LEN(__pdesc, __val) \
394 SET_BITS_OFFSET_LE(__pdesc+28, 28, 4, __val)
395
396#define GET_TX_DESC_TX_BUFFER_SIZE(__pdesc) \
397 SHIFT_AND_MASK_LE(__pdesc+28, 0, 16)
398#define GET_TX_DESC_MCSG4_MAX_LEN(__pdesc) \
399 SHIFT_AND_MASK_LE(__pdesc+28, 16, 4)
400#define GET_TX_DESC_MCSG5_MAX_LEN(__pdesc) \
401 SHIFT_AND_MASK_LE(__pdesc+28, 20, 4)
402#define GET_TX_DESC_MCSG6_MAX_LEN(__pdesc) \
403 SHIFT_AND_MASK_LE(__pdesc+28, 24, 4)
404#define GET_TX_DESC_MCS15_SGI_MAX_LEN(__pdesc) \
405 SHIFT_AND_MASK_LE(__pdesc+28, 28, 4)
406
407#define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val) \
408 SET_BITS_OFFSET_LE(__pdesc+32, 0, 32, __val)
409#define SET_TX_DESC_TX_BUFFER_ADDRESS64(__pdesc, __val) \
410 SET_BITS_OFFSET_LE(__pdesc+36, 0, 32, __val)
411
412#define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc) \
413 SHIFT_AND_MASK_LE(__pdesc+32, 0, 32)
414#define GET_TX_DESC_TX_BUFFER_ADDRESS64(__pdesc) \
415 SHIFT_AND_MASK_LE(__pdesc+36, 0, 32)
416
417#define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val) \
418 SET_BITS_OFFSET_LE(__pdesc+40, 0, 32, __val)
419#define SET_TX_DESC_NEXT_DESC_ADDRESS64(__pdesc, __val) \
420 SET_BITS_OFFSET_LE(__pdesc+44, 0, 32, __val)
421
422#define GET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc) \
423 SHIFT_AND_MASK_LE(__pdesc+40, 0, 32)
424#define GET_TX_DESC_NEXT_DESC_ADDRESS64(__pdesc) \
425 SHIFT_AND_MASK_LE(__pdesc+44, 0, 32)
426
427#define GET_RX_DESC_PKT_LEN(__pdesc) \
428 SHIFT_AND_MASK_LE(__pdesc, 0, 14)
429#define GET_RX_DESC_CRC32(__pdesc) \
430 SHIFT_AND_MASK_LE(__pdesc, 14, 1)
431#define GET_RX_DESC_ICV(__pdesc) \
432 SHIFT_AND_MASK_LE(__pdesc, 15, 1)
433#define GET_RX_DESC_DRV_INFO_SIZE(__pdesc) \
434 SHIFT_AND_MASK_LE(__pdesc, 16, 4)
435#define GET_RX_DESC_SECURITY(__pdesc) \
436 SHIFT_AND_MASK_LE(__pdesc, 20, 3)
437#define GET_RX_DESC_QOS(__pdesc) \
438 SHIFT_AND_MASK_LE(__pdesc, 23, 1)
439#define GET_RX_DESC_SHIFT(__pdesc) \
440 SHIFT_AND_MASK_LE(__pdesc, 24, 2)
441#define GET_RX_DESC_PHYST(__pdesc) \
442 SHIFT_AND_MASK_LE(__pdesc, 26, 1)
443#define GET_RX_DESC_SWDEC(__pdesc) \
444 SHIFT_AND_MASK_LE(__pdesc, 27, 1)
445#define GET_RX_DESC_LS(__pdesc) \
446 SHIFT_AND_MASK_LE(__pdesc, 28, 1)
447#define GET_RX_DESC_FS(__pdesc) \
448 SHIFT_AND_MASK_LE(__pdesc, 29, 1)
449#define GET_RX_DESC_EOR(__pdesc) \
450 SHIFT_AND_MASK_LE(__pdesc, 30, 1)
451#define GET_RX_DESC_OWN(__pdesc) \
452 SHIFT_AND_MASK_LE(__pdesc, 31, 1)
453
454#define SET_RX_DESC_PKT_LEN(__pdesc, __val) \
455 SET_BITS_OFFSET_LE(__pdesc, 0, 14, __val)
456#define SET_RX_DESC_EOR(__pdesc, __val) \
457 SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val)
458#define SET_RX_DESC_OWN(__pdesc, __val) \
459 SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
460
461#define GET_RX_DESC_MACID(__pdesc) \
462 SHIFT_AND_MASK_LE(__pdesc+4, 0, 5)
463#define GET_RX_DESC_TID(__pdesc) \
464 SHIFT_AND_MASK_LE(__pdesc+4, 5, 4)
465#define GET_RX_DESC_HWRSVD(__pdesc) \
466 SHIFT_AND_MASK_LE(__pdesc+4, 9, 5)
467#define GET_RX_DESC_PAGGR(__pdesc) \
468 SHIFT_AND_MASK_LE(__pdesc+4, 14, 1)
469#define GET_RX_DESC_FAGGR(__pdesc) \
470 SHIFT_AND_MASK_LE(__pdesc+4, 15, 1)
471#define GET_RX_DESC_A1_FIT(__pdesc) \
472 SHIFT_AND_MASK_LE(__pdesc+4, 16, 4)
473#define GET_RX_DESC_A2_FIT(__pdesc) \
474 SHIFT_AND_MASK_LE(__pdesc+4, 20, 4)
475#define GET_RX_DESC_PAM(__pdesc) \
476 SHIFT_AND_MASK_LE(__pdesc+4, 24, 1)
477#define GET_RX_DESC_PWR(__pdesc) \
478 SHIFT_AND_MASK_LE(__pdesc+4, 25, 1)
479#define GET_RX_DESC_MD(__pdesc) \
480 SHIFT_AND_MASK_LE(__pdesc+4, 26, 1)
481#define GET_RX_DESC_MF(__pdesc) \
482 SHIFT_AND_MASK_LE(__pdesc+4, 27, 1)
483#define GET_RX_DESC_TYPE(__pdesc) \
484 SHIFT_AND_MASK_LE(__pdesc+4, 28, 2)
485#define GET_RX_DESC_MC(__pdesc) \
486 SHIFT_AND_MASK_LE(__pdesc+4, 30, 1)
487#define GET_RX_DESC_BC(__pdesc) \
488 SHIFT_AND_MASK_LE(__pdesc+4, 31, 1)
489#define GET_RX_DESC_SEQ(__pdesc) \
490 SHIFT_AND_MASK_LE(__pdesc+8, 0, 12)
491#define GET_RX_DESC_FRAG(__pdesc) \
492 SHIFT_AND_MASK_LE(__pdesc+8, 12, 4)
493#define GET_RX_DESC_NEXT_PKT_LEN(__pdesc) \
494 SHIFT_AND_MASK_LE(__pdesc+8, 16, 14)
495#define GET_RX_DESC_NEXT_IND(__pdesc) \
496 SHIFT_AND_MASK_LE(__pdesc+8, 30, 1)
497#define GET_RX_DESC_RSVD(__pdesc) \
498 SHIFT_AND_MASK_LE(__pdesc+8, 31, 1)
499
500#define GET_RX_DESC_RXMCS(__pdesc) \
501 SHIFT_AND_MASK_LE(__pdesc+12, 0, 6)
502#define GET_RX_DESC_RXHT(__pdesc) \
503 SHIFT_AND_MASK_LE(__pdesc+12, 6, 1)
504#define GET_RX_DESC_SPLCP(__pdesc) \
505 SHIFT_AND_MASK_LE(__pdesc+12, 8, 1)
506#define GET_RX_DESC_BW(__pdesc) \
507 SHIFT_AND_MASK_LE(__pdesc+12, 9, 1)
508#define GET_RX_DESC_HTC(__pdesc) \
509 SHIFT_AND_MASK_LE(__pdesc+12, 10, 1)
510#define GET_RX_DESC_HWPC_ERR(__pdesc) \
511 SHIFT_AND_MASK_LE(__pdesc+12, 14, 1)
512#define GET_RX_DESC_HWPC_IND(__pdesc) \
513 SHIFT_AND_MASK_LE(__pdesc+12, 15, 1)
514#define GET_RX_DESC_IV0(__pdesc) \
515 SHIFT_AND_MASK_LE(__pdesc+12, 16, 16)
516
517#define GET_RX_DESC_IV1(__pdesc) \
518 SHIFT_AND_MASK_LE(__pdesc+16, 0, 32)
519#define GET_RX_DESC_TSFL(__pdesc) \
520 SHIFT_AND_MASK_LE(__pdesc+20, 0, 32)
521
522#define GET_RX_DESC_BUFF_ADDR(__pdesc) \
523 SHIFT_AND_MASK_LE(__pdesc+24, 0, 32)
524#define GET_RX_DESC_BUFF_ADDR64(__pdesc) \
525 SHIFT_AND_MASK_LE(__pdesc+28, 0, 32)
526
527#define SET_RX_DESC_BUFF_ADDR(__pdesc, __val) \
528 SET_BITS_OFFSET_LE(__pdesc+24, 0, 32, __val)
529#define SET_RX_DESC_BUFF_ADDR64(__pdesc, __val) \
530 SET_BITS_OFFSET_LE(__pdesc+28, 0, 32, __val)
531
532#define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \
533do { \
534 if (_size > TX_DESC_NEXT_DESC_OFFSET) \
535 memset((void *)__pdesc, 0, TX_DESC_NEXT_DESC_OFFSET); \
536 else \
537 memset((void *)__pdesc, 0, _size); \
538} while (0);
539
540#define RX_HAL_IS_CCK_RATE(_pdesc)\
541 (_pdesc->rxmcs == DESC92D_RATE1M || \
542 _pdesc->rxmcs == DESC92D_RATE2M || \
543 _pdesc->rxmcs == DESC92D_RATE5_5M || \
544 _pdesc->rxmcs == DESC92D_RATE11M)
545
546/* For 92D early mode */
547#define SET_EARLYMODE_PKTNUM(__paddr, __value) \
548 SET_BITS_OFFSET_LE(__paddr, 0, 3, __value)
549#define SET_EARLYMODE_LEN0(__paddr, __value) \
550 SET_BITS_OFFSET_LE(__paddr, 4, 12, __value)
551#define SET_EARLYMODE_LEN1(__paddr, __value) \
552 SET_BITS_OFFSET_LE(__paddr, 16, 12, __value)
553#define SET_EARLYMODE_LEN2_1(__paddr, __value) \
554 SET_BITS_OFFSET_LE(__paddr, 28, 4, __value)
555#define SET_EARLYMODE_LEN2_2(__paddr, __value) \
556 SET_BITS_OFFSET_LE(__paddr+4, 0, 8, __value)
557#define SET_EARLYMODE_LEN3(__paddr, __value) \
558 SET_BITS_OFFSET_LE(__paddr+4, 8, 12, __value)
559#define SET_EARLYMODE_LEN4(__paddr, __value) \
560 SET_BITS_OFFSET_LE(__paddr+4, 20, 12, __value)
561
562struct rx_fwinfo_92d {
563 u8 gain_trsw[4];
564 u8 pwdb_all;
565 u8 cfosho[4];
566 u8 cfotail[4];
567 char rxevm[2];
568 char rxsnr[4];
569 u8 pdsnr[2];
570 u8 csi_current[2];
571 u8 csi_target[2];
572 u8 sigevm;
573 u8 max_ex_pwr;
574 u8 ex_intf_flag:1;
575 u8 sgi_en:1;
576 u8 rxsc:2;
577 u8 reserve:4;
578} __packed;
579
580struct tx_desc_92d {
581 u32 pktsize:16;
582 u32 offset:8;
583 u32 bmc:1;
584 u32 htc:1;
585 u32 lastseg:1;
586 u32 firstseg:1;
587 u32 linip:1;
588 u32 noacm:1;
589 u32 gf:1;
590 u32 own:1;
591
592 u32 macid:5;
593 u32 agg_en:1;
594 u32 bk:1;
595 u32 rdg_en:1;
596 u32 queuesel:5;
597 u32 rd_nav_ext:1;
598 u32 lsig_txop_en:1;
599 u32 pifs:1;
600 u32 rateid:4;
601 u32 nav_usehdr:1;
602 u32 en_descid:1;
603 u32 sectype:2;
604 u32 pktoffset:8;
605
606 u32 rts_rc:6;
607 u32 data_rc:6;
608 u32 rsvd0:2;
609 u32 bar_retryht:2;
610 u32 rsvd1:1;
611 u32 morefrag:1;
612 u32 raw:1;
613 u32 ccx:1;
614 u32 ampdudensity:3;
615 u32 rsvd2:1;
616 u32 ant_sela:1;
617 u32 ant_selb:1;
618 u32 txant_cck:2;
619 u32 txant_l:2;
620 u32 txant_ht:2;
621
622 u32 nextheadpage:8;
623 u32 tailpage:8;
624 u32 seq:12;
625 u32 pktid:4;
626
627 u32 rtsrate:5;
628 u32 apdcfe:1;
629 u32 qos:1;
630 u32 hwseq_enable:1;
631 u32 userrate:1;
632 u32 dis_rtsfb:1;
633 u32 dis_datafb:1;
634 u32 cts2self:1;
635 u32 rts_en:1;
636 u32 hwrts_en:1;
637 u32 portid:1;
638 u32 rsvd3:3;
639 u32 waitdcts:1;
640 u32 cts2ap_en:1;
641 u32 txsc:2;
642 u32 stbc:2;
643 u32 txshort:1;
644 u32 txbw:1;
645 u32 rtsshort:1;
646 u32 rtsbw:1;
647 u32 rtssc:2;
648 u32 rtsstbc:2;
649
650 u32 txrate:6;
651 u32 shortgi:1;
652 u32 ccxt:1;
653 u32 txrate_fb_lmt:5;
654 u32 rtsrate_fb_lmt:4;
655 u32 retrylmt_en:1;
656 u32 txretrylmt:6;
657 u32 usb_txaggnum:8;
658
659 u32 txagca:5;
660 u32 txagcb:5;
661 u32 usemaxlen:1;
662 u32 maxaggnum:5;
663 u32 mcsg1maxlen:4;
664 u32 mcsg2maxlen:4;
665 u32 mcsg3maxlen:4;
666 u32 mcs7sgimaxlen:4;
667
668 u32 txbuffersize:16;
669 u32 mcsg4maxlen:4;
670 u32 mcsg5maxlen:4;
671 u32 mcsg6maxlen:4;
672 u32 mcsg15sgimaxlen:4;
673
674 u32 txbuffaddr;
675 u32 txbufferaddr64;
676 u32 nextdescaddress;
677 u32 nextdescaddress64;
678
679 u32 reserve_pass_pcie_mm_limit[4];
680} __packed;
681
682struct rx_desc_92d {
683 u32 length:14;
684 u32 crc32:1;
685 u32 icverror:1;
686 u32 drv_infosize:4;
687 u32 security:3;
688 u32 qos:1;
689 u32 shift:2;
690 u32 phystatus:1;
691 u32 swdec:1;
692 u32 lastseg:1;
693 u32 firstseg:1;
694 u32 eor:1;
695 u32 own:1;
696
697 u32 macid:5;
698 u32 tid:4;
699 u32 hwrsvd:5;
700 u32 paggr:1;
701 u32 faggr:1;
702 u32 a1_fit:4;
703 u32 a2_fit:4;
704 u32 pam:1;
705 u32 pwr:1;
706 u32 moredata:1;
707 u32 morefrag:1;
708 u32 type:2;
709 u32 mc:1;
710 u32 bc:1;
711
712 u32 seq:12;
713 u32 frag:4;
714 u32 nextpktlen:14;
715 u32 nextind:1;
716 u32 rsvd:1;
717
718 u32 rxmcs:6;
719 u32 rxht:1;
720 u32 amsdu:1;
721 u32 splcp:1;
722 u32 bandwidth:1;
723 u32 htc:1;
724 u32 tcpchk_rpt:1;
725 u32 ipcchk_rpt:1;
726 u32 tcpchk_valid:1;
727 u32 hwpcerr:1;
728 u32 hwpcind:1;
729 u32 iv0:16;
730
731 u32 iv1;
732
733 u32 tsfl;
734
735 u32 bufferaddress;
736 u32 bufferaddress64;
737
738} __packed;
739
740void rtl92de_tx_fill_desc(struct ieee80211_hw *hw,
741 struct ieee80211_hdr *hdr,
742 u8 *pdesc, struct ieee80211_tx_info *info,
743 struct sk_buff *skb, u8 hw_queue,
744 struct rtl_tcb_desc *ptcb_desc);
745bool rtl92de_rx_query_desc(struct ieee80211_hw *hw,
746 struct rtl_stats *stats,
747 struct ieee80211_rx_status *rx_status,
748 u8 *pdesc, struct sk_buff *skb);
749void rtl92de_set_desc(u8 *pdesc, bool istx, u8 desc_name, u8 *val);
750u32 rtl92de_get_desc(u8 *pdesc, bool istx, u8 desc_name);
751void rtl92de_tx_polling(struct ieee80211_hw *hw, u8 hw_queue);
752void rtl92de_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
753 bool b_firstseg, bool b_lastseg,
754 struct sk_buff *skb);
755
756#endif
diff --git a/drivers/net/wireless/rtlwifi/wifi.h b/drivers/net/wireless/rtlwifi/wifi.h
index 6890e197155b..d3c3ffd38984 100644
--- a/drivers/net/wireless/rtlwifi/wifi.h
+++ b/drivers/net/wireless/rtlwifi/wifi.h
@@ -302,9 +302,6 @@ enum hw_variables {
302 HW_VAR_DATA_FILTER, 302 HW_VAR_DATA_FILTER,
303}; 303};
304 304
305#define HWSET_MAX_SIZE 128
306#define EFUSE_MAX_SECTION 16
307
308enum _RT_MEDIA_STATUS { 305enum _RT_MEDIA_STATUS {
309 RT_MEDIA_DISCONNECT = 0, 306 RT_MEDIA_DISCONNECT = 0,
310 RT_MEDIA_CONNECT = 1 307 RT_MEDIA_CONNECT = 1
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-16 12:00:39 -0500