diff options
Diffstat (limited to 'drivers/net/wireless/rtlwifi/rtl8192de/sw.c')
-rw-r--r-- | drivers/net/wireless/rtlwifi/rtl8192de/sw.c | 423 |
1 files changed, 423 insertions, 0 deletions
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/sw.c b/drivers/net/wireless/rtlwifi/rtl8192de/sw.c new file mode 100644 index 000000000000..08837744f6f1 --- /dev/null +++ b/drivers/net/wireless/rtlwifi/rtl8192de/sw.c | |||
@@ -0,0 +1,423 @@ | |||
1 | /****************************************************************************** | ||
2 | * | ||
3 | * Copyright(c) 2009-2010 Realtek Corporation. | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify it | ||
6 | * under the terms of version 2 of the GNU General Public License as | ||
7 | * published by the Free Software Foundation. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
12 | * more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License along with | ||
15 | * this program; if not, write to the Free Software Foundation, Inc., | ||
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | ||
17 | * | ||
18 | * The full GNU General Public License is included in this distribution in the | ||
19 | * file called LICENSE. | ||
20 | * | ||
21 | * Contact Information: | ||
22 | * wlanfae <wlanfae@realtek.com> | ||
23 | * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, | ||
24 | * Hsinchu 300, Taiwan. | ||
25 | * | ||
26 | * Larry Finger <Larry.Finger@lwfinger.net> | ||
27 | * | ||
28 | *****************************************************************************/ | ||
29 | |||
30 | #include <linux/vmalloc.h> | ||
31 | |||
32 | #include "../wifi.h" | ||
33 | #include "../core.h" | ||
34 | #include "../pci.h" | ||
35 | #include "reg.h" | ||
36 | #include "def.h" | ||
37 | #include "phy.h" | ||
38 | #include "dm.h" | ||
39 | #include "hw.h" | ||
40 | #include "sw.h" | ||
41 | #include "trx.h" | ||
42 | #include "led.h" | ||
43 | |||
44 | static void rtl92d_init_aspm_vars(struct ieee80211_hw *hw) | ||
45 | { | ||
46 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | ||
47 | |||
48 | /*close ASPM for AMD defaultly */ | ||
49 | rtlpci->const_amdpci_aspm = 0; | ||
50 | |||
51 | /* | ||
52 | * ASPM PS mode. | ||
53 | * 0 - Disable ASPM, | ||
54 | * 1 - Enable ASPM without Clock Req, | ||
55 | * 2 - Enable ASPM with Clock Req, | ||
56 | * 3 - Alwyas Enable ASPM with Clock Req, | ||
57 | * 4 - Always Enable ASPM without Clock Req. | ||
58 | * set defult to RTL8192CE:3 RTL8192E:2 | ||
59 | * */ | ||
60 | rtlpci->const_pci_aspm = 3; | ||
61 | |||
62 | /*Setting for PCI-E device */ | ||
63 | rtlpci->const_devicepci_aspm_setting = 0x03; | ||
64 | |||
65 | /*Setting for PCI-E bridge */ | ||
66 | rtlpci->const_hostpci_aspm_setting = 0x02; | ||
67 | |||
68 | /* | ||
69 | * In Hw/Sw Radio Off situation. | ||
70 | * 0 - Default, | ||
71 | * 1 - From ASPM setting without low Mac Pwr, | ||
72 | * 2 - From ASPM setting with low Mac Pwr, | ||
73 | * 3 - Bus D3 | ||
74 | * set default to RTL8192CE:0 RTL8192SE:2 | ||
75 | */ | ||
76 | rtlpci->const_hwsw_rfoff_d3 = 0; | ||
77 | |||
78 | /* | ||
79 | * This setting works for those device with | ||
80 | * backdoor ASPM setting such as EPHY setting. | ||
81 | * 0 - Not support ASPM, | ||
82 | * 1 - Support ASPM, | ||
83 | * 2 - According to chipset. | ||
84 | */ | ||
85 | rtlpci->const_support_pciaspm = 1; | ||
86 | } | ||
87 | |||
88 | static int rtl92d_init_sw_vars(struct ieee80211_hw *hw) | ||
89 | { | ||
90 | int err; | ||
91 | u8 tid; | ||
92 | struct rtl_priv *rtlpriv = rtl_priv(hw); | ||
93 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | ||
94 | const struct firmware *firmware; | ||
95 | static int header_print; | ||
96 | |||
97 | rtlpriv->dm.dm_initialgain_enable = true; | ||
98 | rtlpriv->dm.dm_flag = 0; | ||
99 | rtlpriv->dm.disable_framebursting = 0; | ||
100 | rtlpriv->dm.thermalvalue = 0; | ||
101 | rtlpriv->dm.useramask = 1; | ||
102 | |||
103 | /* dual mac */ | ||
104 | if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) | ||
105 | rtlpriv->phy.current_channel = 36; | ||
106 | else | ||
107 | rtlpriv->phy.current_channel = 1; | ||
108 | |||
109 | if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) { | ||
110 | rtlpriv->rtlhal.disable_amsdu_8k = true; | ||
111 | /* No long RX - reduce fragmentation */ | ||
112 | rtlpci->rxbuffersize = 4096; | ||
113 | } | ||
114 | |||
115 | rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13); | ||
116 | |||
117 | rtlpci->receive_config = ( | ||
118 | RCR_APPFCS | ||
119 | | RCR_AMF | ||
120 | | RCR_ADF | ||
121 | | RCR_APP_MIC | ||
122 | | RCR_APP_ICV | ||
123 | | RCR_AICV | ||
124 | | RCR_ACRC32 | ||
125 | | RCR_AB | ||
126 | | RCR_AM | ||
127 | | RCR_APM | ||
128 | | RCR_APP_PHYST_RXFF | ||
129 | | RCR_HTC_LOC_CTRL | ||
130 | ); | ||
131 | |||
132 | rtlpci->irq_mask[0] = (u32) ( | ||
133 | IMR_ROK | ||
134 | | IMR_VODOK | ||
135 | | IMR_VIDOK | ||
136 | | IMR_BEDOK | ||
137 | | IMR_BKDOK | ||
138 | | IMR_MGNTDOK | ||
139 | | IMR_HIGHDOK | ||
140 | | IMR_BDOK | ||
141 | | IMR_RDU | ||
142 | | IMR_RXFOVW | ||
143 | ); | ||
144 | |||
145 | rtlpci->irq_mask[1] = (u32) (IMR_CPWM | IMR_C2HCMD); | ||
146 | |||
147 | /* for LPS & IPS */ | ||
148 | rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps; | ||
149 | rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps; | ||
150 | rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps; | ||
151 | rtlpriv->psc.reg_fwctrl_lps = 3; | ||
152 | rtlpriv->psc.reg_max_lps_awakeintvl = 5; | ||
153 | /* for ASPM, you can close aspm through | ||
154 | * set const_support_pciaspm = 0 */ | ||
155 | rtl92d_init_aspm_vars(hw); | ||
156 | |||
157 | if (rtlpriv->psc.reg_fwctrl_lps == 1) | ||
158 | rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE; | ||
159 | else if (rtlpriv->psc.reg_fwctrl_lps == 2) | ||
160 | rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE; | ||
161 | else if (rtlpriv->psc.reg_fwctrl_lps == 3) | ||
162 | rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE; | ||
163 | |||
164 | /* for firmware buf */ | ||
165 | rtlpriv->rtlhal.pfirmware = vzalloc(0x8000); | ||
166 | if (!rtlpriv->rtlhal.pfirmware) { | ||
167 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | ||
168 | ("Can't alloc buffer for fw.\n")); | ||
169 | return 1; | ||
170 | } | ||
171 | |||
172 | if (!header_print) { | ||
173 | printk(KERN_INFO "rtl8192de: Driver for Realtek RTL8192DE" | ||
174 | " WLAN interface"); | ||
175 | printk(KERN_INFO "rtl8192de: Loading firmware file %s\n", | ||
176 | rtlpriv->cfg->fw_name); | ||
177 | header_print++; | ||
178 | } | ||
179 | /* request fw */ | ||
180 | err = request_firmware(&firmware, rtlpriv->cfg->fw_name, | ||
181 | rtlpriv->io.dev); | ||
182 | if (err) { | ||
183 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | ||
184 | ("Failed to request firmware!\n")); | ||
185 | return 1; | ||
186 | } | ||
187 | if (firmware->size > 0x8000) { | ||
188 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | ||
189 | ("Firmware is too big!\n")); | ||
190 | release_firmware(firmware); | ||
191 | return 1; | ||
192 | } | ||
193 | memcpy(rtlpriv->rtlhal.pfirmware, firmware->data, firmware->size); | ||
194 | rtlpriv->rtlhal.fwsize = firmware->size; | ||
195 | release_firmware(firmware); | ||
196 | |||
197 | /* for early mode */ | ||
198 | rtlpriv->rtlhal.earlymode_enable = true; | ||
199 | for (tid = 0; tid < 8; tid++) | ||
200 | skb_queue_head_init(&rtlpriv->mac80211.skb_waitq[tid]); | ||
201 | return 0; | ||
202 | } | ||
203 | |||
204 | static void rtl92d_deinit_sw_vars(struct ieee80211_hw *hw) | ||
205 | { | ||
206 | struct rtl_priv *rtlpriv = rtl_priv(hw); | ||
207 | u8 tid; | ||
208 | |||
209 | if (rtlpriv->rtlhal.pfirmware) { | ||
210 | vfree(rtlpriv->rtlhal.pfirmware); | ||
211 | rtlpriv->rtlhal.pfirmware = NULL; | ||
212 | } | ||
213 | for (tid = 0; tid < 8; tid++) | ||
214 | skb_queue_purge(&rtlpriv->mac80211.skb_waitq[tid]); | ||
215 | } | ||
216 | |||
217 | static struct rtl_hal_ops rtl8192de_hal_ops = { | ||
218 | .init_sw_vars = rtl92d_init_sw_vars, | ||
219 | .deinit_sw_vars = rtl92d_deinit_sw_vars, | ||
220 | .read_eeprom_info = rtl92de_read_eeprom_info, | ||
221 | .interrupt_recognized = rtl92de_interrupt_recognized, | ||
222 | .hw_init = rtl92de_hw_init, | ||
223 | .hw_disable = rtl92de_card_disable, | ||
224 | .hw_suspend = rtl92de_suspend, | ||
225 | .hw_resume = rtl92de_resume, | ||
226 | .enable_interrupt = rtl92de_enable_interrupt, | ||
227 | .disable_interrupt = rtl92de_disable_interrupt, | ||
228 | .set_network_type = rtl92de_set_network_type, | ||
229 | .set_chk_bssid = rtl92de_set_check_bssid, | ||
230 | .set_qos = rtl92de_set_qos, | ||
231 | .set_bcn_reg = rtl92de_set_beacon_related_registers, | ||
232 | .set_bcn_intv = rtl92de_set_beacon_interval, | ||
233 | .update_interrupt_mask = rtl92de_update_interrupt_mask, | ||
234 | .get_hw_reg = rtl92de_get_hw_reg, | ||
235 | .set_hw_reg = rtl92de_set_hw_reg, | ||
236 | .update_rate_tbl = rtl92de_update_hal_rate_tbl, | ||
237 | .fill_tx_desc = rtl92de_tx_fill_desc, | ||
238 | .fill_tx_cmddesc = rtl92de_tx_fill_cmddesc, | ||
239 | .query_rx_desc = rtl92de_rx_query_desc, | ||
240 | .set_channel_access = rtl92de_update_channel_access_setting, | ||
241 | .radio_onoff_checking = rtl92de_gpio_radio_on_off_checking, | ||
242 | .set_bw_mode = rtl92d_phy_set_bw_mode, | ||
243 | .switch_channel = rtl92d_phy_sw_chnl, | ||
244 | .dm_watchdog = rtl92d_dm_watchdog, | ||
245 | .scan_operation_backup = rtl92d_phy_scan_operation_backup, | ||
246 | .set_rf_power_state = rtl92d_phy_set_rf_power_state, | ||
247 | .led_control = rtl92de_led_control, | ||
248 | .set_desc = rtl92de_set_desc, | ||
249 | .get_desc = rtl92de_get_desc, | ||
250 | .tx_polling = rtl92de_tx_polling, | ||
251 | .enable_hw_sec = rtl92de_enable_hw_security_config, | ||
252 | .set_key = rtl92de_set_key, | ||
253 | .init_sw_leds = rtl92de_init_sw_leds, | ||
254 | .get_bbreg = rtl92d_phy_query_bb_reg, | ||
255 | .set_bbreg = rtl92d_phy_set_bb_reg, | ||
256 | .get_rfreg = rtl92d_phy_query_rf_reg, | ||
257 | .set_rfreg = rtl92d_phy_set_rf_reg, | ||
258 | .linked_set_reg = rtl92d_linked_set_reg, | ||
259 | }; | ||
260 | |||
261 | static struct rtl_mod_params rtl92de_mod_params = { | ||
262 | .sw_crypto = false, | ||
263 | .inactiveps = true, | ||
264 | .swctrl_lps = true, | ||
265 | .fwctrl_lps = false, | ||
266 | }; | ||
267 | |||
268 | static struct rtl_hal_cfg rtl92de_hal_cfg = { | ||
269 | .bar_id = 2, | ||
270 | .write_readback = true, | ||
271 | .name = "rtl8192de", | ||
272 | .fw_name = "rtlwifi/rtl8192defw.bin", | ||
273 | .ops = &rtl8192de_hal_ops, | ||
274 | .mod_params = &rtl92de_mod_params, | ||
275 | |||
276 | .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL, | ||
277 | .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN, | ||
278 | .maps[SYS_CLK] = REG_SYS_CLKR, | ||
279 | .maps[MAC_RCR_AM] = RCR_AM, | ||
280 | .maps[MAC_RCR_AB] = RCR_AB, | ||
281 | .maps[MAC_RCR_ACRC32] = RCR_ACRC32, | ||
282 | .maps[MAC_RCR_ACF] = RCR_ACF, | ||
283 | .maps[MAC_RCR_AAP] = RCR_AAP, | ||
284 | |||
285 | .maps[EFUSE_TEST] = REG_EFUSE_TEST, | ||
286 | .maps[EFUSE_CTRL] = REG_EFUSE_CTRL, | ||
287 | .maps[EFUSE_CLK] = 0, /* just for 92se */ | ||
288 | .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL, | ||
289 | .maps[EFUSE_PWC_EV12V] = PWC_EV12V, | ||
290 | .maps[EFUSE_FEN_ELDR] = FEN_ELDR, | ||
291 | .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN, | ||
292 | .maps[EFUSE_ANA8M] = 0, /* just for 92se */ | ||
293 | .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE, | ||
294 | .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION, | ||
295 | .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN, | ||
296 | |||
297 | .maps[RWCAM] = REG_CAMCMD, | ||
298 | .maps[WCAMI] = REG_CAMWRITE, | ||
299 | .maps[RCAMO] = REG_CAMREAD, | ||
300 | .maps[CAMDBG] = REG_CAMDBG, | ||
301 | .maps[SECR] = REG_SECCFG, | ||
302 | .maps[SEC_CAM_NONE] = CAM_NONE, | ||
303 | .maps[SEC_CAM_WEP40] = CAM_WEP40, | ||
304 | .maps[SEC_CAM_TKIP] = CAM_TKIP, | ||
305 | .maps[SEC_CAM_AES] = CAM_AES, | ||
306 | .maps[SEC_CAM_WEP104] = CAM_WEP104, | ||
307 | |||
308 | .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6, | ||
309 | .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5, | ||
310 | .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4, | ||
311 | .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3, | ||
312 | .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2, | ||
313 | .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1, | ||
314 | .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8, | ||
315 | .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7, | ||
316 | .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6, | ||
317 | .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5, | ||
318 | .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4, | ||
319 | .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3, | ||
320 | .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2, | ||
321 | .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1, | ||
322 | .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2, | ||
323 | .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1, | ||
324 | |||
325 | .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW, | ||
326 | .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT, | ||
327 | .maps[RTL_IMR_BcnInt] = IMR_BcnInt, | ||
328 | .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW, | ||
329 | .maps[RTL_IMR_RDU] = IMR_RDU, | ||
330 | .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND, | ||
331 | .maps[RTL_IMR_BDOK] = IMR_BDOK, | ||
332 | .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK, | ||
333 | .maps[RTL_IMR_TBDER] = IMR_TBDER, | ||
334 | .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK, | ||
335 | .maps[RTL_IMR_TBDOK] = IMR_TBDOK, | ||
336 | .maps[RTL_IMR_BKDOK] = IMR_BKDOK, | ||
337 | .maps[RTL_IMR_BEDOK] = IMR_BEDOK, | ||
338 | .maps[RTL_IMR_VIDOK] = IMR_VIDOK, | ||
339 | .maps[RTL_IMR_VODOK] = IMR_VODOK, | ||
340 | .maps[RTL_IMR_ROK] = IMR_ROK, | ||
341 | .maps[RTL_IBSS_INT_MASKS] = (IMR_BcnInt | IMR_TBDOK | IMR_TBDER), | ||
342 | |||
343 | .maps[RTL_RC_CCK_RATE1M] = DESC92D_RATE1M, | ||
344 | .maps[RTL_RC_CCK_RATE2M] = DESC92D_RATE2M, | ||
345 | .maps[RTL_RC_CCK_RATE5_5M] = DESC92D_RATE5_5M, | ||
346 | .maps[RTL_RC_CCK_RATE11M] = DESC92D_RATE11M, | ||
347 | .maps[RTL_RC_OFDM_RATE6M] = DESC92D_RATE6M, | ||
348 | .maps[RTL_RC_OFDM_RATE9M] = DESC92D_RATE9M, | ||
349 | .maps[RTL_RC_OFDM_RATE12M] = DESC92D_RATE12M, | ||
350 | .maps[RTL_RC_OFDM_RATE18M] = DESC92D_RATE18M, | ||
351 | .maps[RTL_RC_OFDM_RATE24M] = DESC92D_RATE24M, | ||
352 | .maps[RTL_RC_OFDM_RATE36M] = DESC92D_RATE36M, | ||
353 | .maps[RTL_RC_OFDM_RATE48M] = DESC92D_RATE48M, | ||
354 | .maps[RTL_RC_OFDM_RATE54M] = DESC92D_RATE54M, | ||
355 | |||
356 | .maps[RTL_RC_HT_RATEMCS7] = DESC92D_RATEMCS7, | ||
357 | .maps[RTL_RC_HT_RATEMCS15] = DESC92D_RATEMCS15, | ||
358 | }; | ||
359 | |||
360 | static struct pci_device_id rtl92de_pci_ids[] __devinitdata = { | ||
361 | {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8193, rtl92de_hal_cfg)}, | ||
362 | {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x002B, rtl92de_hal_cfg)}, | ||
363 | {}, | ||
364 | }; | ||
365 | |||
366 | MODULE_DEVICE_TABLE(pci, rtl92de_pci_ids); | ||
367 | |||
368 | MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>"); | ||
369 | MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>"); | ||
370 | MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>"); | ||
371 | MODULE_LICENSE("GPL"); | ||
372 | MODULE_DESCRIPTION("Realtek 8192DE 802.11n Dual Mac PCI wireless"); | ||
373 | MODULE_FIRMWARE("rtlwifi/rtl8192defw.bin"); | ||
374 | |||
375 | module_param_named(swenc, rtl92de_mod_params.sw_crypto, bool, 0444); | ||
376 | module_param_named(ips, rtl92de_mod_params.inactiveps, bool, 0444); | ||
377 | module_param_named(swlps, rtl92de_mod_params.swctrl_lps, bool, 0444); | ||
378 | module_param_named(fwlps, rtl92de_mod_params.fwctrl_lps, bool, 0444); | ||
379 | MODULE_PARM_DESC(swenc, "using hardware crypto (default 0 [hardware])\n"); | ||
380 | MODULE_PARM_DESC(ips, "using no link power save (default 1 is open)\n"); | ||
381 | MODULE_PARM_DESC(swlps, "using linked sw control power save (default 1" | ||
382 | " is open)\n"); | ||
383 | |||
384 | static struct pci_driver rtl92de_driver = { | ||
385 | .name = KBUILD_MODNAME, | ||
386 | .id_table = rtl92de_pci_ids, | ||
387 | .probe = rtl_pci_probe, | ||
388 | .remove = rtl_pci_disconnect, | ||
389 | |||
390 | #ifdef CONFIG_PM | ||
391 | .suspend = rtl_pci_suspend, | ||
392 | .resume = rtl_pci_resume, | ||
393 | #endif | ||
394 | |||
395 | }; | ||
396 | |||
397 | /* add global spin lock to solve the problem that | ||
398 | * Dul mac register operation on the same time */ | ||
399 | spinlock_t globalmutex_power; | ||
400 | spinlock_t globalmutex_for_fwdownload; | ||
401 | spinlock_t globalmutex_for_power_and_efuse; | ||
402 | |||
403 | static int __init rtl92de_module_init(void) | ||
404 | { | ||
405 | int ret = 0; | ||
406 | |||
407 | spin_lock_init(&globalmutex_power); | ||
408 | spin_lock_init(&globalmutex_for_fwdownload); | ||
409 | spin_lock_init(&globalmutex_for_power_and_efuse); | ||
410 | |||
411 | ret = pci_register_driver(&rtl92de_driver); | ||
412 | if (ret) | ||
413 | RT_ASSERT(false, (": No device found\n")); | ||
414 | return ret; | ||
415 | } | ||
416 | |||
417 | static void __exit rtl92de_module_exit(void) | ||
418 | { | ||
419 | pci_unregister_driver(&rtl92de_driver); | ||
420 | } | ||
421 | |||
422 | module_init(rtl92de_module_init); | ||
423 | module_exit(rtl92de_module_exit); | ||