diff options
Diffstat (limited to 'drivers/net/wireless/rtlwifi/rtl8723ae/reg.h')
| -rw-r--r-- | drivers/net/wireless/rtlwifi/rtl8723ae/reg.h | 2718 |
1 files changed, 1378 insertions, 1340 deletions
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/reg.h b/drivers/net/wireless/rtlwifi/rtl8723ae/reg.h index ce2c66fd9eee..306059f9b9cc 100644 --- a/drivers/net/wireless/rtlwifi/rtl8723ae/reg.h +++ b/drivers/net/wireless/rtlwifi/rtl8723ae/reg.h | |||
| @@ -11,10 +11,6 @@ | |||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 12 | * more details. | 12 | * more details. |
| 13 | * | 13 | * |
| 14 | * You should have received a copy of the GNU General Public License along with | ||
| 15 | * this program; if not, write to the Free Software Foundation, Inc., | ||
| 16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | ||
| 17 | * | ||
| 18 | * The full GNU General Public License is included in this distribution in the | 14 | * The full GNU General Public License is included in this distribution in the |
| 19 | * file called LICENSE. | 15 | * file called LICENSE. |
| 20 | * | 16 | * |
| @@ -34,13 +30,13 @@ | |||
| 34 | #define REG_SYS_FUNC_EN 0x0002 | 30 | #define REG_SYS_FUNC_EN 0x0002 |
| 35 | #define REG_APS_FSMCO 0x0004 | 31 | #define REG_APS_FSMCO 0x0004 |
| 36 | #define REG_SYS_CLKR 0x0008 | 32 | #define REG_SYS_CLKR 0x0008 |
| 37 | #define REG_9346CR 0x000A | 33 | #define REG_9346CR 0x000A |
| 38 | #define REG_EE_VPD 0x000C | 34 | #define REG_EE_VPD 0x000C |
| 39 | #define REG_AFE_MISC 0x0010 | 35 | #define REG_AFE_MISC 0x0010 |
| 40 | #define REG_SPS0_CTRL 0x0011 | 36 | #define REG_SPS0_CTRL 0x0011 |
| 41 | #define REG_SPS_OCP_CFG 0x0018 | 37 | #define REG_SPS_OCP_CFG 0x0018 |
| 42 | #define REG_RSV_CTRL 0x001C | 38 | #define REG_RSV_CTRL 0x001C |
| 43 | #define REG_RF_CTRL 0x001F | 39 | #define REG_RF_CTRL 0x001F |
| 44 | #define REG_LDOA15_CTRL 0x0020 | 40 | #define REG_LDOA15_CTRL 0x0020 |
| 45 | #define REG_LDOV12D_CTRL 0x0021 | 41 | #define REG_LDOV12D_CTRL 0x0021 |
| 46 | #define REG_LDOHCI12_CTRL 0x0022 | 42 | #define REG_LDOHCI12_CTRL 0x0022 |
| @@ -57,12 +53,12 @@ | |||
| 57 | #define REG_MAC_PINMUX_CFG 0x0043 | 53 | #define REG_MAC_PINMUX_CFG 0x0043 |
| 58 | #define REG_GPIO_PIN_CTRL 0x0044 | 54 | #define REG_GPIO_PIN_CTRL 0x0044 |
| 59 | #define REG_GPIO_INTM 0x0048 | 55 | #define REG_GPIO_INTM 0x0048 |
| 60 | #define REG_LEDCFG0 0x004C | 56 | #define REG_LEDCFG0 0x004C |
| 61 | #define REG_LEDCFG1 0x004D | 57 | #define REG_LEDCFG1 0x004D |
| 62 | #define REG_LEDCFG2 0x004E | 58 | #define REG_LEDCFG2 0x004E |
| 63 | #define REG_LEDCFG3 0x004F | 59 | #define REG_LEDCFG3 0x004F |
| 64 | #define REG_FSIMR 0x0050 | 60 | #define REG_FSIMR 0x0050 |
| 65 | #define REG_FSISR 0x0054 | 61 | #define REG_FSISR 0x0054 |
| 66 | #define REG_GPIO_PIN_CTRL_2 0x0060 | 62 | #define REG_GPIO_PIN_CTRL_2 0x0060 |
| 67 | #define REG_GPIO_IO_SEL_2 0x0062 | 63 | #define REG_GPIO_IO_SEL_2 0x0062 |
| 68 | #define REG_MULTI_FUNC_CTRL 0x0068 | 64 | #define REG_MULTI_FUNC_CTRL 0x0068 |
| @@ -80,25 +76,25 @@ | |||
| 80 | #define REG_USB_SIE_INTF 0x00E0 | 76 | #define REG_USB_SIE_INTF 0x00E0 |
| 81 | #define REG_PCIE_MIO_INTF 0x00E4 | 77 | #define REG_PCIE_MIO_INTF 0x00E4 |
| 82 | #define REG_PCIE_MIO_INTD 0x00E8 | 78 | #define REG_PCIE_MIO_INTD 0x00E8 |
| 83 | #define REG_SYS_CFG 0x00F0 | 79 | #define REG_SYS_CFG 0x00F0 |
| 84 | #define REG_GPIO_OUTSTS 0x00F4 | 80 | #define REG_GPIO_OUTSTS 0x00F4 |
| 85 | 81 | ||
| 86 | #define REG_CR 0x0100 | 82 | #define REG_CR 0x0100 |
| 87 | #define REG_PBP 0x0104 | 83 | #define REG_PBP 0x0104 |
| 88 | #define REG_TRXDMA_CTRL 0x010C | 84 | #define REG_TRXDMA_CTRL 0x010C |
| 89 | #define REG_TRXFF_BNDY 0x0114 | 85 | #define REG_TRXFF_BNDY 0x0114 |
| 90 | #define REG_TRXFF_STATUS 0x0118 | 86 | #define REG_TRXFF_STATUS 0x0118 |
| 91 | #define REG_RXFF_PTR 0x011C | 87 | #define REG_RXFF_PTR 0x011C |
| 92 | #define REG_HIMR 0x0120 | 88 | #define REG_HIMR 0x0120 |
| 93 | #define REG_HISR 0x0124 | 89 | #define REG_HISR 0x0124 |
| 94 | #define REG_HIMRE 0x0128 | 90 | #define REG_HIMRE 0x0128 |
| 95 | #define REG_HISRE 0x012C | 91 | #define REG_HISRE 0x012C |
| 96 | #define REG_CPWM 0x012F | 92 | #define REG_CPWM 0x012F |
| 97 | #define REG_FWIMR 0x0130 | 93 | #define REG_FWIMR 0x0130 |
| 98 | #define REG_FWISR 0x0134 | 94 | #define REG_FWISR 0x0134 |
| 99 | #define REG_PKTBUF_DBG_CTRL 0x0140 | 95 | #define REG_PKTBUF_DBG_CTRL 0x0140 |
| 100 | #define REG_PKTBUF_DBG_DATA_L 0x0144 | 96 | #define REG_PKTBUF_DBG_DATA_L 0x0144 |
| 101 | #define REG_PKTBUF_DBG_DATA_H 0x0148 | 97 | #define REG_PKTBUF_DBG_DATA_H 0x0148 |
| 102 | 98 | ||
| 103 | #define REG_TC0_CTRL 0x0150 | 99 | #define REG_TC0_CTRL 0x0150 |
| 104 | #define REG_TC1_CTRL 0x0154 | 100 | #define REG_TC1_CTRL 0x0154 |
| @@ -109,11 +105,11 @@ | |||
| 109 | #define REG_MBIST_START 0x0174 | 105 | #define REG_MBIST_START 0x0174 |
| 110 | #define REG_MBIST_DONE 0x0178 | 106 | #define REG_MBIST_DONE 0x0178 |
| 111 | #define REG_MBIST_FAIL 0x017C | 107 | #define REG_MBIST_FAIL 0x017C |
| 112 | #define REG_C2HEVT_MSG_NORMAL 0x01A0 | 108 | #define REG_C2HEVT_MSG_NORMAL 0x01A0 |
| 113 | #define REG_C2HEVT_MSG_TEST 0x01B8 | 109 | #define REG_C2HEVT_MSG_TEST 0x01B8 |
| 114 | #define REG_MCUTST_1 0x01c0 | 110 | #define REG_MCUTST_1 0x01c0 |
| 115 | #define REG_FMETHR 0x01C8 | 111 | #define REG_FMETHR 0x01C8 |
| 116 | #define REG_HMETFR 0x01CC | 112 | #define REG_HMETFR 0x01CC |
| 117 | #define REG_HMEBOX_0 0x01D0 | 113 | #define REG_HMEBOX_0 0x01D0 |
| 118 | #define REG_HMEBOX_1 0x01D4 | 114 | #define REG_HMEBOX_1 0x01D4 |
| 119 | #define REG_HMEBOX_2 0x01D8 | 115 | #define REG_HMEBOX_2 0x01D8 |
| @@ -123,10 +119,10 @@ | |||
| 123 | #define REG_BB_ACCEESS_CTRL 0x01E8 | 119 | #define REG_BB_ACCEESS_CTRL 0x01E8 |
| 124 | #define REG_BB_ACCESS_DATA 0x01EC | 120 | #define REG_BB_ACCESS_DATA 0x01EC |
| 125 | 121 | ||
| 126 | #define REG_RQPN 0x0200 | 122 | #define REG_RQPN 0x0200 |
| 127 | #define REG_FIFOPAGE 0x0204 | 123 | #define REG_FIFOPAGE 0x0204 |
| 128 | #define REG_TDECTRL 0x0208 | 124 | #define REG_TDECTRL 0x0208 |
| 129 | #define REG_TXDMA_OFFSET_CHK 0x020C | 125 | #define REG_TXDMA_OFFSET_CHK 0x020C |
| 130 | #define REG_TXDMA_STATUS 0x0210 | 126 | #define REG_TXDMA_STATUS 0x0210 |
| 131 | #define REG_RQPN_NPQ 0x0214 | 127 | #define REG_RQPN_NPQ 0x0214 |
| 132 | 128 | ||
| @@ -135,18 +131,18 @@ | |||
| 135 | #define REG_RXDMA_STATUS 0x0288 | 131 | #define REG_RXDMA_STATUS 0x0288 |
| 136 | 132 | ||
| 137 | #define REG_PCIE_CTRL_REG 0x0300 | 133 | #define REG_PCIE_CTRL_REG 0x0300 |
| 138 | #define REG_INT_MIG 0x0304 | 134 | #define REG_INT_MIG 0x0304 |
| 139 | #define REG_BCNQ_DESA 0x0308 | 135 | #define REG_BCNQ_DESA 0x0308 |
| 140 | #define REG_HQ_DESA 0x0310 | 136 | #define REG_HQ_DESA 0x0310 |
| 141 | #define REG_MGQ_DESA 0x0318 | 137 | #define REG_MGQ_DESA 0x0318 |
| 142 | #define REG_VOQ_DESA 0x0320 | 138 | #define REG_VOQ_DESA 0x0320 |
| 143 | #define REG_VIQ_DESA 0x0328 | 139 | #define REG_VIQ_DESA 0x0328 |
| 144 | #define REG_BEQ_DESA 0x0330 | 140 | #define REG_BEQ_DESA 0x0330 |
| 145 | #define REG_BKQ_DESA 0x0338 | 141 | #define REG_BKQ_DESA 0x0338 |
| 146 | #define REG_RX_DESA 0x0340 | 142 | #define REG_RX_DESA 0x0340 |
| 147 | #define REG_DBI 0x0348 | 143 | #define REG_DBI 0x0348 |
| 148 | #define REG_MDIO 0x0354 | 144 | #define REG_MDIO 0x0354 |
| 149 | #define REG_DBG_SEL 0x0360 | 145 | #define REG_DBG_SEL 0x0360 |
| 150 | #define REG_PCIE_HRPWM 0x0361 | 146 | #define REG_PCIE_HRPWM 0x0361 |
| 151 | #define REG_PCIE_HCPWM 0x0363 | 147 | #define REG_PCIE_HCPWM 0x0363 |
| 152 | #define REG_UART_CTRL 0x0364 | 148 | #define REG_UART_CTRL 0x0364 |
| @@ -162,31 +158,31 @@ | |||
| 162 | #define REG_BKQ_INFORMATION 0x040C | 158 | #define REG_BKQ_INFORMATION 0x040C |
| 163 | #define REG_MGQ_INFORMATION 0x0410 | 159 | #define REG_MGQ_INFORMATION 0x0410 |
| 164 | #define REG_HGQ_INFORMATION 0x0414 | 160 | #define REG_HGQ_INFORMATION 0x0414 |
| 165 | #define REG_BCNQ_INFORMATION 0x0418 | 161 | #define REG_BCNQ_INFORMATION 0x0418 |
| 166 | 162 | ||
| 167 | #define REG_CPU_MGQ_INFORMATION 0x041C | 163 | #define REG_CPU_MGQ_INFORMATION 0x041C |
| 168 | #define REG_FWHW_TXQ_CTRL 0x0420 | 164 | #define REG_FWHW_TXQ_CTRL 0x0420 |
| 169 | #define REG_HWSEQ_CTRL 0x0423 | 165 | #define REG_HWSEQ_CTRL 0x0423 |
| 170 | #define REG_TXPKTBUF_BCNQ_BDNY 0x0424 | 166 | #define REG_TXPKTBUF_BCNQ_BDNY 0x0424 |
| 171 | #define REG_TXPKTBUF_MGQ_BDNY 0x0425 | 167 | #define REG_TXPKTBUF_MGQ_BDNY 0x0425 |
| 172 | #define REG_MULTI_BCNQ_EN 0x0426 | 168 | #define REG_MULTI_BCNQ_EN 0x0426 |
| 173 | #define REG_MULTI_BCNQ_OFFSET 0x0427 | 169 | #define REG_MULTI_BCNQ_OFFSET 0x0427 |
| 174 | #define REG_SPEC_SIFS 0x0428 | 170 | #define REG_SPEC_SIFS 0x0428 |
| 175 | #define REG_RL 0x042A | 171 | #define REG_RL 0x042A |
| 176 | #define REG_DARFRC 0x0430 | 172 | #define REG_DARFRC 0x0430 |
| 177 | #define REG_RARFRC 0x0438 | 173 | #define REG_RARFRC 0x0438 |
| 178 | #define REG_RRSR 0x0440 | 174 | #define REG_RRSR 0x0440 |
| 179 | #define REG_ARFR0 0x0444 | 175 | #define REG_ARFR0 0x0444 |
| 180 | #define REG_ARFR1 0x0448 | 176 | #define REG_ARFR1 0x0448 |
| 181 | #define REG_ARFR2 0x044C | 177 | #define REG_ARFR2 0x044C |
| 182 | #define REG_ARFR3 0x0450 | 178 | #define REG_ARFR3 0x0450 |
| 183 | #define REG_AGGLEN_LMT 0x0458 | 179 | #define REG_AGGLEN_LMT 0x0458 |
| 184 | #define REG_AMPDU_MIN_SPACE 0x045C | 180 | #define REG_AMPDU_MIN_SPACE 0x045C |
| 185 | #define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D | 181 | #define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D |
| 186 | #define REG_FAST_EDCA_CTRL 0x0460 | 182 | #define REG_FAST_EDCA_CTRL 0x0460 |
| 187 | #define REG_RD_RESP_PKT_TH 0x0463 | 183 | #define REG_RD_RESP_PKT_TH 0x0463 |
| 188 | #define REG_INIRTS_RATE_SEL 0x0480 | 184 | #define REG_INIRTS_RATE_SEL 0x0480 |
| 189 | #define REG_INIDATA_RATE_SEL 0x0484 | 185 | #define REG_INIDATA_RATE_SEL 0x0484 |
| 190 | #define REG_POWER_STATUS 0x04A4 | 186 | #define REG_POWER_STATUS 0x04A4 |
| 191 | #define REG_POWER_STAGE1 0x04B4 | 187 | #define REG_POWER_STAGE1 0x04B4 |
| 192 | #define REG_POWER_STAGE2 0x04B8 | 188 | #define REG_POWER_STAGE2 0x04B8 |
| @@ -194,29 +190,29 @@ | |||
| 194 | #define REG_STBC_SETTING 0x04C4 | 190 | #define REG_STBC_SETTING 0x04C4 |
| 195 | #define REG_PROT_MODE_CTRL 0x04C8 | 191 | #define REG_PROT_MODE_CTRL 0x04C8 |
| 196 | #define REG_BAR_MODE_CTRL 0x04CC | 192 | #define REG_BAR_MODE_CTRL 0x04CC |
| 197 | #define REG_RA_TRY_RATE_AGG_LMT 0x04CF | 193 | #define REG_RA_TRY_RATE_AGG_LMT 0x04CF |
| 198 | #define REG_NQOS_SEQ 0x04DC | 194 | #define REG_NQOS_SEQ 0x04DC |
| 199 | #define REG_QOS_SEQ 0x04DE | 195 | #define REG_QOS_SEQ 0x04DE |
| 200 | #define REG_NEED_CPU_HANDLE 0x04E0 | 196 | #define REG_NEED_CPU_HANDLE 0x04E0 |
| 201 | #define REG_PKT_LOSE_RPT 0x04E1 | 197 | #define REG_PKT_LOSE_RPT 0x04E1 |
| 202 | #define REG_PTCL_ERR_STATUS 0x04E2 | 198 | #define REG_PTCL_ERR_STATUS 0x04E2 |
| 203 | #define REG_DUMMY 0x04FC | 199 | #define REG_DUMMY 0x04FC |
| 204 | 200 | ||
| 205 | #define REG_EDCA_VO_PARAM 0x0500 | 201 | #define REG_EDCA_VO_PARAM 0x0500 |
| 206 | #define REG_EDCA_VI_PARAM 0x0504 | 202 | #define REG_EDCA_VI_PARAM 0x0504 |
| 207 | #define REG_EDCA_BE_PARAM 0x0508 | 203 | #define REG_EDCA_BE_PARAM 0x0508 |
| 208 | #define REG_EDCA_BK_PARAM 0x050C | 204 | #define REG_EDCA_BK_PARAM 0x050C |
| 209 | #define REG_BCNTCFG 0x0510 | 205 | #define REG_BCNTCFG 0x0510 |
| 210 | #define REG_PIFS 0x0512 | 206 | #define REG_PIFS 0x0512 |
| 211 | #define REG_RDG_PIFS 0x0513 | 207 | #define REG_RDG_PIFS 0x0513 |
| 212 | #define REG_SIFS_CTX 0x0514 | 208 | #define REG_SIFS_CTX 0x0514 |
| 213 | #define REG_SIFS_TRX 0x0516 | 209 | #define REG_SIFS_TRX 0x0516 |
| 214 | #define REG_AGGR_BREAK_TIME 0x051A | 210 | #define REG_AGGR_BREAK_TIME 0x051A |
| 215 | #define REG_SLOT 0x051B | 211 | #define REG_SLOT 0x051B |
| 216 | #define REG_TX_PTCL_CTRL 0x0520 | 212 | #define REG_TX_PTCL_CTRL 0x0520 |
| 217 | #define REG_TXPAUSE 0x0522 | 213 | #define REG_TXPAUSE 0x0522 |
| 218 | #define REG_DIS_TXREQ_CLR 0x0523 | 214 | #define REG_DIS_TXREQ_CLR 0x0523 |
| 219 | #define REG_RD_CTRL 0x0524 | 215 | #define REG_RD_CTRL 0x0524 |
| 220 | #define REG_TBTT_PROHIBIT 0x0540 | 216 | #define REG_TBTT_PROHIBIT 0x0540 |
| 221 | #define REG_RD_NAV_NXT 0x0544 | 217 | #define REG_RD_NAV_NXT 0x0544 |
| 222 | #define REG_NAV_PROT_LEN 0x0546 | 218 | #define REG_NAV_PROT_LEN 0x0546 |
| @@ -225,21 +221,21 @@ | |||
| 225 | #define REG_MBID_NUM 0x0552 | 221 | #define REG_MBID_NUM 0x0552 |
| 226 | #define REG_DUAL_TSF_RST 0x0553 | 222 | #define REG_DUAL_TSF_RST 0x0553 |
| 227 | #define REG_BCN_INTERVAL 0x0554 | 223 | #define REG_BCN_INTERVAL 0x0554 |
| 228 | #define REG_MBSSID_BCN_SPACE 0x0554 | 224 | #define REG_MBSSID_BCN_SPACE 0x0554 |
| 229 | #define REG_DRVERLYINT 0x0558 | 225 | #define REG_DRVERLYINT 0x0558 |
| 230 | #define REG_BCNDMATIM 0x0559 | 226 | #define REG_BCNDMATIM 0x0559 |
| 231 | #define REG_ATIMWND 0x055A | 227 | #define REG_ATIMWND 0x055A |
| 232 | #define REG_BCN_MAX_ERR 0x055D | 228 | #define REG_BCN_MAX_ERR 0x055D |
| 233 | #define REG_RXTSF_OFFSET_CCK 0x055E | 229 | #define REG_RXTSF_OFFSET_CCK 0x055E |
| 234 | #define REG_RXTSF_OFFSET_OFDM 0x055F | 230 | #define REG_RXTSF_OFFSET_OFDM 0x055F |
| 235 | #define REG_TSFTR 0x0560 | 231 | #define REG_TSFTR 0x0560 |
| 236 | #define REG_INIT_TSFTR 0x0564 | 232 | #define REG_INIT_TSFTR 0x0564 |
| 237 | #define REG_PSTIMER 0x0580 | 233 | #define REG_PSTIMER 0x0580 |
| 238 | #define REG_TIMER0 0x0584 | 234 | #define REG_TIMER0 0x0584 |
| 239 | #define REG_TIMER1 0x0588 | 235 | #define REG_TIMER1 0x0588 |
| 240 | #define REG_ACMHWCTRL 0x05C0 | 236 | #define REG_ACMHWCTRL 0x05C0 |
| 241 | #define REG_ACMRSTCTRL 0x05C1 | 237 | #define REG_ACMRSTCTRL 0x05C1 |
| 242 | #define REG_ACMAVG 0x05C2 | 238 | #define REG_ACMAVG 0x05C2 |
| 243 | #define REG_VO_ADMTIME 0x05C4 | 239 | #define REG_VO_ADMTIME 0x05C4 |
| 244 | #define REG_VI_ADMTIME 0x05C6 | 240 | #define REG_VI_ADMTIME 0x05C6 |
| 245 | #define REG_BE_ADMTIME 0x05C8 | 241 | #define REG_BE_ADMTIME 0x05C8 |
| @@ -248,38 +244,38 @@ | |||
| 248 | 244 | ||
| 249 | #define REG_APSD_CTRL 0x0600 | 245 | #define REG_APSD_CTRL 0x0600 |
| 250 | #define REG_BWOPMODE 0x0603 | 246 | #define REG_BWOPMODE 0x0603 |
| 251 | #define REG_TCR 0x0604 | 247 | #define REG_TCR 0x0604 |
| 252 | #define REG_RCR 0x0608 | 248 | #define REG_RCR 0x0608 |
| 253 | #define REG_RX_PKT_LIMIT 0x060C | 249 | #define REG_RX_PKT_LIMIT 0x060C |
| 254 | #define REG_RX_DLK_TIME 0x060D | 250 | #define REG_RX_DLK_TIME 0x060D |
| 255 | #define REG_RX_DRVINFO_SZ 0x060F | 251 | #define REG_RX_DRVINFO_SZ 0x060F |
| 256 | 252 | ||
| 257 | #define REG_MACID 0x0610 | 253 | #define REG_MACID 0x0610 |
| 258 | #define REG_BSSID 0x0618 | 254 | #define REG_BSSID 0x0618 |
| 259 | #define REG_MAR 0x0620 | 255 | #define REG_MAR 0x0620 |
| 260 | #define REG_MBIDCAMCFG 0x0628 | 256 | #define REG_MBIDCAMCFG 0x0628 |
| 261 | 257 | ||
| 262 | #define REG_USTIME_EDCA 0x0638 | 258 | #define REG_USTIME_EDCA 0x0638 |
| 263 | #define REG_MAC_SPEC_SIFS 0x063A | 259 | #define REG_MAC_SPEC_SIFS 0x063A |
| 264 | #define REG_RESP_SIFS_CCK 0x063C | 260 | #define REG_RESP_SIFS_CCK 0x063C |
| 265 | #define REG_RESP_SIFS_OFDM 0x063E | 261 | #define REG_RESP_SIFS_OFDM 0x063E |
| 266 | #define REG_ACKTO 0x0640 | 262 | #define REG_ACKTO 0x0640 |
| 267 | #define REG_CTS2TO 0x0641 | 263 | #define REG_CTS2TO 0x0641 |
| 268 | #define REG_EIFS 0x0642 | 264 | #define REG_EIFS 0x0642 |
| 269 | 265 | ||
| 270 | #define REG_NAV_CTRL 0x0650 | 266 | #define REG_NAV_CTRL 0x0650 |
| 271 | #define REG_BACAMCMD 0x0654 | 267 | #define REG_BACAMCMD 0x0654 |
| 272 | #define REG_BACAMCONTENT 0x0658 | 268 | #define REG_BACAMCONTENT 0x0658 |
| 273 | #define REG_LBDLY 0x0660 | 269 | #define REG_LBDLY 0x0660 |
| 274 | #define REG_FWDLY 0x0661 | 270 | #define REG_FWDLY 0x0661 |
| 275 | #define REG_RXERR_RPT 0x0664 | 271 | #define REG_RXERR_RPT 0x0664 |
| 276 | #define REG_WMAC_TRXPTCL_CTL 0x0668 | 272 | #define REG_WMAC_TRXPTCL_CTL 0x0668 |
| 277 | 273 | ||
| 278 | #define REG_CAMCMD 0x0670 | 274 | #define REG_CAMCMD 0x0670 |
| 279 | #define REG_CAMWRITE 0x0674 | 275 | #define REG_CAMWRITE 0x0674 |
| 280 | #define REG_CAMREAD 0x0678 | 276 | #define REG_CAMREAD 0x0678 |
| 281 | #define REG_CAMDBG 0x067C | 277 | #define REG_CAMDBG 0x067C |
| 282 | #define REG_SECCFG 0x0680 | 278 | #define REG_SECCFG 0x0680 |
| 283 | 279 | ||
| 284 | #define REG_WOW_CTRL 0x0690 | 280 | #define REG_WOW_CTRL 0x0690 |
| 285 | #define REG_PSSTATUS 0x0691 | 281 | #define REG_PSSTATUS 0x0691 |
| @@ -294,10 +290,10 @@ | |||
| 294 | #define REG_CALB32K_CTRL 0x06AC | 290 | #define REG_CALB32K_CTRL 0x06AC |
| 295 | #define REG_PKT_MON_CTRL 0x06B4 | 291 | #define REG_PKT_MON_CTRL 0x06B4 |
| 296 | #define REG_BT_COEX_TABLE 0x06C0 | 292 | #define REG_BT_COEX_TABLE 0x06C0 |
| 297 | #define REG_WMAC_RESP_TXINFO 0x06D8 | 293 | #define REG_WMAC_RESP_TXINFO 0x06D8 |
| 298 | 294 | ||
| 299 | #define REG_USB_INFO 0xFE17 | 295 | #define REG_USB_INFO 0xFE17 |
| 300 | #define REG_USB_SPECIAL_OPTION 0xFE55 | 296 | #define REG_USB_SPECIAL_OPTION 0xFE55 |
| 301 | #define REG_USB_DMA_AGG_TO 0xFE5B | 297 | #define REG_USB_DMA_AGG_TO 0xFE5B |
| 302 | #define REG_USB_AGG_TO 0xFE5C | 298 | #define REG_USB_AGG_TO 0xFE5C |
| 303 | #define REG_USB_AGG_TH 0xFE5D | 299 | #define REG_USB_AGG_TH 0xFE5D |
| @@ -305,120 +301,148 @@ | |||
| 305 | #define REG_TEST_USB_TXQS 0xFE48 | 301 | #define REG_TEST_USB_TXQS 0xFE48 |
| 306 | #define REG_TEST_SIE_VID 0xFE60 | 302 | #define REG_TEST_SIE_VID 0xFE60 |
| 307 | #define REG_TEST_SIE_PID 0xFE62 | 303 | #define REG_TEST_SIE_PID 0xFE62 |
| 308 | #define REG_TEST_SIE_OPTIONAL 0xFE64 | 304 | #define REG_TEST_SIE_OPTIONAL 0xFE64 |
| 309 | #define REG_TEST_SIE_CHIRP_K 0xFE65 | 305 | #define REG_TEST_SIE_CHIRP_K 0xFE65 |
| 310 | #define REG_TEST_SIE_PHY 0xFE66 | 306 | #define REG_TEST_SIE_PHY 0xFE66 |
| 311 | #define REG_TEST_SIE_MAC_ADDR 0xFE70 | 307 | #define REG_TEST_SIE_MAC_ADDR 0xFE70 |
| 312 | #define REG_TEST_SIE_STRING 0xFE80 | 308 | #define REG_TEST_SIE_STRING 0xFE80 |
| 313 | 309 | ||
| 314 | #define REG_NORMAL_SIE_VID 0xFE60 | 310 | #define REG_NORMAL_SIE_VID 0xFE60 |
| 315 | #define REG_NORMAL_SIE_PID 0xFE62 | 311 | #define REG_NORMAL_SIE_PID 0xFE62 |
| 316 | #define REG_NORMAL_SIE_OPTIONAL 0xFE64 | 312 | #define REG_NORMAL_SIE_OPTIONAL 0xFE64 |
| 317 | #define REG_NORMAL_SIE_EP 0xFE65 | 313 | #define REG_NORMAL_SIE_EP 0xFE65 |
| 318 | #define REG_NORMAL_SIE_PHY 0xFE68 | 314 | #define REG_NORMAL_SIE_PHY 0xFE68 |
| 319 | #define REG_NORMAL_SIE_MAC_ADDR 0xFE70 | 315 | #define REG_NORMAL_SIE_MAC_ADDR 0xFE70 |
| 320 | #define REG_NORMAL_SIE_STRING 0xFE80 | 316 | #define REG_NORMAL_SIE_STRING 0xFE80 |
| 321 | 317 | ||
| 322 | #define CR9346 REG_9346CR | 318 | #define CR9346 REG_9346CR |
| 323 | #define MSR (REG_CR + 2) | 319 | #define MSR (REG_CR + 2) |
| 324 | #define ISR REG_HISR | 320 | #define ISR REG_HISR |
| 325 | #define TSFR REG_TSFTR | 321 | #define TSFR REG_TSFTR |
| 326 | 322 | ||
| 327 | #define MACIDR0 REG_MACID | 323 | #define MACIDR0 REG_MACID |
| 328 | #define MACIDR4 (REG_MACID + 4) | 324 | #define MACIDR4 (REG_MACID + 4) |
| 329 | 325 | ||
| 330 | #define PBP REG_PBP | 326 | #define PBP REG_PBP |
| 331 | 327 | ||
| 332 | #define IDR0 MACIDR0 | 328 | #define IDR0 MACIDR0 |
| 333 | #define IDR4 MACIDR4 | 329 | #define IDR4 MACIDR4 |
| 334 | 330 | ||
| 335 | #define UNUSED_REGISTER 0x1BF | 331 | #define UNUSED_REGISTER 0x1BF |
| 336 | #define DCAM UNUSED_REGISTER | 332 | #define DCAM UNUSED_REGISTER |
| 337 | #define PSR UNUSED_REGISTER | 333 | #define PSR UNUSED_REGISTER |
| 338 | #define BBADDR UNUSED_REGISTER | 334 | #define BBADDR UNUSED_REGISTER |
| 339 | #define PHYDATAR UNUSED_REGISTER | 335 | #define PHYDATAR UNUSED_REGISTER |
| 340 | 336 | ||
| 341 | #define INVALID_BBRF_VALUE 0x12345678 | 337 | #define INVALID_BBRF_VALUE 0x12345678 |
| 342 | 338 | ||
| 343 | #define MAX_MSS_DENSITY_2T 0x13 | 339 | #define MAX_MSS_DENSITY_2T 0x13 |
| 344 | #define MAX_MSS_DENSITY_1T 0x0A | 340 | #define MAX_MSS_DENSITY_1T 0x0A |
| 345 | 341 | ||
| 346 | #define CMDEEPROM_EN BIT(5) | 342 | #define CMDEEPROM_EN BIT(5) |
| 347 | #define CMDEEPROM_SEL BIT(4) | 343 | #define CMDEEPROM_SEL BIT(4) |
| 348 | #define CMD9346CR_9356SEL BIT(4) | 344 | #define CMD9346CR_9356SEL BIT(4) |
| 349 | #define AUTOLOAD_EEPROM (CMDEEPROM_EN|CMDEEPROM_SEL) | 345 | #define AUTOLOAD_EEPROM (CMDEEPROM_EN|CMDEEPROM_SEL) |
| 350 | #define AUTOLOAD_EFUSE CMDEEPROM_EN | 346 | #define AUTOLOAD_EFUSE CMDEEPROM_EN |
| 351 | 347 | ||
| 352 | #define GPIOSEL_GPIO 0 | 348 | #define GPIOSEL_GPIO 0 |
| 353 | #define GPIOSEL_ENBT BIT(5) | 349 | #define GPIOSEL_ENBT BIT(5) |
| 354 | 350 | ||
| 355 | #define GPIO_IN REG_GPIO_PIN_CTRL | 351 | #define GPIO_IN REG_GPIO_PIN_CTRL |
| 356 | #define GPIO_OUT (REG_GPIO_PIN_CTRL+1) | 352 | #define GPIO_OUT (REG_GPIO_PIN_CTRL+1) |
| 357 | #define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) | 353 | #define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) |
| 358 | #define GPIO_MOD (REG_GPIO_PIN_CTRL+3) | 354 | #define GPIO_MOD (REG_GPIO_PIN_CTRL+3) |
| 359 | 355 | ||
| 360 | #define MSR_NOLINK 0x00 | 356 | #define MSR_NOLINK 0x00 |
| 361 | #define MSR_ADHOC 0x01 | 357 | #define MSR_ADHOC 0x01 |
| 362 | #define MSR_INFRA 0x02 | 358 | #define MSR_INFRA 0x02 |
| 363 | #define MSR_AP 0x03 | 359 | #define MSR_AP 0x03 |
| 364 | #define MSR_MASK 0x03 | ||
| 365 | 360 | ||
| 366 | #define RRSR_RSC_OFFSET 21 | 361 | #define RRSR_RSC_OFFSET 21 |
| 367 | #define RRSR_SHORT_OFFSET 23 | 362 | #define RRSR_SHORT_OFFSET 23 |
| 368 | #define RRSR_RSC_BW_40M 0x600000 | 363 | #define RRSR_RSC_BW_40M 0x600000 |
| 369 | #define RRSR_RSC_UPSUBCHNL 0x400000 | 364 | #define RRSR_RSC_UPSUBCHNL 0x400000 |
| 370 | #define RRSR_RSC_LOWSUBCHNL 0x200000 | 365 | #define RRSR_RSC_LOWSUBCHNL 0x200000 |
| 371 | #define RRSR_SHORT 0x800000 | 366 | #define RRSR_SHORT 0x800000 |
| 372 | #define RRSR_1M BIT(0) | 367 | #define RRSR_1M BIT(0) |
| 373 | #define RRSR_2M BIT(1) | 368 | #define RRSR_2M BIT(1) |
| 374 | #define RRSR_5_5M BIT(2) | 369 | #define RRSR_5_5M BIT(2) |
| 375 | #define RRSR_11M BIT(3) | 370 | #define RRSR_11M BIT(3) |
| 376 | #define RRSR_6M BIT(4) | 371 | #define RRSR_6M BIT(4) |
| 377 | #define RRSR_9M BIT(5) | 372 | #define RRSR_9M BIT(5) |
| 378 | #define RRSR_12M BIT(6) | 373 | #define RRSR_12M BIT(6) |
| 379 | #define RRSR_18M BIT(7) | 374 | #define RRSR_18M BIT(7) |
| 380 | #define RRSR_24M BIT(8) | 375 | #define RRSR_24M BIT(8) |
| 381 | #define RRSR_36M BIT(9) | 376 | #define RRSR_36M BIT(9) |
| 382 | #define RRSR_48M BIT(10) | 377 | #define RRSR_48M BIT(10) |
| 383 | #define RRSR_54M BIT(11) | 378 | #define RRSR_54M BIT(11) |
| 384 | #define RRSR_MCS0 BIT(12) | 379 | #define RRSR_MCS0 BIT(12) |
| 385 | #define RRSR_MCS1 BIT(13) | 380 | #define RRSR_MCS1 BIT(13) |
| 386 | #define RRSR_MCS2 BIT(14) | 381 | #define RRSR_MCS2 BIT(14) |
| 387 | #define RRSR_MCS3 BIT(15) | 382 | #define RRSR_MCS3 BIT(15) |
| 388 | #define RRSR_MCS4 BIT(16) | 383 | #define RRSR_MCS4 BIT(16) |
| 389 | #define RRSR_MCS5 BIT(17) | 384 | #define RRSR_MCS5 BIT(17) |
| 390 | #define RRSR_MCS6 BIT(18) | 385 | #define RRSR_MCS6 BIT(18) |
| 391 | #define RRSR_MCS7 BIT(19) | 386 | #define RRSR_MCS7 BIT(19) |
| 392 | #define BRSR_ACKSHORTPMB BIT(23) | 387 | #define BRSR_ACKSHORTPMB BIT(23) |
| 393 | 388 | ||
| 394 | #define RATR_1M 0x00000001 | 389 | #define RATR_1M 0x00000001 |
| 395 | #define RATR_2M 0x00000002 | 390 | #define RATR_2M 0x00000002 |
| 396 | #define RATR_55M 0x00000004 | 391 | #define RATR_55M 0x00000004 |
| 397 | #define RATR_11M 0x00000008 | 392 | #define RATR_11M 0x00000008 |
| 398 | #define RATR_6M 0x00000010 | 393 | #define RATR_6M 0x00000010 |
| 399 | #define RATR_9M 0x00000020 | 394 | #define RATR_9M 0x00000020 |
| 400 | #define RATR_12M 0x00000040 | 395 | #define RATR_12M 0x00000040 |
| 401 | #define RATR_18M 0x00000080 | 396 | #define RATR_18M 0x00000080 |
| 402 | #define RATR_24M 0x00000100 | 397 | #define RATR_24M 0x00000100 |
| 403 | #define RATR_36M 0x00000200 | 398 | #define RATR_36M 0x00000200 |
| 404 | #define RATR_48M 0x00000400 | 399 | #define RATR_48M 0x00000400 |
| 405 | #define RATR_54M 0x00000800 | 400 | #define RATR_54M 0x00000800 |
| 406 | #define RATR_MCS0 0x00001000 | 401 | #define RATR_MCS0 0x00001000 |
| 407 | #define RATR_MCS1 0x00002000 | 402 | #define RATR_MCS1 0x00002000 |
| 408 | #define RATR_MCS2 0x00004000 | 403 | #define RATR_MCS2 0x00004000 |
| 409 | #define RATR_MCS3 0x00008000 | 404 | #define RATR_MCS3 0x00008000 |
| 410 | #define RATR_MCS4 0x00010000 | 405 | #define RATR_MCS4 0x00010000 |
| 411 | #define RATR_MCS5 0x00020000 | 406 | #define RATR_MCS5 0x00020000 |
| 412 | #define RATR_MCS6 0x00040000 | 407 | #define RATR_MCS6 0x00040000 |
| 413 | #define RATR_MCS7 0x00080000 | 408 | #define RATR_MCS7 0x00080000 |
| 414 | #define RATR_MCS8 0x00100000 | 409 | #define RATR_MCS8 0x00100000 |
| 415 | #define RATR_MCS9 0x00200000 | 410 | #define RATR_MCS9 0x00200000 |
| 416 | #define RATR_MCS10 0x00400000 | 411 | #define RATR_MCS10 0x00400000 |
| 417 | #define RATR_MCS11 0x00800000 | 412 | #define RATR_MCS11 0x00800000 |
| 418 | #define RATR_MCS12 0x01000000 | 413 | #define RATR_MCS12 0x01000000 |
| 419 | #define RATR_MCS13 0x02000000 | 414 | #define RATR_MCS13 0x02000000 |
| 420 | #define RATR_MCS14 0x04000000 | 415 | #define RATR_MCS14 0x04000000 |
| 421 | #define RATR_MCS15 0x08000000 | 416 | #define RATR_MCS15 0x08000000 |
| 417 | |||
| 418 | #define RATE_1M BIT(0) | ||
| 419 | #define RATE_2M BIT(1) | ||
| 420 | #define RATE_5_5M BIT(2) | ||
| 421 | #define RATE_11M BIT(3) | ||
| 422 | #define RATE_6M BIT(4) | ||
| 423 | #define RATE_9M BIT(5) | ||
| 424 | #define RATE_12M BIT(6) | ||
| 425 | #define RATE_18M BIT(7) | ||
| 426 | #define RATE_24M BIT(8) | ||
| 427 | #define RATE_36M BIT(9) | ||
| 428 | #define RATE_48M BIT(10) | ||
| 429 | #define RATE_54M BIT(11) | ||
| 430 | #define RATE_MCS0 BIT(12) | ||
| 431 | #define RATE_MCS1 BIT(13) | ||
| 432 | #define RATE_MCS2 BIT(14) | ||
| 433 | #define RATE_MCS3 BIT(15) | ||
| 434 | #define RATE_MCS4 BIT(16) | ||
| 435 | #define RATE_MCS5 BIT(17) | ||
| 436 | #define RATE_MCS6 BIT(18) | ||
| 437 | #define RATE_MCS7 BIT(19) | ||
| 438 | #define RATE_MCS8 BIT(20) | ||
| 439 | #define RATE_MCS9 BIT(21) | ||
| 440 | #define RATE_MCS10 BIT(22) | ||
| 441 | #define RATE_MCS11 BIT(23) | ||
| 442 | #define RATE_MCS12 BIT(24) | ||
| 443 | #define RATE_MCS13 BIT(25) | ||
| 444 | #define RATE_MCS14 BIT(26) | ||
| 445 | #define RATE_MCS15 BIT(27) | ||
| 422 | 446 | ||
| 423 | #define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M) | 447 | #define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M) |
| 424 | #define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M |\ | 448 | #define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M |\ |
| @@ -434,31 +458,31 @@ | |||
| 434 | #define BW_OPMODE_5G BIT(1) | 458 | #define BW_OPMODE_5G BIT(1) |
| 435 | #define BW_OPMODE_11J BIT(0) | 459 | #define BW_OPMODE_11J BIT(0) |
| 436 | 460 | ||
| 437 | #define CAM_VALID BIT(15) | 461 | #define CAM_VALID BIT(15) |
| 438 | #define CAM_NOTVALID 0x0000 | 462 | #define CAM_NOTVALID 0x0000 |
| 439 | #define CAM_USEDK BIT(5) | 463 | #define CAM_USEDK BIT(5) |
| 440 | 464 | ||
| 441 | #define CAM_NONE 0x0 | 465 | #define CAM_NONE 0x0 |
| 442 | #define CAM_WEP40 0x01 | 466 | #define CAM_WEP40 0x01 |
| 443 | #define CAM_TKIP 0x02 | 467 | #define CAM_TKIP 0x02 |
| 444 | #define CAM_AES 0x04 | 468 | #define CAM_AES 0x04 |
| 445 | #define CAM_WEP104 0x05 | 469 | #define CAM_WEP104 0x05 |
| 446 | 470 | ||
| 447 | #define TOTAL_CAM_ENTRY 32 | 471 | #define TOTAL_CAM_ENTRY 32 |
| 448 | #define HALF_CAM_ENTRY 16 | 472 | #define HALF_CAM_ENTRY 16 |
| 449 | 473 | ||
| 450 | #define CAM_WRITE BIT(16) | 474 | #define CAM_WRITE BIT(16) |
| 451 | #define CAM_READ 0x00000000 | 475 | #define CAM_READ 0x00000000 |
| 452 | #define CAM_POLLINIG BIT(31) | 476 | #define CAM_POLLINIG BIT(31) |
| 453 | 477 | ||
| 454 | #define SCR_USEDK 0x01 | 478 | #define SCR_USEDK 0x01 |
| 455 | #define SCR_TXSEC_ENABLE 0x02 | 479 | #define SCR_TXSEC_ENABLE 0x02 |
| 456 | #define SCR_RXSEC_ENABLE 0x04 | 480 | #define SCR_RXSEC_ENABLE 0x04 |
| 457 | 481 | ||
| 458 | #define WOW_PMEN BIT(0) | 482 | #define WOW_PMEN BIT(0) |
| 459 | #define WOW_WOMEN BIT(1) | 483 | #define WOW_WOMEN BIT(1) |
| 460 | #define WOW_MAGIC BIT(2) | 484 | #define WOW_MAGIC BIT(2) |
| 461 | #define WOW_UWF BIT(3) | 485 | #define WOW_UWF BIT(3) |
| 462 | 486 | ||
| 463 | #define IMR8190_DISABLED 0x0 | 487 | #define IMR8190_DISABLED 0x0 |
| 464 | #define IMR_BCNDMAINT6 BIT(31) | 488 | #define IMR_BCNDMAINT6 BIT(31) |
| @@ -467,180 +491,179 @@ | |||
| 467 | #define IMR_BCNDMAINT3 BIT(28) | 491 | #define IMR_BCNDMAINT3 BIT(28) |
| 468 | #define IMR_BCNDMAINT2 BIT(27) | 492 | #define IMR_BCNDMAINT2 BIT(27) |
| 469 | #define IMR_BCNDMAINT1 BIT(26) | 493 | #define IMR_BCNDMAINT1 BIT(26) |
| 470 | #define IMR_BCNDOK8 BIT(25) | 494 | #define IMR_BCNDOK8 BIT(25) |
| 471 | #define IMR_BCNDOK7 BIT(24) | 495 | #define IMR_BCNDOK7 BIT(24) |
| 472 | #define IMR_BCNDOK6 BIT(23) | 496 | #define IMR_BCNDOK6 BIT(23) |
| 473 | #define IMR_BCNDOK5 BIT(22) | 497 | #define IMR_BCNDOK5 BIT(22) |
| 474 | #define IMR_BCNDOK4 BIT(21) | 498 | #define IMR_BCNDOK4 BIT(21) |
| 475 | #define IMR_BCNDOK3 BIT(20) | 499 | #define IMR_BCNDOK3 BIT(20) |
| 476 | #define IMR_BCNDOK2 BIT(19) | 500 | #define IMR_BCNDOK2 BIT(19) |
| 477 | #define IMR_BCNDOK1 BIT(18) | 501 | #define IMR_BCNDOK1 BIT(18) |
| 478 | #define IMR_TIMEOUT2 BIT(17) | 502 | #define IMR_TIMEOUT2 BIT(17) |
| 479 | #define IMR_TIMEOUT1 BIT(16) | 503 | #define IMR_TIMEOUT1 BIT(16) |
| 480 | #define IMR_TXFOVW BIT(15) | 504 | #define IMR_TXFOVW BIT(15) |
| 481 | #define IMR_PSTIMEOUT BIT(14) | 505 | #define IMR_PSTIMEOUT BIT(14) |
| 482 | #define IMR_BCNINT BIT(13) | 506 | #define IMR_BCNINT BIT(13) |
| 483 | #define IMR_RXFOVW BIT(12) | 507 | #define IMR_RXFOVW BIT(12) |
| 484 | #define IMR_RDU BIT(11) | 508 | #define IMR_RDU BIT(11) |
| 485 | #define IMR_ATIMEND BIT(10) | 509 | #define IMR_ATIMEND BIT(10) |
| 486 | #define IMR_BDOK BIT(9) | 510 | #define IMR_BDOK BIT(9) |
| 487 | #define IMR_HIGHDOK BIT(8) | 511 | #define IMR_HIGHDOK BIT(8) |
| 488 | #define IMR_TBDOK BIT(7) | 512 | #define IMR_TBDOK BIT(7) |
| 489 | #define IMR_MGNTDOK BIT(6) | 513 | #define IMR_MGNTDOK BIT(6) |
| 490 | #define IMR_TBDER BIT(5) | 514 | #define IMR_TBDER BIT(5) |
| 491 | #define IMR_BKDOK BIT(4) | 515 | #define IMR_BKDOK BIT(4) |
| 492 | #define IMR_BEDOK BIT(3) | 516 | #define IMR_BEDOK BIT(3) |
| 493 | #define IMR_VIDOK BIT(2) | 517 | #define IMR_VIDOK BIT(2) |
| 494 | #define IMR_VODOK BIT(1) | 518 | #define IMR_VODOK BIT(1) |
| 495 | #define IMR_ROK BIT(0) | 519 | #define IMR_ROK BIT(0) |
| 496 | 520 | ||
| 497 | #define IMR_TXERR BIT(11) | 521 | #define IMR_TXERR BIT(11) |
| 498 | #define IMR_RXERR BIT(10) | 522 | #define IMR_RXERR BIT(10) |
| 499 | #define IMR_CPWM BIT(8) | 523 | #define IMR_CPWM BIT(8) |
| 500 | #define IMR_OCPINT BIT(1) | 524 | #define IMR_OCPINT BIT(1) |
| 501 | #define IMR_WLANOFF BIT(0) | 525 | #define IMR_WLANOFF BIT(0) |
| 502 | 526 | ||
| 503 | /* 8723E series PCIE Host IMR/ISR bit */ | 527 | /* 8723E series PCIE Host IMR/ISR bit */ |
| 504 | /* IMR DW0 Bit 0-31 */ | 528 | /* IMR DW0 Bit 0-31 */ |
| 505 | #define PHIMR_TIMEOUT2 BIT(31) | 529 | #define PHIMR_TIMEOUT2 BIT(31) |
| 506 | #define PHIMR_TIMEOUT1 BIT(30) | 530 | #define PHIMR_TIMEOUT1 BIT(30) |
| 507 | #define PHIMR_PSTIMEOUT BIT(29) | 531 | #define PHIMR_PSTIMEOUT BIT(29) |
| 508 | #define PHIMR_GTINT4 BIT(28) | 532 | #define PHIMR_GTINT4 BIT(28) |
| 509 | #define PHIMR_GTINT3 BIT(27) | 533 | #define PHIMR_GTINT3 BIT(27) |
| 510 | #define PHIMR_TXBCNERR BIT(26) | 534 | #define PHIMR_TXBCNERR BIT(26) |
| 511 | #define PHIMR_TXBCNOK BIT(25) | 535 | #define PHIMR_TXBCNOK BIT(25) |
| 512 | #define PHIMR_TSF_BIT32_TOGGLE BIT(24) | 536 | #define PHIMR_TSF_BIT32_TOGGLE BIT(24) |
| 513 | #define PHIMR_BCNDMAINT3 BIT(23) | 537 | #define PHIMR_BCNDMAINT3 BIT(23) |
| 514 | #define PHIMR_BCNDMAINT2 BIT(22) | 538 | #define PHIMR_BCNDMAINT2 BIT(22) |
| 515 | #define PHIMR_BCNDMAINT1 BIT(21) | 539 | #define PHIMR_BCNDMAINT1 BIT(21) |
| 516 | #define PHIMR_BCNDMAINT0 BIT(20) | 540 | #define PHIMR_BCNDMAINT0 BIT(20) |
| 517 | #define PHIMR_BCNDOK3 BIT(19) | 541 | #define PHIMR_BCNDOK3 BIT(19) |
| 518 | #define PHIMR_BCNDOK2 BIT(18) | 542 | #define PHIMR_BCNDOK2 BIT(18) |
| 519 | #define PHIMR_BCNDOK1 BIT(17) | 543 | #define PHIMR_BCNDOK1 BIT(17) |
| 520 | #define PHIMR_BCNDOK0 BIT(16) | 544 | #define PHIMR_BCNDOK0 BIT(16) |
| 521 | #define PHIMR_HSISR_IND_ON BIT(15) | 545 | #define PHIMR_HSISR_IND_ON BIT(15) |
| 522 | #define PHIMR_BCNDMAINT_E BIT(14) | 546 | #define PHIMR_BCNDMAINT_E BIT(14) |
| 523 | #define PHIMR_ATIMEND_E BIT(13) | 547 | #define PHIMR_ATIMEND_E BIT(13) |
| 524 | #define PHIMR_ATIM_CTW_END BIT(12) | 548 | #define PHIMR_ATIM_CTW_END BIT(12) |
| 525 | #define PHIMR_HISRE_IND BIT(11) | 549 | #define PHIMR_HISRE_IND BIT(11) |
| 526 | #define PHIMR_C2HCMD BIT(10) | 550 | #define PHIMR_C2HCMD BIT(10) |
| 527 | #define PHIMR_CPWM2 BIT(9) | 551 | #define PHIMR_CPWM2 BIT(9) |
| 528 | #define PHIMR_CPWM BIT(8) | 552 | #define PHIMR_CPWM BIT(8) |
| 529 | #define PHIMR_HIGHDOK BIT(7) | 553 | #define PHIMR_HIGHDOK BIT(7) |
| 530 | #define PHIMR_MGNTDOK BIT(6) | 554 | #define PHIMR_MGNTDOK BIT(6) |
| 531 | #define PHIMR_BKDOK BIT(5) | 555 | #define PHIMR_BKDOK BIT(5) |
| 532 | #define PHIMR_BEDOK BIT(4) | 556 | #define PHIMR_BEDOK BIT(4) |
| 533 | #define PHIMR_VIDOK BIT(3) | 557 | #define PHIMR_VIDOK BIT(3) |
| 534 | #define PHIMR_VODOK BIT(2) | 558 | #define PHIMR_VODOK BIT(2) |
| 535 | #define PHIMR_RDU BIT(1) | 559 | #define PHIMR_RDU BIT(1) |
| 536 | #define PHIMR_ROK BIT(0) | 560 | #define PHIMR_ROK BIT(0) |
| 537 | 561 | ||
| 538 | /* PCIE Host Interrupt Status Extension bit */ | 562 | /* PCIE Host Interrupt Status Extension bit */ |
| 539 | #define PHIMR_BCNDMAINT7 BIT(23) | 563 | #define PHIMR_BCNDMAINT7 BIT(23) |
| 540 | #define PHIMR_BCNDMAINT6 BIT(22) | 564 | #define PHIMR_BCNDMAINT6 BIT(22) |
| 541 | #define PHIMR_BCNDMAINT5 BIT(21) | 565 | #define PHIMR_BCNDMAINT5 BIT(21) |
| 542 | #define PHIMR_BCNDMAINT4 BIT(20) | 566 | #define PHIMR_BCNDMAINT4 BIT(20) |
| 543 | #define PHIMR_BCNDOK7 BIT(19) | 567 | #define PHIMR_BCNDOK7 BIT(19) |
| 544 | #define PHIMR_BCNDOK6 BIT(18) | 568 | #define PHIMR_BCNDOK6 BIT(18) |
| 545 | #define PHIMR_BCNDOK5 BIT(17) | 569 | #define PHIMR_BCNDOK5 BIT(17) |
| 546 | #define PHIMR_BCNDOK4 BIT(16) | 570 | #define PHIMR_BCNDOK4 BIT(16) |
| 547 | /* bit12-15: RSVD */ | 571 | /* bit12-15: RSVD */ |
| 548 | #define PHIMR_TXERR BIT(11) | 572 | #define PHIMR_TXERR BIT(11) |
| 549 | #define PHIMR_RXERR BIT(10) | 573 | #define PHIMR_RXERR BIT(10) |
| 550 | #define PHIMR_TXFOVW BIT(9) | 574 | #define PHIMR_TXFOVW BIT(9) |
| 551 | #define PHIMR_RXFOVW BIT(8) | 575 | #define PHIMR_RXFOVW BIT(8) |
| 552 | /* bit2-7: RSV */ | 576 | /* bit2-7: RSVD */ |
| 553 | #define PHIMR_OCPINT BIT(1) | 577 | #define PHIMR_OCPINT BIT(1) |
| 554 | 578 | ||
| 555 | #define HWSET_MAX_SIZE 256 | 579 | #define HWSET_MAX_SIZE 256 |
| 556 | #define EFUSE_MAX_SECTION 32 | 580 | #define EFUSE_MAX_SECTION 32 |
| 557 | #define EFUSE_REAL_CONTENT_LEN 512 | 581 | #define EFUSE_REAL_CONTENT_LEN 512 |
| 558 | #define EFUSE_OOB_PROTECT_BYTES 15 | 582 | #define EFUSE_OOB_PROTECT_BYTES 15 |
| 559 | 583 | ||
| 560 | #define EEPROM_DEFAULT_TSSI 0x0 | 584 | #define EEPROM_DEFAULT_TSSI 0x0 |
| 561 | #define EEPROM_DEFAULT_TXPOWERDIFF 0x0 | 585 | #define EEPROM_DEFAULT_TXPOWERDIFF 0x0 |
| 562 | #define EEPROM_DEFAULT_CRYSTALCAP 0x5 | 586 | #define EEPROM_DEFAULT_CRYSTALCAP 0x5 |
| 563 | #define EEPROM_DEFAULT_BOARDTYPE 0x02 | 587 | #define EEPROM_DEFAULT_BOARDTYPE 0x02 |
| 564 | #define EEPROM_DEFAULT_TXPOWER 0x1010 | 588 | #define EEPROM_DEFAULT_TXPOWER 0x1010 |
| 565 | #define EEPROM_DEFAULT_HT2T_TXPWR 0x10 | 589 | #define EEPROM_DEFAULT_HT2T_TXPWR 0x10 |
| 566 | 590 | ||
| 567 | #define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3 | 591 | #define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3 |
| 568 | #define EEPROM_DEFAULT_THERMALMETER 0x12 | 592 | #define EEPROM_DEFAULT_THERMALMETER 0x12 |
| 569 | #define EEPROM_DEFAULT_ANTTXPOWERDIFF 0x0 | 593 | #define EEPROM_DEFAULT_ANTTXPOWERDIFF 0x0 |
| 570 | #define EEPROM_DEFAULT_TXPWDIFF_CRYSTALCAP 0x5 | 594 | #define EEPROM_DEFAULT_TXPWDIFF_CRYSTALCAP 0x5 |
| 571 | #define EEPROM_DEFAULT_TXPOWERLEVEL 0x22 | 595 | #define EEPROM_DEFAULT_TXPOWERLEVEL 0x22 |
| 572 | #define EEPROM_DEFAULT_HT40_2SDIFF 0x0 | 596 | #define EEPROM_DEFAULT_HT40_2SDIFF 0x0 |
| 573 | #define EEPROM_DEFAULT_HT20_DIFF 2 | 597 | #define EEPROM_DEFAULT_HT20_DIFF 2 |
| 574 | #define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3 | 598 | #define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3 |
| 575 | #define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0 | 599 | #define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0 |
| 576 | #define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0 | 600 | #define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0 |
| 577 | 601 | ||
| 578 | 602 | #define EEPROM_DEFAULT_PID 0x1234 | |
| 579 | #define EEPROM_DEFAULT_PID 0x1234 | 603 | #define EEPROM_DEFAULT_VID 0x5678 |
| 580 | #define EEPROM_DEFAULT_VID 0x5678 | 604 | #define EEPROM_DEFAULT_CUSTOMERID 0xAB |
| 581 | #define EEPROM_DEFAULT_CUSTOMERID 0xAB | ||
| 582 | #define EEPROM_DEFAULT_SUBCUSTOMERID 0xCD | 605 | #define EEPROM_DEFAULT_SUBCUSTOMERID 0xCD |
| 583 | #define EEPROM_DEFAULT_VERSION 0 | 606 | #define EEPROM_DEFAULT_VERSION 0 |
| 584 | 607 | ||
| 585 | #define EEPROM_CHANNEL_PLAN_FCC 0x0 | 608 | #define EEPROM_CHANNEL_PLAN_FCC 0x0 |
| 586 | #define EEPROM_CHANNEL_PLAN_IC 0x1 | 609 | #define EEPROM_CHANNEL_PLAN_IC 0x1 |
| 587 | #define EEPROM_CHANNEL_PLAN_ETSI 0x2 | 610 | #define EEPROM_CHANNEL_PLAN_ETSI 0x2 |
| 588 | #define EEPROM_CHANNEL_PLAN_SPAIN 0x3 | 611 | #define EEPROM_CHANNEL_PLAN_SPAIN 0x3 |
| 589 | #define EEPROM_CHANNEL_PLAN_FRANCE 0x4 | 612 | #define EEPROM_CHANNEL_PLAN_FRANCE 0x4 |
| 590 | #define EEPROM_CHANNEL_PLAN_MKK 0x5 | 613 | #define EEPROM_CHANNEL_PLAN_MKK 0x5 |
| 591 | #define EEPROM_CHANNEL_PLAN_MKK1 0x6 | 614 | #define EEPROM_CHANNEL_PLAN_MKK1 0x6 |
| 592 | #define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 | 615 | #define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 |
| 593 | #define EEPROM_CHANNEL_PLAN_TELEC 0x8 | 616 | #define EEPROM_CHANNEL_PLAN_TELEC 0x8 |
| 594 | #define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 | 617 | #define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 |
| 595 | #define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA | 618 | #define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA |
| 596 | #define EEPROM_CHANNEL_PLAN_NCC 0xB | 619 | #define EEPROM_CHANNEL_PLAN_NCC 0xB |
| 597 | #define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 | 620 | #define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 |
| 598 | 621 | ||
| 599 | #define EEPROM_CID_DEFAULT 0x0 | 622 | #define EEPROM_CID_DEFAULT 0x0 |
| 600 | #define EEPROM_CID_TOSHIBA 0x4 | 623 | #define EEPROM_CID_TOSHIBA 0x4 |
| 601 | #define EEPROM_CID_CCX 0x10 | 624 | #define EEPROM_CID_CCX 0x10 |
| 602 | #define EEPROM_CID_QMI 0x0D | 625 | #define EEPROM_CID_QMI 0x0D |
| 603 | #define EEPROM_CID_WHQL 0xFE | 626 | #define EEPROM_CID_WHQL 0xFE |
| 604 | 627 | ||
| 605 | #define RTL8192_EEPROM_ID 0x8129 | 628 | #define RTL8192_EEPROM_ID 0x8129 |
| 606 | 629 | ||
| 607 | #define RTL8190_EEPROM_ID 0x8129 | 630 | #define RTL8190_EEPROM_ID 0x8129 |
| 608 | #define EEPROM_HPON 0x02 | 631 | #define EEPROM_HPON 0x02 |
| 609 | #define EEPROM_CLK 0x06 | 632 | #define EEPROM_CLK 0x06 |
| 610 | #define EEPROM_TESTR 0x08 | 633 | #define EEPROM_TESTR 0x08 |
| 611 | 634 | ||
| 612 | #define EEPROM_VID 0x49 | 635 | #define EEPROM_VID 0x49 |
| 613 | #define EEPROM_DID 0x4B | 636 | #define EEPROM_DID 0x4B |
| 614 | #define EEPROM_SVID 0x4D | 637 | #define EEPROM_SVID 0x4D |
| 615 | #define EEPROM_SMID 0x4F | 638 | #define EEPROM_SMID 0x4F |
| 616 | 639 | ||
| 617 | #define EEPROM_MAC_ADDR 0x67 | 640 | #define EEPROM_MAC_ADDR 0x67 |
| 618 | 641 | ||
| 619 | #define EEPROM_CCK_TX_PWR_INX 0x5A | 642 | #define EEPROM_CCK_TX_PWR_INX 0x5A |
| 620 | #define EEPROM_HT40_1S_TX_PWR_INX 0x60 | 643 | #define EEPROM_HT40_1S_TX_PWR_INX 0x60 |
| 621 | #define EEPROM_HT40_2S_TX_PWR_INX_DIFF 0x66 | 644 | #define EEPROM_HT40_2S_TX_PWR_INX_DIFF 0x66 |
| 622 | #define EEPROM_HT20_TX_PWR_INX_DIFF 0x69 | 645 | #define EEPROM_HT20_TX_PWR_INX_DIFF 0x69 |
| 623 | #define EEPROM_OFDM_TX_PWR_INX_DIFF 0x6C | 646 | #define EEPROM_OFDM_TX_PWR_INX_DIFF 0x6C |
| 624 | #define EEPROM_HT40_MAX_PWR_OFFSET 0x25 | 647 | #define EEPROM_HT40_MAX_PWR_OFFSET 0x25 |
| 625 | #define EEPROM_HT20_MAX_PWR_OFFSET 0x22 | 648 | #define EEPROM_HT20_MAX_PWR_OFFSET 0x22 |
| 626 | 649 | ||
| 627 | #define EEPROM_THERMAL_METER 0x2a | 650 | #define EEPROM_THERMAL_METER 0x2a |
| 628 | #define EEPROM_XTAL_K 0x78 | 651 | #define EEPROM_XTAL_K 0x78 |
| 629 | #define EEPROM_RF_OPT1 0x79 | 652 | #define EEPROM_RF_OPT1 0x79 |
| 630 | #define EEPROM_RF_OPT2 0x7A | 653 | #define EEPROM_RF_OPT2 0x7A |
| 631 | #define EEPROM_RF_OPT3 0x7B | 654 | #define EEPROM_RF_OPT3 0x7B |
| 632 | #define EEPROM_RF_OPT4 0x7C | 655 | #define EEPROM_RF_OPT4 0x7C |
| 633 | #define EEPROM_CHANNEL_PLAN 0x28 | 656 | #define EEPROM_CHANNEL_PLAN 0x28 |
| 634 | #define EEPROM_VERSION 0x30 | 657 | #define EEPROM_VERSION 0x30 |
| 635 | #define EEPROM_CUSTOMER_ID 0x31 | 658 | #define EEPROM_CUSTOMER_ID 0x31 |
| 636 | 659 | ||
| 637 | #define EEPROM_PWRDIFF 0x54 | 660 | #define EEPROM_PWRDIFF 0x54 |
| 638 | 661 | ||
| 639 | #define EEPROM_TXPOWERCCK 0x10 | 662 | #define EEPROM_TXPOWERCCK 0x10 |
| 640 | #define EEPROM_TXPOWERHT40_1S 0x16 | 663 | #define EEPROM_TXPOWERHT40_1S 0x16 |
| 641 | #define EEPROM_TXPOWERHT40_2SDIFF 0x66 | 664 | #define EEPROM_TXPOWERHT40_2SDIFF 0x66 |
| 642 | #define EEPROM_TXPOWERHT20DIFF 0x1C | 665 | #define EEPROM_TXPOWERHT20DIFF 0x1C |
| 643 | #define EEPROM_TXPOWER_OFDMDIFF 0x1F | 666 | #define EEPROM_TXPOWER_OFDMDIFF 0x1F |
| 644 | 667 | ||
| 645 | #define EEPROM_TXPWR_GROUP 0x22 | 668 | #define EEPROM_TXPWR_GROUP 0x22 |
| 646 | 669 | ||
| @@ -649,169 +672,169 @@ | |||
| 649 | 672 | ||
| 650 | #define EEPROM_CHANNELPLAN 0x28 | 673 | #define EEPROM_CHANNELPLAN 0x28 |
| 651 | 674 | ||
| 652 | #define RF_OPTION1 0x2B | 675 | #define RF_OPTION1 0x2B |
| 653 | #define RF_OPTION2 0x2C | 676 | #define RF_OPTION2 0x2C |
| 654 | #define RF_OPTION3 0x2D | 677 | #define RF_OPTION3 0x2D |
| 655 | #define RF_OPTION4 0x2E | 678 | #define RF_OPTION4 0x2E |
| 656 | 679 | ||
| 657 | #define STOPBECON BIT(6) | 680 | #define STOPBECON BIT(6) |
| 658 | #define STOPHIGHT BIT(5) | 681 | #define STOPHIGHT BIT(5) |
| 659 | #define STOPMGT BIT(4) | 682 | #define STOPMGT BIT(4) |
| 660 | #define STOPVO BIT(3) | 683 | #define STOPVO BIT(3) |
| 661 | #define STOPVI BIT(2) | 684 | #define STOPVI BIT(2) |
| 662 | #define STOPBE BIT(1) | 685 | #define STOPBE BIT(1) |
| 663 | #define STOPBK BIT(0) | 686 | #define STOPBK BIT(0) |
| 664 | 687 | ||
| 665 | #define RCR_APPFCS BIT(31) | 688 | #define RCR_APPFCS BIT(31) |
| 666 | #define RCR_APP_MIC BIT(30) | 689 | #define RCR_APP_MIC BIT(30) |
| 667 | #define RCR_APP_ICV BIT(29) | 690 | #define RCR_APP_ICV BIT(29) |
| 668 | #define RCR_APP_PHYST_RXFF BIT(28) | 691 | #define RCR_APP_PHYST_RXFF BIT(28) |
| 669 | #define RCR_APP_BA_SSN BIT(27) | 692 | #define RCR_APP_BA_SSN BIT(27) |
| 670 | #define RCR_ENMBID BIT(24) | 693 | #define RCR_ENMBID BIT(24) |
| 671 | #define RCR_LSIGEN BIT(23) | 694 | #define RCR_LSIGEN BIT(23) |
| 672 | #define RCR_MFBEN BIT(22) | 695 | #define RCR_MFBEN BIT(22) |
| 673 | #define RCR_HTC_LOC_CTRL BIT(14) | 696 | #define RCR_HTC_LOC_CTRL BIT(14) |
| 674 | #define RCR_AMF BIT(13) | 697 | #define RCR_AMF BIT(13) |
| 675 | #define RCR_ACF BIT(12) | 698 | #define RCR_ACF BIT(12) |
| 676 | #define RCR_ADF BIT(11) | 699 | #define RCR_ADF BIT(11) |
| 677 | #define RCR_AICV BIT(9) | 700 | #define RCR_AICV BIT(9) |
| 678 | #define RCR_ACRC32 BIT(8) | 701 | #define RCR_ACRC32 BIT(8) |
| 679 | #define RCR_CBSSID_BCN BIT(7) | 702 | #define RCR_CBSSID_BCN BIT(7) |
| 680 | #define RCR_CBSSID_DATA BIT(6) | 703 | #define RCR_CBSSID_DATA BIT(6) |
| 681 | #define RCR_CBSSID RCR_CBSSID_DATA | 704 | #define RCR_CBSSID RCR_CBSSID_DATA |
| 682 | #define RCR_APWRMGT BIT(5) | 705 | #define RCR_APWRMGT BIT(5) |
| 683 | #define RCR_ADD3 BIT(4) | 706 | #define RCR_ADD3 BIT(4) |
| 684 | #define RCR_AB BIT(3) | 707 | #define RCR_AB BIT(3) |
| 685 | #define RCR_AM BIT(2) | 708 | #define RCR_AM BIT(2) |
| 686 | #define RCR_APM BIT(1) | 709 | #define RCR_APM BIT(1) |
| 687 | #define RCR_AAP BIT(0) | 710 | #define RCR_AAP BIT(0) |
| 688 | #define RCR_MXDMA_OFFSET 8 | 711 | #define RCR_MXDMA_OFFSET 8 |
| 689 | #define RCR_FIFO_OFFSET 13 | 712 | #define RCR_FIFO_OFFSET 13 |
| 690 | 713 | ||
| 691 | #define RSV_CTRL 0x001C | 714 | #define RSV_CTRL 0x001C |
| 692 | #define RD_CTRL 0x0524 | 715 | #define RD_CTRL 0x0524 |
| 693 | 716 | ||
| 694 | #define REG_USB_INFO 0xFE17 | 717 | #define REG_USB_INFO 0xFE17 |
| 695 | #define REG_USB_SPECIAL_OPTION 0xFE55 | 718 | #define REG_USB_SPECIAL_OPTION 0xFE55 |
| 696 | #define REG_USB_DMA_AGG_TO 0xFE5B | 719 | #define REG_USB_DMA_AGG_TO 0xFE5B |
| 697 | #define REG_USB_AGG_TO 0xFE5C | 720 | #define REG_USB_AGG_TO 0xFE5C |
| 698 | #define REG_USB_AGG_TH 0xFE5D | 721 | #define REG_USB_AGG_TH 0xFE5D |
| 699 | 722 | ||
| 700 | #define REG_USB_VID 0xFE60 | 723 | #define REG_USB_VID 0xFE60 |
| 701 | #define REG_USB_PID 0xFE62 | 724 | #define REG_USB_PID 0xFE62 |
| 702 | #define REG_USB_OPTIONAL 0xFE64 | 725 | #define REG_USB_OPTIONAL 0xFE64 |
| 703 | #define REG_USB_CHIRP_K 0xFE65 | 726 | #define REG_USB_CHIRP_K 0xFE65 |
| 704 | #define REG_USB_PHY 0xFE66 | 727 | #define REG_USB_PHY 0xFE66 |
| 705 | #define REG_USB_MAC_ADDR 0xFE70 | 728 | #define REG_USB_MAC_ADDR 0xFE70 |
| 706 | #define REG_USB_HRPWM 0xFE58 | 729 | #define REG_USB_HRPWM 0xFE58 |
| 707 | #define REG_USB_HCPWM 0xFE57 | 730 | #define REG_USB_HCPWM 0xFE57 |
| 708 | 731 | ||
| 709 | #define SW18_FPWM BIT(3) | 732 | #define SW18_FPWM BIT(3) |
| 710 | 733 | ||
| 711 | #define ISO_MD2PP BIT(0) | 734 | #define ISO_MD2PP BIT(0) |
| 712 | #define ISO_UA2USB BIT(1) | 735 | #define ISO_UA2USB BIT(1) |
| 713 | #define ISO_UD2CORE BIT(2) | 736 | #define ISO_UD2CORE BIT(2) |
| 714 | #define ISO_PA2PCIE BIT(3) | 737 | #define ISO_PA2PCIE BIT(3) |
| 715 | #define ISO_PD2CORE BIT(4) | 738 | #define ISO_PD2CORE BIT(4) |
| 716 | #define ISO_IP2MAC BIT(5) | 739 | #define ISO_IP2MAC BIT(5) |
| 717 | #define ISO_DIOP BIT(6) | 740 | #define ISO_DIOP BIT(6) |
| 718 | #define ISO_DIOE BIT(7) | 741 | #define ISO_DIOE BIT(7) |
| 719 | #define ISO_EB2CORE BIT(8) | 742 | #define ISO_EB2CORE BIT(8) |
| 720 | #define ISO_DIOR BIT(9) | 743 | #define ISO_DIOR BIT(9) |
| 721 | 744 | ||
| 722 | #define PWC_EV25V BIT(14) | 745 | #define PWC_EV25V BIT(14) |
| 723 | #define PWC_EV12V BIT(15) | 746 | #define PWC_EV12V BIT(15) |
| 724 | 747 | ||
| 725 | #define FEN_BBRSTB BIT(0) | 748 | #define FEN_BBRSTB BIT(0) |
| 726 | #define FEN_BB_GLB_RSTn BIT(1) | 749 | #define FEN_BB_GLB_RSTN BIT(1) |
| 727 | #define FEN_USBA BIT(2) | 750 | #define FEN_USBA BIT(2) |
| 728 | #define FEN_UPLL BIT(3) | 751 | #define FEN_UPLL BIT(3) |
| 729 | #define FEN_USBD BIT(4) | 752 | #define FEN_USBD BIT(4) |
| 730 | #define FEN_DIO_PCIE BIT(5) | 753 | #define FEN_DIO_PCIE BIT(5) |
| 731 | #define FEN_PCIEA BIT(6) | 754 | #define FEN_PCIEA BIT(6) |
| 732 | #define FEN_PPLL BIT(7) | 755 | #define FEN_PPLL BIT(7) |
| 733 | #define FEN_PCIED BIT(8) | 756 | #define FEN_PCIED BIT(8) |
| 734 | #define FEN_DIOE BIT(9) | 757 | #define FEN_DIOE BIT(9) |
| 735 | #define FEN_CPUEN BIT(10) | 758 | #define FEN_CPUEN BIT(10) |
| 736 | #define FEN_DCORE BIT(11) | 759 | #define FEN_DCORE BIT(11) |
| 737 | #define FEN_ELDR BIT(12) | 760 | #define FEN_ELDR BIT(12) |
| 738 | #define FEN_DIO_RF BIT(13) | 761 | #define FEN_DIO_RF BIT(13) |
| 739 | #define FEN_HWPDN BIT(14) | 762 | #define FEN_HWPDN BIT(14) |
| 740 | #define FEN_MREGEN BIT(15) | 763 | #define FEN_MREGEN BIT(15) |
| 741 | 764 | ||
| 742 | #define PFM_LDALL BIT(0) | 765 | #define PFM_LDALL BIT(0) |
| 743 | #define PFM_ALDN BIT(1) | 766 | #define PFM_ALDN BIT(1) |
| 744 | #define PFM_LDKP BIT(2) | 767 | #define PFM_LDKP BIT(2) |
| 745 | #define PFM_WOWL BIT(3) | 768 | #define PFM_WOWL BIT(3) |
| 746 | #define EnPDN BIT(4) | 769 | #define ENPDN BIT(4) |
| 747 | #define PDN_PL BIT(5) | 770 | #define PDN_PL BIT(5) |
| 748 | #define APFM_ONMAC BIT(8) | 771 | #define APFM_ONMAC BIT(8) |
| 749 | #define APFM_OFF BIT(9) | 772 | #define APFM_OFF BIT(9) |
| 750 | #define APFM_RSM BIT(10) | 773 | #define APFM_RSM BIT(10) |
| 751 | #define AFSM_HSUS BIT(11) | 774 | #define AFSM_HSUS BIT(11) |
| 752 | #define AFSM_PCIE BIT(12) | 775 | #define AFSM_PCIE BIT(12) |
| 753 | #define APDM_MAC BIT(13) | 776 | #define APDM_MAC BIT(13) |
| 754 | #define APDM_HOST BIT(14) | 777 | #define APDM_HOST BIT(14) |
| 755 | #define APDM_HPDN BIT(15) | 778 | #define APDM_HPDN BIT(15) |
| 756 | #define RDY_MACON BIT(16) | 779 | #define RDY_MACON BIT(16) |
| 757 | #define SUS_HOST BIT(17) | 780 | #define SUS_HOST BIT(17) |
| 758 | #define ROP_ALD BIT(20) | 781 | #define ROP_ALD BIT(20) |
| 759 | #define ROP_PWR BIT(21) | 782 | #define ROP_PWR BIT(21) |
| 760 | #define ROP_SPS BIT(22) | 783 | #define ROP_SPS BIT(22) |
| 761 | #define SOP_MRST BIT(25) | 784 | #define SOP_MRST BIT(25) |
| 762 | #define SOP_FUSE BIT(26) | 785 | #define SOP_FUSE BIT(26) |
| 763 | #define SOP_ABG BIT(27) | 786 | #define SOP_ABG BIT(27) |
| 764 | #define SOP_AMB BIT(28) | 787 | #define SOP_AMB BIT(28) |
| 765 | #define SOP_RCK BIT(29) | 788 | #define SOP_RCK BIT(29) |
| 766 | #define SOP_A8M BIT(30) | 789 | #define SOP_A8M BIT(30) |
| 767 | #define XOP_BTCK BIT(31) | 790 | #define XOP_BTCK BIT(31) |
| 768 | 791 | ||
| 769 | #define ANAD16V_EN BIT(0) | 792 | #define ANAD16V_EN BIT(0) |
| 770 | #define ANA8M BIT(1) | 793 | #define ANA8M BIT(1) |
| 771 | #define MACSLP BIT(4) | 794 | #define MACSLP BIT(4) |
| 772 | #define LOADER_CLK_EN BIT(5) | 795 | #define LOADER_CLK_EN BIT(5) |
| 773 | #define _80M_SSC_DIS BIT(7) | 796 | #define _80M_SSC_DIS BIT(7) |
| 774 | #define _80M_SSC_EN_HO BIT(8) | 797 | #define _80M_SSC_EN_HO BIT(8) |
| 775 | #define PHY_SSC_RSTB BIT(9) | 798 | #define PHY_SSC_RSTB BIT(9) |
| 776 | #define SEC_CLK_EN BIT(10) | 799 | #define SEC_CLK_EN BIT(10) |
| 777 | #define MAC_CLK_EN BIT(11) | 800 | #define MAC_CLK_EN BIT(11) |
| 778 | #define SYS_CLK_EN BIT(12) | 801 | #define SYS_CLK_EN BIT(12) |
| 779 | #define RING_CLK_EN BIT(13) | 802 | #define RING_CLK_EN BIT(13) |
| 780 | 803 | ||
| 781 | #define BOOT_FROM_EEPROM BIT(4) | 804 | #define BOOT_FROM_EEPROM BIT(4) |
| 782 | #define EEPROM_EN BIT(5) | 805 | #define EEPROM_EN BIT(5) |
| 783 | 806 | ||
| 784 | #define AFE_BGEN BIT(0) | 807 | #define AFE_BGEN BIT(0) |
| 785 | #define AFE_MBEN BIT(1) | 808 | #define AFE_MBEN BIT(1) |
| 786 | #define MAC_ID_EN BIT(7) | 809 | #define MAC_ID_EN BIT(7) |
| 787 | 810 | ||
| 788 | #define WLOCK_ALL BIT(0) | 811 | #define WLOCK_ALL BIT(0) |
| 789 | #define WLOCK_00 BIT(1) | 812 | #define WLOCK_00 BIT(1) |
| 790 | #define WLOCK_04 BIT(2) | 813 | #define WLOCK_04 BIT(2) |
| 791 | #define WLOCK_08 BIT(3) | 814 | #define WLOCK_08 BIT(3) |
| 792 | #define WLOCK_40 BIT(4) | 815 | #define WLOCK_40 BIT(4) |
| 793 | #define R_DIS_PRST_0 BIT(5) | 816 | #define R_DIS_PRST_0 BIT(5) |
| 794 | #define R_DIS_PRST_1 BIT(6) | 817 | #define R_DIS_PRST_1 BIT(6) |
| 795 | #define LOCK_ALL_EN BIT(7) | 818 | #define LOCK_ALL_EN BIT(7) |
| 796 | 819 | ||
| 797 | #define RF_EN BIT(0) | 820 | #define RF_EN BIT(0) |
| 798 | #define RF_RSTB BIT(1) | 821 | #define RF_RSTB BIT(1) |
| 799 | #define RF_SDMRSTB BIT(2) | 822 | #define RF_SDMRSTB BIT(2) |
| 800 | 823 | ||
| 801 | #define LDA15_EN BIT(0) | 824 | #define LDA15_EN BIT(0) |
| 802 | #define LDA15_STBY BIT(1) | 825 | #define LDA15_STBY BIT(1) |
| 803 | #define LDA15_OBUF BIT(2) | 826 | #define LDA15_OBUF BIT(2) |
| 804 | #define LDA15_REG_VOS BIT(3) | 827 | #define LDA15_REG_VOS BIT(3) |
| 805 | #define _LDA15_VOADJ(x) (((x) & 0x7) << 4) | 828 | #define _LDA15_VOADJ(x) (((x) & 0x7) << 4) |
| 806 | 829 | ||
| 807 | #define LDV12_EN BIT(0) | 830 | #define LDV12_EN BIT(0) |
| 808 | #define LDV12_SDBY BIT(1) | 831 | #define LDV12_SDBY BIT(1) |
| 809 | #define LPLDO_HSM BIT(2) | 832 | #define LPLDO_HSM BIT(2) |
| 810 | #define LPLDO_LSM_DIS BIT(3) | 833 | #define LPLDO_LSM_DIS BIT(3) |
| 811 | #define _LDV12_VADJ(x) (((x) & 0xF) << 4) | 834 | #define _LDV12_VADJ(x) (((x) & 0xF) << 4) |
| 812 | 835 | ||
| 813 | #define XTAL_EN BIT(0) | 836 | #define XTAL_EN BIT(0) |
| 814 | #define XTAL_BSEL BIT(1) | 837 | #define XTAL_BSEL BIT(1) |
| 815 | #define _XTAL_BOSC(x) (((x) & 0x3) << 2) | 838 | #define _XTAL_BOSC(x) (((x) & 0x3) << 2) |
| 816 | #define _XTAL_CADJ(x) (((x) & 0xF) << 4) | 839 | #define _XTAL_CADJ(x) (((x) & 0xF) << 4) |
| 817 | #define XTAL_GATE_USB BIT(8) | 840 | #define XTAL_GATE_USB BIT(8) |
| @@ -826,146 +849,146 @@ | |||
| 826 | #define _XTAL_BT_DRV(x) (((x) & 0x3) << 21) | 849 | #define _XTAL_BT_DRV(x) (((x) & 0x3) << 21) |
| 827 | #define _XTAL_GPIO(x) (((x) & 0x7) << 23) | 850 | #define _XTAL_GPIO(x) (((x) & 0x7) << 23) |
| 828 | 851 | ||
| 829 | #define CKDLY_AFE BIT(26) | 852 | #define CKDLY_AFE BIT(26) |
| 830 | #define CKDLY_USB BIT(27) | 853 | #define CKDLY_USB BIT(27) |
| 831 | #define CKDLY_DIG BIT(28) | 854 | #define CKDLY_DIG BIT(28) |
| 832 | #define CKDLY_BT BIT(29) | 855 | #define CKDLY_BT BIT(29) |
| 833 | 856 | ||
| 834 | #define APLL_EN BIT(0) | 857 | #define APLL_EN BIT(0) |
| 835 | #define APLL_320_EN BIT(1) | 858 | #define APLL_320_EN BIT(1) |
| 836 | #define APLL_FREF_SEL BIT(2) | 859 | #define APLL_FREF_SEL BIT(2) |
| 837 | #define APLL_EDGE_SEL BIT(3) | 860 | #define APLL_EDGE_SEL BIT(3) |
| 838 | #define APLL_WDOGB BIT(4) | 861 | #define APLL_WDOGB BIT(4) |
| 839 | #define APLL_LPFEN BIT(5) | 862 | #define APLL_LPFEN BIT(5) |
| 840 | 863 | ||
| 841 | #define APLL_REF_CLK_13MHZ 0x1 | 864 | #define APLL_REF_CLK_13MHZ 0x1 |
| 842 | #define APLL_REF_CLK_19_2MHZ 0x2 | 865 | #define APLL_REF_CLK_19_2MHZ 0x2 |
| 843 | #define APLL_REF_CLK_20MHZ 0x3 | 866 | #define APLL_REF_CLK_20MHZ 0x3 |
| 844 | #define APLL_REF_CLK_25MHZ 0x4 | 867 | #define APLL_REF_CLK_25MHZ 0x4 |
| 845 | #define APLL_REF_CLK_26MHZ 0x5 | 868 | #define APLL_REF_CLK_26MHZ 0x5 |
| 846 | #define APLL_REF_CLK_38_4MHZ 0x6 | 869 | #define APLL_REF_CLK_38_4MHZ 0x6 |
| 847 | #define APLL_REF_CLK_40MHZ 0x7 | 870 | #define APLL_REF_CLK_40MHZ 0x7 |
| 848 | 871 | ||
| 849 | #define APLL_320EN BIT(14) | 872 | #define APLL_320EN BIT(14) |
| 850 | #define APLL_80EN BIT(15) | 873 | #define APLL_80EN BIT(15) |
| 851 | #define APLL_1MEN BIT(24) | 874 | #define APLL_1MEN BIT(24) |
| 852 | 875 | ||
| 853 | #define ALD_EN BIT(18) | 876 | #define ALD_EN BIT(18) |
| 854 | #define EF_PD BIT(19) | 877 | #define EF_PD BIT(19) |
| 855 | #define EF_FLAG BIT(31) | 878 | #define EF_FLAG BIT(31) |
| 856 | 879 | ||
| 857 | #define EF_TRPT BIT(7) | 880 | #define EF_TRPT BIT(7) |
| 858 | #define LDOE25_EN BIT(31) | 881 | #define LDOE25_EN BIT(31) |
| 859 | 882 | ||
| 860 | #define RSM_EN BIT(0) | 883 | #define RSM_EN BIT(0) |
| 861 | #define Timer_EN BIT(4) | 884 | #define TIMER_EN BIT(4) |
| 862 | 885 | ||
| 863 | #define TRSW0EN BIT(2) | 886 | #define TRSW0EN BIT(2) |
| 864 | #define TRSW1EN BIT(3) | 887 | #define TRSW1EN BIT(3) |
| 865 | #define EROM_EN BIT(4) | 888 | #define EROM_EN BIT(4) |
| 866 | #define EnBT BIT(5) | 889 | #define ENBT BIT(5) |
| 867 | #define EnUart BIT(8) | 890 | #define ENUART BIT(8) |
| 868 | #define Uart_910 BIT(9) | 891 | #define UART_910 BIT(9) |
| 869 | #define EnPMAC BIT(10) | 892 | #define ENPMAC BIT(10) |
| 870 | #define SIC_SWRST BIT(11) | 893 | #define SIC_SWRST BIT(11) |
| 871 | #define EnSIC BIT(12) | 894 | #define ENSIC BIT(12) |
| 872 | #define SIC_23 BIT(13) | 895 | #define SIC_23 BIT(13) |
| 873 | #define EnHDP BIT(14) | 896 | #define ENHDP BIT(14) |
| 874 | #define SIC_LBK BIT(15) | 897 | #define SIC_LBK BIT(15) |
| 875 | 898 | ||
| 876 | #define LED0PL BIT(4) | 899 | #define LED0PL BIT(4) |
| 877 | #define LED1PL BIT(12) | 900 | #define LED1PL BIT(12) |
| 878 | #define LED0DIS BIT(7) | 901 | #define LED0DIS BIT(7) |
| 879 | 902 | ||
| 880 | #define MCUFWDL_EN BIT(0) | 903 | #define MCUFWDL_EN BIT(0) |
| 881 | #define MCUFWDL_RDY BIT(1) | 904 | #define MCUFWDL_RDY BIT(1) |
| 882 | #define FWDL_ChkSum_rpt BIT(2) | 905 | #define FWDL_CHKSUM_RPT BIT(2) |
| 883 | #define MACINI_RDY BIT(3) | 906 | #define MACINI_RDY BIT(3) |
| 884 | #define BBINI_RDY BIT(4) | 907 | #define BBINI_RDY BIT(4) |
| 885 | #define RFINI_RDY BIT(5) | 908 | #define RFINI_RDY BIT(5) |
| 886 | #define WINTINI_RDY BIT(6) | 909 | #define WINTINI_RDY BIT(6) |
| 887 | #define CPRST BIT(23) | 910 | #define CPRST BIT(23) |
| 888 | 911 | ||
| 889 | #define XCLK_VLD BIT(0) | 912 | #define XCLK_VLD BIT(0) |
| 890 | #define ACLK_VLD BIT(1) | 913 | #define ACLK_VLD BIT(1) |
| 891 | #define UCLK_VLD BIT(2) | 914 | #define UCLK_VLD BIT(2) |
| 892 | #define PCLK_VLD BIT(3) | 915 | #define PCLK_VLD BIT(3) |
| 893 | #define PCIRSTB BIT(4) | 916 | #define PCIRSTB BIT(4) |
| 894 | #define V15_VLD BIT(5) | 917 | #define V15_VLD BIT(5) |
| 895 | #define TRP_B15V_EN BIT(7) | 918 | #define TRP_B15V_EN BIT(7) |
| 896 | #define SIC_IDLE BIT(8) | 919 | #define SIC_IDLE BIT(8) |
| 897 | #define BD_MAC2 BIT(9) | 920 | #define BD_MAC2 BIT(9) |
| 898 | #define BD_MAC1 BIT(10) | 921 | #define BD_MAC1 BIT(10) |
| 899 | #define IC_MACPHY_MODE BIT(11) | 922 | #define IC_MACPHY_MODE BIT(11) |
| 900 | #define BT_FUNC BIT(16) | 923 | #define BT_FUNC BIT(16) |
| 901 | #define VENDOR_ID BIT(19) | 924 | #define VENDOR_ID BIT(19) |
| 902 | #define PAD_HWPD_IDN BIT(22) | 925 | #define PAD_HWPD_IDN BIT(22) |
| 903 | #define TRP_VAUX_EN BIT(23) | 926 | #define TRP_VAUX_EN BIT(23) |
| 904 | #define TRP_BT_EN BIT(24) | 927 | #define TRP_BT_EN BIT(24) |
| 905 | #define BD_PKG_SEL BIT(25) | 928 | #define BD_PKG_SEL BIT(25) |
| 906 | #define BD_HCI_SEL BIT(26) | 929 | #define BD_HCI_SEL BIT(26) |
| 907 | #define TYPE_ID BIT(27) | 930 | #define TYPE_ID BIT(27) |
| 908 | 931 | ||
| 909 | #define CHIP_VER_RTL_MASK 0xF000 | 932 | #define CHIP_VER_RTL_MASK 0xF000 |
| 910 | #define CHIP_VER_RTL_SHIFT 12 | 933 | #define CHIP_VER_RTL_SHIFT 12 |
| 911 | 934 | ||
| 912 | #define REG_LBMODE (REG_CR + 3) | 935 | #define REG_LBMODE (REG_CR + 3) |
| 913 | 936 | ||
| 914 | #define HCI_TXDMA_EN BIT(0) | 937 | #define HCI_TXDMA_EN BIT(0) |
| 915 | #define HCI_RXDMA_EN BIT(1) | 938 | #define HCI_RXDMA_EN BIT(1) |
| 916 | #define TXDMA_EN BIT(2) | 939 | #define TXDMA_EN BIT(2) |
| 917 | #define RXDMA_EN BIT(3) | 940 | #define RXDMA_EN BIT(3) |
| 918 | #define PROTOCOL_EN BIT(4) | 941 | #define PROTOCOL_EN BIT(4) |
| 919 | #define SCHEDULE_EN BIT(5) | 942 | #define SCHEDULE_EN BIT(5) |
| 920 | #define MACTXEN BIT(6) | 943 | #define MACTXEN BIT(6) |
| 921 | #define MACRXEN BIT(7) | 944 | #define MACRXEN BIT(7) |
| 922 | #define ENSWBCN BIT(8) | 945 | #define ENSWBCN BIT(8) |
| 923 | #define ENSEC BIT(9) | 946 | #define ENSEC BIT(9) |
| 924 | 947 | ||
| 925 | #define _NETTYPE(x) (((x) & 0x3) << 16) | 948 | #define _NETTYPE(x) (((x) & 0x3) << 16) |
| 926 | #define MASK_NETTYPE 0x30000 | 949 | #define MASK_NETTYPE 0x30000 |
| 927 | #define NT_NO_LINK 0x0 | 950 | #define NT_NO_LINK 0x0 |
| 928 | #define NT_LINK_AD_HOC 0x1 | 951 | #define NT_LINK_AD_HOC 0x1 |
| 929 | #define NT_LINK_AP 0x2 | 952 | #define NT_LINK_AP 0x2 |
| 930 | #define NT_AS_AP 0x3 | 953 | #define NT_AS_AP 0x3 |
| 931 | 954 | ||
| 932 | #define _LBMODE(x) (((x) & 0xF) << 24) | 955 | #define _LBMODE(x) (((x) & 0xF) << 24) |
| 933 | #define MASK_LBMODE 0xF000000 | 956 | #define MASK_LBMODE 0xF000000 |
| 934 | #define LOOPBACK_NORMAL 0x0 | 957 | #define LOOPBACK_NORMAL 0x0 |
| 935 | #define LOOPBACK_IMMEDIATELY 0xB | 958 | #define LOOPBACK_IMMEDIATELY 0xB |
| 936 | #define LOOPBACK_MAC_DELAY 0x3 | 959 | #define LOOPBACK_MAC_DELAY 0x3 |
| 937 | #define LOOPBACK_PHY 0x1 | 960 | #define LOOPBACK_PHY 0x1 |
| 938 | #define LOOPBACK_DMA 0x7 | 961 | #define LOOPBACK_DMA 0x7 |
| 939 | 962 | ||
| 940 | #define GET_RX_PAGE_SIZE(value) ((value) & 0xF) | 963 | #define GET_RX_PAGE_SIZE(value) ((value) & 0xF) |
| 941 | #define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) | 964 | #define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) |
| 942 | #define _PSRX_MASK 0xF | 965 | #define _PSRX_MASK 0xF |
| 943 | #define _PSTX_MASK 0xF0 | 966 | #define _PSTX_MASK 0xF0 |
| 944 | #define _PSRX(x) (x) | 967 | #define _PSRX(x) (x) |
| 945 | #define _PSTX(x) ((x) << 4) | 968 | #define _PSTX(x) ((x) << 4) |
| 946 | 969 | ||
| 947 | #define PBP_64 0x0 | 970 | #define PBP_64 0x0 |
| 948 | #define PBP_128 0x1 | 971 | #define PBP_128 0x1 |
| 949 | #define PBP_256 0x2 | 972 | #define PBP_256 0x2 |
| 950 | #define PBP_512 0x3 | 973 | #define PBP_512 0x3 |
| 951 | #define PBP_1024 0x4 | 974 | #define PBP_1024 0x4 |
| 952 | 975 | ||
| 953 | #define RXDMA_ARBBW_EN BIT(0) | 976 | #define RXDMA_ARBBW_EN BIT(0) |
| 954 | #define RXSHFT_EN BIT(1) | 977 | #define RXSHFT_EN BIT(1) |
| 955 | #define RXDMA_AGG_EN BIT(2) | 978 | #define RXDMA_AGG_EN BIT(2) |
| 956 | #define QS_VO_QUEUE BIT(8) | 979 | #define QS_VO_QUEUE BIT(8) |
| 957 | #define QS_VI_QUEUE BIT(9) | 980 | #define QS_VI_QUEUE BIT(9) |
| 958 | #define QS_BE_QUEUE BIT(10) | 981 | #define QS_BE_QUEUE BIT(10) |
| 959 | #define QS_BK_QUEUE BIT(11) | 982 | #define QS_BK_QUEUE BIT(11) |
| 960 | #define QS_MANAGER_QUEUE BIT(12) | 983 | #define QS_MANAGER_QUEUE BIT(12) |
| 961 | #define QS_HIGH_QUEUE BIT(13) | 984 | #define QS_HIGH_QUEUE BIT(13) |
| 962 | 985 | ||
| 963 | #define HQSEL_VOQ BIT(0) | 986 | #define HQSEL_VOQ BIT(0) |
| 964 | #define HQSEL_VIQ BIT(1) | 987 | #define HQSEL_VIQ BIT(1) |
| 965 | #define HQSEL_BEQ BIT(2) | 988 | #define HQSEL_BEQ BIT(2) |
| 966 | #define HQSEL_BKQ BIT(3) | 989 | #define HQSEL_BKQ BIT(3) |
| 967 | #define HQSEL_MGTQ BIT(4) | 990 | #define HQSEL_MGTQ BIT(4) |
| 968 | #define HQSEL_HIQ BIT(5) | 991 | #define HQSEL_HIQ BIT(5) |
| 969 | 992 | ||
| 970 | #define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) | 993 | #define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) |
| 971 | #define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) | 994 | #define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) |
| @@ -974,9 +997,9 @@ | |||
| 974 | #define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6) | 997 | #define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6) |
| 975 | #define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4) | 998 | #define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4) |
| 976 | 999 | ||
| 977 | #define QUEUE_LOW 1 | 1000 | #define QUEUE_LOW 1 |
| 978 | #define QUEUE_NORMAL 2 | 1001 | #define QUEUE_NORMAL 2 |
| 979 | #define QUEUE_HIGH 3 | 1002 | #define QUEUE_HIGH 3 |
| 980 | 1003 | ||
| 981 | #define _LLT_NO_ACTIVE 0x0 | 1004 | #define _LLT_NO_ACTIVE 0x0 |
| 982 | #define _LLT_WRITE_ACCESS 0x1 | 1005 | #define _LLT_WRITE_ACCESS 0x1 |
| @@ -984,25 +1007,25 @@ | |||
| 984 | 1007 | ||
| 985 | #define _LLT_INIT_DATA(x) ((x) & 0xFF) | 1008 | #define _LLT_INIT_DATA(x) ((x) & 0xFF) |
| 986 | #define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) | 1009 | #define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) |
| 987 | #define _LLT_OP(x) (((x) & 0x3) << 30) | 1010 | #define _LLT_OP(x) (((x) & 0x3) << 30) |
| 988 | #define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) | 1011 | #define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) |
| 989 | 1012 | ||
| 990 | #define BB_WRITE_READ_MASK (BIT(31) | BIT(30)) | 1013 | #define BB_WRITE_READ_MASK (BIT(31) | BIT(30)) |
| 991 | #define BB_WRITE_EN BIT(30) | 1014 | #define BB_WRITE_EN BIT(30) |
| 992 | #define BB_READ_EN BIT(31) | 1015 | #define BB_READ_EN BIT(31) |
| 993 | 1016 | ||
| 994 | #define _HPQ(x) ((x) & 0xFF) | 1017 | #define _HPQ(x) ((x) & 0xFF) |
| 995 | #define _LPQ(x) (((x) & 0xFF) << 8) | 1018 | #define _LPQ(x) (((x) & 0xFF) << 8) |
| 996 | #define _PUBQ(x) (((x) & 0xFF) << 16) | 1019 | #define _PUBQ(x) (((x) & 0xFF) << 16) |
| 997 | #define _NPQ(x) ((x) & 0xFF) | 1020 | #define _NPQ(x) ((x) & 0xFF) |
| 998 | 1021 | ||
| 999 | #define HPQ_PUBLIC_DIS BIT(24) | 1022 | #define HPQ_PUBLIC_DIS BIT(24) |
| 1000 | #define LPQ_PUBLIC_DIS BIT(25) | 1023 | #define LPQ_PUBLIC_DIS BIT(25) |
| 1001 | #define LD_RQPN BIT(31) | 1024 | #define LD_RQPN BIT(31) |
| 1002 | 1025 | ||
| 1003 | #define BCN_VALID BIT(16) | 1026 | #define BCN_VALID BIT(16) |
| 1004 | #define BCN_HEAD(x) (((x) & 0xFF) << 8) | 1027 | #define BCN_HEAD(x) (((x) & 0xFF) << 8) |
| 1005 | #define BCN_HEAD_MASK 0xFF00 | 1028 | #define BCN_HEAD_MASK 0xFF00 |
| 1006 | 1029 | ||
| 1007 | #define BLK_DESC_NUM_SHIFT 4 | 1030 | #define BLK_DESC_NUM_SHIFT 4 |
| 1008 | #define BLK_DESC_NUM_MASK 0xF | 1031 | #define BLK_DESC_NUM_MASK 0xF |
| @@ -1022,9 +1045,9 @@ | |||
| 1022 | 1045 | ||
| 1023 | #define _RRSR_RSC(x) (((x) & 0x3) << 21) | 1046 | #define _RRSR_RSC(x) (((x) & 0x3) << 21) |
| 1024 | #define RRSR_RSC_RESERVED 0x0 | 1047 | #define RRSR_RSC_RESERVED 0x0 |
| 1025 | #define RRSR_RSC_UPPER_SUBCHANNEL 0x1 | 1048 | #define RRSR_RSC_UPPER_SUBCHANNEL 0x1 |
| 1026 | #define RRSR_RSC_LOWER_SUBCHANNEL 0x2 | 1049 | #define RRSR_RSC_LOWER_SUBCHANNEL 0x2 |
| 1027 | #define RRSR_RSC_DUPLICATE_MODE 0x3 | 1050 | #define RRSR_RSC_DUPLICATE_MODE 0x3 |
| 1028 | 1051 | ||
| 1029 | #define USE_SHORT_G1 BIT(20) | 1052 | #define USE_SHORT_G1 BIT(20) |
| 1030 | 1053 | ||
| @@ -1037,8 +1060,8 @@ | |||
| 1037 | #define _AGGLMT_MCS6(x) (((x) & 0xF) << 24) | 1060 | #define _AGGLMT_MCS6(x) (((x) & 0xF) << 24) |
| 1038 | #define _AGGLMT_MCS7(x) (((x) & 0xF) << 28) | 1061 | #define _AGGLMT_MCS7(x) (((x) & 0xF) << 28) |
| 1039 | 1062 | ||
| 1040 | #define RETRY_LIMIT_SHORT_SHIFT 8 | 1063 | #define RETRY_LIMIT_SHORT_SHIFT 8 |
| 1041 | #define RETRY_LIMIT_LONG_SHIFT 0 | 1064 | #define RETRY_LIMIT_LONG_SHIFT 0 |
| 1042 | 1065 | ||
| 1043 | #define _DARF_RC1(x) ((x) & 0x1F) | 1066 | #define _DARF_RC1(x) ((x) & 0x1F) |
| 1044 | #define _DARF_RC2(x) (((x) & 0x1F) << 8) | 1067 | #define _DARF_RC2(x) (((x) & 0x1F) << 8) |
| @@ -1058,123 +1081,123 @@ | |||
| 1058 | #define _RARF_RC7(x) (((x) & 0x1F) << 16) | 1081 | #define _RARF_RC7(x) (((x) & 0x1F) << 16) |
| 1059 | #define _RARF_RC8(x) (((x) & 0x1F) << 24) | 1082 | #define _RARF_RC8(x) (((x) & 0x1F) << 24) |
| 1060 | 1083 | ||
| 1061 | #define AC_PARAM_TXOP_LIMIT_OFFSET 16 | 1084 | #define AC_PARAM_TXOP_LIMIT_OFFSET 16 |
| 1062 | #define AC_PARAM_ECW_MAX_OFFSET 12 | 1085 | #define AC_PARAM_ECW_MAX_OFFSET 12 |
| 1063 | #define AC_PARAM_ECW_MIN_OFFSET 8 | 1086 | #define AC_PARAM_ECW_MIN_OFFSET 8 |
| 1064 | #define AC_PARAM_AIFS_OFFSET 0 | 1087 | #define AC_PARAM_AIFS_OFFSET 0 |
| 1065 | 1088 | ||
| 1066 | #define _AIFS(x) (x) | 1089 | #define _AIFS(x) (x) |
| 1067 | #define _ECW_MAX_MIN(x) ((x) << 8) | 1090 | #define _ECW_MAX_MIN(x) ((x) << 8) |
| 1068 | #define _TXOP_LIMIT(x) ((x) << 16) | 1091 | #define _TXOP_LIMIT(x) ((x) << 16) |
| 1069 | 1092 | ||
| 1070 | #define _BCNIFS(x) ((x) & 0xFF) | 1093 | #define _BCNIFS(x) ((x) & 0xFF) |
| 1071 | #define _BCNECW(x) ((((x) & 0xF)) << 8) | 1094 | #define _BCNECW(x) ((((x) & 0xF)) << 8) |
| 1072 | 1095 | ||
| 1073 | #define _LRL(x) ((x) & 0x3F) | 1096 | #define _LRL(x) ((x) & 0x3F) |
| 1074 | #define _SRL(x) (((x) & 0x3F) << 8) | 1097 | #define _SRL(x) (((x) & 0x3F) << 8) |
| 1075 | 1098 | ||
| 1076 | #define _SIFS_CCK_CTX(x) ((x) & 0xFF) | 1099 | #define _SIFS_CCK_CTX(x) ((x) & 0xFF) |
| 1077 | #define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8); | 1100 | #define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8) |
| 1078 | 1101 | ||
| 1079 | #define _SIFS_OFDM_CTX(x) ((x) & 0xFF) | 1102 | #define _SIFS_OFDM_CTX(x) ((x) & 0xFF) |
| 1080 | #define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8); | 1103 | #define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8) |
| 1081 | 1104 | ||
| 1082 | #define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8) | 1105 | #define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8) |
| 1083 | 1106 | ||
| 1084 | #define DIS_EDCA_CNT_DWN BIT(11) | 1107 | #define DIS_EDCA_CNT_DWN BIT(11) |
| 1085 | 1108 | ||
| 1086 | #define EN_MBSSID BIT(1) | 1109 | #define EN_MBSSID BIT(1) |
| 1087 | #define EN_TXBCN_RPT BIT(2) | 1110 | #define EN_TXBCN_RPT BIT(2) |
| 1088 | #define EN_BCN_FUNCTION BIT(3) | 1111 | #define EN_BCN_FUNCTION BIT(3) |
| 1089 | 1112 | ||
| 1090 | #define TSFTR_RST BIT(0) | 1113 | #define TSFTR_RST BIT(0) |
| 1091 | #define TSFTR1_RST BIT(1) | 1114 | #define TSFTR1_RST BIT(1) |
| 1092 | 1115 | ||
| 1093 | #define STOP_BCNQ BIT(6) | 1116 | #define STOP_BCNQ BIT(6) |
| 1094 | 1117 | ||
| 1095 | #define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) | 1118 | #define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) |
| 1096 | #define DIS_TSF_UDT0_TEST_CHIP BIT(5) | 1119 | #define DIS_TSF_UDT0_TEST_CHIP BIT(5) |
| 1097 | 1120 | ||
| 1098 | #define AcmHw_HwEn BIT(0) | 1121 | #define ACMHW_HWEN BIT(0) |
| 1099 | #define AcmHw_BeqEn BIT(1) | 1122 | #define ACMHW_BEQEN BIT(1) |
| 1100 | #define AcmHw_ViqEn BIT(2) | 1123 | #define ACMHW_VIQEN BIT(2) |
| 1101 | #define AcmHw_VoqEn BIT(3) | 1124 | #define ACMHW_VOQEN BIT(3) |
| 1102 | #define AcmHw_BeqStatus BIT(4) | 1125 | #define ACMHW_BEQSTATUS BIT(4) |
| 1103 | #define AcmHw_ViqStatus BIT(5) | 1126 | #define ACMHW_VIQSTATUS BIT(5) |
| 1104 | #define AcmHw_VoqStatus BIT(6) | 1127 | #define ACMHW_VOQSTATUS BIT(6) |
| 1105 | 1128 | ||
| 1106 | #define APSDOFF BIT(6) | 1129 | #define APSDOFF BIT(6) |
| 1107 | #define APSDOFF_STATUS BIT(7) | 1130 | #define APSDOFF_STATUS BIT(7) |
| 1108 | 1131 | ||
| 1109 | #define BW_20MHZ BIT(2) | 1132 | #define BW_20MHZ BIT(2) |
| 1110 | 1133 | ||
| 1111 | #define RATE_BITMAP_ALL 0xFFFFF | 1134 | #define RATE_BITMAP_ALL 0xFFFFF |
| 1112 | 1135 | ||
| 1113 | #define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 | 1136 | #define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 |
| 1114 | 1137 | ||
| 1115 | #define TSFRST BIT(0) | 1138 | #define TSFRST BIT(0) |
| 1116 | #define DIS_GCLK BIT(1) | 1139 | #define DIS_GCLK BIT(1) |
| 1117 | #define PAD_SEL BIT(2) | 1140 | #define PAD_SEL BIT(2) |
| 1118 | #define PWR_ST BIT(6) | 1141 | #define PWR_ST BIT(6) |
| 1119 | #define PWRBIT_OW_EN BIT(7) | 1142 | #define PWRBIT_OW_EN BIT(7) |
| 1120 | #define ACRC BIT(8) | 1143 | #define ACRC BIT(8) |
| 1121 | #define CFENDFORM BIT(9) | 1144 | #define CFENDFORM BIT(9) |
| 1122 | #define ICV BIT(10) | 1145 | #define ICV BIT(10) |
| 1123 | 1146 | ||
| 1124 | #define AAP BIT(0) | 1147 | #define AAP BIT(0) |
| 1125 | #define APM BIT(1) | 1148 | #define APM BIT(1) |
| 1126 | #define AM BIT(2) | 1149 | #define AM BIT(2) |
| 1127 | #define AB BIT(3) | 1150 | #define AB BIT(3) |
| 1128 | #define ADD3 BIT(4) | 1151 | #define ADD3 BIT(4) |
| 1129 | #define APWRMGT BIT(5) | 1152 | #define APWRMGT BIT(5) |
| 1130 | #define CBSSID BIT(6) | 1153 | #define CBSSID BIT(6) |
| 1131 | #define CBSSID_DATA BIT(6) | 1154 | #define CBSSID_DATA BIT(6) |
| 1132 | #define CBSSID_BCN BIT(7) | 1155 | #define CBSSID_BCN BIT(7) |
| 1133 | #define ACRC32 BIT(8) | 1156 | #define ACRC32 BIT(8) |
| 1134 | #define AICV BIT(9) | 1157 | #define AICV BIT(9) |
| 1135 | #define ADF BIT(11) | 1158 | #define ADF BIT(11) |
| 1136 | #define ACF BIT(12) | 1159 | #define ACF BIT(12) |
| 1137 | #define AMF BIT(13) | 1160 | #define AMF BIT(13) |
| 1138 | #define HTC_LOC_CTRL BIT(14) | 1161 | #define HTC_LOC_CTRL BIT(14) |
| 1139 | #define UC_DATA_EN BIT(16) | 1162 | #define UC_DATA_EN BIT(16) |
| 1140 | #define BM_DATA_EN BIT(17) | 1163 | #define BM_DATA_EN BIT(17) |
| 1141 | #define MFBEN BIT(22) | 1164 | #define MFBEN BIT(22) |
| 1142 | #define LSIGEN BIT(23) | 1165 | #define LSIGEN BIT(23) |
| 1143 | #define EnMBID BIT(24) | 1166 | #define ENMBID BIT(24) |
| 1144 | #define APP_BASSN BIT(27) | 1167 | #define APP_BASSN BIT(27) |
| 1145 | #define APP_PHYSTS BIT(28) | 1168 | #define APP_PHYSTS BIT(28) |
| 1146 | #define APP_ICV BIT(29) | 1169 | #define APP_ICV BIT(29) |
| 1147 | #define APP_MIC BIT(30) | 1170 | #define APP_MIC BIT(30) |
| 1148 | #define APP_FCS BIT(31) | 1171 | #define APP_FCS BIT(31) |
| 1149 | 1172 | ||
| 1150 | #define _MIN_SPACE(x) ((x) & 0x7) | 1173 | #define _MIN_SPACE(x) ((x) & 0x7) |
| 1151 | #define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3) | 1174 | #define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3) |
| 1152 | 1175 | ||
| 1153 | #define RXERR_TYPE_OFDM_PPDU 0 | 1176 | #define RXERR_TYPE_OFDM_PPDU 0 |
| 1154 | #define RXERR_TYPE_OFDM_FALSE_ALARM 1 | 1177 | #define RXERR_TYPE_OFDM_FALSE_ALARM 1 |
| 1155 | #define RXERR_TYPE_OFDM_MPDU_OK 2 | 1178 | #define RXERR_TYPE_OFDM_MPDU_OK 2 |
| 1156 | #define RXERR_TYPE_OFDM_MPDU_FAIL 3 | 1179 | #define RXERR_TYPE_OFDM_MPDU_FAIL 3 |
| 1157 | #define RXERR_TYPE_CCK_PPDU 4 | 1180 | #define RXERR_TYPE_CCK_PPDU 4 |
| 1158 | #define RXERR_TYPE_CCK_FALSE_ALARM 5 | 1181 | #define RXERR_TYPE_CCK_FALSE_ALARM 5 |
| 1159 | #define RXERR_TYPE_CCK_MPDU_OK 6 | 1182 | #define RXERR_TYPE_CCK_MPDU_OK 6 |
| 1160 | #define RXERR_TYPE_CCK_MPDU_FAIL 7 | 1183 | #define RXERR_TYPE_CCK_MPDU_FAIL 7 |
| 1161 | #define RXERR_TYPE_HT_PPDU 8 | 1184 | #define RXERR_TYPE_HT_PPDU 8 |
| 1162 | #define RXERR_TYPE_HT_FALSE_ALARM 9 | 1185 | #define RXERR_TYPE_HT_FALSE_ALARM 9 |
| 1163 | #define RXERR_TYPE_HT_MPDU_TOTAL 10 | 1186 | #define RXERR_TYPE_HT_MPDU_TOTAL 10 |
| 1164 | #define RXERR_TYPE_HT_MPDU_OK 11 | 1187 | #define RXERR_TYPE_HT_MPDU_OK 11 |
| 1165 | #define RXERR_TYPE_HT_MPDU_FAIL 12 | 1188 | #define RXERR_TYPE_HT_MPDU_FAIL 12 |
| 1166 | #define RXERR_TYPE_RX_FULL_DROP 15 | 1189 | #define RXERR_TYPE_RX_FULL_DROP 15 |
| 1167 | 1190 | ||
| 1168 | #define RXERR_COUNTER_MASK 0xFFFFF | 1191 | #define RXERR_COUNTER_MASK 0xFFFFF |
| 1169 | #define RXERR_RPT_RST BIT(27) | 1192 | #define RXERR_RPT_RST BIT(27) |
| 1170 | #define _RXERR_RPT_SEL(type) ((type) << 28) | 1193 | #define _RXERR_RPT_SEL(type) ((type) << 28) |
| 1171 | 1194 | ||
| 1172 | #define SCR_TxUseDK BIT(0) | 1195 | #define SCR_TXUSEDK BIT(0) |
| 1173 | #define SCR_RxUseDK BIT(1) | 1196 | #define SCR_RXUSEDK BIT(1) |
| 1174 | #define SCR_TxEncEnable BIT(2) | 1197 | #define SCR_TXENCENABLE BIT(2) |
| 1175 | #define SCR_RxDecEnable BIT(3) | 1198 | #define SCR_RXDECENABLE BIT(3) |
| 1176 | #define SCR_SKByA2 BIT(4) | 1199 | #define SCR_SKBYA2 BIT(4) |
| 1177 | #define SCR_NoSKMC BIT(5) | 1200 | #define SCR_NOSKMC BIT(5) |
| 1178 | #define SCR_TXBCUSEDK BIT(6) | 1201 | #define SCR_TXBCUSEDK BIT(6) |
| 1179 | #define SCR_RXBCUSEDK BIT(7) | 1202 | #define SCR_RXBCUSEDK BIT(7) |
| 1180 | 1203 | ||
| @@ -1182,32 +1205,32 @@ | |||
| 1182 | #define USB_IS_FULL_SPEED 1 | 1205 | #define USB_IS_FULL_SPEED 1 |
| 1183 | #define USB_SPEED_MASK BIT(5) | 1206 | #define USB_SPEED_MASK BIT(5) |
| 1184 | 1207 | ||
| 1185 | #define USB_NORMAL_SIE_EP_MASK 0xF | 1208 | #define USB_NORMAL_SIE_EP_MASK 0xF |
| 1186 | #define USB_NORMAL_SIE_EP_SHIFT 4 | 1209 | #define USB_NORMAL_SIE_EP_SHIFT 4 |
| 1187 | 1210 | ||
| 1188 | #define USB_TEST_EP_MASK 0x30 | 1211 | #define USB_TEST_EP_MASK 0x30 |
| 1189 | #define USB_TEST_EP_SHIFT 4 | 1212 | #define USB_TEST_EP_SHIFT 4 |
| 1190 | 1213 | ||
| 1191 | #define USB_AGG_EN BIT(3) | 1214 | #define USB_AGG_EN BIT(3) |
| 1192 | 1215 | ||
| 1193 | #define MAC_ADDR_LEN 6 | 1216 | #define MAC_ADDR_LEN 6 |
| 1194 | #define LAST_ENTRY_OF_TX_PKT_BUFFER 255 | 1217 | #define LAST_ENTRY_OF_TX_PKT_BUFFER 255 |
| 1195 | 1218 | ||
| 1196 | #define POLLING_LLT_THRESHOLD 20 | 1219 | #define POLLING_LLT_THRESHOLD 20 |
| 1197 | #define POLLING_READY_TIMEOUT_COUNT 1000 | 1220 | #define POLLING_READY_TIMEOUT_COUNT 1000 |
| 1198 | 1221 | ||
| 1199 | #define MAX_MSS_DENSITY_2T 0x13 | 1222 | #define MAX_MSS_DENSITY_2T 0x13 |
| 1200 | #define MAX_MSS_DENSITY_1T 0x0A | 1223 | #define MAX_MSS_DENSITY_1T 0x0A |
| 1201 | 1224 | ||
| 1202 | #define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6)) | 1225 | #define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6)) |
| 1203 | #define EPROM_CMD_CONFIG 0x3 | 1226 | #define EPROM_CMD_CONFIG 0x3 |
| 1204 | #define EPROM_CMD_LOAD 1 | 1227 | #define EPROM_CMD_LOAD 1 |
| 1205 | 1228 | ||
| 1206 | #define HWSET_MAX_SIZE_92S HWSET_MAX_SIZE | 1229 | #define HWSET_MAX_SIZE_92S HWSET_MAX_SIZE |
| 1207 | 1230 | ||
| 1208 | #define HAL_8192C_HW_GPIO_WPS_BIT BIT(2) | 1231 | #define HAL_8192C_HW_GPIO_WPS_BIT BIT(2) |
| 1209 | 1232 | ||
| 1210 | #define RPMAC_RESET 0x100 | 1233 | #define RPMAC_RESET 0x100 |
| 1211 | #define RPMAC_TXSTART 0x104 | 1234 | #define RPMAC_TXSTART 0x104 |
| 1212 | #define RPMAC_TXLEGACYSIG 0x108 | 1235 | #define RPMAC_TXLEGACYSIG 0x108 |
| 1213 | #define RPMAC_TXHTSIG1 0x10c | 1236 | #define RPMAC_TXHTSIG1 0x10c |
| @@ -1223,12 +1246,12 @@ | |||
| 1223 | #define RPMAC_TXMACHEADER5 0x134 | 1246 | #define RPMAC_TXMACHEADER5 0x134 |
| 1224 | #define RPMAC_TXDADATYPE 0x138 | 1247 | #define RPMAC_TXDADATYPE 0x138 |
| 1225 | #define RPMAC_TXRANDOMSEED 0x13c | 1248 | #define RPMAC_TXRANDOMSEED 0x13c |
| 1226 | #define RPMAC_CCKPLCPPREAMBLE 0x140 | 1249 | #define RPMAC_CCKPLCPPREAMBLE 0x140 |
| 1227 | #define RPMAC_CCKPLCPHEADER 0x144 | 1250 | #define RPMAC_CCKPLCPHEADER 0x144 |
| 1228 | #define RPMAC_CCKCRC16 0x148 | 1251 | #define RPMAC_CCKCRC16 0x148 |
| 1229 | #define RPMAC_OFDMRXCRC32OK 0x170 | 1252 | #define RPMAC_OFDMRXCRC32OK 0x170 |
| 1230 | #define RPMAC_OFDMRXCRC32Er 0x174 | 1253 | #define RPMAC_OFDMRXCRC32ER 0x174 |
| 1231 | #define RPMAC_OFDMRXPARITYER 0x178 | 1254 | #define RPMAC_OFDMRXPARITYER 0x178 |
| 1232 | #define RPMAC_OFDMRXCRC8ER 0x17c | 1255 | #define RPMAC_OFDMRXCRC8ER 0x17c |
| 1233 | #define RPMAC_CCKCRXRC16ER 0x180 | 1256 | #define RPMAC_CCKCRXRC16ER 0x180 |
| 1234 | #define RPMAC_CCKCRXRC32ER 0x184 | 1257 | #define RPMAC_CCKCRXRC32ER 0x184 |
| @@ -1245,44 +1268,44 @@ | |||
| 1245 | #define RFPGA0_RFTIMING1 0x810 | 1268 | #define RFPGA0_RFTIMING1 0x810 |
| 1246 | #define RFPGA0_RFTIMING2 0x814 | 1269 | #define RFPGA0_RFTIMING2 0x814 |
| 1247 | 1270 | ||
| 1248 | #define RFPGA0_XA_HSSIPARAMETER1 0x820 | 1271 | #define RFPGA0_XA_HSSIPARAMETER1 0x820 |
| 1249 | #define RFPGA0_XA_HSSIPARAMETER2 0x824 | 1272 | #define RFPGA0_XA_HSSIPARAMETER2 0x824 |
| 1250 | #define RFPGA0_XB_HSSIPARAMETER1 0x828 | 1273 | #define RFPGA0_XB_HSSIPARAMETER1 0x828 |
| 1251 | #define RFPGA0_XB_HSSIPARAMETER2 0x82c | 1274 | #define RFPGA0_XB_HSSIPARAMETER2 0x82c |
| 1252 | 1275 | ||
| 1253 | #define RFPGA0_XA_LSSIPARAMETER 0x840 | 1276 | #define RFPGA0_XA_LSSIPARAMETER 0x840 |
| 1254 | #define RFPGA0_XB_LSSIPARAMETER 0x844 | 1277 | #define RFPGA0_XB_LSSIPARAMETER 0x844 |
| 1255 | 1278 | ||
| 1256 | #define RFPGA0_RFWAKEUPPARAMETER 0x850 | 1279 | #define RFPGA0_RFWAKEUPPARAMETER 0x850 |
| 1257 | #define RFPGA0_RFSLEEPUPPARAMETER 0x854 | 1280 | #define RFPGA0_RFSLEEPUPPARAMETER 0x854 |
| 1258 | 1281 | ||
| 1259 | #define RFPGA0_XAB_SWITCHCONTROL 0x858 | 1282 | #define RFPGA0_XAB_SWITCHCONTROL 0x858 |
| 1260 | #define RFPGA0_XCD_SWITCHCONTROL 0x85c | 1283 | #define RFPGA0_XCD_SWITCHCONTROL 0x85c |
| 1261 | 1284 | ||
| 1262 | #define RFPGA0_XA_RFINTERFACEOE 0x860 | 1285 | #define RFPGA0_XA_RFINTERFACEOE 0x860 |
| 1263 | #define RFPGA0_XB_RFINTERFACEOE 0x864 | 1286 | #define RFPGA0_XB_RFINTERFACEOE 0x864 |
| 1264 | 1287 | ||
| 1265 | #define RFPGA0_XAB_RFINTERFACESW 0x870 | 1288 | #define RFPGA0_XAB_RFINTERFACESW 0x870 |
| 1266 | #define RFPGA0_XCD_RFINTERFACESW 0x874 | 1289 | #define RFPGA0_XCD_RFINTERFACESW 0x874 |
| 1267 | 1290 | ||
| 1268 | #define rFPGA0_XAB_RFPARAMETER 0x878 | 1291 | #define RFPGA0_XAB_RFPARAMETER 0x878 |
| 1269 | #define rFPGA0_XCD_RFPARAMETER 0x87c | 1292 | #define RFPGA0_XCD_RFPARAMETER 0x87c |
| 1270 | 1293 | ||
| 1271 | #define RFPGA0_ANALOGPARAMETER1 0x880 | 1294 | #define RFPGA0_ANALOGPARAMETER1 0x880 |
| 1272 | #define RFPGA0_ANALOGPARAMETER2 0x884 | 1295 | #define RFPGA0_ANALOGPARAMETER2 0x884 |
| 1273 | #define RFPGA0_ANALOGPARAMETER3 0x888 | 1296 | #define RFPGA0_ANALOGPARAMETER3 0x888 |
| 1274 | #define RFPGA0_ANALOGPARAMETER4 0x88c | 1297 | #define RFPGA0_ANALOGPARAMETER4 0x88c |
| 1275 | 1298 | ||
| 1276 | #define RFPGA0_XA_LSSIREADBACK 0x8a0 | 1299 | #define RFPGA0_XA_LSSIREADBACK 0x8a0 |
| 1277 | #define RFPGA0_XB_LSSIREADBACK 0x8a4 | 1300 | #define RFPGA0_XB_LSSIREADBACK 0x8a4 |
| 1278 | #define RFPGA0_XC_LSSIREADBACK 0x8a8 | 1301 | #define RFPGA0_XC_LSSIREADBACK 0x8a8 |
| 1279 | #define RFPGA0_XD_LSSIREADBACK 0x8ac | 1302 | #define RFPGA0_XD_LSSIREADBACK 0x8ac |
| 1280 | 1303 | ||
| 1281 | #define RFPGA0_PSDREPORT 0x8b4 | 1304 | #define RFPGA0_PSDREPORT 0x8b4 |
| 1282 | #define TRANSCEIVEA_HSPI_READBACK 0x8b8 | 1305 | #define TRANSCEIVEA_HSPI_READBACK 0x8b8 |
| 1283 | #define TRANSCEIVEB_HSPI_READBACK 0x8bc | 1306 | #define TRANSCEIVEB_HSPI_READBACK 0x8bc |
| 1284 | #define RFPGA0_XAB_RFINTERFACERB 0x8e0 | 1307 | #define RFPGA0_XAB_RFINTERFACERB 0x8e0 |
| 1285 | #define RFPGA0_XCD_RFINTERFACERB 0x8e4 | 1308 | #define RFPGA0_XCD_RFINTERFACERB 0x8e4 |
| 1286 | 1309 | ||
| 1287 | #define RFPGA1_RFMOD 0x900 | 1310 | #define RFPGA1_RFMOD 0x900 |
| 1288 | 1311 | ||
| @@ -1293,12 +1316,12 @@ | |||
| 1293 | #define RCCK0_SYSTEM 0xa00 | 1316 | #define RCCK0_SYSTEM 0xa00 |
| 1294 | 1317 | ||
| 1295 | #define RCCK0_AFESETTING 0xa04 | 1318 | #define RCCK0_AFESETTING 0xa04 |
| 1296 | #define RCCK0_CCA 0xa08 | 1319 | #define RCCK0_CCA 0xa08 |
| 1297 | 1320 | ||
| 1298 | #define RCCK0_RXAGC1 0xa0c | 1321 | #define RCCK0_RXAGC1 0xa0c |
| 1299 | #define RCCK0_RXAGC2 0xa10 | 1322 | #define RCCK0_RXAGC2 0xa10 |
| 1300 | 1323 | ||
| 1301 | #define RCCK0_RXHP 0xa14 | 1324 | #define RCCK0_RXHP 0xa14 |
| 1302 | 1325 | ||
| 1303 | #define RCCK0_DSPPARAMETER1 0xa18 | 1326 | #define RCCK0_DSPPARAMETER1 0xa18 |
| 1304 | #define RCCK0_DSPPARAMETER2 0xa1c | 1327 | #define RCCK0_DSPPARAMETER2 0xa1c |
| @@ -1306,26 +1329,26 @@ | |||
| 1306 | #define RCCK0_TXFILTER1 0xa20 | 1329 | #define RCCK0_TXFILTER1 0xa20 |
| 1307 | #define RCCK0_TXFILTER2 0xa24 | 1330 | #define RCCK0_TXFILTER2 0xa24 |
| 1308 | #define RCCK0_DEBUGPORT 0xa28 | 1331 | #define RCCK0_DEBUGPORT 0xa28 |
| 1309 | #define RCCK0_FALSEALARMREPORT 0xa2c | 1332 | #define RCCK0_FALSEALARMREPORT 0xa2c |
| 1310 | #define RCCK0_TRSSIREPORT 0xa50 | 1333 | #define RCCK0_TRSSIREPORT 0xa50 |
| 1311 | #define RCCK0_RXREPORT 0xa54 | 1334 | #define RCCK0_RXREPORT 0xa54 |
| 1312 | #define RCCK0_FACOUNTERLOWER 0xa5c | 1335 | #define RCCK0_FACOUNTERLOWER 0xa5c |
| 1313 | #define RCCK0_FACOUNTERUPPER 0xa58 | 1336 | #define RCCK0_FACOUNTERUPPER 0xa58 |
| 1314 | 1337 | ||
| 1315 | #define ROFDM0_LSTF 0xc00 | 1338 | #define ROFDM0_LSTF 0xc00 |
| 1316 | 1339 | ||
| 1317 | #define ROFDM0_TRXPATHENABLE 0xc04 | 1340 | #define ROFDM0_TRXPATHENABLE 0xc04 |
| 1318 | #define ROFDM0_TRMUXPAR 0xc08 | 1341 | #define ROFDM0_TRMUXPAR 0xc08 |
| 1319 | #define ROFDM0_TRSWISOLATION 0xc0c | 1342 | #define ROFDM0_TRSWISOLATION 0xc0c |
| 1320 | 1343 | ||
| 1321 | #define ROFDM0_XARXAFE 0xc10 | 1344 | #define ROFDM0_XARXAFE 0xc10 |
| 1322 | #define ROFDM0_XARXIQIMBALANCE 0xc14 | 1345 | #define ROFDM0_XARXIQIMBALANCE 0xc14 |
| 1323 | #define ROFDM0_XBRXAFE 0xc18 | 1346 | #define ROFDM0_XBRXAFE 0xc18 |
| 1324 | #define ROFDM0_XBRXIQIMBALANCE 0xc1c | 1347 | #define ROFDM0_XBRXIQIMBALANCE 0xc1c |
| 1325 | #define ROFDM0_XCRXAFE 0xc20 | 1348 | #define ROFDM0_XCRXAFE 0xc20 |
| 1326 | #define ROFDM0_XCRXIQIMBANLANCE 0xc24 | 1349 | #define ROFDM0_XCRXIQIMBANLANCE 0xc24 |
| 1327 | #define ROFDM0_XDRXAFE 0xc28 | 1350 | #define ROFDM0_XDRXAFE 0xc28 |
| 1328 | #define ROFDM0_XDRXIQIMBALANCE 0xc2c | 1351 | #define ROFDM0_XDRXIQIMBALANCE 0xc2c |
| 1329 | 1352 | ||
| 1330 | #define ROFDM0_RXDETECTOR1 0xc30 | 1353 | #define ROFDM0_RXDETECTOR1 0xc30 |
| 1331 | #define ROFDM0_RXDETECTOR2 0xc34 | 1354 | #define ROFDM0_RXDETECTOR2 0xc34 |
| @@ -1334,8 +1357,8 @@ | |||
| 1334 | 1357 | ||
| 1335 | #define ROFDM0_RXDSP 0xc40 | 1358 | #define ROFDM0_RXDSP 0xc40 |
| 1336 | #define ROFDM0_CFOANDDAGC 0xc44 | 1359 | #define ROFDM0_CFOANDDAGC 0xc44 |
| 1337 | #define ROFDM0_CCADROPTHRESHOLD 0xc48 | 1360 | #define ROFDM0_CCADROPTHRESHOLD 0xc48 |
| 1338 | #define ROFDM0_ECCATHRESHOLD 0xc4c | 1361 | #define ROFDM0_ECCATHRESHOLD 0xc4c |
| 1339 | 1362 | ||
| 1340 | #define ROFDM0_XAAGCCORE1 0xc50 | 1363 | #define ROFDM0_XAAGCCORE1 0xc50 |
| 1341 | #define ROFDM0_XAAGCCORE2 0xc54 | 1364 | #define ROFDM0_XAAGCCORE2 0xc54 |
| @@ -1346,24 +1369,24 @@ | |||
| 1346 | #define ROFDM0_XDAGCCORE1 0xc68 | 1369 | #define ROFDM0_XDAGCCORE1 0xc68 |
| 1347 | #define ROFDM0_XDAGCCORE2 0xc6c | 1370 | #define ROFDM0_XDAGCCORE2 0xc6c |
| 1348 | 1371 | ||
| 1349 | #define ROFDM0_AGCPARAMETER1 0xc70 | 1372 | #define ROFDM0_AGCPARAMETER1 0xc70 |
| 1350 | #define ROFDM0_AGCPARAMETER2 0xc74 | 1373 | #define ROFDM0_AGCPARAMETER2 0xc74 |
| 1351 | #define ROFDM0_AGCRSSITABLE 0xc78 | 1374 | #define ROFDM0_AGCRSSITABLE 0xc78 |
| 1352 | #define ROFDM0_HTSTFAGC 0xc7c | 1375 | #define ROFDM0_HTSTFAGC 0xc7c |
| 1353 | 1376 | ||
| 1354 | #define ROFDM0_XATXIQIMBALANCE 0xc80 | 1377 | #define ROFDM0_XATXIQIMBALANCE 0xc80 |
| 1355 | #define ROFDM0_XATXAFE 0xc84 | 1378 | #define ROFDM0_XATXAFE 0xc84 |
| 1356 | #define ROFDM0_XBTXIQIMBALANCE 0xc88 | 1379 | #define ROFDM0_XBTXIQIMBALANCE 0xc88 |
| 1357 | #define ROFDM0_XBTXAFE 0xc8c | 1380 | #define ROFDM0_XBTXAFE 0xc8c |
| 1358 | #define ROFDM0_XCTXIQIMBALANCE 0xc90 | 1381 | #define ROFDM0_XCTXIQIMBALANCE 0xc90 |
| 1359 | #define ROFDM0_XCTXAFE 0xc94 | 1382 | #define ROFDM0_XCTXAFE 0xc94 |
| 1360 | #define ROFDM0_XDTXIQIMBALANCE 0xc98 | 1383 | #define ROFDM0_XDTXIQIMBALANCE 0xc98 |
| 1361 | #define ROFDM0_XDTXAFE 0xc9c | 1384 | #define ROFDM0_XDTXAFE 0xc9c |
| 1362 | 1385 | ||
| 1363 | #define ROFDM0_RXIQEXTANTA 0xca0 | 1386 | #define ROFDM0_RXIQEXTANTA 0xca0 |
| 1364 | 1387 | ||
| 1365 | #define ROFDM0_RXHPPARAMETER 0xce0 | 1388 | #define ROFDM0_RXHPPARAMETER 0xce0 |
| 1366 | #define ROFDM0_TXPSEUDONOISEWGT 0xce4 | 1389 | #define ROFDM0_TXPSEUDONOISEWGT 0xce4 |
| 1367 | #define ROFDM0_FRAMESYNC 0xcf0 | 1390 | #define ROFDM0_FRAMESYNC 0xcf0 |
| 1368 | #define ROFDM0_DFSREPORT 0xcf4 | 1391 | #define ROFDM0_DFSREPORT 0xcf4 |
| 1369 | #define ROFDM0_TXCOEFF1 0xca4 | 1392 | #define ROFDM0_TXCOEFF1 0xca4 |
| @@ -1373,19 +1396,19 @@ | |||
| 1373 | #define ROFDM0_TXCOEFF5 0xcb4 | 1396 | #define ROFDM0_TXCOEFF5 0xcb4 |
| 1374 | #define ROFDM0_TXCOEFF6 0xcb8 | 1397 | #define ROFDM0_TXCOEFF6 0xcb8 |
| 1375 | 1398 | ||
| 1376 | #define ROFDM1_LSTF 0xd00 | 1399 | #define ROFDM1_LSTF 0xd00 |
| 1377 | #define ROFDM1_TRXPATHENABLE 0xd04 | 1400 | #define ROFDM1_TRXPATHENABLE 0xd04 |
| 1378 | 1401 | ||
| 1379 | #define ROFDM1_CF0 0xd08 | 1402 | #define ROFDM1_CF0 0xd08 |
| 1380 | #define ROFDM1_CSI1 0xd10 | 1403 | #define ROFDM1_CSI1 0xd10 |
| 1381 | #define ROFDM1_SBD 0xd14 | 1404 | #define ROFDM1_SBD 0xd14 |
| 1382 | #define ROFDM1_CSI2 0xd18 | 1405 | #define ROFDM1_CSI2 0xd18 |
| 1383 | #define ROFDM1_CFOTRACKING 0xd2c | 1406 | #define ROFDM1_CFOTRACKING 0xd2c |
| 1384 | #define ROFDM1_TRXMESAURE1 0xd34 | 1407 | #define ROFDM1_TRXMESAURE1 0xd34 |
| 1385 | #define ROFDM1_INTFDET 0xd3c | 1408 | #define ROFDM1_INTFDET 0xd3c |
| 1386 | #define ROFDM1_PSEUDONOISESTATEAB 0xd50 | 1409 | #define ROFDM1_PSEUDONOISESTATEAB 0xd50 |
| 1387 | #define ROFDM1_PSEUDONOISESTATECD 0xd54 | 1410 | #define ROFDM1_PSEUDONOISESTATECD 0xd54 |
| 1388 | #define ROFDM1_RXPSEUDONOISEWGT 0xd58 | 1411 | #define ROFDM1_RXPSEUDONOISEWGT 0xd58 |
| 1389 | 1412 | ||
| 1390 | #define ROFDM_PHYCOUNTER1 0xda0 | 1413 | #define ROFDM_PHYCOUNTER1 0xda0 |
| 1391 | #define ROFDM_PHYCOUNTER2 0xda4 | 1414 | #define ROFDM_PHYCOUNTER2 0xda4 |
| @@ -1397,35 +1420,35 @@ | |||
| 1397 | #define ROFDM_LONGCFOCD 0xdb8 | 1420 | #define ROFDM_LONGCFOCD 0xdb8 |
| 1398 | #define ROFDM_TAILCF0AB 0xdbc | 1421 | #define ROFDM_TAILCF0AB 0xdbc |
| 1399 | #define ROFDM_TAILCF0CD 0xdc0 | 1422 | #define ROFDM_TAILCF0CD 0xdc0 |
| 1400 | #define ROFDM_PWMEASURE1 0xdc4 | 1423 | #define ROFDM_PWMEASURE1 0xdc4 |
| 1401 | #define ROFDM_PWMEASURE2 0xdc8 | 1424 | #define ROFDM_PWMEASURE2 0xdc8 |
| 1402 | #define ROFDM_BWREPORT 0xdcc | 1425 | #define ROFDM_BWREPORT 0xdcc |
| 1403 | #define ROFDM_AGCREPORT 0xdd0 | 1426 | #define ROFDM_AGCREPORT 0xdd0 |
| 1404 | #define ROFDM_RXSNR 0xdd4 | 1427 | #define ROFDM_RXSNR 0xdd4 |
| 1405 | #define ROFDM_RXEVMCSI 0xdd8 | 1428 | #define ROFDM_RXEVMCSI 0xdd8 |
| 1406 | #define ROFDM_SIGREPORT 0xddc | 1429 | #define ROFDM_SIGREPORT 0xddc |
| 1407 | 1430 | ||
| 1408 | #define RTXAGC_A_RATE18_06 0xe00 | 1431 | #define RTXAGC_A_RATE18_06 0xe00 |
| 1409 | #define RTXAGC_A_RATE54_24 0xe04 | 1432 | #define RTXAGC_A_RATE54_24 0xe04 |
| 1410 | #define RTXAGC_A_CCK1_MCS32 0xe08 | 1433 | #define RTXAGC_A_CCK1_MCS32 0xe08 |
| 1411 | #define RTXAGC_A_MCS03_MCS00 0xe10 | 1434 | #define RTXAGC_A_MCS03_MCS00 0xe10 |
| 1412 | #define RTXAGC_A_MCS07_MCS04 0xe14 | 1435 | #define RTXAGC_A_MCS07_MCS04 0xe14 |
| 1413 | #define RTXAGC_A_MCS11_MCS08 0xe18 | 1436 | #define RTXAGC_A_MCS11_MCS08 0xe18 |
| 1414 | #define RTXAGC_A_MCS15_MCS12 0xe1c | 1437 | #define RTXAGC_A_MCS15_MCS12 0xe1c |
| 1415 | 1438 | ||
| 1416 | #define RTXAGC_B_RATE18_06 0x830 | 1439 | #define RTXAGC_B_RATE18_06 0x830 |
| 1417 | #define RTXAGC_B_RATE54_24 0x834 | 1440 | #define RTXAGC_B_RATE54_24 0x834 |
| 1418 | #define RTXAGC_B_CCK1_55_MCS32 0x838 | 1441 | #define RTXAGC_B_CCK1_55_MCS32 0x838 |
| 1419 | #define RTXAGC_B_MCS03_MCS00 0x83c | 1442 | #define RTXAGC_B_MCS03_MCS00 0x83c |
| 1420 | #define RTXAGC_B_MCS07_MCS04 0x848 | 1443 | #define RTXAGC_B_MCS07_MCS04 0x848 |
| 1421 | #define RTXAGC_B_MCS11_MCS08 0x84c | 1444 | #define RTXAGC_B_MCS11_MCS08 0x84c |
| 1422 | #define RTXAGC_B_MCS15_MCS12 0x868 | 1445 | #define RTXAGC_B_MCS15_MCS12 0x868 |
| 1423 | #define RTXAGC_B_CCK11_A_CCK2_11 0x86c | 1446 | #define RTXAGC_B_CCK11_A_CCK2_11 0x86c |
| 1424 | 1447 | ||
| 1425 | #define RZEBRA1_HSSIENABLE 0x0 | 1448 | #define RZEBRA1_HSSIENABLE 0x0 |
| 1426 | #define RZEBRA1_TRXENABLE1 0x1 | 1449 | #define RZEBRA1_TRXENABLE1 0x1 |
| 1427 | #define RZEBRA1_TRXENABLE2 0x2 | 1450 | #define RZEBRA1_TRXENABLE2 0x2 |
| 1428 | #define RZEBRA1_AGC 0x4 | 1451 | #define RZEBRA1_AGC 0x4 |
| 1429 | #define RZEBRA1_CHARGEPUMP 0x5 | 1452 | #define RZEBRA1_CHARGEPUMP 0x5 |
| 1430 | #define RZEBRA1_CHANNEL 0x7 | 1453 | #define RZEBRA1_CHANNEL 0x7 |
| 1431 | 1454 | ||
| @@ -1434,649 +1457,664 @@ | |||
| 1434 | #define RZEBRA1_RXLPF 0xb | 1457 | #define RZEBRA1_RXLPF 0xb |
| 1435 | #define RZEBRA1_RXHPFCORNER 0xc | 1458 | #define RZEBRA1_RXHPFCORNER 0xc |
| 1436 | 1459 | ||
| 1437 | #define RGLOBALCTRL 0 | 1460 | #define RGLOBALCTRL 0 |
| 1438 | #define RRTL8256_TXLPF 19 | 1461 | #define RRTL8256_TXLPF 19 |
| 1439 | #define RRTL8256_RXLPF 11 | 1462 | #define RRTL8256_RXLPF 11 |
| 1440 | #define RRTL8258_TXLPF 0x11 | 1463 | #define RRTL8258_TXLPF 0x11 |
| 1441 | #define RRTL8258_RXLPF 0x13 | 1464 | #define RRTL8258_RXLPF 0x13 |
| 1442 | #define RRTL8258_RSSILPF 0xa | 1465 | #define RRTL8258_RSSILPF 0xa |
| 1443 | 1466 | ||
| 1444 | #define RF_AC 0x00 | 1467 | #define RF_AC 0x00 |
| 1445 | 1468 | ||
| 1446 | #define RF_IQADJ_G1 0x01 | 1469 | #define RF_IQADJ_G1 0x01 |
| 1447 | #define RF_IQADJ_G2 0x02 | 1470 | #define RF_IQADJ_G2 0x02 |
| 1448 | #define RF_POW_TRSW 0x05 | 1471 | #define RF_POW_TRSW 0x05 |
| 1449 | 1472 | ||
| 1450 | #define RF_GAIN_RX 0x06 | 1473 | #define RF_GAIN_RX 0x06 |
| 1451 | #define RF_GAIN_TX 0x07 | 1474 | #define RF_GAIN_TX 0x07 |
| 1452 | 1475 | ||
| 1453 | #define RF_TXM_IDAC 0x08 | 1476 | #define RF_TXM_IDAC 0x08 |
| 1454 | #define RF_BS_IQGEN 0x0F | 1477 | #define RF_BS_IQGEN 0x0F |
| 1455 | 1478 | ||
| 1456 | #define RF_MODE1 0x10 | 1479 | #define RF_MODE1 0x10 |
| 1457 | #define RF_MODE2 0x11 | 1480 | #define RF_MODE2 0x11 |
| 1458 | 1481 | ||
| 1459 | #define RF_RX_AGC_HP 0x12 | 1482 | #define RF_RX_AGC_HP 0x12 |
| 1460 | #define RF_TX_AGC 0x13 | 1483 | #define RF_TX_AGC 0x13 |
| 1461 | #define RF_BIAS 0x14 | 1484 | #define RF_BIAS 0x14 |
| 1462 | #define RF_IPA 0x15 | 1485 | #define RF_IPA 0x15 |
| 1463 | #define RF_POW_ABILITY 0x17 | 1486 | #define RF_POW_ABILITY 0x17 |
| 1464 | #define RF_MODE_AG 0x18 | 1487 | #define RF_MODE_AG 0x18 |
| 1465 | #define RRFCHANNEL 0x18 | 1488 | #define RRFCHANNEL 0x18 |
| 1466 | #define RF_CHNLBW 0x18 | 1489 | #define RF_CHNLBW 0x18 |
| 1467 | #define RF_TOP 0x19 | 1490 | #define RF_TOP 0x19 |
| 1468 | 1491 | ||
| 1469 | #define RF_RX_G1 0x1A | 1492 | #define RF_RX_G1 0x1A |
| 1470 | #define RF_RX_G2 0x1B | 1493 | #define RF_RX_G2 0x1B |
| 1471 | 1494 | ||
| 1472 | #define RF_RX_BB2 0x1C | 1495 | #define RF_RX_BB2 0x1C |
| 1473 | #define RF_RX_BB1 0x1D | 1496 | #define RF_RX_BB1 0x1D |
| 1474 | 1497 | ||
| 1475 | #define RF_RCK1 0x1E | 1498 | #define RF_RCK1 0x1E |
| 1476 | #define RF_RCK2 0x1F | 1499 | #define RF_RCK2 0x1F |
| 1477 | 1500 | ||
| 1478 | #define RF_TX_G1 0x20 | 1501 | #define RF_TX_G1 0x20 |
| 1479 | #define RF_TX_G2 0x21 | 1502 | #define RF_TX_G2 0x21 |
| 1480 | #define RF_TX_G3 0x22 | 1503 | #define RF_TX_G3 0x22 |
| 1481 | 1504 | ||
| 1482 | #define RF_TX_BB1 0x23 | 1505 | #define RF_TX_BB1 0x23 |
| 1483 | #define RF_T_METER 0x24 | 1506 | #define RF_T_METER 0x24 |
| 1484 | 1507 | ||
| 1485 | #define RF_SYN_G1 0x25 | 1508 | #define RF_SYN_G1 0x25 |
| 1486 | #define RF_SYN_G2 0x26 | 1509 | #define RF_SYN_G2 0x26 |
| 1487 | #define RF_SYN_G3 0x27 | 1510 | #define RF_SYN_G3 0x27 |
| 1488 | #define RF_SYN_G4 0x28 | 1511 | #define RF_SYN_G4 0x28 |
| 1489 | #define RF_SYN_G5 0x29 | 1512 | #define RF_SYN_G5 0x29 |
| 1490 | #define RF_SYN_G6 0x2A | 1513 | #define RF_SYN_G6 0x2A |
| 1491 | #define RF_SYN_G7 0x2B | 1514 | #define RF_SYN_G7 0x2B |
| 1492 | #define RF_SYN_G8 0x2C | 1515 | #define RF_SYN_G8 0x2C |
| 1493 | 1516 | ||
| 1494 | #define RF_RCK_OS 0x30 | 1517 | #define RF_RCK_OS 0x30 |
| 1495 | #define RF_TXPA_G1 0x31 | 1518 | #define RF_TXPA_G1 0x31 |
| 1496 | #define RF_TXPA_G2 0x32 | 1519 | #define RF_TXPA_G2 0x32 |
| 1497 | #define RF_TXPA_G3 0x33 | 1520 | #define RF_TXPA_G3 0x33 |
| 1498 | 1521 | ||
| 1499 | #define BBBRESETB 0x100 | 1522 | #define BBBRESETB 0x100 |
| 1500 | #define BGLOBALRESETB 0x200 | 1523 | #define BGLOBALRESETB 0x200 |
| 1501 | #define BOFDMTXSTART 0x4 | 1524 | #define BOFDMTXSTART 0x4 |
| 1502 | #define BCCKTXSTART 0x8 | 1525 | #define BCCKTXSTART 0x8 |
| 1503 | #define BCRC32DEBUG 0x100 | 1526 | #define BCRC32DEBUG 0x100 |
| 1504 | #define BPMACLOOPBACK 0x10 | 1527 | #define BPMACLOOPBACK 0x10 |
| 1505 | #define BTXLSIG 0xffffff | 1528 | #define BTXLSIG 0xffffff |
| 1506 | #define BOFDMTXRATE 0xf | 1529 | #define BOFDMTXRATE 0xf |
| 1507 | #define BOFDMTXRESERVED 0x10 | 1530 | #define BOFDMTXRESERVED 0x10 |
| 1508 | #define BOFDMTXLENGTH 0x1ffe0 | 1531 | #define BOFDMTXLENGTH 0x1ffe0 |
| 1509 | #define BOFDMTXPARITY 0x20000 | 1532 | #define BOFDMTXPARITY 0x20000 |
| 1510 | #define BTXHTSIG1 0xffffff | 1533 | #define BTXHTSIG1 0xffffff |
| 1511 | #define BTXHTMCSRATE 0x7f | 1534 | #define BTXHTMCSRATE 0x7f |
| 1512 | #define BTXHTBW 0x80 | 1535 | #define BTXHTBW 0x80 |
| 1513 | #define BTXHTLENGTH 0xffff00 | 1536 | #define BTXHTLENGTH 0xffff00 |
| 1514 | #define BTXHTSIG2 0xffffff | 1537 | #define BTXHTSIG2 0xffffff |
| 1515 | #define BTXHTSMOOTHING 0x1 | 1538 | #define BTXHTSMOOTHING 0x1 |
| 1516 | #define BTXHTSOUNDING 0x2 | 1539 | #define BTXHTSOUNDING 0x2 |
| 1517 | #define BTXHTRESERVED 0x4 | 1540 | #define BTXHTRESERVED 0x4 |
| 1518 | #define BTXHTAGGREATION 0x8 | 1541 | #define BTXHTAGGREATION 0x8 |
| 1519 | #define BTXHTSTBC 0x30 | 1542 | #define BTXHTSTBC 0x30 |
| 1520 | #define BTXHTADVANCECODING 0x40 | 1543 | #define BTXHTADVANCECODING 0x40 |
| 1521 | #define BTXHTSHORTGI 0x80 | 1544 | #define BTXHTSHORTGI 0x80 |
| 1522 | #define BTXHTNUMBERHT_LTF 0x300 | 1545 | #define BTXHTNUMBERHT_LTF 0x300 |
| 1523 | #define BTXHTCRC8 0x3fc00 | 1546 | #define BTXHTCRC8 0x3fc00 |
| 1524 | #define BCOUNTERRESET 0x10000 | 1547 | #define BCOUNTERRESET 0x10000 |
| 1525 | #define BNUMOFOFDMTX 0xffff | 1548 | #define BNUMOFOFDMTX 0xffff |
| 1526 | #define BNUMOFCCKTX 0xffff0000 | 1549 | #define BNUMOFCCKTX 0xffff0000 |
| 1527 | #define BTXIDLEINTERVAL 0xffff | 1550 | #define BTXIDLEINTERVAL 0xffff |
| 1528 | #define BOFDMSERVICE 0xffff0000 | 1551 | #define BOFDMSERVICE 0xffff0000 |
| 1529 | #define BTXMACHEADER 0xffffffff | 1552 | #define BTXMACHEADER 0xffffffff |
| 1530 | #define BTXDATAINIT 0xff | 1553 | #define BTXDATAINIT 0xff |
| 1531 | #define BTXHTMODE 0x100 | 1554 | #define BTXHTMODE 0x100 |
| 1532 | #define BTXDATATYPE 0x30000 | 1555 | #define BTXDATATYPE 0x30000 |
| 1533 | #define BTXRANDOMSEED 0xffffffff | 1556 | #define BTXRANDOMSEED 0xffffffff |
| 1534 | #define BCCKTXPREAMBLE 0x1 | 1557 | #define BCCKTXPREAMBLE 0x1 |
| 1535 | #define BCCKTXSFD 0xffff0000 | 1558 | #define BCCKTXSFD 0xffff0000 |
| 1536 | #define BCCKTXSIG 0xff | 1559 | #define BCCKTXSIG 0xff |
| 1537 | #define BCCKTXSERVICE 0xff00 | 1560 | #define BCCKTXSERVICE 0xff00 |
| 1538 | #define BCCKLENGTHEXT 0x8000 | 1561 | #define BCCKLENGTHEXT 0x8000 |
| 1539 | #define BCCKTXLENGHT 0xffff0000 | 1562 | #define BCCKTXLENGHT 0xffff0000 |
| 1540 | #define BCCKTXCRC16 0xffff | 1563 | #define BCCKTXCRC16 0xffff |
| 1541 | #define BCCKTXSTATUS 0x1 | 1564 | #define BCCKTXSTATUS 0x1 |
| 1542 | #define BOFDMTXSTATUS 0x2 | 1565 | #define BOFDMTXSTATUS 0x2 |
| 1543 | #define IS_BB_REG_OFFSET_92S(_Offset) \ | 1566 | #define IS_BB_REG_OFFSET_92S(_offset) \ |
| 1544 | ((_Offset >= 0x800) && (_Offset <= 0xfff)) | 1567 | ((_offset >= 0x800) && (_offset <= 0xfff)) |
| 1545 | 1568 | ||
| 1546 | #define BRFMOD 0x1 | 1569 | #define BRFMOD 0x1 |
| 1547 | #define BJAPANMODE 0x2 | 1570 | #define BJAPANMODE 0x2 |
| 1548 | #define BCCKTXSC 0x30 | 1571 | #define BCCKTXSC 0x30 |
| 1549 | #define BCCKEN 0x1000000 | 1572 | #define BCCKEN 0x1000000 |
| 1550 | #define BOFDMEN 0x2000000 | 1573 | #define BOFDMEN 0x2000000 |
| 1551 | 1574 | ||
| 1552 | #define BOFDMRXADCPHASE 0x10000 | 1575 | #define BOFDMRXADCPHASE 0x10000 |
| 1553 | #define BOFDMTXDACPHASE 0x40000 | 1576 | #define BOFDMTXDACPHASE 0x40000 |
| 1554 | #define BXATXAGC 0x3f | 1577 | #define BXATXAGC 0x3f |
| 1555 | 1578 | ||
| 1556 | #define BXBTXAGC 0xf00 | 1579 | #define BXBTXAGC 0xf00 |
| 1557 | #define BXCTXAGC 0xf000 | 1580 | #define BXCTXAGC 0xf000 |
| 1558 | #define BXDTXAGC 0xf0000 | 1581 | #define BXDTXAGC 0xf0000 |
| 1559 | 1582 | ||
| 1560 | #define BPASTART 0xf0000000 | 1583 | #define BPASTART 0xf0000000 |
| 1561 | #define BTRSTART 0x00f00000 | 1584 | #define BTRSTART 0x00f00000 |
| 1562 | #define BRFSTART 0x0000f000 | 1585 | #define BRFSTART 0x0000f000 |
| 1563 | #define BBBSTART 0x000000f0 | 1586 | #define BBBSTART 0x000000f0 |
| 1564 | #define BBBCCKSTART 0x0000000f | 1587 | #define BBBCCKSTART 0x0000000f |
| 1565 | #define BPAEND 0xf | 1588 | #define BPAEND 0xf |
| 1566 | #define BTREND 0x0f000000 | 1589 | #define BTREND 0x0f000000 |
| 1567 | #define BRFEND 0x000f0000 | 1590 | #define BRFEND 0x000f0000 |
| 1568 | #define BCCAMASK 0x000000f0 | 1591 | #define BCCAMASK 0x000000f0 |
| 1569 | #define BR2RCCAMASK 0x00000f00 | 1592 | #define BR2RCCAMASK 0x00000f00 |
| 1570 | #define BHSSI_R2TDELAY 0xf8000000 | 1593 | #define BHSSI_R2TDELAY 0xf8000000 |
| 1571 | #define BHSSI_T2RDELAY 0xf80000 | 1594 | #define BHSSI_T2RDELAY 0xf80000 |
| 1572 | #define BCONTXHSSI 0x400 | 1595 | #define BCONTXHSSI 0x400 |
| 1573 | #define BIGFROMCCK 0x200 | 1596 | #define BIGFROMCCK 0x200 |
| 1574 | #define BAGCADDRESS 0x3f | 1597 | #define BAGCADDRESS 0x3f |
| 1575 | #define BRXHPTX 0x7000 | 1598 | #define BRXHPTX 0x7000 |
| 1576 | #define BRXHP2RX 0x38000 | 1599 | #define BRXHP2RX 0x38000 |
| 1577 | #define BRXHPCCKINI 0xc0000 | 1600 | #define BRXHPCCKINI 0xc0000 |
| 1578 | #define BAGCTXCODE 0xc00000 | 1601 | #define BAGCTXCODE 0xc00000 |
| 1579 | #define BAGCRXCODE 0x300000 | 1602 | #define BAGCRXCODE 0x300000 |
| 1580 | 1603 | ||
| 1581 | #define B3WIREDATALENGTH 0x800 | 1604 | #define B3WIREDATALENGTH 0x800 |
| 1582 | #define B3WIREADDREAALENGTH 0x400 | 1605 | #define B3WIREADDREAALENGTH 0x400 |
| 1583 | 1606 | ||
| 1584 | #define B3WIRERFPOWERDOWN 0x1 | 1607 | #define B3WIRERFPOWERDOWN 0x1 |
| 1585 | #define B5GPAPEPOLARITY 0x40000000 | 1608 | #define B5GPAPEPOLARITY 0x40000000 |
| 1586 | #define B2GPAPEPOLARITY 0x80000000 | 1609 | #define B2GPAPEPOLARITY 0x80000000 |
| 1587 | #define BRFSW_TXDEFAULTANT 0x3 | 1610 | #define BRFSW_TXDEFAULTANT 0x3 |
| 1588 | #define BRFSW_TXOPTIONANT 0x30 | 1611 | #define BRFSW_TXOPTIONANT 0x30 |
| 1589 | #define BRFSW_RXDEFAULTANT 0x300 | 1612 | #define BRFSW_RXDEFAULTANT 0x300 |
| 1590 | #define BRFSW_RXOPTIONANT 0x3000 | 1613 | #define BRFSW_RXOPTIONANT 0x3000 |
| 1591 | #define BRFSI_3WIREDATA 0x1 | 1614 | #define BRFSI_3WIREDATA 0x1 |
| 1592 | #define BRFSI_3WIRECLOCK 0x2 | 1615 | #define BRFSI_3WIRECLOCK 0x2 |
| 1593 | #define BRFSI_3WIRELOAD 0x4 | 1616 | #define BRFSI_3WIRELOAD 0x4 |
| 1594 | #define BRFSI_3WIRERW 0x8 | 1617 | #define BRFSI_3WIRERW 0x8 |
| 1595 | #define BRFSI_3WIRE 0xf | 1618 | #define BRFSI_3WIRE 0xf |
| 1596 | 1619 | ||
| 1597 | #define BRFSI_RFENV 0x10 | 1620 | #define BRFSI_RFENV 0x10 |
| 1598 | 1621 | ||
| 1599 | #define BRFSI_TRSW 0x20 | 1622 | #define BRFSI_TRSW 0x20 |
| 1600 | #define BRFSI_TRSWB 0x40 | 1623 | #define BRFSI_TRSWB 0x40 |
| 1601 | #define BRFSI_ANTSW 0x100 | 1624 | #define BRFSI_ANTSW 0x100 |
| 1602 | #define BRFSI_ANTSWB 0x200 | 1625 | #define BRFSI_ANTSWB 0x200 |
| 1603 | #define BRFSI_PAPE 0x400 | 1626 | #define BRFSI_PAPE 0x400 |
| 1604 | #define BRFSI_PAPE5G 0x800 | 1627 | #define BRFSI_PAPE5G 0x800 |
| 1605 | #define BBANDSELECT 0x1 | 1628 | #define BBANDSELECT 0x1 |
| 1606 | #define BHTSIG2_GI 0x80 | 1629 | #define BHTSIG2_GI 0x80 |
| 1607 | #define BHTSIG2_SMOOTHING 0x01 | 1630 | #define BHTSIG2_SMOOTHING 0x01 |
| 1608 | #define BHTSIG2_SOUNDING 0x02 | 1631 | #define BHTSIG2_SOUNDING 0x02 |
| 1609 | #define BHTSIG2_AGGREATON 0x08 | 1632 | #define BHTSIG2_AGGREATON 0x08 |
| 1610 | #define BHTSIG2_STBC 0x30 | 1633 | #define BHTSIG2_STBC 0x30 |
| 1611 | #define BHTSIG2_ADVCODING 0x40 | 1634 | #define BHTSIG2_ADVCODING 0x40 |
| 1612 | #define BHTSIG2_NUMOFHTLTF 0x300 | 1635 | #define BHTSIG2_NUMOFHTLTF 0x300 |
| 1613 | #define BHTSIG2_CRC8 0x3fc | 1636 | #define BHTSIG2_CRC8 0x3fc |
| 1614 | #define BHTSIG1_MCS 0x7f | 1637 | #define BHTSIG1_MCS 0x7f |
| 1615 | #define BHTSIG1_BANDWIDTH 0x80 | 1638 | #define BHTSIG1_BANDWIDTH 0x80 |
| 1616 | #define BHTSIG1_HTLENGTH 0xffff | 1639 | #define BHTSIG1_HTLENGTH 0xffff |
| 1617 | #define BLSIG_RATE 0xf | 1640 | #define BLSIG_RATE 0xf |
| 1618 | #define BLSIG_RESERVED 0x10 | 1641 | #define BLSIG_RESERVED 0x10 |
| 1619 | #define BLSIG_LENGTH 0x1fffe | 1642 | #define BLSIG_LENGTH 0x1fffe |
| 1620 | #define BLSIG_PARITY 0x20 | 1643 | #define BLSIG_PARITY 0x20 |
| 1621 | #define BCCKRXPHASE 0x4 | 1644 | #define BCCKRXPHASE 0x4 |
| 1622 | 1645 | ||
| 1623 | #define BLSSIREADADDRESS 0x7f800000 | 1646 | #define BLSSIREADADDRESS 0x7f800000 |
| 1624 | #define BLSSIREADEDGE 0x80000000 | 1647 | #define BLSSIREADEDGE 0x80000000 |
| 1625 | 1648 | ||
| 1626 | #define BLSSIREADBACKDATA 0xfffff | 1649 | #define BLSSIREADBACKDATA 0xfffff |
| 1627 | 1650 | ||
| 1628 | #define BLSSIREADOKFLAG 0x1000 | 1651 | #define BLSSIREADOKFLAG 0x1000 |
| 1629 | #define BCCKSAMPLERATE 0x8 | 1652 | #define BCCKSAMPLERATE 0x8 |
| 1630 | #define BREGULATOR0STANDBY 0x1 | 1653 | #define BREGULATOR0STANDBY 0x1 |
| 1631 | #define BREGULATORPLLSTANDBY 0x2 | 1654 | #define BREGULATORPLLSTANDBY 0x2 |
| 1632 | #define BREGULATOR1STANDBY 0x4 | 1655 | #define BREGULATOR1STANDBY 0x4 |
| 1633 | #define BPLLPOWERUP 0x8 | 1656 | #define BPLLPOWERUP 0x8 |
| 1634 | #define BDPLLPOWERUP 0x10 | 1657 | #define BDPLLPOWERUP 0x10 |
| 1635 | #define BDA10POWERUP 0x20 | 1658 | #define BDA10POWERUP 0x20 |
| 1636 | #define BAD7POWERUP 0x200 | 1659 | #define BAD7POWERUP 0x200 |
| 1637 | #define BDA6POWERUP 0x2000 | 1660 | #define BDA6POWERUP 0x2000 |
| 1638 | #define BXTALPOWERUP 0x4000 | 1661 | #define BXTALPOWERUP 0x4000 |
| 1639 | #define B40MDCLKPOWERUP 0x8000 | 1662 | #define B40MDCLKPOWERUP 0x8000 |
| 1640 | #define BDA6DEBUGMODE 0x20000 | 1663 | #define BDA6DEBUGMODE 0x20000 |
| 1641 | #define BDA6SWING 0x380000 | 1664 | #define BDA6SWING 0x380000 |
| 1642 | 1665 | ||
| 1643 | #define BADCLKPHASE 0x4000000 | 1666 | #define BADCLKPHASE 0x4000000 |
| 1644 | #define B80MCLKDELAY 0x18000000 | 1667 | #define B80MCLKDELAY 0x18000000 |
| 1645 | #define BAFEWATCHDOGENABLE 0x20000000 | 1668 | #define BAFEWATCHDOGENABLE 0x20000000 |
| 1646 | 1669 | ||
| 1647 | #define BXTALCAP01 0xc0000000 | 1670 | #define BXTALCAP01 0xc0000000 |
| 1648 | #define BXTALCAP23 0x3 | 1671 | #define BXTALCAP23 0x3 |
| 1649 | #define BXTALCAP92X 0x0f000000 | 1672 | #define BXTALCAP92X 0x0f000000 |
| 1650 | #define BXTALCAP 0x0f000000 | 1673 | #define BXTALCAP 0x0f000000 |
| 1651 | 1674 | ||
| 1652 | #define BINTDIFCLKENABLE 0x400 | 1675 | #define BINTDIFCLKENABLE 0x400 |
| 1653 | #define BEXTSIGCLKENABLE 0x800 | 1676 | #define BEXTSIGCLKENABLE 0x800 |
| 1654 | #define BBANDGAP_MBIAS_POWERUP 0x10000 | 1677 | #define BBANDGAP_MBIAS_POWERUP 0x10000 |
| 1655 | #define BAD11SH_GAIN 0xc0000 | 1678 | #define BAD11SH_GAIN 0xc0000 |
| 1656 | #define BAD11NPUT_RANGE 0x700000 | 1679 | #define BAD11NPUT_RANGE 0x700000 |
| 1657 | #define BAD110P_CURRENT 0x3800000 | 1680 | #define BAD110P_CURRENT 0x3800000 |
| 1658 | #define BLPATH_LOOPBACK 0x4000000 | 1681 | #define BLPATH_LOOPBACK 0x4000000 |
| 1659 | #define BQPATH_LOOPBACK 0x8000000 | 1682 | #define BQPATH_LOOPBACK 0x8000000 |
| 1660 | #define BAFE_LOOPBACK 0x10000000 | 1683 | #define BAFE_LOOPBACK 0x10000000 |
| 1661 | #define BDA10_SWING 0x7e0 | 1684 | #define BDA10_SWING 0x7e0 |
| 1662 | #define BDA10_REVERSE 0x800 | 1685 | #define BDA10_REVERSE 0x800 |
| 1663 | #define BDA_CLK_SOURCE 0x1000 | 1686 | #define BDA_CLK_SOURCE 0x1000 |
| 1664 | #define BDA7INPUT_RANGE 0x6000 | 1687 | #define BDA7INPUT_RANGE 0x6000 |
| 1665 | #define BDA7_GAIN 0x38000 | 1688 | #define BDA7_GAIN 0x38000 |
| 1666 | #define BDA7OUTPUT_CM_MODE 0x40000 | 1689 | #define BDA7OUTPUT_CM_MODE 0x40000 |
| 1667 | #define BDA7INPUT_CM_MODE 0x380000 | 1690 | #define BDA7INPUT_CM_MODE 0x380000 |
| 1668 | #define BDA7CURRENT 0xc00000 | 1691 | #define BDA7CURRENT 0xc00000 |
| 1669 | #define BREGULATOR_ADJUST 0x7000000 | 1692 | #define BREGULATOR_ADJUST 0x7000000 |
| 1670 | #define BAD11POWERUP_ATTX 0x1 | 1693 | #define BAD11POWERUP_ATTX 0x1 |
| 1671 | #define BDA10PS_ATTX 0x10 | 1694 | #define BDA10PS_ATTX 0x10 |
| 1672 | #define BAD11POWERUP_ATRX 0x100 | 1695 | #define BAD11POWERUP_ATRX 0x100 |
| 1673 | #define BDA10PS_ATRX 0x1000 | 1696 | #define BDA10PS_ATRX 0x1000 |
| 1674 | #define BCCKRX_AGC_FORMAT 0x200 | 1697 | #define BCCKRX_AGC_FORMAT 0x200 |
| 1675 | #define BPSDFFT_SAMPLE_POINT 0xc000 | 1698 | #define BPSDFFT_SAMPLE_POINT 0xc000 |
| 1676 | #define BPSD_AVERAGE_NUM 0x3000 | 1699 | #define BPSD_AVERAGE_NUM 0x3000 |
| 1677 | #define BIQPATH_CONTROL 0xc00 | 1700 | #define BIQPATH_CONTROL 0xc00 |
| 1678 | #define BPSD_FREQ 0x3ff | 1701 | #define BPSD_FREQ 0x3ff |
| 1679 | #define BPSD_ANTENNA_PATH 0x30 | 1702 | #define BPSD_ANTENNA_PATH 0x30 |
| 1680 | #define BPSD_IQ_SWITCH 0x40 | 1703 | #define BPSD_IQ_SWITCH 0x40 |
| 1681 | #define BPSD_RX_TRIGGER 0x400000 | 1704 | #define BPSD_RX_TRIGGER 0x400000 |
| 1682 | #define BPSD_TX_TRIGGER 0x80000000 | 1705 | #define BPSD_TX_TRIGGER 0x80000000 |
| 1683 | #define BPSD_SINE_TONE_SCALE 0x7f000000 | 1706 | #define BPSD_SINE_TONE_SCALE 0x7f000000 |
| 1684 | #define BPSD_REPORT 0xffff | 1707 | #define BPSD_REPORT 0xffff |
| 1685 | 1708 | ||
| 1686 | #define BOFDM_TXSC 0x30000000 | 1709 | #define BOFDM_TXSC 0x30000000 |
| 1687 | #define BCCK_TXON 0x1 | 1710 | #define BCCK_TXON 0x1 |
| 1688 | #define BOFDM_TXON 0x2 | 1711 | #define BOFDM_TXON 0x2 |
| 1689 | #define BDEBUG_PAGE 0xfff | 1712 | #define BDEBUG_PAGE 0xfff |
| 1690 | #define BDEBUG_ITEM 0xff | 1713 | #define BDEBUG_ITEM 0xff |
| 1691 | #define BANTL 0x10 | 1714 | #define BANTL 0x10 |
| 1692 | #define BANT_NONHT 0x100 | 1715 | #define BANT_NONHT 0x100 |
| 1693 | #define BANT_HT1 0x1000 | 1716 | #define BANT_HT1 0x1000 |
| 1694 | #define BANT_HT2 0x10000 | 1717 | #define BANT_HT2 0x10000 |
| 1695 | #define BANT_HT1S1 0x100000 | 1718 | #define BANT_HT1S1 0x100000 |
| 1696 | #define BANT_NONHTS1 0x1000000 | 1719 | #define BANT_NONHTS1 0x1000000 |
| 1697 | 1720 | ||
| 1698 | #define BCCK_BBMODE 0x3 | 1721 | #define BCCK_BBMODE 0x3 |
| 1699 | #define BCCK_TXPOWERSAVING 0x80 | 1722 | #define BCCK_TXPOWERSAVING 0x80 |
| 1700 | #define BCCK_RXPOWERSAVING 0x40 | 1723 | #define BCCK_RXPOWERSAVING 0x40 |
| 1701 | 1724 | ||
| 1702 | #define BCCK_SIDEBAND 0x10 | 1725 | #define BCCK_SIDEBAND 0x10 |
| 1703 | 1726 | ||
| 1704 | #define BCCK_SCRAMBLE 0x8 | 1727 | #define BCCK_SCRAMBLE 0x8 |
| 1705 | #define BCCK_ANTDIVERSITY 0x8000 | 1728 | #define BCCK_ANTDIVERSITY 0x8000 |
| 1706 | #define BCCK_CARRIER_RECOVERY 0x4000 | 1729 | #define BCCK_CARRIER_RECOVERY 0x4000 |
| 1707 | #define BCCK_TXRATE 0x3000 | 1730 | #define BCCK_TXRATE 0x3000 |
| 1708 | #define BCCK_DCCANCEL 0x0800 | 1731 | #define BCCK_DCCANCEL 0x0800 |
| 1709 | #define BCCK_ISICANCEL 0x0400 | 1732 | #define BCCK_ISICANCEL 0x0400 |
| 1710 | #define BCCK_MATCH_FILTER 0x0200 | 1733 | #define BCCK_MATCH_FILTER 0x0200 |
| 1711 | #define BCCK_EQUALIZER 0x0100 | 1734 | #define BCCK_EQUALIZER 0x0100 |
| 1712 | #define BCCK_PREAMBLE_DETECT 0x800000 | 1735 | #define BCCK_PREAMBLE_DETECT 0x800000 |
| 1713 | #define BCCK_FAST_FALSECCAi 0x400000 | 1736 | #define BCCK_FAST_FALSECCA 0x400000 |
| 1714 | #define BCCK_CH_ESTSTARTi 0x300000 | 1737 | #define BCCK_CH_ESTSTART 0x300000 |
| 1715 | #define BCCK_CCA_COUNTi 0x080000 | 1738 | #define BCCK_CCA_COUNT 0x080000 |
| 1716 | #define BCCK_CS_LIM 0x070000 | 1739 | #define BCCK_CS_LIM 0x070000 |
| 1717 | #define BCCK_BIST_MODEi 0x80000000 | 1740 | #define BCCK_BIST_MODE 0x80000000 |
| 1718 | #define BCCK_CCAMASK 0x40000000 | 1741 | #define BCCK_CCAMASK 0x40000000 |
| 1719 | #define BCCK_TX_DAC_PHASE 0x4 | 1742 | #define BCCK_TX_DAC_PHASE 0x4 |
| 1720 | #define BCCK_RX_ADC_PHASE 0x20000000 | 1743 | #define BCCK_RX_ADC_PHASE 0x20000000 |
| 1721 | #define BCCKR_CP_MODE 0x0100 | 1744 | #define BCCKR_CP_MODE 0x0100 |
| 1722 | #define BCCK_TXDC_OFFSET 0xf0 | 1745 | #define BCCK_TXDC_OFFSET 0xf0 |
| 1723 | #define BCCK_RXDC_OFFSET 0xf | 1746 | #define BCCK_RXDC_OFFSET 0xf |
| 1724 | #define BCCK_CCA_MODE 0xc000 | 1747 | #define BCCK_CCA_MODE 0xc000 |
| 1725 | #define BCCK_FALSECS_LIM 0x3f00 | 1748 | #define BCCK_FALSECS_LIM 0x3f00 |
| 1726 | #define BCCK_CS_RATIO 0xc00000 | 1749 | #define BCCK_CS_RATIO 0xc00000 |
| 1727 | #define BCCK_CORGBIT_SEL 0x300000 | 1750 | #define BCCK_CORGBIT_SEL 0x300000 |
| 1728 | #define BCCK_PD_LIM 0x0f0000 | 1751 | #define BCCK_PD_LIM 0x0f0000 |
| 1729 | #define BCCK_NEWCCA 0x80000000 | 1752 | #define BCCK_NEWCCA 0x80000000 |
| 1730 | #define BCCK_RXHP_OF_IG 0x8000 | 1753 | #define BCCK_RXHP_OF_IG 0x8000 |
| 1731 | #define BCCK_RXIG 0x7f00 | 1754 | #define BCCK_RXIG 0x7f00 |
| 1732 | #define BCCK_LNA_POLARITY 0x800000 | 1755 | #define BCCK_LNA_POLARITY 0x800000 |
| 1733 | #define BCCK_RX1ST_BAIN 0x7f0000 | 1756 | #define BCCK_RX1ST_BAIN 0x7f0000 |
| 1734 | #define BCCK_RF_EXTEND 0x20000000 | 1757 | #define BCCK_RF_EXTEND 0x20000000 |
| 1735 | #define BCCK_RXAGC_SATLEVEL 0x1f000000 | 1758 | #define BCCK_RXAGC_SATLEVEL 0x1f000000 |
| 1736 | #define BCCK_RXAGC_SATCOUNT 0xe0 | 1759 | #define BCCK_RXAGC_SATCOUNT 0xe0 |
| 1737 | #define bCCKRxRFSettle 0x1f | 1760 | #define BCCKRXRFSETTLE 0x1f |
| 1738 | #define BCCK_FIXED_RXAGC 0x8000 | 1761 | #define BCCK_FIXED_RXAGC 0x8000 |
| 1739 | #define BCCK_ANTENNA_POLARITY 0x2000 | 1762 | #define BCCK_ANTENNA_POLARITY 0x2000 |
| 1740 | #define BCCK_TXFILTER_TYPE 0x0c00 | 1763 | #define BCCK_TXFILTER_TYPE 0x0c00 |
| 1741 | #define BCCK_RXAGC_REPORTTYPE 0x0300 | 1764 | #define BCCK_RXAGC_REPORTTYPE 0x0300 |
| 1742 | #define BCCK_RXDAGC_EN 0x80000000 | 1765 | #define BCCK_RXDAGC_EN 0x80000000 |
| 1743 | #define BCCK_RXDAGC_PERIOD 0x20000000 | 1766 | #define BCCK_RXDAGC_PERIOD 0x20000000 |
| 1744 | #define BCCK_RXDAGC_SATLEVEL 0x1f000000 | 1767 | #define BCCK_RXDAGC_SATLEVEL 0x1f000000 |
| 1745 | #define BCCK_TIMING_RECOVERY 0x800000 | 1768 | #define BCCK_TIMING_RECOVERY 0x800000 |
| 1746 | #define BCCK_TXC0 0x3f0000 | 1769 | #define BCCK_TXC0 0x3f0000 |
| 1747 | #define BCCK_TXC1 0x3f000000 | 1770 | #define BCCK_TXC1 0x3f000000 |
| 1748 | #define BCCK_TXC2 0x3f | 1771 | #define BCCK_TXC2 0x3f |
| 1749 | #define BCCK_TXC3 0x3f00 | 1772 | #define BCCK_TXC3 0x3f00 |
| 1750 | #define BCCK_TXC4 0x3f0000 | 1773 | #define BCCK_TXC4 0x3f0000 |
| 1751 | #define BCCK_TXC5 0x3f000000 | 1774 | #define BCCK_TXC5 0x3f000000 |
| 1752 | #define BCCK_TXC6 0x3f | 1775 | #define BCCK_TXC6 0x3f |
| 1753 | #define BCCK_TXC7 0x3f00 | 1776 | #define BCCK_TXC7 0x3f00 |
| 1754 | #define BCCK_DEBUGPORT 0xff0000 | 1777 | #define BCCK_DEBUGPORT 0xff0000 |
| 1755 | #define BCCK_DAC_DEBUG 0x0f000000 | 1778 | #define BCCK_DAC_DEBUG 0x0f000000 |
| 1756 | #define BCCK_FALSEALARM_ENABLE 0x8000 | 1779 | #define BCCK_FALSEALARM_ENABLE 0x8000 |
| 1757 | #define BCCK_FALSEALARM_READ 0x4000 | 1780 | #define BCCK_FALSEALARM_READ 0x4000 |
| 1758 | #define BCCK_TRSSI 0x7f | 1781 | #define BCCK_TRSSI 0x7f |
| 1759 | #define BCCK_RXAGC_REPORT 0xfe | 1782 | #define BCCK_RXAGC_REPORT 0xfe |
| 1760 | #define BCCK_RXREPORT_ANTSEL 0x80000000 | 1783 | #define BCCK_RXREPORT_ANTSEL 0x80000000 |
| 1761 | #define BCCK_RXREPORT_MFOFF 0x40000000 | 1784 | #define BCCK_RXREPORT_MFOFF 0x40000000 |
| 1762 | #define BCCK_RXREPORT_SQLOSS 0x20000000 | 1785 | #define BCCK_RXREPORT_SQLOSS 0x20000000 |
| 1763 | #define BCCK_RXREPORT_PKTLOSS 0x10000000 | 1786 | #define BCCK_RXREPORT_PKTLOSS 0x10000000 |
| 1764 | #define BCCK_RXREPORT_LOCKEDBIT 0x08000000 | 1787 | #define BCCK_RXREPORT_LOCKEDBIT 0x08000000 |
| 1765 | #define BCCK_RXREPORT_RATEERROR 0x04000000 | 1788 | #define BCCK_RXREPORT_RATEERROR 0x04000000 |
| 1766 | #define BCCK_RXREPORT_RXRATE 0x03000000 | 1789 | #define BCCK_RXREPORT_RXRATE 0x03000000 |
| 1767 | #define BCCK_RXFA_COUNTER_LOWER 0xff | 1790 | #define BCCK_RXFA_COUNTER_LOWER 0xff |
| 1768 | #define BCCK_RXFA_COUNTER_UPPER 0xff000000 | 1791 | #define BCCK_RXFA_COUNTER_UPPER 0xff000000 |
| 1769 | #define BCCK_RXHPAGC_START 0xe000 | 1792 | #define BCCK_RXHPAGC_START 0xe000 |
| 1770 | #define BCCK_RXHPAGC_FINAL 0x1c00 | 1793 | #define BCCK_RXHPAGC_FINAL 0x1c00 |
| 1771 | #define BCCK_RXFALSEALARM_ENABLE 0x8000 | 1794 | #define BCCK_RXFALSEALARM_ENABLE 0x8000 |
| 1772 | #define BCCK_FACOUNTER_FREEZE 0x4000 | 1795 | #define BCCK_FACOUNTER_FREEZE 0x4000 |
| 1773 | #define BCCK_TXPATH_SEL 0x10000000 | 1796 | #define BCCK_TXPATH_SEL 0x10000000 |
| 1774 | #define BCCK_DEFAULT_RXPATH 0xc000000 | 1797 | #define BCCK_DEFAULT_RXPATH 0xc000000 |
| 1775 | #define BCCK_OPTION_RXPATH 0x3000000 | 1798 | #define BCCK_OPTION_RXPATH 0x3000000 |
| 1776 | 1799 | ||
| 1777 | #define BNUM_OFSTF 0x3 | 1800 | #define BNUM_OFSTF 0x3 |
| 1778 | #define BSHIFT_L 0xc0 | 1801 | #define BSHIFT_L 0xc0 |
| 1779 | #define BGI_TH 0xc | 1802 | #define BGI_TH 0xc |
| 1780 | #define BRXPATH_A 0x1 | 1803 | #define BRXPATH_A 0x1 |
| 1781 | #define BRXPATH_B 0x2 | 1804 | #define BRXPATH_B 0x2 |
| 1782 | #define BRXPATH_C 0x4 | 1805 | #define BRXPATH_C 0x4 |
| 1783 | #define BRXPATH_D 0x8 | 1806 | #define BRXPATH_D 0x8 |
| 1784 | #define BTXPATH_A 0x1 | 1807 | #define BTXPATH_A 0x1 |
| 1785 | #define BTXPATH_B 0x2 | 1808 | #define BTXPATH_B 0x2 |
| 1786 | #define BTXPATH_C 0x4 | 1809 | #define BTXPATH_C 0x4 |
| 1787 | #define BTXPATH_D 0x8 | 1810 | #define BTXPATH_D 0x8 |
| 1788 | #define BTRSSI_FREQ 0x200 | 1811 | #define BTRSSI_FREQ 0x200 |
| 1789 | #define BADC_BACKOFF 0x3000 | 1812 | #define BADC_BACKOFF 0x3000 |
| 1790 | #define BDFIR_BACKOFF 0xc000 | 1813 | #define BDFIR_BACKOFF 0xc000 |
| 1791 | #define BTRSSI_LATCH_PHASE 0x10000 | 1814 | #define BTRSSI_LATCH_PHASE 0x10000 |
| 1792 | #define BRX_LDC_OFFSET 0xff | 1815 | #define BRX_LDC_OFFSET 0xff |
| 1793 | #define BRX_QDC_OFFSET 0xff00 | 1816 | #define BRX_QDC_OFFSET 0xff00 |
| 1794 | #define BRX_DFIR_MODE 0x1800000 | 1817 | #define BRX_DFIR_MODE 0x1800000 |
| 1795 | #define BRX_DCNF_TYPE 0xe000000 | 1818 | #define BRX_DCNF_TYPE 0xe000000 |
| 1796 | #define BRXIQIMB_A 0x3ff | 1819 | #define BRXIQIMB_A 0x3ff |
| 1797 | #define BRXIQIMB_B 0xfc00 | 1820 | #define BRXIQIMB_B 0xfc00 |
| 1798 | #define BRXIQIMB_C 0x3f0000 | 1821 | #define BRXIQIMB_C 0x3f0000 |
| 1799 | #define BRXIQIMB_D 0xffc00000 | 1822 | #define BRXIQIMB_D 0xffc00000 |
| 1800 | #define BDC_DC_NOTCH 0x60000 | 1823 | #define BDC_DC_NOTCH 0x60000 |
| 1801 | #define BRXNB_NOTCH 0x1f000000 | 1824 | #define BRXNB_NOTCH 0x1f000000 |
| 1802 | #define BPD_TH 0xf | 1825 | #define BPD_TH 0xf |
| 1803 | #define BPD_TH_OPT2 0xc000 | 1826 | #define BPD_TH_OPT2 0xc000 |
| 1804 | #define BPWED_TH 0x700 | 1827 | #define BPWED_TH 0x700 |
| 1805 | #define BIFMF_WIN_L 0x800 | 1828 | #define BIFMF_WIN_L 0x800 |
| 1806 | #define BPD_OPTION 0x1000 | 1829 | #define BPD_OPTION 0x1000 |
| 1807 | #define BMF_WIN_L 0xe000 | 1830 | #define BMF_WIN_L 0xe000 |
| 1808 | #define BBW_SEARCH_L 0x30000 | 1831 | #define BBW_SEARCH_L 0x30000 |
| 1809 | #define BWIN_ENH_L 0xc0000 | 1832 | #define BWIN_ENH_L 0xc0000 |
| 1810 | #define BBW_TH 0x700000 | 1833 | #define BBW_TH 0x700000 |
| 1811 | #define BED_TH2 0x3800000 | 1834 | #define BED_TH2 0x3800000 |
| 1812 | #define BBW_OPTION 0x4000000 | 1835 | #define BBW_OPTION 0x4000000 |
| 1813 | #define BRADIO_TH 0x18000000 | 1836 | #define BRADIO_TH 0x18000000 |
| 1814 | #define BWINDOW_L 0xe0000000 | 1837 | #define BWINDOW_L 0xe0000000 |
| 1815 | #define BSBD_OPTION 0x1 | 1838 | #define BSBD_OPTION 0x1 |
| 1816 | #define BFRAME_TH 0x1c | 1839 | #define BFRAME_TH 0x1c |
| 1817 | #define BFS_OPTION 0x60 | 1840 | #define BFS_OPTION 0x60 |
| 1818 | #define BDC_SLOPE_CHECK 0x80 | 1841 | #define BDC_SLOPE_CHECK 0x80 |
| 1819 | #define BFGUARD_COUNTER_DC_L 0xe00 | 1842 | #define BFGUARD_COUNTER_DC_L 0xe00 |
| 1820 | #define BFRAME_WEIGHT_SHORT 0x7000 | 1843 | #define BFRAME_WEIGHT_SHORT 0x7000 |
| 1821 | #define BSUB_TUNE 0xe00000 | 1844 | #define BSUB_TUNE 0xe00000 |
| 1822 | #define BFRAME_DC_LENGTH 0xe000000 | 1845 | #define BFRAME_DC_LENGTH 0xe000000 |
| 1823 | #define BSBD_START_OFFSET 0x30000000 | 1846 | #define BSBD_START_OFFSET 0x30000000 |
| 1824 | #define BFRAME_TH_2 0x7 | 1847 | #define BFRAME_TH_2 0x7 |
| 1825 | #define BFRAME_GI2_TH 0x38 | 1848 | #define BFRAME_GI2_TH 0x38 |
| 1826 | #define BGI2_SYNC_EN 0x40 | 1849 | #define BGI2_SYNC_EN 0x40 |
| 1827 | #define BSARCH_SHORT_EARLY 0x300 | 1850 | #define BSARCH_SHORT_EARLY 0x300 |
| 1828 | #define BSARCH_SHORT_LATE 0xc00 | 1851 | #define BSARCH_SHORT_LATE 0xc00 |
| 1829 | #define BSARCH_GI2_LATE 0x70000 | 1852 | #define BSARCH_GI2_LATE 0x70000 |
| 1830 | #define BCFOANTSUM 0x1 | 1853 | #define BCFOANTSUM 0x1 |
| 1831 | #define BCFOACC 0x2 | 1854 | #define BCFOACC 0x2 |
| 1832 | #define BCFOSTARTOFFSET 0xc | 1855 | #define BCFOSTARTOFFSET 0xc |
| 1833 | #define BCFOLOOPBACK 0x70 | 1856 | #define BCFOLOOPBACK 0x70 |
| 1834 | #define BCFOSUMWEIGHT 0x80 | 1857 | #define BCFOSUMWEIGHT 0x80 |
| 1835 | #define BDAGCENABLE 0x10000 | 1858 | #define BDAGCENABLE 0x10000 |
| 1836 | #define BTXIQIMB_A 0x3ff | 1859 | #define BTXIQIMB_A 0x3ff |
| 1837 | #define BTXIQIMB_b 0xfc00 | 1860 | #define BTXIQIMB_b 0xfc00 |
| 1838 | #define BTXIQIMB_C 0x3f0000 | 1861 | #define BTXIQIMB_C 0x3f0000 |
| 1839 | #define BTXIQIMB_D 0xffc00000 | 1862 | #define BTXIQIMB_D 0xffc00000 |
| 1840 | #define BTXIDCOFFSET 0xff | 1863 | #define BTXIDCOFFSET 0xff |
| 1841 | #define BTXIQDCOFFSET 0xff00 | 1864 | #define BTXIQDCOFFSET 0xff00 |
| 1842 | #define BTXDFIRMODE 0x10000 | 1865 | #define BTXDFIRMODE 0x10000 |
| 1843 | #define BTXPESUDO_NOISEON 0x4000000 | 1866 | #define BTXPESUDO_NOISEON 0x4000000 |
| 1844 | #define BTXPESUDO_NOISE_A 0xff | 1867 | #define BTXPESUDO_NOISE_A 0xff |
| 1845 | #define BTXPESUDO_NOISE_B 0xff00 | 1868 | #define BTXPESUDO_NOISE_B 0xff00 |
| 1846 | #define BTXPESUDO_NOISE_C 0xff0000 | 1869 | #define BTXPESUDO_NOISE_C 0xff0000 |
| 1847 | #define BTXPESUDO_NOISE_D 0xff000000 | 1870 | #define BTXPESUDO_NOISE_D 0xff000000 |
| 1848 | #define BCCA_DROPOPTION 0x20000 | 1871 | #define BCCA_DROPOPTION 0x20000 |
| 1849 | #define BCCA_DROPTHRES 0xfff00000 | 1872 | #define BCCA_DROPTHRES 0xfff00000 |
| 1850 | #define BEDCCA_H 0xf | 1873 | #define BEDCCA_H 0xf |
| 1851 | #define BEDCCA_L 0xf0 | 1874 | #define BEDCCA_L 0xf0 |
| 1852 | #define BLAMBDA_ED 0x300 | 1875 | #define BLAMBDA_ED 0x300 |
| 1853 | #define BRX_INITIALGAIN 0x7f | 1876 | #define BRX_INITIALGAIN 0x7f |
| 1854 | #define BRX_ANTDIV_EN 0x80 | 1877 | #define BRX_ANTDIV_EN 0x80 |
| 1855 | #define BRX_AGC_ADDRESS_FOR_LNA 0x7f00 | 1878 | #define BRX_AGC_ADDRESS_FOR_LNA 0x7f00 |
| 1856 | #define BRX_HIGHPOWER_FLOW 0x8000 | 1879 | #define BRX_HIGHPOWER_FLOW 0x8000 |
| 1857 | #define BRX_AGC_FREEZE_THRES 0xc0000 | 1880 | #define BRX_AGC_FREEZE_THRES 0xc0000 |
| 1858 | #define BRX_FREEZESTEP_AGC1 0x300000 | 1881 | #define BRX_FREEZESTEP_AGC1 0x300000 |
| 1859 | #define BRX_FREEZESTEP_AGC2 0xc00000 | 1882 | #define BRX_FREEZESTEP_AGC2 0xc00000 |
| 1860 | #define BRX_FREEZESTEP_AGC3 0x3000000 | 1883 | #define BRX_FREEZESTEP_AGC3 0x3000000 |
| 1861 | #define BRX_FREEZESTEP_AGC0 0xc000000 | 1884 | #define BRX_FREEZESTEP_AGC0 0xc000000 |
| 1862 | #define BRXRSSI_CMP_EN 0x10000000 | 1885 | #define BRXRSSI_CMP_EN 0x10000000 |
| 1863 | #define BRXQUICK_AGCEN 0x20000000 | 1886 | #define BRXQUICK_AGCEN 0x20000000 |
| 1864 | #define BRXAGC_FREEZE_THRES_MODE 0x40000000 | 1887 | #define BRXAGC_FREEZE_THRES_MODE 0x40000000 |
| 1865 | #define BRX_OVERFLOW_CHECKTYPE 0x80000000 | 1888 | #define BRX_OVERFLOW_CHECKTYPE 0x80000000 |
| 1866 | #define BRX_AGCSHIFT 0x7f | 1889 | #define BRX_AGCSHIFT 0x7f |
| 1867 | #define BTRSW_TRI_ONLY 0x80 | 1890 | #define BTRSW_TRI_ONLY 0x80 |
| 1868 | #define BPOWER_THRES 0x300 | 1891 | #define BPOWER_THRES 0x300 |
| 1869 | #define BRXAGC_EN 0x1 | 1892 | #define BRXAGC_EN 0x1 |
| 1870 | #define BRXAGC_TOGETHER_EN 0x2 | 1893 | #define BRXAGC_TOGETHER_EN 0x2 |
| 1871 | #define BRXAGC_MIN 0x4 | 1894 | #define BRXAGC_MIN 0x4 |
| 1872 | #define BRXHP_INI 0x7 | 1895 | #define BRXHP_INI 0x7 |
| 1873 | #define BRXHP_TRLNA 0x70 | 1896 | #define BRXHP_TRLNA 0x70 |
| 1874 | #define BRXHP_RSSI 0x700 | 1897 | #define BRXHP_RSSI 0x700 |
| 1875 | #define BRXHP_BBP1 0x7000 | 1898 | #define BRXHP_BBP1 0x7000 |
| 1876 | #define BRXHP_BBP2 0x70000 | 1899 | #define BRXHP_BBP2 0x70000 |
| 1877 | #define BRXHP_BBP3 0x700000 | 1900 | #define BRXHP_BBP3 0x700000 |
| 1878 | #define BRSSI_H 0x7f0000 | 1901 | #define BRSSI_H 0x7f0000 |
| 1879 | #define BRSSI_GEN 0x7f000000 | 1902 | #define BRSSI_GEN 0x7f000000 |
| 1880 | #define BRXSETTLE_TRSW 0x7 | 1903 | #define BRXSETTLE_TRSW 0x7 |
| 1881 | #define BRXSETTLE_LNA 0x38 | 1904 | #define BRXSETTLE_LNA 0x38 |
| 1882 | #define BRXSETTLE_RSSI 0x1c0 | 1905 | #define BRXSETTLE_RSSI 0x1c0 |
| 1883 | #define BRXSETTLE_BBP 0xe00 | 1906 | #define BRXSETTLE_BBP 0xe00 |
| 1884 | #define BRXSETTLE_RXHP 0x7000 | 1907 | #define BRXSETTLE_RXHP 0x7000 |
| 1885 | #define BRXSETTLE_ANTSW_RSSI 0x38000 | 1908 | #define BRXSETTLE_ANTSW_RSSI 0x38000 |
| 1886 | #define BRXSETTLE_ANTSW 0xc0000 | 1909 | #define BRXSETTLE_ANTSW 0xc0000 |
| 1887 | #define BRXPROCESS_TIME_DAGC 0x300000 | 1910 | #define BRXPROCESS_TIME_DAGC 0x300000 |
| 1888 | #define BRXSETTLE_HSSI 0x400000 | 1911 | #define BRXSETTLE_HSSI 0x400000 |
| 1889 | #define BRXPROCESS_TIME_BBPPW 0x800000 | 1912 | #define BRXPROCESS_TIME_BBPPW 0x800000 |
| 1890 | #define BRXANTENNA_POWER_SHIFT 0x3000000 | 1913 | #define BRXANTENNA_POWER_SHIFT 0x3000000 |
| 1891 | #define BRSSI_TABLE_SELECT 0xc000000 | 1914 | #define BRSSI_TABLE_SELECT 0xc000000 |
| 1892 | #define BRXHP_FINAL 0x7000000 | 1915 | #define BRXHP_FINAL 0x7000000 |
| 1893 | #define BRXHPSETTLE_BBP 0x7 | 1916 | #define BRXHPSETTLE_BBP 0x7 |
| 1894 | #define BRXHTSETTLE_HSSI 0x8 | 1917 | #define BRXHTSETTLE_HSSI 0x8 |
| 1895 | #define BRXHTSETTLE_RXHP 0x70 | 1918 | #define BRXHTSETTLE_RXHP 0x70 |
| 1896 | #define BRXHTSETTLE_BBPPW 0x80 | 1919 | #define BRXHTSETTLE_BBPPW 0x80 |
| 1897 | #define BRXHTSETTLE_IDLE 0x300 | 1920 | #define BRXHTSETTLE_IDLE 0x300 |
| 1898 | #define BRXHTSETTLE_RESERVED 0x1c00 | 1921 | #define BRXHTSETTLE_RESERVED 0x1c00 |
| 1899 | #define BRXHT_RXHP_EN 0x8000 | 1922 | #define BRXHT_RXHP_EN 0x8000 |
| 1900 | #define BRXAGC_FREEZE_THRES 0x30000 | 1923 | #define BRXAGC_FREEZE_THRES 0x30000 |
| 1901 | #define BRXAGC_TOGETHEREN 0x40000 | 1924 | #define BRXAGC_TOGETHEREN 0x40000 |
| 1902 | #define BRXHTAGC_MIN 0x80000 | 1925 | #define BRXHTAGC_MIN 0x80000 |
| 1903 | #define BRXHTAGC_EN 0x100000 | 1926 | #define BRXHTAGC_EN 0x100000 |
| 1904 | #define BRXHTDAGC_EN 0x200000 | 1927 | #define BRXHTDAGC_EN 0x200000 |
| 1905 | #define BRXHT_RXHP_BBP 0x1c00000 | 1928 | #define BRXHT_RXHP_BBP 0x1c00000 |
| 1906 | #define BRXHT_RXHP_FINAL 0xe0000000 | 1929 | #define BRXHT_RXHP_FINAL 0xe0000000 |
| 1907 | #define BRXPW_RADIO_TH 0x3 | 1930 | #define BRXPW_RADIO_TH 0x3 |
| 1908 | #define BRXPW_RADIO_EN 0x4 | 1931 | #define BRXPW_RADIO_EN 0x4 |
| 1909 | #define BRXMF_HOLD 0x3800 | 1932 | #define BRXMF_HOLD 0x3800 |
| 1910 | #define BRXPD_DELAY_TH1 0x38 | 1933 | #define BRXPD_DELAY_TH1 0x38 |
| 1911 | #define BRXPD_DELAY_TH2 0x1c0 | 1934 | #define BRXPD_DELAY_TH2 0x1c0 |
| 1912 | #define BRXPD_DC_COUNT_MAX 0x600 | 1935 | #define BRXPD_DC_COUNT_MAX 0x600 |
| 1913 | #define BRXPD_DELAY_TH 0x8000 | 1936 | #define BRXPD_DELAY_TH 0x8000 |
| 1914 | #define BRXPROCESS_DELAY 0xf0000 | 1937 | #define BRXPROCESS_DELAY 0xf0000 |
| 1915 | #define BRXSEARCHRANGE_GI2_EARLY 0x700000 | 1938 | #define BRXSEARCHRANGE_GI2_EARLY 0x700000 |
| 1916 | #define BRXFRAME_FUARD_COUNTER_L 0x3800000 | 1939 | #define BRXFRAME_FUARD_COUNTER_L 0x3800000 |
| 1917 | #define BRXSGI_GUARD_L 0xc000000 | 1940 | #define BRXSGI_GUARD_L 0xc000000 |
| 1918 | #define BRXSGI_SEARCH_L 0x30000000 | 1941 | #define BRXSGI_SEARCH_L 0x30000000 |
| 1919 | #define BRXSGI_TH 0xc0000000 | 1942 | #define BRXSGI_TH 0xc0000000 |
| 1920 | #define BDFSCNT0 0xff | 1943 | #define BDFSCNT0 0xff |
| 1921 | #define BDFSCNT1 0xff00 | 1944 | #define BDFSCNT1 0xff00 |
| 1922 | #define BDFSFLAG 0xf0000 | 1945 | #define BDFSFLAG 0xf0000 |
| 1923 | #define BMF_WEIGHT_SUM 0x300000 | 1946 | #define BMF_WEIGHT_SUM 0x300000 |
| 1924 | #define BMINIDX_TH 0x7f000000 | 1947 | #define BMINIDX_TH 0x7f000000 |
| 1925 | #define BDAFORMAT 0x40000 | 1948 | #define BDAFORMAT 0x40000 |
| 1926 | #define BTXCH_EMU_ENABLE 0x01000000 | 1949 | #define BTXCH_EMU_ENABLE 0x01000000 |
| 1927 | #define BTRSW_ISOLATION_A 0x7f | 1950 | #define BTRSW_ISOLATION_A 0x7f |
| 1928 | #define BTRSW_ISOLATION_B 0x7f00 | 1951 | #define BTRSW_ISOLATION_B 0x7f00 |
| 1929 | #define BTRSW_ISOLATION_C 0x7f0000 | 1952 | #define BTRSW_ISOLATION_C 0x7f0000 |
| 1930 | #define BTRSW_ISOLATION_D 0x7f000000 | 1953 | #define BTRSW_ISOLATION_D 0x7f000000 |
| 1931 | #define BEXT_LNA_GAIN 0x7c00 | 1954 | #define BEXT_LNA_GAIN 0x7c00 |
| 1932 | 1955 | ||
| 1933 | #define BSTBC_EN 0x4 | 1956 | #define BSTBC_EN 0x4 |
| 1934 | #define BANTENNA_MAPPING 0x10 | 1957 | #define BANTENNA_MAPPING 0x10 |
| 1935 | #define BNSS 0x20 | 1958 | #define BNSS 0x20 |
| 1936 | #define BCFO_ANTSUM_ID 0x200 | 1959 | #define BCFO_ANTSUM_ID 0x200 |
| 1937 | #define BPHY_COUNTER_RESET 0x8000000 | 1960 | #define BPHY_COUNTER_RESET 0x8000000 |
| 1938 | #define BCFO_REPORT_GET 0x4000000 | 1961 | #define BCFO_REPORT_GET 0x4000000 |
| 1939 | #define BOFDM_CONTINUE_TX 0x10000000 | 1962 | #define BOFDM_CONTINUE_TX 0x10000000 |
| 1940 | #define BOFDM_SINGLE_CARRIER 0x20000000 | 1963 | #define BOFDM_SINGLE_CARRIER 0x20000000 |
| 1941 | #define BOFDM_SINGLE_TONE 0x40000000 | 1964 | #define BOFDM_SINGLE_TONE 0x40000000 |
| 1942 | #define BHT_DETECT 0x100 | 1965 | #define BHT_DETECT 0x100 |
| 1943 | #define BCFOEN 0x10000 | 1966 | #define BCFOEN 0x10000 |
| 1944 | #define BCFOVALUE 0xfff00000 | 1967 | #define BCFOVALUE 0xfff00000 |
| 1945 | #define BSIGTONE_RE 0x3f | 1968 | #define BSIGTONE_RE 0x3f |
| 1946 | #define BSIGTONE_IM 0x7f00 | 1969 | #define BSIGTONE_IM 0x7f00 |
| 1947 | #define BCOUNTER_CCA 0xffff | 1970 | #define BCOUNTER_CCA 0xffff |
| 1948 | #define BCOUNTER_PARITYFAIL 0xffff0000 | 1971 | #define BCOUNTER_PARITYFAIL 0xffff0000 |
| 1949 | #define BCOUNTER_RATEILLEGAL 0xffff | 1972 | #define BCOUNTER_RATEILLEGAL 0xffff |
| 1950 | #define BCOUNTER_CRC8FAIL 0xffff0000 | 1973 | #define BCOUNTER_CRC8FAIL 0xffff0000 |
| 1951 | #define BCOUNTER_MCSNOSUPPORT 0xffff | 1974 | #define BCOUNTER_MCSNOSUPPORT 0xffff |
| 1952 | #define BCOUNTER_FASTSYNC 0xffff | 1975 | #define BCOUNTER_FASTSYNC 0xffff |
| 1953 | #define BSHORTCFO 0xfff | 1976 | #define BSHORTCFO 0xfff |
| 1954 | #define BSHORTCFOT_LENGTH 12 | 1977 | #define BSHORTCFOT_LENGTH 12 |
| 1955 | #define BSHORTCFOF_LENGTH 11 | 1978 | #define BSHORTCFOF_LENGTH 11 |
| 1956 | #define BLONGCFO 0x7ff | 1979 | #define BLONGCFO 0x7ff |
| 1957 | #define BLONGCFOT_LENGTH 11 | 1980 | #define BLONGCFOT_LENGTH 11 |
| 1958 | #define BLONGCFOF_LENGTH 11 | 1981 | #define BLONGCFOF_LENGTH 11 |
| 1959 | #define BTAILCFO 0x1fff | 1982 | #define BTAILCFO 0x1fff |
| 1960 | #define BTAILCFOT_LENGTH 13 | 1983 | #define BTAILCFOT_LENGTH 13 |
| 1961 | #define BTAILCFOF_LENGTH 12 | 1984 | #define BTAILCFOF_LENGTH 12 |
| 1962 | #define BNOISE_EN_PWDB 0xffff | 1985 | #define BNOISE_EN_PWDB 0xffff |
| 1963 | #define BCC_POWER_DB 0xffff0000 | 1986 | #define BCC_POWER_DB 0xffff0000 |
| 1964 | #define BMOISE_PWDB 0xffff | 1987 | #define BMOISE_PWDB 0xffff |
| 1965 | #define BPOWERMEAST_LENGTH 10 | 1988 | #define BPOWERMEAST_LENGTH 10 |
| 1966 | #define BPOWERMEASF_LENGTH 3 | 1989 | #define BPOWERMEASF_LENGTH 3 |
| 1967 | #define BRX_HT_BW 0x1 | 1990 | #define BRX_HT_BW 0x1 |
| 1968 | #define BRXSC 0x6 | 1991 | #define BRXSC 0x6 |
| 1969 | #define BRX_HT 0x8 | 1992 | #define BRX_HT 0x8 |
| 1970 | #define BNB_INTF_DET_ON 0x1 | 1993 | #define BNB_INTF_DET_ON 0x1 |
| 1971 | #define BINTF_WIN_LEN_CFG 0x30 | 1994 | #define BINTF_WIN_LEN_CFG 0x30 |
| 1972 | #define BNB_INTF_TH_CFG 0x1c0 | 1995 | #define BNB_INTF_TH_CFG 0x1c0 |
| 1973 | #define BRFGAIN 0x3f | 1996 | #define BRFGAIN 0x3f |
| 1974 | #define BTABLESEL 0x40 | 1997 | #define BTABLESEL 0x40 |
| 1975 | #define BTRSW 0x80 | 1998 | #define BTRSW 0x80 |
| 1976 | #define BRXSNR_A 0xff | 1999 | #define BRXSNR_A 0xff |
| 1977 | #define BRXSNR_B 0xff00 | 2000 | #define BRXSNR_B 0xff00 |
| 1978 | #define BRXSNR_C 0xff0000 | 2001 | #define BRXSNR_C 0xff0000 |
| 1979 | #define BRXSNR_D 0xff000000 | 2002 | #define BRXSNR_D 0xff000000 |
| 1980 | #define BSNR_EVMT_LENGTH 8 | 2003 | #define BSNR_EVMT_LENGTH 8 |
| 1981 | #define BSNR_EVMF_LENGTH 1 | 2004 | #define BSNR_EVMF_LENGTH 1 |
| 1982 | #define BCSI1ST 0xff | 2005 | #define BCSI1ST 0xff |
| 1983 | #define BCSI2ND 0xff00 | 2006 | #define BCSI2ND 0xff00 |
| 1984 | #define BRXEVM1ST 0xff0000 | 2007 | #define BRXEVM1ST 0xff0000 |
| 1985 | #define BRXEVM2ND 0xff000000 | 2008 | #define BRXEVM2ND 0xff000000 |
| 1986 | #define BSIGEVM 0xff | 2009 | #define BSIGEVM 0xff |
| 1987 | #define BPWDB 0xff00 | 2010 | #define BPWDB 0xff00 |
| 1988 | #define BSGIEN 0x10000 | 2011 | #define BSGIEN 0x10000 |
| 1989 | 2012 | ||
| 1990 | #define BSFACTOR_QMA1 0xf | 2013 | #define BSFACTOR_QMA1 0xf |
| 1991 | #define BSFACTOR_QMA2 0xf0 | 2014 | #define BSFACTOR_QMA2 0xf0 |
| 1992 | #define BSFACTOR_QMA3 0xf00 | 2015 | #define BSFACTOR_QMA3 0xf00 |
| 1993 | #define BSFACTOR_QMA4 0xf000 | 2016 | #define BSFACTOR_QMA4 0xf000 |
| 1994 | #define BSFACTOR_QMA5 0xf0000 | 2017 | #define BSFACTOR_QMA5 0xf0000 |
| 1995 | #define BSFACTOR_QMA6 0xf0000 | 2018 | #define BSFACTOR_QMA6 0xf0000 |
| 1996 | #define BSFACTOR_QMA7 0xf00000 | 2019 | #define BSFACTOR_QMA7 0xf00000 |
| 1997 | #define BSFACTOR_QMA8 0xf000000 | 2020 | #define BSFACTOR_QMA8 0xf000000 |
| 1998 | #define BSFACTOR_QMA9 0xf0000000 | 2021 | #define BSFACTOR_QMA9 0xf0000000 |
| 1999 | #define BCSI_SCHEME 0x100000 | 2022 | #define BCSI_SCHEME 0x100000 |
| 2000 | 2023 | ||
| 2001 | #define BNOISE_LVL_TOP_SET 0x3 | 2024 | #define BNOISE_LVL_TOP_SET 0x3 |
| 2002 | #define BCHSMOOTH 0x4 | 2025 | #define BCHSMOOTH 0x4 |
| 2003 | #define BCHSMOOTH_CFG1 0x38 | 2026 | #define BCHSMOOTH_CFG1 0x38 |
| 2004 | #define BCHSMOOTH_CFG2 0x1c0 | 2027 | #define BCHSMOOTH_CFG2 0x1c0 |
| 2005 | #define BCHSMOOTH_CFG3 0xe00 | 2028 | #define BCHSMOOTH_CFG3 0xe00 |
| 2006 | #define BCHSMOOTH_CFG4 0x7000 | 2029 | #define BCHSMOOTH_CFG4 0x7000 |
| 2007 | #define BMRCMODE 0x800000 | 2030 | #define BMRCMODE 0x800000 |
| 2008 | #define BTHEVMCFG 0x7000000 | 2031 | #define BTHEVMCFG 0x7000000 |
| 2009 | 2032 | ||
| 2010 | #define BLOOP_FIT_TYPE 0x1 | 2033 | #define BLOOP_FIT_TYPE 0x1 |
| 2011 | #define BUPD_CFO 0x40 | 2034 | #define BUPD_CFO 0x40 |
| 2012 | #define BUPD_CFO_OFFDATA 0x80 | 2035 | #define BUPD_CFO_OFFDATA 0x80 |
| 2013 | #define BADV_UPD_CFO 0x100 | 2036 | #define BADV_UPD_CFO 0x100 |
| 2014 | #define BADV_TIME_CTRL 0x800 | 2037 | #define BADV_TIME_CTRL 0x800 |
| 2015 | #define BUPD_CLKO 0x1000 | 2038 | #define BUPD_CLKO 0x1000 |
| 2016 | #define BFC 0x6000 | 2039 | #define BFC 0x6000 |
| 2017 | #define BTRACKING_MODE 0x8000 | 2040 | #define BTRACKING_MODE 0x8000 |
| 2018 | #define BPHCMP_ENABLE 0x10000 | 2041 | #define BPHCMP_ENABLE 0x10000 |
| 2019 | #define BUPD_CLKO_LTF 0x20000 | 2042 | #define BUPD_CLKO_LTF 0x20000 |
| 2020 | #define BCOM_CH_CFO 0x40000 | 2043 | #define BCOM_CH_CFO 0x40000 |
| 2021 | #define BCSI_ESTI_MODE 0x80000 | 2044 | #define BCSI_ESTI_MODE 0x80000 |
| 2022 | #define BADV_UPD_EQZ 0x100000 | 2045 | #define BADV_UPD_EQZ 0x100000 |
| 2023 | #define BUCHCFG 0x7000000 | 2046 | #define BUCHCFG 0x7000000 |
| 2024 | #define BUPDEQZ 0x8000000 | 2047 | #define BUPDEQZ 0x8000000 |
| 2025 | 2048 | ||
| 2026 | #define BRX_PESUDO_NOISE_ON 0x20000000 | 2049 | #define BRX_PESUDO_NOISE_ON 0x20000000 |
| 2027 | #define BRX_PESUDO_NOISE_A 0xff | 2050 | #define BRX_PESUDO_NOISE_A 0xff |
| 2028 | #define BRX_PESUDO_NOISE_B 0xff00 | 2051 | #define BRX_PESUDO_NOISE_B 0xff00 |
| 2029 | #define BRX_PESUDO_NOISE_C 0xff0000 | 2052 | #define BRX_PESUDO_NOISE_C 0xff0000 |
| 2030 | #define BRX_PESUDO_NOISE_D 0xff000000 | 2053 | #define BRX_PESUDO_NOISE_D 0xff000000 |
| 2031 | #define BRX_PESUDO_NOISESTATE_A 0xffff | 2054 | #define BRX_PESUDO_NOISESTATE_A 0xffff |
| 2032 | #define BRX_PESUDO_NOISESTATE_B 0xffff0000 | 2055 | #define BRX_PESUDO_NOISESTATE_B 0xffff0000 |
| 2033 | #define BRX_PESUDO_NOISESTATE_C 0xffff | 2056 | #define BRX_PESUDO_NOISESTATE_C 0xffff |
| 2034 | #define BRX_PESUDO_NOISESTATE_D 0xffff0000 | 2057 | #define BRX_PESUDO_NOISESTATE_D 0xffff0000 |
| 2035 | 2058 | ||
| 2036 | #define BZEBRA1_HSSIENABLE 0x8 | 2059 | #define BZEBRA1_HSSIENABLE 0x8 |
| 2037 | #define BZEBRA1_TRXCONTROL 0xc00 | 2060 | #define BZEBRA1_TRXCONTROL 0xc00 |
| 2038 | #define BZEBRA1_TRXGAINSETTING 0x07f | 2061 | #define BZEBRA1_TRXGAINSETTING 0x07f |
| 2039 | #define BZEBRA1_RXCOUNTER 0xc00 | 2062 | #define BZEBRA1_RXCOUNTER 0xc00 |
| 2040 | #define BZEBRA1_TXCHANGEPUMP 0x38 | 2063 | #define BZEBRA1_TXCHANGEPUMP 0x38 |
| 2041 | #define BZEBRA1_RXCHANGEPUMP 0x7 | 2064 | #define BZEBRA1_RXCHANGEPUMP 0x7 |
| 2042 | #define BZEBRA1_CHANNEL_NUM 0xf80 | 2065 | #define BZEBRA1_CHANNEL_NUM 0xf80 |
| 2043 | #define BZEBRA1_TXLPFBW 0x400 | 2066 | #define BZEBRA1_TXLPFBW 0x400 |
| 2044 | #define BZEBRA1_RXLPFBW 0x600 | 2067 | #define BZEBRA1_RXLPFBW 0x600 |
| 2045 | 2068 | ||
| 2046 | #define BRTL8256REG_MODE_CTRL1 0x100 | 2069 | #define BRTL8256REG_MODE_CTRL1 0x100 |
| 2047 | #define BRTL8256REG_MODE_CTRL0 0x40 | 2070 | #define BRTL8256REG_MODE_CTRL0 0x40 |
| 2048 | #define BRTL8256REG_TXLPFBW 0x18 | 2071 | #define BRTL8256REG_TXLPFBW 0x18 |
| 2049 | #define BRTL8256REG_RXLPFBW 0x600 | 2072 | #define BRTL8256REG_RXLPFBW 0x600 |
| 2050 | 2073 | ||
| 2051 | #define BRTL8258_TXLPFBW 0xc | 2074 | #define BRTL8258_TXLPFBW 0xc |
| 2052 | #define BRTL8258_RXLPFBW 0xc00 | 2075 | #define BRTL8258_RXLPFBW 0xc00 |
| 2053 | #define BRTL8258_RSSILPFBW 0xc0 | 2076 | #define BRTL8258_RSSILPFBW 0xc0 |
| 2054 | 2077 | ||
| 2055 | #define BBYTE0 0x1 | 2078 | #define BBYTE0 0x1 |
| 2056 | #define BBYTE1 0x2 | 2079 | #define BBYTE1 0x2 |
| 2057 | #define BBYTE2 0x4 | 2080 | #define BBYTE2 0x4 |
| 2058 | #define BBYTE3 0x8 | 2081 | #define BBYTE3 0x8 |
| 2059 | #define BWORD0 0x3 | 2082 | #define BWORD0 0x3 |
| 2060 | #define BWORD1 0xc | 2083 | #define BWORD1 0xc |
| 2061 | #define BWORD 0xf | 2084 | #define BWORD 0xf |
| 2062 | 2085 | ||
| 2063 | #define BENABLE 0x1 | 2086 | #define MASKBYTE0 0xff |
| 2064 | #define BDISABLE 0x0 | 2087 | #define MASKBYTE1 0xff00 |
| 2065 | 2088 | #define MASKBYTE2 0xff0000 | |
| 2066 | #define LEFT_ANTENNA 0x0 | 2089 | #define MASKBYTE3 0xff000000 |
| 2067 | #define RIGHT_ANTENNA 0x1 | 2090 | #define MASKHWORD 0xffff0000 |
| 2068 | 2091 | #define MASKLWORD 0x0000ffff | |
| 2069 | #define TCHECK_TXSTATUS 500 | 2092 | #define MASKDWORD 0xffffffff |
| 2070 | #define TUPDATE_RXCOUNTER 100 | 2093 | #define MASK12BITS 0xfff |
| 2094 | #define MASKH4BITS 0xf0000000 | ||
| 2095 | #define MASKOFDM_D 0xffc00000 | ||
| 2096 | #define MASKCCK 0x3f3f3f3f | ||
| 2097 | |||
| 2098 | #define MASK4BITS 0x0f | ||
| 2099 | #define MASK20BITS 0xfffff | ||
| 2100 | #define RFREG_OFFSET_MASK 0xfffff | ||
| 2101 | |||
| 2102 | #define BENABLE 0x1 | ||
| 2103 | #define BDISABLE 0x0 | ||
| 2104 | |||
| 2105 | #define LEFT_ANTENNA 0x0 | ||
| 2106 | #define RIGHT_ANTENNA 0x1 | ||
| 2107 | |||
| 2108 | #define TCHECK_TXSTATUS 500 | ||
| 2109 | #define TUPDATE_RXCOUNTER 100 | ||
| 2071 | 2110 | ||
| 2072 | /* 2 EFUSE_TEST (For RTL8723 partially) */ | 2111 | /* 2 EFUSE_TEST (For RTL8723 partially) */ |
| 2073 | #define EFUSE_SEL(x) (((x) & 0x3) << 8) | 2112 | #define EFUSE_SEL(x) (((x) & 0x3) << 8) |
| 2074 | #define EFUSE_SEL_MASK 0x300 | 2113 | #define EFUSE_SEL_MASK 0x300 |
| 2075 | #define EFUSE_WIFI_SEL_0 0x0 | 2114 | #define EFUSE_WIFI_SEL_0 0x0 |
| 2076 | |||
| 2077 | /* Enable GPIO[9] as WiFi HW PDn source*/ | 2115 | /* Enable GPIO[9] as WiFi HW PDn source*/ |
| 2078 | #define WL_HWPDN_EN BIT(0) | 2116 | #define WL_HWPDN_EN BIT(0) |
| 2079 | /* WiFi HW PDn polarity control*/ | 2117 | /* WiFi HW PDn polarity control*/ |
| 2080 | #define WL_HWPDN_SL BIT(1) | 2118 | #define WL_HWPDN_SL BIT(1) |
| 2081 | 2119 | ||
| 2082 | #endif | 2120 | #endif |