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-rw-r--r--drivers/net/wireless/rtlwifi/pci.c4
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192c/fw_common.h13
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/fw.h12
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192se/fw.h1
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/btc.h7
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/def.h197
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/dm.c422
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/dm.h50
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/fw.c254
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/fw.h55
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/hal_bt_coexist.c414
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/hal_bt_coexist.h38
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/hal_btc.c1232
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/hal_btc.h66
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/hw.c1512
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/hw.h66
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/led.c54
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/led.h13
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/phy.c894
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/phy.h67
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/pwrseq.c91
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/pwrseq.h543
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/reg.h2718
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/rf.c261
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/rf.h18
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/sw.c220
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/sw.h12
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/table.c8
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/table.h8
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/trx.c458
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/trx.h325
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723be/hw.c2
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723be/sw.c2
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723com/dm_common.c14
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723com/fw_common.c84
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723com/fw_common.h39
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723com/phy_common.c46
-rw-r--r--drivers/net/wireless/rtlwifi/wifi.h19
38 files changed, 5403 insertions, 4836 deletions
diff --git a/drivers/net/wireless/rtlwifi/pci.c b/drivers/net/wireless/rtlwifi/pci.c
index 37a78bf01f94..1dbb22b537ef 100644
--- a/drivers/net/wireless/rtlwifi/pci.c
+++ b/drivers/net/wireless/rtlwifi/pci.c
@@ -952,10 +952,8 @@ static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
952 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb); 952 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb);
953 953
954 /*Shared IRQ or HW disappared */ 954 /*Shared IRQ or HW disappared */
955 if (!inta || inta == 0xffff) { 955 if (!inta || inta == 0xffff)
956 ret = IRQ_NONE;
957 goto done; 956 goto done;
958 }
959 957
960 /*<1> beacon related */ 958 /*<1> beacon related */
961 if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) { 959 if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {
diff --git a/drivers/net/wireless/rtlwifi/rtl8192c/fw_common.h b/drivers/net/wireless/rtlwifi/rtl8192c/fw_common.h
index 15b2055e6212..695a3bd94636 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192c/fw_common.h
+++ b/drivers/net/wireless/rtlwifi/rtl8192c/fw_common.h
@@ -60,19 +60,6 @@ struct rtl92c_firmware_header {
60 __le32 rsvd5; 60 __le32 rsvd5;
61}; 61};
62 62
63enum rtl8192c_h2c_cmd {
64 H2C_AP_OFFLOAD = 0,
65 H2C_SETPWRMODE = 1,
66 H2C_JOINBSSRPT = 2,
67 H2C_RSVDPAGE = 3,
68 H2C_RSSI_REPORT = 5,
69 H2C_RA_MASK = 6,
70 H2C_MACID_PS_MODE = 7,
71 H2C_P2P_PS_OFFLOAD = 8,
72 H2C_P2P_PS_CTW_CMD = 32,
73 MAX_H2CCMD
74};
75
76#define pagenum_128(_len) (u32)(((_len)>>7) + ((_len)&0x7F ? 1 : 0)) 63#define pagenum_128(_len) (u32)(((_len)>>7) + ((_len)&0x7F ? 1 : 0))
77 64
78#define SET_H2CCMD_PWRMODE_PARM_MODE(__ph2ccmd, __val) \ 65#define SET_H2CCMD_PWRMODE_PARM_MODE(__ph2ccmd, __val) \
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/fw.h b/drivers/net/wireless/rtlwifi/rtl8192de/fw.h
index 1ffacdda734c..a55a803a0b4d 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192de/fw.h
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/fw.h
@@ -132,18 +132,6 @@ struct rtl92d_firmware_header {
132 u32 rsvd5; 132 u32 rsvd5;
133}; 133};
134 134
135enum rtl8192d_h2c_cmd {
136 H2C_AP_OFFLOAD = 0,
137 H2C_SETPWRMODE = 1,
138 H2C_JOINBSSRPT = 2,
139 H2C_RSVDPAGE = 3,
140 H2C_RSSI_REPORT = 5,
141 H2C_RA_MASK = 6,
142 H2C_MAC_MODE_SEL = 9,
143 H2C_PWRM = 15,
144 MAX_H2CCMD
145};
146
147int rtl92d_download_fw(struct ieee80211_hw *hw); 135int rtl92d_download_fw(struct ieee80211_hw *hw);
148void rtl92d_fill_h2c_cmd(struct ieee80211_hw *hw, u8 element_id, 136void rtl92d_fill_h2c_cmd(struct ieee80211_hw *hw, u8 element_id,
149 u32 cmd_len, u8 *p_cmdbuffer); 137 u32 cmd_len, u8 *p_cmdbuffer);
diff --git a/drivers/net/wireless/rtlwifi/rtl8192se/fw.h b/drivers/net/wireless/rtlwifi/rtl8192se/fw.h
index d53f4332464d..b1e44b86e8ed 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192se/fw.h
+++ b/drivers/net/wireless/rtlwifi/rtl8192se/fw.h
@@ -336,7 +336,6 @@ enum fw_h2c_cmd {
336 H2C_TMP3, 336 H2C_TMP3,
337 H2C_WOWLAN_UPDATE_IV_CMD, /*50*/ 337 H2C_WOWLAN_UPDATE_IV_CMD, /*50*/
338 H2C_TMP4, 338 H2C_TMP4,
339 MAX_H2CCMD /*52*/
340}; 339};
341 340
342/* The following macros are used for FW 341/* The following macros are used for FW
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/btc.h b/drivers/net/wireless/rtlwifi/rtl8723ae/btc.h
index 417afeed36af..06c448c010fd 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/btc.h
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/btc.h
@@ -11,10 +11,6 @@
11 ** FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 ** FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 ** more details. 12 ** more details.
13 ** 13 **
14 ** You should have received a copy of the GNU General Public License along with
15 ** this program; if not, write to the Free Software Foundation, Inc.,
16 ** 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 **
18 ** The full GNU General Public License is included in this distribution in the 14 ** The full GNU General Public License is included in this distribution in the
19 ** file called LICENSE. 15 ** file called LICENSE.
20 ** 16 **
@@ -24,8 +20,7 @@
24 ** Hsinchu 300, Taiwan. 20 ** Hsinchu 300, Taiwan.
25 ** Larry Finger <Larry.Finger@lwfinger.net> 21 ** Larry Finger <Larry.Finger@lwfinger.net>
26 ** 22 **
27 ***************************************************************************** 23 ******************************************************************************/
28 */
29 24
30#ifndef __RTL8723E_BTC_H__ 25#ifndef __RTL8723E_BTC_H__
31#define __RTL8723E_BTC_H__ 26#define __RTL8723E_BTC_H__
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/def.h b/drivers/net/wireless/rtlwifi/rtl8723ae/def.h
index debe261a7eeb..94bdd4bbca5d 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/def.h
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/def.h
@@ -11,10 +11,6 @@
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details. 12 * more details.
13 * 13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the 14 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE. 15 * file called LICENSE.
20 * 16 *
@@ -25,55 +21,145 @@
25 * 21 *
26 * Larry Finger <Larry.Finger@lwfinger.net> 22 * Larry Finger <Larry.Finger@lwfinger.net>
27 * 23 *
28 **************************************************************************** 24 *****************************************************************************/
29 */
30 25
31#ifndef __RTL8723E_DEF_H__ 26#ifndef __RTL8723E_DEF_H__
32#define __RTL8723E_DEF_H__ 27#define __RTL8723E_DEF_H__
33 28
29#define HAL_RETRY_LIMIT_INFRA 48
30#define HAL_RETRY_LIMIT_AP_ADHOC 7
31
32#define RESET_DELAY_8185 20
33
34#define RT_IBSS_INT_MASKS (IMR_BCNINT | IMR_TBDOK | IMR_TBDER)
35#define RT_AC_INT_MASKS (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
36
37#define NUM_OF_FIRMWARE_QUEUE 10
38#define NUM_OF_PAGES_IN_FW 0x100
39#define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x07
40#define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x07
41#define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x07
42#define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x07
43#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0x0
44#define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x0
45#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x02
46#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0x02
47#define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x2
48#define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0xA1
49
50#define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM 0x026
51#define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM 0x048
52#define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM 0x048
53#define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM 0x026
54#define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM 0x00
55
56#define MAX_LINES_HWCONFIG_TXT 1000
57#define MAX_BYTES_LINE_HWCONFIG_TXT 256
58
59#define SW_THREE_WIRE 0
60#define HW_THREE_WIRE 2
61
62#define BT_DEMO_BOARD 0
63#define BT_QA_BOARD 1
64#define BT_FPGA 2
65
66#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
34#define HAL_PRIME_CHNL_OFFSET_LOWER 1 67#define HAL_PRIME_CHNL_OFFSET_LOWER 1
68#define HAL_PRIME_CHNL_OFFSET_UPPER 2
35 69
36#define RX_MPDU_QUEUE 0 70#define MAX_H2C_QUEUE_NUM 10
37 71
38#define CHIP_8723 BIT(0) 72#define RX_MPDU_QUEUE 0
39#define NORMAL_CHIP BIT(3) 73#define RX_CMD_QUEUE 1
40#define RF_TYPE_1T2R BIT(4) 74#define RX_MAX_QUEUE 2
41#define RF_TYPE_2T2R BIT(5) 75#define AC2QUEUEID(_AC) (_AC)
42#define CHIP_VENDOR_UMC BIT(7)
43#define B_CUT_VERSION BIT(12)
44#define C_CUT_VERSION BIT(13)
45#define D_CUT_VERSION ((BIT(12)|BIT(13)))
46#define E_CUT_VERSION BIT(14)
47#define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28))
48 76
77#define C2H_RX_CMD_HDR_LEN 8
78#define GET_C2H_CMD_CMD_LEN(__prxhdr) \
79 LE_BITS_TO_4BYTE((__prxhdr), 0, 16)
80#define GET_C2H_CMD_ELEMENT_ID(__prxhdr) \
81 LE_BITS_TO_4BYTE((__prxhdr), 16, 8)
82#define GET_C2H_CMD_CMD_SEQ(__prxhdr) \
83 LE_BITS_TO_4BYTE((__prxhdr), 24, 7)
84#define GET_C2H_CMD_CONTINUE(__prxhdr) \
85 LE_BITS_TO_4BYTE((__prxhdr), 31, 1)
86#define GET_C2H_CMD_CONTENT(__prxhdr) \
87 ((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN)
88
89#define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr) \
90 LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8)
91#define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr) \
92 LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8)
93#define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr) \
94 LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16)
95#define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr) \
96 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5)
97#define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr) \
98 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1)
99#define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr) \
100 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5)
101#define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr) \
102 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1)
103#define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr) \
104 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4)
105#define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr) \
106 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)
107
108#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
109#define CHIP_BONDING_92C_1T2R 0x1
110
111#define CHIP_8723 BIT(0)
112#define NORMAL_CHIP BIT(3)
113#define RF_TYPE_1T1R (~(BIT(4)|BIT(5)|BIT(6)))
114#define RF_TYPE_1T2R BIT(4)
115#define RF_TYPE_2T2R BIT(5)
116#define CHIP_VENDOR_UMC BIT(7)
117#define B_CUT_VERSION BIT(12)
118#define C_CUT_VERSION BIT(13)
119#define D_CUT_VERSION ((BIT(12)|BIT(13)))
120#define E_CUT_VERSION BIT(14)
121#define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28))
49 122
50/* MASK */ 123/* MASK */
51#define IC_TYPE_MASK (BIT(0)|BIT(1)|BIT(2)) 124#define IC_TYPE_MASK (BIT(0)|BIT(1)|BIT(2))
52#define CHIP_TYPE_MASK BIT(3) 125#define CHIP_TYPE_MASK BIT(3)
53#define RF_TYPE_MASK (BIT(4)|BIT(5)|BIT(6)) 126#define RF_TYPE_MASK (BIT(4)|BIT(5)|BIT(6))
54#define MANUFACTUER_MASK BIT(7) 127#define MANUFACTUER_MASK BIT(7)
55#define ROM_VERSION_MASK (BIT(11)|BIT(10)|BIT(9)|BIT(8)) 128#define ROM_VERSION_MASK (BIT(11)|BIT(10)|BIT(9)|BIT(8))
56#define CUT_VERSION_MASK (BIT(15)|BIT(14)|BIT(13)|BIT(12)) 129#define CUT_VERSION_MASK (BIT(15)|BIT(14)|BIT(13)|BIT(12))
57 130
58/* Get element */ 131/* Get element */
59#define GET_CVID_IC_TYPE(version) ((version) & IC_TYPE_MASK) 132#define GET_CVID_IC_TYPE(version) ((version) & IC_TYPE_MASK)
133#define GET_CVID_CHIP_TYPE(version) ((version) & CHIP_TYPE_MASK)
134#define GET_CVID_RF_TYPE(version) ((version) & RF_TYPE_MASK)
60#define GET_CVID_MANUFACTUER(version) ((version) & MANUFACTUER_MASK) 135#define GET_CVID_MANUFACTUER(version) ((version) & MANUFACTUER_MASK)
136#define GET_CVID_ROM_VERSION(version) ((version) & ROM_VERSION_MASK)
61#define GET_CVID_CUT_VERSION(version) ((version) & CUT_VERSION_MASK) 137#define GET_CVID_CUT_VERSION(version) ((version) & CUT_VERSION_MASK)
62 138
63#define IS_81XXC(version) ((GET_CVID_IC_TYPE(version) == 0) ?\ 139#define IS_81XXC(version) ((GET_CVID_IC_TYPE(version) == 0) ?\
64 true : false) 140 true : false)
65#define IS_8723_SERIES(version) \ 141#define IS_8723_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723) ? \
66 ((GET_CVID_IC_TYPE(version) == CHIP_8723) ? true : false) 142 true : false)
67#define IS_CHIP_VENDOR_UMC(version) \ 143#define IS_1T1R(version) ((GET_CVID_RF_TYPE(version)) ? false : true)
68 ((GET_CVID_MANUFACTUER(version)) ? true : false) 144#define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R)\
69 145 ? true : false)
70#define IS_VENDOR_UMC_A_CUT(version) ((IS_CHIP_VENDOR_UMC(version)) ? \ 146#define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R)\
71 ((GET_CVID_CUT_VERSION(version)) ? false : true) : false) 147 ? true : false)
72#define IS_VENDOR_8723_A_CUT(version) ((IS_8723_SERIES(version)) ? \ 148#define IS_CHIP_VENDOR_UMC(version) ((GET_CVID_MANUFACTUER(version)) ? \
73 ((GET_CVID_CUT_VERSION(version)) ? false : true) : false) 149 true : false)
74#define IS_81xxC_VENDOR_UMC_B_CUT(version) ((IS_CHIP_VENDOR_UMC(version)) \ 150
75 ? ((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? \ 151#define IS_VENDOR_UMC_A_CUT(version) ((IS_CHIP_VENDOR_UMC(version))\
76 true : false) : false) 152 ? ((GET_CVID_CUT_VERSION(version)) ? \
153 false : true) : false)
154#define IS_VENDOR_8723_A_CUT(version) ((IS_8723_SERIES(version))\
155 ? ((GET_CVID_CUT_VERSION(version)) ? \
156 false : true) : false)
157#define IS_VENDOR_8723A_B_CUT(version) ((IS_8723_SERIES(version))\
158 ? ((GET_CVID_CUT_VERSION(version) == \
159 B_CUT_VERSION) ? true : false) : false)
160#define IS_81xxC_VENDOR_UMC_B_CUT(version) ((IS_CHIP_VENDOR_UMC(version))\
161 ? ((GET_CVID_CUT_VERSION(version) == \
162 B_CUT_VERSION) ? true : false) : false)
77 163
78enum rf_optype { 164enum rf_optype {
79 RF_OP_BY_SW_3WIRE = 0, 165 RF_OP_BY_SW_3WIRE = 0,
@@ -93,7 +179,7 @@ enum power_save_mode {
93 POWER_SAVE_MODE_SAVE, 179 POWER_SAVE_MODE_SAVE,
94}; 180};
95 181
96enum power_polocy_config { 182enum power_policy_config {
97 POWERCFG_MAX_POWER_SAVINGS, 183 POWERCFG_MAX_POWER_SAVINGS,
98 POWERCFG_GLOBAL_POWER_SAVINGS, 184 POWERCFG_GLOBAL_POWER_SAVINGS,
99 POWERCFG_LOCAL_POWER_SAVINGS, 185 POWERCFG_LOCAL_POWER_SAVINGS,
@@ -143,6 +229,41 @@ enum rtl_desc_qsel {
143 QSLT_CMD = 0x13, 229 QSLT_CMD = 0x13,
144}; 230};
145 231
232enum rtl_desc8723e_rate {
233 DESC92C_RATE1M = 0x00,
234 DESC92C_RATE2M = 0x01,
235 DESC92C_RATE5_5M = 0x02,
236 DESC92C_RATE11M = 0x03,
237
238 DESC92C_RATE6M = 0x04,
239 DESC92C_RATE9M = 0x05,
240 DESC92C_RATE12M = 0x06,
241 DESC92C_RATE18M = 0x07,
242 DESC92C_RATE24M = 0x08,
243 DESC92C_RATE36M = 0x09,
244 DESC92C_RATE48M = 0x0a,
245 DESC92C_RATE54M = 0x0b,
246
247 DESC92C_RATEMCS0 = 0x0c,
248 DESC92C_RATEMCS1 = 0x0d,
249 DESC92C_RATEMCS2 = 0x0e,
250 DESC92C_RATEMCS3 = 0x0f,
251 DESC92C_RATEMCS4 = 0x10,
252 DESC92C_RATEMCS5 = 0x11,
253 DESC92C_RATEMCS6 = 0x12,
254 DESC92C_RATEMCS7 = 0x13,
255 DESC92C_RATEMCS8 = 0x14,
256 DESC92C_RATEMCS9 = 0x15,
257 DESC92C_RATEMCS10 = 0x16,
258 DESC92C_RATEMCS11 = 0x17,
259 DESC92C_RATEMCS12 = 0x18,
260 DESC92C_RATEMCS13 = 0x19,
261 DESC92C_RATEMCS14 = 0x1a,
262 DESC92C_RATEMCS15 = 0x1b,
263 DESC92C_RATEMCS15_SG = 0x1c,
264 DESC92C_RATEMCS32 = 0x20,
265};
266
146struct phy_sts_cck_8723e_t { 267struct phy_sts_cck_8723e_t {
147 u8 adc_pwdb_X[4]; 268 u8 adc_pwdb_X[4];
148 u8 sq_rpt; 269 u8 sq_rpt;
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/dm.c b/drivers/net/wireless/rtlwifi/rtl8723ae/dm.c
index 25cc83058b01..a0e86922780a 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/dm.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/dm.c
@@ -11,10 +11,6 @@
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details. 12 * more details.
13 * 13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the 14 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE. 15 * file called LICENSE.
20 * 16 *
@@ -25,8 +21,7 @@
25 * 21 *
26 * Larry Finger <Larry.Finger@lwfinger.net> 22 * Larry Finger <Larry.Finger@lwfinger.net>
27 * 23 *
28 **************************************************************************** 24 *****************************************************************************/
29 */
30 25
31#include "../wifi.h" 26#include "../wifi.h"
32#include "../base.h" 27#include "../base.h"
@@ -151,7 +146,7 @@ static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = {
151 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} 146 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}
152}; 147};
153 148
154static void rtl8723ae_dm_diginit(struct ieee80211_hw *hw) 149static void rtl8723e_dm_diginit(struct ieee80211_hw *hw)
155{ 150{
156 struct rtl_priv *rtlpriv = rtl_priv(hw); 151 struct rtl_priv *rtlpriv = rtl_priv(hw);
157 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 152 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
@@ -176,7 +171,7 @@ static void rtl8723ae_dm_diginit(struct ieee80211_hw *hw)
176 dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_MAX; 171 dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_MAX;
177} 172}
178 173
179static u8 rtl_init_gain_min_pwdb(struct ieee80211_hw *hw) 174static u8 rtl8723e_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw)
180{ 175{
181 struct rtl_priv *rtlpriv = rtl_priv(hw); 176 struct rtl_priv *rtlpriv = rtl_priv(hw);
182 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 177 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
@@ -195,14 +190,15 @@ static u8 rtl_init_gain_min_pwdb(struct ieee80211_hw *hw)
195 } else if (dm_digtable->cursta_cstate == DIG_STA_CONNECT || 190 } else if (dm_digtable->cursta_cstate == DIG_STA_CONNECT ||
196 dm_digtable->cursta_cstate == DIG_STA_BEFORE_CONNECT) { 191 dm_digtable->cursta_cstate == DIG_STA_BEFORE_CONNECT) {
197 rssi_val_min = rtlpriv->dm.undec_sm_pwdb; 192 rssi_val_min = rtlpriv->dm.undec_sm_pwdb;
198 } else if (dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) { 193 } else if (dm_digtable->curmultista_cstate ==
194 DIG_MULTISTA_CONNECT) {
199 rssi_val_min = rtlpriv->dm.entry_min_undec_sm_pwdb; 195 rssi_val_min = rtlpriv->dm.entry_min_undec_sm_pwdb;
200 } 196 }
201 197
202 return (u8) rssi_val_min; 198 return (u8) rssi_val_min;
203} 199}
204 200
205static void rtl8723ae_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw) 201static void rtl8723e_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
206{ 202{
207 u32 ret_value; 203 u32 ret_value;
208 struct rtl_priv *rtlpriv = rtl_priv(hw); 204 struct rtl_priv *rtlpriv = rtl_priv(hw);
@@ -239,8 +235,7 @@ static void rtl8723ae_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
239 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2); 235 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2);
240 236
241 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, 237 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
242 "cnt_parity_fail = %d, cnt_rate_illegal = %d, " 238 "cnt_parity_fail = %d, cnt_rate_illegal = %d, cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
243 "cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
244 falsealm_cnt->cnt_parity_fail, 239 falsealm_cnt->cnt_parity_fail,
245 falsealm_cnt->cnt_rate_illegal, 240 falsealm_cnt->cnt_rate_illegal,
246 falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail); 241 falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail);
@@ -263,52 +258,60 @@ static void rtl92c_dm_ctrl_initgain_by_fa(struct ieee80211_hw *hw)
263 value_igi += 0; 258 value_igi += 0;
264 else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH2) 259 else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH2)
265 value_igi++; 260 value_igi++;
266 else 261 else if (rtlpriv->falsealm_cnt.cnt_all >= DM_DIG_FA_TH2)
267 value_igi += 2; 262 value_igi += 2;
268 263 if (value_igi > DM_DIG_FA_UPPER)
269 value_igi = clamp(value_igi, (u8)DM_DIG_FA_LOWER, (u8)DM_DIG_FA_UPPER); 264 value_igi = DM_DIG_FA_UPPER;
265 else if (value_igi < DM_DIG_FA_LOWER)
266 value_igi = DM_DIG_FA_LOWER;
270 if (rtlpriv->falsealm_cnt.cnt_all > 10000) 267 if (rtlpriv->falsealm_cnt.cnt_all > 10000)
271 value_igi = 0x32; 268 value_igi = 0x32;
272 269
273 dm_digtable->cur_igvalue = value_igi; 270 dm_digtable->cur_igvalue = value_igi;
274 rtl8723ae_dm_write_dig(hw); 271 rtl8723e_dm_write_dig(hw);
275} 272}
276 273
277static void rtl92c_dm_ctrl_initgain_by_rssi(struct ieee80211_hw *hw) 274static void rtl92c_dm_ctrl_initgain_by_rssi(struct ieee80211_hw *hw)
278{ 275{
279 struct rtl_priv *rtlpriv = rtl_priv(hw); 276 struct rtl_priv *rtlpriv = rtl_priv(hw);
280 struct dig_t *dgtbl = &rtlpriv->dm_digtable; 277 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
281 278
282 if (rtlpriv->falsealm_cnt.cnt_all > dgtbl->fa_highthresh) { 279 if (rtlpriv->falsealm_cnt.cnt_all > dm_digtable->fa_highthresh) {
283 if ((dgtbl->back_val - 2) < dgtbl->back_range_min) 280 if ((dm_digtable->back_val - 2) <
284 dgtbl->back_val = dgtbl->back_range_min; 281 dm_digtable->back_range_min)
282 dm_digtable->back_val =
283 dm_digtable->back_range_min;
285 else 284 else
286 dgtbl->back_val -= 2; 285 dm_digtable->back_val -= 2;
287 } else if (rtlpriv->falsealm_cnt.cnt_all < dgtbl->fa_lowthresh) { 286 } else if (rtlpriv->falsealm_cnt.cnt_all < dm_digtable->fa_lowthresh) {
288 if ((dgtbl->back_val + 2) > dgtbl->back_range_max) 287 if ((dm_digtable->back_val + 2) >
289 dgtbl->back_val = dgtbl->back_range_max; 288 dm_digtable->back_range_max)
289 dm_digtable->back_val =
290 dm_digtable->back_range_max;
290 else 291 else
291 dgtbl->back_val += 2; 292 dm_digtable->back_val += 2;
292 } 293 }
293 294
294 if ((dgtbl->rssi_val_min + 10 - dgtbl->back_val) > 295 if ((dm_digtable->rssi_val_min + 10 - dm_digtable->back_val) >
295 dgtbl->rx_gain_max) 296 dm_digtable->rx_gain_max)
296 dgtbl->cur_igvalue = dgtbl->rx_gain_max; 297 dm_digtable->cur_igvalue = dm_digtable->rx_gain_max;
297 else if ((dgtbl->rssi_val_min + 10 - 298 else if ((dm_digtable->rssi_val_min + 10 -
298 dgtbl->back_val) < dgtbl->rx_gain_min) 299 dm_digtable->back_val) < dm_digtable->rx_gain_min)
299 dgtbl->cur_igvalue = dgtbl->rx_gain_min; 300 dm_digtable->cur_igvalue = dm_digtable->rx_gain_min;
300 else 301 else
301 dgtbl->cur_igvalue = dgtbl->rssi_val_min + 10 - dgtbl->back_val; 302 dm_digtable->cur_igvalue = dm_digtable->rssi_val_min + 10 -
303 dm_digtable->back_val;
302 304
303 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, 305 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
304 "rssi_val_min = %x back_val %x\n", 306 "rssi_val_min = %x back_val %x\n",
305 dgtbl->rssi_val_min, dgtbl->back_val); 307 dm_digtable->rssi_val_min, dm_digtable->back_val);
306 308
307 rtl8723ae_dm_write_dig(hw); 309 rtl8723e_dm_write_dig(hw);
308} 310}
309 311
310static void rtl8723ae_dm_initial_gain_multi_sta(struct ieee80211_hw *hw) 312static void rtl8723e_dm_initial_gain_multi_sta(struct ieee80211_hw *hw)
311{ 313{
314 static u8 binitialized;
312 struct rtl_priv *rtlpriv = rtl_priv(hw); 315 struct rtl_priv *rtlpriv = rtl_priv(hw);
313 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 316 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
314 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 317 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
@@ -318,16 +321,15 @@ static void rtl8723ae_dm_initial_gain_multi_sta(struct ieee80211_hw *hw)
318 if (mac->opmode == NL80211_IFTYPE_ADHOC) 321 if (mac->opmode == NL80211_IFTYPE_ADHOC)
319 multi_sta = true; 322 multi_sta = true;
320 323
321 if ((!multi_sta) || 324 if (!multi_sta || (dm_digtable->cursta_cstate != DIG_STA_DISCONNECT)) {
322 (dm_digtable->cursta_cstate != DIG_STA_DISCONNECT)) { 325 binitialized = false;
323 rtlpriv->initialized = false;
324 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX; 326 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
325 return; 327 return;
326 } else if (!rtlpriv->initialized) { 328 } else if (!binitialized) {
327 rtlpriv->initialized = true; 329 binitialized = true;
328 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_0; 330 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
329 dm_digtable->cur_igvalue = 0x20; 331 dm_digtable->cur_igvalue = 0x20;
330 rtl8723ae_dm_write_dig(hw); 332 rtl8723e_dm_write_dig(hw);
331 } 333 }
332 334
333 if (dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) { 335 if (dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) {
@@ -337,7 +339,7 @@ static void rtl8723ae_dm_initial_gain_multi_sta(struct ieee80211_hw *hw)
337 if (dm_digtable->dig_ext_port_stage == 339 if (dm_digtable->dig_ext_port_stage ==
338 DIG_EXT_PORT_STAGE_2) { 340 DIG_EXT_PORT_STAGE_2) {
339 dm_digtable->cur_igvalue = 0x20; 341 dm_digtable->cur_igvalue = 0x20;
340 rtl8723ae_dm_write_dig(hw); 342 rtl8723e_dm_write_dig(hw);
341 } 343 }
342 344
343 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_1; 345 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_1;
@@ -348,7 +350,7 @@ static void rtl8723ae_dm_initial_gain_multi_sta(struct ieee80211_hw *hw)
348 } else if (dm_digtable->dig_ext_port_stage != DIG_EXT_PORT_STAGE_0) { 350 } else if (dm_digtable->dig_ext_port_stage != DIG_EXT_PORT_STAGE_0) {
349 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_0; 351 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
350 dm_digtable->cur_igvalue = 0x20; 352 dm_digtable->cur_igvalue = 0x20;
351 rtl8723ae_dm_write_dig(hw); 353 rtl8723e_dm_write_dig(hw);
352 } 354 }
353 355
354 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, 356 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
@@ -357,22 +359,22 @@ static void rtl8723ae_dm_initial_gain_multi_sta(struct ieee80211_hw *hw)
357 dm_digtable->dig_ext_port_stage); 359 dm_digtable->dig_ext_port_stage);
358} 360}
359 361
360static void rtl8723ae_dm_initial_gain_sta(struct ieee80211_hw *hw) 362static void rtl8723e_dm_initial_gain_sta(struct ieee80211_hw *hw)
361{ 363{
362 struct rtl_priv *rtlpriv = rtl_priv(hw); 364 struct rtl_priv *rtlpriv = rtl_priv(hw);
363 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 365 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
364 366
365 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, 367 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
366 "presta_cstate = %x, cursta_cstate = %x\n", 368 "presta_cstate = %x, cursta_cstate = %x\n",
367 dm_digtable->presta_cstate, 369 dm_digtable->presta_cstate,
368 dm_digtable->cursta_cstate); 370 dm_digtable->cursta_cstate);
369 371
370 if (dm_digtable->presta_cstate == dm_digtable->cursta_cstate || 372 if (dm_digtable->presta_cstate == dm_digtable->cursta_cstate ||
371 dm_digtable->cursta_cstate == DIG_STA_BEFORE_CONNECT || 373 dm_digtable->cursta_cstate == DIG_STA_BEFORE_CONNECT ||
372 dm_digtable->cursta_cstate == DIG_STA_CONNECT) { 374 dm_digtable->cursta_cstate == DIG_STA_CONNECT) {
373
374 if (dm_digtable->cursta_cstate != DIG_STA_DISCONNECT) { 375 if (dm_digtable->cursta_cstate != DIG_STA_DISCONNECT) {
375 dm_digtable->rssi_val_min = rtl_init_gain_min_pwdb(hw); 376 dm_digtable->rssi_val_min =
377 rtl8723e_dm_initial_gain_min_pwdb(hw);
376 rtl92c_dm_ctrl_initgain_by_rssi(hw); 378 rtl92c_dm_ctrl_initgain_by_rssi(hw);
377 } 379 }
378 } else { 380 } else {
@@ -381,16 +383,17 @@ static void rtl8723ae_dm_initial_gain_sta(struct ieee80211_hw *hw)
381 dm_digtable->back_val = DM_DIG_BACKOFF_DEFAULT; 383 dm_digtable->back_val = DM_DIG_BACKOFF_DEFAULT;
382 dm_digtable->cur_igvalue = 0x20; 384 dm_digtable->cur_igvalue = 0x20;
383 dm_digtable->pre_igvalue = 0; 385 dm_digtable->pre_igvalue = 0;
384 rtl8723ae_dm_write_dig(hw); 386 rtl8723e_dm_write_dig(hw);
385 } 387 }
386} 388}
387static void rtl8723ae_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw) 389
390static void rtl8723e_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
388{ 391{
389 struct rtl_priv *rtlpriv = rtl_priv(hw); 392 struct rtl_priv *rtlpriv = rtl_priv(hw);
390 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 393 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
391 394
392 if (dm_digtable->cursta_cstate == DIG_STA_CONNECT) { 395 if (dm_digtable->cursta_cstate == DIG_STA_CONNECT) {
393 dm_digtable->rssi_val_min = rtl_init_gain_min_pwdb(hw); 396 dm_digtable->rssi_val_min = rtl8723e_dm_initial_gain_min_pwdb(hw);
394 397
395 if (dm_digtable->pre_cck_pd_state == CCK_PD_STAGE_LowRssi) { 398 if (dm_digtable->pre_cck_pd_state == CCK_PD_STAGE_LowRssi) {
396 if (dm_digtable->rssi_val_min <= 25) 399 if (dm_digtable->rssi_val_min <= 25)
@@ -418,12 +421,11 @@ static void rtl8723ae_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
418 CCK_FA_STAGE_High; 421 CCK_FA_STAGE_High;
419 else 422 else
420 dm_digtable->cur_cck_fa_state = 423 dm_digtable->cur_cck_fa_state =
421 CCK_FA_STAGE_Low; 424 CCK_FA_STAGE_LOW;
422
423 if (dm_digtable->pre_cck_fa_state != 425 if (dm_digtable->pre_cck_fa_state !=
424 dm_digtable->cur_cck_fa_state) { 426 dm_digtable->cur_cck_fa_state) {
425 if (dm_digtable->cur_cck_fa_state == 427 if (dm_digtable->cur_cck_fa_state ==
426 CCK_FA_STAGE_Low) 428 CCK_FA_STAGE_LOW)
427 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 429 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
428 0x83); 430 0x83);
429 else 431 else
@@ -449,13 +451,13 @@ static void rtl8723ae_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
449 451
450} 452}
451 453
452static void rtl8723ae_dm_ctrl_initgain_by_twoport(struct ieee80211_hw *hw) 454static void rtl8723e_dm_ctrl_initgain_by_twoport(struct ieee80211_hw *hw)
453{ 455{
454 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 456 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
455 struct rtl_priv *rtlpriv = rtl_priv(hw); 457 struct rtl_priv *rtlpriv = rtl_priv(hw);
456 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 458 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
457 459
458 if (mac->act_scanning == true) 460 if (mac->act_scanning)
459 return; 461 return;
460 462
461 if (mac->link_state >= MAC80211_LINKED) 463 if (mac->link_state >= MAC80211_LINKED)
@@ -463,28 +465,29 @@ static void rtl8723ae_dm_ctrl_initgain_by_twoport(struct ieee80211_hw *hw)
463 else 465 else
464 dm_digtable->cursta_cstate = DIG_STA_DISCONNECT; 466 dm_digtable->cursta_cstate = DIG_STA_DISCONNECT;
465 467
466 rtl8723ae_dm_initial_gain_sta(hw); 468 rtl8723e_dm_initial_gain_sta(hw);
467 rtl8723ae_dm_initial_gain_multi_sta(hw); 469 rtl8723e_dm_initial_gain_multi_sta(hw);
468 rtl8723ae_dm_cck_packet_detection_thresh(hw); 470 rtl8723e_dm_cck_packet_detection_thresh(hw);
469 471
470 dm_digtable->presta_cstate = dm_digtable->cursta_cstate; 472 dm_digtable->presta_cstate = dm_digtable->cursta_cstate;
471 473
472} 474}
473 475
474static void rtl8723ae_dm_dig(struct ieee80211_hw *hw) 476static void rtl8723e_dm_dig(struct ieee80211_hw *hw)
475{ 477{
476 struct rtl_priv *rtlpriv = rtl_priv(hw); 478 struct rtl_priv *rtlpriv = rtl_priv(hw);
477 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 479 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
478 480
479 if (rtlpriv->dm.dm_initialgain_enable == false) 481 if (!rtlpriv->dm.dm_initialgain_enable)
480 return; 482 return;
481 if (dm_digtable->dig_enable_flag == false) 483 if (!dm_digtable->dig_enable_flag)
482 return; 484 return;
483 485
484 rtl8723ae_dm_ctrl_initgain_by_twoport(hw); 486 rtl8723e_dm_ctrl_initgain_by_twoport(hw);
487
485} 488}
486 489
487static void rtl8723ae_dm_dynamic_txpower(struct ieee80211_hw *hw) 490static void rtl8723e_dm_dynamic_txpower(struct ieee80211_hw *hw)
488{ 491{
489 struct rtl_priv *rtlpriv = rtl_priv(hw); 492 struct rtl_priv *rtlpriv = rtl_priv(hw);
490 struct rtl_phy *rtlphy = &(rtlpriv->phy); 493 struct rtl_phy *rtlphy = &(rtlpriv->phy);
@@ -502,7 +505,7 @@ static void rtl8723ae_dm_dynamic_txpower(struct ieee80211_hw *hw)
502 if ((mac->link_state < MAC80211_LINKED) && 505 if ((mac->link_state < MAC80211_LINKED) &&
503 (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) { 506 (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) {
504 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 507 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
505 "Not connected\n"); 508 "Not connected to any\n");
506 509
507 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL; 510 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
508 511
@@ -512,18 +515,21 @@ static void rtl8723ae_dm_dynamic_txpower(struct ieee80211_hw *hw)
512 515
513 if (mac->link_state >= MAC80211_LINKED) { 516 if (mac->link_state >= MAC80211_LINKED) {
514 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 517 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
515 undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb; 518 undec_sm_pwdb =
519 rtlpriv->dm.entry_min_undec_sm_pwdb;
516 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 520 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
517 "AP Client PWDB = 0x%lx\n", 521 "AP Client PWDB = 0x%lx\n",
518 undec_sm_pwdb); 522 undec_sm_pwdb);
519 } else { 523 } else {
520 undec_sm_pwdb = rtlpriv->dm.undec_sm_pwdb; 524 undec_sm_pwdb =
525 rtlpriv->dm.undec_sm_pwdb;
521 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 526 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
522 "STA Default Port PWDB = 0x%lx\n", 527 "STA Default Port PWDB = 0x%lx\n",
523 undec_sm_pwdb); 528 undec_sm_pwdb);
524 } 529 }
525 } else { 530 } else {
526 undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb; 531 undec_sm_pwdb =
532 rtlpriv->dm.entry_min_undec_sm_pwdb;
527 533
528 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 534 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
529 "AP Ext Port PWDB = 0x%lx\n", 535 "AP Ext Port PWDB = 0x%lx\n",
@@ -534,37 +540,39 @@ static void rtl8723ae_dm_dynamic_txpower(struct ieee80211_hw *hw)
534 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1; 540 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
535 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 541 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
536 "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n"); 542 "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n");
537 } else if ((undec_sm_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) && 543 } else if ((undec_sm_pwdb <
538 (undec_sm_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL1)) { 544 (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) &&
545 (undec_sm_pwdb >=
546 TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
539 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1; 547 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
540 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 548 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
541 "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x10)\n"); 549 "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x10)\n");
542 } else if (undec_sm_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) { 550 } else if (undec_sm_pwdb <
551 (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
543 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL; 552 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
544 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 553 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
545 "TXHIGHPWRLEVEL_NORMAL\n"); 554 "TXHIGHPWRLEVEL_NORMAL\n");
546 } 555 }
547 556
548 if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl)) { 557 if (rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl) {
549 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 558 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
550 "PHY_SetTxPowerLevel8192S() Channel = %d\n", 559 "PHY_SetTxPowerLevel8192S() Channel = %d\n",
551 rtlphy->current_channel); 560 rtlphy->current_channel);
552 rtl8723ae_phy_set_txpower_level(hw, rtlphy->current_channel); 561 rtl8723e_phy_set_txpower_level(hw, rtlphy->current_channel);
553 } 562 }
554 563
555 rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl; 564 rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
556} 565}
557 566
558void rtl8723ae_dm_write_dig(struct ieee80211_hw *hw) 567void rtl8723e_dm_write_dig(struct ieee80211_hw *hw)
559{ 568{
560 struct rtl_priv *rtlpriv = rtl_priv(hw); 569 struct rtl_priv *rtlpriv = rtl_priv(hw);
561 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 570 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
562 571
563 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, 572 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
564 "cur_igvalue = 0x%x, " 573 "cur_igvalue = 0x%x, pre_igvalue = 0x%x, back_val = %d\n",
565 "pre_igvalue = 0x%x, back_val = %d\n", 574 dm_digtable->cur_igvalue, dm_digtable->pre_igvalue,
566 dm_digtable->cur_igvalue, dm_digtable->pre_igvalue, 575 dm_digtable->back_val);
567 dm_digtable->back_val);
568 576
569 if (dm_digtable->pre_igvalue != dm_digtable->cur_igvalue) { 577 if (dm_digtable->pre_igvalue != dm_digtable->cur_igvalue) {
570 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f, 578 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f,
@@ -576,32 +584,39 @@ void rtl8723ae_dm_write_dig(struct ieee80211_hw *hw)
576 } 584 }
577} 585}
578 586
579static void rtl8723ae_dm_check_edca_turbo(struct ieee80211_hw *hw) 587static void rtl8723e_dm_pwdb_monitor(struct ieee80211_hw *hw)
588{
589}
590
591static void rtl8723e_dm_check_edca_turbo(struct ieee80211_hw *hw)
580{ 592{
581 struct rtl_priv *rtlpriv = rtl_priv(hw); 593 struct rtl_priv *rtlpriv = rtl_priv(hw);
582 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
583 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 594 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
584 595
596 static u64 last_txok_cnt;
597 static u64 last_rxok_cnt;
598 static u32 last_bt_edca_ul;
599 static u32 last_bt_edca_dl;
585 u64 cur_txok_cnt = 0; 600 u64 cur_txok_cnt = 0;
586 u64 cur_rxok_cnt = 0; 601 u64 cur_rxok_cnt = 0;
587 u32 edca_be_ul = 0x5ea42b; 602 u32 edca_be_ul = 0x5ea42b;
588 u32 edca_be_dl = 0x5ea42b; 603 u32 edca_be_dl = 0x5ea42b;
589 bool bt_change_edca = false; 604 bool bt_change_edca = false;
590 605
591 if ((mac->last_bt_edca_ul != rtlpcipriv->bt_coexist.bt_edca_ul) || 606 if ((last_bt_edca_ul != rtlpriv->btcoexist.bt_edca_ul) ||
592 (mac->last_bt_edca_dl != rtlpcipriv->bt_coexist.bt_edca_dl)) { 607 (last_bt_edca_dl != rtlpriv->btcoexist.bt_edca_dl)) {
593 rtlpriv->dm.current_turbo_edca = false; 608 rtlpriv->dm.current_turbo_edca = false;
594 mac->last_bt_edca_ul = rtlpcipriv->bt_coexist.bt_edca_ul; 609 last_bt_edca_ul = rtlpriv->btcoexist.bt_edca_ul;
595 mac->last_bt_edca_dl = rtlpcipriv->bt_coexist.bt_edca_dl; 610 last_bt_edca_dl = rtlpriv->btcoexist.bt_edca_dl;
596 } 611 }
597 612
598 if (rtlpcipriv->bt_coexist.bt_edca_ul != 0) { 613 if (rtlpriv->btcoexist.bt_edca_ul != 0) {
599 edca_be_ul = rtlpcipriv->bt_coexist.bt_edca_ul; 614 edca_be_ul = rtlpriv->btcoexist.bt_edca_ul;
600 bt_change_edca = true; 615 bt_change_edca = true;
601 } 616 }
602 617
603 if (rtlpcipriv->bt_coexist.bt_edca_dl != 0) { 618 if (rtlpriv->btcoexist.bt_edca_dl != 0) {
604 edca_be_ul = rtlpcipriv->bt_coexist.bt_edca_dl; 619 edca_be_ul = rtlpriv->btcoexist.bt_edca_dl;
605 bt_change_edca = true; 620 bt_change_edca = true;
606 } 621 }
607 622
@@ -609,22 +624,11 @@ static void rtl8723ae_dm_check_edca_turbo(struct ieee80211_hw *hw)
609 rtlpriv->dm.current_turbo_edca = false; 624 rtlpriv->dm.current_turbo_edca = false;
610 return; 625 return;
611 } 626 }
612
613 if ((!mac->ht_enable) && (!rtlpcipriv->bt_coexist.bt_coexistence)) {
614 if (!(edca_be_ul & 0xffff0000))
615 edca_be_ul |= 0x005e0000;
616
617 if (!(edca_be_dl & 0xffff0000))
618 edca_be_dl |= 0x005e0000;
619 }
620
621 if ((bt_change_edca) || ((!rtlpriv->dm.is_any_nonbepkts) && 627 if ((bt_change_edca) || ((!rtlpriv->dm.is_any_nonbepkts) &&
622 (!rtlpriv->dm.disable_framebursting))) { 628 (!rtlpriv->dm.disable_framebursting))) {
623 629
624 cur_txok_cnt = rtlpriv->stats.txbytesunicast - 630 cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
625 mac->last_txok_cnt; 631 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
626 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast -
627 mac->last_rxok_cnt;
628 632
629 if (cur_rxok_cnt > 4 * cur_txok_cnt) { 633 if (cur_rxok_cnt > 4 * cur_txok_cnt) {
630 if (!rtlpriv->dm.is_cur_rdlstate || 634 if (!rtlpriv->dm.is_cur_rdlstate ||
@@ -647,18 +651,20 @@ static void rtl8723ae_dm_check_edca_turbo(struct ieee80211_hw *hw)
647 } else { 651 } else {
648 if (rtlpriv->dm.current_turbo_edca) { 652 if (rtlpriv->dm.current_turbo_edca) {
649 u8 tmp = AC0_BE; 653 u8 tmp = AC0_BE;
650 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM, 654 rtlpriv->cfg->ops->set_hw_reg(hw,
651 &tmp); 655 HW_VAR_AC_PARAM,
656 (u8 *)(&tmp));
652 rtlpriv->dm.current_turbo_edca = false; 657 rtlpriv->dm.current_turbo_edca = false;
653 } 658 }
654 } 659 }
655 660
656 rtlpriv->dm.is_any_nonbepkts = false; 661 rtlpriv->dm.is_any_nonbepkts = false;
657 mac->last_txok_cnt = rtlpriv->stats.txbytesunicast; 662 last_txok_cnt = rtlpriv->stats.txbytesunicast;
658 mac->last_rxok_cnt = rtlpriv->stats.rxbytesunicast; 663 last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
659} 664}
660 665
661static void rtl8723ae_dm_initialize_txpower_tracking(struct ieee80211_hw *hw) 666static void rtl8723e_dm_initialize_txpower_tracking_thermalmeter(
667 struct ieee80211_hw *hw)
662{ 668{
663 struct rtl_priv *rtlpriv = rtl_priv(hw); 669 struct rtl_priv *rtlpriv = rtl_priv(hw);
664 670
@@ -667,10 +673,20 @@ static void rtl8723ae_dm_initialize_txpower_tracking(struct ieee80211_hw *hw)
667 673
668 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 674 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
669 "pMgntInfo->txpower_tracking = %d\n", 675 "pMgntInfo->txpower_tracking = %d\n",
670 rtlpriv->dm.txpower_tracking); 676 rtlpriv->dm.txpower_tracking);
671} 677}
672 678
673void rtl8723ae_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw) 679static void rtl8723e_dm_initialize_txpower_tracking(struct ieee80211_hw *hw)
680{
681 rtl8723e_dm_initialize_txpower_tracking_thermalmeter(hw);
682}
683
684void rtl8723e_dm_check_txpower_tracking(struct ieee80211_hw *hw)
685{
686 return;
687}
688
689void rtl8723e_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
674{ 690{
675 struct rtl_priv *rtlpriv = rtl_priv(hw); 691 struct rtl_priv *rtlpriv = rtl_priv(hw);
676 struct rate_adaptive *p_ra = &(rtlpriv->ra); 692 struct rate_adaptive *p_ra = &(rtlpriv->ra);
@@ -682,101 +698,32 @@ void rtl8723ae_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
682 rtlpriv->dm.useramask = true; 698 rtlpriv->dm.useramask = true;
683 else 699 else
684 rtlpriv->dm.useramask = false; 700 rtlpriv->dm.useramask = false;
685}
686 701
687static void rtl8723ae_dm_refresh_rate_adaptive_mask(struct ieee80211_hw *hw)
688{
689 struct rtl_priv *rtlpriv = rtl_priv(hw);
690 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
691 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
692 struct rate_adaptive *p_ra = &(rtlpriv->ra);
693 u32 low_rssithresh_for_ra, high_rssithresh_for_ra;
694 struct ieee80211_sta *sta = NULL;
695
696 if (is_hal_stop(rtlhal)) {
697 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
698 " driver is going to unload\n");
699 return;
700 }
701
702 if (!rtlpriv->dm.useramask) {
703 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
704 " driver does not control rate adaptive mask\n");
705 return;
706 }
707
708 if (mac->link_state == MAC80211_LINKED &&
709 mac->opmode == NL80211_IFTYPE_STATION) {
710 switch (p_ra->pre_ratr_state) {
711 case DM_RATR_STA_HIGH:
712 high_rssithresh_for_ra = 50;
713 low_rssithresh_for_ra = 20;
714 break;
715 case DM_RATR_STA_MIDDLE:
716 high_rssithresh_for_ra = 55;
717 low_rssithresh_for_ra = 20;
718 break;
719 case DM_RATR_STA_LOW:
720 high_rssithresh_for_ra = 50;
721 low_rssithresh_for_ra = 25;
722 break;
723 default:
724 high_rssithresh_for_ra = 50;
725 low_rssithresh_for_ra = 20;
726 break;
727 }
728
729 if (rtlpriv->dm.undec_sm_pwdb > high_rssithresh_for_ra)
730 p_ra->ratr_state = DM_RATR_STA_HIGH;
731 else if (rtlpriv->dm.undec_sm_pwdb > low_rssithresh_for_ra)
732 p_ra->ratr_state = DM_RATR_STA_MIDDLE;
733 else
734 p_ra->ratr_state = DM_RATR_STA_LOW;
735
736 if (p_ra->pre_ratr_state != p_ra->ratr_state) {
737 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
738 "RSSI = %ld\n",
739 rtlpriv->dm.undec_sm_pwdb);
740 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
741 "RSSI_LEVEL = %d\n", p_ra->ratr_state);
742 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
743 "PreState = %d, CurState = %d\n",
744 p_ra->pre_ratr_state, p_ra->ratr_state);
745
746 rcu_read_lock();
747 sta = rtl_find_sta(hw, mac->bssid);
748 if (sta)
749 rtlpriv->cfg->ops->update_rate_tbl(hw, sta,
750 p_ra->ratr_state);
751 rcu_read_unlock();
752
753 p_ra->pre_ratr_state = p_ra->ratr_state;
754 }
755 }
756} 702}
757 703
758void rtl8723ae_dm_rf_saving(struct ieee80211_hw *hw, u8 force_in_normal) 704void rtl8723e_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal)
759{ 705{
760 struct rtl_priv *rtlpriv = rtl_priv(hw); 706 struct rtl_priv *rtlpriv = rtl_priv(hw);
761 struct ps_t *dm_pstable = &rtlpriv->dm_pstable; 707 struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
708 static u8 initialize;
709 static u32 reg_874, reg_c70, reg_85c, reg_a74;
762 710
763 if (!rtlpriv->reg_init) { 711 if (initialize == 0) {
764 rtlpriv->reg_874 = (rtl_get_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, 712 reg_874 = (rtl_get_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
765 MASKDWORD) & 0x1CC000) >> 14; 713 MASKDWORD) & 0x1CC000) >> 14;
766 714
767 rtlpriv->reg_c70 = (rtl_get_bbreg(hw, ROFDM0_AGCPARAMETER1, 715 reg_c70 = (rtl_get_bbreg(hw, ROFDM0_AGCPARAMETER1,
768 MASKDWORD) & BIT(3)) >> 3; 716 MASKDWORD) & BIT(3)) >> 3;
769 717
770 rtlpriv->reg_85c = (rtl_get_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 718 reg_85c = (rtl_get_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
771 MASKDWORD) & 0xFF000000) >> 24; 719 MASKDWORD) & 0xFF000000) >> 24;
772 720
773 rtlpriv->reg_a74 = (rtl_get_bbreg(hw, 0xa74, MASKDWORD) & 721 reg_a74 = (rtl_get_bbreg(hw, 0xa74, MASKDWORD) & 0xF000) >> 12;
774 0xF000) >> 12;
775 722
776 rtlpriv->reg_init = true; 723 initialize = 1;
777 } 724 }
778 725
779 if (!force_in_normal) { 726 if (!bforce_in_normal) {
780 if (dm_pstable->rssi_val_min != 0) { 727 if (dm_pstable->rssi_val_min != 0) {
781 if (dm_pstable->pre_rfstate == RF_NORMAL) { 728 if (dm_pstable->pre_rfstate == RF_NORMAL) {
782 if (dm_pstable->rssi_val_min >= 30) 729 if (dm_pstable->rssi_val_min >= 30)
@@ -798,7 +745,6 @@ void rtl8723ae_dm_rf_saving(struct ieee80211_hw *hw, u8 force_in_normal)
798 745
799 if (dm_pstable->pre_rfstate != dm_pstable->cur_rfstate) { 746 if (dm_pstable->pre_rfstate != dm_pstable->cur_rfstate) {
800 if (dm_pstable->cur_rfstate == RF_SAVE) { 747 if (dm_pstable->cur_rfstate == RF_SAVE) {
801
802 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, 748 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
803 BIT(5), 0x1); 749 BIT(5), 0x1);
804 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, 750 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
@@ -813,12 +759,12 @@ void rtl8723ae_dm_rf_saving(struct ieee80211_hw *hw, u8 force_in_normal)
813 rtl_set_bbreg(hw, 0x818, BIT(28), 0x1); 759 rtl_set_bbreg(hw, 0x818, BIT(28), 0x1);
814 } else { 760 } else {
815 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, 761 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
816 0x1CC000, rtlpriv->reg_874); 762 0x1CC000, reg_874);
817 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), 763 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3),
818 rtlpriv->reg_c70); 764 reg_c70);
819 rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 0xFF000000, 765 rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 0xFF000000,
820 rtlpriv->reg_85c); 766 reg_85c);
821 rtl_set_bbreg(hw, 0xa74, 0xF000, rtlpriv->reg_a74); 767 rtl_set_bbreg(hw, 0xa74, 0xF000, reg_a74);
822 rtl_set_bbreg(hw, 0x818, BIT(28), 0x0); 768 rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
823 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, 769 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
824 BIT(5), 0x0); 770 BIT(5), 0x0);
@@ -828,7 +774,7 @@ void rtl8723ae_dm_rf_saving(struct ieee80211_hw *hw, u8 force_in_normal)
828 } 774 }
829} 775}
830 776
831static void rtl8723ae_dm_dynamic_bpowersaving(struct ieee80211_hw *hw) 777static void rtl8723e_dm_dynamic_bb_powersaving(struct ieee80211_hw *hw)
832{ 778{
833 struct rtl_priv *rtlpriv = rtl_priv(hw); 779 struct rtl_priv *rtlpriv = rtl_priv(hw);
834 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 780 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
@@ -847,48 +793,49 @@ static void rtl8723ae_dm_dynamic_bpowersaving(struct ieee80211_hw *hw)
847 rtlpriv->dm.entry_min_undec_sm_pwdb; 793 rtlpriv->dm.entry_min_undec_sm_pwdb;
848 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD, 794 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
849 "AP Client PWDB = 0x%lx\n", 795 "AP Client PWDB = 0x%lx\n",
850 dm_pstable->rssi_val_min); 796 dm_pstable->rssi_val_min);
851 } else { 797 } else {
852 dm_pstable->rssi_val_min = rtlpriv->dm.undec_sm_pwdb; 798 dm_pstable->rssi_val_min =
799 rtlpriv->dm.undec_sm_pwdb;
853 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD, 800 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
854 "STA Default Port PWDB = 0x%lx\n", 801 "STA Default Port PWDB = 0x%lx\n",
855 dm_pstable->rssi_val_min); 802 dm_pstable->rssi_val_min);
856 } 803 }
857 } else { 804 } else {
858 dm_pstable->rssi_val_min = rtlpriv->dm.entry_min_undec_sm_pwdb; 805 dm_pstable->rssi_val_min =
806 rtlpriv->dm.entry_min_undec_sm_pwdb;
859 807
860 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD, 808 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
861 "AP Ext Port PWDB = 0x%lx\n", 809 "AP Ext Port PWDB = 0x%lx\n",
862 dm_pstable->rssi_val_min); 810 dm_pstable->rssi_val_min);
863 } 811 }
864 812
865 rtl8723ae_dm_rf_saving(hw, false); 813 rtl8723e_dm_rf_saving(hw, false);
866} 814}
867 815
868void rtl8723ae_dm_init(struct ieee80211_hw *hw) 816void rtl8723e_dm_init(struct ieee80211_hw *hw)
869{ 817{
870 struct rtl_priv *rtlpriv = rtl_priv(hw); 818 struct rtl_priv *rtlpriv = rtl_priv(hw);
871 819
872 rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER; 820 rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
873 rtl8723ae_dm_diginit(hw); 821 rtl8723e_dm_diginit(hw);
874 rtl8723_dm_init_dynamic_txpower(hw); 822 rtl8723_dm_init_dynamic_txpower(hw);
875 rtl8723_dm_init_edca_turbo(hw); 823 rtl8723_dm_init_edca_turbo(hw);
876 rtl8723ae_dm_init_rate_adaptive_mask(hw); 824 rtl8723e_dm_init_rate_adaptive_mask(hw);
877 rtl8723ae_dm_initialize_txpower_tracking(hw); 825 rtl8723e_dm_initialize_txpower_tracking(hw);
878 rtl8723_dm_init_dynamic_bb_powersaving(hw); 826 rtl8723_dm_init_dynamic_bb_powersaving(hw);
879} 827}
880 828
881void rtl8723ae_dm_watchdog(struct ieee80211_hw *hw) 829void rtl8723e_dm_watchdog(struct ieee80211_hw *hw)
882{ 830{
883 struct rtl_priv *rtlpriv = rtl_priv(hw); 831 struct rtl_priv *rtlpriv = rtl_priv(hw);
884 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 832 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
885 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
886 bool fw_current_inpsmode = false; 833 bool fw_current_inpsmode = false;
887 bool fw_ps_awake = true; 834 bool fw_ps_awake = true;
888 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 835 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
889 (u8 *) (&fw_current_inpsmode)); 836 (u8 *)(&fw_current_inpsmode));
890 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON, 837 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
891 (u8 *) (&fw_ps_awake)); 838 (u8 *)(&fw_ps_awake));
892 839
893 if (ppsc->p2p_ps_info.p2p_ps_mode) 840 if (ppsc->p2p_ps_info.p2p_ps_mode)
894 fw_ps_awake = false; 841 fw_ps_awake = false;
@@ -896,58 +843,57 @@ void rtl8723ae_dm_watchdog(struct ieee80211_hw *hw)
896 if ((ppsc->rfpwr_state == ERFON) && 843 if ((ppsc->rfpwr_state == ERFON) &&
897 ((!fw_current_inpsmode) && fw_ps_awake) && 844 ((!fw_current_inpsmode) && fw_ps_awake) &&
898 (!ppsc->rfchange_inprogress)) { 845 (!ppsc->rfchange_inprogress)) {
899 rtl8723ae_dm_dig(hw); 846 rtl8723e_dm_pwdb_monitor(hw);
900 rtl8723ae_dm_false_alarm_counter_statistics(hw); 847 rtl8723e_dm_dig(hw);
901 rtl8723ae_dm_dynamic_bpowersaving(hw); 848 rtl8723e_dm_false_alarm_counter_statistics(hw);
902 rtl8723ae_dm_dynamic_txpower(hw); 849 rtl8723e_dm_dynamic_bb_powersaving(hw);
903 rtl8723ae_dm_refresh_rate_adaptive_mask(hw); 850 rtl8723e_dm_dynamic_txpower(hw);
904 rtl8723ae_dm_bt_coexist(hw); 851 rtl8723e_dm_check_txpower_tracking(hw);
905 rtl8723ae_dm_check_edca_turbo(hw); 852 /* rtl92c_dm_refresh_rate_adaptive_mask(hw); */
853 rtl8723e_dm_bt_coexist(hw);
854 rtl8723e_dm_check_edca_turbo(hw);
906 } 855 }
907 if (rtlpcipriv->bt_coexist.init_set) 856 if (rtlpriv->btcoexist.init_set)
908 rtl_write_byte(rtlpriv, 0x76e, 0xc); 857 rtl_write_byte(rtlpriv, 0x76e, 0xc);
909} 858}
910 859
911static void rtl8723ae_dm_init_bt_coexist(struct ieee80211_hw *hw) 860static void rtl8723e_dm_init_bt_coexist(struct ieee80211_hw *hw)
912{ 861{
913 struct rtl_priv *rtlpriv = rtl_priv(hw); 862 struct rtl_priv *rtlpriv = rtl_priv(hw);
914 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
915 863
916 rtlpcipriv->bt_coexist.bt_rfreg_origin_1e 864 rtlpriv->btcoexist.bt_rfreg_origin_1e
917 = rtl_get_rfreg(hw, (enum radio_path)0, RF_RCK1, 0xfffff); 865 = rtl_get_rfreg(hw, (enum radio_path)0, RF_RCK1, 0xfffff);
918 rtlpcipriv->bt_coexist.bt_rfreg_origin_1f 866 rtlpriv->btcoexist.bt_rfreg_origin_1f
919 = rtl_get_rfreg(hw, (enum radio_path)0, RF_RCK2, 0xf0); 867 = rtl_get_rfreg(hw, (enum radio_path)0, RF_RCK2, 0xf0);
920 868
921 rtlpcipriv->bt_coexist.cstate = 0; 869 rtlpriv->btcoexist.cstate = 0;
922 rtlpcipriv->bt_coexist.previous_state = 0; 870 rtlpriv->btcoexist.previous_state = 0;
923 rtlpcipriv->bt_coexist.cstate_h = 0; 871 rtlpriv->btcoexist.cstate_h = 0;
924 rtlpcipriv->bt_coexist.previous_state_h = 0; 872 rtlpriv->btcoexist.previous_state_h = 0;
925 rtlpcipriv->bt_coexist.lps_counter = 0; 873 rtlpriv->btcoexist.lps_counter = 0;
926 874
927 /* Enable counter statistics */ 875 /* Enable counter statistics */
928 rtl_write_byte(rtlpriv, 0x76e, 0x4); 876 rtl_write_byte(rtlpriv, 0x76e, 0x4);
929 rtl_write_byte(rtlpriv, 0x778, 0x3); 877 rtl_write_byte(rtlpriv, 0x778, 0x3);
930 rtl_write_byte(rtlpriv, 0x40, 0x20); 878 rtl_write_byte(rtlpriv, 0x40, 0x20);
931 879
932 rtlpcipriv->bt_coexist.init_set = true; 880 rtlpriv->btcoexist.init_set = true;
933} 881}
934 882
935void rtl8723ae_dm_bt_coexist(struct ieee80211_hw *hw) 883void rtl8723e_dm_bt_coexist(struct ieee80211_hw *hw)
936{ 884{
937 struct rtl_priv *rtlpriv = rtl_priv(hw); 885 struct rtl_priv *rtlpriv = rtl_priv(hw);
938 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
939 u8 tmp_byte = 0; 886 u8 tmp_byte = 0;
940 if (!rtlpcipriv->bt_coexist.bt_coexistence) { 887 if (!rtlpriv->btcoexist.bt_coexistence) {
941 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 888 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
942 "[DM]{BT], BT not exist!!\n"); 889 "[DM]{BT], BT not exist!!\n");
943 return; 890 return;
944 } 891 }
945 892
946 if (!rtlpcipriv->bt_coexist.init_set) { 893 if (!rtlpriv->btcoexist.init_set) {
947 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 894 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
948 "[DM][BT], rtl8723ae_dm_bt_coexist()\n"); 895 "[DM][BT], rtl8723e_dm_bt_coexist()\n");
949 896 rtl8723e_dm_init_bt_coexist(hw);
950 rtl8723ae_dm_init_bt_coexist(hw);
951 } 897 }
952 898
953 tmp_byte = rtl_read_byte(rtlpriv, 0x40); 899 tmp_byte = rtl_read_byte(rtlpriv, 0x40);
@@ -955,5 +901,5 @@ void rtl8723ae_dm_bt_coexist(struct ieee80211_hw *hw)
955 "[DM][BT], 0x40 is 0x%x", tmp_byte); 901 "[DM][BT], 0x40 is 0x%x", tmp_byte);
956 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 902 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
957 "[DM][BT], bt_dm_coexist start"); 903 "[DM][BT], bt_dm_coexist start");
958 rtl8723ae_dm_bt_coexist_8723(hw); 904 rtl8723e_dm_bt_coexist_8723(hw);
959} 905}
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/dm.h b/drivers/net/wireless/rtlwifi/rtl8723ae/dm.h
index d253bb53d03e..6fa0feb05f6d 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/dm.h
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/dm.h
@@ -25,17 +25,23 @@
25 * 25 *
26 * Larry Finger <Larry.Finger@lwfinger.net> 26 * Larry Finger <Larry.Finger@lwfinger.net>
27 * 27 *
28 **************************************************************************** 28 *****************************************************************************/
29 */
30 29
31#ifndef __RTL8723E_DM_H__ 30#ifndef __RTL8723E_DM_H__
32#define __RTL8723E_DM_H__ 31#define __RTL8723E_DM_H__
33 32
33#define HAL_DM_DIG_DISABLE BIT(0)
34#define HAL_DM_HIPWR_DISABLE BIT(1) 34#define HAL_DM_HIPWR_DISABLE BIT(1)
35 35
36#define OFDM_TABLE_LENGTH 37
37#define CCK_TABLE_LENGTH 33
38
36#define OFDM_TABLE_SIZE 37 39#define OFDM_TABLE_SIZE 37
37#define CCK_TABLE_SIZE 33 40#define CCK_TABLE_SIZE 33
38 41
42#define BW_AUTO_SWITCH_HIGH_LOW 25
43#define BW_AUTO_SWITCH_LOW_HIGH 30
44
39#define DM_DIG_THRESH_HIGH 40 45#define DM_DIG_THRESH_HIGH 40
40#define DM_DIG_THRESH_LOW 35 46#define DM_DIG_THRESH_LOW 35
41 47
@@ -63,12 +69,18 @@
63#define DM_RATR_STA_MIDDLE 2 69#define DM_RATR_STA_MIDDLE 2
64#define DM_RATR_STA_LOW 3 70#define DM_RATR_STA_LOW 3
65 71
72#define CTS2SELF_THVAL 30
73#define REGC38_TH 20
74
75#define WAIOTTHVAL 25
76
66#define TXHIGHPWRLEVEL_NORMAL 0 77#define TXHIGHPWRLEVEL_NORMAL 0
67#define TXHIGHPWRLEVEL_LEVEL1 1 78#define TXHIGHPWRLEVEL_LEVEL1 1
68#define TXHIGHPWRLEVEL_LEVEL2 2 79#define TXHIGHPWRLEVEL_LEVEL2 2
69#define TXHIGHPWRLEVEL_BT1 3 80#define TXHIGHPWRLEVEL_BT1 3
70#define TXHIGHPWRLEVEL_BT2 4 81#define TXHIGHPWRLEVEL_BT2 4
71 82
83#define DM_TYPE_BYFW 0
72#define DM_TYPE_BYDRIVER 1 84#define DM_TYPE_BYDRIVER 1
73 85
74#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 86#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
@@ -82,6 +94,7 @@ struct swat_t {
82 long trying_threshold; 94 long trying_threshold;
83 u8 cur_antenna; 95 u8 cur_antenna;
84 u8 pre_antenna; 96 u8 pre_antenna;
97
85}; 98};
86 99
87enum tag_dynamic_init_gain_operation_type_definition { 100enum tag_dynamic_init_gain_operation_type_definition {
@@ -98,7 +111,7 @@ enum tag_dynamic_init_gain_operation_type_definition {
98enum tag_cck_packet_detection_threshold_type_definition { 111enum tag_cck_packet_detection_threshold_type_definition {
99 CCK_PD_STAGE_LowRssi = 0, 112 CCK_PD_STAGE_LowRssi = 0,
100 CCK_PD_STAGE_HighRssi = 1, 113 CCK_PD_STAGE_HighRssi = 1,
101 CCK_FA_STAGE_Low = 2, 114 CCK_FA_STAGE_LOW = 2,
102 CCK_FA_STAGE_High = 3, 115 CCK_FA_STAGE_High = 3,
103 CCK_PD_STAGE_MAX = 4, 116 CCK_PD_STAGE_MAX = 4,
104}; 117};
@@ -138,17 +151,24 @@ enum dm_dig_connect_e {
138 DIG_CONNECT_MAX 151 DIG_CONNECT_MAX
139}; 152};
140 153
154#define BT_RSSI_STATE_NORMAL_POWER BIT_OFFSET_LEN_MASK_32(0, 1)
155#define BT_RSSI_STATE_AMDPU_OFF BIT_OFFSET_LEN_MASK_32(1, 1)
156#define BT_RSSI_STATE_SPECIAL_LOW BIT_OFFSET_LEN_MASK_32(2, 1)
157#define BT_RSSI_STATE_BG_EDCA_LOW BIT_OFFSET_LEN_MASK_32(3, 1)
158#define BT_RSSI_STATE_TXPOWER_LOW BIT_OFFSET_LEN_MASK_32(4, 1)
141#define GET_UNDECORATED_AVERAGE_RSSI(_priv) \ 159#define GET_UNDECORATED_AVERAGE_RSSI(_priv) \
142 ((((struct rtl_priv *)(_priv))->mac80211.opmode == \ 160 ( \
143 NL80211_IFTYPE_ADHOC) ? \ 161 (((struct rtl_priv *)(_priv))->mac80211.opmode == \
144 (((struct rtl_priv *)(_priv))->dm.entry_min_undec_sm_pwdb) \ 162 NL80211_IFTYPE_ADHOC) ? \
145 : (((struct rtl_priv *)(_priv))->dm.undec_sm_pwdb)) 163 (((struct rtl_priv *)(_priv))->dm.entry_min_undec_sm_pwdb) : \
146 164 (((struct rtl_priv *)(_priv))->dm.undec_sm_pwdb) \
147void rtl8723ae_dm_init(struct ieee80211_hw *hw); 165 )
148void rtl8723ae_dm_watchdog(struct ieee80211_hw *hw); 166
149void rtl8723ae_dm_write_dig(struct ieee80211_hw *hw); 167void rtl8723e_dm_init(struct ieee80211_hw *hw);
150void rtl8723ae_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw); 168void rtl8723e_dm_watchdog(struct ieee80211_hw *hw);
151void rtl8723ae_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal); 169void rtl8723e_dm_write_dig(struct ieee80211_hw *hw);
152void rtl8723ae_dm_bt_coexist(struct ieee80211_hw *hw); 170void rtl8723e_dm_check_txpower_tracking(struct ieee80211_hw *hw);
153 171void rtl8723e_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);
172void rtl8723e_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal);
173void rtl8723e_dm_bt_coexist(struct ieee80211_hw *hw);
154#endif 174#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/fw.c b/drivers/net/wireless/rtlwifi/rtl8723ae/fw.c
index 728b7563ad36..97d92e2d3cc9 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/fw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/fw.c
@@ -11,10 +11,6 @@
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details. 12 * more details.
13 * 13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the 14 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE. 15 * file called LICENSE.
20 * 16 *
@@ -25,8 +21,7 @@
25 * 21 *
26 * Larry Finger <Larry.Finger@lwfinger.net> 22 * Larry Finger <Larry.Finger@lwfinger.net>
27 * 23 *
28 **************************************************************************** 24 *****************************************************************************/
29 */
30 25
31#include "../wifi.h" 26#include "../wifi.h"
32#include "../pci.h" 27#include "../pci.h"
@@ -36,7 +31,8 @@
36#include "fw.h" 31#include "fw.h"
37#include "../rtl8723com/fw_common.h" 32#include "../rtl8723com/fw_common.h"
38 33
39static bool rtl8723ae_check_fw_read_last_h2c(struct ieee80211_hw *hw, u8 boxnum) 34static bool _rtl8723e_check_fw_read_last_h2c(struct ieee80211_hw *hw,
35 u8 boxnum)
40{ 36{
41 struct rtl_priv *rtlpriv = rtl_priv(hw); 37 struct rtl_priv *rtlpriv = rtl_priv(hw);
42 u8 val_hmetfr, val_mcutst_1; 38 u8 val_hmetfr, val_mcutst_1;
@@ -50,17 +46,17 @@ static bool rtl8723ae_check_fw_read_last_h2c(struct ieee80211_hw *hw, u8 boxnum)
50 return result; 46 return result;
51} 47}
52 48
53static void _rtl8723ae_fill_h2c_command(struct ieee80211_hw *hw, 49static void _rtl8723e_fill_h2c_command(struct ieee80211_hw *hw, u8 element_id,
54 u8 element_id, u32 cmd_len, 50 u32 cmd_len, u8 *cmdbuffer)
55 u8 *p_cmdbuffer)
56{ 51{
57 struct rtl_priv *rtlpriv = rtl_priv(hw); 52 struct rtl_priv *rtlpriv = rtl_priv(hw);
58 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 53 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
59 u8 boxnum; 54 u8 boxnum;
60 u16 box_reg = 0, box_extreg = 0; 55 u16 box_reg = 0, box_extreg = 0;
61 u8 u1tmp; 56 u8 u1b_tmp;
62 bool isfw_rd = false; 57 bool isfw_read = false;
63 bool bwrite_success = false; 58 u8 buf_index = 0;
59 bool bwrite_sucess = false;
64 u8 wait_h2c_limmit = 100; 60 u8 wait_h2c_limmit = 100;
65 u8 wait_writeh2c_limmit = 100; 61 u8 wait_writeh2c_limmit = 100;
66 u8 boxcontent[4], boxextcontent[2]; 62 u8 boxcontent[4], boxextcontent[2];
@@ -83,7 +79,7 @@ static void _rtl8723ae_fill_h2c_command(struct ieee80211_hw *hw,
83 h2c_waitcounter++; 79 h2c_waitcounter++;
84 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, 80 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
85 "Wait 100 us (%d times)...\n", 81 "Wait 100 us (%d times)...\n",
86 h2c_waitcounter); 82 h2c_waitcounter);
87 udelay(100); 83 udelay(100);
88 84
89 if (h2c_waitcounter > 1000) 85 if (h2c_waitcounter > 1000)
@@ -99,12 +95,11 @@ static void _rtl8723ae_fill_h2c_command(struct ieee80211_hw *hw,
99 } 95 }
100 } 96 }
101 97
102 while (!bwrite_success) { 98 while (!bwrite_sucess) {
103 wait_writeh2c_limmit--; 99 wait_writeh2c_limmit--;
104 if (wait_writeh2c_limmit == 0) { 100 if (wait_writeh2c_limmit == 0) {
105 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 101 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
106 "Write H2C fail because no trigger " 102 "Write H2C fail because no trigger for FW INT!\n");
107 "for FW INT!\n");
108 break; 103 break;
109 } 104 }
110 105
@@ -128,34 +123,35 @@ static void _rtl8723ae_fill_h2c_command(struct ieee80211_hw *hw,
128 break; 123 break;
129 default: 124 default:
130 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 125 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
131 "switch case not processed\n"); 126 "switch case not process\n");
132 break; 127 break;
133 } 128 }
134 129
135 isfw_rd = rtl8723ae_check_fw_read_last_h2c(hw, boxnum); 130 isfw_read = _rtl8723e_check_fw_read_last_h2c(hw, boxnum);
136 while (!isfw_rd) { 131 while (!isfw_read) {
137 132
138 wait_h2c_limmit--; 133 wait_h2c_limmit--;
139 if (wait_h2c_limmit == 0) { 134 if (wait_h2c_limmit == 0) {
140 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, 135 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
141 "Waiting too long for FW read clear HMEBox(%d)!\n", 136 "Wating too long for FW read clear HMEBox(%d)!\n",
142 boxnum); 137 boxnum);
143 break; 138 break;
144 } 139 }
145 140
146 udelay(10); 141 udelay(10);
147 142
148 isfw_rd = rtl8723ae_check_fw_read_last_h2c(hw, boxnum); 143 isfw_read = _rtl8723e_check_fw_read_last_h2c(hw,
149 u1tmp = rtl_read_byte(rtlpriv, 0x1BF); 144 boxnum);
145 u1b_tmp = rtl_read_byte(rtlpriv, 0x1BF);
150 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, 146 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
151 "Waiting for FW read clear HMEBox(%d)!!! " 147 "Waiting for FW read clear HMEBox(%d)!!! 0x1BF = %2x\n",
152 "0x1BF = %2x\n", boxnum, u1tmp); 148 boxnum, u1b_tmp);
153 } 149 }
154 150
155 if (!isfw_rd) { 151 if (!isfw_read) {
156 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, 152 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
157 "Write H2C register BOX[%d] fail!!!!! " 153 "Write H2C register BOX[%d] fail!!!!! Fw do not read.\n",
158 "Fw do not read.\n", boxnum); 154 boxnum);
159 break; 155 break;
160 } 156 }
161 157
@@ -169,8 +165,8 @@ static void _rtl8723ae_fill_h2c_command(struct ieee80211_hw *hw,
169 switch (cmd_len) { 165 switch (cmd_len) {
170 case 1: 166 case 1:
171 boxcontent[0] &= ~(BIT(7)); 167 boxcontent[0] &= ~(BIT(7));
172 memcpy((u8 *) (boxcontent) + 1, 168 memcpy((u8 *)(boxcontent) + 1,
173 p_cmdbuffer, 1); 169 cmdbuffer + buf_index, 1);
174 170
175 for (idx = 0; idx < 4; idx++) { 171 for (idx = 0; idx < 4; idx++) {
176 rtl_write_byte(rtlpriv, box_reg + idx, 172 rtl_write_byte(rtlpriv, box_reg + idx,
@@ -179,8 +175,8 @@ static void _rtl8723ae_fill_h2c_command(struct ieee80211_hw *hw,
179 break; 175 break;
180 case 2: 176 case 2:
181 boxcontent[0] &= ~(BIT(7)); 177 boxcontent[0] &= ~(BIT(7));
182 memcpy((u8 *) (boxcontent) + 1, 178 memcpy((u8 *)(boxcontent) + 1,
183 p_cmdbuffer, 2); 179 cmdbuffer + buf_index, 2);
184 180
185 for (idx = 0; idx < 4; idx++) { 181 for (idx = 0; idx < 4; idx++) {
186 rtl_write_byte(rtlpriv, box_reg + idx, 182 rtl_write_byte(rtlpriv, box_reg + idx,
@@ -189,8 +185,8 @@ static void _rtl8723ae_fill_h2c_command(struct ieee80211_hw *hw,
189 break; 185 break;
190 case 3: 186 case 3:
191 boxcontent[0] &= ~(BIT(7)); 187 boxcontent[0] &= ~(BIT(7));
192 memcpy((u8 *) (boxcontent) + 1, 188 memcpy((u8 *)(boxcontent) + 1,
193 p_cmdbuffer, 3); 189 cmdbuffer + buf_index, 3);
194 190
195 for (idx = 0; idx < 4; idx++) { 191 for (idx = 0; idx < 4; idx++) {
196 rtl_write_byte(rtlpriv, box_reg + idx, 192 rtl_write_byte(rtlpriv, box_reg + idx,
@@ -199,10 +195,10 @@ static void _rtl8723ae_fill_h2c_command(struct ieee80211_hw *hw,
199 break; 195 break;
200 case 4: 196 case 4:
201 boxcontent[0] |= (BIT(7)); 197 boxcontent[0] |= (BIT(7));
202 memcpy((u8 *) (boxextcontent), 198 memcpy((u8 *)(boxextcontent),
203 p_cmdbuffer, 2); 199 cmdbuffer + buf_index, 2);
204 memcpy((u8 *) (boxcontent) + 1, 200 memcpy((u8 *)(boxcontent) + 1,
205 p_cmdbuffer + 2, 2); 201 cmdbuffer + buf_index + 2, 2);
206 202
207 for (idx = 0; idx < 2; idx++) { 203 for (idx = 0; idx < 2; idx++) {
208 rtl_write_byte(rtlpriv, box_extreg + idx, 204 rtl_write_byte(rtlpriv, box_extreg + idx,
@@ -216,10 +212,10 @@ static void _rtl8723ae_fill_h2c_command(struct ieee80211_hw *hw,
216 break; 212 break;
217 case 5: 213 case 5:
218 boxcontent[0] |= (BIT(7)); 214 boxcontent[0] |= (BIT(7));
219 memcpy((u8 *) (boxextcontent), 215 memcpy((u8 *)(boxextcontent),
220 p_cmdbuffer, 2); 216 cmdbuffer + buf_index, 2);
221 memcpy((u8 *) (boxcontent) + 1, 217 memcpy((u8 *)(boxcontent) + 1,
222 p_cmdbuffer + 2, 3); 218 cmdbuffer + buf_index + 2, 3);
223 219
224 for (idx = 0; idx < 2; idx++) { 220 for (idx = 0; idx < 2; idx++) {
225 rtl_write_byte(rtlpriv, box_extreg + idx, 221 rtl_write_byte(rtlpriv, box_extreg + idx,
@@ -237,7 +233,7 @@ static void _rtl8723ae_fill_h2c_command(struct ieee80211_hw *hw,
237 break; 233 break;
238 } 234 }
239 235
240 bwrite_success = true; 236 bwrite_sucess = true;
241 237
242 rtlhal->last_hmeboxnum = boxnum + 1; 238 rtlhal->last_hmeboxnum = boxnum + 1;
243 if (rtlhal->last_hmeboxnum == 4) 239 if (rtlhal->last_hmeboxnum == 4)
@@ -245,7 +241,7 @@ static void _rtl8723ae_fill_h2c_command(struct ieee80211_hw *hw,
245 241
246 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, 242 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
247 "pHalData->last_hmeboxnum = %d\n", 243 "pHalData->last_hmeboxnum = %d\n",
248 rtlhal->last_hmeboxnum); 244 rtlhal->last_hmeboxnum);
249 } 245 }
250 246
251 spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag); 247 spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
@@ -255,52 +251,49 @@ static void _rtl8723ae_fill_h2c_command(struct ieee80211_hw *hw,
255 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "go out\n"); 251 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "go out\n");
256} 252}
257 253
258void rtl8723ae_fill_h2c_cmd(struct ieee80211_hw *hw, 254void rtl8723e_fill_h2c_cmd(struct ieee80211_hw *hw,
259 u8 element_id, u32 cmd_len, u8 *p_cmdbuffer) 255 u8 element_id, u32 cmd_len, u8 *cmdbuffer)
260{ 256{
261 struct rtl_priv *rtlpriv = rtl_priv(hw); 257 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
262 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 258 u32 tmp_cmdbuf[2];
263 259
264 if (rtlhal->fw_ready == false) { 260 if (!rtlhal->fw_ready) {
265 RT_ASSERT(false, 261 RT_ASSERT(false,
266 "return H2C cmd because of Fw download fail!!!\n"); 262 "return H2C cmd because of Fw download fail!!!\n");
267 return; 263 return;
268 } 264 }
269 265 memset(tmp_cmdbuf, 0, 8);
270 _rtl8723ae_fill_h2c_command(hw, element_id, cmd_len, p_cmdbuffer); 266 memcpy(tmp_cmdbuf, cmdbuffer, cmd_len);
271 return; 267 _rtl8723e_fill_h2c_command(hw, element_id, cmd_len,
268 (u8 *)&tmp_cmdbuf);
272} 269}
273 270
274static bool _rtl8723ae_cmd_send_packet(struct ieee80211_hw *hw, 271void rtl8723e_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode)
275 struct sk_buff *skb)
276{ 272{
277 struct rtl_priv *rtlpriv = rtl_priv(hw); 273 struct rtl_priv *rtlpriv = rtl_priv(hw);
278 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 274 u8 u1_h2c_set_pwrmode[3] = { 0 };
279 struct rtl8192_tx_ring *ring; 275 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
280 struct rtl_tx_desc *pdesc;
281 unsigned long flags;
282 struct sk_buff *pskb = NULL;
283
284 ring = &rtlpci->tx_ring[BEACON_QUEUE];
285
286 pskb = __skb_dequeue(&ring->queue);
287 if (pskb)
288 kfree_skb(pskb);
289
290 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
291
292 pdesc = &ring->desc[0];
293 276
294 rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *) pdesc, 1, 1, skb); 277 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "FW LPS mode = %d\n", mode);
295 278
296 __skb_queue_tail(&ring->queue, skb); 279 SET_H2CCMD_PWRMODE_PARM_MODE(u1_h2c_set_pwrmode, mode);
280 SET_H2CCMD_PWRMODE_PARM_SMART_PS(u1_h2c_set_pwrmode,
281 (rtlpriv->mac80211.p2p) ? ppsc->smart_ps : 1);
282 SET_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(u1_h2c_set_pwrmode,
283 ppsc->reg_max_lps_awakeintvl);
297 284
298 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 285 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
286 "rtl8723e_set_fw_rsvdpagepkt(): u1_h2c_set_pwrmode\n",
287 u1_h2c_set_pwrmode, 3);
288 rtl8723e_fill_h2c_cmd(hw, H2C_SETPWRMODE, 3, u1_h2c_set_pwrmode);
289}
299 290
300 rtlpriv->cfg->ops->tx_polling(hw, BEACON_QUEUE); 291#define BEACON_PG 0 /* ->1 */
292#define PSPOLL_PG 2
293#define NULL_PG 3
294#define PROBERSP_PG 4 /* ->5 */
301 295
302 return true; 296#define TOTAL_RESERVED_PKT_LEN 768
303}
304 297
305static u8 reserved_page_packet[TOTAL_RESERVED_PKT_LEN] = { 298static u8 reserved_page_packet[TOTAL_RESERVED_PKT_LEN] = {
306 /* page 0 beacon */ 299 /* page 0 beacon */
@@ -412,111 +405,111 @@ static u8 reserved_page_packet[TOTAL_RESERVED_PKT_LEN] = {
412 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 405 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
413}; 406};
414 407
415void rtl8723ae_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool dl_finished) 408void rtl8723e_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished)
416{ 409{
417 struct rtl_priv *rtlpriv = rtl_priv(hw); 410 struct rtl_priv *rtlpriv = rtl_priv(hw);
418 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 411 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
419 struct sk_buff *skb = NULL; 412 struct sk_buff *skb = NULL;
420
421 u32 totalpacketlen; 413 u32 totalpacketlen;
422 bool rtstatus; 414 bool rtstatus;
423 u8 u1RsvdPageLoc[3] = { 0 }; 415 u8 u1rsvdpageloc[3] = { 0 };
424 bool dlok = false; 416 bool b_dlok = false;
425
426 u8 *beacon; 417 u8 *beacon;
427 u8 *p_pspoll; 418 u8 *p_pspoll;
428 u8 *nullfunc; 419 u8 *nullfunc;
429 u8 *p_probersp; 420 u8 *p_probersp;
421
430 /*--------------------------------------------------------- 422 /*---------------------------------------------------------
431 (1) beacon 423 * (1) beacon
432 --------------------------------------------------------- 424 *---------------------------------------------------------
433 */ 425 */
434 beacon = &reserved_page_packet[BEACON_PG * 128]; 426 beacon = &reserved_page_packet[BEACON_PG * 128];
435 SET_80211_HDR_ADDRESS2(beacon, mac->mac_addr); 427 SET_80211_HDR_ADDRESS2(beacon, mac->mac_addr);
436 SET_80211_HDR_ADDRESS3(beacon, mac->bssid); 428 SET_80211_HDR_ADDRESS3(beacon, mac->bssid);
437 429
438 /*------------------------------------------------------- 430 /*-------------------------------------------------------
439 (2) ps-poll 431 * (2) ps-poll
440 -------------------------------------------------------- 432 *--------------------------------------------------------
441 */ 433 */
442 p_pspoll = &reserved_page_packet[PSPOLL_PG * 128]; 434 p_pspoll = &reserved_page_packet[PSPOLL_PG * 128];
443 SET_80211_PS_POLL_AID(p_pspoll, (mac->assoc_id | 0xc000)); 435 SET_80211_PS_POLL_AID(p_pspoll, (mac->assoc_id | 0xc000));
444 SET_80211_PS_POLL_BSSID(p_pspoll, mac->bssid); 436 SET_80211_PS_POLL_BSSID(p_pspoll, mac->bssid);
445 SET_80211_PS_POLL_TA(p_pspoll, mac->mac_addr); 437 SET_80211_PS_POLL_TA(p_pspoll, mac->mac_addr);
446 438
447 SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1RsvdPageLoc, PSPOLL_PG); 439 SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1rsvdpageloc, PSPOLL_PG);
448 440
449 /*-------------------------------------------------------- 441 /*--------------------------------------------------------
450 (3) null data 442 * (3) null data
451 ---------------------------------------------------------i 443 *---------------------------------------------------------
452 */ 444 */
453 nullfunc = &reserved_page_packet[NULL_PG * 128]; 445 nullfunc = &reserved_page_packet[NULL_PG * 128];
454 SET_80211_HDR_ADDRESS1(nullfunc, mac->bssid); 446 SET_80211_HDR_ADDRESS1(nullfunc, mac->bssid);
455 SET_80211_HDR_ADDRESS2(nullfunc, mac->mac_addr); 447 SET_80211_HDR_ADDRESS2(nullfunc, mac->mac_addr);
456 SET_80211_HDR_ADDRESS3(nullfunc, mac->bssid); 448 SET_80211_HDR_ADDRESS3(nullfunc, mac->bssid);
457 449
458 SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1RsvdPageLoc, NULL_PG); 450 SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1rsvdpageloc, NULL_PG);
459 451
460 /*--------------------------------------------------------- 452 /*---------------------------------------------------------
461 (4) probe response 453 * (4) probe response
462 ---------------------------------------------------------- 454 *----------------------------------------------------------
463 */ 455 */
464 p_probersp = &reserved_page_packet[PROBERSP_PG * 128]; 456 p_probersp = &reserved_page_packet[PROBERSP_PG * 128];
465 SET_80211_HDR_ADDRESS1(p_probersp, mac->bssid); 457 SET_80211_HDR_ADDRESS1(p_probersp, mac->bssid);
466 SET_80211_HDR_ADDRESS2(p_probersp, mac->mac_addr); 458 SET_80211_HDR_ADDRESS2(p_probersp, mac->mac_addr);
467 SET_80211_HDR_ADDRESS3(p_probersp, mac->bssid); 459 SET_80211_HDR_ADDRESS3(p_probersp, mac->bssid);
468 460
469 SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1RsvdPageLoc, PROBERSP_PG); 461 SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1rsvdpageloc, PROBERSP_PG);
470 462
471 totalpacketlen = TOTAL_RESERVED_PKT_LEN; 463 totalpacketlen = TOTAL_RESERVED_PKT_LEN;
472 464
473 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD, 465 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
474 "rtl8723ae_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n", 466 "rtl8723e_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
475 &reserved_page_packet[0], totalpacketlen); 467 &reserved_page_packet[0], totalpacketlen);
476 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG, 468 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
477 "rtl8723ae_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n", 469 "rtl8723e_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
478 u1RsvdPageLoc, 3); 470 u1rsvdpageloc, 3);
479 471
480 skb = dev_alloc_skb(totalpacketlen); 472 skb = dev_alloc_skb(totalpacketlen);
481 memcpy((u8 *) skb_put(skb, totalpacketlen), 473 memcpy((u8 *)skb_put(skb, totalpacketlen),
482 &reserved_page_packet, totalpacketlen); 474 &reserved_page_packet, totalpacketlen);
483 475
484 rtstatus = _rtl8723ae_cmd_send_packet(hw, skb); 476 rtstatus = rtl8723_cmd_send_packet(hw, skb);
485 477
486 if (rtstatus) 478 if (rtstatus)
487 dlok = true; 479 b_dlok = true;
488 480
489 if (dlok) { 481 if (b_dlok) {
490 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 482 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
491 "Set RSVD page location to Fw.\n"); 483 "Set RSVD page location to Fw.\n");
492 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG, 484 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
493 "H2C_RSVDPAGE:\n", 485 "H2C_RSVDPAGE:\n",
494 u1RsvdPageLoc, 3); 486 u1rsvdpageloc, 3);
495 rtl8723ae_fill_h2c_cmd(hw, H2C_RSVDPAGE, 487 rtl8723e_fill_h2c_cmd(hw, H2C_RSVDPAGE,
496 sizeof(u1RsvdPageLoc), u1RsvdPageLoc); 488 sizeof(u1rsvdpageloc), u1rsvdpageloc);
497 } else 489 } else
498 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 490 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
499 "Set RSVD page location to Fw FAIL!!!!!!.\n"); 491 "Set RSVD page location to Fw FAIL!!!!!!.\n");
500} 492}
501 493
502void rtl8723ae_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus) 494void rtl8723e_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus)
503{ 495{
504 u8 u1_joinbssrpt_parm[1] = { 0 }; 496 u8 u1_joinbssrpt_parm[1] = { 0 };
505 497
506 SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(u1_joinbssrpt_parm, mstatus); 498 SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(u1_joinbssrpt_parm, mstatus);
507 499
508 rtl8723ae_fill_h2c_cmd(hw, H2C_JOINBSSRPT, 1, u1_joinbssrpt_parm); 500 rtl8723e_fill_h2c_cmd(hw, H2C_JOINBSSRPT, 1, u1_joinbssrpt_parm);
509} 501}
510 502
511static void rtl8723e_set_p2p_ctw_period_cmd(struct ieee80211_hw *hw, 503static void rtl8723e_set_p2p_ctw_period_cmd(struct ieee80211_hw *hw,
512 u8 ctwindow) 504 u8 ctwindow)
513{ 505{
514 u8 u1_ctwindow_period[1] = {ctwindow}; 506 u8 u1_ctwindow_period[1] = { ctwindow};
507
508 rtl8723e_fill_h2c_cmd(hw, H2C_P2P_PS_CTW_CMD, 1, u1_ctwindow_period);
515 509
516 rtl8723ae_fill_h2c_cmd(hw, H2C_P2P_PS_CTW_CMD, 1, u1_ctwindow_period);
517} 510}
518 511
519void rtl8723ae_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state) 512void rtl8723e_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state)
520{ 513{
521 struct rtl_priv *rtlpriv = rtl_priv(hw); 514 struct rtl_priv *rtlpriv = rtl_priv(hw);
522 struct rtl_ps_ctl *rtlps = rtl_psc(rtl_priv(hw)); 515 struct rtl_ps_ctl *rtlps = rtl_psc(rtl_priv(hw));
@@ -530,7 +523,7 @@ void rtl8723ae_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state)
530 switch (p2p_ps_state) { 523 switch (p2p_ps_state) {
531 case P2P_PS_DISABLE: 524 case P2P_PS_DISABLE:
532 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_DISABLE\n"); 525 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_DISABLE\n");
533 memset(p2p_ps_offload, 0, sizeof(struct p2p_ps_offload_t)); 526 memset(p2p_ps_offload, 0, sizeof(*p2p_ps_offload));
534 break; 527 break;
535 case P2P_PS_ENABLE: 528 case P2P_PS_ENABLE:
536 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_ENABLE\n"); 529 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_ENABLE\n");
@@ -542,7 +535,7 @@ void rtl8723ae_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state)
542 } 535 }
543 536
544 /* hw only support 2 set of NoA */ 537 /* hw only support 2 set of NoA */
545 for (i = 0; i < p2pinfo->noa_num; i++) { 538 for (i = 0 ; i < p2pinfo->noa_num ; i++) {
546 /* To control the register setting for which NOA*/ 539 /* To control the register setting for which NOA*/
547 rtl_write_byte(rtlpriv, 0x5cf, (i << 4)); 540 rtl_write_byte(rtlpriv, 0x5cf, (i << 4));
548 if (i == 0) 541 if (i == 0)
@@ -561,27 +554,33 @@ void rtl8723ae_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state)
561 554
562 start_time = p2pinfo->noa_start_time[i]; 555 start_time = p2pinfo->noa_start_time[i];
563 if (p2pinfo->noa_count_type[i] != 1) { 556 if (p2pinfo->noa_count_type[i] != 1) {
564 while (start_time <= (tsf_low+(50*1024))) { 557 while (start_time <=
565 start_time += p2pinfo->noa_interval[i]; 558 (tsf_low+(50*1024))) {
559 start_time +=
560 p2pinfo->noa_interval[i];
566 if (p2pinfo->noa_count_type[i] != 255) 561 if (p2pinfo->noa_count_type[i] != 255)
567 p2pinfo->noa_count_type[i]--; 562 p2pinfo->noa_count_type[i]--;
568 } 563 }
569 } 564 }
570 rtl_write_dword(rtlpriv, 0x5E8, start_time); 565 rtl_write_dword(rtlpriv, 0x5E8, start_time);
571 rtl_write_dword(rtlpriv, 0x5EC, 566 rtl_write_dword(rtlpriv, 0x5EC,
572 p2pinfo->noa_count_type[i]); 567 p2pinfo->noa_count_type[i]);
568
573 } 569 }
570
574 if ((p2pinfo->opp_ps == 1) || (p2pinfo->noa_num > 0)) { 571 if ((p2pinfo->opp_ps == 1) || (p2pinfo->noa_num > 0)) {
575 /* rst p2p circuit */ 572 /* rst p2p circuit */
576 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, BIT(4)); 573 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, BIT(4));
577 574
578 p2p_ps_offload->offload_en = 1; 575 p2p_ps_offload->offload_en = 1;
576
579 if (P2P_ROLE_GO == rtlpriv->mac80211.p2p) { 577 if (P2P_ROLE_GO == rtlpriv->mac80211.p2p) {
580 p2p_ps_offload->role = 1; 578 p2p_ps_offload->role = 1;
581 p2p_ps_offload->allstasleep = 0; 579 p2p_ps_offload->allstasleep = 0;
582 } else { 580 } else {
583 p2p_ps_offload->role = 0; 581 p2p_ps_offload->role = 0;
584 } 582 }
583
585 p2p_ps_offload->discovery = 0; 584 p2p_ps_offload->discovery = 0;
586 } 585 }
587 break; 586 break;
@@ -597,26 +596,7 @@ void rtl8723ae_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state)
597 default: 596 default:
598 break; 597 break;
599 } 598 }
600 rtl8723ae_fill_h2c_cmd(hw, H2C_P2P_PS_OFFLOAD, 1, (u8 *)p2p_ps_offload);
601}
602
603void rtl8723ae_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode)
604{
605 struct rtl_priv *rtlpriv = rtl_priv(hw);
606 u8 u1_h2c_set_pwrmode[3] = { 0 };
607 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
608
609 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "FW LPS mode = %d\n", mode);
610 599
611 SET_H2CCMD_PWRMODE_PARM_MODE(u1_h2c_set_pwrmode, mode); 600 rtl8723e_fill_h2c_cmd(hw, H2C_P2P_PS_OFFLOAD, 1, (u8 *)p2p_ps_offload);
612 SET_H2CCMD_PWRMODE_PARM_SMART_PS_23A(u1_h2c_set_pwrmode,
613 (rtlpriv->mac80211.p2p) ?
614 ppsc->smart_ps : 1);
615 SET_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(u1_h2c_set_pwrmode,
616 ppsc->reg_max_lps_awakeintvl);
617 601
618 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
619 "rtl8723ae_set_fw_rsvdpagepkt(): u1_h2c_set_pwrmode\n",
620 u1_h2c_set_pwrmode, 3);
621 rtl8723ae_fill_h2c_cmd(hw, H2C_SETPWRMODE, 3, u1_h2c_set_pwrmode);
622} 602}
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/fw.h b/drivers/net/wireless/rtlwifi/rtl8723ae/fw.h
index d355b85dd9fe..ad70f2b3d9f0 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/fw.h
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/fw.h
@@ -24,50 +24,28 @@
24 * Hsinchu 300, Taiwan. 24 * Hsinchu 300, Taiwan.
25 * Larry Finger <Larry.Finger@lwfinger.net> 25 * Larry Finger <Larry.Finger@lwfinger.net>
26 * 26 *
27 **************************************************************************** 27 *****************************************************************************/
28 */
29 28
30#ifndef __RTL92C__FW__H__ 29#ifndef __RTL92C__FW__H__
31#define __RTL92C__FW__H__ 30#define __RTL92C__FW__H__
32 31
32#define FW_8192C_SIZE 0x3000
33#define FW_8192C_START_ADDRESS 0x1000 33#define FW_8192C_START_ADDRESS 0x1000
34#define FW_8192C_END_ADDRESS 0x3FFF 34#define FW_8192C_END_ADDRESS 0x3FFF
35#define FW_8192C_PAGE_SIZE 4096 35#define FW_8192C_PAGE_SIZE 4096
36#define FW_8192C_POLLING_DELAY 5 36#define FW_8192C_POLLING_DELAY 5
37#define FW_8192C_POLLING_TIMEOUT_COUNT 6000 37#define FW_8192C_POLLING_TIMEOUT_COUNT 1000
38 38
39#define BEACON_PG 0 39#define IS_FW_HEADER_EXIST(_pfwhdr) \
40#define PSPOLL_PG 2 40 ((_pfwhdr->signature&0xFFFF) == 0x2300 ||\
41#define NULL_PG 3 41 (_pfwhdr->signature&0xFFFF) == 0x2301 ||\
42#define PROBERSP_PG 4 /* ->5 */ 42 (_pfwhdr->signature&0xFFFF) == 0x2302)
43 43
44#define TOTAL_RESERVED_PKT_LEN 768 44#define pagenum_128(_len) (u32)(((_len)>>7) + ((_len)&0x7F ? 1 : 0))
45
46#define IS_FW_HEADER_EXIST(_pfwhdr) \
47 ((_pfwhdr->signature&0xFF00) == 0x2300)
48
49struct rtl8723ae_firmware_header {
50 u16 signature;
51 u8 category;
52 u8 function;
53 u16 version;
54 u8 subversion;
55 u8 rsvd1;
56 u8 month;
57 u8 date;
58 u8 hour;
59 u8 minute;
60 u16 ramcodeSize;
61 u16 rsvd2;
62 u32 svnindex;
63 u32 rsvd3;
64 u32 rsvd4;
65 u32 rsvd5;
66};
67 45
68#define SET_H2CCMD_PWRMODE_PARM_MODE(__ph2ccmd, __val) \ 46#define SET_H2CCMD_PWRMODE_PARM_MODE(__ph2ccmd, __val) \
69 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val) 47 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
70#define SET_H2CCMD_PWRMODE_PARM_SMART_PS_23A(__ph2ccmd, __val) \ 48#define SET_H2CCMD_PWRMODE_PARM_SMART_PS(__ph2ccmd, __val) \
71 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+1, 0, 8, __val) 49 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+1, 0, 8, __val)
72#define SET_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__ph2ccmd, __val) \ 50#define SET_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__ph2ccmd, __val) \
73 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+2, 0, 8, __val) 51 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+2, 0, 8, __val)
@@ -80,11 +58,10 @@ struct rtl8723ae_firmware_header {
80#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__ph2ccmd, __val) \ 58#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__ph2ccmd, __val) \
81 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+2, 0, 8, __val) 59 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+2, 0, 8, __val)
82 60
83void rtl8723ae_fill_h2c_cmd(struct ieee80211_hw *hw, u8 element_id, 61void rtl8723e_fill_h2c_cmd(struct ieee80211_hw *hw, u8 element_id,
84 u32 cmd_len, u8 *p_cmdbuffer); 62 u32 cmd_len, u8 *p_cmdbuffer);
85void rtl8723ae_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode); 63void rtl8723e_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode);
86void rtl8723ae_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished); 64void rtl8723e_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished);
87void rtl8723ae_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus); 65void rtl8723e_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus);
88void rtl8723ae_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state); 66void rtl8723e_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state);
89
90#endif 67#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/hal_bt_coexist.c b/drivers/net/wireless/rtlwifi/rtl8723ae/hal_bt_coexist.c
index 5b4a714f3c8c..5aac45d5a974 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/hal_bt_coexist.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/hal_bt_coexist.c
@@ -11,10 +11,6 @@
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details. 12 * more details.
13 * 13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the 14 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE. 15 * file called LICENSE.
20 * 16 *
@@ -31,96 +27,102 @@
31#include "../pci.h" 27#include "../pci.h"
32#include "dm.h" 28#include "dm.h"
33#include "fw.h" 29#include "fw.h"
34#include "../rtl8723com/fw_common.h"
35#include "phy.h" 30#include "phy.h"
36#include "reg.h" 31#include "reg.h"
37#include "hal_btc.h" 32#include "hal_btc.h"
38 33
39void rtl8723ae_dm_bt_reject_ap_aggregated_packet(struct ieee80211_hw *hw, 34static bool bt_operation_on;
40 bool reject) 35
36void rtl8723e_dm_bt_reject_ap_aggregated_packet(struct ieee80211_hw *hw,
37 bool b_reject)
41{ 38{
42} 39}
43 40
44void _rtl8723_dm_bt_check_wifi_state(struct ieee80211_hw *hw) 41void _rtl8723_dm_bt_check_wifi_state(struct ieee80211_hw *hw)
45{ 42{
46 struct rtl_priv *rtlpriv = rtl_priv(hw); 43 struct rtl_priv *rtlpriv = rtl_priv(hw);
47 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
48 struct rtl_phy *rtlphy = &(rtlpriv->phy); 44 struct rtl_phy *rtlphy = &(rtlpriv->phy);
49 45
50 if (rtlpriv->link_info.busytraffic) { 46 if (rtlpriv->link_info.busytraffic) {
51 rtlpcipriv->bt_coexist.cstate &= ~BT_COEX_STATE_WIFI_IDLE; 47 rtlpriv->btcoexist.cstate &=
48 ~BT_COEX_STATE_WIFI_IDLE;
52 49
53 if (rtlpriv->link_info.tx_busy_traffic) 50 if (rtlpriv->link_info.tx_busy_traffic)
54 rtlpcipriv->bt_coexist.cstate |= 51 rtlpriv->btcoexist.cstate |=
55 BT_COEX_STATE_WIFI_UPLINK; 52 BT_COEX_STATE_WIFI_UPLINK;
56 else 53 else
57 rtlpcipriv->bt_coexist.cstate &= 54 rtlpriv->btcoexist.cstate &=
58 ~BT_COEX_STATE_WIFI_UPLINK; 55 ~BT_COEX_STATE_WIFI_UPLINK;
59 56
60 if (rtlpriv->link_info.rx_busy_traffic) 57 if (rtlpriv->link_info.rx_busy_traffic)
61 rtlpcipriv->bt_coexist.cstate |= 58 rtlpriv->btcoexist.cstate |=
62 BT_COEX_STATE_WIFI_DOWNLINK; 59 BT_COEX_STATE_WIFI_DOWNLINK;
63 else 60 else
64 rtlpcipriv->bt_coexist.cstate &= 61 rtlpriv->btcoexist.cstate &=
65 ~BT_COEX_STATE_WIFI_DOWNLINK; 62 ~BT_COEX_STATE_WIFI_DOWNLINK;
66 } else { 63 } else {
67 rtlpcipriv->bt_coexist.cstate |= BT_COEX_STATE_WIFI_IDLE; 64 rtlpriv->btcoexist.cstate |= BT_COEX_STATE_WIFI_IDLE;
68 rtlpcipriv->bt_coexist.cstate &= ~BT_COEX_STATE_WIFI_UPLINK; 65 rtlpriv->btcoexist.cstate &=
69 rtlpcipriv->bt_coexist.cstate &= ~BT_COEX_STATE_WIFI_DOWNLINK; 66 ~BT_COEX_STATE_WIFI_UPLINK;
67 rtlpriv->btcoexist.cstate &=
68 ~BT_COEX_STATE_WIFI_DOWNLINK;
70 } 69 }
71 70
72 if (rtlpriv->mac80211.mode == WIRELESS_MODE_G || 71 if (rtlpriv->mac80211.mode == WIRELESS_MODE_G ||
73 rtlpriv->mac80211.mode == WIRELESS_MODE_B) { 72 rtlpriv->mac80211.mode == WIRELESS_MODE_B) {
74 rtlpcipriv->bt_coexist.cstate |= BT_COEX_STATE_WIFI_LEGACY; 73 rtlpriv->btcoexist.cstate |=
75 rtlpcipriv->bt_coexist.cstate &= ~BT_COEX_STATE_WIFI_HT20; 74 BT_COEX_STATE_WIFI_LEGACY;
76 rtlpcipriv->bt_coexist.cstate &= ~BT_COEX_STATE_WIFI_HT40; 75 rtlpriv->btcoexist.cstate &=
76 ~BT_COEX_STATE_WIFI_HT20;
77 rtlpriv->btcoexist.cstate &=
78 ~BT_COEX_STATE_WIFI_HT40;
77 } else { 79 } else {
78 rtlpcipriv->bt_coexist.cstate &= ~BT_COEX_STATE_WIFI_LEGACY; 80 rtlpriv->btcoexist.cstate &=
81 ~BT_COEX_STATE_WIFI_LEGACY;
79 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) { 82 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
80 rtlpcipriv->bt_coexist.cstate |= 83 rtlpriv->btcoexist.cstate |=
81 BT_COEX_STATE_WIFI_HT40; 84 BT_COEX_STATE_WIFI_HT40;
82 rtlpcipriv->bt_coexist.cstate &= 85 rtlpriv->btcoexist.cstate &=
83 ~BT_COEX_STATE_WIFI_HT20; 86 ~BT_COEX_STATE_WIFI_HT20;
84 } else { 87 } else {
85 rtlpcipriv->bt_coexist.cstate |= 88 rtlpriv->btcoexist.cstate |=
86 BT_COEX_STATE_WIFI_HT20; 89 BT_COEX_STATE_WIFI_HT20;
87 rtlpcipriv->bt_coexist.cstate &= 90 rtlpriv->btcoexist.cstate &=
88 ~BT_COEX_STATE_WIFI_HT40; 91 ~BT_COEX_STATE_WIFI_HT40;
89 } 92 }
90 } 93 }
91 94
92 if (rtlpriv->bt_operation_on) 95 if (bt_operation_on)
93 rtlpcipriv->bt_coexist.cstate |= BT_COEX_STATE_BT30; 96 rtlpriv->btcoexist.cstate |= BT_COEX_STATE_BT30;
94 else 97 else
95 rtlpcipriv->bt_coexist.cstate &= ~BT_COEX_STATE_BT30; 98 rtlpriv->btcoexist.cstate &= ~BT_COEX_STATE_BT30;
96} 99}
97 100
98u8 rtl8723ae_dm_bt_check_coex_rssi_state1(struct ieee80211_hw *hw, 101u8 rtl8723e_dm_bt_check_coex_rssi_state1(struct ieee80211_hw *hw,
99 u8 level_num, u8 rssi_thresh, 102 u8 level_num, u8 rssi_thresh,
100 u8 rssi_thresh1) 103 u8 rssi_thresh1)
101 104
102{ 105{
103 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
104 struct rtl_priv *rtlpriv = rtl_priv(hw); 106 struct rtl_priv *rtlpriv = rtl_priv(hw);
105 long smooth; 107 long undecoratedsmoothed_pwdb;
106 u8 bt_rssi_state = 0; 108 u8 bt_rssi_state = 0;
107 109
108 smooth = rtl8723ae_dm_bt_get_rx_ss(hw); 110 undecoratedsmoothed_pwdb = rtl8723e_dm_bt_get_rx_ss(hw);
109 111
110 if (level_num == 2) { 112 if (level_num == 2) {
111 rtlpcipriv->bt_coexist.cstate &= 113 rtlpriv->btcoexist.cstate &=
112 ~BT_COEX_STATE_WIFI_RSSI_1_MEDIUM; 114 ~BT_COEX_STATE_WIFI_RSSI_1_MEDIUM;
113 115
114 if ((rtlpcipriv->bt_coexist.bt_pre_rssi_state == 116 if ((rtlpriv->btcoexist.bt_pre_rssi_state ==
115 BT_RSSI_STATE_LOW) || 117 BT_RSSI_STATE_LOW) ||
116 (rtlpcipriv->bt_coexist.bt_pre_rssi_state == 118 (rtlpriv->btcoexist.bt_pre_rssi_state ==
117 BT_RSSI_STATE_STAY_LOW)) { 119 BT_RSSI_STATE_STAY_LOW)) {
118 if (smooth >= (rssi_thresh + 120 if (undecoratedsmoothed_pwdb >=
119 BT_FW_COEX_THRESH_TOL)) { 121 (rssi_thresh + BT_FW_COEX_THRESH_TOL)) {
120 bt_rssi_state = BT_RSSI_STATE_HIGH; 122 bt_rssi_state = BT_RSSI_STATE_HIGH;
121 rtlpcipriv->bt_coexist.cstate |= 123 rtlpriv->btcoexist.cstate |=
122 BT_COEX_STATE_WIFI_RSSI_1_HIGH; 124 BT_COEX_STATE_WIFI_RSSI_1_HIGH;
123 rtlpcipriv->bt_coexist.cstate &= 125 rtlpriv->btcoexist.cstate &=
124 ~BT_COEX_STATE_WIFI_RSSI_1_LOW; 126 ~BT_COEX_STATE_WIFI_RSSI_1_LOW;
125 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 127 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
126 "[DM][BT], RSSI_1 state switch to High\n"); 128 "[DM][BT], RSSI_1 state switch to High\n");
@@ -130,12 +132,12 @@ u8 rtl8723ae_dm_bt_check_coex_rssi_state1(struct ieee80211_hw *hw,
130 "[DM][BT], RSSI_1 state stay at Low\n"); 132 "[DM][BT], RSSI_1 state stay at Low\n");
131 } 133 }
132 } else { 134 } else {
133 if (smooth < rssi_thresh) { 135 if (undecoratedsmoothed_pwdb < rssi_thresh) {
134 bt_rssi_state = BT_RSSI_STATE_LOW; 136 bt_rssi_state = BT_RSSI_STATE_LOW;
135 rtlpcipriv->bt_coexist.cstate |= 137 rtlpriv->btcoexist.cstate |=
136 BT_COEX_STATE_WIFI_RSSI_1_LOW; 138 BT_COEX_STATE_WIFI_RSSI_1_LOW;
137 rtlpcipriv->bt_coexist.cstate &= 139 rtlpriv->btcoexist.cstate &=
138 ~BT_COEX_STATE_WIFI_RSSI_1_HIGH; 140 ~BT_COEX_STATE_WIFI_RSSI_1_HIGH;
139 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 141 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
140 "[DM][BT], RSSI_1 state switch to Low\n"); 142 "[DM][BT], RSSI_1 state switch to Low\n");
141 } else { 143 } else {
@@ -148,22 +150,22 @@ u8 rtl8723ae_dm_bt_check_coex_rssi_state1(struct ieee80211_hw *hw,
148 if (rssi_thresh > rssi_thresh1) { 150 if (rssi_thresh > rssi_thresh1) {
149 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 151 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
150 "[DM][BT], RSSI_1 thresh error!!\n"); 152 "[DM][BT], RSSI_1 thresh error!!\n");
151 return rtlpcipriv->bt_coexist.bt_pre_rssi_state; 153 return rtlpriv->btcoexist.bt_pre_rssi_state;
152 } 154 }
153 155
154 if ((rtlpcipriv->bt_coexist.bt_pre_rssi_state == 156 if ((rtlpriv->btcoexist.bt_pre_rssi_state ==
155 BT_RSSI_STATE_LOW) || 157 BT_RSSI_STATE_LOW) ||
156 (rtlpcipriv->bt_coexist.bt_pre_rssi_state == 158 (rtlpriv->btcoexist.bt_pre_rssi_state ==
157 BT_RSSI_STATE_STAY_LOW)) { 159 BT_RSSI_STATE_STAY_LOW)) {
158 if (smooth >= 160 if (undecoratedsmoothed_pwdb >=
159 (rssi_thresh+BT_FW_COEX_THRESH_TOL)) { 161 (rssi_thresh+BT_FW_COEX_THRESH_TOL)) {
160 bt_rssi_state = BT_RSSI_STATE_MEDIUM; 162 bt_rssi_state = BT_RSSI_STATE_MEDIUM;
161 rtlpcipriv->bt_coexist.cstate |= 163 rtlpriv->btcoexist.cstate |=
162 BT_COEX_STATE_WIFI_RSSI_1_MEDIUM; 164 BT_COEX_STATE_WIFI_RSSI_1_MEDIUM;
163 rtlpcipriv->bt_coexist.cstate &= 165 rtlpriv->btcoexist.cstate &=
164 ~BT_COEX_STATE_WIFI_RSSI_1_LOW; 166 ~BT_COEX_STATE_WIFI_RSSI_1_LOW;
165 rtlpcipriv->bt_coexist.cstate &= 167 rtlpriv->btcoexist.cstate &=
166 ~BT_COEX_STATE_WIFI_RSSI_1_HIGH; 168 ~BT_COEX_STATE_WIFI_RSSI_1_HIGH;
167 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 169 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
168 "[DM][BT], RSSI_1 state switch to Medium\n"); 170 "[DM][BT], RSSI_1 state switch to Medium\n");
169 } else { 171 } else {
@@ -171,28 +173,28 @@ u8 rtl8723ae_dm_bt_check_coex_rssi_state1(struct ieee80211_hw *hw,
171 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 173 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
172 "[DM][BT], RSSI_1 state stay at Low\n"); 174 "[DM][BT], RSSI_1 state stay at Low\n");
173 } 175 }
174 } else if ((rtlpcipriv->bt_coexist.bt_pre_rssi_state == 176 } else if ((rtlpriv->btcoexist.bt_pre_rssi_state ==
175 BT_RSSI_STATE_MEDIUM) || 177 BT_RSSI_STATE_MEDIUM) ||
176 (rtlpcipriv->bt_coexist.bt_pre_rssi_state == 178 (rtlpriv->btcoexist.bt_pre_rssi_state ==
177 BT_RSSI_STATE_STAY_MEDIUM)) { 179 BT_RSSI_STATE_STAY_MEDIUM)) {
178 if (smooth >= (rssi_thresh1 + 180 if (undecoratedsmoothed_pwdb >=
179 BT_FW_COEX_THRESH_TOL)) { 181 (rssi_thresh1 + BT_FW_COEX_THRESH_TOL)) {
180 bt_rssi_state = BT_RSSI_STATE_HIGH; 182 bt_rssi_state = BT_RSSI_STATE_HIGH;
181 rtlpcipriv->bt_coexist.cstate |= 183 rtlpriv->btcoexist.cstate |=
182 BT_COEX_STATE_WIFI_RSSI_1_HIGH; 184 BT_COEX_STATE_WIFI_RSSI_1_HIGH;
183 rtlpcipriv->bt_coexist.cstate &= 185 rtlpriv->btcoexist.cstate &=
184 ~BT_COEX_STATE_WIFI_RSSI_1_LOW; 186 ~BT_COEX_STATE_WIFI_RSSI_1_LOW;
185 rtlpcipriv->bt_coexist.cstate &= 187 rtlpriv->btcoexist.cstate &=
186 ~BT_COEX_STATE_WIFI_RSSI_1_MEDIUM; 188 ~BT_COEX_STATE_WIFI_RSSI_1_MEDIUM;
187 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 189 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
188 "[DM][BT], RSSI_1 state switch to High\n"); 190 "[DM][BT], RSSI_1 state switch to High\n");
189 } else if (smooth < rssi_thresh) { 191 } else if (undecoratedsmoothed_pwdb < rssi_thresh) {
190 bt_rssi_state = BT_RSSI_STATE_LOW; 192 bt_rssi_state = BT_RSSI_STATE_LOW;
191 rtlpcipriv->bt_coexist.cstate |= 193 rtlpriv->btcoexist.cstate |=
192 BT_COEX_STATE_WIFI_RSSI_1_LOW; 194 BT_COEX_STATE_WIFI_RSSI_1_LOW;
193 rtlpcipriv->bt_coexist.cstate &= 195 rtlpriv->btcoexist.cstate &=
194 ~BT_COEX_STATE_WIFI_RSSI_1_HIGH; 196 ~BT_COEX_STATE_WIFI_RSSI_1_HIGH;
195 rtlpcipriv->bt_coexist.cstate &= 197 rtlpriv->btcoexist.cstate &=
196 ~BT_COEX_STATE_WIFI_RSSI_1_MEDIUM; 198 ~BT_COEX_STATE_WIFI_RSSI_1_MEDIUM;
197 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 199 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
198 "[DM][BT], RSSI_1 state switch to Low\n"); 200 "[DM][BT], RSSI_1 state switch to Low\n");
@@ -202,13 +204,13 @@ u8 rtl8723ae_dm_bt_check_coex_rssi_state1(struct ieee80211_hw *hw,
202 "[DM][BT], RSSI_1 state stay at Medium\n"); 204 "[DM][BT], RSSI_1 state stay at Medium\n");
203 } 205 }
204 } else { 206 } else {
205 if (smooth < rssi_thresh1) { 207 if (undecoratedsmoothed_pwdb < rssi_thresh1) {
206 bt_rssi_state = BT_RSSI_STATE_MEDIUM; 208 bt_rssi_state = BT_RSSI_STATE_MEDIUM;
207 rtlpcipriv->bt_coexist.cstate |= 209 rtlpriv->btcoexist.cstate |=
208 BT_COEX_STATE_WIFI_RSSI_1_MEDIUM; 210 BT_COEX_STATE_WIFI_RSSI_1_MEDIUM;
209 rtlpcipriv->bt_coexist.cstate &= 211 rtlpriv->btcoexist.cstate &=
210 ~BT_COEX_STATE_WIFI_RSSI_1_HIGH; 212 ~BT_COEX_STATE_WIFI_RSSI_1_HIGH;
211 rtlpcipriv->bt_coexist.cstate &= 213 rtlpriv->btcoexist.cstate &=
212 ~BT_COEX_STATE_WIFI_RSSI_1_LOW; 214 ~BT_COEX_STATE_WIFI_RSSI_1_LOW;
213 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 215 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
214 "[DM][BT], RSSI_1 state switch to Medium\n"); 216 "[DM][BT], RSSI_1 state switch to Medium\n");
@@ -219,38 +221,37 @@ u8 rtl8723ae_dm_bt_check_coex_rssi_state1(struct ieee80211_hw *hw,
219 } 221 }
220 } 222 }
221 } 223 }
222 224 rtlpriv->btcoexist.bt_pre_rssi_state1 = bt_rssi_state;
223 rtlpcipriv->bt_coexist.bt_pre_rssi_state1 = bt_rssi_state;
224 225
225 return bt_rssi_state; 226 return bt_rssi_state;
226} 227}
227 228
228u8 rtl8723ae_dm_bt_check_coex_rssi_state(struct ieee80211_hw *hw, 229u8 rtl8723e_dm_bt_check_coex_rssi_state(struct ieee80211_hw *hw,
229 u8 level_num, u8 rssi_thresh, 230 u8 level_num,
230 u8 rssi_thresh1) 231 u8 rssi_thresh,
232 u8 rssi_thresh1)
231{ 233{
232 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
233 struct rtl_priv *rtlpriv = rtl_priv(hw); 234 struct rtl_priv *rtlpriv = rtl_priv(hw);
234 long smooth; 235 long undecoratedsmoothed_pwdb = 0;
235 u8 bt_rssi_state = 0; 236 u8 bt_rssi_state = 0;
236 237
237 smooth = rtl8723ae_dm_bt_get_rx_ss(hw); 238 undecoratedsmoothed_pwdb = rtl8723e_dm_bt_get_rx_ss(hw);
238 239
239 if (level_num == 2) { 240 if (level_num == 2) {
240 rtlpcipriv->bt_coexist.cstate &= 241 rtlpriv->btcoexist.cstate &=
241 ~BT_COEX_STATE_WIFI_RSSI_MEDIUM; 242 ~BT_COEX_STATE_WIFI_RSSI_MEDIUM;
242 243
243 if ((rtlpcipriv->bt_coexist.bt_pre_rssi_state == 244 if ((rtlpriv->btcoexist.bt_pre_rssi_state ==
244 BT_RSSI_STATE_LOW) || 245 BT_RSSI_STATE_LOW) ||
245 (rtlpcipriv->bt_coexist.bt_pre_rssi_state == 246 (rtlpriv->btcoexist.bt_pre_rssi_state ==
246 BT_RSSI_STATE_STAY_LOW)){ 247 BT_RSSI_STATE_STAY_LOW)) {
247 if (smooth >= 248 if (undecoratedsmoothed_pwdb >=
248 (rssi_thresh + BT_FW_COEX_THRESH_TOL)) { 249 (rssi_thresh + BT_FW_COEX_THRESH_TOL)) {
249 bt_rssi_state = BT_RSSI_STATE_HIGH; 250 bt_rssi_state = BT_RSSI_STATE_HIGH;
250 rtlpcipriv->bt_coexist.cstate |= 251 rtlpriv->btcoexist.cstate
251 BT_COEX_STATE_WIFI_RSSI_HIGH; 252 |= BT_COEX_STATE_WIFI_RSSI_HIGH;
252 rtlpcipriv->bt_coexist.cstate &= 253 rtlpriv->btcoexist.cstate
253 ~BT_COEX_STATE_WIFI_RSSI_LOW; 254 &= ~BT_COEX_STATE_WIFI_RSSI_LOW;
254 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 255 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
255 "[DM][BT], RSSI state switch to High\n"); 256 "[DM][BT], RSSI state switch to High\n");
256 } else { 257 } else {
@@ -259,12 +260,12 @@ u8 rtl8723ae_dm_bt_check_coex_rssi_state(struct ieee80211_hw *hw,
259 "[DM][BT], RSSI state stay at Low\n"); 260 "[DM][BT], RSSI state stay at Low\n");
260 } 261 }
261 } else { 262 } else {
262 if (smooth < rssi_thresh) { 263 if (undecoratedsmoothed_pwdb < rssi_thresh) {
263 bt_rssi_state = BT_RSSI_STATE_LOW; 264 bt_rssi_state = BT_RSSI_STATE_LOW;
264 rtlpcipriv->bt_coexist.cstate |= 265 rtlpriv->btcoexist.cstate
265 BT_COEX_STATE_WIFI_RSSI_LOW; 266 |= BT_COEX_STATE_WIFI_RSSI_LOW;
266 rtlpcipriv->bt_coexist.cstate &= 267 rtlpriv->btcoexist.cstate
267 ~BT_COEX_STATE_WIFI_RSSI_HIGH; 268 &= ~BT_COEX_STATE_WIFI_RSSI_HIGH;
268 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 269 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
269 "[DM][BT], RSSI state switch to Low\n"); 270 "[DM][BT], RSSI state switch to Low\n");
270 } else { 271 } else {
@@ -277,20 +278,20 @@ u8 rtl8723ae_dm_bt_check_coex_rssi_state(struct ieee80211_hw *hw,
277 if (rssi_thresh > rssi_thresh1) { 278 if (rssi_thresh > rssi_thresh1) {
278 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 279 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
279 "[DM][BT], RSSI thresh error!!\n"); 280 "[DM][BT], RSSI thresh error!!\n");
280 return rtlpcipriv->bt_coexist.bt_pre_rssi_state; 281 return rtlpriv->btcoexist.bt_pre_rssi_state;
281 } 282 }
282 if ((rtlpcipriv->bt_coexist.bt_pre_rssi_state == 283 if ((rtlpriv->btcoexist.bt_pre_rssi_state ==
283 BT_RSSI_STATE_LOW) || 284 BT_RSSI_STATE_LOW) ||
284 (rtlpcipriv->bt_coexist.bt_pre_rssi_state == 285 (rtlpriv->btcoexist.bt_pre_rssi_state ==
285 BT_RSSI_STATE_STAY_LOW)) { 286 BT_RSSI_STATE_STAY_LOW)) {
286 if (smooth >= 287 if (undecoratedsmoothed_pwdb >=
287 (rssi_thresh + BT_FW_COEX_THRESH_TOL)) { 288 (rssi_thresh + BT_FW_COEX_THRESH_TOL)) {
288 bt_rssi_state = BT_RSSI_STATE_MEDIUM; 289 bt_rssi_state = BT_RSSI_STATE_MEDIUM;
289 rtlpcipriv->bt_coexist.cstate 290 rtlpriv->btcoexist.cstate
290 |= BT_COEX_STATE_WIFI_RSSI_MEDIUM; 291 |= BT_COEX_STATE_WIFI_RSSI_MEDIUM;
291 rtlpcipriv->bt_coexist.cstate 292 rtlpriv->btcoexist.cstate
292 &= ~BT_COEX_STATE_WIFI_RSSI_LOW; 293 &= ~BT_COEX_STATE_WIFI_RSSI_LOW;
293 rtlpcipriv->bt_coexist.cstate 294 rtlpriv->btcoexist.cstate
294 &= ~BT_COEX_STATE_WIFI_RSSI_HIGH; 295 &= ~BT_COEX_STATE_WIFI_RSSI_HIGH;
295 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 296 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
296 "[DM][BT], RSSI state switch to Medium\n"); 297 "[DM][BT], RSSI state switch to Medium\n");
@@ -299,28 +300,28 @@ u8 rtl8723ae_dm_bt_check_coex_rssi_state(struct ieee80211_hw *hw,
299 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 300 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
300 "[DM][BT], RSSI state stay at Low\n"); 301 "[DM][BT], RSSI state stay at Low\n");
301 } 302 }
302 } else if ((rtlpcipriv->bt_coexist.bt_pre_rssi_state == 303 } else if ((rtlpriv->btcoexist.bt_pre_rssi_state ==
303 BT_RSSI_STATE_MEDIUM) || 304 BT_RSSI_STATE_MEDIUM) ||
304 (rtlpcipriv->bt_coexist.bt_pre_rssi_state == 305 (rtlpriv->btcoexist.bt_pre_rssi_state ==
305 BT_RSSI_STATE_STAY_MEDIUM)) { 306 BT_RSSI_STATE_STAY_MEDIUM)) {
306 if (smooth >= 307 if (undecoratedsmoothed_pwdb >=
307 (rssi_thresh1 + BT_FW_COEX_THRESH_TOL)) { 308 (rssi_thresh1 + BT_FW_COEX_THRESH_TOL)) {
308 bt_rssi_state = BT_RSSI_STATE_HIGH; 309 bt_rssi_state = BT_RSSI_STATE_HIGH;
309 rtlpcipriv->bt_coexist.cstate 310 rtlpriv->btcoexist.cstate
310 |= BT_COEX_STATE_WIFI_RSSI_HIGH; 311 |= BT_COEX_STATE_WIFI_RSSI_HIGH;
311 rtlpcipriv->bt_coexist.cstate 312 rtlpriv->btcoexist.cstate
312 &= ~BT_COEX_STATE_WIFI_RSSI_LOW; 313 &= ~BT_COEX_STATE_WIFI_RSSI_LOW;
313 rtlpcipriv->bt_coexist.cstate 314 rtlpriv->btcoexist.cstate
314 &= ~BT_COEX_STATE_WIFI_RSSI_MEDIUM; 315 &= ~BT_COEX_STATE_WIFI_RSSI_MEDIUM;
315 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 316 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
316 "[DM][BT], RSSI state switch to High\n"); 317 "[DM][BT], RSSI state switch to High\n");
317 } else if (smooth < rssi_thresh) { 318 } else if (undecoratedsmoothed_pwdb < rssi_thresh) {
318 bt_rssi_state = BT_RSSI_STATE_LOW; 319 bt_rssi_state = BT_RSSI_STATE_LOW;
319 rtlpcipriv->bt_coexist.cstate 320 rtlpriv->btcoexist.cstate
320 |= BT_COEX_STATE_WIFI_RSSI_LOW; 321 |= BT_COEX_STATE_WIFI_RSSI_LOW;
321 rtlpcipriv->bt_coexist.cstate 322 rtlpriv->btcoexist.cstate
322 &= ~BT_COEX_STATE_WIFI_RSSI_HIGH; 323 &= ~BT_COEX_STATE_WIFI_RSSI_HIGH;
323 rtlpcipriv->bt_coexist.cstate 324 rtlpriv->btcoexist.cstate
324 &= ~BT_COEX_STATE_WIFI_RSSI_MEDIUM; 325 &= ~BT_COEX_STATE_WIFI_RSSI_MEDIUM;
325 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 326 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
326 "[DM][BT], RSSI state switch to Low\n"); 327 "[DM][BT], RSSI state switch to Low\n");
@@ -330,13 +331,13 @@ u8 rtl8723ae_dm_bt_check_coex_rssi_state(struct ieee80211_hw *hw,
330 "[DM][BT], RSSI state stay at Medium\n"); 331 "[DM][BT], RSSI state stay at Medium\n");
331 } 332 }
332 } else { 333 } else {
333 if (smooth < rssi_thresh1) { 334 if (undecoratedsmoothed_pwdb < rssi_thresh1) {
334 bt_rssi_state = BT_RSSI_STATE_MEDIUM; 335 bt_rssi_state = BT_RSSI_STATE_MEDIUM;
335 rtlpcipriv->bt_coexist.cstate 336 rtlpriv->btcoexist.cstate
336 |= BT_COEX_STATE_WIFI_RSSI_MEDIUM; 337 |= BT_COEX_STATE_WIFI_RSSI_MEDIUM;
337 rtlpcipriv->bt_coexist.cstate 338 rtlpriv->btcoexist.cstate
338 &= ~BT_COEX_STATE_WIFI_RSSI_HIGH; 339 &= ~BT_COEX_STATE_WIFI_RSSI_HIGH;
339 rtlpcipriv->bt_coexist.cstate 340 rtlpriv->btcoexist.cstate
340 &= ~BT_COEX_STATE_WIFI_RSSI_LOW; 341 &= ~BT_COEX_STATE_WIFI_RSSI_LOW;
341 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 342 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
342 "[DM][BT], RSSI state switch to Medium\n"); 343 "[DM][BT], RSSI state switch to Medium\n");
@@ -347,31 +348,32 @@ u8 rtl8723ae_dm_bt_check_coex_rssi_state(struct ieee80211_hw *hw,
347 } 348 }
348 } 349 }
349 } 350 }
350 351 rtlpriv->btcoexist.bt_pre_rssi_state = bt_rssi_state;
351 rtlpcipriv->bt_coexist.bt_pre_rssi_state = bt_rssi_state;
352 return bt_rssi_state; 352 return bt_rssi_state;
353} 353}
354 354
355long rtl8723ae_dm_bt_get_rx_ss(struct ieee80211_hw *hw) 355long rtl8723e_dm_bt_get_rx_ss(struct ieee80211_hw *hw)
356{ 356{
357 struct rtl_priv *rtlpriv = rtl_priv(hw); 357 struct rtl_priv *rtlpriv = rtl_priv(hw);
358 long smooth = 0; 358 long undecoratedsmoothed_pwdb = 0;
359
360 if (rtlpriv->mac80211.link_state >= MAC80211_LINKED)
361 smooth = GET_UNDECORATED_AVERAGE_RSSI(rtlpriv);
362 else
363 smooth = rtlpriv->dm.entry_min_undec_sm_pwdb;
364 359
360 if (rtlpriv->mac80211.link_state >= MAC80211_LINKED) {
361 undecoratedsmoothed_pwdb =
362 GET_UNDECORATED_AVERAGE_RSSI(rtlpriv);
363 } else {
364 undecoratedsmoothed_pwdb
365 = rtlpriv->dm.entry_min_undec_sm_pwdb;
366 }
365 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 367 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
366 "rtl8723ae_dm_bt_get_rx_ss() = %ld\n", smooth); 368 "rtl8723e_dm_bt_get_rx_ss() = %ld\n",
369 undecoratedsmoothed_pwdb);
367 370
368 return smooth; 371 return undecoratedsmoothed_pwdb;
369} 372}
370 373
371void rtl8723ae_dm_bt_balance(struct ieee80211_hw *hw, 374void rtl8723e_dm_bt_balance(struct ieee80211_hw *hw,
372 bool balance_on, u8 ms0, u8 ms1) 375 bool balance_on, u8 ms0, u8 ms1)
373{ 376{
374 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
375 struct rtl_priv *rtlpriv = rtl_priv(hw); 377 struct rtl_priv *rtlpriv = rtl_priv(hw);
376 u8 h2c_parameter[3] = {0}; 378 u8 h2c_parameter[3] = {0};
377 379
@@ -379,27 +381,26 @@ void rtl8723ae_dm_bt_balance(struct ieee80211_hw *hw,
379 h2c_parameter[2] = 1; 381 h2c_parameter[2] = 1;
380 h2c_parameter[1] = ms1; 382 h2c_parameter[1] = ms1;
381 h2c_parameter[0] = ms0; 383 h2c_parameter[0] = ms0;
382 rtlpcipriv->bt_coexist.fw_coexist_all_off = false; 384 rtlpriv->btcoexist.fw_coexist_all_off = false;
383 } else { 385 } else {
384 h2c_parameter[2] = 0; 386 h2c_parameter[2] = 0;
385 h2c_parameter[1] = 0; 387 h2c_parameter[1] = 0;
386 h2c_parameter[0] = 0; 388 h2c_parameter[0] = 0;
387 } 389 }
388 rtlpcipriv->bt_coexist.balance_on = balance_on; 390 rtlpriv->btcoexist.balance_on = balance_on;
389 391
390 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 392 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
391 "[DM][BT], Balance=[%s:%dms:%dms], write 0xc=0x%x\n", 393 "[DM][BT], Balance=[%s:%dms:%dms], write 0xc=0x%x\n",
392 balance_on ? "ON" : "OFF", ms0, ms1, 394 balance_on ? "ON" : "OFF", ms0, ms1, h2c_parameter[0]<<16 |
393 h2c_parameter[0]<<16 | h2c_parameter[1]<<8 | h2c_parameter[2]); 395 h2c_parameter[1]<<8 | h2c_parameter[2]);
394 396
395 rtl8723ae_fill_h2c_cmd(hw, 0xc, 3, h2c_parameter); 397 rtl8723e_fill_h2c_cmd(hw, 0xc, 3, h2c_parameter);
396} 398}
397 399
398 400
399void rtl8723ae_dm_bt_agc_table(struct ieee80211_hw *hw, u8 type) 401void rtl8723e_dm_bt_agc_table(struct ieee80211_hw *hw, u8 type)
400{ 402{
401 struct rtl_priv *rtlpriv = rtl_priv(hw); 403 struct rtl_priv *rtlpriv = rtl_priv(hw);
402 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
403 404
404 if (type == BT_AGCTABLE_OFF) { 405 if (type == BT_AGCTABLE_OFF) {
405 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 406 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
@@ -410,15 +411,15 @@ void rtl8723ae_dm_bt_agc_table(struct ieee80211_hw *hw, u8 type)
410 rtl_write_dword(rtlpriv, 0xc78, 0x611f0001); 411 rtl_write_dword(rtlpriv, 0xc78, 0x611f0001);
411 rtl_write_dword(rtlpriv, 0xc78, 0x60200001); 412 rtl_write_dword(rtlpriv, 0xc78, 0x60200001);
412 413
413 rtl8723ae_phy_set_rf_reg(hw, RF90_PATH_A, 414 rtl8723e_phy_set_rf_reg(hw, RF90_PATH_A,
414 RF_RX_AGC_HP, 0xfffff, 0x32000); 415 RF_RX_AGC_HP, 0xfffff, 0x32000);
415 rtl8723ae_phy_set_rf_reg(hw, RF90_PATH_A, 416 rtl8723e_phy_set_rf_reg(hw, RF90_PATH_A,
416 RF_RX_AGC_HP, 0xfffff, 0x71000); 417 RF_RX_AGC_HP, 0xfffff, 0x71000);
417 rtl8723ae_phy_set_rf_reg(hw, RF90_PATH_A, 418 rtl8723e_phy_set_rf_reg(hw, RF90_PATH_A,
418 RF_RX_AGC_HP, 0xfffff, 0xb0000); 419 RF_RX_AGC_HP, 0xfffff, 0xb0000);
419 rtl8723ae_phy_set_rf_reg(hw, RF90_PATH_A, 420 rtl8723e_phy_set_rf_reg(hw, RF90_PATH_A,
420 RF_RX_AGC_HP, 0xfffff, 0xfc000); 421 RF_RX_AGC_HP, 0xfffff, 0xfc000);
421 rtl8723ae_phy_set_rf_reg(hw, RF90_PATH_A, 422 rtl8723e_phy_set_rf_reg(hw, RF90_PATH_A,
422 RF_RX_G1, 0xfffff, 0x30355); 423 RF_RX_G1, 0xfffff, 0x30355);
423 } else if (type == BT_AGCTABLE_ON) { 424 } else if (type == BT_AGCTABLE_ON) {
424 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 425 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
@@ -429,25 +430,24 @@ void rtl8723ae_dm_bt_agc_table(struct ieee80211_hw *hw, u8 type)
429 rtl_write_dword(rtlpriv, 0xc78, 0x4b1f0001); 430 rtl_write_dword(rtlpriv, 0xc78, 0x4b1f0001);
430 rtl_write_dword(rtlpriv, 0xc78, 0x4a200001); 431 rtl_write_dword(rtlpriv, 0xc78, 0x4a200001);
431 432
432 rtl8723ae_phy_set_rf_reg(hw, RF90_PATH_A, 433 rtl8723e_phy_set_rf_reg(hw, RF90_PATH_A,
433 RF_RX_AGC_HP, 0xfffff, 0xdc000); 434 RF_RX_AGC_HP, 0xfffff, 0xdc000);
434 rtl8723ae_phy_set_rf_reg(hw, RF90_PATH_A, 435 rtl8723e_phy_set_rf_reg(hw, RF90_PATH_A,
435 RF_RX_AGC_HP, 0xfffff, 0x90000); 436 RF_RX_AGC_HP, 0xfffff, 0x90000);
436 rtl8723ae_phy_set_rf_reg(hw, RF90_PATH_A, 437 rtl8723e_phy_set_rf_reg(hw, RF90_PATH_A,
437 RF_RX_AGC_HP, 0xfffff, 0x51000); 438 RF_RX_AGC_HP, 0xfffff, 0x51000);
438 rtl8723ae_phy_set_rf_reg(hw, RF90_PATH_A, 439 rtl8723e_phy_set_rf_reg(hw, RF90_PATH_A,
439 RF_RX_AGC_HP, 0xfffff, 0x12000); 440 RF_RX_AGC_HP, 0xfffff, 0x12000);
440 rtl8723ae_phy_set_rf_reg(hw, RF90_PATH_A, 441 rtl8723e_phy_set_rf_reg(hw, RF90_PATH_A,
441 RF_RX_G1, 0xfffff, 0x00355); 442 RF_RX_G1, 0xfffff, 0x00355);
442 443
443 rtlpcipriv->bt_coexist.sw_coexist_all_off = false; 444 rtlpriv->btcoexist.sw_coexist_all_off = false;
444 } 445 }
445} 446}
446 447
447void rtl8723ae_dm_bt_bback_off_level(struct ieee80211_hw *hw, u8 type) 448void rtl8723e_dm_bt_bb_back_off_level(struct ieee80211_hw *hw, u8 type)
448{ 449{
449 struct rtl_priv *rtlpriv = rtl_priv(hw); 450 struct rtl_priv *rtlpriv = rtl_priv(hw);
450 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
451 451
452 if (type == BT_BB_BACKOFF_OFF) { 452 if (type == BT_BB_BACKOFF_OFF) {
453 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 453 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
@@ -457,87 +457,81 @@ void rtl8723ae_dm_bt_bback_off_level(struct ieee80211_hw *hw, u8 type)
457 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 457 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
458 "[BT]BBBackOffLevel On!\n"); 458 "[BT]BBBackOffLevel On!\n");
459 rtl_write_dword(rtlpriv, 0xc04, 0x3a07611); 459 rtl_write_dword(rtlpriv, 0xc04, 0x3a07611);
460 rtlpcipriv->bt_coexist.sw_coexist_all_off = false; 460 rtlpriv->btcoexist.sw_coexist_all_off = false;
461 } 461 }
462} 462}
463 463
464void rtl8723ae_dm_bt_fw_coex_all_off(struct ieee80211_hw *hw) 464void rtl8723e_dm_bt_fw_coex_all_off(struct ieee80211_hw *hw)
465{ 465{
466 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
467 struct rtl_priv *rtlpriv = rtl_priv(hw); 466 struct rtl_priv *rtlpriv = rtl_priv(hw);
468 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 467 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
469 "rtl8723ae_dm_bt_fw_coex_all_off()\n"); 468 "rtl8723e_dm_bt_fw_coex_all_off()\n");
470 469
471 if (rtlpcipriv->bt_coexist.fw_coexist_all_off) 470 if (rtlpriv->btcoexist.fw_coexist_all_off)
472 return; 471 return;
473 472
474 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 473 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
475 "rtl8723ae_dm_bt_fw_coex_all_off(), real Do\n"); 474 "rtl8723e_dm_bt_fw_coex_all_off(), real Do\n");
476 rtl8723ae_dm_bt_fw_coex_all_off_8723a(hw); 475 rtl8723e_dm_bt_fw_coex_all_off_8723a(hw);
477 rtlpcipriv->bt_coexist.fw_coexist_all_off = true; 476 rtlpriv->btcoexist.fw_coexist_all_off = true;
478} 477}
479 478
480void rtl8723ae_dm_bt_sw_coex_all_off(struct ieee80211_hw *hw) 479void rtl8723e_dm_bt_sw_coex_all_off(struct ieee80211_hw *hw)
481{ 480{
482 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
483 struct rtl_priv *rtlpriv = rtl_priv(hw); 481 struct rtl_priv *rtlpriv = rtl_priv(hw);
484 482
485 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 483 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
486 "rtl8723ae_dm_bt_sw_coex_all_off()\n"); 484 "rtl8723e_dm_bt_sw_coex_all_off()\n");
487 485
488 if (rtlpcipriv->bt_coexist.sw_coexist_all_off) 486 if (rtlpriv->btcoexist.sw_coexist_all_off)
489 return; 487 return;
490 488
491 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 489 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
492 "rtl8723ae_dm_bt_sw_coex_all_off(), real Do\n"); 490 "rtl8723e_dm_bt_sw_coex_all_off(), real Do\n");
493 rtl8723ae_dm_bt_sw_coex_all_off_8723a(hw); 491 rtl8723e_dm_bt_sw_coex_all_off_8723a(hw);
494 rtlpcipriv->bt_coexist.sw_coexist_all_off = true; 492 rtlpriv->btcoexist.sw_coexist_all_off = true;
495} 493}
496 494
497void rtl8723ae_dm_bt_hw_coex_all_off(struct ieee80211_hw *hw) 495void rtl8723e_dm_bt_hw_coex_all_off(struct ieee80211_hw *hw)
498{ 496{
499 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
500 struct rtl_priv *rtlpriv = rtl_priv(hw); 497 struct rtl_priv *rtlpriv = rtl_priv(hw);
501 498
502 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 499 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
503 "rtl8723ae_dm_bt_hw_coex_all_off()\n"); 500 "rtl8723e_dm_bt_hw_coex_all_off()\n");
504 501
505 if (rtlpcipriv->bt_coexist.hw_coexist_all_off) 502 if (rtlpriv->btcoexist.hw_coexist_all_off)
506 return; 503 return;
507 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 504 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
508 "rtl8723ae_dm_bt_hw_coex_all_off(), real Do\n"); 505 "rtl8723e_dm_bt_hw_coex_all_off(), real Do\n");
509 506
510 rtl8723ae_dm_bt_hw_coex_all_off_8723a(hw); 507 rtl8723e_dm_bt_hw_coex_all_off_8723a(hw);
511 508
512 rtlpcipriv->bt_coexist.hw_coexist_all_off = true; 509 rtlpriv->btcoexist.hw_coexist_all_off = true;
513} 510}
514 511
515void rtl8723ae_btdm_coex_all_off(struct ieee80211_hw *hw) 512void rtl8723e_btdm_coex_all_off(struct ieee80211_hw *hw)
516{ 513{
517 rtl8723ae_dm_bt_fw_coex_all_off(hw); 514 rtl8723e_dm_bt_fw_coex_all_off(hw);
518 rtl8723ae_dm_bt_sw_coex_all_off(hw); 515 rtl8723e_dm_bt_sw_coex_all_off(hw);
519 rtl8723ae_dm_bt_hw_coex_all_off(hw); 516 rtl8723e_dm_bt_hw_coex_all_off(hw);
520} 517}
521 518
522bool rtl8723ae_dm_bt_is_coexist_state_changed(struct ieee80211_hw *hw) 519bool rtl8723e_dm_bt_is_coexist_state_changed(struct ieee80211_hw *hw)
523{ 520{
524 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 521 struct rtl_priv *rtlpriv = rtl_priv(hw);
525 522
526 if ((rtlpcipriv->bt_coexist.previous_state == 523 if ((rtlpriv->btcoexist.previous_state == rtlpriv->btcoexist.cstate) &&
527 rtlpcipriv->bt_coexist.cstate) && 524 (rtlpriv->btcoexist.previous_state_h ==
528 (rtlpcipriv->bt_coexist.previous_state_h == 525 rtlpriv->btcoexist.cstate_h))
529 rtlpcipriv->bt_coexist.cstate_h))
530 return false; 526 return false;
531 else 527 return true;
532 return true;
533} 528}
534 529
535bool rtl8723ae_dm_bt_is_wifi_up_link(struct ieee80211_hw *hw) 530bool rtl8723e_dm_bt_is_wifi_up_link(struct ieee80211_hw *hw)
536{ 531{
537 struct rtl_priv *rtlpriv = rtl_priv(hw); 532 struct rtl_priv *rtlpriv = rtl_priv(hw);
538 533
539 if (rtlpriv->link_info.tx_busy_traffic) 534 if (rtlpriv->link_info.tx_busy_traffic)
540 return true; 535 return true;
541 else 536 return false;
542 return false;
543} 537}
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/hal_bt_coexist.h b/drivers/net/wireless/rtlwifi/rtl8723ae/hal_bt_coexist.h
index 76f4d122dbc1..bcd64a22acc0 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/hal_bt_coexist.h
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/hal_bt_coexist.h
@@ -53,8 +53,8 @@
53#define BT_COEX_STATE_WIFI_LEGACY BIT(3) 53#define BT_COEX_STATE_WIFI_LEGACY BIT(3)
54 54
55#define BT_COEX_STATE_WIFI_RSSI_LOW BIT(4) 55#define BT_COEX_STATE_WIFI_RSSI_LOW BIT(4)
56#define BT_COEX_STATE_WIFI_RSSI_MEDIUM BIT(5) 56#define BT_COEX_STATE_WIFI_RSSI_MEDIUM BIT(5)
57#define BT_COEX_STATE_WIFI_RSSI_HIGH BIT(6) 57#define BT_COEX_STATE_WIFI_RSSI_HIGH BIT(6)
58#define BT_COEX_STATE_DEC_BT_POWER BIT(7) 58#define BT_COEX_STATE_DEC_BT_POWER BIT(7)
59 59
60#define BT_COEX_STATE_WIFI_IDLE BIT(8) 60#define BT_COEX_STATE_WIFI_IDLE BIT(8)
@@ -78,7 +78,7 @@
78#define BT_COEX_STATE_WIFI_RSSI_1_MEDIUM BIT(25) 78#define BT_COEX_STATE_WIFI_RSSI_1_MEDIUM BIT(25)
79#define BT_COEX_STATE_WIFI_RSSI_1_HIGH BIT(26) 79#define BT_COEX_STATE_WIFI_RSSI_1_HIGH BIT(26)
80 80
81#define BT_COEX_STATE_BTINFO_COMMON BIT(30) 81#define BT_COEX_STATE_BTINFO_COMMON BIT(30)
82#define BT_COEX_STATE_BTINFO_B_HID_SCOESCO BIT(31) 82#define BT_COEX_STATE_BTINFO_B_HID_SCOESCO BIT(31)
83#define BT_COEX_STATE_BTINFO_B_FTP_A2DP BIT(29) 83#define BT_COEX_STATE_BTINFO_B_FTP_A2DP BIT(29)
84 84
@@ -133,28 +133,26 @@
133#define BTINFO_B_SCO_ESCO BIT(1) 133#define BTINFO_B_SCO_ESCO BIT(1)
134#define BTINFO_B_CONNECTION BIT(0) 134#define BTINFO_B_CONNECTION BIT(0)
135 135
136void rtl8723e_btdm_coex_all_off(struct ieee80211_hw *hw);
137void rtl8723e_dm_bt_fw_coex_all_off(struct ieee80211_hw *hw);
136 138
137void rtl8723ae_btdm_coex_all_off(struct ieee80211_hw *hw); 139void rtl8723e_dm_bt_sw_coex_all_off(struct ieee80211_hw *hw);
138void rtl8723ae_dm_bt_fw_coex_all_off(struct ieee80211_hw *hw); 140void rtl8723e_dm_bt_hw_coex_all_off(struct ieee80211_hw *hw);
139 141long rtl8723e_dm_bt_get_rx_ss(struct ieee80211_hw *hw);
140void rtl8723ae_dm_bt_sw_coex_all_off(struct ieee80211_hw *hw); 142void rtl8723e_dm_bt_balance(struct ieee80211_hw *hw,
141void rtl8723ae_dm_bt_hw_coex_all_off(struct ieee80211_hw *hw);
142long rtl8723ae_dm_bt_get_rx_ss(struct ieee80211_hw *hw);
143void rtl8723ae_dm_bt_balance(struct ieee80211_hw *hw,
144 bool balance_on, u8 ms0, u8 ms1); 143 bool balance_on, u8 ms0, u8 ms1);
145void rtl8723ae_dm_bt_agc_table(struct ieee80211_hw *hw, u8 type); 144void rtl8723e_dm_bt_agc_table(struct ieee80211_hw *hw, u8 tyep);
146void rtl8723ae_dm_bt_bback_off_level(struct ieee80211_hw *hw, u8 type); 145void rtl8723e_dm_bt_bb_back_off_level(struct ieee80211_hw *hw, u8 type);
147u8 rtl8723ae_dm_bt_check_coex_rssi_state(struct ieee80211_hw *hw, 146u8 rtl8723e_dm_bt_check_coex_rssi_state(struct ieee80211_hw *hw,
148 u8 level_num, u8 rssi_thresh, 147 u8 level_num, u8 rssi_thresh,
149 u8 rssi_thresh1); 148 u8 rssi_thresh1);
150u8 rtl8723ae_dm_bt_check_coex_rssi_state1(struct ieee80211_hw *hw, 149u8 rtl8723e_dm_bt_check_coex_rssi_state1(struct ieee80211_hw *hw,
151 u8 level_num, u8 rssi_thresh, 150 u8 level_num, u8 rssi_thresh,
152 u8 rssi_thresh1); 151 u8 rssi_thresh1);
153void _rtl8723_dm_bt_check_wifi_state(struct ieee80211_hw *hw); 152void _rtl8723_dm_bt_check_wifi_state(struct ieee80211_hw *hw);
154void rtl8723ae_dm_bt_reject_ap_aggregated_packet(struct ieee80211_hw *hw, 153void rtl8723e_dm_bt_reject_ap_aggregated_packet(struct ieee80211_hw *hw,
155 bool reject); 154 bool b_reject);
156 155bool rtl8723e_dm_bt_is_coexist_state_changed(struct ieee80211_hw *hw);
157bool rtl8723ae_dm_bt_is_coexist_state_changed(struct ieee80211_hw *hw); 156bool rtl8723e_dm_bt_is_wifi_up_link(struct ieee80211_hw *hw);
158bool rtl8723ae_dm_bt_is_wifi_up_link(struct ieee80211_hw *hw);
159 157
160#endif 158#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/hal_btc.c b/drivers/net/wireless/rtlwifi/rtl8723ae/hal_btc.c
index f76c50f5ab80..747958abd256 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/hal_btc.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/hal_btc.c
@@ -11,10 +11,6 @@
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details. 12 * more details.
13 * 13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the 14 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE. 15 * file called LICENSE.
20 * 16 *
@@ -25,34 +21,33 @@
25 * 21 *
26 * Larry Finger <Larry.Finger@lwfinger.net> 22 * Larry Finger <Larry.Finger@lwfinger.net>
27 * 23 *
28 **************************************************************************** 24 *****************************************************************************/
29 */
30#include "hal_btc.h" 25#include "hal_btc.h"
31#include "../pci.h" 26#include "../pci.h"
32#include "phy.h" 27#include "phy.h"
33#include "../rtl8723com/phy_common.h"
34#include "fw.h" 28#include "fw.h"
35#include "../rtl8723com/fw_common.h"
36#include "reg.h" 29#include "reg.h"
37#include "def.h" 30#include "def.h"
31#include "../rtl8723com/phy_common.h"
32
33static struct bt_coexist_8723 hal_coex_8723;
38 34
39void rtl8723ae_bt_coex_off_before_lps(struct ieee80211_hw *hw) 35void rtl8723e_dm_bt_turn_off_bt_coexist_before_enter_lps(struct ieee80211_hw *hw)
40{ 36{
41 struct rtl_priv *rtlpriv = rtl_priv(hw); 37 struct rtl_priv *rtlpriv = rtl_priv(hw);
42 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
43 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 38 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
44 39
45 if (!rtlpcipriv->bt_coexist.bt_coexistence) 40 if (!rtlpriv->btcoexist.bt_coexistence)
46 return; 41 return;
47 42
48 if (ppsc->inactiveps) { 43 if (ppsc->inactiveps) {
49 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 44 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
50 "[BT][DM], Before enter IPS, turn off all Coexist DM\n"); 45 "[BT][DM], Before enter IPS, turn off all Coexist DM\n");
51 rtlpcipriv->bt_coexist.cstate = 0; 46 rtlpriv->btcoexist.cstate = 0;
52 rtlpcipriv->bt_coexist.previous_state = 0; 47 rtlpriv->btcoexist.previous_state = 0;
53 rtlpcipriv->bt_coexist.cstate_h = 0; 48 rtlpriv->btcoexist.cstate_h = 0;
54 rtlpcipriv->bt_coexist.previous_state_h = 0; 49 rtlpriv->btcoexist.previous_state_h = 0;
55 rtl8723ae_btdm_coex_all_off(hw); 50 rtl8723e_btdm_coex_all_off(hw);
56 } 51 }
57} 52}
58 53
@@ -60,10 +55,8 @@ static enum rt_media_status mgnt_link_status_query(struct ieee80211_hw *hw)
60{ 55{
61 struct rtl_priv *rtlpriv = rtl_priv(hw); 56 struct rtl_priv *rtlpriv = rtl_priv(hw);
62 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 57 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
63 enum rt_media_status m_status = RT_MEDIA_DISCONNECT; 58 enum rt_media_status m_status = RT_MEDIA_DISCONNECT;
64
65 u8 bibss = (mac->opmode == NL80211_IFTYPE_ADHOC) ? 1 : 0; 59 u8 bibss = (mac->opmode == NL80211_IFTYPE_ADHOC) ? 1 : 0;
66
67 if (bibss || rtlpriv->mac80211.link_state >= MAC80211_LINKED) 60 if (bibss || rtlpriv->mac80211.link_state >= MAC80211_LINKED)
68 m_status = RT_MEDIA_CONNECT; 61 m_status = RT_MEDIA_CONNECT;
69 62
@@ -71,15 +64,14 @@ static enum rt_media_status mgnt_link_status_query(struct ieee80211_hw *hw)
71} 64}
72 65
73void rtl_8723e_bt_wifi_media_status_notify(struct ieee80211_hw *hw, 66void rtl_8723e_bt_wifi_media_status_notify(struct ieee80211_hw *hw,
74 bool mstatus) 67 bool mstatus)
75{ 68{
76 struct rtl_priv *rtlpriv = rtl_priv(hw); 69 struct rtl_priv *rtlpriv = rtl_priv(hw);
77 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
78 struct rtl_phy *rtlphy = &(rtlpriv->phy); 70 struct rtl_phy *rtlphy = &(rtlpriv->phy);
79 u8 h2c_parameter[3] = {0}; 71 u8 h2c_parameter[3] = {0};
80 u8 chnl; 72 u8 chnl;
81 73
82 if (!rtlpcipriv->bt_coexist.bt_coexistence) 74 if (!rtlpriv->btcoexist.bt_coexistence)
83 return; 75 return;
84 76
85 if (RT_MEDIA_CONNECT == mstatus) 77 if (RT_MEDIA_CONNECT == mstatus)
@@ -98,14 +90,13 @@ void rtl_8723e_bt_wifi_media_status_notify(struct ieee80211_hw *hw,
98 h2c_parameter[2] = 0x20; 90 h2c_parameter[2] = 0x20;
99 91
100 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 92 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
101 "[BTCoex], FW write 0x19 = 0x%x\n", 93 "[BTCoex], FW write 0x19=0x%x\n",
102 h2c_parameter[0]<<16|h2c_parameter[1]<<8|h2c_parameter[2]); 94 h2c_parameter[0]<<16|h2c_parameter[1]<<8|h2c_parameter[2]);
103 95
104 rtl8723ae_fill_h2c_cmd(hw, 0x19, 3, h2c_parameter); 96 rtl8723e_fill_h2c_cmd(hw, 0x19, 3, h2c_parameter);
105
106} 97}
107 98
108static bool rtl8723ae_dm_bt_is_wifi_busy(struct ieee80211_hw *hw) 99static bool rtl8723e_dm_bt_is_wifi_busy(struct ieee80211_hw *hw)
109{ 100{
110 struct rtl_priv *rtlpriv = rtl_priv(hw); 101 struct rtl_priv *rtlpriv = rtl_priv(hw);
111 if (rtlpriv->link_info.busytraffic || 102 if (rtlpriv->link_info.busytraffic ||
@@ -116,12 +107,12 @@ static bool rtl8723ae_dm_bt_is_wifi_busy(struct ieee80211_hw *hw)
116 return false; 107 return false;
117} 108}
118 109
119static void rtl8723ae_dm_bt_set_fw_3a(struct ieee80211_hw *hw, 110static void rtl8723e_dm_bt_set_fw_3a(struct ieee80211_hw *hw,
120 u8 byte1, u8 byte2, u8 byte3, 111 u8 byte1, u8 byte2, u8 byte3, u8 byte4,
121 u8 byte4, u8 byte5) 112 u8 byte5)
122{ 113{
123 struct rtl_priv *rtlpriv = rtl_priv(hw); 114 struct rtl_priv *rtlpriv = rtl_priv(hw);
124 u8 h2c_parameter[5] = {0}; 115 u8 h2c_parameter[5];
125 116
126 h2c_parameter[0] = byte1; 117 h2c_parameter[0] = byte1;
127 h2c_parameter[1] = byte2; 118 h2c_parameter[1] = byte2;
@@ -129,37 +120,37 @@ static void rtl8723ae_dm_bt_set_fw_3a(struct ieee80211_hw *hw,
129 h2c_parameter[3] = byte4; 120 h2c_parameter[3] = byte4;
130 h2c_parameter[4] = byte5; 121 h2c_parameter[4] = byte5;
131 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 122 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
132 "[BTCoex], FW write 0x3a(4bytes) = 0x%x%8x\n", 123 "[BTCoex], FW write 0x3a(4bytes)=0x%x%8x\n",
133 h2c_parameter[0], h2c_parameter[1]<<24 | h2c_parameter[2]<<16 | 124 h2c_parameter[0], h2c_parameter[1]<<24 |
134 h2c_parameter[3]<<8 | h2c_parameter[4]); 125 h2c_parameter[2]<<16 | h2c_parameter[3]<<8 |
135 rtl8723ae_fill_h2c_cmd(hw, 0x3a, 5, h2c_parameter); 126 h2c_parameter[4]);
127 rtl8723e_fill_h2c_cmd(hw, 0x3a, 5, h2c_parameter);
136} 128}
137 129
138static bool rtl8723ae_dm_bt_need_to_dec_bt_pwr(struct ieee80211_hw *hw) 130static bool rtl8723e_dm_bt_need_to_dec_bt_pwr(struct ieee80211_hw *hw)
139{ 131{
140 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
141 struct rtl_priv *rtlpriv = rtl_priv(hw); 132 struct rtl_priv *rtlpriv = rtl_priv(hw);
142 133
143 if (mgnt_link_status_query(hw) == RT_MEDIA_CONNECT) { 134 if (mgnt_link_status_query(hw) == RT_MEDIA_CONNECT) {
144 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 135 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
145 "Need to decrease bt power\n"); 136 "Need to decrease bt power\n");
146 rtlpcipriv->bt_coexist.cstate |= BT_COEX_STATE_DEC_BT_POWER; 137 rtlpriv->btcoexist.cstate |=
147 return true; 138 BT_COEX_STATE_DEC_BT_POWER;
139 return true;
148 } 140 }
149 141
150 rtlpcipriv->bt_coexist.cstate &= ~BT_COEX_STATE_DEC_BT_POWER; 142 rtlpriv->btcoexist.cstate &= ~BT_COEX_STATE_DEC_BT_POWER;
151 return false; 143 return false;
152} 144}
153 145
154static bool rtl8723ae_dm_bt_is_same_coexist_state(struct ieee80211_hw *hw) 146static bool rtl8723e_dm_bt_is_same_coexist_state(struct ieee80211_hw *hw)
155{ 147{
156 struct rtl_priv *rtlpriv = rtl_priv(hw); 148 struct rtl_priv *rtlpriv = rtl_priv(hw);
157 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
158 149
159 if ((rtlpcipriv->bt_coexist.previous_state == 150 if ((rtlpriv->btcoexist.previous_state ==
160 rtlpcipriv->bt_coexist.cstate) && 151 rtlpriv->btcoexist.cstate) &&
161 (rtlpcipriv->bt_coexist.previous_state_h == 152 (rtlpriv->btcoexist.previous_state_h ==
162 rtlpcipriv->bt_coexist.cstate_h)) { 153 rtlpriv->btcoexist.cstate_h)) {
163 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 154 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
164 "[DM][BT], Coexist state do not chang!!\n"); 155 "[DM][BT], Coexist state do not chang!!\n");
165 return true; 156 return true;
@@ -170,86 +161,84 @@ static bool rtl8723ae_dm_bt_is_same_coexist_state(struct ieee80211_hw *hw)
170 } 161 }
171} 162}
172 163
173static void rtl8723ae_dm_bt_set_coex_table(struct ieee80211_hw *hw, 164static void rtl8723e_dm_bt_set_coex_table(struct ieee80211_hw *hw,
174 u32 val_0x6c0, u32 val_0x6c8, 165 u32 val_0x6c0, u32 val_0x6c8,
175 u32 val_0x6cc) 166 u32 val_0x6cc)
176{ 167{
177 struct rtl_priv *rtlpriv = rtl_priv(hw); 168 struct rtl_priv *rtlpriv = rtl_priv(hw);
178 169
179 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 170 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
180 "set coex table, set 0x6c0 = 0x%x\n", val_0x6c0); 171 "set coex table, set 0x6c0=0x%x\n", val_0x6c0);
181 rtl_write_dword(rtlpriv, 0x6c0, val_0x6c0); 172 rtl_write_dword(rtlpriv, 0x6c0, val_0x6c0);
182 173
183 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 174 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
184 "set coex table, set 0x6c8 = 0x%x\n", val_0x6c8); 175 "set coex table, set 0x6c8=0x%x\n", val_0x6c8);
185 rtl_write_dword(rtlpriv, 0x6c8, val_0x6c8); 176 rtl_write_dword(rtlpriv, 0x6c8, val_0x6c8);
186 177
187 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 178 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
188 "set coex table, set 0x6cc = 0x%x\n", val_0x6cc); 179 "set coex table, set 0x6cc=0x%x\n", val_0x6cc);
189 rtl_write_byte(rtlpriv, 0x6cc, val_0x6cc); 180 rtl_write_byte(rtlpriv, 0x6cc, val_0x6cc);
190} 181}
191 182
192static void rtl8723ae_dm_bt_set_hw_pta_mode(struct ieee80211_hw *hw, bool mode) 183static void rtl8723e_dm_bt_set_hw_pta_mode(struct ieee80211_hw *hw, bool b_mode)
193{ 184{
194 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
195 struct rtl_priv *rtlpriv = rtl_priv(hw); 185 struct rtl_priv *rtlpriv = rtl_priv(hw);
196 186
197 if (BT_PTA_MODE_ON == mode) { 187 if (BT_PTA_MODE_ON == b_mode) {
198 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, "PTA mode on, "); 188 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, "PTA mode on, ");
199 /* Enable GPIO 0/1/2/3/8 pins for bt */ 189 /* Enable GPIO 0/1/2/3/8 pins for bt */
200 rtl_write_byte(rtlpriv, 0x40, 0x20); 190 rtl_write_byte(rtlpriv, 0x40, 0x20);
201 rtlpcipriv->bt_coexist.hw_coexist_all_off = false; 191 rtlpriv->btcoexist.hw_coexist_all_off = false;
202 } else { 192 } else {
203 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, "PTA mode off\n"); 193 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, "PTA mode off\n");
204 rtl_write_byte(rtlpriv, 0x40, 0x0); 194 rtl_write_byte(rtlpriv, 0x40, 0x0);
205 } 195 }
206} 196}
207 197
208static void rtl8723ae_dm_bt_set_sw_rf_rx_lpf_corner(struct ieee80211_hw *hw, 198static void rtl8723e_dm_bt_set_sw_rf_rx_lpf_corner(struct ieee80211_hw *hw,
209 u8 type) 199 u8 type)
210{ 200{
211 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
212 struct rtl_priv *rtlpriv = rtl_priv(hw); 201 struct rtl_priv *rtlpriv = rtl_priv(hw);
213 202
214 if (BT_RF_RX_LPF_CORNER_SHRINK == type) { 203 if (BT_RF_RX_LPF_CORNER_SHRINK == type) {
215 /* Shrink RF Rx LPF corner, 0x1e[7:4]=1111 ==> [11:4] by Jenyu*/ 204 /* Shrink RF Rx LPF corner, 0x1e[7:4]=1111 ==> [11:4] */
216 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 205 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
217 "Shrink RF Rx LPF corner!!\n"); 206 "Shrink RF Rx LPF corner!!\n");
218 rtl8723ae_phy_set_rf_reg(hw, RF90_PATH_A, 0x1e, 0xfffff, 207 rtl8723e_phy_set_rf_reg(hw, RF90_PATH_A, 0x1e,
219 0xf0ff7); 208 0xfffff, 0xf0ff7);
220 rtlpcipriv->bt_coexist.sw_coexist_all_off = false; 209 rtlpriv->btcoexist.sw_coexist_all_off = false;
221 } else if (BT_RF_RX_LPF_CORNER_RESUME == type) { 210 } else if (BT_RF_RX_LPF_CORNER_RESUME == type) {
222 /*Resume RF Rx LPF corner*/ 211 /*Resume RF Rx LPF corner*/
223 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 212 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
224 "Resume RF Rx LPF corner!!\n"); 213 "Resume RF Rx LPF corner!!\n");
225 rtl8723ae_phy_set_rf_reg(hw, RF90_PATH_A, 0x1e, 0xfffff, 214 rtl8723e_phy_set_rf_reg(hw, RF90_PATH_A, 0x1e, 0xfffff,
226 rtlpcipriv->bt_coexist.bt_rfreg_origin_1e); 215 rtlpriv->btcoexist.bt_rfreg_origin_1e);
227 } 216 }
228} 217}
229 218
230static void rtl8723ae_bt_set_penalty_tx_rate_adap(struct ieee80211_hw *hw, 219static void dm_bt_set_sw_penalty_tx_rate_adapt(struct ieee80211_hw *hw,
231 u8 ra_type) 220 u8 ra_type)
232{ 221{
233 struct rtl_priv *rtlpriv = rtl_priv(hw); 222 struct rtl_priv *rtlpriv = rtl_priv(hw);
234 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 223 u8 tmp_u1;
235 u8 tmu1;
236 224
237 tmu1 = rtl_read_byte(rtlpriv, 0x4fd); 225 tmp_u1 = rtl_read_byte(rtlpriv, 0x4fd);
238 tmu1 |= BIT(0); 226 tmp_u1 |= BIT(0);
239 if (BT_TX_RATE_ADAPTIVE_LOW_PENALTY == ra_type) { 227 if (BT_TX_RATE_ADAPTIVE_LOW_PENALTY == ra_type) {
240 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 228 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
241 "Tx rate adaptive, set low penalty!!\n"); 229 "Tx rate adaptive, set low penalty!!\n");
242 tmu1 &= ~BIT(2); 230 tmp_u1 &= ~BIT(2);
243 rtlpcipriv->bt_coexist.sw_coexist_all_off = false; 231 rtlpriv->btcoexist.sw_coexist_all_off = false;
244 } else if (BT_TX_RATE_ADAPTIVE_NORMAL == ra_type) { 232 } else if (BT_TX_RATE_ADAPTIVE_NORMAL == ra_type) {
245 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 233 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
246 "Tx rate adaptive, set normal!!\n"); 234 "Tx rate adaptive, set normal!!\n");
247 tmu1 |= BIT(2); 235 tmp_u1 |= BIT(2);
248 } 236 }
249 rtl_write_byte(rtlpriv, 0x4fd, tmu1); 237
238 rtl_write_byte(rtlpriv, 0x4fd, tmp_u1);
250} 239}
251 240
252static void rtl8723ae_dm_bt_btdm_structure_reload(struct ieee80211_hw *hw, 241static void rtl8723e_dm_bt_btdm_structure_reload(struct ieee80211_hw *hw,
253 struct btdm_8723 *btdm) 242 struct btdm_8723 *btdm)
254{ 243{
255 btdm->all_off = false; 244 btdm->all_off = false;
@@ -292,32 +281,31 @@ static void rtl8723ae_dm_bt_btdm_structure_reload(struct ieee80211_hw *hw,
292 btdm->dec_bt_pwr = false; 281 btdm->dec_bt_pwr = false;
293} 282}
294 283
295static void dm_bt_btdm_structure_reload_all_off(struct ieee80211_hw *hw, 284static void rtl8723e_dm_bt_btdm_structure_reload_all_off(struct ieee80211_hw *hw,
296 struct btdm_8723 *btdm) 285 struct btdm_8723 *btdm)
297{ 286{
298 rtl8723ae_dm_bt_btdm_structure_reload(hw, btdm); 287 rtl8723e_dm_bt_btdm_structure_reload(hw, btdm);
299 btdm->all_off = true; 288 btdm->all_off = true;
300 btdm->pta_on = false; 289 btdm->pta_on = false;
301 btdm->wlan_act_hi = 0x10; 290 btdm->wlan_act_hi = 0x10;
302} 291}
303 292
304static bool rtl8723ae_dm_bt_is_2_ant_common_action(struct ieee80211_hw *hw) 293static bool rtl8723e_dm_bt_is_2_ant_common_action(struct ieee80211_hw *hw)
305{ 294{
306 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
307 struct rtl_priv *rtlpriv = rtl_priv(hw); 295 struct rtl_priv *rtlpriv = rtl_priv(hw);
308 struct btdm_8723 btdm8723; 296 struct btdm_8723 btdm8723;
309 bool common = false; 297 bool b_common = false;
310 298
311 rtl8723ae_dm_bt_btdm_structure_reload(hw, &btdm8723); 299 rtl8723e_dm_bt_btdm_structure_reload(hw, &btdm8723);
312 300
313 if (!rtl8723ae_dm_bt_is_wifi_busy(hw) 301 if (!rtl8723e_dm_bt_is_wifi_busy(hw) &&
314 && !rtlpcipriv->bt_coexist.bt_busy) { 302 !rtlpriv->btcoexist.bt_busy) {
315 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 303 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
316 "Wifi idle + Bt idle, bt coex mechanism always off!!\n"); 304 "Wifi idle + Bt idle, bt coex mechanism always off!!\n");
317 dm_bt_btdm_structure_reload_all_off(hw, &btdm8723); 305 rtl8723e_dm_bt_btdm_structure_reload_all_off(hw, &btdm8723);
318 common = true; 306 b_common = true;
319 } else if (rtl8723ae_dm_bt_is_wifi_busy(hw) 307 } else if (rtl8723e_dm_bt_is_wifi_busy(hw) &&
320 && !rtlpcipriv->bt_coexist.bt_busy) { 308 !rtlpriv->btcoexist.bt_busy) {
321 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 309 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
322 "Wifi non-idle + Bt disabled/idle!!\n"); 310 "Wifi non-idle + Bt disabled/idle!!\n");
323 btdm8723.low_penalty_rate_adaptive = true; 311 btdm8723.low_penalty_rate_adaptive = true;
@@ -338,17 +326,17 @@ static bool rtl8723ae_dm_bt_is_2_ant_common_action(struct ieee80211_hw *hw)
338 btdm8723.tdma_dac_swing = TDMA_DAC_SWING_OFF; 326 btdm8723.tdma_dac_swing = TDMA_DAC_SWING_OFF;
339 btdm8723.b2_ant_hid_en = false; 327 btdm8723.b2_ant_hid_en = false;
340 328
341 common = true; 329 b_common = true;
342 } else if (rtlpcipriv->bt_coexist.bt_busy) { 330 } else if (rtlpriv->btcoexist.bt_busy) {
343 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 331 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
344 "Bt non-idle!\n"); 332 "Bt non-idle!\n");
345 if (mgnt_link_status_query(hw) == RT_MEDIA_CONNECT) { 333 if (mgnt_link_status_query(hw) == RT_MEDIA_CONNECT) {
346 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 334 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
347 "Wifi connection exist\n"); 335 "Wifi connection exist\n");
348 common = false; 336 b_common = false;
349 } else { 337 } else {
350 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 338 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
351 "No Wifi connection!\n"); 339 "No Wifi connection!\n");
352 btdm8723.rf_rx_lpf_shrink = true; 340 btdm8723.rf_rx_lpf_shrink = true;
353 btdm8723.low_penalty_rate_adaptive = false; 341 btdm8723.low_penalty_rate_adaptive = false;
354 btdm8723.reject_aggre_pkt = false; 342 btdm8723.reject_aggre_pkt = false;
@@ -367,27 +355,28 @@ static bool rtl8723ae_dm_bt_is_2_ant_common_action(struct ieee80211_hw *hw)
367 btdm8723.tdma_dac_swing = TDMA_DAC_SWING_OFF; 355 btdm8723.tdma_dac_swing = TDMA_DAC_SWING_OFF;
368 btdm8723.b2_ant_hid_en = false; 356 btdm8723.b2_ant_hid_en = false;
369 357
370 common = true; 358 b_common = true;
371 } 359 }
372 } 360 }
373 361
374 if (rtl8723ae_dm_bt_need_to_dec_bt_pwr(hw)) 362 if (rtl8723e_dm_bt_need_to_dec_bt_pwr(hw))
375 btdm8723.dec_bt_pwr = true; 363 btdm8723.dec_bt_pwr = true;
376 364
377 if (common) 365 if (b_common)
378 rtlpcipriv->bt_coexist.cstate |= BT_COEX_STATE_BTINFO_COMMON; 366 rtlpriv->btcoexist.cstate |=
367 BT_COEX_STATE_BTINFO_COMMON;
379 368
380 if (common && rtl8723ae_dm_bt_is_coexist_state_changed(hw)) 369 if (b_common && rtl8723e_dm_bt_is_coexist_state_changed(hw))
381 rtl8723ae_dm_bt_set_bt_dm(hw, &btdm8723); 370 rtl8723e_dm_bt_set_bt_dm(hw, &btdm8723);
382 371
383 return common; 372 return b_common;
384} 373}
385 374
386static void rtl8723ae_dm_bt_set_sw_full_time_dac_swing(struct ieee80211_hw *hw, 375static void rtl8723e_dm_bt_set_sw_full_time_dac_swing(
387 bool sw_dac_swing_on, 376 struct ieee80211_hw *hw,
388 u32 sw_dac_swing_lvl) 377 bool sw_dac_swing_on,
378 u32 sw_dac_swing_lvl)
389{ 379{
390 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
391 struct rtl_priv *rtlpriv = rtl_priv(hw); 380 struct rtl_priv *rtlpriv = rtl_priv(hw);
392 381
393 if (sw_dac_swing_on) { 382 if (sw_dac_swing_on) {
@@ -395,7 +384,7 @@ static void rtl8723ae_dm_bt_set_sw_full_time_dac_swing(struct ieee80211_hw *hw,
395 "[BTCoex], SwDacSwing = 0x%x\n", sw_dac_swing_lvl); 384 "[BTCoex], SwDacSwing = 0x%x\n", sw_dac_swing_lvl);
396 rtl8723_phy_set_bb_reg(hw, 0x880, 0xff000000, 385 rtl8723_phy_set_bb_reg(hw, 0x880, 0xff000000,
397 sw_dac_swing_lvl); 386 sw_dac_swing_lvl);
398 rtlpcipriv->bt_coexist.sw_coexist_all_off = false; 387 rtlpriv->btcoexist.sw_coexist_all_off = false;
399 } else { 388 } else {
400 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 389 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
401 "[BTCoex], SwDacSwing Off!\n"); 390 "[BTCoex], SwDacSwing Off!\n");
@@ -403,10 +392,9 @@ static void rtl8723ae_dm_bt_set_sw_full_time_dac_swing(struct ieee80211_hw *hw,
403 } 392 }
404} 393}
405 394
406static void rtl8723ae_dm_bt_set_fw_dec_bt_pwr(struct ieee80211_hw *hw, 395static void rtl8723e_dm_bt_set_fw_dec_bt_pwr(
407 bool dec_bt_pwr) 396 struct ieee80211_hw *hw, bool dec_bt_pwr)
408{ 397{
409 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
410 struct rtl_priv *rtlpriv = rtl_priv(hw); 398 struct rtl_priv *rtlpriv = rtl_priv(hw);
411 u8 h2c_parameter[1] = {0}; 399 u8 h2c_parameter[1] = {0};
412 400
@@ -414,87 +402,86 @@ static void rtl8723ae_dm_bt_set_fw_dec_bt_pwr(struct ieee80211_hw *hw,
414 402
415 if (dec_bt_pwr) { 403 if (dec_bt_pwr) {
416 h2c_parameter[0] |= BIT(1); 404 h2c_parameter[0] |= BIT(1);
417 rtlpcipriv->bt_coexist.fw_coexist_all_off = false; 405 rtlpriv->btcoexist.fw_coexist_all_off = false;
418 } 406 }
419 407
420 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 408 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
421 "[BTCoex], decrease Bt Power : %s, write 0x21 = 0x%x\n", 409 "[BTCoex], decrease Bt Power : %s, write 0x21=0x%x\n",
422 (dec_bt_pwr ? "Yes!!" : "No!!"), h2c_parameter[0]); 410 (dec_bt_pwr ? "Yes!!" : "No!!"), h2c_parameter[0]);
423 411
424 rtl8723ae_fill_h2c_cmd(hw, 0x21, 1, h2c_parameter); 412 rtl8723e_fill_h2c_cmd(hw, 0x21, 1, h2c_parameter);
425} 413}
426 414
427static void rtl8723ae_dm_bt_set_fw_2_ant_hid(struct ieee80211_hw *hw, 415static void rtl8723e_dm_bt_set_fw_2_ant_hid(struct ieee80211_hw *hw,
428 bool enable, bool dac_swing_on) 416 bool b_enable, bool b_dac_swing_on)
429{ 417{
430 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
431 struct rtl_priv *rtlpriv = rtl_priv(hw); 418 struct rtl_priv *rtlpriv = rtl_priv(hw);
432 u8 h2c_parameter[1] = {0}; 419 u8 h2c_parameter[1] = {0};
433 420
434 if (enable) { 421 if (b_enable) {
435 h2c_parameter[0] |= BIT(0); 422 h2c_parameter[0] |= BIT(0);
436 rtlpcipriv->bt_coexist.fw_coexist_all_off = false; 423 rtlpriv->btcoexist.fw_coexist_all_off = false;
437 } 424 }
438 if (dac_swing_on) 425 if (b_dac_swing_on)
439 h2c_parameter[0] |= BIT(1); /* Dac Swing default enable */ 426 h2c_parameter[0] |= BIT(1); /* Dac Swing default enable */
427
440 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 428 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
441 "[BTCoex], turn 2-Ant+HID mode %s, DACSwing:%s, write 0x15 = 0x%x\n", 429 "[BTCoex], turn 2-Ant+HID mode %s, DACSwing:%s, write 0x15=0x%x\n",
442 (enable ? "ON!!" : "OFF!!"), (dac_swing_on ? "ON" : "OFF"), 430 (b_enable ? "ON!!" : "OFF!!"), (b_dac_swing_on ? "ON" : "OFF"),
443 h2c_parameter[0]); 431 h2c_parameter[0]);
444 432
445 rtl8723ae_fill_h2c_cmd(hw, 0x15, 1, h2c_parameter); 433 rtl8723e_fill_h2c_cmd(hw, 0x15, 1, h2c_parameter);
446} 434}
447 435
448static void rtl8723ae_dm_bt_set_fw_tdma_ctrl(struct ieee80211_hw *hw, 436static void rtl8723e_dm_bt_set_fw_tdma_ctrl(struct ieee80211_hw *hw,
449 bool enable, u8 ant_num, u8 nav_en, 437 bool b_enable, u8 ant_num,
450 u8 dac_swing_en) 438 u8 nav_en, u8 dac_swing_en)
451{ 439{
452 struct rtl_priv *rtlpriv = rtl_priv(hw); 440 struct rtl_priv *rtlpriv = rtl_priv(hw);
453 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
454 u8 h2c_parameter[1] = {0}; 441 u8 h2c_parameter[1] = {0};
455 u8 h2c_parameter1[1] = {0}; 442 u8 h2c_parameter1[1] = {0};
456 443
457 h2c_parameter[0] = 0; 444 h2c_parameter[0] = 0;
458 h2c_parameter1[0] = 0; 445 h2c_parameter1[0] = 0;
459 446
460 if (enable) { 447 if (b_enable) {
461 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 448 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
462 "[BTCoex], set BT PTA update manager to trigger update!!\n"); 449 "[BTCoex], set BT PTA update manager to trigger update!!\n");
463 h2c_parameter1[0] |= BIT(0); 450 h2c_parameter1[0] |= BIT(0);
464 451
465 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 452 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
466 "[BTCoex], turn TDMA mode ON!!\n"); 453 "[BTCoex], turn TDMA mode ON!!\n");
467 h2c_parameter[0] |= BIT(0); /* function enable */ 454 h2c_parameter[0] |= BIT(0); /* function enable */
468 if (TDMA_1ANT == ant_num) { 455 if (TDMA_1ANT == ant_num) {
469 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 456 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
470 "[BTCoex], TDMA_1ANT\n"); 457 "[BTCoex], TDMA_1ANT\n");
471 h2c_parameter[0] |= BIT(1); 458 h2c_parameter[0] |= BIT(1);
472 } else if (TDMA_2ANT == ant_num) { 459 } else if (TDMA_2ANT == ant_num) {
473 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 460 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
474 "[BTCoex], TDMA_2ANT\n"); 461 "[BTCoex], TDMA_2ANT\n");
475 } else { 462 } else {
476 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 463 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
477 "[BTCoex], Unknown Ant\n"); 464 "[BTCoex], Unknown Ant\n");
478 } 465 }
479 466
480 if (TDMA_NAV_OFF == nav_en) { 467 if (TDMA_NAV_OFF == nav_en) {
481 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 468 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
482 "[BTCoex], TDMA_NAV_OFF\n"); 469 "[BTCoex], TDMA_NAV_OFF\n");
483 } else if (TDMA_NAV_ON == nav_en) { 470 } else if (TDMA_NAV_ON == nav_en) {
484 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 471 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
485 "[BTCoex], TDMA_NAV_ON\n"); 472 "[BTCoex], TDMA_NAV_ON\n");
486 h2c_parameter[0] |= BIT(2); 473 h2c_parameter[0] |= BIT(2);
487 } 474 }
488 475
489 if (TDMA_DAC_SWING_OFF == dac_swing_en) { 476 if (TDMA_DAC_SWING_OFF == dac_swing_en) {
490 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 477 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
491 "[BTCoex], TDMA_DAC_SWING_OFF\n"); 478 "[BTCoex], TDMA_DAC_SWING_OFF\n");
492 } else if (TDMA_DAC_SWING_ON == dac_swing_en) { 479 } else if (TDMA_DAC_SWING_ON == dac_swing_en) {
493 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 480 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
494 "[BTCoex], TDMA_DAC_SWING_ON\n"); 481 "[BTCoex], TDMA_DAC_SWING_ON\n");
495 h2c_parameter[0] |= BIT(4); 482 h2c_parameter[0] |= BIT(4);
496 } 483 }
497 rtlpcipriv->bt_coexist.fw_coexist_all_off = false; 484 rtlpriv->btcoexist.fw_coexist_all_off = false;
498 } else { 485 } else {
499 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 486 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
500 "[BTCoex], set BT PTA update manager to no update!!\n"); 487 "[BTCoex], set BT PTA update manager to no update!!\n");
@@ -503,46 +490,46 @@ static void rtl8723ae_dm_bt_set_fw_tdma_ctrl(struct ieee80211_hw *hw,
503 } 490 }
504 491
505 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 492 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
506 "[BTCoex], FW2AntTDMA, write 0x26 = 0x%x\n", 493 "[BTCoex], FW2AntTDMA, write 0x26=0x%x\n",
507 h2c_parameter1[0]); 494 h2c_parameter1[0]);
508 rtl8723ae_fill_h2c_cmd(hw, 0x26, 1, h2c_parameter1); 495 rtl8723e_fill_h2c_cmd(hw, 0x26, 1, h2c_parameter1);
509 496
510 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 497 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
511 "[BTCoex], FW2AntTDMA, write 0x14 = 0x%x\n", h2c_parameter[0]); 498 "[BTCoex], FW2AntTDMA, write 0x14=0x%x\n",
512 rtl8723ae_fill_h2c_cmd(hw, 0x14, 1, h2c_parameter); 499 h2c_parameter[0]);
500 rtl8723e_fill_h2c_cmd(hw, 0x14, 1, h2c_parameter);
513} 501}
514 502
515static void rtl8723ae_dm_bt_set_fw_ignore_wlan_act(struct ieee80211_hw *hw, 503static void rtl8723e_dm_bt_set_fw_ignore_wlan_act(struct ieee80211_hw *hw,
516 bool enable) 504 bool b_enable)
517{ 505{
518 struct rtl_priv *rtlpriv = rtl_priv(hw); 506 struct rtl_priv *rtlpriv = rtl_priv(hw);
519 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
520 u8 h2c_parameter[1] = {0}; 507 u8 h2c_parameter[1] = {0};
521 508
522 if (enable) { 509 if (b_enable) {
523 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 510 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
524 "[BTCoex], BT Ignore Wlan_Act !!\n"); 511 "[BTCoex], BT Ignore Wlan_Act !!\n");
525 h2c_parameter[0] |= BIT(0); /* function enable */ 512 h2c_parameter[0] |= BIT(0); /* function enable */
526 rtlpcipriv->bt_coexist.fw_coexist_all_off = false; 513 rtlpriv->btcoexist.fw_coexist_all_off = false;
527 } else { 514 } else {
528 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 515 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
529 "[BTCoex], BT don't ignore Wlan_Act !!\n"); 516 "[BTCoex], BT don't ignore Wlan_Act !!\n");
530 } 517 }
531 518
532 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 519 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
533 "[BTCoex], set FW for BT Ignore Wlan_Act, write 0x25 = 0x%x\n", 520 "[BTCoex], set FW for BT Ignore Wlan_Act, write 0x25=0x%x\n",
534 h2c_parameter[0]); 521 h2c_parameter[0]);
535 522
536 rtl8723ae_fill_h2c_cmd(hw, 0x25, 1, h2c_parameter); 523 rtl8723e_fill_h2c_cmd(hw, 0x25, 1, h2c_parameter);
537} 524}
538 525
539static void rtl8723ae_dm_bt_set_fw_tra_tdma_ctrl(struct ieee80211_hw *hw, 526static void rtl8723e_dm_bt_set_fw_tra_tdma_ctrl(struct ieee80211_hw *hw,
540 bool enable, u8 ant_num, 527 bool b_enable, u8 ant_num,
541 u8 nav_en) 528 u8 nav_en)
542{ 529{
543 struct rtl_priv *rtlpriv = rtl_priv(hw); 530 struct rtl_priv *rtlpriv = rtl_priv(hw);
544 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
545 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 531 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
532
546 u8 h2c_parameter[2] = {0}; 533 u8 h2c_parameter[2] = {0};
547 534
548 /* Only 8723 B cut should do this */ 535 /* Only 8723 B cut should do this */
@@ -552,460 +539,467 @@ static void rtl8723ae_dm_bt_set_fw_tra_tdma_ctrl(struct ieee80211_hw *hw,
552 return; 539 return;
553 } 540 }
554 541
555 if (enable) { 542 if (b_enable) {
556 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 543 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
557 "[BTCoex], turn TTDMA mode ON!!\n"); 544 "[BTCoex], turn TTDMA mode ON!!\n");
558 h2c_parameter[0] |= BIT(0); /* function enable */ 545 h2c_parameter[0] |= BIT(0); /* function enable */
559 if (TDMA_1ANT == ant_num) { 546 if (TDMA_1ANT == ant_num) {
560 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 547 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
561 "[BTCoex], TTDMA_1ANT\n"); 548 "[BTCoex], TTDMA_1ANT\n");
562 h2c_parameter[0] |= BIT(1); 549 h2c_parameter[0] |= BIT(1);
563 } else if (TDMA_2ANT == ant_num) { 550 } else if (TDMA_2ANT == ant_num) {
564 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 551 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
565 "[BTCoex], TTDMA_2ANT\n"); 552 "[BTCoex], TTDMA_2ANT\n");
566 } else { 553 } else {
567 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 554 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
568 "[BTCoex], Unknown Ant\n"); 555 "[BTCoex], Unknown Ant\n");
569 } 556 }
570 557
571 if (TDMA_NAV_OFF == nav_en) { 558 if (TDMA_NAV_OFF == nav_en) {
572 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 559 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
573 "[BTCoex], TTDMA_NAV_OFF\n"); 560 "[BTCoex], TTDMA_NAV_OFF\n");
574 } else if (TDMA_NAV_ON == nav_en) { 561 } else if (TDMA_NAV_ON == nav_en) {
575 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 562 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
576 "[BTCoex], TTDMA_NAV_ON\n"); 563 "[BTCoex], TTDMA_NAV_ON\n");
577 h2c_parameter[1] |= BIT(0); 564 h2c_parameter[1] |= BIT(0);
578 } 565 }
579 566
580 rtlpcipriv->bt_coexist.fw_coexist_all_off = false; 567 rtlpriv->btcoexist.fw_coexist_all_off = false;
581 } else { 568 } else {
582 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 569 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
583 "[BTCoex], turn TTDMA mode OFF!!\n"); 570 "[BTCoex], turn TTDMA mode OFF!!\n");
584 } 571 }
585 572
586 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 573 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
587 "[BTCoex], FW Traditional TDMA, write 0x33 = 0x%x\n", 574 "[BTCoex], FW Traditional TDMA, write 0x33=0x%x\n",
588 h2c_parameter[0] << 8 | h2c_parameter[1]); 575 h2c_parameter[0] << 8 | h2c_parameter[1]);
589 576
590 rtl8723ae_fill_h2c_cmd(hw, 0x33, 2, h2c_parameter); 577 rtl8723e_fill_h2c_cmd(hw, 0x33, 2, h2c_parameter);
591} 578}
592 579
593static void rtl8723ae_dm_bt_set_fw_dac_swing_level(struct ieee80211_hw *hw, 580static void rtl8723e_dm_bt_set_fw_dac_swing_level(struct ieee80211_hw *hw,
594 u8 dac_swing_lvl) 581 u8 dac_swing_lvl)
595{ 582{
596 struct rtl_priv *rtlpriv = rtl_priv(hw); 583 struct rtl_priv *rtlpriv = rtl_priv(hw);
597 u8 h2c_parameter[1] = {0}; 584 u8 h2c_parameter[1] = {0};
598
599 h2c_parameter[0] = dac_swing_lvl; 585 h2c_parameter[0] = dac_swing_lvl;
600 586
601 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 587 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
602 "[BTCoex], Set Dac Swing Level = 0x%x\n", dac_swing_lvl); 588 "[BTCoex], Set Dac Swing Level=0x%x\n", dac_swing_lvl);
603 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 589 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
604 "[BTCoex], write 0x29 = 0x%x\n", h2c_parameter[0]); 590 "[BTCoex], write 0x29=0x%x\n", h2c_parameter[0]);
605 591
606 rtl8723ae_fill_h2c_cmd(hw, 0x29, 1, h2c_parameter); 592 rtl8723e_fill_h2c_cmd(hw, 0x29, 1, h2c_parameter);
607} 593}
608 594
609static void rtl8723ae_dm_bt_set_fw_bt_hid_info(struct ieee80211_hw *hw, 595static void rtl8723e_dm_bt_set_fw_bt_hid_info(struct ieee80211_hw *hw,
610 bool enable) 596 bool b_enable)
611{ 597{
612 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
613 struct rtl_priv *rtlpriv = rtl_priv(hw); 598 struct rtl_priv *rtlpriv = rtl_priv(hw);
614 u8 h2c_parameter[1] = {0}; 599 u8 h2c_parameter[1] = {0};
615
616 h2c_parameter[0] = 0; 600 h2c_parameter[0] = 0;
617 601
618 if (enable) { 602 if (b_enable) {
619 h2c_parameter[0] |= BIT(0); 603 h2c_parameter[0] |= BIT(0);
620 rtlpcipriv->bt_coexist.fw_coexist_all_off = false; 604 rtlpriv->btcoexist.fw_coexist_all_off = false;
621 } 605 }
622 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 606 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
623 "[BTCoex], Set BT HID information = 0x%x\n", enable); 607 "[BTCoex], Set BT HID information=0x%x\n", b_enable);
624 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 608 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
625 "[BTCoex], write 0x24 = 0x%x\n", h2c_parameter[0]); 609 "[BTCoex], write 0x24=0x%x\n", h2c_parameter[0]);
626 610
627 rtl8723ae_fill_h2c_cmd(hw, 0x24, 1, h2c_parameter); 611 rtl8723e_fill_h2c_cmd(hw, 0x24, 1, h2c_parameter);
628} 612}
629 613
630static void rtl8723ae_dm_bt_set_fw_bt_retry_index(struct ieee80211_hw *hw, 614static void rtl8723e_dm_bt_set_fw_bt_retry_index(struct ieee80211_hw *hw,
631 u8 retry_index) 615 u8 retry_index)
632{ 616{
633 struct rtl_priv *rtlpriv = rtl_priv(hw); 617 struct rtl_priv *rtlpriv = rtl_priv(hw);
634 u8 h2c_parameter[1] = {0}; 618 u8 h2c_parameter[1] = {0};
635
636 h2c_parameter[0] = retry_index; 619 h2c_parameter[0] = retry_index;
637 620
638 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 621 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
639 "[BTCoex], Set BT Retry Index=%d\n", retry_index); 622 "[BTCoex], Set BT Retry Index=%d\n", retry_index);
640 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 623 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
641 "[BTCoex], write 0x23 = 0x%x\n", h2c_parameter[0]); 624 "[BTCoex], write 0x23=0x%x\n", h2c_parameter[0]);
642 625
643 rtl8723ae_fill_h2c_cmd(hw, 0x23, 1, h2c_parameter); 626 rtl8723e_fill_h2c_cmd(hw, 0x23, 1, h2c_parameter);
644} 627}
645 628
646static void rtl8723ae_dm_bt_set_fw_wlan_act(struct ieee80211_hw *hw, 629static void rtl8723e_dm_bt_set_fw_wlan_act(struct ieee80211_hw *hw,
647 u8 wlan_act_hi, u8 wlan_act_lo) 630 u8 wlan_act_hi, u8 wlan_act_lo)
648{ 631{
649 struct rtl_priv *rtlpriv = rtl_priv(hw); 632 struct rtl_priv *rtlpriv = rtl_priv(hw);
650 u8 h2c_parameter_hi[1] = {0}; 633 u8 h2c_parameter_hi[1] = {0};
651 u8 h2c_parameter_lo[1] = {0}; 634 u8 h2c_parameter_lo[1] = {0};
652
653 h2c_parameter_hi[0] = wlan_act_hi; 635 h2c_parameter_hi[0] = wlan_act_hi;
654 h2c_parameter_lo[0] = wlan_act_lo; 636 h2c_parameter_lo[0] = wlan_act_lo;
655 637
656 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 638 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
657 "[BTCoex], Set WLAN_ACT Hi:Lo = 0x%x/0x%x\n", wlan_act_hi, 639 "[BTCoex], Set WLAN_ACT Hi:Lo=0x%x/0x%x\n",
658 wlan_act_lo); 640 wlan_act_hi, wlan_act_lo);
659 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 641 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
660 "[BTCoex], write 0x22 = 0x%x\n", h2c_parameter_hi[0]); 642 "[BTCoex], write 0x22=0x%x\n", h2c_parameter_hi[0]);
661 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 643 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
662 "[BTCoex], write 0x11 = 0x%x\n", h2c_parameter_lo[0]); 644 "[BTCoex], write 0x11=0x%x\n", h2c_parameter_lo[0]);
663 645
664 /* WLAN_ACT = High duration, unit:ms */ 646 /* WLAN_ACT = High duration, unit:ms */
665 rtl8723ae_fill_h2c_cmd(hw, 0x22, 1, h2c_parameter_hi); 647 rtl8723e_fill_h2c_cmd(hw, 0x22, 1, h2c_parameter_hi);
666 /* WLAN_ACT = Low duration, unit:3*625us */ 648 /* WLAN_ACT = Low duration, unit:3*625us */
667 rtl8723ae_fill_h2c_cmd(hw, 0x11, 1, h2c_parameter_lo); 649 rtl8723e_fill_h2c_cmd(hw, 0x11, 1, h2c_parameter_lo);
668} 650}
669 651
670void rtl8723ae_dm_bt_set_bt_dm(struct ieee80211_hw *hw, struct btdm_8723 *btdm) 652void rtl8723e_dm_bt_set_bt_dm(struct ieee80211_hw *hw,
653 struct btdm_8723 *btdm)
671{ 654{
672 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
673 struct rtl_priv *rtlpriv = rtl_priv(hw); 655 struct rtl_priv *rtlpriv = rtl_priv(hw);
674 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 656 struct btdm_8723 *btdm_8723 = &hal_coex_8723.btdm;
675 struct btdm_8723 *btdm_8723 = &rtlhal->hal_coex_8723.btdm;
676 u8 i; 657 u8 i;
658
677 bool fw_current_inpsmode = false; 659 bool fw_current_inpsmode = false;
678 bool fw_ps_awake = true; 660 bool fw_ps_awake = true;
679 661
680 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 662 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
681 (u8 *)(&fw_current_inpsmode)); 663 (u8 *)(&fw_current_inpsmode));
682 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON, 664 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
683 (u8 *)(&fw_ps_awake)); 665 (u8 *)(&fw_ps_awake));
684 666
685 /* check new setting is different than the old one, 667 /* check new setting is different with the old one, */
686 * if all the same, don't do the setting again. 668 /* if all the same, don't do the setting again. */
687 */
688 if (memcmp(btdm_8723, btdm, sizeof(struct btdm_8723)) == 0) { 669 if (memcmp(btdm_8723, btdm, sizeof(struct btdm_8723)) == 0) {
689 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 670 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
690 "[BTCoex], the same coexist setting, return!!\n"); 671 "[BTCoex], the same coexist setting, return!!\n");
691 return; 672 return;
692 } else { /* save the new coexist setting */ 673 } else { /* save the new coexist setting */
693 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 674 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
694 "[BTCoex], UPDATE TO NEW COEX SETTING!!\n"); 675 "[BTCoex], UPDATE TO NEW COEX SETTING!!\n");
695 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 676 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
696 "[BTCoex], original/new bAllOff = 0x%x/ 0x%x\n", 677 "[BTCoex], original/new bAllOff=0x%x/ 0x%x\n",
697 btdm_8723->all_off, btdm->all_off); 678 btdm_8723->all_off, btdm->all_off);
698 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 679 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
699 "[BTCoex], original/new agc_table_en = 0x%x/ 0x%x\n", 680 "[BTCoex], original/new agc_table_en=0x%x/ 0x%x\n",
700 btdm_8723->agc_table_en, btdm->agc_table_en); 681 btdm_8723->agc_table_en, btdm->agc_table_en);
701 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 682 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
702 "[BTCoex], original/new adc_back_off_on = 0x%x/ 0x%x\n", 683 "[BTCoex], original/new adc_back_off_on=0x%x/ 0x%x\n",
703 btdm_8723->adc_back_off_on, btdm->adc_back_off_on); 684 btdm_8723->adc_back_off_on,
685 btdm->adc_back_off_on);
704 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 686 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
705 "[BTCoex], original/new b2_ant_hid_en = 0x%x/ 0x%x\n", 687 "[BTCoex], original/new b2_ant_hid_en=0x%x/ 0x%x\n",
706 btdm_8723->b2_ant_hid_en, btdm->b2_ant_hid_en); 688 btdm_8723->b2_ant_hid_en, btdm->b2_ant_hid_en);
707 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 689 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
708 "[BTCoex], original/new bLowPenaltyRateAdaptive = 0x%x/ 0x%x\n", 690 "[BTCoex], original/new bLowPenaltyRateAdaptive=0x%x/ 0x%x\n",
709 btdm_8723->low_penalty_rate_adaptive, 691 btdm_8723->low_penalty_rate_adaptive,
710 btdm->low_penalty_rate_adaptive); 692 btdm->low_penalty_rate_adaptive);
711 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 693 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
712 "[BTCoex], original/new bRfRxLpfShrink = 0x%x/ 0x%x\n", 694 "[BTCoex], original/new bRfRxLpfShrink=0x%x/ 0x%x\n",
713 btdm_8723->rf_rx_lpf_shrink, btdm->rf_rx_lpf_shrink); 695 btdm_8723->rf_rx_lpf_shrink,
696 btdm->rf_rx_lpf_shrink);
714 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 697 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
715 "[BTCoex], original/new bRejectAggrePkt = 0x%x/ 0x%x\n", 698 "[BTCoex], original/new bRejectAggrePkt=0x%x/ 0x%x\n",
716 btdm_8723->reject_aggre_pkt, btdm->reject_aggre_pkt); 699 btdm_8723->reject_aggre_pkt,
700 btdm->reject_aggre_pkt);
717 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 701 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
718 "[BTCoex], original/new tdma_on = 0x%x/ 0x%x\n", 702 "[BTCoex], original/new tdma_on=0x%x/ 0x%x\n",
719 btdm_8723->tdma_on, btdm->tdma_on); 703 btdm_8723->tdma_on, btdm->tdma_on);
720 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 704 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
721 "[BTCoex], original/new tdmaAnt = 0x%x/ 0x%x\n", 705 "[BTCoex], original/new tdmaAnt=0x%x/ 0x%x\n",
722 btdm_8723->tdma_ant, btdm->tdma_ant); 706 btdm_8723->tdma_ant, btdm->tdma_ant);
723 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 707 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
724 "[BTCoex], original/new tdmaNav = 0x%x/ 0x%x\n", 708 "[BTCoex], original/new tdmaNav=0x%x/ 0x%x\n",
725 btdm_8723->tdma_nav, btdm->tdma_nav); 709 btdm_8723->tdma_nav, btdm->tdma_nav);
726 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 710 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
727 "[BTCoex], original/new tdma_dac_swing = 0x%x/ 0x%x\n", 711 "[BTCoex], original/new tdma_dac_swing=0x%x/ 0x%x\n",
728 btdm_8723->tdma_dac_swing, btdm->tdma_dac_swing); 712 btdm_8723->tdma_dac_swing, btdm->tdma_dac_swing);
729 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 713 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
730 "[BTCoex], original/new fwDacSwingLvl = 0x%x/ 0x%x\n", 714 "[BTCoex], original/new fw_dac_swing_lvl=0x%x/ 0x%x\n",
731 btdm_8723->fw_dac_swing_lvl, btdm->fw_dac_swing_lvl); 715 btdm_8723->fw_dac_swing_lvl,
716 btdm->fw_dac_swing_lvl);
732 717
733 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 718 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
734 "[BTCoex], original/new bTraTdmaOn = 0x%x/ 0x%x\n", 719 "[BTCoex], original/new bTraTdmaOn=0x%x/ 0x%x\n",
735 btdm_8723->tra_tdma_on, btdm->tra_tdma_on); 720 btdm_8723->tra_tdma_on, btdm->tra_tdma_on);
736 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 721 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
737 "[BTCoex], original/new traTdmaAnt = 0x%x/ 0x%x\n", 722 "[BTCoex], original/new traTdmaAnt=0x%x/ 0x%x\n",
738 btdm_8723->tra_tdma_ant, btdm->tra_tdma_ant); 723 btdm_8723->tra_tdma_ant, btdm->tra_tdma_ant);
739 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 724 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
740 "[BTCoex], original/new traTdmaNav = 0x%x/ 0x%x\n", 725 "[BTCoex], original/new traTdmaNav=0x%x/ 0x%x\n",
741 btdm_8723->tra_tdma_nav, btdm->tra_tdma_nav); 726 btdm_8723->tra_tdma_nav, btdm->tra_tdma_nav);
742 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 727 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
743 "[BTCoex], original/new bPsTdmaOn = 0x%x/ 0x%x\n", 728 "[BTCoex], original/new bPsTdmaOn=0x%x/ 0x%x\n",
744 btdm_8723->ps_tdma_on, btdm->ps_tdma_on); 729 btdm_8723->ps_tdma_on, btdm->ps_tdma_on);
745 for (i = 0; i < 5; i++) { 730 for (i = 0; i < 5; i++) {
746 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 731 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
747 "[BTCoex], original/new psTdmaByte[i] = 0x%x/ 0x%x\n", 732 "[BTCoex], original/new psTdmaByte[i]=0x%x/ 0x%x\n",
748 btdm_8723->ps_tdma_byte[i], 733 btdm_8723->ps_tdma_byte[i],
749 btdm->ps_tdma_byte[i]); 734 btdm->ps_tdma_byte[i]);
750 } 735 }
751 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 736 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
752 "[BTCoex], original/new bIgnoreWlanAct = 0x%x/ 0x%x\n", 737 "[BTCoex], original/new bIgnoreWlanAct=0x%x/ 0x%x\n",
753 btdm_8723->ignore_wlan_act, btdm->ignore_wlan_act); 738 btdm_8723->ignore_wlan_act,
739 btdm->ignore_wlan_act);
740
754 741
755 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 742 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
756 "[BTCoex], original/new bPtaOn = 0x%x/ 0x%x\n", 743 "[BTCoex], original/new bPtaOn=0x%x/ 0x%x\n",
757 btdm_8723->pta_on, btdm->pta_on); 744 btdm_8723->pta_on, btdm->pta_on);
758 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 745 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
759 "[BTCoex], original/new val_0x6c0 = 0x%x/ 0x%x\n", 746 "[BTCoex], original/new val_0x6c0=0x%x/ 0x%x\n",
760 btdm_8723->val_0x6c0, btdm->val_0x6c0); 747 btdm_8723->val_0x6c0, btdm->val_0x6c0);
761 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 748 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
762 "[BTCoex], original/new val_0x6c8 = 0x%x/ 0x%x\n", 749 "[BTCoex], original/new val_0x6c8=0x%x/ 0x%x\n",
763 btdm_8723->val_0x6c8, btdm->val_0x6c8); 750 btdm_8723->val_0x6c8, btdm->val_0x6c8);
764 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 751 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
765 "[BTCoex], original/new val_0x6cc = 0x%x/ 0x%x\n", 752 "[BTCoex], original/new val_0x6cc=0x%x/ 0x%x\n",
766 btdm_8723->val_0x6cc, btdm->val_0x6cc); 753 btdm_8723->val_0x6cc, btdm->val_0x6cc);
767 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 754 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
768 "[BTCoex], original/new sw_dac_swing_on = 0x%x/ 0x%x\n", 755 "[BTCoex], original/new sw_dac_swing_on=0x%x/ 0x%x\n",
769 btdm_8723->sw_dac_swing_on, btdm->sw_dac_swing_on); 756 btdm_8723->sw_dac_swing_on,
757 btdm->sw_dac_swing_on);
770 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 758 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
771 "[BTCoex], original/new sw_dac_swing_lvl = 0x%x/ 0x%x\n", 759 "[BTCoex], original/new sw_dac_swing_lvl=0x%x/ 0x%x\n",
772 btdm_8723->sw_dac_swing_lvl, 760 btdm_8723->sw_dac_swing_lvl,
773 btdm->sw_dac_swing_lvl); 761 btdm->sw_dac_swing_lvl);
774 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 762 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
775 "[BTCoex], original/new wlanActHi = 0x%x/ 0x%x\n", 763 "[BTCoex], original/new wlanActHi=0x%x/ 0x%x\n",
776 btdm_8723->wlan_act_hi, btdm->wlan_act_hi); 764 btdm_8723->wlan_act_hi, btdm->wlan_act_hi);
777 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 765 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
778 "[BTCoex], original/new wlanActLo = 0x%x/ 0x%x\n", 766 "[BTCoex], original/new wlanActLo=0x%x/ 0x%x\n",
779 btdm_8723->wlan_act_lo, btdm->wlan_act_lo); 767 btdm_8723->wlan_act_lo, btdm->wlan_act_lo);
780 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 768 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
781 "[BTCoex], original/new btRetryIndex = 0x%x/ 0x%x\n", 769 "[BTCoex], original/new btRetryIndex=0x%x/ 0x%x\n",
782 btdm_8723->bt_retry_index, btdm->bt_retry_index); 770 btdm_8723->bt_retry_index, btdm->bt_retry_index);
783 771
784 memcpy(btdm_8723, btdm, sizeof(struct btdm_8723)); 772 memcpy(btdm_8723, btdm, sizeof(struct btdm_8723));
785 } 773 }
786 /* 774 /* Here we only consider when Bt Operation
787 * Here we only consider when Bt Operation
788 * inquiry/paging/pairing is ON 775 * inquiry/paging/pairing is ON
789 * we only need to turn off TDMA 776 * we only need to turn off TDMA
790 */ 777 */
791 778
792 if (rtlpcipriv->bt_coexist.hold_for_bt_operation) { 779 if (rtlpriv->btcoexist.hold_for_bt_operation) {
793 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 780 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
794 "[BTCoex], set to ignore wlanAct for BT OP!!\n"); 781 "[BTCoex], set to ignore wlanAct for BT OP!!\n");
795 rtl8723ae_dm_bt_set_fw_ignore_wlan_act(hw, true); 782 rtl8723e_dm_bt_set_fw_ignore_wlan_act(hw, true);
796 return; 783 return;
797 } 784 }
798 785
799 if (btdm->all_off) { 786 if (btdm->all_off) {
800 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 787 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
801 "[BTCoex], disable all coexist mechanism !!\n"); 788 "[BTCoex], disable all coexist mechanism !!\n");
802 rtl8723ae_btdm_coex_all_off(hw); 789 rtl8723e_btdm_coex_all_off(hw);
803 return; 790 return;
804 } 791 }
805 792
806 rtl8723ae_dm_bt_reject_ap_aggregated_packet(hw, btdm->reject_aggre_pkt); 793 rtl8723e_dm_bt_reject_ap_aggregated_packet(hw, btdm->reject_aggre_pkt);
807 794
808 if (btdm->low_penalty_rate_adaptive) 795 if (btdm->low_penalty_rate_adaptive)
809 rtl8723ae_bt_set_penalty_tx_rate_adap(hw, 796 dm_bt_set_sw_penalty_tx_rate_adapt(hw, BT_TX_RATE_ADAPTIVE_LOW_PENALTY);
810 BT_TX_RATE_ADAPTIVE_LOW_PENALTY);
811 else 797 else
812 rtl8723ae_bt_set_penalty_tx_rate_adap(hw, 798 dm_bt_set_sw_penalty_tx_rate_adapt(hw,
813 BT_TX_RATE_ADAPTIVE_NORMAL); 799 BT_TX_RATE_ADAPTIVE_NORMAL);
814 800
815 if (btdm->rf_rx_lpf_shrink) 801 if (btdm->rf_rx_lpf_shrink)
816 rtl8723ae_dm_bt_set_sw_rf_rx_lpf_corner(hw, 802 rtl8723e_dm_bt_set_sw_rf_rx_lpf_corner(hw,
817 BT_RF_RX_LPF_CORNER_SHRINK); 803 BT_RF_RX_LPF_CORNER_SHRINK);
818 else 804 else
819 rtl8723ae_dm_bt_set_sw_rf_rx_lpf_corner(hw, 805 rtl8723e_dm_bt_set_sw_rf_rx_lpf_corner(hw,
820 BT_RF_RX_LPF_CORNER_RESUME); 806 BT_RF_RX_LPF_CORNER_RESUME);
821 807
822 if (btdm->agc_table_en) 808 if (btdm->agc_table_en)
823 rtl8723ae_dm_bt_agc_table(hw, BT_AGCTABLE_ON); 809 rtl8723e_dm_bt_agc_table(hw, BT_AGCTABLE_ON);
824 else 810 else
825 rtl8723ae_dm_bt_agc_table(hw, BT_AGCTABLE_OFF); 811 rtl8723e_dm_bt_agc_table(hw, BT_AGCTABLE_OFF);
826 812
827 if (btdm->adc_back_off_on) 813 if (btdm->adc_back_off_on)
828 rtl8723ae_dm_bt_bback_off_level(hw, BT_BB_BACKOFF_ON); 814 rtl8723e_dm_bt_bb_back_off_level(hw, BT_BB_BACKOFF_ON);
829 else 815 else
830 rtl8723ae_dm_bt_bback_off_level(hw, BT_BB_BACKOFF_OFF); 816 rtl8723e_dm_bt_bb_back_off_level(hw, BT_BB_BACKOFF_OFF);
831 817
832 rtl8723ae_dm_bt_set_fw_bt_retry_index(hw, btdm->bt_retry_index); 818 rtl8723e_dm_bt_set_fw_bt_retry_index(hw, btdm->bt_retry_index);
833 819
834 rtl8723ae_dm_bt_set_fw_dac_swing_level(hw, btdm->fw_dac_swing_lvl); 820 rtl8723e_dm_bt_set_fw_dac_swing_level(hw, btdm->fw_dac_swing_lvl);
835 rtl8723ae_dm_bt_set_fw_wlan_act(hw, btdm->wlan_act_hi, 821 rtl8723e_dm_bt_set_fw_wlan_act(hw, btdm->wlan_act_hi,
836 btdm->wlan_act_lo); 822 btdm->wlan_act_lo);
837 823
838 rtl8723ae_dm_bt_set_coex_table(hw, btdm->val_0x6c0, 824 rtl8723e_dm_bt_set_coex_table(hw, btdm->val_0x6c0,
839 btdm->val_0x6c8, btdm->val_0x6cc); 825 btdm->val_0x6c8, btdm->val_0x6cc);
840 rtl8723ae_dm_bt_set_hw_pta_mode(hw, btdm->pta_on); 826 rtl8723e_dm_bt_set_hw_pta_mode(hw, btdm->pta_on);
841 827
842 /* Note: There is a constraint between TDMA and 2AntHID 828 /* Note: There is a constraint between TDMA and 2AntHID
843 * Only one of 2AntHid and tdma can be turned on 829 * Only one of 2AntHid and tdma can be turn on
844 * We should turn off those mechanisms first 830 * We should turn off those mechanisms should be turned off first
845 * and then turn on them on. 831 * and then turn on those mechanisms should be turned on.
846 */ 832 */
847 if (btdm->b2_ant_hid_en) { 833 if (btdm->b2_ant_hid_en) {
848 /* turn off tdma */ 834 /* turn off tdma */
849 rtl8723ae_dm_bt_set_fw_tra_tdma_ctrl(hw, btdm->tra_tdma_on, 835 rtl8723e_dm_bt_set_fw_tra_tdma_ctrl(hw, btdm->tra_tdma_on,
850 btdm->tra_tdma_ant, 836 btdm->tra_tdma_ant,
851 btdm->tra_tdma_nav); 837 btdm->tra_tdma_nav);
852 rtl8723ae_dm_bt_set_fw_tdma_ctrl(hw, false, btdm->tdma_ant, 838 rtl8723e_dm_bt_set_fw_tdma_ctrl(hw, false, btdm->tdma_ant,
853 btdm->tdma_nav, 839 btdm->tdma_nav,
854 btdm->tdma_dac_swing); 840 btdm->tdma_dac_swing);
855 841
856 /* turn off Pstdma */ 842 /* turn off Pstdma */
857 rtl8723ae_dm_bt_set_fw_ignore_wlan_act(hw, 843 rtl8723e_dm_bt_set_fw_ignore_wlan_act(hw,
858 btdm->ignore_wlan_act); 844 btdm->ignore_wlan_act);
859 /* Antenna control by PTA, 0x870 = 0x300. */ 845 /* Antenna control by PTA, 0x870 = 0x300. */
860 rtl8723ae_dm_bt_set_fw_3a(hw, 0x0, 0x0, 0x0, 0x8, 0x0); 846 rtl8723e_dm_bt_set_fw_3a(hw, 0x0, 0x0, 0x0, 0x8, 0x0);
861 847
862 /* turn on 2AntHid */ 848 /* turn on 2AntHid */
863 rtl8723ae_dm_bt_set_fw_bt_hid_info(hw, true); 849 rtl8723e_dm_bt_set_fw_bt_hid_info(hw, true);
864 rtl8723ae_dm_bt_set_fw_2_ant_hid(hw, true, true); 850 rtl8723e_dm_bt_set_fw_2_ant_hid(hw, true, true);
865 } else if (btdm->tdma_on) { 851 } else if (btdm->tdma_on) {
866 /* turn off 2AntHid */ 852 /* turn off 2AntHid */
867 rtl8723ae_dm_bt_set_fw_bt_hid_info(hw, false); 853 rtl8723e_dm_bt_set_fw_bt_hid_info(hw, false);
868 rtl8723ae_dm_bt_set_fw_2_ant_hid(hw, false, false); 854 rtl8723e_dm_bt_set_fw_2_ant_hid(hw, false, false);
869 855
870 /* turn off pstdma */ 856 /* turn off pstdma */
871 rtl8723ae_dm_bt_set_fw_ignore_wlan_act(hw, 857 rtl8723e_dm_bt_set_fw_ignore_wlan_act(hw,
872 btdm->ignore_wlan_act); 858 btdm->ignore_wlan_act);
873 /* Antenna control by PTA, 0x870 = 0x300. */ 859 /* Antenna control by PTA, 0x870 = 0x300. */
874 rtl8723ae_dm_bt_set_fw_3a(hw, 0x0, 0x0, 0x0, 0x8, 0x0); 860 rtl8723e_dm_bt_set_fw_3a(hw, 0x0, 0x0, 0x0, 0x8, 0x0);
875 861
876 /* turn on tdma */ 862 /* turn on tdma */
877 rtl8723ae_dm_bt_set_fw_tra_tdma_ctrl(hw, btdm->tra_tdma_on, 863 rtl8723e_dm_bt_set_fw_tra_tdma_ctrl(hw, btdm->tra_tdma_on,
878 btdm->tra_tdma_ant, btdm->tra_tdma_nav); 864 btdm->tra_tdma_ant,
879 rtl8723ae_dm_bt_set_fw_tdma_ctrl(hw, true, btdm->tdma_ant, 865 btdm->tra_tdma_nav);
880 btdm->tdma_nav, btdm->tdma_dac_swing); 866 rtl8723e_dm_bt_set_fw_tdma_ctrl(hw, true, btdm->tdma_ant,
867 btdm->tdma_nav,
868 btdm->tdma_dac_swing);
881 } else if (btdm->ps_tdma_on) { 869 } else if (btdm->ps_tdma_on) {
882 /* turn off 2AntHid */ 870 /* turn off 2AntHid */
883 rtl8723ae_dm_bt_set_fw_bt_hid_info(hw, false); 871 rtl8723e_dm_bt_set_fw_bt_hid_info(hw, false);
884 rtl8723ae_dm_bt_set_fw_2_ant_hid(hw, false, false); 872 rtl8723e_dm_bt_set_fw_2_ant_hid(hw, false, false);
885 873
886 /* turn off tdma */ 874 /* turn off tdma */
887 rtl8723ae_dm_bt_set_fw_tra_tdma_ctrl(hw, btdm->tra_tdma_on, 875 rtl8723e_dm_bt_set_fw_tra_tdma_ctrl(hw, btdm->tra_tdma_on,
888 btdm->tra_tdma_ant, btdm->tra_tdma_nav); 876 btdm->tra_tdma_ant,
889 rtl8723ae_dm_bt_set_fw_tdma_ctrl(hw, false, btdm->tdma_ant, 877 btdm->tra_tdma_nav);
890 btdm->tdma_nav, btdm->tdma_dac_swing); 878 rtl8723e_dm_bt_set_fw_tdma_ctrl(hw, false, btdm->tdma_ant,
879 btdm->tdma_nav,
880 btdm->tdma_dac_swing);
891 881
892 /* turn on pstdma */ 882 /* turn on pstdma */
893 rtl8723ae_dm_bt_set_fw_ignore_wlan_act(hw, 883 rtl8723e_dm_bt_set_fw_ignore_wlan_act(hw,
894 btdm->ignore_wlan_act); 884 btdm->ignore_wlan_act);
895 rtl8723ae_dm_bt_set_fw_3a(hw, 885 rtl8723e_dm_bt_set_fw_3a(hw, btdm->ps_tdma_byte[0],
896 btdm->ps_tdma_byte[0], 886 btdm->ps_tdma_byte[1],
897 btdm->ps_tdma_byte[1], 887 btdm->ps_tdma_byte[2],
898 btdm->ps_tdma_byte[2], 888 btdm->ps_tdma_byte[3],
899 btdm->ps_tdma_byte[3], 889 btdm->ps_tdma_byte[4]);
900 btdm->ps_tdma_byte[4]);
901 } else { 890 } else {
902 /* turn off 2AntHid */ 891 /* turn off 2AntHid */
903 rtl8723ae_dm_bt_set_fw_bt_hid_info(hw, false); 892 rtl8723e_dm_bt_set_fw_bt_hid_info(hw, false);
904 rtl8723ae_dm_bt_set_fw_2_ant_hid(hw, false, false); 893 rtl8723e_dm_bt_set_fw_2_ant_hid(hw, false, false);
905 894
906 /* turn off tdma */ 895 /* turn off tdma */
907 rtl8723ae_dm_bt_set_fw_tra_tdma_ctrl(hw, btdm->tra_tdma_on, 896 rtl8723e_dm_bt_set_fw_tra_tdma_ctrl(hw, btdm->tra_tdma_on,
908 btdm->tra_tdma_ant, btdm->tra_tdma_nav); 897 btdm->tra_tdma_ant,
909 rtl8723ae_dm_bt_set_fw_tdma_ctrl(hw, false, btdm->tdma_ant, 898 btdm->tra_tdma_nav);
910 btdm->tdma_nav, btdm->tdma_dac_swing); 899 rtl8723e_dm_bt_set_fw_tdma_ctrl(hw, false, btdm->tdma_ant,
900 btdm->tdma_nav,
901 btdm->tdma_dac_swing);
911 902
912 /* turn off pstdma */ 903 /* turn off pstdma */
913 rtl8723ae_dm_bt_set_fw_ignore_wlan_act(hw, 904 rtl8723e_dm_bt_set_fw_ignore_wlan_act(hw,
914 btdm->ignore_wlan_act); 905 btdm->ignore_wlan_act);
915 /* Antenna control by PTA, 0x870 = 0x300. */ 906 /* Antenna control by PTA, 0x870 = 0x300. */
916 rtl8723ae_dm_bt_set_fw_3a(hw, 0x0, 0x0, 0x0, 0x8, 0x0); 907 rtl8723e_dm_bt_set_fw_3a(hw, 0x0, 0x0, 0x0, 0x8, 0x0);
917 } 908 }
918 909
919 /* Note: 910 /* Note:
920 * We should add delay for making sure sw DacSwing can be set 911 * We should add delay for making sure
921 * sucessfully. Because of that rtl8723ae_dm_bt_set_fw_2_ant_hid() 912 * sw DacSwing can be set sucessfully.
922 * and rtl8723ae_dm_bt_set_fw_tdma_ctrl() 913 * because of that rtl8723e_dm_bt_set_fw_2_ant_hid()
914 * and rtl8723e_dm_bt_set_fw_tdma_ctrl()
923 * will overwrite the reg 0x880. 915 * will overwrite the reg 0x880.
924 */ 916 */
925 mdelay(30); 917 mdelay(30);
926 rtl8723ae_dm_bt_set_sw_full_time_dac_swing(hw, 918 rtl8723e_dm_bt_set_sw_full_time_dac_swing(hw, btdm->sw_dac_swing_on,
927 btdm->sw_dac_swing_on, btdm->sw_dac_swing_lvl); 919 btdm->sw_dac_swing_lvl);
928 rtl8723ae_dm_bt_set_fw_dec_bt_pwr(hw, btdm->dec_bt_pwr); 920 rtl8723e_dm_bt_set_fw_dec_bt_pwr(hw, btdm->dec_bt_pwr);
929} 921}
930 922
931/*============================================================ 923/* ============================================================ */
932 * extern function start with BTDM_ 924/* extern function start with BTDM_ */
933 *============================================================ 925/* ============================================================i
934 */ 926 */
935static u32 rtl8723ae_dm_bt_tx_rx_couter_h(struct ieee80211_hw *hw) 927static u32 rtl8723e_dm_bt_tx_rx_couter_h(struct ieee80211_hw *hw)
936{ 928{
937 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 929 u32 counters = 0;
938 u32 counters = 0;
939 930
940 counters = rtlhal->hal_coex_8723.high_priority_tx + 931 counters = hal_coex_8723.high_priority_tx +
941 rtlhal->hal_coex_8723.high_priority_rx; 932 hal_coex_8723.high_priority_rx;
942 return counters; 933 return counters;
943} 934}
944 935
945static u32 rtl8723ae_dm_bt_tx_rx_couter_l(struct ieee80211_hw *hw) 936static u32 rtl8723e_dm_bt_tx_rx_couter_l(struct ieee80211_hw *hw)
946{ 937{
947 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 938 u32 counters = 0;
948 939
949 return rtlhal->hal_coex_8723.low_priority_tx + 940 counters = hal_coex_8723.low_priority_tx +
950 rtlhal->hal_coex_8723.low_priority_rx; 941 hal_coex_8723.low_priority_rx;
942 return counters;
951} 943}
952 944
953static u8 rtl8723ae_dm_bt_bt_tx_rx_counter_level(struct ieee80211_hw *hw) 945static u8 rtl8723e_dm_bt_bt_tx_rx_counter_level(struct ieee80211_hw *hw)
954{ 946{
955 struct rtl_priv *rtlpriv = rtl_priv(hw); 947 struct rtl_priv *rtlpriv = rtl_priv(hw);
956 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 948 u32 bt_tx_rx_cnt = 0;
957 u32 bt_tx_rx_cnt = 0; 949 u8 bt_tx_rx_cnt_lvl = 0;
958 u8 bt_tx_rx_cnt_lvl = 0;
959 950
960 bt_tx_rx_cnt = rtl8723ae_dm_bt_tx_rx_couter_h(hw) + 951 bt_tx_rx_cnt = rtl8723e_dm_bt_tx_rx_couter_h(hw)
961 rtl8723ae_dm_bt_tx_rx_couter_l(hw); 952 + rtl8723e_dm_bt_tx_rx_couter_l(hw);
962 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 953 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
963 "[BTCoex], BT TxRx Counters = %d\n", bt_tx_rx_cnt); 954 "[BTCoex], BT TxRx Counters = %d\n", bt_tx_rx_cnt);
964 955
965 rtlpcipriv->bt_coexist.cstate_h &= 956 rtlpriv->btcoexist.cstate_h &= ~
966 ~(BT_COEX_STATE_BT_CNT_LEVEL_0 | BT_COEX_STATE_BT_CNT_LEVEL_1 | 957 (BT_COEX_STATE_BT_CNT_LEVEL_0 | BT_COEX_STATE_BT_CNT_LEVEL_1|
967 BT_COEX_STATE_BT_CNT_LEVEL_2); 958 BT_COEX_STATE_BT_CNT_LEVEL_2);
968 959
969 if (bt_tx_rx_cnt >= BT_TXRX_CNT_THRES_3) { 960 if (bt_tx_rx_cnt >= BT_TXRX_CNT_THRES_3) {
970 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 961 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
971 "[BTCoex], BT TxRx Counters at level 3\n"); 962 "[BTCoex], BT TxRx Counters at level 3\n");
972 bt_tx_rx_cnt_lvl = BT_TXRX_CNT_LEVEL_3; 963 bt_tx_rx_cnt_lvl = BT_TXRX_CNT_LEVEL_3;
973 rtlpcipriv->bt_coexist.cstate_h |= BT_COEX_STATE_BT_CNT_LEVEL_3; 964 rtlpriv->btcoexist.cstate_h |=
965 BT_COEX_STATE_BT_CNT_LEVEL_3;
974 } else if (bt_tx_rx_cnt >= BT_TXRX_CNT_THRES_2) { 966 } else if (bt_tx_rx_cnt >= BT_TXRX_CNT_THRES_2) {
975 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 967 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
976 "[BTCoex], BT TxRx Counters at level 2\n"); 968 "[BTCoex], BT TxRx Counters at level 2\n");
977 bt_tx_rx_cnt_lvl = BT_TXRX_CNT_LEVEL_2; 969 bt_tx_rx_cnt_lvl = BT_TXRX_CNT_LEVEL_2;
978 rtlpcipriv->bt_coexist.cstate_h |= BT_COEX_STATE_BT_CNT_LEVEL_2; 970 rtlpriv->btcoexist.cstate_h |=
971 BT_COEX_STATE_BT_CNT_LEVEL_2;
979 } else if (bt_tx_rx_cnt >= BT_TXRX_CNT_THRES_1) { 972 } else if (bt_tx_rx_cnt >= BT_TXRX_CNT_THRES_1) {
980 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 973 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
981 "[BTCoex], BT TxRx Counters at level 1\n"); 974 "[BTCoex], BT TxRx Counters at level 1\n");
982 bt_tx_rx_cnt_lvl = BT_TXRX_CNT_LEVEL_1; 975 bt_tx_rx_cnt_lvl = BT_TXRX_CNT_LEVEL_1;
983 rtlpcipriv->bt_coexist.cstate_h |= BT_COEX_STATE_BT_CNT_LEVEL_1; 976 rtlpriv->btcoexist.cstate_h |=
977 BT_COEX_STATE_BT_CNT_LEVEL_1;
984 } else { 978 } else {
985 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 979 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
986 "[BTCoex], BT TxRx Counters at level 0\n"); 980 "[BTCoex], BT TxRx Counters at level 0\n");
987 bt_tx_rx_cnt_lvl = BT_TXRX_CNT_LEVEL_0; 981 bt_tx_rx_cnt_lvl = BT_TXRX_CNT_LEVEL_0;
988 rtlpcipriv->bt_coexist.cstate_h |= BT_COEX_STATE_BT_CNT_LEVEL_0; 982 rtlpriv->btcoexist.cstate_h |=
983 BT_COEX_STATE_BT_CNT_LEVEL_0;
989 } 984 }
990 return bt_tx_rx_cnt_lvl; 985 return bt_tx_rx_cnt_lvl;
991} 986}
992 987
993static void rtl8723ae_dm_bt_2_ant_hid_sco_esco(struct ieee80211_hw *hw) 988static void rtl8723e_dm_bt_2_ant_hid_sco_esco(struct ieee80211_hw *hw)
994{ 989{
995 struct rtl_priv *rtlpriv = rtl_priv(hw); 990 struct rtl_priv *rtlpriv = rtl_priv(hw);
996 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
997 struct rtl_phy *rtlphy = &(rtlpriv->phy); 991 struct rtl_phy *rtlphy = &(rtlpriv->phy);
998 struct btdm_8723 btdm8723; 992 struct btdm_8723 btdm8723;
999 u8 bt_rssi_state, bt_rssi_state1; 993 u8 bt_rssi_state, bt_rssi_state1;
1000 u8 bt_tx_rx_cnt_lvl; 994 u8 bt_tx_rx_cnt_lvl = 0;
1001 995
1002 rtl8723ae_dm_bt_btdm_structure_reload(hw, &btdm8723); 996 rtl8723e_dm_bt_btdm_structure_reload(hw, &btdm8723);
1003 997
1004 btdm8723.rf_rx_lpf_shrink = true; 998 btdm8723.rf_rx_lpf_shrink = true;
1005 btdm8723.low_penalty_rate_adaptive = true; 999 btdm8723.low_penalty_rate_adaptive = true;
1006 btdm8723.reject_aggre_pkt = false; 1000 btdm8723.reject_aggre_pkt = false;
1007 1001
1008 bt_tx_rx_cnt_lvl = rtl8723ae_dm_bt_bt_tx_rx_counter_level(hw); 1002 bt_tx_rx_cnt_lvl = rtl8723e_dm_bt_bt_tx_rx_counter_level(hw);
1009 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 1003 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
1010 "[BTCoex], BT TxRx Counters = %d\n", bt_tx_rx_cnt_lvl); 1004 "[BTCoex], BT TxRx Counters = %d\n", bt_tx_rx_cnt_lvl);
1011 1005
@@ -1051,10 +1045,10 @@ static void rtl8723ae_dm_bt_2_ant_hid_sco_esco(struct ieee80211_hw *hw)
1051 } else { 1045 } else {
1052 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 1046 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
1053 "HT20 or Legacy\n"); 1047 "HT20 or Legacy\n");
1054 bt_rssi_state = rtl8723ae_dm_bt_check_coex_rssi_state(hw, 2, 1048 bt_rssi_state =
1055 47, 0); 1049 rtl8723e_dm_bt_check_coex_rssi_state(hw, 2, 47, 0);
1056 bt_rssi_state1 = rtl8723ae_dm_bt_check_coex_rssi_state1(hw, 2, 1050 bt_rssi_state1 =
1057 27, 0); 1051 rtl8723e_dm_bt_check_coex_rssi_state1(hw, 2, 27, 0);
1058 1052
1059 /* coex table */ 1053 /* coex table */
1060 btdm8723.val_0x6c0 = 0x55555555; 1054 btdm8723.val_0x6c0 = 0x55555555;
@@ -1063,15 +1057,15 @@ static void rtl8723ae_dm_bt_2_ant_hid_sco_esco(struct ieee80211_hw *hw)
1063 1057
1064 /* sw mechanism */ 1058 /* sw mechanism */
1065 if ((bt_rssi_state == BT_RSSI_STATE_HIGH) || 1059 if ((bt_rssi_state == BT_RSSI_STATE_HIGH) ||
1066 (bt_rssi_state == BT_RSSI_STATE_STAY_HIGH)) { 1060 (bt_rssi_state == BT_RSSI_STATE_STAY_HIGH)) {
1067 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 1061 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
1068 "Wifi rssi high\n"); 1062 "Wifi rssi high\n");
1069 btdm8723.agc_table_en = true; 1063 btdm8723.agc_table_en = true;
1070 btdm8723.adc_back_off_on = true; 1064 btdm8723.adc_back_off_on = true;
1071 btdm8723.sw_dac_swing_on = false; 1065 btdm8723.sw_dac_swing_on = false;
1072 } else { 1066 } else {
1073 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 1067 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
1074 "Wifi rssi low\n"); 1068 "Wifi rssi low\n");
1075 btdm8723.agc_table_en = false; 1069 btdm8723.agc_table_en = false;
1076 btdm8723.adc_back_off_on = false; 1070 btdm8723.adc_back_off_on = false;
1077 btdm8723.sw_dac_swing_on = false; 1071 btdm8723.sw_dac_swing_on = false;
@@ -1080,16 +1074,15 @@ static void rtl8723ae_dm_bt_2_ant_hid_sco_esco(struct ieee80211_hw *hw)
1080 /* fw mechanism */ 1074 /* fw mechanism */
1081 btdm8723.ps_tdma_on = true; 1075 btdm8723.ps_tdma_on = true;
1082 if ((bt_rssi_state1 == BT_RSSI_STATE_HIGH) || 1076 if ((bt_rssi_state1 == BT_RSSI_STATE_HIGH) ||
1083 (bt_rssi_state1 == BT_RSSI_STATE_STAY_HIGH)) { 1077 (bt_rssi_state1 == BT_RSSI_STATE_STAY_HIGH)) {
1084 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 1078 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
1085 "Wifi rssi-1 high\n"); 1079 "Wifi rssi-1 high\n");
1086 /* only rssi high we need to do this, 1080 /* only rssi high we need to do this, */
1087 * when rssi low, the value will modified by fw 1081 /* when rssi low, the value will modified by fw */
1088 */
1089 rtl_write_byte(rtlpriv, 0x883, 0x40); 1082 rtl_write_byte(rtlpriv, 0x883, 0x40);
1090 if (bt_tx_rx_cnt_lvl == BT_TXRX_CNT_LEVEL_2) { 1083 if (bt_tx_rx_cnt_lvl == BT_TXRX_CNT_LEVEL_2) {
1091 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 1084 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
1092 "[BTCoex], BT TxRx Counters >= 1400\n"); 1085 "[BTCoex], BT TxRx Counters >= 1400\n");
1093 btdm8723.ps_tdma_byte[0] = 0xa3; 1086 btdm8723.ps_tdma_byte[0] = 0xa3;
1094 btdm8723.ps_tdma_byte[1] = 0x5; 1087 btdm8723.ps_tdma_byte[1] = 0x5;
1095 btdm8723.ps_tdma_byte[2] = 0x5; 1088 btdm8723.ps_tdma_byte[2] = 0x5;
@@ -1097,7 +1090,7 @@ static void rtl8723ae_dm_bt_2_ant_hid_sco_esco(struct ieee80211_hw *hw)
1097 btdm8723.ps_tdma_byte[4] = 0x80; 1090 btdm8723.ps_tdma_byte[4] = 0x80;
1098 } else if (bt_tx_rx_cnt_lvl == BT_TXRX_CNT_LEVEL_1) { 1091 } else if (bt_tx_rx_cnt_lvl == BT_TXRX_CNT_LEVEL_1) {
1099 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 1092 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
1100 "[BTCoex], BT TxRx Counters >= 1200 && < 1400\n"); 1093 "[BTCoex], BT TxRx Counters>= 1200 && < 1400\n");
1101 btdm8723.ps_tdma_byte[0] = 0xa3; 1094 btdm8723.ps_tdma_byte[0] = 0xa3;
1102 btdm8723.ps_tdma_byte[1] = 0xa; 1095 btdm8723.ps_tdma_byte[1] = 0xa;
1103 btdm8723.ps_tdma_byte[2] = 0xa; 1096 btdm8723.ps_tdma_byte[2] = 0xa;
@@ -1114,7 +1107,7 @@ static void rtl8723ae_dm_bt_2_ant_hid_sco_esco(struct ieee80211_hw *hw)
1114 } 1107 }
1115 } else { 1108 } else {
1116 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 1109 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
1117 "Wifi rssi-1 low\n"); 1110 "Wifi rssi-1 low\n");
1118 if (bt_tx_rx_cnt_lvl == BT_TXRX_CNT_LEVEL_2) { 1111 if (bt_tx_rx_cnt_lvl == BT_TXRX_CNT_LEVEL_2) {
1119 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 1112 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
1120 "[BTCoex], BT TxRx Counters >= 1400\n"); 1113 "[BTCoex], BT TxRx Counters >= 1400\n");
@@ -1143,16 +1136,15 @@ static void rtl8723ae_dm_bt_2_ant_hid_sco_esco(struct ieee80211_hw *hw)
1143 } 1136 }
1144 } 1137 }
1145 1138
1146 if (rtl8723ae_dm_bt_need_to_dec_bt_pwr(hw)) 1139 if (rtl8723e_dm_bt_need_to_dec_bt_pwr(hw))
1147 btdm8723.dec_bt_pwr = true; 1140 btdm8723.dec_bt_pwr = true;
1148 1141
1149 /* Always ignore WlanAct if bHid|bSCOBusy|bSCOeSCO */ 1142 /* Always ignore WlanAct if bHid|bSCOBusy|bSCOeSCO */
1150 1143
1151 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 1144 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
1152 "[BTCoex], BT btInqPageStartTime = 0x%x, btTxRxCntLvl = %d\n", 1145 "[BTCoex], BT btInqPageStartTime = 0x%x, btTxRxCntLvl = %d\n",
1153 rtlhal->hal_coex_8723.bt_inq_page_start_time, 1146 hal_coex_8723.bt_inq_page_start_time, bt_tx_rx_cnt_lvl);
1154 bt_tx_rx_cnt_lvl); 1147 if ((hal_coex_8723.bt_inq_page_start_time) ||
1155 if ((rtlhal->hal_coex_8723.bt_inq_page_start_time) ||
1156 (BT_TXRX_CNT_LEVEL_3 == bt_tx_rx_cnt_lvl)) { 1148 (BT_TXRX_CNT_LEVEL_3 == bt_tx_rx_cnt_lvl)) {
1157 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 1149 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
1158 "[BTCoex], Set BT inquiry / page scan 0x3a setting\n"); 1150 "[BTCoex], Set BT inquiry / page scan 0x3a setting\n");
@@ -1164,33 +1156,35 @@ static void rtl8723ae_dm_bt_2_ant_hid_sco_esco(struct ieee80211_hw *hw)
1164 btdm8723.ps_tdma_byte[4] = 0x80; 1156 btdm8723.ps_tdma_byte[4] = 0x80;
1165 } 1157 }
1166 1158
1167 if (rtl8723ae_dm_bt_is_coexist_state_changed(hw)) 1159 if (rtl8723e_dm_bt_is_coexist_state_changed(hw))
1168 rtl8723ae_dm_bt_set_bt_dm(hw, &btdm8723); 1160 rtl8723e_dm_bt_set_bt_dm(hw, &btdm8723);
1161
1169} 1162}
1170 1163
1171static void rtl8723ae_dm_bt_2_ant_fta2dp(struct ieee80211_hw *hw) 1164static void rtl8723e_dm_bt_2_ant_ftp_a2dp(struct ieee80211_hw *hw)
1172{ 1165{
1173 struct rtl_priv *rtlpriv = rtl_priv(hw); 1166 struct rtl_priv *rtlpriv = rtl_priv(hw);
1174 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1175 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1167 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1176 struct btdm_8723 btdm8723; 1168 struct btdm_8723 btdm8723;
1169
1177 u8 bt_rssi_state, bt_rssi_state1; 1170 u8 bt_rssi_state, bt_rssi_state1;
1178 u32 bt_tx_rx_cnt_lvl; 1171 u32 bt_tx_rx_cnt_lvl = 0;
1172
1173 rtl8723e_dm_bt_btdm_structure_reload(hw, &btdm8723);
1179 1174
1180 rtl8723ae_dm_bt_btdm_structure_reload(hw, &btdm8723);
1181 btdm8723.rf_rx_lpf_shrink = true; 1175 btdm8723.rf_rx_lpf_shrink = true;
1182 btdm8723.low_penalty_rate_adaptive = true; 1176 btdm8723.low_penalty_rate_adaptive = true;
1183 btdm8723.reject_aggre_pkt = false; 1177 btdm8723.reject_aggre_pkt = false;
1184 1178
1185 bt_tx_rx_cnt_lvl = rtl8723ae_dm_bt_bt_tx_rx_counter_level(hw); 1179 bt_tx_rx_cnt_lvl = rtl8723e_dm_bt_bt_tx_rx_counter_level(hw);
1186 1180
1187 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 1181 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
1188 "[BTCoex], BT TxRx Counters = %d\n", bt_tx_rx_cnt_lvl); 1182 "[BTCoex], BT TxRx Counters = %d\n", bt_tx_rx_cnt_lvl);
1189 1183
1190 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) { 1184 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
1191 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, "HT40\n"); 1185 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, "HT40\n");
1192 bt_rssi_state = rtl8723ae_dm_bt_check_coex_rssi_state(hw, 2, 1186 bt_rssi_state =
1193 37, 0); 1187 rtl8723e_dm_bt_check_coex_rssi_state(hw, 2, 37, 0);
1194 1188
1195 /* coex table */ 1189 /* coex table */
1196 btdm8723.val_0x6c0 = 0x55555555; 1190 btdm8723.val_0x6c0 = 0x55555555;
@@ -1205,12 +1199,12 @@ static void rtl8723ae_dm_bt_2_ant_fta2dp(struct ieee80211_hw *hw)
1205 /* fw mechanism */ 1199 /* fw mechanism */
1206 btdm8723.ps_tdma_on = true; 1200 btdm8723.ps_tdma_on = true;
1207 if ((bt_rssi_state == BT_RSSI_STATE_HIGH) || 1201 if ((bt_rssi_state == BT_RSSI_STATE_HIGH) ||
1208 (bt_rssi_state == BT_RSSI_STATE_STAY_HIGH)) { 1202 (bt_rssi_state == BT_RSSI_STATE_STAY_HIGH)) {
1209 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 1203 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
1210 "Wifi rssi high\n"); 1204 "Wifi rssi high\n");
1211 if (bt_tx_rx_cnt_lvl == BT_TXRX_CNT_LEVEL_2) { 1205 if (bt_tx_rx_cnt_lvl == BT_TXRX_CNT_LEVEL_2) {
1212 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 1206 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
1213 "[BTCoex], BT TxRx Counters >= 1400\n"); 1207 "[BTCoex], BT TxRx Counters >= 1400\n");
1214 btdm8723.ps_tdma_byte[0] = 0xa3; 1208 btdm8723.ps_tdma_byte[0] = 0xa3;
1215 btdm8723.ps_tdma_byte[1] = 0x5; 1209 btdm8723.ps_tdma_byte[1] = 0x5;
1216 btdm8723.ps_tdma_byte[2] = 0x5; 1210 btdm8723.ps_tdma_byte[2] = 0x5;
@@ -1244,7 +1238,8 @@ static void rtl8723ae_dm_bt_2_ant_fta2dp(struct ieee80211_hw *hw)
1244 btdm8723.ps_tdma_byte[2] = 0x5; 1238 btdm8723.ps_tdma_byte[2] = 0x5;
1245 btdm8723.ps_tdma_byte[3] = 0x0; 1239 btdm8723.ps_tdma_byte[3] = 0x0;
1246 btdm8723.ps_tdma_byte[4] = 0x80; 1240 btdm8723.ps_tdma_byte[4] = 0x80;
1247 } else if (bt_tx_rx_cnt_lvl == BT_TXRX_CNT_LEVEL_1) { 1241 } else if (bt_tx_rx_cnt_lvl ==
1242 BT_TXRX_CNT_LEVEL_1) {
1248 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 1243 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
1249 "[BTCoex], BT TxRx Counters >= 1200 && < 1400\n"); 1244 "[BTCoex], BT TxRx Counters >= 1200 && < 1400\n");
1250 btdm8723.ps_tdma_byte[0] = 0xa3; 1245 btdm8723.ps_tdma_byte[0] = 0xa3;
@@ -1265,10 +1260,10 @@ static void rtl8723ae_dm_bt_2_ant_fta2dp(struct ieee80211_hw *hw)
1265 } else { 1260 } else {
1266 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 1261 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
1267 "HT20 or Legacy\n"); 1262 "HT20 or Legacy\n");
1268 bt_rssi_state = rtl8723ae_dm_bt_check_coex_rssi_state(hw, 2, 1263 bt_rssi_state =
1269 47, 0); 1264 rtl8723e_dm_bt_check_coex_rssi_state(hw, 2, 47, 0);
1270 bt_rssi_state1 = rtl8723ae_dm_bt_check_coex_rssi_state1(hw, 2, 1265 bt_rssi_state1 =
1271 27, 0); 1266 rtl8723e_dm_bt_check_coex_rssi_state1(hw, 2, 27, 0);
1272 1267
1273 /* coex table */ 1268 /* coex table */
1274 btdm8723.val_0x6c0 = 0x55555555; 1269 btdm8723.val_0x6c0 = 0x55555555;
@@ -1277,7 +1272,7 @@ static void rtl8723ae_dm_bt_2_ant_fta2dp(struct ieee80211_hw *hw)
1277 1272
1278 /* sw mechanism */ 1273 /* sw mechanism */
1279 if ((bt_rssi_state == BT_RSSI_STATE_HIGH) || 1274 if ((bt_rssi_state == BT_RSSI_STATE_HIGH) ||
1280 (bt_rssi_state == BT_RSSI_STATE_STAY_HIGH)) { 1275 (bt_rssi_state == BT_RSSI_STATE_STAY_HIGH)) {
1281 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 1276 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
1282 "Wifi rssi high\n"); 1277 "Wifi rssi high\n");
1283 btdm8723.agc_table_en = true; 1278 btdm8723.agc_table_en = true;
@@ -1294,12 +1289,11 @@ static void rtl8723ae_dm_bt_2_ant_fta2dp(struct ieee80211_hw *hw)
1294 /* fw mechanism */ 1289 /* fw mechanism */
1295 btdm8723.ps_tdma_on = true; 1290 btdm8723.ps_tdma_on = true;
1296 if ((bt_rssi_state1 == BT_RSSI_STATE_HIGH) || 1291 if ((bt_rssi_state1 == BT_RSSI_STATE_HIGH) ||
1297 (bt_rssi_state1 == BT_RSSI_STATE_STAY_HIGH)) { 1292 (bt_rssi_state1 == BT_RSSI_STATE_STAY_HIGH)) {
1298 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 1293 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
1299 "Wifi rssi-1 high\n"); 1294 "Wifi rssi-1 high\n");
1300 /* only rssi high we need to do this, 1295 /* only rssi high we need to do this, */
1301 * when rssi low, the value will modified by fw 1296 /* when rssi low, the value will modified by fw */
1302 */
1303 rtl_write_byte(rtlpriv, 0x883, 0x40); 1297 rtl_write_byte(rtlpriv, 0x883, 0x40);
1304 if (bt_tx_rx_cnt_lvl == BT_TXRX_CNT_LEVEL_2) { 1298 if (bt_tx_rx_cnt_lvl == BT_TXRX_CNT_LEVEL_2) {
1305 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 1299 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
@@ -1357,15 +1351,14 @@ static void rtl8723ae_dm_bt_2_ant_fta2dp(struct ieee80211_hw *hw)
1357 } 1351 }
1358 } 1352 }
1359 1353
1360 if (rtl8723ae_dm_bt_need_to_dec_bt_pwr(hw)) 1354 if (rtl8723e_dm_bt_need_to_dec_bt_pwr(hw))
1361 btdm8723.dec_bt_pwr = true; 1355 btdm8723.dec_bt_pwr = true;
1362 1356
1363 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 1357 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
1364 "[BTCoex], BT btInqPageStartTime = 0x%x, btTxRxCntLvl = %d\n", 1358 "[BTCoex], BT btInqPageStartTime = 0x%x, btTxRxCntLvl = %d\n",
1365 rtlhal->hal_coex_8723.bt_inq_page_start_time, 1359 hal_coex_8723.bt_inq_page_start_time, bt_tx_rx_cnt_lvl);
1366 bt_tx_rx_cnt_lvl);
1367 1360
1368 if ((rtlhal->hal_coex_8723.bt_inq_page_start_time) || 1361 if ((hal_coex_8723.bt_inq_page_start_time) ||
1369 (BT_TXRX_CNT_LEVEL_3 == bt_tx_rx_cnt_lvl)) { 1362 (BT_TXRX_CNT_LEVEL_3 == bt_tx_rx_cnt_lvl)) {
1370 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 1363 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
1371 "[BTCoex], Set BT inquiry / page scan 0x3a setting\n"); 1364 "[BTCoex], Set BT inquiry / page scan 0x3a setting\n");
@@ -1377,379 +1370,373 @@ static void rtl8723ae_dm_bt_2_ant_fta2dp(struct ieee80211_hw *hw)
1377 btdm8723.ps_tdma_byte[4] = 0x80; 1370 btdm8723.ps_tdma_byte[4] = 0x80;
1378 } 1371 }
1379 1372
1380 if (rtl8723ae_dm_bt_is_coexist_state_changed(hw)) 1373 if (rtl8723e_dm_bt_is_coexist_state_changed(hw))
1381 rtl8723ae_dm_bt_set_bt_dm(hw, &btdm8723); 1374 rtl8723e_dm_bt_set_bt_dm(hw, &btdm8723);
1375
1382} 1376}
1383 1377
1384static void rtl8723ae_dm_bt_inq_page_monitor(struct ieee80211_hw *hw) 1378static void rtl8723e_dm_bt_inq_page_monitor(struct ieee80211_hw *hw)
1385{ 1379{
1386 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1387 struct rtl_priv *rtlpriv = rtl_priv(hw); 1380 struct rtl_priv *rtlpriv = rtl_priv(hw);
1388 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1381 u32 cur_time;
1389 u32 cur_time = jiffies;
1390 1382
1391 if (rtlhal->hal_coex_8723.c2h_bt_inquiry_page) { 1383 cur_time = jiffies;
1384 if (hal_coex_8723.c2h_bt_inquiry_page) {
1392 /* bt inquiry or page is started. */ 1385 /* bt inquiry or page is started. */
1393 if (rtlhal->hal_coex_8723.bt_inq_page_start_time == 0) { 1386 if (hal_coex_8723.bt_inq_page_start_time == 0) {
1394 rtlpcipriv->bt_coexist.cstate |= 1387 rtlpriv->btcoexist.cstate |=
1395 BT_COEX_STATE_BT_INQ_PAGE; 1388 BT_COEX_STATE_BT_INQ_PAGE;
1396 rtlhal->hal_coex_8723.bt_inq_page_start_time = cur_time; 1389 hal_coex_8723.bt_inq_page_start_time = cur_time;
1397 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 1390 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
1398 "[BTCoex], BT Inquiry/page is started at time : 0x%x\n", 1391 "[BTCoex], BT Inquiry/page is started at time : 0x%x\n",
1399 rtlhal->hal_coex_8723.bt_inq_page_start_time); 1392 hal_coex_8723.bt_inq_page_start_time);
1400 } 1393 }
1401 } 1394 }
1402 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 1395 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
1403 "[BTCoex], BT Inquiry/page started time : 0x%x, cur_time : 0x%x\n", 1396 "[BTCoex], BT Inquiry/page started time : 0x%x, cur_time : 0x%x\n",
1404 rtlhal->hal_coex_8723.bt_inq_page_start_time, cur_time); 1397 hal_coex_8723.bt_inq_page_start_time, cur_time);
1405 1398
1406 if (rtlhal->hal_coex_8723.bt_inq_page_start_time) { 1399 if (hal_coex_8723.bt_inq_page_start_time) {
1407 if ((((long)cur_time - 1400 if ((((long)cur_time -
1408 (long)rtlhal->hal_coex_8723.bt_inq_page_start_time) / HZ) >= 1401 (long)hal_coex_8723.bt_inq_page_start_time) / HZ)
1409 10) { 1402 >= 10) {
1410 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 1403 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
1411 "[BTCoex], BT Inquiry/page >= 10sec!!!"); 1404 "[BTCoex], BT Inquiry/page >= 10sec!!!");
1412 rtlhal->hal_coex_8723.bt_inq_page_start_time = 0; 1405 hal_coex_8723.bt_inq_page_start_time = 0;
1413 rtlpcipriv->bt_coexist.cstate &= 1406 rtlpriv->btcoexist.cstate &=
1414 ~BT_COEX_STATE_BT_INQ_PAGE; 1407 ~BT_COEX_STATE_BT_INQ_PAGE;
1415 } 1408 }
1416 } 1409 }
1417} 1410}
1418 1411
1419static void rtl8723ae_dm_bt_reset_action_profile_state(struct ieee80211_hw *hw) 1412static void rtl8723e_dm_bt_reset_action_profile_state(struct ieee80211_hw *hw)
1420{ 1413{
1421 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 1414 struct rtl_priv *rtlpriv = rtl_priv(hw);
1422 1415
1423 rtlpcipriv->bt_coexist.cstate &= 1416 rtlpriv->btcoexist.cstate &= ~
1424 ~(BT_COEX_STATE_PROFILE_HID | BT_COEX_STATE_PROFILE_A2DP | 1417 (BT_COEX_STATE_PROFILE_HID | BT_COEX_STATE_PROFILE_A2DP|
1425 BT_COEX_STATE_PROFILE_PAN | BT_COEX_STATE_PROFILE_SCO); 1418 BT_COEX_STATE_PROFILE_PAN | BT_COEX_STATE_PROFILE_SCO);
1426 1419
1427 rtlpcipriv->bt_coexist.cstate &= 1420 rtlpriv->btcoexist.cstate &= ~
1428 ~(BT_COEX_STATE_BTINFO_COMMON | 1421 (BT_COEX_STATE_BTINFO_COMMON |
1429 BT_COEX_STATE_BTINFO_B_HID_SCOESCO | 1422 BT_COEX_STATE_BTINFO_B_HID_SCOESCO|
1430 BT_COEX_STATE_BTINFO_B_FTP_A2DP); 1423 BT_COEX_STATE_BTINFO_B_FTP_A2DP);
1431} 1424}
1432 1425
1433static void _rtl8723ae_dm_bt_coexist_2_ant(struct ieee80211_hw *hw) 1426static void _rtl8723e_dm_bt_coexist_2_ant(struct ieee80211_hw *hw)
1434{ 1427{
1435 struct rtl_priv *rtlpriv = rtl_priv(hw); 1428 struct rtl_priv *rtlpriv = rtl_priv(hw);
1436 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1429 u8 bt_retry_cnt;
1437 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1438 u8 bt_info_original; 1430 u8 bt_info_original;
1439 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 1431 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
1440 "[BTCoex] Get bt info by fw!!\n"); 1432 "[BTCoex] Get bt info by fw!!\n");
1441 1433
1442 _rtl8723_dm_bt_check_wifi_state(hw); 1434 _rtl8723_dm_bt_check_wifi_state(hw);
1443 1435
1444 if (rtlhal->hal_coex_8723.c2h_bt_info_req_sent) { 1436 if (hal_coex_8723.c2h_bt_info_req_sent) {
1445 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 1437 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
1446 "[BTCoex] c2h for btInfo not rcvd yet!!\n"); 1438 "[BTCoex] c2h for bt_info not rcvd yet!!\n");
1447 } 1439 }
1448 1440
1449 bt_info_original = rtlhal->hal_coex_8723.c2h_bt_info_original; 1441 bt_retry_cnt = hal_coex_8723.bt_retry_cnt;
1442 bt_info_original = hal_coex_8723.c2h_bt_info_original;
1450 1443
1451 /* when bt inquiry or page scan, we have to set h2c 0x25 1444 /* when bt inquiry or page scan, we have to set h2c 0x25 */
1452 * ignore wlanact for continuous 4x2secs 1445 /* ignore wlanact for continuous 4x2secs */
1453 */ 1446 rtl8723e_dm_bt_inq_page_monitor(hw);
1454 rtl8723ae_dm_bt_inq_page_monitor(hw); 1447 rtl8723e_dm_bt_reset_action_profile_state(hw);
1455 rtl8723ae_dm_bt_reset_action_profile_state(hw);
1456
1457 if (rtl8723ae_dm_bt_is_2_ant_common_action(hw)) {
1458 rtlpcipriv->bt_coexist.bt_profile_case = BT_COEX_MECH_COMMON;
1459 rtlpcipriv->bt_coexist.bt_profile_action = BT_COEX_MECH_COMMON;
1460 1448
1449 if (rtl8723e_dm_bt_is_2_ant_common_action(hw)) {
1450 rtlpriv->btcoexist.bt_profile_case = BT_COEX_MECH_COMMON;
1451 rtlpriv->btcoexist.bt_profile_action = BT_COEX_MECH_COMMON;
1461 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 1452 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
1462 "Action 2-Ant common.\n"); 1453 "Action 2-Ant common.\n");
1463 } else { 1454 } else {
1464 if ((bt_info_original & BTINFO_B_HID) || 1455 if ((bt_info_original & BTINFO_B_HID) ||
1465 (bt_info_original & BTINFO_B_SCO_BUSY) || 1456 (bt_info_original & BTINFO_B_SCO_BUSY) ||
1466 (bt_info_original & BTINFO_B_SCO_ESCO)) { 1457 (bt_info_original & BTINFO_B_SCO_ESCO)) {
1467 rtlpcipriv->bt_coexist.cstate |= 1458 rtlpriv->btcoexist.cstate |=
1468 BT_COEX_STATE_BTINFO_B_HID_SCOESCO; 1459 BT_COEX_STATE_BTINFO_B_HID_SCOESCO;
1469 rtlpcipriv->bt_coexist.bt_profile_case = 1460 rtlpriv->btcoexist.bt_profile_case =
1470 BT_COEX_MECH_HID_SCO_ESCO; 1461 BT_COEX_MECH_HID_SCO_ESCO;
1471 rtlpcipriv->bt_coexist.bt_profile_action = 1462 rtlpriv->btcoexist.bt_profile_action =
1472 BT_COEX_MECH_HID_SCO_ESCO; 1463 BT_COEX_MECH_HID_SCO_ESCO;
1473 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 1464 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
1474 "[BTCoex], BTInfo: bHid|bSCOBusy|bSCOeSCO\n"); 1465 "[BTCoex], BTInfo: bHid|bSCOBusy|bSCOeSCO\n");
1475 rtl8723ae_dm_bt_2_ant_hid_sco_esco(hw); 1466 rtl8723e_dm_bt_2_ant_hid_sco_esco(hw);
1476 } else if ((bt_info_original & BTINFO_B_FTP) || 1467 } else if ((bt_info_original & BTINFO_B_FTP) ||
1477 (bt_info_original & BTINFO_B_A2DP)) { 1468 (bt_info_original & BTINFO_B_A2DP)) {
1478 rtlpcipriv->bt_coexist.cstate |= 1469 rtlpriv->btcoexist.cstate |=
1479 BT_COEX_STATE_BTINFO_B_FTP_A2DP; 1470 BT_COEX_STATE_BTINFO_B_FTP_A2DP;
1480 rtlpcipriv->bt_coexist.bt_profile_case = 1471 rtlpriv->btcoexist.bt_profile_case =
1481 BT_COEX_MECH_FTP_A2DP; 1472 BT_COEX_MECH_FTP_A2DP;
1482 rtlpcipriv->bt_coexist.bt_profile_action = 1473 rtlpriv->btcoexist.bt_profile_action =
1483 BT_COEX_MECH_FTP_A2DP; 1474 BT_COEX_MECH_FTP_A2DP;
1484 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 1475 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
1485 "BTInfo: bFTP|bA2DP\n"); 1476 "BTInfo: bFTP|bA2DP\n");
1486 rtl8723ae_dm_bt_2_ant_fta2dp(hw); 1477 rtl8723e_dm_bt_2_ant_ftp_a2dp(hw);
1487 } else { 1478 } else {
1488 rtlpcipriv->bt_coexist.cstate |= 1479 rtlpriv->btcoexist.cstate |=
1489 BT_COEX_STATE_BTINFO_B_HID_SCOESCO; 1480 BT_COEX_STATE_BTINFO_B_HID_SCOESCO;
1490 rtlpcipriv->bt_coexist.bt_profile_case = 1481 rtlpriv->btcoexist.bt_profile_case =
1491 BT_COEX_MECH_NONE; 1482 BT_COEX_MECH_NONE;
1492 rtlpcipriv->bt_coexist.bt_profile_action = 1483 rtlpriv->btcoexist.bt_profile_action =
1493 BT_COEX_MECH_NONE; 1484 BT_COEX_MECH_NONE;
1494 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 1485 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
1495 "[BTCoex], BTInfo: undefined case!!!!\n"); 1486 "[BTCoex], BTInfo: undefined case!!!!\n");
1496 rtl8723ae_dm_bt_2_ant_hid_sco_esco(hw); 1487 rtl8723e_dm_bt_2_ant_hid_sco_esco(hw);
1497 } 1488 }
1498 } 1489 }
1499} 1490}
1500 1491
1501static void _rtl8723ae_dm_bt_coexist_1_ant(struct ieee80211_hw *hw) 1492static void _rtl8723e_dm_bt_coexist_1_ant(struct ieee80211_hw *hw)
1502{ 1493{
1494 return;
1503} 1495}
1504 1496
1505void rtl8723ae_dm_bt_hw_coex_all_off_8723a(struct ieee80211_hw *hw) 1497void rtl8723e_dm_bt_hw_coex_all_off_8723a(struct ieee80211_hw *hw)
1506{ 1498{
1507 rtl8723ae_dm_bt_set_coex_table(hw, 0x5a5aaaaa, 0xcc, 0x3); 1499 rtl8723e_dm_bt_set_coex_table(hw, 0x5a5aaaaa, 0xcc, 0x3);
1508 rtl8723ae_dm_bt_set_hw_pta_mode(hw, true); 1500 rtl8723e_dm_bt_set_hw_pta_mode(hw, true);
1509} 1501}
1510 1502
1511void rtl8723ae_dm_bt_fw_coex_all_off_8723a(struct ieee80211_hw *hw) 1503void rtl8723e_dm_bt_fw_coex_all_off_8723a(struct ieee80211_hw *hw)
1512{ 1504{
1513 rtl8723ae_dm_bt_set_fw_ignore_wlan_act(hw, false); 1505 rtl8723e_dm_bt_set_fw_ignore_wlan_act(hw, false);
1514 rtl8723ae_dm_bt_set_fw_3a(hw, 0x0, 0x0, 0x0, 0x8, 0x0); 1506 rtl8723e_dm_bt_set_fw_3a(hw, 0x0, 0x0, 0x0, 0x8, 0x0);
1515 rtl8723ae_dm_bt_set_fw_2_ant_hid(hw, false, false); 1507 rtl8723e_dm_bt_set_fw_2_ant_hid(hw, false, false);
1516 rtl8723ae_dm_bt_set_fw_tra_tdma_ctrl(hw, false, 1508 rtl8723e_dm_bt_set_fw_tra_tdma_ctrl(hw, false, TDMA_2ANT,
1517 TDMA_2ANT, TDMA_NAV_OFF); 1509 TDMA_NAV_OFF);
1518 rtl8723ae_dm_bt_set_fw_tdma_ctrl(hw, false, TDMA_2ANT, 1510 rtl8723e_dm_bt_set_fw_tdma_ctrl(hw, false, TDMA_2ANT, TDMA_NAV_OFF,
1519 TDMA_NAV_OFF, TDMA_DAC_SWING_OFF); 1511 TDMA_DAC_SWING_OFF);
1520 rtl8723ae_dm_bt_set_fw_dac_swing_level(hw, 0); 1512 rtl8723e_dm_bt_set_fw_dac_swing_level(hw, 0);
1521 rtl8723ae_dm_bt_set_fw_bt_hid_info(hw, false); 1513 rtl8723e_dm_bt_set_fw_bt_hid_info(hw, false);
1522 rtl8723ae_dm_bt_set_fw_bt_retry_index(hw, 2); 1514 rtl8723e_dm_bt_set_fw_bt_retry_index(hw, 2);
1523 rtl8723ae_dm_bt_set_fw_wlan_act(hw, 0x10, 0x10); 1515 rtl8723e_dm_bt_set_fw_wlan_act(hw, 0x10, 0x10);
1524 rtl8723ae_dm_bt_set_fw_dec_bt_pwr(hw, false); 1516 rtl8723e_dm_bt_set_fw_dec_bt_pwr(hw, false);
1525} 1517}
1526 1518
1527void rtl8723ae_dm_bt_sw_coex_all_off_8723a(struct ieee80211_hw *hw) 1519void rtl8723e_dm_bt_sw_coex_all_off_8723a(struct ieee80211_hw *hw)
1528{ 1520{
1529 rtl8723ae_dm_bt_agc_table(hw, BT_AGCTABLE_OFF); 1521 rtl8723e_dm_bt_agc_table(hw, BT_AGCTABLE_OFF);
1530 rtl8723ae_dm_bt_bback_off_level(hw, BT_BB_BACKOFF_OFF); 1522 rtl8723e_dm_bt_bb_back_off_level(hw, BT_BB_BACKOFF_OFF);
1531 rtl8723ae_dm_bt_reject_ap_aggregated_packet(hw, false); 1523 rtl8723e_dm_bt_reject_ap_aggregated_packet(hw, false);
1532 1524
1533 rtl8723ae_bt_set_penalty_tx_rate_adap(hw, BT_TX_RATE_ADAPTIVE_NORMAL); 1525 dm_bt_set_sw_penalty_tx_rate_adapt(hw, BT_TX_RATE_ADAPTIVE_NORMAL);
1534 rtl8723ae_dm_bt_set_sw_rf_rx_lpf_corner(hw, BT_RF_RX_LPF_CORNER_RESUME); 1526 rtl8723e_dm_bt_set_sw_rf_rx_lpf_corner(hw, BT_RF_RX_LPF_CORNER_RESUME);
1535 rtl8723ae_dm_bt_set_sw_full_time_dac_swing(hw, false, 0xc0); 1527 rtl8723e_dm_bt_set_sw_full_time_dac_swing(hw, false, 0xc0);
1536} 1528}
1537 1529
1538static void rtl8723ae_dm_bt_query_bt_information(struct ieee80211_hw *hw) 1530static void rtl8723e_dm_bt_query_bt_information(struct ieee80211_hw *hw)
1539{ 1531{
1540 struct rtl_priv *rtlpriv = rtl_priv(hw); 1532 struct rtl_priv *rtlpriv = rtl_priv(hw);
1541 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1542 u8 h2c_parameter[1] = {0}; 1533 u8 h2c_parameter[1] = {0};
1543 1534
1544 rtlhal->hal_coex_8723.c2h_bt_info_req_sent = true; 1535 hal_coex_8723.c2h_bt_info_req_sent = true;
1545 1536
1546 h2c_parameter[0] |= BIT(0); 1537 h2c_parameter[0] |= BIT(0);
1547 1538
1548 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 1539 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
1549 "Query Bt information, write 0x38 = 0x%x\n", 1540 "Query Bt information, write 0x38=0x%x\n", h2c_parameter[0]);
1550 h2c_parameter[0]);
1551 1541
1552 rtl8723ae_fill_h2c_cmd(hw, 0x38, 1, h2c_parameter); 1542 rtl8723e_fill_h2c_cmd(hw, 0x38, 1, h2c_parameter);
1553} 1543}
1554 1544
1555static void rtl8723ae_dm_bt_bt_hw_counters_monitor(struct ieee80211_hw *hw) 1545static void rtl8723e_dm_bt_bt_hw_counters_monitor(struct ieee80211_hw *hw)
1556{ 1546{
1557 struct rtl_priv *rtlpriv = rtl_priv(hw); 1547 struct rtl_priv *rtlpriv = rtl_priv(hw);
1558 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1548 u32 reg_hp_tx_rx, reg_lp_tx_rx, u32_tmp;
1559 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 1549 u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
1560 u32 reg_htx_rx, reg_ltx_rx, u32_tmp; 1550
1561 u32 reg_htx, reg_hrx, reg_ltx, reg_lrx; 1551 reg_hp_tx_rx = REG_HIGH_PRIORITY_TXRX;
1562 1552 reg_lp_tx_rx = REG_LOW_PRIORITY_TXRX;
1563 reg_htx_rx = REG_HIGH_PRIORITY_TXRX; 1553
1564 reg_ltx_rx = REG_LOW_PRIORITY_TXRX; 1554 u32_tmp = rtl_read_dword(rtlpriv, reg_hp_tx_rx);
1565 1555 reg_hp_tx = u32_tmp & MASKLWORD;
1566 u32_tmp = rtl_read_dword(rtlpriv, reg_htx_rx); 1556 reg_hp_rx = (u32_tmp & MASKHWORD)>>16;
1567 reg_htx = u32_tmp & MASKLWORD; 1557
1568 reg_hrx = (u32_tmp & MASKHWORD)>>16; 1558 u32_tmp = rtl_read_dword(rtlpriv, reg_lp_tx_rx);
1569 1559 reg_lp_tx = u32_tmp & MASKLWORD;
1570 u32_tmp = rtl_read_dword(rtlpriv, reg_ltx_rx); 1560 reg_lp_rx = (u32_tmp & MASKHWORD)>>16;
1571 reg_ltx = u32_tmp & MASKLWORD; 1561
1572 reg_lrx = (u32_tmp & MASKHWORD)>>16; 1562 if (rtlpriv->btcoexist.lps_counter > 1) {
1573 1563 reg_hp_tx %= rtlpriv->btcoexist.lps_counter;
1574 if (rtlpcipriv->bt_coexist.lps_counter > 1) { 1564 reg_hp_rx %= rtlpriv->btcoexist.lps_counter;
1575 reg_htx %= rtlpcipriv->bt_coexist.lps_counter; 1565 reg_lp_tx %= rtlpriv->btcoexist.lps_counter;
1576 reg_hrx %= rtlpcipriv->bt_coexist.lps_counter; 1566 reg_lp_rx %= rtlpriv->btcoexist.lps_counter;
1577 reg_ltx %= rtlpcipriv->bt_coexist.lps_counter;
1578 reg_lrx %= rtlpcipriv->bt_coexist.lps_counter;
1579 } 1567 }
1580 1568
1581 rtlhal->hal_coex_8723.high_priority_tx = reg_htx; 1569 hal_coex_8723.high_priority_tx = reg_hp_tx;
1582 rtlhal->hal_coex_8723.high_priority_rx = reg_hrx; 1570 hal_coex_8723.high_priority_rx = reg_hp_rx;
1583 rtlhal->hal_coex_8723.low_priority_tx = reg_ltx; 1571 hal_coex_8723.low_priority_tx = reg_lp_tx;
1584 rtlhal->hal_coex_8723.low_priority_rx = reg_lrx; 1572 hal_coex_8723.low_priority_rx = reg_lp_rx;
1585 1573
1586 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 1574 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
1587 "High Priority Tx/Rx (reg 0x%x)=%x(%d)/%x(%d)\n", 1575 "High Priority Tx/Rx (reg 0x%x)=%x(%d)/%x(%d)\n",
1588 reg_htx_rx, reg_htx, reg_htx, reg_hrx, reg_hrx); 1576 reg_hp_tx_rx, reg_hp_tx, reg_hp_tx, reg_hp_rx, reg_hp_rx);
1589 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 1577 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
1590 "Low Priority Tx/Rx (reg 0x%x)=%x(%d)/%x(%d)\n", 1578 "Low Priority Tx/Rx (reg 0x%x)=%x(%d)/%x(%d)\n",
1591 reg_ltx_rx, reg_ltx, reg_ltx, reg_lrx, reg_lrx); 1579 reg_lp_tx_rx, reg_lp_tx, reg_lp_tx, reg_lp_rx, reg_lp_rx);
1592 rtlpcipriv->bt_coexist.lps_counter = 0; 1580 rtlpriv->btcoexist.lps_counter = 0;
1581 /* rtl_write_byte(rtlpriv, 0x76e, 0xc); */
1593} 1582}
1594 1583
1595static void rtl8723ae_dm_bt_bt_enable_disable_check(struct ieee80211_hw *hw) 1584static void rtl8723e_dm_bt_bt_enable_disable_check(struct ieee80211_hw *hw)
1596{ 1585{
1597 struct rtl_priv *rtlpriv = rtl_priv(hw); 1586 struct rtl_priv *rtlpriv = rtl_priv(hw);
1598 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1599 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1600 bool bt_alife = true; 1587 bool bt_alife = true;
1601 1588
1602 if (rtlhal->hal_coex_8723.high_priority_tx == 0 && 1589 if (hal_coex_8723.high_priority_tx == 0 &&
1603 rtlhal->hal_coex_8723.high_priority_rx == 0 && 1590 hal_coex_8723.high_priority_rx == 0 &&
1604 rtlhal->hal_coex_8723.low_priority_tx == 0 && 1591 hal_coex_8723.low_priority_tx == 0 &&
1605 rtlhal->hal_coex_8723.low_priority_rx == 0) 1592 hal_coex_8723.low_priority_rx == 0) {
1606 bt_alife = false; 1593 bt_alife = false;
1607 if (rtlhal->hal_coex_8723.high_priority_tx == 0xeaea && 1594 }
1608 rtlhal->hal_coex_8723.high_priority_rx == 0xeaea && 1595 if (hal_coex_8723.high_priority_tx == 0xeaea &&
1609 rtlhal->hal_coex_8723.low_priority_tx == 0xeaea && 1596 hal_coex_8723.high_priority_rx == 0xeaea &&
1610 rtlhal->hal_coex_8723.low_priority_rx == 0xeaea) 1597 hal_coex_8723.low_priority_tx == 0xeaea &&
1598 hal_coex_8723.low_priority_rx == 0xeaea) {
1611 bt_alife = false; 1599 bt_alife = false;
1612 if (rtlhal->hal_coex_8723.high_priority_tx == 0xffff && 1600 }
1613 rtlhal->hal_coex_8723.high_priority_rx == 0xffff && 1601 if (hal_coex_8723.high_priority_tx == 0xffff &&
1614 rtlhal->hal_coex_8723.low_priority_tx == 0xffff && 1602 hal_coex_8723.high_priority_rx == 0xffff &&
1615 rtlhal->hal_coex_8723.low_priority_rx == 0xffff) 1603 hal_coex_8723.low_priority_tx == 0xffff &&
1604 hal_coex_8723.low_priority_rx == 0xffff) {
1616 bt_alife = false; 1605 bt_alife = false;
1606 }
1617 if (bt_alife) { 1607 if (bt_alife) {
1618 rtlpcipriv->bt_coexist.bt_active_zero_cnt = 0; 1608 rtlpriv->btcoexist.bt_active_zero_cnt = 0;
1619 rtlpcipriv->bt_coexist.cur_bt_disabled = false; 1609 rtlpriv->btcoexist.cur_bt_disabled = false;
1620 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 1610 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
1621 "8723A BT is enabled !!\n"); 1611 "8723A BT is enabled !!\n");
1622 } else { 1612 } else {
1623 rtlpcipriv->bt_coexist.bt_active_zero_cnt++; 1613 rtlpriv->btcoexist.bt_active_zero_cnt++;
1624 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 1614 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
1625 "8723A bt all counters = 0, %d times!!\n", 1615 "8723A bt all counters=0, %d times!!\n",
1626 rtlpcipriv->bt_coexist.bt_active_zero_cnt); 1616 rtlpriv->btcoexist.bt_active_zero_cnt);
1627 if (rtlpcipriv->bt_coexist.bt_active_zero_cnt >= 2) { 1617 if (rtlpriv->btcoexist.bt_active_zero_cnt >= 2) {
1628 rtlpcipriv->bt_coexist.cur_bt_disabled = true; 1618 rtlpriv->btcoexist.cur_bt_disabled = true;
1629 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 1619 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
1630 "8723A BT is disabled !!\n"); 1620 "8723A BT is disabled !!\n");
1631 } 1621 }
1632 } 1622 }
1633 if (rtlpcipriv->bt_coexist.pre_bt_disabled != 1623 if (rtlpriv->btcoexist.pre_bt_disabled !=
1634 rtlpcipriv->bt_coexist.cur_bt_disabled) { 1624 rtlpriv->btcoexist.cur_bt_disabled) {
1635 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 1625 RT_TRACE(rtlpriv, COMP_BT_COEXIST,
1636 "8723A BT is from %s to %s!!\n", 1626 DBG_TRACE, "8723A BT is from %s to %s!!\n",
1637 (rtlpcipriv->bt_coexist.pre_bt_disabled ? 1627 (rtlpriv->btcoexist.pre_bt_disabled ?
1638 "disabled" : "enabled"), 1628 "disabled" : "enabled"),
1639 (rtlpcipriv->bt_coexist.cur_bt_disabled ? 1629 (rtlpriv->btcoexist.cur_bt_disabled ?
1640 "disabled" : "enabled")); 1630 "disabled" : "enabled"));
1641 rtlpcipriv->bt_coexist.pre_bt_disabled 1631 rtlpriv->btcoexist.pre_bt_disabled
1642 = rtlpcipriv->bt_coexist.cur_bt_disabled; 1632 = rtlpriv->btcoexist.cur_bt_disabled;
1643 } 1633 }
1644} 1634}
1645 1635
1646 1636
1647void rtl8723ae_dm_bt_coexist_8723(struct ieee80211_hw *hw) 1637void rtl8723e_dm_bt_coexist_8723(struct ieee80211_hw *hw)
1648{ 1638{
1649 struct rtl_priv *rtlpriv = rtl_priv(hw); 1639 struct rtl_priv *rtlpriv = rtl_priv(hw);
1650 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1651 1640
1652 rtl8723ae_dm_bt_query_bt_information(hw); 1641 rtl8723e_dm_bt_query_bt_information(hw);
1653 rtl8723ae_dm_bt_bt_hw_counters_monitor(hw); 1642 rtl8723e_dm_bt_bt_hw_counters_monitor(hw);
1654 rtl8723ae_dm_bt_bt_enable_disable_check(hw); 1643 rtl8723e_dm_bt_bt_enable_disable_check(hw);
1655 1644
1656 if (rtlpcipriv->bt_coexist.bt_ant_num == ANT_X2) { 1645 if (rtlpriv->btcoexist.bt_ant_num == ANT_X2) {
1657 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 1646 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
1658 "[BTCoex], 2 Ant mechanism\n"); 1647 "[BTCoex], 2 Ant mechanism\n");
1659 _rtl8723ae_dm_bt_coexist_2_ant(hw); 1648 _rtl8723e_dm_bt_coexist_2_ant(hw);
1660 } else { 1649 } else {
1661 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 1650 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
1662 "[BTCoex], 1 Ant mechanism\n"); 1651 "[BTCoex], 1 Ant mechanism\n");
1663 _rtl8723ae_dm_bt_coexist_1_ant(hw); 1652 _rtl8723e_dm_bt_coexist_1_ant(hw);
1664 } 1653 }
1665 1654
1666 if (!rtl8723ae_dm_bt_is_same_coexist_state(hw)) { 1655 if (!rtl8723e_dm_bt_is_same_coexist_state(hw)) {
1667 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 1656 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
1668 "[BTCoex], Coexist State[bitMap] change from 0x%x%8x to 0x%x%8x\n", 1657 "[BTCoex], Coexist State[bitMap] change from 0x%x%8x to 0x%x%8x\n",
1669 rtlpcipriv->bt_coexist.previous_state_h, 1658 rtlpriv->btcoexist.previous_state_h,
1670 rtlpcipriv->bt_coexist.previous_state, 1659 rtlpriv->btcoexist.previous_state,
1671 rtlpcipriv->bt_coexist.cstate_h, 1660 rtlpriv->btcoexist.cstate_h,
1672 rtlpcipriv->bt_coexist.cstate); 1661 rtlpriv->btcoexist.cstate);
1673 rtlpcipriv->bt_coexist.previous_state 1662 rtlpriv->btcoexist.previous_state
1674 = rtlpcipriv->bt_coexist.cstate; 1663 = rtlpriv->btcoexist.cstate;
1675 rtlpcipriv->bt_coexist.previous_state_h 1664 rtlpriv->btcoexist.previous_state_h
1676 = rtlpcipriv->bt_coexist.cstate_h; 1665 = rtlpriv->btcoexist.cstate_h;
1677 } 1666 }
1678} 1667}
1679 1668
1680static void rtl8723ae_dm_bt_parse_bt_info(struct ieee80211_hw *hw, 1669static void rtl8723e_dm_bt_parse_bt_info(struct ieee80211_hw *hw,
1681 u8 *tmbuf, u8 len) 1670 u8 *tmp_buf, u8 len)
1682{ 1671{
1683 struct rtl_priv *rtlpriv = rtl_priv(hw); 1672 struct rtl_priv *rtlpriv = rtl_priv(hw);
1684 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1685 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1686 u8 bt_info; 1673 u8 bt_info;
1687 u8 i; 1674 u8 i;
1688 1675
1689 rtlhal->hal_coex_8723.c2h_bt_info_req_sent = false; 1676 hal_coex_8723.c2h_bt_info_req_sent = false;
1690 rtlhal->hal_coex_8723.bt_retry_cnt = 0; 1677 hal_coex_8723.bt_retry_cnt = 0;
1691 for (i = 0; i < len; i++) { 1678 for (i = 0; i < len; i++) {
1692 if (i == 0) 1679 if (i == 0)
1693 rtlhal->hal_coex_8723.c2h_bt_info_original = tmbuf[i]; 1680 hal_coex_8723.c2h_bt_info_original = tmp_buf[i];
1694 else if (i == 1) 1681 else if (i == 1)
1695 rtlhal->hal_coex_8723.bt_retry_cnt = tmbuf[i]; 1682 hal_coex_8723.bt_retry_cnt = tmp_buf[i];
1696 if (i == len-1) { 1683 if (i == len-1)
1697 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 1684 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
1698 "0x%2x]", tmbuf[i]); 1685 "0x%2x]", tmp_buf[i]);
1699 } else { 1686 else
1700 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 1687 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
1701 "0x%2x, ", tmbuf[i]); 1688 "0x%2x, ", tmp_buf[i]);
1702 } 1689
1703 } 1690 }
1704 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 1691 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
1705 "BT info bt_info (Data)= 0x%x\n", 1692 "BT info bt_info (Data)= 0x%x\n",
1706 rtlhal->hal_coex_8723.c2h_bt_info_original); 1693 hal_coex_8723.c2h_bt_info_original);
1707 bt_info = rtlhal->hal_coex_8723.c2h_bt_info_original; 1694 bt_info = hal_coex_8723.c2h_bt_info_original;
1708 1695
1709 if (bt_info & BIT(2)) 1696 if (bt_info & BIT(2))
1710 rtlhal->hal_coex_8723.c2h_bt_inquiry_page = true; 1697 hal_coex_8723.c2h_bt_inquiry_page = true;
1711 else 1698 else
1712 rtlhal->hal_coex_8723.c2h_bt_inquiry_page = false; 1699 hal_coex_8723.c2h_bt_inquiry_page = false;
1700
1713 1701
1714 if (bt_info & BTINFO_B_CONNECTION) { 1702 if (bt_info & BTINFO_B_CONNECTION) {
1715 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 1703 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
1716 "[BTC2H], BTInfo: bConnect=true\n"); 1704 "[BTC2H], BTInfo: bConnect=true\n");
1717 rtlpcipriv->bt_coexist.bt_busy = true; 1705 rtlpriv->btcoexist.bt_busy = true;
1718 rtlpcipriv->bt_coexist.cstate &= ~BT_COEX_STATE_BT_IDLE; 1706 rtlpriv->btcoexist.cstate &= ~BT_COEX_STATE_BT_IDLE;
1719 } else { 1707 } else {
1720 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 1708 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
1721 "[BTC2H], BTInfo: bConnect=false\n"); 1709 "[BTC2H], BTInfo: bConnect=false\n");
1722 rtlpcipriv->bt_coexist.bt_busy = false; 1710 rtlpriv->btcoexist.bt_busy = false;
1723 rtlpcipriv->bt_coexist.cstate |= BT_COEX_STATE_BT_IDLE; 1711 rtlpriv->btcoexist.cstate |= BT_COEX_STATE_BT_IDLE;
1724 } 1712 }
1725} 1713}
1726void rtl_8723e_c2h_command_handle(struct ieee80211_hw *hw) 1714void rtl_8723e_c2h_command_handle(struct ieee80211_hw *hw)
1727{ 1715{
1728 struct rtl_priv *rtlpriv = rtl_priv(hw); 1716 struct rtl_priv *rtlpriv = rtl_priv(hw);
1729 struct c2h_evt_hdr c2h_event; 1717 struct c2h_evt_hdr c2h_event;
1730 u8 *ptmbuf; 1718 u8 *ptmp_buf = NULL;
1731 u8 index; 1719 u8 index = 0;
1732 u8 u1tmp; 1720 u8 u1b_tmp = 0;
1733
1734 memset(&c2h_event, 0, sizeof(c2h_event)); 1721 memset(&c2h_event, 0, sizeof(c2h_event));
1735 u1tmp = rtl_read_byte(rtlpriv, REG_C2HEVT_MSG_NORMAL); 1722 u1b_tmp = rtl_read_byte(rtlpriv, REG_C2HEVT_MSG_NORMAL);
1736 RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG, 1723 RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
1737 "&&&&&&: REG_C2HEVT_MSG_NORMAL is 0x%x\n", u1tmp); 1724 "&&&&&&: REG_C2HEVT_MSG_NORMAL is 0x%x\n", u1b_tmp);
1738 c2h_event.cmd_id = u1tmp & 0xF; 1725 c2h_event.cmd_id = u1b_tmp & 0xF;
1739 c2h_event.cmd_len = (u1tmp & 0xF0) >> 4; 1726 c2h_event.cmd_len = (u1b_tmp & 0xF0) >> 4;
1740 c2h_event.cmd_seq = rtl_read_byte(rtlpriv, REG_C2HEVT_MSG_NORMAL + 1); 1727 c2h_event.cmd_seq = rtl_read_byte(rtlpriv, REG_C2HEVT_MSG_NORMAL + 1);
1741 RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG, 1728 RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
1742 "cmd_id: %d, cmd_len: %d, cmd_seq: %d\n", 1729 "cmd_id: %d, cmd_len: %d, cmd_seq: %d\n",
1743 c2h_event.cmd_id , c2h_event.cmd_len, c2h_event.cmd_seq); 1730 c2h_event.cmd_id , c2h_event.cmd_len, c2h_event.cmd_seq);
1744 u1tmp = rtl_read_byte(rtlpriv, 0x01AF); 1731 u1b_tmp = rtl_read_byte(rtlpriv, 0x01AF);
1745 if (u1tmp == C2H_EVT_HOST_CLOSE) { 1732 if (u1b_tmp == C2H_EVT_HOST_CLOSE) {
1746 return; 1733 return;
1747 } else if (u1tmp != C2H_EVT_FW_CLOSE) { 1734 } else if (u1b_tmp != C2H_EVT_FW_CLOSE) {
1748 rtl_write_byte(rtlpriv, 0x1AF, 0x00); 1735 rtl_write_byte(rtlpriv, 0x1AF, 0x00);
1749 return; 1736 return;
1750 } 1737 }
1751 ptmbuf = kmalloc(c2h_event.cmd_len, GFP_KERNEL); 1738 ptmp_buf = kmalloc(c2h_event.cmd_len, GFP_KERNEL);
1752 if (ptmbuf == NULL) { 1739 if (ptmp_buf == NULL) {
1753 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE, 1740 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
1754 "malloc cmd buf failed\n"); 1741 "malloc cmd buf failed\n");
1755 return; 1742 return;
@@ -1757,30 +1744,37 @@ void rtl_8723e_c2h_command_handle(struct ieee80211_hw *hw)
1757 1744
1758 /* Read the content */ 1745 /* Read the content */
1759 for (index = 0; index < c2h_event.cmd_len; index++) 1746 for (index = 0; index < c2h_event.cmd_len; index++)
1760 ptmbuf[index] = rtl_read_byte(rtlpriv, REG_C2HEVT_MSG_NORMAL + 1747 ptmp_buf[index] = rtl_read_byte(rtlpriv,
1761 2 + index); 1748 REG_C2HEVT_MSG_NORMAL + 2 + index);
1749
1762 1750
1763 switch (c2h_event.cmd_id) { 1751 switch (c2h_event.cmd_id) {
1764 case C2H_BT_RSSI: 1752 case C2H_BT_RSSI:
1765 break; 1753 break;
1766 1754
1767 case C2H_BT_OP_MODE: 1755 case C2H_BT_OP_MODE:
1768 break; 1756 break;
1769 1757
1770 case BT_INFO: 1758 case BT_INFO:
1771 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE, 1759 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
1772 "BT info Byte[0] (ID) is 0x%x\n", c2h_event.cmd_id); 1760 "BT info Byte[0] (ID) is 0x%x\n",
1761 c2h_event.cmd_id);
1773 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE, 1762 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
1774 "BT info Byte[1] (Seq) is 0x%x\n", c2h_event.cmd_seq); 1763 "BT info Byte[1] (Seq) is 0x%x\n",
1764 c2h_event.cmd_seq);
1775 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE, 1765 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
1776 "BT info Byte[2] (Data)= 0x%x\n", ptmbuf[0]); 1766 "BT info Byte[2] (Data)= 0x%x\n", ptmp_buf[0]);
1767
1768 rtl8723e_dm_bt_parse_bt_info(hw, ptmp_buf, c2h_event.cmd_len);
1769
1770 if (rtlpriv->cfg->ops->get_btc_status())
1771 rtlpriv->btcoexist.btc_ops->btc_periodical(rtlpriv);
1777 1772
1778 rtl8723ae_dm_bt_parse_bt_info(hw, ptmbuf, c2h_event.cmd_len);
1779 break; 1773 break;
1780 default: 1774 default:
1781 break; 1775 break;
1782 } 1776 }
1783 kfree(ptmbuf); 1777 kfree(ptmp_buf);
1784 1778
1785 rtl_write_byte(rtlpriv, 0x01AF, C2H_EVT_HOST_CLOSE); 1779 rtl_write_byte(rtlpriv, 0x01AF, C2H_EVT_HOST_CLOSE);
1786} 1780}
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/hal_btc.h b/drivers/net/wireless/rtlwifi/rtl8723ae/hal_btc.h
index 4325ecd58f0c..3723d7476717 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/hal_btc.h
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/hal_btc.h
@@ -11,10 +11,6 @@
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details. 12 * more details.
13 * 13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the 14 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE. 15 * file called LICENSE.
20 * 16 *
@@ -24,8 +20,7 @@
24 * Hsinchu 300, Taiwan. 20 * Hsinchu 300, Taiwan.
25 * Larry Finger <Larry.Finger@lwfinger.net> 21 * Larry Finger <Larry.Finger@lwfinger.net>
26 * 22 *
27 **************************************************************************** 23 *****************************************************************************/
28 */
29 24
30#ifndef __RTL8723E_HAL_BTC_H__ 25#ifndef __RTL8723E_HAL_BTC_H__
31#define __RTL8723E_HAL_BTC_H__ 26#define __RTL8723E_HAL_BTC_H__
@@ -34,21 +29,31 @@
34#include "btc.h" 29#include "btc.h"
35#include "hal_bt_coexist.h" 30#include "hal_bt_coexist.h"
36 31
37#define BT_TXRX_CNT_THRES_1 1200 32#define BT_TXRX_CNT_THRES_1 1200
38#define BT_TXRX_CNT_THRES_2 1400 33#define BT_TXRX_CNT_THRES_2 1400
39#define BT_TXRX_CNT_THRES_3 3000 34#define BT_TXRX_CNT_THRES_3 3000
40#define BT_TXRX_CNT_LEVEL_0 0 /* < 1200 */ 35/* < 1200 */
41#define BT_TXRX_CNT_LEVEL_1 1 /* >= 1200 && < 1400 */ 36#define BT_TXRX_CNT_LEVEL_0 0
42#define BT_TXRX_CNT_LEVEL_2 2 /* >= 1400 */ 37/* >= 1200 && < 1400 */
43#define BT_TXRX_CNT_LEVEL_3 3 38#define BT_TXRX_CNT_LEVEL_1 1
39/* >= 1400 */
40#define BT_TXRX_CNT_LEVEL_2 2
41#define BT_TXRX_CNT_LEVEL_3 3
42
43#define BT_COEX_DISABLE 0
44#define BT_Q_PKT_OFF 0
45#define BT_Q_PKT_ON 1
46
47#define BT_TX_PWR_OFF 0
48#define BT_TX_PWR_ON 1
44 49
45/* TDMA mode definition */ 50/* TDMA mode definition */
46#define TDMA_2ANT 0 51#define TDMA_2ANT 0
47#define TDMA_1ANT 1 52#define TDMA_1ANT 1
48#define TDMA_NAV_OFF 0 53#define TDMA_NAV_OFF 0
49#define TDMA_NAV_ON 1 54#define TDMA_NAV_ON 1
50#define TDMA_DAC_SWING_OFF 0 55#define TDMA_DAC_SWING_OFF 0
51#define TDMA_DAC_SWING_ON 1 56#define TDMA_DAC_SWING_ON 1
52 57
53/* PTA mode related definition */ 58/* PTA mode related definition */
54#define BT_PTA_MODE_OFF 0 59#define BT_PTA_MODE_OFF 0
@@ -80,6 +85,7 @@ enum bt_traffic_mode_profile {
80 BT_PROFILE_SCO 85 BT_PROFILE_SCO
81}; 86};
82 87
88/*
83enum hci_ext_bt_operation { 89enum hci_ext_bt_operation {
84 HCI_BT_OP_NONE = 0x0, 90 HCI_BT_OP_NONE = 0x0,
85 HCI_BT_OP_INQUIRE_START = 0x1, 91 HCI_BT_OP_INQUIRE_START = 0x1,
@@ -93,6 +99,7 @@ enum hci_ext_bt_operation {
93 HCI_BT_OP_BT_DEV_DISABLE = 0x9, 99 HCI_BT_OP_BT_DEV_DISABLE = 0x9,
94 HCI_BT_OP_MAX, 100 HCI_BT_OP_MAX,
95}; 101};
102*/
96 103
97enum bt_spec { 104enum bt_spec {
98 BT_SPEC_1_0_b = 0x00, 105 BT_SPEC_1_0_b = 0x00,
@@ -123,12 +130,12 @@ enum bt_state {
123 BT_INFO_STATE_MAX = 7 130 BT_INFO_STATE_MAX = 7
124}; 131};
125 132
126enum rtl8723ae_c2h_evt { 133enum rtl8723e_c2h_evt {
127 C2H_DBG = 0, 134 C2H_DBG = 0,
128 C2H_TSF = 1, 135 C2H_TSF = 1,
129 C2H_AP_RPT_RSP = 2, 136 C2H_AP_RPT_RSP = 2,
130 C2H_CCX_TX_RPT = 3, /* The FW notify the report of the specific */ 137 /* The FW notify the report of the specific tx packet. */
131 /* tx packet. */ 138 C2H_CCX_TX_RPT = 3,
132 C2H_BT_RSSI = 4, 139 C2H_BT_RSSI = 4,
133 C2H_BT_OP_MODE = 5, 140 C2H_BT_OP_MODE = 5,
134 C2H_HW_INFO_EXCH = 10, 141 C2H_HW_INFO_EXCH = 10,
@@ -137,15 +144,16 @@ enum rtl8723ae_c2h_evt {
137 MAX_C2HEVENT 144 MAX_C2HEVENT
138}; 145};
139 146
140void rtl8723ae_dm_bt_fw_coex_all_off_8723a(struct ieee80211_hw *hw); 147void rtl8723e_dm_bt_fw_coex_all_off_8723a(struct ieee80211_hw *hw);
141void rtl8723ae_dm_bt_sw_coex_all_off_8723a(struct ieee80211_hw *hw); 148void rtl8723e_dm_bt_sw_coex_all_off_8723a(struct ieee80211_hw *hw);
142void rtl8723ae_dm_bt_hw_coex_all_off_8723a(struct ieee80211_hw *hw); 149void rtl8723e_dm_bt_hw_coex_all_off_8723a(struct ieee80211_hw *hw);
143void rtl8723ae_dm_bt_coexist_8723(struct ieee80211_hw *hw); 150void rtl8723e_dm_bt_coexist_8723(struct ieee80211_hw *hw);
144void rtl8723ae_dm_bt_set_bt_dm(struct ieee80211_hw *hw, 151void rtl8723e_dm_bt_set_bt_dm(struct ieee80211_hw *hw,
145 struct btdm_8723 *p_btdm); 152 struct btdm_8723 *p_btdm);
146void rtl_8723e_c2h_command_handle(struct ieee80211_hw *hw); 153void rtl_8723e_c2h_command_handle(struct ieee80211_hw *hw);
147void rtl_8723e_bt_wifi_media_status_notify(struct ieee80211_hw *hw, 154void rtl_8723e_bt_wifi_media_status_notify(struct ieee80211_hw *hw,
148 bool mstatus); 155 bool mstatus);
149void rtl8723ae_bt_coex_off_before_lps(struct ieee80211_hw *hw); 156void rtl8723e_dm_bt_turn_off_bt_coexist_before_enter_lps(
157 struct ieee80211_hw *hw);
150 158
151#endif 159#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/hw.c b/drivers/net/wireless/rtlwifi/rtl8723ae/hw.c
index 3338206af947..9e1671c7962f 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/hw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/hw.c
@@ -11,10 +11,6 @@
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details. 12 * more details.
13 * 13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the 14 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE. 15 * file called LICENSE.
20 * 16 *
@@ -37,6 +33,7 @@
37#include "reg.h" 33#include "reg.h"
38#include "def.h" 34#include "def.h"
39#include "phy.h" 35#include "phy.h"
36#include "../rtl8723com/phy_common.h"
40#include "dm.h" 37#include "dm.h"
41#include "../rtl8723com/dm_common.h" 38#include "../rtl8723com/dm_common.h"
42#include "fw.h" 39#include "fw.h"
@@ -47,8 +44,10 @@
47#include "pwrseq.h" 44#include "pwrseq.h"
48#include "btc.h" 45#include "btc.h"
49 46
50static void _rtl8723ae_set_bcn_ctrl_reg(struct ieee80211_hw *hw, 47#define LLT_CONFIG 5
51 u8 set_bits, u8 clear_bits) 48
49static void _rtl8723e_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
50 u8 set_bits, u8 clear_bits)
52{ 51{
53 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 52 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
54 struct rtl_priv *rtlpriv = rtl_priv(hw); 53 struct rtl_priv *rtlpriv = rtl_priv(hw);
@@ -59,7 +58,7 @@ static void _rtl8723ae_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
59 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val); 58 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
60} 59}
61 60
62static void _rtl8723ae_stop_tx_beacon(struct ieee80211_hw *hw) 61static void _rtl8723e_stop_tx_beacon(struct ieee80211_hw *hw)
63{ 62{
64 struct rtl_priv *rtlpriv = rtl_priv(hw); 63 struct rtl_priv *rtlpriv = rtl_priv(hw);
65 u8 tmp1byte; 64 u8 tmp1byte;
@@ -72,7 +71,7 @@ static void _rtl8723ae_stop_tx_beacon(struct ieee80211_hw *hw)
72 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 71 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
73} 72}
74 73
75static void _rtl8723ae_resume_tx_beacon(struct ieee80211_hw *hw) 74static void _rtl8723e_resume_tx_beacon(struct ieee80211_hw *hw)
76{ 75{
77 struct rtl_priv *rtlpriv = rtl_priv(hw); 76 struct rtl_priv *rtlpriv = rtl_priv(hw);
78 u8 tmp1byte; 77 u8 tmp1byte;
@@ -85,17 +84,17 @@ static void _rtl8723ae_resume_tx_beacon(struct ieee80211_hw *hw)
85 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 84 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
86} 85}
87 86
88static void _rtl8723ae_enable_bcn_sufunc(struct ieee80211_hw *hw) 87static void _rtl8723e_enable_bcn_sub_func(struct ieee80211_hw *hw)
89{ 88{
90 _rtl8723ae_set_bcn_ctrl_reg(hw, 0, BIT(1)); 89 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(1));
91} 90}
92 91
93static void _rtl8723ae_disable_bcn_sufunc(struct ieee80211_hw *hw) 92static void _rtl8723e_disable_bcn_sub_func(struct ieee80211_hw *hw)
94{ 93{
95 _rtl8723ae_set_bcn_ctrl_reg(hw, BIT(1), 0); 94 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(1), 0);
96} 95}
97 96
98void rtl8723ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 97void rtl8723e_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
99{ 98{
100 struct rtl_priv *rtlpriv = rtl_priv(hw); 99 struct rtl_priv *rtlpriv = rtl_priv(hw);
101 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 100 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
@@ -103,54 +102,55 @@ void rtl8723ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
103 102
104 switch (variable) { 103 switch (variable) {
105 case HW_VAR_RCR: 104 case HW_VAR_RCR:
106 *((u32 *) (val)) = rtlpci->receive_config; 105 *((u32 *)(val)) = rtlpci->receive_config;
107 break; 106 break;
108 case HW_VAR_RF_STATE: 107 case HW_VAR_RF_STATE:
109 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; 108 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
110 break; 109 break;
111 case HW_VAR_FWLPS_RF_ON:{ 110 case HW_VAR_FWLPS_RF_ON:{
112 enum rf_pwrstate rfState; 111 enum rf_pwrstate rfstate;
113 u32 val_rcr; 112 u32 val_rcr;
114 113
115 rtlpriv->cfg->ops->get_hw_reg(hw, 114 rtlpriv->cfg->ops->get_hw_reg(hw,
116 HW_VAR_RF_STATE, 115 HW_VAR_RF_STATE,
117 (u8 *) (&rfState)); 116 (u8 *)(&rfstate));
118 if (rfState == ERFOFF) { 117 if (rfstate == ERFOFF) {
119 *((bool *) (val)) = true; 118 *((bool *)(val)) = true;
120 } else { 119 } else {
121 val_rcr = rtl_read_dword(rtlpriv, REG_RCR); 120 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
122 val_rcr &= 0x00070000; 121 val_rcr &= 0x00070000;
123 if (val_rcr) 122 if (val_rcr)
124 *((bool *) (val)) = false; 123 *((bool *)(val)) = false;
125 else 124 else
126 *((bool *) (val)) = true; 125 *((bool *)(val)) = true;
126 }
127 break;
127 } 128 }
128 break; }
129 case HW_VAR_FW_PSMODE_STATUS: 129 case HW_VAR_FW_PSMODE_STATUS:
130 *((bool *) (val)) = ppsc->fw_current_inpsmode; 130 *((bool *)(val)) = ppsc->fw_current_inpsmode;
131 break; 131 break;
132 case HW_VAR_CORRECT_TSF:{ 132 case HW_VAR_CORRECT_TSF:{
133 u64 tsf; 133 u64 tsf;
134 u32 *ptsf_low = (u32 *)&tsf; 134 u32 *ptsf_low = (u32 *)&tsf;
135 u32 *ptsf_high = ((u32 *)&tsf) + 1; 135 u32 *ptsf_high = ((u32 *)&tsf) + 1;
136 136
137 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); 137 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
138 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); 138 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
139 139
140 *((u64 *) (val)) = tsf; 140 *((u64 *)(val)) = tsf;
141 141
142 break; } 142 break;
143 }
143 default: 144 default:
144 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 145 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
145 "switch case not process\n"); 146 "switch case not process\n");
146 break; 147 break;
147 } 148 }
148} 149}
149 150
150void rtl8723ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 151void rtl8723e_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
151{ 152{
152 struct rtl_priv *rtlpriv = rtl_priv(hw); 153 struct rtl_priv *rtlpriv = rtl_priv(hw);
153 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
154 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 154 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
155 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 155 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
156 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 156 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
@@ -158,362 +158,400 @@ void rtl8723ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
158 u8 idx; 158 u8 idx;
159 159
160 switch (variable) { 160 switch (variable) {
161 case HW_VAR_ETHER_ADDR: 161 case HW_VAR_ETHER_ADDR:{
162 for (idx = 0; idx < ETH_ALEN; idx++) { 162 for (idx = 0; idx < ETH_ALEN; idx++) {
163 rtl_write_byte(rtlpriv, (REG_MACID + idx), 163 rtl_write_byte(rtlpriv, (REG_MACID + idx),
164 val[idx]); 164 val[idx]);
165 }
166 break;
165 } 167 }
166 break;
167 case HW_VAR_BASIC_RATE:{ 168 case HW_VAR_BASIC_RATE:{
168 u16 rate_cfg = ((u16 *) val)[0]; 169 u16 b_rate_cfg = ((u16 *)val)[0];
169 u8 rate_index = 0; 170 u8 rate_index = 0;
170 rate_cfg = rate_cfg & 0x15f; 171
171 rate_cfg |= 0x01; 172 b_rate_cfg = b_rate_cfg & 0x15f;
172 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff); 173 b_rate_cfg |= 0x01;
173 rtl_write_byte(rtlpriv, REG_RRSR + 1, 174 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
174 (rate_cfg >> 8) & 0xff); 175 rtl_write_byte(rtlpriv, REG_RRSR + 1,
175 while (rate_cfg > 0x1) { 176 (b_rate_cfg >> 8) & 0xff);
176 rate_cfg = (rate_cfg >> 1); 177 while (b_rate_cfg > 0x1) {
177 rate_index++; 178 b_rate_cfg = (b_rate_cfg >> 1);
179 rate_index++;
180 }
181 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
182 rate_index);
183 break;
178 } 184 }
179 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 185 case HW_VAR_BSSID:{
180 rate_index); 186 for (idx = 0; idx < ETH_ALEN; idx++) {
181 break; } 187 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
182 case HW_VAR_BSSID: 188 val[idx]);
183 for (idx = 0; idx < ETH_ALEN; idx++) { 189 }
184 rtl_write_byte(rtlpriv, (REG_BSSID + idx), 190 break;
185 val[idx]);
186 } 191 }
187 break; 192 case HW_VAR_SIFS:{
188 case HW_VAR_SIFS: 193 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
189 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); 194 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
190 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
191 195
192 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); 196 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
193 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); 197 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
194 198
195 if (!mac->ht_enable) 199 if (!mac->ht_enable)
196 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 200 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
197 0x0e0e); 201 0x0e0e);
198 else 202 else
199 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 203 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
200 *((u16 *) val)); 204 *((u16 *)val));
201 break; 205 break;
206 }
202 case HW_VAR_SLOT_TIME:{ 207 case HW_VAR_SLOT_TIME:{
203 u8 e_aci; 208 u8 e_aci;
204 209
205 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 210 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
206 "HW_VAR_SLOT_TIME %x\n", val[0]); 211 "HW_VAR_SLOT_TIME %x\n", val[0]);
207 212
208 rtl_write_byte(rtlpriv, REG_SLOT, val[0]); 213 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
209 214
210 for (e_aci = 0; e_aci < AC_MAX; e_aci++) { 215 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
211 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM, 216 rtlpriv->cfg->ops->set_hw_reg(hw,
212 &e_aci); 217 HW_VAR_AC_PARAM,
218 (u8 *)(&e_aci));
219 }
220 break;
213 } 221 }
214 break; }
215 case HW_VAR_ACK_PREAMBLE:{ 222 case HW_VAR_ACK_PREAMBLE:{
216 u8 reg_tmp; 223 u8 reg_tmp;
217 u8 short_preamble = (bool)*val; 224 u8 short_preamble = (bool)(*(u8 *)val);
218 reg_tmp = (mac->cur_40_prime_sc) << 5; 225
219 if (short_preamble) 226 reg_tmp = (mac->cur_40_prime_sc) << 5;
220 reg_tmp |= 0x80; 227 if (short_preamble)
221 228 reg_tmp |= 0x80;
222 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp); 229
223 break; } 230 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
231 break;
232 }
224 case HW_VAR_AMPDU_MIN_SPACE:{ 233 case HW_VAR_AMPDU_MIN_SPACE:{
225 u8 min_spacing_to_set; 234 u8 min_spacing_to_set;
226 u8 sec_min_space; 235 u8 sec_min_space;
227 236
228 min_spacing_to_set = *val; 237 min_spacing_to_set = *((u8 *)val);
229 if (min_spacing_to_set <= 7) { 238 if (min_spacing_to_set <= 7) {
230 sec_min_space = 0; 239 sec_min_space = 0;
231 240
232 if (min_spacing_to_set < sec_min_space) 241 if (min_spacing_to_set < sec_min_space)
233 min_spacing_to_set = sec_min_space; 242 min_spacing_to_set = sec_min_space;
234 243
235 mac->min_space_cfg = ((mac->min_space_cfg & 244 mac->min_space_cfg = ((mac->min_space_cfg &
236 0xf8) | 245 0xf8) |
237 min_spacing_to_set); 246 min_spacing_to_set);
238 247
239 *val = min_spacing_to_set; 248 *val = min_spacing_to_set;
240 249
241 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 250 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
242 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", 251 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
243 mac->min_space_cfg); 252 mac->min_space_cfg);
244 253
245 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 254 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
246 mac->min_space_cfg); 255 mac->min_space_cfg);
256 }
257 break;
247 } 258 }
248 break; }
249 case HW_VAR_SHORTGI_DENSITY:{ 259 case HW_VAR_SHORTGI_DENSITY:{
250 u8 density_to_set; 260 u8 density_to_set;
251 261
252 density_to_set = *val; 262 density_to_set = *((u8 *)val);
253 mac->min_space_cfg |= (density_to_set << 3); 263 mac->min_space_cfg |= (density_to_set << 3);
254 264
255 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 265 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
256 "Set HW_VAR_SHORTGI_DENSITY: %#x\n", 266 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
257 mac->min_space_cfg); 267 mac->min_space_cfg);
258 268
259 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 269 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
260 mac->min_space_cfg); 270 mac->min_space_cfg);
261 271
262 break; } 272 break;
273 }
263 case HW_VAR_AMPDU_FACTOR:{ 274 case HW_VAR_AMPDU_FACTOR:{
264 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9}; 275 u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 };
265 u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97}; 276 u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97};
266 u8 factor_toset; 277 u8 factor_toset;
267 u8 *p_regtoset = NULL; 278 u8 *p_regtoset = NULL;
268 u8 index; 279 u8 index = 0;
269 280
270 if ((pcipriv->bt_coexist.bt_coexistence) && 281 if ((rtlpriv->btcoexist.bt_coexistence) &&
271 (pcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) 282 (rtlpriv->btcoexist.bt_coexist_type ==
272 p_regtoset = regtoset_bt; 283 BT_CSR_BC4))
273 else 284 p_regtoset = regtoset_bt;
274 p_regtoset = regtoset_normal; 285 else
275 286 p_regtoset = regtoset_normal;
276 factor_toset = *val; 287
277 if (factor_toset <= 3) { 288 factor_toset = *((u8 *)val);
278 factor_toset = (1 << (factor_toset + 2)); 289 if (factor_toset <= 3) {
279 if (factor_toset > 0xf) 290 factor_toset = (1 << (factor_toset + 2));
280 factor_toset = 0xf; 291 if (factor_toset > 0xf)
281 292 factor_toset = 0xf;
282 for (index = 0; index < 4; index++) { 293
283 if ((p_regtoset[index] & 0xf0) > 294 for (index = 0; index < 4; index++) {
284 (factor_toset << 4)) 295 if ((p_regtoset[index] & 0xf0) >
285 p_regtoset[index] = 296 (factor_toset << 4))
286 (p_regtoset[index] & 0x0f) | 297 p_regtoset[index] =
287 (factor_toset << 4); 298 (p_regtoset[index] & 0x0f) |
288 299 (factor_toset << 4);
289 if ((p_regtoset[index] & 0x0f) > 300
290 factor_toset) 301 if ((p_regtoset[index] & 0x0f) >
291 p_regtoset[index] = 302 factor_toset)
292 (p_regtoset[index] & 0xf0) | 303 p_regtoset[index] =
293 (factor_toset); 304 (p_regtoset[index] & 0xf0) |
294 305 (factor_toset);
295 rtl_write_byte(rtlpriv, 306
296 (REG_AGGLEN_LMT + index), 307 rtl_write_byte(rtlpriv,
297 p_regtoset[index]); 308 (REG_AGGLEN_LMT + index),
309 p_regtoset[index]);
310 }
298 311
312 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
313 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
314 factor_toset);
299 } 315 }
300 316 break;
301 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
302 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
303 factor_toset);
304 } 317 }
305 break; }
306 case HW_VAR_AC_PARAM:{ 318 case HW_VAR_AC_PARAM:{
307 u8 e_aci = *val; 319 u8 e_aci = *((u8 *)val);
308 rtl8723_dm_init_edca_turbo(hw);
309 320
310 if (rtlpci->acm_method != EACMWAY2_SW) 321 rtl8723_dm_init_edca_turbo(hw);
311 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL, 322
312 &e_aci); 323 if (rtlpci->acm_method != EACMWAY2_SW)
313 break; } 324 rtlpriv->cfg->ops->set_hw_reg(hw,
325 HW_VAR_ACM_CTRL,
326 (u8 *)(&e_aci));
327 break;
328 }
314 case HW_VAR_ACM_CTRL:{ 329 case HW_VAR_ACM_CTRL:{
315 u8 e_aci = *val; 330 u8 e_aci = *((u8 *)val);
316 union aci_aifsn *p_aci_aifsn = 331 union aci_aifsn *p_aci_aifsn =
317 (union aci_aifsn *)(&(mac->ac[0].aifs)); 332 (union aci_aifsn *)(&mac->ac[0].aifs);
318 u8 acm = p_aci_aifsn->f.acm; 333 u8 acm = p_aci_aifsn->f.acm;
319 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL); 334 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
320 335
321 acm_ctrl |= ((rtlpci->acm_method == 2) ? 0x0 : 0x1); 336 acm_ctrl =
322 337 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
323 if (acm) { 338
324 switch (e_aci) { 339 if (acm) {
325 case AC0_BE: 340 switch (e_aci) {
326 acm_ctrl |= AcmHw_BeqEn; 341 case AC0_BE:
327 break; 342 acm_ctrl |= ACMHW_BEQEN;
328 case AC2_VI: 343 break;
329 acm_ctrl |= AcmHw_ViqEn; 344 case AC2_VI:
330 break; 345 acm_ctrl |= ACMHW_VIQEN;
331 case AC3_VO: 346 break;
332 acm_ctrl |= AcmHw_VoqEn; 347 case AC3_VO:
333 break; 348 acm_ctrl |= ACMHW_VOQEN;
334 default: 349 break;
335 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 350 default:
336 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n", 351 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
337 acm); 352 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
338 break; 353 acm);
339 } 354 break;
340 } else { 355 }
341 switch (e_aci) { 356 } else {
342 case AC0_BE: 357 switch (e_aci) {
343 acm_ctrl &= (~AcmHw_BeqEn); 358 case AC0_BE:
344 break; 359 acm_ctrl &= (~ACMHW_BEQEN);
345 case AC2_VI: 360 break;
346 acm_ctrl &= (~AcmHw_ViqEn); 361 case AC2_VI:
347 break; 362 acm_ctrl &= (~ACMHW_VIQEN);
348 case AC3_VO: 363 break;
349 acm_ctrl &= (~AcmHw_BeqEn); 364 case AC3_VO:
350 break; 365 acm_ctrl &= (~ACMHW_BEQEN);
351 default: 366 break;
352 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 367 default:
353 "switch case not processed\n"); 368 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
354 break; 369 "switch case not process\n");
370 break;
371 }
355 } 372 }
356 }
357 373
358 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE, 374 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
359 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", 375 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
360 acm_ctrl); 376 acm_ctrl);
361 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl); 377 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
362 break; } 378 break;
363 case HW_VAR_RCR: 379 }
364 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]); 380 case HW_VAR_RCR:{
365 rtlpci->receive_config = ((u32 *) (val))[0]; 381 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
366 break; 382 rtlpci->receive_config = ((u32 *)(val))[0];
383 break;
384 }
367 case HW_VAR_RETRY_LIMIT:{ 385 case HW_VAR_RETRY_LIMIT:{
368 u8 retry_limit = *val; 386 u8 retry_limit = ((u8 *)(val))[0];
369 387
370 rtl_write_word(rtlpriv, REG_RL, 388 rtl_write_word(rtlpriv, REG_RL,
371 retry_limit << RETRY_LIMIT_SHORT_SHIFT | 389 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
372 retry_limit << RETRY_LIMIT_LONG_SHIFT); 390 retry_limit << RETRY_LIMIT_LONG_SHIFT);
373 break; } 391 break;
392 }
374 case HW_VAR_DUAL_TSF_RST: 393 case HW_VAR_DUAL_TSF_RST:
375 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); 394 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
376 break; 395 break;
377 case HW_VAR_EFUSE_BYTES: 396 case HW_VAR_EFUSE_BYTES:
378 rtlefuse->efuse_usedbytes = *((u16 *) val); 397 rtlefuse->efuse_usedbytes = *((u16 *)val);
379 break; 398 break;
380 case HW_VAR_EFUSE_USAGE: 399 case HW_VAR_EFUSE_USAGE:
381 rtlefuse->efuse_usedpercentage = *val; 400 rtlefuse->efuse_usedpercentage = *((u8 *)val);
382 break; 401 break;
383 case HW_VAR_IO_CMD: 402 case HW_VAR_IO_CMD:
384 rtl8723ae_phy_set_io_cmd(hw, (*(enum io_type *)val)); 403 rtl8723e_phy_set_io_cmd(hw, (*(enum io_type *)val));
385 break; 404 break;
386 case HW_VAR_WPA_CONFIG: 405 case HW_VAR_WPA_CONFIG:
387 rtl_write_byte(rtlpriv, REG_SECCFG, *val); 406 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
388 break; 407 break;
389 case HW_VAR_SET_RPWM:{ 408 case HW_VAR_SET_RPWM:{
390 u8 rpwm_val; 409 u8 rpwm_val;
391 410
392 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM); 411 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
393 udelay(1); 412 udelay(1);
394 413
395 if (rpwm_val & BIT(7)) { 414 if (rpwm_val & BIT(7)) {
396 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val); 415 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
397 } else { 416 (*(u8 *)val));
398 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val | BIT(7)); 417 } else {
399 } 418 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
419 ((*(u8 *)val) | BIT(7)));
420 }
400 421
401 break; } 422 break;
423 }
402 case HW_VAR_H2C_FW_PWRMODE:{ 424 case HW_VAR_H2C_FW_PWRMODE:{
403 u8 psmode = *val; 425 u8 psmode = (*(u8 *)val);
404 426
405 if (psmode != FW_PS_ACTIVE_MODE) 427 if (psmode != FW_PS_ACTIVE_MODE)
406 rtl8723ae_dm_rf_saving(hw, true); 428 rtl8723e_dm_rf_saving(hw, true);
407 429
408 rtl8723ae_set_fw_pwrmode_cmd(hw, *val); 430 rtl8723e_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
409 break; } 431 break;
432 }
410 case HW_VAR_FW_PSMODE_STATUS: 433 case HW_VAR_FW_PSMODE_STATUS:
411 ppsc->fw_current_inpsmode = *((bool *) val); 434 ppsc->fw_current_inpsmode = *((bool *)val);
412 break; 435 break;
413 case HW_VAR_H2C_FW_JOINBSSRPT:{ 436 case HW_VAR_H2C_FW_JOINBSSRPT:{
414 u8 mstatus = *val; 437 u8 mstatus = (*(u8 *)val);
415 u8 tmp_regcr, tmp_reg422; 438 u8 tmp_regcr, tmp_reg422;
416 bool recover = false; 439 bool b_recover = false;
417 440
418 if (mstatus == RT_MEDIA_CONNECT) { 441 if (mstatus == RT_MEDIA_CONNECT) {
419 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL); 442 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
420 443 NULL);
421 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); 444
422 rtl_write_byte(rtlpriv, REG_CR + 1, 445 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
423 (tmp_regcr | BIT(0))); 446 rtl_write_byte(rtlpriv, REG_CR + 1,
424 447 (tmp_regcr | BIT(0)));
425 _rtl8723ae_set_bcn_ctrl_reg(hw, 0, BIT(3)); 448
426 _rtl8723ae_set_bcn_ctrl_reg(hw, BIT(4), 0); 449 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(3));
450 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(4), 0);
451
452 tmp_reg422 =
453 rtl_read_byte(rtlpriv,
454 REG_FWHW_TXQ_CTRL + 2);
455 if (tmp_reg422 & BIT(6))
456 b_recover = true;
457 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
458 tmp_reg422 & (~BIT(6)));
427 459
428 tmp_reg422 = rtl_read_byte(rtlpriv, 460 rtl8723e_set_fw_rsvdpagepkt(hw, 0);
429 REG_FWHW_TXQ_CTRL + 2);
430 if (tmp_reg422 & BIT(6))
431 recover = true;
432 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
433 tmp_reg422 & (~BIT(6)));
434 461
435 rtl8723ae_set_fw_rsvdpagepkt(hw, 0); 462 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(3), 0);
463 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(4));
436 464
437 _rtl8723ae_set_bcn_ctrl_reg(hw, BIT(3), 0); 465 if (b_recover) {
438 _rtl8723ae_set_bcn_ctrl_reg(hw, 0, BIT(4)); 466 rtl_write_byte(rtlpriv,
467 REG_FWHW_TXQ_CTRL + 2,
468 tmp_reg422);
469 }
439 470
440 if (recover) 471 rtl_write_byte(rtlpriv, REG_CR + 1,
441 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, 472 (tmp_regcr & ~(BIT(0))));
442 tmp_reg422); 473 }
474 rtl8723e_set_fw_joinbss_report_cmd(hw, (*(u8 *)val));
443 475
444 rtl_write_byte(rtlpriv, REG_CR + 1, 476 break;
445 (tmp_regcr & ~(BIT(0))));
446 } 477 }
447 rtl8723ae_set_fw_joinbss_report_cmd(hw, *val); 478 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:{
448 479 rtl8723e_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
449 break; }
450 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
451 rtl8723ae_set_p2p_ps_offload_cmd(hw, *val);
452 break; 480 break;
481 }
453 case HW_VAR_AID:{ 482 case HW_VAR_AID:{
454 u16 u2btmp; 483 u16 u2btmp;
455 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); 484
456 u2btmp &= 0xC000; 485 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
457 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp | 486 u2btmp &= 0xC000;
458 mac->assoc_id)); 487 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
459 break; } 488 (u2btmp | mac->assoc_id));
489
490 break;
491 }
460 case HW_VAR_CORRECT_TSF:{ 492 case HW_VAR_CORRECT_TSF:{
461 u8 btype_ibss = *val; 493 u8 btype_ibss = ((u8 *)(val))[0];
462 494
463 if (btype_ibss == true) 495 if (btype_ibss)
464 _rtl8723ae_stop_tx_beacon(hw); 496 _rtl8723e_stop_tx_beacon(hw);
465 497
466 _rtl8723ae_set_bcn_ctrl_reg(hw, 0, BIT(3)); 498 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(3));
467 499
468 rtl_write_dword(rtlpriv, REG_TSFTR, 500 rtl_write_dword(rtlpriv, REG_TSFTR,
469 (u32) (mac->tsf & 0xffffffff)); 501 (u32)(mac->tsf & 0xffffffff));
470 rtl_write_dword(rtlpriv, REG_TSFTR + 4, 502 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
471 (u32) ((mac->tsf >> 32) & 0xffffffff)); 503 (u32)((mac->tsf >> 32) & 0xffffffff));
472 504
473 _rtl8723ae_set_bcn_ctrl_reg(hw, BIT(3), 0); 505 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(3), 0);
474 506
475 if (btype_ibss == true) 507 if (btype_ibss)
476 _rtl8723ae_resume_tx_beacon(hw); 508 _rtl8723e_resume_tx_beacon(hw);
477 break; } 509
478 case HW_VAR_FW_LPS_ACTION: { 510 break;
479 bool enter_fwlps = *((bool *)val); 511 }
480 u8 rpwm_val, fw_pwrmode; 512 case HW_VAR_FW_LPS_ACTION:{
481 bool fw_current_inps; 513 bool b_enter_fwlps = *((bool *)val);
482 514 u8 rpwm_val, fw_pwrmode;
483 if (enter_fwlps) { 515 bool fw_current_inps;
484 rpwm_val = 0x02; /* RF off */ 516
485 fw_current_inps = true; 517 if (b_enter_fwlps) {
486 rtlpriv->cfg->ops->set_hw_reg(hw, 518 rpwm_val = 0x02; /* RF off */
487 HW_VAR_FW_PSMODE_STATUS, 519 fw_current_inps = true;
488 (u8 *)(&fw_current_inps)); 520 rtlpriv->cfg->ops->set_hw_reg(hw,
489 rtlpriv->cfg->ops->set_hw_reg(hw, 521 HW_VAR_FW_PSMODE_STATUS,
490 HW_VAR_H2C_FW_PWRMODE, 522 (u8 *)(&fw_current_inps));
491 &ppsc->fwctrl_psmode); 523 rtlpriv->cfg->ops->set_hw_reg(hw,
492 524 HW_VAR_H2C_FW_PWRMODE,
493 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, 525 (u8 *)(&ppsc->fwctrl_psmode));
494 &rpwm_val); 526
495 } else { 527 rtlpriv->cfg->ops->set_hw_reg(hw,
496 rpwm_val = 0x0C; /* RF on */ 528 HW_VAR_SET_RPWM,
497 fw_pwrmode = FW_PS_ACTIVE_MODE; 529 (u8 *)(&rpwm_val));
498 fw_current_inps = false; 530 } else {
499 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, 531 rpwm_val = 0x0C; /* RF on */
500 &rpwm_val); 532 fw_pwrmode = FW_PS_ACTIVE_MODE;
501 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 533 fw_current_inps = false;
502 &fw_pwrmode); 534 rtlpriv->cfg->ops->set_hw_reg(hw,
503 535 HW_VAR_SET_RPWM,
504 rtlpriv->cfg->ops->set_hw_reg(hw, 536 (u8 *)(&rpwm_val));
505 HW_VAR_FW_PSMODE_STATUS, 537 rtlpriv->cfg->ops->set_hw_reg(hw,
506 (u8 *)(&fw_current_inps)); 538 HW_VAR_H2C_FW_PWRMODE,
539 (u8 *)(&fw_pwrmode));
540
541 rtlpriv->cfg->ops->set_hw_reg(hw,
542 HW_VAR_FW_PSMODE_STATUS,
543 (u8 *)(&fw_current_inps));
544 }
545 break;
507 } 546 }
508 break; }
509 default: 547 default:
510 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 548 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
511 "switch case not processed\n"); 549 "switch case not process\n");
512 break; 550 break;
513 } 551 }
514} 552}
515 553
516static bool _rtl8723ae_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) 554static bool _rtl8723e_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
517{ 555{
518 struct rtl_priv *rtlpriv = rtl_priv(hw); 556 struct rtl_priv *rtlpriv = rtl_priv(hw);
519 bool status = true; 557 bool status = true;
@@ -540,24 +578,49 @@ static bool _rtl8723ae_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
540 return status; 578 return status;
541} 579}
542 580
543static bool _rtl8723ae_llt_table_init(struct ieee80211_hw *hw) 581static bool _rtl8723e_llt_table_init(struct ieee80211_hw *hw)
544{ 582{
545 struct rtl_priv *rtlpriv = rtl_priv(hw); 583 struct rtl_priv *rtlpriv = rtl_priv(hw);
546 unsigned short i; 584 unsigned short i;
547 u8 txpktbuf_bndy; 585 u8 txpktbuf_bndy;
548 u8 maxPage; 586 u8 maxpage;
549 bool status; 587 bool status;
550 u8 ubyte; 588 u8 ubyte;
551 589
552 maxPage = 255; 590#if LLT_CONFIG == 1
591 maxpage = 255;
592 txpktbuf_bndy = 252;
593#elif LLT_CONFIG == 2
594 maxpage = 127;
595 txpktbuf_bndy = 124;
596#elif LLT_CONFIG == 3
597 maxpage = 255;
598 txpktbuf_bndy = 174;
599#elif LLT_CONFIG == 4
600 maxpage = 255;
553 txpktbuf_bndy = 246; 601 txpktbuf_bndy = 246;
602#elif LLT_CONFIG == 5
603 maxpage = 255;
604 txpktbuf_bndy = 246;
605#endif
554 606
555 rtl_write_byte(rtlpriv, REG_CR, 0x8B); 607 rtl_write_byte(rtlpriv, REG_CR, 0x8B);
556 608
609#if LLT_CONFIG == 1
610 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c);
611 rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c);
612#elif LLT_CONFIG == 2
613 rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010);
614#elif LLT_CONFIG == 3
615 rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484);
616#elif LLT_CONFIG == 4
617 rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c);
618#elif LLT_CONFIG == 5
557 rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000); 619 rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000);
558 620
559 rtl_write_dword(rtlpriv, REG_RQPN, 0x80ac1c29); 621 rtl_write_dword(rtlpriv, REG_RQPN, 0x80ac1c29);
560 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x03); 622 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x03);
623#endif
561 624
562 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy)); 625 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy));
563 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy); 626 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
@@ -570,22 +633,22 @@ static bool _rtl8723ae_llt_table_init(struct ieee80211_hw *hw)
570 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4); 633 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
571 634
572 for (i = 0; i < (txpktbuf_bndy - 1); i++) { 635 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
573 status = _rtl8723ae_llt_write(hw, i, i + 1); 636 status = _rtl8723e_llt_write(hw, i, i + 1);
574 if (true != status) 637 if (true != status)
575 return status; 638 return status;
576 } 639 }
577 640
578 status = _rtl8723ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); 641 status = _rtl8723e_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
579 if (true != status) 642 if (true != status)
580 return status; 643 return status;
581 644
582 for (i = txpktbuf_bndy; i < maxPage; i++) { 645 for (i = txpktbuf_bndy; i < maxpage; i++) {
583 status = _rtl8723ae_llt_write(hw, i, (i + 1)); 646 status = _rtl8723e_llt_write(hw, i, (i + 1));
584 if (true != status) 647 if (true != status)
585 return status; 648 return status;
586 } 649 }
587 650
588 status = _rtl8723ae_llt_write(hw, maxPage, txpktbuf_bndy); 651 status = _rtl8723e_llt_write(hw, maxpage, txpktbuf_bndy);
589 if (true != status) 652 if (true != status)
590 return status; 653 return status;
591 654
@@ -596,28 +659,29 @@ static bool _rtl8723ae_llt_table_init(struct ieee80211_hw *hw)
596 return true; 659 return true;
597} 660}
598 661
599static void _rtl8723ae_gen_refresh_led_state(struct ieee80211_hw *hw) 662static void _rtl8723e_gen_refresh_led_state(struct ieee80211_hw *hw)
600{ 663{
601 struct rtl_priv *rtlpriv = rtl_priv(hw); 664 struct rtl_priv *rtlpriv = rtl_priv(hw);
602 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 665 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
603 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 666 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
604 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0); 667 struct rtl_led *pled0 = &pcipriv->ledctl.sw_led0;
605 668
606 if (rtlpriv->rtlhal.up_first_time) 669 if (rtlpriv->rtlhal.up_first_time)
607 return; 670 return;
608 671
609 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) 672 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
610 rtl8723ae_sw_led_on(hw, pLed0); 673 rtl8723e_sw_led_on(hw, pled0);
611 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT) 674 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
612 rtl8723ae_sw_led_on(hw, pLed0); 675 rtl8723e_sw_led_on(hw, pled0);
613 else 676 else
614 rtl8723ae_sw_led_off(hw, pLed0); 677 rtl8723e_sw_led_off(hw, pled0);
615} 678}
616 679
617static bool _rtl8712e_init_mac(struct ieee80211_hw *hw) 680static bool _rtl8712e_init_mac(struct ieee80211_hw *hw)
618{ 681{
619 struct rtl_priv *rtlpriv = rtl_priv(hw); 682 struct rtl_priv *rtlpriv = rtl_priv(hw);
620 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 683 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
684
621 unsigned char bytetmp; 685 unsigned char bytetmp;
622 unsigned short wordtmp; 686 unsigned short wordtmp;
623 u16 retry = 0; 687 u16 retry = 0;
@@ -631,7 +695,6 @@ static bool _rtl8712e_init_mac(struct ieee80211_hw *hw)
631 else 695 else
632 mac_func_enable = false; 696 mac_func_enable = false;
633 697
634
635 /* HW Power on sequence */ 698 /* HW Power on sequence */
636 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 699 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
637 PWR_INTF_PCI_MSK, Rtl8723_NIC_ENABLE_FLOW)) 700 PWR_INTF_PCI_MSK, Rtl8723_NIC_ENABLE_FLOW))
@@ -670,7 +733,7 @@ static bool _rtl8712e_init_mac(struct ieee80211_hw *hw)
670 rtl_write_word(rtlpriv, REG_CR + 1, 0x06); 733 rtl_write_word(rtlpriv, REG_CR + 1, 0x06);
671 734
672 if (!mac_func_enable) { 735 if (!mac_func_enable) {
673 if (_rtl8723ae_llt_table_init(hw) == false) 736 if (!_rtl8723e_llt_table_init(hw))
674 return false; 737 return false;
675 } 738 }
676 739
@@ -679,7 +742,8 @@ static bool _rtl8712e_init_mac(struct ieee80211_hw *hw)
679 742
680 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff); 743 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff);
681 744
682 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL) & 0xf; 745 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
746 wordtmp &= 0xf;
683 wordtmp |= 0xF771; 747 wordtmp |= 0xF771;
684 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp); 748 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
685 749
@@ -722,22 +786,23 @@ static bool _rtl8712e_init_mac(struct ieee80211_hw *hw)
722 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL); 786 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
723 } while ((retry < 200) && (bytetmp & BIT(7))); 787 } while ((retry < 200) && (bytetmp & BIT(7)));
724 788
725 _rtl8723ae_gen_refresh_led_state(hw); 789 _rtl8723e_gen_refresh_led_state(hw);
726 790
727 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0); 791 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
728 792
729 return true; 793 return true;
730} 794}
731 795
732static void _rtl8723ae_hw_configure(struct ieee80211_hw *hw) 796static void _rtl8723e_hw_configure(struct ieee80211_hw *hw)
733{ 797{
734 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 798 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
735 struct rtl_priv *rtlpriv = rtl_priv(hw); 799 struct rtl_priv *rtlpriv = rtl_priv(hw);
736 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
737 u8 reg_bw_opmode; 800 u8 reg_bw_opmode;
738 u32 reg_prsr; 801 u32 reg_ratr, reg_prsr;
739 802
740 reg_bw_opmode = BW_OPMODE_20MHZ; 803 reg_bw_opmode = BW_OPMODE_20MHZ;
804 reg_ratr = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
805 RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
741 reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG; 806 reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
742 807
743 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8); 808 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
@@ -763,8 +828,8 @@ static void _rtl8723ae_hw_configure(struct ieee80211_hw *hw)
763 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000); 828 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
764 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504); 829 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
765 830
766 if ((pcipriv->bt_coexist.bt_coexistence) && 831 if ((rtlpriv->btcoexist.bt_coexistence) &&
767 (pcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) 832 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4))
768 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431); 833 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431);
769 else 834 else
770 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841); 835 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
@@ -783,8 +848,8 @@ static void _rtl8723ae_hw_configure(struct ieee80211_hw *hw)
783 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C); 848 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
784 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16); 849 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
785 850
786 if ((pcipriv->bt_coexist.bt_coexistence) && 851 if ((rtlpriv->btcoexist.bt_coexistence) &&
787 (pcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) { 852 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4)) {
788 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); 853 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
789 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402); 854 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402);
790 } else { 855 } else {
@@ -792,8 +857,8 @@ static void _rtl8723ae_hw_configure(struct ieee80211_hw *hw)
792 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); 857 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
793 } 858 }
794 859
795 if ((pcipriv->bt_coexist.bt_coexistence) && 860 if ((rtlpriv->btcoexist.bt_coexistence) &&
796 (pcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) 861 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4))
797 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666); 862 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
798 else 863 else
799 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666); 864 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666);
@@ -813,7 +878,7 @@ static void _rtl8723ae_hw_configure(struct ieee80211_hw *hw)
813 rtl_write_dword(rtlpriv, 0x394, 0x1); 878 rtl_write_dword(rtlpriv, 0x394, 0x1);
814} 879}
815 880
816static void _rtl8723ae_enable_aspm_back_door(struct ieee80211_hw *hw) 881static void _rtl8723e_enable_aspm_back_door(struct ieee80211_hw *hw)
817{ 882{
818 struct rtl_priv *rtlpriv = rtl_priv(hw); 883 struct rtl_priv *rtlpriv = rtl_priv(hw);
819 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 884 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
@@ -831,15 +896,15 @@ static void _rtl8723ae_enable_aspm_back_door(struct ieee80211_hw *hw)
831 rtl_write_byte(rtlpriv, 0x352, 0x1); 896 rtl_write_byte(rtlpriv, 0x352, 0x1);
832} 897}
833 898
834void rtl8723ae_enable_hw_security_config(struct ieee80211_hw *hw) 899void rtl8723e_enable_hw_security_config(struct ieee80211_hw *hw)
835{ 900{
836 struct rtl_priv *rtlpriv = rtl_priv(hw); 901 struct rtl_priv *rtlpriv = rtl_priv(hw);
837 u8 sec_reg_value; 902 u8 sec_reg_value;
838 903
839 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 904 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
840 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", 905 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
841 rtlpriv->sec.pairwise_enc_algorithm, 906 rtlpriv->sec.pairwise_enc_algorithm,
842 rtlpriv->sec.group_enc_algorithm); 907 rtlpriv->sec.group_enc_algorithm);
843 908
844 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { 909 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
845 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 910 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
@@ -847,11 +912,11 @@ void rtl8723ae_enable_hw_security_config(struct ieee80211_hw *hw)
847 return; 912 return;
848 } 913 }
849 914
850 sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable; 915 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
851 916
852 if (rtlpriv->sec.use_defaultkey) { 917 if (rtlpriv->sec.use_defaultkey) {
853 sec_reg_value |= SCR_TxUseDK; 918 sec_reg_value |= SCR_TXUSEDK;
854 sec_reg_value |= SCR_RxUseDK; 919 sec_reg_value |= SCR_RXUSEDK;
855 } 920 }
856 921
857 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK); 922 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
@@ -865,7 +930,7 @@ void rtl8723ae_enable_hw_security_config(struct ieee80211_hw *hw)
865 930
866} 931}
867 932
868int rtl8723ae_hw_init(struct ieee80211_hw *hw) 933int rtl8723e_hw_init(struct ieee80211_hw *hw)
869{ 934{
870 struct rtl_priv *rtlpriv = rtl_priv(hw); 935 struct rtl_priv *rtlpriv = rtl_priv(hw);
871 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 936 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
@@ -888,6 +953,7 @@ int rtl8723ae_hw_init(struct ieee80211_hw *hw)
888 */ 953 */
889 local_save_flags(flags); 954 local_save_flags(flags);
890 local_irq_enable(); 955 local_irq_enable();
956 rtlhal->fw_ready = false;
891 957
892 rtlpriv->intf_ops->disable_aspm(hw); 958 rtlpriv->intf_ops->disable_aspm(hw);
893 rtstatus = _rtl8712e_init_mac(hw); 959 rtstatus = _rtl8712e_init_mac(hw);
@@ -897,20 +963,19 @@ int rtl8723ae_hw_init(struct ieee80211_hw *hw)
897 goto exit; 963 goto exit;
898 } 964 }
899 965
900 err = rtl8723_download_fw(hw, false); 966 err = rtl8723_download_fw(hw, false, FW_8192C_POLLING_TIMEOUT_COUNT);
901 if (err) { 967 if (err) {
902 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 968 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
903 "Failed to download FW. Init HW without FW now..\n"); 969 "Failed to download FW. Init HW without FW now..\n");
904 err = 1; 970 err = 1;
905 goto exit; 971 goto exit;
906 } else {
907 rtlhal->fw_ready = true;
908 } 972 }
973 rtlhal->fw_ready = true;
909 974
910 rtlhal->last_hmeboxnum = 0; 975 rtlhal->last_hmeboxnum = 0;
911 rtl8723ae_phy_mac_config(hw); 976 rtl8723e_phy_mac_config(hw);
912 /* because the last function modifies RCR, we update 977 /* because last function modify RCR, so we update
913 * rcr var here, or TP will be unstable as ther receive_config 978 * rcr var here, or TP will unstable for receive_config
914 * is wrong, RX RCR_ACRC32 will cause TP unstable & Rx 979 * is wrong, RX RCR_ACRC32 will cause TP unstable & Rx
915 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252 980 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
916 */ 981 */
@@ -918,9 +983,9 @@ int rtl8723ae_hw_init(struct ieee80211_hw *hw)
918 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV); 983 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
919 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 984 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
920 985
921 rtl8723ae_phy_bb_config(hw); 986 rtl8723e_phy_bb_config(hw);
922 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE; 987 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
923 rtl8723ae_phy_rf_config(hw); 988 rtl8723e_phy_rf_config(hw);
924 if (IS_VENDOR_UMC_A_CUT(rtlhal->version)) { 989 if (IS_VENDOR_UMC_A_CUT(rtlhal->version)) {
925 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255); 990 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
926 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00); 991 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
@@ -939,28 +1004,29 @@ int rtl8723ae_hw_init(struct ieee80211_hw *hw)
939 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); 1004 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
940 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); 1005 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
941 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); 1006 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
942 _rtl8723ae_hw_configure(hw); 1007 _rtl8723e_hw_configure(hw);
943 rtl_cam_reset_all_entry(hw); 1008 rtl_cam_reset_all_entry(hw);
944 rtl8723ae_enable_hw_security_config(hw); 1009 rtl8723e_enable_hw_security_config(hw);
945 1010
946 ppsc->rfpwr_state = ERFON; 1011 ppsc->rfpwr_state = ERFON;
947 1012
948 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); 1013 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
949 _rtl8723ae_enable_aspm_back_door(hw); 1014 _rtl8723e_enable_aspm_back_door(hw);
950 rtlpriv->intf_ops->enable_aspm(hw); 1015 rtlpriv->intf_ops->enable_aspm(hw);
951 1016
952 rtl8723ae_bt_hw_init(hw); 1017 rtl8723e_bt_hw_init(hw);
953 1018
954 if (ppsc->rfpwr_state == ERFON) { 1019 if (ppsc->rfpwr_state == ERFON) {
955 rtl8723ae_phy_set_rfpath_switch(hw, 1); 1020 rtl8723e_phy_set_rfpath_switch(hw, 1);
956 if (rtlphy->iqk_initialized) { 1021 if (rtlphy->iqk_initialized) {
957 rtl8723ae_phy_iq_calibrate(hw, true); 1022 rtl8723e_phy_iq_calibrate(hw, true);
958 } else { 1023 } else {
959 rtl8723ae_phy_iq_calibrate(hw, false); 1024 rtl8723e_phy_iq_calibrate(hw, false);
960 rtlphy->iqk_initialized = true; 1025 rtlphy->iqk_initialized = true;
961 } 1026 }
962 1027
963 rtl8723ae_phy_lc_calibrate(hw); 1028 rtl8723e_dm_check_txpower_tracking(hw);
1029 rtl8723e_phy_lc_calibrate(hw);
964 } 1030 }
965 1031
966 tmp_u1b = efuse_read_1byte(hw, 0x1FA); 1032 tmp_u1b = efuse_read_1byte(hw, 0x1FA);
@@ -970,20 +1036,21 @@ int rtl8723ae_hw_init(struct ieee80211_hw *hw)
970 } 1036 }
971 1037
972 if (!(tmp_u1b & BIT(4))) { 1038 if (!(tmp_u1b & BIT(4))) {
973 tmp_u1b = rtl_read_byte(rtlpriv, 0x16) & 0x0F; 1039 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
1040 tmp_u1b &= 0x0F;
974 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80); 1041 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
975 udelay(10); 1042 udelay(10);
976 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90); 1043 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
977 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "under 1.5V\n"); 1044 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "under 1.5V\n");
978 } 1045 }
979 rtl8723ae_dm_init(hw); 1046 rtl8723e_dm_init(hw);
980exit: 1047exit:
981 local_irq_restore(flags); 1048 local_irq_restore(flags);
982 rtlpriv->rtlhal.being_init_adapter = false; 1049 rtlpriv->rtlhal.being_init_adapter = false;
983 return err; 1050 return err;
984} 1051}
985 1052
986static enum version_8723e _rtl8723ae_read_chip_version(struct ieee80211_hw *hw) 1053static enum version_8723e _rtl8723e_read_chip_version(struct ieee80211_hw *hw)
987{ 1054{
988 struct rtl_priv *rtlpriv = rtl_priv(hw); 1055 struct rtl_priv *rtlpriv = rtl_priv(hw);
989 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1056 struct rtl_phy *rtlphy = &(rtlpriv->phy);
@@ -993,41 +1060,41 @@ static enum version_8723e _rtl8723ae_read_chip_version(struct ieee80211_hw *hw)
993 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG); 1060 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
994 if (value32 & TRP_VAUX_EN) { 1061 if (value32 & TRP_VAUX_EN) {
995 version = (enum version_8723e)(version | 1062 version = (enum version_8723e)(version |
996 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0)); 1063 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0));
997 /* RTL8723 with BT function. */ 1064 /* RTL8723 with BT function. */
998 version = (enum version_8723e)(version | 1065 version = (enum version_8723e)(version |
999 ((value32 & BT_FUNC) ? CHIP_8723 : 0)); 1066 ((value32 & BT_FUNC) ? CHIP_8723 : 0));
1000 1067
1001 } else { 1068 } else {
1002 /* Normal mass production chip. */ 1069 /* Normal mass production chip. */
1003 version = (enum version_8723e) NORMAL_CHIP; 1070 version = (enum version_8723e) NORMAL_CHIP;
1004 version = (enum version_8723e)(version | 1071 version = (enum version_8723e)(version |
1005 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0)); 1072 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0));
1006 /* RTL8723 with BT function. */ 1073 /* RTL8723 with BT function. */
1007 version = (enum version_8723e)(version | 1074 version = (enum version_8723e)(version |
1008 ((value32 & BT_FUNC) ? CHIP_8723 : 0)); 1075 ((value32 & BT_FUNC) ? CHIP_8723 : 0));
1009 if (IS_CHIP_VENDOR_UMC(version)) 1076 if (IS_CHIP_VENDOR_UMC(version))
1010 version = (enum version_8723e)(version | 1077 version = (enum version_8723e)(version |
1011 ((value32 & CHIP_VER_RTL_MASK)));/* IC version (CUT) */ 1078 ((value32 & CHIP_VER_RTL_MASK)));/* IC version (CUT) */
1012 if (IS_8723_SERIES(version)) { 1079 if (IS_8723_SERIES(version)) {
1013 value32 = rtl_read_dword(rtlpriv, REG_GPIO_OUTSTS); 1080 value32 = rtl_read_dword(rtlpriv, REG_GPIO_OUTSTS);
1014 /* ROM code version */ 1081 /* ROM code version. */
1015 version = (enum version_8723e)(version | 1082 version = (enum version_8723e)(version |
1016 ((value32 & RF_RL_ID)>>20)); 1083 ((value32 & RF_RL_ID)>>20));
1017 } 1084 }
1018 } 1085 }
1019 1086
1020 if (IS_8723_SERIES(version)) { 1087 if (IS_8723_SERIES(version)) {
1021 value32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL); 1088 value32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
1022 rtlphy->polarity_ctl = ((value32 & WL_HWPDN_SL) ? 1089 rtlphy->polarity_ctl = ((value32 & WL_HWPDN_SL) ?
1023 RT_POLARITY_HIGH_ACT : 1090 RT_POLARITY_HIGH_ACT :
1024 RT_POLARITY_LOW_ACT); 1091 RT_POLARITY_LOW_ACT);
1025 } 1092 }
1026 switch (version) { 1093 switch (version) {
1027 case VERSION_TEST_UMC_CHIP_8723: 1094 case VERSION_TEST_UMC_CHIP_8723:
1028 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1095 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1029 "Chip Version ID: VERSION_TEST_UMC_CHIP_8723.\n"); 1096 "Chip Version ID: VERSION_TEST_UMC_CHIP_8723.\n");
1030 break; 1097 break;
1031 case VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT: 1098 case VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT:
1032 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1099 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1033 "Chip Version ID: VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT.\n"); 1100 "Chip Version ID: VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT.\n");
@@ -1051,113 +1118,124 @@ static enum version_8723e _rtl8723ae_read_chip_version(struct ieee80211_hw *hw)
1051 return version; 1118 return version;
1052} 1119}
1053 1120
1054static int _rtl8723ae_set_media_status(struct ieee80211_hw *hw, 1121static int _rtl8723e_set_media_status(struct ieee80211_hw *hw,
1055 enum nl80211_iftype type) 1122 enum nl80211_iftype type)
1056{ 1123{
1057 struct rtl_priv *rtlpriv = rtl_priv(hw); 1124 struct rtl_priv *rtlpriv = rtl_priv(hw);
1058 u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc; 1125 u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;
1059 enum led_ctl_mode ledaction = LED_CTL_NO_LINK; 1126 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1127 u8 mode = MSR_NOLINK;
1060 1128
1061 rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0); 1129 rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0);
1062 RT_TRACE(rtlpriv, COMP_BEACON, DBG_LOUD, 1130 RT_TRACE(rtlpriv, COMP_BEACON, DBG_LOUD,
1063 "clear 0x550 when set HW_VAR_MEDIA_STATUS\n"); 1131 "clear 0x550 when set HW_VAR_MEDIA_STATUS\n");
1064
1065 if (type == NL80211_IFTYPE_UNSPECIFIED ||
1066 type == NL80211_IFTYPE_STATION) {
1067 _rtl8723ae_stop_tx_beacon(hw);
1068 _rtl8723ae_enable_bcn_sufunc(hw);
1069 } else if (type == NL80211_IFTYPE_ADHOC ||
1070 type == NL80211_IFTYPE_AP) {
1071 _rtl8723ae_resume_tx_beacon(hw);
1072 _rtl8723ae_disable_bcn_sufunc(hw);
1073 } else {
1074 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1075 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1076 type);
1077 }
1078 1132
1079 switch (type) { 1133 switch (type) {
1080 case NL80211_IFTYPE_UNSPECIFIED: 1134 case NL80211_IFTYPE_UNSPECIFIED:
1081 bt_msr |= MSR_NOLINK; 1135 mode = MSR_NOLINK;
1082 ledaction = LED_CTL_LINK;
1083 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1136 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1084 "Set Network type to NO LINK!\n"); 1137 "Set Network type to NO LINK!\n");
1085 break; 1138 break;
1086 case NL80211_IFTYPE_ADHOC: 1139 case NL80211_IFTYPE_ADHOC:
1087 bt_msr |= MSR_ADHOC; 1140 mode = MSR_ADHOC;
1088 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1141 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1089 "Set Network type to Ad Hoc!\n"); 1142 "Set Network type to Ad Hoc!\n");
1090 break; 1143 break;
1091 case NL80211_IFTYPE_STATION: 1144 case NL80211_IFTYPE_STATION:
1092 bt_msr |= MSR_INFRA; 1145 mode = MSR_INFRA;
1093 ledaction = LED_CTL_LINK; 1146 ledaction = LED_CTL_LINK;
1094 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1147 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1095 "Set Network type to STA!\n"); 1148 "Set Network type to STA!\n");
1096 break; 1149 break;
1097 case NL80211_IFTYPE_AP: 1150 case NL80211_IFTYPE_AP:
1098 bt_msr |= MSR_AP; 1151 mode = MSR_AP;
1152 ledaction = LED_CTL_LINK;
1099 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1153 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1100 "Set Network type to AP!\n"); 1154 "Set Network type to AP!\n");
1101 break; 1155 break;
1102 default: 1156 default:
1103 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1157 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1104 "Network type %d not supported!\n", 1158 "Network type %d not support!\n", type);
1105 type);
1106 return 1; 1159 return 1;
1160 break;
1161 }
1107 1162
1163 /* MSR_INFRA == Link in infrastructure network;
1164 * MSR_ADHOC == Link in ad hoc network;
1165 * Therefore, check link state is necessary.
1166 *
1167 * MSR_AP == AP mode; link state is not cared here.
1168 */
1169 if (mode != MSR_AP &&
1170 rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1171 mode = MSR_NOLINK;
1172 ledaction = LED_CTL_NO_LINK;
1173 }
1174 if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1175 _rtl8723e_stop_tx_beacon(hw);
1176 _rtl8723e_enable_bcn_sub_func(hw);
1177 } else if (mode == MSR_ADHOC || mode == MSR_AP) {
1178 _rtl8723e_resume_tx_beacon(hw);
1179 _rtl8723e_disable_bcn_sub_func(hw);
1180 } else {
1181 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1182 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1183 mode);
1108 } 1184 }
1109 1185
1110 rtl_write_byte(rtlpriv, (MSR), bt_msr); 1186 rtl_write_byte(rtlpriv, (MSR), bt_msr | mode);
1111 rtlpriv->cfg->ops->led_control(hw, ledaction); 1187 rtlpriv->cfg->ops->led_control(hw, ledaction);
1112 if ((bt_msr & MSR_MASK) == MSR_AP) 1188 if (mode == MSR_AP)
1113 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); 1189 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1114 else 1190 else
1115 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); 1191 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1116 return 0; 1192 return 0;
1117} 1193}
1118 1194
1119void rtl8723ae_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) 1195void rtl8723e_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1120{ 1196{
1121 struct rtl_priv *rtlpriv = rtl_priv(hw); 1197 struct rtl_priv *rtlpriv = rtl_priv(hw);
1122 u32 reg_rcr; 1198 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1199 u32 reg_rcr = rtlpci->receive_config;
1123 1200
1124 if (rtlpriv->psc.rfpwr_state != ERFON) 1201 if (rtlpriv->psc.rfpwr_state != ERFON)
1125 return; 1202 return;
1126 1203
1127 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr)); 1204 if (check_bssid) {
1128
1129 if (check_bssid == true) {
1130 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN); 1205 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1131 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, 1206 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1132 (u8 *)(&reg_rcr)); 1207 (u8 *)(&reg_rcr));
1133 _rtl8723ae_set_bcn_ctrl_reg(hw, 0, BIT(4)); 1208 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(4));
1134 } else if (check_bssid == false) { 1209 } else if (!check_bssid) {
1135 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN)); 1210 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1136 _rtl8723ae_set_bcn_ctrl_reg(hw, BIT(4), 0); 1211 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(4), 0);
1137 rtlpriv->cfg->ops->set_hw_reg(hw, 1212 rtlpriv->cfg->ops->set_hw_reg(hw,
1138 HW_VAR_RCR, (u8 *) (&reg_rcr)); 1213 HW_VAR_RCR, (u8 *)(&reg_rcr));
1139 } 1214 }
1140} 1215}
1141 1216
1142int rtl8723ae_set_network_type(struct ieee80211_hw *hw, 1217int rtl8723e_set_network_type(struct ieee80211_hw *hw,
1143 enum nl80211_iftype type) 1218 enum nl80211_iftype type)
1144{ 1219{
1145 struct rtl_priv *rtlpriv = rtl_priv(hw); 1220 struct rtl_priv *rtlpriv = rtl_priv(hw);
1146 1221
1147 if (_rtl8723ae_set_media_status(hw, type)) 1222 if (_rtl8723e_set_media_status(hw, type))
1148 return -EOPNOTSUPP; 1223 return -EOPNOTSUPP;
1149 1224
1150 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { 1225 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1151 if (type != NL80211_IFTYPE_AP) 1226 if (type != NL80211_IFTYPE_AP)
1152 rtl8723ae_set_check_bssid(hw, true); 1227 rtl8723e_set_check_bssid(hw, true);
1153 } else { 1228 } else {
1154 rtl8723ae_set_check_bssid(hw, false); 1229 rtl8723e_set_check_bssid(hw, false);
1155 } 1230 }
1231
1156 return 0; 1232 return 0;
1157} 1233}
1158 1234
1159/* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */ 1235/* don't set REG_EDCA_BE_PARAM here
1160void rtl8723ae_set_qos(struct ieee80211_hw *hw, int aci) 1236 * because mac80211 will send pkt when scan
1237 */
1238void rtl8723e_set_qos(struct ieee80211_hw *hw, int aci)
1161{ 1239{
1162 struct rtl_priv *rtlpriv = rtl_priv(hw); 1240 struct rtl_priv *rtlpriv = rtl_priv(hw);
1163 1241
@@ -1167,7 +1245,6 @@ void rtl8723ae_set_qos(struct ieee80211_hw *hw, int aci)
1167 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f); 1245 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1168 break; 1246 break;
1169 case AC0_BE: 1247 case AC0_BE:
1170 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4ac_param); */
1171 break; 1248 break;
1172 case AC2_VI: 1249 case AC2_VI:
1173 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322); 1250 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
@@ -1181,7 +1258,19 @@ void rtl8723ae_set_qos(struct ieee80211_hw *hw, int aci)
1181 } 1258 }
1182} 1259}
1183 1260
1184void rtl8723ae_enable_interrupt(struct ieee80211_hw *hw) 1261static void rtl8723e_clear_interrupt(struct ieee80211_hw *hw)
1262{
1263 struct rtl_priv *rtlpriv = rtl_priv(hw);
1264 u32 tmp;
1265
1266 tmp = rtl_read_dword(rtlpriv, REG_HISR);
1267 rtl_write_dword(rtlpriv, REG_HISR, tmp);
1268
1269 tmp = rtl_read_dword(rtlpriv, REG_HISRE);
1270 rtl_write_dword(rtlpriv, REG_HISRE, tmp);
1271}
1272
1273void rtl8723e_enable_interrupt(struct ieee80211_hw *hw)
1185{ 1274{
1186 struct rtl_priv *rtlpriv = rtl_priv(hw); 1275 struct rtl_priv *rtlpriv = rtl_priv(hw);
1187 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1276 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
@@ -1191,37 +1280,39 @@ void rtl8723ae_enable_interrupt(struct ieee80211_hw *hw)
1191 rtlpci->irq_enabled = true; 1280 rtlpci->irq_enabled = true;
1192} 1281}
1193 1282
1194void rtl8723ae_disable_interrupt(struct ieee80211_hw *hw) 1283void rtl8723e_disable_interrupt(struct ieee80211_hw *hw)
1195{ 1284{
1196 struct rtl_priv *rtlpriv = rtl_priv(hw); 1285 struct rtl_priv *rtlpriv = rtl_priv(hw);
1197 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1286 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1198 1287 rtl8723e_clear_interrupt(hw);/*clear it here first*/
1199 rtl_write_dword(rtlpriv, 0x3a8, IMR8190_DISABLED); 1288 rtl_write_dword(rtlpriv, 0x3a8, IMR8190_DISABLED);
1200 rtl_write_dword(rtlpriv, 0x3ac, IMR8190_DISABLED); 1289 rtl_write_dword(rtlpriv, 0x3ac, IMR8190_DISABLED);
1201 rtlpci->irq_enabled = false; 1290 rtlpci->irq_enabled = false;
1202 synchronize_irq(rtlpci->pdev->irq); 1291 /*synchronize_irq(rtlpci->pdev->irq);*/
1203} 1292}
1204 1293
1205static void _rtl8723ae_poweroff_adapter(struct ieee80211_hw *hw) 1294static void _rtl8723e_poweroff_adapter(struct ieee80211_hw *hw)
1206{ 1295{
1207 struct rtl_priv *rtlpriv = rtl_priv(hw); 1296 struct rtl_priv *rtlpriv = rtl_priv(hw);
1208 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1297 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1209 u8 u1tmp; 1298 u8 u1b_tmp;
1210 1299
1211 /* Combo (PCIe + USB) Card and PCIe-MF Card */ 1300 /* Combo (PCIe + USB) Card and PCIe-MF Card */
1212 /* 1. Run LPS WL RFOFF flow */ 1301 /* 1. Run LPS WL RFOFF flow */
1213 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1302 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1214 PWR_INTF_PCI_MSK, Rtl8723_NIC_LPS_ENTER_FLOW); 1303 PWR_INTF_PCI_MSK, Rtl8723_NIC_LPS_ENTER_FLOW);
1215 1304
1216 /* 2. 0x1F[7:0] = 0 */ 1305 /* 2. 0x1F[7:0] = 0 */
1217 /* turn off RF */ 1306 /* turn off RF */
1218 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); 1307 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1219 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready) 1308 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) &&
1309 rtlhal->fw_ready) {
1220 rtl8723ae_firmware_selfreset(hw); 1310 rtl8723ae_firmware_selfreset(hw);
1311 }
1221 1312
1222 /* Reset MCU. Suggested by Filen. */ 1313 /* Reset MCU. Suggested by Filen. */
1223 u1tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1); 1314 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1224 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1tmp & (~BIT(2)))); 1315 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2))));
1225 1316
1226 /* g. MCUFWDL 0x80[1:0]=0 */ 1317 /* g. MCUFWDL 0x80[1:0]=0 */
1227 /* reset MCU ready status */ 1318 /* reset MCU ready status */
@@ -1232,39 +1323,38 @@ static void _rtl8723ae_poweroff_adapter(struct ieee80211_hw *hw)
1232 PWR_INTF_PCI_MSK, Rtl8723_NIC_DISABLE_FLOW); 1323 PWR_INTF_PCI_MSK, Rtl8723_NIC_DISABLE_FLOW);
1233 1324
1234 /* Reset MCU IO Wrapper */ 1325 /* Reset MCU IO Wrapper */
1235 u1tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1); 1326 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1236 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1tmp & (~BIT(0)))); 1327 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1237 u1tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1); 1328 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1238 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1tmp | BIT(0)); 1329 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0));
1239 1330
1240 /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */ 1331 /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1241 /* lock ISO/CLK/Power control register */ 1332 /* lock ISO/CLK/Power control register */
1242 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e); 1333 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1243} 1334}
1244 1335
1245void rtl8723ae_card_disable(struct ieee80211_hw *hw) 1336void rtl8723e_card_disable(struct ieee80211_hw *hw)
1246{ 1337{
1247 struct rtl_priv *rtlpriv = rtl_priv(hw); 1338 struct rtl_priv *rtlpriv = rtl_priv(hw);
1248 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1339 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1249 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1340 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1250 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1251 enum nl80211_iftype opmode; 1341 enum nl80211_iftype opmode;
1252 1342
1253 mac->link_state = MAC80211_NOLINK; 1343 mac->link_state = MAC80211_NOLINK;
1254 opmode = NL80211_IFTYPE_UNSPECIFIED; 1344 opmode = NL80211_IFTYPE_UNSPECIFIED;
1255 _rtl8723ae_set_media_status(hw, opmode); 1345 _rtl8723e_set_media_status(hw, opmode);
1256 if (rtlpci->driver_is_goingto_unload || 1346 if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1257 ppsc->rfoff_reason > RF_CHANGE_BY_PS) 1347 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1258 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1348 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1259 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1349 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1260 _rtl8723ae_poweroff_adapter(hw); 1350 _rtl8723e_poweroff_adapter(hw);
1261 1351
1262 /* after power off we should do iqk again */ 1352 /* after power off we should do iqk again */
1263 rtlpriv->phy.iqk_initialized = false; 1353 rtlpriv->phy.iqk_initialized = false;
1264} 1354}
1265 1355
1266void rtl8723ae_interrupt_recognized(struct ieee80211_hw *hw, 1356void rtl8723e_interrupt_recognized(struct ieee80211_hw *hw,
1267 u32 *p_inta, u32 *p_intb) 1357 u32 *p_inta, u32 *p_intb)
1268{ 1358{
1269 struct rtl_priv *rtlpriv = rtl_priv(hw); 1359 struct rtl_priv *rtlpriv = rtl_priv(hw);
1270 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1360 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
@@ -1273,7 +1363,7 @@ void rtl8723ae_interrupt_recognized(struct ieee80211_hw *hw,
1273 rtl_write_dword(rtlpriv, 0x3a0, *p_inta); 1363 rtl_write_dword(rtlpriv, 0x3a0, *p_inta);
1274} 1364}
1275 1365
1276void rtl8723ae_set_beacon_related_registers(struct ieee80211_hw *hw) 1366void rtl8723e_set_beacon_related_registers(struct ieee80211_hw *hw)
1277{ 1367{
1278 1368
1279 struct rtl_priv *rtlpriv = rtl_priv(hw); 1369 struct rtl_priv *rtlpriv = rtl_priv(hw);
@@ -1282,17 +1372,17 @@ void rtl8723ae_set_beacon_related_registers(struct ieee80211_hw *hw)
1282 1372
1283 bcn_interval = mac->beacon_interval; 1373 bcn_interval = mac->beacon_interval;
1284 atim_window = 2; /*FIX MERGE */ 1374 atim_window = 2; /*FIX MERGE */
1285 rtl8723ae_disable_interrupt(hw); 1375 rtl8723e_disable_interrupt(hw);
1286 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window); 1376 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1287 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1377 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1288 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f); 1378 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1289 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18); 1379 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1290 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18); 1380 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1291 rtl_write_byte(rtlpriv, 0x606, 0x30); 1381 rtl_write_byte(rtlpriv, 0x606, 0x30);
1292 rtl8723ae_enable_interrupt(hw); 1382 rtl8723e_enable_interrupt(hw);
1293} 1383}
1294 1384
1295void rtl8723ae_set_beacon_interval(struct ieee80211_hw *hw) 1385void rtl8723e_set_beacon_interval(struct ieee80211_hw *hw)
1296{ 1386{
1297 struct rtl_priv *rtlpriv = rtl_priv(hw); 1387 struct rtl_priv *rtlpriv = rtl_priv(hw);
1298 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1388 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
@@ -1300,13 +1390,13 @@ void rtl8723ae_set_beacon_interval(struct ieee80211_hw *hw)
1300 1390
1301 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, 1391 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1302 "beacon_interval:%d\n", bcn_interval); 1392 "beacon_interval:%d\n", bcn_interval);
1303 rtl8723ae_disable_interrupt(hw); 1393 rtl8723e_disable_interrupt(hw);
1304 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1394 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1305 rtl8723ae_enable_interrupt(hw); 1395 rtl8723e_enable_interrupt(hw);
1306} 1396}
1307 1397
1308void rtl8723ae_update_interrupt_mask(struct ieee80211_hw *hw, 1398void rtl8723e_update_interrupt_mask(struct ieee80211_hw *hw,
1309 u32 add_msr, u32 rm_msr) 1399 u32 add_msr, u32 rm_msr)
1310{ 1400{
1311 struct rtl_priv *rtlpriv = rtl_priv(hw); 1401 struct rtl_priv *rtlpriv = rtl_priv(hw);
1312 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1402 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
@@ -1318,11 +1408,11 @@ void rtl8723ae_update_interrupt_mask(struct ieee80211_hw *hw,
1318 rtlpci->irq_mask[0] |= add_msr; 1408 rtlpci->irq_mask[0] |= add_msr;
1319 if (rm_msr) 1409 if (rm_msr)
1320 rtlpci->irq_mask[0] &= (~rm_msr); 1410 rtlpci->irq_mask[0] &= (~rm_msr);
1321 rtl8723ae_disable_interrupt(hw); 1411 rtl8723e_disable_interrupt(hw);
1322 rtl8723ae_enable_interrupt(hw); 1412 rtl8723e_enable_interrupt(hw);
1323} 1413}
1324 1414
1325static u8 _rtl8723ae_get_chnl_group(u8 chnl) 1415static u8 _rtl8723e_get_chnl_group(u8 chnl)
1326{ 1416{
1327 u8 group; 1417 u8 group;
1328 1418
@@ -1335,9 +1425,9 @@ static u8 _rtl8723ae_get_chnl_group(u8 chnl)
1335 return group; 1425 return group;
1336} 1426}
1337 1427
1338static void _rtl8723ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw, 1428static void _rtl8723e_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1339 bool autoload_fail, 1429 bool autoload_fail,
1340 u8 *hwinfo) 1430 u8 *hwinfo)
1341{ 1431{
1342 struct rtl_priv *rtlpriv = rtl_priv(hw); 1432 struct rtl_priv *rtlpriv = rtl_priv(hw);
1343 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1433 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
@@ -1347,19 +1437,14 @@ static void _rtl8723ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1347 for (rf_path = 0; rf_path < 1; rf_path++) { 1437 for (rf_path = 0; rf_path < 1; rf_path++) {
1348 for (i = 0; i < 3; i++) { 1438 for (i = 0; i < 3; i++) {
1349 if (!autoload_fail) { 1439 if (!autoload_fail) {
1350 rtlefuse->eeprom_chnlarea_txpwr_cck 1440 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] =
1351 [rf_path][i] =
1352 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i]; 1441 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
1353 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s 1442 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1354 [rf_path][i] = 1443 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 + i];
1355 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path *
1356 3 + i];
1357 } else { 1444 } else {
1358 rtlefuse->eeprom_chnlarea_txpwr_cck 1445 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] =
1359 [rf_path][i] =
1360 EEPROM_DEFAULT_TXPOWERLEVEL; 1446 EEPROM_DEFAULT_TXPOWERLEVEL;
1361 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s 1447 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1362 [rf_path][i] =
1363 EEPROM_DEFAULT_TXPOWERLEVEL; 1448 EEPROM_DEFAULT_TXPOWERLEVEL;
1364 } 1449 }
1365 } 1450 }
@@ -1380,43 +1465,43 @@ static void _rtl8723ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1380 for (i = 0; i < 3; i++) 1465 for (i = 0; i < 3; i++)
1381 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1466 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1382 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path, 1467 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path,
1383 i, rtlefuse->eeprom_chnlarea_txpwr_cck 1468 i, rtlefuse->eeprom_chnlarea_txpwr_cck
1384 [rf_path][i]); 1469 [rf_path][i]);
1385 for (rf_path = 0; rf_path < 2; rf_path++) 1470 for (rf_path = 0; rf_path < 2; rf_path++)
1386 for (i = 0; i < 3; i++) 1471 for (i = 0; i < 3; i++)
1387 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1472 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1388 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n", 1473 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1389 rf_path, i, 1474 rf_path, i,
1390 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s 1475 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1391 [rf_path][i]); 1476 [rf_path][i]);
1392 for (rf_path = 0; rf_path < 2; rf_path++) 1477 for (rf_path = 0; rf_path < 2; rf_path++)
1393 for (i = 0; i < 3; i++) 1478 for (i = 0; i < 3; i++)
1394 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1479 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1395 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n", 1480 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1396 rf_path, i, 1481 rf_path, i,
1397 rtlefuse->eprom_chnl_txpwr_ht40_2sdf 1482 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1398 [rf_path][i]); 1483 [rf_path][i]);
1399 1484
1400 for (rf_path = 0; rf_path < 2; rf_path++) { 1485 for (rf_path = 0; rf_path < 2; rf_path++) {
1401 for (i = 0; i < 14; i++) { 1486 for (i = 0; i < 14; i++) {
1402 index = _rtl8723ae_get_chnl_group((u8) i); 1487 index = _rtl8723e_get_chnl_group((u8)i);
1403 1488
1404 rtlefuse->txpwrlevel_cck[rf_path][i] = 1489 rtlefuse->txpwrlevel_cck[rf_path][i] =
1405 rtlefuse->eeprom_chnlarea_txpwr_cck 1490 rtlefuse->eeprom_chnlarea_txpwr_cck
1406 [rf_path][index]; 1491 [rf_path][index];
1407 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 1492 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1408 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s 1493 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1409 [rf_path][index]; 1494 [rf_path][index];
1410 1495
1411 if ((rtlefuse->eeprom_chnlarea_txpwr_ht40_1s 1496 if ((rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1412 [rf_path][index] -
1413 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[rf_path]
1414 [index]) > 0) {
1415 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1416 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1417 [rf_path][index] - 1497 [rf_path][index] -
1418 rtlefuse->eprom_chnl_txpwr_ht40_2sdf 1498 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1419 [rf_path][index]; 1499 [rf_path][index]) > 0) {
1500 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1501 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1502 [rf_path][index] -
1503 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1504 [rf_path][index];
1420 } else { 1505 } else {
1421 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0; 1506 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
1422 } 1507 }
@@ -1424,8 +1509,8 @@ static void _rtl8723ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1424 1509
1425 for (i = 0; i < 14; i++) { 1510 for (i = 0; i < 14; i++) {
1426 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1511 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1427 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = " 1512 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1428 "[0x%x / 0x%x / 0x%x]\n", rf_path, i, 1513 rf_path, i,
1429 rtlefuse->txpwrlevel_cck[rf_path][i], 1514 rtlefuse->txpwrlevel_cck[rf_path][i],
1430 rtlefuse->txpwrlevel_ht40_1s[rf_path][i], 1515 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1431 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]); 1516 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
@@ -1446,22 +1531,20 @@ static void _rtl8723ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1446 1531
1447 for (rf_path = 0; rf_path < 2; rf_path++) { 1532 for (rf_path = 0; rf_path < 2; rf_path++) {
1448 for (i = 0; i < 14; i++) { 1533 for (i = 0; i < 14; i++) {
1449 index = _rtl8723ae_get_chnl_group((u8) i); 1534 index = _rtl8723e_get_chnl_group((u8)i);
1450 1535
1451 if (rf_path == RF90_PATH_A) { 1536 if (rf_path == RF90_PATH_A) {
1452 rtlefuse->pwrgroup_ht20[rf_path][i] = 1537 rtlefuse->pwrgroup_ht20[rf_path][i] =
1453 (rtlefuse->eeprom_pwrlimit_ht20[index] & 1538 (rtlefuse->eeprom_pwrlimit_ht20[index] & 0xf);
1454 0xf);
1455 rtlefuse->pwrgroup_ht40[rf_path][i] = 1539 rtlefuse->pwrgroup_ht40[rf_path][i] =
1456 (rtlefuse->eeprom_pwrlimit_ht40[index] & 1540 (rtlefuse->eeprom_pwrlimit_ht40[index] & 0xf);
1457 0xf);
1458 } else if (rf_path == RF90_PATH_B) { 1541 } else if (rf_path == RF90_PATH_B) {
1459 rtlefuse->pwrgroup_ht20[rf_path][i] = 1542 rtlefuse->pwrgroup_ht20[rf_path][i] =
1460 ((rtlefuse->eeprom_pwrlimit_ht20[index] & 1543 ((rtlefuse->eeprom_pwrlimit_ht20[index] &
1461 0xf0) >> 4); 1544 0xf0) >> 4);
1462 rtlefuse->pwrgroup_ht40[rf_path][i] = 1545 rtlefuse->pwrgroup_ht40[rf_path][i] =
1463 ((rtlefuse->eeprom_pwrlimit_ht40[index] & 1546 ((rtlefuse->eeprom_pwrlimit_ht40[index] &
1464 0xf0) >> 4); 1547 0xf0) >> 4);
1465 } 1548 }
1466 1549
1467 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1550 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
@@ -1474,7 +1557,7 @@ static void _rtl8723ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1474 } 1557 }
1475 1558
1476 for (i = 0; i < 14; i++) { 1559 for (i = 0; i < 14; i++) {
1477 index = _rtl8723ae_get_chnl_group((u8) i); 1560 index = _rtl8723e_get_chnl_group((u8)i);
1478 1561
1479 if (!autoload_fail) 1562 if (!autoload_fail)
1480 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index]; 1563 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
@@ -1491,7 +1574,7 @@ static void _rtl8723ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1491 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3)) 1574 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
1492 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0; 1575 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
1493 1576
1494 index = _rtl8723ae_get_chnl_group((u8) i); 1577 index = _rtl8723e_get_chnl_group((u8)i);
1495 1578
1496 if (!autoload_fail) 1579 if (!autoload_fail)
1497 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index]; 1580 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
@@ -1509,19 +1592,19 @@ static void _rtl8723ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1509 for (i = 0; i < 14; i++) 1592 for (i = 0; i < 14; i++)
1510 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1593 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1511 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i, 1594 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1512 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]); 1595 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
1513 for (i = 0; i < 14; i++) 1596 for (i = 0; i < 14; i++)
1514 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1597 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1515 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i, 1598 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i,
1516 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]); 1599 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
1517 for (i = 0; i < 14; i++) 1600 for (i = 0; i < 14; i++)
1518 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1601 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1519 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i, 1602 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1520 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]); 1603 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
1521 for (i = 0; i < 14; i++) 1604 for (i = 0; i < 14; i++)
1522 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1605 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1523 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i, 1606 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i,
1524 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]); 1607 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
1525 1608
1526 if (!autoload_fail) 1609 if (!autoload_fail)
1527 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7); 1610 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
@@ -1534,10 +1617,11 @@ static void _rtl8723ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1534 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A]; 1617 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
1535 else 1618 else
1536 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI; 1619 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
1620
1537 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1621 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1538 "TSSI_A = 0x%x, TSSI_B = 0x%x\n", 1622 "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1539 rtlefuse->eeprom_tssi[RF90_PATH_A], 1623 rtlefuse->eeprom_tssi[RF90_PATH_A],
1540 rtlefuse->eeprom_tssi[RF90_PATH_B]); 1624 rtlefuse->eeprom_tssi[RF90_PATH_B]);
1541 1625
1542 if (!autoload_fail) 1626 if (!autoload_fail)
1543 tempval = hwinfo[EEPROM_THERMAL_METER]; 1627 tempval = hwinfo[EEPROM_THERMAL_METER];
@@ -1553,8 +1637,8 @@ static void _rtl8723ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1553 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); 1637 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1554} 1638}
1555 1639
1556static void _rtl8723ae_read_adapter_info(struct ieee80211_hw *hw, 1640static void _rtl8723e_read_adapter_info(struct ieee80211_hw *hw,
1557 bool pseudo_test) 1641 bool b_pseudo_test)
1558{ 1642{
1559 struct rtl_priv *rtlpriv = rtl_priv(hw); 1643 struct rtl_priv *rtlpriv = rtl_priv(hw);
1560 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1644 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
@@ -1563,7 +1647,7 @@ static void _rtl8723ae_read_adapter_info(struct ieee80211_hw *hw,
1563 u8 hwinfo[HWSET_MAX_SIZE]; 1647 u8 hwinfo[HWSET_MAX_SIZE];
1564 u16 eeprom_id; 1648 u16 eeprom_id;
1565 1649
1566 if (pseudo_test) { 1650 if (b_pseudo_test) {
1567 /* need add */ 1651 /* need add */
1568 return; 1652 return;
1569 } 1653 }
@@ -1577,7 +1661,7 @@ static void _rtl8723ae_read_adapter_info(struct ieee80211_hw *hw,
1577 "RTL819X Not boot from eeprom, check it !!"); 1661 "RTL819X Not boot from eeprom, check it !!");
1578 } 1662 }
1579 1663
1580 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, ("MAP\n"), 1664 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP\n",
1581 hwinfo, HWSET_MAX_SIZE); 1665 hwinfo, HWSET_MAX_SIZE);
1582 1666
1583 eeprom_id = *((u16 *)&hwinfo[0]); 1667 eeprom_id = *((u16 *)&hwinfo[0]);
@@ -1590,13 +1674,13 @@ static void _rtl8723ae_read_adapter_info(struct ieee80211_hw *hw,
1590 rtlefuse->autoload_failflag = false; 1674 rtlefuse->autoload_failflag = false;
1591 } 1675 }
1592 1676
1593 if (rtlefuse->autoload_failflag == true) 1677 if (rtlefuse->autoload_failflag)
1594 return; 1678 return;
1595 1679
1596 rtlefuse->eeprom_vid = *(u16 *) &hwinfo[EEPROM_VID]; 1680 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
1597 rtlefuse->eeprom_did = *(u16 *) &hwinfo[EEPROM_DID]; 1681 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
1598 rtlefuse->eeprom_svid = *(u16 *) &hwinfo[EEPROM_SVID]; 1682 rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
1599 rtlefuse->eeprom_smid = *(u16 *) &hwinfo[EEPROM_SMID]; 1683 rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
1600 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1684 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1601 "EEPROMId = 0x%4x\n", eeprom_id); 1685 "EEPROMId = 0x%4x\n", eeprom_id);
1602 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1686 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
@@ -1610,16 +1694,16 @@ static void _rtl8723ae_read_adapter_info(struct ieee80211_hw *hw,
1610 1694
1611 for (i = 0; i < 6; i += 2) { 1695 for (i = 0; i < 6; i += 2) {
1612 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i]; 1696 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1613 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue; 1697 *((u16 *)(&rtlefuse->dev_addr[i])) = usvalue;
1614 } 1698 }
1615 1699
1616 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1700 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1617 "dev_addr: %pM\n", rtlefuse->dev_addr); 1701 "dev_addr: %pM\n", rtlefuse->dev_addr);
1618 1702
1619 _rtl8723ae_read_txpower_info_from_hwpg(hw, 1703 _rtl8723e_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
1620 rtlefuse->autoload_failflag, hwinfo); 1704 hwinfo);
1621 1705
1622 rtl8723ae_read_bt_coexist_info_from_hwpg(hw, 1706 rtl8723e_read_bt_coexist_info_from_hwpg(hw,
1623 rtlefuse->autoload_failflag, hwinfo); 1707 rtlefuse->autoload_failflag, hwinfo);
1624 1708
1625 rtlefuse->eeprom_channelplan = hwinfo[EEPROM_CHANNELPLAN]; 1709 rtlefuse->eeprom_channelplan = hwinfo[EEPROM_CHANNELPLAN];
@@ -1645,6 +1729,14 @@ static void _rtl8723ae_read_adapter_info(struct ieee80211_hw *hw,
1645 CHK_SVID_SMID(0x10EC, 0x6178) || 1729 CHK_SVID_SMID(0x10EC, 0x6178) ||
1646 CHK_SVID_SMID(0x10EC, 0x6179) || 1730 CHK_SVID_SMID(0x10EC, 0x6179) ||
1647 CHK_SVID_SMID(0x10EC, 0x6180) || 1731 CHK_SVID_SMID(0x10EC, 0x6180) ||
1732 CHK_SVID_SMID(0x10EC, 0x7151) ||
1733 CHK_SVID_SMID(0x10EC, 0x7152) ||
1734 CHK_SVID_SMID(0x10EC, 0x7154) ||
1735 CHK_SVID_SMID(0x10EC, 0x7155) ||
1736 CHK_SVID_SMID(0x10EC, 0x7177) ||
1737 CHK_SVID_SMID(0x10EC, 0x7178) ||
1738 CHK_SVID_SMID(0x10EC, 0x7179) ||
1739 CHK_SVID_SMID(0x10EC, 0x7180) ||
1648 CHK_SVID_SMID(0x10EC, 0x8151) || 1740 CHK_SVID_SMID(0x10EC, 0x8151) ||
1649 CHK_SVID_SMID(0x10EC, 0x8152) || 1741 CHK_SVID_SMID(0x10EC, 0x8152) ||
1650 CHK_SVID_SMID(0x10EC, 0x8154) || 1742 CHK_SVID_SMID(0x10EC, 0x8154) ||
@@ -1672,7 +1764,10 @@ static void _rtl8723ae_read_adapter_info(struct ieee80211_hw *hw,
1672 CHK_SVID_SMID(0x10EC, 0x7193) || 1764 CHK_SVID_SMID(0x10EC, 0x7193) ||
1673 CHK_SVID_SMID(0x10EC, 0x8191) || 1765 CHK_SVID_SMID(0x10EC, 0x8191) ||
1674 CHK_SVID_SMID(0x10EC, 0x8192) || 1766 CHK_SVID_SMID(0x10EC, 0x8192) ||
1675 CHK_SVID_SMID(0x10EC, 0x8193)) 1767 CHK_SVID_SMID(0x10EC, 0x8193) ||
1768 CHK_SVID_SMID(0x10EC, 0x9191) ||
1769 CHK_SVID_SMID(0x10EC, 0x9192) ||
1770 CHK_SVID_SMID(0x10EC, 0x9193))
1676 rtlhal->oem_id = RT_CID_819X_SAMSUNG; 1771 rtlhal->oem_id = RT_CID_819X_SAMSUNG;
1677 else if (CHK_SVID_SMID(0x10EC, 0x8195) || 1772 else if (CHK_SVID_SMID(0x10EC, 0x8195) ||
1678 CHK_SVID_SMID(0x10EC, 0x9195) || 1773 CHK_SVID_SMID(0x10EC, 0x9195) ||
@@ -1729,7 +1824,7 @@ static void _rtl8723ae_read_adapter_info(struct ieee80211_hw *hw,
1729 else 1824 else
1730 rtlhal->oem_id = RT_CID_DEFAULT; 1825 rtlhal->oem_id = RT_CID_DEFAULT;
1731 } else { 1826 } else {
1732 rtlhal->oem_id = RT_CID_DEFAULT; 1827 rtlhal->oem_id = RT_CID_DEFAULT;
1733 } 1828 }
1734 break; 1829 break;
1735 case EEPROM_CID_TOSHIBA: 1830 case EEPROM_CID_TOSHIBA:
@@ -1751,18 +1846,31 @@ static void _rtl8723ae_read_adapter_info(struct ieee80211_hw *hw,
1751 } 1846 }
1752} 1847}
1753 1848
1754static void _rtl8723ae_hal_customized_behavior(struct ieee80211_hw *hw) 1849static void _rtl8723e_hal_customized_behavior(struct ieee80211_hw *hw)
1755{ 1850{
1756 struct rtl_priv *rtlpriv = rtl_priv(hw); 1851 struct rtl_priv *rtlpriv = rtl_priv(hw);
1757 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1852 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1758 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1853 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1759 1854
1760 pcipriv->ledctl.led_opendrain = true; 1855 pcipriv->ledctl.led_opendrain = true;
1856 switch (rtlhal->oem_id) {
1857 case RT_CID_819X_HP:
1858 pcipriv->ledctl.led_opendrain = true;
1859 break;
1860 case RT_CID_819X_LENOVO:
1861 case RT_CID_DEFAULT:
1862 case RT_CID_TOSHIBA:
1863 case RT_CID_CCX:
1864 case RT_CID_819X_ACER:
1865 case RT_CID_WHQL:
1866 default:
1867 break;
1868 }
1761 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1869 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1762 "RT Customized ID: 0x%02X\n", rtlhal->oem_id); 1870 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
1763} 1871}
1764 1872
1765void rtl8723ae_read_eeprom_info(struct ieee80211_hw *hw) 1873void rtl8723e_read_eeprom_info(struct ieee80211_hw *hw)
1766{ 1874{
1767 struct rtl_priv *rtlpriv = rtl_priv(hw); 1875 struct rtl_priv *rtlpriv = rtl_priv(hw);
1768 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1876 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
@@ -1775,7 +1883,7 @@ void rtl8723ae_read_eeprom_info(struct ieee80211_hw *hw)
1775 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0); 1883 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
1776 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST], value32); 1884 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST], value32);
1777 1885
1778 rtlhal->version = _rtl8723ae_read_chip_version(hw); 1886 rtlhal->version = _rtl8723e_read_chip_version(hw);
1779 1887
1780 if (get_rf_type(rtlphy) == RF_1T1R) 1888 if (get_rf_type(rtlphy) == RF_1T1R)
1781 rtlpriv->dm.rfpath_rxenable[0] = true; 1889 rtlpriv->dm.rfpath_rxenable[0] = true;
@@ -1783,7 +1891,7 @@ void rtl8723ae_read_eeprom_info(struct ieee80211_hw *hw)
1783 rtlpriv->dm.rfpath_rxenable[0] = 1891 rtlpriv->dm.rfpath_rxenable[0] =
1784 rtlpriv->dm.rfpath_rxenable[1] = true; 1892 rtlpriv->dm.rfpath_rxenable[1] = true;
1785 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n", 1893 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
1786 rtlhal->version); 1894 rtlhal->version);
1787 1895
1788 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); 1896 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1789 if (tmp_u1b & BIT(4)) { 1897 if (tmp_u1b & BIT(4)) {
@@ -1796,33 +1904,34 @@ void rtl8723ae_read_eeprom_info(struct ieee80211_hw *hw)
1796 if (tmp_u1b & BIT(5)) { 1904 if (tmp_u1b & BIT(5)) {
1797 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); 1905 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1798 rtlefuse->autoload_failflag = false; 1906 rtlefuse->autoload_failflag = false;
1799 _rtl8723ae_read_adapter_info(hw, false); 1907 _rtl8723e_read_adapter_info(hw, false);
1800 } else { 1908 } else {
1801 rtlefuse->autoload_failflag = true; 1909 rtlefuse->autoload_failflag = true;
1802 _rtl8723ae_read_adapter_info(hw, false); 1910 _rtl8723e_read_adapter_info(hw, false);
1803 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n"); 1911 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
1804 } 1912 }
1805 _rtl8723ae_hal_customized_behavior(hw); 1913 _rtl8723e_hal_customized_behavior(hw);
1806} 1914}
1807 1915
1808static void rtl8723ae_update_hal_rate_table(struct ieee80211_hw *hw, 1916static void rtl8723e_update_hal_rate_table(struct ieee80211_hw *hw,
1809 struct ieee80211_sta *sta) 1917 struct ieee80211_sta *sta)
1810{ 1918{
1811 struct rtl_priv *rtlpriv = rtl_priv(hw); 1919 struct rtl_priv *rtlpriv = rtl_priv(hw);
1812 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1813 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1920 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1814 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1921 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1815 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1922 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1816 u32 ratr_value; 1923 u32 ratr_value;
1817 u8 ratr_index = 0; 1924 u8 ratr_index = 0;
1818 u8 nmode = mac->ht_enable; 1925 u8 b_nmode = mac->ht_enable;
1819 u8 mimo_ps = IEEE80211_SMPS_OFF; 1926 u16 shortgi_rate;
1927 u32 tmp_ratr_value;
1820 u8 curtxbw_40mhz = mac->bw_40; 1928 u8 curtxbw_40mhz = mac->bw_40;
1821 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 1929 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1822 1 : 0; 1930 1 : 0;
1823 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 1931 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1824 1 : 0; 1932 1 : 0;
1825 enum wireless_mode wirelessmode = mac->mode; 1933 enum wireless_mode wirelessmode = mac->mode;
1934 u32 ratr_mask;
1826 1935
1827 if (rtlhal->current_bandtype == BAND_ON_5G) 1936 if (rtlhal->current_bandtype == BAND_ON_5G)
1828 ratr_value = sta->supp_rates[1] << 4; 1937 ratr_value = sta->supp_rates[1] << 4;
@@ -1831,7 +1940,7 @@ static void rtl8723ae_update_hal_rate_table(struct ieee80211_hw *hw,
1831 if (mac->opmode == NL80211_IFTYPE_ADHOC) 1940 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1832 ratr_value = 0xfff; 1941 ratr_value = 0xfff;
1833 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 1942 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1834 sta->ht_cap.mcs.rx_mask[0] << 12); 1943 sta->ht_cap.mcs.rx_mask[0] << 12);
1835 switch (wirelessmode) { 1944 switch (wirelessmode) {
1836 case WIRELESS_MODE_B: 1945 case WIRELESS_MODE_B:
1837 if (ratr_value & 0x0000000c) 1946 if (ratr_value & 0x0000000c)
@@ -1844,20 +1953,14 @@ static void rtl8723ae_update_hal_rate_table(struct ieee80211_hw *hw,
1844 break; 1953 break;
1845 case WIRELESS_MODE_N_24G: 1954 case WIRELESS_MODE_N_24G:
1846 case WIRELESS_MODE_N_5G: 1955 case WIRELESS_MODE_N_5G:
1847 nmode = 1; 1956 b_nmode = 1;
1848 if (mimo_ps == IEEE80211_SMPS_STATIC) { 1957 if (get_rf_type(rtlphy) == RF_1T2R ||
1849 ratr_value &= 0x0007F005; 1958 get_rf_type(rtlphy) == RF_1T1R)
1850 } else { 1959 ratr_mask = 0x000ff005;
1851 u32 ratr_mask; 1960 else
1852 1961 ratr_mask = 0x0f0ff005;
1853 if (get_rf_type(rtlphy) == RF_1T2R ||
1854 get_rf_type(rtlphy) == RF_1T1R)
1855 ratr_mask = 0x000ff005;
1856 else
1857 ratr_mask = 0x0f0ff005;
1858 1962
1859 ratr_value &= ratr_mask; 1963 ratr_value &= ratr_mask;
1860 }
1861 break; 1964 break;
1862 default: 1965 default:
1863 if (rtlphy->rf_type == RF_1T2R) 1966 if (rtlphy->rf_type == RF_1T2R)
@@ -1868,19 +1971,30 @@ static void rtl8723ae_update_hal_rate_table(struct ieee80211_hw *hw,
1868 break; 1971 break;
1869 } 1972 }
1870 1973
1871 if ((pcipriv->bt_coexist.bt_coexistence) && 1974 if ((rtlpriv->btcoexist.bt_coexistence) &&
1872 (pcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) && 1975 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
1873 (pcipriv->bt_coexist.bt_cur_state) && 1976 (rtlpriv->btcoexist.bt_cur_state) &&
1874 (pcipriv->bt_coexist.bt_ant_isolation) && 1977 (rtlpriv->btcoexist.bt_ant_isolation) &&
1875 ((pcipriv->bt_coexist.bt_service == BT_SCO) || 1978 ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
1876 (pcipriv->bt_coexist.bt_service == BT_BUSY))) 1979 (rtlpriv->btcoexist.bt_service == BT_BUSY)))
1877 ratr_value &= 0x0fffcfc0; 1980 ratr_value &= 0x0fffcfc0;
1878 else 1981 else
1879 ratr_value &= 0x0FFFFFFF; 1982 ratr_value &= 0x0FFFFFFF;
1880 1983
1881 if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) || 1984 if (b_nmode &&
1882 (!curtxbw_40mhz && curshortgi_20mhz))) 1985 ((curtxbw_40mhz && curshortgi_40mhz) ||
1986 (!curtxbw_40mhz && curshortgi_20mhz))) {
1883 ratr_value |= 0x10000000; 1987 ratr_value |= 0x10000000;
1988 tmp_ratr_value = (ratr_value >> 12);
1989
1990 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1991 if ((1 << shortgi_rate) & tmp_ratr_value)
1992 break;
1993 }
1994
1995 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1996 (shortgi_rate << 4) | (shortgi_rate);
1997 }
1884 1998
1885 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value); 1999 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1886 2000
@@ -1888,8 +2002,9 @@ static void rtl8723ae_update_hal_rate_table(struct ieee80211_hw *hw,
1888 "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0)); 2002 "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
1889} 2003}
1890 2004
1891static void rtl8723ae_update_hal_rate_mask(struct ieee80211_hw *hw, 2005static void rtl8723e_update_hal_rate_mask(struct ieee80211_hw *hw,
1892 struct ieee80211_sta *sta, u8 rssi_level) 2006 struct ieee80211_sta *sta,
2007 u8 rssi_level)
1893{ 2008{
1894 struct rtl_priv *rtlpriv = rtl_priv(hw); 2009 struct rtl_priv *rtlpriv = rtl_priv(hw);
1895 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2010 struct rtl_phy *rtlphy = &(rtlpriv->phy);
@@ -1898,7 +2013,8 @@ static void rtl8723ae_update_hal_rate_mask(struct ieee80211_hw *hw,
1898 struct rtl_sta_info *sta_entry = NULL; 2013 struct rtl_sta_info *sta_entry = NULL;
1899 u32 ratr_bitmap; 2014 u32 ratr_bitmap;
1900 u8 ratr_index; 2015 u8 ratr_index;
1901 u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0; 2016 u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
2017 ? 1 : 0;
1902 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 2018 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1903 1 : 0; 2019 1 : 0;
1904 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 2020 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
@@ -1907,9 +2023,9 @@ static void rtl8723ae_update_hal_rate_mask(struct ieee80211_hw *hw,
1907 bool shortgi = false; 2023 bool shortgi = false;
1908 u8 rate_mask[5]; 2024 u8 rate_mask[5];
1909 u8 macid = 0; 2025 u8 macid = 0;
1910 u8 mimo_ps = IEEE80211_SMPS_OFF; 2026 /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/
1911 2027
1912 sta_entry = (struct rtl_sta_info *) sta->drv_priv; 2028 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1913 wirelessmode = sta_entry->wireless_mode; 2029 wirelessmode = sta_entry->wireless_mode;
1914 if (mac->opmode == NL80211_IFTYPE_STATION) 2030 if (mac->opmode == NL80211_IFTYPE_STATION)
1915 curtxbw_40mhz = mac->bw_40; 2031 curtxbw_40mhz = mac->bw_40;
@@ -1944,54 +2060,44 @@ static void rtl8723ae_update_hal_rate_mask(struct ieee80211_hw *hw,
1944 ratr_bitmap &= 0x00000ff5; 2060 ratr_bitmap &= 0x00000ff5;
1945 break; 2061 break;
1946 case WIRELESS_MODE_A: 2062 case WIRELESS_MODE_A:
1947 ratr_index = RATR_INX_WIRELESS_A; 2063 ratr_index = RATR_INX_WIRELESS_G;
1948 ratr_bitmap &= 0x00000ff0; 2064 ratr_bitmap &= 0x00000ff0;
1949 break; 2065 break;
1950 case WIRELESS_MODE_N_24G: 2066 case WIRELESS_MODE_N_24G:
1951 case WIRELESS_MODE_N_5G: 2067 case WIRELESS_MODE_N_5G:
1952 ratr_index = RATR_INX_WIRELESS_NGB; 2068 ratr_index = RATR_INX_WIRELESS_NGB;
1953 2069 if (rtlphy->rf_type == RF_1T2R ||
1954 if (mimo_ps == IEEE80211_SMPS_STATIC) { 2070 rtlphy->rf_type == RF_1T1R) {
1955 if (rssi_level == 1) 2071 if (curtxbw_40mhz) {
1956 ratr_bitmap &= 0x00070000; 2072 if (rssi_level == 1)
1957 else if (rssi_level == 2) 2073 ratr_bitmap &= 0x000f0000;
1958 ratr_bitmap &= 0x0007f000; 2074 else if (rssi_level == 2)
1959 else 2075 ratr_bitmap &= 0x000ff000;
1960 ratr_bitmap &= 0x0007f005; 2076 else
2077 ratr_bitmap &= 0x000ff015;
2078 } else {
2079 if (rssi_level == 1)
2080 ratr_bitmap &= 0x000f0000;
2081 else if (rssi_level == 2)
2082 ratr_bitmap &= 0x000ff000;
2083 else
2084 ratr_bitmap &= 0x000ff005;
2085 }
1961 } else { 2086 } else {
1962 if (rtlphy->rf_type == RF_1T2R || 2087 if (curtxbw_40mhz) {
1963 rtlphy->rf_type == RF_1T1R) { 2088 if (rssi_level == 1)
1964 if (curtxbw_40mhz) { 2089 ratr_bitmap &= 0x0f0f0000;
1965 if (rssi_level == 1) 2090 else if (rssi_level == 2)
1966 ratr_bitmap &= 0x000f0000; 2091 ratr_bitmap &= 0x0f0ff000;
1967 else if (rssi_level == 2) 2092 else
1968 ratr_bitmap &= 0x000ff000; 2093 ratr_bitmap &= 0x0f0ff015;
1969 else
1970 ratr_bitmap &= 0x000ff015;
1971 } else {
1972 if (rssi_level == 1)
1973 ratr_bitmap &= 0x000f0000;
1974 else if (rssi_level == 2)
1975 ratr_bitmap &= 0x000ff000;
1976 else
1977 ratr_bitmap &= 0x000ff005;
1978 }
1979 } else { 2094 } else {
1980 if (curtxbw_40mhz) { 2095 if (rssi_level == 1)
1981 if (rssi_level == 1) 2096 ratr_bitmap &= 0x0f0f0000;
1982 ratr_bitmap &= 0x0f0f0000; 2097 else if (rssi_level == 2)
1983 else if (rssi_level == 2) 2098 ratr_bitmap &= 0x0f0ff000;
1984 ratr_bitmap &= 0x0f0ff000; 2099 else
1985 else 2100 ratr_bitmap &= 0x0f0ff005;
1986 ratr_bitmap &= 0x0f0ff015;
1987 } else {
1988 if (rssi_level == 1)
1989 ratr_bitmap &= 0x0f0f0000;
1990 else if (rssi_level == 2)
1991 ratr_bitmap &= 0x0f0ff000;
1992 else
1993 ratr_bitmap &= 0x0f0ff005;
1994 }
1995 } 2101 }
1996 } 2102 }
1997 2103
@@ -2016,30 +2122,30 @@ static void rtl8723ae_update_hal_rate_mask(struct ieee80211_hw *hw,
2016 2122
2017 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 2123 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2018 "ratr_bitmap :%x\n", ratr_bitmap); 2124 "ratr_bitmap :%x\n", ratr_bitmap);
2019 /* convert ratr_bitmap to le byte array */ 2125 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2020 rate_mask[0] = ratr_bitmap; 2126 (ratr_index << 28);
2021 rate_mask[1] = (ratr_bitmap >>= 8);
2022 rate_mask[2] = (ratr_bitmap >>= 8);
2023 rate_mask[3] = ((ratr_bitmap >> 8) & 0x0f) | (ratr_index << 4);
2024 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80; 2127 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2025 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 2128 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2026 "Rate_index:%x, ratr_bitmap: %*phC\n", 2129 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x\n",
2027 ratr_index, 5, rate_mask); 2130 ratr_index, ratr_bitmap,
2028 rtl8723ae_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask); 2131 rate_mask[0], rate_mask[1],
2132 rate_mask[2], rate_mask[3],
2133 rate_mask[4]);
2134 rtl8723e_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
2029} 2135}
2030 2136
2031void rtl8723ae_update_hal_rate_tbl(struct ieee80211_hw *hw, 2137void rtl8723e_update_hal_rate_tbl(struct ieee80211_hw *hw,
2032 struct ieee80211_sta *sta, u8 rssi_level) 2138 struct ieee80211_sta *sta, u8 rssi_level)
2033{ 2139{
2034 struct rtl_priv *rtlpriv = rtl_priv(hw); 2140 struct rtl_priv *rtlpriv = rtl_priv(hw);
2035 2141
2036 if (rtlpriv->dm.useramask) 2142 if (rtlpriv->dm.useramask)
2037 rtl8723ae_update_hal_rate_mask(hw, sta, rssi_level); 2143 rtl8723e_update_hal_rate_mask(hw, sta, rssi_level);
2038 else 2144 else
2039 rtl8723ae_update_hal_rate_table(hw, sta); 2145 rtl8723e_update_hal_rate_table(hw, sta);
2040} 2146}
2041 2147
2042void rtl8723ae_update_channel_access_setting(struct ieee80211_hw *hw) 2148void rtl8723e_update_channel_access_setting(struct ieee80211_hw *hw)
2043{ 2149{
2044 struct rtl_priv *rtlpriv = rtl_priv(hw); 2150 struct rtl_priv *rtlpriv = rtl_priv(hw);
2045 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2151 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
@@ -2053,14 +2159,14 @@ void rtl8723ae_update_channel_access_setting(struct ieee80211_hw *hw)
2053 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); 2159 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2054} 2160}
2055 2161
2056bool rtl8723ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) 2162bool rtl8723e_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2057{ 2163{
2058 struct rtl_priv *rtlpriv = rtl_priv(hw); 2164 struct rtl_priv *rtlpriv = rtl_priv(hw);
2059 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 2165 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2060 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2166 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2061 enum rf_pwrstate e_rfpowerstate_toset; 2167 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2062 u8 u1tmp; 2168 u8 u1tmp;
2063 bool actuallyset = false; 2169 bool b_actuallyset = false;
2064 2170
2065 if (rtlpriv->rtlhal.being_init_adapter) 2171 if (rtlpriv->rtlhal.being_init_adapter)
2066 return false; 2172 return false;
@@ -2077,6 +2183,8 @@ bool rtl8723ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2077 spin_unlock(&rtlpriv->locks.rf_ps_lock); 2183 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2078 } 2184 }
2079 2185
2186 cur_rfstate = ppsc->rfpwr_state;
2187
2080 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2, 2188 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
2081 rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL_2)&~(BIT(1))); 2189 rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL_2)&~(BIT(1)));
2082 2190
@@ -2087,24 +2195,23 @@ bool rtl8723ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2087 else 2195 else
2088 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF; 2196 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
2089 2197
2090 if ((ppsc->hwradiooff == true) && (e_rfpowerstate_toset == ERFON)) { 2198 if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) {
2091 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 2199 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2092 "GPIOChangeRF - HW Radio ON, RF ON\n"); 2200 "GPIOChangeRF - HW Radio ON, RF ON\n");
2093 2201
2094 e_rfpowerstate_toset = ERFON; 2202 e_rfpowerstate_toset = ERFON;
2095 ppsc->hwradiooff = false; 2203 ppsc->hwradiooff = false;
2096 actuallyset = true; 2204 b_actuallyset = true;
2097 } else if ((ppsc->hwradiooff == false) 2205 } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
2098 && (e_rfpowerstate_toset == ERFOFF)) {
2099 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 2206 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2100 "GPIOChangeRF - HW Radio OFF, RF OFF\n"); 2207 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
2101 2208
2102 e_rfpowerstate_toset = ERFOFF; 2209 e_rfpowerstate_toset = ERFOFF;
2103 ppsc->hwradiooff = true; 2210 ppsc->hwradiooff = true;
2104 actuallyset = true; 2211 b_actuallyset = true;
2105 } 2212 }
2106 2213
2107 if (actuallyset) { 2214 if (b_actuallyset) {
2108 spin_lock(&rtlpriv->locks.rf_ps_lock); 2215 spin_lock(&rtlpriv->locks.rf_ps_lock);
2109 ppsc->rfchange_inprogress = false; 2216 ppsc->rfchange_inprogress = false;
2110 spin_unlock(&rtlpriv->locks.rf_ps_lock); 2217 spin_unlock(&rtlpriv->locks.rf_ps_lock);
@@ -2119,11 +2226,12 @@ bool rtl8723ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2119 2226
2120 *valid = 1; 2227 *valid = 1;
2121 return !ppsc->hwradiooff; 2228 return !ppsc->hwradiooff;
2229
2122} 2230}
2123 2231
2124void rtl8723ae_set_key(struct ieee80211_hw *hw, u32 key_index, 2232void rtl8723e_set_key(struct ieee80211_hw *hw, u32 key_index,
2125 u8 *p_macaddr, bool is_group, u8 enc_algo, 2233 u8 *p_macaddr, bool is_group, u8 enc_algo,
2126 bool is_wepkey, bool clear_all) 2234 bool is_wepkey, bool clear_all)
2127{ 2235{
2128 struct rtl_priv *rtlpriv = rtl_priv(hw); 2236 struct rtl_priv *rtlpriv = rtl_priv(hw);
2129 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2237 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
@@ -2131,6 +2239,7 @@ void rtl8723ae_set_key(struct ieee80211_hw *hw, u32 key_index,
2131 u8 *macaddr = p_macaddr; 2239 u8 *macaddr = p_macaddr;
2132 u32 entry_id = 0; 2240 u32 entry_id = 0;
2133 bool is_pairwise = false; 2241 bool is_pairwise = false;
2242
2134 static u8 cam_const_addr[4][6] = { 2243 static u8 cam_const_addr[4][6] = {
2135 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 2244 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2136 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, 2245 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
@@ -2158,6 +2267,7 @@ void rtl8723ae_set_key(struct ieee80211_hw *hw, u32 key_index,
2158 rtlpriv->sec.key_len[idx] = 0; 2267 rtlpriv->sec.key_len[idx] = 0;
2159 } 2268 }
2160 } 2269 }
2270
2161 } else { 2271 } else {
2162 switch (enc_algo) { 2272 switch (enc_algo) {
2163 case WEP40_ENCRYPTION: 2273 case WEP40_ENCRYPTION:
@@ -2173,8 +2283,8 @@ void rtl8723ae_set_key(struct ieee80211_hw *hw, u32 key_index,
2173 enc_algo = CAM_AES; 2283 enc_algo = CAM_AES;
2174 break; 2284 break;
2175 default: 2285 default:
2176 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 2286 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
2177 "switch case not processed\n"); 2287 "switch case not process\n");
2178 enc_algo = CAM_TKIP; 2288 enc_algo = CAM_TKIP;
2179 break; 2289 break;
2180 } 2290 }
@@ -2188,8 +2298,8 @@ void rtl8723ae_set_key(struct ieee80211_hw *hw, u32 key_index,
2188 entry_id = key_index; 2298 entry_id = key_index;
2189 } else { 2299 } else {
2190 if (mac->opmode == NL80211_IFTYPE_AP) { 2300 if (mac->opmode == NL80211_IFTYPE_AP) {
2191 entry_id = rtl_cam_get_free_entry(hw, 2301 entry_id =
2192 macaddr); 2302 rtl_cam_get_free_entry(hw, p_macaddr);
2193 if (entry_id >= TOTAL_CAM_ENTRY) { 2303 if (entry_id >= TOTAL_CAM_ENTRY) {
2194 RT_TRACE(rtlpriv, COMP_SEC, 2304 RT_TRACE(rtlpriv, COMP_SEC,
2195 DBG_EMERG, 2305 DBG_EMERG,
@@ -2220,22 +2330,22 @@ void rtl8723ae_set_key(struct ieee80211_hw *hw, u32 key_index,
2220 "set Pairwiase key\n"); 2330 "set Pairwiase key\n");
2221 2331
2222 rtl_cam_add_one_entry(hw, macaddr, key_index, 2332 rtl_cam_add_one_entry(hw, macaddr, key_index,
2223 entry_id, enc_algo, 2333 entry_id, enc_algo,
2224 CAM_CONFIG_NO_USEDK, 2334 CAM_CONFIG_NO_USEDK,
2225 rtlpriv->sec.key_buf[key_index]); 2335 rtlpriv->sec.key_buf[key_index]);
2226 } else { 2336 } else {
2227 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2337 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2228 "set group key\n"); 2338 "set group key\n");
2229 2339
2230 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 2340 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2231 rtl_cam_add_one_entry(hw, 2341 rtl_cam_add_one_entry(hw,
2232 rtlefuse->dev_addr, 2342 rtlefuse->dev_addr,
2233 PAIRWISE_KEYIDX, 2343 PAIRWISE_KEYIDX,
2234 CAM_PAIRWISE_KEY_POSITION, 2344 CAM_PAIRWISE_KEY_POSITION,
2235 enc_algo, 2345 enc_algo,
2236 CAM_CONFIG_NO_USEDK, 2346 CAM_CONFIG_NO_USEDK,
2237 rtlpriv->sec.key_buf 2347 rtlpriv->sec.key_buf
2238 [entry_id]); 2348 [entry_id]);
2239 } 2349 }
2240 2350
2241 rtl_cam_add_one_entry(hw, macaddr, key_index, 2351 rtl_cam_add_one_entry(hw, macaddr, key_index,
@@ -2248,45 +2358,43 @@ void rtl8723ae_set_key(struct ieee80211_hw *hw, u32 key_index,
2248 } 2358 }
2249} 2359}
2250 2360
2251static void rtl8723ae_bt_var_init(struct ieee80211_hw *hw) 2361static void rtl8723e_bt_var_init(struct ieee80211_hw *hw)
2252{ 2362{
2253 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2254 struct rtl_priv *rtlpriv = rtl_priv(hw); 2363 struct rtl_priv *rtlpriv = rtl_priv(hw);
2255 2364
2256 pcipriv->bt_coexist.bt_coexistence = 2365 rtlpriv->btcoexist.bt_coexistence =
2257 pcipriv->bt_coexist.eeprom_bt_coexist; 2366 rtlpriv->btcoexist.eeprom_bt_coexist;
2258 pcipriv->bt_coexist.bt_ant_num = 2367 rtlpriv->btcoexist.bt_ant_num =
2259 pcipriv->bt_coexist.eeprom_bt_ant_num; 2368 rtlpriv->btcoexist.eeprom_bt_ant_num;
2260 pcipriv->bt_coexist.bt_coexist_type = 2369 rtlpriv->btcoexist.bt_coexist_type =
2261 pcipriv->bt_coexist.eeprom_bt_type; 2370 rtlpriv->btcoexist.eeprom_bt_type;
2262 2371
2263 pcipriv->bt_coexist.bt_ant_isolation = 2372 rtlpriv->btcoexist.bt_ant_isolation =
2264 pcipriv->bt_coexist.eeprom_bt_ant_isol; 2373 rtlpriv->btcoexist.eeprom_bt_ant_isol;
2265 2374
2266 pcipriv->bt_coexist.bt_radio_shared_type = 2375 rtlpriv->btcoexist.bt_radio_shared_type =
2267 pcipriv->bt_coexist.eeprom_bt_radio_shared; 2376 rtlpriv->btcoexist.eeprom_bt_radio_shared;
2268 2377
2269 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2378 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2270 "BT Coexistance = 0x%x\n", 2379 "BT Coexistance = 0x%x\n",
2271 pcipriv->bt_coexist.bt_coexistence); 2380 rtlpriv->btcoexist.bt_coexistence);
2272 2381
2273 if (pcipriv->bt_coexist.bt_coexistence) { 2382 if (rtlpriv->btcoexist.bt_coexistence) {
2274 pcipriv->bt_coexist.bt_busy_traffic = false; 2383 rtlpriv->btcoexist.bt_busy_traffic = false;
2275 pcipriv->bt_coexist.bt_traffic_mode_set = false; 2384 rtlpriv->btcoexist.bt_traffic_mode_set = false;
2276 pcipriv->bt_coexist.bt_non_traffic_mode_set = false; 2385 rtlpriv->btcoexist.bt_non_traffic_mode_set = false;
2277 2386
2278 pcipriv->bt_coexist.cstate = 0; 2387 rtlpriv->btcoexist.cstate = 0;
2279 pcipriv->bt_coexist.previous_state = 0; 2388 rtlpriv->btcoexist.previous_state = 0;
2280 2389
2281 if (pcipriv->bt_coexist.bt_ant_num == ANT_X2) { 2390 if (rtlpriv->btcoexist.bt_ant_num == ANT_X2) {
2282 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2391 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2283 "BlueTooth BT_Ant_Num = Antx2\n"); 2392 "BlueTooth BT_Ant_Num = Antx2\n");
2284 } else if (pcipriv->bt_coexist.bt_ant_num == ANT_X1) { 2393 } else if (rtlpriv->btcoexist.bt_ant_num == ANT_X1) {
2285 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2394 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2286 "BlueTooth BT_Ant_Num = Antx1\n"); 2395 "BlueTooth BT_Ant_Num = Antx1\n");
2287 } 2396 }
2288 2397 switch (rtlpriv->btcoexist.bt_coexist_type) {
2289 switch (pcipriv->bt_coexist.bt_coexist_type) {
2290 case BT_2WIRE: 2398 case BT_2WIRE:
2291 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2399 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2292 "BlueTooth BT_CoexistType = BT_2Wire\n"); 2400 "BlueTooth BT_CoexistType = BT_2Wire\n");
@@ -2318,20 +2426,19 @@ static void rtl8723ae_bt_var_init(struct ieee80211_hw *hw)
2318 } 2426 }
2319 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2427 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2320 "BlueTooth BT_Ant_isolation = %d\n", 2428 "BlueTooth BT_Ant_isolation = %d\n",
2321 pcipriv->bt_coexist.bt_ant_isolation); 2429 rtlpriv->btcoexist.bt_ant_isolation);
2322 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2430 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2323 "BT_RadioSharedType = 0x%x\n", 2431 "BT_RadioSharedType = 0x%x\n",
2324 pcipriv->bt_coexist.bt_radio_shared_type); 2432 rtlpriv->btcoexist.bt_radio_shared_type);
2325 pcipriv->bt_coexist.bt_active_zero_cnt = 0; 2433 rtlpriv->btcoexist.bt_active_zero_cnt = 0;
2326 pcipriv->bt_coexist.cur_bt_disabled = false; 2434 rtlpriv->btcoexist.cur_bt_disabled = false;
2327 pcipriv->bt_coexist.pre_bt_disabled = false; 2435 rtlpriv->btcoexist.pre_bt_disabled = false;
2328 } 2436 }
2329} 2437}
2330 2438
2331void rtl8723ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw, 2439void rtl8723e_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2332 bool auto_load_fail, u8 *hwinfo) 2440 bool auto_load_fail, u8 *hwinfo)
2333{ 2441{
2334 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2335 struct rtl_priv *rtlpriv = rtl_priv(hw); 2442 struct rtl_priv *rtlpriv = rtl_priv(hw);
2336 u8 value; 2443 u8 value;
2337 u32 tmpu_32; 2444 u32 tmpu_32;
@@ -2339,47 +2446,50 @@ void rtl8723ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2339 if (!auto_load_fail) { 2446 if (!auto_load_fail) {
2340 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL); 2447 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
2341 if (tmpu_32 & BIT(18)) 2448 if (tmpu_32 & BIT(18))
2342 pcipriv->bt_coexist.eeprom_bt_coexist = 1; 2449 rtlpriv->btcoexist.eeprom_bt_coexist = 1;
2343 else 2450 else
2344 pcipriv->bt_coexist.eeprom_bt_coexist = 0; 2451 rtlpriv->btcoexist.eeprom_bt_coexist = 0;
2345 value = hwinfo[RF_OPTION4]; 2452 value = hwinfo[RF_OPTION4];
2346 pcipriv->bt_coexist.eeprom_bt_type = BT_RTL8723A; 2453 rtlpriv->btcoexist.eeprom_bt_type = BT_RTL8723A;
2347 pcipriv->bt_coexist.eeprom_bt_ant_num = (value & 0x1); 2454 rtlpriv->btcoexist.eeprom_bt_ant_num = (value & 0x1);
2348 pcipriv->bt_coexist.eeprom_bt_ant_isol = ((value & 0x10) >> 4); 2455 rtlpriv->btcoexist.eeprom_bt_ant_isol = ((value & 0x10) >> 4);
2349 pcipriv->bt_coexist.eeprom_bt_radio_shared = 2456 rtlpriv->btcoexist.eeprom_bt_radio_shared =
2350 ((value & 0x20) >> 5); 2457 ((value & 0x20) >> 5);
2351 } else { 2458 } else {
2352 pcipriv->bt_coexist.eeprom_bt_coexist = 0; 2459 rtlpriv->btcoexist.eeprom_bt_coexist = 0;
2353 pcipriv->bt_coexist.eeprom_bt_type = BT_RTL8723A; 2460 rtlpriv->btcoexist.eeprom_bt_type = BT_RTL8723A;
2354 pcipriv->bt_coexist.eeprom_bt_ant_num = ANT_X2; 2461 rtlpriv->btcoexist.eeprom_bt_ant_num = ANT_X2;
2355 pcipriv->bt_coexist.eeprom_bt_ant_isol = 0; 2462 rtlpriv->btcoexist.eeprom_bt_ant_isol = 0;
2356 pcipriv->bt_coexist.eeprom_bt_radio_shared = BT_RADIO_SHARED; 2463 rtlpriv->btcoexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2357 } 2464 }
2358 2465
2359 rtl8723ae_bt_var_init(hw); 2466 rtl8723e_bt_var_init(hw);
2360} 2467}
2361 2468
2362void rtl8723ae_bt_reg_init(struct ieee80211_hw *hw) 2469void rtl8723e_bt_reg_init(struct ieee80211_hw *hw)
2363{ 2470{
2364 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2471 struct rtl_priv *rtlpriv = rtl_priv(hw);
2365 2472
2366 /* 0:Low, 1:High, 2:From Efuse. */ 2473 /* 0:Low, 1:High, 2:From Efuse. */
2367 pcipriv->bt_coexist.reg_bt_iso = 2; 2474 rtlpriv->btcoexist.reg_bt_iso = 2;
2368 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */ 2475 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2369 pcipriv->bt_coexist.reg_bt_sco = 3; 2476 rtlpriv->btcoexist.reg_bt_sco = 3;
2370 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */ 2477 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2371 pcipriv->bt_coexist.reg_bt_sco = 0; 2478 rtlpriv->btcoexist.reg_bt_sco = 0;
2372} 2479}
2373 2480
2374 2481void rtl8723e_bt_hw_init(struct ieee80211_hw *hw)
2375void rtl8723ae_bt_hw_init(struct ieee80211_hw *hw)
2376{ 2482{
2483 struct rtl_priv *rtlpriv = rtl_priv(hw);
2484
2485 if (rtlpriv->cfg->ops->get_btc_status())
2486 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
2377} 2487}
2378 2488
2379void rtl8723ae_suspend(struct ieee80211_hw *hw) 2489void rtl8723e_suspend(struct ieee80211_hw *hw)
2380{ 2490{
2381} 2491}
2382 2492
2383void rtl8723ae_resume(struct ieee80211_hw *hw) 2493void rtl8723e_resume(struct ieee80211_hw *hw)
2384{ 2494{
2385} 2495}
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/hw.h b/drivers/net/wireless/rtlwifi/rtl8723ae/hw.h
index d3bc39fb27a5..32c1ace97c3f 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/hw.h
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/hw.h
@@ -11,10 +11,6 @@
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details. 12 * more details.
13 * 13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the 14 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE. 15 * file called LICENSE.
20 * 16 *
@@ -34,38 +30,38 @@
34 ((rtlefuse->eeprom_svid == (_val1)) && \ 30 ((rtlefuse->eeprom_svid == (_val1)) && \
35 (rtlefuse->eeprom_smid == (_val2))) 31 (rtlefuse->eeprom_smid == (_val2)))
36 32
37void rtl8723ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val); 33void rtl8723e_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
38void rtl8723ae_read_eeprom_info(struct ieee80211_hw *hw); 34void rtl8723e_read_eeprom_info(struct ieee80211_hw *hw);
39 35
40void rtl8723ae_interrupt_recognized(struct ieee80211_hw *hw, 36void rtl8723e_interrupt_recognized(struct ieee80211_hw *hw,
41 u32 *p_inta, u32 *p_intb); 37 u32 *p_inta, u32 *p_intb);
42int rtl8723ae_hw_init(struct ieee80211_hw *hw); 38int rtl8723e_hw_init(struct ieee80211_hw *hw);
43void rtl8723ae_card_disable(struct ieee80211_hw *hw); 39void rtl8723e_card_disable(struct ieee80211_hw *hw);
44void rtl8723ae_enable_interrupt(struct ieee80211_hw *hw); 40void rtl8723e_enable_interrupt(struct ieee80211_hw *hw);
45void rtl8723ae_disable_interrupt(struct ieee80211_hw *hw); 41void rtl8723e_disable_interrupt(struct ieee80211_hw *hw);
46int rtl8723ae_set_network_type(struct ieee80211_hw *hw, 42int rtl8723e_set_network_type(struct ieee80211_hw *hw,
47 enum nl80211_iftype type); 43 enum nl80211_iftype type);
48void rtl8723ae_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid); 44void rtl8723e_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid);
49void rtl8723ae_set_qos(struct ieee80211_hw *hw, int aci); 45void rtl8723e_set_qos(struct ieee80211_hw *hw, int aci);
50void rtl8723ae_set_beacon_related_registers(struct ieee80211_hw *hw); 46void rtl8723e_set_beacon_related_registers(struct ieee80211_hw *hw);
51void rtl8723ae_set_beacon_interval(struct ieee80211_hw *hw); 47void rtl8723e_set_beacon_interval(struct ieee80211_hw *hw);
52void rtl8723ae_update_interrupt_mask(struct ieee80211_hw *hw, 48void rtl8723e_update_interrupt_mask(struct ieee80211_hw *hw,
53 u32 add_msr, u32 rm_msr); 49 u32 add_msr, u32 rm_msr);
54void rtl8723ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val); 50void rtl8723e_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
55void rtl8723ae_update_hal_rate_tbl(struct ieee80211_hw *hw, 51void rtl8723e_update_hal_rate_tbl(struct ieee80211_hw *hw,
56 struct ieee80211_sta *sta, u8 rssi_level); 52 struct ieee80211_sta *sta, u8 rssi_level);
57void rtl8723ae_update_channel_access_setting(struct ieee80211_hw *hw); 53void rtl8723e_update_channel_access_setting(struct ieee80211_hw *hw);
58bool rtl8723ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid); 54bool rtl8723e_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid);
59void rtl8723ae_enable_hw_security_config(struct ieee80211_hw *hw); 55void rtl8723e_enable_hw_security_config(struct ieee80211_hw *hw);
60void rtl8723ae_set_key(struct ieee80211_hw *hw, u32 key_index, 56void rtl8723e_set_key(struct ieee80211_hw *hw, u32 key_index,
61 u8 *p_macaddr, bool is_group, u8 enc_algo, 57 u8 *p_macaddr, bool is_group, u8 enc_algo,
62 bool is_wepkey, bool clear_all); 58 bool is_wepkey, bool clear_all);
63 59
64void rtl8723ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw, 60void rtl8723e_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
65 bool autoload_fail, u8 *hwinfo); 61 bool autoload_fail, u8 *hwinfo);
66void rtl8723ae_bt_reg_init(struct ieee80211_hw *hw); 62void rtl8723e_bt_reg_init(struct ieee80211_hw *hw);
67void rtl8723ae_bt_hw_init(struct ieee80211_hw *hw); 63void rtl8723e_bt_hw_init(struct ieee80211_hw *hw);
68void rtl8723ae_suspend(struct ieee80211_hw *hw); 64void rtl8723e_suspend(struct ieee80211_hw *hw);
69void rtl8723ae_resume(struct ieee80211_hw *hw); 65void rtl8723e_resume(struct ieee80211_hw *hw);
70 66
71#endif 67#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/led.c b/drivers/net/wireless/rtlwifi/rtl8723ae/led.c
index 061526fe6e2d..13173351cbfd 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/led.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/led.c
@@ -32,44 +32,44 @@
32#include "reg.h" 32#include "reg.h"
33#include "led.h" 33#include "led.h"
34 34
35static void _rtl8723ae_init_led(struct ieee80211_hw *hw, 35static void _rtl8723e_init_led(struct ieee80211_hw *hw,
36 struct rtl_led *pled, enum rtl_led_pin ledpin) 36 struct rtl_led *pled, enum rtl_led_pin ledpin)
37{ 37{
38 pled->hw = hw; 38 pled->hw = hw;
39 pled->ledpin = ledpin; 39 pled->ledpin = ledpin;
40 pled->ledon = false; 40 pled->ledon = false;
41} 41}
42 42
43void rtl8723ae_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled) 43void rtl8723e_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
44{ 44{
45 struct rtl_priv *rtlpriv = rtl_priv(hw);
46 u8 ledcfg; 45 u8 ledcfg;
46 struct rtl_priv *rtlpriv = rtl_priv(hw);
47 47
48 RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD, 48 RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD,
49 "LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin); 49 "LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin);
50 50
51 ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
52
53 switch (pled->ledpin) { 51 switch (pled->ledpin) {
54 case LED_PIN_GPIO0: 52 case LED_PIN_GPIO0:
55 break; 53 break;
56 case LED_PIN_LED0: 54 case LED_PIN_LED0:
55 ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
57 ledcfg &= ~BIT(6); 56 ledcfg &= ~BIT(6);
58 rtl_write_byte(rtlpriv, 57 rtl_write_byte(rtlpriv,
59 REG_LEDCFG2, (ledcfg & 0xf0) | BIT(5)); 58 REG_LEDCFG2, (ledcfg & 0xf0) | BIT(5));
60 break; 59 break;
61 case LED_PIN_LED1: 60 case LED_PIN_LED1:
62 rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg & 0x0f) | BIT(5)); 61 ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG1);
62 rtl_write_byte(rtlpriv, REG_LEDCFG1, ledcfg & 0x10);
63 break; 63 break;
64 default: 64 default:
65 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 65 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
66 "switch case not processed\n"); 66 "switch case not process\n");
67 break; 67 break;
68 } 68 }
69 pled->ledon = true; 69 pled->ledon = true;
70} 70}
71 71
72void rtl8723ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled) 72void rtl8723e_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
73{ 73{
74 struct rtl_priv *rtlpriv = rtl_priv(hw); 74 struct rtl_priv *rtlpriv = rtl_priv(hw);
75 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 75 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
@@ -86,7 +86,7 @@ void rtl8723ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
86 case LED_PIN_LED0: 86 case LED_PIN_LED0:
87 ledcfg &= 0xf0; 87 ledcfg &= 0xf0;
88 if (pcipriv->ledctl.led_opendrain) { 88 if (pcipriv->ledctl.led_opendrain) {
89 ledcfg &= 0x90; 89 ledcfg &= 0x90; /* Set to software control. */
90 rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg|BIT(3))); 90 rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg|BIT(3)));
91 ledcfg = rtl_read_byte(rtlpriv, REG_MAC_PINMUX_CFG); 91 ledcfg = rtl_read_byte(rtlpriv, REG_MAC_PINMUX_CFG);
92 ledcfg &= 0xFE; 92 ledcfg &= 0xFE;
@@ -94,50 +94,51 @@ void rtl8723ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
94 } else { 94 } else {
95 ledcfg &= ~BIT(6); 95 ledcfg &= ~BIT(6);
96 rtl_write_byte(rtlpriv, REG_LEDCFG2, 96 rtl_write_byte(rtlpriv, REG_LEDCFG2,
97 (ledcfg | BIT(3) | BIT(5))); 97 (ledcfg | BIT(3) | BIT(5)));
98 } 98 }
99 break; 99 break;
100 case LED_PIN_LED1: 100 case LED_PIN_LED1:
101 ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG1) & 0x10; 101 ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG1);
102 rtl_write_byte(rtlpriv, REG_LEDCFG1, (ledcfg | BIT(3))); 102 ledcfg &= 0x10; /* Set to software control. */
103 rtl_write_byte(rtlpriv, REG_LEDCFG1, ledcfg|BIT(3));
104
103 break; 105 break;
104 default: 106 default:
105 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 107 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
106 "switch case not processed\n"); 108 "switch case not process\n");
107 break; 109 break;
108 } 110 }
109 pled->ledon = false; 111 pled->ledon = false;
110} 112}
111 113
112void rtl8723ae_init_sw_leds(struct ieee80211_hw *hw) 114void rtl8723e_init_sw_leds(struct ieee80211_hw *hw)
113{ 115{
114 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 116 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
115 117 _rtl8723e_init_led(hw, &pcipriv->ledctl.sw_led0, LED_PIN_LED0);
116 _rtl8723ae_init_led(hw, &(pcipriv->ledctl.sw_led0), LED_PIN_LED0); 118 _rtl8723e_init_led(hw, &pcipriv->ledctl.sw_led1, LED_PIN_LED1);
117 _rtl8723ae_init_led(hw, &(pcipriv->ledctl.sw_led1), LED_PIN_LED1);
118} 119}
119 120
120static void _rtl8723ae_sw_led_control(struct ieee80211_hw *hw, 121static void _rtl8723e_sw_led_control(struct ieee80211_hw *hw,
121 enum led_ctl_mode ledaction) 122 enum led_ctl_mode ledaction)
122{ 123{
123 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 124 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
124 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0); 125 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
125
126 switch (ledaction) { 126 switch (ledaction) {
127 case LED_CTL_POWER_ON: 127 case LED_CTL_POWER_ON:
128 case LED_CTL_LINK: 128 case LED_CTL_LINK:
129 case LED_CTL_NO_LINK: 129 case LED_CTL_NO_LINK:
130 rtl8723ae_sw_led_on(hw, pLed0); 130 rtl8723e_sw_led_on(hw, pLed0);
131 break; 131 break;
132 case LED_CTL_POWER_OFF: 132 case LED_CTL_POWER_OFF:
133 rtl8723ae_sw_led_off(hw, pLed0); 133 rtl8723e_sw_led_off(hw, pLed0);
134 break; 134 break;
135 default: 135 default:
136 break; 136 break;
137 } 137 }
138} 138}
139 139
140void rtl8723ae_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction) 140void rtl8723e_led_control(struct ieee80211_hw *hw,
141 enum led_ctl_mode ledaction)
141{ 142{
142 struct rtl_priv *rtlpriv = rtl_priv(hw); 143 struct rtl_priv *rtlpriv = rtl_priv(hw);
143 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 144 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
@@ -152,6 +153,7 @@ void rtl8723ae_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction)
152 ledaction == LED_CTL_POWER_ON)) { 153 ledaction == LED_CTL_POWER_ON)) {
153 return; 154 return;
154 } 155 }
155 RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD, "ledaction %d,\n", ledaction); 156 RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD, "ledaction %d,\n",
156 _rtl8723ae_sw_led_control(hw, ledaction); 157 ledaction);
158 _rtl8723e_sw_led_control(hw, ledaction);
157} 159}
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/led.h b/drivers/net/wireless/rtlwifi/rtl8723ae/led.h
index 2cb88e78f62a..c22b19f542a6 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/led.h
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/led.h
@@ -11,10 +11,6 @@
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details. 12 * more details.
13 * 13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the 14 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE. 15 * file called LICENSE.
20 * 16 *
@@ -30,10 +26,9 @@
30#ifndef __RTL92CE_LED_H__ 26#ifndef __RTL92CE_LED_H__
31#define __RTL92CE_LED_H__ 27#define __RTL92CE_LED_H__
32 28
33void rtl8723ae_init_sw_leds(struct ieee80211_hw *hw); 29void rtl8723e_init_sw_leds(struct ieee80211_hw *hw);
34void rtl8723ae_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled); 30void rtl8723e_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled);
35void rtl8723ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled); 31void rtl8723e_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled);
36void rtl8723ae_led_control(struct ieee80211_hw *hw, 32void rtl8723e_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction);
37 enum led_ctl_mode ledaction);
38 33
39#endif 34#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/phy.c b/drivers/net/wireless/rtlwifi/rtl8723ae/phy.c
index 3ea78afdec73..1e2fa9300350 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/phy.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/phy.c
@@ -11,10 +11,6 @@
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details. 12 * more details.
13 * 13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the 14 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE. 15 * file called LICENSE.
20 * 16 *
@@ -30,7 +26,6 @@
30#include "../wifi.h" 26#include "../wifi.h"
31#include "../pci.h" 27#include "../pci.h"
32#include "../ps.h" 28#include "../ps.h"
33#include "../core.h"
34#include "reg.h" 29#include "reg.h"
35#include "def.h" 30#include "def.h"
36#include "phy.h" 31#include "phy.h"
@@ -39,29 +34,31 @@
39#include "table.h" 34#include "table.h"
40#include "../rtl8723com/phy_common.h" 35#include "../rtl8723com/phy_common.h"
41 36
42/* static forward definitions */ 37static void _rtl8723e_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
43static u32 _phy_fw_rf_serial_read(struct ieee80211_hw *hw, 38 enum radio_path rfpath, u32 offset,
44 enum radio_path rfpath, u32 offset); 39 u32 data);
45static void _phy_fw_rf_serial_write(struct ieee80211_hw *hw, 40static bool _rtl8723e_phy_bb8192c_config_parafile(struct ieee80211_hw *hw);
46 enum radio_path rfpath, 41static bool _rtl8723e_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
47 u32 offset, u32 data); 42static bool _rtl8723e_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
48static bool _phy_bb8192c_config_parafile(struct ieee80211_hw *hw); 43 u8 configtype);
49static bool _phy_cfg_mac_w_header(struct ieee80211_hw *hw); 44static bool _rtl8723e_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
50static bool _phy_cfg_bb_w_header(struct ieee80211_hw *hw, u8 configtype); 45 u8 configtype);
51static bool _phy_cfg_bb_w_pgheader(struct ieee80211_hw *hw, u8 configtype); 46static bool _rtl8723e_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
52static bool _phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, u8 channel, 47 u8 channel, u8 *stage, u8 *step,
53 u8 *stage, u8 *step, u32 *delay); 48 u32 *delay);
54static u8 _phy_dbm_to_txpwr_Idx(struct ieee80211_hw *hw, 49static u8 _rtl8723e_phy_dbm_to_txpwr_idx(struct ieee80211_hw *hw,
55 enum wireless_mode wirelessmode, 50 enum wireless_mode wirelessmode,
56 long power_indbm); 51 long power_indbm);
57static void rtl8723ae_phy_set_io(struct ieee80211_hw *hw); 52static void rtl8723e_phy_set_rf_on(struct ieee80211_hw *hw);
58 53static void rtl8723e_phy_set_io(struct ieee80211_hw *hw);
59u32 rtl8723ae_phy_query_rf_reg(struct ieee80211_hw *hw, 54
60 enum radio_path rfpath, u32 regaddr, u32 bitmask) 55u32 rtl8723e_phy_query_rf_reg(struct ieee80211_hw *hw,
56 enum radio_path rfpath,
57 u32 regaddr, u32 bitmask)
61{ 58{
62 struct rtl_priv *rtlpriv = rtl_priv(hw); 59 struct rtl_priv *rtlpriv = rtl_priv(hw);
63 u32 original_value, readback_value, bitshift; 60 u32 original_value = 0, readback_value, bitshift;
64 struct rtl_phy *rtlphy = &(rtlpriv->phy); 61 struct rtl_phy *rtlphy = &rtlpriv->phy;
65 unsigned long flags; 62 unsigned long flags;
66 63
67 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 64 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
@@ -70,10 +67,10 @@ u32 rtl8723ae_phy_query_rf_reg(struct ieee80211_hw *hw,
70 67
71 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags); 68 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
72 69
73 if (rtlphy->rf_mode != RF_OP_BY_FW) 70 if (rtlphy->rf_mode != RF_OP_BY_FW) {
74 original_value = rtl8723_phy_rf_serial_read(hw, rfpath, regaddr); 71 original_value = rtl8723_phy_rf_serial_read(hw,
75 else 72 rfpath, regaddr);
76 original_value = _phy_fw_rf_serial_read(hw, rfpath, regaddr); 73 }
77 74
78 bitshift = rtl8723_phy_calculate_bit_shift(bitmask); 75 bitshift = rtl8723_phy_calculate_bit_shift(bitmask);
79 readback_value = (original_value & bitmask) >> bitshift; 76 readback_value = (original_value & bitmask) >> bitshift;
@@ -82,45 +79,46 @@ u32 rtl8723ae_phy_query_rf_reg(struct ieee80211_hw *hw,
82 79
83 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 80 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
84 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n", 81 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
85 regaddr, rfpath, bitmask, original_value); 82 regaddr, rfpath, bitmask, original_value);
86 83
87 return readback_value; 84 return readback_value;
88} 85}
89 86
90void rtl8723ae_phy_set_rf_reg(struct ieee80211_hw *hw, 87void rtl8723e_phy_set_rf_reg(struct ieee80211_hw *hw,
91 enum radio_path rfpath, 88 enum radio_path rfpath,
92 u32 regaddr, u32 bitmask, u32 data) 89 u32 regaddr, u32 bitmask, u32 data)
93{ 90{
94 struct rtl_priv *rtlpriv = rtl_priv(hw); 91 struct rtl_priv *rtlpriv = rtl_priv(hw);
95 struct rtl_phy *rtlphy = &(rtlpriv->phy); 92 struct rtl_phy *rtlphy = &rtlpriv->phy;
96 u32 original_value, bitshift; 93 u32 original_value = 0, bitshift;
97 unsigned long flags; 94 unsigned long flags;
98 95
99 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 96 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
100 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", 97 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
101 regaddr, bitmask, data, rfpath); 98 regaddr, bitmask, data, rfpath);
102 99
103 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags); 100 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
104 101
105 if (rtlphy->rf_mode != RF_OP_BY_FW) { 102 if (rtlphy->rf_mode != RF_OP_BY_FW) {
106 if (bitmask != RFREG_OFFSET_MASK) { 103 if (bitmask != RFREG_OFFSET_MASK) {
107 original_value = rtl8723_phy_rf_serial_read(hw, rfpath, 104 original_value = rtl8723_phy_rf_serial_read(hw,
105 rfpath,
108 regaddr); 106 regaddr);
109 bitshift = rtl8723_phy_calculate_bit_shift(bitmask); 107 bitshift = rtl8723_phy_calculate_bit_shift(bitmask);
110 data = ((original_value & (~bitmask)) | 108 data =
111 (data << bitshift)); 109 ((original_value & (~bitmask)) |
110 (data << bitshift));
112 } 111 }
113 112
114 rtl8723_phy_rf_serial_write(hw, rfpath, regaddr, data); 113 rtl8723_phy_rf_serial_write(hw, rfpath, regaddr, data);
115 } else { 114 } else {
116 if (bitmask != RFREG_OFFSET_MASK) { 115 if (bitmask != RFREG_OFFSET_MASK) {
117 original_value = _phy_fw_rf_serial_read(hw, rfpath,
118 regaddr);
119 bitshift = rtl8723_phy_calculate_bit_shift(bitmask); 116 bitshift = rtl8723_phy_calculate_bit_shift(bitmask);
120 data = ((original_value & (~bitmask)) | 117 data =
121 (data << bitshift)); 118 ((original_value & (~bitmask)) |
119 (data << bitshift));
122 } 120 }
123 _phy_fw_rf_serial_write(hw, rfpath, regaddr, data); 121 _rtl8723e_phy_fw_rf_serial_write(hw, rfpath, regaddr, data);
124 } 122 }
125 123
126 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags); 124 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
@@ -128,23 +126,17 @@ void rtl8723ae_phy_set_rf_reg(struct ieee80211_hw *hw,
128 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 126 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
129 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", 127 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
130 regaddr, bitmask, data, rfpath); 128 regaddr, bitmask, data, rfpath);
131}
132 129
133static u32 _phy_fw_rf_serial_read(struct ieee80211_hw *hw,
134 enum radio_path rfpath, u32 offset)
135{
136 RT_ASSERT(false, "deprecated!\n");
137 return 0;
138} 130}
139 131
140static void _phy_fw_rf_serial_write(struct ieee80211_hw *hw, 132static void _rtl8723e_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
141 enum radio_path rfpath, 133 enum radio_path rfpath, u32 offset,
142 u32 offset, u32 data) 134 u32 data)
143{ 135{
144 RT_ASSERT(false, "deprecated!\n"); 136 RT_ASSERT(false, "deprecated!\n");
145} 137}
146 138
147static void _rtl8723ae_phy_bb_config_1t(struct ieee80211_hw *hw) 139static void _rtl8723e_phy_bb_config_1t(struct ieee80211_hw *hw)
148{ 140{
149 rtl_set_bbreg(hw, RFPGA0_TXINFO, 0x3, 0x2); 141 rtl_set_bbreg(hw, RFPGA0_TXINFO, 0x3, 0x2);
150 rtl_set_bbreg(hw, RFPGA1_TXINFO, 0x300033, 0x200022); 142 rtl_set_bbreg(hw, RFPGA1_TXINFO, 0x300033, 0x200022);
@@ -158,20 +150,20 @@ static void _rtl8723ae_phy_bb_config_1t(struct ieee80211_hw *hw)
158 rtl_set_bbreg(hw, 0xe88, 0x0c000000, 0x2); 150 rtl_set_bbreg(hw, 0xe88, 0x0c000000, 0x2);
159} 151}
160 152
161bool rtl8723ae_phy_mac_config(struct ieee80211_hw *hw) 153bool rtl8723e_phy_mac_config(struct ieee80211_hw *hw)
162{ 154{
163 struct rtl_priv *rtlpriv = rtl_priv(hw); 155 struct rtl_priv *rtlpriv = rtl_priv(hw);
164 bool rtstatus = _phy_cfg_mac_w_header(hw); 156 bool rtstatus = _rtl8723e_phy_config_mac_with_headerfile(hw);
165 rtl_write_byte(rtlpriv, 0x04CA, 0x0A); 157 rtl_write_byte(rtlpriv, 0x04CA, 0x0A);
166 return rtstatus; 158 return rtstatus;
167} 159}
168 160
169bool rtl8723ae_phy_bb_config(struct ieee80211_hw *hw) 161bool rtl8723e_phy_bb_config(struct ieee80211_hw *hw)
170{ 162{
171 bool rtstatus = true; 163 bool rtstatus = true;
172 struct rtl_priv *rtlpriv = rtl_priv(hw); 164 struct rtl_priv *rtlpriv = rtl_priv(hw);
173 u8 tmpu1b; 165 u8 tmpu1b;
174 u8 reg_hwparafile = 1; 166 u8 b_reg_hwparafile = 1;
175 167
176 rtl8723_phy_init_bb_rf_reg_def(hw); 168 rtl8723_phy_init_bb_rf_reg_def(hw);
177 169
@@ -186,67 +178,72 @@ bool rtl8723ae_phy_bb_config(struct ieee80211_hw *hw)
186 178
187 /* 3. 0x02[1:0] = 2b'11 */ 179 /* 3. 0x02[1:0] = 2b'11 */
188 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN); 180 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
189 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, (tmpu1b | 181 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
190 FEN_BB_GLB_RSTn | FEN_BBRSTB)); 182 (tmpu1b | FEN_BB_GLB_RSTN | FEN_BBRSTB));
191 183
192 /* 4. 0x25[6] = 0 */ 184 /* 4. 0x25[6] = 0 */
193 tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+1); 185 tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+1);
194 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+1, (tmpu1b&(~BIT(6)))); 186 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+1, (tmpu1b & (~BIT(6))));
195 187
196 /* 5. 0x24[20] = 0 Advised by SD3 Alex Wang. 2011.02.09. */ 188 /* 5. 0x24[20] = 0 //Advised by SD3 Alex Wang. 2011.02.09. */
197 tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+2); 189 tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+2);
198 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+2, (tmpu1b&(~BIT(4)))); 190 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+2, (tmpu1b & (~BIT(4))));
199 191
200 /* 6. 0x1f[7:0] = 0x07 */ 192 /* 6. 0x1f[7:0] = 0x07 */
201 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x07); 193 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x07);
202 194
203 if (reg_hwparafile == 1) 195 if (b_reg_hwparafile == 1)
204 rtstatus = _phy_bb8192c_config_parafile(hw); 196 rtstatus = _rtl8723e_phy_bb8192c_config_parafile(hw);
205 return rtstatus; 197 return rtstatus;
206} 198}
207 199
208bool rtl8723ae_phy_rf_config(struct ieee80211_hw *hw) 200bool rtl8723e_phy_rf_config(struct ieee80211_hw *hw)
209{ 201{
210 return rtl8723ae_phy_rf6052_config(hw); 202 return rtl8723e_phy_rf6052_config(hw);
211} 203}
212 204
213static bool _phy_bb8192c_config_parafile(struct ieee80211_hw *hw) 205static bool _rtl8723e_phy_bb8192c_config_parafile(struct ieee80211_hw *hw)
214{ 206{
215 struct rtl_priv *rtlpriv = rtl_priv(hw); 207 struct rtl_priv *rtlpriv = rtl_priv(hw);
216 struct rtl_phy *rtlphy = &(rtlpriv->phy); 208 struct rtl_phy *rtlphy = &rtlpriv->phy;
217 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 209 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
218 bool rtstatus; 210 bool rtstatus;
219 211
220 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "==>\n"); 212 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "\n");
221 rtstatus = _phy_cfg_bb_w_header(hw, BASEBAND_CONFIG_PHY_REG); 213 rtstatus = _rtl8723e_phy_config_bb_with_headerfile(hw,
214 BASEBAND_CONFIG_PHY_REG);
222 if (rtstatus != true) { 215 if (rtstatus != true) {
223 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Write BB Reg Fail!!"); 216 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Write BB Reg Fail!!");
224 return false; 217 return false;
225 } 218 }
226 219
227 if (rtlphy->rf_type == RF_1T2R) { 220 if (rtlphy->rf_type == RF_1T2R) {
228 _rtl8723ae_phy_bb_config_1t(hw); 221 _rtl8723e_phy_bb_config_1t(hw);
229 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Config to 1T!!\n"); 222 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Config to 1T!!\n");
230 } 223 }
231 if (rtlefuse->autoload_failflag == false) { 224 if (rtlefuse->autoload_failflag == false) {
232 rtlphy->pwrgroup_cnt = 0; 225 rtlphy->pwrgroup_cnt = 0;
233 rtstatus = _phy_cfg_bb_w_pgheader(hw, BASEBAND_CONFIG_PHY_REG); 226 rtstatus = _rtl8723e_phy_config_bb_with_pgheaderfile(hw,
227 BASEBAND_CONFIG_PHY_REG);
234 } 228 }
235 if (rtstatus != true) { 229 if (rtstatus != true) {
236 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "BB_PG Reg Fail!!"); 230 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "BB_PG Reg Fail!!");
237 return false; 231 return false;
238 } 232 }
239 rtstatus = _phy_cfg_bb_w_header(hw, BASEBAND_CONFIG_AGC_TAB); 233 rtstatus =
234 _rtl8723e_phy_config_bb_with_headerfile(hw, BASEBAND_CONFIG_AGC_TAB);
240 if (rtstatus != true) { 235 if (rtstatus != true) {
241 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "AGC Table Fail\n"); 236 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "AGC Table Fail\n");
242 return false; 237 return false;
243 } 238 }
244 rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw, 239 rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw,
245 RFPGA0_XA_HSSIPARAMETER2, 0x200)); 240 RFPGA0_XA_HSSIPARAMETER2,
241 0x200));
242
246 return true; 243 return true;
247} 244}
248 245
249static bool _phy_cfg_mac_w_header(struct ieee80211_hw *hw) 246static bool _rtl8723e_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
250{ 247{
251 struct rtl_priv *rtlpriv = rtl_priv(hw); 248 struct rtl_priv *rtlpriv = rtl_priv(hw);
252 u32 i; 249 u32 i;
@@ -264,7 +261,8 @@ static bool _phy_cfg_mac_w_header(struct ieee80211_hw *hw)
264 return true; 261 return true;
265} 262}
266 263
267static bool _phy_cfg_bb_w_header(struct ieee80211_hw *hw, u8 configtype) 264static bool _rtl8723e_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
265 u8 configtype)
268{ 266{
269 int i; 267 int i;
270 u32 *phy_regarray_table; 268 u32 *phy_regarray_table;
@@ -278,13 +276,23 @@ static bool _phy_cfg_bb_w_header(struct ieee80211_hw *hw, u8 configtype)
278 phy_regarray_table = RTL8723EPHY_REG_1TARRAY; 276 phy_regarray_table = RTL8723EPHY_REG_1TARRAY;
279 if (configtype == BASEBAND_CONFIG_PHY_REG) { 277 if (configtype == BASEBAND_CONFIG_PHY_REG) {
280 for (i = 0; i < phy_reg_arraylen; i = i + 2) { 278 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
281 rtl_addr_delay(phy_regarray_table[i]); 279 if (phy_regarray_table[i] == 0xfe)
280 mdelay(50);
281 else if (phy_regarray_table[i] == 0xfd)
282 mdelay(5);
283 else if (phy_regarray_table[i] == 0xfc)
284 mdelay(1);
285 else if (phy_regarray_table[i] == 0xfb)
286 udelay(50);
287 else if (phy_regarray_table[i] == 0xfa)
288 udelay(5);
289 else if (phy_regarray_table[i] == 0xf9)
290 udelay(1);
282 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD, 291 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
283 phy_regarray_table[i + 1]); 292 phy_regarray_table[i + 1]);
284 udelay(1); 293 udelay(1);
285 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 294 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
286 "The phy_regarray_table[0] is %x" 295 "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
287 " Rtl819XPHY_REGArray[1] is %x\n",
288 phy_regarray_table[i], 296 phy_regarray_table[i],
289 phy_regarray_table[i + 1]); 297 phy_regarray_table[i + 1]);
290 } 298 }
@@ -294,8 +302,7 @@ static bool _phy_cfg_bb_w_header(struct ieee80211_hw *hw, u8 configtype)
294 agctab_array_table[i + 1]); 302 agctab_array_table[i + 1]);
295 udelay(1); 303 udelay(1);
296 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 304 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
297 "The agctab_array_table[0] is " 305 "The agctab_array_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
298 "%x Rtl819XPHY_REGArray[1] is %x\n",
299 agctab_array_table[i], 306 agctab_array_table[i],
300 agctab_array_table[i + 1]); 307 agctab_array_table[i + 1]);
301 } 308 }
@@ -303,132 +310,163 @@ static bool _phy_cfg_bb_w_header(struct ieee80211_hw *hw, u8 configtype)
303 return true; 310 return true;
304} 311}
305 312
306static void _st_pwrIdx_dfrate_off(struct ieee80211_hw *hw, u32 regaddr, 313static void store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,
307 u32 bitmask, u32 data) 314 u32 regaddr, u32 bitmask,
315 u32 data)
308{ 316{
309 struct rtl_priv *rtlpriv = rtl_priv(hw); 317 struct rtl_priv *rtlpriv = rtl_priv(hw);
310 struct rtl_phy *rtlphy = &(rtlpriv->phy); 318 struct rtl_phy *rtlphy = &rtlpriv->phy;
311 319
312 switch (regaddr) { 320 if (regaddr == RTXAGC_A_RATE18_06) {
313 case RTXAGC_A_RATE18_06: 321 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][0] =
314 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][0] = data; 322 data;
315 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 323 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
316 "MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n", 324 "MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n",
317 rtlphy->pwrgroup_cnt, 325 rtlphy->pwrgroup_cnt,
318 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][0]); 326 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
319 break; 327 pwrgroup_cnt][0]);
320 case RTXAGC_A_RATE54_24: 328 }
321 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][1] = data; 329 if (regaddr == RTXAGC_A_RATE54_24) {
330 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][1] =
331 data;
322 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 332 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
323 "MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n", 333 "MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n",
324 rtlphy->pwrgroup_cnt, 334 rtlphy->pwrgroup_cnt,
325 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][1]); 335 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
326 break; 336 pwrgroup_cnt][1]);
327 case RTXAGC_A_CCK1_MCS32: 337 }
328 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][6] = data; 338 if (regaddr == RTXAGC_A_CCK1_MCS32) {
339 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][6] =
340 data;
329 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 341 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
330 "MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n", 342 "MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n",
331 rtlphy->pwrgroup_cnt, 343 rtlphy->pwrgroup_cnt,
332 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][6]); 344 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
333 break; 345 pwrgroup_cnt][6]);
334 case RTXAGC_B_CCK11_A_CCK2_11: 346 }
335 if (bitmask == 0xffffff00) { 347 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) {
336 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][7] = data; 348 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][7] =
337 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 349 data;
338 "MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n", 350 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
339 rtlphy->pwrgroup_cnt, 351 "MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n",
340 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][7]); 352 rtlphy->pwrgroup_cnt,
341 } 353 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
342 if (bitmask == 0x000000ff) { 354 pwrgroup_cnt][7]);
343 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][15] = data; 355 }
344 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 356 if (regaddr == RTXAGC_A_MCS03_MCS00) {
345 "MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n", 357 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][2] =
346 rtlphy->pwrgroup_cnt, 358 data;
347 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][15]);
348 }
349 break;
350 case RTXAGC_A_MCS03_MCS00:
351 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][2] = data;
352 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 359 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
353 "MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n", 360 "MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n",
354 rtlphy->pwrgroup_cnt, 361 rtlphy->pwrgroup_cnt,
355 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][2]); 362 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
356 break; 363 pwrgroup_cnt][2]);
357 case RTXAGC_A_MCS07_MCS04: 364 }
358 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][3] = data; 365 if (regaddr == RTXAGC_A_MCS07_MCS04) {
366 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][3] =
367 data;
359 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 368 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
360 "MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n", 369 "MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n",
361 rtlphy->pwrgroup_cnt, 370 rtlphy->pwrgroup_cnt,
362 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][3]); 371 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
363 break; 372 pwrgroup_cnt][3]);
364 case RTXAGC_A_MCS11_MCS08: 373 }
365 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][4] = data; 374 if (regaddr == RTXAGC_A_MCS11_MCS08) {
375 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][4] =
376 data;
366 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 377 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
367 "MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n", 378 "MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n",
368 rtlphy->pwrgroup_cnt, 379 rtlphy->pwrgroup_cnt,
369 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][4]); 380 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
370 break; 381 pwrgroup_cnt][4]);
371 case RTXAGC_A_MCS15_MCS12: 382 }
372 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][5] = data; 383 if (regaddr == RTXAGC_A_MCS15_MCS12) {
384 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][5] =
385 data;
373 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 386 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
374 "MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n", 387 "MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n",
375 rtlphy->pwrgroup_cnt, 388 rtlphy->pwrgroup_cnt,
376 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][5]); 389 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
377 break; 390 pwrgroup_cnt][5]);
378 case RTXAGC_B_RATE18_06: 391 }
379 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][8] = data; 392 if (regaddr == RTXAGC_B_RATE18_06) {
393 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][8] =
394 data;
380 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 395 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
381 "MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n", 396 "MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n",
382 rtlphy->pwrgroup_cnt, 397 rtlphy->pwrgroup_cnt,
383 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][8]); 398 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
384 break; 399 pwrgroup_cnt][8]);
385 case RTXAGC_B_RATE54_24: 400 }
386 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][9] = data; 401 if (regaddr == RTXAGC_B_RATE54_24) {
402 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][9] =
403 data;
387 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 404 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
388 "MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n", 405 "MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n",
389 rtlphy->pwrgroup_cnt, 406 rtlphy->pwrgroup_cnt,
390 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][9]); 407 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
391 break; 408 pwrgroup_cnt][9]);
392 case RTXAGC_B_CCK1_55_MCS32: 409 }
393 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][14] = data; 410 if (regaddr == RTXAGC_B_CCK1_55_MCS32) {
411 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][14] =
412 data;
394 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 413 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
395 "MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n", 414 "MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n",
396 rtlphy->pwrgroup_cnt, 415 rtlphy->pwrgroup_cnt,
397 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][14]); 416 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
398 break; 417 pwrgroup_cnt][14]);
399 case RTXAGC_B_MCS03_MCS00: 418 }
400 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][10] = data; 419 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) {
420 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][15] =
421 data;
422 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
423 "MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n",
424 rtlphy->pwrgroup_cnt,
425 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
426 pwrgroup_cnt][15]);
427 }
428 if (regaddr == RTXAGC_B_MCS03_MCS00) {
429 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][10] =
430 data;
401 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 431 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
402 "MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n", 432 "MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n",
403 rtlphy->pwrgroup_cnt, 433 rtlphy->pwrgroup_cnt,
404 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][10]); 434 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
405 break; 435 pwrgroup_cnt][10]);
406 case RTXAGC_B_MCS07_MCS04: 436 }
407 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][11] = data; 437 if (regaddr == RTXAGC_B_MCS07_MCS04) {
438 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][11] =
439 data;
408 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 440 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
409 "MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n", 441 "MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n",
410 rtlphy->pwrgroup_cnt, 442 rtlphy->pwrgroup_cnt,
411 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][11]); 443 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
412 break; 444 pwrgroup_cnt][11]);
413 case RTXAGC_B_MCS11_MCS08: 445 }
414 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][12] = data; 446 if (regaddr == RTXAGC_B_MCS11_MCS08) {
447 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][12] =
448 data;
415 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 449 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
416 "MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n", 450 "MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n",
417 rtlphy->pwrgroup_cnt, 451 rtlphy->pwrgroup_cnt,
418 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][12]); 452 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
419 break; 453 pwrgroup_cnt][12]);
420 case RTXAGC_B_MCS15_MCS12: 454 }
421 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][13] = data; 455 if (regaddr == RTXAGC_B_MCS15_MCS12) {
456 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][13] =
457 data;
422 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 458 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
423 "MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n", 459 "MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n",
424 rtlphy->pwrgroup_cnt, 460 rtlphy->pwrgroup_cnt,
425 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][13]); 461 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
462 pwrgroup_cnt][13]);
463
426 rtlphy->pwrgroup_cnt++; 464 rtlphy->pwrgroup_cnt++;
427 break;
428 } 465 }
429} 466}
430 467
431static bool _phy_cfg_bb_w_pgheader(struct ieee80211_hw *hw, u8 configtype) 468static bool _rtl8723e_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
469 u8 configtype)
432{ 470{
433 struct rtl_priv *rtlpriv = rtl_priv(hw); 471 struct rtl_priv *rtlpriv = rtl_priv(hw);
434 int i; 472 int i;
@@ -440,11 +478,23 @@ static bool _phy_cfg_bb_w_pgheader(struct ieee80211_hw *hw, u8 configtype)
440 478
441 if (configtype == BASEBAND_CONFIG_PHY_REG) { 479 if (configtype == BASEBAND_CONFIG_PHY_REG) {
442 for (i = 0; i < phy_regarray_pg_len; i = i + 3) { 480 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
443 rtl_addr_delay(phy_regarray_table_pg[i]); 481 if (phy_regarray_table_pg[i] == 0xfe)
444 482 mdelay(50);
445 _st_pwrIdx_dfrate_off(hw, phy_regarray_table_pg[i], 483 else if (phy_regarray_table_pg[i] == 0xfd)
446 phy_regarray_table_pg[i + 1], 484 mdelay(5);
447 phy_regarray_table_pg[i + 2]); 485 else if (phy_regarray_table_pg[i] == 0xfc)
486 mdelay(1);
487 else if (phy_regarray_table_pg[i] == 0xfb)
488 udelay(50);
489 else if (phy_regarray_table_pg[i] == 0xfa)
490 udelay(5);
491 else if (phy_regarray_table_pg[i] == 0xf9)
492 udelay(1);
493
494 store_pwrindex_diffrate_offset(hw,
495 phy_regarray_table_pg[i],
496 phy_regarray_table_pg[i + 1],
497 phy_regarray_table_pg[i + 2]);
448 } 498 }
449 } else { 499 } else {
450 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, 500 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
@@ -453,45 +503,57 @@ static bool _phy_cfg_bb_w_pgheader(struct ieee80211_hw *hw, u8 configtype)
453 return true; 503 return true;
454} 504}
455 505
456bool rtl8723ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, 506bool rtl8723e_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
457 enum radio_path rfpath) 507 enum radio_path rfpath)
458{ 508{
459 struct rtl_priv *rtlpriv = rtl_priv(hw);
460 int i; 509 int i;
510 bool rtstatus = true;
461 u32 *radioa_array_table; 511 u32 *radioa_array_table;
462 u16 radioa_arraylen; 512 u32 *radiob_array_table;
513 u16 radioa_arraylen, radiob_arraylen;
463 514
464 radioa_arraylen = Rtl8723ERADIOA_1TARRAYLENGTH; 515 radioa_arraylen = RTL8723ERADIOA_1TARRAYLENGTH;
465 radioa_array_table = RTL8723E_RADIOA_1TARRAY; 516 radioa_array_table = RTL8723E_RADIOA_1TARRAY;
517 radiob_arraylen = RTL8723E_RADIOB_1TARRAYLENGTH;
518 radiob_array_table = RTL8723E_RADIOB_1TARRAY;
519
520 rtstatus = true;
466 521
467 switch (rfpath) { 522 switch (rfpath) {
468 case RF90_PATH_A: 523 case RF90_PATH_A:
469 for (i = 0; i < radioa_arraylen; i = i + 2) { 524 for (i = 0; i < radioa_arraylen; i = i + 2) {
470 rtl_rfreg_delay(hw, rfpath, radioa_array_table[i], 525 if (radioa_array_table[i] == 0xfe) {
471 RFREG_OFFSET_MASK, 526 mdelay(50);
472 radioa_array_table[i + 1]); 527 } else if (radioa_array_table[i] == 0xfd) {
528 mdelay(5);
529 } else if (radioa_array_table[i] == 0xfc) {
530 mdelay(1);
531 } else if (radioa_array_table[i] == 0xfb) {
532 udelay(50);
533 } else if (radioa_array_table[i] == 0xfa) {
534 udelay(5);
535 } else if (radioa_array_table[i] == 0xf9) {
536 udelay(1);
537 } else {
538 rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
539 RFREG_OFFSET_MASK,
540 radioa_array_table[i + 1]);
541 udelay(1);
542 }
473 } 543 }
474 break; 544 break;
475 case RF90_PATH_B: 545 case RF90_PATH_B:
476 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
477 "switch case not process\n");
478 break;
479 case RF90_PATH_C: 546 case RF90_PATH_C:
480 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
481 "switch case not process\n");
482 break;
483 case RF90_PATH_D: 547 case RF90_PATH_D:
484 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
485 "switch case not process\n");
486 break; 548 break;
487 } 549 }
488 return true; 550 return true;
489} 551}
490 552
491void rtl8723ae_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw) 553void rtl8723e_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
492{ 554{
493 struct rtl_priv *rtlpriv = rtl_priv(hw); 555 struct rtl_priv *rtlpriv = rtl_priv(hw);
494 struct rtl_phy *rtlphy = &(rtlpriv->phy); 556 struct rtl_phy *rtlphy = &rtlpriv->phy;
495 557
496 rtlphy->default_initialgain[0] = 558 rtlphy->default_initialgain[0] =
497 (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0); 559 (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
@@ -504,10 +566,10 @@ void rtl8723ae_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
504 566
505 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 567 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
506 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n", 568 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
507 rtlphy->default_initialgain[0], 569 rtlphy->default_initialgain[0],
508 rtlphy->default_initialgain[1], 570 rtlphy->default_initialgain[1],
509 rtlphy->default_initialgain[2], 571 rtlphy->default_initialgain[2],
510 rtlphy->default_initialgain[3]); 572 rtlphy->default_initialgain[3]);
511 573
512 rtlphy->framesync = (u8) rtl_get_bbreg(hw, 574 rtlphy->framesync = (u8) rtl_get_bbreg(hw,
513 ROFDM0_RXDETECTOR3, MASKBYTE0); 575 ROFDM0_RXDETECTOR3, MASKBYTE0);
@@ -516,37 +578,43 @@ void rtl8723ae_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
516 578
517 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 579 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
518 "Default framesync (0x%x) = 0x%x\n", 580 "Default framesync (0x%x) = 0x%x\n",
519 ROFDM0_RXDETECTOR3, rtlphy->framesync); 581 ROFDM0_RXDETECTOR3, rtlphy->framesync);
520} 582}
521 583
522void rtl8723ae_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel) 584void rtl8723e_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
523{ 585{
524 struct rtl_priv *rtlpriv = rtl_priv(hw); 586 struct rtl_priv *rtlpriv = rtl_priv(hw);
525 struct rtl_phy *rtlphy = &(rtlpriv->phy); 587 struct rtl_phy *rtlphy = &rtlpriv->phy;
526 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 588 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
527 u8 txpwr_level; 589 u8 txpwr_level;
528 long txpwr_dbm; 590 long txpwr_dbm;
529 591
530 txpwr_level = rtlphy->cur_cck_txpwridx; 592 txpwr_level = rtlphy->cur_cck_txpwridx;
531 txpwr_dbm = rtl8723_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_B, txpwr_level); 593 txpwr_dbm = rtl8723_phy_txpwr_idx_to_dbm(hw,
594 WIRELESS_MODE_B, txpwr_level);
532 txpwr_level = rtlphy->cur_ofdm24g_txpwridx + 595 txpwr_level = rtlphy->cur_ofdm24g_txpwridx +
533 rtlefuse->legacy_ht_txpowerdiff; 596 rtlefuse->legacy_ht_txpowerdiff;
534 if (rtl8723_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G, txpwr_level) > txpwr_dbm) 597 if (rtl8723_phy_txpwr_idx_to_dbm(hw,
535 txpwr_dbm = rtl8723_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G, 598 WIRELESS_MODE_G,
536 txpwr_level); 599 txpwr_level) > txpwr_dbm)
600 txpwr_dbm =
601 rtl8723_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
602 txpwr_level);
537 txpwr_level = rtlphy->cur_ofdm24g_txpwridx; 603 txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
538 if (rtl8723_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G, txpwr_level) > 604 if (rtl8723_phy_txpwr_idx_to_dbm(hw,
539 txpwr_dbm) 605 WIRELESS_MODE_N_24G,
540 txpwr_dbm = rtl8723_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G, 606 txpwr_level) > txpwr_dbm)
541 txpwr_level); 607 txpwr_dbm =
608 rtl8723_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
609 txpwr_level);
542 *powerlevel = txpwr_dbm; 610 *powerlevel = txpwr_dbm;
543} 611}
544 612
545static void _rtl8723ae_get_txpower_index(struct ieee80211_hw *hw, u8 channel, 613static void _rtl8723e_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
546 u8 *cckpowerlevel, u8 *ofdmpowerlevel) 614 u8 *cckpowerlevel, u8 *ofdmpowerlevel)
547{ 615{
548 struct rtl_priv *rtlpriv = rtl_priv(hw); 616 struct rtl_priv *rtlpriv = rtl_priv(hw);
549 struct rtl_phy *rtlphy = &(rtlpriv->phy); 617 struct rtl_phy *rtlphy = &rtlpriv->phy;
550 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 618 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
551 u8 index = (channel - 1); 619 u8 index = (channel - 1);
552 620
@@ -567,66 +635,70 @@ static void _rtl8723ae_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
567 } 635 }
568} 636}
569 637
570static void _rtl8723ae_ccxpower_index_check(struct ieee80211_hw *hw, 638static void _rtl8723e_ccxpower_index_check(struct ieee80211_hw *hw,
571 u8 channel, u8 *cckpowerlevel, 639 u8 channel, u8 *cckpowerlevel,
572 u8 *ofdmpowerlevel) 640 u8 *ofdmpowerlevel)
573{ 641{
574 struct rtl_priv *rtlpriv = rtl_priv(hw); 642 struct rtl_priv *rtlpriv = rtl_priv(hw);
575 struct rtl_phy *rtlphy = &(rtlpriv->phy); 643 struct rtl_phy *rtlphy = &rtlpriv->phy;
576 644
577 rtlphy->cur_cck_txpwridx = cckpowerlevel[0]; 645 rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
578 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0]; 646 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
647
579} 648}
580 649
581void rtl8723ae_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel) 650void rtl8723e_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
582{ 651{
583 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 652 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
584 u8 cckpowerlevel[2], ofdmpowerlevel[2]; 653 u8 cckpowerlevel[2], ofdmpowerlevel[2];
585 654
586 if (rtlefuse->txpwr_fromeprom == false) 655 if (rtlefuse->txpwr_fromeprom == false)
587 return; 656 return;
588 _rtl8723ae_get_txpower_index(hw, channel, &cckpowerlevel[0], 657 _rtl8723e_get_txpower_index(hw, channel,
589 &ofdmpowerlevel[0]); 658 &cckpowerlevel[0], &ofdmpowerlevel[0]);
590 _rtl8723ae_ccxpower_index_check(hw, channel, &cckpowerlevel[0], 659 _rtl8723e_ccxpower_index_check(hw,
591 &ofdmpowerlevel[0]); 660 channel, &cckpowerlevel[0],
592 rtl8723ae_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]); 661 &ofdmpowerlevel[0]);
593 rtl8723ae_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel); 662 rtl8723e_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
663 rtl8723e_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel);
594} 664}
595 665
596bool rtl8723ae_phy_update_txpower_dbm(struct ieee80211_hw *hw, long power_indbm) 666bool rtl8723e_phy_update_txpower_dbm(struct ieee80211_hw *hw, long power_indbm)
597{ 667{
598 struct rtl_priv *rtlpriv = rtl_priv(hw); 668 struct rtl_priv *rtlpriv = rtl_priv(hw);
599 struct rtl_phy *rtlphy = &(rtlpriv->phy); 669 struct rtl_phy *rtlphy = &rtlpriv->phy;
600 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 670 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
601 u8 idx; 671 u8 idx;
602 u8 rf_path; 672 u8 rf_path;
603 u8 ccktxpwridx = _phy_dbm_to_txpwr_Idx(hw, WIRELESS_MODE_B, 673 u8 ccktxpwridx = _rtl8723e_phy_dbm_to_txpwr_idx(hw,
604 power_indbm); 674 WIRELESS_MODE_B,
605 u8 ofdmtxpwridx = _phy_dbm_to_txpwr_Idx(hw, WIRELESS_MODE_N_24G, 675 power_indbm);
606 power_indbm); 676 u8 ofdmtxpwridx = _rtl8723e_phy_dbm_to_txpwr_idx(hw,
677 WIRELESS_MODE_N_24G,
678 power_indbm);
607 if (ofdmtxpwridx - rtlefuse->legacy_ht_txpowerdiff > 0) 679 if (ofdmtxpwridx - rtlefuse->legacy_ht_txpowerdiff > 0)
608 ofdmtxpwridx -= rtlefuse->legacy_ht_txpowerdiff; 680 ofdmtxpwridx -= rtlefuse->legacy_ht_txpowerdiff;
609 else 681 else
610 ofdmtxpwridx = 0; 682 ofdmtxpwridx = 0;
611 RT_TRACE(rtlpriv, COMP_TXAGC, DBG_TRACE, 683 RT_TRACE(rtlpriv, COMP_TXAGC, DBG_TRACE,
612 "%lx dBm, ccktxpwridx = %d, ofdmtxpwridx = %d\n", 684 "%lx dBm, ccktxpwridx = %d, ofdmtxpwridx = %d\n",
613 power_indbm, ccktxpwridx, ofdmtxpwridx); 685 power_indbm, ccktxpwridx, ofdmtxpwridx);
614 for (idx = 0; idx < 14; idx++) { 686 for (idx = 0; idx < 14; idx++) {
615 for (rf_path = 0; rf_path < 2; rf_path++) { 687 for (rf_path = 0; rf_path < 2; rf_path++) {
616 rtlefuse->txpwrlevel_cck[rf_path][idx] = ccktxpwridx; 688 rtlefuse->txpwrlevel_cck[rf_path][idx] = ccktxpwridx;
617 rtlefuse->txpwrlevel_ht40_1s[rf_path][idx] = 689 rtlefuse->txpwrlevel_ht40_1s[rf_path][idx] =
618 ofdmtxpwridx; 690 ofdmtxpwridx;
619 rtlefuse->txpwrlevel_ht40_2s[rf_path][idx] = 691 rtlefuse->txpwrlevel_ht40_2s[rf_path][idx] =
620 ofdmtxpwridx; 692 ofdmtxpwridx;
621 } 693 }
622 } 694 }
623 rtl8723ae_phy_set_txpower_level(hw, rtlphy->current_channel); 695 rtl8723e_phy_set_txpower_level(hw, rtlphy->current_channel);
624 return true; 696 return true;
625} 697}
626 698
627static u8 _phy_dbm_to_txpwr_Idx(struct ieee80211_hw *hw, 699static u8 _rtl8723e_phy_dbm_to_txpwr_idx(struct ieee80211_hw *hw,
628 enum wireless_mode wirelessmode, 700 enum wireless_mode wirelessmode,
629 long power_indbm) 701 long power_indbm)
630{ 702{
631 u8 txpwridx; 703 u8 txpwridx;
632 long offset; 704 long offset;
@@ -645,7 +717,7 @@ static u8 _phy_dbm_to_txpwr_Idx(struct ieee80211_hw *hw,
645 } 717 }
646 718
647 if ((power_indbm - offset) > 0) 719 if ((power_indbm - offset) > 0)
648 txpwridx = (u8) ((power_indbm - offset) * 2); 720 txpwridx = (u8)((power_indbm - offset) * 2);
649 else 721 else
650 txpwridx = 0; 722 txpwridx = 0;
651 723
@@ -655,19 +727,48 @@ static u8 _phy_dbm_to_txpwr_Idx(struct ieee80211_hw *hw,
655 return txpwridx; 727 return txpwridx;
656} 728}
657 729
658void rtl8723ae_phy_set_bw_mode_callback(struct ieee80211_hw *hw) 730void rtl8723e_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
731{
732 struct rtl_priv *rtlpriv = rtl_priv(hw);
733 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
734 enum io_type iotype;
735
736 if (!is_hal_stop(rtlhal)) {
737 switch (operation) {
738 case SCAN_OPT_BACKUP_BAND0:
739 iotype = IO_CMD_PAUSE_BAND0_DM_BY_SCAN;
740 rtlpriv->cfg->ops->set_hw_reg(hw,
741 HW_VAR_IO_CMD,
742 (u8 *)&iotype);
743
744 break;
745 case SCAN_OPT_RESTORE:
746 iotype = IO_CMD_RESUME_DM_BY_SCAN;
747 rtlpriv->cfg->ops->set_hw_reg(hw,
748 HW_VAR_IO_CMD,
749 (u8 *)&iotype);
750 break;
751 default:
752 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
753 "Unknown Scan Backup operation.\n");
754 break;
755 }
756 }
757}
758
759void rtl8723e_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
659{ 760{
660 struct rtl_priv *rtlpriv = rtl_priv(hw); 761 struct rtl_priv *rtlpriv = rtl_priv(hw);
661 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 762 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
662 struct rtl_phy *rtlphy = &(rtlpriv->phy); 763 struct rtl_phy *rtlphy = &rtlpriv->phy;
663 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 764 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
664 u8 reg_bw_opmode; 765 u8 reg_bw_opmode;
665 u8 reg_prsr_rsc; 766 u8 reg_prsr_rsc;
666 767
667 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, 768 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
668 "Switch to %s bandwidth\n", 769 "Switch to %s bandwidth\n",
669 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ? 770 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
670 "20MHz" : "40MHz"); 771 "20MHz" : "40MHz");
671 772
672 if (is_hal_stop(rtlhal)) { 773 if (is_hal_stop(rtlhal)) {
673 rtlphy->set_bwmode_inprogress = false; 774 rtlphy->set_bwmode_inprogress = false;
@@ -719,16 +820,16 @@ void rtl8723ae_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
719 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw); 820 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
720 break; 821 break;
721 } 822 }
722 rtl8723ae_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw); 823 rtl8723e_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
723 rtlphy->set_bwmode_inprogress = false; 824 rtlphy->set_bwmode_inprogress = false;
724 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n"); 825 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "\n");
725} 826}
726 827
727void rtl8723ae_phy_set_bw_mode(struct ieee80211_hw *hw, 828void rtl8723e_phy_set_bw_mode(struct ieee80211_hw *hw,
728 enum nl80211_channel_type ch_type) 829 enum nl80211_channel_type ch_type)
729{ 830{
730 struct rtl_priv *rtlpriv = rtl_priv(hw); 831 struct rtl_priv *rtlpriv = rtl_priv(hw);
731 struct rtl_phy *rtlphy = &(rtlpriv->phy); 832 struct rtl_phy *rtlphy = &rtlpriv->phy;
732 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 833 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
733 u8 tmp_bw = rtlphy->current_chan_bw; 834 u8 tmp_bw = rtlphy->current_chan_bw;
734 835
@@ -736,20 +837,20 @@ void rtl8723ae_phy_set_bw_mode(struct ieee80211_hw *hw,
736 return; 837 return;
737 rtlphy->set_bwmode_inprogress = true; 838 rtlphy->set_bwmode_inprogress = true;
738 if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) { 839 if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
739 rtl8723ae_phy_set_bw_mode_callback(hw); 840 rtl8723e_phy_set_bw_mode_callback(hw);
740 } else { 841 } else {
741 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 842 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
742 "FALSE driver sleep or unload\n"); 843 "false driver sleep or unload\n");
743 rtlphy->set_bwmode_inprogress = false; 844 rtlphy->set_bwmode_inprogress = false;
744 rtlphy->current_chan_bw = tmp_bw; 845 rtlphy->current_chan_bw = tmp_bw;
745 } 846 }
746} 847}
747 848
748void rtl8723ae_phy_sw_chnl_callback(struct ieee80211_hw *hw) 849void rtl8723e_phy_sw_chnl_callback(struct ieee80211_hw *hw)
749{ 850{
750 struct rtl_priv *rtlpriv = rtl_priv(hw); 851 struct rtl_priv *rtlpriv = rtl_priv(hw);
751 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 852 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
752 struct rtl_phy *rtlphy = &(rtlpriv->phy); 853 struct rtl_phy *rtlphy = &rtlpriv->phy;
753 u32 delay; 854 u32 delay;
754 855
755 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, 856 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
@@ -759,7 +860,7 @@ void rtl8723ae_phy_sw_chnl_callback(struct ieee80211_hw *hw)
759 do { 860 do {
760 if (!rtlphy->sw_chnl_inprogress) 861 if (!rtlphy->sw_chnl_inprogress)
761 break; 862 break;
762 if (!_phy_sw_chnl_step_by_step 863 if (!_rtl8723e_phy_sw_chnl_step_by_step
763 (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage, 864 (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage,
764 &rtlphy->sw_chnl_step, &delay)) { 865 &rtlphy->sw_chnl_step, &delay)) {
765 if (delay > 0) 866 if (delay > 0)
@@ -771,13 +872,13 @@ void rtl8723ae_phy_sw_chnl_callback(struct ieee80211_hw *hw)
771 } 872 }
772 break; 873 break;
773 } while (true); 874 } while (true);
774 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n"); 875 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "\n");
775} 876}
776 877
777u8 rtl8723ae_phy_sw_chnl(struct ieee80211_hw *hw) 878u8 rtl8723e_phy_sw_chnl(struct ieee80211_hw *hw)
778{ 879{
779 struct rtl_priv *rtlpriv = rtl_priv(hw); 880 struct rtl_priv *rtlpriv = rtl_priv(hw);
780 struct rtl_phy *rtlphy = &(rtlpriv->phy); 881 struct rtl_phy *rtlphy = &rtlpriv->phy;
781 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 882 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
782 883
783 if (rtlphy->sw_chnl_inprogress) 884 if (rtlphy->sw_chnl_inprogress)
@@ -790,9 +891,9 @@ u8 rtl8723ae_phy_sw_chnl(struct ieee80211_hw *hw)
790 rtlphy->sw_chnl_stage = 0; 891 rtlphy->sw_chnl_stage = 0;
791 rtlphy->sw_chnl_step = 0; 892 rtlphy->sw_chnl_step = 0;
792 if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) { 893 if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
793 rtl8723ae_phy_sw_chnl_callback(hw); 894 rtl8723e_phy_sw_chnl_callback(hw);
794 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD, 895 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
795 "sw_chnl_inprogress false schedule workitem\n"); 896 "sw_chnl_inprogress false schdule workitem\n");
796 rtlphy->sw_chnl_inprogress = false; 897 rtlphy->sw_chnl_inprogress = false;
797 } else { 898 } else {
798 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD, 899 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
@@ -802,31 +903,33 @@ u8 rtl8723ae_phy_sw_chnl(struct ieee80211_hw *hw)
802 return 1; 903 return 1;
803} 904}
804 905
805static void _rtl8723ae_phy_sw_rf_seting(struct ieee80211_hw *hw, u8 channel) 906static void _rtl8723e_phy_sw_rf_seting(struct ieee80211_hw *hw, u8 channel)
806{ 907{
807 struct rtl_priv *rtlpriv = rtl_priv(hw); 908 struct rtl_priv *rtlpriv = rtl_priv(hw);
808 struct rtl_phy *rtlphy = &(rtlpriv->phy); 909 struct rtl_phy *rtlphy = &rtlpriv->phy;
809 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 910 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
810 911
811 if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version)) { 912 if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version)) {
812 if (channel == 6 && rtlphy->current_chan_bw == 913 if (channel == 6 && rtlphy->current_chan_bw ==
813 HT_CHANNEL_WIDTH_20) 914 HT_CHANNEL_WIDTH_20)
814 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 915 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1,
815 0x00255); 916 MASKDWORD, 0x00255);
816 else{ 917 else{
817 u32 backupRF0x1A = (u32)rtl_get_rfreg(hw, RF90_PATH_A, 918 u32 backuprf0x1a = (u32)rtl_get_rfreg(hw,
818 RF_RX_G1, RFREG_OFFSET_MASK); 919 RF90_PATH_A, RF_RX_G1,
819 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 920 RFREG_OFFSET_MASK);
820 backupRF0x1A); 921 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1,
922 MASKDWORD, backuprf0x1a);
821 } 923 }
822 } 924 }
823} 925}
824 926
825static bool _phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, u8 channel, 927static bool _rtl8723e_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
826 u8 *stage, u8 *step, u32 *delay) 928 u8 channel, u8 *stage, u8 *step,
929 u32 *delay)
827{ 930{
828 struct rtl_priv *rtlpriv = rtl_priv(hw); 931 struct rtl_priv *rtlpriv = rtl_priv(hw);
829 struct rtl_phy *rtlphy = &(rtlpriv->phy); 932 struct rtl_phy *rtlphy = &rtlpriv->phy;
830 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT]; 933 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
831 u32 precommoncmdcnt; 934 u32 precommoncmdcnt;
832 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT]; 935 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
@@ -839,14 +942,16 @@ static bool _phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, u8 channel,
839 942
840 precommoncmdcnt = 0; 943 precommoncmdcnt = 0;
841 rtl8723_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++, 944 rtl8723_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
842 MAX_PRECMD_CNT, CMDID_SET_TXPOWEROWER_LEVEL, 945 MAX_PRECMD_CNT,
843 0, 0, 0); 946 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
844 rtl8723_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++, 947 rtl8723_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
845 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0); 948 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
949
846 postcommoncmdcnt = 0; 950 postcommoncmdcnt = 0;
847 951
848 rtl8723_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++, 952 rtl8723_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
849 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0); 953 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
954
850 rfdependcmdcnt = 0; 955 rfdependcmdcnt = 0;
851 956
852 RT_ASSERT((channel >= 1 && channel <= 14), 957 RT_ASSERT((channel >= 1 && channel <= 14),
@@ -854,10 +959,11 @@ static bool _phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, u8 channel,
854 959
855 rtl8723_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++, 960 rtl8723_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
856 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG, 961 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
857 RF_CHNLBW, channel, 10); 962 RF_CHNLBW, channel, 10);
858 963
859 rtl8723_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++, 964 rtl8723_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
860 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0, 0); 965 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0,
966 0);
861 967
862 do { 968 do {
863 switch (*stage) { 969 switch (*stage) {
@@ -870,6 +976,10 @@ static bool _phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, u8 channel,
870 case 2: 976 case 2:
871 currentcmd = &postcommoncmd[*step]; 977 currentcmd = &postcommoncmd[*step];
872 break; 978 break;
979 default:
980 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
981 "Invalid 'stage' = %d, Check it!\n", *stage);
982 return true;
873 } 983 }
874 984
875 if (currentcmd->cmdid == CMDID_END) { 985 if (currentcmd->cmdid == CMDID_END) {
@@ -884,7 +994,7 @@ static bool _phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, u8 channel,
884 994
885 switch (currentcmd->cmdid) { 995 switch (currentcmd->cmdid) {
886 case CMDID_SET_TXPOWEROWER_LEVEL: 996 case CMDID_SET_TXPOWEROWER_LEVEL:
887 rtl8723ae_phy_set_txpower_level(hw, channel); 997 rtl8723e_phy_set_txpower_level(hw, channel);
888 break; 998 break;
889 case CMDID_WRITEPORT_ULONG: 999 case CMDID_WRITEPORT_ULONG:
890 rtl_write_dword(rtlpriv, currentcmd->para1, 1000 rtl_write_dword(rtlpriv, currentcmd->para1,
@@ -909,10 +1019,10 @@ static bool _phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, u8 channel,
909 RFREG_OFFSET_MASK, 1019 RFREG_OFFSET_MASK,
910 rtlphy->rfreg_chnlval[rfpath]); 1020 rtlphy->rfreg_chnlval[rfpath]);
911 } 1021 }
912 _rtl8723ae_phy_sw_rf_seting(hw, channel); 1022 _rtl8723e_phy_sw_rf_seting(hw, channel);
913 break; 1023 break;
914 default: 1024 default:
915 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1025 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
916 "switch case not process\n"); 1026 "switch case not process\n");
917 break; 1027 break;
918 } 1028 }
@@ -925,7 +1035,7 @@ static bool _phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, u8 channel,
925 return false; 1035 return false;
926} 1036}
927 1037
928static u8 _rtl8723ae_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb) 1038static u8 _rtl8723e_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb)
929{ 1039{
930 u32 reg_eac, reg_e94, reg_e9c, reg_ea4; 1040 u32 reg_eac, reg_e94, reg_e9c, reg_ea4;
931 u8 result = 0x00; 1041 u8 result = 0x00;
@@ -968,7 +1078,7 @@ static u8 _rtl8723ae_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb)
968 return result; 1078 return result;
969} 1079}
970 1080
971static u8 _rtl8723ae_phy_path_b_iqk(struct ieee80211_hw *hw) 1081static u8 _rtl8723e_phy_path_b_iqk(struct ieee80211_hw *hw)
972{ 1082{
973 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc; 1083 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
974 u8 result = 0x00; 1084 u8 result = 0x00;
@@ -995,8 +1105,8 @@ static u8 _rtl8723ae_phy_path_b_iqk(struct ieee80211_hw *hw)
995 return result; 1105 return result;
996} 1106}
997 1107
998static bool phy_simularity_comp(struct ieee80211_hw *hw, long result[][8], 1108static bool _rtl8723e_phy_simularity_compare(struct ieee80211_hw *hw,
999 u8 c1, u8 c2) 1109 long result[][8], u8 c1, u8 c2)
1000{ 1110{
1001 u32 i, j, diff, simularity_bitmap, bound; 1111 u32 i, j, diff, simularity_bitmap, bound;
1002 1112
@@ -1047,11 +1157,21 @@ static bool phy_simularity_comp(struct ieee80211_hw *hw, long result[][8],
1047 1157
1048} 1158}
1049 1159
1050static void _rtl8723ae_phy_iq_calibrate(struct ieee80211_hw *hw, 1160static void rtl8723_phy_save_adda_registers(struct ieee80211_hw *hw,
1051 long result[][8], u8 t, bool is2t) 1161 u32 *addareg, u32 *addabackup,
1162 u32 registernum)
1163{
1164 u32 i;
1165
1166 for (i = 0; i < registernum; i++)
1167 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);
1168}
1169
1170static void _rtl8723e_phy_iq_calibrate(struct ieee80211_hw *hw,
1171 long result[][8], u8 t, bool is2t)
1052{ 1172{
1053 struct rtl_priv *rtlpriv = rtl_priv(hw); 1173 struct rtl_priv *rtlpriv = rtl_priv(hw);
1054 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1174 struct rtl_phy *rtlphy = &rtlpriv->phy;
1055 u32 i; 1175 u32 i;
1056 u8 patha_ok, pathb_ok; 1176 u8 patha_ok, pathb_ok;
1057 u32 adda_reg[IQK_ADDA_REG_NUM] = { 1177 u32 adda_reg[IQK_ADDA_REG_NUM] = {
@@ -1060,22 +1180,28 @@ static void _rtl8723ae_phy_iq_calibrate(struct ieee80211_hw *hw,
1060 0xe88, 0xe8c, 0xed0, 0xed4, 1180 0xe88, 0xe8c, 0xed0, 0xed4,
1061 0xed8, 0xedc, 0xee0, 0xeec 1181 0xed8, 0xedc, 0xee0, 0xeec
1062 }; 1182 };
1183
1063 u32 iqk_mac_reg[IQK_MAC_REG_NUM] = { 1184 u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1064 0x522, 0x550, 0x551, 0x040 1185 0x522, 0x550, 0x551, 0x040
1065 }; 1186 };
1187
1066 const u32 retrycount = 2; 1188 const u32 retrycount = 2;
1067 1189
1190 u32 bbvalue;
1191
1068 if (t == 0) { 1192 if (t == 0) {
1069 rtl8723_save_adda_registers(hw, adda_reg, rtlphy->adda_backup, 1193 bbvalue = rtl_get_bbreg(hw, 0x800, MASKDWORD);
1070 16); 1194
1195 rtl8723_phy_save_adda_registers(hw, adda_reg,
1196 rtlphy->adda_backup, 16);
1071 rtl8723_phy_save_mac_registers(hw, iqk_mac_reg, 1197 rtl8723_phy_save_mac_registers(hw, iqk_mac_reg,
1072 rtlphy->iqk_mac_backup); 1198 rtlphy->iqk_mac_backup);
1073 } 1199 }
1074 rtl8723_phy_path_adda_on(hw, adda_reg, true, is2t); 1200 rtl8723_phy_path_adda_on(hw, adda_reg, true, is2t);
1075 if (t == 0) { 1201 if (t == 0) {
1076 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw, 1202 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
1077 RFPGA0_XA_HSSIPARAMETER1, 1203 RFPGA0_XA_HSSIPARAMETER1,
1078 BIT(8)); 1204 BIT(8));
1079 } 1205 }
1080 1206
1081 if (!rtlphy->rfpi_enable) 1207 if (!rtlphy->rfpi_enable)
@@ -1101,7 +1227,7 @@ static void _rtl8723ae_phy_iq_calibrate(struct ieee80211_hw *hw,
1101 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00); 1227 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
1102 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); 1228 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
1103 for (i = 0; i < retrycount; i++) { 1229 for (i = 0; i < retrycount; i++) {
1104 patha_ok = _rtl8723ae_phy_path_a_iqk(hw, is2t); 1230 patha_ok = _rtl8723e_phy_path_a_iqk(hw, is2t);
1105 if (patha_ok == 0x03) { 1231 if (patha_ok == 0x03) {
1106 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & 1232 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1107 0x3FF0000) >> 16; 1233 0x3FF0000) >> 16;
@@ -1115,7 +1241,8 @@ static void _rtl8723ae_phy_iq_calibrate(struct ieee80211_hw *hw,
1115 } else if (i == (retrycount - 1) && patha_ok == 0x01) 1241 } else if (i == (retrycount - 1) && patha_ok == 0x01)
1116 1242
1117 result[t][0] = (rtl_get_bbreg(hw, 0xe94, 1243 result[t][0] = (rtl_get_bbreg(hw, 0xe94,
1118 MASKDWORD) & 0x3FF0000) >> 16; 1244 MASKDWORD) & 0x3FF0000) >>
1245 16;
1119 result[t][1] = 1246 result[t][1] =
1120 (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 0x3FF0000) >> 16; 1247 (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 0x3FF0000) >> 16;
1121 1248
@@ -1125,11 +1252,12 @@ static void _rtl8723ae_phy_iq_calibrate(struct ieee80211_hw *hw,
1125 rtl8723_phy_path_a_standby(hw); 1252 rtl8723_phy_path_a_standby(hw);
1126 rtl8723_phy_path_adda_on(hw, adda_reg, false, is2t); 1253 rtl8723_phy_path_adda_on(hw, adda_reg, false, is2t);
1127 for (i = 0; i < retrycount; i++) { 1254 for (i = 0; i < retrycount; i++) {
1128 pathb_ok = _rtl8723ae_phy_path_b_iqk(hw); 1255 pathb_ok = _rtl8723e_phy_path_b_iqk(hw);
1129 if (pathb_ok == 0x03) { 1256 if (pathb_ok == 0x03) {
1130 result[t][4] = 1257 result[t][4] = (rtl_get_bbreg(hw,
1131 (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) & 1258 0xeb4,
1132 0x3FF0000) >> 16; 1259 MASKDWORD) &
1260 0x3FF0000) >> 16;
1133 result[t][5] = 1261 result[t][5] =
1134 (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & 1262 (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1135 0x3FF0000) >> 16; 1263 0x3FF0000) >> 16;
@@ -1141,9 +1269,10 @@ static void _rtl8723ae_phy_iq_calibrate(struct ieee80211_hw *hw,
1141 0x3FF0000) >> 16; 1269 0x3FF0000) >> 16;
1142 break; 1270 break;
1143 } else if (i == (retrycount - 1) && pathb_ok == 0x01) { 1271 } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1144 result[t][4] = 1272 result[t][4] = (rtl_get_bbreg(hw,
1145 (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) & 1273 0xeb4,
1146 0x3FF0000) >> 16; 1274 MASKDWORD) &
1275 0x3FF0000) >> 16;
1147 } 1276 }
1148 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & 1277 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1149 0x3FF0000) >> 16; 1278 0x3FF0000) >> 16;
@@ -1166,11 +1295,11 @@ static void _rtl8723ae_phy_iq_calibrate(struct ieee80211_hw *hw,
1166 } 1295 }
1167} 1296}
1168 1297
1169static void _rtl8723ae_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t) 1298static void _rtl8723e_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
1170{ 1299{
1171 struct rtl_priv *rtlpriv = rtl_priv(hw);
1172 u8 tmpreg; 1300 u8 tmpreg;
1173 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal; 1301 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
1302 struct rtl_priv *rtlpriv = rtl_priv(hw);
1174 1303
1175 tmpreg = rtl_read_byte(rtlpriv, 0xd03); 1304 tmpreg = rtl_read_byte(rtlpriv, 0xd03);
1176 1305
@@ -1211,14 +1340,14 @@ static void _rtl8723ae_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
1211 } 1340 }
1212} 1341}
1213 1342
1214static void _rtl8723ae_phy_set_rfpath_switch(struct ieee80211_hw *hw, 1343static void _rtl8723e_phy_set_rfpath_switch(struct ieee80211_hw *hw,
1215 bool bmain, bool is2t) 1344 bool bmain, bool is2t)
1216{ 1345{
1217 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1346 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1218 1347
1219 if (is_hal_stop(rtlhal)) { 1348 if (is_hal_stop(rtlhal)) {
1220 rtl_set_bbreg(hw, REG_LEDCFG0, BIT(23), 0x01); 1349 rtl_set_bbreg(hw, REG_LEDCFG0, BIT(23), 0x01);
1221 rtl_set_bbreg(hw, rFPGA0_XAB_RFPARAMETER, BIT(13), 0x01); 1350 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
1222 } 1351 }
1223 if (is2t) { 1352 if (is2t) {
1224 if (bmain) 1353 if (bmain)
@@ -1234,21 +1363,23 @@ static void _rtl8723ae_phy_set_rfpath_switch(struct ieee80211_hw *hw,
1234 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x1); 1363 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x1);
1235 1364
1236 } 1365 }
1366
1237} 1367}
1238 1368
1239#undef IQK_ADDA_REG_NUM 1369#undef IQK_ADDA_REG_NUM
1240#undef IQK_DELAY_TIME 1370#undef IQK_DELAY_TIME
1241 1371
1242void rtl8723ae_phy_iq_calibrate(struct ieee80211_hw *hw, bool recovery) 1372void rtl8723e_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
1243{ 1373{
1244 struct rtl_priv *rtlpriv = rtl_priv(hw); 1374 struct rtl_priv *rtlpriv = rtl_priv(hw);
1245 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1375 struct rtl_phy *rtlphy = &rtlpriv->phy;
1376
1246 long result[4][8]; 1377 long result[4][8];
1247 u8 i, final_candidate; 1378 u8 i, final_candidate;
1248 bool patha_ok, pathb_ok; 1379 bool b_patha_ok, b_pathb_ok;
1249 long reg_e94, reg_e9c, reg_ea4, reg_eb4, reg_ebc, reg_tmp = 0; 1380 long reg_e94, reg_e9c, reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4,
1381 reg_ecc, reg_tmp = 0;
1250 bool is12simular, is13simular, is23simular; 1382 bool is12simular, is13simular, is23simular;
1251 bool start_conttx = false, singletone = false;
1252 u32 iqk_bb_reg[10] = { 1383 u32 iqk_bb_reg[10] = {
1253 ROFDM0_XARXIQIMBALANCE, 1384 ROFDM0_XARXIQIMBALANCE,
1254 ROFDM0_XBRXIQIMBALANCE, 1385 ROFDM0_XBRXIQIMBALANCE,
@@ -1262,13 +1393,12 @@ void rtl8723ae_phy_iq_calibrate(struct ieee80211_hw *hw, bool recovery)
1262 ROFDM0_RXIQEXTANTA 1393 ROFDM0_RXIQEXTANTA
1263 }; 1394 };
1264 1395
1265 if (recovery) { 1396 if (b_recovery) {
1266 rtl8723_phy_reload_adda_registers(hw, iqk_bb_reg, 1397 rtl8723_phy_reload_adda_registers(hw,
1398 iqk_bb_reg,
1267 rtlphy->iqk_bb_backup, 10); 1399 rtlphy->iqk_bb_backup, 10);
1268 return; 1400 return;
1269 } 1401 }
1270 if (start_conttx || singletone)
1271 return;
1272 for (i = 0; i < 8; i++) { 1402 for (i = 0; i < 8; i++) {
1273 result[0][i] = 0; 1403 result[0][i] = 0;
1274 result[1][i] = 0; 1404 result[1][i] = 0;
@@ -1276,30 +1406,33 @@ void rtl8723ae_phy_iq_calibrate(struct ieee80211_hw *hw, bool recovery)
1276 result[3][i] = 0; 1406 result[3][i] = 0;
1277 } 1407 }
1278 final_candidate = 0xff; 1408 final_candidate = 0xff;
1279 patha_ok = false; 1409 b_patha_ok = false;
1280 pathb_ok = false; 1410 b_pathb_ok = false;
1281 is12simular = false; 1411 is12simular = false;
1282 is23simular = false; 1412 is23simular = false;
1283 is13simular = false; 1413 is13simular = false;
1284 for (i = 0; i < 3; i++) { 1414 for (i = 0; i < 3; i++) {
1285 _rtl8723ae_phy_iq_calibrate(hw, result, i, false); 1415 _rtl8723e_phy_iq_calibrate(hw, result, i, false);
1286 if (i == 1) { 1416 if (i == 1) {
1287 is12simular = phy_simularity_comp(hw, result, 0, 1); 1417 is12simular =
1418 _rtl8723e_phy_simularity_compare(hw, result, 0, 1);
1288 if (is12simular) { 1419 if (is12simular) {
1289 final_candidate = 0; 1420 final_candidate = 0;
1290 break; 1421 break;
1291 } 1422 }
1292 } 1423 }
1293 if (i == 2) { 1424 if (i == 2) {
1294 is13simular = phy_simularity_comp(hw, result, 0, 2); 1425 is13simular =
1426 _rtl8723e_phy_simularity_compare(hw, result, 0, 2);
1295 if (is13simular) { 1427 if (is13simular) {
1296 final_candidate = 0; 1428 final_candidate = 0;
1297 break; 1429 break;
1298 } 1430 }
1299 is23simular = phy_simularity_comp(hw, result, 1, 2); 1431 is23simular =
1300 if (is23simular) { 1432 _rtl8723e_phy_simularity_compare(hw, result, 1, 2);
1433 if (is23simular)
1301 final_candidate = 1; 1434 final_candidate = 1;
1302 } else { 1435 else {
1303 for (i = 0; i < 8; i++) 1436 for (i = 0; i < 8; i++)
1304 reg_tmp += result[3][i]; 1437 reg_tmp += result[3][i];
1305 1438
@@ -1314,50 +1447,54 @@ void rtl8723ae_phy_iq_calibrate(struct ieee80211_hw *hw, bool recovery)
1314 reg_e94 = result[i][0]; 1447 reg_e94 = result[i][0];
1315 reg_e9c = result[i][1]; 1448 reg_e9c = result[i][1];
1316 reg_ea4 = result[i][2]; 1449 reg_ea4 = result[i][2];
1450 reg_eac = result[i][3];
1317 reg_eb4 = result[i][4]; 1451 reg_eb4 = result[i][4];
1318 reg_ebc = result[i][5]; 1452 reg_ebc = result[i][5];
1453 reg_ec4 = result[i][6];
1454 reg_ecc = result[i][7];
1319 } 1455 }
1320 if (final_candidate != 0xff) { 1456 if (final_candidate != 0xff) {
1321 rtlphy->reg_e94 = reg_e94 = result[final_candidate][0]; 1457 rtlphy->reg_e94 = reg_e94 = result[final_candidate][0];
1322 rtlphy->reg_e9c = reg_e9c = result[final_candidate][1]; 1458 rtlphy->reg_e9c = reg_e9c = result[final_candidate][1];
1323 reg_ea4 = result[final_candidate][2]; 1459 reg_ea4 = result[final_candidate][2];
1460 reg_eac = result[final_candidate][3];
1324 rtlphy->reg_eb4 = reg_eb4 = result[final_candidate][4]; 1461 rtlphy->reg_eb4 = reg_eb4 = result[final_candidate][4];
1325 rtlphy->reg_ebc = reg_ebc = result[final_candidate][5]; 1462 rtlphy->reg_ebc = reg_ebc = result[final_candidate][5];
1326 patha_ok = pathb_ok = true; 1463 reg_ec4 = result[final_candidate][6];
1464 reg_ecc = result[final_candidate][7];
1465 b_patha_ok = true;
1466 b_pathb_ok = true;
1327 } else { 1467 } else {
1328 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100; 1468 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100;
1329 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0; 1469 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0;
1330 } 1470 }
1331 if (reg_e94 != 0) /*&&(reg_ea4 != 0) */ 1471 if (reg_e94 != 0)
1332 rtl8723_phy_path_a_fill_iqk_matrix(hw, patha_ok, result, 1472 rtl8723_phy_path_a_fill_iqk_matrix(hw, b_patha_ok, result,
1333 final_candidate, 1473 final_candidate,
1334 (reg_ea4 == 0)); 1474 (reg_ea4 == 0));
1335 rtl8723_save_adda_registers(hw, iqk_bb_reg, rtlphy->iqk_bb_backup, 10); 1475 rtl8723_phy_save_adda_registers(hw, iqk_bb_reg,
1476 rtlphy->iqk_bb_backup, 10);
1336} 1477}
1337 1478
1338void rtl8723ae_phy_lc_calibrate(struct ieee80211_hw *hw) 1479void rtl8723e_phy_lc_calibrate(struct ieee80211_hw *hw)
1339{ 1480{
1340 bool start_conttx = false, singletone = false; 1481 _rtl8723e_phy_lc_calibrate(hw, false);
1341
1342 if (start_conttx || singletone)
1343 return;
1344 _rtl8723ae_phy_lc_calibrate(hw, false);
1345} 1482}
1346 1483
1347void rtl8723ae_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain) 1484void rtl8723e_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
1348{ 1485{
1349 _rtl8723ae_phy_set_rfpath_switch(hw, bmain, false); 1486 _rtl8723e_phy_set_rfpath_switch(hw, bmain, false);
1350} 1487}
1351 1488
1352bool rtl8723ae_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype) 1489bool rtl8723e_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
1353{ 1490{
1354 struct rtl_priv *rtlpriv = rtl_priv(hw); 1491 struct rtl_priv *rtlpriv = rtl_priv(hw);
1355 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1492 struct rtl_phy *rtlphy = &rtlpriv->phy;
1356 bool postprocessing = false; 1493 bool postprocessing = false;
1357 1494
1358 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 1495 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1359 "-->IO Cmd(%#x), set_io_inprogress(%d)\n", 1496 "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
1360 iotype, rtlphy->set_io_inprogress); 1497 iotype, rtlphy->set_io_inprogress);
1361 do { 1498 do {
1362 switch (iotype) { 1499 switch (iotype) {
1363 case IO_CMD_RESUME_DM_BY_SCAN: 1500 case IO_CMD_RESUME_DM_BY_SCAN:
@@ -1365,13 +1502,13 @@ bool rtl8723ae_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
1365 "[IO CMD] Resume DM after scan.\n"); 1502 "[IO CMD] Resume DM after scan.\n");
1366 postprocessing = true; 1503 postprocessing = true;
1367 break; 1504 break;
1368 case IO_CMD_PAUSE_DM_BY_SCAN: 1505 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
1369 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 1506 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1370 "[IO CMD] Pause DM before scan.\n"); 1507 "[IO CMD] Pause DM before scan.\n");
1371 postprocessing = true; 1508 postprocessing = true;
1372 break; 1509 break;
1373 default: 1510 default:
1374 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1511 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1375 "switch case not process\n"); 1512 "switch case not process\n");
1376 break; 1513 break;
1377 } 1514 }
@@ -1382,42 +1519,42 @@ bool rtl8723ae_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
1382 } else { 1519 } else {
1383 return false; 1520 return false;
1384 } 1521 }
1385 rtl8723ae_phy_set_io(hw); 1522 rtl8723e_phy_set_io(hw);
1386 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "<--IO Type(%#x)\n", iotype); 1523 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "IO Type(%#x)\n", iotype);
1387 return true; 1524 return true;
1388} 1525}
1389 1526
1390static void rtl8723ae_phy_set_io(struct ieee80211_hw *hw) 1527static void rtl8723e_phy_set_io(struct ieee80211_hw *hw)
1391{ 1528{
1392 struct rtl_priv *rtlpriv = rtl_priv(hw); 1529 struct rtl_priv *rtlpriv = rtl_priv(hw);
1393 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1530 struct rtl_phy *rtlphy = &rtlpriv->phy;
1394 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 1531 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
1395 1532
1396 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 1533 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1397 "--->Cmd(%#x), set_io_inprogress(%d)\n", 1534 "--->Cmd(%#x), set_io_inprogress(%d)\n",
1398 rtlphy->current_io_type, rtlphy->set_io_inprogress); 1535 rtlphy->current_io_type, rtlphy->set_io_inprogress);
1399 switch (rtlphy->current_io_type) { 1536 switch (rtlphy->current_io_type) {
1400 case IO_CMD_RESUME_DM_BY_SCAN: 1537 case IO_CMD_RESUME_DM_BY_SCAN:
1401 dm_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1; 1538 dm_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;
1402 rtl8723ae_dm_write_dig(hw); 1539 rtl8723e_dm_write_dig(hw);
1403 rtl8723ae_phy_set_txpower_level(hw, rtlphy->current_channel); 1540 rtl8723e_phy_set_txpower_level(hw, rtlphy->current_channel);
1404 break; 1541 break;
1405 case IO_CMD_PAUSE_DM_BY_SCAN: 1542 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
1406 rtlphy->initgain_backup.xaagccore1 = dm_digtable->cur_igvalue; 1543 rtlphy->initgain_backup.xaagccore1 = dm_digtable->cur_igvalue;
1407 dm_digtable->cur_igvalue = 0x17; 1544 dm_digtable->cur_igvalue = 0x17;
1408 rtl8723ae_dm_write_dig(hw); 1545 rtl8723e_dm_write_dig(hw);
1409 break; 1546 break;
1410 default: 1547 default:
1411 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1548 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1412 "switch case not process\n"); 1549 "switch case not process\n");
1413 break; 1550 break;
1414 } 1551 }
1415 rtlphy->set_io_inprogress = false; 1552 rtlphy->set_io_inprogress = false;
1416 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 1553 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1417 "<---(%#x)\n", rtlphy->current_io_type); 1554 "(%#x)\n", rtlphy->current_io_type);
1418} 1555}
1419 1556
1420static void rtl8723ae_phy_set_rf_on(struct ieee80211_hw *hw) 1557static void rtl8723e_phy_set_rf_on(struct ieee80211_hw *hw)
1421{ 1558{
1422 struct rtl_priv *rtlpriv = rtl_priv(hw); 1559 struct rtl_priv *rtlpriv = rtl_priv(hw);
1423 1560
@@ -1429,11 +1566,11 @@ static void rtl8723ae_phy_set_rf_on(struct ieee80211_hw *hw)
1429 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 1566 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1430} 1567}
1431 1568
1432static void _rtl8723ae_phy_set_rf_sleep(struct ieee80211_hw *hw) 1569static void _rtl8723e_phy_set_rf_sleep(struct ieee80211_hw *hw)
1433{ 1570{
1434 struct rtl_priv *rtlpriv = rtl_priv(hw);
1435 u32 u4b_tmp; 1571 u32 u4b_tmp;
1436 u8 delay = 5; 1572 u8 delay = 5;
1573 struct rtl_priv *rtlpriv = rtl_priv(hw);
1437 1574
1438 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 1575 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1439 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); 1576 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
@@ -1459,45 +1596,47 @@ static void _rtl8723ae_phy_set_rf_sleep(struct ieee80211_hw *hw)
1459 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22); 1596 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
1460} 1597}
1461 1598
1462static bool _rtl8723ae_phy_set_rf_power_state(struct ieee80211_hw *hw, 1599static bool _rtl8723e_phy_set_rf_power_state(struct ieee80211_hw *hw,
1463 enum rf_pwrstate rfpwr_state) 1600 enum rf_pwrstate rfpwr_state)
1464{ 1601{
1465 struct rtl_priv *rtlpriv = rtl_priv(hw); 1602 struct rtl_priv *rtlpriv = rtl_priv(hw);
1466 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1603 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1467 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1604 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1468 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1605 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1469 struct rtl8192_tx_ring *ring = NULL;
1470 bool bresult = true; 1606 bool bresult = true;
1471 u8 i, queue_id; 1607 u8 i, queue_id;
1608 struct rtl8192_tx_ring *ring = NULL;
1472 1609
1473 switch (rfpwr_state) { 1610 switch (rfpwr_state) {
1474 case ERFON: 1611 case ERFON:
1475 if ((ppsc->rfpwr_state == ERFOFF) && 1612 if ((ppsc->rfpwr_state == ERFOFF) &&
1476 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) { 1613 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
1477 bool rtstatus; 1614 bool rtstatus;
1478 u32 InitializeCount = 0; 1615 u32 initializecount = 0;
1616
1479 do { 1617 do {
1480 InitializeCount++; 1618 initializecount++;
1481 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 1619 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
1482 "IPS Set eRf nic enable\n"); 1620 "IPS Set eRf nic enable\n");
1483 rtstatus = rtl_ps_enable_nic(hw); 1621 rtstatus = rtl_ps_enable_nic(hw);
1484 } while ((rtstatus != true) && (InitializeCount < 10)); 1622 } while (!rtstatus && (initializecount < 10));
1485 RT_CLEAR_PS_LEVEL(ppsc, 1623 RT_CLEAR_PS_LEVEL(ppsc,
1486 RT_RF_OFF_LEVL_HALT_NIC); 1624 RT_RF_OFF_LEVL_HALT_NIC);
1487 } else { 1625 } else {
1488 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 1626 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
1489 "Set ERFON sleeped:%d ms\n", 1627 "Set ERFON sleeped:%d ms\n",
1490 jiffies_to_msecs(jiffies - 1628 jiffies_to_msecs(jiffies -
1491 ppsc->last_sleep_jiffies)); 1629 ppsc->
1630 last_sleep_jiffies));
1492 ppsc->last_awake_jiffies = jiffies; 1631 ppsc->last_awake_jiffies = jiffies;
1493 rtl8723ae_phy_set_rf_on(hw); 1632 rtl8723e_phy_set_rf_on(hw);
1494 } 1633 }
1495 if (mac->link_state == MAC80211_LINKED) { 1634 if (mac->link_state == MAC80211_LINKED) {
1496 rtlpriv->cfg->ops->led_control(hw, 1635 rtlpriv->cfg->ops->led_control(hw,
1497 LED_CTL_LINK); 1636 LED_CTL_LINK);
1498 } else { 1637 } else {
1499 rtlpriv->cfg->ops->led_control(hw, 1638 rtlpriv->cfg->ops->led_control(hw,
1500 LED_CTL_NO_LINK); 1639 LED_CTL_NO_LINK);
1501 } 1640 }
1502 break; 1641 break;
1503 case ERFOFF: 1642 case ERFOFF:
@@ -1509,10 +1648,10 @@ static bool _rtl8723ae_phy_set_rf_power_state(struct ieee80211_hw *hw,
1509 } else { 1648 } else {
1510 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) { 1649 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
1511 rtlpriv->cfg->ops->led_control(hw, 1650 rtlpriv->cfg->ops->led_control(hw,
1512 LED_CTL_NO_LINK); 1651 LED_CTL_NO_LINK);
1513 } else { 1652 } else {
1514 rtlpriv->cfg->ops->led_control(hw, 1653 rtlpriv->cfg->ops->led_control(hw,
1515 LED_CTL_POWER_OFF); 1654 LED_CTL_POWER_OFF);
1516 } 1655 }
1517 } 1656 }
1518 break; 1657 break;
@@ -1522,7 +1661,8 @@ static bool _rtl8723ae_phy_set_rf_power_state(struct ieee80211_hw *hw,
1522 for (queue_id = 0, i = 0; 1661 for (queue_id = 0, i = 0;
1523 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) { 1662 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
1524 ring = &pcipriv->dev.tx_ring[queue_id]; 1663 ring = &pcipriv->dev.tx_ring[queue_id];
1525 if (skb_queue_len(&ring->queue) == 0) { 1664 if (queue_id == BEACON_QUEUE ||
1665 skb_queue_len(&ring->queue) == 0) {
1526 queue_id++; 1666 queue_id++;
1527 continue; 1667 continue;
1528 } else { 1668 } else {
@@ -1536,22 +1676,23 @@ static bool _rtl8723ae_phy_set_rf_power_state(struct ieee80211_hw *hw,
1536 } 1676 }
1537 if (i >= MAX_DOZE_WAITING_TIMES_9x) { 1677 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
1538 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1678 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1539 "\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n", 1679 "ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
1540 MAX_DOZE_WAITING_TIMES_9x, 1680 MAX_DOZE_WAITING_TIMES_9x,
1541 queue_id, 1681 queue_id,
1542 skb_queue_len(&ring->queue)); 1682 skb_queue_len(&ring->queue));
1543 break; 1683 break;
1544 } 1684 }
1545 } 1685 }
1546 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 1686 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
1547 "Set ERFSLEEP awaked:%d ms\n", 1687 "Set ERFSLEEP awaked:%d ms\n",
1548 jiffies_to_msecs(jiffies - ppsc->last_awake_jiffies)); 1688 jiffies_to_msecs(jiffies -
1689 ppsc->last_awake_jiffies));
1549 ppsc->last_sleep_jiffies = jiffies; 1690 ppsc->last_sleep_jiffies = jiffies;
1550 _rtl8723ae_phy_set_rf_sleep(hw); 1691 _rtl8723e_phy_set_rf_sleep(hw);
1551 break; 1692 break;
1552 default: 1693 default:
1553 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1694 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1554 "switch case not processed\n"); 1695 "switch case not process\n");
1555 bresult = false; 1696 bresult = false;
1556 break; 1697 break;
1557 } 1698 }
@@ -1560,14 +1701,15 @@ static bool _rtl8723ae_phy_set_rf_power_state(struct ieee80211_hw *hw,
1560 return bresult; 1701 return bresult;
1561} 1702}
1562 1703
1563bool rtl8723ae_phy_set_rf_power_state(struct ieee80211_hw *hw, 1704bool rtl8723e_phy_set_rf_power_state(struct ieee80211_hw *hw,
1564 enum rf_pwrstate rfpwr_state) 1705 enum rf_pwrstate rfpwr_state)
1565{ 1706{
1566 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1707 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1708
1567 bool bresult = false; 1709 bool bresult = false;
1568 1710
1569 if (rfpwr_state == ppsc->rfpwr_state) 1711 if (rfpwr_state == ppsc->rfpwr_state)
1570 return bresult; 1712 return bresult;
1571 bresult = _rtl8723ae_phy_set_rf_power_state(hw, rfpwr_state); 1713 bresult = _rtl8723e_phy_set_rf_power_state(hw, rfpwr_state);
1572 return bresult; 1714 return bresult;
1573} 1715}
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/phy.h b/drivers/net/wireless/rtlwifi/rtl8723ae/phy.h
index cd43139ed332..b85f5c7c5c01 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/phy.h
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/phy.h
@@ -11,10 +11,6 @@
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details. 12 * more details.
13 * 13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the 14 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE. 15 * file called LICENSE.
20 * 16 *
@@ -39,6 +35,7 @@
39#define RT_CANNOT_IO(hw) false 35#define RT_CANNOT_IO(hw) false
40#define HIGHPOWER_RADIOA_ARRAYLEN 22 36#define HIGHPOWER_RADIOA_ARRAYLEN 22
41 37
38#define IQK_ADDA_REG_NUM 16
42#define MAX_TOLERANCE 5 39#define MAX_TOLERANCE 5
43#define IQK_DELAY_TIME 1 40#define IQK_DELAY_TIME 1
44 41
@@ -49,12 +46,15 @@
49 46
50#define LOOP_LIMIT 5 47#define LOOP_LIMIT 5
51#define MAX_STALL_TIME 50 48#define MAX_STALL_TIME 50
52#define AntennaDiversityValue 0x80 49#define ANTENNADIVERSITYVALUE 0x80
53#define MAX_TXPWR_IDX_NMODE_92S 63 50#define MAX_TXPWR_IDX_NMODE_92S 63
54#define Reset_Cnt_Limit 3 51#define Reset_Cnt_Limit 3
55 52
53#define IQK_ADDA_REG_NUM 16
56#define IQK_MAC_REG_NUM 4 54#define IQK_MAC_REG_NUM 4
57 55
56#define IQK_DELAY_TIME 1
57
58#define RF6052_MAX_PATH 2 58#define RF6052_MAX_PATH 2
59 59
60#define CT_OFFSET_MAC_ADDR 0X16 60#define CT_OFFSET_MAC_ADDR 0X16
@@ -166,36 +166,37 @@ struct tx_power_struct {
166 u32 mcs_original_offset[4][16]; 166 u32 mcs_original_offset[4][16];
167}; 167};
168 168
169u32 rtl8723ae_phy_query_rf_reg(struct ieee80211_hw *hw, 169u32 rtl8723e_phy_query_rf_reg(struct ieee80211_hw *hw,
170 enum radio_path rfpath, u32 regaddr,
171 u32 bitmask);
172void rtl8723ae_phy_set_rf_reg(struct ieee80211_hw *hw,
173 enum radio_path rfpath, u32 regaddr, 170 enum radio_path rfpath, u32 regaddr,
174 u32 bitmask, u32 data); 171 u32 bitmask);
175bool rtl8723ae_phy_mac_config(struct ieee80211_hw *hw); 172void rtl8723e_phy_set_rf_reg(struct ieee80211_hw *hw,
176bool rtl8723ae_phy_bb_config(struct ieee80211_hw *hw); 173 enum radio_path rfpath, u32 regaddr,
177bool rtl8723ae_phy_rf_config(struct ieee80211_hw *hw); 174 u32 bitmask, u32 data);
175bool rtl8723e_phy_mac_config(struct ieee80211_hw *hw);
176bool rtl8723e_phy_bb_config(struct ieee80211_hw *hw);
177bool rtl8723e_phy_rf_config(struct ieee80211_hw *hw);
178bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw *hw, 178bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw *hw,
179 enum radio_path rfpath); 179 enum radio_path rfpath);
180void rtl8723ae_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw); 180void rtl8723e_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
181void rtl8723ae_phy_get_txpower_level(struct ieee80211_hw *hw, 181void rtl8723e_phy_get_txpower_level(struct ieee80211_hw *hw,
182 long *powerlevel); 182 long *powerlevel);
183void rtl8723ae_phy_set_txpower_level(struct ieee80211_hw *hw, 183void rtl8723e_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
184 u8 channel); 184bool rtl8723e_phy_update_txpower_dbm(struct ieee80211_hw *hw,
185bool rtl8723ae_phy_update_txpower_dbm(struct ieee80211_hw *hw, 185 long power_indbm);
186 long power_indbm); 186void rtl8723e_phy_scan_operation_backup(struct ieee80211_hw *hw,
187void rtl8723ae_phy_set_bw_mode_callback(struct ieee80211_hw *hw); 187 u8 operation);
188void rtl8723ae_phy_set_bw_mode(struct ieee80211_hw *hw, 188void rtl8723e_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
189 enum nl80211_channel_type ch_type); 189void rtl8723e_phy_set_bw_mode(struct ieee80211_hw *hw,
190void rtl8723ae_phy_sw_chnl_callback(struct ieee80211_hw *hw); 190 enum nl80211_channel_type ch_type);
191u8 rtl8723ae_phy_sw_chnl(struct ieee80211_hw *hw); 191void rtl8723e_phy_sw_chnl_callback(struct ieee80211_hw *hw);
192void rtl8723ae_phy_iq_calibrate(struct ieee80211_hw *hw, bool recovery); 192u8 rtl8723e_phy_sw_chnl(struct ieee80211_hw *hw);
193void rtl8723ae_phy_lc_calibrate(struct ieee80211_hw *hw); 193void rtl8723e_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
194void rtl8723ae_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain); 194void rtl8723e_phy_lc_calibrate(struct ieee80211_hw *hw);
195bool rtl8723ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, 195void rtl8723e_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
196 enum radio_path rfpath); 196bool rtl8723e_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
197bool rtl8723ae_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype); 197 enum radio_path rfpath);
198bool rtl8723ae_phy_set_rf_power_state(struct ieee80211_hw *hw, 198bool rtl8723e_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
199 enum rf_pwrstate rfpwr_state); 199bool rtl8723e_phy_set_rf_power_state(struct ieee80211_hw *hw,
200 enum rf_pwrstate rfpwr_state);
200 201
201#endif 202#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/pwrseq.c b/drivers/net/wireless/rtlwifi/rtl8723ae/pwrseq.c
index f907d7fd1ea4..2f7f81af8a55 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/pwrseq.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/pwrseq.c
@@ -11,10 +11,6 @@
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details. 12 * more details.
13 * 13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the 14 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE. 15 * file called LICENSE.
20 * 16 *
@@ -30,80 +26,87 @@
30#include "../pwrseqcmd.h" 26#include "../pwrseqcmd.h"
31#include "pwrseq.h" 27#include "pwrseq.h"
32 28
33/* drivers should parse arrays below and do the corresponding actions */ 29/* drivers should parse below arrays and do the corresponding actions */
34
35/*3 Power on Array*/ 30/*3 Power on Array*/
36struct wlan_pwr_cfg rtl8723A_power_on_flow[RTL8723A_TRANS_CARDEMU_TO_ACT_STPS 31struct wlan_pwr_cfg rtl8723A_power_on_flow
37 + RTL8723A_TRANS_END_STPS] = { 32 [RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS +
38 RTL8723A_TRANS_CARDEMU_TO_ACT, 33 RTL8723A_TRANS_END_STEPS] = {
34 RTL8723A_TRANS_CARDEMU_TO_ACT
39 RTL8723A_TRANS_END 35 RTL8723A_TRANS_END
40}; 36};
41 37
42/*3Radio off GPIO Array */ 38/*3Radio off GPIO Array */
43struct wlan_pwr_cfg rtl8723A_radio_off_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STPS 39struct wlan_pwr_cfg rtl8723A_radio_off_flow
44 + RTL8723A_TRANS_END_STPS] = { 40 [RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
45 RTL8723A_TRANS_ACT_TO_CARDEMU, 41 RTL8723A_TRANS_END_STEPS] = {
42 RTL8723A_TRANS_ACT_TO_CARDEMU
46 RTL8723A_TRANS_END 43 RTL8723A_TRANS_END
47}; 44};
48 45
49/*3Card Disable Array*/ 46/*3Card Disable Array*/
50struct wlan_pwr_cfg 47struct wlan_pwr_cfg rtl8723A_card_disable_flow
51rtl8723A_card_disable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STPS 48 [RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
52 + RTL8723A_TRANS_CARDEMU_TO_PDN_STPS 49 RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS +
53 + RTL8723A_TRANS_END_STPS] = { 50 RTL8723A_TRANS_END_STEPS] = {
54 RTL8723A_TRANS_ACT_TO_CARDEMU, 51 RTL8723A_TRANS_ACT_TO_CARDEMU
55 RTL8723A_TRANS_CARDEMU_TO_CARDDIS, 52 RTL8723A_TRANS_CARDEMU_TO_CARDDIS
56 RTL8723A_TRANS_END 53 RTL8723A_TRANS_END
57}; 54};
58 55
59/*3 Card Enable Array*/ 56/*3 Card Enable Array*/
60struct wlan_pwr_cfg rtl8723A_card_enable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STPS 57struct wlan_pwr_cfg rtl8723A_card_enable_flow
61 + RTL8723A_TRANS_CARDEMU_TO_PDN_STPS 58 [RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
62 + RTL8723A_TRANS_END_STPS] = { 59 RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS +
63 RTL8723A_TRANS_CARDDIS_TO_CARDEMU, 60 RTL8723A_TRANS_END_STEPS] = {
64 RTL8723A_TRANS_CARDEMU_TO_ACT, 61 RTL8723A_TRANS_CARDDIS_TO_CARDEMU
62 RTL8723A_TRANS_CARDEMU_TO_ACT
65 RTL8723A_TRANS_END 63 RTL8723A_TRANS_END
66}; 64};
67 65
68/*3Suspend Array*/ 66/*3Suspend Array*/
69struct wlan_pwr_cfg rtl8723A_suspend_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STPS 67struct wlan_pwr_cfg rtl8723A_suspend_flow
70 + RTL8723A_TRANS_CARDEMU_TO_SUS_STPS 68 [RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
71 + RTL8723A_TRANS_END_STPS] = { 69 RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS +
72 RTL8723A_TRANS_ACT_TO_CARDEMU, 70 RTL8723A_TRANS_END_STEPS] = {
73 RTL8723A_TRANS_CARDEMU_TO_SUS, 71 RTL8723A_TRANS_ACT_TO_CARDEMU
72 RTL8723A_TRANS_CARDEMU_TO_SUS
74 RTL8723A_TRANS_END 73 RTL8723A_TRANS_END
75}; 74};
76 75
77/*3 Resume Array*/ 76/*3 Resume Array*/
78struct wlan_pwr_cfg rtl8723A_resume_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STPS 77struct wlan_pwr_cfg rtl8723A_resume_flow
79 + RTL8723A_TRANS_CARDEMU_TO_SUS_STPS 78 [RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
80 + RTL8723A_TRANS_END_STPS] = { 79 RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS +
81 RTL8723A_TRANS_SUS_TO_CARDEMU, 80 RTL8723A_TRANS_END_STEPS] = {
82 RTL8723A_TRANS_CARDEMU_TO_ACT, 81 RTL8723A_TRANS_SUS_TO_CARDEMU
82 RTL8723A_TRANS_CARDEMU_TO_ACT
83 RTL8723A_TRANS_END 83 RTL8723A_TRANS_END
84}; 84};
85 85
86/*3HWPDN Array*/ 86/*3HWPDN Array*/
87struct wlan_pwr_cfg rtl8723A_hwpdn_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STPS 87struct wlan_pwr_cfg rtl8723A_hwpdn_flow
88 + RTL8723A_TRANS_CARDEMU_TO_PDN_STPS 88 [RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
89 + RTL8723A_TRANS_END_STPS] = { 89 RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS +
90 RTL8723A_TRANS_ACT_TO_CARDEMU, 90 RTL8723A_TRANS_END_STEPS] = {
91 RTL8723A_TRANS_CARDEMU_TO_PDN, 91 RTL8723A_TRANS_ACT_TO_CARDEMU
92 RTL8723A_TRANS_CARDEMU_TO_PDN
92 RTL8723A_TRANS_END 93 RTL8723A_TRANS_END
93}; 94};
94 95
95/*3 Enter LPS */ 96/*3 Enter LPS */
96struct wlan_pwr_cfg rtl8723A_enter_lps_flow[RTL8723A_TRANS_ACT_TO_LPS_STPS 97struct wlan_pwr_cfg rtl8723A_enter_lps_flow
97 + RTL8723A_TRANS_END_STPS] = { 98 [RTL8723A_TRANS_ACT_TO_LPS_STEPS +
99 RTL8723A_TRANS_END_STEPS] = {
98 /*FW behavior*/ 100 /*FW behavior*/
99 RTL8723A_TRANS_ACT_TO_LPS, 101 RTL8723A_TRANS_ACT_TO_LPS
100 RTL8723A_TRANS_END 102 RTL8723A_TRANS_END
101}; 103};
102 104
103/*3 Leave LPS */ 105/*3 Leave LPS */
104struct wlan_pwr_cfg rtl8723A_leave_lps_flow[RTL8723A_TRANS_LPS_TO_ACT_STPS 106struct wlan_pwr_cfg rtl8723A_leave_lps_flow
105 + RTL8723A_TRANS_END_STPS] = { 107 [RTL8723A_TRANS_LPS_TO_ACT_STEPS +
108 RTL8723A_TRANS_END_STEPS] = {
106 /*FW behavior*/ 109 /*FW behavior*/
107 RTL8723A_TRANS_LPS_TO_ACT, 110 RTL8723A_TRANS_LPS_TO_ACT
108 RTL8723A_TRANS_END 111 RTL8723A_TRANS_END
109}; 112};
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/pwrseq.h b/drivers/net/wireless/rtlwifi/rtl8723ae/pwrseq.h
index a418acb4d0ca..4ac7db526f15 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/pwrseq.h
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/pwrseq.h
@@ -11,10 +11,6 @@
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details. 12 * more details.
13 * 13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the 14 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE. 15 * file called LICENSE.
20 * 16 *
@@ -30,282 +26,305 @@
30#ifndef __RTL8723E_PWRSEQ_H__ 26#ifndef __RTL8723E_PWRSEQ_H__
31#define __RTL8723E_PWRSEQ_H__ 27#define __RTL8723E_PWRSEQ_H__
32 28
29#include "../pwrseqcmd.h"
33/* 30/*
34 Check document WM-20110607-Paul-RTL8723A_Power_Architecture-R02.vsd 31 * Check document WM-20110607-Paul-RTL8723A_Power_Architecture-R02.vsd
35 There are 6 HW Power States: 32 * There are 6 HW Power States:
36 0: POFF--Power Off 33 * 0: POFF--Power Off
37 1: PDN--Power Down 34 * 1: PDN--Power Down
38 2: CARDEMU--Card Emulation 35 * 2: CARDEMU--Card Emulation
39 3: ACT--Active Mode 36 * 3: ACT--Active Mode
40 4: LPS--Low Power State 37 * 4: LPS--Low Power State
41 5: SUS--Suspend 38 * 5: SUS--Suspend
42 39 *
43 The transision from different states are defined below 40 * The transision from different states are defined below
44 TRANS_CARDEMU_TO_ACT 41 * TRANS_CARDEMU_TO_ACT
45 TRANS_ACT_TO_CARDEMU 42 * TRANS_ACT_TO_CARDEMU
46 TRANS_CARDEMU_TO_SUS 43 * TRANS_CARDEMU_TO_SUS
47 TRANS_SUS_TO_CARDEMU 44 * TRANS_SUS_TO_CARDEMU
48 TRANS_CARDEMU_TO_PDN 45 * TRANS_CARDEMU_TO_PDN
49 TRANS_ACT_TO_LPS 46 * TRANS_ACT_TO_LPS
50 TRANS_LPS_TO_ACT 47 * TRANS_LPS_TO_ACT
48 *
49 * TRANS_END
50 */
51 51
52 TRANS_END 52#define RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS 10
53*/ 53#define RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS 10
54#define RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS 10
55#define RTL8723A_TRANS_SUS_TO_CARDEMU_STEPS 10
56#define RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS 10
57#define RTL8723A_TRANS_PDN_TO_CARDEMU_STEPS 10
58#define RTL8723A_TRANS_ACT_TO_LPS_STEPS 15
59#define RTL8723A_TRANS_LPS_TO_ACT_STEPS 15
60#define RTL8723A_TRANS_END_STEPS 1
54 61
55#define RTL8723A_TRANS_CARDEMU_TO_ACT_STPS 10 62/* format */
56#define RTL8723A_TRANS_ACT_TO_CARDEMU_STPS 10 63/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }*/
57#define RTL8723A_TRANS_CARDEMU_TO_SUS_STPS 10
58#define RTL8723A_TRANS_SUS_TO_CARDEMU_STPS 10
59#define RTL8723A_TRANS_CARDEMU_TO_PDN_STPS 10
60#define RTL8723A_TRANS_PDN_TO_CARDEMU_STPS 10
61#define RTL8723A_TRANS_ACT_TO_LPS_STPS 15
62#define RTL8723A_TRANS_LPS_TO_ACT_STPS 15
63#define RTL8723A_TRANS_END_STPS 1
64 64
65#define RTL8723A_TRANS_CARDEMU_TO_ACT \
66 /* disable SW LPS 0x04[10]=0*/ \
67 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
68 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), 0},\
69 /* wait till 0x04[17] = 1 power ready*/ \
70 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
71 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)},\
72 /* release WLON reset 0x04[16]=1*/ \
73 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
74 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},\
75 /* disable HWPDN 0x04[15]=0*/ \
76 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
77 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},\
78 /* disable WL suspend*/ \
79 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
80 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0},\
81 /* polling until return 0*/ \
82 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
83 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},\
84 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
85 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0},
65 86
66#define RTL8723A_TRANS_CARDEMU_TO_ACT \ 87/* format */
67 /* format */ \ 88/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
68 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, \
69 * comments here*/ \
70 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
71 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), 0}, \
72 /* disable SW LPS 0x04[10]=0*/ \
73 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
74 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
75 /* wait till 0x04[17] = 1 power ready*/ \
76 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
77 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
78 /* release WLON reset 0x04[16]=1*/ \
79 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
80 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}, \
81 /* disable HWPDN 0x04[15]=0*/ \
82 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
83 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0}, \
84 /* disable WL suspend*/ \
85 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
86 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
87 /* polling until return 0*/ \
88 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
89 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0}
90 89
91#define RTL8723A_TRANS_ACT_TO_CARDEMU \ 90#define RTL8723A_TRANS_ACT_TO_CARDEMU \
92 /* format */ \ 91 /*0x1F[7:0] = 0 turn off RF*/ \
93 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, \ 92 {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
94 * comments here*/ \ 93 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, \
95 {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 94 {0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
96 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, \ 95 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},\
97 /*0x1F[7:0] = 0 turn off RF*/ \ 96 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
98 {0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 97 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
99 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}, \ 98 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
100 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 99 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0},
101 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
102 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
103 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0}
104 100
105#define RTL8723A_TRANS_CARDEMU_TO_SUS \ 101/* format */
106 /* format */ \ 102/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/
107 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, \ 103#define RTL8723A_TRANS_CARDEMU_TO_SUS \
108 * comments here*/ \
109 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
110 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4)|BIT(3), \
111 (BIT(4)|BIT(3))}, \
112 /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ 104 /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
113 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | \ 105 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
114 PWR_INTF_SDIO_MSK, \ 106 PWR_BASEADDR_MAC, PWR_CMD_WRITE, \
115 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)},\ 107 BIT(4)|BIT(3), (BIT(4)|BIT(3))},\
116 /*0x04[12:11] = 2b'01 enable WL suspend*/ \ 108/*0x04[12:11] = 2b'01 enable WL suspend*/ \
117 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \ 109 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK| \
118 PWR_BASEADDR_MAC, \ 110 PWR_INTF_SDIO_MSK,\
119 PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)|BIT(4)}, \ 111 PWR_BASEADDR_MAC, \
120 /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ 112 PWR_CMD_WRITE, \
121 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 113 BIT(3)|BIT(4), BIT(3)}, \
122 PWR_BASEADDR_SDIO, \ 114/*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
123 PWR_CMD_WRITE, BIT(0), BIT(0)}, \ 115 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
124 /*Set SDIO suspend local register*/ \ 116 PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, \
125 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 117 PWR_CMD_WRITE, BIT(3)|BIT(4), \
126 PWR_BASEADDR_SDIO, \ 118 BIT(3)|BIT(4)}, \
127 PWR_CMD_POLLING, BIT(1), 0} \ 119/*Set SDIO suspend local register*/ \
128 /*wait power state to suspend*/ 120 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
121 PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
122 PWR_CMD_WRITE, BIT(0), BIT(0)}, \
123/*wait power state to suspend*/ \
124 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
125 PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
126 PWR_CMD_POLLING, BIT(1), 0},
127
128/* format */
129/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
130
131#define RTL8723A_TRANS_SUS_TO_CARDEMU \
132 /*Set SDIO suspend local register*/ \
133 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
134 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0},\
135 /*wait power state to suspend*/ \
136 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
137 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)},\
138 /*0x04[12:11] = 2b'01enable WL suspend*/ \
139 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
140 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},
141
142/* format */
143/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
144
145#define RTL8723A_TRANS_CARDEMU_TO_CARDDIS \
146 /*0x04[12:11] = 2b'01 enable WL suspend*/ \
147 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
148 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, \
149 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
150/*0x04[10] = 1, enable SW LPS*/ \
151 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
152 PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC,\
153 PWR_CMD_WRITE, BIT(2), BIT(2)}, \
154/*Set SDIO suspend local register*/ \
155 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
156 PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
157 PWR_CMD_WRITE, BIT(0), BIT(0)}, \
158 /*wait power state to suspend*/ \
159 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
160 PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
161 PWR_CMD_POLLING, BIT(1), 0},
162
163/* format */
164/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
129 165
130#define RTL8723A_TRANS_SUS_TO_CARDEMU \ 166#define RTL8723A_TRANS_CARDDIS_TO_CARDEMU\
131 /* format */ \ 167/*Set SDIO suspend local register*/ \
132 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\ 168 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
133 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 169 PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
134 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \ 170 PWR_CMD_WRITE, BIT(0), 0}, \
135 /*Set SDIO suspend local register*/ \ 171 /*wait power state to suspend*/ \
136 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 172 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
137 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \ 173 PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
138 /*wait power state to suspend*/ \ 174 PWR_CMD_POLLING, BIT(1), BIT(1)},\
139 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 175 /*0x04[12:11] = 2b'00enable WL suspend*/ \
140 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0} \ 176 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
141 /*0x04[12:11] = 2b'01enable WL suspend*/ 177 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
178 PWR_CMD_WRITE, BIT(3)|BIT(4), 0},\
179/*PCIe DMA start*/ \
180 {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
181 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
182 PWR_CMD_WRITE, 0xFF, 0},
142 183
143#define RTL8723A_TRANS_CARDEMU_TO_CARDDIS \ 184/* format */
144 /* format */ \ 185/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
145 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\ 186#define RTL8723A_TRANS_CARDEMU_TO_PDN \
146 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 187 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
147 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, \ 188 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
148 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)},\ 189 PWR_CMD_WRITE, BIT(0), 0},/* 0x04[16] = 0*/\
149 /*0x04[12:11] = 2b'01 enable WL suspend*/ \ 190 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
150 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \ 191 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
151 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), BIT(2)}, \ 192 PWR_CMD_WRITE, BIT(7), BIT(7)},/* 0x04[15] = 1*/
152 /*0x04[10] = 1, enable SW LPS*/ \
153 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
154 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
155 /*Set SDIO suspend local register*/ \
156 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
157 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0} \
158 /*wait power state to suspend*/
159 193
160#define RTL8723A_TRANS_CARDDIS_TO_CARDEMU \ 194/* format */
161 /* format */ \ 195/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
162 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\ 196#define RTL8723A_TRANS_PDN_TO_CARDEMU \
163 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 197 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
164 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \ 198 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
165 /*Set SDIO suspend local register*/ \ 199 PWR_CMD_WRITE, BIT(7), 0},/* 0x04[15] = 0*/
166 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
167 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
168 /*wait power state to suspend*/ \
169 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
170 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, \
171 /*0x04[12:11] = 2b'00enable WL suspend*/ \
172 {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
173 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0} \
174 /*PCIe DMA start*/
175 200
176#define RTL8723A_TRANS_CARDEMU_TO_PDN \ 201/* format */
177 /* format */ \ 202/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
178 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
179 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
180 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
181 /* 0x04[16] = 0*/\
182 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
183 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)} \
184 /* 0x04[15] = 1*/
185 203
186#define RTL8723A_TRANS_PDN_TO_CARDEMU \ 204#define RTL8723A_TRANS_ACT_TO_LPS \
187 /* format */ \ 205 {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
188 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\ 206 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
189 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 207 PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
190 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0} \ 208 {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
191 /* 0x04[15] = 0*/ 209 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
210 PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
211 /*Should be zero if no packet is transmitting*/ \
212 {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
213 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
214 PWR_CMD_POLLING, 0xFF, 0},\
215 /*Should be zero if no packet is transmitting*/ \
216 {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
217 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
218 PWR_CMD_POLLING, 0xFF, 0},\
219 /*Should be zero if no packet is transmitting*/ \
220 {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
221 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
222 PWR_CMD_POLLING, 0xFF, 0},\
223 /*Should be zero if no packet is transmitting*/ \
224 {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
225 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
226 PWR_CMD_POLLING, 0xFF, 0},\
227 /*CCK and OFDM are disabled,and clock are gated*/ \
228 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
229 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
230 PWR_CMD_WRITE, BIT(0), 0},\
231 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
232 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
233 PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/\
234 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
235 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
236 PWR_CMD_WRITE, BIT(1), 0},/*Whole BB is reset*/ \
237 {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
238 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
239 PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \
240 {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
241 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
242 PWR_CMD_WRITE, BIT(1), 0},/*check if removed later*/ \
243 /*Respond TxOK to scheduler*/ \
244 {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
245 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
246 PWR_CMD_WRITE, BIT(5), BIT(5)},\
192 247
193#define RTL8723A_TRANS_ACT_TO_LPS \ 248#define RTL8723A_TRANS_LPS_TO_ACT\
194 /* format */ \ 249/* format */ \
195 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\ 250/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */ \
196 {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 251 {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
197 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \ 252 PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
198 /*PCIe DMA stop*/ \ 253 PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
199 {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 254 {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
200 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F}, \ 255 PWR_INTF_USB_MSK, PWR_BASEADDR_MAC,\
201 /*Tx Pause*/ \ 256 PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
202 {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 257 {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
203 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \ 258 PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC,\
204 /*Should be zero if no packet is transmitting*/ \ 259 PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
205 {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 260 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
206 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \ 261 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
207 /*Should be zero if no packet is transmitting*/ \ 262 PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
208 {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 263 /*. 0x08[4] = 0 switch TSF to 40M*/\
209 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \ 264 {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
210 /*Should be zero if no packet is transmitting*/ \ 265 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
211 {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 266 PWR_CMD_WRITE, BIT(4), 0}, \
212 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \ 267 /*Polling 0x109[7]=0 TSF in 40M*/\
213 /*Should be zero if no packet is transmitting*/ \ 268 {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
214 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 269 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
215 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \ 270 PWR_CMD_POLLING, BIT(7), 0}, \
216 /*CCK and OFDM are disabled,and clock are gated*/ \ 271 /*. 0x29[7:6] = 2b'00 enable BB clock*/\
217 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 272 {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
218 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, \ 273 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
219 /*Delay 1us*/ \ 274 PWR_CMD_WRITE, BIT(6)|BIT(7), 0},\
220 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 275 /*. 0x101[1] = 1*/\
221 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \ 276 {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
222 /*Whole BB is reset*/ \ 277 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
223 {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 278 PWR_CMD_WRITE, BIT(1), BIT(1)},\
224 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F}, \ 279 /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
225 /*Reset MAC TRX*/ \ 280 {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
226 {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 281 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
227 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \ 282 PWR_CMD_WRITE, 0xFF, 0xFF},\
228 /*check if removed later*/ \ 283 /*. 0x02[1:0] = 2b'11 enable BB macro*/\
229 {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 284 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
230 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)} \ 285 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
231 /*Respond TxOK to scheduler*/ 286 PWR_CMD_WRITE, BIT(1)|BIT(0), BIT(1)|BIT(0)},\
287 {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
288 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
289 PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
232 290
233#define RTL8723A_TRANS_LPS_TO_ACT \ 291/* format */
234 /* format */ \ 292/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
235 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
236 {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
237 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, \
238 /*SDIO RPWM*/ \
239 {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \
240 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, \
241 /*USB RPWM*/ \
242 {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
243 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, \
244 /*PCIe RPWM*/ \
245 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
246 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, \
247 /*Delay*/ \
248 {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
249 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
250 /* 0x08[4] = 0 switch TSF to 40M*/ \
251 {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
252 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0}, \
253 /*Polling 0x109[7]=0 TSF in 40M*/ \
254 {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
255 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6)|BIT(7), 0}, \
256 /*. 0x29[7:6] = 2b'00 enable BB clock*/ \
257 {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
258 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
259 /*. 0x101[1] = 1*/ \
260 {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
261 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \
262 /* 0x100[7:0] = 0xFF enable WMAC TRX*/ \
263 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
264 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1)|BIT(0), \
265 BIT(1)|BIT(0)}, \
266 /* 0x02[1:0] = 2b'11 enable BB macro*/ \
267 {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
268 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0} \
269 /*. 0x522 = 0*/
270 293
271#define RTL8723A_TRANS_END \ 294#define RTL8723A_TRANS_END \
272 /* format */ \ 295 {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
273 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
274 {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
275 0, PWR_CMD_END, 0, 0} 296 0, PWR_CMD_END, 0, 0}
276 297
277extern struct 298extern struct wlan_pwr_cfg rtl8723A_power_on_flow
278wlan_pwr_cfg rtl8723A_power_on_flow[RTL8723A_TRANS_CARDEMU_TO_ACT_STPS 299 [RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS +
279 + RTL8723A_TRANS_END_STPS]; 300 RTL8723A_TRANS_END_STEPS];
280extern struct 301extern struct wlan_pwr_cfg rtl8723A_radio_off_flow
281wlan_pwr_cfg rtl8723A_radio_off_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STPS 302 [RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
282 + RTL8723A_TRANS_END_STPS]; 303 RTL8723A_TRANS_END_STEPS];
283extern struct 304extern struct wlan_pwr_cfg rtl8723A_card_disable_flow
284wlan_pwr_cfg rtl8723A_card_disable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STPS 305 [RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
285 + RTL8723A_TRANS_CARDEMU_TO_PDN_STPS 306 RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS +
286 + RTL8723A_TRANS_END_STPS]; 307 RTL8723A_TRANS_END_STEPS];
287extern struct 308extern struct wlan_pwr_cfg rtl8723A_card_enable_flow
288wlan_pwr_cfg rtl8723A_card_enable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STPS 309 [RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
289 + RTL8723A_TRANS_CARDEMU_TO_PDN_STPS 310 RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS +
290 + RTL8723A_TRANS_END_STPS]; 311 RTL8723A_TRANS_END_STEPS];
291extern struct 312extern struct wlan_pwr_cfg rtl8723A_suspend_flow
292wlan_pwr_cfg rtl8723A_suspend_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STPS 313 [RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
293 + RTL8723A_TRANS_CARDEMU_TO_SUS_STPS 314 RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS +
294 + RTL8723A_TRANS_END_STPS]; 315 RTL8723A_TRANS_END_STEPS];
295extern struct 316extern struct wlan_pwr_cfg rtl8723A_resume_flow
296wlan_pwr_cfg rtl8723A_resume_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STPS 317 [RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
297 + RTL8723A_TRANS_CARDEMU_TO_SUS_STPS 318 RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS +
298 + RTL8723A_TRANS_END_STPS]; 319 RTL8723A_TRANS_END_STEPS];
299extern struct 320extern struct wlan_pwr_cfg rtl8723A_hwpdn_flow
300wlan_pwr_cfg rtl8723A_hwpdn_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STPS 321 [RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
301 + RTL8723A_TRANS_CARDEMU_TO_PDN_STPS 322 RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS +
302 + RTL8723A_TRANS_END_STPS]; 323 RTL8723A_TRANS_END_STEPS];
303extern struct 324extern struct wlan_pwr_cfg rtl8723A_enter_lps_flow
304wlan_pwr_cfg rtl8723A_enter_lps_flow[RTL8723A_TRANS_ACT_TO_LPS_STPS 325 [RTL8723A_TRANS_ACT_TO_LPS_STEPS + RTL8723A_TRANS_END_STEPS];
305 + RTL8723A_TRANS_END_STPS]; 326extern struct wlan_pwr_cfg rtl8723A_leave_lps_flow
306extern struct 327 [RTL8723A_TRANS_LPS_TO_ACT_STEPS + RTL8723A_TRANS_END_STEPS];
307wlan_pwr_cfg rtl8723A_leave_lps_flow[RTL8723A_TRANS_LPS_TO_ACT_STPS
308 + RTL8723A_TRANS_END_STPS];
309 328
310/* RTL8723 Power Configuration CMDs for PCIe interface */ 329/* RTL8723 Power Configuration CMDs for PCIe interface */
311#define Rtl8723_NIC_PWR_ON_FLOW rtl8723A_power_on_flow 330#define Rtl8723_NIC_PWR_ON_FLOW rtl8723A_power_on_flow
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/reg.h b/drivers/net/wireless/rtlwifi/rtl8723ae/reg.h
index ce2c66fd9eee..306059f9b9cc 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/reg.h
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/reg.h
@@ -11,10 +11,6 @@
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details. 12 * more details.
13 * 13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the 14 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE. 15 * file called LICENSE.
20 * 16 *
@@ -34,13 +30,13 @@
34#define REG_SYS_FUNC_EN 0x0002 30#define REG_SYS_FUNC_EN 0x0002
35#define REG_APS_FSMCO 0x0004 31#define REG_APS_FSMCO 0x0004
36#define REG_SYS_CLKR 0x0008 32#define REG_SYS_CLKR 0x0008
37#define REG_9346CR 0x000A 33#define REG_9346CR 0x000A
38#define REG_EE_VPD 0x000C 34#define REG_EE_VPD 0x000C
39#define REG_AFE_MISC 0x0010 35#define REG_AFE_MISC 0x0010
40#define REG_SPS0_CTRL 0x0011 36#define REG_SPS0_CTRL 0x0011
41#define REG_SPS_OCP_CFG 0x0018 37#define REG_SPS_OCP_CFG 0x0018
42#define REG_RSV_CTRL 0x001C 38#define REG_RSV_CTRL 0x001C
43#define REG_RF_CTRL 0x001F 39#define REG_RF_CTRL 0x001F
44#define REG_LDOA15_CTRL 0x0020 40#define REG_LDOA15_CTRL 0x0020
45#define REG_LDOV12D_CTRL 0x0021 41#define REG_LDOV12D_CTRL 0x0021
46#define REG_LDOHCI12_CTRL 0x0022 42#define REG_LDOHCI12_CTRL 0x0022
@@ -57,12 +53,12 @@
57#define REG_MAC_PINMUX_CFG 0x0043 53#define REG_MAC_PINMUX_CFG 0x0043
58#define REG_GPIO_PIN_CTRL 0x0044 54#define REG_GPIO_PIN_CTRL 0x0044
59#define REG_GPIO_INTM 0x0048 55#define REG_GPIO_INTM 0x0048
60#define REG_LEDCFG0 0x004C 56#define REG_LEDCFG0 0x004C
61#define REG_LEDCFG1 0x004D 57#define REG_LEDCFG1 0x004D
62#define REG_LEDCFG2 0x004E 58#define REG_LEDCFG2 0x004E
63#define REG_LEDCFG3 0x004F 59#define REG_LEDCFG3 0x004F
64#define REG_FSIMR 0x0050 60#define REG_FSIMR 0x0050
65#define REG_FSISR 0x0054 61#define REG_FSISR 0x0054
66#define REG_GPIO_PIN_CTRL_2 0x0060 62#define REG_GPIO_PIN_CTRL_2 0x0060
67#define REG_GPIO_IO_SEL_2 0x0062 63#define REG_GPIO_IO_SEL_2 0x0062
68#define REG_MULTI_FUNC_CTRL 0x0068 64#define REG_MULTI_FUNC_CTRL 0x0068
@@ -80,25 +76,25 @@
80#define REG_USB_SIE_INTF 0x00E0 76#define REG_USB_SIE_INTF 0x00E0
81#define REG_PCIE_MIO_INTF 0x00E4 77#define REG_PCIE_MIO_INTF 0x00E4
82#define REG_PCIE_MIO_INTD 0x00E8 78#define REG_PCIE_MIO_INTD 0x00E8
83#define REG_SYS_CFG 0x00F0 79#define REG_SYS_CFG 0x00F0
84#define REG_GPIO_OUTSTS 0x00F4 80#define REG_GPIO_OUTSTS 0x00F4
85 81
86#define REG_CR 0x0100 82#define REG_CR 0x0100
87#define REG_PBP 0x0104 83#define REG_PBP 0x0104
88#define REG_TRXDMA_CTRL 0x010C 84#define REG_TRXDMA_CTRL 0x010C
89#define REG_TRXFF_BNDY 0x0114 85#define REG_TRXFF_BNDY 0x0114
90#define REG_TRXFF_STATUS 0x0118 86#define REG_TRXFF_STATUS 0x0118
91#define REG_RXFF_PTR 0x011C 87#define REG_RXFF_PTR 0x011C
92#define REG_HIMR 0x0120 88#define REG_HIMR 0x0120
93#define REG_HISR 0x0124 89#define REG_HISR 0x0124
94#define REG_HIMRE 0x0128 90#define REG_HIMRE 0x0128
95#define REG_HISRE 0x012C 91#define REG_HISRE 0x012C
96#define REG_CPWM 0x012F 92#define REG_CPWM 0x012F
97#define REG_FWIMR 0x0130 93#define REG_FWIMR 0x0130
98#define REG_FWISR 0x0134 94#define REG_FWISR 0x0134
99#define REG_PKTBUF_DBG_CTRL 0x0140 95#define REG_PKTBUF_DBG_CTRL 0x0140
100#define REG_PKTBUF_DBG_DATA_L 0x0144 96#define REG_PKTBUF_DBG_DATA_L 0x0144
101#define REG_PKTBUF_DBG_DATA_H 0x0148 97#define REG_PKTBUF_DBG_DATA_H 0x0148
102 98
103#define REG_TC0_CTRL 0x0150 99#define REG_TC0_CTRL 0x0150
104#define REG_TC1_CTRL 0x0154 100#define REG_TC1_CTRL 0x0154
@@ -109,11 +105,11 @@
109#define REG_MBIST_START 0x0174 105#define REG_MBIST_START 0x0174
110#define REG_MBIST_DONE 0x0178 106#define REG_MBIST_DONE 0x0178
111#define REG_MBIST_FAIL 0x017C 107#define REG_MBIST_FAIL 0x017C
112#define REG_C2HEVT_MSG_NORMAL 0x01A0 108#define REG_C2HEVT_MSG_NORMAL 0x01A0
113#define REG_C2HEVT_MSG_TEST 0x01B8 109#define REG_C2HEVT_MSG_TEST 0x01B8
114#define REG_MCUTST_1 0x01c0 110#define REG_MCUTST_1 0x01c0
115#define REG_FMETHR 0x01C8 111#define REG_FMETHR 0x01C8
116#define REG_HMETFR 0x01CC 112#define REG_HMETFR 0x01CC
117#define REG_HMEBOX_0 0x01D0 113#define REG_HMEBOX_0 0x01D0
118#define REG_HMEBOX_1 0x01D4 114#define REG_HMEBOX_1 0x01D4
119#define REG_HMEBOX_2 0x01D8 115#define REG_HMEBOX_2 0x01D8
@@ -123,10 +119,10 @@
123#define REG_BB_ACCEESS_CTRL 0x01E8 119#define REG_BB_ACCEESS_CTRL 0x01E8
124#define REG_BB_ACCESS_DATA 0x01EC 120#define REG_BB_ACCESS_DATA 0x01EC
125 121
126#define REG_RQPN 0x0200 122#define REG_RQPN 0x0200
127#define REG_FIFOPAGE 0x0204 123#define REG_FIFOPAGE 0x0204
128#define REG_TDECTRL 0x0208 124#define REG_TDECTRL 0x0208
129#define REG_TXDMA_OFFSET_CHK 0x020C 125#define REG_TXDMA_OFFSET_CHK 0x020C
130#define REG_TXDMA_STATUS 0x0210 126#define REG_TXDMA_STATUS 0x0210
131#define REG_RQPN_NPQ 0x0214 127#define REG_RQPN_NPQ 0x0214
132 128
@@ -135,18 +131,18 @@
135#define REG_RXDMA_STATUS 0x0288 131#define REG_RXDMA_STATUS 0x0288
136 132
137#define REG_PCIE_CTRL_REG 0x0300 133#define REG_PCIE_CTRL_REG 0x0300
138#define REG_INT_MIG 0x0304 134#define REG_INT_MIG 0x0304
139#define REG_BCNQ_DESA 0x0308 135#define REG_BCNQ_DESA 0x0308
140#define REG_HQ_DESA 0x0310 136#define REG_HQ_DESA 0x0310
141#define REG_MGQ_DESA 0x0318 137#define REG_MGQ_DESA 0x0318
142#define REG_VOQ_DESA 0x0320 138#define REG_VOQ_DESA 0x0320
143#define REG_VIQ_DESA 0x0328 139#define REG_VIQ_DESA 0x0328
144#define REG_BEQ_DESA 0x0330 140#define REG_BEQ_DESA 0x0330
145#define REG_BKQ_DESA 0x0338 141#define REG_BKQ_DESA 0x0338
146#define REG_RX_DESA 0x0340 142#define REG_RX_DESA 0x0340
147#define REG_DBI 0x0348 143#define REG_DBI 0x0348
148#define REG_MDIO 0x0354 144#define REG_MDIO 0x0354
149#define REG_DBG_SEL 0x0360 145#define REG_DBG_SEL 0x0360
150#define REG_PCIE_HRPWM 0x0361 146#define REG_PCIE_HRPWM 0x0361
151#define REG_PCIE_HCPWM 0x0363 147#define REG_PCIE_HCPWM 0x0363
152#define REG_UART_CTRL 0x0364 148#define REG_UART_CTRL 0x0364
@@ -162,31 +158,31 @@
162#define REG_BKQ_INFORMATION 0x040C 158#define REG_BKQ_INFORMATION 0x040C
163#define REG_MGQ_INFORMATION 0x0410 159#define REG_MGQ_INFORMATION 0x0410
164#define REG_HGQ_INFORMATION 0x0414 160#define REG_HGQ_INFORMATION 0x0414
165#define REG_BCNQ_INFORMATION 0x0418 161#define REG_BCNQ_INFORMATION 0x0418
166 162
167#define REG_CPU_MGQ_INFORMATION 0x041C 163#define REG_CPU_MGQ_INFORMATION 0x041C
168#define REG_FWHW_TXQ_CTRL 0x0420 164#define REG_FWHW_TXQ_CTRL 0x0420
169#define REG_HWSEQ_CTRL 0x0423 165#define REG_HWSEQ_CTRL 0x0423
170#define REG_TXPKTBUF_BCNQ_BDNY 0x0424 166#define REG_TXPKTBUF_BCNQ_BDNY 0x0424
171#define REG_TXPKTBUF_MGQ_BDNY 0x0425 167#define REG_TXPKTBUF_MGQ_BDNY 0x0425
172#define REG_MULTI_BCNQ_EN 0x0426 168#define REG_MULTI_BCNQ_EN 0x0426
173#define REG_MULTI_BCNQ_OFFSET 0x0427 169#define REG_MULTI_BCNQ_OFFSET 0x0427
174#define REG_SPEC_SIFS 0x0428 170#define REG_SPEC_SIFS 0x0428
175#define REG_RL 0x042A 171#define REG_RL 0x042A
176#define REG_DARFRC 0x0430 172#define REG_DARFRC 0x0430
177#define REG_RARFRC 0x0438 173#define REG_RARFRC 0x0438
178#define REG_RRSR 0x0440 174#define REG_RRSR 0x0440
179#define REG_ARFR0 0x0444 175#define REG_ARFR0 0x0444
180#define REG_ARFR1 0x0448 176#define REG_ARFR1 0x0448
181#define REG_ARFR2 0x044C 177#define REG_ARFR2 0x044C
182#define REG_ARFR3 0x0450 178#define REG_ARFR3 0x0450
183#define REG_AGGLEN_LMT 0x0458 179#define REG_AGGLEN_LMT 0x0458
184#define REG_AMPDU_MIN_SPACE 0x045C 180#define REG_AMPDU_MIN_SPACE 0x045C
185#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D 181#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D
186#define REG_FAST_EDCA_CTRL 0x0460 182#define REG_FAST_EDCA_CTRL 0x0460
187#define REG_RD_RESP_PKT_TH 0x0463 183#define REG_RD_RESP_PKT_TH 0x0463
188#define REG_INIRTS_RATE_SEL 0x0480 184#define REG_INIRTS_RATE_SEL 0x0480
189#define REG_INIDATA_RATE_SEL 0x0484 185#define REG_INIDATA_RATE_SEL 0x0484
190#define REG_POWER_STATUS 0x04A4 186#define REG_POWER_STATUS 0x04A4
191#define REG_POWER_STAGE1 0x04B4 187#define REG_POWER_STAGE1 0x04B4
192#define REG_POWER_STAGE2 0x04B8 188#define REG_POWER_STAGE2 0x04B8
@@ -194,29 +190,29 @@
194#define REG_STBC_SETTING 0x04C4 190#define REG_STBC_SETTING 0x04C4
195#define REG_PROT_MODE_CTRL 0x04C8 191#define REG_PROT_MODE_CTRL 0x04C8
196#define REG_BAR_MODE_CTRL 0x04CC 192#define REG_BAR_MODE_CTRL 0x04CC
197#define REG_RA_TRY_RATE_AGG_LMT 0x04CF 193#define REG_RA_TRY_RATE_AGG_LMT 0x04CF
198#define REG_NQOS_SEQ 0x04DC 194#define REG_NQOS_SEQ 0x04DC
199#define REG_QOS_SEQ 0x04DE 195#define REG_QOS_SEQ 0x04DE
200#define REG_NEED_CPU_HANDLE 0x04E0 196#define REG_NEED_CPU_HANDLE 0x04E0
201#define REG_PKT_LOSE_RPT 0x04E1 197#define REG_PKT_LOSE_RPT 0x04E1
202#define REG_PTCL_ERR_STATUS 0x04E2 198#define REG_PTCL_ERR_STATUS 0x04E2
203#define REG_DUMMY 0x04FC 199#define REG_DUMMY 0x04FC
204 200
205#define REG_EDCA_VO_PARAM 0x0500 201#define REG_EDCA_VO_PARAM 0x0500
206#define REG_EDCA_VI_PARAM 0x0504 202#define REG_EDCA_VI_PARAM 0x0504
207#define REG_EDCA_BE_PARAM 0x0508 203#define REG_EDCA_BE_PARAM 0x0508
208#define REG_EDCA_BK_PARAM 0x050C 204#define REG_EDCA_BK_PARAM 0x050C
209#define REG_BCNTCFG 0x0510 205#define REG_BCNTCFG 0x0510
210#define REG_PIFS 0x0512 206#define REG_PIFS 0x0512
211#define REG_RDG_PIFS 0x0513 207#define REG_RDG_PIFS 0x0513
212#define REG_SIFS_CTX 0x0514 208#define REG_SIFS_CTX 0x0514
213#define REG_SIFS_TRX 0x0516 209#define REG_SIFS_TRX 0x0516
214#define REG_AGGR_BREAK_TIME 0x051A 210#define REG_AGGR_BREAK_TIME 0x051A
215#define REG_SLOT 0x051B 211#define REG_SLOT 0x051B
216#define REG_TX_PTCL_CTRL 0x0520 212#define REG_TX_PTCL_CTRL 0x0520
217#define REG_TXPAUSE 0x0522 213#define REG_TXPAUSE 0x0522
218#define REG_DIS_TXREQ_CLR 0x0523 214#define REG_DIS_TXREQ_CLR 0x0523
219#define REG_RD_CTRL 0x0524 215#define REG_RD_CTRL 0x0524
220#define REG_TBTT_PROHIBIT 0x0540 216#define REG_TBTT_PROHIBIT 0x0540
221#define REG_RD_NAV_NXT 0x0544 217#define REG_RD_NAV_NXT 0x0544
222#define REG_NAV_PROT_LEN 0x0546 218#define REG_NAV_PROT_LEN 0x0546
@@ -225,21 +221,21 @@
225#define REG_MBID_NUM 0x0552 221#define REG_MBID_NUM 0x0552
226#define REG_DUAL_TSF_RST 0x0553 222#define REG_DUAL_TSF_RST 0x0553
227#define REG_BCN_INTERVAL 0x0554 223#define REG_BCN_INTERVAL 0x0554
228#define REG_MBSSID_BCN_SPACE 0x0554 224#define REG_MBSSID_BCN_SPACE 0x0554
229#define REG_DRVERLYINT 0x0558 225#define REG_DRVERLYINT 0x0558
230#define REG_BCNDMATIM 0x0559 226#define REG_BCNDMATIM 0x0559
231#define REG_ATIMWND 0x055A 227#define REG_ATIMWND 0x055A
232#define REG_BCN_MAX_ERR 0x055D 228#define REG_BCN_MAX_ERR 0x055D
233#define REG_RXTSF_OFFSET_CCK 0x055E 229#define REG_RXTSF_OFFSET_CCK 0x055E
234#define REG_RXTSF_OFFSET_OFDM 0x055F 230#define REG_RXTSF_OFFSET_OFDM 0x055F
235#define REG_TSFTR 0x0560 231#define REG_TSFTR 0x0560
236#define REG_INIT_TSFTR 0x0564 232#define REG_INIT_TSFTR 0x0564
237#define REG_PSTIMER 0x0580 233#define REG_PSTIMER 0x0580
238#define REG_TIMER0 0x0584 234#define REG_TIMER0 0x0584
239#define REG_TIMER1 0x0588 235#define REG_TIMER1 0x0588
240#define REG_ACMHWCTRL 0x05C0 236#define REG_ACMHWCTRL 0x05C0
241#define REG_ACMRSTCTRL 0x05C1 237#define REG_ACMRSTCTRL 0x05C1
242#define REG_ACMAVG 0x05C2 238#define REG_ACMAVG 0x05C2
243#define REG_VO_ADMTIME 0x05C4 239#define REG_VO_ADMTIME 0x05C4
244#define REG_VI_ADMTIME 0x05C6 240#define REG_VI_ADMTIME 0x05C6
245#define REG_BE_ADMTIME 0x05C8 241#define REG_BE_ADMTIME 0x05C8
@@ -248,38 +244,38 @@
248 244
249#define REG_APSD_CTRL 0x0600 245#define REG_APSD_CTRL 0x0600
250#define REG_BWOPMODE 0x0603 246#define REG_BWOPMODE 0x0603
251#define REG_TCR 0x0604 247#define REG_TCR 0x0604
252#define REG_RCR 0x0608 248#define REG_RCR 0x0608
253#define REG_RX_PKT_LIMIT 0x060C 249#define REG_RX_PKT_LIMIT 0x060C
254#define REG_RX_DLK_TIME 0x060D 250#define REG_RX_DLK_TIME 0x060D
255#define REG_RX_DRVINFO_SZ 0x060F 251#define REG_RX_DRVINFO_SZ 0x060F
256 252
257#define REG_MACID 0x0610 253#define REG_MACID 0x0610
258#define REG_BSSID 0x0618 254#define REG_BSSID 0x0618
259#define REG_MAR 0x0620 255#define REG_MAR 0x0620
260#define REG_MBIDCAMCFG 0x0628 256#define REG_MBIDCAMCFG 0x0628
261 257
262#define REG_USTIME_EDCA 0x0638 258#define REG_USTIME_EDCA 0x0638
263#define REG_MAC_SPEC_SIFS 0x063A 259#define REG_MAC_SPEC_SIFS 0x063A
264#define REG_RESP_SIFS_CCK 0x063C 260#define REG_RESP_SIFS_CCK 0x063C
265#define REG_RESP_SIFS_OFDM 0x063E 261#define REG_RESP_SIFS_OFDM 0x063E
266#define REG_ACKTO 0x0640 262#define REG_ACKTO 0x0640
267#define REG_CTS2TO 0x0641 263#define REG_CTS2TO 0x0641
268#define REG_EIFS 0x0642 264#define REG_EIFS 0x0642
269 265
270#define REG_NAV_CTRL 0x0650 266#define REG_NAV_CTRL 0x0650
271#define REG_BACAMCMD 0x0654 267#define REG_BACAMCMD 0x0654
272#define REG_BACAMCONTENT 0x0658 268#define REG_BACAMCONTENT 0x0658
273#define REG_LBDLY 0x0660 269#define REG_LBDLY 0x0660
274#define REG_FWDLY 0x0661 270#define REG_FWDLY 0x0661
275#define REG_RXERR_RPT 0x0664 271#define REG_RXERR_RPT 0x0664
276#define REG_WMAC_TRXPTCL_CTL 0x0668 272#define REG_WMAC_TRXPTCL_CTL 0x0668
277 273
278#define REG_CAMCMD 0x0670 274#define REG_CAMCMD 0x0670
279#define REG_CAMWRITE 0x0674 275#define REG_CAMWRITE 0x0674
280#define REG_CAMREAD 0x0678 276#define REG_CAMREAD 0x0678
281#define REG_CAMDBG 0x067C 277#define REG_CAMDBG 0x067C
282#define REG_SECCFG 0x0680 278#define REG_SECCFG 0x0680
283 279
284#define REG_WOW_CTRL 0x0690 280#define REG_WOW_CTRL 0x0690
285#define REG_PSSTATUS 0x0691 281#define REG_PSSTATUS 0x0691
@@ -294,10 +290,10 @@
294#define REG_CALB32K_CTRL 0x06AC 290#define REG_CALB32K_CTRL 0x06AC
295#define REG_PKT_MON_CTRL 0x06B4 291#define REG_PKT_MON_CTRL 0x06B4
296#define REG_BT_COEX_TABLE 0x06C0 292#define REG_BT_COEX_TABLE 0x06C0
297#define REG_WMAC_RESP_TXINFO 0x06D8 293#define REG_WMAC_RESP_TXINFO 0x06D8
298 294
299#define REG_USB_INFO 0xFE17 295#define REG_USB_INFO 0xFE17
300#define REG_USB_SPECIAL_OPTION 0xFE55 296#define REG_USB_SPECIAL_OPTION 0xFE55
301#define REG_USB_DMA_AGG_TO 0xFE5B 297#define REG_USB_DMA_AGG_TO 0xFE5B
302#define REG_USB_AGG_TO 0xFE5C 298#define REG_USB_AGG_TO 0xFE5C
303#define REG_USB_AGG_TH 0xFE5D 299#define REG_USB_AGG_TH 0xFE5D
@@ -305,120 +301,148 @@
305#define REG_TEST_USB_TXQS 0xFE48 301#define REG_TEST_USB_TXQS 0xFE48
306#define REG_TEST_SIE_VID 0xFE60 302#define REG_TEST_SIE_VID 0xFE60
307#define REG_TEST_SIE_PID 0xFE62 303#define REG_TEST_SIE_PID 0xFE62
308#define REG_TEST_SIE_OPTIONAL 0xFE64 304#define REG_TEST_SIE_OPTIONAL 0xFE64
309#define REG_TEST_SIE_CHIRP_K 0xFE65 305#define REG_TEST_SIE_CHIRP_K 0xFE65
310#define REG_TEST_SIE_PHY 0xFE66 306#define REG_TEST_SIE_PHY 0xFE66
311#define REG_TEST_SIE_MAC_ADDR 0xFE70 307#define REG_TEST_SIE_MAC_ADDR 0xFE70
312#define REG_TEST_SIE_STRING 0xFE80 308#define REG_TEST_SIE_STRING 0xFE80
313 309
314#define REG_NORMAL_SIE_VID 0xFE60 310#define REG_NORMAL_SIE_VID 0xFE60
315#define REG_NORMAL_SIE_PID 0xFE62 311#define REG_NORMAL_SIE_PID 0xFE62
316#define REG_NORMAL_SIE_OPTIONAL 0xFE64 312#define REG_NORMAL_SIE_OPTIONAL 0xFE64
317#define REG_NORMAL_SIE_EP 0xFE65 313#define REG_NORMAL_SIE_EP 0xFE65
318#define REG_NORMAL_SIE_PHY 0xFE68 314#define REG_NORMAL_SIE_PHY 0xFE68
319#define REG_NORMAL_SIE_MAC_ADDR 0xFE70 315#define REG_NORMAL_SIE_MAC_ADDR 0xFE70
320#define REG_NORMAL_SIE_STRING 0xFE80 316#define REG_NORMAL_SIE_STRING 0xFE80
321 317
322#define CR9346 REG_9346CR 318#define CR9346 REG_9346CR
323#define MSR (REG_CR + 2) 319#define MSR (REG_CR + 2)
324#define ISR REG_HISR 320#define ISR REG_HISR
325#define TSFR REG_TSFTR 321#define TSFR REG_TSFTR
326 322
327#define MACIDR0 REG_MACID 323#define MACIDR0 REG_MACID
328#define MACIDR4 (REG_MACID + 4) 324#define MACIDR4 (REG_MACID + 4)
329 325
330#define PBP REG_PBP 326#define PBP REG_PBP
331 327
332#define IDR0 MACIDR0 328#define IDR0 MACIDR0
333#define IDR4 MACIDR4 329#define IDR4 MACIDR4
334 330
335#define UNUSED_REGISTER 0x1BF 331#define UNUSED_REGISTER 0x1BF
336#define DCAM UNUSED_REGISTER 332#define DCAM UNUSED_REGISTER
337#define PSR UNUSED_REGISTER 333#define PSR UNUSED_REGISTER
338#define BBADDR UNUSED_REGISTER 334#define BBADDR UNUSED_REGISTER
339#define PHYDATAR UNUSED_REGISTER 335#define PHYDATAR UNUSED_REGISTER
340 336
341#define INVALID_BBRF_VALUE 0x12345678 337#define INVALID_BBRF_VALUE 0x12345678
342 338
343#define MAX_MSS_DENSITY_2T 0x13 339#define MAX_MSS_DENSITY_2T 0x13
344#define MAX_MSS_DENSITY_1T 0x0A 340#define MAX_MSS_DENSITY_1T 0x0A
345 341
346#define CMDEEPROM_EN BIT(5) 342#define CMDEEPROM_EN BIT(5)
347#define CMDEEPROM_SEL BIT(4) 343#define CMDEEPROM_SEL BIT(4)
348#define CMD9346CR_9356SEL BIT(4) 344#define CMD9346CR_9356SEL BIT(4)
349#define AUTOLOAD_EEPROM (CMDEEPROM_EN|CMDEEPROM_SEL) 345#define AUTOLOAD_EEPROM (CMDEEPROM_EN|CMDEEPROM_SEL)
350#define AUTOLOAD_EFUSE CMDEEPROM_EN 346#define AUTOLOAD_EFUSE CMDEEPROM_EN
351 347
352#define GPIOSEL_GPIO 0 348#define GPIOSEL_GPIO 0
353#define GPIOSEL_ENBT BIT(5) 349#define GPIOSEL_ENBT BIT(5)
354 350
355#define GPIO_IN REG_GPIO_PIN_CTRL 351#define GPIO_IN REG_GPIO_PIN_CTRL
356#define GPIO_OUT (REG_GPIO_PIN_CTRL+1) 352#define GPIO_OUT (REG_GPIO_PIN_CTRL+1)
357#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) 353#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2)
358#define GPIO_MOD (REG_GPIO_PIN_CTRL+3) 354#define GPIO_MOD (REG_GPIO_PIN_CTRL+3)
359 355
360#define MSR_NOLINK 0x00 356#define MSR_NOLINK 0x00
361#define MSR_ADHOC 0x01 357#define MSR_ADHOC 0x01
362#define MSR_INFRA 0x02 358#define MSR_INFRA 0x02
363#define MSR_AP 0x03 359#define MSR_AP 0x03
364#define MSR_MASK 0x03
365 360
366#define RRSR_RSC_OFFSET 21 361#define RRSR_RSC_OFFSET 21
367#define RRSR_SHORT_OFFSET 23 362#define RRSR_SHORT_OFFSET 23
368#define RRSR_RSC_BW_40M 0x600000 363#define RRSR_RSC_BW_40M 0x600000
369#define RRSR_RSC_UPSUBCHNL 0x400000 364#define RRSR_RSC_UPSUBCHNL 0x400000
370#define RRSR_RSC_LOWSUBCHNL 0x200000 365#define RRSR_RSC_LOWSUBCHNL 0x200000
371#define RRSR_SHORT 0x800000 366#define RRSR_SHORT 0x800000
372#define RRSR_1M BIT(0) 367#define RRSR_1M BIT(0)
373#define RRSR_2M BIT(1) 368#define RRSR_2M BIT(1)
374#define RRSR_5_5M BIT(2) 369#define RRSR_5_5M BIT(2)
375#define RRSR_11M BIT(3) 370#define RRSR_11M BIT(3)
376#define RRSR_6M BIT(4) 371#define RRSR_6M BIT(4)
377#define RRSR_9M BIT(5) 372#define RRSR_9M BIT(5)
378#define RRSR_12M BIT(6) 373#define RRSR_12M BIT(6)
379#define RRSR_18M BIT(7) 374#define RRSR_18M BIT(7)
380#define RRSR_24M BIT(8) 375#define RRSR_24M BIT(8)
381#define RRSR_36M BIT(9) 376#define RRSR_36M BIT(9)
382#define RRSR_48M BIT(10) 377#define RRSR_48M BIT(10)
383#define RRSR_54M BIT(11) 378#define RRSR_54M BIT(11)
384#define RRSR_MCS0 BIT(12) 379#define RRSR_MCS0 BIT(12)
385#define RRSR_MCS1 BIT(13) 380#define RRSR_MCS1 BIT(13)
386#define RRSR_MCS2 BIT(14) 381#define RRSR_MCS2 BIT(14)
387#define RRSR_MCS3 BIT(15) 382#define RRSR_MCS3 BIT(15)
388#define RRSR_MCS4 BIT(16) 383#define RRSR_MCS4 BIT(16)
389#define RRSR_MCS5 BIT(17) 384#define RRSR_MCS5 BIT(17)
390#define RRSR_MCS6 BIT(18) 385#define RRSR_MCS6 BIT(18)
391#define RRSR_MCS7 BIT(19) 386#define RRSR_MCS7 BIT(19)
392#define BRSR_ACKSHORTPMB BIT(23) 387#define BRSR_ACKSHORTPMB BIT(23)
393 388
394#define RATR_1M 0x00000001 389#define RATR_1M 0x00000001
395#define RATR_2M 0x00000002 390#define RATR_2M 0x00000002
396#define RATR_55M 0x00000004 391#define RATR_55M 0x00000004
397#define RATR_11M 0x00000008 392#define RATR_11M 0x00000008
398#define RATR_6M 0x00000010 393#define RATR_6M 0x00000010
399#define RATR_9M 0x00000020 394#define RATR_9M 0x00000020
400#define RATR_12M 0x00000040 395#define RATR_12M 0x00000040
401#define RATR_18M 0x00000080 396#define RATR_18M 0x00000080
402#define RATR_24M 0x00000100 397#define RATR_24M 0x00000100
403#define RATR_36M 0x00000200 398#define RATR_36M 0x00000200
404#define RATR_48M 0x00000400 399#define RATR_48M 0x00000400
405#define RATR_54M 0x00000800 400#define RATR_54M 0x00000800
406#define RATR_MCS0 0x00001000 401#define RATR_MCS0 0x00001000
407#define RATR_MCS1 0x00002000 402#define RATR_MCS1 0x00002000
408#define RATR_MCS2 0x00004000 403#define RATR_MCS2 0x00004000
409#define RATR_MCS3 0x00008000 404#define RATR_MCS3 0x00008000
410#define RATR_MCS4 0x00010000 405#define RATR_MCS4 0x00010000
411#define RATR_MCS5 0x00020000 406#define RATR_MCS5 0x00020000
412#define RATR_MCS6 0x00040000 407#define RATR_MCS6 0x00040000
413#define RATR_MCS7 0x00080000 408#define RATR_MCS7 0x00080000
414#define RATR_MCS8 0x00100000 409#define RATR_MCS8 0x00100000
415#define RATR_MCS9 0x00200000 410#define RATR_MCS9 0x00200000
416#define RATR_MCS10 0x00400000 411#define RATR_MCS10 0x00400000
417#define RATR_MCS11 0x00800000 412#define RATR_MCS11 0x00800000
418#define RATR_MCS12 0x01000000 413#define RATR_MCS12 0x01000000
419#define RATR_MCS13 0x02000000 414#define RATR_MCS13 0x02000000
420#define RATR_MCS14 0x04000000 415#define RATR_MCS14 0x04000000
421#define RATR_MCS15 0x08000000 416#define RATR_MCS15 0x08000000
417
418#define RATE_1M BIT(0)
419#define RATE_2M BIT(1)
420#define RATE_5_5M BIT(2)
421#define RATE_11M BIT(3)
422#define RATE_6M BIT(4)
423#define RATE_9M BIT(5)
424#define RATE_12M BIT(6)
425#define RATE_18M BIT(7)
426#define RATE_24M BIT(8)
427#define RATE_36M BIT(9)
428#define RATE_48M BIT(10)
429#define RATE_54M BIT(11)
430#define RATE_MCS0 BIT(12)
431#define RATE_MCS1 BIT(13)
432#define RATE_MCS2 BIT(14)
433#define RATE_MCS3 BIT(15)
434#define RATE_MCS4 BIT(16)
435#define RATE_MCS5 BIT(17)
436#define RATE_MCS6 BIT(18)
437#define RATE_MCS7 BIT(19)
438#define RATE_MCS8 BIT(20)
439#define RATE_MCS9 BIT(21)
440#define RATE_MCS10 BIT(22)
441#define RATE_MCS11 BIT(23)
442#define RATE_MCS12 BIT(24)
443#define RATE_MCS13 BIT(25)
444#define RATE_MCS14 BIT(26)
445#define RATE_MCS15 BIT(27)
422 446
423#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M) 447#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M)
424#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M |\ 448#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M |\
@@ -434,31 +458,31 @@
434#define BW_OPMODE_5G BIT(1) 458#define BW_OPMODE_5G BIT(1)
435#define BW_OPMODE_11J BIT(0) 459#define BW_OPMODE_11J BIT(0)
436 460
437#define CAM_VALID BIT(15) 461#define CAM_VALID BIT(15)
438#define CAM_NOTVALID 0x0000 462#define CAM_NOTVALID 0x0000
439#define CAM_USEDK BIT(5) 463#define CAM_USEDK BIT(5)
440 464
441#define CAM_NONE 0x0 465#define CAM_NONE 0x0
442#define CAM_WEP40 0x01 466#define CAM_WEP40 0x01
443#define CAM_TKIP 0x02 467#define CAM_TKIP 0x02
444#define CAM_AES 0x04 468#define CAM_AES 0x04
445#define CAM_WEP104 0x05 469#define CAM_WEP104 0x05
446 470
447#define TOTAL_CAM_ENTRY 32 471#define TOTAL_CAM_ENTRY 32
448#define HALF_CAM_ENTRY 16 472#define HALF_CAM_ENTRY 16
449 473
450#define CAM_WRITE BIT(16) 474#define CAM_WRITE BIT(16)
451#define CAM_READ 0x00000000 475#define CAM_READ 0x00000000
452#define CAM_POLLINIG BIT(31) 476#define CAM_POLLINIG BIT(31)
453 477
454#define SCR_USEDK 0x01 478#define SCR_USEDK 0x01
455#define SCR_TXSEC_ENABLE 0x02 479#define SCR_TXSEC_ENABLE 0x02
456#define SCR_RXSEC_ENABLE 0x04 480#define SCR_RXSEC_ENABLE 0x04
457 481
458#define WOW_PMEN BIT(0) 482#define WOW_PMEN BIT(0)
459#define WOW_WOMEN BIT(1) 483#define WOW_WOMEN BIT(1)
460#define WOW_MAGIC BIT(2) 484#define WOW_MAGIC BIT(2)
461#define WOW_UWF BIT(3) 485#define WOW_UWF BIT(3)
462 486
463#define IMR8190_DISABLED 0x0 487#define IMR8190_DISABLED 0x0
464#define IMR_BCNDMAINT6 BIT(31) 488#define IMR_BCNDMAINT6 BIT(31)
@@ -467,180 +491,179 @@
467#define IMR_BCNDMAINT3 BIT(28) 491#define IMR_BCNDMAINT3 BIT(28)
468#define IMR_BCNDMAINT2 BIT(27) 492#define IMR_BCNDMAINT2 BIT(27)
469#define IMR_BCNDMAINT1 BIT(26) 493#define IMR_BCNDMAINT1 BIT(26)
470#define IMR_BCNDOK8 BIT(25) 494#define IMR_BCNDOK8 BIT(25)
471#define IMR_BCNDOK7 BIT(24) 495#define IMR_BCNDOK7 BIT(24)
472#define IMR_BCNDOK6 BIT(23) 496#define IMR_BCNDOK6 BIT(23)
473#define IMR_BCNDOK5 BIT(22) 497#define IMR_BCNDOK5 BIT(22)
474#define IMR_BCNDOK4 BIT(21) 498#define IMR_BCNDOK4 BIT(21)
475#define IMR_BCNDOK3 BIT(20) 499#define IMR_BCNDOK3 BIT(20)
476#define IMR_BCNDOK2 BIT(19) 500#define IMR_BCNDOK2 BIT(19)
477#define IMR_BCNDOK1 BIT(18) 501#define IMR_BCNDOK1 BIT(18)
478#define IMR_TIMEOUT2 BIT(17) 502#define IMR_TIMEOUT2 BIT(17)
479#define IMR_TIMEOUT1 BIT(16) 503#define IMR_TIMEOUT1 BIT(16)
480#define IMR_TXFOVW BIT(15) 504#define IMR_TXFOVW BIT(15)
481#define IMR_PSTIMEOUT BIT(14) 505#define IMR_PSTIMEOUT BIT(14)
482#define IMR_BCNINT BIT(13) 506#define IMR_BCNINT BIT(13)
483#define IMR_RXFOVW BIT(12) 507#define IMR_RXFOVW BIT(12)
484#define IMR_RDU BIT(11) 508#define IMR_RDU BIT(11)
485#define IMR_ATIMEND BIT(10) 509#define IMR_ATIMEND BIT(10)
486#define IMR_BDOK BIT(9) 510#define IMR_BDOK BIT(9)
487#define IMR_HIGHDOK BIT(8) 511#define IMR_HIGHDOK BIT(8)
488#define IMR_TBDOK BIT(7) 512#define IMR_TBDOK BIT(7)
489#define IMR_MGNTDOK BIT(6) 513#define IMR_MGNTDOK BIT(6)
490#define IMR_TBDER BIT(5) 514#define IMR_TBDER BIT(5)
491#define IMR_BKDOK BIT(4) 515#define IMR_BKDOK BIT(4)
492#define IMR_BEDOK BIT(3) 516#define IMR_BEDOK BIT(3)
493#define IMR_VIDOK BIT(2) 517#define IMR_VIDOK BIT(2)
494#define IMR_VODOK BIT(1) 518#define IMR_VODOK BIT(1)
495#define IMR_ROK BIT(0) 519#define IMR_ROK BIT(0)
496 520
497#define IMR_TXERR BIT(11) 521#define IMR_TXERR BIT(11)
498#define IMR_RXERR BIT(10) 522#define IMR_RXERR BIT(10)
499#define IMR_CPWM BIT(8) 523#define IMR_CPWM BIT(8)
500#define IMR_OCPINT BIT(1) 524#define IMR_OCPINT BIT(1)
501#define IMR_WLANOFF BIT(0) 525#define IMR_WLANOFF BIT(0)
502 526
503/* 8723E series PCIE Host IMR/ISR bit */ 527/* 8723E series PCIE Host IMR/ISR bit */
504/* IMR DW0 Bit 0-31 */ 528/* IMR DW0 Bit 0-31 */
505#define PHIMR_TIMEOUT2 BIT(31) 529#define PHIMR_TIMEOUT2 BIT(31)
506#define PHIMR_TIMEOUT1 BIT(30) 530#define PHIMR_TIMEOUT1 BIT(30)
507#define PHIMR_PSTIMEOUT BIT(29) 531#define PHIMR_PSTIMEOUT BIT(29)
508#define PHIMR_GTINT4 BIT(28) 532#define PHIMR_GTINT4 BIT(28)
509#define PHIMR_GTINT3 BIT(27) 533#define PHIMR_GTINT3 BIT(27)
510#define PHIMR_TXBCNERR BIT(26) 534#define PHIMR_TXBCNERR BIT(26)
511#define PHIMR_TXBCNOK BIT(25) 535#define PHIMR_TXBCNOK BIT(25)
512#define PHIMR_TSF_BIT32_TOGGLE BIT(24) 536#define PHIMR_TSF_BIT32_TOGGLE BIT(24)
513#define PHIMR_BCNDMAINT3 BIT(23) 537#define PHIMR_BCNDMAINT3 BIT(23)
514#define PHIMR_BCNDMAINT2 BIT(22) 538#define PHIMR_BCNDMAINT2 BIT(22)
515#define PHIMR_BCNDMAINT1 BIT(21) 539#define PHIMR_BCNDMAINT1 BIT(21)
516#define PHIMR_BCNDMAINT0 BIT(20) 540#define PHIMR_BCNDMAINT0 BIT(20)
517#define PHIMR_BCNDOK3 BIT(19) 541#define PHIMR_BCNDOK3 BIT(19)
518#define PHIMR_BCNDOK2 BIT(18) 542#define PHIMR_BCNDOK2 BIT(18)
519#define PHIMR_BCNDOK1 BIT(17) 543#define PHIMR_BCNDOK1 BIT(17)
520#define PHIMR_BCNDOK0 BIT(16) 544#define PHIMR_BCNDOK0 BIT(16)
521#define PHIMR_HSISR_IND_ON BIT(15) 545#define PHIMR_HSISR_IND_ON BIT(15)
522#define PHIMR_BCNDMAINT_E BIT(14) 546#define PHIMR_BCNDMAINT_E BIT(14)
523#define PHIMR_ATIMEND_E BIT(13) 547#define PHIMR_ATIMEND_E BIT(13)
524#define PHIMR_ATIM_CTW_END BIT(12) 548#define PHIMR_ATIM_CTW_END BIT(12)
525#define PHIMR_HISRE_IND BIT(11) 549#define PHIMR_HISRE_IND BIT(11)
526#define PHIMR_C2HCMD BIT(10) 550#define PHIMR_C2HCMD BIT(10)
527#define PHIMR_CPWM2 BIT(9) 551#define PHIMR_CPWM2 BIT(9)
528#define PHIMR_CPWM BIT(8) 552#define PHIMR_CPWM BIT(8)
529#define PHIMR_HIGHDOK BIT(7) 553#define PHIMR_HIGHDOK BIT(7)
530#define PHIMR_MGNTDOK BIT(6) 554#define PHIMR_MGNTDOK BIT(6)
531#define PHIMR_BKDOK BIT(5) 555#define PHIMR_BKDOK BIT(5)
532#define PHIMR_BEDOK BIT(4) 556#define PHIMR_BEDOK BIT(4)
533#define PHIMR_VIDOK BIT(3) 557#define PHIMR_VIDOK BIT(3)
534#define PHIMR_VODOK BIT(2) 558#define PHIMR_VODOK BIT(2)
535#define PHIMR_RDU BIT(1) 559#define PHIMR_RDU BIT(1)
536#define PHIMR_ROK BIT(0) 560#define PHIMR_ROK BIT(0)
537 561
538/* PCIE Host Interrupt Status Extension bit */ 562/* PCIE Host Interrupt Status Extension bit */
539#define PHIMR_BCNDMAINT7 BIT(23) 563#define PHIMR_BCNDMAINT7 BIT(23)
540#define PHIMR_BCNDMAINT6 BIT(22) 564#define PHIMR_BCNDMAINT6 BIT(22)
541#define PHIMR_BCNDMAINT5 BIT(21) 565#define PHIMR_BCNDMAINT5 BIT(21)
542#define PHIMR_BCNDMAINT4 BIT(20) 566#define PHIMR_BCNDMAINT4 BIT(20)
543#define PHIMR_BCNDOK7 BIT(19) 567#define PHIMR_BCNDOK7 BIT(19)
544#define PHIMR_BCNDOK6 BIT(18) 568#define PHIMR_BCNDOK6 BIT(18)
545#define PHIMR_BCNDOK5 BIT(17) 569#define PHIMR_BCNDOK5 BIT(17)
546#define PHIMR_BCNDOK4 BIT(16) 570#define PHIMR_BCNDOK4 BIT(16)
547/* bit12-15: RSVD */ 571/* bit12-15: RSVD */
548#define PHIMR_TXERR BIT(11) 572#define PHIMR_TXERR BIT(11)
549#define PHIMR_RXERR BIT(10) 573#define PHIMR_RXERR BIT(10)
550#define PHIMR_TXFOVW BIT(9) 574#define PHIMR_TXFOVW BIT(9)
551#define PHIMR_RXFOVW BIT(8) 575#define PHIMR_RXFOVW BIT(8)
552/* bit2-7: RSV */ 576/* bit2-7: RSVD */
553#define PHIMR_OCPINT BIT(1) 577#define PHIMR_OCPINT BIT(1)
554 578
555#define HWSET_MAX_SIZE 256 579#define HWSET_MAX_SIZE 256
556#define EFUSE_MAX_SECTION 32 580#define EFUSE_MAX_SECTION 32
557#define EFUSE_REAL_CONTENT_LEN 512 581#define EFUSE_REAL_CONTENT_LEN 512
558#define EFUSE_OOB_PROTECT_BYTES 15 582#define EFUSE_OOB_PROTECT_BYTES 15
559 583
560#define EEPROM_DEFAULT_TSSI 0x0 584#define EEPROM_DEFAULT_TSSI 0x0
561#define EEPROM_DEFAULT_TXPOWERDIFF 0x0 585#define EEPROM_DEFAULT_TXPOWERDIFF 0x0
562#define EEPROM_DEFAULT_CRYSTALCAP 0x5 586#define EEPROM_DEFAULT_CRYSTALCAP 0x5
563#define EEPROM_DEFAULT_BOARDTYPE 0x02 587#define EEPROM_DEFAULT_BOARDTYPE 0x02
564#define EEPROM_DEFAULT_TXPOWER 0x1010 588#define EEPROM_DEFAULT_TXPOWER 0x1010
565#define EEPROM_DEFAULT_HT2T_TXPWR 0x10 589#define EEPROM_DEFAULT_HT2T_TXPWR 0x10
566 590
567#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3 591#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3
568#define EEPROM_DEFAULT_THERMALMETER 0x12 592#define EEPROM_DEFAULT_THERMALMETER 0x12
569#define EEPROM_DEFAULT_ANTTXPOWERDIFF 0x0 593#define EEPROM_DEFAULT_ANTTXPOWERDIFF 0x0
570#define EEPROM_DEFAULT_TXPWDIFF_CRYSTALCAP 0x5 594#define EEPROM_DEFAULT_TXPWDIFF_CRYSTALCAP 0x5
571#define EEPROM_DEFAULT_TXPOWERLEVEL 0x22 595#define EEPROM_DEFAULT_TXPOWERLEVEL 0x22
572#define EEPROM_DEFAULT_HT40_2SDIFF 0x0 596#define EEPROM_DEFAULT_HT40_2SDIFF 0x0
573#define EEPROM_DEFAULT_HT20_DIFF 2 597#define EEPROM_DEFAULT_HT20_DIFF 2
574#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3 598#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3
575#define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0 599#define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0
576#define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0 600#define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0
577 601
578 602#define EEPROM_DEFAULT_PID 0x1234
579#define EEPROM_DEFAULT_PID 0x1234 603#define EEPROM_DEFAULT_VID 0x5678
580#define EEPROM_DEFAULT_VID 0x5678 604#define EEPROM_DEFAULT_CUSTOMERID 0xAB
581#define EEPROM_DEFAULT_CUSTOMERID 0xAB
582#define EEPROM_DEFAULT_SUBCUSTOMERID 0xCD 605#define EEPROM_DEFAULT_SUBCUSTOMERID 0xCD
583#define EEPROM_DEFAULT_VERSION 0 606#define EEPROM_DEFAULT_VERSION 0
584 607
585#define EEPROM_CHANNEL_PLAN_FCC 0x0 608#define EEPROM_CHANNEL_PLAN_FCC 0x0
586#define EEPROM_CHANNEL_PLAN_IC 0x1 609#define EEPROM_CHANNEL_PLAN_IC 0x1
587#define EEPROM_CHANNEL_PLAN_ETSI 0x2 610#define EEPROM_CHANNEL_PLAN_ETSI 0x2
588#define EEPROM_CHANNEL_PLAN_SPAIN 0x3 611#define EEPROM_CHANNEL_PLAN_SPAIN 0x3
589#define EEPROM_CHANNEL_PLAN_FRANCE 0x4 612#define EEPROM_CHANNEL_PLAN_FRANCE 0x4
590#define EEPROM_CHANNEL_PLAN_MKK 0x5 613#define EEPROM_CHANNEL_PLAN_MKK 0x5
591#define EEPROM_CHANNEL_PLAN_MKK1 0x6 614#define EEPROM_CHANNEL_PLAN_MKK1 0x6
592#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 615#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
593#define EEPROM_CHANNEL_PLAN_TELEC 0x8 616#define EEPROM_CHANNEL_PLAN_TELEC 0x8
594#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 617#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9
595#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA 618#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
596#define EEPROM_CHANNEL_PLAN_NCC 0xB 619#define EEPROM_CHANNEL_PLAN_NCC 0xB
597#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 620#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
598 621
599#define EEPROM_CID_DEFAULT 0x0 622#define EEPROM_CID_DEFAULT 0x0
600#define EEPROM_CID_TOSHIBA 0x4 623#define EEPROM_CID_TOSHIBA 0x4
601#define EEPROM_CID_CCX 0x10 624#define EEPROM_CID_CCX 0x10
602#define EEPROM_CID_QMI 0x0D 625#define EEPROM_CID_QMI 0x0D
603#define EEPROM_CID_WHQL 0xFE 626#define EEPROM_CID_WHQL 0xFE
604 627
605#define RTL8192_EEPROM_ID 0x8129 628#define RTL8192_EEPROM_ID 0x8129
606 629
607#define RTL8190_EEPROM_ID 0x8129 630#define RTL8190_EEPROM_ID 0x8129
608#define EEPROM_HPON 0x02 631#define EEPROM_HPON 0x02
609#define EEPROM_CLK 0x06 632#define EEPROM_CLK 0x06
610#define EEPROM_TESTR 0x08 633#define EEPROM_TESTR 0x08
611 634
612#define EEPROM_VID 0x49 635#define EEPROM_VID 0x49
613#define EEPROM_DID 0x4B 636#define EEPROM_DID 0x4B
614#define EEPROM_SVID 0x4D 637#define EEPROM_SVID 0x4D
615#define EEPROM_SMID 0x4F 638#define EEPROM_SMID 0x4F
616 639
617#define EEPROM_MAC_ADDR 0x67 640#define EEPROM_MAC_ADDR 0x67
618 641
619#define EEPROM_CCK_TX_PWR_INX 0x5A 642#define EEPROM_CCK_TX_PWR_INX 0x5A
620#define EEPROM_HT40_1S_TX_PWR_INX 0x60 643#define EEPROM_HT40_1S_TX_PWR_INX 0x60
621#define EEPROM_HT40_2S_TX_PWR_INX_DIFF 0x66 644#define EEPROM_HT40_2S_TX_PWR_INX_DIFF 0x66
622#define EEPROM_HT20_TX_PWR_INX_DIFF 0x69 645#define EEPROM_HT20_TX_PWR_INX_DIFF 0x69
623#define EEPROM_OFDM_TX_PWR_INX_DIFF 0x6C 646#define EEPROM_OFDM_TX_PWR_INX_DIFF 0x6C
624#define EEPROM_HT40_MAX_PWR_OFFSET 0x25 647#define EEPROM_HT40_MAX_PWR_OFFSET 0x25
625#define EEPROM_HT20_MAX_PWR_OFFSET 0x22 648#define EEPROM_HT20_MAX_PWR_OFFSET 0x22
626 649
627#define EEPROM_THERMAL_METER 0x2a 650#define EEPROM_THERMAL_METER 0x2a
628#define EEPROM_XTAL_K 0x78 651#define EEPROM_XTAL_K 0x78
629#define EEPROM_RF_OPT1 0x79 652#define EEPROM_RF_OPT1 0x79
630#define EEPROM_RF_OPT2 0x7A 653#define EEPROM_RF_OPT2 0x7A
631#define EEPROM_RF_OPT3 0x7B 654#define EEPROM_RF_OPT3 0x7B
632#define EEPROM_RF_OPT4 0x7C 655#define EEPROM_RF_OPT4 0x7C
633#define EEPROM_CHANNEL_PLAN 0x28 656#define EEPROM_CHANNEL_PLAN 0x28
634#define EEPROM_VERSION 0x30 657#define EEPROM_VERSION 0x30
635#define EEPROM_CUSTOMER_ID 0x31 658#define EEPROM_CUSTOMER_ID 0x31
636 659
637#define EEPROM_PWRDIFF 0x54 660#define EEPROM_PWRDIFF 0x54
638 661
639#define EEPROM_TXPOWERCCK 0x10 662#define EEPROM_TXPOWERCCK 0x10
640#define EEPROM_TXPOWERHT40_1S 0x16 663#define EEPROM_TXPOWERHT40_1S 0x16
641#define EEPROM_TXPOWERHT40_2SDIFF 0x66 664#define EEPROM_TXPOWERHT40_2SDIFF 0x66
642#define EEPROM_TXPOWERHT20DIFF 0x1C 665#define EEPROM_TXPOWERHT20DIFF 0x1C
643#define EEPROM_TXPOWER_OFDMDIFF 0x1F 666#define EEPROM_TXPOWER_OFDMDIFF 0x1F
644 667
645#define EEPROM_TXPWR_GROUP 0x22 668#define EEPROM_TXPWR_GROUP 0x22
646 669
@@ -649,169 +672,169 @@
649 672
650#define EEPROM_CHANNELPLAN 0x28 673#define EEPROM_CHANNELPLAN 0x28
651 674
652#define RF_OPTION1 0x2B 675#define RF_OPTION1 0x2B
653#define RF_OPTION2 0x2C 676#define RF_OPTION2 0x2C
654#define RF_OPTION3 0x2D 677#define RF_OPTION3 0x2D
655#define RF_OPTION4 0x2E 678#define RF_OPTION4 0x2E
656 679
657#define STOPBECON BIT(6) 680#define STOPBECON BIT(6)
658#define STOPHIGHT BIT(5) 681#define STOPHIGHT BIT(5)
659#define STOPMGT BIT(4) 682#define STOPMGT BIT(4)
660#define STOPVO BIT(3) 683#define STOPVO BIT(3)
661#define STOPVI BIT(2) 684#define STOPVI BIT(2)
662#define STOPBE BIT(1) 685#define STOPBE BIT(1)
663#define STOPBK BIT(0) 686#define STOPBK BIT(0)
664 687
665#define RCR_APPFCS BIT(31) 688#define RCR_APPFCS BIT(31)
666#define RCR_APP_MIC BIT(30) 689#define RCR_APP_MIC BIT(30)
667#define RCR_APP_ICV BIT(29) 690#define RCR_APP_ICV BIT(29)
668#define RCR_APP_PHYST_RXFF BIT(28) 691#define RCR_APP_PHYST_RXFF BIT(28)
669#define RCR_APP_BA_SSN BIT(27) 692#define RCR_APP_BA_SSN BIT(27)
670#define RCR_ENMBID BIT(24) 693#define RCR_ENMBID BIT(24)
671#define RCR_LSIGEN BIT(23) 694#define RCR_LSIGEN BIT(23)
672#define RCR_MFBEN BIT(22) 695#define RCR_MFBEN BIT(22)
673#define RCR_HTC_LOC_CTRL BIT(14) 696#define RCR_HTC_LOC_CTRL BIT(14)
674#define RCR_AMF BIT(13) 697#define RCR_AMF BIT(13)
675#define RCR_ACF BIT(12) 698#define RCR_ACF BIT(12)
676#define RCR_ADF BIT(11) 699#define RCR_ADF BIT(11)
677#define RCR_AICV BIT(9) 700#define RCR_AICV BIT(9)
678#define RCR_ACRC32 BIT(8) 701#define RCR_ACRC32 BIT(8)
679#define RCR_CBSSID_BCN BIT(7) 702#define RCR_CBSSID_BCN BIT(7)
680#define RCR_CBSSID_DATA BIT(6) 703#define RCR_CBSSID_DATA BIT(6)
681#define RCR_CBSSID RCR_CBSSID_DATA 704#define RCR_CBSSID RCR_CBSSID_DATA
682#define RCR_APWRMGT BIT(5) 705#define RCR_APWRMGT BIT(5)
683#define RCR_ADD3 BIT(4) 706#define RCR_ADD3 BIT(4)
684#define RCR_AB BIT(3) 707#define RCR_AB BIT(3)
685#define RCR_AM BIT(2) 708#define RCR_AM BIT(2)
686#define RCR_APM BIT(1) 709#define RCR_APM BIT(1)
687#define RCR_AAP BIT(0) 710#define RCR_AAP BIT(0)
688#define RCR_MXDMA_OFFSET 8 711#define RCR_MXDMA_OFFSET 8
689#define RCR_FIFO_OFFSET 13 712#define RCR_FIFO_OFFSET 13
690 713
691#define RSV_CTRL 0x001C 714#define RSV_CTRL 0x001C
692#define RD_CTRL 0x0524 715#define RD_CTRL 0x0524
693 716
694#define REG_USB_INFO 0xFE17 717#define REG_USB_INFO 0xFE17
695#define REG_USB_SPECIAL_OPTION 0xFE55 718#define REG_USB_SPECIAL_OPTION 0xFE55
696#define REG_USB_DMA_AGG_TO 0xFE5B 719#define REG_USB_DMA_AGG_TO 0xFE5B
697#define REG_USB_AGG_TO 0xFE5C 720#define REG_USB_AGG_TO 0xFE5C
698#define REG_USB_AGG_TH 0xFE5D 721#define REG_USB_AGG_TH 0xFE5D
699 722
700#define REG_USB_VID 0xFE60 723#define REG_USB_VID 0xFE60
701#define REG_USB_PID 0xFE62 724#define REG_USB_PID 0xFE62
702#define REG_USB_OPTIONAL 0xFE64 725#define REG_USB_OPTIONAL 0xFE64
703#define REG_USB_CHIRP_K 0xFE65 726#define REG_USB_CHIRP_K 0xFE65
704#define REG_USB_PHY 0xFE66 727#define REG_USB_PHY 0xFE66
705#define REG_USB_MAC_ADDR 0xFE70 728#define REG_USB_MAC_ADDR 0xFE70
706#define REG_USB_HRPWM 0xFE58 729#define REG_USB_HRPWM 0xFE58
707#define REG_USB_HCPWM 0xFE57 730#define REG_USB_HCPWM 0xFE57
708 731
709#define SW18_FPWM BIT(3) 732#define SW18_FPWM BIT(3)
710 733
711#define ISO_MD2PP BIT(0) 734#define ISO_MD2PP BIT(0)
712#define ISO_UA2USB BIT(1) 735#define ISO_UA2USB BIT(1)
713#define ISO_UD2CORE BIT(2) 736#define ISO_UD2CORE BIT(2)
714#define ISO_PA2PCIE BIT(3) 737#define ISO_PA2PCIE BIT(3)
715#define ISO_PD2CORE BIT(4) 738#define ISO_PD2CORE BIT(4)
716#define ISO_IP2MAC BIT(5) 739#define ISO_IP2MAC BIT(5)
717#define ISO_DIOP BIT(6) 740#define ISO_DIOP BIT(6)
718#define ISO_DIOE BIT(7) 741#define ISO_DIOE BIT(7)
719#define ISO_EB2CORE BIT(8) 742#define ISO_EB2CORE BIT(8)
720#define ISO_DIOR BIT(9) 743#define ISO_DIOR BIT(9)
721 744
722#define PWC_EV25V BIT(14) 745#define PWC_EV25V BIT(14)
723#define PWC_EV12V BIT(15) 746#define PWC_EV12V BIT(15)
724 747
725#define FEN_BBRSTB BIT(0) 748#define FEN_BBRSTB BIT(0)
726#define FEN_BB_GLB_RSTn BIT(1) 749#define FEN_BB_GLB_RSTN BIT(1)
727#define FEN_USBA BIT(2) 750#define FEN_USBA BIT(2)
728#define FEN_UPLL BIT(3) 751#define FEN_UPLL BIT(3)
729#define FEN_USBD BIT(4) 752#define FEN_USBD BIT(4)
730#define FEN_DIO_PCIE BIT(5) 753#define FEN_DIO_PCIE BIT(5)
731#define FEN_PCIEA BIT(6) 754#define FEN_PCIEA BIT(6)
732#define FEN_PPLL BIT(7) 755#define FEN_PPLL BIT(7)
733#define FEN_PCIED BIT(8) 756#define FEN_PCIED BIT(8)
734#define FEN_DIOE BIT(9) 757#define FEN_DIOE BIT(9)
735#define FEN_CPUEN BIT(10) 758#define FEN_CPUEN BIT(10)
736#define FEN_DCORE BIT(11) 759#define FEN_DCORE BIT(11)
737#define FEN_ELDR BIT(12) 760#define FEN_ELDR BIT(12)
738#define FEN_DIO_RF BIT(13) 761#define FEN_DIO_RF BIT(13)
739#define FEN_HWPDN BIT(14) 762#define FEN_HWPDN BIT(14)
740#define FEN_MREGEN BIT(15) 763#define FEN_MREGEN BIT(15)
741 764
742#define PFM_LDALL BIT(0) 765#define PFM_LDALL BIT(0)
743#define PFM_ALDN BIT(1) 766#define PFM_ALDN BIT(1)
744#define PFM_LDKP BIT(2) 767#define PFM_LDKP BIT(2)
745#define PFM_WOWL BIT(3) 768#define PFM_WOWL BIT(3)
746#define EnPDN BIT(4) 769#define ENPDN BIT(4)
747#define PDN_PL BIT(5) 770#define PDN_PL BIT(5)
748#define APFM_ONMAC BIT(8) 771#define APFM_ONMAC BIT(8)
749#define APFM_OFF BIT(9) 772#define APFM_OFF BIT(9)
750#define APFM_RSM BIT(10) 773#define APFM_RSM BIT(10)
751#define AFSM_HSUS BIT(11) 774#define AFSM_HSUS BIT(11)
752#define AFSM_PCIE BIT(12) 775#define AFSM_PCIE BIT(12)
753#define APDM_MAC BIT(13) 776#define APDM_MAC BIT(13)
754#define APDM_HOST BIT(14) 777#define APDM_HOST BIT(14)
755#define APDM_HPDN BIT(15) 778#define APDM_HPDN BIT(15)
756#define RDY_MACON BIT(16) 779#define RDY_MACON BIT(16)
757#define SUS_HOST BIT(17) 780#define SUS_HOST BIT(17)
758#define ROP_ALD BIT(20) 781#define ROP_ALD BIT(20)
759#define ROP_PWR BIT(21) 782#define ROP_PWR BIT(21)
760#define ROP_SPS BIT(22) 783#define ROP_SPS BIT(22)
761#define SOP_MRST BIT(25) 784#define SOP_MRST BIT(25)
762#define SOP_FUSE BIT(26) 785#define SOP_FUSE BIT(26)
763#define SOP_ABG BIT(27) 786#define SOP_ABG BIT(27)
764#define SOP_AMB BIT(28) 787#define SOP_AMB BIT(28)
765#define SOP_RCK BIT(29) 788#define SOP_RCK BIT(29)
766#define SOP_A8M BIT(30) 789#define SOP_A8M BIT(30)
767#define XOP_BTCK BIT(31) 790#define XOP_BTCK BIT(31)
768 791
769#define ANAD16V_EN BIT(0) 792#define ANAD16V_EN BIT(0)
770#define ANA8M BIT(1) 793#define ANA8M BIT(1)
771#define MACSLP BIT(4) 794#define MACSLP BIT(4)
772#define LOADER_CLK_EN BIT(5) 795#define LOADER_CLK_EN BIT(5)
773#define _80M_SSC_DIS BIT(7) 796#define _80M_SSC_DIS BIT(7)
774#define _80M_SSC_EN_HO BIT(8) 797#define _80M_SSC_EN_HO BIT(8)
775#define PHY_SSC_RSTB BIT(9) 798#define PHY_SSC_RSTB BIT(9)
776#define SEC_CLK_EN BIT(10) 799#define SEC_CLK_EN BIT(10)
777#define MAC_CLK_EN BIT(11) 800#define MAC_CLK_EN BIT(11)
778#define SYS_CLK_EN BIT(12) 801#define SYS_CLK_EN BIT(12)
779#define RING_CLK_EN BIT(13) 802#define RING_CLK_EN BIT(13)
780 803
781#define BOOT_FROM_EEPROM BIT(4) 804#define BOOT_FROM_EEPROM BIT(4)
782#define EEPROM_EN BIT(5) 805#define EEPROM_EN BIT(5)
783 806
784#define AFE_BGEN BIT(0) 807#define AFE_BGEN BIT(0)
785#define AFE_MBEN BIT(1) 808#define AFE_MBEN BIT(1)
786#define MAC_ID_EN BIT(7) 809#define MAC_ID_EN BIT(7)
787 810
788#define WLOCK_ALL BIT(0) 811#define WLOCK_ALL BIT(0)
789#define WLOCK_00 BIT(1) 812#define WLOCK_00 BIT(1)
790#define WLOCK_04 BIT(2) 813#define WLOCK_04 BIT(2)
791#define WLOCK_08 BIT(3) 814#define WLOCK_08 BIT(3)
792#define WLOCK_40 BIT(4) 815#define WLOCK_40 BIT(4)
793#define R_DIS_PRST_0 BIT(5) 816#define R_DIS_PRST_0 BIT(5)
794#define R_DIS_PRST_1 BIT(6) 817#define R_DIS_PRST_1 BIT(6)
795#define LOCK_ALL_EN BIT(7) 818#define LOCK_ALL_EN BIT(7)
796 819
797#define RF_EN BIT(0) 820#define RF_EN BIT(0)
798#define RF_RSTB BIT(1) 821#define RF_RSTB BIT(1)
799#define RF_SDMRSTB BIT(2) 822#define RF_SDMRSTB BIT(2)
800 823
801#define LDA15_EN BIT(0) 824#define LDA15_EN BIT(0)
802#define LDA15_STBY BIT(1) 825#define LDA15_STBY BIT(1)
803#define LDA15_OBUF BIT(2) 826#define LDA15_OBUF BIT(2)
804#define LDA15_REG_VOS BIT(3) 827#define LDA15_REG_VOS BIT(3)
805#define _LDA15_VOADJ(x) (((x) & 0x7) << 4) 828#define _LDA15_VOADJ(x) (((x) & 0x7) << 4)
806 829
807#define LDV12_EN BIT(0) 830#define LDV12_EN BIT(0)
808#define LDV12_SDBY BIT(1) 831#define LDV12_SDBY BIT(1)
809#define LPLDO_HSM BIT(2) 832#define LPLDO_HSM BIT(2)
810#define LPLDO_LSM_DIS BIT(3) 833#define LPLDO_LSM_DIS BIT(3)
811#define _LDV12_VADJ(x) (((x) & 0xF) << 4) 834#define _LDV12_VADJ(x) (((x) & 0xF) << 4)
812 835
813#define XTAL_EN BIT(0) 836#define XTAL_EN BIT(0)
814#define XTAL_BSEL BIT(1) 837#define XTAL_BSEL BIT(1)
815#define _XTAL_BOSC(x) (((x) & 0x3) << 2) 838#define _XTAL_BOSC(x) (((x) & 0x3) << 2)
816#define _XTAL_CADJ(x) (((x) & 0xF) << 4) 839#define _XTAL_CADJ(x) (((x) & 0xF) << 4)
817#define XTAL_GATE_USB BIT(8) 840#define XTAL_GATE_USB BIT(8)
@@ -826,146 +849,146 @@
826#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21) 849#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21)
827#define _XTAL_GPIO(x) (((x) & 0x7) << 23) 850#define _XTAL_GPIO(x) (((x) & 0x7) << 23)
828 851
829#define CKDLY_AFE BIT(26) 852#define CKDLY_AFE BIT(26)
830#define CKDLY_USB BIT(27) 853#define CKDLY_USB BIT(27)
831#define CKDLY_DIG BIT(28) 854#define CKDLY_DIG BIT(28)
832#define CKDLY_BT BIT(29) 855#define CKDLY_BT BIT(29)
833 856
834#define APLL_EN BIT(0) 857#define APLL_EN BIT(0)
835#define APLL_320_EN BIT(1) 858#define APLL_320_EN BIT(1)
836#define APLL_FREF_SEL BIT(2) 859#define APLL_FREF_SEL BIT(2)
837#define APLL_EDGE_SEL BIT(3) 860#define APLL_EDGE_SEL BIT(3)
838#define APLL_WDOGB BIT(4) 861#define APLL_WDOGB BIT(4)
839#define APLL_LPFEN BIT(5) 862#define APLL_LPFEN BIT(5)
840 863
841#define APLL_REF_CLK_13MHZ 0x1 864#define APLL_REF_CLK_13MHZ 0x1
842#define APLL_REF_CLK_19_2MHZ 0x2 865#define APLL_REF_CLK_19_2MHZ 0x2
843#define APLL_REF_CLK_20MHZ 0x3 866#define APLL_REF_CLK_20MHZ 0x3
844#define APLL_REF_CLK_25MHZ 0x4 867#define APLL_REF_CLK_25MHZ 0x4
845#define APLL_REF_CLK_26MHZ 0x5 868#define APLL_REF_CLK_26MHZ 0x5
846#define APLL_REF_CLK_38_4MHZ 0x6 869#define APLL_REF_CLK_38_4MHZ 0x6
847#define APLL_REF_CLK_40MHZ 0x7 870#define APLL_REF_CLK_40MHZ 0x7
848 871
849#define APLL_320EN BIT(14) 872#define APLL_320EN BIT(14)
850#define APLL_80EN BIT(15) 873#define APLL_80EN BIT(15)
851#define APLL_1MEN BIT(24) 874#define APLL_1MEN BIT(24)
852 875
853#define ALD_EN BIT(18) 876#define ALD_EN BIT(18)
854#define EF_PD BIT(19) 877#define EF_PD BIT(19)
855#define EF_FLAG BIT(31) 878#define EF_FLAG BIT(31)
856 879
857#define EF_TRPT BIT(7) 880#define EF_TRPT BIT(7)
858#define LDOE25_EN BIT(31) 881#define LDOE25_EN BIT(31)
859 882
860#define RSM_EN BIT(0) 883#define RSM_EN BIT(0)
861#define Timer_EN BIT(4) 884#define TIMER_EN BIT(4)
862 885
863#define TRSW0EN BIT(2) 886#define TRSW0EN BIT(2)
864#define TRSW1EN BIT(3) 887#define TRSW1EN BIT(3)
865#define EROM_EN BIT(4) 888#define EROM_EN BIT(4)
866#define EnBT BIT(5) 889#define ENBT BIT(5)
867#define EnUart BIT(8) 890#define ENUART BIT(8)
868#define Uart_910 BIT(9) 891#define UART_910 BIT(9)
869#define EnPMAC BIT(10) 892#define ENPMAC BIT(10)
870#define SIC_SWRST BIT(11) 893#define SIC_SWRST BIT(11)
871#define EnSIC BIT(12) 894#define ENSIC BIT(12)
872#define SIC_23 BIT(13) 895#define SIC_23 BIT(13)
873#define EnHDP BIT(14) 896#define ENHDP BIT(14)
874#define SIC_LBK BIT(15) 897#define SIC_LBK BIT(15)
875 898
876#define LED0PL BIT(4) 899#define LED0PL BIT(4)
877#define LED1PL BIT(12) 900#define LED1PL BIT(12)
878#define LED0DIS BIT(7) 901#define LED0DIS BIT(7)
879 902
880#define MCUFWDL_EN BIT(0) 903#define MCUFWDL_EN BIT(0)
881#define MCUFWDL_RDY BIT(1) 904#define MCUFWDL_RDY BIT(1)
882#define FWDL_ChkSum_rpt BIT(2) 905#define FWDL_CHKSUM_RPT BIT(2)
883#define MACINI_RDY BIT(3) 906#define MACINI_RDY BIT(3)
884#define BBINI_RDY BIT(4) 907#define BBINI_RDY BIT(4)
885#define RFINI_RDY BIT(5) 908#define RFINI_RDY BIT(5)
886#define WINTINI_RDY BIT(6) 909#define WINTINI_RDY BIT(6)
887#define CPRST BIT(23) 910#define CPRST BIT(23)
888 911
889#define XCLK_VLD BIT(0) 912#define XCLK_VLD BIT(0)
890#define ACLK_VLD BIT(1) 913#define ACLK_VLD BIT(1)
891#define UCLK_VLD BIT(2) 914#define UCLK_VLD BIT(2)
892#define PCLK_VLD BIT(3) 915#define PCLK_VLD BIT(3)
893#define PCIRSTB BIT(4) 916#define PCIRSTB BIT(4)
894#define V15_VLD BIT(5) 917#define V15_VLD BIT(5)
895#define TRP_B15V_EN BIT(7) 918#define TRP_B15V_EN BIT(7)
896#define SIC_IDLE BIT(8) 919#define SIC_IDLE BIT(8)
897#define BD_MAC2 BIT(9) 920#define BD_MAC2 BIT(9)
898#define BD_MAC1 BIT(10) 921#define BD_MAC1 BIT(10)
899#define IC_MACPHY_MODE BIT(11) 922#define IC_MACPHY_MODE BIT(11)
900#define BT_FUNC BIT(16) 923#define BT_FUNC BIT(16)
901#define VENDOR_ID BIT(19) 924#define VENDOR_ID BIT(19)
902#define PAD_HWPD_IDN BIT(22) 925#define PAD_HWPD_IDN BIT(22)
903#define TRP_VAUX_EN BIT(23) 926#define TRP_VAUX_EN BIT(23)
904#define TRP_BT_EN BIT(24) 927#define TRP_BT_EN BIT(24)
905#define BD_PKG_SEL BIT(25) 928#define BD_PKG_SEL BIT(25)
906#define BD_HCI_SEL BIT(26) 929#define BD_HCI_SEL BIT(26)
907#define TYPE_ID BIT(27) 930#define TYPE_ID BIT(27)
908 931
909#define CHIP_VER_RTL_MASK 0xF000 932#define CHIP_VER_RTL_MASK 0xF000
910#define CHIP_VER_RTL_SHIFT 12 933#define CHIP_VER_RTL_SHIFT 12
911 934
912#define REG_LBMODE (REG_CR + 3) 935#define REG_LBMODE (REG_CR + 3)
913 936
914#define HCI_TXDMA_EN BIT(0) 937#define HCI_TXDMA_EN BIT(0)
915#define HCI_RXDMA_EN BIT(1) 938#define HCI_RXDMA_EN BIT(1)
916#define TXDMA_EN BIT(2) 939#define TXDMA_EN BIT(2)
917#define RXDMA_EN BIT(3) 940#define RXDMA_EN BIT(3)
918#define PROTOCOL_EN BIT(4) 941#define PROTOCOL_EN BIT(4)
919#define SCHEDULE_EN BIT(5) 942#define SCHEDULE_EN BIT(5)
920#define MACTXEN BIT(6) 943#define MACTXEN BIT(6)
921#define MACRXEN BIT(7) 944#define MACRXEN BIT(7)
922#define ENSWBCN BIT(8) 945#define ENSWBCN BIT(8)
923#define ENSEC BIT(9) 946#define ENSEC BIT(9)
924 947
925#define _NETTYPE(x) (((x) & 0x3) << 16) 948#define _NETTYPE(x) (((x) & 0x3) << 16)
926#define MASK_NETTYPE 0x30000 949#define MASK_NETTYPE 0x30000
927#define NT_NO_LINK 0x0 950#define NT_NO_LINK 0x0
928#define NT_LINK_AD_HOC 0x1 951#define NT_LINK_AD_HOC 0x1
929#define NT_LINK_AP 0x2 952#define NT_LINK_AP 0x2
930#define NT_AS_AP 0x3 953#define NT_AS_AP 0x3
931 954
932#define _LBMODE(x) (((x) & 0xF) << 24) 955#define _LBMODE(x) (((x) & 0xF) << 24)
933#define MASK_LBMODE 0xF000000 956#define MASK_LBMODE 0xF000000
934#define LOOPBACK_NORMAL 0x0 957#define LOOPBACK_NORMAL 0x0
935#define LOOPBACK_IMMEDIATELY 0xB 958#define LOOPBACK_IMMEDIATELY 0xB
936#define LOOPBACK_MAC_DELAY 0x3 959#define LOOPBACK_MAC_DELAY 0x3
937#define LOOPBACK_PHY 0x1 960#define LOOPBACK_PHY 0x1
938#define LOOPBACK_DMA 0x7 961#define LOOPBACK_DMA 0x7
939 962
940#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) 963#define GET_RX_PAGE_SIZE(value) ((value) & 0xF)
941#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) 964#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4)
942#define _PSRX_MASK 0xF 965#define _PSRX_MASK 0xF
943#define _PSTX_MASK 0xF0 966#define _PSTX_MASK 0xF0
944#define _PSRX(x) (x) 967#define _PSRX(x) (x)
945#define _PSTX(x) ((x) << 4) 968#define _PSTX(x) ((x) << 4)
946 969
947#define PBP_64 0x0 970#define PBP_64 0x0
948#define PBP_128 0x1 971#define PBP_128 0x1
949#define PBP_256 0x2 972#define PBP_256 0x2
950#define PBP_512 0x3 973#define PBP_512 0x3
951#define PBP_1024 0x4 974#define PBP_1024 0x4
952 975
953#define RXDMA_ARBBW_EN BIT(0) 976#define RXDMA_ARBBW_EN BIT(0)
954#define RXSHFT_EN BIT(1) 977#define RXSHFT_EN BIT(1)
955#define RXDMA_AGG_EN BIT(2) 978#define RXDMA_AGG_EN BIT(2)
956#define QS_VO_QUEUE BIT(8) 979#define QS_VO_QUEUE BIT(8)
957#define QS_VI_QUEUE BIT(9) 980#define QS_VI_QUEUE BIT(9)
958#define QS_BE_QUEUE BIT(10) 981#define QS_BE_QUEUE BIT(10)
959#define QS_BK_QUEUE BIT(11) 982#define QS_BK_QUEUE BIT(11)
960#define QS_MANAGER_QUEUE BIT(12) 983#define QS_MANAGER_QUEUE BIT(12)
961#define QS_HIGH_QUEUE BIT(13) 984#define QS_HIGH_QUEUE BIT(13)
962 985
963#define HQSEL_VOQ BIT(0) 986#define HQSEL_VOQ BIT(0)
964#define HQSEL_VIQ BIT(1) 987#define HQSEL_VIQ BIT(1)
965#define HQSEL_BEQ BIT(2) 988#define HQSEL_BEQ BIT(2)
966#define HQSEL_BKQ BIT(3) 989#define HQSEL_BKQ BIT(3)
967#define HQSEL_MGTQ BIT(4) 990#define HQSEL_MGTQ BIT(4)
968#define HQSEL_HIQ BIT(5) 991#define HQSEL_HIQ BIT(5)
969 992
970#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) 993#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14)
971#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) 994#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12)
@@ -974,9 +997,9 @@
974#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6) 997#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6)
975#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4) 998#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4)
976 999
977#define QUEUE_LOW 1 1000#define QUEUE_LOW 1
978#define QUEUE_NORMAL 2 1001#define QUEUE_NORMAL 2
979#define QUEUE_HIGH 3 1002#define QUEUE_HIGH 3
980 1003
981#define _LLT_NO_ACTIVE 0x0 1004#define _LLT_NO_ACTIVE 0x0
982#define _LLT_WRITE_ACCESS 0x1 1005#define _LLT_WRITE_ACCESS 0x1
@@ -984,25 +1007,25 @@
984 1007
985#define _LLT_INIT_DATA(x) ((x) & 0xFF) 1008#define _LLT_INIT_DATA(x) ((x) & 0xFF)
986#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) 1009#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8)
987#define _LLT_OP(x) (((x) & 0x3) << 30) 1010#define _LLT_OP(x) (((x) & 0x3) << 30)
988#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) 1011#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3)
989 1012
990#define BB_WRITE_READ_MASK (BIT(31) | BIT(30)) 1013#define BB_WRITE_READ_MASK (BIT(31) | BIT(30))
991#define BB_WRITE_EN BIT(30) 1014#define BB_WRITE_EN BIT(30)
992#define BB_READ_EN BIT(31) 1015#define BB_READ_EN BIT(31)
993 1016
994#define _HPQ(x) ((x) & 0xFF) 1017#define _HPQ(x) ((x) & 0xFF)
995#define _LPQ(x) (((x) & 0xFF) << 8) 1018#define _LPQ(x) (((x) & 0xFF) << 8)
996#define _PUBQ(x) (((x) & 0xFF) << 16) 1019#define _PUBQ(x) (((x) & 0xFF) << 16)
997#define _NPQ(x) ((x) & 0xFF) 1020#define _NPQ(x) ((x) & 0xFF)
998 1021
999#define HPQ_PUBLIC_DIS BIT(24) 1022#define HPQ_PUBLIC_DIS BIT(24)
1000#define LPQ_PUBLIC_DIS BIT(25) 1023#define LPQ_PUBLIC_DIS BIT(25)
1001#define LD_RQPN BIT(31) 1024#define LD_RQPN BIT(31)
1002 1025
1003#define BCN_VALID BIT(16) 1026#define BCN_VALID BIT(16)
1004#define BCN_HEAD(x) (((x) & 0xFF) << 8) 1027#define BCN_HEAD(x) (((x) & 0xFF) << 8)
1005#define BCN_HEAD_MASK 0xFF00 1028#define BCN_HEAD_MASK 0xFF00
1006 1029
1007#define BLK_DESC_NUM_SHIFT 4 1030#define BLK_DESC_NUM_SHIFT 4
1008#define BLK_DESC_NUM_MASK 0xF 1031#define BLK_DESC_NUM_MASK 0xF
@@ -1022,9 +1045,9 @@
1022 1045
1023#define _RRSR_RSC(x) (((x) & 0x3) << 21) 1046#define _RRSR_RSC(x) (((x) & 0x3) << 21)
1024#define RRSR_RSC_RESERVED 0x0 1047#define RRSR_RSC_RESERVED 0x0
1025#define RRSR_RSC_UPPER_SUBCHANNEL 0x1 1048#define RRSR_RSC_UPPER_SUBCHANNEL 0x1
1026#define RRSR_RSC_LOWER_SUBCHANNEL 0x2 1049#define RRSR_RSC_LOWER_SUBCHANNEL 0x2
1027#define RRSR_RSC_DUPLICATE_MODE 0x3 1050#define RRSR_RSC_DUPLICATE_MODE 0x3
1028 1051
1029#define USE_SHORT_G1 BIT(20) 1052#define USE_SHORT_G1 BIT(20)
1030 1053
@@ -1037,8 +1060,8 @@
1037#define _AGGLMT_MCS6(x) (((x) & 0xF) << 24) 1060#define _AGGLMT_MCS6(x) (((x) & 0xF) << 24)
1038#define _AGGLMT_MCS7(x) (((x) & 0xF) << 28) 1061#define _AGGLMT_MCS7(x) (((x) & 0xF) << 28)
1039 1062
1040#define RETRY_LIMIT_SHORT_SHIFT 8 1063#define RETRY_LIMIT_SHORT_SHIFT 8
1041#define RETRY_LIMIT_LONG_SHIFT 0 1064#define RETRY_LIMIT_LONG_SHIFT 0
1042 1065
1043#define _DARF_RC1(x) ((x) & 0x1F) 1066#define _DARF_RC1(x) ((x) & 0x1F)
1044#define _DARF_RC2(x) (((x) & 0x1F) << 8) 1067#define _DARF_RC2(x) (((x) & 0x1F) << 8)
@@ -1058,123 +1081,123 @@
1058#define _RARF_RC7(x) (((x) & 0x1F) << 16) 1081#define _RARF_RC7(x) (((x) & 0x1F) << 16)
1059#define _RARF_RC8(x) (((x) & 0x1F) << 24) 1082#define _RARF_RC8(x) (((x) & 0x1F) << 24)
1060 1083
1061#define AC_PARAM_TXOP_LIMIT_OFFSET 16 1084#define AC_PARAM_TXOP_LIMIT_OFFSET 16
1062#define AC_PARAM_ECW_MAX_OFFSET 12 1085#define AC_PARAM_ECW_MAX_OFFSET 12
1063#define AC_PARAM_ECW_MIN_OFFSET 8 1086#define AC_PARAM_ECW_MIN_OFFSET 8
1064#define AC_PARAM_AIFS_OFFSET 0 1087#define AC_PARAM_AIFS_OFFSET 0
1065 1088
1066#define _AIFS(x) (x) 1089#define _AIFS(x) (x)
1067#define _ECW_MAX_MIN(x) ((x) << 8) 1090#define _ECW_MAX_MIN(x) ((x) << 8)
1068#define _TXOP_LIMIT(x) ((x) << 16) 1091#define _TXOP_LIMIT(x) ((x) << 16)
1069 1092
1070#define _BCNIFS(x) ((x) & 0xFF) 1093#define _BCNIFS(x) ((x) & 0xFF)
1071#define _BCNECW(x) ((((x) & 0xF)) << 8) 1094#define _BCNECW(x) ((((x) & 0xF)) << 8)
1072 1095
1073#define _LRL(x) ((x) & 0x3F) 1096#define _LRL(x) ((x) & 0x3F)
1074#define _SRL(x) (((x) & 0x3F) << 8) 1097#define _SRL(x) (((x) & 0x3F) << 8)
1075 1098
1076#define _SIFS_CCK_CTX(x) ((x) & 0xFF) 1099#define _SIFS_CCK_CTX(x) ((x) & 0xFF)
1077#define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8); 1100#define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8)
1078 1101
1079#define _SIFS_OFDM_CTX(x) ((x) & 0xFF) 1102#define _SIFS_OFDM_CTX(x) ((x) & 0xFF)
1080#define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8); 1103#define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8)
1081 1104
1082#define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8) 1105#define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8)
1083 1106
1084#define DIS_EDCA_CNT_DWN BIT(11) 1107#define DIS_EDCA_CNT_DWN BIT(11)
1085 1108
1086#define EN_MBSSID BIT(1) 1109#define EN_MBSSID BIT(1)
1087#define EN_TXBCN_RPT BIT(2) 1110#define EN_TXBCN_RPT BIT(2)
1088#define EN_BCN_FUNCTION BIT(3) 1111#define EN_BCN_FUNCTION BIT(3)
1089 1112
1090#define TSFTR_RST BIT(0) 1113#define TSFTR_RST BIT(0)
1091#define TSFTR1_RST BIT(1) 1114#define TSFTR1_RST BIT(1)
1092 1115
1093#define STOP_BCNQ BIT(6) 1116#define STOP_BCNQ BIT(6)
1094 1117
1095#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) 1118#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4)
1096#define DIS_TSF_UDT0_TEST_CHIP BIT(5) 1119#define DIS_TSF_UDT0_TEST_CHIP BIT(5)
1097 1120
1098#define AcmHw_HwEn BIT(0) 1121#define ACMHW_HWEN BIT(0)
1099#define AcmHw_BeqEn BIT(1) 1122#define ACMHW_BEQEN BIT(1)
1100#define AcmHw_ViqEn BIT(2) 1123#define ACMHW_VIQEN BIT(2)
1101#define AcmHw_VoqEn BIT(3) 1124#define ACMHW_VOQEN BIT(3)
1102#define AcmHw_BeqStatus BIT(4) 1125#define ACMHW_BEQSTATUS BIT(4)
1103#define AcmHw_ViqStatus BIT(5) 1126#define ACMHW_VIQSTATUS BIT(5)
1104#define AcmHw_VoqStatus BIT(6) 1127#define ACMHW_VOQSTATUS BIT(6)
1105 1128
1106#define APSDOFF BIT(6) 1129#define APSDOFF BIT(6)
1107#define APSDOFF_STATUS BIT(7) 1130#define APSDOFF_STATUS BIT(7)
1108 1131
1109#define BW_20MHZ BIT(2) 1132#define BW_20MHZ BIT(2)
1110 1133
1111#define RATE_BITMAP_ALL 0xFFFFF 1134#define RATE_BITMAP_ALL 0xFFFFF
1112 1135
1113#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 1136#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1
1114 1137
1115#define TSFRST BIT(0) 1138#define TSFRST BIT(0)
1116#define DIS_GCLK BIT(1) 1139#define DIS_GCLK BIT(1)
1117#define PAD_SEL BIT(2) 1140#define PAD_SEL BIT(2)
1118#define PWR_ST BIT(6) 1141#define PWR_ST BIT(6)
1119#define PWRBIT_OW_EN BIT(7) 1142#define PWRBIT_OW_EN BIT(7)
1120#define ACRC BIT(8) 1143#define ACRC BIT(8)
1121#define CFENDFORM BIT(9) 1144#define CFENDFORM BIT(9)
1122#define ICV BIT(10) 1145#define ICV BIT(10)
1123 1146
1124#define AAP BIT(0) 1147#define AAP BIT(0)
1125#define APM BIT(1) 1148#define APM BIT(1)
1126#define AM BIT(2) 1149#define AM BIT(2)
1127#define AB BIT(3) 1150#define AB BIT(3)
1128#define ADD3 BIT(4) 1151#define ADD3 BIT(4)
1129#define APWRMGT BIT(5) 1152#define APWRMGT BIT(5)
1130#define CBSSID BIT(6) 1153#define CBSSID BIT(6)
1131#define CBSSID_DATA BIT(6) 1154#define CBSSID_DATA BIT(6)
1132#define CBSSID_BCN BIT(7) 1155#define CBSSID_BCN BIT(7)
1133#define ACRC32 BIT(8) 1156#define ACRC32 BIT(8)
1134#define AICV BIT(9) 1157#define AICV BIT(9)
1135#define ADF BIT(11) 1158#define ADF BIT(11)
1136#define ACF BIT(12) 1159#define ACF BIT(12)
1137#define AMF BIT(13) 1160#define AMF BIT(13)
1138#define HTC_LOC_CTRL BIT(14) 1161#define HTC_LOC_CTRL BIT(14)
1139#define UC_DATA_EN BIT(16) 1162#define UC_DATA_EN BIT(16)
1140#define BM_DATA_EN BIT(17) 1163#define BM_DATA_EN BIT(17)
1141#define MFBEN BIT(22) 1164#define MFBEN BIT(22)
1142#define LSIGEN BIT(23) 1165#define LSIGEN BIT(23)
1143#define EnMBID BIT(24) 1166#define ENMBID BIT(24)
1144#define APP_BASSN BIT(27) 1167#define APP_BASSN BIT(27)
1145#define APP_PHYSTS BIT(28) 1168#define APP_PHYSTS BIT(28)
1146#define APP_ICV BIT(29) 1169#define APP_ICV BIT(29)
1147#define APP_MIC BIT(30) 1170#define APP_MIC BIT(30)
1148#define APP_FCS BIT(31) 1171#define APP_FCS BIT(31)
1149 1172
1150#define _MIN_SPACE(x) ((x) & 0x7) 1173#define _MIN_SPACE(x) ((x) & 0x7)
1151#define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3) 1174#define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3)
1152 1175
1153#define RXERR_TYPE_OFDM_PPDU 0 1176#define RXERR_TYPE_OFDM_PPDU 0
1154#define RXERR_TYPE_OFDM_FALSE_ALARM 1 1177#define RXERR_TYPE_OFDM_FALSE_ALARM 1
1155#define RXERR_TYPE_OFDM_MPDU_OK 2 1178#define RXERR_TYPE_OFDM_MPDU_OK 2
1156#define RXERR_TYPE_OFDM_MPDU_FAIL 3 1179#define RXERR_TYPE_OFDM_MPDU_FAIL 3
1157#define RXERR_TYPE_CCK_PPDU 4 1180#define RXERR_TYPE_CCK_PPDU 4
1158#define RXERR_TYPE_CCK_FALSE_ALARM 5 1181#define RXERR_TYPE_CCK_FALSE_ALARM 5
1159#define RXERR_TYPE_CCK_MPDU_OK 6 1182#define RXERR_TYPE_CCK_MPDU_OK 6
1160#define RXERR_TYPE_CCK_MPDU_FAIL 7 1183#define RXERR_TYPE_CCK_MPDU_FAIL 7
1161#define RXERR_TYPE_HT_PPDU 8 1184#define RXERR_TYPE_HT_PPDU 8
1162#define RXERR_TYPE_HT_FALSE_ALARM 9 1185#define RXERR_TYPE_HT_FALSE_ALARM 9
1163#define RXERR_TYPE_HT_MPDU_TOTAL 10 1186#define RXERR_TYPE_HT_MPDU_TOTAL 10
1164#define RXERR_TYPE_HT_MPDU_OK 11 1187#define RXERR_TYPE_HT_MPDU_OK 11
1165#define RXERR_TYPE_HT_MPDU_FAIL 12 1188#define RXERR_TYPE_HT_MPDU_FAIL 12
1166#define RXERR_TYPE_RX_FULL_DROP 15 1189#define RXERR_TYPE_RX_FULL_DROP 15
1167 1190
1168#define RXERR_COUNTER_MASK 0xFFFFF 1191#define RXERR_COUNTER_MASK 0xFFFFF
1169#define RXERR_RPT_RST BIT(27) 1192#define RXERR_RPT_RST BIT(27)
1170#define _RXERR_RPT_SEL(type) ((type) << 28) 1193#define _RXERR_RPT_SEL(type) ((type) << 28)
1171 1194
1172#define SCR_TxUseDK BIT(0) 1195#define SCR_TXUSEDK BIT(0)
1173#define SCR_RxUseDK BIT(1) 1196#define SCR_RXUSEDK BIT(1)
1174#define SCR_TxEncEnable BIT(2) 1197#define SCR_TXENCENABLE BIT(2)
1175#define SCR_RxDecEnable BIT(3) 1198#define SCR_RXDECENABLE BIT(3)
1176#define SCR_SKByA2 BIT(4) 1199#define SCR_SKBYA2 BIT(4)
1177#define SCR_NoSKMC BIT(5) 1200#define SCR_NOSKMC BIT(5)
1178#define SCR_TXBCUSEDK BIT(6) 1201#define SCR_TXBCUSEDK BIT(6)
1179#define SCR_RXBCUSEDK BIT(7) 1202#define SCR_RXBCUSEDK BIT(7)
1180 1203
@@ -1182,32 +1205,32 @@
1182#define USB_IS_FULL_SPEED 1 1205#define USB_IS_FULL_SPEED 1
1183#define USB_SPEED_MASK BIT(5) 1206#define USB_SPEED_MASK BIT(5)
1184 1207
1185#define USB_NORMAL_SIE_EP_MASK 0xF 1208#define USB_NORMAL_SIE_EP_MASK 0xF
1186#define USB_NORMAL_SIE_EP_SHIFT 4 1209#define USB_NORMAL_SIE_EP_SHIFT 4
1187 1210
1188#define USB_TEST_EP_MASK 0x30 1211#define USB_TEST_EP_MASK 0x30
1189#define USB_TEST_EP_SHIFT 4 1212#define USB_TEST_EP_SHIFT 4
1190 1213
1191#define USB_AGG_EN BIT(3) 1214#define USB_AGG_EN BIT(3)
1192 1215
1193#define MAC_ADDR_LEN 6 1216#define MAC_ADDR_LEN 6
1194#define LAST_ENTRY_OF_TX_PKT_BUFFER 255 1217#define LAST_ENTRY_OF_TX_PKT_BUFFER 255
1195 1218
1196#define POLLING_LLT_THRESHOLD 20 1219#define POLLING_LLT_THRESHOLD 20
1197#define POLLING_READY_TIMEOUT_COUNT 1000 1220#define POLLING_READY_TIMEOUT_COUNT 1000
1198 1221
1199#define MAX_MSS_DENSITY_2T 0x13 1222#define MAX_MSS_DENSITY_2T 0x13
1200#define MAX_MSS_DENSITY_1T 0x0A 1223#define MAX_MSS_DENSITY_1T 0x0A
1201 1224
1202#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6)) 1225#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6))
1203#define EPROM_CMD_CONFIG 0x3 1226#define EPROM_CMD_CONFIG 0x3
1204#define EPROM_CMD_LOAD 1 1227#define EPROM_CMD_LOAD 1
1205 1228
1206#define HWSET_MAX_SIZE_92S HWSET_MAX_SIZE 1229#define HWSET_MAX_SIZE_92S HWSET_MAX_SIZE
1207 1230
1208#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2) 1231#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2)
1209 1232
1210#define RPMAC_RESET 0x100 1233#define RPMAC_RESET 0x100
1211#define RPMAC_TXSTART 0x104 1234#define RPMAC_TXSTART 0x104
1212#define RPMAC_TXLEGACYSIG 0x108 1235#define RPMAC_TXLEGACYSIG 0x108
1213#define RPMAC_TXHTSIG1 0x10c 1236#define RPMAC_TXHTSIG1 0x10c
@@ -1223,12 +1246,12 @@
1223#define RPMAC_TXMACHEADER5 0x134 1246#define RPMAC_TXMACHEADER5 0x134
1224#define RPMAC_TXDADATYPE 0x138 1247#define RPMAC_TXDADATYPE 0x138
1225#define RPMAC_TXRANDOMSEED 0x13c 1248#define RPMAC_TXRANDOMSEED 0x13c
1226#define RPMAC_CCKPLCPPREAMBLE 0x140 1249#define RPMAC_CCKPLCPPREAMBLE 0x140
1227#define RPMAC_CCKPLCPHEADER 0x144 1250#define RPMAC_CCKPLCPHEADER 0x144
1228#define RPMAC_CCKCRC16 0x148 1251#define RPMAC_CCKCRC16 0x148
1229#define RPMAC_OFDMRXCRC32OK 0x170 1252#define RPMAC_OFDMRXCRC32OK 0x170
1230#define RPMAC_OFDMRXCRC32Er 0x174 1253#define RPMAC_OFDMRXCRC32ER 0x174
1231#define RPMAC_OFDMRXPARITYER 0x178 1254#define RPMAC_OFDMRXPARITYER 0x178
1232#define RPMAC_OFDMRXCRC8ER 0x17c 1255#define RPMAC_OFDMRXCRC8ER 0x17c
1233#define RPMAC_CCKCRXRC16ER 0x180 1256#define RPMAC_CCKCRXRC16ER 0x180
1234#define RPMAC_CCKCRXRC32ER 0x184 1257#define RPMAC_CCKCRXRC32ER 0x184
@@ -1245,44 +1268,44 @@
1245#define RFPGA0_RFTIMING1 0x810 1268#define RFPGA0_RFTIMING1 0x810
1246#define RFPGA0_RFTIMING2 0x814 1269#define RFPGA0_RFTIMING2 0x814
1247 1270
1248#define RFPGA0_XA_HSSIPARAMETER1 0x820 1271#define RFPGA0_XA_HSSIPARAMETER1 0x820
1249#define RFPGA0_XA_HSSIPARAMETER2 0x824 1272#define RFPGA0_XA_HSSIPARAMETER2 0x824
1250#define RFPGA0_XB_HSSIPARAMETER1 0x828 1273#define RFPGA0_XB_HSSIPARAMETER1 0x828
1251#define RFPGA0_XB_HSSIPARAMETER2 0x82c 1274#define RFPGA0_XB_HSSIPARAMETER2 0x82c
1252 1275
1253#define RFPGA0_XA_LSSIPARAMETER 0x840 1276#define RFPGA0_XA_LSSIPARAMETER 0x840
1254#define RFPGA0_XB_LSSIPARAMETER 0x844 1277#define RFPGA0_XB_LSSIPARAMETER 0x844
1255 1278
1256#define RFPGA0_RFWAKEUPPARAMETER 0x850 1279#define RFPGA0_RFWAKEUPPARAMETER 0x850
1257#define RFPGA0_RFSLEEPUPPARAMETER 0x854 1280#define RFPGA0_RFSLEEPUPPARAMETER 0x854
1258 1281
1259#define RFPGA0_XAB_SWITCHCONTROL 0x858 1282#define RFPGA0_XAB_SWITCHCONTROL 0x858
1260#define RFPGA0_XCD_SWITCHCONTROL 0x85c 1283#define RFPGA0_XCD_SWITCHCONTROL 0x85c
1261 1284
1262#define RFPGA0_XA_RFINTERFACEOE 0x860 1285#define RFPGA0_XA_RFINTERFACEOE 0x860
1263#define RFPGA0_XB_RFINTERFACEOE 0x864 1286#define RFPGA0_XB_RFINTERFACEOE 0x864
1264 1287
1265#define RFPGA0_XAB_RFINTERFACESW 0x870 1288#define RFPGA0_XAB_RFINTERFACESW 0x870
1266#define RFPGA0_XCD_RFINTERFACESW 0x874 1289#define RFPGA0_XCD_RFINTERFACESW 0x874
1267 1290
1268#define rFPGA0_XAB_RFPARAMETER 0x878 1291#define RFPGA0_XAB_RFPARAMETER 0x878
1269#define rFPGA0_XCD_RFPARAMETER 0x87c 1292#define RFPGA0_XCD_RFPARAMETER 0x87c
1270 1293
1271#define RFPGA0_ANALOGPARAMETER1 0x880 1294#define RFPGA0_ANALOGPARAMETER1 0x880
1272#define RFPGA0_ANALOGPARAMETER2 0x884 1295#define RFPGA0_ANALOGPARAMETER2 0x884
1273#define RFPGA0_ANALOGPARAMETER3 0x888 1296#define RFPGA0_ANALOGPARAMETER3 0x888
1274#define RFPGA0_ANALOGPARAMETER4 0x88c 1297#define RFPGA0_ANALOGPARAMETER4 0x88c
1275 1298
1276#define RFPGA0_XA_LSSIREADBACK 0x8a0 1299#define RFPGA0_XA_LSSIREADBACK 0x8a0
1277#define RFPGA0_XB_LSSIREADBACK 0x8a4 1300#define RFPGA0_XB_LSSIREADBACK 0x8a4
1278#define RFPGA0_XC_LSSIREADBACK 0x8a8 1301#define RFPGA0_XC_LSSIREADBACK 0x8a8
1279#define RFPGA0_XD_LSSIREADBACK 0x8ac 1302#define RFPGA0_XD_LSSIREADBACK 0x8ac
1280 1303
1281#define RFPGA0_PSDREPORT 0x8b4 1304#define RFPGA0_PSDREPORT 0x8b4
1282#define TRANSCEIVEA_HSPI_READBACK 0x8b8 1305#define TRANSCEIVEA_HSPI_READBACK 0x8b8
1283#define TRANSCEIVEB_HSPI_READBACK 0x8bc 1306#define TRANSCEIVEB_HSPI_READBACK 0x8bc
1284#define RFPGA0_XAB_RFINTERFACERB 0x8e0 1307#define RFPGA0_XAB_RFINTERFACERB 0x8e0
1285#define RFPGA0_XCD_RFINTERFACERB 0x8e4 1308#define RFPGA0_XCD_RFINTERFACERB 0x8e4
1286 1309
1287#define RFPGA1_RFMOD 0x900 1310#define RFPGA1_RFMOD 0x900
1288 1311
@@ -1293,12 +1316,12 @@
1293#define RCCK0_SYSTEM 0xa00 1316#define RCCK0_SYSTEM 0xa00
1294 1317
1295#define RCCK0_AFESETTING 0xa04 1318#define RCCK0_AFESETTING 0xa04
1296#define RCCK0_CCA 0xa08 1319#define RCCK0_CCA 0xa08
1297 1320
1298#define RCCK0_RXAGC1 0xa0c 1321#define RCCK0_RXAGC1 0xa0c
1299#define RCCK0_RXAGC2 0xa10 1322#define RCCK0_RXAGC2 0xa10
1300 1323
1301#define RCCK0_RXHP 0xa14 1324#define RCCK0_RXHP 0xa14
1302 1325
1303#define RCCK0_DSPPARAMETER1 0xa18 1326#define RCCK0_DSPPARAMETER1 0xa18
1304#define RCCK0_DSPPARAMETER2 0xa1c 1327#define RCCK0_DSPPARAMETER2 0xa1c
@@ -1306,26 +1329,26 @@
1306#define RCCK0_TXFILTER1 0xa20 1329#define RCCK0_TXFILTER1 0xa20
1307#define RCCK0_TXFILTER2 0xa24 1330#define RCCK0_TXFILTER2 0xa24
1308#define RCCK0_DEBUGPORT 0xa28 1331#define RCCK0_DEBUGPORT 0xa28
1309#define RCCK0_FALSEALARMREPORT 0xa2c 1332#define RCCK0_FALSEALARMREPORT 0xa2c
1310#define RCCK0_TRSSIREPORT 0xa50 1333#define RCCK0_TRSSIREPORT 0xa50
1311#define RCCK0_RXREPORT 0xa54 1334#define RCCK0_RXREPORT 0xa54
1312#define RCCK0_FACOUNTERLOWER 0xa5c 1335#define RCCK0_FACOUNTERLOWER 0xa5c
1313#define RCCK0_FACOUNTERUPPER 0xa58 1336#define RCCK0_FACOUNTERUPPER 0xa58
1314 1337
1315#define ROFDM0_LSTF 0xc00 1338#define ROFDM0_LSTF 0xc00
1316 1339
1317#define ROFDM0_TRXPATHENABLE 0xc04 1340#define ROFDM0_TRXPATHENABLE 0xc04
1318#define ROFDM0_TRMUXPAR 0xc08 1341#define ROFDM0_TRMUXPAR 0xc08
1319#define ROFDM0_TRSWISOLATION 0xc0c 1342#define ROFDM0_TRSWISOLATION 0xc0c
1320 1343
1321#define ROFDM0_XARXAFE 0xc10 1344#define ROFDM0_XARXAFE 0xc10
1322#define ROFDM0_XARXIQIMBALANCE 0xc14 1345#define ROFDM0_XARXIQIMBALANCE 0xc14
1323#define ROFDM0_XBRXAFE 0xc18 1346#define ROFDM0_XBRXAFE 0xc18
1324#define ROFDM0_XBRXIQIMBALANCE 0xc1c 1347#define ROFDM0_XBRXIQIMBALANCE 0xc1c
1325#define ROFDM0_XCRXAFE 0xc20 1348#define ROFDM0_XCRXAFE 0xc20
1326#define ROFDM0_XCRXIQIMBANLANCE 0xc24 1349#define ROFDM0_XCRXIQIMBANLANCE 0xc24
1327#define ROFDM0_XDRXAFE 0xc28 1350#define ROFDM0_XDRXAFE 0xc28
1328#define ROFDM0_XDRXIQIMBALANCE 0xc2c 1351#define ROFDM0_XDRXIQIMBALANCE 0xc2c
1329 1352
1330#define ROFDM0_RXDETECTOR1 0xc30 1353#define ROFDM0_RXDETECTOR1 0xc30
1331#define ROFDM0_RXDETECTOR2 0xc34 1354#define ROFDM0_RXDETECTOR2 0xc34
@@ -1334,8 +1357,8 @@
1334 1357
1335#define ROFDM0_RXDSP 0xc40 1358#define ROFDM0_RXDSP 0xc40
1336#define ROFDM0_CFOANDDAGC 0xc44 1359#define ROFDM0_CFOANDDAGC 0xc44
1337#define ROFDM0_CCADROPTHRESHOLD 0xc48 1360#define ROFDM0_CCADROPTHRESHOLD 0xc48
1338#define ROFDM0_ECCATHRESHOLD 0xc4c 1361#define ROFDM0_ECCATHRESHOLD 0xc4c
1339 1362
1340#define ROFDM0_XAAGCCORE1 0xc50 1363#define ROFDM0_XAAGCCORE1 0xc50
1341#define ROFDM0_XAAGCCORE2 0xc54 1364#define ROFDM0_XAAGCCORE2 0xc54
@@ -1346,24 +1369,24 @@
1346#define ROFDM0_XDAGCCORE1 0xc68 1369#define ROFDM0_XDAGCCORE1 0xc68
1347#define ROFDM0_XDAGCCORE2 0xc6c 1370#define ROFDM0_XDAGCCORE2 0xc6c
1348 1371
1349#define ROFDM0_AGCPARAMETER1 0xc70 1372#define ROFDM0_AGCPARAMETER1 0xc70
1350#define ROFDM0_AGCPARAMETER2 0xc74 1373#define ROFDM0_AGCPARAMETER2 0xc74
1351#define ROFDM0_AGCRSSITABLE 0xc78 1374#define ROFDM0_AGCRSSITABLE 0xc78
1352#define ROFDM0_HTSTFAGC 0xc7c 1375#define ROFDM0_HTSTFAGC 0xc7c
1353 1376
1354#define ROFDM0_XATXIQIMBALANCE 0xc80 1377#define ROFDM0_XATXIQIMBALANCE 0xc80
1355#define ROFDM0_XATXAFE 0xc84 1378#define ROFDM0_XATXAFE 0xc84
1356#define ROFDM0_XBTXIQIMBALANCE 0xc88 1379#define ROFDM0_XBTXIQIMBALANCE 0xc88
1357#define ROFDM0_XBTXAFE 0xc8c 1380#define ROFDM0_XBTXAFE 0xc8c
1358#define ROFDM0_XCTXIQIMBALANCE 0xc90 1381#define ROFDM0_XCTXIQIMBALANCE 0xc90
1359#define ROFDM0_XCTXAFE 0xc94 1382#define ROFDM0_XCTXAFE 0xc94
1360#define ROFDM0_XDTXIQIMBALANCE 0xc98 1383#define ROFDM0_XDTXIQIMBALANCE 0xc98
1361#define ROFDM0_XDTXAFE 0xc9c 1384#define ROFDM0_XDTXAFE 0xc9c
1362 1385
1363#define ROFDM0_RXIQEXTANTA 0xca0 1386#define ROFDM0_RXIQEXTANTA 0xca0
1364 1387
1365#define ROFDM0_RXHPPARAMETER 0xce0 1388#define ROFDM0_RXHPPARAMETER 0xce0
1366#define ROFDM0_TXPSEUDONOISEWGT 0xce4 1389#define ROFDM0_TXPSEUDONOISEWGT 0xce4
1367#define ROFDM0_FRAMESYNC 0xcf0 1390#define ROFDM0_FRAMESYNC 0xcf0
1368#define ROFDM0_DFSREPORT 0xcf4 1391#define ROFDM0_DFSREPORT 0xcf4
1369#define ROFDM0_TXCOEFF1 0xca4 1392#define ROFDM0_TXCOEFF1 0xca4
@@ -1373,19 +1396,19 @@
1373#define ROFDM0_TXCOEFF5 0xcb4 1396#define ROFDM0_TXCOEFF5 0xcb4
1374#define ROFDM0_TXCOEFF6 0xcb8 1397#define ROFDM0_TXCOEFF6 0xcb8
1375 1398
1376#define ROFDM1_LSTF 0xd00 1399#define ROFDM1_LSTF 0xd00
1377#define ROFDM1_TRXPATHENABLE 0xd04 1400#define ROFDM1_TRXPATHENABLE 0xd04
1378 1401
1379#define ROFDM1_CF0 0xd08 1402#define ROFDM1_CF0 0xd08
1380#define ROFDM1_CSI1 0xd10 1403#define ROFDM1_CSI1 0xd10
1381#define ROFDM1_SBD 0xd14 1404#define ROFDM1_SBD 0xd14
1382#define ROFDM1_CSI2 0xd18 1405#define ROFDM1_CSI2 0xd18
1383#define ROFDM1_CFOTRACKING 0xd2c 1406#define ROFDM1_CFOTRACKING 0xd2c
1384#define ROFDM1_TRXMESAURE1 0xd34 1407#define ROFDM1_TRXMESAURE1 0xd34
1385#define ROFDM1_INTFDET 0xd3c 1408#define ROFDM1_INTFDET 0xd3c
1386#define ROFDM1_PSEUDONOISESTATEAB 0xd50 1409#define ROFDM1_PSEUDONOISESTATEAB 0xd50
1387#define ROFDM1_PSEUDONOISESTATECD 0xd54 1410#define ROFDM1_PSEUDONOISESTATECD 0xd54
1388#define ROFDM1_RXPSEUDONOISEWGT 0xd58 1411#define ROFDM1_RXPSEUDONOISEWGT 0xd58
1389 1412
1390#define ROFDM_PHYCOUNTER1 0xda0 1413#define ROFDM_PHYCOUNTER1 0xda0
1391#define ROFDM_PHYCOUNTER2 0xda4 1414#define ROFDM_PHYCOUNTER2 0xda4
@@ -1397,35 +1420,35 @@
1397#define ROFDM_LONGCFOCD 0xdb8 1420#define ROFDM_LONGCFOCD 0xdb8
1398#define ROFDM_TAILCF0AB 0xdbc 1421#define ROFDM_TAILCF0AB 0xdbc
1399#define ROFDM_TAILCF0CD 0xdc0 1422#define ROFDM_TAILCF0CD 0xdc0
1400#define ROFDM_PWMEASURE1 0xdc4 1423#define ROFDM_PWMEASURE1 0xdc4
1401#define ROFDM_PWMEASURE2 0xdc8 1424#define ROFDM_PWMEASURE2 0xdc8
1402#define ROFDM_BWREPORT 0xdcc 1425#define ROFDM_BWREPORT 0xdcc
1403#define ROFDM_AGCREPORT 0xdd0 1426#define ROFDM_AGCREPORT 0xdd0
1404#define ROFDM_RXSNR 0xdd4 1427#define ROFDM_RXSNR 0xdd4
1405#define ROFDM_RXEVMCSI 0xdd8 1428#define ROFDM_RXEVMCSI 0xdd8
1406#define ROFDM_SIGREPORT 0xddc 1429#define ROFDM_SIGREPORT 0xddc
1407 1430
1408#define RTXAGC_A_RATE18_06 0xe00 1431#define RTXAGC_A_RATE18_06 0xe00
1409#define RTXAGC_A_RATE54_24 0xe04 1432#define RTXAGC_A_RATE54_24 0xe04
1410#define RTXAGC_A_CCK1_MCS32 0xe08 1433#define RTXAGC_A_CCK1_MCS32 0xe08
1411#define RTXAGC_A_MCS03_MCS00 0xe10 1434#define RTXAGC_A_MCS03_MCS00 0xe10
1412#define RTXAGC_A_MCS07_MCS04 0xe14 1435#define RTXAGC_A_MCS07_MCS04 0xe14
1413#define RTXAGC_A_MCS11_MCS08 0xe18 1436#define RTXAGC_A_MCS11_MCS08 0xe18
1414#define RTXAGC_A_MCS15_MCS12 0xe1c 1437#define RTXAGC_A_MCS15_MCS12 0xe1c
1415 1438
1416#define RTXAGC_B_RATE18_06 0x830 1439#define RTXAGC_B_RATE18_06 0x830
1417#define RTXAGC_B_RATE54_24 0x834 1440#define RTXAGC_B_RATE54_24 0x834
1418#define RTXAGC_B_CCK1_55_MCS32 0x838 1441#define RTXAGC_B_CCK1_55_MCS32 0x838
1419#define RTXAGC_B_MCS03_MCS00 0x83c 1442#define RTXAGC_B_MCS03_MCS00 0x83c
1420#define RTXAGC_B_MCS07_MCS04 0x848 1443#define RTXAGC_B_MCS07_MCS04 0x848
1421#define RTXAGC_B_MCS11_MCS08 0x84c 1444#define RTXAGC_B_MCS11_MCS08 0x84c
1422#define RTXAGC_B_MCS15_MCS12 0x868 1445#define RTXAGC_B_MCS15_MCS12 0x868
1423#define RTXAGC_B_CCK11_A_CCK2_11 0x86c 1446#define RTXAGC_B_CCK11_A_CCK2_11 0x86c
1424 1447
1425#define RZEBRA1_HSSIENABLE 0x0 1448#define RZEBRA1_HSSIENABLE 0x0
1426#define RZEBRA1_TRXENABLE1 0x1 1449#define RZEBRA1_TRXENABLE1 0x1
1427#define RZEBRA1_TRXENABLE2 0x2 1450#define RZEBRA1_TRXENABLE2 0x2
1428#define RZEBRA1_AGC 0x4 1451#define RZEBRA1_AGC 0x4
1429#define RZEBRA1_CHARGEPUMP 0x5 1452#define RZEBRA1_CHARGEPUMP 0x5
1430#define RZEBRA1_CHANNEL 0x7 1453#define RZEBRA1_CHANNEL 0x7
1431 1454
@@ -1434,649 +1457,664 @@
1434#define RZEBRA1_RXLPF 0xb 1457#define RZEBRA1_RXLPF 0xb
1435#define RZEBRA1_RXHPFCORNER 0xc 1458#define RZEBRA1_RXHPFCORNER 0xc
1436 1459
1437#define RGLOBALCTRL 0 1460#define RGLOBALCTRL 0
1438#define RRTL8256_TXLPF 19 1461#define RRTL8256_TXLPF 19
1439#define RRTL8256_RXLPF 11 1462#define RRTL8256_RXLPF 11
1440#define RRTL8258_TXLPF 0x11 1463#define RRTL8258_TXLPF 0x11
1441#define RRTL8258_RXLPF 0x13 1464#define RRTL8258_RXLPF 0x13
1442#define RRTL8258_RSSILPF 0xa 1465#define RRTL8258_RSSILPF 0xa
1443 1466
1444#define RF_AC 0x00 1467#define RF_AC 0x00
1445 1468
1446#define RF_IQADJ_G1 0x01 1469#define RF_IQADJ_G1 0x01
1447#define RF_IQADJ_G2 0x02 1470#define RF_IQADJ_G2 0x02
1448#define RF_POW_TRSW 0x05 1471#define RF_POW_TRSW 0x05
1449 1472
1450#define RF_GAIN_RX 0x06 1473#define RF_GAIN_RX 0x06
1451#define RF_GAIN_TX 0x07 1474#define RF_GAIN_TX 0x07
1452 1475
1453#define RF_TXM_IDAC 0x08 1476#define RF_TXM_IDAC 0x08
1454#define RF_BS_IQGEN 0x0F 1477#define RF_BS_IQGEN 0x0F
1455 1478
1456#define RF_MODE1 0x10 1479#define RF_MODE1 0x10
1457#define RF_MODE2 0x11 1480#define RF_MODE2 0x11
1458 1481
1459#define RF_RX_AGC_HP 0x12 1482#define RF_RX_AGC_HP 0x12
1460#define RF_TX_AGC 0x13 1483#define RF_TX_AGC 0x13
1461#define RF_BIAS 0x14 1484#define RF_BIAS 0x14
1462#define RF_IPA 0x15 1485#define RF_IPA 0x15
1463#define RF_POW_ABILITY 0x17 1486#define RF_POW_ABILITY 0x17
1464#define RF_MODE_AG 0x18 1487#define RF_MODE_AG 0x18
1465#define RRFCHANNEL 0x18 1488#define RRFCHANNEL 0x18
1466#define RF_CHNLBW 0x18 1489#define RF_CHNLBW 0x18
1467#define RF_TOP 0x19 1490#define RF_TOP 0x19
1468 1491
1469#define RF_RX_G1 0x1A 1492#define RF_RX_G1 0x1A
1470#define RF_RX_G2 0x1B 1493#define RF_RX_G2 0x1B
1471 1494
1472#define RF_RX_BB2 0x1C 1495#define RF_RX_BB2 0x1C
1473#define RF_RX_BB1 0x1D 1496#define RF_RX_BB1 0x1D
1474 1497
1475#define RF_RCK1 0x1E 1498#define RF_RCK1 0x1E
1476#define RF_RCK2 0x1F 1499#define RF_RCK2 0x1F
1477 1500
1478#define RF_TX_G1 0x20 1501#define RF_TX_G1 0x20
1479#define RF_TX_G2 0x21 1502#define RF_TX_G2 0x21
1480#define RF_TX_G3 0x22 1503#define RF_TX_G3 0x22
1481 1504
1482#define RF_TX_BB1 0x23 1505#define RF_TX_BB1 0x23
1483#define RF_T_METER 0x24 1506#define RF_T_METER 0x24
1484 1507
1485#define RF_SYN_G1 0x25 1508#define RF_SYN_G1 0x25
1486#define RF_SYN_G2 0x26 1509#define RF_SYN_G2 0x26
1487#define RF_SYN_G3 0x27 1510#define RF_SYN_G3 0x27
1488#define RF_SYN_G4 0x28 1511#define RF_SYN_G4 0x28
1489#define RF_SYN_G5 0x29 1512#define RF_SYN_G5 0x29
1490#define RF_SYN_G6 0x2A 1513#define RF_SYN_G6 0x2A
1491#define RF_SYN_G7 0x2B 1514#define RF_SYN_G7 0x2B
1492#define RF_SYN_G8 0x2C 1515#define RF_SYN_G8 0x2C
1493 1516
1494#define RF_RCK_OS 0x30 1517#define RF_RCK_OS 0x30
1495#define RF_TXPA_G1 0x31 1518#define RF_TXPA_G1 0x31
1496#define RF_TXPA_G2 0x32 1519#define RF_TXPA_G2 0x32
1497#define RF_TXPA_G3 0x33 1520#define RF_TXPA_G3 0x33
1498 1521
1499#define BBBRESETB 0x100 1522#define BBBRESETB 0x100
1500#define BGLOBALRESETB 0x200 1523#define BGLOBALRESETB 0x200
1501#define BOFDMTXSTART 0x4 1524#define BOFDMTXSTART 0x4
1502#define BCCKTXSTART 0x8 1525#define BCCKTXSTART 0x8
1503#define BCRC32DEBUG 0x100 1526#define BCRC32DEBUG 0x100
1504#define BPMACLOOPBACK 0x10 1527#define BPMACLOOPBACK 0x10
1505#define BTXLSIG 0xffffff 1528#define BTXLSIG 0xffffff
1506#define BOFDMTXRATE 0xf 1529#define BOFDMTXRATE 0xf
1507#define BOFDMTXRESERVED 0x10 1530#define BOFDMTXRESERVED 0x10
1508#define BOFDMTXLENGTH 0x1ffe0 1531#define BOFDMTXLENGTH 0x1ffe0
1509#define BOFDMTXPARITY 0x20000 1532#define BOFDMTXPARITY 0x20000
1510#define BTXHTSIG1 0xffffff 1533#define BTXHTSIG1 0xffffff
1511#define BTXHTMCSRATE 0x7f 1534#define BTXHTMCSRATE 0x7f
1512#define BTXHTBW 0x80 1535#define BTXHTBW 0x80
1513#define BTXHTLENGTH 0xffff00 1536#define BTXHTLENGTH 0xffff00
1514#define BTXHTSIG2 0xffffff 1537#define BTXHTSIG2 0xffffff
1515#define BTXHTSMOOTHING 0x1 1538#define BTXHTSMOOTHING 0x1
1516#define BTXHTSOUNDING 0x2 1539#define BTXHTSOUNDING 0x2
1517#define BTXHTRESERVED 0x4 1540#define BTXHTRESERVED 0x4
1518#define BTXHTAGGREATION 0x8 1541#define BTXHTAGGREATION 0x8
1519#define BTXHTSTBC 0x30 1542#define BTXHTSTBC 0x30
1520#define BTXHTADVANCECODING 0x40 1543#define BTXHTADVANCECODING 0x40
1521#define BTXHTSHORTGI 0x80 1544#define BTXHTSHORTGI 0x80
1522#define BTXHTNUMBERHT_LTF 0x300 1545#define BTXHTNUMBERHT_LTF 0x300
1523#define BTXHTCRC8 0x3fc00 1546#define BTXHTCRC8 0x3fc00
1524#define BCOUNTERRESET 0x10000 1547#define BCOUNTERRESET 0x10000
1525#define BNUMOFOFDMTX 0xffff 1548#define BNUMOFOFDMTX 0xffff
1526#define BNUMOFCCKTX 0xffff0000 1549#define BNUMOFCCKTX 0xffff0000
1527#define BTXIDLEINTERVAL 0xffff 1550#define BTXIDLEINTERVAL 0xffff
1528#define BOFDMSERVICE 0xffff0000 1551#define BOFDMSERVICE 0xffff0000
1529#define BTXMACHEADER 0xffffffff 1552#define BTXMACHEADER 0xffffffff
1530#define BTXDATAINIT 0xff 1553#define BTXDATAINIT 0xff
1531#define BTXHTMODE 0x100 1554#define BTXHTMODE 0x100
1532#define BTXDATATYPE 0x30000 1555#define BTXDATATYPE 0x30000
1533#define BTXRANDOMSEED 0xffffffff 1556#define BTXRANDOMSEED 0xffffffff
1534#define BCCKTXPREAMBLE 0x1 1557#define BCCKTXPREAMBLE 0x1
1535#define BCCKTXSFD 0xffff0000 1558#define BCCKTXSFD 0xffff0000
1536#define BCCKTXSIG 0xff 1559#define BCCKTXSIG 0xff
1537#define BCCKTXSERVICE 0xff00 1560#define BCCKTXSERVICE 0xff00
1538#define BCCKLENGTHEXT 0x8000 1561#define BCCKLENGTHEXT 0x8000
1539#define BCCKTXLENGHT 0xffff0000 1562#define BCCKTXLENGHT 0xffff0000
1540#define BCCKTXCRC16 0xffff 1563#define BCCKTXCRC16 0xffff
1541#define BCCKTXSTATUS 0x1 1564#define BCCKTXSTATUS 0x1
1542#define BOFDMTXSTATUS 0x2 1565#define BOFDMTXSTATUS 0x2
1543#define IS_BB_REG_OFFSET_92S(_Offset) \ 1566#define IS_BB_REG_OFFSET_92S(_offset) \
1544 ((_Offset >= 0x800) && (_Offset <= 0xfff)) 1567 ((_offset >= 0x800) && (_offset <= 0xfff))
1545 1568
1546#define BRFMOD 0x1 1569#define BRFMOD 0x1
1547#define BJAPANMODE 0x2 1570#define BJAPANMODE 0x2
1548#define BCCKTXSC 0x30 1571#define BCCKTXSC 0x30
1549#define BCCKEN 0x1000000 1572#define BCCKEN 0x1000000
1550#define BOFDMEN 0x2000000 1573#define BOFDMEN 0x2000000
1551 1574
1552#define BOFDMRXADCPHASE 0x10000 1575#define BOFDMRXADCPHASE 0x10000
1553#define BOFDMTXDACPHASE 0x40000 1576#define BOFDMTXDACPHASE 0x40000
1554#define BXATXAGC 0x3f 1577#define BXATXAGC 0x3f
1555 1578
1556#define BXBTXAGC 0xf00 1579#define BXBTXAGC 0xf00
1557#define BXCTXAGC 0xf000 1580#define BXCTXAGC 0xf000
1558#define BXDTXAGC 0xf0000 1581#define BXDTXAGC 0xf0000
1559 1582
1560#define BPASTART 0xf0000000 1583#define BPASTART 0xf0000000
1561#define BTRSTART 0x00f00000 1584#define BTRSTART 0x00f00000
1562#define BRFSTART 0x0000f000 1585#define BRFSTART 0x0000f000
1563#define BBBSTART 0x000000f0 1586#define BBBSTART 0x000000f0
1564#define BBBCCKSTART 0x0000000f 1587#define BBBCCKSTART 0x0000000f
1565#define BPAEND 0xf 1588#define BPAEND 0xf
1566#define BTREND 0x0f000000 1589#define BTREND 0x0f000000
1567#define BRFEND 0x000f0000 1590#define BRFEND 0x000f0000
1568#define BCCAMASK 0x000000f0 1591#define BCCAMASK 0x000000f0
1569#define BR2RCCAMASK 0x00000f00 1592#define BR2RCCAMASK 0x00000f00
1570#define BHSSI_R2TDELAY 0xf8000000 1593#define BHSSI_R2TDELAY 0xf8000000
1571#define BHSSI_T2RDELAY 0xf80000 1594#define BHSSI_T2RDELAY 0xf80000
1572#define BCONTXHSSI 0x400 1595#define BCONTXHSSI 0x400
1573#define BIGFROMCCK 0x200 1596#define BIGFROMCCK 0x200
1574#define BAGCADDRESS 0x3f 1597#define BAGCADDRESS 0x3f
1575#define BRXHPTX 0x7000 1598#define BRXHPTX 0x7000
1576#define BRXHP2RX 0x38000 1599#define BRXHP2RX 0x38000
1577#define BRXHPCCKINI 0xc0000 1600#define BRXHPCCKINI 0xc0000
1578#define BAGCTXCODE 0xc00000 1601#define BAGCTXCODE 0xc00000
1579#define BAGCRXCODE 0x300000 1602#define BAGCRXCODE 0x300000
1580 1603
1581#define B3WIREDATALENGTH 0x800 1604#define B3WIREDATALENGTH 0x800
1582#define B3WIREADDREAALENGTH 0x400 1605#define B3WIREADDREAALENGTH 0x400
1583 1606
1584#define B3WIRERFPOWERDOWN 0x1 1607#define B3WIRERFPOWERDOWN 0x1
1585#define B5GPAPEPOLARITY 0x40000000 1608#define B5GPAPEPOLARITY 0x40000000
1586#define B2GPAPEPOLARITY 0x80000000 1609#define B2GPAPEPOLARITY 0x80000000
1587#define BRFSW_TXDEFAULTANT 0x3 1610#define BRFSW_TXDEFAULTANT 0x3
1588#define BRFSW_TXOPTIONANT 0x30 1611#define BRFSW_TXOPTIONANT 0x30
1589#define BRFSW_RXDEFAULTANT 0x300 1612#define BRFSW_RXDEFAULTANT 0x300
1590#define BRFSW_RXOPTIONANT 0x3000 1613#define BRFSW_RXOPTIONANT 0x3000
1591#define BRFSI_3WIREDATA 0x1 1614#define BRFSI_3WIREDATA 0x1
1592#define BRFSI_3WIRECLOCK 0x2 1615#define BRFSI_3WIRECLOCK 0x2
1593#define BRFSI_3WIRELOAD 0x4 1616#define BRFSI_3WIRELOAD 0x4
1594#define BRFSI_3WIRERW 0x8 1617#define BRFSI_3WIRERW 0x8
1595#define BRFSI_3WIRE 0xf 1618#define BRFSI_3WIRE 0xf
1596 1619
1597#define BRFSI_RFENV 0x10 1620#define BRFSI_RFENV 0x10
1598 1621
1599#define BRFSI_TRSW 0x20 1622#define BRFSI_TRSW 0x20
1600#define BRFSI_TRSWB 0x40 1623#define BRFSI_TRSWB 0x40
1601#define BRFSI_ANTSW 0x100 1624#define BRFSI_ANTSW 0x100
1602#define BRFSI_ANTSWB 0x200 1625#define BRFSI_ANTSWB 0x200
1603#define BRFSI_PAPE 0x400 1626#define BRFSI_PAPE 0x400
1604#define BRFSI_PAPE5G 0x800 1627#define BRFSI_PAPE5G 0x800
1605#define BBANDSELECT 0x1 1628#define BBANDSELECT 0x1
1606#define BHTSIG2_GI 0x80 1629#define BHTSIG2_GI 0x80
1607#define BHTSIG2_SMOOTHING 0x01 1630#define BHTSIG2_SMOOTHING 0x01
1608#define BHTSIG2_SOUNDING 0x02 1631#define BHTSIG2_SOUNDING 0x02
1609#define BHTSIG2_AGGREATON 0x08 1632#define BHTSIG2_AGGREATON 0x08
1610#define BHTSIG2_STBC 0x30 1633#define BHTSIG2_STBC 0x30
1611#define BHTSIG2_ADVCODING 0x40 1634#define BHTSIG2_ADVCODING 0x40
1612#define BHTSIG2_NUMOFHTLTF 0x300 1635#define BHTSIG2_NUMOFHTLTF 0x300
1613#define BHTSIG2_CRC8 0x3fc 1636#define BHTSIG2_CRC8 0x3fc
1614#define BHTSIG1_MCS 0x7f 1637#define BHTSIG1_MCS 0x7f
1615#define BHTSIG1_BANDWIDTH 0x80 1638#define BHTSIG1_BANDWIDTH 0x80
1616#define BHTSIG1_HTLENGTH 0xffff 1639#define BHTSIG1_HTLENGTH 0xffff
1617#define BLSIG_RATE 0xf 1640#define BLSIG_RATE 0xf
1618#define BLSIG_RESERVED 0x10 1641#define BLSIG_RESERVED 0x10
1619#define BLSIG_LENGTH 0x1fffe 1642#define BLSIG_LENGTH 0x1fffe
1620#define BLSIG_PARITY 0x20 1643#define BLSIG_PARITY 0x20
1621#define BCCKRXPHASE 0x4 1644#define BCCKRXPHASE 0x4
1622 1645
1623#define BLSSIREADADDRESS 0x7f800000 1646#define BLSSIREADADDRESS 0x7f800000
1624#define BLSSIREADEDGE 0x80000000 1647#define BLSSIREADEDGE 0x80000000
1625 1648
1626#define BLSSIREADBACKDATA 0xfffff 1649#define BLSSIREADBACKDATA 0xfffff
1627 1650
1628#define BLSSIREADOKFLAG 0x1000 1651#define BLSSIREADOKFLAG 0x1000
1629#define BCCKSAMPLERATE 0x8 1652#define BCCKSAMPLERATE 0x8
1630#define BREGULATOR0STANDBY 0x1 1653#define BREGULATOR0STANDBY 0x1
1631#define BREGULATORPLLSTANDBY 0x2 1654#define BREGULATORPLLSTANDBY 0x2
1632#define BREGULATOR1STANDBY 0x4 1655#define BREGULATOR1STANDBY 0x4
1633#define BPLLPOWERUP 0x8 1656#define BPLLPOWERUP 0x8
1634#define BDPLLPOWERUP 0x10 1657#define BDPLLPOWERUP 0x10
1635#define BDA10POWERUP 0x20 1658#define BDA10POWERUP 0x20
1636#define BAD7POWERUP 0x200 1659#define BAD7POWERUP 0x200
1637#define BDA6POWERUP 0x2000 1660#define BDA6POWERUP 0x2000
1638#define BXTALPOWERUP 0x4000 1661#define BXTALPOWERUP 0x4000
1639#define B40MDCLKPOWERUP 0x8000 1662#define B40MDCLKPOWERUP 0x8000
1640#define BDA6DEBUGMODE 0x20000 1663#define BDA6DEBUGMODE 0x20000
1641#define BDA6SWING 0x380000 1664#define BDA6SWING 0x380000
1642 1665
1643#define BADCLKPHASE 0x4000000 1666#define BADCLKPHASE 0x4000000
1644#define B80MCLKDELAY 0x18000000 1667#define B80MCLKDELAY 0x18000000
1645#define BAFEWATCHDOGENABLE 0x20000000 1668#define BAFEWATCHDOGENABLE 0x20000000
1646 1669
1647#define BXTALCAP01 0xc0000000 1670#define BXTALCAP01 0xc0000000
1648#define BXTALCAP23 0x3 1671#define BXTALCAP23 0x3
1649#define BXTALCAP92X 0x0f000000 1672#define BXTALCAP92X 0x0f000000
1650#define BXTALCAP 0x0f000000 1673#define BXTALCAP 0x0f000000
1651 1674
1652#define BINTDIFCLKENABLE 0x400 1675#define BINTDIFCLKENABLE 0x400
1653#define BEXTSIGCLKENABLE 0x800 1676#define BEXTSIGCLKENABLE 0x800
1654#define BBANDGAP_MBIAS_POWERUP 0x10000 1677#define BBANDGAP_MBIAS_POWERUP 0x10000
1655#define BAD11SH_GAIN 0xc0000 1678#define BAD11SH_GAIN 0xc0000
1656#define BAD11NPUT_RANGE 0x700000 1679#define BAD11NPUT_RANGE 0x700000
1657#define BAD110P_CURRENT 0x3800000 1680#define BAD110P_CURRENT 0x3800000
1658#define BLPATH_LOOPBACK 0x4000000 1681#define BLPATH_LOOPBACK 0x4000000
1659#define BQPATH_LOOPBACK 0x8000000 1682#define BQPATH_LOOPBACK 0x8000000
1660#define BAFE_LOOPBACK 0x10000000 1683#define BAFE_LOOPBACK 0x10000000
1661#define BDA10_SWING 0x7e0 1684#define BDA10_SWING 0x7e0
1662#define BDA10_REVERSE 0x800 1685#define BDA10_REVERSE 0x800
1663#define BDA_CLK_SOURCE 0x1000 1686#define BDA_CLK_SOURCE 0x1000
1664#define BDA7INPUT_RANGE 0x6000 1687#define BDA7INPUT_RANGE 0x6000
1665#define BDA7_GAIN 0x38000 1688#define BDA7_GAIN 0x38000
1666#define BDA7OUTPUT_CM_MODE 0x40000 1689#define BDA7OUTPUT_CM_MODE 0x40000
1667#define BDA7INPUT_CM_MODE 0x380000 1690#define BDA7INPUT_CM_MODE 0x380000
1668#define BDA7CURRENT 0xc00000 1691#define BDA7CURRENT 0xc00000
1669#define BREGULATOR_ADJUST 0x7000000 1692#define BREGULATOR_ADJUST 0x7000000
1670#define BAD11POWERUP_ATTX 0x1 1693#define BAD11POWERUP_ATTX 0x1
1671#define BDA10PS_ATTX 0x10 1694#define BDA10PS_ATTX 0x10
1672#define BAD11POWERUP_ATRX 0x100 1695#define BAD11POWERUP_ATRX 0x100
1673#define BDA10PS_ATRX 0x1000 1696#define BDA10PS_ATRX 0x1000
1674#define BCCKRX_AGC_FORMAT 0x200 1697#define BCCKRX_AGC_FORMAT 0x200
1675#define BPSDFFT_SAMPLE_POINT 0xc000 1698#define BPSDFFT_SAMPLE_POINT 0xc000
1676#define BPSD_AVERAGE_NUM 0x3000 1699#define BPSD_AVERAGE_NUM 0x3000
1677#define BIQPATH_CONTROL 0xc00 1700#define BIQPATH_CONTROL 0xc00
1678#define BPSD_FREQ 0x3ff 1701#define BPSD_FREQ 0x3ff
1679#define BPSD_ANTENNA_PATH 0x30 1702#define BPSD_ANTENNA_PATH 0x30
1680#define BPSD_IQ_SWITCH 0x40 1703#define BPSD_IQ_SWITCH 0x40
1681#define BPSD_RX_TRIGGER 0x400000 1704#define BPSD_RX_TRIGGER 0x400000
1682#define BPSD_TX_TRIGGER 0x80000000 1705#define BPSD_TX_TRIGGER 0x80000000
1683#define BPSD_SINE_TONE_SCALE 0x7f000000 1706#define BPSD_SINE_TONE_SCALE 0x7f000000
1684#define BPSD_REPORT 0xffff 1707#define BPSD_REPORT 0xffff
1685 1708
1686#define BOFDM_TXSC 0x30000000 1709#define BOFDM_TXSC 0x30000000
1687#define BCCK_TXON 0x1 1710#define BCCK_TXON 0x1
1688#define BOFDM_TXON 0x2 1711#define BOFDM_TXON 0x2
1689#define BDEBUG_PAGE 0xfff 1712#define BDEBUG_PAGE 0xfff
1690#define BDEBUG_ITEM 0xff 1713#define BDEBUG_ITEM 0xff
1691#define BANTL 0x10 1714#define BANTL 0x10
1692#define BANT_NONHT 0x100 1715#define BANT_NONHT 0x100
1693#define BANT_HT1 0x1000 1716#define BANT_HT1 0x1000
1694#define BANT_HT2 0x10000 1717#define BANT_HT2 0x10000
1695#define BANT_HT1S1 0x100000 1718#define BANT_HT1S1 0x100000
1696#define BANT_NONHTS1 0x1000000 1719#define BANT_NONHTS1 0x1000000
1697 1720
1698#define BCCK_BBMODE 0x3 1721#define BCCK_BBMODE 0x3
1699#define BCCK_TXPOWERSAVING 0x80 1722#define BCCK_TXPOWERSAVING 0x80
1700#define BCCK_RXPOWERSAVING 0x40 1723#define BCCK_RXPOWERSAVING 0x40
1701 1724
1702#define BCCK_SIDEBAND 0x10 1725#define BCCK_SIDEBAND 0x10
1703 1726
1704#define BCCK_SCRAMBLE 0x8 1727#define BCCK_SCRAMBLE 0x8
1705#define BCCK_ANTDIVERSITY 0x8000 1728#define BCCK_ANTDIVERSITY 0x8000
1706#define BCCK_CARRIER_RECOVERY 0x4000 1729#define BCCK_CARRIER_RECOVERY 0x4000
1707#define BCCK_TXRATE 0x3000 1730#define BCCK_TXRATE 0x3000
1708#define BCCK_DCCANCEL 0x0800 1731#define BCCK_DCCANCEL 0x0800
1709#define BCCK_ISICANCEL 0x0400 1732#define BCCK_ISICANCEL 0x0400
1710#define BCCK_MATCH_FILTER 0x0200 1733#define BCCK_MATCH_FILTER 0x0200
1711#define BCCK_EQUALIZER 0x0100 1734#define BCCK_EQUALIZER 0x0100
1712#define BCCK_PREAMBLE_DETECT 0x800000 1735#define BCCK_PREAMBLE_DETECT 0x800000
1713#define BCCK_FAST_FALSECCAi 0x400000 1736#define BCCK_FAST_FALSECCA 0x400000
1714#define BCCK_CH_ESTSTARTi 0x300000 1737#define BCCK_CH_ESTSTART 0x300000
1715#define BCCK_CCA_COUNTi 0x080000 1738#define BCCK_CCA_COUNT 0x080000
1716#define BCCK_CS_LIM 0x070000 1739#define BCCK_CS_LIM 0x070000
1717#define BCCK_BIST_MODEi 0x80000000 1740#define BCCK_BIST_MODE 0x80000000
1718#define BCCK_CCAMASK 0x40000000 1741#define BCCK_CCAMASK 0x40000000
1719#define BCCK_TX_DAC_PHASE 0x4 1742#define BCCK_TX_DAC_PHASE 0x4
1720#define BCCK_RX_ADC_PHASE 0x20000000 1743#define BCCK_RX_ADC_PHASE 0x20000000
1721#define BCCKR_CP_MODE 0x0100 1744#define BCCKR_CP_MODE 0x0100
1722#define BCCK_TXDC_OFFSET 0xf0 1745#define BCCK_TXDC_OFFSET 0xf0
1723#define BCCK_RXDC_OFFSET 0xf 1746#define BCCK_RXDC_OFFSET 0xf
1724#define BCCK_CCA_MODE 0xc000 1747#define BCCK_CCA_MODE 0xc000
1725#define BCCK_FALSECS_LIM 0x3f00 1748#define BCCK_FALSECS_LIM 0x3f00
1726#define BCCK_CS_RATIO 0xc00000 1749#define BCCK_CS_RATIO 0xc00000
1727#define BCCK_CORGBIT_SEL 0x300000 1750#define BCCK_CORGBIT_SEL 0x300000
1728#define BCCK_PD_LIM 0x0f0000 1751#define BCCK_PD_LIM 0x0f0000
1729#define BCCK_NEWCCA 0x80000000 1752#define BCCK_NEWCCA 0x80000000
1730#define BCCK_RXHP_OF_IG 0x8000 1753#define BCCK_RXHP_OF_IG 0x8000
1731#define BCCK_RXIG 0x7f00 1754#define BCCK_RXIG 0x7f00
1732#define BCCK_LNA_POLARITY 0x800000 1755#define BCCK_LNA_POLARITY 0x800000
1733#define BCCK_RX1ST_BAIN 0x7f0000 1756#define BCCK_RX1ST_BAIN 0x7f0000
1734#define BCCK_RF_EXTEND 0x20000000 1757#define BCCK_RF_EXTEND 0x20000000
1735#define BCCK_RXAGC_SATLEVEL 0x1f000000 1758#define BCCK_RXAGC_SATLEVEL 0x1f000000
1736#define BCCK_RXAGC_SATCOUNT 0xe0 1759#define BCCK_RXAGC_SATCOUNT 0xe0
1737#define bCCKRxRFSettle 0x1f 1760#define BCCKRXRFSETTLE 0x1f
1738#define BCCK_FIXED_RXAGC 0x8000 1761#define BCCK_FIXED_RXAGC 0x8000
1739#define BCCK_ANTENNA_POLARITY 0x2000 1762#define BCCK_ANTENNA_POLARITY 0x2000
1740#define BCCK_TXFILTER_TYPE 0x0c00 1763#define BCCK_TXFILTER_TYPE 0x0c00
1741#define BCCK_RXAGC_REPORTTYPE 0x0300 1764#define BCCK_RXAGC_REPORTTYPE 0x0300
1742#define BCCK_RXDAGC_EN 0x80000000 1765#define BCCK_RXDAGC_EN 0x80000000
1743#define BCCK_RXDAGC_PERIOD 0x20000000 1766#define BCCK_RXDAGC_PERIOD 0x20000000
1744#define BCCK_RXDAGC_SATLEVEL 0x1f000000 1767#define BCCK_RXDAGC_SATLEVEL 0x1f000000
1745#define BCCK_TIMING_RECOVERY 0x800000 1768#define BCCK_TIMING_RECOVERY 0x800000
1746#define BCCK_TXC0 0x3f0000 1769#define BCCK_TXC0 0x3f0000
1747#define BCCK_TXC1 0x3f000000 1770#define BCCK_TXC1 0x3f000000
1748#define BCCK_TXC2 0x3f 1771#define BCCK_TXC2 0x3f
1749#define BCCK_TXC3 0x3f00 1772#define BCCK_TXC3 0x3f00
1750#define BCCK_TXC4 0x3f0000 1773#define BCCK_TXC4 0x3f0000
1751#define BCCK_TXC5 0x3f000000 1774#define BCCK_TXC5 0x3f000000
1752#define BCCK_TXC6 0x3f 1775#define BCCK_TXC6 0x3f
1753#define BCCK_TXC7 0x3f00 1776#define BCCK_TXC7 0x3f00
1754#define BCCK_DEBUGPORT 0xff0000 1777#define BCCK_DEBUGPORT 0xff0000
1755#define BCCK_DAC_DEBUG 0x0f000000 1778#define BCCK_DAC_DEBUG 0x0f000000
1756#define BCCK_FALSEALARM_ENABLE 0x8000 1779#define BCCK_FALSEALARM_ENABLE 0x8000
1757#define BCCK_FALSEALARM_READ 0x4000 1780#define BCCK_FALSEALARM_READ 0x4000
1758#define BCCK_TRSSI 0x7f 1781#define BCCK_TRSSI 0x7f
1759#define BCCK_RXAGC_REPORT 0xfe 1782#define BCCK_RXAGC_REPORT 0xfe
1760#define BCCK_RXREPORT_ANTSEL 0x80000000 1783#define BCCK_RXREPORT_ANTSEL 0x80000000
1761#define BCCK_RXREPORT_MFOFF 0x40000000 1784#define BCCK_RXREPORT_MFOFF 0x40000000
1762#define BCCK_RXREPORT_SQLOSS 0x20000000 1785#define BCCK_RXREPORT_SQLOSS 0x20000000
1763#define BCCK_RXREPORT_PKTLOSS 0x10000000 1786#define BCCK_RXREPORT_PKTLOSS 0x10000000
1764#define BCCK_RXREPORT_LOCKEDBIT 0x08000000 1787#define BCCK_RXREPORT_LOCKEDBIT 0x08000000
1765#define BCCK_RXREPORT_RATEERROR 0x04000000 1788#define BCCK_RXREPORT_RATEERROR 0x04000000
1766#define BCCK_RXREPORT_RXRATE 0x03000000 1789#define BCCK_RXREPORT_RXRATE 0x03000000
1767#define BCCK_RXFA_COUNTER_LOWER 0xff 1790#define BCCK_RXFA_COUNTER_LOWER 0xff
1768#define BCCK_RXFA_COUNTER_UPPER 0xff000000 1791#define BCCK_RXFA_COUNTER_UPPER 0xff000000
1769#define BCCK_RXHPAGC_START 0xe000 1792#define BCCK_RXHPAGC_START 0xe000
1770#define BCCK_RXHPAGC_FINAL 0x1c00 1793#define BCCK_RXHPAGC_FINAL 0x1c00
1771#define BCCK_RXFALSEALARM_ENABLE 0x8000 1794#define BCCK_RXFALSEALARM_ENABLE 0x8000
1772#define BCCK_FACOUNTER_FREEZE 0x4000 1795#define BCCK_FACOUNTER_FREEZE 0x4000
1773#define BCCK_TXPATH_SEL 0x10000000 1796#define BCCK_TXPATH_SEL 0x10000000
1774#define BCCK_DEFAULT_RXPATH 0xc000000 1797#define BCCK_DEFAULT_RXPATH 0xc000000
1775#define BCCK_OPTION_RXPATH 0x3000000 1798#define BCCK_OPTION_RXPATH 0x3000000
1776 1799
1777#define BNUM_OFSTF 0x3 1800#define BNUM_OFSTF 0x3
1778#define BSHIFT_L 0xc0 1801#define BSHIFT_L 0xc0
1779#define BGI_TH 0xc 1802#define BGI_TH 0xc
1780#define BRXPATH_A 0x1 1803#define BRXPATH_A 0x1
1781#define BRXPATH_B 0x2 1804#define BRXPATH_B 0x2
1782#define BRXPATH_C 0x4 1805#define BRXPATH_C 0x4
1783#define BRXPATH_D 0x8 1806#define BRXPATH_D 0x8
1784#define BTXPATH_A 0x1 1807#define BTXPATH_A 0x1
1785#define BTXPATH_B 0x2 1808#define BTXPATH_B 0x2
1786#define BTXPATH_C 0x4 1809#define BTXPATH_C 0x4
1787#define BTXPATH_D 0x8 1810#define BTXPATH_D 0x8
1788#define BTRSSI_FREQ 0x200 1811#define BTRSSI_FREQ 0x200
1789#define BADC_BACKOFF 0x3000 1812#define BADC_BACKOFF 0x3000
1790#define BDFIR_BACKOFF 0xc000 1813#define BDFIR_BACKOFF 0xc000
1791#define BTRSSI_LATCH_PHASE 0x10000 1814#define BTRSSI_LATCH_PHASE 0x10000
1792#define BRX_LDC_OFFSET 0xff 1815#define BRX_LDC_OFFSET 0xff
1793#define BRX_QDC_OFFSET 0xff00 1816#define BRX_QDC_OFFSET 0xff00
1794#define BRX_DFIR_MODE 0x1800000 1817#define BRX_DFIR_MODE 0x1800000
1795#define BRX_DCNF_TYPE 0xe000000 1818#define BRX_DCNF_TYPE 0xe000000
1796#define BRXIQIMB_A 0x3ff 1819#define BRXIQIMB_A 0x3ff
1797#define BRXIQIMB_B 0xfc00 1820#define BRXIQIMB_B 0xfc00
1798#define BRXIQIMB_C 0x3f0000 1821#define BRXIQIMB_C 0x3f0000
1799#define BRXIQIMB_D 0xffc00000 1822#define BRXIQIMB_D 0xffc00000
1800#define BDC_DC_NOTCH 0x60000 1823#define BDC_DC_NOTCH 0x60000
1801#define BRXNB_NOTCH 0x1f000000 1824#define BRXNB_NOTCH 0x1f000000
1802#define BPD_TH 0xf 1825#define BPD_TH 0xf
1803#define BPD_TH_OPT2 0xc000 1826#define BPD_TH_OPT2 0xc000
1804#define BPWED_TH 0x700 1827#define BPWED_TH 0x700
1805#define BIFMF_WIN_L 0x800 1828#define BIFMF_WIN_L 0x800
1806#define BPD_OPTION 0x1000 1829#define BPD_OPTION 0x1000
1807#define BMF_WIN_L 0xe000 1830#define BMF_WIN_L 0xe000
1808#define BBW_SEARCH_L 0x30000 1831#define BBW_SEARCH_L 0x30000
1809#define BWIN_ENH_L 0xc0000 1832#define BWIN_ENH_L 0xc0000
1810#define BBW_TH 0x700000 1833#define BBW_TH 0x700000
1811#define BED_TH2 0x3800000 1834#define BED_TH2 0x3800000
1812#define BBW_OPTION 0x4000000 1835#define BBW_OPTION 0x4000000
1813#define BRADIO_TH 0x18000000 1836#define BRADIO_TH 0x18000000
1814#define BWINDOW_L 0xe0000000 1837#define BWINDOW_L 0xe0000000
1815#define BSBD_OPTION 0x1 1838#define BSBD_OPTION 0x1
1816#define BFRAME_TH 0x1c 1839#define BFRAME_TH 0x1c
1817#define BFS_OPTION 0x60 1840#define BFS_OPTION 0x60
1818#define BDC_SLOPE_CHECK 0x80 1841#define BDC_SLOPE_CHECK 0x80
1819#define BFGUARD_COUNTER_DC_L 0xe00 1842#define BFGUARD_COUNTER_DC_L 0xe00
1820#define BFRAME_WEIGHT_SHORT 0x7000 1843#define BFRAME_WEIGHT_SHORT 0x7000
1821#define BSUB_TUNE 0xe00000 1844#define BSUB_TUNE 0xe00000
1822#define BFRAME_DC_LENGTH 0xe000000 1845#define BFRAME_DC_LENGTH 0xe000000
1823#define BSBD_START_OFFSET 0x30000000 1846#define BSBD_START_OFFSET 0x30000000
1824#define BFRAME_TH_2 0x7 1847#define BFRAME_TH_2 0x7
1825#define BFRAME_GI2_TH 0x38 1848#define BFRAME_GI2_TH 0x38
1826#define BGI2_SYNC_EN 0x40 1849#define BGI2_SYNC_EN 0x40
1827#define BSARCH_SHORT_EARLY 0x300 1850#define BSARCH_SHORT_EARLY 0x300
1828#define BSARCH_SHORT_LATE 0xc00 1851#define BSARCH_SHORT_LATE 0xc00
1829#define BSARCH_GI2_LATE 0x70000 1852#define BSARCH_GI2_LATE 0x70000
1830#define BCFOANTSUM 0x1 1853#define BCFOANTSUM 0x1
1831#define BCFOACC 0x2 1854#define BCFOACC 0x2
1832#define BCFOSTARTOFFSET 0xc 1855#define BCFOSTARTOFFSET 0xc
1833#define BCFOLOOPBACK 0x70 1856#define BCFOLOOPBACK 0x70
1834#define BCFOSUMWEIGHT 0x80 1857#define BCFOSUMWEIGHT 0x80
1835#define BDAGCENABLE 0x10000 1858#define BDAGCENABLE 0x10000
1836#define BTXIQIMB_A 0x3ff 1859#define BTXIQIMB_A 0x3ff
1837#define BTXIQIMB_b 0xfc00 1860#define BTXIQIMB_b 0xfc00
1838#define BTXIQIMB_C 0x3f0000 1861#define BTXIQIMB_C 0x3f0000
1839#define BTXIQIMB_D 0xffc00000 1862#define BTXIQIMB_D 0xffc00000
1840#define BTXIDCOFFSET 0xff 1863#define BTXIDCOFFSET 0xff
1841#define BTXIQDCOFFSET 0xff00 1864#define BTXIQDCOFFSET 0xff00
1842#define BTXDFIRMODE 0x10000 1865#define BTXDFIRMODE 0x10000
1843#define BTXPESUDO_NOISEON 0x4000000 1866#define BTXPESUDO_NOISEON 0x4000000
1844#define BTXPESUDO_NOISE_A 0xff 1867#define BTXPESUDO_NOISE_A 0xff
1845#define BTXPESUDO_NOISE_B 0xff00 1868#define BTXPESUDO_NOISE_B 0xff00
1846#define BTXPESUDO_NOISE_C 0xff0000 1869#define BTXPESUDO_NOISE_C 0xff0000
1847#define BTXPESUDO_NOISE_D 0xff000000 1870#define BTXPESUDO_NOISE_D 0xff000000
1848#define BCCA_DROPOPTION 0x20000 1871#define BCCA_DROPOPTION 0x20000
1849#define BCCA_DROPTHRES 0xfff00000 1872#define BCCA_DROPTHRES 0xfff00000
1850#define BEDCCA_H 0xf 1873#define BEDCCA_H 0xf
1851#define BEDCCA_L 0xf0 1874#define BEDCCA_L 0xf0
1852#define BLAMBDA_ED 0x300 1875#define BLAMBDA_ED 0x300
1853#define BRX_INITIALGAIN 0x7f 1876#define BRX_INITIALGAIN 0x7f
1854#define BRX_ANTDIV_EN 0x80 1877#define BRX_ANTDIV_EN 0x80
1855#define BRX_AGC_ADDRESS_FOR_LNA 0x7f00 1878#define BRX_AGC_ADDRESS_FOR_LNA 0x7f00
1856#define BRX_HIGHPOWER_FLOW 0x8000 1879#define BRX_HIGHPOWER_FLOW 0x8000
1857#define BRX_AGC_FREEZE_THRES 0xc0000 1880#define BRX_AGC_FREEZE_THRES 0xc0000
1858#define BRX_FREEZESTEP_AGC1 0x300000 1881#define BRX_FREEZESTEP_AGC1 0x300000
1859#define BRX_FREEZESTEP_AGC2 0xc00000 1882#define BRX_FREEZESTEP_AGC2 0xc00000
1860#define BRX_FREEZESTEP_AGC3 0x3000000 1883#define BRX_FREEZESTEP_AGC3 0x3000000
1861#define BRX_FREEZESTEP_AGC0 0xc000000 1884#define BRX_FREEZESTEP_AGC0 0xc000000
1862#define BRXRSSI_CMP_EN 0x10000000 1885#define BRXRSSI_CMP_EN 0x10000000
1863#define BRXQUICK_AGCEN 0x20000000 1886#define BRXQUICK_AGCEN 0x20000000
1864#define BRXAGC_FREEZE_THRES_MODE 0x40000000 1887#define BRXAGC_FREEZE_THRES_MODE 0x40000000
1865#define BRX_OVERFLOW_CHECKTYPE 0x80000000 1888#define BRX_OVERFLOW_CHECKTYPE 0x80000000
1866#define BRX_AGCSHIFT 0x7f 1889#define BRX_AGCSHIFT 0x7f
1867#define BTRSW_TRI_ONLY 0x80 1890#define BTRSW_TRI_ONLY 0x80
1868#define BPOWER_THRES 0x300 1891#define BPOWER_THRES 0x300
1869#define BRXAGC_EN 0x1 1892#define BRXAGC_EN 0x1
1870#define BRXAGC_TOGETHER_EN 0x2 1893#define BRXAGC_TOGETHER_EN 0x2
1871#define BRXAGC_MIN 0x4 1894#define BRXAGC_MIN 0x4
1872#define BRXHP_INI 0x7 1895#define BRXHP_INI 0x7
1873#define BRXHP_TRLNA 0x70 1896#define BRXHP_TRLNA 0x70
1874#define BRXHP_RSSI 0x700 1897#define BRXHP_RSSI 0x700
1875#define BRXHP_BBP1 0x7000 1898#define BRXHP_BBP1 0x7000
1876#define BRXHP_BBP2 0x70000 1899#define BRXHP_BBP2 0x70000
1877#define BRXHP_BBP3 0x700000 1900#define BRXHP_BBP3 0x700000
1878#define BRSSI_H 0x7f0000 1901#define BRSSI_H 0x7f0000
1879#define BRSSI_GEN 0x7f000000 1902#define BRSSI_GEN 0x7f000000
1880#define BRXSETTLE_TRSW 0x7 1903#define BRXSETTLE_TRSW 0x7
1881#define BRXSETTLE_LNA 0x38 1904#define BRXSETTLE_LNA 0x38
1882#define BRXSETTLE_RSSI 0x1c0 1905#define BRXSETTLE_RSSI 0x1c0
1883#define BRXSETTLE_BBP 0xe00 1906#define BRXSETTLE_BBP 0xe00
1884#define BRXSETTLE_RXHP 0x7000 1907#define BRXSETTLE_RXHP 0x7000
1885#define BRXSETTLE_ANTSW_RSSI 0x38000 1908#define BRXSETTLE_ANTSW_RSSI 0x38000
1886#define BRXSETTLE_ANTSW 0xc0000 1909#define BRXSETTLE_ANTSW 0xc0000
1887#define BRXPROCESS_TIME_DAGC 0x300000 1910#define BRXPROCESS_TIME_DAGC 0x300000
1888#define BRXSETTLE_HSSI 0x400000 1911#define BRXSETTLE_HSSI 0x400000
1889#define BRXPROCESS_TIME_BBPPW 0x800000 1912#define BRXPROCESS_TIME_BBPPW 0x800000
1890#define BRXANTENNA_POWER_SHIFT 0x3000000 1913#define BRXANTENNA_POWER_SHIFT 0x3000000
1891#define BRSSI_TABLE_SELECT 0xc000000 1914#define BRSSI_TABLE_SELECT 0xc000000
1892#define BRXHP_FINAL 0x7000000 1915#define BRXHP_FINAL 0x7000000
1893#define BRXHPSETTLE_BBP 0x7 1916#define BRXHPSETTLE_BBP 0x7
1894#define BRXHTSETTLE_HSSI 0x8 1917#define BRXHTSETTLE_HSSI 0x8
1895#define BRXHTSETTLE_RXHP 0x70 1918#define BRXHTSETTLE_RXHP 0x70
1896#define BRXHTSETTLE_BBPPW 0x80 1919#define BRXHTSETTLE_BBPPW 0x80
1897#define BRXHTSETTLE_IDLE 0x300 1920#define BRXHTSETTLE_IDLE 0x300
1898#define BRXHTSETTLE_RESERVED 0x1c00 1921#define BRXHTSETTLE_RESERVED 0x1c00
1899#define BRXHT_RXHP_EN 0x8000 1922#define BRXHT_RXHP_EN 0x8000
1900#define BRXAGC_FREEZE_THRES 0x30000 1923#define BRXAGC_FREEZE_THRES 0x30000
1901#define BRXAGC_TOGETHEREN 0x40000 1924#define BRXAGC_TOGETHEREN 0x40000
1902#define BRXHTAGC_MIN 0x80000 1925#define BRXHTAGC_MIN 0x80000
1903#define BRXHTAGC_EN 0x100000 1926#define BRXHTAGC_EN 0x100000
1904#define BRXHTDAGC_EN 0x200000 1927#define BRXHTDAGC_EN 0x200000
1905#define BRXHT_RXHP_BBP 0x1c00000 1928#define BRXHT_RXHP_BBP 0x1c00000
1906#define BRXHT_RXHP_FINAL 0xe0000000 1929#define BRXHT_RXHP_FINAL 0xe0000000
1907#define BRXPW_RADIO_TH 0x3 1930#define BRXPW_RADIO_TH 0x3
1908#define BRXPW_RADIO_EN 0x4 1931#define BRXPW_RADIO_EN 0x4
1909#define BRXMF_HOLD 0x3800 1932#define BRXMF_HOLD 0x3800
1910#define BRXPD_DELAY_TH1 0x38 1933#define BRXPD_DELAY_TH1 0x38
1911#define BRXPD_DELAY_TH2 0x1c0 1934#define BRXPD_DELAY_TH2 0x1c0
1912#define BRXPD_DC_COUNT_MAX 0x600 1935#define BRXPD_DC_COUNT_MAX 0x600
1913#define BRXPD_DELAY_TH 0x8000 1936#define BRXPD_DELAY_TH 0x8000
1914#define BRXPROCESS_DELAY 0xf0000 1937#define BRXPROCESS_DELAY 0xf0000
1915#define BRXSEARCHRANGE_GI2_EARLY 0x700000 1938#define BRXSEARCHRANGE_GI2_EARLY 0x700000
1916#define BRXFRAME_FUARD_COUNTER_L 0x3800000 1939#define BRXFRAME_FUARD_COUNTER_L 0x3800000
1917#define BRXSGI_GUARD_L 0xc000000 1940#define BRXSGI_GUARD_L 0xc000000
1918#define BRXSGI_SEARCH_L 0x30000000 1941#define BRXSGI_SEARCH_L 0x30000000
1919#define BRXSGI_TH 0xc0000000 1942#define BRXSGI_TH 0xc0000000
1920#define BDFSCNT0 0xff 1943#define BDFSCNT0 0xff
1921#define BDFSCNT1 0xff00 1944#define BDFSCNT1 0xff00
1922#define BDFSFLAG 0xf0000 1945#define BDFSFLAG 0xf0000
1923#define BMF_WEIGHT_SUM 0x300000 1946#define BMF_WEIGHT_SUM 0x300000
1924#define BMINIDX_TH 0x7f000000 1947#define BMINIDX_TH 0x7f000000
1925#define BDAFORMAT 0x40000 1948#define BDAFORMAT 0x40000
1926#define BTXCH_EMU_ENABLE 0x01000000 1949#define BTXCH_EMU_ENABLE 0x01000000
1927#define BTRSW_ISOLATION_A 0x7f 1950#define BTRSW_ISOLATION_A 0x7f
1928#define BTRSW_ISOLATION_B 0x7f00 1951#define BTRSW_ISOLATION_B 0x7f00
1929#define BTRSW_ISOLATION_C 0x7f0000 1952#define BTRSW_ISOLATION_C 0x7f0000
1930#define BTRSW_ISOLATION_D 0x7f000000 1953#define BTRSW_ISOLATION_D 0x7f000000
1931#define BEXT_LNA_GAIN 0x7c00 1954#define BEXT_LNA_GAIN 0x7c00
1932 1955
1933#define BSTBC_EN 0x4 1956#define BSTBC_EN 0x4
1934#define BANTENNA_MAPPING 0x10 1957#define BANTENNA_MAPPING 0x10
1935#define BNSS 0x20 1958#define BNSS 0x20
1936#define BCFO_ANTSUM_ID 0x200 1959#define BCFO_ANTSUM_ID 0x200
1937#define BPHY_COUNTER_RESET 0x8000000 1960#define BPHY_COUNTER_RESET 0x8000000
1938#define BCFO_REPORT_GET 0x4000000 1961#define BCFO_REPORT_GET 0x4000000
1939#define BOFDM_CONTINUE_TX 0x10000000 1962#define BOFDM_CONTINUE_TX 0x10000000
1940#define BOFDM_SINGLE_CARRIER 0x20000000 1963#define BOFDM_SINGLE_CARRIER 0x20000000
1941#define BOFDM_SINGLE_TONE 0x40000000 1964#define BOFDM_SINGLE_TONE 0x40000000
1942#define BHT_DETECT 0x100 1965#define BHT_DETECT 0x100
1943#define BCFOEN 0x10000 1966#define BCFOEN 0x10000
1944#define BCFOVALUE 0xfff00000 1967#define BCFOVALUE 0xfff00000
1945#define BSIGTONE_RE 0x3f 1968#define BSIGTONE_RE 0x3f
1946#define BSIGTONE_IM 0x7f00 1969#define BSIGTONE_IM 0x7f00
1947#define BCOUNTER_CCA 0xffff 1970#define BCOUNTER_CCA 0xffff
1948#define BCOUNTER_PARITYFAIL 0xffff0000 1971#define BCOUNTER_PARITYFAIL 0xffff0000
1949#define BCOUNTER_RATEILLEGAL 0xffff 1972#define BCOUNTER_RATEILLEGAL 0xffff
1950#define BCOUNTER_CRC8FAIL 0xffff0000 1973#define BCOUNTER_CRC8FAIL 0xffff0000
1951#define BCOUNTER_MCSNOSUPPORT 0xffff 1974#define BCOUNTER_MCSNOSUPPORT 0xffff
1952#define BCOUNTER_FASTSYNC 0xffff 1975#define BCOUNTER_FASTSYNC 0xffff
1953#define BSHORTCFO 0xfff 1976#define BSHORTCFO 0xfff
1954#define BSHORTCFOT_LENGTH 12 1977#define BSHORTCFOT_LENGTH 12
1955#define BSHORTCFOF_LENGTH 11 1978#define BSHORTCFOF_LENGTH 11
1956#define BLONGCFO 0x7ff 1979#define BLONGCFO 0x7ff
1957#define BLONGCFOT_LENGTH 11 1980#define BLONGCFOT_LENGTH 11
1958#define BLONGCFOF_LENGTH 11 1981#define BLONGCFOF_LENGTH 11
1959#define BTAILCFO 0x1fff 1982#define BTAILCFO 0x1fff
1960#define BTAILCFOT_LENGTH 13 1983#define BTAILCFOT_LENGTH 13
1961#define BTAILCFOF_LENGTH 12 1984#define BTAILCFOF_LENGTH 12
1962#define BNOISE_EN_PWDB 0xffff 1985#define BNOISE_EN_PWDB 0xffff
1963#define BCC_POWER_DB 0xffff0000 1986#define BCC_POWER_DB 0xffff0000
1964#define BMOISE_PWDB 0xffff 1987#define BMOISE_PWDB 0xffff
1965#define BPOWERMEAST_LENGTH 10 1988#define BPOWERMEAST_LENGTH 10
1966#define BPOWERMEASF_LENGTH 3 1989#define BPOWERMEASF_LENGTH 3
1967#define BRX_HT_BW 0x1 1990#define BRX_HT_BW 0x1
1968#define BRXSC 0x6 1991#define BRXSC 0x6
1969#define BRX_HT 0x8 1992#define BRX_HT 0x8
1970#define BNB_INTF_DET_ON 0x1 1993#define BNB_INTF_DET_ON 0x1
1971#define BINTF_WIN_LEN_CFG 0x30 1994#define BINTF_WIN_LEN_CFG 0x30
1972#define BNB_INTF_TH_CFG 0x1c0 1995#define BNB_INTF_TH_CFG 0x1c0
1973#define BRFGAIN 0x3f 1996#define BRFGAIN 0x3f
1974#define BTABLESEL 0x40 1997#define BTABLESEL 0x40
1975#define BTRSW 0x80 1998#define BTRSW 0x80
1976#define BRXSNR_A 0xff 1999#define BRXSNR_A 0xff
1977#define BRXSNR_B 0xff00 2000#define BRXSNR_B 0xff00
1978#define BRXSNR_C 0xff0000 2001#define BRXSNR_C 0xff0000
1979#define BRXSNR_D 0xff000000 2002#define BRXSNR_D 0xff000000
1980#define BSNR_EVMT_LENGTH 8 2003#define BSNR_EVMT_LENGTH 8
1981#define BSNR_EVMF_LENGTH 1 2004#define BSNR_EVMF_LENGTH 1
1982#define BCSI1ST 0xff 2005#define BCSI1ST 0xff
1983#define BCSI2ND 0xff00 2006#define BCSI2ND 0xff00
1984#define BRXEVM1ST 0xff0000 2007#define BRXEVM1ST 0xff0000
1985#define BRXEVM2ND 0xff000000 2008#define BRXEVM2ND 0xff000000
1986#define BSIGEVM 0xff 2009#define BSIGEVM 0xff
1987#define BPWDB 0xff00 2010#define BPWDB 0xff00
1988#define BSGIEN 0x10000 2011#define BSGIEN 0x10000
1989 2012
1990#define BSFACTOR_QMA1 0xf 2013#define BSFACTOR_QMA1 0xf
1991#define BSFACTOR_QMA2 0xf0 2014#define BSFACTOR_QMA2 0xf0
1992#define BSFACTOR_QMA3 0xf00 2015#define BSFACTOR_QMA3 0xf00
1993#define BSFACTOR_QMA4 0xf000 2016#define BSFACTOR_QMA4 0xf000
1994#define BSFACTOR_QMA5 0xf0000 2017#define BSFACTOR_QMA5 0xf0000
1995#define BSFACTOR_QMA6 0xf0000 2018#define BSFACTOR_QMA6 0xf0000
1996#define BSFACTOR_QMA7 0xf00000 2019#define BSFACTOR_QMA7 0xf00000
1997#define BSFACTOR_QMA8 0xf000000 2020#define BSFACTOR_QMA8 0xf000000
1998#define BSFACTOR_QMA9 0xf0000000 2021#define BSFACTOR_QMA9 0xf0000000
1999#define BCSI_SCHEME 0x100000 2022#define BCSI_SCHEME 0x100000
2000 2023
2001#define BNOISE_LVL_TOP_SET 0x3 2024#define BNOISE_LVL_TOP_SET 0x3
2002#define BCHSMOOTH 0x4 2025#define BCHSMOOTH 0x4
2003#define BCHSMOOTH_CFG1 0x38 2026#define BCHSMOOTH_CFG1 0x38
2004#define BCHSMOOTH_CFG2 0x1c0 2027#define BCHSMOOTH_CFG2 0x1c0
2005#define BCHSMOOTH_CFG3 0xe00 2028#define BCHSMOOTH_CFG3 0xe00
2006#define BCHSMOOTH_CFG4 0x7000 2029#define BCHSMOOTH_CFG4 0x7000
2007#define BMRCMODE 0x800000 2030#define BMRCMODE 0x800000
2008#define BTHEVMCFG 0x7000000 2031#define BTHEVMCFG 0x7000000
2009 2032
2010#define BLOOP_FIT_TYPE 0x1 2033#define BLOOP_FIT_TYPE 0x1
2011#define BUPD_CFO 0x40 2034#define BUPD_CFO 0x40
2012#define BUPD_CFO_OFFDATA 0x80 2035#define BUPD_CFO_OFFDATA 0x80
2013#define BADV_UPD_CFO 0x100 2036#define BADV_UPD_CFO 0x100
2014#define BADV_TIME_CTRL 0x800 2037#define BADV_TIME_CTRL 0x800
2015#define BUPD_CLKO 0x1000 2038#define BUPD_CLKO 0x1000
2016#define BFC 0x6000 2039#define BFC 0x6000
2017#define BTRACKING_MODE 0x8000 2040#define BTRACKING_MODE 0x8000
2018#define BPHCMP_ENABLE 0x10000 2041#define BPHCMP_ENABLE 0x10000
2019#define BUPD_CLKO_LTF 0x20000 2042#define BUPD_CLKO_LTF 0x20000
2020#define BCOM_CH_CFO 0x40000 2043#define BCOM_CH_CFO 0x40000
2021#define BCSI_ESTI_MODE 0x80000 2044#define BCSI_ESTI_MODE 0x80000
2022#define BADV_UPD_EQZ 0x100000 2045#define BADV_UPD_EQZ 0x100000
2023#define BUCHCFG 0x7000000 2046#define BUCHCFG 0x7000000
2024#define BUPDEQZ 0x8000000 2047#define BUPDEQZ 0x8000000
2025 2048
2026#define BRX_PESUDO_NOISE_ON 0x20000000 2049#define BRX_PESUDO_NOISE_ON 0x20000000
2027#define BRX_PESUDO_NOISE_A 0xff 2050#define BRX_PESUDO_NOISE_A 0xff
2028#define BRX_PESUDO_NOISE_B 0xff00 2051#define BRX_PESUDO_NOISE_B 0xff00
2029#define BRX_PESUDO_NOISE_C 0xff0000 2052#define BRX_PESUDO_NOISE_C 0xff0000
2030#define BRX_PESUDO_NOISE_D 0xff000000 2053#define BRX_PESUDO_NOISE_D 0xff000000
2031#define BRX_PESUDO_NOISESTATE_A 0xffff 2054#define BRX_PESUDO_NOISESTATE_A 0xffff
2032#define BRX_PESUDO_NOISESTATE_B 0xffff0000 2055#define BRX_PESUDO_NOISESTATE_B 0xffff0000
2033#define BRX_PESUDO_NOISESTATE_C 0xffff 2056#define BRX_PESUDO_NOISESTATE_C 0xffff
2034#define BRX_PESUDO_NOISESTATE_D 0xffff0000 2057#define BRX_PESUDO_NOISESTATE_D 0xffff0000
2035 2058
2036#define BZEBRA1_HSSIENABLE 0x8 2059#define BZEBRA1_HSSIENABLE 0x8
2037#define BZEBRA1_TRXCONTROL 0xc00 2060#define BZEBRA1_TRXCONTROL 0xc00
2038#define BZEBRA1_TRXGAINSETTING 0x07f 2061#define BZEBRA1_TRXGAINSETTING 0x07f
2039#define BZEBRA1_RXCOUNTER 0xc00 2062#define BZEBRA1_RXCOUNTER 0xc00
2040#define BZEBRA1_TXCHANGEPUMP 0x38 2063#define BZEBRA1_TXCHANGEPUMP 0x38
2041#define BZEBRA1_RXCHANGEPUMP 0x7 2064#define BZEBRA1_RXCHANGEPUMP 0x7
2042#define BZEBRA1_CHANNEL_NUM 0xf80 2065#define BZEBRA1_CHANNEL_NUM 0xf80
2043#define BZEBRA1_TXLPFBW 0x400 2066#define BZEBRA1_TXLPFBW 0x400
2044#define BZEBRA1_RXLPFBW 0x600 2067#define BZEBRA1_RXLPFBW 0x600
2045 2068
2046#define BRTL8256REG_MODE_CTRL1 0x100 2069#define BRTL8256REG_MODE_CTRL1 0x100
2047#define BRTL8256REG_MODE_CTRL0 0x40 2070#define BRTL8256REG_MODE_CTRL0 0x40
2048#define BRTL8256REG_TXLPFBW 0x18 2071#define BRTL8256REG_TXLPFBW 0x18
2049#define BRTL8256REG_RXLPFBW 0x600 2072#define BRTL8256REG_RXLPFBW 0x600
2050 2073
2051#define BRTL8258_TXLPFBW 0xc 2074#define BRTL8258_TXLPFBW 0xc
2052#define BRTL8258_RXLPFBW 0xc00 2075#define BRTL8258_RXLPFBW 0xc00
2053#define BRTL8258_RSSILPFBW 0xc0 2076#define BRTL8258_RSSILPFBW 0xc0
2054 2077
2055#define BBYTE0 0x1 2078#define BBYTE0 0x1
2056#define BBYTE1 0x2 2079#define BBYTE1 0x2
2057#define BBYTE2 0x4 2080#define BBYTE2 0x4
2058#define BBYTE3 0x8 2081#define BBYTE3 0x8
2059#define BWORD0 0x3 2082#define BWORD0 0x3
2060#define BWORD1 0xc 2083#define BWORD1 0xc
2061#define BWORD 0xf 2084#define BWORD 0xf
2062 2085
2063#define BENABLE 0x1 2086#define MASKBYTE0 0xff
2064#define BDISABLE 0x0 2087#define MASKBYTE1 0xff00
2065 2088#define MASKBYTE2 0xff0000
2066#define LEFT_ANTENNA 0x0 2089#define MASKBYTE3 0xff000000
2067#define RIGHT_ANTENNA 0x1 2090#define MASKHWORD 0xffff0000
2068 2091#define MASKLWORD 0x0000ffff
2069#define TCHECK_TXSTATUS 500 2092#define MASKDWORD 0xffffffff
2070#define TUPDATE_RXCOUNTER 100 2093#define MASK12BITS 0xfff
2094#define MASKH4BITS 0xf0000000
2095#define MASKOFDM_D 0xffc00000
2096#define MASKCCK 0x3f3f3f3f
2097
2098#define MASK4BITS 0x0f
2099#define MASK20BITS 0xfffff
2100#define RFREG_OFFSET_MASK 0xfffff
2101
2102#define BENABLE 0x1
2103#define BDISABLE 0x0
2104
2105#define LEFT_ANTENNA 0x0
2106#define RIGHT_ANTENNA 0x1
2107
2108#define TCHECK_TXSTATUS 500
2109#define TUPDATE_RXCOUNTER 100
2071 2110
2072/* 2 EFUSE_TEST (For RTL8723 partially) */ 2111/* 2 EFUSE_TEST (For RTL8723 partially) */
2073#define EFUSE_SEL(x) (((x) & 0x3) << 8) 2112#define EFUSE_SEL(x) (((x) & 0x3) << 8)
2074#define EFUSE_SEL_MASK 0x300 2113#define EFUSE_SEL_MASK 0x300
2075#define EFUSE_WIFI_SEL_0 0x0 2114#define EFUSE_WIFI_SEL_0 0x0
2076
2077/* Enable GPIO[9] as WiFi HW PDn source*/ 2115/* Enable GPIO[9] as WiFi HW PDn source*/
2078#define WL_HWPDN_EN BIT(0) 2116#define WL_HWPDN_EN BIT(0)
2079/* WiFi HW PDn polarity control*/ 2117/* WiFi HW PDn polarity control*/
2080#define WL_HWPDN_SL BIT(1) 2118#define WL_HWPDN_SL BIT(1)
2081 2119
2082#endif 2120#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/rf.c b/drivers/net/wireless/rtlwifi/rtl8723ae/rf.c
index 50dd2fb2c93d..9ebc8281ff99 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/rf.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/rf.c
@@ -11,10 +11,6 @@
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details. 12 * more details.
13 * 13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the 14 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE. 15 * file called LICENSE.
20 * 16 *
@@ -34,10 +30,12 @@
34#include "rf.h" 30#include "rf.h"
35#include "dm.h" 31#include "dm.h"
36 32
37void rtl8723ae_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth) 33static bool _rtl8723e_phy_rf6052_config_parafile(struct ieee80211_hw *hw);
34
35void rtl8723e_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
38{ 36{
39 struct rtl_priv *rtlpriv = rtl_priv(hw); 37 struct rtl_priv *rtlpriv = rtl_priv(hw);
40 struct rtl_phy *rtlphy = &(rtlpriv->phy); 38 struct rtl_phy *rtlphy = &rtlpriv->phy;
41 39
42 switch (bandwidth) { 40 switch (bandwidth) {
43 case HT_CHANNEL_WIDTH_20: 41 case HT_CHANNEL_WIDTH_20:
@@ -59,11 +57,11 @@ void rtl8723ae_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
59 } 57 }
60} 58}
61 59
62void rtl8723ae_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw, 60void rtl8723e_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
63 u8 *ppowerlevel) 61 u8 *ppowerlevel)
64{ 62{
65 struct rtl_priv *rtlpriv = rtl_priv(hw); 63 struct rtl_priv *rtlpriv = rtl_priv(hw);
66 struct rtl_phy *rtlphy = &(rtlpriv->phy); 64 struct rtl_phy *rtlphy = &rtlpriv->phy;
67 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 65 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
68 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 66 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
69 u32 tx_agc[2] = {0, 0}, tmpval; 67 u32 tx_agc[2] = {0, 0}, tmpval;
@@ -79,7 +77,8 @@ void rtl8723ae_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
79 tx_agc[RF90_PATH_B] = 0x3f3f3f3f; 77 tx_agc[RF90_PATH_B] = 0x3f3f3f3f;
80 78
81 if (turbo_scanoff) { 79 if (turbo_scanoff) {
82 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) { 80 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B;
81 idx1++) {
83 tx_agc[idx1] = ppowerlevel[idx1] | 82 tx_agc[idx1] = ppowerlevel[idx1] |
84 (ppowerlevel[idx1] << 8) | 83 (ppowerlevel[idx1] << 8) |
85 (ppowerlevel[idx1] << 16) | 84 (ppowerlevel[idx1] << 16) |
@@ -89,24 +88,27 @@ void rtl8723ae_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
89 } else { 88 } else {
90 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) { 89 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
91 tx_agc[idx1] = ppowerlevel[idx1] | 90 tx_agc[idx1] = ppowerlevel[idx1] |
92 (ppowerlevel[idx1] << 8) | 91 (ppowerlevel[idx1] << 8) |
93 (ppowerlevel[idx1] << 16) | 92 (ppowerlevel[idx1] << 16) |
94 (ppowerlevel[idx1] << 24); 93 (ppowerlevel[idx1] << 24);
95 } 94 }
96 95
97 if (rtlefuse->eeprom_regulatory == 0) { 96 if (rtlefuse->eeprom_regulatory == 0) {
98 tmpval = (rtlphy->mcs_offset[0][6]) + 97 tmpval =
99 (rtlphy->mcs_offset[0][7] << 8); 98 (rtlphy->mcs_txpwrlevel_origoffset[0][6]) +
99 (rtlphy->mcs_txpwrlevel_origoffset[0][7] <<
100 8);
100 tx_agc[RF90_PATH_A] += tmpval; 101 tx_agc[RF90_PATH_A] += tmpval;
101 102
102 tmpval = (rtlphy->mcs_offset[0][14]) + 103 tmpval = (rtlphy->mcs_txpwrlevel_origoffset[0][14]) +
103 (rtlphy->mcs_offset[0][15] << 24); 104 (rtlphy->mcs_txpwrlevel_origoffset[0][15] <<
105 24);
104 tx_agc[RF90_PATH_B] += tmpval; 106 tx_agc[RF90_PATH_B] += tmpval;
105 } 107 }
106 } 108 }
107 109
108 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) { 110 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
109 ptr = (u8 *) (&(tx_agc[idx1])); 111 ptr = (u8 *)&tx_agc[idx1];
110 for (idx2 = 0; idx2 < 4; idx2++) { 112 for (idx2 = 0; idx2 < 4; idx2++) {
111 if (*ptr > RF6052_MAX_TX_PWR) 113 if (*ptr > RF6052_MAX_TX_PWR)
112 *ptr = RF6052_MAX_TX_PWR; 114 *ptr = RF6052_MAX_TX_PWR;
@@ -119,7 +121,7 @@ void rtl8723ae_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
119 121
120 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 122 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
121 "CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, 123 "CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
122 RTXAGC_A_CCK1_MCS32); 124 RTXAGC_A_CCK1_MCS32);
123 125
124 tmpval = tx_agc[RF90_PATH_A] >> 8; 126 tmpval = tx_agc[RF90_PATH_A] >> 8;
125 127
@@ -129,100 +131,99 @@ void rtl8723ae_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
129 131
130 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 132 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
131 "CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, 133 "CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
132 RTXAGC_B_CCK11_A_CCK2_11); 134 RTXAGC_B_CCK11_A_CCK2_11);
133 135
134 tmpval = tx_agc[RF90_PATH_B] >> 24; 136 tmpval = tx_agc[RF90_PATH_B] >> 24;
135 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval); 137 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval);
136 138
137 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 139 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
138 "CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval, 140 "CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
139 RTXAGC_B_CCK11_A_CCK2_11); 141 RTXAGC_B_CCK11_A_CCK2_11);
140 142
141 tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff; 143 tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff;
142 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval); 144 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval);
143 145
144 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 146 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
145 "CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", tmpval, 147 "CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
146 RTXAGC_B_CCK1_55_MCS32); 148 RTXAGC_B_CCK1_55_MCS32);
147} 149}
148 150
149static void rtl8723ae_phy_get_power_base(struct ieee80211_hw *hw, 151static void rtl8723e_phy_get_power_base(struct ieee80211_hw *hw,
150 u8 *ppowerlevel, u8 channel, 152 u8 *ppowerlevel, u8 channel,
151 u32 *ofdmbase, u32 *mcsbase) 153 u32 *ofdmbase, u32 *mcsbase)
152{ 154{
153 struct rtl_priv *rtlpriv = rtl_priv(hw); 155 struct rtl_priv *rtlpriv = rtl_priv(hw);
154 struct rtl_phy *rtlphy = &(rtlpriv->phy); 156 struct rtl_phy *rtlphy = &rtlpriv->phy;
155 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 157 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
156 u32 powerBase0, powerBase1; 158 u32 powerbase0, powerbase1;
157 u8 legacy_pwrdiff, ht20_pwrdiff; 159 u8 legacy_pwrdiff, ht20_pwrdiff;
158 u8 i, powerlevel[2]; 160 u8 i, powerlevel[2];
159 161
160 for (i = 0; i < 2; i++) { 162 for (i = 0; i < 2; i++) {
161 powerlevel[i] = ppowerlevel[i]; 163 powerlevel[i] = ppowerlevel[i];
162 legacy_pwrdiff = rtlefuse->txpwr_legacyhtdiff[i][channel - 1]; 164 legacy_pwrdiff = rtlefuse->txpwr_legacyhtdiff[i][channel - 1];
163 powerBase0 = powerlevel[i] + legacy_pwrdiff; 165 powerbase0 = powerlevel[i] + legacy_pwrdiff;
164 166
165 powerBase0 = (powerBase0 << 24) | (powerBase0 << 16) | 167 powerbase0 = (powerbase0 << 24) | (powerbase0 << 16) |
166 (powerBase0 << 8) | powerBase0; 168 (powerbase0 << 8) | powerbase0;
167 *(ofdmbase + i) = powerBase0; 169 *(ofdmbase + i) = powerbase0;
168 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 170 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
169 " [OFDM power base index rf(%c) = 0x%x]\n", 171 " [OFDM power base index rf(%c) = 0x%x]\n",
170 ((i == 0) ? 'A' : 'B'), *(ofdmbase + i)); 172 ((i == 0) ? 'A' : 'B'), *(ofdmbase + i));
171 } 173 }
172 174
173 for (i = 0; i < 2; i++) { 175 for (i = 0; i < 2; i++) {
174 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) { 176 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) {
175 ht20_pwrdiff = rtlefuse->txpwr_ht20diff[i][channel - 1]; 177 ht20_pwrdiff =
178 rtlefuse->txpwr_ht20diff[i][channel - 1];
176 powerlevel[i] += ht20_pwrdiff; 179 powerlevel[i] += ht20_pwrdiff;
177 } 180 }
178 powerBase1 = powerlevel[i]; 181 powerbase1 = powerlevel[i];
179 powerBase1 = (powerBase1 << 24) | 182 powerbase1 = (powerbase1 << 24) |
180 (powerBase1 << 16) | (powerBase1 << 8) | powerBase1; 183 (powerbase1 << 16) | (powerbase1 << 8) | powerbase1;
181 184
182 *(mcsbase + i) = powerBase1; 185 *(mcsbase + i) = powerbase1;
183 186
184 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 187 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
185 " [MCS power base index rf(%c) = 0x%x]\n", 188 " [MCS power base index rf(%c) = 0x%x]\n",
186 ((i == 0) ? 'A' : 'B'), *(mcsbase + i)); 189 ((i == 0) ? 'A' : 'B'), *(mcsbase + i));
187 } 190 }
188} 191}
189 192
190static void rtl8723ae_get_txpwr_val_by_reg(struct ieee80211_hw *hw, 193static void get_txpower_writeval_by_reg(struct ieee80211_hw *hw,
191 u8 channel, u8 index, 194 u8 channel, u8 index,
192 u32 *powerBase0, 195 u32 *powerbase0,
193 u32 *powerBase1, 196 u32 *powerbase1,
194 u32 *p_outwriteval) 197 u32 *p_outwriteval)
195{ 198{
196 struct rtl_priv *rtlpriv = rtl_priv(hw); 199 struct rtl_priv *rtlpriv = rtl_priv(hw);
197 struct rtl_phy *rtlphy = &(rtlpriv->phy); 200 struct rtl_phy *rtlphy = &rtlpriv->phy;
198 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 201 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
199 u8 i, chnlgroup = 0, pwr_diff_limit[4]; 202 u8 i, chnlgroup = 0, pwr_diff_limit[4];
200 u32 writeVal, customer_limit, rf; 203 u32 writeval, customer_limit, rf;
201 204
202 for (rf = 0; rf < 2; rf++) { 205 for (rf = 0; rf < 2; rf++) {
203 switch (rtlefuse->eeprom_regulatory) { 206 switch (rtlefuse->eeprom_regulatory) {
204 case 0: 207 case 0:
205 chnlgroup = 0; 208 chnlgroup = 0;
206 209
207 writeVal = rtlphy->mcs_offset[chnlgroup] 210 writeval =
208 [index + (rf ? 8 : 0)] + 211 rtlphy->mcs_txpwrlevel_origoffset[chnlgroup][index +
209 ((index < 2) ? powerBase0[rf] : 212 (rf ? 8 : 0)]
210 powerBase1[rf]); 213 + ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
211 214
212 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 215 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
213 "RTK better performance, " 216 "RTK better performance, writeval(%c) = 0x%x\n",
214 "writeVal(%c) = 0x%x\n", 217 ((rf == 0) ? 'A' : 'B'), writeval);
215 ((rf == 0) ? 'A' : 'B'), writeVal);
216 break; 218 break;
217 case 1: 219 case 1:
218 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) { 220 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
219 writeVal = ((index < 2) ? powerBase0[rf] : 221 writeval = ((index < 2) ? powerbase0[rf] :
220 powerBase1[rf]); 222 powerbase1[rf]);
221 223
222 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 224 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
223 "Realtek regulatory, 40MHz, " 225 "Realtek regulatory, 40MHz, writeval(%c) = 0x%x\n",
224 "writeVal(%c) = 0x%x\n", 226 ((rf == 0) ? 'A' : 'B'), writeval);
225 ((rf == 0) ? 'A' : 'B'), writeVal);
226 } else { 227 } else {
227 if (rtlphy->pwrgroup_cnt == 1) 228 if (rtlphy->pwrgroup_cnt == 1)
228 chnlgroup = 0; 229 chnlgroup = 0;
@@ -234,29 +235,30 @@ static void rtl8723ae_get_txpwr_val_by_reg(struct ieee80211_hw *hw,
234 else if (channel > 9) 235 else if (channel > 9)
235 chnlgroup = 2; 236 chnlgroup = 2;
236 if (rtlphy->current_chan_bw == 237 if (rtlphy->current_chan_bw ==
237 HT_CHANNEL_WIDTH_20) 238 HT_CHANNEL_WIDTH_20)
238 chnlgroup++; 239 chnlgroup++;
239 else 240 else
240 chnlgroup += 4; 241 chnlgroup += 4;
241 } 242 }
242 243
243 writeVal = rtlphy->mcs_offset[chnlgroup] 244 writeval =
245 rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
244 [index + (rf ? 8 : 0)] + ((index < 2) ? 246 [index + (rf ? 8 : 0)] + ((index < 2) ?
245 powerBase0[rf] : 247 powerbase0[rf] :
246 powerBase1[rf]); 248 powerbase1[rf]);
247 249
248 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 250 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
249 "Realtek regulatory, 20MHz, writeVal(%c) = 0x%x\n", 251 "Realtek regulatory, 20MHz, writeval(%c) = 0x%x\n",
250 ((rf == 0) ? 'A' : 'B'), writeVal); 252 ((rf == 0) ? 'A' : 'B'), writeval);
251 } 253 }
252 break; 254 break;
253 case 2: 255 case 2:
254 writeVal = 256 writeval =
255 ((index < 2) ? powerBase0[rf] : powerBase1[rf]); 257 ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
256 258
257 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 259 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
258 "Better regulatory, writeVal(%c) = 0x%x\n", 260 "Better regulatory, writeval(%c) = 0x%x\n",
259 ((rf == 0) ? 'A' : 'B'), writeVal); 261 ((rf == 0) ? 'A' : 'B'), writeval);
260 break; 262 break;
261 case 3: 263 case 3:
262 chnlgroup = 0; 264 chnlgroup = 0;
@@ -265,18 +267,21 @@ static void rtl8723ae_get_txpwr_val_by_reg(struct ieee80211_hw *hw,
265 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 267 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
266 "customer's limit, 40MHz rf(%c) = 0x%x\n", 268 "customer's limit, 40MHz rf(%c) = 0x%x\n",
267 ((rf == 0) ? 'A' : 'B'), 269 ((rf == 0) ? 'A' : 'B'),
268 rtlefuse->pwrgroup_ht40[rf][channel-1]); 270 rtlefuse->pwrgroup_ht40[rf][channel -
271 1]);
269 } else { 272 } else {
270 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 273 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
271 "customer's limit, 20MHz rf(%c) = 0x%x\n", 274 "customer's limit, 20MHz rf(%c) = 0x%x\n",
272 ((rf == 0) ? 'A' : 'B'), 275 ((rf == 0) ? 'A' : 'B'),
273 rtlefuse->pwrgroup_ht20[rf][channel-1]); 276 rtlefuse->pwrgroup_ht20[rf][channel -
277 1]);
274 } 278 }
275 for (i = 0; i < 4; i++) { 279 for (i = 0; i < 4; i++) {
276 pwr_diff_limit[i] = 280 pwr_diff_limit[i] =
277 (u8) ((rtlphy->mcs_offset 281 (u8)((rtlphy->mcs_txpwrlevel_origoffset
278 [chnlgroup][index + (rf ? 8 : 0)] & 282 [chnlgroup][index +
279 (0x7f << (i * 8))) >> (i * 8)); 283 (rf ? 8 : 0)] & (0x7f <<
284 (i * 8))) >> (i * 8));
280 285
281 if (rtlphy->current_chan_bw == 286 if (rtlphy->current_chan_bw ==
282 HT_CHANNEL_WIDTH_20_40) { 287 HT_CHANNEL_WIDTH_20_40) {
@@ -302,41 +307,42 @@ static void rtl8723ae_get_txpwr_val_by_reg(struct ieee80211_hw *hw,
302 307
303 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 308 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
304 "Customer's limit rf(%c) = 0x%x\n", 309 "Customer's limit rf(%c) = 0x%x\n",
305 ((rf == 0) ? 'A' : 'B'), customer_limit); 310 ((rf == 0) ? 'A' : 'B'), customer_limit);
306 311
307 writeVal = customer_limit + 312 writeval = customer_limit +
308 ((index < 2) ? powerBase0[rf] : powerBase1[rf]); 313 ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
309 314
310 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 315 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
311 "Customer, writeVal rf(%c)= 0x%x\n", 316 "Customer, writeval rf(%c)= 0x%x\n",
312 ((rf == 0) ? 'A' : 'B'), writeVal); 317 ((rf == 0) ? 'A' : 'B'), writeval);
313 break; 318 break;
314 default: 319 default:
315 chnlgroup = 0; 320 chnlgroup = 0;
316 writeVal = rtlphy->mcs_offset[chnlgroup][index + 321 writeval =
317 (rf ? 8 : 0)] + ((index < 2) ? powerBase0[rf] : 322 rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
318 powerBase1[rf]); 323 [index + (rf ? 8 : 0)]
324 + ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
319 325
320 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 326 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
321 "RTK better performance, writeVal rf(%c) = 0x%x\n", 327 "RTK better performance, writeval rf(%c) = 0x%x\n",
322 ((rf == 0) ? 'A' : 'B'), writeVal); 328 ((rf == 0) ? 'A' : 'B'), writeval);
323 break; 329 break;
324 } 330 }
325 331
326 if (rtlpriv->dm.dynamic_txhighpower_lvl == TXHIGHPWRLEVEL_BT1) 332 if (rtlpriv->dm.dynamic_txhighpower_lvl == TXHIGHPWRLEVEL_BT1)
327 writeVal = writeVal - 0x06060606; 333 writeval = writeval - 0x06060606;
328 else if (rtlpriv->dm.dynamic_txhighpower_lvl == 334 else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
329 TXHIGHPWRLEVEL_BT2) 335 TXHIGHPWRLEVEL_BT2)
330 writeVal = writeVal - 0x0c0c0c0c; 336 writeval = writeval - 0x0c0c0c0c;
331 *(p_outwriteval + rf) = writeVal; 337 *(p_outwriteval + rf) = writeval;
332 } 338 }
333} 339}
334 340
335static void _rtl8723ae_write_ofdm_power_reg(struct ieee80211_hw *hw, 341static void _rtl8723e_write_ofdm_power_reg(struct ieee80211_hw *hw,
336 u8 index, u32 *pValue) 342 u8 index, u32 *pvalue)
337{ 343{
338 struct rtl_priv *rtlpriv = rtl_priv(hw); 344 struct rtl_priv *rtlpriv = rtl_priv(hw);
339 struct rtl_phy *rtlphy = &(rtlpriv->phy); 345 struct rtl_phy *rtlphy = &rtlpriv->phy;
340 346
341 u16 regoffset_a[6] = { 347 u16 regoffset_a[6] = {
342 RTXAGC_A_RATE18_06, RTXAGC_A_RATE54_24, 348 RTXAGC_A_RATE18_06, RTXAGC_A_RATE54_24,
@@ -349,29 +355,29 @@ static void _rtl8723ae_write_ofdm_power_reg(struct ieee80211_hw *hw,
349 RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12 355 RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12
350 }; 356 };
351 u8 i, rf, pwr_val[4]; 357 u8 i, rf, pwr_val[4];
352 u32 writeVal; 358 u32 writeval;
353 u16 regoffset; 359 u16 regoffset;
354 360
355 for (rf = 0; rf < 2; rf++) { 361 for (rf = 0; rf < 2; rf++) {
356 writeVal = pValue[rf]; 362 writeval = pvalue[rf];
357 for (i = 0; i < 4; i++) { 363 for (i = 0; i < 4; i++) {
358 pwr_val[i] = (u8) ((writeVal & (0x7f << 364 pwr_val[i] = (u8)((writeval & (0x7f <<
359 (i * 8))) >> (i * 8)); 365 (i * 8))) >> (i * 8));
360 366
361 if (pwr_val[i] > RF6052_MAX_TX_PWR) 367 if (pwr_val[i] > RF6052_MAX_TX_PWR)
362 pwr_val[i] = RF6052_MAX_TX_PWR; 368 pwr_val[i] = RF6052_MAX_TX_PWR;
363 } 369 }
364 writeVal = (pwr_val[3] << 24) | (pwr_val[2] << 16) | 370 writeval = (pwr_val[3] << 24) | (pwr_val[2] << 16) |
365 (pwr_val[1] << 8) | pwr_val[0]; 371 (pwr_val[1] << 8) | pwr_val[0];
366 372
367 if (rf == 0) 373 if (rf == 0)
368 regoffset = regoffset_a[index]; 374 regoffset = regoffset_a[index];
369 else 375 else
370 regoffset = regoffset_b[index]; 376 regoffset = regoffset_b[index];
371 rtl_set_bbreg(hw, regoffset, MASKDWORD, writeVal); 377 rtl_set_bbreg(hw, regoffset, MASKDWORD, writeval);
372 378
373 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 379 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
374 "Set 0x%x = %08x\n", regoffset, writeVal); 380 "Set 0x%x = %08x\n", regoffset, writeval);
375 381
376 if (((get_rf_type(rtlphy) == RF_2T2R) && 382 if (((get_rf_type(rtlphy) == RF_2T2R) &&
377 (regoffset == RTXAGC_A_MCS15_MCS12 || 383 (regoffset == RTXAGC_A_MCS15_MCS12 ||
@@ -380,7 +386,7 @@ static void _rtl8723ae_write_ofdm_power_reg(struct ieee80211_hw *hw,
380 (regoffset == RTXAGC_A_MCS07_MCS04 || 386 (regoffset == RTXAGC_A_MCS07_MCS04 ||
381 regoffset == RTXAGC_B_MCS07_MCS04))) { 387 regoffset == RTXAGC_B_MCS07_MCS04))) {
382 388
383 writeVal = pwr_val[3]; 389 writeval = pwr_val[3];
384 if (regoffset == RTXAGC_A_MCS15_MCS12 || 390 if (regoffset == RTXAGC_A_MCS15_MCS12 ||
385 regoffset == RTXAGC_A_MCS07_MCS04) 391 regoffset == RTXAGC_A_MCS07_MCS04)
386 regoffset = 0xc90; 392 regoffset = 0xc90;
@@ -389,37 +395,49 @@ static void _rtl8723ae_write_ofdm_power_reg(struct ieee80211_hw *hw,
389 regoffset = 0xc98; 395 regoffset = 0xc98;
390 396
391 for (i = 0; i < 3; i++) { 397 for (i = 0; i < 3; i++) {
392 writeVal = (writeVal > 6) ? (writeVal - 6) : 0; 398 writeval = (writeval > 6) ? (writeval - 6) : 0;
393 rtl_write_byte(rtlpriv, (u32) (regoffset + i), 399 rtl_write_byte(rtlpriv, (u32) (regoffset + i),
394 (u8) writeVal); 400 (u8)writeval);
395 } 401 }
396 } 402 }
397 } 403 }
398} 404}
399 405
400void rtl8723ae_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw, 406void rtl8723e_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
401 u8 *ppowerlevel, u8 channel) 407 u8 *ppowerlevel, u8 channel)
402{ 408{
403 u32 writeVal[2], powerBase0[2], powerBase1[2]; 409 u32 writeval[2], powerbase0[2], powerbase1[2];
404 u8 index; 410 u8 index;
405 411
406 rtl8723ae_phy_get_power_base(hw, ppowerlevel, 412 rtl8723e_phy_get_power_base(hw, ppowerlevel,
407 channel, &powerBase0[0], &powerBase1[0]); 413 channel, &powerbase0[0], &powerbase1[0]);
408 414
409 for (index = 0; index < 6; index++) { 415 for (index = 0; index < 6; index++) {
410 rtl8723ae_get_txpwr_val_by_reg(hw, channel, index, 416 get_txpower_writeval_by_reg(hw, channel, index, &powerbase0[0],
411 &powerBase0[0], 417 &powerbase1[0],
412 &powerBase1[0], 418 &writeval[0]);
413 &writeVal[0]);
414 419
415 _rtl8723ae_write_ofdm_power_reg(hw, index, &writeVal[0]); 420 _rtl8723e_write_ofdm_power_reg(hw, index, &writeval[0]);
416 } 421 }
417} 422}
418 423
419static bool _rtl8723ae_phy_rf6052_config_parafile(struct ieee80211_hw *hw) 424bool rtl8723e_phy_rf6052_config(struct ieee80211_hw *hw)
420{ 425{
421 struct rtl_priv *rtlpriv = rtl_priv(hw); 426 struct rtl_priv *rtlpriv = rtl_priv(hw);
422 struct rtl_phy *rtlphy = &(rtlpriv->phy); 427 struct rtl_phy *rtlphy = &rtlpriv->phy;
428
429 if (rtlphy->rf_type == RF_1T1R)
430 rtlphy->num_total_rfpath = 1;
431 else
432 rtlphy->num_total_rfpath = 2;
433
434 return _rtl8723e_phy_rf6052_config_parafile(hw);
435}
436
437static bool _rtl8723e_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
438{
439 struct rtl_priv *rtlpriv = rtl_priv(hw);
440 struct rtl_phy *rtlphy = &rtlpriv->phy;
423 u32 u4_regvalue = 0; 441 u32 u4_regvalue = 0;
424 u8 rfpath; 442 u8 rfpath;
425 bool rtstatus = true; 443 bool rtstatus = true;
@@ -457,11 +475,12 @@ static bool _rtl8723ae_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
457 475
458 switch (rfpath) { 476 switch (rfpath) {
459 case RF90_PATH_A: 477 case RF90_PATH_A:
460 rtstatus = rtl8723ae_phy_config_rf_with_headerfile(hw, 478 rtstatus = rtl8723e_phy_config_rf_with_headerfile(hw,
461 (enum radio_path)rfpath); 479 (enum radio_path)rfpath);
462 break; 480 break;
463 case RF90_PATH_B: 481 case RF90_PATH_B:
464 rtstatus = rtl8723ae_phy_config_rf_with_headerfile(hw, 482 rtstatus =
483 rtl8723e_phy_config_rf_with_headerfile(hw,
465 (enum radio_path)rfpath); 484 (enum radio_path)rfpath);
466 break; 485 break;
467 case RF90_PATH_C: 486 case RF90_PATH_C:
@@ -469,6 +488,7 @@ static bool _rtl8723ae_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
469 case RF90_PATH_D: 488 case RF90_PATH_D:
470 break; 489 break;
471 } 490 }
491
472 switch (rfpath) { 492 switch (rfpath) {
473 case RF90_PATH_A: 493 case RF90_PATH_A:
474 case RF90_PATH_C: 494 case RF90_PATH_C:
@@ -481,25 +501,14 @@ static bool _rtl8723ae_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
481 BRFSI_RFENV << 16, u4_regvalue); 501 BRFSI_RFENV << 16, u4_regvalue);
482 break; 502 break;
483 } 503 }
504
484 if (rtstatus != true) { 505 if (rtstatus != true) {
485 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 506 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
486 "Radio[%d] Fail!!", rfpath); 507 "Radio[%d] Fail!!", rfpath);
487 return false; 508 return false;
488 } 509 }
489 } 510 }
490 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "<---\n");
491 return rtstatus;
492}
493
494bool rtl8723ae_phy_rf6052_config(struct ieee80211_hw *hw)
495{
496 struct rtl_priv *rtlpriv = rtl_priv(hw);
497 struct rtl_phy *rtlphy = &(rtlpriv->phy);
498 511
499 if (rtlphy->rf_type == RF_1T1R) 512 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "\n");
500 rtlphy->num_total_rfpath = 1; 513 return rtstatus;
501 else
502 rtlphy->num_total_rfpath = 2;
503
504 return _rtl8723ae_phy_rf6052_config_parafile(hw);
505} 514}
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/rf.h b/drivers/net/wireless/rtlwifi/rtl8723ae/rf.h
index 57f1933ee663..f3f45b16361f 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/rf.h
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/rf.h
@@ -11,10 +11,6 @@
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details. 12 * more details.
13 * 13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the 14 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE. 15 * file called LICENSE.
20 * 16 *
@@ -31,12 +27,14 @@
31#define __RTL8723E_RF_H__ 27#define __RTL8723E_RF_H__
32 28
33#define RF6052_MAX_TX_PWR 0x3F 29#define RF6052_MAX_TX_PWR 0x3F
30#define RF6052_MAX_REG 0x3F
34 31
35void rtl8723ae_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth); 32void rtl8723e_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw,
36void rtl8723ae_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw, 33 u8 bandwidth);
37 u8 *ppowerlevel); 34void rtl8723e_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
38void rtl8723ae_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw, 35 u8 *ppowerlevel);
39 u8 *ppowerlevel, u8 channel); 36void rtl8723e_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
40bool rtl8723ae_phy_rf6052_config(struct ieee80211_hw *hw); 37 u8 *ppowerlevel, u8 channel);
38bool rtl8723e_phy_rf6052_config(struct ieee80211_hw *hw);
41 39
42#endif 40#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/sw.c b/drivers/net/wireless/rtlwifi/rtl8723ae/sw.c
index 73cba1eec8cf..d8f8cc49a430 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/sw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/sw.c
@@ -11,10 +11,6 @@
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details. 12 * more details.
13 * 13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the 14 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE. 15 * file called LICENSE.
20 * 16 *
@@ -28,34 +24,35 @@
28 *****************************************************************************/ 24 *****************************************************************************/
29 25
30#include "../wifi.h" 26#include "../wifi.h"
31#include <linux/vmalloc.h>
32#include <linux/module.h>
33
34#include "../core.h" 27#include "../core.h"
35#include "../pci.h" 28#include "../pci.h"
36#include "../base.h"
37#include "reg.h" 29#include "reg.h"
38#include "def.h" 30#include "def.h"
39#include "phy.h" 31#include "phy.h"
40#include "../rtl8723com/phy_common.h"
41#include "dm.h" 32#include "dm.h"
42#include "hw.h"
43#include "fw.h" 33#include "fw.h"
44#include "../rtl8723com/fw_common.h" 34#include "../rtl8723com/fw_common.h"
35#include "hw.h"
45#include "sw.h" 36#include "sw.h"
46#include "trx.h" 37#include "trx.h"
47#include "led.h" 38#include "led.h"
48#include "table.h" 39#include "table.h"
49#include "hal_btc.h" 40#include "hal_btc.h"
41#include "../btcoexist/rtl_btc.h"
42#include "../rtl8723com/phy_common.h"
50 43
51static void rtl8723ae_init_aspm_vars(struct ieee80211_hw *hw) 44#include <linux/vmalloc.h>
45#include <linux/module.h>
46
47static void rtl8723e_init_aspm_vars(struct ieee80211_hw *hw)
52{ 48{
53 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 49 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
54 50
55 /*close ASPM for AMD defaultly */ 51 /*close ASPM for AMD defaultly */
56 rtlpci->const_amdpci_aspm = 0; 52 rtlpci->const_amdpci_aspm = 0;
57 53
58 /* ASPM PS mode. 54 /**
55 * ASPM PS mode.
59 * 0 - Disable ASPM, 56 * 0 - Disable ASPM,
60 * 1 - Enable ASPM without Clock Req, 57 * 1 - Enable ASPM without Clock Req,
61 * 2 - Enable ASPM with Clock Req, 58 * 2 - Enable ASPM with Clock Req,
@@ -71,7 +68,8 @@ static void rtl8723ae_init_aspm_vars(struct ieee80211_hw *hw)
71 /*Setting for PCI-E bridge */ 68 /*Setting for PCI-E bridge */
72 rtlpci->const_hostpci_aspm_setting = 0x02; 69 rtlpci->const_hostpci_aspm_setting = 0x02;
73 70
74 /* In Hw/Sw Radio Off situation. 71 /**
72 * In Hw/Sw Radio Off situation.
75 * 0 - Default, 73 * 0 - Default,
76 * 1 - From ASPM setting without low Mac Pwr, 74 * 1 - From ASPM setting without low Mac Pwr,
77 * 2 - From ASPM setting with low Mac Pwr, 75 * 2 - From ASPM setting with low Mac Pwr,
@@ -80,7 +78,8 @@ static void rtl8723ae_init_aspm_vars(struct ieee80211_hw *hw)
80 */ 78 */
81 rtlpci->const_hwsw_rfoff_d3 = 0; 79 rtlpci->const_hwsw_rfoff_d3 = 0;
82 80
83 /* This setting works for those device with 81 /**
82 * This setting works for those device with
84 * backdoor ASPM setting such as EPHY setting. 83 * backdoor ASPM setting such as EPHY setting.
85 * 0 - Not support ASPM, 84 * 0 - Not support ASPM,
86 * 1 - Support ASPM, 85 * 1 - Support ASPM,
@@ -89,14 +88,17 @@ static void rtl8723ae_init_aspm_vars(struct ieee80211_hw *hw)
89 rtlpci->const_support_pciaspm = 1; 88 rtlpci->const_support_pciaspm = 1;
90} 89}
91 90
92int rtl8723ae_init_sw_vars(struct ieee80211_hw *hw) 91int rtl8723e_init_sw_vars(struct ieee80211_hw *hw)
93{ 92{
94 struct rtl_priv *rtlpriv = rtl_priv(hw); 93 struct rtl_priv *rtlpriv = rtl_priv(hw);
95 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 94 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
96 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 95 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
97 int err; 96 int err = 0;
97
98 rtl8723e_bt_reg_init(hw);
99
100 rtlpriv->btcoexist.btc_ops = rtl_btc_get_ops_pointer();
98 101
99 rtl8723ae_bt_reg_init(hw);
100 rtlpriv->dm.dm_initialgain_enable = 1; 102 rtlpriv->dm.dm_initialgain_enable = 1;
101 rtlpriv->dm.dm_flag = 0; 103 rtlpriv->dm.dm_flag = 0;
102 rtlpriv->dm.disable_framebursting = 0; 104 rtlpriv->dm.disable_framebursting = 0;
@@ -138,7 +140,9 @@ int rtl8723ae_init_sw_vars(struct ieee80211_hw *hw)
138 PHIMR_PSTIMEOUT | 140 PHIMR_PSTIMEOUT |
139 0); 141 0);
140 142
141 rtlpci->irq_mask[1] = (u32)(PHIMR_RXFOVW | 0); 143 rtlpci->irq_mask[1] =
144 (u32)(PHIMR_RXFOVW |
145 0);
142 146
143 /* for debug level */ 147 /* for debug level */
144 rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug; 148 rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
@@ -146,12 +150,11 @@ int rtl8723ae_init_sw_vars(struct ieee80211_hw *hw)
146 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps; 150 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
147 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps; 151 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
148 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps; 152 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
153 if (rtlpriv->cfg->mod_params->disable_watchdog)
154 pr_info("watchdog disabled\n");
149 rtlpriv->psc.reg_fwctrl_lps = 3; 155 rtlpriv->psc.reg_fwctrl_lps = 3;
150 rtlpriv->psc.reg_max_lps_awakeintvl = 5; 156 rtlpriv->psc.reg_max_lps_awakeintvl = 5;
151 /* for ASPM, you can close aspm through 157 rtl8723e_init_aspm_vars(hw);
152 * set const_support_pciaspm = 0
153 */
154 rtl8723ae_init_aspm_vars(hw);
155 158
156 if (rtlpriv->psc.reg_fwctrl_lps == 1) 159 if (rtlpriv->psc.reg_fwctrl_lps == 1)
157 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE; 160 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
@@ -186,7 +189,7 @@ int rtl8723ae_init_sw_vars(struct ieee80211_hw *hw)
186 return 0; 189 return 0;
187} 190}
188 191
189void rtl8723ae_deinit_sw_vars(struct ieee80211_hw *hw) 192void rtl8723e_deinit_sw_vars(struct ieee80211_hw *hw)
190{ 193{
191 struct rtl_priv *rtlpriv = rtl_priv(hw); 194 struct rtl_priv *rtlpriv = rtl_priv(hw);
192 195
@@ -196,59 +199,69 @@ void rtl8723ae_deinit_sw_vars(struct ieee80211_hw *hw)
196 } 199 }
197} 200}
198 201
199static bool is_fw_header(struct rtl92c_firmware_header *hdr) 202/* get bt coexist status */
203bool rtl8723e_get_btc_status(void)
204{
205 return true;
206}
207
208static bool is_fw_header(struct rtl8723e_firmware_header *hdr)
200{ 209{
201 return (hdr->signature & 0xfff0) == 0x2300; 210 return (hdr->signature & 0xfff0) == 0x2300;
202} 211}
203 212
204static struct rtl_hal_ops rtl8723ae_hal_ops = { 213static struct rtl_hal_ops rtl8723e_hal_ops = {
205 .init_sw_vars = rtl8723ae_init_sw_vars, 214 .init_sw_vars = rtl8723e_init_sw_vars,
206 .deinit_sw_vars = rtl8723ae_deinit_sw_vars, 215 .deinit_sw_vars = rtl8723e_deinit_sw_vars,
207 .read_eeprom_info = rtl8723ae_read_eeprom_info, 216 .read_eeprom_info = rtl8723e_read_eeprom_info,
208 .interrupt_recognized = rtl8723ae_interrupt_recognized, 217 .interrupt_recognized = rtl8723e_interrupt_recognized,
209 .hw_init = rtl8723ae_hw_init, 218 .hw_init = rtl8723e_hw_init,
210 .hw_disable = rtl8723ae_card_disable, 219 .hw_disable = rtl8723e_card_disable,
211 .hw_suspend = rtl8723ae_suspend, 220 .hw_suspend = rtl8723e_suspend,
212 .hw_resume = rtl8723ae_resume, 221 .hw_resume = rtl8723e_resume,
213 .enable_interrupt = rtl8723ae_enable_interrupt, 222 .enable_interrupt = rtl8723e_enable_interrupt,
214 .disable_interrupt = rtl8723ae_disable_interrupt, 223 .disable_interrupt = rtl8723e_disable_interrupt,
215 .set_network_type = rtl8723ae_set_network_type, 224 .set_network_type = rtl8723e_set_network_type,
216 .set_chk_bssid = rtl8723ae_set_check_bssid, 225 .set_chk_bssid = rtl8723e_set_check_bssid,
217 .set_qos = rtl8723ae_set_qos, 226 .set_qos = rtl8723e_set_qos,
218 .set_bcn_reg = rtl8723ae_set_beacon_related_registers, 227 .set_bcn_reg = rtl8723e_set_beacon_related_registers,
219 .set_bcn_intv = rtl8723ae_set_beacon_interval, 228 .set_bcn_intv = rtl8723e_set_beacon_interval,
220 .update_interrupt_mask = rtl8723ae_update_interrupt_mask, 229 .update_interrupt_mask = rtl8723e_update_interrupt_mask,
221 .get_hw_reg = rtl8723ae_get_hw_reg, 230 .get_hw_reg = rtl8723e_get_hw_reg,
222 .set_hw_reg = rtl8723ae_set_hw_reg, 231 .set_hw_reg = rtl8723e_set_hw_reg,
223 .update_rate_tbl = rtl8723ae_update_hal_rate_tbl, 232 .update_rate_tbl = rtl8723e_update_hal_rate_tbl,
224 .fill_tx_desc = rtl8723ae_tx_fill_desc, 233 .fill_tx_desc = rtl8723e_tx_fill_desc,
225 .fill_tx_cmddesc = rtl8723ae_tx_fill_cmddesc, 234 .fill_tx_cmddesc = rtl8723e_tx_fill_cmddesc,
226 .query_rx_desc = rtl8723ae_rx_query_desc, 235 .query_rx_desc = rtl8723e_rx_query_desc,
227 .set_channel_access = rtl8723ae_update_channel_access_setting, 236 .set_channel_access = rtl8723e_update_channel_access_setting,
228 .radio_onoff_checking = rtl8723ae_gpio_radio_on_off_checking, 237 .radio_onoff_checking = rtl8723e_gpio_radio_on_off_checking,
229 .set_bw_mode = rtl8723ae_phy_set_bw_mode, 238 .set_bw_mode = rtl8723e_phy_set_bw_mode,
230 .switch_channel = rtl8723ae_phy_sw_chnl, 239 .switch_channel = rtl8723e_phy_sw_chnl,
231 .dm_watchdog = rtl8723ae_dm_watchdog, 240 .dm_watchdog = rtl8723e_dm_watchdog,
232 .scan_operation_backup = rtl_phy_scan_operation_backup, 241 .scan_operation_backup = rtl8723e_phy_scan_operation_backup,
233 .set_rf_power_state = rtl8723ae_phy_set_rf_power_state, 242 .set_rf_power_state = rtl8723e_phy_set_rf_power_state,
234 .led_control = rtl8723ae_led_control, 243 .led_control = rtl8723e_led_control,
235 .set_desc = rtl8723ae_set_desc, 244 .set_desc = rtl8723e_set_desc,
236 .get_desc = rtl8723ae_get_desc, 245 .get_desc = rtl8723e_get_desc,
237 .tx_polling = rtl8723ae_tx_polling, 246 .is_tx_desc_closed = rtl8723e_is_tx_desc_closed,
238 .enable_hw_sec = rtl8723ae_enable_hw_security_config, 247 .tx_polling = rtl8723e_tx_polling,
239 .set_key = rtl8723ae_set_key, 248 .enable_hw_sec = rtl8723e_enable_hw_security_config,
240 .init_sw_leds = rtl8723ae_init_sw_leds, 249 .set_key = rtl8723e_set_key,
250 .init_sw_leds = rtl8723e_init_sw_leds,
241 .get_bbreg = rtl8723_phy_query_bb_reg, 251 .get_bbreg = rtl8723_phy_query_bb_reg,
242 .set_bbreg = rtl8723_phy_set_bb_reg, 252 .set_bbreg = rtl8723_phy_set_bb_reg,
243 .get_rfreg = rtl8723ae_phy_query_rf_reg, 253 .get_rfreg = rtl8723e_phy_query_rf_reg,
244 .set_rfreg = rtl8723ae_phy_set_rf_reg, 254 .set_rfreg = rtl8723e_phy_set_rf_reg,
245 .c2h_command_handle = rtl_8723e_c2h_command_handle, 255 .c2h_command_handle = rtl_8723e_c2h_command_handle,
246 .bt_wifi_media_status_notify = rtl_8723e_bt_wifi_media_status_notify, 256 .bt_wifi_media_status_notify = rtl_8723e_bt_wifi_media_status_notify,
247 .bt_coex_off_before_lps = rtl8723ae_bt_coex_off_before_lps, 257 .bt_coex_off_before_lps =
258 rtl8723e_dm_bt_turn_off_bt_coexist_before_enter_lps,
259 .get_btc_status = rtl8723e_get_btc_status,
260 .rx_command_packet = rtl8723e_rx_command_packet,
248 .is_fw_header = is_fw_header, 261 .is_fw_header = is_fw_header,
249}; 262};
250 263
251static struct rtl_mod_params rtl8723ae_mod_params = { 264static struct rtl_mod_params rtl8723e_mod_params = {
252 .sw_crypto = false, 265 .sw_crypto = false,
253 .inactiveps = true, 266 .inactiveps = true,
254 .swctrl_lps = false, 267 .swctrl_lps = false,
@@ -256,13 +269,13 @@ static struct rtl_mod_params rtl8723ae_mod_params = {
256 .debug = DBG_EMERG, 269 .debug = DBG_EMERG,
257}; 270};
258 271
259static struct rtl_hal_cfg rtl8723ae_hal_cfg = { 272static struct rtl_hal_cfg rtl8723e_hal_cfg = {
260 .bar_id = 2, 273 .bar_id = 2,
261 .write_readback = true, 274 .write_readback = true,
262 .name = "rtl8723ae_pci", 275 .name = "rtl8723e_pci",
263 .fw_name = "rtlwifi/rtl8723fw.bin", 276 .fw_name = "rtlwifi/rtl8723efw.bin",
264 .ops = &rtl8723ae_hal_ops, 277 .ops = &rtl8723e_hal_ops,
265 .mod_params = &rtl8723ae_mod_params, 278 .mod_params = &rtl8723e_mod_params,
266 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL, 279 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
267 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN, 280 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
268 .maps[SYS_CLK] = REG_SYS_CLKR, 281 .maps[SYS_CLK] = REG_SYS_CLKR,
@@ -271,6 +284,8 @@ static struct rtl_hal_cfg rtl8723ae_hal_cfg = {
271 .maps[MAC_RCR_ACRC32] = ACRC32, 284 .maps[MAC_RCR_ACRC32] = ACRC32,
272 .maps[MAC_RCR_ACF] = ACF, 285 .maps[MAC_RCR_ACF] = ACF,
273 .maps[MAC_RCR_AAP] = AAP, 286 .maps[MAC_RCR_AAP] = AAP,
287 .maps[MAC_HIMR] = REG_HIMR,
288 .maps[MAC_HIMRE] = REG_HIMRE,
274 .maps[EFUSE_TEST] = REG_EFUSE_TEST, 289 .maps[EFUSE_TEST] = REG_EFUSE_TEST,
275 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL, 290 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
276 .maps[EFUSE_CLK] = 0, 291 .maps[EFUSE_CLK] = 0,
@@ -328,62 +343,63 @@ static struct rtl_hal_cfg rtl8723ae_hal_cfg = {
328 .maps[RTL_IMR_VIDOK] = PHIMR_VIDOK, 343 .maps[RTL_IMR_VIDOK] = PHIMR_VIDOK,
329 .maps[RTL_IMR_VODOK] = PHIMR_VODOK, 344 .maps[RTL_IMR_VODOK] = PHIMR_VODOK,
330 .maps[RTL_IMR_ROK] = PHIMR_ROK, 345 .maps[RTL_IMR_ROK] = PHIMR_ROK,
331 .maps[RTL_IBSS_INT_MASKS] = (PHIMR_BCNDMAINT0 | 346 .maps[RTL_IBSS_INT_MASKS] =
332 PHIMR_TXBCNOK | PHIMR_TXBCNERR), 347 (PHIMR_BCNDMAINT0 | PHIMR_TXBCNOK | PHIMR_TXBCNERR),
333 .maps[RTL_IMR_C2HCMD] = PHIMR_C2HCMD, 348 .maps[RTL_IMR_C2HCMD] = PHIMR_C2HCMD,
334 349
335 350
336 .maps[RTL_RC_CCK_RATE1M] = DESC92_RATE1M, 351 .maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,
337 .maps[RTL_RC_CCK_RATE2M] = DESC92_RATE2M, 352 .maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M,
338 .maps[RTL_RC_CCK_RATE5_5M] = DESC92_RATE5_5M, 353 .maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M,
339 .maps[RTL_RC_CCK_RATE11M] = DESC92_RATE11M, 354 .maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M,
340 .maps[RTL_RC_OFDM_RATE6M] = DESC92_RATE6M, 355 .maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M,
341 .maps[RTL_RC_OFDM_RATE9M] = DESC92_RATE9M, 356 .maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M,
342 .maps[RTL_RC_OFDM_RATE12M] = DESC92_RATE12M, 357 .maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M,
343 .maps[RTL_RC_OFDM_RATE18M] = DESC92_RATE18M, 358 .maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M,
344 .maps[RTL_RC_OFDM_RATE24M] = DESC92_RATE24M, 359 .maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M,
345 .maps[RTL_RC_OFDM_RATE36M] = DESC92_RATE36M, 360 .maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M,
346 .maps[RTL_RC_OFDM_RATE48M] = DESC92_RATE48M, 361 .maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M,
347 .maps[RTL_RC_OFDM_RATE54M] = DESC92_RATE54M, 362 .maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M,
348 363
349 .maps[RTL_RC_HT_RATEMCS7] = DESC92_RATEMCS7, 364 .maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7,
350 .maps[RTL_RC_HT_RATEMCS15] = DESC92_RATEMCS15, 365 .maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,
351}; 366};
352 367
353static struct pci_device_id rtl8723ae_pci_ids[] = { 368static struct pci_device_id rtl8723e_pci_ids[] = {
354 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8723, rtl8723ae_hal_cfg)}, 369 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8723, rtl8723e_hal_cfg)},
355 {}, 370 {},
356}; 371};
357 372
358MODULE_DEVICE_TABLE(pci, rtl8723ae_pci_ids); 373MODULE_DEVICE_TABLE(pci, rtl8723e_pci_ids);
359 374
360MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>"); 375MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
361MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>"); 376MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
362MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
363MODULE_LICENSE("GPL"); 377MODULE_LICENSE("GPL");
364MODULE_DESCRIPTION("Realtek 8723E 802.11n PCI wireless"); 378MODULE_DESCRIPTION("Realtek 8723E 802.11n PCI wireless");
365MODULE_FIRMWARE("rtlwifi/rtl8723fw.bin"); 379MODULE_FIRMWARE("rtlwifi/rtl8723efw.bin");
366MODULE_FIRMWARE("rtlwifi/rtl8723fw_B.bin"); 380
367 381module_param_named(swenc, rtl8723e_mod_params.sw_crypto, bool, 0444);
368module_param_named(swenc, rtl8723ae_mod_params.sw_crypto, bool, 0444); 382module_param_named(debug, rtl8723e_mod_params.debug, int, 0444);
369module_param_named(debug, rtl8723ae_mod_params.debug, int, 0444); 383module_param_named(ips, rtl8723e_mod_params.inactiveps, bool, 0444);
370module_param_named(ips, rtl8723ae_mod_params.inactiveps, bool, 0444); 384module_param_named(swlps, rtl8723e_mod_params.swctrl_lps, bool, 0444);
371module_param_named(swlps, rtl8723ae_mod_params.swctrl_lps, bool, 0444); 385module_param_named(fwlps, rtl8723e_mod_params.fwctrl_lps, bool, 0444);
372module_param_named(fwlps, rtl8723ae_mod_params.fwctrl_lps, bool, 0444); 386module_param_named(disable_watchdog, rtl8723e_mod_params.disable_watchdog,
387 bool, 0444);
373MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n"); 388MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
374MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n"); 389MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
375MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n"); 390MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
376MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n"); 391MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
377MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)"); 392MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");
393MODULE_PARM_DESC(disable_watchdog, "Set to 1 to disable the watchdog (default 0)\n");
378 394
379static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume); 395static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
380 396
381static struct pci_driver rtl8723ae_driver = { 397static struct pci_driver rtl8723e_driver = {
382 .name = KBUILD_MODNAME, 398 .name = KBUILD_MODNAME,
383 .id_table = rtl8723ae_pci_ids, 399 .id_table = rtl8723e_pci_ids,
384 .probe = rtl_pci_probe, 400 .probe = rtl_pci_probe,
385 .remove = rtl_pci_disconnect, 401 .remove = rtl_pci_disconnect,
386 .driver.pm = &rtlwifi_pm_ops, 402 .driver.pm = &rtlwifi_pm_ops,
387}; 403};
388 404
389module_pci_driver(rtl8723ae_driver); 405module_pci_driver(rtl8723e_driver);
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/sw.h b/drivers/net/wireless/rtlwifi/rtl8723ae/sw.h
index fc4fde5e3eb5..46478780d262 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/sw.h
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/sw.h
@@ -11,10 +11,6 @@
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details. 12 * more details.
13 * 13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the 14 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE. 15 * file called LICENSE.
20 * 16 *
@@ -30,8 +26,10 @@
30#ifndef __RTL8723E_SW_H__ 26#ifndef __RTL8723E_SW_H__
31#define __RTL8723E_SW_H__ 27#define __RTL8723E_SW_H__
32 28
33int rtl8723ae_init_sw_vars(struct ieee80211_hw *hw); 29int rtl8723e_init_sw_vars(struct ieee80211_hw *hw);
34void rtl8723ae_deinit_sw_vars(struct ieee80211_hw *hw); 30void rtl8723e_deinit_sw_vars(struct ieee80211_hw *hw);
35void rtl8723ae_init_var_map(struct ieee80211_hw *hw); 31void rtl8723e_init_var_map(struct ieee80211_hw *hw);
32bool rtl8723e_get_btc_status(void);
33
36 34
37#endif 35#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/table.c b/drivers/net/wireless/rtlwifi/rtl8723ae/table.c
index 9b0b50cc4ade..61e86045f15c 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/table.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/table.c
@@ -11,10 +11,6 @@
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details. 12 * more details.
13 * 13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the 14 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE. 15 * file called LICENSE.
20 * 16 *
@@ -335,7 +331,7 @@ u32 RTL8723EPHY_REG_ARRAY_PG[RTL8723E_PHY_REG_ARRAY_PGLENGTH] = {
335 0x868, 0xffffffff, 0x00000000, 331 0x868, 0xffffffff, 0x00000000,
336}; 332};
337 333
338u32 RTL8723E_RADIOA_1TARRAY[Rtl8723ERADIOA_1TARRAYLENGTH] = { 334u32 RTL8723E_RADIOA_1TARRAY[RTL8723ERADIOA_1TARRAYLENGTH] = {
339 0x000, 0x00030159, 335 0x000, 0x00030159,
340 0x001, 0x00031284, 336 0x001, 0x00031284,
341 0x002, 0x00098000, 337 0x002, 0x00098000,
@@ -479,12 +475,10 @@ u32 RTL8723E_RADIOA_1TARRAY[Rtl8723ERADIOA_1TARRAYLENGTH] = {
479 0x000, 0x00030159, 475 0x000, 0x00030159,
480}; 476};
481 477
482
483u32 RTL8723E_RADIOB_1TARRAY[RTL8723E_RADIOB_1TARRAYLENGTH] = { 478u32 RTL8723E_RADIOB_1TARRAY[RTL8723E_RADIOB_1TARRAYLENGTH] = {
484 0x0, 479 0x0,
485}; 480};
486 481
487
488u32 RTL8723EMAC_ARRAY[RTL8723E_MACARRAYLENGTH] = { 482u32 RTL8723EMAC_ARRAY[RTL8723E_MACARRAYLENGTH] = {
489 0x420, 0x00000080, 483 0x420, 0x00000080,
490 0x423, 0x00000000, 484 0x423, 0x00000000,
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/table.h b/drivers/net/wireless/rtlwifi/rtl8723ae/table.h
index f5ce71375c20..57a548ceba7d 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/table.h
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/table.h
@@ -11,10 +11,6 @@
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details. 12 * more details.
13 * 13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the 14 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE. 15 * file called LICENSE.
20 * 16 *
@@ -38,8 +34,8 @@
38extern u32 RTL8723EPHY_REG_1TARRAY[RTL8723E_PHY_REG_1TARRAY_LENGTH]; 34extern u32 RTL8723EPHY_REG_1TARRAY[RTL8723E_PHY_REG_1TARRAY_LENGTH];
39#define RTL8723E_PHY_REG_ARRAY_PGLENGTH 336 35#define RTL8723E_PHY_REG_ARRAY_PGLENGTH 336
40extern u32 RTL8723EPHY_REG_ARRAY_PG[RTL8723E_PHY_REG_ARRAY_PGLENGTH]; 36extern u32 RTL8723EPHY_REG_ARRAY_PG[RTL8723E_PHY_REG_ARRAY_PGLENGTH];
41#define Rtl8723ERADIOA_1TARRAYLENGTH 282 37#define RTL8723ERADIOA_1TARRAYLENGTH 282
42extern u32 RTL8723E_RADIOA_1TARRAY[Rtl8723ERADIOA_1TARRAYLENGTH]; 38extern u32 RTL8723E_RADIOA_1TARRAY[RTL8723ERADIOA_1TARRAYLENGTH];
43#define RTL8723E_RADIOB_1TARRAYLENGTH 1 39#define RTL8723E_RADIOB_1TARRAYLENGTH 1
44extern u32 RTL8723E_RADIOB_1TARRAY[RTL8723E_RADIOB_1TARRAYLENGTH]; 40extern u32 RTL8723E_RADIOB_1TARRAY[RTL8723E_RADIOB_1TARRAYLENGTH];
45#define RTL8723E_MACARRAYLENGTH 172 41#define RTL8723E_MACARRAYLENGTH 172
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/trx.c b/drivers/net/wireless/rtlwifi/rtl8723ae/trx.c
index 10b7577b6ae5..ca84150b3b3e 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/trx.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/trx.c
@@ -11,10 +11,6 @@
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details. 12 * more details.
13 * 13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the 14 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE. 15 * file called LICENSE.
20 * 16 *
@@ -37,7 +33,7 @@
37#include "trx.h" 33#include "trx.h"
38#include "led.h" 34#include "led.h"
39 35
40static u8 _rtl8723ae_map_hwqueue_to_fwqueue(struct sk_buff *skb, u8 hw_queue) 36static u8 _rtl8723e_map_hwqueue_to_fwqueue(struct sk_buff *skb, u8 hw_queue)
41{ 37{
42 __le16 fc = rtl_get_fc(skb); 38 __le16 fc = rtl_get_fc(skb);
43 39
@@ -49,16 +45,174 @@ static u8 _rtl8723ae_map_hwqueue_to_fwqueue(struct sk_buff *skb, u8 hw_queue)
49 return skb->priority; 45 return skb->priority;
50} 46}
51 47
52static void _rtl8723ae_query_rxphystatus(struct ieee80211_hw *hw, 48/* mac80211's rate_idx is like this:
53 struct rtl_stats *pstatus, u8 *pdesc, 49 *
54 struct rx_fwinfo_8723e *p_drvinfo, 50 * 2.4G band:rx_status->band == IEEE80211_BAND_2GHZ
55 bool bpacket_match_bssid, 51 *
56 bool bpacket_toself, bool packet_beacon) 52 * B/G rate:
53 * (rx_status->flag & RX_FLAG_HT) = 0,
54 * DESC92C_RATE1M-->DESC92C_RATE54M ==> idx is 0-->11,
55 *
56 * N rate:
57 * (rx_status->flag & RX_FLAG_HT) = 1,
58 * DESC92C_RATEMCS0-->DESC92C_RATEMCS15 ==> idx is 0-->15
59 *
60 * 5G band:rx_status->band == IEEE80211_BAND_5GHZ
61 * A rate:
62 * (rx_status->flag & RX_FLAG_HT) = 0,
63 * DESC92C_RATE6M-->DESC92C_RATE54M ==> idx is 0-->7,
64 *
65 * N rate:
66 * (rx_status->flag & RX_FLAG_HT) = 1,
67 * DESC92C_RATEMCS0-->DESC92C_RATEMCS15 ==> idx is 0-->15
68 */
69static int _rtl8723e_rate_mapping(struct ieee80211_hw *hw,
70 bool isht, u8 desc_rate)
71{
72 int rate_idx;
73
74 if (!isht) {
75 if (IEEE80211_BAND_2GHZ == hw->conf.chandef.chan->band) {
76 switch (desc_rate) {
77 case DESC92C_RATE1M:
78 rate_idx = 0;
79 break;
80 case DESC92C_RATE2M:
81 rate_idx = 1;
82 break;
83 case DESC92C_RATE5_5M:
84 rate_idx = 2;
85 break;
86 case DESC92C_RATE11M:
87 rate_idx = 3;
88 break;
89 case DESC92C_RATE6M:
90 rate_idx = 4;
91 break;
92 case DESC92C_RATE9M:
93 rate_idx = 5;
94 break;
95 case DESC92C_RATE12M:
96 rate_idx = 6;
97 break;
98 case DESC92C_RATE18M:
99 rate_idx = 7;
100 break;
101 case DESC92C_RATE24M:
102 rate_idx = 8;
103 break;
104 case DESC92C_RATE36M:
105 rate_idx = 9;
106 break;
107 case DESC92C_RATE48M:
108 rate_idx = 10;
109 break;
110 case DESC92C_RATE54M:
111 rate_idx = 11;
112 break;
113 default:
114 rate_idx = 0;
115 break;
116 }
117 } else {
118 switch (desc_rate) {
119 case DESC92C_RATE6M:
120 rate_idx = 0;
121 break;
122 case DESC92C_RATE9M:
123 rate_idx = 1;
124 break;
125 case DESC92C_RATE12M:
126 rate_idx = 2;
127 break;
128 case DESC92C_RATE18M:
129 rate_idx = 3;
130 break;
131 case DESC92C_RATE24M:
132 rate_idx = 4;
133 break;
134 case DESC92C_RATE36M:
135 rate_idx = 5;
136 break;
137 case DESC92C_RATE48M:
138 rate_idx = 6;
139 break;
140 case DESC92C_RATE54M:
141 rate_idx = 7;
142 break;
143 default:
144 rate_idx = 0;
145 break;
146 }
147 }
148 } else {
149 switch (desc_rate) {
150 case DESC92C_RATEMCS0:
151 rate_idx = 0;
152 break;
153 case DESC92C_RATEMCS1:
154 rate_idx = 1;
155 break;
156 case DESC92C_RATEMCS2:
157 rate_idx = 2;
158 break;
159 case DESC92C_RATEMCS3:
160 rate_idx = 3;
161 break;
162 case DESC92C_RATEMCS4:
163 rate_idx = 4;
164 break;
165 case DESC92C_RATEMCS5:
166 rate_idx = 5;
167 break;
168 case DESC92C_RATEMCS6:
169 rate_idx = 6;
170 break;
171 case DESC92C_RATEMCS7:
172 rate_idx = 7;
173 break;
174 case DESC92C_RATEMCS8:
175 rate_idx = 8;
176 break;
177 case DESC92C_RATEMCS9:
178 rate_idx = 9;
179 break;
180 case DESC92C_RATEMCS10:
181 rate_idx = 10;
182 break;
183 case DESC92C_RATEMCS11:
184 rate_idx = 11;
185 break;
186 case DESC92C_RATEMCS12:
187 rate_idx = 12;
188 break;
189 case DESC92C_RATEMCS13:
190 rate_idx = 13;
191 break;
192 case DESC92C_RATEMCS14:
193 rate_idx = 14;
194 break;
195 case DESC92C_RATEMCS15:
196 rate_idx = 15;
197 break;
198 default:
199 rate_idx = 0;
200 break;
201 }
202 }
203 return rate_idx;
204}
205
206static void _rtl8723e_query_rxphystatus(struct ieee80211_hw *hw,
207 struct rtl_stats *pstatus, u8 *pdesc,
208 struct rx_fwinfo_8723e *p_drvinfo,
209 bool bpacket_match_bssid,
210 bool bpacket_toself, bool packet_beacon)
57{ 211{
58 struct rtl_priv *rtlpriv = rtl_priv(hw); 212 struct rtl_priv *rtlpriv = rtl_priv(hw);
59 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv); 213 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
60 struct phy_sts_cck_8723e_t *cck_buf; 214 struct phy_sts_cck_8723e_t *cck_buf;
61 s8 rx_pwr_all, rx_pwr[4]; 215 s8 rx_pwr_all = 0, rx_pwr[4];
62 u8 rf_rx_num = 0, evm, pwdb_all; 216 u8 rf_rx_num = 0, evm, pwdb_all;
63 u8 i, max_spatial_stream; 217 u8 i, max_spatial_stream;
64 u32 rssi, total_rssi = 0; 218 u32 rssi, total_rssi = 0;
@@ -68,8 +222,8 @@ static void _rtl8723ae_query_rxphystatus(struct ieee80211_hw *hw,
68 pstatus->packet_matchbssid = bpacket_match_bssid; 222 pstatus->packet_matchbssid = bpacket_match_bssid;
69 pstatus->packet_toself = bpacket_toself; 223 pstatus->packet_toself = bpacket_toself;
70 pstatus->packet_beacon = packet_beacon; 224 pstatus->packet_beacon = packet_beacon;
71 pstatus->rx_mimo_sig_qual[0] = -1; 225 pstatus->rx_mimo_signalquality[0] = -1;
72 pstatus->rx_mimo_sig_qual[1] = -1; 226 pstatus->rx_mimo_signalquality[1] = -1;
73 227
74 if (is_cck) { 228 if (is_cck) {
75 u8 report, cck_highpwr; 229 u8 report, cck_highpwr;
@@ -77,14 +231,14 @@ static void _rtl8723ae_query_rxphystatus(struct ieee80211_hw *hw,
77 /* CCK Driver info Structure is not the same as OFDM packet. */ 231 /* CCK Driver info Structure is not the same as OFDM packet. */
78 cck_buf = (struct phy_sts_cck_8723e_t *)p_drvinfo; 232 cck_buf = (struct phy_sts_cck_8723e_t *)p_drvinfo;
79 233
80 /* (1)Hardware does not provide RSSI for CCK 234 /* (1)Hardware does not provide RSSI for CCK */
81 * (2)PWDB, Average PWDB cacluated by 235 /* (2)PWDB, Average PWDB cacluated by
82 * hardware (for rate adaptive) 236 * hardware (for rate adaptive)
83 */ 237 */
84 if (ppsc->rfpwr_state == ERFON) 238 if (ppsc->rfpwr_state == ERFON)
85 cck_highpwr = (u8) rtl_get_bbreg(hw, 239 cck_highpwr = (u8)rtl_get_bbreg(hw,
86 RFPGA0_XA_HSSIPARAMETER2, 240 RFPGA0_XA_HSSIPARAMETER2,
87 BIT(9)); 241 BIT(9));
88 else 242 else
89 cck_highpwr = false; 243 cck_highpwr = false;
90 244
@@ -127,8 +281,9 @@ static void _rtl8723ae_query_rxphystatus(struct ieee80211_hw *hw,
127 } 281 }
128 282
129 pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all); 283 pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all);
130 /* CCK gain is smaller than OFDM/MCS gain, 284 /* CCK gain is smaller than OFDM/MCS gain, */
131 * so we add gain diff. From experience, the val is 6 285 /* so we add gain diff by experiences,
286 * the val is 6
132 */ 287 */
133 pwdb_all += 6; 288 pwdb_all += 6;
134 if (pwdb_all > 100) 289 if (pwdb_all > 100)
@@ -152,9 +307,9 @@ static void _rtl8723ae_query_rxphystatus(struct ieee80211_hw *hw,
152 if (bpacket_match_bssid) { 307 if (bpacket_match_bssid) {
153 u8 sq; 308 u8 sq;
154 309
155 if (pstatus->rx_pwdb_all > 40) { 310 if (pstatus->rx_pwdb_all > 40)
156 sq = 100; 311 sq = 100;
157 } else { 312 else {
158 sq = cck_buf->sq_rpt; 313 sq = cck_buf->sq_rpt;
159 if (sq > 64) 314 if (sq > 64)
160 sq = 0; 315 sq = 0;
@@ -165,8 +320,8 @@ static void _rtl8723ae_query_rxphystatus(struct ieee80211_hw *hw,
165 } 320 }
166 321
167 pstatus->signalquality = sq; 322 pstatus->signalquality = sq;
168 pstatus->rx_mimo_sig_qual[0] = sq; 323 pstatus->rx_mimo_signalquality[0] = sq;
169 pstatus->rx_mimo_sig_qual[1] = -1; 324 pstatus->rx_mimo_signalquality[1] = -1;
170 } 325 }
171 } else { 326 } else {
172 rtlpriv->dm.rfpath_rxenable[0] = 327 rtlpriv->dm.rfpath_rxenable[0] =
@@ -179,18 +334,20 @@ static void _rtl8723ae_query_rxphystatus(struct ieee80211_hw *hw,
179 if (rtlpriv->dm.rfpath_rxenable[i]) 334 if (rtlpriv->dm.rfpath_rxenable[i])
180 rf_rx_num++; 335 rf_rx_num++;
181 336
182 rx_pwr[i] = ((p_drvinfo->gain_trsw[i] & 0x3f)*2) - 110; 337 rx_pwr[i] = ((p_drvinfo->gain_trsw[i] &
338 0x3f) * 2) - 110;
183 339
184 /* Translate DBM to percentage. */ 340 /* Translate DBM to percentage. */
185 rssi = rtl_query_rxpwrpercentage(rx_pwr[i]); 341 rssi = rtl_query_rxpwrpercentage(rx_pwr[i]);
186 total_rssi += rssi; 342 total_rssi += rssi;
187 343
188 /* Get Rx snr value in DB */ 344 /* Get Rx snr value in DB */
189 rtlpriv->stats.rx_snr_db[i] = (p_drvinfo->rxsnr[i] / 2); 345 rtlpriv->stats.rx_snr_db[i] =
346 (long)(p_drvinfo->rxsnr[i] / 2);
190 347
191 /* Record Signal Strength for next packet */ 348 /* Record Signal Strength for next packet */
192 if (bpacket_match_bssid) 349 if (bpacket_match_bssid)
193 pstatus->rx_mimo_signalstrength[i] = (u8) rssi; 350 pstatus->rx_mimo_signalstrength[i] = (u8)rssi;
194 } 351 }
195 352
196 /* (2)PWDB, Average PWDB cacluated by 353 /* (2)PWDB, Average PWDB cacluated by
@@ -204,8 +361,8 @@ static void _rtl8723ae_query_rxphystatus(struct ieee80211_hw *hw,
204 pstatus->recvsignalpower = rx_pwr_all; 361 pstatus->recvsignalpower = rx_pwr_all;
205 362
206 /* (3)EVM of HT rate */ 363 /* (3)EVM of HT rate */
207 if (pstatus->is_ht && pstatus->rate >= DESC92_RATEMCS8 && 364 if (pstatus->is_ht && pstatus->rate >= DESC92C_RATEMCS8 &&
208 pstatus->rate <= DESC92_RATEMCS15) 365 pstatus->rate <= DESC92C_RATEMCS15)
209 max_spatial_stream = 2; 366 max_spatial_stream = 2;
210 else 367 else
211 max_spatial_stream = 1; 368 max_spatial_stream = 1;
@@ -218,8 +375,10 @@ static void _rtl8723ae_query_rxphystatus(struct ieee80211_hw *hw,
218 * spatial stream only 375 * spatial stream only
219 */ 376 */
220 if (i == 0) 377 if (i == 0)
221 pstatus->signalquality = (evm & 0xff); 378 pstatus->signalquality =
222 pstatus->rx_mimo_sig_qual[i] = (evm & 0xff); 379 (u8)(evm & 0xff);
380 pstatus->rx_mimo_signalquality[i] =
381 (u8)(evm & 0xff);
223 } 382 }
224 } 383 }
225 } 384 }
@@ -235,71 +394,73 @@ static void _rtl8723ae_query_rxphystatus(struct ieee80211_hw *hw,
235 total_rssi /= rf_rx_num)); 394 total_rssi /= rf_rx_num));
236} 395}
237 396
238static void _rtl8723ae_translate_rx_signal_stuff(struct ieee80211_hw *hw, 397static void translate_rx_signal_stuff(struct ieee80211_hw *hw,
239 struct sk_buff *skb, struct rtl_stats *pstatus, 398 struct sk_buff *skb,
240 u8 *pdesc, struct rx_fwinfo_8723e *p_drvinfo) 399 struct rtl_stats *pstatus, u8 *pdesc,
400 struct rx_fwinfo_8723e *p_drvinfo)
241{ 401{
242 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 402 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
243 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 403 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
244 struct ieee80211_hdr *hdr; 404 struct ieee80211_hdr *hdr;
245 u8 *tmp_buf; 405 u8 *tmp_buf;
246 u8 *praddr; 406 u8 *praddr;
247 __le16 fc; 407 /*u8 *psaddr;*/
248 u16 type; 408 u16 fc, type;
249 bool packet_matchbssid, packet_toself, packet_beacon = false; 409 bool packet_matchbssid, packet_toself, packet_beacon;
250 410
251 tmp_buf = skb->data + pstatus->rx_drvinfo_size + pstatus->rx_bufshift; 411 tmp_buf = skb->data + pstatus->rx_drvinfo_size + pstatus->rx_bufshift;
252 412
253 hdr = (struct ieee80211_hdr *)tmp_buf; 413 hdr = (struct ieee80211_hdr *)tmp_buf;
254 fc = hdr->frame_control; 414 fc = le16_to_cpu(hdr->frame_control);
255 type = WLAN_FC_GET_TYPE(fc); 415 type = WLAN_FC_GET_TYPE(hdr->frame_control);
256 praddr = hdr->addr1; 416 praddr = hdr->addr1;
257 417
258 packet_matchbssid = 418 packet_matchbssid = ((IEEE80211_FTYPE_CTL != type) &&
259 ((IEEE80211_FTYPE_CTL != type) && 419 (ether_addr_equal(mac->bssid, (fc & IEEE80211_FCTL_TODS) ?
260 ether_addr_equal(mac->bssid, 420 hdr->addr1 : (fc & IEEE80211_FCTL_FROMDS) ?
261 (le16_to_cpu(fc) & IEEE80211_FCTL_TODS) ? hdr->addr1 : 421 hdr->addr2 : hdr->addr3)) &&
262 (le16_to_cpu(fc) & IEEE80211_FCTL_FROMDS) ? hdr->addr2 : 422 (!pstatus->hwerror) &&
263 hdr->addr3) && 423 (!pstatus->crc) && (!pstatus->icv));
264 (!pstatus->hwerror) && (!pstatus->crc) && (!pstatus->icv));
265 424
266 packet_toself = (packet_matchbssid && 425 packet_toself = packet_matchbssid &&
267 ether_addr_equal(praddr, rtlefuse->dev_addr)); 426 (ether_addr_equal(praddr, rtlefuse->dev_addr));
268 427
269 if (ieee80211_is_beacon(fc)) 428 if (ieee80211_is_beacon(hdr->frame_control))
270 packet_beacon = true; 429 packet_beacon = true;
430 else
431 packet_beacon = false;
271 432
272 _rtl8723ae_query_rxphystatus(hw, pstatus, pdesc, p_drvinfo, 433 _rtl8723e_query_rxphystatus(hw, pstatus, pdesc, p_drvinfo,
273 packet_matchbssid, packet_toself, 434 packet_matchbssid, packet_toself,
274 packet_beacon); 435 packet_beacon);
275 436
276 rtl_process_phyinfo(hw, tmp_buf, pstatus); 437 rtl_process_phyinfo(hw, tmp_buf, pstatus);
277} 438}
278 439
279bool rtl8723ae_rx_query_desc(struct ieee80211_hw *hw, 440bool rtl8723e_rx_query_desc(struct ieee80211_hw *hw,
280 struct rtl_stats *status, 441 struct rtl_stats *status,
281 struct ieee80211_rx_status *rx_status, 442 struct ieee80211_rx_status *rx_status,
282 u8 *pdesc, struct sk_buff *skb) 443 u8 *pdesc, struct sk_buff *skb)
283{ 444{
284 struct rx_fwinfo_8723e *p_drvinfo; 445 struct rx_fwinfo_8723e *p_drvinfo;
285 struct ieee80211_hdr *hdr; 446 struct ieee80211_hdr *hdr;
286 u32 phystatus = GET_RX_DESC_PHYST(pdesc); 447 u32 phystatus = GET_RX_DESC_PHYST(pdesc);
287 448
288 status->length = (u16) GET_RX_DESC_PKT_LEN(pdesc); 449 status->length = (u16)GET_RX_DESC_PKT_LEN(pdesc);
289 status->rx_drvinfo_size = (u8) GET_RX_DESC_DRV_INFO_SIZE(pdesc) * 450 status->rx_drvinfo_size = (u8)GET_RX_DESC_DRV_INFO_SIZE(pdesc) *
290 RX_DRV_INFO_SIZE_UNIT; 451 RX_DRV_INFO_SIZE_UNIT;
291 status->rx_bufshift = (u8) (GET_RX_DESC_SHIFT(pdesc) & 0x03); 452 status->rx_bufshift = (u8)(GET_RX_DESC_SHIFT(pdesc) & 0x03);
292 status->icv = (u16) GET_RX_DESC_ICV(pdesc); 453 status->icv = (u16)GET_RX_DESC_ICV(pdesc);
293 status->crc = (u16) GET_RX_DESC_CRC32(pdesc); 454 status->crc = (u16)GET_RX_DESC_CRC32(pdesc);
294 status->hwerror = (status->crc | status->icv); 455 status->hwerror = (status->crc | status->icv);
295 status->decrypted = !GET_RX_DESC_SWDEC(pdesc); 456 status->decrypted = !GET_RX_DESC_SWDEC(pdesc);
296 status->rate = (u8) GET_RX_DESC_RXMCS(pdesc); 457 status->rate = (u8)GET_RX_DESC_RXMCS(pdesc);
297 status->shortpreamble = (u16) GET_RX_DESC_SPLCP(pdesc); 458 status->shortpreamble = (u16)GET_RX_DESC_SPLCP(pdesc);
298 status->isampdu = (bool) (GET_RX_DESC_PAGGR(pdesc) == 1); 459 status->isampdu = (bool)(GET_RX_DESC_PAGGR(pdesc) == 1);
299 status->isfirst_ampdu = (bool) ((GET_RX_DESC_PAGGR(pdesc) == 1) 460 status->isfirst_ampdu = (bool)((GET_RX_DESC_PAGGR(pdesc) == 1) &&
300 && (GET_RX_DESC_FAGGR(pdesc) == 1)); 461 (GET_RX_DESC_FAGGR(pdesc) == 1));
301 status->timestamp_low = GET_RX_DESC_TSFL(pdesc); 462 status->timestamp_low = GET_RX_DESC_TSFL(pdesc);
302 status->rx_is40Mhzpacket = (bool) GET_RX_DESC_BW(pdesc); 463 status->rx_is40Mhzpacket = (bool)GET_RX_DESC_BW(pdesc);
303 status->is_ht = (bool)GET_RX_DESC_RXHT(pdesc); 464 status->is_ht = (bool)GET_RX_DESC_RXHT(pdesc);
304 465
305 status->is_cck = RTL8723E_RX_HAL_IS_CCK_RATE(status->rate); 466 status->is_cck = RTL8723E_RX_HAL_IS_CCK_RATE(status->rate);
@@ -307,6 +468,9 @@ bool rtl8723ae_rx_query_desc(struct ieee80211_hw *hw,
307 rx_status->freq = hw->conf.chandef.chan->center_freq; 468 rx_status->freq = hw->conf.chandef.chan->center_freq;
308 rx_status->band = hw->conf.chandef.chan->band; 469 rx_status->band = hw->conf.chandef.chan->band;
309 470
471 hdr = (struct ieee80211_hdr *)(skb->data + status->rx_drvinfo_size
472 + status->rx_bufshift);
473
310 if (status->crc) 474 if (status->crc)
311 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 475 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
312 476
@@ -320,69 +484,68 @@ bool rtl8723ae_rx_query_desc(struct ieee80211_hw *hw,
320 484
321 /* hw will set status->decrypted true, if it finds the 485 /* hw will set status->decrypted true, if it finds the
322 * frame is open data frame or mgmt frame. 486 * frame is open data frame or mgmt frame.
323 * Thus hw will not decrypt a robust managment frame 487 * So hw will not decryption robust managment frame
324 * for IEEE80211w but still set status->decrypted 488 * for IEEE80211w but still set status->decrypted
325 * true, so here we should set it back to undecrypted 489 * true, so here we should set it back to undecrypted
326 * for IEEE80211w frame, and mac80211 sw will help 490 * for IEEE80211w frame, and mac80211 sw will help
327 * to decrypt it 491 * to decrypt it
328 */ 492 */
329 if (status->decrypted) { 493 if (status->decrypted) {
330 hdr = (struct ieee80211_hdr *)(skb->data +
331 status->rx_drvinfo_size + status->rx_bufshift);
332
333 if (!hdr) { 494 if (!hdr) {
334 /* during testing, hdr could be NULL here */ 495 WARN_ON_ONCE(true);
496 pr_err("decrypted is true but hdr NULL, from skb %p\n",
497 rtl_get_hdr(skb));
335 return false; 498 return false;
336 } 499 }
337 if ((_ieee80211_is_robust_mgmt_frame(hdr)) && 500 if ((!_ieee80211_is_robust_mgmt_frame(hdr)) &&
338 (ieee80211_has_protected(hdr->frame_control))) 501 (ieee80211_has_protected(hdr->frame_control)))
339 rx_status->flag &= ~RX_FLAG_DECRYPTED;
340 else
341 rx_status->flag |= RX_FLAG_DECRYPTED; 502 rx_status->flag |= RX_FLAG_DECRYPTED;
503 else
504 rx_status->flag &= ~RX_FLAG_DECRYPTED;
342 } 505 }
343 506
344 /* rate_idx: index of data rate into band's 507 /* rate_idx: index of data rate into band's
345 * supported rates or MCS index if HT rates 508 * supported rates or MCS index if HT rates
346 * are use (RX_FLAG_HT) 509 * are use (RX_FLAG_HT)
510 * Notice: this is diff with windows define
347 */ 511 */
348 rx_status->rate_idx = rtlwifi_rate_mapping(hw, status->is_ht, 512 rx_status->rate_idx = _rtl8723e_rate_mapping(hw,
349 status->rate, false); 513 status->is_ht, status->rate);
350 514
351 rx_status->mactime = status->timestamp_low; 515 rx_status->mactime = status->timestamp_low;
352 if (phystatus == true) { 516 if (phystatus == true) {
353 p_drvinfo = (struct rx_fwinfo_8723e *)(skb->data + 517 p_drvinfo = (struct rx_fwinfo_8723e *)(skb->data +
354 status->rx_bufshift); 518 status->rx_bufshift);
355 519
356 _rtl8723ae_translate_rx_signal_stuff(hw, 520 translate_rx_signal_stuff(hw, skb, status, pdesc, p_drvinfo);
357 skb, status, pdesc, p_drvinfo);
358 } 521 }
359
360 /*rx_status->qual = status->signal; */
361 rx_status->signal = status->recvsignalpower + 10; 522 rx_status->signal = status->recvsignalpower + 10;
362
363 return true; 523 return true;
364} 524}
365 525
366void rtl8723ae_tx_fill_desc(struct ieee80211_hw *hw, 526void rtl8723e_tx_fill_desc(struct ieee80211_hw *hw,
367 struct ieee80211_hdr *hdr, u8 *pdesc_tx, 527 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
368 u8 *pbd_desc_tx, struct ieee80211_tx_info *info, 528 u8 *txbd, struct ieee80211_tx_info *info,
369 struct ieee80211_sta *sta, 529 struct ieee80211_sta *sta,
370 struct sk_buff *skb, u8 hw_queue, 530 struct sk_buff *skb,
371 struct rtl_tcb_desc *ptcdesc) 531 u8 hw_queue, struct rtl_tcb_desc *ptcb_desc)
372{ 532{
373 struct rtl_priv *rtlpriv = rtl_priv(hw); 533 struct rtl_priv *rtlpriv = rtl_priv(hw);
374 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 534 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
375 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 535 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
376 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 536 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
377 bool defaultadapter = true; 537 bool b_defaultadapter = true;
378 u8 *pdesc = pdesc_tx; 538 /* bool b_trigger_ac = false; */
539 u8 *pdesc = (u8 *)pdesc_tx;
379 u16 seq_number; 540 u16 seq_number;
380 __le16 fc = hdr->frame_control; 541 __le16 fc = hdr->frame_control;
381 u8 fw_qsel = _rtl8723ae_map_hwqueue_to_fwqueue(skb, hw_queue); 542 u8 fw_qsel = _rtl8723e_map_hwqueue_to_fwqueue(skb, hw_queue);
382 bool firstseg = ((hdr->seq_ctrl & 543 bool firstseg = ((hdr->seq_ctrl &
383 cpu_to_le16(IEEE80211_SCTL_FRAG)) == 0); 544 cpu_to_le16(IEEE80211_SCTL_FRAG)) == 0);
545
384 bool lastseg = ((hdr->frame_control & 546 bool lastseg = ((hdr->frame_control &
385 cpu_to_le16(IEEE80211_FCTL_MOREFRAGS)) == 0); 547 cpu_to_le16(IEEE80211_FCTL_MOREFRAGS)) == 0);
548
386 dma_addr_t mapping = pci_map_single(rtlpci->pdev, 549 dma_addr_t mapping = pci_map_single(rtlpci->pdev,
387 skb->data, skb->len, 550 skb->data, skb->len,
388 PCI_DMA_TODEVICE); 551 PCI_DMA_TODEVICE);
@@ -398,12 +561,13 @@ void rtl8723ae_tx_fill_desc(struct ieee80211_hw *hw,
398 } else if (mac->opmode == NL80211_IFTYPE_AP || 561 } else if (mac->opmode == NL80211_IFTYPE_AP ||
399 mac->opmode == NL80211_IFTYPE_ADHOC) { 562 mac->opmode == NL80211_IFTYPE_ADHOC) {
400 if (sta) 563 if (sta)
401 bw_40 = sta->bandwidth >= IEEE80211_STA_RX_BW_40; 564 bw_40 = sta->ht_cap.cap &
565 IEEE80211_HT_CAP_SUP_WIDTH_20_40;
402 } 566 }
403 567
404 seq_number = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4; 568 seq_number = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
405 569
406 rtl_get_tcb_desc(hw, info, sta, skb, ptcdesc); 570 rtl_get_tcb_desc(hw, info, sta, skb, ptcb_desc);
407 571
408 CLEAR_PCI_TX_DESC_CONTENT(pdesc, sizeof(struct tx_desc_8723e)); 572 CLEAR_PCI_TX_DESC_CONTENT(pdesc, sizeof(struct tx_desc_8723e));
409 573
@@ -415,9 +579,9 @@ void rtl8723ae_tx_fill_desc(struct ieee80211_hw *hw,
415 if (firstseg) { 579 if (firstseg) {
416 SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN); 580 SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN);
417 581
418 SET_TX_DESC_TX_RATE(pdesc, ptcdesc->hw_rate); 582 SET_TX_DESC_TX_RATE(pdesc, ptcb_desc->hw_rate);
419 583
420 if (ptcdesc->use_shortgi || ptcdesc->use_shortpreamble) 584 if (ptcb_desc->use_shortgi || ptcb_desc->use_shortpreamble)
421 SET_TX_DESC_DATA_SHORTGI(pdesc, 1); 585 SET_TX_DESC_DATA_SHORTGI(pdesc, 1);
422 586
423 if (info->flags & IEEE80211_TX_CTL_AMPDU) { 587 if (info->flags & IEEE80211_TX_CTL_AMPDU) {
@@ -426,31 +590,33 @@ void rtl8723ae_tx_fill_desc(struct ieee80211_hw *hw,
426 } 590 }
427 SET_TX_DESC_SEQ(pdesc, seq_number); 591 SET_TX_DESC_SEQ(pdesc, seq_number);
428 592
429 SET_TX_DESC_RTS_ENABLE(pdesc, ((ptcdesc->rts_enable && 593 SET_TX_DESC_RTS_ENABLE(pdesc,
430 !ptcdesc-> 594 ((ptcb_desc->rts_enable &&
431 cts_enable) ? 1 : 0)); 595 !ptcb_desc->cts_enable) ? 1 : 0));
432 SET_TX_DESC_HW_RTS_ENABLE(pdesc, 596 SET_TX_DESC_HW_RTS_ENABLE(pdesc,
433 ((ptcdesc->rts_enable 597 ((ptcb_desc->rts_enable ||
434 || ptcdesc->cts_enable) ? 1 : 0)); 598 ptcb_desc->cts_enable) ? 1 : 0));
435 SET_TX_DESC_CTS2SELF(pdesc, ((ptcdesc->cts_enable) ? 1 : 0)); 599 SET_TX_DESC_CTS2SELF(pdesc,
436 SET_TX_DESC_RTS_STBC(pdesc, ((ptcdesc->rts_stbc) ? 1 : 0)); 600 ((ptcb_desc->cts_enable) ? 1 : 0));
437 601 SET_TX_DESC_RTS_STBC(pdesc,
438 SET_TX_DESC_RTS_RATE(pdesc, ptcdesc->rts_rate); 602 ((ptcb_desc->rts_stbc) ? 1 : 0));
603
604 SET_TX_DESC_RTS_RATE(pdesc, ptcb_desc->rts_rate);
439 SET_TX_DESC_RTS_BW(pdesc, 0); 605 SET_TX_DESC_RTS_BW(pdesc, 0);
440 SET_TX_DESC_RTS_SC(pdesc, ptcdesc->rts_sc); 606 SET_TX_DESC_RTS_SC(pdesc, ptcb_desc->rts_sc);
441 SET_TX_DESC_RTS_SHORT(pdesc, 607 SET_TX_DESC_RTS_SHORT(pdesc,
442 ((ptcdesc->rts_rate <= DESC92_RATE54M) ? 608 ((ptcb_desc->rts_rate <= DESC92C_RATE54M) ?
443 (ptcdesc->rts_use_shortpreamble ? 1 : 0) 609 (ptcb_desc->rts_use_shortpreamble ? 1 : 0)
444 : (ptcdesc->rts_use_shortgi ? 1 : 0))); 610 : (ptcb_desc->rts_use_shortgi ? 1 : 0)));
445 611
446 if (bw_40) { 612 if (bw_40) {
447 if (ptcdesc->packet_bw) { 613 if (ptcb_desc->packet_bw == HT_CHANNEL_WIDTH_20_40) {
448 SET_TX_DESC_DATA_BW(pdesc, 1); 614 SET_TX_DESC_DATA_BW(pdesc, 1);
449 SET_TX_DESC_TX_SUB_CARRIER(pdesc, 3); 615 SET_TX_DESC_TX_SUB_CARRIER(pdesc, 3);
450 } else { 616 } else {
451 SET_TX_DESC_DATA_BW(pdesc, 0); 617 SET_TX_DESC_DATA_BW(pdesc, 0);
452 SET_TX_DESC_TX_SUB_CARRIER(pdesc, 618 SET_TX_DESC_TX_SUB_CARRIER(pdesc,
453 mac->cur_40_prime_sc); 619 mac->cur_40_prime_sc);
454 } 620 }
455 } else { 621 } else {
456 SET_TX_DESC_DATA_BW(pdesc, 0); 622 SET_TX_DESC_DATA_BW(pdesc, 0);
@@ -481,6 +647,7 @@ void rtl8723ae_tx_fill_desc(struct ieee80211_hw *hw,
481 default: 647 default:
482 SET_TX_DESC_SEC_TYPE(pdesc, 0x0); 648 SET_TX_DESC_SEC_TYPE(pdesc, 0x0);
483 break; 649 break;
650
484 } 651 }
485 } 652 }
486 653
@@ -490,7 +657,7 @@ void rtl8723ae_tx_fill_desc(struct ieee80211_hw *hw,
490 SET_TX_DESC_DATA_RATE_FB_LIMIT(pdesc, 0x1F); 657 SET_TX_DESC_DATA_RATE_FB_LIMIT(pdesc, 0x1F);
491 SET_TX_DESC_RTS_RATE_FB_LIMIT(pdesc, 0xF); 658 SET_TX_DESC_RTS_RATE_FB_LIMIT(pdesc, 0xF);
492 SET_TX_DESC_DISABLE_FB(pdesc, 0); 659 SET_TX_DESC_DISABLE_FB(pdesc, 0);
493 SET_TX_DESC_USE_RATE(pdesc, ptcdesc->use_driver_rate ? 1 : 0); 660 SET_TX_DESC_USE_RATE(pdesc, ptcb_desc->use_driver_rate ? 1 : 0);
494 661
495 if (ieee80211_is_data_qos(fc)) { 662 if (ieee80211_is_data_qos(fc)) {
496 if (mac->rdg_en) { 663 if (mac->rdg_en) {
@@ -510,18 +677,21 @@ void rtl8723ae_tx_fill_desc(struct ieee80211_hw *hw,
510 SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping); 677 SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping);
511 678
512 if (rtlpriv->dm.useramask) { 679 if (rtlpriv->dm.useramask) {
513 SET_TX_DESC_RATE_ID(pdesc, ptcdesc->ratr_index); 680 SET_TX_DESC_RATE_ID(pdesc, ptcb_desc->ratr_index);
514 SET_TX_DESC_MACID(pdesc, ptcdesc->mac_id); 681 SET_TX_DESC_MACID(pdesc, ptcb_desc->mac_id);
515 } else { 682 } else {
516 SET_TX_DESC_RATE_ID(pdesc, 0xC + ptcdesc->ratr_index); 683 SET_TX_DESC_RATE_ID(pdesc, 0xC + ptcb_desc->ratr_index);
517 SET_TX_DESC_MACID(pdesc, ptcdesc->ratr_index); 684 SET_TX_DESC_MACID(pdesc, ptcb_desc->ratr_index);
518 } 685 }
519 686
520 if ((!ieee80211_is_data_qos(fc)) && ppsc->fwctrl_lps) { 687 if ((!ieee80211_is_data_qos(fc)) && ppsc->fwctrl_lps) {
521 SET_TX_DESC_HWSEQ_EN_8723(pdesc, 1); 688 SET_TX_DESC_HWSEQ_EN_8723(pdesc, 1);
689 /* SET_TX_DESC_HWSEQ_EN(pdesc, 1); */
690 /* SET_TX_DESC_PKT_ID(pdesc, 8); */
522 691
523 if (!defaultadapter) 692 if (!b_defaultadapter)
524 SET_TX_DESC_HWSEQ_SEL_8723(pdesc, 1); 693 SET_TX_DESC_HWSEQ_SEL_8723(pdesc, 1);
694 /* SET_TX_DESC_QOS(pdesc, 1); */
525 } 695 }
526 696
527 SET_TX_DESC_MORE_FRAG(pdesc, (lastseg ? 0 : 1)); 697 SET_TX_DESC_MORE_FRAG(pdesc, (lastseg ? 0 : 1));
@@ -534,17 +704,19 @@ void rtl8723ae_tx_fill_desc(struct ieee80211_hw *hw,
534 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, "\n"); 704 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, "\n");
535} 705}
536 706
537void rtl8723ae_tx_fill_cmddesc(struct ieee80211_hw *hw, 707void rtl8723e_tx_fill_cmddesc(struct ieee80211_hw *hw,
538 u8 *pdesc, bool firstseg, 708 u8 *pdesc, bool firstseg,
539 bool lastseg, struct sk_buff *skb) 709 bool lastseg, struct sk_buff *skb)
540{ 710{
541 struct rtl_priv *rtlpriv = rtl_priv(hw); 711 struct rtl_priv *rtlpriv = rtl_priv(hw);
542 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 712 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
543 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
544 u8 fw_queue = QSLT_BEACON; 713 u8 fw_queue = QSLT_BEACON;
714
545 dma_addr_t mapping = pci_map_single(rtlpci->pdev, 715 dma_addr_t mapping = pci_map_single(rtlpci->pdev,
546 skb->data, skb->len, 716 skb->data, skb->len,
547 PCI_DMA_TODEVICE); 717 PCI_DMA_TODEVICE);
718
719 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
548 __le16 fc = hdr->frame_control; 720 __le16 fc = hdr->frame_control;
549 721
550 if (pci_dma_mapping_error(rtlpci->pdev, mapping)) { 722 if (pci_dma_mapping_error(rtlpci->pdev, mapping)) {
@@ -557,7 +729,7 @@ void rtl8723ae_tx_fill_cmddesc(struct ieee80211_hw *hw,
557 if (firstseg) 729 if (firstseg)
558 SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN); 730 SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN);
559 731
560 SET_TX_DESC_TX_RATE(pdesc, DESC92_RATE1M); 732 SET_TX_DESC_TX_RATE(pdesc, DESC92C_RATE1M);
561 733
562 SET_TX_DESC_SEQ(pdesc, 0); 734 SET_TX_DESC_SEQ(pdesc, 0);
563 735
@@ -577,7 +749,7 @@ void rtl8723ae_tx_fill_cmddesc(struct ieee80211_hw *hw,
577 749
578 SET_TX_DESC_OWN(pdesc, 1); 750 SET_TX_DESC_OWN(pdesc, 1);
579 751
580 SET_TX_DESC_PKT_SIZE(pdesc, (u16) (skb->len)); 752 SET_TX_DESC_PKT_SIZE((u8 *)pdesc, (u16)(skb->len));
581 753
582 SET_TX_DESC_FIRST_SEG(pdesc, 1); 754 SET_TX_DESC_FIRST_SEG(pdesc, 1);
583 SET_TX_DESC_LAST_SEG(pdesc, 1); 755 SET_TX_DESC_LAST_SEG(pdesc, 1);
@@ -597,8 +769,8 @@ void rtl8723ae_tx_fill_cmddesc(struct ieee80211_hw *hw,
597 pdesc, TX_DESC_SIZE); 769 pdesc, TX_DESC_SIZE);
598} 770}
599 771
600void rtl8723ae_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx, 772void rtl8723e_set_desc(struct ieee80211_hw *hw, u8 *pdesc,
601 u8 desc_name, u8 *val) 773 bool istx, u8 desc_name, u8 *val)
602{ 774{
603 if (istx == true) { 775 if (istx == true) {
604 switch (desc_name) { 776 switch (desc_name) {
@@ -635,7 +807,7 @@ void rtl8723ae_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
635 } 807 }
636} 808}
637 809
638u32 rtl8723ae_get_desc(u8 *pdesc, bool istx, u8 desc_name) 810u32 rtl8723e_get_desc(u8 *pdesc, bool istx, u8 desc_name)
639{ 811{
640 u32 ret = 0; 812 u32 ret = 0;
641 813
@@ -660,6 +832,9 @@ u32 rtl8723ae_get_desc(u8 *pdesc, bool istx, u8 desc_name)
660 case HW_DESC_RXPKT_LEN: 832 case HW_DESC_RXPKT_LEN:
661 ret = GET_RX_DESC_PKT_LEN(pdesc); 833 ret = GET_RX_DESC_PKT_LEN(pdesc);
662 break; 834 break;
835 case HW_DESC_RXBUFF_ADDR:
836 ret = GET_RX_DESC_BUFF_ADDR(pdesc);
837 break;
663 default: 838 default:
664 RT_ASSERT(false, "ERR rxdesc :%d not process\n", 839 RT_ASSERT(false, "ERR rxdesc :%d not process\n",
665 desc_name); 840 desc_name);
@@ -669,7 +844,25 @@ u32 rtl8723ae_get_desc(u8 *pdesc, bool istx, u8 desc_name)
669 return ret; 844 return ret;
670} 845}
671 846
672void rtl8723ae_tx_polling(struct ieee80211_hw *hw, u8 hw_queue) 847bool rtl8723e_is_tx_desc_closed(struct ieee80211_hw *hw,
848 u8 hw_queue, u16 index)
849{
850 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
851 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
852 u8 *entry = (u8 *)(&ring->desc[ring->idx]);
853 u8 own = (u8)rtl8723e_get_desc(entry, true, HW_DESC_OWN);
854
855 /**
856 *beacon packet will only use the first
857 *descriptor defautly,and the own may not
858 *be cleared by the hardware
859 */
860 if (own)
861 return false;
862 return true;
863}
864
865void rtl8723e_tx_polling(struct ieee80211_hw *hw, u8 hw_queue)
673{ 866{
674 struct rtl_priv *rtlpriv = rtl_priv(hw); 867 struct rtl_priv *rtlpriv = rtl_priv(hw);
675 if (hw_queue == BEACON_QUEUE) { 868 if (hw_queue == BEACON_QUEUE) {
@@ -679,3 +872,10 @@ void rtl8723ae_tx_polling(struct ieee80211_hw *hw, u8 hw_queue)
679 BIT(0) << (hw_queue)); 872 BIT(0) << (hw_queue));
680 } 873 }
681} 874}
875
876u32 rtl8723e_rx_command_packet(struct ieee80211_hw *hw,
877 struct rtl_stats status,
878 struct sk_buff *skb)
879{
880 return 0;
881}
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/trx.h b/drivers/net/wireless/rtlwifi/rtl8723ae/trx.h
index 4380b7d3a91a..017da7e194d8 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/trx.h
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/trx.h
@@ -11,10 +11,6 @@
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details. 12 * more details.
13 * 13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the 14 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE. 15 * file called LICENSE.
20 * 16 *
@@ -30,77 +26,77 @@
30#ifndef __RTL8723E_TRX_H__ 26#ifndef __RTL8723E_TRX_H__
31#define __RTL8723E_TRX_H__ 27#define __RTL8723E_TRX_H__
32 28
33#define TX_DESC_SIZE 64 29#define TX_DESC_SIZE 64
34#define TX_DESC_AGGR_SUBFRAME_SIZE 32 30#define TX_DESC_AGGR_SUBFRAME_SIZE 32
35 31
36#define RX_DESC_SIZE 32 32#define RX_DESC_SIZE 32
37#define RX_DRV_INFO_SIZE_UNIT 8 33#define RX_DRV_INFO_SIZE_UNIT 8
38 34
39#define TX_DESC_NEXT_DESC_OFFSET 40 35#define TX_DESC_NEXT_DESC_OFFSET 40
40#define USB_HWDESC_HEADER_LEN 32 36#define USB_HWDESC_HEADER_LEN 32
41#define CRCLENGTH 4 37#define CRCLENGTH 4
42 38
43#define SET_TX_DESC_PKT_SIZE(__pdesc, __val) \ 39#define SET_TX_DESC_PKT_SIZE(__pdesc, __val) \
44 SET_BITS_TO_LE_4BYTE(__pdesc, 0, 16, __val) 40 SET_BITS_TO_LE_4BYTE(__pdesc, 0, 16, __val)
45#define SET_TX_DESC_OFFSET(__pdesc, __val) \ 41#define SET_TX_DESC_OFFSET(__pdesc, __val) \
46 SET_BITS_TO_LE_4BYTE(__pdesc, 16, 8, __val) 42 SET_BITS_TO_LE_4BYTE(__pdesc, 16, 8, __val)
47#define SET_TX_DESC_BMC(__pdesc, __val) \ 43#define SET_TX_DESC_BMC(__pdesc, __val) \
48 SET_BITS_TO_LE_4BYTE(__pdesc, 24, 1, __val) 44 SET_BITS_TO_LE_4BYTE(__pdesc, 24, 1, __val)
49#define SET_TX_DESC_HTC(__pdesc, __val) \ 45#define SET_TX_DESC_HTC(__pdesc, __val) \
50 SET_BITS_TO_LE_4BYTE(__pdesc, 25, 1, __val) 46 SET_BITS_TO_LE_4BYTE(__pdesc, 25, 1, __val)
51#define SET_TX_DESC_LAST_SEG(__pdesc, __val) \ 47#define SET_TX_DESC_LAST_SEG(__pdesc, __val) \
52 SET_BITS_TO_LE_4BYTE(__pdesc, 26, 1, __val) 48 SET_BITS_TO_LE_4BYTE(__pdesc, 26, 1, __val)
53#define SET_TX_DESC_FIRST_SEG(__pdesc, __val) \ 49#define SET_TX_DESC_FIRST_SEG(__pdesc, __val) \
54 SET_BITS_TO_LE_4BYTE(__pdesc, 27, 1, __val) 50 SET_BITS_TO_LE_4BYTE(__pdesc, 27, 1, __val)
55#define SET_TX_DESC_LINIP(__pdesc, __val) \ 51#define SET_TX_DESC_LINIP(__pdesc, __val) \
56 SET_BITS_TO_LE_4BYTE(__pdesc, 28, 1, __val) 52 SET_BITS_TO_LE_4BYTE(__pdesc, 28, 1, __val)
57#define SET_TX_DESC_NO_ACM(__pdesc, __val) \ 53#define SET_TX_DESC_NO_ACM(__pdesc, __val) \
58 SET_BITS_TO_LE_4BYTE(__pdesc, 29, 1, __val) 54 SET_BITS_TO_LE_4BYTE(__pdesc, 29, 1, __val)
59#define SET_TX_DESC_GF(__pdesc, __val) \ 55#define SET_TX_DESC_GF(__pdesc, __val) \
60 SET_BITS_TO_LE_4BYTE(__pdesc, 30, 1, __val) 56 SET_BITS_TO_LE_4BYTE(__pdesc, 30, 1, __val)
61#define SET_TX_DESC_OWN(__pdesc, __val) \ 57#define SET_TX_DESC_OWN(__pdesc, __val) \
62 SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val) 58 SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val)
63 59
64#define GET_TX_DESC_PKT_SIZE(__pdesc) \ 60#define GET_TX_DESC_PKT_SIZE(__pdesc) \
65 LE_BITS_TO_4BYTE(__pdesc, 0, 16) 61 LE_BITS_TO_4BYTE(__pdesc, 0, 16)
66#define GET_TX_DESC_OFFSET(__pdesc) \ 62#define GET_TX_DESC_OFFSET(__pdesc) \
67 LE_BITS_TO_4BYTE(__pdesc, 16, 8) 63 LE_BITS_TO_4BYTE(__pdesc, 16, 8)
68#define GET_TX_DESC_BMC(__pdesc) \ 64#define GET_TX_DESC_BMC(__pdesc) \
69 LE_BITS_TO_4BYTE(__pdesc, 24, 1) 65 LE_BITS_TO_4BYTE(__pdesc, 24, 1)
70#define GET_TX_DESC_HTC(__pdesc) \ 66#define GET_TX_DESC_HTC(__pdesc) \
71 LE_BITS_TO_4BYTE(__pdesc, 25, 1) 67 LE_BITS_TO_4BYTE(__pdesc, 25, 1)
72#define GET_TX_DESC_LAST_SEG(__pdesc) \ 68#define GET_TX_DESC_LAST_SEG(__pdesc) \
73 LE_BITS_TO_4BYTE(__pdesc, 26, 1) 69 LE_BITS_TO_4BYTE(__pdesc, 26, 1)
74#define GET_TX_DESC_FIRST_SEG(__pdesc) \ 70#define GET_TX_DESC_FIRST_SEG(__pdesc) \
75 LE_BITS_TO_4BYTE(__pdesc, 27, 1) 71 LE_BITS_TO_4BYTE(__pdesc, 27, 1)
76#define GET_TX_DESC_LINIP(__pdesc) \ 72#define GET_TX_DESC_LINIP(__pdesc) \
77 LE_BITS_TO_4BYTE(__pdesc, 28, 1) 73 LE_BITS_TO_4BYTE(__pdesc, 28, 1)
78#define GET_TX_DESC_NO_ACM(__pdesc) \ 74#define GET_TX_DESC_NO_ACM(__pdesc) \
79 LE_BITS_TO_4BYTE(__pdesc, 29, 1) 75 LE_BITS_TO_4BYTE(__pdesc, 29, 1)
80#define GET_TX_DESC_GF(__pdesc) \ 76#define GET_TX_DESC_GF(__pdesc) \
81 LE_BITS_TO_4BYTE(__pdesc, 30, 1) 77 LE_BITS_TO_4BYTE(__pdesc, 30, 1)
82#define GET_TX_DESC_OWN(__pdesc) \ 78#define GET_TX_DESC_OWN(__pdesc) \
83 LE_BITS_TO_4BYTE(__pdesc, 31, 1) 79 LE_BITS_TO_4BYTE(__pdesc, 31, 1)
84 80
85#define SET_TX_DESC_MACID(__pdesc, __val) \ 81#define SET_TX_DESC_MACID(__pdesc, __val) \
86 SET_BITS_TO_LE_4BYTE(__pdesc+4, 0, 5, __val) 82 SET_BITS_TO_LE_4BYTE(__pdesc+4, 0, 5, __val)
87#define SET_TX_DESC_AGG_BREAK(__pdesc, __val) \ 83#define SET_TX_DESC_AGG_BREAK(__pdesc, __val) \
88 SET_BITS_TO_LE_4BYTE(__pdesc+4, 5, 1, __val) 84 SET_BITS_TO_LE_4BYTE(__pdesc+4, 5, 1, __val)
89#define SET_TX_DESC_BK(__pdesc, __val) \ 85#define SET_TX_DESC_BK(__pdesc, __val) \
90 SET_BITS_TO_LE_4BYTE(__pdesc+4, 6, 1, __val) 86 SET_BITS_TO_LE_4BYTE(__pdesc+4, 6, 1, __val)
91#define SET_TX_DESC_RDG_ENABLE(__pdesc, __val) \ 87#define SET_TX_DESC_RDG_ENABLE(__pdesc, __val) \
92 SET_BITS_TO_LE_4BYTE(__pdesc+4, 7, 1, __val) 88 SET_BITS_TO_LE_4BYTE(__pdesc+4, 7, 1, __val)
93#define SET_TX_DESC_QUEUE_SEL(__pdesc, __val) \ 89#define SET_TX_DESC_QUEUE_SEL(__pdesc, __val) \
94 SET_BITS_TO_LE_4BYTE(__pdesc+4, 8, 5, __val) 90 SET_BITS_TO_LE_4BYTE(__pdesc+4, 8, 5, __val)
95#define SET_TX_DESC_RDG_NAV_EXT(__pdesc, __val) \ 91#define SET_TX_DESC_RDG_NAV_EXT(__pdesc, __val) \
96 SET_BITS_TO_LE_4BYTE(__pdesc+4, 13, 1, __val) 92 SET_BITS_TO_LE_4BYTE(__pdesc+4, 13, 1, __val)
97#define SET_TX_DESC_LSIG_TXOP_EN(__pdesc, __val) \ 93#define SET_TX_DESC_LSIG_TXOP_EN(__pdesc, __val) \
98 SET_BITS_TO_LE_4BYTE(__pdesc+4, 14, 1, __val) 94 SET_BITS_TO_LE_4BYTE(__pdesc+4, 14, 1, __val)
99#define SET_TX_DESC_PIFS(__pdesc, __val) \ 95#define SET_TX_DESC_PIFS(__pdesc, __val) \
100 SET_BITS_TO_LE_4BYTE(__pdesc+4, 15, 1, __val) 96 SET_BITS_TO_LE_4BYTE(__pdesc+4, 15, 1, __val)
101#define SET_TX_DESC_RATE_ID(__pdesc, __val) \ 97#define SET_TX_DESC_RATE_ID(__pdesc, __val) \
102 SET_BITS_TO_LE_4BYTE(__pdesc+4, 16, 4, __val) 98 SET_BITS_TO_LE_4BYTE(__pdesc+4, 16, 4, __val)
103#define SET_TX_DESC_NAV_USE_HDR(__pdesc, __val) \ 99#define SET_TX_DESC_NAV_USE_HDR(__pdesc, __val) \
104 SET_BITS_TO_LE_4BYTE(__pdesc+4, 20, 1, __val) 100 SET_BITS_TO_LE_4BYTE(__pdesc+4, 20, 1, __val)
105#define SET_TX_DESC_EN_DESC_ID(__pdesc, __val) \ 101#define SET_TX_DESC_EN_DESC_ID(__pdesc, __val) \
106 SET_BITS_TO_LE_4BYTE(__pdesc+4, 21, 1, __val) 102 SET_BITS_TO_LE_4BYTE(__pdesc+4, 21, 1, __val)
@@ -109,34 +105,34 @@
109#define SET_TX_DESC_PKT_OFFSET(__pdesc, __val) \ 105#define SET_TX_DESC_PKT_OFFSET(__pdesc, __val) \
110 SET_BITS_TO_LE_4BYTE(__pdesc+4, 24, 8, __val) 106 SET_BITS_TO_LE_4BYTE(__pdesc+4, 24, 8, __val)
111 107
112#define GET_TX_DESC_MACID(__pdesc) \ 108#define GET_TX_DESC_MACID(__pdesc) \
113 LE_BITS_TO_4BYTE(__pdesc+4, 0, 5) 109 LE_BITS_TO_4BYTE(__pdesc+4, 0, 5)
114#define GET_TX_DESC_AGG_ENABLE(__pdesc) \ 110#define GET_TX_DESC_AGG_ENABLE(__pdesc) \
115 LE_BITS_TO_4BYTE(__pdesc+4, 5, 1) 111 LE_BITS_TO_4BYTE(__pdesc+4, 5, 1)
116#define GET_TX_DESC_AGG_BREAK(__pdesc) \ 112#define GET_TX_DESC_AGG_BREAK(__pdesc) \
117 LE_BITS_TO_4BYTE(__pdesc+4, 6, 1) 113 LE_BITS_TO_4BYTE(__pdesc+4, 6, 1)
118#define GET_TX_DESC_RDG_ENABLE(__pdesc) \ 114#define GET_TX_DESC_RDG_ENABLE(__pdesc) \
119 LE_BITS_TO_4BYTE(__pdesc+4, 7, 1) 115 LE_BITS_TO_4BYTE(__pdesc+4, 7, 1)
120#define GET_TX_DESC_QUEUE_SEL(__pdesc) \ 116#define GET_TX_DESC_QUEUE_SEL(__pdesc) \
121 LE_BITS_TO_4BYTE(__pdesc+4, 8, 5) 117 LE_BITS_TO_4BYTE(__pdesc+4, 8, 5)
122#define GET_TX_DESC_RDG_NAV_EXT(__pdesc) \ 118#define GET_TX_DESC_RDG_NAV_EXT(__pdesc) \
123 LE_BITS_TO_4BYTE(__pdesc+4, 13, 1) 119 LE_BITS_TO_4BYTE(__pdesc+4, 13, 1)
124#define GET_TX_DESC_LSIG_TXOP_EN(__pdesc) \ 120#define GET_TX_DESC_LSIG_TXOP_EN(__pdesc) \
125 LE_BITS_TO_4BYTE(__pdesc+4, 14, 1) 121 LE_BITS_TO_4BYTE(__pdesc+4, 14, 1)
126#define GET_TX_DESC_PIFS(__pdesc) \ 122#define GET_TX_DESC_PIFS(__pdesc) \
127 LE_BITS_TO_4BYTE(__pdesc+4, 15, 1) 123 LE_BITS_TO_4BYTE(__pdesc+4, 15, 1)
128#define GET_TX_DESC_RATE_ID(__pdesc) \ 124#define GET_TX_DESC_RATE_ID(__pdesc) \
129 LE_BITS_TO_4BYTE(__pdesc+4, 16, 4) 125 LE_BITS_TO_4BYTE(__pdesc+4, 16, 4)
130#define GET_TX_DESC_NAV_USE_HDR(__pdesc) \ 126#define GET_TX_DESC_NAV_USE_HDR(__pdesc) \
131 LE_BITS_TO_4BYTE(__pdesc+4, 20, 1) 127 LE_BITS_TO_4BYTE(__pdesc+4, 20, 1)
132#define GET_TX_DESC_EN_DESC_ID(__pdesc) \ 128#define GET_TX_DESC_EN_DESC_ID(__pdesc) \
133 LE_BITS_TO_4BYTE(__pdesc+4, 21, 1) 129 LE_BITS_TO_4BYTE(__pdesc+4, 21, 1)
134#define GET_TX_DESC_SEC_TYPE(__pdesc) \ 130#define GET_TX_DESC_SEC_TYPE(__pdesc) \
135 LE_BITS_TO_4BYTE(__pdesc+4, 22, 2) 131 LE_BITS_TO_4BYTE(__pdesc+4, 22, 2)
136#define GET_TX_DESC_PKT_OFFSET(__pdesc) \ 132#define GET_TX_DESC_PKT_OFFSET(__pdesc) \
137 LE_BITS_TO_4BYTE(__pdesc+4, 24, 8) 133 LE_BITS_TO_4BYTE(__pdesc+4, 24, 8)
138 134
139#define SET_TX_DESC_RTS_RC(__pdesc, __val) \ 135#define SET_TX_DESC_RTS_RC(__pdesc, __val) \
140 SET_BITS_TO_LE_4BYTE(__pdesc+8, 0, 6, __val) 136 SET_BITS_TO_LE_4BYTE(__pdesc+8, 0, 6, __val)
141#define SET_TX_DESC_DATA_RC(__pdesc, __val) \ 137#define SET_TX_DESC_DATA_RC(__pdesc, __val) \
142 SET_BITS_TO_LE_4BYTE(__pdesc+8, 6, 6, __val) 138 SET_BITS_TO_LE_4BYTE(__pdesc+8, 6, 6, __val)
@@ -144,9 +140,9 @@
144 SET_BITS_TO_LE_4BYTE(__pdesc+8, 14, 2, __val) 140 SET_BITS_TO_LE_4BYTE(__pdesc+8, 14, 2, __val)
145#define SET_TX_DESC_MORE_FRAG(__pdesc, __val) \ 141#define SET_TX_DESC_MORE_FRAG(__pdesc, __val) \
146 SET_BITS_TO_LE_4BYTE(__pdesc+8, 17, 1, __val) 142 SET_BITS_TO_LE_4BYTE(__pdesc+8, 17, 1, __val)
147#define SET_TX_DESC_RAW(__pdesc, __val) \ 143#define SET_TX_DESC_RAW(__pdesc, __val) \
148 SET_BITS_TO_LE_4BYTE(__pdesc+8, 18, 1, __val) 144 SET_BITS_TO_LE_4BYTE(__pdesc+8, 18, 1, __val)
149#define SET_TX_DESC_CCX(__pdesc, __val) \ 145#define SET_TX_DESC_CCX(__pdesc, __val) \
150 SET_BITS_TO_LE_4BYTE(__pdesc+8, 19, 1, __val) 146 SET_BITS_TO_LE_4BYTE(__pdesc+8, 19, 1, __val)
151#define SET_TX_DESC_AMPDU_DENSITY(__pdesc, __val) \ 147#define SET_TX_DESC_AMPDU_DENSITY(__pdesc, __val) \
152 SET_BITS_TO_LE_4BYTE(__pdesc+8, 20, 3, __val) 148 SET_BITS_TO_LE_4BYTE(__pdesc+8, 20, 3, __val)
@@ -161,62 +157,62 @@
161#define SET_TX_DESC_TX_ANT_HT(__pdesc, __val) \ 157#define SET_TX_DESC_TX_ANT_HT(__pdesc, __val) \
162 SET_BITS_TO_LE_4BYTE(__pdesc+8, 30, 2, __val) 158 SET_BITS_TO_LE_4BYTE(__pdesc+8, 30, 2, __val)
163 159
164#define GET_TX_DESC_RTS_RC(__pdesc) \ 160#define GET_TX_DESC_RTS_RC(__pdesc) \
165 LE_BITS_TO_4BYTE(__pdesc+8, 0, 6) 161 LE_BITS_TO_4BYTE(__pdesc+8, 0, 6)
166#define GET_TX_DESC_DATA_RC(__pdesc) \ 162#define GET_TX_DESC_DATA_RC(__pdesc) \
167 LE_BITS_TO_4BYTE(__pdesc+8, 6, 6) 163 LE_BITS_TO_4BYTE(__pdesc+8, 6, 6)
168#define GET_TX_DESC_BAR_RTY_TH(__pdesc) \ 164#define GET_TX_DESC_BAR_RTY_TH(__pdesc) \
169 LE_BITS_TO_4BYTE(__pdesc+8, 14, 2) 165 LE_BITS_TO_4BYTE(__pdesc+8, 14, 2)
170#define GET_TX_DESC_MORE_FRAG(__pdesc) \ 166#define GET_TX_DESC_MORE_FRAG(__pdesc) \
171 LE_BITS_TO_4BYTE(__pdesc+8, 17, 1) 167 LE_BITS_TO_4BYTE(__pdesc+8, 17, 1)
172#define GET_TX_DESC_RAW(__pdesc) \ 168#define GET_TX_DESC_RAW(__pdesc) \
173 LE_BITS_TO_4BYTE(__pdesc+8, 18, 1) 169 LE_BITS_TO_4BYTE(__pdesc+8, 18, 1)
174#define GET_TX_DESC_CCX(__pdesc) \ 170#define GET_TX_DESC_CCX(__pdesc) \
175 LE_BITS_TO_4BYTE(__pdesc+8, 19, 1) 171 LE_BITS_TO_4BYTE(__pdesc+8, 19, 1)
176#define GET_TX_DESC_AMPDU_DENSITY(__pdesc) \ 172#define GET_TX_DESC_AMPDU_DENSITY(__pdesc) \
177 LE_BITS_TO_4BYTE(__pdesc+8, 20, 3) 173 LE_BITS_TO_4BYTE(__pdesc+8, 20, 3)
178#define GET_TX_DESC_ANTSEL_A(__pdesc) \ 174#define GET_TX_DESC_ANTSEL_A(__pdesc) \
179 LE_BITS_TO_4BYTE(__pdesc+8, 24, 1) 175 LE_BITS_TO_4BYTE(__pdesc+8, 24, 1)
180#define GET_TX_DESC_ANTSEL_B(__pdesc) \ 176#define GET_TX_DESC_ANTSEL_B(__pdesc) \
181 LE_BITS_TO_4BYTE(__pdesc+8, 25, 1) 177 LE_BITS_TO_4BYTE(__pdesc+8, 25, 1)
182#define GET_TX_DESC_TX_ANT_CCK(__pdesc) \ 178#define GET_TX_DESC_TX_ANT_CCK(__pdesc) \
183 LE_BITS_TO_4BYTE(__pdesc+8, 26, 2) 179 LE_BITS_TO_4BYTE(__pdesc+8, 26, 2)
184#define GET_TX_DESC_TX_ANTL(__pdesc) \ 180#define GET_TX_DESC_TX_ANTL(__pdesc) \
185 LE_BITS_TO_4BYTE(__pdesc+8, 28, 2) 181 LE_BITS_TO_4BYTE(__pdesc+8, 28, 2)
186#define GET_TX_DESC_TX_ANT_HT(__pdesc) \ 182#define GET_TX_DESC_TX_ANT_HT(__pdesc) \
187 LE_BITS_TO_4BYTE(__pdesc+8, 30, 2) 183 LE_BITS_TO_4BYTE(__pdesc+8, 30, 2)
188 184
189#define SET_TX_DESC_NEXT_HEAP_PAGE(__pdesc, __val) \ 185#define SET_TX_DESC_NEXT_HEAP_PAGE(__pdesc, __val) \
190 SET_BITS_TO_LE_4BYTE(__pdesc+12, 0, 8, __val) 186 SET_BITS_TO_LE_4BYTE(__pdesc+12, 0, 8, __val)
191#define SET_TX_DESC_TAIL_PAGE(__pdesc, __val) \ 187#define SET_TX_DESC_TAIL_PAGE(__pdesc, __val) \
192 SET_BITS_TO_LE_4BYTE(__pdesc+12, 8, 8, __val) 188 SET_BITS_TO_LE_4BYTE(__pdesc+12, 8, 8, __val)
193#define SET_TX_DESC_SEQ(__pdesc, __val) \ 189#define SET_TX_DESC_SEQ(__pdesc, __val) \
194 SET_BITS_TO_LE_4BYTE(__pdesc+12, 16, 12, __val) 190 SET_BITS_TO_LE_4BYTE(__pdesc+12, 16, 12, __val)
195#define SET_TX_DESC_PKT_ID(__pdesc, __val) \ 191#define SET_TX_DESC_PKT_ID(__pdesc, __val) \
196 SET_BITS_TO_LE_4BYTE(__pdesc+12, 28, 4, __val) 192 SET_BITS_TO_LE_4BYTE(__pdesc+12, 28, 4, __val)
197 193
198#define GET_TX_DESC_NEXT_HEAP_PAGE(__pdesc) \ 194#define GET_TX_DESC_NEXT_HEAP_PAGE(__pdesc) \
199 LE_BITS_TO_4BYTE(__pdesc+12, 0, 8) 195 LE_BITS_TO_4BYTE(__pdesc+12, 0, 8)
200#define GET_TX_DESC_TAIL_PAGE(__pdesc) \ 196#define GET_TX_DESC_TAIL_PAGE(__pdesc) \
201 LE_BITS_TO_4BYTE(__pdesc+12, 8, 8) 197 LE_BITS_TO_4BYTE(__pdesc+12, 8, 8)
202#define GET_TX_DESC_SEQ(__pdesc) \ 198#define GET_TX_DESC_SEQ(__pdesc) \
203 LE_BITS_TO_4BYTE(__pdesc+12, 16, 12) 199 LE_BITS_TO_4BYTE(__pdesc+12, 16, 12)
204#define GET_TX_DESC_PKT_ID(__pdesc) \ 200#define GET_TX_DESC_PKT_ID(__pdesc) \
205 LE_BITS_TO_4BYTE(__pdesc+12, 28, 4) 201 LE_BITS_TO_4BYTE(__pdesc+12, 28, 4)
206 202
207/* For RTL8723 */ 203/* For RTL8723 */
208#define SET_TX_DESC_TRIGGER_INT(__pdesc, __val) \ 204#define SET_TX_DESC_TRIGGER_INT(__pdesc, __val) \
209 SET_BITS_TO_LE_4BYTE(__pdesc+12, 30, 1, __val) 205 SET_BITS_TO_LE_4BYTE(__pdesc+12, 30, 1, __val)
210#define SET_TX_DESC_HWSEQ_EN_8723(__pdesc, __val) \ 206#define SET_TX_DESC_HWSEQ_EN_8723(__pdesc, __val) \
211 SET_BITS_TO_LE_4BYTE(__pdesc+12, 31, 1, __val) 207 SET_BITS_TO_LE_4BYTE(__pdesc+12, 31, 1, __val)
212#define SET_TX_DESC_HWSEQ_SEL_8723(__pTxDesc, __Value) \ 208#define SET_TX_DESC_HWSEQ_SEL_8723(__txdesc, __value) \
213 SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 6, 2, __Value) 209 SET_BITS_TO_LE_4BYTE(__txdesc+16, 6, 2, __value)
214 210
215#define SET_TX_DESC_RTS_RATE(__pdesc, __val) \ 211#define SET_TX_DESC_RTS_RATE(__pdesc, __val) \
216 SET_BITS_TO_LE_4BYTE(__pdesc+16, 0, 5, __val) 212 SET_BITS_TO_LE_4BYTE(__pdesc+16, 0, 5, __val)
217#define SET_TX_DESC_AP_DCFE(__pdesc, __val) \ 213#define SET_TX_DESC_AP_DCFE(__pdesc, __val) \
218 SET_BITS_TO_LE_4BYTE(__pdesc+16, 5, 1, __val) 214 SET_BITS_TO_LE_4BYTE(__pdesc+16, 5, 1, __val)
219#define SET_TX_DESC_QOS(__pdesc, __val) \ 215#define SET_TX_DESC_QOS(__pdesc, __val) \
220 SET_BITS_TO_LE_4BYTE(__pdesc+16, 6, 1, __val) 216 SET_BITS_TO_LE_4BYTE(__pdesc+16, 6, 1, __val)
221#define SET_TX_DESC_HWSEQ_EN(__pdesc, __val) \ 217#define SET_TX_DESC_HWSEQ_EN(__pdesc, __val) \
222 SET_BITS_TO_LE_4BYTE(__pdesc+16, 7, 1, __val) 218 SET_BITS_TO_LE_4BYTE(__pdesc+16, 7, 1, __val)
@@ -248,54 +244,54 @@
248 SET_BITS_TO_LE_4BYTE(__pdesc+16, 25, 1, __val) 244 SET_BITS_TO_LE_4BYTE(__pdesc+16, 25, 1, __val)
249#define SET_TX_DESC_RTS_SHORT(__pdesc, __val) \ 245#define SET_TX_DESC_RTS_SHORT(__pdesc, __val) \
250 SET_BITS_TO_LE_4BYTE(__pdesc+16, 26, 1, __val) 246 SET_BITS_TO_LE_4BYTE(__pdesc+16, 26, 1, __val)
251#define SET_TX_DESC_RTS_BW(__pdesc, __val) \ 247#define SET_TX_DESC_RTS_BW(__pdesc, __val) \
252 SET_BITS_TO_LE_4BYTE(__pdesc+16, 27, 1, __val) 248 SET_BITS_TO_LE_4BYTE(__pdesc+16, 27, 1, __val)
253#define SET_TX_DESC_RTS_SC(__pdesc, __val) \ 249#define SET_TX_DESC_RTS_SC(__pdesc, __val) \
254 SET_BITS_TO_LE_4BYTE(__pdesc+16, 28, 2, __val) 250 SET_BITS_TO_LE_4BYTE(__pdesc+16, 28, 2, __val)
255#define SET_TX_DESC_RTS_STBC(__pdesc, __val) \ 251#define SET_TX_DESC_RTS_STBC(__pdesc, __val) \
256 SET_BITS_TO_LE_4BYTE(__pdesc+16, 30, 2, __val) 252 SET_BITS_TO_LE_4BYTE(__pdesc+16, 30, 2, __val)
257 253
258#define GET_TX_DESC_RTS_RATE(__pdesc) \ 254#define GET_TX_DESC_RTS_RATE(__pdesc) \
259 LE_BITS_TO_4BYTE(__pdesc+16, 0, 5) 255 LE_BITS_TO_4BYTE(__pdesc+16, 0, 5)
260#define GET_TX_DESC_AP_DCFE(__pdesc) \ 256#define GET_TX_DESC_AP_DCFE(__pdesc) \
261 LE_BITS_TO_4BYTE(__pdesc+16, 5, 1) 257 LE_BITS_TO_4BYTE(__pdesc+16, 5, 1)
262#define GET_TX_DESC_QOS(__pdesc) \ 258#define GET_TX_DESC_QOS(__pdesc) \
263 LE_BITS_TO_4BYTE(__pdesc+16, 6, 1) 259 LE_BITS_TO_4BYTE(__pdesc+16, 6, 1)
264#define GET_TX_DESC_HWSEQ_EN(__pdesc) \ 260#define GET_TX_DESC_HWSEQ_EN(__pdesc) \
265 LE_BITS_TO_4BYTE(__pdesc+16, 7, 1) 261 LE_BITS_TO_4BYTE(__pdesc+16, 7, 1)
266#define GET_TX_DESC_USE_RATE(__pdesc) \ 262#define GET_TX_DESC_USE_RATE(__pdesc) \
267 LE_BITS_TO_4BYTE(__pdesc+16, 8, 1) 263 LE_BITS_TO_4BYTE(__pdesc+16, 8, 1)
268#define GET_TX_DESC_DISABLE_RTS_FB(__pdesc) \ 264#define GET_TX_DESC_DISABLE_RTS_FB(__pdesc) \
269 LE_BITS_TO_4BYTE(__pdesc+16, 9, 1) 265 LE_BITS_TO_4BYTE(__pdesc+16, 9, 1)
270#define GET_TX_DESC_DISABLE_FB(__pdesc) \ 266#define GET_TX_DESC_DISABLE_FB(__pdesc) \
271 LE_BITS_TO_4BYTE(__pdesc+16, 10, 1) 267 LE_BITS_TO_4BYTE(__pdesc+16, 10, 1)
272#define GET_TX_DESC_CTS2SELF(__pdesc) \ 268#define GET_TX_DESC_CTS2SELF(__pdesc) \
273 LE_BITS_TO_4BYTE(__pdesc+16, 11, 1) 269 LE_BITS_TO_4BYTE(__pdesc+16, 11, 1)
274#define GET_TX_DESC_RTS_ENABLE(__pdesc) \ 270#define GET_TX_DESC_RTS_ENABLE(__pdesc) \
275 LE_BITS_TO_4BYTE(__pdesc+16, 12, 1) 271 LE_BITS_TO_4BYTE(__pdesc+16, 12, 1)
276#define GET_TX_DESC_HW_RTS_ENABLE(__pdesc) \ 272#define GET_TX_DESC_HW_RTS_ENABLE(__pdesc) \
277 LE_BITS_TO_4BYTE(__pdesc+16, 13, 1) 273 LE_BITS_TO_4BYTE(__pdesc+16, 13, 1)
278#define GET_TX_DESC_PORT_ID(__pdesc) \ 274#define GET_TX_DESC_PORT_ID(__pdesc) \
279 LE_BITS_TO_4BYTE(__pdesc+16, 14, 1) 275 LE_BITS_TO_4BYTE(__pdesc+16, 14, 1)
280#define GET_TX_DESC_WAIT_DCTS(__pdesc) \ 276#define GET_TX_DESC_WAIT_DCTS(__pdesc) \
281 LE_BITS_TO_4BYTE(__pdesc+16, 18, 1) 277 LE_BITS_TO_4BYTE(__pdesc+16, 18, 1)
282#define GET_TX_DESC_CTS2AP_EN(__pdesc) \ 278#define GET_TX_DESC_CTS2AP_EN(__pdesc) \
283 LE_BITS_TO_4BYTE(__pdesc+16, 19, 1) 279 LE_BITS_TO_4BYTE(__pdesc+16, 19, 1)
284#define GET_TX_DESC_TX_SUB_CARRIER(__pdesc) \ 280#define GET_TX_DESC_TX_SUB_CARRIER(__pdesc) \
285 LE_BITS_TO_4BYTE(__pdesc+16, 20, 2) 281 LE_BITS_TO_4BYTE(__pdesc+16, 20, 2)
286#define GET_TX_DESC_TX_STBC(__pdesc) \ 282#define GET_TX_DESC_TX_STBC(__pdesc) \
287 LE_BITS_TO_4BYTE(__pdesc+16, 22, 2) 283 LE_BITS_TO_4BYTE(__pdesc+16, 22, 2)
288#define GET_TX_DESC_DATA_SHORT(__pdesc) \ 284#define GET_TX_DESC_DATA_SHORT(__pdesc) \
289 LE_BITS_TO_4BYTE(__pdesc+16, 24, 1) 285 LE_BITS_TO_4BYTE(__pdesc+16, 24, 1)
290#define GET_TX_DESC_DATA_BW(__pdesc) \ 286#define GET_TX_DESC_DATA_BW(__pdesc) \
291 LE_BITS_TO_4BYTE(__pdesc+16, 25, 1) 287 LE_BITS_TO_4BYTE(__pdesc+16, 25, 1)
292#define GET_TX_DESC_RTS_SHORT(__pdesc) \ 288#define GET_TX_DESC_RTS_SHORT(__pdesc) \
293 LE_BITS_TO_4BYTE(__pdesc+16, 26, 1) 289 LE_BITS_TO_4BYTE(__pdesc+16, 26, 1)
294#define GET_TX_DESC_RTS_BW(__pdesc) \ 290#define GET_TX_DESC_RTS_BW(__pdesc) \
295 LE_BITS_TO_4BYTE(__pdesc+16, 27, 1) 291 LE_BITS_TO_4BYTE(__pdesc+16, 27, 1)
296#define GET_TX_DESC_RTS_SC(__pdesc) \ 292#define GET_TX_DESC_RTS_SC(__pdesc) \
297 LE_BITS_TO_4BYTE(__pdesc+16, 28, 2) 293 LE_BITS_TO_4BYTE(__pdesc+16, 28, 2)
298#define GET_TX_DESC_RTS_STBC(__pdesc) \ 294#define GET_TX_DESC_RTS_STBC(__pdesc) \
299 LE_BITS_TO_4BYTE(__pdesc+16, 30, 2) 295 LE_BITS_TO_4BYTE(__pdesc+16, 30, 2)
300 296
301#define SET_TX_DESC_TX_RATE(__pdesc, __val) \ 297#define SET_TX_DESC_TX_RATE(__pdesc, __val) \
@@ -315,17 +311,17 @@
315#define SET_TX_DESC_USB_TXAGG_NUM(__pdesc, __val) \ 311#define SET_TX_DESC_USB_TXAGG_NUM(__pdesc, __val) \
316 SET_BITS_TO_LE_4BYTE(__pdesc+20, 24, 8, __val) 312 SET_BITS_TO_LE_4BYTE(__pdesc+20, 24, 8, __val)
317 313
318#define GET_TX_DESC_TX_RATE(__pdesc) \ 314#define GET_TX_DESC_TX_RATE(__pdesc) \
319 LE_BITS_TO_4BYTE(__pdesc+20, 0, 6) 315 LE_BITS_TO_4BYTE(__pdesc+20, 0, 6)
320#define GET_TX_DESC_DATA_SHORTGI(__pdesc) \ 316#define GET_TX_DESC_DATA_SHORTGI(__pdesc) \
321 LE_BITS_TO_4BYTE(__pdesc+20, 6, 1) 317 LE_BITS_TO_4BYTE(__pdesc+20, 6, 1)
322#define GET_TX_DESC_CCX_TAG(__pdesc) \ 318#define GET_TX_DESC_CCX_TAG(__pdesc) \
323 LE_BITS_TO_4BYTE(__pdesc+20, 7, 1) 319 LE_BITS_TO_4BYTE(__pdesc+20, 7, 1)
324#define GET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc) \ 320#define GET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc) \
325 LE_BITS_TO_4BYTE(__pdesc+20, 8, 5) 321 LE_BITS_TO_4BYTE(__pdesc+20, 8, 5)
326#define GET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc) \ 322#define GET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc) \
327 LE_BITS_TO_4BYTE(__pdesc+20, 13, 4) 323 LE_BITS_TO_4BYTE(__pdesc+20, 13, 4)
328#define GET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc) \ 324#define GET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc) \
329 LE_BITS_TO_4BYTE(__pdesc+20, 17, 1) 325 LE_BITS_TO_4BYTE(__pdesc+20, 17, 1)
330#define GET_TX_DESC_DATA_RETRY_LIMIT(__pdesc) \ 326#define GET_TX_DESC_DATA_RETRY_LIMIT(__pdesc) \
331 LE_BITS_TO_4BYTE(__pdesc+20, 18, 6) 327 LE_BITS_TO_4BYTE(__pdesc+20, 18, 6)
@@ -336,9 +332,9 @@
336 SET_BITS_TO_LE_4BYTE(__pdesc+24, 0, 5, __val) 332 SET_BITS_TO_LE_4BYTE(__pdesc+24, 0, 5, __val)
337#define SET_TX_DESC_TXAGC_B(__pdesc, __val) \ 333#define SET_TX_DESC_TXAGC_B(__pdesc, __val) \
338 SET_BITS_TO_LE_4BYTE(__pdesc+24, 5, 5, __val) 334 SET_BITS_TO_LE_4BYTE(__pdesc+24, 5, 5, __val)
339#define SET_TX_DESC_USE_MAX_LEN(__pdesc, __val) \ 335#define SET_TX_DESC_USE_MAX_LEN(__pdesc, __val) \
340 SET_BITS_TO_LE_4BYTE(__pdesc+24, 10, 1, __val) 336 SET_BITS_TO_LE_4BYTE(__pdesc+24, 10, 1, __val)
341#define SET_TX_DESC_MAX_AGG_NUM(__pdesc, __val) \ 337#define SET_TX_DESC_MAX_AGG_NUM(__pdesc, __val) \
342 SET_BITS_TO_LE_4BYTE(__pdesc+24, 11, 5, __val) 338 SET_BITS_TO_LE_4BYTE(__pdesc+24, 11, 5, __val)
343#define SET_TX_DESC_MCSG1_MAX_LEN(__pdesc, __val) \ 339#define SET_TX_DESC_MCSG1_MAX_LEN(__pdesc, __val) \
344 SET_BITS_TO_LE_4BYTE(__pdesc+24, 16, 4, __val) 340 SET_BITS_TO_LE_4BYTE(__pdesc+24, 16, 4, __val)
@@ -349,19 +345,19 @@
349#define SET_TX_DESC_MCS7_SGI_MAX_LEN(__pdesc, __val)\ 345#define SET_TX_DESC_MCS7_SGI_MAX_LEN(__pdesc, __val)\
350 SET_BITS_TO_LE_4BYTE(__pdesc+24, 28, 4, __val) 346 SET_BITS_TO_LE_4BYTE(__pdesc+24, 28, 4, __val)
351 347
352#define GET_TX_DESC_TXAGC_A(__pdesc) \ 348#define GET_TX_DESC_TXAGC_A(__pdesc) \
353 LE_BITS_TO_4BYTE(__pdesc+24, 0, 5) 349 LE_BITS_TO_4BYTE(__pdesc+24, 0, 5)
354#define GET_TX_DESC_TXAGC_B(__pdesc) \ 350#define GET_TX_DESC_TXAGC_B(__pdesc) \
355 LE_BITS_TO_4BYTE(__pdesc+24, 5, 5) 351 LE_BITS_TO_4BYTE(__pdesc+24, 5, 5)
356#define GET_TX_DESC_USE_MAX_LEN(__pdesc) \ 352#define GET_TX_DESC_USE_MAX_LEN(__pdesc) \
357 LE_BITS_TO_4BYTE(__pdesc+24, 10, 1) 353 LE_BITS_TO_4BYTE(__pdesc+24, 10, 1)
358#define GET_TX_DESC_MAX_AGG_NUM(__pdesc) \ 354#define GET_TX_DESC_MAX_AGG_NUM(__pdesc) \
359 LE_BITS_TO_4BYTE(__pdesc+24, 11, 5) 355 LE_BITS_TO_4BYTE(__pdesc+24, 11, 5)
360#define GET_TX_DESC_MCSG1_MAX_LEN(__pdesc) \ 356#define GET_TX_DESC_MCSG1_MAX_LEN(__pdesc) \
361 LE_BITS_TO_4BYTE(__pdesc+24, 16, 4) 357 LE_BITS_TO_4BYTE(__pdesc+24, 16, 4)
362#define GET_TX_DESC_MCSG2_MAX_LEN(__pdesc) \ 358#define GET_TX_DESC_MCSG2_MAX_LEN(__pdesc) \
363 LE_BITS_TO_4BYTE(__pdesc+24, 20, 4) 359 LE_BITS_TO_4BYTE(__pdesc+24, 20, 4)
364#define GET_TX_DESC_MCSG3_MAX_LEN(__pdesc) \ 360#define GET_TX_DESC_MCSG3_MAX_LEN(__pdesc) \
365 LE_BITS_TO_4BYTE(__pdesc+24, 24, 4) 361 LE_BITS_TO_4BYTE(__pdesc+24, 24, 4)
366#define GET_TX_DESC_MCS7_SGI_MAX_LEN(__pdesc) \ 362#define GET_TX_DESC_MCS7_SGI_MAX_LEN(__pdesc) \
367 LE_BITS_TO_4BYTE(__pdesc+24, 28, 4) 363 LE_BITS_TO_4BYTE(__pdesc+24, 28, 4)
@@ -379,11 +375,11 @@
379 375
380#define GET_TX_DESC_TX_BUFFER_SIZE(__pdesc) \ 376#define GET_TX_DESC_TX_BUFFER_SIZE(__pdesc) \
381 LE_BITS_TO_4BYTE(__pdesc+28, 0, 16) 377 LE_BITS_TO_4BYTE(__pdesc+28, 0, 16)
382#define GET_TX_DESC_MCSG4_MAX_LEN(__pdesc) \ 378#define GET_TX_DESC_MCSG4_MAX_LEN(__pdesc) \
383 LE_BITS_TO_4BYTE(__pdesc+28, 16, 4) 379 LE_BITS_TO_4BYTE(__pdesc+28, 16, 4)
384#define GET_TX_DESC_MCSG5_MAX_LEN(__pdesc) \ 380#define GET_TX_DESC_MCSG5_MAX_LEN(__pdesc) \
385 LE_BITS_TO_4BYTE(__pdesc+28, 20, 4) 381 LE_BITS_TO_4BYTE(__pdesc+28, 20, 4)
386#define GET_TX_DESC_MCSG6_MAX_LEN(__pdesc) \ 382#define GET_TX_DESC_MCSG6_MAX_LEN(__pdesc) \
387 LE_BITS_TO_4BYTE(__pdesc+28, 24, 4) 383 LE_BITS_TO_4BYTE(__pdesc+28, 24, 4)
388#define GET_TX_DESC_MCS15_SGI_MAX_LEN(__pdesc) \ 384#define GET_TX_DESC_MCS15_SGI_MAX_LEN(__pdesc) \
389 LE_BITS_TO_4BYTE(__pdesc+28, 28, 4) 385 LE_BITS_TO_4BYTE(__pdesc+28, 28, 4)
@@ -395,7 +391,7 @@
395 391
396#define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc) \ 392#define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc) \
397 LE_BITS_TO_4BYTE(__pdesc+32, 0, 32) 393 LE_BITS_TO_4BYTE(__pdesc+32, 0, 32)
398#define GET_TX_DESC_TX_BUFFER_ADDRESS64(__pdesc) \ 394#define GET_TX_DESC_TX_BUFFER_ADDRESS64(__pdesc) \
399 LE_BITS_TO_4BYTE(__pdesc+36, 0, 32) 395 LE_BITS_TO_4BYTE(__pdesc+36, 0, 32)
400 396
401#define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val) \ 397#define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val) \
@@ -410,97 +406,97 @@
410 406
411#define GET_RX_DESC_PKT_LEN(__pdesc) \ 407#define GET_RX_DESC_PKT_LEN(__pdesc) \
412 LE_BITS_TO_4BYTE(__pdesc, 0, 14) 408 LE_BITS_TO_4BYTE(__pdesc, 0, 14)
413#define GET_RX_DESC_CRC32(__pdesc) \ 409#define GET_RX_DESC_CRC32(__pdesc) \
414 LE_BITS_TO_4BYTE(__pdesc, 14, 1) 410 LE_BITS_TO_4BYTE(__pdesc, 14, 1)
415#define GET_RX_DESC_ICV(__pdesc) \ 411#define GET_RX_DESC_ICV(__pdesc) \
416 LE_BITS_TO_4BYTE(__pdesc, 15, 1) 412 LE_BITS_TO_4BYTE(__pdesc, 15, 1)
417#define GET_RX_DESC_DRV_INFO_SIZE(__pdesc) \ 413#define GET_RX_DESC_DRV_INFO_SIZE(__pdesc) \
418 LE_BITS_TO_4BYTE(__pdesc, 16, 4) 414 LE_BITS_TO_4BYTE(__pdesc, 16, 4)
419#define GET_RX_DESC_SECURITY(__pdesc) \ 415#define GET_RX_DESC_SECURITY(__pdesc) \
420 LE_BITS_TO_4BYTE(__pdesc, 20, 3) 416 LE_BITS_TO_4BYTE(__pdesc, 20, 3)
421#define GET_RX_DESC_QOS(__pdesc) \ 417#define GET_RX_DESC_QOS(__pdesc) \
422 LE_BITS_TO_4BYTE(__pdesc, 23, 1) 418 LE_BITS_TO_4BYTE(__pdesc, 23, 1)
423#define GET_RX_DESC_SHIFT(__pdesc) \ 419#define GET_RX_DESC_SHIFT(__pdesc) \
424 LE_BITS_TO_4BYTE(__pdesc, 24, 2) 420 LE_BITS_TO_4BYTE(__pdesc, 24, 2)
425#define GET_RX_DESC_PHYST(__pdesc) \ 421#define GET_RX_DESC_PHYST(__pdesc) \
426 LE_BITS_TO_4BYTE(__pdesc, 26, 1) 422 LE_BITS_TO_4BYTE(__pdesc, 26, 1)
427#define GET_RX_DESC_SWDEC(__pdesc) \ 423#define GET_RX_DESC_SWDEC(__pdesc) \
428 LE_BITS_TO_4BYTE(__pdesc, 27, 1) 424 LE_BITS_TO_4BYTE(__pdesc, 27, 1)
429#define GET_RX_DESC_LS(__pdesc) \ 425#define GET_RX_DESC_LS(__pdesc) \
430 LE_BITS_TO_4BYTE(__pdesc, 28, 1) 426 LE_BITS_TO_4BYTE(__pdesc, 28, 1)
431#define GET_RX_DESC_FS(__pdesc) \ 427#define GET_RX_DESC_FS(__pdesc) \
432 LE_BITS_TO_4BYTE(__pdesc, 29, 1) 428 LE_BITS_TO_4BYTE(__pdesc, 29, 1)
433#define GET_RX_DESC_EOR(__pdesc) \ 429#define GET_RX_DESC_EOR(__pdesc) \
434 LE_BITS_TO_4BYTE(__pdesc, 30, 1) 430 LE_BITS_TO_4BYTE(__pdesc, 30, 1)
435#define GET_RX_DESC_OWN(__pdesc) \ 431#define GET_RX_DESC_OWN(__pdesc) \
436 LE_BITS_TO_4BYTE(__pdesc, 31, 1) 432 LE_BITS_TO_4BYTE(__pdesc, 31, 1)
437 433
438#define SET_RX_DESC_PKT_LEN(__pdesc, __val) \ 434#define SET_RX_DESC_PKT_LEN(__pdesc, __val) \
439 SET_BITS_TO_LE_4BYTE(__pdesc, 0, 14, __val) 435 SET_BITS_TO_LE_4BYTE(__pdesc, 0, 14, __val)
440#define SET_RX_DESC_EOR(__pdesc, __val) \ 436#define SET_RX_DESC_EOR(__pdesc, __val) \
441 SET_BITS_TO_LE_4BYTE(__pdesc, 30, 1, __val) 437 SET_BITS_TO_LE_4BYTE(__pdesc, 30, 1, __val)
442#define SET_RX_DESC_OWN(__pdesc, __val) \ 438#define SET_RX_DESC_OWN(__pdesc, __val) \
443 SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val) 439 SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val)
444 440
445#define GET_RX_DESC_MACID(__pdesc) \ 441#define GET_RX_DESC_MACID(__pdesc) \
446 LE_BITS_TO_4BYTE(__pdesc+4, 0, 5) 442 LE_BITS_TO_4BYTE(__pdesc+4, 0, 5)
447#define GET_RX_DESC_TID(__pdesc) \ 443#define GET_RX_DESC_TID(__pdesc) \
448 LE_BITS_TO_4BYTE(__pdesc+4, 5, 4) 444 LE_BITS_TO_4BYTE(__pdesc+4, 5, 4)
449#define GET_RX_DESC_HWRSVD(__pdesc) \ 445#define GET_RX_DESC_HWRSVD(__pdesc) \
450 LE_BITS_TO_4BYTE(__pdesc+4, 9, 5) 446 LE_BITS_TO_4BYTE(__pdesc+4, 9, 5)
451#define GET_RX_DESC_PAGGR(__pdesc) \ 447#define GET_RX_DESC_PAGGR(__pdesc) \
452 LE_BITS_TO_4BYTE(__pdesc+4, 14, 1) 448 LE_BITS_TO_4BYTE(__pdesc+4, 14, 1)
453#define GET_RX_DESC_FAGGR(__pdesc) \ 449#define GET_RX_DESC_FAGGR(__pdesc) \
454 LE_BITS_TO_4BYTE(__pdesc+4, 15, 1) 450 LE_BITS_TO_4BYTE(__pdesc+4, 15, 1)
455#define GET_RX_DESC_A1_FIT(__pdesc) \ 451#define GET_RX_DESC_A1_FIT(__pdesc) \
456 LE_BITS_TO_4BYTE(__pdesc+4, 16, 4) 452 LE_BITS_TO_4BYTE(__pdesc+4, 16, 4)
457#define GET_RX_DESC_A2_FIT(__pdesc) \ 453#define GET_RX_DESC_A2_FIT(__pdesc) \
458 LE_BITS_TO_4BYTE(__pdesc+4, 20, 4) 454 LE_BITS_TO_4BYTE(__pdesc+4, 20, 4)
459#define GET_RX_DESC_PAM(__pdesc) \ 455#define GET_RX_DESC_PAM(__pdesc) \
460 LE_BITS_TO_4BYTE(__pdesc+4, 24, 1) 456 LE_BITS_TO_4BYTE(__pdesc+4, 24, 1)
461#define GET_RX_DESC_PWR(__pdesc) \ 457#define GET_RX_DESC_PWR(__pdesc) \
462 LE_BITS_TO_4BYTE(__pdesc+4, 25, 1) 458 LE_BITS_TO_4BYTE(__pdesc+4, 25, 1)
463#define GET_RX_DESC_MD(__pdesc) \ 459#define GET_RX_DESC_MD(__pdesc) \
464 LE_BITS_TO_4BYTE(__pdesc+4, 26, 1) 460 LE_BITS_TO_4BYTE(__pdesc+4, 26, 1)
465#define GET_RX_DESC_MF(__pdesc) \ 461#define GET_RX_DESC_MF(__pdesc) \
466 LE_BITS_TO_4BYTE(__pdesc+4, 27, 1) 462 LE_BITS_TO_4BYTE(__pdesc+4, 27, 1)
467#define GET_RX_DESC_TYPE(__pdesc) \ 463#define GET_RX_DESC_TYPE(__pdesc) \
468 LE_BITS_TO_4BYTE(__pdesc+4, 28, 2) 464 LE_BITS_TO_4BYTE(__pdesc+4, 28, 2)
469#define GET_RX_DESC_MC(__pdesc) \ 465#define GET_RX_DESC_MC(__pdesc) \
470 LE_BITS_TO_4BYTE(__pdesc+4, 30, 1) 466 LE_BITS_TO_4BYTE(__pdesc+4, 30, 1)
471#define GET_RX_DESC_BC(__pdesc) \ 467#define GET_RX_DESC_BC(__pdesc) \
472 LE_BITS_TO_4BYTE(__pdesc+4, 31, 1) 468 LE_BITS_TO_4BYTE(__pdesc+4, 31, 1)
473#define GET_RX_DESC_SEQ(__pdesc) \ 469#define GET_RX_DESC_SEQ(__pdesc) \
474 LE_BITS_TO_4BYTE(__pdesc+8, 0, 12) 470 LE_BITS_TO_4BYTE(__pdesc+8, 0, 12)
475#define GET_RX_DESC_FRAG(__pdesc) \ 471#define GET_RX_DESC_FRAG(__pdesc) \
476 LE_BITS_TO_4BYTE(__pdesc+8, 12, 4) 472 LE_BITS_TO_4BYTE(__pdesc+8, 12, 4)
477#define GET_RX_DESC_NEXT_PKT_LEN(__pdesc) \ 473#define GET_RX_DESC_NEXT_PKT_LEN(__pdesc) \
478 LE_BITS_TO_4BYTE(__pdesc+8, 16, 14) 474 LE_BITS_TO_4BYTE(__pdesc+8, 16, 14)
479#define GET_RX_DESC_NEXT_IND(__pdesc) \ 475#define GET_RX_DESC_NEXT_IND(__pdesc) \
480 LE_BITS_TO_4BYTE(__pdesc+8, 30, 1) 476 LE_BITS_TO_4BYTE(__pdesc+8, 30, 1)
481#define GET_RX_DESC_RSVD(__pdesc) \ 477#define GET_RX_DESC_RSVD(__pdesc) \
482 LE_BITS_TO_4BYTE(__pdesc+8, 31, 1) 478 LE_BITS_TO_4BYTE(__pdesc+8, 31, 1)
483 479
484#define GET_RX_DESC_RXMCS(__pdesc) \ 480#define GET_RX_DESC_RXMCS(__pdesc) \
485 LE_BITS_TO_4BYTE(__pdesc+12, 0, 6) 481 LE_BITS_TO_4BYTE(__pdesc+12, 0, 6)
486#define GET_RX_DESC_RXHT(__pdesc) \ 482#define GET_RX_DESC_RXHT(__pdesc) \
487 LE_BITS_TO_4BYTE(__pdesc+12, 6, 1) 483 LE_BITS_TO_4BYTE(__pdesc+12, 6, 1)
488#define GET_RX_DESC_SPLCP(__pdesc) \ 484#define GET_RX_DESC_SPLCP(__pdesc) \
489 LE_BITS_TO_4BYTE(__pdesc+12, 8, 1) 485 LE_BITS_TO_4BYTE(__pdesc+12, 8, 1)
490#define GET_RX_DESC_BW(__pdesc) \ 486#define GET_RX_DESC_BW(__pdesc) \
491 LE_BITS_TO_4BYTE(__pdesc+12, 9, 1) 487 LE_BITS_TO_4BYTE(__pdesc+12, 9, 1)
492#define GET_RX_DESC_HTC(__pdesc) \ 488#define GET_RX_DESC_HTC(__pdesc) \
493 LE_BITS_TO_4BYTE(__pdesc+12, 10, 1) 489 LE_BITS_TO_4BYTE(__pdesc+12, 10, 1)
494#define GET_RX_DESC_HWPC_ERR(__pdesc) \ 490#define GET_RX_DESC_HWPC_ERR(__pdesc) \
495 LE_BITS_TO_4BYTE(__pdesc+12, 14, 1) 491 LE_BITS_TO_4BYTE(__pdesc+12, 14, 1)
496#define GET_RX_DESC_HWPC_IND(__pdesc) \ 492#define GET_RX_DESC_HWPC_IND(__pdesc) \
497 LE_BITS_TO_4BYTE(__pdesc+12, 15, 1) 493 LE_BITS_TO_4BYTE(__pdesc+12, 15, 1)
498#define GET_RX_DESC_IV0(__pdesc) \ 494#define GET_RX_DESC_IV0(__pdesc) \
499 LE_BITS_TO_4BYTE(__pdesc+12, 16, 16) 495 LE_BITS_TO_4BYTE(__pdesc+12, 16, 16)
500 496
501#define GET_RX_DESC_IV1(__pdesc) \ 497#define GET_RX_DESC_IV1(__pdesc) \
502 LE_BITS_TO_4BYTE(__pdesc+16, 0, 32) 498 LE_BITS_TO_4BYTE(__pdesc+16, 0, 32)
503#define GET_RX_DESC_TSFL(__pdesc) \ 499#define GET_RX_DESC_TSFL(__pdesc) \
504 LE_BITS_TO_4BYTE(__pdesc+20, 0, 32) 500 LE_BITS_TO_4BYTE(__pdesc+20, 0, 32)
505 501
506#define GET_RX_DESC_BUFF_ADDR(__pdesc) \ 502#define GET_RX_DESC_BUFF_ADDR(__pdesc) \
@@ -508,17 +504,17 @@
508#define GET_RX_DESC_BUFF_ADDR64(__pdesc) \ 504#define GET_RX_DESC_BUFF_ADDR64(__pdesc) \
509 LE_BITS_TO_4BYTE(__pdesc+28, 0, 32) 505 LE_BITS_TO_4BYTE(__pdesc+28, 0, 32)
510 506
511#define SET_RX_DESC_BUFF_ADDR(__pdesc, __val) \ 507#define SET_RX_DESC_BUFF_ADDR(__pdesc, __val) \
512 SET_BITS_TO_LE_4BYTE(__pdesc+24, 0, 32, __val) 508 SET_BITS_TO_LE_4BYTE(__pdesc+24, 0, 32, __val)
513#define SET_RX_DESC_BUFF_ADDR64(__pdesc, __val) \ 509#define SET_RX_DESC_BUFF_ADDR64(__pdesc, __val) \
514 SET_BITS_TO_LE_4BYTE(__pdesc+28, 0, 32, __val) 510 SET_BITS_TO_LE_4BYTE(__pdesc+28, 0, 32, __val)
515 511
516#define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \ 512#define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \
517do { \ 513do { \
518 if (_size > TX_DESC_NEXT_DESC_OFFSET) \ 514 if (_size > TX_DESC_NEXT_DESC_OFFSET) \
519 memset(__pdesc, 0, TX_DESC_NEXT_DESC_OFFSET); \ 515 memset(__pdesc, 0, TX_DESC_NEXT_DESC_OFFSET); \
520 else \ 516 else \
521 memset(__pdesc, 0, _size); \ 517 memset(__pdesc, 0, _size); \
522} while (0) 518} while (0)
523 519
524struct rx_fwinfo_8723e { 520struct rx_fwinfo_8723e {
@@ -699,22 +695,27 @@ struct rx_desc_8723e {
699 695
700} __packed; 696} __packed;
701 697
702void rtl8723ae_tx_fill_desc(struct ieee80211_hw *hw, 698void rtl8723e_tx_fill_desc(struct ieee80211_hw *hw,
703 struct ieee80211_hdr *hdr, u8 *pdesc, 699 struct ieee80211_hdr *hdr,
704 u8 *pbd_desc_tx, struct ieee80211_tx_info *info, 700 u8 *pdesc, u8 *txbd,
705 struct ieee80211_sta *sta, 701 struct ieee80211_tx_info *info,
706 struct sk_buff *skb, u8 hw_queue, 702 struct ieee80211_sta *sta,
707 struct rtl_tcb_desc *ptcb_desc); 703 struct sk_buff *skb, u8 hw_queue,
708bool rtl8723ae_rx_query_desc(struct ieee80211_hw *hw, 704 struct rtl_tcb_desc *ptcb_desc);
709 struct rtl_stats *status, 705bool rtl8723e_rx_query_desc(struct ieee80211_hw *hw,
710 struct ieee80211_rx_status *rx_status, 706 struct rtl_stats *status,
711 u8 *pdesc, struct sk_buff *skb); 707 struct ieee80211_rx_status *rx_status,
712void rtl8723ae_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx, 708 u8 *pdesc, struct sk_buff *skb);
713 u8 desc_name, u8 *val); 709void rtl8723e_set_desc(struct ieee80211_hw *hw,
714u32 rtl8723ae_get_desc(u8 *pdesc, bool istx, u8 desc_name); 710 u8 *pdesc, bool istx, u8 desc_name, u8 *val);
715void rtl8723ae_tx_polling(struct ieee80211_hw *hw, u8 hw_queue); 711u32 rtl8723e_get_desc(u8 *pdesc, bool istx, u8 desc_name);
716void rtl8723ae_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc, 712bool rtl8723e_is_tx_desc_closed(struct ieee80211_hw *hw,
717 bool b_firstseg, bool b_lastseg, 713 u8 hw_queue, u16 index);
714void rtl8723e_tx_polling(struct ieee80211_hw *hw, u8 hw_queue);
715void rtl8723e_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
716 bool firstseg, bool lastseg,
717 struct sk_buff *skb);
718u32 rtl8723e_rx_command_packet(struct ieee80211_hw *hw,
719 struct rtl_stats status,
718 struct sk_buff *skb); 720 struct sk_buff *skb);
719
720#endif 721#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8723be/hw.c b/drivers/net/wireless/rtlwifi/rtl8723be/hw.c
index c0689c1d8d76..d296b5ca9db1 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723be/hw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723be/hw.c
@@ -1015,7 +1015,7 @@ int rtl8723be_hw_init(struct ieee80211_hw *hw)
1015 tmp_u1b &= 0x7F; 1015 tmp_u1b &= 0x7F;
1016 rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b); 1016 rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b);
1017 1017
1018 err = rtl8723_download_fw(hw, true); 1018 err = rtl8723_download_fw(hw, true, FW_8192C_POLLING_TIMEOUT_COUNT);
1019 if (err) { 1019 if (err) {
1020 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1020 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1021 "Failed to download FW. Init HW without FW now..\n"); 1021 "Failed to download FW. Init HW without FW now..\n");
diff --git a/drivers/net/wireless/rtlwifi/rtl8723be/sw.c b/drivers/net/wireless/rtlwifi/rtl8723be/sw.c
index 532913c6622a..8b4a5f3e8e82 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723be/sw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723be/sw.c
@@ -196,7 +196,7 @@ bool rtl8723be_get_btc_status(void)
196 return true; 196 return true;
197} 197}
198 198
199static bool is_fw_header(struct rtl92c_firmware_header *hdr) 199static bool is_fw_header(struct rtl8723e_firmware_header *hdr)
200{ 200{
201 return (hdr->signature & 0xfff0) == 0x5300; 201 return (hdr->signature & 0xfff0) == 0x5300;
202} 202}
diff --git a/drivers/net/wireless/rtlwifi/rtl8723com/dm_common.c b/drivers/net/wireless/rtlwifi/rtl8723com/dm_common.c
index 4e254b72bf45..064340641913 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723com/dm_common.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723com/dm_common.c
@@ -44,7 +44,6 @@ EXPORT_SYMBOL_GPL(rtl8723_dm_init_dynamic_txpower);
44void rtl8723_dm_init_edca_turbo(struct ieee80211_hw *hw) 44void rtl8723_dm_init_edca_turbo(struct ieee80211_hw *hw)
45{ 45{
46 struct rtl_priv *rtlpriv = rtl_priv(hw); 46 struct rtl_priv *rtlpriv = rtl_priv(hw);
47
48 rtlpriv->dm.current_turbo_edca = false; 47 rtlpriv->dm.current_turbo_edca = false;
49 rtlpriv->dm.is_any_nonbepkts = false; 48 rtlpriv->dm.is_any_nonbepkts = false;
50 rtlpriv->dm.is_cur_rdlstate = false; 49 rtlpriv->dm.is_cur_rdlstate = false;
@@ -54,12 +53,13 @@ EXPORT_SYMBOL_GPL(rtl8723_dm_init_edca_turbo);
54void rtl8723_dm_init_dynamic_bb_powersaving(struct ieee80211_hw *hw) 53void rtl8723_dm_init_dynamic_bb_powersaving(struct ieee80211_hw *hw)
55{ 54{
56 struct rtl_priv *rtlpriv = rtl_priv(hw); 55 struct rtl_priv *rtlpriv = rtl_priv(hw);
56 struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
57 57
58 rtlpriv->dm_pstable.pre_ccastate = CCA_MAX; 58 dm_pstable->pre_ccastate = CCA_MAX;
59 rtlpriv->dm_pstable.cur_ccasate = CCA_MAX; 59 dm_pstable->cur_ccasate = CCA_MAX;
60 rtlpriv->dm_pstable.pre_rfstate = RF_MAX; 60 dm_pstable->pre_rfstate = RF_MAX;
61 rtlpriv->dm_pstable.cur_rfstate = RF_MAX; 61 dm_pstable->cur_rfstate = RF_MAX;
62 rtlpriv->dm_pstable.rssi_val_min = 0; 62 dm_pstable->rssi_val_min = 0;
63 rtlpriv->dm_pstable.initialize = 0; 63 dm_pstable->initialize = 0;
64} 64}
65EXPORT_SYMBOL_GPL(rtl8723_dm_init_dynamic_bb_powersaving); 65EXPORT_SYMBOL_GPL(rtl8723_dm_init_dynamic_bb_powersaving);
diff --git a/drivers/net/wireless/rtlwifi/rtl8723com/fw_common.c b/drivers/net/wireless/rtlwifi/rtl8723com/fw_common.c
index 540278ff462b..6f35506a8fd2 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723com/fw_common.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723com/fw_common.c
@@ -36,7 +36,8 @@ void rtl8723_enable_fw_download(struct ieee80211_hw *hw, bool enable)
36 36
37 if (enable) { 37 if (enable) {
38 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 38 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
39 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp | 0x04); 39 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1,
40 tmp | 0x04);
40 41
41 tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL); 42 tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
42 rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp | 0x01); 43 rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp | 0x01);
@@ -95,7 +96,7 @@ void rtl8723_fw_page_write(struct ieee80211_hw *hw,
95} 96}
96EXPORT_SYMBOL_GPL(rtl8723_fw_page_write); 97EXPORT_SYMBOL_GPL(rtl8723_fw_page_write);
97 98
98static void rtl8723_fill_dummy(u8 *pfwbuf, u32 *pfwlen) 99void rtl8723_fill_dummy(u8 *pfwbuf, u32 *pfwlen)
99{ 100{
100 u32 fwlen = *pfwlen; 101 u32 fwlen = *pfwlen;
101 u8 remain = (u8) (fwlen % 4); 102 u8 remain = (u8) (fwlen % 4);
@@ -109,60 +110,64 @@ static void rtl8723_fill_dummy(u8 *pfwbuf, u32 *pfwlen)
109 } 110 }
110 *pfwlen = fwlen; 111 *pfwlen = fwlen;
111} 112}
113EXPORT_SYMBOL(rtl8723_fill_dummy);
112 114
113void rtl8723_write_fw(struct ieee80211_hw *hw, 115void rtl8723_write_fw(struct ieee80211_hw *hw,
114 enum version_8723e version, 116 enum version_8723e version,
115 u8 *buffer, u32 size) 117 u8 *buffer, u32 size, u8 max_page)
116{ 118{
117 struct rtl_priv *rtlpriv = rtl_priv(hw); 119 struct rtl_priv *rtlpriv = rtl_priv(hw);
118 u8 *bufferptr = buffer; 120 u8 *bufferptr = buffer;
119 u32 pagenums, remainsize; 121 u32 page_nums, remain_size;
120 u32 page, offset; 122 u32 page, offset;
121 123
122 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "FW size is %d bytes,\n", size); 124 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE, "FW size is %d bytes,\n", size);
123 125
124 rtl8723_fill_dummy(bufferptr, &size); 126 rtl8723_fill_dummy(bufferptr, &size);
125 127
126 pagenums = size / FW_8192C_PAGE_SIZE; 128 page_nums = size / FW_8192C_PAGE_SIZE;
127 remainsize = size % FW_8192C_PAGE_SIZE; 129 remain_size = size % FW_8192C_PAGE_SIZE;
128 130
129 if (pagenums > 8) { 131 if (page_nums > max_page) {
130 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 132 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
131 "Page numbers should not greater then 8\n"); 133 "Page numbers should not greater than %d\n", max_page);
132 } 134 }
133 for (page = 0; page < pagenums; page++) { 135 for (page = 0; page < page_nums; page++) {
134 offset = page * FW_8192C_PAGE_SIZE; 136 offset = page * FW_8192C_PAGE_SIZE;
135 rtl8723_fw_page_write(hw, page, (bufferptr + offset), 137 rtl8723_fw_page_write(hw, page, (bufferptr + offset),
136 FW_8192C_PAGE_SIZE); 138 FW_8192C_PAGE_SIZE);
137 } 139 }
138 if (remainsize) { 140
139 offset = pagenums * FW_8192C_PAGE_SIZE; 141 if (remain_size) {
140 page = pagenums; 142 offset = page_nums * FW_8192C_PAGE_SIZE;
143 page = page_nums;
141 rtl8723_fw_page_write(hw, page, (bufferptr + offset), 144 rtl8723_fw_page_write(hw, page, (bufferptr + offset),
142 remainsize); 145 remain_size);
143 } 146 }
147 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE, "FW write done.\n");
144} 148}
145EXPORT_SYMBOL_GPL(rtl8723_write_fw); 149EXPORT_SYMBOL_GPL(rtl8723_write_fw);
146 150
147void rtl8723ae_firmware_selfreset(struct ieee80211_hw *hw) 151void rtl8723ae_firmware_selfreset(struct ieee80211_hw *hw)
148{ 152{
149 u8 u1tmp; 153 u8 u1b_tmp;
150 u8 delay = 100; 154 u8 delay = 100;
151 struct rtl_priv *rtlpriv = rtl_priv(hw); 155 struct rtl_priv *rtlpriv = rtl_priv(hw);
152 156
153 rtl_write_byte(rtlpriv, REG_HMETFR + 3, 0x20); 157 rtl_write_byte(rtlpriv, REG_HMETFR + 3, 0x20);
154 u1tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 158 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
155 159
156 while (u1tmp & BIT(2)) { 160 while (u1b_tmp & BIT(2)) {
157 delay--; 161 delay--;
158 if (delay == 0) 162 if (delay == 0)
159 break; 163 break;
160 udelay(50); 164 udelay(50);
161 u1tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 165 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
162 } 166 }
163 if (delay == 0) { 167 if (delay == 0) {
164 u1tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 168 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
165 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, u1tmp&(~BIT(2))); 169 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1,
170 u1b_tmp&(~BIT(2)));
166 } 171 }
167} 172}
168EXPORT_SYMBOL_GPL(rtl8723ae_firmware_selfreset); 173EXPORT_SYMBOL_GPL(rtl8723ae_firmware_selfreset);
@@ -190,7 +195,8 @@ void rtl8723be_firmware_selfreset(struct ieee80211_hw *hw)
190} 195}
191EXPORT_SYMBOL_GPL(rtl8723be_firmware_selfreset); 196EXPORT_SYMBOL_GPL(rtl8723be_firmware_selfreset);
192 197
193int rtl8723_fw_free_to_go(struct ieee80211_hw *hw, bool is_8723be) 198int rtl8723_fw_free_to_go(struct ieee80211_hw *hw, bool is_8723be,
199 int max_count)
194{ 200{
195 struct rtl_priv *rtlpriv = rtl_priv(hw); 201 struct rtl_priv *rtlpriv = rtl_priv(hw);
196 int err = -EIO; 202 int err = -EIO;
@@ -199,10 +205,10 @@ int rtl8723_fw_free_to_go(struct ieee80211_hw *hw, bool is_8723be)
199 205
200 do { 206 do {
201 value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL); 207 value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
202 } while ((counter++ < FW_8192C_POLLING_TIMEOUT_COUNT) && 208 } while ((counter++ < max_count) &&
203 (!(value32 & FWDL_CHKSUM_RPT))); 209 (!(value32 & FWDL_CHKSUM_RPT)));
204 210
205 if (counter >= FW_8192C_POLLING_TIMEOUT_COUNT) { 211 if (counter >= max_count) {
206 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 212 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
207 "chksum report fail ! REG_MCUFWDL:0x%08x .\n", 213 "chksum report fail ! REG_MCUFWDL:0x%08x .\n",
208 value32); 214 value32);
@@ -223,15 +229,15 @@ int rtl8723_fw_free_to_go(struct ieee80211_hw *hw, bool is_8723be)
223 value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL); 229 value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
224 if (value32 & WINTINI_RDY) { 230 if (value32 & WINTINI_RDY) {
225 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE, 231 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
226 "Polling FW ready success!! " 232 "Polling FW ready success!! REG_MCUFWDL:0x%08x .\n",
227 "REG_MCUFWDL:0x%08x .\n",
228 value32); 233 value32);
229 err = 0; 234 err = 0;
230 goto exit; 235 goto exit;
231 } 236 }
232 udelay(FW_8192C_POLLING_DELAY);
233 237
234 } while (counter++ < FW_8192C_POLLING_TIMEOUT_COUNT); 238 mdelay(FW_8192C_POLLING_DELAY);
239
240 } while (counter++ < max_count);
235 241
236 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 242 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
237 "Polling FW ready fail!! REG_MCUFWDL:0x%08x .\n", 243 "Polling FW ready fail!! REG_MCUFWDL:0x%08x .\n",
@@ -243,25 +249,28 @@ exit:
243EXPORT_SYMBOL_GPL(rtl8723_fw_free_to_go); 249EXPORT_SYMBOL_GPL(rtl8723_fw_free_to_go);
244 250
245int rtl8723_download_fw(struct ieee80211_hw *hw, 251int rtl8723_download_fw(struct ieee80211_hw *hw,
246 bool is_8723be) 252 bool is_8723be, int max_count)
247{ 253{
248 struct rtl_priv *rtlpriv = rtl_priv(hw); 254 struct rtl_priv *rtlpriv = rtl_priv(hw);
249 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 255 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
250 struct rtl92c_firmware_header *pfwheader; 256 struct rtl8723e_firmware_header *pfwheader;
251 u8 *pfwdata; 257 u8 *pfwdata;
252 u32 fwsize; 258 u32 fwsize;
253 int err; 259 int err;
254 enum version_8723e version = rtlhal->version; 260 enum version_8723e version = rtlhal->version;
261 int max_page;
255 262
256 if (!rtlhal->pfirmware) 263 if (!rtlhal->pfirmware)
257 return 1; 264 return 1;
258 265
259 pfwheader = (struct rtl92c_firmware_header *)rtlhal->pfirmware; 266 pfwheader = (struct rtl8723e_firmware_header *)rtlhal->pfirmware;
260 pfwdata = rtlhal->pfirmware; 267 pfwdata = rtlhal->pfirmware;
261 fwsize = rtlhal->fwsize; 268 fwsize = rtlhal->fwsize;
262 RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
263 "normal Firmware SIZE %d\n", fwsize);
264 269
270 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE)
271 max_page = 6;
272 else
273 max_page = 8;
265 if (rtlpriv->cfg->ops->is_fw_header(pfwheader)) { 274 if (rtlpriv->cfg->ops->is_fw_header(pfwheader)) {
266 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, 275 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD,
267 "Firmware Version(%d), Signature(%#x), Size(%d)\n", 276 "Firmware Version(%d), Signature(%#x), Size(%d)\n",
@@ -271,23 +280,24 @@ int rtl8723_download_fw(struct ieee80211_hw *hw,
271 pfwdata = pfwdata + sizeof(struct rtl92c_firmware_header); 280 pfwdata = pfwdata + sizeof(struct rtl92c_firmware_header);
272 fwsize = fwsize - sizeof(struct rtl92c_firmware_header); 281 fwsize = fwsize - sizeof(struct rtl92c_firmware_header);
273 } 282 }
274 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) { 283
275 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0); 284 if (rtl_read_byte(rtlpriv, REG_MCUFWDL)&BIT(7)) {
276 if (is_8723be) 285 if (is_8723be)
277 rtl8723be_firmware_selfreset(hw); 286 rtl8723be_firmware_selfreset(hw);
278 else 287 else
279 rtl8723ae_firmware_selfreset(hw); 288 rtl8723ae_firmware_selfreset(hw);
289 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
280 } 290 }
281 rtl8723_enable_fw_download(hw, true); 291 rtl8723_enable_fw_download(hw, true);
282 rtl8723_write_fw(hw, version, pfwdata, fwsize); 292 rtl8723_write_fw(hw, version, pfwdata, fwsize, max_page);
283 rtl8723_enable_fw_download(hw, false); 293 rtl8723_enable_fw_download(hw, false);
284 294
285 err = rtl8723_fw_free_to_go(hw, is_8723be); 295 err = rtl8723_fw_free_to_go(hw, is_8723be, max_count);
286 if (err) { 296 if (err) {
287 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 297 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
288 "Firmware is not ready to run!\n"); 298 "Firmware is not ready to run!\n");
289 } else { 299 } else {
290 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, 300 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
291 "Firmware is ready to run!\n"); 301 "Firmware is ready to run!\n");
292 } 302 }
293 return 0; 303 return 0;
diff --git a/drivers/net/wireless/rtlwifi/rtl8723com/fw_common.h b/drivers/net/wireless/rtlwifi/rtl8723com/fw_common.h
index cf1cc5804d06..f9bab10d4726 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723com/fw_common.h
+++ b/drivers/net/wireless/rtlwifi/rtl8723com/fw_common.h
@@ -30,7 +30,7 @@
30#define REG_MCUFWDL 0x0080 30#define REG_MCUFWDL 0x0080
31#define FW_8192C_START_ADDRESS 0x1000 31#define FW_8192C_START_ADDRESS 0x1000
32#define FW_8192C_PAGE_SIZE 4096 32#define FW_8192C_PAGE_SIZE 4096
33#define FW_8192C_POLLING_TIMEOUT_COUNT 6000 33#define FW_8723A_POLLING_TIMEOUT_COUNT 6000
34#define FW_8192C_POLLING_DELAY 5 34#define FW_8192C_POLLING_DELAY 5
35 35
36#define MCUFWDL_RDY BIT(1) 36#define MCUFWDL_RDY BIT(1)
@@ -49,16 +49,23 @@ enum version_8723e {
49 VERSION_UNKNOWN = 0xFF, 49 VERSION_UNKNOWN = 0xFF,
50}; 50};
51 51
52enum rtl8723ae_h2c_cmd { 52struct rtl8723e_firmware_header {
53 H2C_AP_OFFLOAD = 0, 53 u16 signature;
54 H2C_SETPWRMODE = 1, 54 u8 category;
55 H2C_JOINBSSRPT = 2, 55 u8 function;
56 H2C_RSVDPAGE = 3, 56 u16 version;
57 H2C_RSSI_REPORT = 4, 57 u8 subversion;
58 H2C_P2P_PS_CTW_CMD = 5, 58 u8 rsvd1;
59 H2C_P2P_PS_OFFLOAD = 6, 59 u8 month;
60 H2C_RA_MASK = 7, 60 u8 date;
61 MAX_H2CCMD 61 u8 hour;
62 u8 minute;
63 u16 ramcodesize;
64 u16 rsvd2;
65 u32 svnindex;
66 u32 rsvd3;
67 u32 rsvd4;
68 u32 rsvd5;
62}; 69};
63 70
64enum rtl8723be_cmd { 71enum rtl8723be_cmd {
@@ -120,7 +127,11 @@ void rtl8723_fw_page_write(struct ieee80211_hw *hw,
120 u32 page, const u8 *buffer, u32 size); 127 u32 page, const u8 *buffer, u32 size);
121void rtl8723_write_fw(struct ieee80211_hw *hw, 128void rtl8723_write_fw(struct ieee80211_hw *hw,
122 enum version_8723e version, 129 enum version_8723e version,
123 u8 *buffer, u32 size); 130 u8 *buffer, u32 size, u8 max_page);
124int rtl8723_fw_free_to_go(struct ieee80211_hw *hw, bool is_8723be); 131int rtl8723_fw_free_to_go(struct ieee80211_hw *hw, bool is_8723be, int count);
125int rtl8723_download_fw(struct ieee80211_hw *hw, bool is_8723be); 132int rtl8723_download_fw(struct ieee80211_hw *hw, bool is_8723be, int count);
133bool rtl8723_cmd_send_packet(struct ieee80211_hw *hw,
134 struct sk_buff *skb);
135void rtl8723_fill_dummy(u8 *pfwbuf, u32 *pfwlen);
136
126#endif 137#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8723com/phy_common.c b/drivers/net/wireless/rtlwifi/rtl8723com/phy_common.c
index d73b659bd2b5..56aff32b9c56 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723com/phy_common.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723com/phy_common.c
@@ -43,9 +43,8 @@ u32 rtl8723_phy_query_bb_reg(struct ieee80211_hw *hw,
43 returnvalue = (originalvalue & bitmask) >> bitshift; 43 returnvalue = (originalvalue & bitmask) >> bitshift;
44 44
45 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 45 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
46 "BBR MASK = 0x%x Addr[0x%x]= 0x%x\n", 46 "BBR MASK=0x%x Addr[0x%x]=0x%x\n", bitmask,
47 bitmask, regaddr, originalvalue); 47 regaddr, originalvalue);
48
49 return returnvalue; 48 return returnvalue;
50} 49}
51EXPORT_SYMBOL_GPL(rtl8723_phy_query_bb_reg); 50EXPORT_SYMBOL_GPL(rtl8723_phy_query_bb_reg);
@@ -57,8 +56,8 @@ void rtl8723_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr,
57 u32 originalvalue, bitshift; 56 u32 originalvalue, bitshift;
58 57
59 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 58 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
60 "regaddr(%#x), bitmask(%#x), data(%#x)\n", 59 "regaddr(%#x), bitmask(%#x), data(%#x)\n", regaddr, bitmask,
61 regaddr, bitmask, data); 60 data);
62 61
63 if (bitmask != MASKDWORD) { 62 if (bitmask != MASKDWORD) {
64 originalvalue = rtl_read_dword(rtlpriv, regaddr); 63 originalvalue = rtl_read_dword(rtlpriv, regaddr);
@@ -70,7 +69,7 @@ void rtl8723_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr,
70 69
71 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 70 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
72 "regaddr(%#x), bitmask(%#x), data(%#x)\n", 71 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
73 regaddr, bitmask, data); 72 regaddr, bitmask, data);
74} 73}
75EXPORT_SYMBOL_GPL(rtl8723_phy_set_bb_reg); 74EXPORT_SYMBOL_GPL(rtl8723_phy_set_bb_reg);
76 75
@@ -97,7 +96,7 @@ u32 rtl8723_phy_rf_serial_read(struct ieee80211_hw *hw,
97 u8 rfpi_enable = 0; 96 u8 rfpi_enable = 0;
98 u32 retvalue; 97 u32 retvalue;
99 98
100 offset &= 0xff; 99 offset &= 0x3f;
101 newoffset = offset; 100 newoffset = offset;
102 if (RT_CANNOT_IO(hw)) { 101 if (RT_CANNOT_IO(hw)) {
103 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "return all one\n"); 102 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "return all one\n");
@@ -109,12 +108,15 @@ u32 rtl8723_phy_rf_serial_read(struct ieee80211_hw *hw,
109 else 108 else
110 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD); 109 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
111 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) | 110 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
112 (newoffset << 23) | BLSSIREADEDGE; 111 (newoffset << 23) | BLSSIREADEDGE;
113 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, 112 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
114 tmplong & (~BLSSIREADEDGE)); 113 tmplong & (~BLSSIREADEDGE));
115 mdelay(1); 114 mdelay(1);
116 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); 115 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
117 mdelay(2); 116 mdelay(1);
117 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
118 tmplong | BLSSIREADEDGE);
119 mdelay(1);
118 if (rfpath == RF90_PATH_A) 120 if (rfpath == RF90_PATH_A)
119 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, 121 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
120 BIT(8)); 122 BIT(8));
@@ -128,8 +130,8 @@ u32 rtl8723_phy_rf_serial_read(struct ieee80211_hw *hw,
128 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb, 130 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
129 BLSSIREADBACKDATA); 131 BLSSIREADBACKDATA);
130 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 132 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
131 "RFR-%d Addr[0x%x]= 0x%x\n", 133 "RFR-%d Addr[0x%x]=0x%x\n",
132 rfpath, pphyreg->rf_rb, retvalue); 134 rfpath, pphyreg->rf_rb, retvalue);
133 return retvalue; 135 return retvalue;
134} 136}
135EXPORT_SYMBOL_GPL(rtl8723_phy_rf_serial_read); 137EXPORT_SYMBOL_GPL(rtl8723_phy_rf_serial_read);
@@ -148,13 +150,14 @@ void rtl8723_phy_rf_serial_write(struct ieee80211_hw *hw,
148 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "stop\n"); 150 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "stop\n");
149 return; 151 return;
150 } 152 }
151 offset &= 0xff; 153 offset &= 0x3f;
152 newoffset = offset; 154 newoffset = offset;
153 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; 155 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
154 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); 156 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
155 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 157 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
156 "RFW-%d Addr[0x%x]= 0x%x\n", rfpath, 158 "RFW-%d Addr[0x%x]=0x%x\n",
157 pphyreg->rf3wire_offset, data_and_addr); 159 rfpath, pphyreg->rf3wire_offset,
160 data_and_addr);
158} 161}
159EXPORT_SYMBOL_GPL(rtl8723_phy_rf_serial_write); 162EXPORT_SYMBOL_GPL(rtl8723_phy_rf_serial_write);
160 163
@@ -171,6 +174,8 @@ long rtl8723_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
171 break; 174 break;
172 case WIRELESS_MODE_G: 175 case WIRELESS_MODE_G:
173 case WIRELESS_MODE_N_24G: 176 case WIRELESS_MODE_N_24G:
177 offset = -8;
178 break;
174 default: 179 default:
175 offset = -8; 180 offset = -8;
176 break; 181 break;
@@ -202,14 +207,14 @@ void rtl8723_phy_init_bb_rf_reg_def(struct ieee80211_hw *hw)
202 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE; 207 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
203 208
204 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset = 209 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
205 RFPGA0_XA_LSSIPARAMETER; 210 RFPGA0_XA_LSSIPARAMETER;
206 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset = 211 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
207 RFPGA0_XB_LSSIPARAMETER; 212 RFPGA0_XB_LSSIPARAMETER;
208 213
209 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = rFPGA0_XAB_RFPARAMETER; 214 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
210 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = rFPGA0_XAB_RFPARAMETER; 215 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
211 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = rFPGA0_XCD_RFPARAMETER; 216 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
212 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = rFPGA0_XCD_RFPARAMETER; 217 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
213 218
214 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE; 219 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
215 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE; 220 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
@@ -264,6 +269,7 @@ void rtl8723_phy_init_bb_rf_reg_def(struct ieee80211_hw *hw)
264 269
265 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK; 270 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK;
266 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK; 271 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK;
272
267} 273}
268EXPORT_SYMBOL_GPL(rtl8723_phy_init_bb_rf_reg_def); 274EXPORT_SYMBOL_GPL(rtl8723_phy_init_bb_rf_reg_def);
269 275
diff --git a/drivers/net/wireless/rtlwifi/wifi.h b/drivers/net/wireless/rtlwifi/wifi.h
index b2a2f5110efe..e34b8eaa9ba7 100644
--- a/drivers/net/wireless/rtlwifi/wifi.h
+++ b/drivers/net/wireless/rtlwifi/wifi.h
@@ -143,6 +143,21 @@
143#define FCS_LEN 4 143#define FCS_LEN 4
144#define EM_HDR_LEN 8 144#define EM_HDR_LEN 8
145 145
146enum rtl8192c_h2c_cmd {
147 H2C_AP_OFFLOAD = 0,
148 H2C_SETPWRMODE = 1,
149 H2C_JOINBSSRPT = 2,
150 H2C_RSVDPAGE = 3,
151 H2C_RSSI_REPORT = 5,
152 H2C_RA_MASK = 6,
153 H2C_MACID_PS_MODE = 7,
154 H2C_P2P_PS_OFFLOAD = 8,
155 H2C_MAC_MODE_SEL = 9,
156 H2C_PWRM = 15,
157 H2C_P2P_PS_CTW_CMD = 24,
158 MAX_H2CCMD
159};
160
146#define MAX_TX_COUNT 4 161#define MAX_TX_COUNT 4
147#define MAX_REGULATION_NUM 4 162#define MAX_REGULATION_NUM 4
148#define MAX_RF_PATH_NUM 4 163#define MAX_RF_PATH_NUM 4
@@ -2041,6 +2056,8 @@ struct rtl_wow_pattern {
2041 u32 mask[4]; 2056 u32 mask[4];
2042}; 2057};
2043 2058
2059struct rtl8723e_firmware_header;
2060
2044struct rtl_hal_ops { 2061struct rtl_hal_ops {
2045 int (*init_sw_vars) (struct ieee80211_hw *hw); 2062 int (*init_sw_vars) (struct ieee80211_hw *hw);
2046 void (*deinit_sw_vars) (struct ieee80211_hw *hw); 2063 void (*deinit_sw_vars) (struct ieee80211_hw *hw);
@@ -2145,7 +2162,7 @@ struct rtl_hal_ops {
2145 void (*fill_h2c_cmd) (struct ieee80211_hw *hw, u8 element_id, 2162 void (*fill_h2c_cmd) (struct ieee80211_hw *hw, u8 element_id,
2146 u32 cmd_len, u8 *p_cmdbuffer); 2163 u32 cmd_len, u8 *p_cmdbuffer);
2147 bool (*get_btc_status) (void); 2164 bool (*get_btc_status) (void);
2148 bool (*is_fw_header) (struct rtl92c_firmware_header *hdr); 2165 bool (*is_fw_header)(struct rtl8723e_firmware_header *hdr);
2149 u32 (*rx_command_packet)(struct ieee80211_hw *hw, 2166 u32 (*rx_command_packet)(struct ieee80211_hw *hw,
2150 struct rtl_stats status, struct sk_buff *skb); 2167 struct rtl_stats status, struct sk_buff *skb);
2151 void (*add_wowlan_pattern)(struct ieee80211_hw *hw, 2168 void (*add_wowlan_pattern)(struct ieee80211_hw *hw,
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-20 07:55:48 -0400