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-rw-r--r--drivers/net/wireless/brcm80211/brcmfmac/Makefile3
-rw-r--r--drivers/net/wireless/brcm80211/brcmfmac/bcmchip.h7
-rw-r--r--drivers/net/wireless/brcm80211/brcmfmac/dhd.h18
-rw-r--r--drivers/net/wireless/brcm80211/brcmfmac/dhd_common.c5
-rw-r--r--drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c301
-rw-r--r--drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c709
-rw-r--r--drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.c622
-rw-r--r--drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.h136
-rw-r--r--drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c41
-rw-r--r--drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.h9
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/aiutils.h76
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/ampdu.c6
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/channel.c118
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/dma.c44
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/dma.h3
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c121
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.h2
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/main.c687
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/main.h19
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/phy/phy_cmn.c10
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/phy/phy_int.h5
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/phy/phy_n.c38
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/pmu.c1
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/pub.h38
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/rate.h5
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/srom.c469
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/srom.h5
-rw-r--r--drivers/net/wireless/brcm80211/brcmutil/utils.c218
-rw-r--r--drivers/net/wireless/brcm80211/include/brcmu_utils.h30
-rw-r--r--drivers/net/wireless/brcm80211/include/defs.h1
-rw-r--r--drivers/net/wireless/brcm80211/include/soc.h12
31 files changed, 1463 insertions, 2296 deletions
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/Makefile b/drivers/net/wireless/brcm80211/brcmfmac/Makefile
index b44e3094588a..d58aa1b0a932 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/Makefile
+++ b/drivers/net/wireless/brcm80211/brcmfmac/Makefile
@@ -26,7 +26,8 @@ DHDOFILES = \
26 dhd_sdio.o \ 26 dhd_sdio.o \
27 dhd_linux.o \ 27 dhd_linux.o \
28 bcmsdh.o \ 28 bcmsdh.o \
29 bcmsdh_sdmmc.o 29 bcmsdh_sdmmc.o \
30 sdio_chip.o
30 31
31obj-$(CONFIG_BRCMFMAC) += brcmfmac.o 32obj-$(CONFIG_BRCMFMAC) += brcmfmac.o
32brcmfmac-objs += $(DHDOFILES) 33brcmfmac-objs += $(DHDOFILES)
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/bcmchip.h b/drivers/net/wireless/brcm80211/brcmfmac/bcmchip.h
index d7d3afd5a10f..cecb5e5f412b 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/bcmchip.h
+++ b/drivers/net/wireless/brcm80211/brcmfmac/bcmchip.h
@@ -18,13 +18,6 @@
18#define _bcmchip_h_ 18#define _bcmchip_h_
19 19
20/* bcm4329 */ 20/* bcm4329 */
21/* SDIO device core, ID 0x829 */
22#define BCM4329_CORE_BUS_BASE 0x18011000
23/* internal memory core, ID 0x80e */
24#define BCM4329_CORE_SOCRAM_BASE 0x18003000
25/* ARM Cortex M3 core, ID 0x82a */
26#define BCM4329_CORE_ARM_BASE 0x18002000
27#define BCM4329_RAMSIZE 0x48000
28/* firmware name */ 21/* firmware name */
29#define BCM4329_FW_NAME "brcm/bcm4329-fullmac-4.bin" 22#define BCM4329_FW_NAME "brcm/bcm4329-fullmac-4.bin"
30#define BCM4329_NV_NAME "brcm/bcm4329-fullmac-4.txt" 23#define BCM4329_NV_NAME "brcm/bcm4329-fullmac-4.txt"
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/dhd.h b/drivers/net/wireless/brcm80211/brcmfmac/dhd.h
index 4645766b4070..6da519e7578f 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/dhd.h
+++ b/drivers/net/wireless/brcm80211/brcmfmac/dhd.h
@@ -87,7 +87,7 @@
87#define TOE_TX_CSUM_OL 0x00000001 87#define TOE_TX_CSUM_OL 0x00000001
88#define TOE_RX_CSUM_OL 0x00000002 88#define TOE_RX_CSUM_OL 0x00000002
89 89
90#define BRCMF_BSS_INFO_VERSION 108 /* current ver of brcmf_bss_info struct */ 90#define BRCMF_BSS_INFO_VERSION 108 /* curr ver of brcmf_bss_info_le struct */
91 91
92/* size of brcmf_scan_params not including variable length array */ 92/* size of brcmf_scan_params not including variable length array */
93#define BRCMF_SCAN_PARAMS_FIXED_SIZE 64 93#define BRCMF_SCAN_PARAMS_FIXED_SIZE 64
@@ -122,8 +122,6 @@
122 122
123/* For supporting multiple interfaces */ 123/* For supporting multiple interfaces */
124#define BRCMF_MAX_IFS 16 124#define BRCMF_MAX_IFS 16
125#define BRCMF_DEL_IF -0xe
126#define BRCMF_BAD_IF -0xf
127 125
128#define DOT11_BSSTYPE_ANY 2 126#define DOT11_BSSTYPE_ANY 2
129#define DOT11_MAX_DEFAULT_KEYS 4 127#define DOT11_MAX_DEFAULT_KEYS 4
@@ -365,7 +363,7 @@ struct brcmf_pkt_filter_enable_le {
365 * Applications MUST CHECK ie_offset field and length field to access IEs and 363 * Applications MUST CHECK ie_offset field and length field to access IEs and
366 * next bss_info structure in a vector (in struct brcmf_scan_results) 364 * next bss_info structure in a vector (in struct brcmf_scan_results)
367 */ 365 */
368struct brcmf_bss_info { 366struct brcmf_bss_info_le {
369 __le32 version; /* version field */ 367 __le32 version; /* version field */
370 __le32 length; /* byte length of data in this record, 368 __le32 length; /* byte length of data in this record,
371 * starting at version and including IEs 369 * starting at version and including IEs
@@ -466,14 +464,13 @@ struct brcmf_scan_results {
466 u32 buflen; 464 u32 buflen;
467 u32 version; 465 u32 version;
468 u32 count; 466 u32 count;
469 struct brcmf_bss_info bss_info[1]; 467 struct brcmf_bss_info_le bss_info_le[];
470}; 468};
471 469
472struct brcmf_scan_results_le { 470struct brcmf_scan_results_le {
473 __le32 buflen; 471 __le32 buflen;
474 __le32 version; 472 __le32 version;
475 __le32 count; 473 __le32 count;
476 struct brcmf_bss_info bss_info[1];
477}; 474};
478 475
479/* used for association with a specific BSSID and chanspec list */ 476/* used for association with a specific BSSID and chanspec list */
@@ -493,10 +490,6 @@ struct brcmf_join_params {
493 struct brcmf_assoc_params_le params_le; 490 struct brcmf_assoc_params_le params_le;
494}; 491};
495 492
496/* size of brcmf_scan_results not including variable length array */
497#define BRCMF_SCAN_RESULTS_FIXED_SIZE \
498 (sizeof(struct brcmf_scan_results) - sizeof(struct brcmf_bss_info))
499
500/* incremental scan results struct */ 493/* incremental scan results struct */
501struct brcmf_iscan_results { 494struct brcmf_iscan_results {
502 union { 495 union {
@@ -511,7 +504,7 @@ struct brcmf_iscan_results {
511 504
512/* size of brcmf_iscan_results not including variable length array */ 505/* size of brcmf_iscan_results not including variable length array */
513#define BRCMF_ISCAN_RESULTS_FIXED_SIZE \ 506#define BRCMF_ISCAN_RESULTS_FIXED_SIZE \
514 (BRCMF_SCAN_RESULTS_FIXED_SIZE + \ 507 (sizeof(struct brcmf_scan_results) + \
515 offsetof(struct brcmf_iscan_results, results)) 508 offsetof(struct brcmf_iscan_results, results))
516 509
517struct brcmf_wsec_key { 510struct brcmf_wsec_key {
@@ -734,8 +727,7 @@ extern int brcmf_c_host_event(struct brcmf_info *drvr_priv, int *idx,
734extern void brcmf_c_init(void); 727extern void brcmf_c_init(void);
735 728
736extern int brcmf_add_if(struct brcmf_info *drvr_priv, int ifidx, 729extern int brcmf_add_if(struct brcmf_info *drvr_priv, int ifidx,
737 struct net_device *ndev, char *name, u8 *mac_addr, 730 char *name, u8 *mac_addr);
738 u32 flags, u8 bssidx);
739extern void brcmf_del_if(struct brcmf_info *drvr_priv, int ifidx); 731extern void brcmf_del_if(struct brcmf_info *drvr_priv, int ifidx);
740 732
741/* Send packet to dongle via data channel */ 733/* Send packet to dongle via data channel */
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/dhd_common.c b/drivers/net/wireless/brcm80211/brcmfmac/dhd_common.c
index 891826197f96..40928e58b6a6 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/dhd_common.c
+++ b/drivers/net/wireless/brcm80211/brcmfmac/dhd_common.c
@@ -488,10 +488,9 @@ brcmf_c_host_event(struct brcmf_info *drvr_priv, int *ifidx, void *pktdata,
488 488
489 if (ifevent->ifidx > 0 && ifevent->ifidx < BRCMF_MAX_IFS) { 489 if (ifevent->ifidx > 0 && ifevent->ifidx < BRCMF_MAX_IFS) {
490 if (ifevent->action == BRCMF_E_IF_ADD) 490 if (ifevent->action == BRCMF_E_IF_ADD)
491 brcmf_add_if(drvr_priv, ifevent->ifidx, NULL, 491 brcmf_add_if(drvr_priv, ifevent->ifidx,
492 event->ifname, 492 event->ifname,
493 pvt_data->eth.h_dest, 493 pvt_data->eth.h_dest);
494 ifevent->flags, ifevent->bssidx);
495 else 494 else
496 brcmf_del_if(drvr_priv, ifevent->ifidx); 495 brcmf_del_if(drvr_priv, ifevent->ifidx);
497 } else { 496 } else {
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c b/drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c
index 4acbac5a74c6..719fd9397eb6 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c
+++ b/drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c
@@ -58,7 +58,6 @@ struct brcmf_if {
58 struct net_device *ndev; 58 struct net_device *ndev;
59 struct net_device_stats stats; 59 struct net_device_stats stats;
60 int idx; /* iface idx in dongle */ 60 int idx; /* iface idx in dongle */
61 int state; /* interface state */
62 u8 mac_addr[ETH_ALEN]; /* assigned MAC address */ 61 u8 mac_addr[ETH_ALEN]; /* assigned MAC address */
63}; 62};
64 63
@@ -80,20 +79,6 @@ struct brcmf_info {
80/* Error bits */ 79/* Error bits */
81module_param(brcmf_msg_level, int, 0); 80module_param(brcmf_msg_level, int, 0);
82 81
83
84static int brcmf_net2idx(struct brcmf_info *drvr_priv, struct net_device *ndev)
85{
86 int i = 0;
87
88 while (i < BRCMF_MAX_IFS) {
89 if (drvr_priv->iflist[i] && drvr_priv->iflist[i]->ndev == ndev)
90 return i;
91 i++;
92 }
93
94 return BRCMF_BAD_IF;
95}
96
97int brcmf_ifname2idx(struct brcmf_info *drvr_priv, char *name) 82int brcmf_ifname2idx(struct brcmf_info *drvr_priv, char *name)
98{ 83{
99 int i = BRCMF_MAX_IFS; 84 int i = BRCMF_MAX_IFS;
@@ -285,14 +270,9 @@ _brcmf_set_mac_address(struct work_struct *work)
285 270
286static int brcmf_netdev_set_mac_address(struct net_device *ndev, void *addr) 271static int brcmf_netdev_set_mac_address(struct net_device *ndev, void *addr)
287{ 272{
288 struct brcmf_info *drvr_priv = *(struct brcmf_info **) 273 struct brcmf_if *ifp = netdev_priv(ndev);
289 netdev_priv(ndev); 274 struct brcmf_info *drvr_priv = ifp->info;
290 struct sockaddr *sa = (struct sockaddr *)addr; 275 struct sockaddr *sa = (struct sockaddr *)addr;
291 int ifidx;
292
293 ifidx = brcmf_net2idx(drvr_priv, ndev);
294 if (ifidx == BRCMF_BAD_IF)
295 return -1;
296 276
297 memcpy(&drvr_priv->macvalue, sa->sa_data, ETH_ALEN); 277 memcpy(&drvr_priv->macvalue, sa->sa_data, ETH_ALEN);
298 schedule_work(&drvr_priv->setmacaddr_work); 278 schedule_work(&drvr_priv->setmacaddr_work);
@@ -301,13 +281,8 @@ static int brcmf_netdev_set_mac_address(struct net_device *ndev, void *addr)
301 281
302static void brcmf_netdev_set_multicast_list(struct net_device *ndev) 282static void brcmf_netdev_set_multicast_list(struct net_device *ndev)
303{ 283{
304 struct brcmf_info *drvr_priv = *(struct brcmf_info **) 284 struct brcmf_if *ifp = netdev_priv(ndev);
305 netdev_priv(ndev); 285 struct brcmf_info *drvr_priv = ifp->info;
306 int ifidx;
307
308 ifidx = brcmf_net2idx(drvr_priv, ndev);
309 if (ifidx == BRCMF_BAD_IF)
310 return;
311 286
312 schedule_work(&drvr_priv->multicast_work); 287 schedule_work(&drvr_priv->multicast_work);
313} 288}
@@ -341,9 +316,8 @@ int brcmf_sendpkt(struct brcmf_pub *drvr, int ifidx, struct sk_buff *pktbuf)
341static int brcmf_netdev_start_xmit(struct sk_buff *skb, struct net_device *ndev) 316static int brcmf_netdev_start_xmit(struct sk_buff *skb, struct net_device *ndev)
342{ 317{
343 int ret; 318 int ret;
344 struct brcmf_info *drvr_priv = *(struct brcmf_info **) 319 struct brcmf_if *ifp = netdev_priv(ndev);
345 netdev_priv(ndev); 320 struct brcmf_info *drvr_priv = ifp->info;
346 int ifidx;
347 321
348 brcmf_dbg(TRACE, "Enter\n"); 322 brcmf_dbg(TRACE, "Enter\n");
349 323
@@ -355,9 +329,8 @@ static int brcmf_netdev_start_xmit(struct sk_buff *skb, struct net_device *ndev)
355 return -ENODEV; 329 return -ENODEV;
356 } 330 }
357 331
358 ifidx = brcmf_net2idx(drvr_priv, ndev); 332 if (!drvr_priv->iflist[ifp->idx]) {
359 if (ifidx == BRCMF_BAD_IF) { 333 brcmf_dbg(ERROR, "bad ifidx %d\n", ifp->idx);
360 brcmf_dbg(ERROR, "bad ifidx %d\n", ifidx);
361 netif_stop_queue(ndev); 334 netif_stop_queue(ndev);
362 return -ENODEV; 335 return -ENODEV;
363 } 336 }
@@ -367,20 +340,20 @@ static int brcmf_netdev_start_xmit(struct sk_buff *skb, struct net_device *ndev)
367 struct sk_buff *skb2; 340 struct sk_buff *skb2;
368 341
369 brcmf_dbg(INFO, "%s: insufficient headroom\n", 342 brcmf_dbg(INFO, "%s: insufficient headroom\n",
370 brcmf_ifname(&drvr_priv->pub, ifidx)); 343 brcmf_ifname(&drvr_priv->pub, ifp->idx));
371 drvr_priv->pub.tx_realloc++; 344 drvr_priv->pub.tx_realloc++;
372 skb2 = skb_realloc_headroom(skb, drvr_priv->pub.hdrlen); 345 skb2 = skb_realloc_headroom(skb, drvr_priv->pub.hdrlen);
373 dev_kfree_skb(skb); 346 dev_kfree_skb(skb);
374 skb = skb2; 347 skb = skb2;
375 if (skb == NULL) { 348 if (skb == NULL) {
376 brcmf_dbg(ERROR, "%s: skb_realloc_headroom failed\n", 349 brcmf_dbg(ERROR, "%s: skb_realloc_headroom failed\n",
377 brcmf_ifname(&drvr_priv->pub, ifidx)); 350 brcmf_ifname(&drvr_priv->pub, ifp->idx));
378 ret = -ENOMEM; 351 ret = -ENOMEM;
379 goto done; 352 goto done;
380 } 353 }
381 } 354 }
382 355
383 ret = brcmf_sendpkt(&drvr_priv->pub, ifidx, skb); 356 ret = brcmf_sendpkt(&drvr_priv->pub, ifp->idx, skb);
384 357
385done: 358done:
386 if (ret) 359 if (ret)
@@ -482,12 +455,10 @@ void brcmf_rx_frame(struct brcmf_pub *drvr, int ifidx, struct sk_buff *skb,
482 skb_mac_header(skb), 455 skb_mac_header(skb),
483 &event, &data); 456 &event, &data);
484 457
485 if (drvr_priv->iflist[ifidx] && 458 if (drvr_priv->iflist[ifidx]) {
486 !drvr_priv->iflist[ifidx]->state)
487 ifp = drvr_priv->iflist[ifidx]; 459 ifp = drvr_priv->iflist[ifidx];
488
489 if (ifp->ndev)
490 ifp->ndev->last_rx = jiffies; 460 ifp->ndev->last_rx = jiffies;
461 }
491 462
492 drvr->dstats.rx_bytes += skb->len; 463 drvr->dstats.rx_bytes += skb->len;
493 drvr->rx_packets++; /* Local count */ 464 drvr->rx_packets++; /* Local count */
@@ -524,19 +495,11 @@ void brcmf_txcomplete(struct brcmf_pub *drvr, struct sk_buff *txp, bool success)
524 495
525static struct net_device_stats *brcmf_netdev_get_stats(struct net_device *ndev) 496static struct net_device_stats *brcmf_netdev_get_stats(struct net_device *ndev)
526{ 497{
527 struct brcmf_info *drvr_priv = *(struct brcmf_info **) 498 struct brcmf_if *ifp = netdev_priv(ndev);
528 netdev_priv(ndev); 499 struct brcmf_info *drvr_priv = ifp->info;
529 struct brcmf_if *ifp;
530 int ifidx;
531 500
532 brcmf_dbg(TRACE, "Enter\n"); 501 brcmf_dbg(TRACE, "Enter\n");
533 502
534 ifidx = brcmf_net2idx(drvr_priv, ndev);
535 if (ifidx == BRCMF_BAD_IF)
536 return NULL;
537
538 ifp = drvr_priv->iflist[ifidx];
539
540 if (drvr_priv->pub.up) 503 if (drvr_priv->pub.up)
541 /* Use the protocol to get dongle stats */ 504 /* Use the protocol to get dongle stats */
542 brcmf_proto_dstats(&drvr_priv->pub); 505 brcmf_proto_dstats(&drvr_priv->pub);
@@ -637,8 +600,8 @@ static int brcmf_toe_set(struct brcmf_info *drvr_priv, int ifidx, u32 toe_ol)
637static void brcmf_ethtool_get_drvinfo(struct net_device *ndev, 600static void brcmf_ethtool_get_drvinfo(struct net_device *ndev,
638 struct ethtool_drvinfo *info) 601 struct ethtool_drvinfo *info)
639{ 602{
640 struct brcmf_info *drvr_priv = *(struct brcmf_info **) 603 struct brcmf_if *ifp = netdev_priv(ndev);
641 netdev_priv(ndev); 604 struct brcmf_info *drvr_priv = ifp->info;
642 605
643 sprintf(info->driver, KBUILD_MODNAME); 606 sprintf(info->driver, KBUILD_MODNAME);
644 sprintf(info->version, "%lu", drvr_priv->pub.drv_version); 607 sprintf(info->version, "%lu", drvr_priv->pub.drv_version);
@@ -765,14 +728,12 @@ static int brcmf_ethtool(struct brcmf_info *drvr_priv, void __user *uaddr)
765static int brcmf_netdev_ioctl_entry(struct net_device *ndev, struct ifreq *ifr, 728static int brcmf_netdev_ioctl_entry(struct net_device *ndev, struct ifreq *ifr,
766 int cmd) 729 int cmd)
767{ 730{
768 struct brcmf_info *drvr_priv = *(struct brcmf_info **) 731 struct brcmf_if *ifp = netdev_priv(ndev);
769 netdev_priv(ndev); 732 struct brcmf_info *drvr_priv = ifp->info;
770 int ifidx;
771 733
772 ifidx = brcmf_net2idx(drvr_priv, ndev); 734 brcmf_dbg(TRACE, "ifidx %d, cmd 0x%04x\n", ifp->idx, cmd);
773 brcmf_dbg(TRACE, "ifidx %d, cmd 0x%04x\n", ifidx, cmd);
774 735
775 if (ifidx == BRCMF_BAD_IF) 736 if (!drvr_priv->iflist[ifp->idx])
776 return -1; 737 return -1;
777 738
778 if (cmd == SIOCETHTOOL) 739 if (cmd == SIOCETHTOOL)
@@ -788,17 +749,14 @@ s32 brcmf_exec_dcmd(struct net_device *ndev, u32 cmd, void *arg, u32 len)
788 s32 err = 0; 749 s32 err = 0;
789 int buflen = 0; 750 int buflen = 0;
790 bool is_set_key_cmd; 751 bool is_set_key_cmd;
791 struct brcmf_info *drvr_priv = *(struct brcmf_info **) 752 struct brcmf_if *ifp = netdev_priv(ndev);
792 netdev_priv(ndev); 753 struct brcmf_info *drvr_priv = ifp->info;
793 int ifidx;
794 754
795 memset(&dcmd, 0, sizeof(dcmd)); 755 memset(&dcmd, 0, sizeof(dcmd));
796 dcmd.cmd = cmd; 756 dcmd.cmd = cmd;
797 dcmd.buf = arg; 757 dcmd.buf = arg;
798 dcmd.len = len; 758 dcmd.len = len;
799 759
800 ifidx = brcmf_net2idx(drvr_priv, ndev);
801
802 if (dcmd.buf != NULL) 760 if (dcmd.buf != NULL)
803 buflen = min_t(uint, dcmd.len, BRCMF_DCMD_MAXLEN); 761 buflen = min_t(uint, dcmd.len, BRCMF_DCMD_MAXLEN);
804 762
@@ -826,7 +784,7 @@ s32 brcmf_exec_dcmd(struct net_device *ndev, u32 cmd, void *arg, u32 len)
826 if (is_set_key_cmd) 784 if (is_set_key_cmd)
827 brcmf_netdev_wait_pend8021x(ndev); 785 brcmf_netdev_wait_pend8021x(ndev);
828 786
829 err = brcmf_proto_dcmd(&drvr_priv->pub, ifidx, &dcmd, buflen); 787 err = brcmf_proto_dcmd(&drvr_priv->pub, ifp->idx, &dcmd, buflen);
830 788
831done: 789done:
832 if (err > 0) 790 if (err > 0)
@@ -837,7 +795,8 @@ done:
837 795
838static int brcmf_netdev_stop(struct net_device *ndev) 796static int brcmf_netdev_stop(struct net_device *ndev)
839{ 797{
840 struct brcmf_pub *drvr = *(struct brcmf_pub **) netdev_priv(ndev); 798 struct brcmf_if *ifp = netdev_priv(ndev);
799 struct brcmf_pub *drvr = &ifp->info->pub;
841 800
842 brcmf_dbg(TRACE, "Enter\n"); 801 brcmf_dbg(TRACE, "Enter\n");
843 brcmf_cfg80211_down(drvr->config); 802 brcmf_cfg80211_down(drvr->config);
@@ -853,16 +812,14 @@ static int brcmf_netdev_stop(struct net_device *ndev)
853 812
854static int brcmf_netdev_open(struct net_device *ndev) 813static int brcmf_netdev_open(struct net_device *ndev)
855{ 814{
856 struct brcmf_info *drvr_priv = *(struct brcmf_info **) 815 struct brcmf_if *ifp = netdev_priv(ndev);
857 netdev_priv(ndev); 816 struct brcmf_info *drvr_priv = ifp->info;
858 u32 toe_ol; 817 u32 toe_ol;
859 int ifidx = brcmf_net2idx(drvr_priv, ndev);
860 s32 ret = 0; 818 s32 ret = 0;
861 819
862 brcmf_dbg(TRACE, "ifidx %d\n", ifidx); 820 brcmf_dbg(TRACE, "ifidx %d\n", ifp->idx);
863
864 if (ifidx == 0) { /* do it only for primary eth0 */
865 821
822 if (ifp->idx == 0) { /* do it only for primary eth0 */
866 /* try to bring up bus */ 823 /* try to bring up bus */
867 ret = brcmf_bus_start(&drvr_priv->pub); 824 ret = brcmf_bus_start(&drvr_priv->pub);
868 if (ret != 0) { 825 if (ret != 0) {
@@ -874,12 +831,12 @@ static int brcmf_netdev_open(struct net_device *ndev)
874 memcpy(ndev->dev_addr, drvr_priv->pub.mac, ETH_ALEN); 831 memcpy(ndev->dev_addr, drvr_priv->pub.mac, ETH_ALEN);
875 832
876 /* Get current TOE mode from dongle */ 833 /* Get current TOE mode from dongle */
877 if (brcmf_toe_get(drvr_priv, ifidx, &toe_ol) >= 0 834 if (brcmf_toe_get(drvr_priv, ifp->idx, &toe_ol) >= 0
878 && (toe_ol & TOE_TX_CSUM_OL) != 0) 835 && (toe_ol & TOE_TX_CSUM_OL) != 0)
879 drvr_priv->iflist[ifidx]->ndev->features |= 836 drvr_priv->iflist[ifp->idx]->ndev->features |=
880 NETIF_F_IP_CSUM; 837 NETIF_F_IP_CSUM;
881 else 838 else
882 drvr_priv->iflist[ifidx]->ndev->features &= 839 drvr_priv->iflist[ifp->idx]->ndev->features &=
883 ~NETIF_F_IP_CSUM; 840 ~NETIF_F_IP_CSUM;
884 } 841 }
885 /* Allow transmit calls */ 842 /* Allow transmit calls */
@@ -893,75 +850,62 @@ static int brcmf_netdev_open(struct net_device *ndev)
893 return ret; 850 return ret;
894} 851}
895 852
853static const struct net_device_ops brcmf_netdev_ops_pri = {
854 .ndo_open = brcmf_netdev_open,
855 .ndo_stop = brcmf_netdev_stop,
856 .ndo_get_stats = brcmf_netdev_get_stats,
857 .ndo_do_ioctl = brcmf_netdev_ioctl_entry,
858 .ndo_start_xmit = brcmf_netdev_start_xmit,
859 .ndo_set_mac_address = brcmf_netdev_set_mac_address,
860 .ndo_set_rx_mode = brcmf_netdev_set_multicast_list
861};
862
896int 863int
897brcmf_add_if(struct brcmf_info *drvr_priv, int ifidx, struct net_device *ndev, 864brcmf_add_if(struct brcmf_info *drvr_priv, int ifidx, char *name, u8 *mac_addr)
898 char *name, u8 *mac_addr, u32 flags, u8 bssidx)
899{ 865{
900 struct brcmf_if *ifp; 866 struct brcmf_if *ifp;
901 int ret = 0, err = 0; 867 struct net_device *ndev;
902 868
903 brcmf_dbg(TRACE, "idx %d, handle->%p\n", ifidx, ndev); 869 brcmf_dbg(TRACE, "idx %d\n", ifidx);
904 870
905 ifp = drvr_priv->iflist[ifidx]; 871 ifp = drvr_priv->iflist[ifidx];
906 if (!ifp) { 872 /*
907 ifp = kmalloc(sizeof(struct brcmf_if), GFP_ATOMIC); 873 * Delete the existing interface before overwriting it
908 if (!ifp) 874 * in case we missed the BRCMF_E_IF_DEL event.
909 return -ENOMEM; 875 */
876 if (ifp) {
877 brcmf_dbg(ERROR, "ERROR: netdev:%s already exists, try free & unregister\n",
878 ifp->ndev->name);
879 netif_stop_queue(ifp->ndev);
880 unregister_netdev(ifp->ndev);
881 free_netdev(ifp->ndev);
882 drvr_priv->iflist[ifidx] = NULL;
883 }
884
885 /* Allocate netdev, including space for private structure */
886 ndev = alloc_netdev(sizeof(struct brcmf_if), name, ether_setup);
887 if (!ndev) {
888 brcmf_dbg(ERROR, "OOM - alloc_netdev\n");
889 return -ENOMEM;
910 } 890 }
911 891
912 memset(ifp, 0, sizeof(struct brcmf_if)); 892 ifp = netdev_priv(ndev);
893 ifp->ndev = ndev;
913 ifp->info = drvr_priv; 894 ifp->info = drvr_priv;
914 drvr_priv->iflist[ifidx] = ifp; 895 drvr_priv->iflist[ifidx] = ifp;
896 ifp->idx = ifidx;
915 if (mac_addr != NULL) 897 if (mac_addr != NULL)
916 memcpy(&ifp->mac_addr, mac_addr, ETH_ALEN); 898 memcpy(&ifp->mac_addr, mac_addr, ETH_ALEN);
917 899
918 if (ndev == NULL) { 900 if (brcmf_net_attach(&drvr_priv->pub, ifp->idx)) {
919 ifp->state = BRCMF_E_IF_ADD; 901 brcmf_dbg(ERROR, "brcmf_net_attach failed");
920 ifp->idx = ifidx; 902 free_netdev(ifp->ndev);
921 /* 903 drvr_priv->iflist[ifidx] = NULL;
922 * Delete the existing interface before overwriting it 904 return -EOPNOTSUPP;
923 * in case we missed the BRCMF_E_IF_DEL event. 905 }
924 */
925 if (ifp->ndev != NULL) {
926 brcmf_dbg(ERROR, "ERROR: netdev:%s already exists, try free & unregister\n",
927 ifp->ndev->name);
928 netif_stop_queue(ifp->ndev);
929 unregister_netdev(ifp->ndev);
930 free_netdev(ifp->ndev);
931 }
932
933 /* Allocate netdev, including space for private structure */
934 ifp->ndev = alloc_netdev(sizeof(drvr_priv), "wlan%d",
935 ether_setup);
936 if (!ifp->ndev) {
937 brcmf_dbg(ERROR, "OOM - alloc_netdev\n");
938 ret = -ENOMEM;
939 }
940
941 if (ret == 0) {
942 memcpy(netdev_priv(ifp->ndev), &drvr_priv,
943 sizeof(drvr_priv));
944 err = brcmf_net_attach(&drvr_priv->pub, ifp->idx);
945 if (err != 0) {
946 brcmf_dbg(ERROR, "brcmf_net_attach failed, err %d\n",
947 err);
948 ret = -EOPNOTSUPP;
949 } else {
950 brcmf_dbg(TRACE, " ==== pid:%x, net_device for if:%s created ===\n",
951 current->pid, ifp->ndev->name);
952 ifp->state = 0;
953 }
954 }
955
956 if (ret < 0) {
957 if (ifp->ndev)
958 free_netdev(ifp->ndev);
959 906
960 drvr_priv->iflist[ifp->idx] = NULL; 907 brcmf_dbg(TRACE, " ==== pid:%x, net_device for if:%s created ===\n",
961 kfree(ifp); 908 current->pid, ifp->ndev->name);
962 }
963 } else
964 ifp->ndev = ndev;
965 909
966 return 0; 910 return 0;
967} 911}
@@ -977,47 +921,36 @@ void brcmf_del_if(struct brcmf_info *drvr_priv, int ifidx)
977 brcmf_dbg(ERROR, "Null interface\n"); 921 brcmf_dbg(ERROR, "Null interface\n");
978 return; 922 return;
979 } 923 }
924 if (ifp->ndev) {
925 if (ifidx == 0) {
926 if (ifp->ndev->netdev_ops == &brcmf_netdev_ops_pri) {
927 rtnl_lock();
928 brcmf_netdev_stop(ifp->ndev);
929 rtnl_unlock();
930 }
931 } else {
932 netif_stop_queue(ifp->ndev);
933 }
980 934
981 ifp->state = BRCMF_E_IF_DEL;
982 ifp->idx = ifidx;
983 if (ifp->ndev != NULL) {
984 netif_stop_queue(ifp->ndev);
985 unregister_netdev(ifp->ndev); 935 unregister_netdev(ifp->ndev);
986 free_netdev(ifp->ndev);
987 drvr_priv->iflist[ifidx] = NULL; 936 drvr_priv->iflist[ifidx] = NULL;
988 kfree(ifp); 937 if (ifidx == 0)
938 brcmf_cfg80211_detach(drvr_priv->pub.config);
939 free_netdev(ifp->ndev);
989 } 940 }
990} 941}
991 942
992struct brcmf_pub *brcmf_attach(struct brcmf_bus *bus, uint bus_hdrlen) 943struct brcmf_pub *brcmf_attach(struct brcmf_bus *bus, uint bus_hdrlen)
993{ 944{
994 struct brcmf_info *drvr_priv = NULL; 945 struct brcmf_info *drvr_priv = NULL;
995 struct net_device *ndev;
996 946
997 brcmf_dbg(TRACE, "Enter\n"); 947 brcmf_dbg(TRACE, "Enter\n");
998 948
999 /* Allocate netdev, including space for private structure */
1000 ndev = alloc_netdev(sizeof(drvr_priv), "wlan%d", ether_setup);
1001 if (!ndev) {
1002 brcmf_dbg(ERROR, "OOM - alloc_netdev\n");
1003 goto fail;
1004 }
1005
1006 /* Allocate primary brcmf_info */ 949 /* Allocate primary brcmf_info */
1007 drvr_priv = kzalloc(sizeof(struct brcmf_info), GFP_ATOMIC); 950 drvr_priv = kzalloc(sizeof(struct brcmf_info), GFP_ATOMIC);
1008 if (!drvr_priv) 951 if (!drvr_priv)
1009 goto fail; 952 goto fail;
1010 953
1011 /*
1012 * Save the brcmf_info into the priv
1013 */
1014 memcpy(netdev_priv(ndev), &drvr_priv, sizeof(drvr_priv));
1015
1016 if (brcmf_add_if(drvr_priv, 0, ndev, ndev->name, NULL, 0, 0) ==
1017 BRCMF_BAD_IF)
1018 goto fail;
1019
1020 ndev->netdev_ops = NULL;
1021 mutex_init(&drvr_priv->proto_block); 954 mutex_init(&drvr_priv->proto_block);
1022 955
1023 /* Link to info module */ 956 /* Link to info module */
@@ -1033,29 +966,12 @@ struct brcmf_pub *brcmf_attach(struct brcmf_bus *bus, uint bus_hdrlen)
1033 goto fail; 966 goto fail;
1034 } 967 }
1035 968
1036 /* Attach and link in the cfg80211 */
1037 drvr_priv->pub.config =
1038 brcmf_cfg80211_attach(ndev,
1039 brcmf_bus_get_device(bus),
1040 &drvr_priv->pub);
1041 if (drvr_priv->pub.config == NULL) {
1042 brcmf_dbg(ERROR, "wl_cfg80211_attach failed\n");
1043 goto fail;
1044 }
1045
1046 INIT_WORK(&drvr_priv->setmacaddr_work, _brcmf_set_mac_address); 969 INIT_WORK(&drvr_priv->setmacaddr_work, _brcmf_set_mac_address);
1047 INIT_WORK(&drvr_priv->multicast_work, _brcmf_set_multicast_list); 970 INIT_WORK(&drvr_priv->multicast_work, _brcmf_set_multicast_list);
1048 971
1049 /*
1050 * Save the brcmf_info into the priv
1051 */
1052 memcpy(netdev_priv(ndev), &drvr_priv, sizeof(drvr_priv));
1053
1054 return &drvr_priv->pub; 972 return &drvr_priv->pub;
1055 973
1056fail: 974fail:
1057 if (ndev)
1058 free_netdev(ndev);
1059 if (drvr_priv) 975 if (drvr_priv)
1060 brcmf_detach(&drvr_priv->pub); 976 brcmf_detach(&drvr_priv->pub);
1061 977
@@ -1123,16 +1039,6 @@ int brcmf_bus_start(struct brcmf_pub *drvr)
1123 return 0; 1039 return 0;
1124} 1040}
1125 1041
1126static struct net_device_ops brcmf_netdev_ops_pri = {
1127 .ndo_open = brcmf_netdev_open,
1128 .ndo_stop = brcmf_netdev_stop,
1129 .ndo_get_stats = brcmf_netdev_get_stats,
1130 .ndo_do_ioctl = brcmf_netdev_ioctl_entry,
1131 .ndo_start_xmit = brcmf_netdev_start_xmit,
1132 .ndo_set_mac_address = brcmf_netdev_set_mac_address,
1133 .ndo_set_rx_mode = brcmf_netdev_set_multicast_list
1134};
1135
1136int brcmf_net_attach(struct brcmf_pub *drvr, int ifidx) 1042int brcmf_net_attach(struct brcmf_pub *drvr, int ifidx)
1137{ 1043{
1138 struct brcmf_info *drvr_priv = drvr->info; 1044 struct brcmf_info *drvr_priv = drvr->info;
@@ -1169,6 +1075,18 @@ int brcmf_net_attach(struct brcmf_pub *drvr, int ifidx)
1169 1075
1170 memcpy(ndev->dev_addr, temp_addr, ETH_ALEN); 1076 memcpy(ndev->dev_addr, temp_addr, ETH_ALEN);
1171 1077
1078 /* attach to cfg80211 for primary interface */
1079 if (!ifidx) {
1080 drvr->config =
1081 brcmf_cfg80211_attach(ndev,
1082 brcmf_bus_get_device(drvr->bus),
1083 drvr);
1084 if (drvr->config == NULL) {
1085 brcmf_dbg(ERROR, "wl_cfg80211_attach failed\n");
1086 goto fail;
1087 }
1088 }
1089
1172 if (register_netdev(ndev) != 0) { 1090 if (register_netdev(ndev) != 0) {
1173 brcmf_dbg(ERROR, "couldn't register the net device\n"); 1091 brcmf_dbg(ERROR, "couldn't register the net device\n");
1174 goto fail; 1092 goto fail;
@@ -1210,21 +1128,13 @@ void brcmf_detach(struct brcmf_pub *drvr)
1210 if (drvr) { 1128 if (drvr) {
1211 drvr_priv = drvr->info; 1129 drvr_priv = drvr->info;
1212 if (drvr_priv) { 1130 if (drvr_priv) {
1213 struct brcmf_if *ifp;
1214 int i; 1131 int i;
1215 1132
1216 for (i = 1; i < BRCMF_MAX_IFS; i++) 1133 /* make sure primary interface removed last */
1134 for (i = BRCMF_MAX_IFS-1; i > -1; i--)
1217 if (drvr_priv->iflist[i]) 1135 if (drvr_priv->iflist[i])
1218 brcmf_del_if(drvr_priv, i); 1136 brcmf_del_if(drvr_priv, i);
1219 1137
1220 ifp = drvr_priv->iflist[0];
1221 if (ifp->ndev->netdev_ops == &brcmf_netdev_ops_pri) {
1222 rtnl_lock();
1223 brcmf_netdev_stop(ifp->ndev);
1224 rtnl_unlock();
1225 unregister_netdev(ifp->ndev);
1226 }
1227
1228 cancel_work_sync(&drvr_priv->setmacaddr_work); 1138 cancel_work_sync(&drvr_priv->setmacaddr_work);
1229 cancel_work_sync(&drvr_priv->multicast_work); 1139 cancel_work_sync(&drvr_priv->multicast_work);
1230 1140
@@ -1233,10 +1143,6 @@ void brcmf_detach(struct brcmf_pub *drvr)
1233 if (drvr->prot) 1143 if (drvr->prot)
1234 brcmf_proto_detach(drvr); 1144 brcmf_proto_detach(drvr);
1235 1145
1236 brcmf_cfg80211_detach(drvr->config);
1237
1238 free_netdev(ifp->ndev);
1239 kfree(ifp);
1240 kfree(drvr_priv); 1146 kfree(drvr_priv);
1241 } 1147 }
1242 } 1148 }
@@ -1302,7 +1208,8 @@ static int brcmf_get_pend_8021x_cnt(struct brcmf_info *drvr_priv)
1302 1208
1303int brcmf_netdev_wait_pend8021x(struct net_device *ndev) 1209int brcmf_netdev_wait_pend8021x(struct net_device *ndev)
1304{ 1210{
1305 struct brcmf_info *drvr_priv = *(struct brcmf_info **)netdev_priv(ndev); 1211 struct brcmf_if *ifp = netdev_priv(ndev);
1212 struct brcmf_info *drvr_priv = ifp->info;
1306 int timeout = 10 * HZ / 1000; 1213 int timeout = 10 * HZ / 1000;
1307 int ntimes = MAX_WAIT_FOR_8021X_TX; 1214 int ntimes = MAX_WAIT_FOR_8021X_TX;
1308 int pend = brcmf_get_pend_8021x_cnt(drvr_priv); 1215 int pend = brcmf_get_pend_8021x_cnt(drvr_priv);
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c b/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c
index 313b8bf592d1..22913af26db8 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c
+++ b/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c
@@ -28,6 +28,7 @@
28#include <linux/semaphore.h> 28#include <linux/semaphore.h>
29#include <linux/firmware.h> 29#include <linux/firmware.h>
30#include <linux/module.h> 30#include <linux/module.h>
31#include <linux/bcma/bcma.h>
31#include <asm/unaligned.h> 32#include <asm/unaligned.h>
32#include <defs.h> 33#include <defs.h>
33#include <brcmu_wifi.h> 34#include <brcmu_wifi.h>
@@ -35,6 +36,7 @@
35#include <brcm_hw_ids.h> 36#include <brcm_hw_ids.h>
36#include <soc.h> 37#include <soc.h>
37#include "sdio_host.h" 38#include "sdio_host.h"
39#include "sdio_chip.h"
38 40
39#define DCMD_RESP_TIMEOUT 2000 /* In milli second */ 41#define DCMD_RESP_TIMEOUT 2000 /* In milli second */
40 42
@@ -134,33 +136,6 @@ struct rte_console {
134/* Force no backplane reset */ 136/* Force no backplane reset */
135#define SBSDIO_DEVCTL_RST_NOBPRESET 0x20 137#define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
136 138
137/* SBSDIO_FUNC1_CHIPCLKCSR */
138
139/* Force ALP request to backplane */
140#define SBSDIO_FORCE_ALP 0x01
141/* Force HT request to backplane */
142#define SBSDIO_FORCE_HT 0x02
143/* Force ILP request to backplane */
144#define SBSDIO_FORCE_ILP 0x04
145/* Make ALP ready (power up xtal) */
146#define SBSDIO_ALP_AVAIL_REQ 0x08
147/* Make HT ready (power up PLL) */
148#define SBSDIO_HT_AVAIL_REQ 0x10
149/* Squelch clock requests from HW */
150#define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
151/* Status: ALP is ready */
152#define SBSDIO_ALP_AVAIL 0x40
153/* Status: HT is ready */
154#define SBSDIO_HT_AVAIL 0x80
155
156#define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
157#define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
158#define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
159#define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
160
161#define SBSDIO_CLKAV(regval, alponly) \
162 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
163
164/* direct(mapped) cis space */ 139/* direct(mapped) cis space */
165 140
166/* MAPPED common CIS address */ 141/* MAPPED common CIS address */
@@ -335,50 +310,6 @@ struct rte_console {
335/* Flags for SDH calls */ 310/* Flags for SDH calls */
336#define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED) 311#define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
337 312
338/* sbimstate */
339#define SBIM_IBE 0x20000 /* inbanderror */
340#define SBIM_TO 0x40000 /* timeout */
341#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
342#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
343
344/* sbtmstatelow */
345
346/* reset */
347#define SBTML_RESET 0x0001
348/* reject field */
349#define SBTML_REJ_MASK 0x0006
350/* reject */
351#define SBTML_REJ 0x0002
352/* temporary reject, for error recovery */
353#define SBTML_TMPREJ 0x0004
354
355/* Shift to locate the SI control flags in sbtml */
356#define SBTML_SICF_SHIFT 16
357
358/* sbtmstatehigh */
359#define SBTMH_SERR 0x0001 /* serror */
360#define SBTMH_INT 0x0002 /* interrupt */
361#define SBTMH_BUSY 0x0004 /* busy */
362#define SBTMH_TO 0x0020 /* timeout (sonics >= 2.3) */
363
364/* Shift to locate the SI status flags in sbtmh */
365#define SBTMH_SISF_SHIFT 16
366
367/* sbidlow */
368#define SBIDL_INIT 0x80 /* initiator */
369
370/* sbidhigh */
371#define SBIDH_RC_MASK 0x000f /* revision code */
372#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
373#define SBIDH_RCE_SHIFT 8
374#define SBCOREREV(sbidh) \
375 ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | \
376 ((sbidh) & SBIDH_RC_MASK))
377#define SBIDH_CC_MASK 0x8ff0 /* core code */
378#define SBIDH_CC_SHIFT 4
379#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
380#define SBIDH_VC_SHIFT 16
381
382/* 313/*
383 * Conversion of 802.1D priority to precedence level 314 * Conversion of 802.1D priority to precedence level
384 */ 315 */
@@ -388,17 +319,6 @@ static uint prio2prec(u32 prio)
388 (prio^2) : prio; 319 (prio^2) : prio;
389} 320}
390 321
391/*
392 * Core reg address translation.
393 * Both macro's returns a 32 bits byte address on the backplane bus.
394 */
395#define CORE_CC_REG(base, field) \
396 (base + offsetof(struct chipcregs, field))
397#define CORE_BUS_REG(base, field) \
398 (base + offsetof(struct sdpcmd_regs, field))
399#define CORE_SB(base, field) \
400 (base + SBCONFIGOFF + offsetof(struct sbconfig, field))
401
402/* core registers */ 322/* core registers */
403struct sdpcmd_regs { 323struct sdpcmd_regs {
404 u32 corecontrol; /* 0x00, rev8 */ 324 u32 corecontrol; /* 0x00, rev8 */
@@ -524,21 +444,6 @@ struct sdpcm_shared_le {
524 444
525 445
526/* misc chip info needed by some of the routines */ 446/* misc chip info needed by some of the routines */
527struct chip_info {
528 u32 chip;
529 u32 chiprev;
530 u32 cccorebase;
531 u32 ccrev;
532 u32 cccaps;
533 u32 buscorebase; /* 32 bits backplane bus address */
534 u32 buscorerev;
535 u32 buscoretype;
536 u32 ramcorebase;
537 u32 armcorebase;
538 u32 pmurev;
539 u32 ramsize;
540};
541
542/* Private data for SDIO bus interaction */ 447/* Private data for SDIO bus interaction */
543struct brcmf_bus { 448struct brcmf_bus {
544 struct brcmf_pub *drvr; 449 struct brcmf_pub *drvr;
@@ -574,7 +479,7 @@ struct brcmf_bus {
574 uint txminmax; 479 uint txminmax;
575 480
576 struct sk_buff *glomd; /* Packet containing glomming descriptor */ 481 struct sk_buff *glomd; /* Packet containing glomming descriptor */
577 struct sk_buff *glom; /* Packet chain for glommed superframe */ 482 struct sk_buff_head glom; /* Packet list for glommed superframe */
578 uint glomerr; /* Glom packet read errors */ 483 uint glomerr; /* Glom packet read errors */
579 484
580 u8 *rxbuf; /* Buffer for receiving control packets */ 485 u8 *rxbuf; /* Buffer for receiving control packets */
@@ -663,46 +568,6 @@ struct brcmf_bus {
663 u32 fw_ptr; 568 u32 fw_ptr;
664}; 569};
665 570
666struct sbconfig {
667 u32 PAD[2];
668 u32 sbipsflag; /* initiator port ocp slave flag */
669 u32 PAD[3];
670 u32 sbtpsflag; /* target port ocp slave flag */
671 u32 PAD[11];
672 u32 sbtmerrloga; /* (sonics >= 2.3) */
673 u32 PAD;
674 u32 sbtmerrlog; /* (sonics >= 2.3) */
675 u32 PAD[3];
676 u32 sbadmatch3; /* address match3 */
677 u32 PAD;
678 u32 sbadmatch2; /* address match2 */
679 u32 PAD;
680 u32 sbadmatch1; /* address match1 */
681 u32 PAD[7];
682 u32 sbimstate; /* initiator agent state */
683 u32 sbintvec; /* interrupt mask */
684 u32 sbtmstatelow; /* target state */
685 u32 sbtmstatehigh; /* target state */
686 u32 sbbwa0; /* bandwidth allocation table0 */
687 u32 PAD;
688 u32 sbimconfiglow; /* initiator configuration */
689 u32 sbimconfighigh; /* initiator configuration */
690 u32 sbadmatch0; /* address match0 */
691 u32 PAD;
692 u32 sbtmconfiglow; /* target configuration */
693 u32 sbtmconfighigh; /* target configuration */
694 u32 sbbconfig; /* broadcast configuration */
695 u32 PAD;
696 u32 sbbstate; /* broadcast state */
697 u32 PAD[3];
698 u32 sbactcnfg; /* activate configuration */
699 u32 PAD[3];
700 u32 sbflagst; /* current sbflags */
701 u32 PAD[3];
702 u32 sbidlow; /* identification */
703 u32 sbidhigh; /* identification */
704};
705
706/* clkstate */ 571/* clkstate */
707#define CLK_NONE 0 572#define CLK_NONE 0
708#define CLK_SDONLY 1 573#define CLK_SDONLY 1
@@ -750,10 +615,12 @@ static bool data_ok(struct brcmf_bus *bus)
750static void 615static void
751r_sdreg32(struct brcmf_bus *bus, u32 *regvar, u32 reg_offset, u32 *retryvar) 616r_sdreg32(struct brcmf_bus *bus, u32 *regvar, u32 reg_offset, u32 *retryvar)
752{ 617{
618 u8 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
753 *retryvar = 0; 619 *retryvar = 0;
754 do { 620 do {
755 *regvar = brcmf_sdcard_reg_read(bus->sdiodev, 621 *regvar = brcmf_sdcard_reg_read(bus->sdiodev,
756 bus->ci->buscorebase + reg_offset, sizeof(u32)); 622 bus->ci->c_inf[idx].base + reg_offset,
623 sizeof(u32));
757 } while (brcmf_sdcard_regfail(bus->sdiodev) && 624 } while (brcmf_sdcard_regfail(bus->sdiodev) &&
758 (++(*retryvar) <= retry_limit)); 625 (++(*retryvar) <= retry_limit));
759 if (*retryvar) { 626 if (*retryvar) {
@@ -768,10 +635,11 @@ r_sdreg32(struct brcmf_bus *bus, u32 *regvar, u32 reg_offset, u32 *retryvar)
768static void 635static void
769w_sdreg32(struct brcmf_bus *bus, u32 regval, u32 reg_offset, u32 *retryvar) 636w_sdreg32(struct brcmf_bus *bus, u32 regval, u32 reg_offset, u32 *retryvar)
770{ 637{
638 u8 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
771 *retryvar = 0; 639 *retryvar = 0;
772 do { 640 do {
773 brcmf_sdcard_reg_write(bus->sdiodev, 641 brcmf_sdcard_reg_write(bus->sdiodev,
774 bus->ci->buscorebase + reg_offset, 642 bus->ci->c_inf[idx].base + reg_offset,
775 sizeof(u32), regval); 643 sizeof(u32), regval);
776 } while (brcmf_sdcard_regfail(bus->sdiodev) && 644 } while (brcmf_sdcard_regfail(bus->sdiodev) &&
777 (++(*retryvar) <= retry_limit)); 645 (++(*retryvar) <= retry_limit));
@@ -812,10 +680,6 @@ static int brcmf_sdbrcm_htclk(struct brcmf_bus *bus, bool on, bool pendok)
812 clkreq = 680 clkreq =
813 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ; 681 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
814 682
815 if ((bus->ci->chip == BCM4329_CHIP_ID)
816 && (bus->ci->chiprev == 0))
817 clkreq |= SBSDIO_FORCE_ALP;
818
819 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, 683 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
820 SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err); 684 SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
821 if (err) { 685 if (err) {
@@ -823,14 +687,6 @@ static int brcmf_sdbrcm_htclk(struct brcmf_bus *bus, bool on, bool pendok)
823 return -EBADE; 687 return -EBADE;
824 } 688 }
825 689
826 if (pendok && ((bus->ci->buscoretype == PCMCIA_CORE_ID)
827 && (bus->ci->buscorerev == 9))) {
828 u32 dummy, retries;
829 r_sdreg32(bus, &dummy,
830 offsetof(struct sdpcmd_regs, clockctlstatus),
831 &retries);
832 }
833
834 /* Check current status */ 690 /* Check current status */
835 clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1, 691 clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
836 SBSDIO_FUNC1_CHIPCLKCSR, &err); 692 SBSDIO_FUNC1_CHIPCLKCSR, &err);
@@ -1034,11 +890,9 @@ static int brcmf_sdbrcm_bussleep(struct brcmf_bus *bus, bool sleep)
1034 SBSDIO_FORCE_HW_CLKREQ_OFF, NULL); 890 SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
1035 891
1036 /* Isolate the bus */ 892 /* Isolate the bus */
1037 if (bus->ci->chip != BCM4329_CHIP_ID) { 893 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1038 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, 894 SBSDIO_DEVICE_CTL,
1039 SBSDIO_DEVICE_CTL, 895 SBSDIO_DEVCTL_PADS_ISO, NULL);
1040 SBSDIO_DEVCTL_PADS_ISO, NULL);
1041 }
1042 896
1043 /* Change state */ 897 /* Change state */
1044 bus->sleeping = true; 898 bus->sleeping = true;
@@ -1049,13 +903,6 @@ static int brcmf_sdbrcm_bussleep(struct brcmf_bus *bus, bool sleep)
1049 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, 903 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1050 SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL); 904 SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
1051 905
1052 /* Force pad isolation off if possible
1053 (in case power never toggled) */
1054 if ((bus->ci->buscoretype == PCMCIA_CORE_ID)
1055 && (bus->ci->buscorerev >= 10))
1056 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1057 SBSDIO_DEVICE_CTL, 0, NULL);
1058
1059 /* Make sure the controller has the bus up */ 906 /* Make sure the controller has the bus up */
1060 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false); 907 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
1061 908
@@ -1222,6 +1069,51 @@ static void brcmf_sdbrcm_rxfail(struct brcmf_bus *bus, bool abort, bool rtx)
1222 bus->drvr->busstate = BRCMF_BUS_DOWN; 1069 bus->drvr->busstate = BRCMF_BUS_DOWN;
1223} 1070}
1224 1071
1072/* copy a buffer into a pkt buffer chain */
1073static uint brcmf_sdbrcm_glom_from_buf(struct brcmf_bus *bus, uint len)
1074{
1075 uint n, ret = 0;
1076 struct sk_buff *p;
1077 u8 *buf;
1078
1079 buf = bus->dataptr;
1080
1081 /* copy the data */
1082 skb_queue_walk(&bus->glom, p) {
1083 n = min_t(uint, p->len, len);
1084 memcpy(p->data, buf, n);
1085 buf += n;
1086 len -= n;
1087 ret += n;
1088 if (!len)
1089 break;
1090 }
1091
1092 return ret;
1093}
1094
1095/* return total length of buffer chain */
1096static uint brcmf_sdbrcm_glom_len(struct brcmf_bus *bus)
1097{
1098 struct sk_buff *p;
1099 uint total;
1100
1101 total = 0;
1102 skb_queue_walk(&bus->glom, p)
1103 total += p->len;
1104 return total;
1105}
1106
1107static void brcmf_sdbrcm_free_glom(struct brcmf_bus *bus)
1108{
1109 struct sk_buff *cur, *next;
1110
1111 skb_queue_walk_safe(&bus->glom, cur, next) {
1112 skb_unlink(cur, &bus->glom);
1113 brcmu_pkt_buf_free_skb(cur);
1114 }
1115}
1116
1225static u8 brcmf_sdbrcm_rxglom(struct brcmf_bus *bus, u8 rxseq) 1117static u8 brcmf_sdbrcm_rxglom(struct brcmf_bus *bus, u8 rxseq)
1226{ 1118{
1227 u16 dlen, totlen; 1119 u16 dlen, totlen;
@@ -1240,7 +1132,8 @@ static u8 brcmf_sdbrcm_rxglom(struct brcmf_bus *bus, u8 rxseq)
1240 /* If packets, issue read(s) and send up packet chain */ 1132 /* If packets, issue read(s) and send up packet chain */
1241 /* Return sequence numbers consumed? */ 1133 /* Return sequence numbers consumed? */
1242 1134
1243 brcmf_dbg(TRACE, "start: glomd %p glom %p\n", bus->glomd, bus->glom); 1135 brcmf_dbg(TRACE, "start: glomd %p glom %p\n",
1136 bus->glomd, skb_peek(&bus->glom));
1244 1137
1245 /* If there's a descriptor, generate the packet chain */ 1138 /* If there's a descriptor, generate the packet chain */
1246 if (bus->glomd) { 1139 if (bus->glomd) {
@@ -1287,12 +1180,7 @@ static u8 brcmf_sdbrcm_rxglom(struct brcmf_bus *bus, u8 rxseq)
1287 num, sublen); 1180 num, sublen);
1288 break; 1181 break;
1289 } 1182 }
1290 if (!pfirst) { 1183 skb_queue_tail(&bus->glom, pnext);
1291 pfirst = plast = pnext;
1292 } else {
1293 plast->next = pnext;
1294 plast = pnext;
1295 }
1296 1184
1297 /* Adhere to start alignment requirements */ 1185 /* Adhere to start alignment requirements */
1298 pkt_align(pnext, sublen, BRCMF_SDALIGN); 1186 pkt_align(pnext, sublen, BRCMF_SDALIGN);
@@ -1308,12 +1196,9 @@ static u8 brcmf_sdbrcm_rxglom(struct brcmf_bus *bus, u8 rxseq)
1308 brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n", 1196 brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
1309 bus->nextlen, totlen, rxseq); 1197 bus->nextlen, totlen, rxseq);
1310 } 1198 }
1311 bus->glom = pfirst;
1312 pfirst = pnext = NULL; 1199 pfirst = pnext = NULL;
1313 } else { 1200 } else {
1314 if (pfirst) 1201 brcmf_sdbrcm_free_glom(bus);
1315 brcmu_pkt_buf_free_skb(pfirst);
1316 bus->glom = NULL;
1317 num = 0; 1202 num = 0;
1318 } 1203 }
1319 1204
@@ -1325,18 +1210,18 @@ static u8 brcmf_sdbrcm_rxglom(struct brcmf_bus *bus, u8 rxseq)
1325 1210
1326 /* Ok -- either we just generated a packet chain, 1211 /* Ok -- either we just generated a packet chain,
1327 or had one from before */ 1212 or had one from before */
1328 if (bus->glom) { 1213 if (!skb_queue_empty(&bus->glom)) {
1329 if (BRCMF_GLOM_ON()) { 1214 if (BRCMF_GLOM_ON()) {
1330 brcmf_dbg(GLOM, "try superframe read, packet chain:\n"); 1215 brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
1331 for (pnext = bus->glom; pnext; pnext = pnext->next) { 1216 skb_queue_walk(&bus->glom, pnext) {
1332 brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n", 1217 brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
1333 pnext, (u8 *) (pnext->data), 1218 pnext, (u8 *) (pnext->data),
1334 pnext->len, pnext->len); 1219 pnext->len, pnext->len);
1335 } 1220 }
1336 } 1221 }
1337 1222
1338 pfirst = bus->glom; 1223 pfirst = skb_peek(&bus->glom);
1339 dlen = (u16) brcmu_pkttotlen(pfirst); 1224 dlen = (u16) brcmf_sdbrcm_glom_len(bus);
1340 1225
1341 /* Do an SDIO read for the superframe. Configurable iovar to 1226 /* Do an SDIO read for the superframe. Configurable iovar to
1342 * read directly into the chained packet, or allocate a large 1227 * read directly into the chained packet, or allocate a large
@@ -1354,8 +1239,7 @@ static u8 brcmf_sdbrcm_rxglom(struct brcmf_bus *bus, u8 rxseq)
1354 SDIO_FUNC_2, 1239 SDIO_FUNC_2,
1355 F2SYNC, bus->dataptr, dlen, 1240 F2SYNC, bus->dataptr, dlen,
1356 NULL); 1241 NULL);
1357 sublen = (u16) brcmu_pktfrombuf(pfirst, 0, dlen, 1242 sublen = (u16) brcmf_sdbrcm_glom_from_buf(bus, dlen);
1358 bus->dataptr);
1359 if (sublen != dlen) { 1243 if (sublen != dlen) {
1360 brcmf_dbg(ERROR, "FAILED TO COPY, dlen %d sublen %d\n", 1244 brcmf_dbg(ERROR, "FAILED TO COPY, dlen %d sublen %d\n",
1361 dlen, sublen); 1245 dlen, sublen);
@@ -1380,9 +1264,8 @@ static u8 brcmf_sdbrcm_rxglom(struct brcmf_bus *bus, u8 rxseq)
1380 } else { 1264 } else {
1381 bus->glomerr = 0; 1265 bus->glomerr = 0;
1382 brcmf_sdbrcm_rxfail(bus, true, false); 1266 brcmf_sdbrcm_rxfail(bus, true, false);
1383 brcmu_pkt_buf_free_skb(bus->glom);
1384 bus->rxglomfail++; 1267 bus->rxglomfail++;
1385 bus->glom = NULL; 1268 brcmf_sdbrcm_free_glom(bus);
1386 } 1269 }
1387 return 0; 1270 return 0;
1388 } 1271 }
@@ -1503,9 +1386,8 @@ static u8 brcmf_sdbrcm_rxglom(struct brcmf_bus *bus, u8 rxseq)
1503 } else { 1386 } else {
1504 bus->glomerr = 0; 1387 bus->glomerr = 0;
1505 brcmf_sdbrcm_rxfail(bus, true, false); 1388 brcmf_sdbrcm_rxfail(bus, true, false);
1506 brcmu_pkt_buf_free_skb(bus->glom);
1507 bus->rxglomfail++; 1389 bus->rxglomfail++;
1508 bus->glom = NULL; 1390 brcmf_sdbrcm_free_glom(bus);
1509 } 1391 }
1510 bus->nextlen = 0; 1392 bus->nextlen = 0;
1511 return 0; 1393 return 0;
@@ -1513,7 +1395,6 @@ static u8 brcmf_sdbrcm_rxglom(struct brcmf_bus *bus, u8 rxseq)
1513 1395
1514 /* Basic SD framing looks ok - process each packet (header) */ 1396 /* Basic SD framing looks ok - process each packet (header) */
1515 save_pfirst = pfirst; 1397 save_pfirst = pfirst;
1516 bus->glom = NULL;
1517 plast = NULL; 1398 plast = NULL;
1518 1399
1519 for (num = 0; pfirst; rxseq++, pfirst = pnext) { 1400 for (num = 0; pfirst; rxseq++, pfirst = pnext) {
@@ -1850,10 +1731,10 @@ brcmf_sdbrcm_readframes(struct brcmf_bus *bus, uint maxframes, bool *finished)
1850 rxseq++, rxleft--) { 1731 rxseq++, rxleft--) {
1851 1732
1852 /* Handle glomming separately */ 1733 /* Handle glomming separately */
1853 if (bus->glom || bus->glomd) { 1734 if (bus->glomd || !skb_queue_empty(&bus->glom)) {
1854 u8 cnt; 1735 u8 cnt;
1855 brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n", 1736 brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
1856 bus->glomd, bus->glom); 1737 bus->glomd, skb_peek(&bus->glom));
1857 cnt = brcmf_sdbrcm_rxglom(bus, rxseq); 1738 cnt = brcmf_sdbrcm_rxglom(bus, rxseq);
1858 brcmf_dbg(GLOM, "rxglom returned %d\n", cnt); 1739 brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
1859 rxseq += cnt - 1; 1740 rxseq += cnt - 1;
@@ -3210,135 +3091,11 @@ static int brcmf_sdbrcm_write_vars(struct brcmf_bus *bus)
3210 return bcmerror; 3091 return bcmerror;
3211} 3092}
3212 3093
3213static void
3214brcmf_sdbrcm_chip_disablecore(struct brcmf_sdio_dev *sdiodev, u32 corebase)
3215{
3216 u32 regdata;
3217
3218 regdata = brcmf_sdcard_reg_read(sdiodev,
3219 CORE_SB(corebase, sbtmstatelow), 4);
3220 if (regdata & SBTML_RESET)
3221 return;
3222
3223 regdata = brcmf_sdcard_reg_read(sdiodev,
3224 CORE_SB(corebase, sbtmstatelow), 4);
3225 if ((regdata & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) != 0) {
3226 /*
3227 * set target reject and spin until busy is clear
3228 * (preserve core-specific bits)
3229 */
3230 regdata = brcmf_sdcard_reg_read(sdiodev,
3231 CORE_SB(corebase, sbtmstatelow), 4);
3232 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow),
3233 4, regdata | SBTML_REJ);
3234
3235 regdata = brcmf_sdcard_reg_read(sdiodev,
3236 CORE_SB(corebase, sbtmstatelow), 4);
3237 udelay(1);
3238 SPINWAIT((brcmf_sdcard_reg_read(sdiodev,
3239 CORE_SB(corebase, sbtmstatehigh), 4) &
3240 SBTMH_BUSY), 100000);
3241
3242 regdata = brcmf_sdcard_reg_read(sdiodev,
3243 CORE_SB(corebase, sbtmstatehigh), 4);
3244 if (regdata & SBTMH_BUSY)
3245 brcmf_dbg(ERROR, "ARM core still busy\n");
3246
3247 regdata = brcmf_sdcard_reg_read(sdiodev,
3248 CORE_SB(corebase, sbidlow), 4);
3249 if (regdata & SBIDL_INIT) {
3250 regdata = brcmf_sdcard_reg_read(sdiodev,
3251 CORE_SB(corebase, sbimstate), 4) |
3252 SBIM_RJ;
3253 brcmf_sdcard_reg_write(sdiodev,
3254 CORE_SB(corebase, sbimstate), 4,
3255 regdata);
3256 regdata = brcmf_sdcard_reg_read(sdiodev,
3257 CORE_SB(corebase, sbimstate), 4);
3258 udelay(1);
3259 SPINWAIT((brcmf_sdcard_reg_read(sdiodev,
3260 CORE_SB(corebase, sbimstate), 4) &
3261 SBIM_BY), 100000);
3262 }
3263
3264 /* set reset and reject while enabling the clocks */
3265 brcmf_sdcard_reg_write(sdiodev,
3266 CORE_SB(corebase, sbtmstatelow), 4,
3267 (((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
3268 SBTML_REJ | SBTML_RESET));
3269 regdata = brcmf_sdcard_reg_read(sdiodev,
3270 CORE_SB(corebase, sbtmstatelow), 4);
3271 udelay(10);
3272
3273 /* clear the initiator reject bit */
3274 regdata = brcmf_sdcard_reg_read(sdiodev,
3275 CORE_SB(corebase, sbidlow), 4);
3276 if (regdata & SBIDL_INIT) {
3277 regdata = brcmf_sdcard_reg_read(sdiodev,
3278 CORE_SB(corebase, sbimstate), 4) &
3279 ~SBIM_RJ;
3280 brcmf_sdcard_reg_write(sdiodev,
3281 CORE_SB(corebase, sbimstate), 4,
3282 regdata);
3283 }
3284 }
3285
3286 /* leave reset and reject asserted */
3287 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
3288 (SBTML_REJ | SBTML_RESET));
3289 udelay(1);
3290}
3291
3292static void
3293brcmf_sdbrcm_chip_resetcore(struct brcmf_sdio_dev *sdiodev, u32 corebase)
3294{
3295 u32 regdata;
3296
3297 /*
3298 * Must do the disable sequence first to work for
3299 * arbitrary current core state.
3300 */
3301 brcmf_sdbrcm_chip_disablecore(sdiodev, corebase);
3302
3303 /*
3304 * Now do the initialization sequence.
3305 * set reset while enabling the clock and
3306 * forcing them on throughout the core
3307 */
3308 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
3309 ((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
3310 SBTML_RESET);
3311 udelay(1);
3312
3313 regdata = brcmf_sdcard_reg_read(sdiodev,
3314 CORE_SB(corebase, sbtmstatehigh), 4);
3315 if (regdata & SBTMH_SERR)
3316 brcmf_sdcard_reg_write(sdiodev,
3317 CORE_SB(corebase, sbtmstatehigh), 4, 0);
3318
3319 regdata = brcmf_sdcard_reg_read(sdiodev,
3320 CORE_SB(corebase, sbimstate), 4);
3321 if (regdata & (SBIM_IBE | SBIM_TO))
3322 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbimstate), 4,
3323 regdata & ~(SBIM_IBE | SBIM_TO));
3324
3325 /* clear reset and allow it to propagate throughout the core */
3326 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
3327 (SICF_FGC << SBTML_SICF_SHIFT) |
3328 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
3329 udelay(1);
3330
3331 /* leave clock enabled */
3332 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
3333 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
3334 udelay(1);
3335}
3336
3337static int brcmf_sdbrcm_download_state(struct brcmf_bus *bus, bool enter) 3094static int brcmf_sdbrcm_download_state(struct brcmf_bus *bus, bool enter)
3338{ 3095{
3339 uint retries; 3096 uint retries;
3340 u32 regdata;
3341 int bcmerror = 0; 3097 int bcmerror = 0;
3098 struct chip_info *ci = bus->ci;
3342 3099
3343 /* To enter download state, disable ARM and reset SOCRAM. 3100 /* To enter download state, disable ARM and reset SOCRAM.
3344 * To exit download state, simply reset ARM (default is RAM boot). 3101 * To exit download state, simply reset ARM (default is RAM boot).
@@ -3346,10 +3103,9 @@ static int brcmf_sdbrcm_download_state(struct brcmf_bus *bus, bool enter)
3346 if (enter) { 3103 if (enter) {
3347 bus->alp_only = true; 3104 bus->alp_only = true;
3348 3105
3349 brcmf_sdbrcm_chip_disablecore(bus->sdiodev, 3106 ci->coredisable(bus->sdiodev, ci, BCMA_CORE_ARM_CM3);
3350 bus->ci->armcorebase);
3351 3107
3352 brcmf_sdbrcm_chip_resetcore(bus->sdiodev, bus->ci->ramcorebase); 3108 ci->resetcore(bus->sdiodev, ci, BCMA_CORE_INTERNAL_MEM);
3353 3109
3354 /* Clear the top bit of memory */ 3110 /* Clear the top bit of memory */
3355 if (bus->ramsize) { 3111 if (bus->ramsize) {
@@ -3358,11 +3114,7 @@ static int brcmf_sdbrcm_download_state(struct brcmf_bus *bus, bool enter)
3358 (u8 *)&zeros, 4); 3114 (u8 *)&zeros, 4);
3359 } 3115 }
3360 } else { 3116 } else {
3361 regdata = brcmf_sdcard_reg_read(bus->sdiodev, 3117 if (!ci->iscoreup(bus->sdiodev, ci, BCMA_CORE_INTERNAL_MEM)) {
3362 CORE_SB(bus->ci->ramcorebase, sbtmstatelow), 4);
3363 regdata &= (SBTML_RESET | SBTML_REJ_MASK |
3364 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
3365 if ((SICF_CLOCK_EN << SBTML_SICF_SHIFT) != regdata) {
3366 brcmf_dbg(ERROR, "SOCRAM core is down after reset?\n"); 3118 brcmf_dbg(ERROR, "SOCRAM core is down after reset?\n");
3367 bcmerror = -EBADE; 3119 bcmerror = -EBADE;
3368 goto fail; 3120 goto fail;
@@ -3377,7 +3129,7 @@ static int brcmf_sdbrcm_download_state(struct brcmf_bus *bus, bool enter)
3377 w_sdreg32(bus, 0xFFFFFFFF, 3129 w_sdreg32(bus, 0xFFFFFFFF,
3378 offsetof(struct sdpcmd_regs, intstatus), &retries); 3130 offsetof(struct sdpcmd_regs, intstatus), &retries);
3379 3131
3380 brcmf_sdbrcm_chip_resetcore(bus->sdiodev, bus->ci->armcorebase); 3132 ci->resetcore(bus->sdiodev, ci, BCMA_CORE_ARM_CM3);
3381 3133
3382 /* Allow HT Clock now that the ARM is running. */ 3134 /* Allow HT Clock now that the ARM is running. */
3383 bus->alp_only = false; 3135 bus->alp_only = false;
@@ -3661,11 +3413,7 @@ void brcmf_sdbrcm_bus_stop(struct brcmf_bus *bus)
3661 /* Clear any held glomming stuff */ 3413 /* Clear any held glomming stuff */
3662 if (bus->glomd) 3414 if (bus->glomd)
3663 brcmu_pkt_buf_free_skb(bus->glomd); 3415 brcmu_pkt_buf_free_skb(bus->glomd);
3664 3416 brcmf_sdbrcm_free_glom(bus);
3665 if (bus->glom)
3666 brcmu_pkt_buf_free_skb(bus->glom);
3667
3668 bus->glom = bus->glomd = NULL;
3669 3417
3670 /* Clear rx control and wake any waiters */ 3418 /* Clear rx control and wake any waiters */
3671 bus->rxlen = 0; 3419 bus->rxlen = 0;
@@ -3950,269 +3698,6 @@ fail:
3950 return false; 3698 return false;
3951} 3699}
3952 3700
3953/* SDIO Pad drive strength to select value mappings */
3954struct sdiod_drive_str {
3955 u8 strength; /* Pad Drive Strength in mA */
3956 u8 sel; /* Chip-specific select value */
3957};
3958
3959/* SDIO Drive Strength to sel value table for PMU Rev 1 */
3960static const struct sdiod_drive_str sdiod_drive_strength_tab1[] = {
3961 {
3962 4, 0x2}, {
3963 2, 0x3}, {
3964 1, 0x0}, {
3965 0, 0x0}
3966 };
3967
3968/* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */
3969static const struct sdiod_drive_str sdiod_drive_strength_tab2[] = {
3970 {
3971 12, 0x7}, {
3972 10, 0x6}, {
3973 8, 0x5}, {
3974 6, 0x4}, {
3975 4, 0x2}, {
3976 2, 0x1}, {
3977 0, 0x0}
3978 };
3979
3980/* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */
3981static const struct sdiod_drive_str sdiod_drive_strength_tab3[] = {
3982 {
3983 32, 0x7}, {
3984 26, 0x6}, {
3985 22, 0x5}, {
3986 16, 0x4}, {
3987 12, 0x3}, {
3988 8, 0x2}, {
3989 4, 0x1}, {
3990 0, 0x0}
3991 };
3992
3993#define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
3994
3995static char *brcmf_chipname(uint chipid, char *buf, uint len)
3996{
3997 const char *fmt;
3998
3999 fmt = ((chipid > 0xa000) || (chipid < 0x4000)) ? "%d" : "%x";
4000 snprintf(buf, len, fmt, chipid);
4001 return buf;
4002}
4003
4004static void brcmf_sdbrcm_sdiod_drive_strength_init(struct brcmf_bus *bus,
4005 u32 drivestrength) {
4006 struct sdiod_drive_str *str_tab = NULL;
4007 u32 str_mask = 0;
4008 u32 str_shift = 0;
4009 char chn[8];
4010
4011 if (!(bus->ci->cccaps & CC_CAP_PMU))
4012 return;
4013
4014 switch (SDIOD_DRVSTR_KEY(bus->ci->chip, bus->ci->pmurev)) {
4015 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 1):
4016 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab1;
4017 str_mask = 0x30000000;
4018 str_shift = 28;
4019 break;
4020 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 2):
4021 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 3):
4022 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab2;
4023 str_mask = 0x00003800;
4024 str_shift = 11;
4025 break;
4026 case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 8):
4027 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab3;
4028 str_mask = 0x00003800;
4029 str_shift = 11;
4030 break;
4031 default:
4032 brcmf_dbg(ERROR, "No SDIO Drive strength init done for chip %s rev %d pmurev %d\n",
4033 brcmf_chipname(bus->ci->chip, chn, 8),
4034 bus->ci->chiprev, bus->ci->pmurev);
4035 break;
4036 }
4037
4038 if (str_tab != NULL) {
4039 u32 drivestrength_sel = 0;
4040 u32 cc_data_temp;
4041 int i;
4042
4043 for (i = 0; str_tab[i].strength != 0; i++) {
4044 if (drivestrength >= str_tab[i].strength) {
4045 drivestrength_sel = str_tab[i].sel;
4046 break;
4047 }
4048 }
4049
4050 brcmf_sdcard_reg_write(bus->sdiodev,
4051 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
4052 4, 1);
4053 cc_data_temp = brcmf_sdcard_reg_read(bus->sdiodev,
4054 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr), 4);
4055 cc_data_temp &= ~str_mask;
4056 drivestrength_sel <<= str_shift;
4057 cc_data_temp |= drivestrength_sel;
4058 brcmf_sdcard_reg_write(bus->sdiodev,
4059 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
4060 4, cc_data_temp);
4061
4062 brcmf_dbg(INFO, "SDIO: %dmA drive strength selected, set to 0x%08x\n",
4063 drivestrength, cc_data_temp);
4064 }
4065}
4066
4067static int
4068brcmf_sdbrcm_chip_recognition(struct brcmf_sdio_dev *sdiodev,
4069 struct chip_info *ci, u32 regs)
4070{
4071 u32 regdata;
4072
4073 /*
4074 * Get CC core rev
4075 * Chipid is assume to be at offset 0 from regs arg
4076 * For different chiptypes or old sdio hosts w/o chipcommon,
4077 * other ways of recognition should be added here.
4078 */
4079 ci->cccorebase = regs;
4080 regdata = brcmf_sdcard_reg_read(sdiodev,
4081 CORE_CC_REG(ci->cccorebase, chipid), 4);
4082 ci->chip = regdata & CID_ID_MASK;
4083 ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
4084
4085 brcmf_dbg(INFO, "chipid=0x%x chiprev=%d\n", ci->chip, ci->chiprev);
4086
4087 /* Address of cores for new chips should be added here */
4088 switch (ci->chip) {
4089 case BCM4329_CHIP_ID:
4090 ci->buscorebase = BCM4329_CORE_BUS_BASE;
4091 ci->ramcorebase = BCM4329_CORE_SOCRAM_BASE;
4092 ci->armcorebase = BCM4329_CORE_ARM_BASE;
4093 ci->ramsize = BCM4329_RAMSIZE;
4094 break;
4095 default:
4096 brcmf_dbg(ERROR, "chipid 0x%x is not supported\n", ci->chip);
4097 return -ENODEV;
4098 }
4099
4100 regdata = brcmf_sdcard_reg_read(sdiodev,
4101 CORE_SB(ci->cccorebase, sbidhigh), 4);
4102 ci->ccrev = SBCOREREV(regdata);
4103
4104 regdata = brcmf_sdcard_reg_read(sdiodev,
4105 CORE_CC_REG(ci->cccorebase, pmucapabilities), 4);
4106 ci->pmurev = regdata & PCAP_REV_MASK;
4107
4108 regdata = brcmf_sdcard_reg_read(sdiodev,
4109 CORE_SB(ci->buscorebase, sbidhigh), 4);
4110 ci->buscorerev = SBCOREREV(regdata);
4111 ci->buscoretype = (regdata & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
4112
4113 brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, buscore rev/type=%d/0x%x\n",
4114 ci->ccrev, ci->pmurev, ci->buscorerev, ci->buscoretype);
4115
4116 /* get chipcommon capabilites */
4117 ci->cccaps = brcmf_sdcard_reg_read(sdiodev,
4118 CORE_CC_REG(ci->cccorebase, capabilities), 4);
4119
4120 return 0;
4121}
4122
4123static int
4124brcmf_sdbrcm_chip_attach(struct brcmf_bus *bus, u32 regs)
4125{
4126 struct chip_info *ci;
4127 int err;
4128 u8 clkval, clkset;
4129
4130 brcmf_dbg(TRACE, "Enter\n");
4131
4132 /* alloc chip_info_t */
4133 ci = kzalloc(sizeof(struct chip_info), GFP_ATOMIC);
4134 if (NULL == ci)
4135 return -ENOMEM;
4136
4137 /* bus/core/clk setup for register access */
4138 /* Try forcing SDIO core to do ALPAvail request only */
4139 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
4140 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4141 SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
4142 if (err) {
4143 brcmf_dbg(ERROR, "error writing for HT off\n");
4144 goto fail;
4145 }
4146
4147 /* If register supported, wait for ALPAvail and then force ALP */
4148 /* This may take up to 15 milliseconds */
4149 clkval = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4150 SBSDIO_FUNC1_CHIPCLKCSR, NULL);
4151 if ((clkval & ~SBSDIO_AVBITS) == clkset) {
4152 SPINWAIT(((clkval =
4153 brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4154 SBSDIO_FUNC1_CHIPCLKCSR,
4155 NULL)),
4156 !SBSDIO_ALPAV(clkval)),
4157 PMU_MAX_TRANSITION_DLY);
4158 if (!SBSDIO_ALPAV(clkval)) {
4159 brcmf_dbg(ERROR, "timeout on ALPAV wait, clkval 0x%02x\n",
4160 clkval);
4161 err = -EBUSY;
4162 goto fail;
4163 }
4164 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF |
4165 SBSDIO_FORCE_ALP;
4166 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4167 SBSDIO_FUNC1_CHIPCLKCSR,
4168 clkset, &err);
4169 udelay(65);
4170 } else {
4171 brcmf_dbg(ERROR, "ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
4172 clkset, clkval);
4173 err = -EACCES;
4174 goto fail;
4175 }
4176
4177 /* Also, disable the extra SDIO pull-ups */
4178 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4179 SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
4180
4181 err = brcmf_sdbrcm_chip_recognition(bus->sdiodev, ci, regs);
4182 if (err)
4183 goto fail;
4184
4185 /*
4186 * Make sure any on-chip ARM is off (in case strapping is wrong),
4187 * or downloaded code was already running.
4188 */
4189 brcmf_sdbrcm_chip_disablecore(bus->sdiodev, ci->armcorebase);
4190
4191 brcmf_sdcard_reg_write(bus->sdiodev,
4192 CORE_CC_REG(ci->cccorebase, gpiopullup), 4, 0);
4193 brcmf_sdcard_reg_write(bus->sdiodev,
4194 CORE_CC_REG(ci->cccorebase, gpiopulldown), 4, 0);
4195
4196 /* Disable F2 to clear any intermediate frame state on the dongle */
4197 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
4198 SDIO_FUNC_ENABLE_1, NULL);
4199
4200 /* WAR: cmd52 backplane read so core HW will drop ALPReq */
4201 clkval = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4202 0, NULL);
4203
4204 /* Done with backplane-dependent accesses, can drop clock... */
4205 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4206 SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
4207
4208 bus->ci = ci;
4209 return 0;
4210fail:
4211 bus->ci = NULL;
4212 kfree(ci);
4213 return err;
4214}
4215
4216static bool 3701static bool
4217brcmf_sdbrcm_probe_attach(struct brcmf_bus *bus, u32 regsva) 3702brcmf_sdbrcm_probe_attach(struct brcmf_bus *bus, u32 regsva)
4218{ 3703{
@@ -4220,6 +3705,7 @@ brcmf_sdbrcm_probe_attach(struct brcmf_bus *bus, u32 regsva)
4220 int err = 0; 3705 int err = 0;
4221 int reg_addr; 3706 int reg_addr;
4222 u32 reg_val; 3707 u32 reg_val;
3708 u8 idx;
4223 3709
4224 bus->alp_only = true; 3710 bus->alp_only = true;
4225 3711
@@ -4234,7 +3720,7 @@ brcmf_sdbrcm_probe_attach(struct brcmf_bus *bus, u32 regsva)
4234#endif /* BCMDBG */ 3720#endif /* BCMDBG */
4235 3721
4236 /* 3722 /*
4237 * Force PLL off until brcmf_sdbrcm_chip_attach() 3723 * Force PLL off until brcmf_sdio_chip_attach()
4238 * programs PLL control regs 3724 * programs PLL control regs
4239 */ 3725 */
4240 3726
@@ -4252,8 +3738,8 @@ brcmf_sdbrcm_probe_attach(struct brcmf_bus *bus, u32 regsva)
4252 goto fail; 3738 goto fail;
4253 } 3739 }
4254 3740
4255 if (brcmf_sdbrcm_chip_attach(bus, regsva)) { 3741 if (brcmf_sdio_chip_attach(bus->sdiodev, &bus->ci, regsva)) {
4256 brcmf_dbg(ERROR, "brcmf_sdbrcm_chip_attach failed!\n"); 3742 brcmf_dbg(ERROR, "brcmf_sdio_chip_attach failed!\n");
4257 goto fail; 3743 goto fail;
4258 } 3744 }
4259 3745
@@ -4262,11 +3748,10 @@ brcmf_sdbrcm_probe_attach(struct brcmf_bus *bus, u32 regsva)
4262 goto fail; 3748 goto fail;
4263 } 3749 }
4264 3750
4265 brcmf_sdbrcm_sdiod_drive_strength_init(bus, SDIO_DRIVE_STRENGTH); 3751 brcmf_sdio_chip_drivestrengthinit(bus->sdiodev, bus->ci,
3752 SDIO_DRIVE_STRENGTH);
4266 3753
4267 /* Get info on the ARM and SOCRAM cores... */ 3754 /* Get info on the SOCRAM cores... */
4268 brcmf_sdcard_reg_read(bus->sdiodev,
4269 CORE_SB(bus->ci->armcorebase, sbidhigh), 4);
4270 bus->ramsize = bus->ci->ramsize; 3755 bus->ramsize = bus->ci->ramsize;
4271 if (!(bus->ramsize)) { 3756 if (!(bus->ramsize)) {
4272 brcmf_dbg(ERROR, "failed to find SOCRAM memory!\n"); 3757 brcmf_dbg(ERROR, "failed to find SOCRAM memory!\n");
@@ -4274,7 +3759,8 @@ brcmf_sdbrcm_probe_attach(struct brcmf_bus *bus, u32 regsva)
4274 } 3759 }
4275 3760
4276 /* Set core control so an SDIO reset does a backplane reset */ 3761 /* Set core control so an SDIO reset does a backplane reset */
4277 reg_addr = bus->ci->buscorebase + 3762 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
3763 reg_addr = bus->ci->c_inf[idx].base +
4278 offsetof(struct sdpcmd_regs, corecontrol); 3764 offsetof(struct sdpcmd_regs, corecontrol);
4279 reg_val = brcmf_sdcard_reg_read(bus->sdiodev, reg_addr, sizeof(u32)); 3765 reg_val = brcmf_sdcard_reg_read(bus->sdiodev, reg_addr, sizeof(u32));
4280 brcmf_sdcard_reg_write(bus->sdiodev, reg_addr, sizeof(u32), 3766 brcmf_sdcard_reg_write(bus->sdiodev, reg_addr, sizeof(u32),
@@ -4364,15 +3850,6 @@ brcmf_sdbrcm_watchdog(unsigned long data)
4364 } 3850 }
4365} 3851}
4366 3852
4367static void
4368brcmf_sdbrcm_chip_detach(struct brcmf_bus *bus)
4369{
4370 brcmf_dbg(TRACE, "Enter\n");
4371
4372 kfree(bus->ci);
4373 bus->ci = NULL;
4374}
4375
4376static void brcmf_sdbrcm_release_dongle(struct brcmf_bus *bus) 3853static void brcmf_sdbrcm_release_dongle(struct brcmf_bus *bus)
4377{ 3854{
4378 brcmf_dbg(TRACE, "Enter\n"); 3855 brcmf_dbg(TRACE, "Enter\n");
@@ -4380,7 +3857,7 @@ static void brcmf_sdbrcm_release_dongle(struct brcmf_bus *bus)
4380 if (bus->ci) { 3857 if (bus->ci) {
4381 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false); 3858 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
4382 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false); 3859 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
4383 brcmf_sdbrcm_chip_detach(bus); 3860 brcmf_sdio_chip_detach(&bus->ci);
4384 if (bus->vars && bus->varsz) 3861 if (bus->vars && bus->varsz)
4385 kfree(bus->vars); 3862 kfree(bus->vars);
4386 bus->vars = NULL; 3863 bus->vars = NULL;
@@ -4440,6 +3917,7 @@ void *brcmf_sdbrcm_probe(u16 bus_no, u16 slot, u16 func, uint bustype,
4440 3917
4441 bus->sdiodev = sdiodev; 3918 bus->sdiodev = sdiodev;
4442 sdiodev->bus = bus; 3919 sdiodev->bus = bus;
3920 skb_queue_head_init(&bus->glom);
4443 bus->txbound = BRCMF_TXBOUND; 3921 bus->txbound = BRCMF_TXBOUND;
4444 bus->rxbound = BRCMF_RXBOUND; 3922 bus->rxbound = BRCMF_RXBOUND;
4445 bus->txminmax = BRCMF_TXMINMAX; 3923 bus->txminmax = BRCMF_TXMINMAX;
@@ -4521,9 +3999,10 @@ void *brcmf_sdbrcm_probe(u16 bus_no, u16 slot, u16 func, uint bustype,
4521 goto fail; 3999 goto fail;
4522 } 4000 }
4523 } 4001 }
4524 /* Ok, have the per-port tell the stack we're open for business */ 4002
4525 if (brcmf_net_attach(bus->drvr, 0) != 0) { 4003 /* add interface and open for business */
4526 brcmf_dbg(ERROR, "Net attach failed!!\n"); 4004 if (brcmf_add_if((struct brcmf_info *)bus->drvr, 0, "wlan%d", NULL)) {
4005 brcmf_dbg(ERROR, "Add primary net device interface failed!!\n");
4527 goto fail; 4006 goto fail;
4528 } 4007 }
4529 4008
@@ -4554,10 +4033,6 @@ struct device *brcmf_bus_get_device(struct brcmf_bus *bus)
4554void 4033void
4555brcmf_sdbrcm_wd_timer(struct brcmf_bus *bus, uint wdtick) 4034brcmf_sdbrcm_wd_timer(struct brcmf_bus *bus, uint wdtick)
4556{ 4035{
4557 /* don't start the wd until fw is loaded */
4558 if (bus->drvr->busstate == BRCMF_BUS_DOWN)
4559 return;
4560
4561 /* Totally stop the timer */ 4036 /* Totally stop the timer */
4562 if (!wdtick && bus->wd_timer_valid == true) { 4037 if (!wdtick && bus->wd_timer_valid == true) {
4563 del_timer_sync(&bus->timer); 4038 del_timer_sync(&bus->timer);
@@ -4566,6 +4041,10 @@ brcmf_sdbrcm_wd_timer(struct brcmf_bus *bus, uint wdtick)
4566 return; 4041 return;
4567 } 4042 }
4568 4043
4044 /* don't start the wd until fw is loaded */
4045 if (bus->drvr->busstate == BRCMF_BUS_DOWN)
4046 return;
4047
4569 if (wdtick) { 4048 if (wdtick) {
4570 if (bus->save_ms != BRCMF_WD_POLL_MS) { 4049 if (bus->save_ms != BRCMF_WD_POLL_MS) {
4571 if (bus->wd_timer_valid == true) 4050 if (bus->wd_timer_valid == true)
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.c b/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.c
new file mode 100644
index 000000000000..f6b1822031fe
--- /dev/null
+++ b/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.c
@@ -0,0 +1,622 @@
1/*
2 * Copyright (c) 2011 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16/* ***** SDIO interface chip backplane handle functions ***** */
17
18#include <linux/types.h>
19#include <linux/netdevice.h>
20#include <linux/mmc/card.h>
21#include <linux/ssb/ssb_regs.h>
22#include <linux/bcma/bcma.h>
23
24#include <chipcommon.h>
25#include <brcm_hw_ids.h>
26#include <brcmu_wifi.h>
27#include <brcmu_utils.h>
28#include <soc.h>
29#include "dhd.h"
30#include "dhd_dbg.h"
31#include "sdio_host.h"
32#include "sdio_chip.h"
33
34/* chip core base & ramsize */
35/* bcm4329 */
36/* SDIO device core, ID 0x829 */
37#define BCM4329_CORE_BUS_BASE 0x18011000
38/* internal memory core, ID 0x80e */
39#define BCM4329_CORE_SOCRAM_BASE 0x18003000
40/* ARM Cortex M3 core, ID 0x82a */
41#define BCM4329_CORE_ARM_BASE 0x18002000
42#define BCM4329_RAMSIZE 0x48000
43
44#define SBCOREREV(sbidh) \
45 ((((sbidh) & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT) | \
46 ((sbidh) & SSB_IDHIGH_RCLO))
47
48/* SOC Interconnect types (aka chip types) */
49#define SOCI_SB 0
50#define SOCI_AI 1
51
52/* EROM CompIdentB */
53#define CIB_REV_MASK 0xff000000
54#define CIB_REV_SHIFT 24
55
56#define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
57/* SDIO Pad drive strength to select value mappings */
58struct sdiod_drive_str {
59 u8 strength; /* Pad Drive Strength in mA */
60 u8 sel; /* Chip-specific select value */
61};
62/* SDIO Drive Strength to sel value table for PMU Rev 1 */
63static const struct sdiod_drive_str sdiod_drive_strength_tab1[] = {
64 {
65 4, 0x2}, {
66 2, 0x3}, {
67 1, 0x0}, {
68 0, 0x0}
69 };
70/* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */
71static const struct sdiod_drive_str sdiod_drive_strength_tab2[] = {
72 {
73 12, 0x7}, {
74 10, 0x6}, {
75 8, 0x5}, {
76 6, 0x4}, {
77 4, 0x2}, {
78 2, 0x1}, {
79 0, 0x0}
80 };
81/* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */
82static const struct sdiod_drive_str sdiod_drive_strength_tab3[] = {
83 {
84 32, 0x7}, {
85 26, 0x6}, {
86 22, 0x5}, {
87 16, 0x4}, {
88 12, 0x3}, {
89 8, 0x2}, {
90 4, 0x1}, {
91 0, 0x0}
92 };
93
94u8
95brcmf_sdio_chip_getinfidx(struct chip_info *ci, u16 coreid)
96{
97 u8 idx;
98
99 for (idx = 0; idx < BRCMF_MAX_CORENUM; idx++)
100 if (coreid == ci->c_inf[idx].id)
101 return idx;
102
103 return BRCMF_MAX_CORENUM;
104}
105
106static u32
107brcmf_sdio_sb_corerev(struct brcmf_sdio_dev *sdiodev,
108 struct chip_info *ci, u16 coreid)
109{
110 u32 regdata;
111 u8 idx;
112
113 idx = brcmf_sdio_chip_getinfidx(ci, coreid);
114
115 regdata = brcmf_sdcard_reg_read(sdiodev,
116 CORE_SB(ci->c_inf[idx].base, sbidhigh), 4);
117 return SBCOREREV(regdata);
118}
119
120static u32
121brcmf_sdio_ai_corerev(struct brcmf_sdio_dev *sdiodev,
122 struct chip_info *ci, u16 coreid)
123{
124 u8 idx;
125
126 idx = brcmf_sdio_chip_getinfidx(ci, coreid);
127
128 return (ci->c_inf[idx].cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
129}
130
131static bool
132brcmf_sdio_sb_iscoreup(struct brcmf_sdio_dev *sdiodev,
133 struct chip_info *ci, u16 coreid)
134{
135 u32 regdata;
136 u8 idx;
137
138 idx = brcmf_sdio_chip_getinfidx(ci, coreid);
139
140 regdata = brcmf_sdcard_reg_read(sdiodev,
141 CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4);
142 regdata &= (SSB_TMSLOW_RESET | SSB_TMSLOW_REJECT |
143 SSB_IMSTATE_REJECT | SSB_TMSLOW_CLOCK);
144 return (SSB_TMSLOW_CLOCK == regdata);
145}
146
147static bool
148brcmf_sdio_ai_iscoreup(struct brcmf_sdio_dev *sdiodev,
149 struct chip_info *ci, u16 coreid)
150{
151 u32 regdata;
152 u8 idx;
153 bool ret;
154
155 idx = brcmf_sdio_chip_getinfidx(ci, coreid);
156
157 regdata = brcmf_sdcard_reg_read(sdiodev,
158 ci->c_inf[idx].wrapbase+BCMA_IOCTL, 4);
159 ret = (regdata & (BCMA_IOCTL_FGC | BCMA_IOCTL_CLK)) == BCMA_IOCTL_CLK;
160
161 regdata = brcmf_sdcard_reg_read(sdiodev,
162 ci->c_inf[idx].wrapbase+BCMA_RESET_CTL,
163 4);
164 ret = ret && ((regdata & BCMA_RESET_CTL_RESET) == 0);
165
166 return ret;
167}
168
169static void
170brcmf_sdio_sb_coredisable(struct brcmf_sdio_dev *sdiodev,
171 struct chip_info *ci, u16 coreid)
172{
173 u32 regdata;
174 u8 idx;
175
176 idx = brcmf_sdio_chip_getinfidx(ci, coreid);
177
178 regdata = brcmf_sdcard_reg_read(sdiodev,
179 CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4);
180 if (regdata & SSB_TMSLOW_RESET)
181 return;
182
183 regdata = brcmf_sdcard_reg_read(sdiodev,
184 CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4);
185 if ((regdata & SSB_TMSLOW_CLOCK) != 0) {
186 /*
187 * set target reject and spin until busy is clear
188 * (preserve core-specific bits)
189 */
190 regdata = brcmf_sdcard_reg_read(sdiodev,
191 CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4);
192 brcmf_sdcard_reg_write(sdiodev,
193 CORE_SB(ci->c_inf[idx].base, sbtmstatelow),
194 4, regdata | SSB_TMSLOW_REJECT);
195
196 regdata = brcmf_sdcard_reg_read(sdiodev,
197 CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4);
198 udelay(1);
199 SPINWAIT((brcmf_sdcard_reg_read(sdiodev,
200 CORE_SB(ci->c_inf[idx].base, sbtmstatehigh), 4) &
201 SSB_TMSHIGH_BUSY), 100000);
202
203 regdata = brcmf_sdcard_reg_read(sdiodev,
204 CORE_SB(ci->c_inf[idx].base, sbtmstatehigh), 4);
205 if (regdata & SSB_TMSHIGH_BUSY)
206 brcmf_dbg(ERROR, "core state still busy\n");
207
208 regdata = brcmf_sdcard_reg_read(sdiodev,
209 CORE_SB(ci->c_inf[idx].base, sbidlow), 4);
210 if (regdata & SSB_IDLOW_INITIATOR) {
211 regdata = brcmf_sdcard_reg_read(sdiodev,
212 CORE_SB(ci->c_inf[idx].base, sbimstate), 4) |
213 SSB_IMSTATE_REJECT;
214 brcmf_sdcard_reg_write(sdiodev,
215 CORE_SB(ci->c_inf[idx].base, sbimstate), 4,
216 regdata);
217 regdata = brcmf_sdcard_reg_read(sdiodev,
218 CORE_SB(ci->c_inf[idx].base, sbimstate), 4);
219 udelay(1);
220 SPINWAIT((brcmf_sdcard_reg_read(sdiodev,
221 CORE_SB(ci->c_inf[idx].base, sbimstate), 4) &
222 SSB_IMSTATE_BUSY), 100000);
223 }
224
225 /* set reset and reject while enabling the clocks */
226 brcmf_sdcard_reg_write(sdiodev,
227 CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4,
228 (SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
229 SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET));
230 regdata = brcmf_sdcard_reg_read(sdiodev,
231 CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4);
232 udelay(10);
233
234 /* clear the initiator reject bit */
235 regdata = brcmf_sdcard_reg_read(sdiodev,
236 CORE_SB(ci->c_inf[idx].base, sbidlow), 4);
237 if (regdata & SSB_IDLOW_INITIATOR) {
238 regdata = brcmf_sdcard_reg_read(sdiodev,
239 CORE_SB(ci->c_inf[idx].base, sbimstate), 4) &
240 ~SSB_IMSTATE_REJECT;
241 brcmf_sdcard_reg_write(sdiodev,
242 CORE_SB(ci->c_inf[idx].base, sbimstate), 4,
243 regdata);
244 }
245 }
246
247 /* leave reset and reject asserted */
248 brcmf_sdcard_reg_write(sdiodev,
249 CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4,
250 (SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET));
251 udelay(1);
252}
253
254static void
255brcmf_sdio_ai_coredisable(struct brcmf_sdio_dev *sdiodev,
256 struct chip_info *ci, u16 coreid)
257{
258 u8 idx;
259 u32 regdata;
260
261 idx = brcmf_sdio_chip_getinfidx(ci, coreid);
262
263 /* if core is already in reset, just return */
264 regdata = brcmf_sdcard_reg_read(sdiodev,
265 ci->c_inf[idx].wrapbase+BCMA_RESET_CTL,
266 4);
267 if ((regdata & BCMA_RESET_CTL_RESET) != 0)
268 return;
269
270 brcmf_sdcard_reg_write(sdiodev, ci->c_inf[idx].wrapbase+BCMA_IOCTL,
271 4, 0);
272 regdata = brcmf_sdcard_reg_read(sdiodev,
273 ci->c_inf[idx].wrapbase+BCMA_IOCTL, 4);
274 udelay(10);
275
276 brcmf_sdcard_reg_write(sdiodev, ci->c_inf[idx].wrapbase+BCMA_RESET_CTL,
277 4, BCMA_RESET_CTL_RESET);
278 udelay(1);
279}
280
281static void
282brcmf_sdio_sb_resetcore(struct brcmf_sdio_dev *sdiodev,
283 struct chip_info *ci, u16 coreid)
284{
285 u32 regdata;
286 u8 idx;
287
288 idx = brcmf_sdio_chip_getinfidx(ci, coreid);
289
290 /*
291 * Must do the disable sequence first to work for
292 * arbitrary current core state.
293 */
294 brcmf_sdio_sb_coredisable(sdiodev, ci, coreid);
295
296 /*
297 * Now do the initialization sequence.
298 * set reset while enabling the clock and
299 * forcing them on throughout the core
300 */
301 brcmf_sdcard_reg_write(sdiodev,
302 CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4,
303 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET);
304 regdata = brcmf_sdcard_reg_read(sdiodev,
305 CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4);
306 udelay(1);
307
308 /* clear any serror */
309 regdata = brcmf_sdcard_reg_read(sdiodev,
310 CORE_SB(ci->c_inf[idx].base, sbtmstatehigh), 4);
311 if (regdata & SSB_TMSHIGH_SERR)
312 brcmf_sdcard_reg_write(sdiodev,
313 CORE_SB(ci->c_inf[idx].base, sbtmstatehigh), 4, 0);
314
315 regdata = brcmf_sdcard_reg_read(sdiodev,
316 CORE_SB(ci->c_inf[idx].base, sbimstate), 4);
317 if (regdata & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO))
318 brcmf_sdcard_reg_write(sdiodev,
319 CORE_SB(ci->c_inf[idx].base, sbimstate), 4,
320 regdata & ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO));
321
322 /* clear reset and allow it to propagate throughout the core */
323 brcmf_sdcard_reg_write(sdiodev,
324 CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4,
325 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK);
326 regdata = brcmf_sdcard_reg_read(sdiodev,
327 CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4);
328 udelay(1);
329
330 /* leave clock enabled */
331 brcmf_sdcard_reg_write(sdiodev,
332 CORE_SB(ci->c_inf[idx].base, sbtmstatelow),
333 4, SSB_TMSLOW_CLOCK);
334 regdata = brcmf_sdcard_reg_read(sdiodev,
335 CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4);
336 udelay(1);
337}
338
339static void
340brcmf_sdio_ai_resetcore(struct brcmf_sdio_dev *sdiodev,
341 struct chip_info *ci, u16 coreid)
342{
343 u8 idx;
344 u32 regdata;
345
346 idx = brcmf_sdio_chip_getinfidx(ci, coreid);
347
348 /* must disable first to work for arbitrary current core state */
349 brcmf_sdio_ai_coredisable(sdiodev, ci, coreid);
350
351 /* now do initialization sequence */
352 brcmf_sdcard_reg_write(sdiodev, ci->c_inf[idx].wrapbase+BCMA_IOCTL,
353 4, BCMA_IOCTL_FGC | BCMA_IOCTL_CLK);
354 regdata = brcmf_sdcard_reg_read(sdiodev,
355 ci->c_inf[idx].wrapbase+BCMA_IOCTL, 4);
356 brcmf_sdcard_reg_write(sdiodev, ci->c_inf[idx].wrapbase+BCMA_RESET_CTL,
357 4, 0);
358 udelay(1);
359
360 brcmf_sdcard_reg_write(sdiodev, ci->c_inf[idx].wrapbase+BCMA_IOCTL,
361 4, BCMA_IOCTL_CLK);
362 regdata = brcmf_sdcard_reg_read(sdiodev,
363 ci->c_inf[idx].wrapbase+BCMA_IOCTL, 4);
364 udelay(1);
365}
366
367static int brcmf_sdio_chip_recognition(struct brcmf_sdio_dev *sdiodev,
368 struct chip_info *ci, u32 regs)
369{
370 u32 regdata;
371
372 /*
373 * Get CC core rev
374 * Chipid is assume to be at offset 0 from regs arg
375 * For different chiptypes or old sdio hosts w/o chipcommon,
376 * other ways of recognition should be added here.
377 */
378 ci->c_inf[0].id = BCMA_CORE_CHIPCOMMON;
379 ci->c_inf[0].base = regs;
380 regdata = brcmf_sdcard_reg_read(sdiodev,
381 CORE_CC_REG(ci->c_inf[0].base, chipid), 4);
382 ci->chip = regdata & CID_ID_MASK;
383 ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
384 ci->socitype = (regdata & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
385
386 brcmf_dbg(INFO, "chipid=0x%x chiprev=%d\n", ci->chip, ci->chiprev);
387
388 /* Address of cores for new chips should be added here */
389 switch (ci->chip) {
390 case BCM4329_CHIP_ID:
391 ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
392 ci->c_inf[1].base = BCM4329_CORE_BUS_BASE;
393 ci->c_inf[2].id = BCMA_CORE_INTERNAL_MEM;
394 ci->c_inf[2].base = BCM4329_CORE_SOCRAM_BASE;
395 ci->c_inf[3].id = BCMA_CORE_ARM_CM3;
396 ci->c_inf[3].base = BCM4329_CORE_ARM_BASE;
397 ci->ramsize = BCM4329_RAMSIZE;
398 break;
399 default:
400 brcmf_dbg(ERROR, "chipid 0x%x is not supported\n", ci->chip);
401 return -ENODEV;
402 }
403
404 switch (ci->socitype) {
405 case SOCI_SB:
406 ci->iscoreup = brcmf_sdio_sb_iscoreup;
407 ci->corerev = brcmf_sdio_sb_corerev;
408 ci->coredisable = brcmf_sdio_sb_coredisable;
409 ci->resetcore = brcmf_sdio_sb_resetcore;
410 break;
411 case SOCI_AI:
412 ci->iscoreup = brcmf_sdio_ai_iscoreup;
413 ci->corerev = brcmf_sdio_ai_corerev;
414 ci->coredisable = brcmf_sdio_ai_coredisable;
415 ci->resetcore = brcmf_sdio_ai_resetcore;
416 break;
417 default:
418 brcmf_dbg(ERROR, "socitype %u not supported\n", ci->socitype);
419 return -ENODEV;
420 }
421
422 return 0;
423}
424
425static int
426brcmf_sdio_chip_buscoreprep(struct brcmf_sdio_dev *sdiodev)
427{
428 int err = 0;
429 u8 clkval, clkset;
430
431 /* Try forcing SDIO core to do ALPAvail request only */
432 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
433 brcmf_sdcard_cfg_write(sdiodev, SDIO_FUNC_1,
434 SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
435 if (err) {
436 brcmf_dbg(ERROR, "error writing for HT off\n");
437 return err;
438 }
439
440 /* If register supported, wait for ALPAvail and then force ALP */
441 /* This may take up to 15 milliseconds */
442 clkval = brcmf_sdcard_cfg_read(sdiodev, SDIO_FUNC_1,
443 SBSDIO_FUNC1_CHIPCLKCSR, NULL);
444
445 if ((clkval & ~SBSDIO_AVBITS) != clkset) {
446 brcmf_dbg(ERROR, "ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
447 clkset, clkval);
448 return -EACCES;
449 }
450
451 SPINWAIT(((clkval = brcmf_sdcard_cfg_read(sdiodev, SDIO_FUNC_1,
452 SBSDIO_FUNC1_CHIPCLKCSR, NULL)),
453 !SBSDIO_ALPAV(clkval)),
454 PMU_MAX_TRANSITION_DLY);
455 if (!SBSDIO_ALPAV(clkval)) {
456 brcmf_dbg(ERROR, "timeout on ALPAV wait, clkval 0x%02x\n",
457 clkval);
458 return -EBUSY;
459 }
460
461 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP;
462 brcmf_sdcard_cfg_write(sdiodev, SDIO_FUNC_1,
463 SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
464 udelay(65);
465
466 /* Also, disable the extra SDIO pull-ups */
467 brcmf_sdcard_cfg_write(sdiodev, SDIO_FUNC_1,
468 SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
469
470 return 0;
471}
472
473static void
474brcmf_sdio_chip_buscoresetup(struct brcmf_sdio_dev *sdiodev,
475 struct chip_info *ci)
476{
477 /* get chipcommon rev */
478 ci->c_inf[0].rev = ci->corerev(sdiodev, ci, ci->c_inf[0].id);
479
480 /* get chipcommon capabilites */
481 ci->c_inf[0].caps =
482 brcmf_sdcard_reg_read(sdiodev,
483 CORE_CC_REG(ci->c_inf[0].base, capabilities), 4);
484
485 /* get pmu caps & rev */
486 if (ci->c_inf[0].caps & CC_CAP_PMU) {
487 ci->pmucaps = brcmf_sdcard_reg_read(sdiodev,
488 CORE_CC_REG(ci->c_inf[0].base, pmucapabilities), 4);
489 ci->pmurev = ci->pmucaps & PCAP_REV_MASK;
490 }
491
492 ci->c_inf[1].rev = ci->corerev(sdiodev, ci, ci->c_inf[1].id);
493
494 brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, buscore rev/type=%d/0x%x\n",
495 ci->c_inf[0].rev, ci->pmurev,
496 ci->c_inf[1].rev, ci->c_inf[1].id);
497
498 /*
499 * Make sure any on-chip ARM is off (in case strapping is wrong),
500 * or downloaded code was already running.
501 */
502 ci->coredisable(sdiodev, ci, BCMA_CORE_ARM_CM3);
503}
504
505int brcmf_sdio_chip_attach(struct brcmf_sdio_dev *sdiodev,
506 struct chip_info **ci_ptr, u32 regs)
507{
508 int ret;
509 struct chip_info *ci;
510
511 brcmf_dbg(TRACE, "Enter\n");
512
513 /* alloc chip_info_t */
514 ci = kzalloc(sizeof(struct chip_info), GFP_ATOMIC);
515 if (!ci)
516 return -ENOMEM;
517
518 ret = brcmf_sdio_chip_buscoreprep(sdiodev);
519 if (ret != 0)
520 goto err;
521
522 ret = brcmf_sdio_chip_recognition(sdiodev, ci, regs);
523 if (ret != 0)
524 goto err;
525
526 brcmf_sdio_chip_buscoresetup(sdiodev, ci);
527
528 brcmf_sdcard_reg_write(sdiodev,
529 CORE_CC_REG(ci->c_inf[0].base, gpiopullup), 4, 0);
530 brcmf_sdcard_reg_write(sdiodev,
531 CORE_CC_REG(ci->c_inf[0].base, gpiopulldown), 4, 0);
532
533 *ci_ptr = ci;
534 return 0;
535
536err:
537 kfree(ci);
538 return ret;
539}
540
541void
542brcmf_sdio_chip_detach(struct chip_info **ci_ptr)
543{
544 brcmf_dbg(TRACE, "Enter\n");
545
546 kfree(*ci_ptr);
547 *ci_ptr = NULL;
548}
549
550static char *brcmf_sdio_chip_name(uint chipid, char *buf, uint len)
551{
552 const char *fmt;
553
554 fmt = ((chipid > 0xa000) || (chipid < 0x4000)) ? "%d" : "%x";
555 snprintf(buf, len, fmt, chipid);
556 return buf;
557}
558
559void
560brcmf_sdio_chip_drivestrengthinit(struct brcmf_sdio_dev *sdiodev,
561 struct chip_info *ci, u32 drivestrength)
562{
563 struct sdiod_drive_str *str_tab = NULL;
564 u32 str_mask = 0;
565 u32 str_shift = 0;
566 char chn[8];
567
568 if (!(ci->c_inf[0].caps & CC_CAP_PMU))
569 return;
570
571 switch (SDIOD_DRVSTR_KEY(ci->chip, ci->pmurev)) {
572 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 1):
573 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab1;
574 str_mask = 0x30000000;
575 str_shift = 28;
576 break;
577 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 2):
578 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 3):
579 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab2;
580 str_mask = 0x00003800;
581 str_shift = 11;
582 break;
583 case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 8):
584 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab3;
585 str_mask = 0x00003800;
586 str_shift = 11;
587 break;
588 default:
589 brcmf_dbg(ERROR, "No SDIO Drive strength init done for chip %s rev %d pmurev %d\n",
590 brcmf_sdio_chip_name(ci->chip, chn, 8),
591 ci->chiprev, ci->pmurev);
592 break;
593 }
594
595 if (str_tab != NULL) {
596 u32 drivestrength_sel = 0;
597 u32 cc_data_temp;
598 int i;
599
600 for (i = 0; str_tab[i].strength != 0; i++) {
601 if (drivestrength >= str_tab[i].strength) {
602 drivestrength_sel = str_tab[i].sel;
603 break;
604 }
605 }
606
607 brcmf_sdcard_reg_write(sdiodev,
608 CORE_CC_REG(ci->c_inf[0].base, chipcontrol_addr),
609 4, 1);
610 cc_data_temp = brcmf_sdcard_reg_read(sdiodev,
611 CORE_CC_REG(ci->c_inf[0].base, chipcontrol_addr), 4);
612 cc_data_temp &= ~str_mask;
613 drivestrength_sel <<= str_shift;
614 cc_data_temp |= drivestrength_sel;
615 brcmf_sdcard_reg_write(sdiodev,
616 CORE_CC_REG(ci->c_inf[0].base, chipcontrol_addr),
617 4, cc_data_temp);
618
619 brcmf_dbg(INFO, "SDIO: %dmA drive strength selected, set to 0x%08x\n",
620 drivestrength, cc_data_temp);
621 }
622}
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.h b/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.h
new file mode 100644
index 000000000000..ce974d76bd92
--- /dev/null
+++ b/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.h
@@ -0,0 +1,136 @@
1/*
2 * Copyright (c) 2011 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCMFMAC_SDIO_CHIP_H_
18#define _BRCMFMAC_SDIO_CHIP_H_
19
20/*
21 * Core reg address translation.
22 * Both macro's returns a 32 bits byte address on the backplane bus.
23 */
24#define CORE_CC_REG(base, field) \
25 (base + offsetof(struct chipcregs, field))
26#define CORE_BUS_REG(base, field) \
27 (base + offsetof(struct sdpcmd_regs, field))
28#define CORE_SB(base, field) \
29 (base + SBCONFIGOFF + offsetof(struct sbconfig, field))
30
31/* SDIO function 1 register CHIPCLKCSR */
32/* Force ALP request to backplane */
33#define SBSDIO_FORCE_ALP 0x01
34/* Force HT request to backplane */
35#define SBSDIO_FORCE_HT 0x02
36/* Force ILP request to backplane */
37#define SBSDIO_FORCE_ILP 0x04
38/* Make ALP ready (power up xtal) */
39#define SBSDIO_ALP_AVAIL_REQ 0x08
40/* Make HT ready (power up PLL) */
41#define SBSDIO_HT_AVAIL_REQ 0x10
42/* Squelch clock requests from HW */
43#define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
44/* Status: ALP is ready */
45#define SBSDIO_ALP_AVAIL 0x40
46/* Status: HT is ready */
47#define SBSDIO_HT_AVAIL 0x80
48#define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
49#define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
50#define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
51#define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
52#define SBSDIO_CLKAV(regval, alponly) \
53 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
54
55#define BRCMF_MAX_CORENUM 6
56
57struct chip_core_info {
58 u16 id;
59 u16 rev;
60 u32 base;
61 u32 wrapbase;
62 u32 caps;
63 u32 cib;
64};
65
66struct chip_info {
67 u32 chip;
68 u32 chiprev;
69 u32 socitype;
70 /* core info */
71 /* always put chipcommon core at 0, bus core at 1 */
72 struct chip_core_info c_inf[BRCMF_MAX_CORENUM];
73 u32 pmurev;
74 u32 pmucaps;
75 u32 ramsize;
76
77 bool (*iscoreup)(struct brcmf_sdio_dev *sdiodev, struct chip_info *ci,
78 u16 coreid);
79 u32 (*corerev)(struct brcmf_sdio_dev *sdiodev, struct chip_info *ci,
80 u16 coreid);
81 void (*coredisable)(struct brcmf_sdio_dev *sdiodev,
82 struct chip_info *ci, u16 coreid);
83 void (*resetcore)(struct brcmf_sdio_dev *sdiodev,
84 struct chip_info *ci, u16 coreid);
85};
86
87struct sbconfig {
88 u32 PAD[2];
89 u32 sbipsflag; /* initiator port ocp slave flag */
90 u32 PAD[3];
91 u32 sbtpsflag; /* target port ocp slave flag */
92 u32 PAD[11];
93 u32 sbtmerrloga; /* (sonics >= 2.3) */
94 u32 PAD;
95 u32 sbtmerrlog; /* (sonics >= 2.3) */
96 u32 PAD[3];
97 u32 sbadmatch3; /* address match3 */
98 u32 PAD;
99 u32 sbadmatch2; /* address match2 */
100 u32 PAD;
101 u32 sbadmatch1; /* address match1 */
102 u32 PAD[7];
103 u32 sbimstate; /* initiator agent state */
104 u32 sbintvec; /* interrupt mask */
105 u32 sbtmstatelow; /* target state */
106 u32 sbtmstatehigh; /* target state */
107 u32 sbbwa0; /* bandwidth allocation table0 */
108 u32 PAD;
109 u32 sbimconfiglow; /* initiator configuration */
110 u32 sbimconfighigh; /* initiator configuration */
111 u32 sbadmatch0; /* address match0 */
112 u32 PAD;
113 u32 sbtmconfiglow; /* target configuration */
114 u32 sbtmconfighigh; /* target configuration */
115 u32 sbbconfig; /* broadcast configuration */
116 u32 PAD;
117 u32 sbbstate; /* broadcast state */
118 u32 PAD[3];
119 u32 sbactcnfg; /* activate configuration */
120 u32 PAD[3];
121 u32 sbflagst; /* current sbflags */
122 u32 PAD[3];
123 u32 sbidlow; /* identification */
124 u32 sbidhigh; /* identification */
125};
126
127extern int brcmf_sdio_chip_attach(struct brcmf_sdio_dev *sdiodev,
128 struct chip_info **ci_ptr, u32 regs);
129extern void brcmf_sdio_chip_detach(struct chip_info **ci_ptr);
130extern void brcmf_sdio_chip_drivestrengthinit(struct brcmf_sdio_dev *sdiodev,
131 struct chip_info *ci,
132 u32 drivestrength);
133extern u8 brcmf_sdio_chip_getinfidx(struct chip_info *ci, u16 coreid);
134
135
136#endif /* _BRCMFMAC_SDIO_CHIP_H_ */
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c b/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c
index 5eddabe5228a..cc19a733ac65 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c
+++ b/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c
@@ -1997,7 +1997,7 @@ done:
1997} 1997}
1998 1998
1999static s32 brcmf_inform_single_bss(struct brcmf_cfg80211_priv *cfg_priv, 1999static s32 brcmf_inform_single_bss(struct brcmf_cfg80211_priv *cfg_priv,
2000 struct brcmf_bss_info *bi) 2000 struct brcmf_bss_info_le *bi)
2001{ 2001{
2002 struct wiphy *wiphy = cfg_to_wiphy(cfg_priv); 2002 struct wiphy *wiphy = cfg_to_wiphy(cfg_priv);
2003 struct ieee80211_channel *notify_channel; 2003 struct ieee80211_channel *notify_channel;
@@ -2049,18 +2049,27 @@ static s32 brcmf_inform_single_bss(struct brcmf_cfg80211_priv *cfg_priv,
2049 notify_timestamp, notify_capability, notify_interval, notify_ie, 2049 notify_timestamp, notify_capability, notify_interval, notify_ie,
2050 notify_ielen, notify_signal, GFP_KERNEL); 2050 notify_ielen, notify_signal, GFP_KERNEL);
2051 2051
2052 if (!bss) { 2052 if (!bss)
2053 WL_ERR("cfg80211_inform_bss_frame error\n"); 2053 return -ENOMEM;
2054 return -EINVAL; 2054
2055 } 2055 cfg80211_put_bss(bss);
2056 2056
2057 return err; 2057 return err;
2058} 2058}
2059 2059
2060static struct brcmf_bss_info_le *
2061next_bss_le(struct brcmf_scan_results *list, struct brcmf_bss_info_le *bss)
2062{
2063 if (bss == NULL)
2064 return list->bss_info_le;
2065 return (struct brcmf_bss_info_le *)((unsigned long)bss +
2066 le32_to_cpu(bss->length));
2067}
2068
2060static s32 brcmf_inform_bss(struct brcmf_cfg80211_priv *cfg_priv) 2069static s32 brcmf_inform_bss(struct brcmf_cfg80211_priv *cfg_priv)
2061{ 2070{
2062 struct brcmf_scan_results *bss_list; 2071 struct brcmf_scan_results *bss_list;
2063 struct brcmf_bss_info *bi = NULL; /* must be initialized */ 2072 struct brcmf_bss_info_le *bi = NULL; /* must be initialized */
2064 s32 err = 0; 2073 s32 err = 0;
2065 int i; 2074 int i;
2066 2075
@@ -2072,7 +2081,7 @@ static s32 brcmf_inform_bss(struct brcmf_cfg80211_priv *cfg_priv)
2072 } 2081 }
2073 WL_SCAN("scanned AP count (%d)\n", bss_list->count); 2082 WL_SCAN("scanned AP count (%d)\n", bss_list->count);
2074 for (i = 0; i < bss_list->count && i < WL_AP_MAX; i++) { 2083 for (i = 0; i < bss_list->count && i < WL_AP_MAX; i++) {
2075 bi = next_bss(bss_list, bi); 2084 bi = next_bss_le(bss_list, bi);
2076 err = brcmf_inform_single_bss(cfg_priv, bi); 2085 err = brcmf_inform_single_bss(cfg_priv, bi);
2077 if (err) 2086 if (err)
2078 break; 2087 break;
@@ -2085,8 +2094,9 @@ static s32 wl_inform_ibss(struct brcmf_cfg80211_priv *cfg_priv,
2085{ 2094{
2086 struct wiphy *wiphy = cfg_to_wiphy(cfg_priv); 2095 struct wiphy *wiphy = cfg_to_wiphy(cfg_priv);
2087 struct ieee80211_channel *notify_channel; 2096 struct ieee80211_channel *notify_channel;
2088 struct brcmf_bss_info *bi = NULL; 2097 struct brcmf_bss_info_le *bi = NULL;
2089 struct ieee80211_supported_band *band; 2098 struct ieee80211_supported_band *band;
2099 struct cfg80211_bss *bss;
2090 u8 *buf = NULL; 2100 u8 *buf = NULL;
2091 s32 err = 0; 2101 s32 err = 0;
2092 u16 channel; 2102 u16 channel;
@@ -2114,7 +2124,7 @@ static s32 wl_inform_ibss(struct brcmf_cfg80211_priv *cfg_priv,
2114 goto CleanUp; 2124 goto CleanUp;
2115 } 2125 }
2116 2126
2117 bi = (struct brcmf_bss_info *)(buf + 4); 2127 bi = (struct brcmf_bss_info_le *)(buf + 4);
2118 2128
2119 channel = bi->ctl_ch ? bi->ctl_ch : 2129 channel = bi->ctl_ch ? bi->ctl_ch :
2120 CHSPEC_CHANNEL(le16_to_cpu(bi->chanspec)); 2130 CHSPEC_CHANNEL(le16_to_cpu(bi->chanspec));
@@ -2140,10 +2150,17 @@ static s32 wl_inform_ibss(struct brcmf_cfg80211_priv *cfg_priv,
2140 WL_CONN("signal: %d\n", notify_signal); 2150 WL_CONN("signal: %d\n", notify_signal);
2141 WL_CONN("notify_timestamp: %#018llx\n", notify_timestamp); 2151 WL_CONN("notify_timestamp: %#018llx\n", notify_timestamp);
2142 2152
2143 cfg80211_inform_bss(wiphy, notify_channel, bssid, 2153 bss = cfg80211_inform_bss(wiphy, notify_channel, bssid,
2144 notify_timestamp, notify_capability, notify_interval, 2154 notify_timestamp, notify_capability, notify_interval,
2145 notify_ie, notify_ielen, notify_signal, GFP_KERNEL); 2155 notify_ie, notify_ielen, notify_signal, GFP_KERNEL);
2146 2156
2157 if (!bss) {
2158 err = -ENOMEM;
2159 goto CleanUp;
2160 }
2161
2162 cfg80211_put_bss(bss);
2163
2147CleanUp: 2164CleanUp:
2148 2165
2149 kfree(buf); 2166 kfree(buf);
@@ -2188,7 +2205,7 @@ static struct brcmf_tlv *brcmf_parse_tlvs(void *buf, int buflen, uint key)
2188 2205
2189static s32 brcmf_update_bss_info(struct brcmf_cfg80211_priv *cfg_priv) 2206static s32 brcmf_update_bss_info(struct brcmf_cfg80211_priv *cfg_priv)
2190{ 2207{
2191 struct brcmf_bss_info *bi; 2208 struct brcmf_bss_info_le *bi;
2192 struct brcmf_ssid *ssid; 2209 struct brcmf_ssid *ssid;
2193 struct brcmf_tlv *tim; 2210 struct brcmf_tlv *tim;
2194 u16 beacon_interval; 2211 u16 beacon_interval;
@@ -2211,7 +2228,7 @@ static s32 brcmf_update_bss_info(struct brcmf_cfg80211_priv *cfg_priv)
2211 goto update_bss_info_out; 2228 goto update_bss_info_out;
2212 } 2229 }
2213 2230
2214 bi = (struct brcmf_bss_info *)(cfg_priv->extra_buf + 4); 2231 bi = (struct brcmf_bss_info_le *)(cfg_priv->extra_buf + 4);
2215 err = brcmf_inform_single_bss(cfg_priv, bi); 2232 err = brcmf_inform_single_bss(cfg_priv, bi);
2216 if (err) 2233 if (err)
2217 goto update_bss_info_out; 2234 goto update_bss_info_out;
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.h b/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.h
index 62dc46144ede..a613b49cb13f 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.h
+++ b/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.h
@@ -352,15 +352,6 @@ brcmf_cfg80211_connect_info *cfg_to_conn(struct brcmf_cfg80211_priv *cfg)
352 return &cfg->conn_info; 352 return &cfg->conn_info;
353} 353}
354 354
355static inline struct brcmf_bss_info *next_bss(struct brcmf_scan_results *list,
356 struct brcmf_bss_info *bss)
357{
358 return bss = bss ?
359 (struct brcmf_bss_info *)((unsigned long)bss +
360 le32_to_cpu(bss->length)) :
361 list->bss_info;
362}
363
364extern struct brcmf_cfg80211_dev *brcmf_cfg80211_attach(struct net_device *ndev, 355extern struct brcmf_cfg80211_dev *brcmf_cfg80211_attach(struct net_device *ndev,
365 struct device *busdev, 356 struct device *busdev,
366 void *data); 357 void *data);
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
index 106a7424a7cd..b51d1e421e24 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
+++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
@@ -38,88 +38,12 @@
38/* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */ 38/* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
39#define SI_PCIE_DMA_H32 0x80000000 39#define SI_PCIE_DMA_H32 0x80000000
40 40
41/* core codes */
42#define NODEV_CORE_ID 0x700 /* Invalid coreid */
43#define CC_CORE_ID 0x800 /* chipcommon core */
44#define ILINE20_CORE_ID 0x801 /* iline20 core */
45#define SRAM_CORE_ID 0x802 /* sram core */
46#define SDRAM_CORE_ID 0x803 /* sdram core */
47#define PCI_CORE_ID 0x804 /* pci core */
48#define MIPS_CORE_ID 0x805 /* mips core */
49#define ENET_CORE_ID 0x806 /* enet mac core */
50#define CODEC_CORE_ID 0x807 /* v90 codec core */
51#define USB_CORE_ID 0x808 /* usb 1.1 host/device core */
52#define ADSL_CORE_ID 0x809 /* ADSL core */
53#define ILINE100_CORE_ID 0x80a /* iline100 core */
54#define IPSEC_CORE_ID 0x80b /* ipsec core */
55#define UTOPIA_CORE_ID 0x80c /* utopia core */
56#define PCMCIA_CORE_ID 0x80d /* pcmcia core */
57#define SOCRAM_CORE_ID 0x80e /* internal memory core */
58#define MEMC_CORE_ID 0x80f /* memc sdram core */
59#define OFDM_CORE_ID 0x810 /* OFDM phy core */
60#define EXTIF_CORE_ID 0x811 /* external interface core */
61#define D11_CORE_ID 0x812 /* 802.11 MAC core */
62#define APHY_CORE_ID 0x813 /* 802.11a phy core */
63#define BPHY_CORE_ID 0x814 /* 802.11b phy core */
64#define GPHY_CORE_ID 0x815 /* 802.11g phy core */
65#define MIPS33_CORE_ID 0x816 /* mips3302 core */
66#define USB11H_CORE_ID 0x817 /* usb 1.1 host core */
67#define USB11D_CORE_ID 0x818 /* usb 1.1 device core */
68#define USB20H_CORE_ID 0x819 /* usb 2.0 host core */
69#define USB20D_CORE_ID 0x81a /* usb 2.0 device core */
70#define SDIOH_CORE_ID 0x81b /* sdio host core */
71#define ROBO_CORE_ID 0x81c /* roboswitch core */
72#define ATA100_CORE_ID 0x81d /* parallel ATA core */
73#define SATAXOR_CORE_ID 0x81e /* serial ATA & XOR DMA core */
74#define GIGETH_CORE_ID 0x81f /* gigabit ethernet core */
75#define PCIE_CORE_ID 0x820 /* pci express core */
76#define NPHY_CORE_ID 0x821 /* 802.11n 2x2 phy core */
77#define SRAMC_CORE_ID 0x822 /* SRAM controller core */
78#define MINIMAC_CORE_ID 0x823 /* MINI MAC/phy core */
79#define ARM11_CORE_ID 0x824 /* ARM 1176 core */
80#define ARM7S_CORE_ID 0x825 /* ARM7tdmi-s core */
81#define LPPHY_CORE_ID 0x826 /* 802.11a/b/g phy core */
82#define PMU_CORE_ID 0x827 /* PMU core */
83#define SSNPHY_CORE_ID 0x828 /* 802.11n single-stream phy core */
84#define SDIOD_CORE_ID 0x829 /* SDIO device core */
85#define ARMCM3_CORE_ID 0x82a /* ARM Cortex M3 core */
86#define HTPHY_CORE_ID 0x82b /* 802.11n 4x4 phy core */
87#define MIPS74K_CORE_ID 0x82c /* mips 74k core */
88#define GMAC_CORE_ID 0x82d /* Gigabit MAC core */
89#define DMEMC_CORE_ID 0x82e /* DDR1/2 memory controller core */
90#define PCIERC_CORE_ID 0x82f /* PCIE Root Complex core */
91#define OCP_CORE_ID 0x830 /* OCP2OCP bridge core */
92#define SC_CORE_ID 0x831 /* shared common core */
93#define AHB_CORE_ID 0x832 /* OCP2AHB bridge core */
94#define SPIH_CORE_ID 0x833 /* SPI host core */
95#define I2S_CORE_ID 0x834 /* I2S core */
96#define DMEMS_CORE_ID 0x835 /* SDR/DDR1 memory controller core */
97#define DEF_SHIM_COMP 0x837 /* SHIM component in ubus/6362 */
98#define OOB_ROUTER_CORE_ID 0x367 /* OOB router core ID */
99#define DEF_AI_COMP 0xfff /* Default component, in ai chips it
100 * maps all unused address ranges
101 */
102
103/* chipcommon being the first core: */ 41/* chipcommon being the first core: */
104#define SI_CC_IDX 0 42#define SI_CC_IDX 0
105 43
106/* SOC Interconnect types (aka chip types) */ 44/* SOC Interconnect types (aka chip types) */
107#define SOCI_AI 1 45#define SOCI_AI 1
108 46
109/* Common core control flags */
110#define SICF_BIST_EN 0x8000
111#define SICF_PME_EN 0x4000
112#define SICF_CORE_BITS 0x3ffc
113#define SICF_FGC 0x0002
114#define SICF_CLOCK_EN 0x0001
115
116/* Common core status flags */
117#define SISF_BIST_DONE 0x8000
118#define SISF_BIST_ERROR 0x4000
119#define SISF_GATED_CLK 0x2000
120#define SISF_DMA64 0x1000
121#define SISF_CORE_BITS 0x0fff
122
123/* A register that is common to all cores to 47/* A register that is common to all cores to
124 * communicate w/PMU regarding clock control. 48 * communicate w/PMU regarding clock control.
125 */ 49 */
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/ampdu.c b/drivers/net/wireless/brcm80211/brcmsmac/ampdu.c
index 7f27dbdb6b60..43f7a724dda8 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/ampdu.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/ampdu.c
@@ -649,7 +649,7 @@ brcms_c_sendampdu(struct ampdu_info *ampdu, struct brcms_txq_info *qi,
649 len = roundup(len, 4); 649 len = roundup(len, 4);
650 ampdu_len += (len + (ndelim + 1) * AMPDU_DELIMITER_LEN); 650 ampdu_len += (len + (ndelim + 1) * AMPDU_DELIMITER_LEN);
651 651
652 dma_len += (u16) brcmu_pkttotlen(p); 652 dma_len += (u16) p->len;
653 653
654 BCMMSG(wlc->wiphy, "wl%d: ampdu_len %d" 654 BCMMSG(wlc->wiphy, "wl%d: ampdu_len %d"
655 " seg_cnt %d null delim %d\n", 655 " seg_cnt %d null delim %d\n",
@@ -741,9 +741,7 @@ brcms_c_sendampdu(struct ampdu_info *ampdu, struct brcms_txq_info *qi,
741 if (p) { 741 if (p) {
742 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && 742 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) &&
743 ((u8) (p->priority) == tid)) { 743 ((u8) (p->priority) == tid)) {
744 744 plen = p->len + AMPDU_MAX_MPDU_OVERHEAD;
745 plen = brcmu_pkttotlen(p) +
746 AMPDU_MAX_MPDU_OVERHEAD;
747 plen = max(scb_ampdu->min_len, plen); 745 plen = max(scb_ampdu->min_len, plen);
748 746
749 if ((plen + ampdu_len) > max_ampdu_bytes) { 747 if ((plen + ampdu_len) > max_ampdu_bytes) {
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/channel.c b/drivers/net/wireless/brcm80211/brcmsmac/channel.c
index 89ad1b7dab8f..55e9f45fce22 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/channel.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/channel.c
@@ -1153,121 +1153,6 @@ brcms_c_channel_set_chanspec(struct brcms_cm_info *wlc_cm, u16 chanspec,
1153 &txpwr); 1153 &txpwr);
1154} 1154}
1155 1155
1156#ifdef POWER_DBG
1157static void wlc_phy_txpower_limits_dump(struct txpwr_limits *txpwr)
1158{
1159 int i;
1160 char buf[80];
1161 char fraction[4][4] = { " ", ".25", ".5 ", ".75" };
1162
1163 sprintf(buf, "CCK ");
1164 for (i = 0; i < BRCMS_NUM_RATES_CCK; i++)
1165 sprintf(buf[strlen(buf)], " %2d%s",
1166 txpwr->cck[i] / BRCMS_TXPWR_DB_FACTOR,
1167 fraction[txpwr->cck[i] % BRCMS_TXPWR_DB_FACTOR]);
1168 printk(KERN_DEBUG "%s\n", buf);
1169
1170 sprintf(buf, "20 MHz OFDM SISO ");
1171 for (i = 0; i < BRCMS_NUM_RATES_OFDM; i++)
1172 sprintf(buf[strlen(buf)], " %2d%s",
1173 txpwr->ofdm[i] / BRCMS_TXPWR_DB_FACTOR,
1174 fraction[txpwr->ofdm[i] % BRCMS_TXPWR_DB_FACTOR]);
1175 printk(KERN_DEBUG "%s\n", buf);
1176
1177 sprintf(buf, "20 MHz OFDM CDD ");
1178 for (i = 0; i < BRCMS_NUM_RATES_OFDM; i++)
1179 sprintf(buf[strlen(buf)], " %2d%s",
1180 txpwr->ofdm_cdd[i] / BRCMS_TXPWR_DB_FACTOR,
1181 fraction[txpwr->ofdm_cdd[i] % BRCMS_TXPWR_DB_FACTOR]);
1182 printk(KERN_DEBUG "%s\n", buf);
1183
1184 sprintf(buf, "40 MHz OFDM SISO ");
1185 for (i = 0; i < BRCMS_NUM_RATES_OFDM; i++)
1186 sprintf(buf[strlen(buf)], " %2d%s",
1187 txpwr->ofdm_40_siso[i] / BRCMS_TXPWR_DB_FACTOR,
1188 fraction[txpwr->ofdm_40_siso[i] %
1189 BRCMS_TXPWR_DB_FACTOR]);
1190 printk(KERN_DEBUG "%s\n", buf);
1191
1192 sprintf(buf, "40 MHz OFDM CDD ");
1193 for (i = 0; i < BRCMS_NUM_RATES_OFDM; i++)
1194 sprintf(buf[strlen(buf)], " %2d%s",
1195 txpwr->ofdm_40_cdd[i] / BRCMS_TXPWR_DB_FACTOR,
1196 fraction[txpwr->ofdm_40_cdd[i] %
1197 BRCMS_TXPWR_DB_FACTOR]);
1198 printk(KERN_DEBUG "%s\n", buf);
1199
1200 sprintf(buf, "20 MHz MCS0-7 SISO ");
1201 for (i = 0; i < BRCMS_NUM_RATES_MCS_1_STREAM; i++)
1202 sprintf(buf[strlen(buf)], " %2d%s",
1203 txpwr->mcs_20_siso[i] / BRCMS_TXPWR_DB_FACTOR,
1204 fraction[txpwr->mcs_20_siso[i] %
1205 BRCMS_TXPWR_DB_FACTOR]);
1206 printk(KERN_DEBUG "%s\n", buf);
1207
1208 sprintf(buf, "20 MHz MCS0-7 CDD ");
1209 for (i = 0; i < BRCMS_NUM_RATES_MCS_1_STREAM; i++)
1210 sprintf(buf[strlen(buf)], " %2d%s",
1211 txpwr->mcs_20_cdd[i] / BRCMS_TXPWR_DB_FACTOR,
1212 fraction[txpwr->mcs_20_cdd[i] %
1213 BRCMS_TXPWR_DB_FACTOR]);
1214 printk(KERN_DEBUG "%s\n", buf);
1215
1216 sprintf(buf, "20 MHz MCS0-7 STBC ");
1217 for (i = 0; i < BRCMS_NUM_RATES_MCS_1_STREAM; i++)
1218 sprintf(buf[strlen(buf)], " %2d%s",
1219 txpwr->mcs_20_stbc[i] / BRCMS_TXPWR_DB_FACTOR,
1220 fraction[txpwr->mcs_20_stbc[i] %
1221 BRCMS_TXPWR_DB_FACTOR]);
1222 printk(KERN_DEBUG "%s\n", buf);
1223
1224 sprintf(buf, "20 MHz MCS8-15 SDM ");
1225 for (i = 0; i < BRCMS_NUM_RATES_MCS_2_STREAM; i++)
1226 sprintf(buf[strlen(buf)], " %2d%s",
1227 txpwr->mcs_20_mimo[i] / BRCMS_TXPWR_DB_FACTOR,
1228 fraction[txpwr->mcs_20_mimo[i] %
1229 BRCMS_TXPWR_DB_FACTOR]);
1230 printk(KERN_DEBUG "%s\n", buf);
1231
1232 sprintf(buf, "40 MHz MCS0-7 SISO ");
1233 for (i = 0; i < BRCMS_NUM_RATES_MCS_1_STREAM; i++)
1234 sprintf(buf[strlen(buf)], " %2d%s",
1235 txpwr->mcs_40_siso[i] / BRCMS_TXPWR_DB_FACTOR,
1236 fraction[txpwr->mcs_40_siso[i] %
1237 BRCMS_TXPWR_DB_FACTOR]);
1238 printk(KERN_DEBUG "%s\n", buf);
1239
1240 sprintf(buf, "40 MHz MCS0-7 CDD ");
1241 for (i = 0; i < BRCMS_NUM_RATES_MCS_1_STREAM; i++)
1242 sprintf(buf[strlen(buf)], " %2d%s",
1243 txpwr->mcs_40_cdd[i] / BRCMS_TXPWR_DB_FACTOR,
1244 fraction[txpwr->mcs_40_cdd[i] %
1245 BRCMS_TXPWR_DB_FACTOR]);
1246 printk(KERN_DEBUG "%s\n", buf);
1247
1248 sprintf(buf, "40 MHz MCS0-7 STBC ");
1249 for (i = 0; i < BRCMS_NUM_RATES_MCS_1_STREAM; i++)
1250 sprintf(buf[strlen(buf)], " %2d%s",
1251 txpwr->mcs_40_stbc[i] / BRCMS_TXPWR_DB_FACTOR,
1252 fraction[txpwr->mcs_40_stbc[i] %
1253 BRCMS_TXPWR_DB_FACTOR]);
1254 printk(KERN_DEBUG "%s\n", buf);
1255
1256 sprintf(buf, "40 MHz MCS8-15 SDM ");
1257 for (i = 0; i < BRCMS_NUM_RATES_MCS_2_STREAM; i++)
1258 sprintf(buf[strlen(buf)], " %2d%s",
1259 txpwr->mcs_40_mimo[i] / BRCMS_TXPWR_DB_FACTOR,
1260 fraction[txpwr->mcs_40_mimo[i] %
1261 BRCMS_TXPWR_DB_FACTOR]);
1262 }
1263 printk(KERN_DEBUG "%s\n", buf);
1264
1265 printk(KERN_DEBUG "MCS32 %2d%s\n",
1266 txpwr->mcs32 / BRCMS_TXPWR_DB_FACTOR,
1267 fraction[txpwr->mcs32 % BRCMS_TXPWR_DB_FACTOR]);
1268}
1269#endif /* POWER_DBG */
1270
1271void 1156void
1272brcms_c_channel_reg_limits(struct brcms_cm_info *wlc_cm, u16 chanspec, 1157brcms_c_channel_reg_limits(struct brcms_cm_info *wlc_cm, u16 chanspec,
1273 struct txpwr_limits *txpwr) 1158 struct txpwr_limits *txpwr)
@@ -1478,9 +1363,6 @@ brcms_c_channel_reg_limits(struct brcms_cm_info *wlc_cm, u16 chanspec,
1478 txpwr->mcs_40_stbc[i] = txpwr->mcs_40_cdd[i]; 1363 txpwr->mcs_40_stbc[i] = txpwr->mcs_40_cdd[i];
1479 } 1364 }
1480 1365
1481#ifdef POWER_DBG
1482 wlc_phy_txpower_limits_dump(txpwr);
1483#endif
1484 return; 1366 return;
1485} 1367}
1486 1368
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/dma.c b/drivers/net/wireless/brcm80211/brcmsmac/dma.c
index b56a30297c26..e286fb4d4813 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/dma.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/dma.c
@@ -14,7 +14,6 @@
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16#include <linux/slab.h> 16#include <linux/slab.h>
17#include <linux/skbuff.h>
18#include <linux/delay.h> 17#include <linux/delay.h>
19#include <linux/pci.h> 18#include <linux/pci.h>
20 19
@@ -22,6 +21,7 @@
22#include <aiutils.h> 21#include <aiutils.h>
23#include "types.h" 22#include "types.h"
24#include "dma.h" 23#include "dma.h"
24#include "soc.h"
25 25
26/* 26/*
27 * DMA hardware requires each descriptor ring to be 8kB aligned, and fit within 27 * DMA hardware requires each descriptor ring to be 8kB aligned, and fit within
@@ -358,13 +358,14 @@ static uint nrxdactive(struct dma_info *di, uint h, uint t)
358 358
359static uint _dma_ctrlflags(struct dma_info *di, uint mask, uint flags) 359static uint _dma_ctrlflags(struct dma_info *di, uint mask, uint flags)
360{ 360{
361 uint dmactrlflags = di->dma.dmactrlflags; 361 uint dmactrlflags;
362 362
363 if (di == NULL) { 363 if (di == NULL) {
364 DMA_ERROR(("%s: _dma_ctrlflags: NULL dma handle\n", di->name)); 364 DMA_ERROR(("_dma_ctrlflags: NULL dma handle\n"));
365 return 0; 365 return 0;
366 } 366 }
367 367
368 dmactrlflags = di->dma.dmactrlflags;
368 dmactrlflags &= ~mask; 369 dmactrlflags &= ~mask;
369 dmactrlflags |= flags; 370 dmactrlflags |= flags;
370 371
@@ -900,7 +901,7 @@ static struct sk_buff *_dma_getnextrxp(struct dma_info *di, bool forceall)
900 901
901/* 902/*
902 * !! rx entry routine 903 * !! rx entry routine
903 * returns a pointer to the next frame received, or NULL if there are no more 904 * returns the number packages in the next frame, or 0 if there are no more
904 * if DMA_CTRL_RXMULTI is defined, DMA scattering(multiple buffers) is 905 * if DMA_CTRL_RXMULTI is defined, DMA scattering(multiple buffers) is
905 * supported with pkts chain 906 * supported with pkts chain
906 * otherwise, it's treated as giant pkt and will be tossed. 907 * otherwise, it's treated as giant pkt and will be tossed.
@@ -908,38 +909,40 @@ static struct sk_buff *_dma_getnextrxp(struct dma_info *di, bool forceall)
908 * buffer data. After it reaches the max size of buffer, the data continues 909 * buffer data. After it reaches the max size of buffer, the data continues
909 * in next DMA descriptor buffer WITHOUT DMA header 910 * in next DMA descriptor buffer WITHOUT DMA header
910 */ 911 */
911struct sk_buff *dma_rx(struct dma_pub *pub) 912int dma_rx(struct dma_pub *pub, struct sk_buff_head *skb_list)
912{ 913{
913 struct dma_info *di = (struct dma_info *)pub; 914 struct dma_info *di = (struct dma_info *)pub;
914 struct sk_buff *p, *head, *tail; 915 struct sk_buff_head dma_frames;
916 struct sk_buff *p, *next;
915 uint len; 917 uint len;
916 uint pkt_len; 918 uint pkt_len;
917 int resid = 0; 919 int resid = 0;
920 int pktcnt = 1;
918 921
922 skb_queue_head_init(&dma_frames);
919 next_frame: 923 next_frame:
920 head = _dma_getnextrxp(di, false); 924 p = _dma_getnextrxp(di, false);
921 if (head == NULL) 925 if (p == NULL)
922 return NULL; 926 return 0;
923 927
924 len = le16_to_cpu(*(__le16 *) (head->data)); 928 len = le16_to_cpu(*(__le16 *) (p->data));
925 DMA_TRACE(("%s: dma_rx len %d\n", di->name, len)); 929 DMA_TRACE(("%s: dma_rx len %d\n", di->name, len));
926 dma_spin_for_len(len, head); 930 dma_spin_for_len(len, p);
927 931
928 /* set actual length */ 932 /* set actual length */
929 pkt_len = min((di->rxoffset + len), di->rxbufsize); 933 pkt_len = min((di->rxoffset + len), di->rxbufsize);
930 __skb_trim(head, pkt_len); 934 __skb_trim(p, pkt_len);
935 skb_queue_tail(&dma_frames, p);
931 resid = len - (di->rxbufsize - di->rxoffset); 936 resid = len - (di->rxbufsize - di->rxoffset);
932 937
933 /* check for single or multi-buffer rx */ 938 /* check for single or multi-buffer rx */
934 if (resid > 0) { 939 if (resid > 0) {
935 tail = head;
936 while ((resid > 0) && (p = _dma_getnextrxp(di, false))) { 940 while ((resid > 0) && (p = _dma_getnextrxp(di, false))) {
937 tail->next = p;
938 pkt_len = min_t(uint, resid, di->rxbufsize); 941 pkt_len = min_t(uint, resid, di->rxbufsize);
939 __skb_trim(p, pkt_len); 942 __skb_trim(p, pkt_len);
940 943 skb_queue_tail(&dma_frames, p);
941 tail = p;
942 resid -= di->rxbufsize; 944 resid -= di->rxbufsize;
945 pktcnt++;
943 } 946 }
944 947
945#ifdef BCMDBG 948#ifdef BCMDBG
@@ -958,13 +961,18 @@ struct sk_buff *dma_rx(struct dma_pub *pub)
958 if ((di->dma.dmactrlflags & DMA_CTRL_RXMULTI) == 0) { 961 if ((di->dma.dmactrlflags & DMA_CTRL_RXMULTI) == 0) {
959 DMA_ERROR(("%s: dma_rx: bad frame length (%d)\n", 962 DMA_ERROR(("%s: dma_rx: bad frame length (%d)\n",
960 di->name, len)); 963 di->name, len));
961 brcmu_pkt_buf_free_skb(head); 964 skb_queue_walk_safe(&dma_frames, p, next) {
965 skb_unlink(p, &dma_frames);
966 brcmu_pkt_buf_free_skb(p);
967 }
962 di->dma.rxgiants++; 968 di->dma.rxgiants++;
969 pktcnt = 1;
963 goto next_frame; 970 goto next_frame;
964 } 971 }
965 } 972 }
966 973
967 return head; 974 skb_queue_splice_tail(&dma_frames, skb_list);
975 return pktcnt;
968} 976}
969 977
970static bool dma64_rxidle(struct dma_info *di) 978static bool dma64_rxidle(struct dma_info *di)
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/dma.h b/drivers/net/wireless/brcm80211/brcmsmac/dma.h
index ebc5bc546f3b..d317c7c12f91 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/dma.h
+++ b/drivers/net/wireless/brcm80211/brcmsmac/dma.h
@@ -18,6 +18,7 @@
18#define _BRCM_DMA_H_ 18#define _BRCM_DMA_H_
19 19
20#include <linux/delay.h> 20#include <linux/delay.h>
21#include <linux/skbuff.h>
21#include "types.h" /* forward structure declarations */ 22#include "types.h" /* forward structure declarations */
22 23
23/* map/unmap direction */ 24/* map/unmap direction */
@@ -80,7 +81,7 @@ extern struct dma_pub *dma_attach(char *name, struct si_pub *sih,
80 uint nrxpost, uint rxoffset, uint *msg_level); 81 uint nrxpost, uint rxoffset, uint *msg_level);
81 82
82void dma_rxinit(struct dma_pub *pub); 83void dma_rxinit(struct dma_pub *pub);
83struct sk_buff *dma_rx(struct dma_pub *pub); 84int dma_rx(struct dma_pub *pub, struct sk_buff_head *skb_list);
84bool dma_rxfill(struct dma_pub *pub); 85bool dma_rxfill(struct dma_pub *pub);
85bool dma_rxreset(struct dma_pub *pub); 86bool dma_rxreset(struct dma_pub *pub);
86bool dma_txreset(struct dma_pub *pub); 87bool dma_txreset(struct dma_pub *pub);
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c b/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c
index 0d8a9cdf897a..8457e969eb4f 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c
@@ -216,8 +216,7 @@ static const struct ieee80211_supported_band brcms_band_2GHz_nphy_template = {
216 .ht_cap = { 216 .ht_cap = {
217 /* from include/linux/ieee80211.h */ 217 /* from include/linux/ieee80211.h */
218 .cap = IEEE80211_HT_CAP_GRN_FLD | 218 .cap = IEEE80211_HT_CAP_GRN_FLD |
219 IEEE80211_HT_CAP_SGI_20 | 219 IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40,
220 IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_40MHZ_INTOLERANT,
221 .ht_supported = true, 220 .ht_supported = true,
222 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K, 221 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K,
223 .ampdu_density = AMPDU_DEF_MPDU_DENSITY, 222 .ampdu_density = AMPDU_DEF_MPDU_DENSITY,
@@ -238,8 +237,7 @@ static const struct ieee80211_supported_band brcms_band_5GHz_nphy_template = {
238 BRCMS_LEGACY_5G_RATE_OFFSET, 237 BRCMS_LEGACY_5G_RATE_OFFSET,
239 .ht_cap = { 238 .ht_cap = {
240 .cap = IEEE80211_HT_CAP_GRN_FLD | IEEE80211_HT_CAP_SGI_20 | 239 .cap = IEEE80211_HT_CAP_GRN_FLD | IEEE80211_HT_CAP_SGI_20 |
241 IEEE80211_HT_CAP_SGI_40 | 240 IEEE80211_HT_CAP_SGI_40,
242 IEEE80211_HT_CAP_40MHZ_INTOLERANT, /* No 40 mhz yet */
243 .ht_supported = true, 241 .ht_supported = true,
244 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K, 242 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K,
245 .ampdu_density = AMPDU_DEF_MPDU_DENSITY, 243 .ampdu_density = AMPDU_DEF_MPDU_DENSITY,
@@ -287,6 +285,7 @@ static int brcms_ops_start(struct ieee80211_hw *hw)
287{ 285{
288 struct brcms_info *wl = hw->priv; 286 struct brcms_info *wl = hw->priv;
289 bool blocked; 287 bool blocked;
288 int err;
290 289
291 ieee80211_wake_queues(hw); 290 ieee80211_wake_queues(hw);
292 spin_lock_bh(&wl->lock); 291 spin_lock_bh(&wl->lock);
@@ -295,57 +294,69 @@ static int brcms_ops_start(struct ieee80211_hw *hw)
295 if (!blocked) 294 if (!blocked)
296 wiphy_rfkill_stop_polling(wl->pub->ieee_hw->wiphy); 295 wiphy_rfkill_stop_polling(wl->pub->ieee_hw->wiphy);
297 296
298 return 0; 297 spin_lock_bh(&wl->lock);
298 /* avoid acknowledging frames before a non-monitor device is added */
299 wl->mute_tx = true;
300
301 if (!wl->pub->up)
302 err = brcms_up(wl);
303 else
304 err = -ENODEV;
305 spin_unlock_bh(&wl->lock);
306
307 if (err != 0)
308 wiphy_err(hw->wiphy, "%s: brcms_up() returned %d\n", __func__,
309 err);
310 return err;
299} 311}
300 312
301static void brcms_ops_stop(struct ieee80211_hw *hw) 313static void brcms_ops_stop(struct ieee80211_hw *hw)
302{ 314{
315 struct brcms_info *wl = hw->priv;
316 int status;
317
303 ieee80211_stop_queues(hw); 318 ieee80211_stop_queues(hw);
319
320 if (wl->wlc == NULL)
321 return;
322
323 spin_lock_bh(&wl->lock);
324 status = brcms_c_chipmatch(wl->wlc->hw->vendorid,
325 wl->wlc->hw->deviceid);
326 spin_unlock_bh(&wl->lock);
327 if (!status) {
328 wiphy_err(wl->wiphy,
329 "wl: brcms_ops_stop: chipmatch failed\n");
330 return;
331 }
332
333 /* put driver in down state */
334 spin_lock_bh(&wl->lock);
335 brcms_down(wl);
336 spin_unlock_bh(&wl->lock);
304} 337}
305 338
306static int 339static int
307brcms_ops_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 340brcms_ops_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
308{ 341{
309 struct brcms_info *wl; 342 struct brcms_info *wl = hw->priv;
310 int err;
311 343
312 /* Just STA for now */ 344 /* Just STA for now */
313 if (vif->type != NL80211_IFTYPE_AP && 345 if (vif->type != NL80211_IFTYPE_STATION) {
314 vif->type != NL80211_IFTYPE_MESH_POINT &&
315 vif->type != NL80211_IFTYPE_STATION &&
316 vif->type != NL80211_IFTYPE_WDS &&
317 vif->type != NL80211_IFTYPE_ADHOC) {
318 wiphy_err(hw->wiphy, "%s: Attempt to add type %d, only" 346 wiphy_err(hw->wiphy, "%s: Attempt to add type %d, only"
319 " STA for now\n", __func__, vif->type); 347 " STA for now\n", __func__, vif->type);
320 return -EOPNOTSUPP; 348 return -EOPNOTSUPP;
321 } 349 }
322 350
323 wl = hw->priv; 351 wl->mute_tx = false;
324 spin_lock_bh(&wl->lock); 352 brcms_c_mute(wl->wlc, false);
325 if (!wl->pub->up)
326 err = brcms_up(wl);
327 else
328 err = -ENODEV;
329 spin_unlock_bh(&wl->lock);
330
331 if (err != 0)
332 wiphy_err(hw->wiphy, "%s: brcms_up() returned %d\n", __func__,
333 err);
334 353
335 return err; 354 return 0;
336} 355}
337 356
338static void 357static void
339brcms_ops_remove_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 358brcms_ops_remove_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
340{ 359{
341 struct brcms_info *wl;
342
343 wl = hw->priv;
344
345 /* put driver in down state */
346 spin_lock_bh(&wl->lock);
347 brcms_down(wl);
348 spin_unlock_bh(&wl->lock);
349} 360}
350 361
351static int brcms_ops_config(struct ieee80211_hw *hw, u32 changed) 362static int brcms_ops_config(struct ieee80211_hw *hw, u32 changed)
@@ -609,13 +620,6 @@ brcms_ops_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
609 wl->pub->global_ampdu->scb = scb; 620 wl->pub->global_ampdu->scb = scb;
610 wl->pub->global_ampdu->max_pdu = 16; 621 wl->pub->global_ampdu->max_pdu = 16;
611 622
612 sta->ht_cap.ht_supported = true;
613 sta->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
614 sta->ht_cap.ampdu_density = AMPDU_DEF_MPDU_DENSITY;
615 sta->ht_cap.cap = IEEE80211_HT_CAP_GRN_FLD |
616 IEEE80211_HT_CAP_SGI_20 |
617 IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_40MHZ_INTOLERANT;
618
619 /* 623 /*
620 * minstrel_ht initiates addBA on our behalf by calling 624 * minstrel_ht initiates addBA on our behalf by calling
621 * ieee80211_start_tx_ba_session() 625 * ieee80211_start_tx_ba_session()
@@ -877,37 +881,18 @@ static void brcms_free(struct brcms_info *wl)
877} 881}
878 882
879/* 883/*
880* called from both kernel as from this kernel module. 884* called from both kernel as from this kernel module (error flow on attach)
881* precondition: perimeter lock is not acquired. 885* precondition: perimeter lock is not acquired.
882*/ 886*/
883static void brcms_remove(struct pci_dev *pdev) 887static void brcms_remove(struct pci_dev *pdev)
884{ 888{
885 struct brcms_info *wl; 889 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
886 struct ieee80211_hw *hw; 890 struct brcms_info *wl = hw->priv;
887 int status;
888
889 hw = pci_get_drvdata(pdev);
890 wl = hw->priv;
891 if (!wl) {
892 pr_err("wl: brcms_remove: pci_get_drvdata failed\n");
893 return;
894 }
895 891
896 spin_lock_bh(&wl->lock);
897 status = brcms_c_chipmatch(pdev->vendor, pdev->device);
898 spin_unlock_bh(&wl->lock);
899 if (!status) {
900 wiphy_err(wl->wiphy, "wl: brcms_remove: chipmatch "
901 "failed\n");
902 return;
903 }
904 if (wl->wlc) { 892 if (wl->wlc) {
905 wiphy_rfkill_set_hw_state(wl->pub->ieee_hw->wiphy, false); 893 wiphy_rfkill_set_hw_state(wl->pub->ieee_hw->wiphy, false);
906 wiphy_rfkill_stop_polling(wl->pub->ieee_hw->wiphy); 894 wiphy_rfkill_stop_polling(wl->pub->ieee_hw->wiphy);
907 ieee80211_unregister_hw(hw); 895 ieee80211_unregister_hw(hw);
908 spin_lock_bh(&wl->lock);
909 brcms_down(wl);
910 spin_unlock_bh(&wl->lock);
911 } 896 }
912 pci_disable_device(pdev); 897 pci_disable_device(pdev);
913 898
@@ -1081,9 +1066,6 @@ static struct brcms_info *brcms_attach(u16 vendor, u16 device,
1081 1066
1082 wl->pub->ieee_hw = hw; 1067 wl->pub->ieee_hw = hw;
1083 1068
1084 /* disable mpc */
1085 brcms_c_set_radio_mpc(wl->wlc, false);
1086
1087 /* register our interrupt handler */ 1069 /* register our interrupt handler */
1088 if (request_irq(irq, brcms_isr, IRQF_SHARED, KBUILD_MODNAME, wl)) { 1070 if (request_irq(irq, brcms_isr, IRQF_SHARED, KBUILD_MODNAME, wl)) {
1089 wiphy_err(wl->wiphy, "wl%d: request_irq() failed\n", unit); 1071 wiphy_err(wl->wiphy, "wl%d: request_irq() failed\n", unit);
@@ -1319,8 +1301,7 @@ void brcms_init(struct brcms_info *wl)
1319{ 1301{
1320 BCMMSG(wl->pub->ieee_hw->wiphy, "wl%d\n", wl->pub->unit); 1302 BCMMSG(wl->pub->ieee_hw->wiphy, "wl%d\n", wl->pub->unit);
1321 brcms_reset(wl); 1303 brcms_reset(wl);
1322 1304 brcms_c_init(wl->wlc, wl->mute_tx);
1323 brcms_c_init(wl->wlc);
1324} 1305}
1325 1306
1326/* 1307/*
@@ -1337,6 +1318,14 @@ uint brcms_reset(struct brcms_info *wl)
1337 return 0; 1318 return 0;
1338} 1319}
1339 1320
1321void brcms_fatal_error(struct brcms_info *wl)
1322{
1323 wiphy_err(wl->wlc->wiphy, "wl%d: fatal error, reinitializing\n",
1324 wl->wlc->pub->unit);
1325 brcms_reset(wl);
1326 ieee80211_restart_hw(wl->pub->ieee_hw);
1327}
1328
1340/* 1329/*
1341 * These are interrupt on/off entry points. Disable interrupts 1330 * These are interrupt on/off entry points. Disable interrupts
1342 * during interrupt state transition. 1331 * during interrupt state transition.
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.h b/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.h
index 177f0e44e4b6..6242f188b717 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.h
+++ b/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.h
@@ -80,6 +80,7 @@ struct brcms_info {
80 struct brcms_firmware fw; 80 struct brcms_firmware fw;
81 struct wiphy *wiphy; 81 struct wiphy *wiphy;
82 struct brcms_ucode ucode; 82 struct brcms_ucode ucode;
83 bool mute_tx;
83}; 84};
84 85
85/* misc callbacks */ 86/* misc callbacks */
@@ -104,5 +105,6 @@ extern bool brcms_del_timer(struct brcms_timer *timer);
104extern void brcms_msleep(struct brcms_info *wl, uint ms); 105extern void brcms_msleep(struct brcms_info *wl, uint ms);
105extern void brcms_dpc(unsigned long data); 106extern void brcms_dpc(unsigned long data);
106extern void brcms_timer(struct brcms_timer *t); 107extern void brcms_timer(struct brcms_timer *t);
108extern void brcms_fatal_error(struct brcms_info *wl);
107 109
108#endif /* _BRCM_MAC80211_IF_H_ */ 110#endif /* _BRCM_MAC80211_IF_H_ */
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/main.c b/drivers/net/wireless/brcm80211/brcmsmac/main.c
index 510e9bb52287..36e3e0638300 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
@@ -30,44 +30,21 @@
30#include "mac80211_if.h" 30#include "mac80211_if.h"
31#include "ucode_loader.h" 31#include "ucode_loader.h"
32#include "main.h" 32#include "main.h"
33#include "soc.h"
33 34
34/* 35/*
35 * Indication for txflowcontrol that all priority bits in 36 * Indication for txflowcontrol that all priority bits in
36 * TXQ_STOP_FOR_PRIOFC_MASK are to be considered. 37 * TXQ_STOP_FOR_PRIOFC_MASK are to be considered.
37 */ 38 */
38#define ALLPRIO -1 39#define ALLPRIO -1
39
40/*
41 * 32 SSID chars, max of 4 chars for each SSID char "\xFF", plus NULL.
42 */
43#define SSID_FMT_BUF_LEN ((4 * IEEE80211_MAX_SSID_LEN) + 1)
44 40
45/* watchdog timer, in unit of ms */ 41/* watchdog timer, in unit of ms */
46#define TIMER_INTERVAL_WATCHDOG 1000 42#define TIMER_INTERVAL_WATCHDOG 1000
47/* radio monitor timer, in unit of ms */ 43/* radio monitor timer, in unit of ms */
48#define TIMER_INTERVAL_RADIOCHK 800 44#define TIMER_INTERVAL_RADIOCHK 800
49
50/* Max MPC timeout, in unit of watchdog */
51#ifndef BRCMS_MPC_MAX_DELAYCNT
52#define BRCMS_MPC_MAX_DELAYCNT 10
53#endif
54
55/* Min MPC timeout, in unit of watchdog */
56#define BRCMS_MPC_MIN_DELAYCNT 1
57#define BRCMS_MPC_THRESHOLD 3 /* MPC count threshold level */
58 45
59/* beacon interval, in unit of 1024TU */ 46/* beacon interval, in unit of 1024TU */
60#define BEACON_INTERVAL_DEFAULT 100 47#define BEACON_INTERVAL_DEFAULT 100
61/* DTIM interval, in unit of beacon interval */
62#define DTIM_INTERVAL_DEFAULT 3
63
64/* Scale down delays to accommodate QT slow speed */
65/* beacon interval, in unit of 1024TU */
66#define BEACON_INTERVAL_DEF_QT 20
67/* DTIM interval, in unit of beacon interval */
68#define DTIM_INTERVAL_DEF_QT 1
69
70#define TBTT_ALIGN_LEEWAY_US 100 /* min leeway before first TBTT in us */
71 48
72/* n-mode support capability */ 49/* n-mode support capability */
73/* 2x2 includes both 1x1 & 2x2 devices 50/* 2x2 includes both 1x1 & 2x2 devices
@@ -78,113 +55,71 @@
78#define WL_11N_3x3 3 55#define WL_11N_3x3 3
79#define WL_11N_4x4 4 56#define WL_11N_4x4 4
80 57
81/* define 11n feature disable flags */ 58#define EDCF_ACI_MASK 0x60
82#define WLFEATURE_DISABLE_11N 0x00000001 59#define EDCF_ACI_SHIFT 5
83#define WLFEATURE_DISABLE_11N_STBC_TX 0x00000002 60#define EDCF_ECWMIN_MASK 0x0f
84#define WLFEATURE_DISABLE_11N_STBC_RX 0x00000004 61#define EDCF_ECWMAX_SHIFT 4
85#define WLFEATURE_DISABLE_11N_SGI_TX 0x00000008 62#define EDCF_AIFSN_MASK 0x0f
86#define WLFEATURE_DISABLE_11N_SGI_RX 0x00000010 63#define EDCF_AIFSN_MAX 15
87#define WLFEATURE_DISABLE_11N_AMPDU_TX 0x00000020 64#define EDCF_ECWMAX_MASK 0xf0
88#define WLFEATURE_DISABLE_11N_AMPDU_RX 0x00000040 65
89#define WLFEATURE_DISABLE_11N_GF 0x00000080 66#define EDCF_AC_BE_TXOP_STA 0x0000
90 67#define EDCF_AC_BK_TXOP_STA 0x0000
91#define EDCF_ACI_MASK 0x60 68#define EDCF_AC_VO_ACI_STA 0x62
92#define EDCF_ACI_SHIFT 5 69#define EDCF_AC_VO_ECW_STA 0x32
93#define EDCF_ECWMIN_MASK 0x0f 70#define EDCF_AC_VI_ACI_STA 0x42
94#define EDCF_ECWMAX_SHIFT 4 71#define EDCF_AC_VI_ECW_STA 0x43
95#define EDCF_AIFSN_MASK 0x0f 72#define EDCF_AC_BK_ECW_STA 0xA4
96#define EDCF_AIFSN_MAX 15 73#define EDCF_AC_VI_TXOP_STA 0x005e
97#define EDCF_ECWMAX_MASK 0xf0 74#define EDCF_AC_VO_TXOP_STA 0x002f
98 75#define EDCF_AC_BE_ACI_STA 0x03
99#define EDCF_AC_BE_TXOP_STA 0x0000 76#define EDCF_AC_BE_ECW_STA 0xA4
100#define EDCF_AC_BK_TXOP_STA 0x0000 77#define EDCF_AC_BK_ACI_STA 0x27
101#define EDCF_AC_VO_ACI_STA 0x62 78#define EDCF_AC_VO_TXOP_AP 0x002f
102#define EDCF_AC_VO_ECW_STA 0x32 79
103#define EDCF_AC_VI_ACI_STA 0x42 80#define EDCF_TXOP2USEC(txop) ((txop) << 5)
104#define EDCF_AC_VI_ECW_STA 0x43 81#define EDCF_ECW2CW(exp) ((1 << (exp)) - 1)
105#define EDCF_AC_BK_ECW_STA 0xA4 82
106#define EDCF_AC_VI_TXOP_STA 0x005e 83#define APHY_SYMBOL_TIME 4
107#define EDCF_AC_VO_TXOP_STA 0x002f 84#define APHY_PREAMBLE_TIME 16
108#define EDCF_AC_BE_ACI_STA 0x03 85#define APHY_SIGNAL_TIME 4
109#define EDCF_AC_BE_ECW_STA 0xA4 86#define APHY_SIFS_TIME 16
110#define EDCF_AC_BK_ACI_STA 0x27 87#define APHY_SERVICE_NBITS 16
111#define EDCF_AC_VO_TXOP_AP 0x002f 88#define APHY_TAIL_NBITS 6
112 89#define BPHY_SIFS_TIME 10
113#define EDCF_TXOP2USEC(txop) ((txop) << 5) 90#define BPHY_PLCP_SHORT_TIME 96
114#define EDCF_ECW2CW(exp) ((1 << (exp)) - 1) 91
115 92#define PREN_PREAMBLE 24
116#define APHY_SYMBOL_TIME 4 93#define PREN_MM_EXT 12
117#define APHY_PREAMBLE_TIME 16 94#define PREN_PREAMBLE_EXT 4
118#define APHY_SIGNAL_TIME 4
119#define APHY_SIFS_TIME 16
120#define APHY_SERVICE_NBITS 16
121#define APHY_TAIL_NBITS 6
122#define BPHY_SIFS_TIME 10
123#define BPHY_PLCP_SHORT_TIME 96
124
125#define PREN_PREAMBLE 24
126#define PREN_MM_EXT 12
127#define PREN_PREAMBLE_EXT 4
128 95
129#define DOT11_MAC_HDR_LEN 24 96#define DOT11_MAC_HDR_LEN 24
130#define DOT11_ACK_LEN 10 97#define DOT11_ACK_LEN 10
131#define DOT11_BA_LEN 4 98#define DOT11_BA_LEN 4
132#define DOT11_OFDM_SIGNAL_EXTENSION 6 99#define DOT11_OFDM_SIGNAL_EXTENSION 6
133#define DOT11_MIN_FRAG_LEN 256 100#define DOT11_MIN_FRAG_LEN 256
134#define DOT11_RTS_LEN 16 101#define DOT11_RTS_LEN 16
135#define DOT11_CTS_LEN 10 102#define DOT11_CTS_LEN 10
136#define DOT11_BA_BITMAP_LEN 128 103#define DOT11_BA_BITMAP_LEN 128
137#define DOT11_MIN_BEACON_PERIOD 1 104#define DOT11_MIN_BEACON_PERIOD 1
138#define DOT11_MAX_BEACON_PERIOD 0xFFFF 105#define DOT11_MAX_BEACON_PERIOD 0xFFFF
139#define DOT11_MAXNUMFRAGS 16 106#define DOT11_MAXNUMFRAGS 16
140#define DOT11_MAX_FRAG_LEN 2346 107#define DOT11_MAX_FRAG_LEN 2346
141 108
142#define BPHY_PLCP_TIME 192 109#define BPHY_PLCP_TIME 192
143#define RIFS_11N_TIME 2 110#define RIFS_11N_TIME 2
144
145#define WME_VER 1
146#define WME_SUBTYPE_PARAM_IE 1
147#define WME_TYPE 2
148#define WME_OUI "\x00\x50\xf2"
149
150#define AC_BE 0
151#define AC_BK 1
152#define AC_VI 2
153#define AC_VO 3
154 111
155#define BCN_TMPL_LEN 512 /* length of the BCN template area */ 112/* length of the BCN template area */
113#define BCN_TMPL_LEN 512
156 114
157/* brcms_bss_info flag bit values */ 115/* brcms_bss_info flag bit values */
158#define BRCMS_BSS_HT 0x0020 /* BSS is HT (MIMO) capable */ 116#define BRCMS_BSS_HT 0x0020 /* BSS is HT (MIMO) capable */
159 117
160/* Flags used in brcms_c_txq_info.stopped */ 118/* chip rx buffer offset */
161/* per prio flow control bits */ 119#define BRCMS_HWRXOFF 38
162#define TXQ_STOP_FOR_PRIOFC_MASK 0x000000FF
163/* stop txq enqueue for packet drain */
164#define TXQ_STOP_FOR_PKT_DRAIN 0x00000100
165/* stop txq enqueue for ampdu flow control */
166#define TXQ_STOP_FOR_AMPDU_FLOW_CNTRL 0x00000200
167
168#define BRCMS_HWRXOFF 38 /* chip rx buffer offset */
169
170/* Find basic rate for a given rate */
171static u8 brcms_basic_rate(struct brcms_c_info *wlc, u32 rspec)
172{
173 if (is_mcs_rate(rspec))
174 return wlc->band->basic_rate[mcs_table[rspec & RSPEC_RATE_MASK]
175 .leg_ofdm];
176 return wlc->band->basic_rate[rspec & RSPEC_RATE_MASK];
177}
178
179static u16 frametype(u32 rspec, u8 mimoframe)
180{
181 if (is_mcs_rate(rspec))
182 return mimoframe;
183 return is_cck_rate(rspec) ? FT_CCK : FT_OFDM;
184}
185 120
186/* rfdisable delay timer 500 ms, runs of ALP clock */ 121/* rfdisable delay timer 500 ms, runs of ALP clock */
187#define RFDISABLE_DEFAULT 10000000 122#define RFDISABLE_DEFAULT 10000000
188 123
189#define BRCMS_TEMPSENSE_PERIOD 10 /* 10 second timeout */ 124#define BRCMS_TEMPSENSE_PERIOD 10 /* 10 second timeout */
190 125
@@ -194,87 +129,83 @@ static u16 frametype(u32 rspec, u8 mimoframe)
194 * These constants are used ONLY by wlc_prio2prec_map. Do not use them 129 * These constants are used ONLY by wlc_prio2prec_map. Do not use them
195 * elsewhere. 130 * elsewhere.
196 */ 131 */
197#define _BRCMS_PREC_NONE 0 /* None = - */ 132#define _BRCMS_PREC_NONE 0 /* None = - */
198#define _BRCMS_PREC_BK 2 /* BK - Background */ 133#define _BRCMS_PREC_BK 2 /* BK - Background */
199#define _BRCMS_PREC_BE 4 /* BE - Best-effort */ 134#define _BRCMS_PREC_BE 4 /* BE - Best-effort */
200#define _BRCMS_PREC_EE 6 /* EE - Excellent-effort */ 135#define _BRCMS_PREC_EE 6 /* EE - Excellent-effort */
201#define _BRCMS_PREC_CL 8 /* CL - Controlled Load */ 136#define _BRCMS_PREC_CL 8 /* CL - Controlled Load */
202#define _BRCMS_PREC_VI 10 /* Vi - Video */ 137#define _BRCMS_PREC_VI 10 /* Vi - Video */
203#define _BRCMS_PREC_VO 12 /* Vo - Voice */ 138#define _BRCMS_PREC_VO 12 /* Vo - Voice */
204#define _BRCMS_PREC_NC 14 /* NC - Network Control */ 139#define _BRCMS_PREC_NC 14 /* NC - Network Control */
205 140
206/* The BSS is generating beacons in HW */ 141/* synthpu_dly times in us */
207#define BRCMS_BSSCFG_HW_BCN 0x20 142#define SYNTHPU_DLY_APHY_US 3700
208 143#define SYNTHPU_DLY_BPHY_US 1050
209#define SYNTHPU_DLY_APHY_US 3700 /* a phy synthpu_dly time in us */ 144#define SYNTHPU_DLY_NPHY_US 2048
210#define SYNTHPU_DLY_BPHY_US 1050 /* b/g phy synthpu_dly time in us */ 145#define SYNTHPU_DLY_LPPHY_US 300
211#define SYNTHPU_DLY_NPHY_US 2048 /* n phy REV3 synthpu_dly time in us */ 146
212#define SYNTHPU_DLY_LPPHY_US 300 /* lpphy synthpu_dly time in us */ 147#define ANTCNT 10 /* vanilla M_MAX_ANTCNT val */
213
214#define SYNTHPU_DLY_PHY_US_QT 100 /* QT synthpu_dly time in us */
215
216#define ANTCNT 10 /* vanilla M_MAX_ANTCNT value */
217 148
218/* Per-AC retry limit register definitions; uses defs.h bitfield macros */ 149/* Per-AC retry limit register definitions; uses defs.h bitfield macros */
219#define EDCF_SHORT_S 0 150#define EDCF_SHORT_S 0
220#define EDCF_SFB_S 4 151#define EDCF_SFB_S 4
221#define EDCF_LONG_S 8 152#define EDCF_LONG_S 8
222#define EDCF_LFB_S 12 153#define EDCF_LFB_S 12
223#define EDCF_SHORT_M BITFIELD_MASK(4) 154#define EDCF_SHORT_M BITFIELD_MASK(4)
224#define EDCF_SFB_M BITFIELD_MASK(4) 155#define EDCF_SFB_M BITFIELD_MASK(4)
225#define EDCF_LONG_M BITFIELD_MASK(4) 156#define EDCF_LONG_M BITFIELD_MASK(4)
226#define EDCF_LFB_M BITFIELD_MASK(4) 157#define EDCF_LFB_M BITFIELD_MASK(4)
227 158
228#define RETRY_SHORT_DEF 7 /* Default Short retry Limit */ 159#define RETRY_SHORT_DEF 7 /* Default Short retry Limit */
229#define RETRY_SHORT_MAX 255 /* Maximum Short retry Limit */ 160#define RETRY_SHORT_MAX 255 /* Maximum Short retry Limit */
230#define RETRY_LONG_DEF 4 /* Default Long retry count */ 161#define RETRY_LONG_DEF 4 /* Default Long retry count */
231#define RETRY_SHORT_FB 3 /* Short count for fallback rate */ 162#define RETRY_SHORT_FB 3 /* Short count for fb rate */
232#define RETRY_LONG_FB 2 /* Long count for fallback rate */ 163#define RETRY_LONG_FB 2 /* Long count for fb rate */
233 164
234#define APHY_CWMIN 15 165#define APHY_CWMIN 15
235#define PHY_CWMAX 1023 166#define PHY_CWMAX 1023
236 167
237#define EDCF_AIFSN_MIN 1 168#define EDCF_AIFSN_MIN 1
238 169
239#define FRAGNUM_MASK 0xF 170#define FRAGNUM_MASK 0xF
240 171
241#define APHY_SLOT_TIME 9 172#define APHY_SLOT_TIME 9
242#define BPHY_SLOT_TIME 20 173#define BPHY_SLOT_TIME 20
243 174
244#define WL_SPURAVOID_OFF 0 175#define WL_SPURAVOID_OFF 0
245#define WL_SPURAVOID_ON1 1 176#define WL_SPURAVOID_ON1 1
246#define WL_SPURAVOID_ON2 2 177#define WL_SPURAVOID_ON2 2
247 178
248/* invalid core flags, use the saved coreflags */ 179/* invalid core flags, use the saved coreflags */
249#define BRCMS_USE_COREFLAGS 0xffffffff 180#define BRCMS_USE_COREFLAGS 0xffffffff
250 181
251/* values for PLCPHdr_override */ 182/* values for PLCPHdr_override */
252#define BRCMS_PLCP_AUTO -1 183#define BRCMS_PLCP_AUTO -1
253#define BRCMS_PLCP_SHORT 0 184#define BRCMS_PLCP_SHORT 0
254#define BRCMS_PLCP_LONG 1 185#define BRCMS_PLCP_LONG 1
255 186
256/* values for g_protection_override and n_protection_override */ 187/* values for g_protection_override and n_protection_override */
257#define BRCMS_PROTECTION_AUTO -1 188#define BRCMS_PROTECTION_AUTO -1
258#define BRCMS_PROTECTION_OFF 0 189#define BRCMS_PROTECTION_OFF 0
259#define BRCMS_PROTECTION_ON 1 190#define BRCMS_PROTECTION_ON 1
260#define BRCMS_PROTECTION_MMHDR_ONLY 2 191#define BRCMS_PROTECTION_MMHDR_ONLY 2
261#define BRCMS_PROTECTION_CTS_ONLY 3 192#define BRCMS_PROTECTION_CTS_ONLY 3
262 193
263/* values for g_protection_control and n_protection_control */ 194/* values for g_protection_control and n_protection_control */
264#define BRCMS_PROTECTION_CTL_OFF 0 195#define BRCMS_PROTECTION_CTL_OFF 0
265#define BRCMS_PROTECTION_CTL_LOCAL 1 196#define BRCMS_PROTECTION_CTL_LOCAL 1
266#define BRCMS_PROTECTION_CTL_OVERLAP 2 197#define BRCMS_PROTECTION_CTL_OVERLAP 2
267 198
268/* values for n_protection */ 199/* values for n_protection */
269#define BRCMS_N_PROTECTION_OFF 0 200#define BRCMS_N_PROTECTION_OFF 0
270#define BRCMS_N_PROTECTION_OPTIONAL 1 201#define BRCMS_N_PROTECTION_OPTIONAL 1
271#define BRCMS_N_PROTECTION_20IN40 2 202#define BRCMS_N_PROTECTION_20IN40 2
272#define BRCMS_N_PROTECTION_MIXEDMODE 3 203#define BRCMS_N_PROTECTION_MIXEDMODE 3
273 204
274/* values for band specific 40MHz capabilities */ 205/* values for band specific 40MHz capabilities */
275#define BRCMS_N_BW_20ALL 0 206#define BRCMS_N_BW_20ALL 0
276#define BRCMS_N_BW_40ALL 1 207#define BRCMS_N_BW_40ALL 1
277#define BRCMS_N_BW_20IN2G_40IN5G 2 208#define BRCMS_N_BW_20IN2G_40IN5G 2
278 209
279/* bitflags for SGI support (sgi_rx iovar) */ 210/* bitflags for SGI support (sgi_rx iovar) */
280#define BRCMS_N_SGI_20 0x01 211#define BRCMS_N_SGI_20 0x01
@@ -282,48 +213,42 @@ static u16 frametype(u32 rspec, u8 mimoframe)
282 213
283/* defines used by the nrate iovar */ 214/* defines used by the nrate iovar */
284/* MSC in use,indicates b0-6 holds an mcs */ 215/* MSC in use,indicates b0-6 holds an mcs */
285#define NRATE_MCS_INUSE 0x00000080 216#define NRATE_MCS_INUSE 0x00000080
286/* rate/mcs value */ 217/* rate/mcs value */
287#define NRATE_RATE_MASK 0x0000007f 218#define NRATE_RATE_MASK 0x0000007f
288/* stf mode mask: siso, cdd, stbc, sdm */ 219/* stf mode mask: siso, cdd, stbc, sdm */
289#define NRATE_STF_MASK 0x0000ff00 220#define NRATE_STF_MASK 0x0000ff00
290/* stf mode shift */ 221/* stf mode shift */
291#define NRATE_STF_SHIFT 8 222#define NRATE_STF_SHIFT 8
292/* bit indicates override both rate & mode */
293#define NRATE_OVERRIDE 0x80000000
294/* bit indicate to override mcs only */ 223/* bit indicate to override mcs only */
295#define NRATE_OVERRIDE_MCS_ONLY 0x40000000 224#define NRATE_OVERRIDE_MCS_ONLY 0x40000000
296#define NRATE_SGI_MASK 0x00800000 /* sgi mode */ 225#define NRATE_SGI_MASK 0x00800000 /* sgi mode */
297#define NRATE_SGI_SHIFT 23 /* sgi mode */ 226#define NRATE_SGI_SHIFT 23 /* sgi mode */
298#define NRATE_LDPC_CODING 0x00400000 /* bit indicates adv coding in use */ 227#define NRATE_LDPC_CODING 0x00400000 /* adv coding in use */
299#define NRATE_LDPC_SHIFT 22 /* ldpc shift */ 228#define NRATE_LDPC_SHIFT 22 /* ldpc shift */
300 229
301#define NRATE_STF_SISO 0 /* stf mode SISO */ 230#define NRATE_STF_SISO 0 /* stf mode SISO */
302#define NRATE_STF_CDD 1 /* stf mode CDD */ 231#define NRATE_STF_CDD 1 /* stf mode CDD */
303#define NRATE_STF_STBC 2 /* stf mode STBC */ 232#define NRATE_STF_STBC 2 /* stf mode STBC */
304#define NRATE_STF_SDM 3 /* stf mode SDM */ 233#define NRATE_STF_SDM 3 /* stf mode SDM */
305 234
306#define MAX_DMA_SEGS 4 235#define MAX_DMA_SEGS 4
307 236
308/* Max # of entries in Tx FIFO based on 4kb page size */ 237/* Max # of entries in Tx FIFO based on 4kb page size */
309#define NTXD 256 238#define NTXD 256
310/* Max # of entries in Rx FIFO based on 4kb page size */ 239/* Max # of entries in Rx FIFO based on 4kb page size */
311#define NRXD 256 240#define NRXD 256
312 241
313/* try to keep this # rbufs posted to the chip */ 242/* try to keep this # rbufs posted to the chip */
314#define NRXBUFPOST 32 243#define NRXBUFPOST 32
315 244
316/* data msg txq hiwat mark */ 245/* data msg txq hiwat mark */
317#define BRCMS_DATAHIWAT 50 246#define BRCMS_DATAHIWAT 50
318 247
319/* bounded rx loops */ 248/* max # frames to process in brcms_c_recv() */
320#define RXBND 8 /* max # frames to process in brcms_c_recv() */ 249#define RXBND 8
321#define TXSBND 8 /* max # tx status to process in wlc_txstatus() */ 250/* max # tx status to process in wlc_txstatus() */
322 251#define TXSBND 8
323/*
324 * 32 SSID chars, max of 4 chars for each SSID char "\xFF", plus NULL.
325 */
326#define SSID_FMT_BUF_LEN ((4 * IEEE80211_MAX_SSID_LEN) + 1)
327 252
328/* brcmu_format_flags() bit description structure */ 253/* brcmu_format_flags() bit description structure */
329struct brcms_c_bit_desc { 254struct brcms_c_bit_desc {
@@ -375,10 +300,22 @@ uint brcm_msg_level =
375#endif /* BCMDBG */ 300#endif /* BCMDBG */
376 301
377/* TX FIFO number to WME/802.1E Access Category */ 302/* TX FIFO number to WME/802.1E Access Category */
378static const u8 wme_fifo2ac[] = { AC_BK, AC_BE, AC_VI, AC_VO, AC_BE, AC_BE }; 303static const u8 wme_fifo2ac[] = {
304 IEEE80211_AC_BK,
305 IEEE80211_AC_BE,
306 IEEE80211_AC_VI,
307 IEEE80211_AC_VO,
308 IEEE80211_AC_BE,
309 IEEE80211_AC_BE
310};
379 311
380/* WME/802.1E Access Category to TX FIFO number */ 312/* ieee80211 Access Category to TX FIFO number */
381static const u8 wme_ac2fifo[] = { 1, 0, 2, 3 }; 313static const u8 wme_ac2fifo[] = {
314 TX_AC_VO_FIFO,
315 TX_AC_VI_FIFO,
316 TX_AC_BE_FIFO,
317 TX_AC_BK_FIFO
318};
382 319
383/* 802.1D Priority to precedence queue mapping */ 320/* 802.1D Priority to precedence queue mapping */
384const u8 wlc_prio2prec_map[] = { 321const u8 wlc_prio2prec_map[] = {
@@ -405,13 +342,6 @@ static const u16 xmtfifo_sz[][NFIFO] = {
405 {9, 58, 22, 14, 14, 5}, 342 {9, 58, 22, 14, 14, 5},
406}; 343};
407 344
408static const u8 acbitmap2maxprio[] = {
409 PRIO_8021D_BE, PRIO_8021D_BE, PRIO_8021D_BK, PRIO_8021D_BK,
410 PRIO_8021D_VI, PRIO_8021D_VI, PRIO_8021D_VI, PRIO_8021D_VI,
411 PRIO_8021D_VO, PRIO_8021D_VO, PRIO_8021D_VO, PRIO_8021D_VO,
412 PRIO_8021D_VO, PRIO_8021D_VO, PRIO_8021D_VO, PRIO_8021D_VO
413};
414
415#ifdef BCMDBG 345#ifdef BCMDBG
416static const char * const fifo_names[] = { 346static const char * const fifo_names[] = {
417 "AC_BK", "AC_BE", "AC_VI", "AC_VO", "BCMC", "ATIM" }; 347 "AC_BK", "AC_BE", "AC_VI", "AC_VO", "BCMC", "ATIM" };
@@ -424,6 +354,22 @@ static const char fifo_names[6][0];
424static struct brcms_c_info *wlc_info_dbg = (struct brcms_c_info *) (NULL); 354static struct brcms_c_info *wlc_info_dbg = (struct brcms_c_info *) (NULL);
425#endif 355#endif
426 356
357/* Find basic rate for a given rate */
358static u8 brcms_basic_rate(struct brcms_c_info *wlc, u32 rspec)
359{
360 if (is_mcs_rate(rspec))
361 return wlc->band->basic_rate[mcs_table[rspec & RSPEC_RATE_MASK]
362 .leg_ofdm];
363 return wlc->band->basic_rate[rspec & RSPEC_RATE_MASK];
364}
365
366static u16 frametype(u32 rspec, u8 mimoframe)
367{
368 if (is_mcs_rate(rspec))
369 return mimoframe;
370 return is_cck_rate(rspec) ? FT_CCK : FT_OFDM;
371}
372
427/* currently the best mechanism for determining SIFS is the band in use */ 373/* currently the best mechanism for determining SIFS is the band in use */
428static u16 get_sifs(struct brcms_band *band) 374static u16 get_sifs(struct brcms_band *band)
429{ 375{
@@ -470,20 +416,6 @@ static int brcms_chspec_bw(u16 chanspec)
470 return BRCMS_10_MHZ; 416 return BRCMS_10_MHZ;
471} 417}
472 418
473/*
474 * return true if Minimum Power Consumption should
475 * be entered, false otherwise
476 */
477static bool brcms_c_is_non_delay_mpc(struct brcms_c_info *wlc)
478{
479 return false;
480}
481
482static bool brcms_c_ismpc(struct brcms_c_info *wlc)
483{
484 return (wlc->mpc_delay_off == 0) && (brcms_c_is_non_delay_mpc(wlc));
485}
486
487static void brcms_c_bsscfg_mfree(struct brcms_bss_cfg *cfg) 419static void brcms_c_bsscfg_mfree(struct brcms_bss_cfg *cfg)
488{ 420{
489 if (cfg == NULL) 421 if (cfg == NULL)
@@ -669,9 +601,8 @@ static void brcms_b_update_slot_timing(struct brcms_hardware *wlc_hw,
669 * calculate frame duration of a given rate and length, return 601 * calculate frame duration of a given rate and length, return
670 * time in usec unit 602 * time in usec unit
671 */ 603 */
672uint 604static uint brcms_c_calc_frame_time(struct brcms_c_info *wlc, u32 ratespec,
673brcms_c_calc_frame_time(struct brcms_c_info *wlc, u32 ratespec, 605 u8 preamble_type, uint mac_len)
674 u8 preamble_type, uint mac_len)
675{ 606{
676 uint nsyms, dur = 0, Ndps, kNdps; 607 uint nsyms, dur = 0, Ndps, kNdps;
677 uint rate = rspec2rate(ratespec); 608 uint rate = rspec2rate(ratespec);
@@ -969,7 +900,7 @@ brcms_c_dotxstatus(struct brcms_c_info *wlc, struct tx_status *txs)
969 lfbl, /* Long Frame Rate Fallback Limit */ 900 lfbl, /* Long Frame Rate Fallback Limit */
970 fbl; 901 fbl;
971 902
972 if (queue < AC_COUNT) { 903 if (queue < IEEE80211_NUM_ACS) {
973 sfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]], 904 sfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
974 EDCF_SFB); 905 EDCF_SFB);
975 lfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]], 906 lfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
@@ -1018,7 +949,7 @@ brcms_c_dotxstatus(struct brcms_c_info *wlc, struct tx_status *txs)
1018 tx_info->flags |= IEEE80211_TX_STAT_ACK; 949 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1019 } 950 }
1020 951
1021 totlen = brcmu_pkttotlen(p); 952 totlen = p->len;
1022 free_pdu = true; 953 free_pdu = true;
1023 954
1024 brcms_c_txfifo_complete(wlc, queue, 1); 955 brcms_c_txfifo_complete(wlc, queue, 1);
@@ -2352,13 +2283,6 @@ void brcms_b_antsel_type_set(struct brcms_hardware *wlc_hw, u8 antsel_type)
2352 wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type); 2283 wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2353} 2284}
2354 2285
2355static void brcms_c_fatal_error(struct brcms_c_info *wlc)
2356{
2357 wiphy_err(wlc->wiphy, "wl%d: fatal error, reinitializing\n",
2358 wlc->pub->unit);
2359 brcms_init(wlc->wl);
2360}
2361
2362static void brcms_b_fifoerrors(struct brcms_hardware *wlc_hw) 2286static void brcms_b_fifoerrors(struct brcms_hardware *wlc_hw)
2363{ 2287{
2364 bool fatal = false; 2288 bool fatal = false;
@@ -2414,7 +2338,7 @@ static void brcms_b_fifoerrors(struct brcms_hardware *wlc_hw)
2414 } 2338 }
2415 2339
2416 if (fatal) { 2340 if (fatal) {
2417 brcms_c_fatal_error(wlc_hw->wlc); /* big hammer */ 2341 brcms_fatal_error(wlc_hw->wlc->wl); /* big hammer */
2418 break; 2342 break;
2419 } else 2343 } else
2420 W_REG(&regs->intctrlregs[idx].intstatus, 2344 W_REG(&regs->intctrlregs[idx].intstatus,
@@ -2479,6 +2403,7 @@ void brcms_c_intrsrestore(struct brcms_c_info *wlc, u32 macintmask)
2479 W_REG(&wlc_hw->regs->macintmask, wlc->macintmask); 2403 W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
2480} 2404}
2481 2405
2406/* assumes that the d11 MAC is enabled */
2482static void brcms_b_tx_fifo_suspend(struct brcms_hardware *wlc_hw, 2407static void brcms_b_tx_fifo_suspend(struct brcms_hardware *wlc_hw,
2483 uint tx_fifo) 2408 uint tx_fifo)
2484{ 2409{
@@ -2535,11 +2460,12 @@ static void brcms_b_tx_fifo_resume(struct brcms_hardware *wlc_hw,
2535 } 2460 }
2536} 2461}
2537 2462
2538static void brcms_b_mute(struct brcms_hardware *wlc_hw, bool on, u32 flags) 2463/* precondition: requires the mac core to be enabled */
2464static void brcms_b_mute(struct brcms_hardware *wlc_hw, bool mute_tx)
2539{ 2465{
2540 static const u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0}; 2466 static const u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2541 2467
2542 if (on) { 2468 if (mute_tx) {
2543 /* suspend tx fifos */ 2469 /* suspend tx fifos */
2544 brcms_b_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO); 2470 brcms_b_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2545 brcms_b_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO); 2471 brcms_b_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
@@ -2561,14 +2487,20 @@ static void brcms_b_mute(struct brcms_hardware *wlc_hw, bool on, u32 flags)
2561 wlc_hw->etheraddr); 2487 wlc_hw->etheraddr);
2562 } 2488 }
2563 2489
2564 wlc_phy_mute_upd(wlc_hw->band->pi, on, flags); 2490 wlc_phy_mute_upd(wlc_hw->band->pi, mute_tx, 0);
2565 2491
2566 if (on) 2492 if (mute_tx)
2567 brcms_c_ucode_mute_override_set(wlc_hw); 2493 brcms_c_ucode_mute_override_set(wlc_hw);
2568 else 2494 else
2569 brcms_c_ucode_mute_override_clear(wlc_hw); 2495 brcms_c_ucode_mute_override_clear(wlc_hw);
2570} 2496}
2571 2497
2498void
2499brcms_c_mute(struct brcms_c_info *wlc, bool mute_tx)
2500{
2501 brcms_b_mute(wlc->hw, mute_tx);
2502}
2503
2572/* 2504/*
2573 * Read and clear macintmask and macintstatus and intstatus registers. 2505 * Read and clear macintmask and macintstatus and intstatus registers.
2574 * This routine should be called with interrupts off 2506 * This routine should be called with interrupts off
@@ -3437,8 +3369,7 @@ static void brcms_b_coreinit(struct brcms_c_info *wlc)
3437} 3369}
3438 3370
3439void 3371void
3440static brcms_b_init(struct brcms_hardware *wlc_hw, u16 chanspec, 3372static brcms_b_init(struct brcms_hardware *wlc_hw, u16 chanspec) {
3441 bool mute) {
3442 u32 macintmask; 3373 u32 macintmask;
3443 bool fastclk; 3374 bool fastclk;
3444 struct brcms_c_info *wlc = wlc_hw->wlc; 3375 struct brcms_c_info *wlc = wlc_hw->wlc;
@@ -3463,10 +3394,6 @@ static brcms_b_init(struct brcms_hardware *wlc_hw, u16 chanspec,
3463 /* core-specific initialization */ 3394 /* core-specific initialization */
3464 brcms_b_coreinit(wlc); 3395 brcms_b_coreinit(wlc);
3465 3396
3466 /* suspend the tx fifos and mute the phy for preism cac time */
3467 if (mute)
3468 brcms_b_mute(wlc_hw, ON, PHY_MUTE_FOR_PREISM);
3469
3470 /* band-specific inits */ 3397 /* band-specific inits */
3471 brcms_b_bsinit(wlc, chanspec); 3398 brcms_b_bsinit(wlc, chanspec);
3472 3399
@@ -3656,42 +3583,30 @@ static void brcms_c_bandinit_ordered(struct brcms_c_info *wlc,
3656 brcms_c_set_phy_chanspec(wlc, chanspec); 3583 brcms_c_set_phy_chanspec(wlc, chanspec);
3657} 3584}
3658 3585
3659static void brcms_c_mac_bcn_promisc(struct brcms_c_info *wlc) 3586/*
3660{ 3587 * Set or clear maccontrol bits MCTL_PROMISC, MCTL_BCNS_PROMISC and
3661 if (wlc->bcnmisc_monitor) 3588 * MCTL_KEEPCONTROL
3662 brcms_b_mctrl(wlc->hw, MCTL_BCNS_PROMISC, MCTL_BCNS_PROMISC); 3589 */
3663 else
3664 brcms_b_mctrl(wlc->hw, MCTL_BCNS_PROMISC, 0);
3665}
3666
3667void brcms_c_mac_bcn_promisc_change(struct brcms_c_info *wlc, bool promisc)
3668{
3669 wlc->bcnmisc_monitor = promisc;
3670 brcms_c_mac_bcn_promisc(wlc);
3671}
3672
3673/* set or clear maccontrol bits MCTL_PROMISC and MCTL_KEEPCONTROL */
3674static void brcms_c_mac_promisc(struct brcms_c_info *wlc) 3590static void brcms_c_mac_promisc(struct brcms_c_info *wlc)
3675{ 3591{
3676 u32 promisc_bits = 0; 3592 u32 promisc_bits = 0;
3677 3593
3678 /* 3594 if (wlc->bcnmisc_monitor)
3679 * promiscuous mode just sets MCTL_PROMISC 3595 promisc_bits |= MCTL_BCNS_PROMISC;
3680 * Note: APs get all BSS traffic without the need to set
3681 * the MCTL_PROMISC bit since all BSS data traffic is
3682 * directed at the AP
3683 */
3684 if (wlc->pub->promisc)
3685 promisc_bits |= MCTL_PROMISC;
3686 3596
3687 /* monitor mode needs both MCTL_PROMISC and MCTL_KEEPCONTROL
3688 * Note: monitor mode also needs MCTL_BCNS_PROMISC, but that is
3689 * handled in brcms_c_mac_bcn_promisc()
3690 */
3691 if (wlc->monitor) 3597 if (wlc->monitor)
3692 promisc_bits |= MCTL_PROMISC | MCTL_KEEPCONTROL; 3598 promisc_bits |=
3599 MCTL_PROMISC | MCTL_BCNS_PROMISC | MCTL_KEEPCONTROL;
3693 3600
3694 brcms_b_mctrl(wlc->hw, MCTL_PROMISC | MCTL_KEEPCONTROL, promisc_bits); 3601 brcms_b_mctrl(wlc->hw,
3602 MCTL_PROMISC | MCTL_BCNS_PROMISC | MCTL_KEEPCONTROL,
3603 promisc_bits);
3604}
3605
3606void brcms_c_mac_bcn_promisc_change(struct brcms_c_info *wlc, bool promisc)
3607{
3608 wlc->bcnmisc_monitor = promisc;
3609 brcms_c_mac_promisc(wlc);
3695} 3610}
3696 3611
3697/* 3612/*
@@ -3723,7 +3638,6 @@ static void brcms_c_ucode_mac_upd(struct brcms_c_info *wlc)
3723 } 3638 }
3724 3639
3725 /* update the various promisc bits */ 3640 /* update the various promisc bits */
3726 brcms_c_mac_bcn_promisc(wlc);
3727 brcms_c_mac_promisc(wlc); 3641 brcms_c_mac_promisc(wlc);
3728} 3642}
3729 3643
@@ -3979,7 +3893,7 @@ static void brcms_c_set_home_chanspec(struct brcms_c_info *wlc, u16 chanspec)
3979 3893
3980void 3894void
3981brcms_b_set_chanspec(struct brcms_hardware *wlc_hw, u16 chanspec, 3895brcms_b_set_chanspec(struct brcms_hardware *wlc_hw, u16 chanspec,
3982 bool mute, struct txpwr_limits *txpwr) 3896 bool mute_tx, struct txpwr_limits *txpwr)
3983{ 3897{
3984 uint bandunit; 3898 uint bandunit;
3985 3899
@@ -4005,7 +3919,7 @@ brcms_b_set_chanspec(struct brcms_hardware *wlc_hw, u16 chanspec,
4005 } 3919 }
4006 } 3920 }
4007 3921
4008 wlc_phy_initcal_enable(wlc_hw->band->pi, !mute); 3922 wlc_phy_initcal_enable(wlc_hw->band->pi, !mute_tx);
4009 3923
4010 if (!wlc_hw->up) { 3924 if (!wlc_hw->up) {
4011 if (wlc_hw->clk) 3925 if (wlc_hw->clk)
@@ -4017,7 +3931,7 @@ brcms_b_set_chanspec(struct brcms_hardware *wlc_hw, u16 chanspec,
4017 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec); 3931 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
4018 3932
4019 /* Update muting of the channel */ 3933 /* Update muting of the channel */
4020 brcms_b_mute(wlc_hw, mute, 0); 3934 brcms_b_mute(wlc_hw, mute_tx);
4021 } 3935 }
4022} 3936}
4023 3937
@@ -4205,7 +4119,7 @@ void brcms_c_wme_setparams(struct brcms_c_info *wlc, u16 aci,
4205 EDCF_TXOP2USEC(acp_shm.txop); 4119 EDCF_TXOP2USEC(acp_shm.txop);
4206 acp_shm.aifs = (params->aifs & EDCF_AIFSN_MASK); 4120 acp_shm.aifs = (params->aifs & EDCF_AIFSN_MASK);
4207 4121
4208 if (aci == AC_VI && acp_shm.txop == 0 4122 if (aci == IEEE80211_AC_VI && acp_shm.txop == 0
4209 && acp_shm.aifs < EDCF_AIFSN_MAX) 4123 && acp_shm.aifs < EDCF_AIFSN_MAX)
4210 acp_shm.aifs++; 4124 acp_shm.aifs++;
4211 4125
@@ -4242,7 +4156,7 @@ void brcms_c_wme_setparams(struct brcms_c_info *wlc, u16 aci,
4242 } 4156 }
4243} 4157}
4244 4158
4245void brcms_c_edcf_setparams(struct brcms_c_info *wlc, bool suspend) 4159static void brcms_c_edcf_setparams(struct brcms_c_info *wlc, bool suspend)
4246{ 4160{
4247 u16 aci; 4161 u16 aci;
4248 int i_ac; 4162 int i_ac;
@@ -4255,7 +4169,7 @@ void brcms_c_edcf_setparams(struct brcms_c_info *wlc, bool suspend)
4255 }; /* ucode needs these parameters during its initialization */ 4169 }; /* ucode needs these parameters during its initialization */
4256 const struct edcf_acparam *edcf_acp = &default_edcf_acparams[0]; 4170 const struct edcf_acparam *edcf_acp = &default_edcf_acparams[0];
4257 4171
4258 for (i_ac = 0; i_ac < AC_COUNT; i_ac++, edcf_acp++) { 4172 for (i_ac = 0; i_ac < IEEE80211_NUM_ACS; i_ac++, edcf_acp++) {
4259 /* find out which ac this set of params applies to */ 4173 /* find out which ac this set of params applies to */
4260 aci = (edcf_acp->ACI & EDCF_ACI_MASK) >> EDCF_ACI_SHIFT; 4174 aci = (edcf_acp->ACI & EDCF_ACI_MASK) >> EDCF_ACI_SHIFT;
4261 4175
@@ -4277,17 +4191,6 @@ void brcms_c_edcf_setparams(struct brcms_c_info *wlc, bool suspend)
4277 } 4191 }
4278} 4192}
4279 4193
4280/* maintain LED behavior in down state */
4281static void brcms_c_down_led_upd(struct brcms_c_info *wlc)
4282{
4283 /*
4284 * maintain LEDs while in down state, turn on sbclk if
4285 * not available yet. Turn on sbclk if necessary
4286 */
4287 brcms_b_pllreq(wlc->hw, true, BRCMS_PLLREQ_FLIP);
4288 brcms_b_pllreq(wlc->hw, false, BRCMS_PLLREQ_FLIP);
4289}
4290
4291static void brcms_c_radio_monitor_start(struct brcms_c_info *wlc) 4194static void brcms_c_radio_monitor_start(struct brcms_c_info *wlc)
4292{ 4195{
4293 /* Don't start the timer if HWRADIO feature is disabled */ 4196 /* Don't start the timer if HWRADIO feature is disabled */
@@ -4299,28 +4202,6 @@ static void brcms_c_radio_monitor_start(struct brcms_c_info *wlc)
4299 brcms_add_timer(wlc->radio_timer, TIMER_INTERVAL_RADIOCHK, true); 4202 brcms_add_timer(wlc->radio_timer, TIMER_INTERVAL_RADIOCHK, true);
4300} 4203}
4301 4204
4302static void brcms_c_radio_disable(struct brcms_c_info *wlc)
4303{
4304 if (!wlc->pub->up) {
4305 brcms_c_down_led_upd(wlc);
4306 return;
4307 }
4308
4309 brcms_c_radio_monitor_start(wlc);
4310 brcms_down(wlc->wl);
4311}
4312
4313static void brcms_c_radio_enable(struct brcms_c_info *wlc)
4314{
4315 if (wlc->pub->up)
4316 return;
4317
4318 if (brcms_deviceremoved(wlc))
4319 return;
4320
4321 brcms_up(wlc->wl);
4322}
4323
4324static bool brcms_c_radio_monitor_stop(struct brcms_c_info *wlc) 4205static bool brcms_c_radio_monitor_stop(struct brcms_c_info *wlc)
4325{ 4206{
4326 if (!wlc->radio_monitor) 4207 if (!wlc->radio_monitor)
@@ -4343,18 +4224,6 @@ static void brcms_c_radio_hwdisable_upd(struct brcms_c_info *wlc)
4343 mboolclr(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE); 4224 mboolclr(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
4344} 4225}
4345 4226
4346/*
4347 * centralized radio disable/enable function,
4348 * invoke radio enable/disable after updating hwradio status
4349 */
4350static void brcms_c_radio_upd(struct brcms_c_info *wlc)
4351{
4352 if (wlc->pub->radio_disabled)
4353 brcms_c_radio_disable(wlc);
4354 else
4355 brcms_c_radio_enable(wlc);
4356}
4357
4358/* update hwradio status and return it */ 4227/* update hwradio status and return it */
4359bool brcms_c_check_radio_disabled(struct brcms_c_info *wlc) 4228bool brcms_c_check_radio_disabled(struct brcms_c_info *wlc)
4360{ 4229{
@@ -4376,12 +4245,7 @@ static void brcms_c_radio_timer(void *arg)
4376 return; 4245 return;
4377 } 4246 }
4378 4247
4379 /* cap mpc off count */
4380 if (wlc->mpc_offcnt < BRCMS_MPC_MAX_DELAYCNT)
4381 wlc->mpc_offcnt++;
4382
4383 brcms_c_radio_hwdisable_upd(wlc); 4248 brcms_c_radio_hwdisable_upd(wlc);
4384 brcms_c_radio_upd(wlc);
4385} 4249}
4386 4250
4387/* common low-level watchdog code */ 4251/* common low-level watchdog code */
@@ -4407,60 +4271,6 @@ static void brcms_b_watchdog(void *arg)
4407 wlc_phy_watchdog(wlc_hw->band->pi); 4271 wlc_phy_watchdog(wlc_hw->band->pi);
4408} 4272}
4409 4273
4410static void brcms_c_radio_mpc_upd(struct brcms_c_info *wlc)
4411{
4412 bool mpc_radio, radio_state;
4413
4414 /*
4415 * Clear the WL_RADIO_MPC_DISABLE bit when mpc feature is disabled
4416 * in case the WL_RADIO_MPC_DISABLE bit was set. Stop the radio
4417 * monitor also when WL_RADIO_MPC_DISABLE is the only reason that
4418 * the radio is going down.
4419 */
4420 if (!wlc->mpc) {
4421 if (!wlc->pub->radio_disabled)
4422 return;
4423 mboolclr(wlc->pub->radio_disabled, WL_RADIO_MPC_DISABLE);
4424 brcms_c_radio_upd(wlc);
4425 if (!wlc->pub->radio_disabled)
4426 brcms_c_radio_monitor_stop(wlc);
4427 return;
4428 }
4429
4430 /*
4431 * sync ismpc logic with WL_RADIO_MPC_DISABLE bit in
4432 * wlc->pub->radio_disabled to go ON, always call radio_upd
4433 * synchronously to go OFF, postpone radio_upd to later when
4434 * context is safe(e.g. watchdog)
4435 */
4436 radio_state =
4437 (mboolisset(wlc->pub->radio_disabled, WL_RADIO_MPC_DISABLE) ? OFF :
4438 ON);
4439 mpc_radio = (brcms_c_ismpc(wlc) == true) ? OFF : ON;
4440
4441 if (radio_state == ON && mpc_radio == OFF)
4442 wlc->mpc_delay_off = wlc->mpc_dlycnt;
4443 else if (radio_state == OFF && mpc_radio == ON) {
4444 mboolclr(wlc->pub->radio_disabled, WL_RADIO_MPC_DISABLE);
4445 brcms_c_radio_upd(wlc);
4446 if (wlc->mpc_offcnt < BRCMS_MPC_THRESHOLD)
4447 wlc->mpc_dlycnt = BRCMS_MPC_MAX_DELAYCNT;
4448 else
4449 wlc->mpc_dlycnt = BRCMS_MPC_MIN_DELAYCNT;
4450 }
4451 /*
4452 * Below logic is meant to capture the transition from mpc off
4453 * to mpc on for reasons other than wlc->mpc_delay_off keeping
4454 * the mpc off. In that case reset wlc->mpc_delay_off to
4455 * wlc->mpc_dlycnt, so that we restart the countdown of mpc_delay_off
4456 */
4457 if ((wlc->prev_non_delay_mpc == false) &&
4458 (brcms_c_is_non_delay_mpc(wlc) == true) && wlc->mpc_delay_off)
4459 wlc->mpc_delay_off = wlc->mpc_dlycnt;
4460
4461 wlc->prev_non_delay_mpc = brcms_c_is_non_delay_mpc(wlc);
4462}
4463
4464/* common watchdog code */ 4274/* common watchdog code */
4465static void brcms_c_watchdog(void *arg) 4275static void brcms_c_watchdog(void *arg)
4466{ 4276{
@@ -4481,21 +4291,7 @@ static void brcms_c_watchdog(void *arg)
4481 /* increment second count */ 4291 /* increment second count */
4482 wlc->pub->now++; 4292 wlc->pub->now++;
4483 4293
4484 /* delay radio disable */
4485 if (wlc->mpc_delay_off) {
4486 if (--wlc->mpc_delay_off == 0) {
4487 mboolset(wlc->pub->radio_disabled,
4488 WL_RADIO_MPC_DISABLE);
4489 if (wlc->mpc && brcms_c_ismpc(wlc))
4490 wlc->mpc_offcnt = 0;
4491 }
4492 }
4493
4494 /* mpc sync */
4495 brcms_c_radio_mpc_upd(wlc);
4496 /* radio sync: sw/hw/mpc --> radio_disable/radio_enable */
4497 brcms_c_radio_hwdisable_upd(wlc); 4294 brcms_c_radio_hwdisable_upd(wlc);
4498 brcms_c_radio_upd(wlc);
4499 /* if radio is disable, driver may be down, quit here */ 4295 /* if radio is disable, driver may be down, quit here */
4500 if (wlc->pub->radio_disabled) 4296 if (wlc->pub->radio_disabled)
4501 return; 4297 return;
@@ -4599,9 +4395,6 @@ static void brcms_c_info_init(struct brcms_c_info *wlc, int unit)
4599 /* WME QoS mode is Auto by default */ 4395 /* WME QoS mode is Auto by default */
4600 wlc->pub->_ampdu = AMPDU_AGG_HOST; 4396 wlc->pub->_ampdu = AMPDU_AGG_HOST;
4601 wlc->pub->bcmerror = 0; 4397 wlc->pub->bcmerror = 0;
4602
4603 /* initialize mpc delay */
4604 wlc->mpc_delay_off = wlc->mpc_dlycnt = BRCMS_MPC_MIN_DELAYCNT;
4605} 4398}
4606 4399
4607static uint brcms_c_attach_module(struct brcms_c_info *wlc) 4400static uint brcms_c_attach_module(struct brcms_c_info *wlc)
@@ -5259,9 +5052,6 @@ static void brcms_c_ap_upd(struct brcms_c_info *wlc)
5259{ 5052{
5260 /* STA-BSS; short capable */ 5053 /* STA-BSS; short capable */
5261 wlc->PLCPHdr_override = BRCMS_PLCP_SHORT; 5054 wlc->PLCPHdr_override = BRCMS_PLCP_SHORT;
5262
5263 /* fixup mpc */
5264 wlc->mpc = true;
5265} 5055}
5266 5056
5267/* Initialize just the hardware when coming out of POR or S3/S5 system states */ 5057/* Initialize just the hardware when coming out of POR or S3/S5 system states */
@@ -5376,7 +5166,7 @@ static void brcms_c_wme_retries_write(struct brcms_c_info *wlc)
5376 if (!wlc->clk) 5166 if (!wlc->clk)
5377 return; 5167 return;
5378 5168
5379 for (ac = 0; ac < AC_COUNT; ac++) 5169 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
5380 brcms_b_write_shm(wlc->hw, M_AC_TXLMT_ADDR(ac), 5170 brcms_b_write_shm(wlc->hw, M_AC_TXLMT_ADDR(ac),
5381 wlc->wme_retries[ac]); 5171 wlc->wme_retries[ac]);
5382} 5172}
@@ -5575,7 +5365,6 @@ uint brcms_c_down(struct brcms_c_info *wlc)
5575 if (!wlc->pub->up) 5365 if (!wlc->pub->up)
5576 return callbacks; 5366 return callbacks;
5577 5367
5578 /* in between, mpc could try to bring down again.. */
5579 wlc->going_down = true; 5368 wlc->going_down = true;
5580 5369
5581 callbacks += brcms_b_bmac_down_prep(wlc->hw); 5370 callbacks += brcms_b_bmac_down_prep(wlc->hw);
@@ -5852,7 +5641,7 @@ int brcms_c_set_rate_limit(struct brcms_c_info *wlc, u16 srl, u16 lrl)
5852 5641
5853 brcms_b_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL); 5642 brcms_b_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL);
5854 5643
5855 for (ac = 0; ac < AC_COUNT; ac++) { 5644 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) {
5856 wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac], 5645 wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac],
5857 EDCF_SHORT, wlc->SRL); 5646 EDCF_SHORT, wlc->SRL);
5858 wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac], 5647 wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac],
@@ -6103,7 +5892,6 @@ void brcms_c_print_txdesc(struct d11txh *txh)
6103 5892
6104 u8 *rtsph = txh->RTSPhyHeader; 5893 u8 *rtsph = txh->RTSPhyHeader;
6105 struct ieee80211_rts rts = txh->rts_frame; 5894 struct ieee80211_rts rts = txh->rts_frame;
6106 char hexbuf[256];
6107 5895
6108 /* add plcp header along with txh descriptor */ 5896 /* add plcp header along with txh descriptor */
6109 printk(KERN_DEBUG "Raw TxDesc + plcp header:\n"); 5897 printk(KERN_DEBUG "Raw TxDesc + plcp header:\n");
@@ -6124,17 +5912,16 @@ void brcms_c_print_txdesc(struct d11txh *txh)
6124 printk(KERN_DEBUG "XtraFrameTypes: %04x ", xtraft); 5912 printk(KERN_DEBUG "XtraFrameTypes: %04x ", xtraft);
6125 printk(KERN_DEBUG "\n"); 5913 printk(KERN_DEBUG "\n");
6126 5914
6127 brcmu_format_hex(hexbuf, iv, sizeof(txh->IV)); 5915 print_hex_dump_bytes("SecIV:", DUMP_PREFIX_OFFSET, iv, sizeof(txh->IV));
6128 printk(KERN_DEBUG "SecIV: %s\n", hexbuf); 5916 print_hex_dump_bytes("RA:", DUMP_PREFIX_OFFSET,
6129 brcmu_format_hex(hexbuf, ra, sizeof(txh->TxFrameRA)); 5917 ra, sizeof(txh->TxFrameRA));
6130 printk(KERN_DEBUG "RA: %s\n", hexbuf);
6131 5918
6132 printk(KERN_DEBUG "Fb FES Time: %04x ", tfestfb); 5919 printk(KERN_DEBUG "Fb FES Time: %04x ", tfestfb);
6133 brcmu_format_hex(hexbuf, rtspfb, sizeof(txh->RTSPLCPFallback)); 5920 print_hex_dump_bytes("Fb RTS PLCP:", DUMP_PREFIX_OFFSET,
6134 printk(KERN_DEBUG "RTS PLCP: %s ", hexbuf); 5921 rtspfb, sizeof(txh->RTSPLCPFallback));
6135 printk(KERN_DEBUG "RTS DUR: %04x ", rtsdfb); 5922 printk(KERN_DEBUG "RTS DUR: %04x ", rtsdfb);
6136 brcmu_format_hex(hexbuf, fragpfb, sizeof(txh->FragPLCPFallback)); 5923 print_hex_dump_bytes("PLCP:", DUMP_PREFIX_OFFSET,
6137 printk(KERN_DEBUG "PLCP: %s ", hexbuf); 5924 fragpfb, sizeof(txh->FragPLCPFallback));
6138 printk(KERN_DEBUG "DUR: %04x", fragdfb); 5925 printk(KERN_DEBUG "DUR: %04x", fragdfb);
6139 printk(KERN_DEBUG "\n"); 5926 printk(KERN_DEBUG "\n");
6140 5927
@@ -6149,18 +5936,18 @@ void brcms_c_print_txdesc(struct d11txh *txh)
6149 printk(KERN_DEBUG "MaxAggbyte_fb: %04x\n", mabyte_f); 5936 printk(KERN_DEBUG "MaxAggbyte_fb: %04x\n", mabyte_f);
6150 printk(KERN_DEBUG "MinByte: %04x\n", mmbyte); 5937 printk(KERN_DEBUG "MinByte: %04x\n", mmbyte);
6151 5938
6152 brcmu_format_hex(hexbuf, rtsph, sizeof(txh->RTSPhyHeader)); 5939 print_hex_dump_bytes("RTS PLCP:", DUMP_PREFIX_OFFSET,
6153 printk(KERN_DEBUG "RTS PLCP: %s ", hexbuf); 5940 rtsph, sizeof(txh->RTSPhyHeader));
6154 brcmu_format_hex(hexbuf, (u8 *) &rts, sizeof(txh->rts_frame)); 5941 print_hex_dump_bytes("RTS Frame:", DUMP_PREFIX_OFFSET,
6155 printk(KERN_DEBUG "RTS Frame: %s", hexbuf); 5942 (u8 *)&rts, sizeof(txh->rts_frame));
6156 printk(KERN_DEBUG "\n"); 5943 printk(KERN_DEBUG "\n");
6157} 5944}
6158#endif /* defined(BCMDBG) */ 5945#endif /* defined(BCMDBG) */
6159 5946
6160#if defined(BCMDBG) 5947#if defined(BCMDBG)
6161int 5948static int
6162brcms_c_format_flags(const struct brcms_c_bit_desc *bd, u32 flags, char *buf, 5949brcms_c_format_flags(const struct brcms_c_bit_desc *bd, u32 flags, char *buf,
6163 int len) 5950 int len)
6164{ 5951{
6165 int i; 5952 int i;
6166 char *p = buf; 5953 char *p = buf;
@@ -6916,7 +6703,7 @@ brcms_c_d11hdrs_mac80211(struct brcms_c_info *wlc, struct ieee80211_hw *hw,
6916 qos = ieee80211_is_data_qos(h->frame_control); 6703 qos = ieee80211_is_data_qos(h->frame_control);
6917 6704
6918 /* compute length of frame in bytes for use in PLCP computations */ 6705 /* compute length of frame in bytes for use in PLCP computations */
6919 len = brcmu_pkttotlen(p); 6706 len = p->len;
6920 phylen = len + FCS_LEN; 6707 phylen = len + FCS_LEN;
6921 6708
6922 /* Get tx_info */ 6709 /* Get tx_info */
@@ -8253,12 +8040,6 @@ int brcms_c_get_tx_power(struct brcms_c_info *wlc)
8253 return (int)(qdbm / BRCMS_TXPWR_DB_FACTOR); 8040 return (int)(qdbm / BRCMS_TXPWR_DB_FACTOR);
8254} 8041}
8255 8042
8256void brcms_c_set_radio_mpc(struct brcms_c_info *wlc, bool mpc)
8257{
8258 wlc->mpc = mpc;
8259 brcms_c_radio_mpc_upd(wlc);
8260}
8261
8262/* Process received frames */ 8043/* Process received frames */
8263/* 8044/*
8264 * Return true if more frames need to be processed. false otherwise. 8045 * Return true if more frames need to be processed. false otherwise.
@@ -8328,21 +8109,17 @@ static bool
8328brcms_b_recv(struct brcms_hardware *wlc_hw, uint fifo, bool bound) 8109brcms_b_recv(struct brcms_hardware *wlc_hw, uint fifo, bool bound)
8329{ 8110{
8330 struct sk_buff *p; 8111 struct sk_buff *p;
8331 struct sk_buff *head = NULL; 8112 struct sk_buff *next = NULL;
8332 struct sk_buff *tail = NULL; 8113 struct sk_buff_head recv_frames;
8114
8333 uint n = 0; 8115 uint n = 0;
8334 uint bound_limit = bound ? RXBND : -1; 8116 uint bound_limit = bound ? RXBND : -1;
8335 8117
8336 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 8118 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
8337 /* gather received frames */ 8119 skb_queue_head_init(&recv_frames);
8338 while ((p = dma_rx(wlc_hw->di[fifo]))) {
8339 8120
8340 if (!tail) 8121 /* gather received frames */
8341 head = tail = p; 8122 while (dma_rx(wlc_hw->di[fifo], &recv_frames)) {
8342 else {
8343 tail->prev = p;
8344 tail = p;
8345 }
8346 8123
8347 /* !give others some time to run! */ 8124 /* !give others some time to run! */
8348 if (++n >= bound_limit) 8125 if (++n >= bound_limit)
@@ -8353,12 +8130,11 @@ brcms_b_recv(struct brcms_hardware *wlc_hw, uint fifo, bool bound)
8353 dma_rxfill(wlc_hw->di[fifo]); 8130 dma_rxfill(wlc_hw->di[fifo]);
8354 8131
8355 /* process each frame */ 8132 /* process each frame */
8356 while ((p = head) != NULL) { 8133 skb_queue_walk_safe(&recv_frames, p, next) {
8357 struct d11rxhdr_le *rxh_le; 8134 struct d11rxhdr_le *rxh_le;
8358 struct d11rxhdr *rxh; 8135 struct d11rxhdr *rxh;
8359 head = head->prev;
8360 p->prev = NULL;
8361 8136
8137 skb_unlink(p, &recv_frames);
8362 rxh_le = (struct d11rxhdr_le *)p->data; 8138 rxh_le = (struct d11rxhdr_le *)p->data;
8363 rxh = (struct d11rxhdr *)p->data; 8139 rxh = (struct d11rxhdr *)p->data;
8364 8140
@@ -8448,8 +8224,7 @@ bool brcms_c_dpc(struct brcms_c_info *wlc, bool bounded)
8448 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n", 8224 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
8449 __func__, wlc_hw->sih->chip, 8225 __func__, wlc_hw->sih->chip,
8450 wlc_hw->sih->chiprev); 8226 wlc_hw->sih->chiprev);
8451 /* big hammer */ 8227 brcms_fatal_error(wlc_hw->wlc->wl);
8452 brcms_init(wlc->wl);
8453 } 8228 }
8454 8229
8455 /* gptimer timeout */ 8230 /* gptimer timeout */
@@ -8470,15 +8245,14 @@ bool brcms_c_dpc(struct brcms_c_info *wlc, bool bounded)
8470 return wlc->macintstatus != 0; 8245 return wlc->macintstatus != 0;
8471 8246
8472 fatal: 8247 fatal:
8473 brcms_init(wlc->wl); 8248 brcms_fatal_error(wlc_hw->wlc->wl);
8474 return wlc->macintstatus != 0; 8249 return wlc->macintstatus != 0;
8475} 8250}
8476 8251
8477void brcms_c_init(struct brcms_c_info *wlc) 8252void brcms_c_init(struct brcms_c_info *wlc, bool mute_tx)
8478{ 8253{
8479 struct d11regs __iomem *regs; 8254 struct d11regs __iomem *regs;
8480 u16 chanspec; 8255 u16 chanspec;
8481 bool mute = false;
8482 8256
8483 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit); 8257 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
8484 8258
@@ -8494,7 +8268,7 @@ void brcms_c_init(struct brcms_c_info *wlc)
8494 else 8268 else
8495 chanspec = brcms_c_init_chanspec(wlc); 8269 chanspec = brcms_c_init_chanspec(wlc);
8496 8270
8497 brcms_b_init(wlc->hw, chanspec, mute); 8271 brcms_b_init(wlc->hw, chanspec);
8498 8272
8499 /* update beacon listen interval */ 8273 /* update beacon listen interval */
8500 brcms_c_bcn_li_upd(wlc); 8274 brcms_c_bcn_li_upd(wlc);
@@ -8560,15 +8334,16 @@ void brcms_c_init(struct brcms_c_info *wlc)
8560 /* ..now really unleash hell (allow the MAC out of suspend) */ 8334 /* ..now really unleash hell (allow the MAC out of suspend) */
8561 brcms_c_enable_mac(wlc); 8335 brcms_c_enable_mac(wlc);
8562 8336
8337 /* suspend the tx fifos and mute the phy for preism cac time */
8338 if (mute_tx)
8339 brcms_b_mute(wlc->hw, true);
8340
8563 /* clear tx flow control */ 8341 /* clear tx flow control */
8564 brcms_c_txflowcontrol_reset(wlc); 8342 brcms_c_txflowcontrol_reset(wlc);
8565 8343
8566 /* enable the RF Disable Delay timer */ 8344 /* enable the RF Disable Delay timer */
8567 W_REG(&wlc->regs->rfdisabledly, RFDISABLE_DEFAULT); 8345 W_REG(&wlc->regs->rfdisabledly, RFDISABLE_DEFAULT);
8568 8346
8569 /* initialize mpc delay */
8570 wlc->mpc_delay_off = wlc->mpc_dlycnt = BRCMS_MPC_MIN_DELAYCNT;
8571
8572 /* 8347 /*
8573 * Initialize WME parameters; if they haven't been set by some other 8348 * Initialize WME parameters; if they haven't been set by some other
8574 * mechanism (IOVar, etc) then read them from the hardware. 8349 * mechanism (IOVar, etc) then read them from the hardware.
@@ -8577,7 +8352,7 @@ void brcms_c_init(struct brcms_c_info *wlc)
8577 /* Uninitialized; read from HW */ 8352 /* Uninitialized; read from HW */
8578 int ac; 8353 int ac;
8579 8354
8580 for (ac = 0; ac < AC_COUNT; ac++) 8355 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
8581 wlc->wme_retries[ac] = 8356 wlc->wme_retries[ac] =
8582 brcms_b_read_shm(wlc->hw, M_AC_TXLMT_ADDR(ac)); 8357 brcms_b_read_shm(wlc->hw, M_AC_TXLMT_ADDR(ac));
8583 } 8358 }
@@ -8754,8 +8529,6 @@ brcms_c_attach(struct brcms_info *wl, u16 vendor, u16 device, uint unit,
8754 brcms_c_ht_update_sgi_rx(wlc, 0); 8529 brcms_c_ht_update_sgi_rx(wlc, 0);
8755 } 8530 }
8756 8531
8757 /* initialize radio_mpc_disable according to wlc->mpc */
8758 brcms_c_radio_mpc_upd(wlc);
8759 brcms_b_antsel_set(wlc->hw, wlc->asi->antsel_avail); 8532 brcms_b_antsel_set(wlc->hw, wlc->asi->antsel_avail);
8760 8533
8761 if (perr) 8534 if (perr)
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/main.h b/drivers/net/wireless/brcm80211/brcmsmac/main.h
index c0e0fcfdfaf8..251c350b3164 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/main.h
+++ b/drivers/net/wireless/brcm80211/brcmsmac/main.h
@@ -44,8 +44,6 @@
44/* transmit buffer max headroom for protocol headers */ 44/* transmit buffer max headroom for protocol headers */
45#define TXOFF (D11_TXH_LEN + D11_PHY_HDR_LEN) 45#define TXOFF (D11_TXH_LEN + D11_PHY_HDR_LEN)
46 46
47#define AC_COUNT 4
48
49/* Macros for doing definition and get/set of bitfields 47/* Macros for doing definition and get/set of bitfields
50 * Usage example, e.g. a three-bit field (bits 4-6): 48 * Usage example, e.g. a three-bit field (bits 4-6):
51 * #define <NAME>_M BITFIELD_MASK(3) 49 * #define <NAME>_M BITFIELD_MASK(3)
@@ -427,11 +425,6 @@ struct brcms_txq_info {
427 * bandinit_pending: track band init in auto band. 425 * bandinit_pending: track band init in auto band.
428 * radio_monitor: radio timer is running. 426 * radio_monitor: radio timer is running.
429 * going_down: down path intermediate variable. 427 * going_down: down path intermediate variable.
430 * mpc: enable minimum power consumption.
431 * mpc_dlycnt: # of watchdog cnt before turn disable radio.
432 * mpc_offcnt: # of watchdog cnt that radio is disabled.
433 * mpc_delay_off: delay radio disable by # of watchdog cnt.
434 * prev_non_delay_mpc: prev state brcms_c_is_non_delay_mpc.
435 * wdtimer: timer for watchdog routine. 428 * wdtimer: timer for watchdog routine.
436 * radio_timer: timer for hw radio button monitor routine. 429 * radio_timer: timer for hw radio button monitor routine.
437 * monitor: monitor (MPDU sniffing) mode. 430 * monitor: monitor (MPDU sniffing) mode.
@@ -441,7 +434,7 @@ struct brcms_txq_info {
441 * bcn_li_dtim: beacon listen interval in # dtims. 434 * bcn_li_dtim: beacon listen interval in # dtims.
442 * WDarmed: watchdog timer is armed. 435 * WDarmed: watchdog timer is armed.
443 * WDlast: last time wlc_watchdog() was called. 436 * WDlast: last time wlc_watchdog() was called.
444 * edcf_txop[AC_COUNT]: current txop for each ac. 437 * edcf_txop[IEEE80211_NUM_ACS]: current txop for each ac.
445 * wme_retries: per-AC retry limits. 438 * wme_retries: per-AC retry limits.
446 * tx_prec_map: Precedence map based on HW FIFO space. 439 * tx_prec_map: Precedence map based on HW FIFO space.
447 * fifo2prec_map[NFIFO]: pointer to fifo2_prec map based on WME. 440 * fifo2prec_map[NFIFO]: pointer to fifo2_prec map based on WME.
@@ -522,12 +515,6 @@ struct brcms_c_info {
522 bool radio_monitor; 515 bool radio_monitor;
523 bool going_down; 516 bool going_down;
524 517
525 bool mpc;
526 u8 mpc_dlycnt;
527 u8 mpc_offcnt;
528 u8 mpc_delay_off;
529 u8 prev_non_delay_mpc;
530
531 struct brcms_timer *wdtimer; 518 struct brcms_timer *wdtimer;
532 struct brcms_timer *radio_timer; 519 struct brcms_timer *radio_timer;
533 520
@@ -546,9 +533,9 @@ struct brcms_c_info {
546 u32 WDlast; 533 u32 WDlast;
547 534
548 /* WME */ 535 /* WME */
549 u16 edcf_txop[AC_COUNT]; 536 u16 edcf_txop[IEEE80211_NUM_ACS];
550 537
551 u16 wme_retries[AC_COUNT]; 538 u16 wme_retries[IEEE80211_NUM_ACS];
552 u16 tx_prec_map; 539 u16 tx_prec_map;
553 u16 fifo2prec_map[NFIFO]; 540 u16 fifo2prec_map[NFIFO];
554 541
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_cmn.c b/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_cmn.c
index a3149254cbcd..e17edf7e6833 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_cmn.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_cmn.c
@@ -112,7 +112,7 @@ static const struct chan_info_basic chan_info_all[] = {
112 {216, 50800} 112 {216, 50800}
113}; 113};
114 114
115const u8 ofdm_rate_lookup[] = { 115static const u8 ofdm_rate_lookup[] = {
116 116
117 BRCM_RATE_48M, 117 BRCM_RATE_48M,
118 BRCM_RATE_24M, 118 BRCM_RATE_24M,
@@ -190,15 +190,7 @@ u16 read_radio_reg(struct brcms_phy *pi, u16 addr)
190 data = R_REG(&pi->regs->radioregdata); 190 data = R_REG(&pi->regs->radioregdata);
191 } else { 191 } else {
192 W_REG_FLUSH(&pi->regs->phy4waddr, addr); 192 W_REG_FLUSH(&pi->regs->phy4waddr, addr);
193
194#ifdef __ARM_ARCH_4T__
195 __asm__(" .align 4 ");
196 __asm__(" nop ");
197 data = R_REG(&pi->regs->phy4wdatalo);
198#else
199 data = R_REG(&pi->regs->phy4wdatalo); 193 data = R_REG(&pi->regs->phy4wdatalo);
200#endif
201
202 } 194 }
203 pi->phy_wreg = 0; 195 pi->phy_wreg = 0;
204 196
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_int.h b/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_int.h
index bea85241a244..5f9478b1c993 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_int.h
+++ b/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_int.h
@@ -774,11 +774,6 @@ struct brcms_phy {
774 s16 nphy_noise_win[PHY_CORE_MAX][PHY_NOISE_WINDOW_SZ]; 774 s16 nphy_noise_win[PHY_CORE_MAX][PHY_NOISE_WINDOW_SZ];
775 u8 nphy_noise_index; 775 u8 nphy_noise_index;
776 776
777 u8 nphy_txpid2g[PHY_CORE_NUM_2];
778 u8 nphy_txpid5g[PHY_CORE_NUM_2];
779 u8 nphy_txpid5gl[PHY_CORE_NUM_2];
780 u8 nphy_txpid5gh[PHY_CORE_NUM_2];
781
782 bool nphy_gain_boost; 777 bool nphy_gain_boost;
783 bool nphy_elna_gain_config; 778 bool nphy_elna_gain_config;
784 u16 old_bphy_test; 779 u16 old_bphy_test;
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_n.c b/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_n.c
index cd19c2f7a347..ec9b56639d54 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_n.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_n.c
@@ -29,6 +29,7 @@
29#include "phy_radio.h" 29#include "phy_radio.h"
30#include "phyreg_n.h" 30#include "phyreg_n.h"
31#include "phytbl_n.h" 31#include "phytbl_n.h"
32#include "soc.h"
32 33
33#define READ_RADIO_REG2(pi, radio_type, jspace, core, reg_name) \ 34#define READ_RADIO_REG2(pi, radio_type, jspace, core, reg_name) \
34 read_radio_reg(pi, radio_type##_##jspace##_##reg_name | \ 35 read_radio_reg(pi, radio_type##_##jspace##_##reg_name | \
@@ -14417,12 +14418,6 @@ static void wlc_phy_txpwr_srom_read_ppr_nphy(struct brcms_phy *pi)
14417 switch (band_num) { 14418 switch (band_num) {
14418 case 0: 14419 case 0:
14419 14420
14420 pi->nphy_txpid2g[PHY_CORE_0] =
14421 (u8) wlapi_getintvar(shim,
14422 BRCMS_SROM_TXPID2GA0);
14423 pi->nphy_txpid2g[PHY_CORE_1] =
14424 (u8) wlapi_getintvar(shim,
14425 BRCMS_SROM_TXPID2GA1);
14426 pi->nphy_pwrctrl_info[PHY_CORE_0].max_pwr_2g = 14421 pi->nphy_pwrctrl_info[PHY_CORE_0].max_pwr_2g =
14427 (s8) wlapi_getintvar(shim, 14422 (s8) wlapi_getintvar(shim,
14428 BRCMS_SROM_MAXP2GA0); 14423 BRCMS_SROM_MAXP2GA0);
@@ -14486,12 +14481,6 @@ static void wlc_phy_txpwr_srom_read_ppr_nphy(struct brcms_phy *pi)
14486 break; 14481 break;
14487 case 1: 14482 case 1:
14488 14483
14489 pi->nphy_txpid5g[PHY_CORE_0] =
14490 (u8) wlapi_getintvar(shim,
14491 BRCMS_SROM_TXPID5GA0);
14492 pi->nphy_txpid5g[PHY_CORE_1] =
14493 (u8) wlapi_getintvar(shim,
14494 BRCMS_SROM_TXPID5GA1);
14495 pi->nphy_pwrctrl_info[PHY_CORE_0].max_pwr_5gm = 14484 pi->nphy_pwrctrl_info[PHY_CORE_0].max_pwr_5gm =
14496 (s8) wlapi_getintvar(shim, BRCMS_SROM_MAXP5GA0); 14485 (s8) wlapi_getintvar(shim, BRCMS_SROM_MAXP5GA0);
14497 pi->nphy_pwrctrl_info[PHY_CORE_1].max_pwr_5gm = 14486 pi->nphy_pwrctrl_info[PHY_CORE_1].max_pwr_5gm =
@@ -14551,12 +14540,6 @@ static void wlc_phy_txpwr_srom_read_ppr_nphy(struct brcms_phy *pi)
14551 break; 14540 break;
14552 case 2: 14541 case 2:
14553 14542
14554 pi->nphy_txpid5gl[0] =
14555 (u8) wlapi_getintvar(shim,
14556 BRCMS_SROM_TXPID5GLA0);
14557 pi->nphy_txpid5gl[1] =
14558 (u8) wlapi_getintvar(shim,
14559 BRCMS_SROM_TXPID5GLA1);
14560 pi->nphy_pwrctrl_info[0].max_pwr_5gl = 14543 pi->nphy_pwrctrl_info[0].max_pwr_5gl =
14561 (s8) wlapi_getintvar(shim, 14544 (s8) wlapi_getintvar(shim,
14562 BRCMS_SROM_MAXP5GLA0); 14545 BRCMS_SROM_MAXP5GLA0);
@@ -14615,12 +14598,6 @@ static void wlc_phy_txpwr_srom_read_ppr_nphy(struct brcms_phy *pi)
14615 break; 14598 break;
14616 case 3: 14599 case 3:
14617 14600
14618 pi->nphy_txpid5gh[0] =
14619 (u8) wlapi_getintvar(shim,
14620 BRCMS_SROM_TXPID5GHA0);
14621 pi->nphy_txpid5gh[1] =
14622 (u8) wlapi_getintvar(shim,
14623 BRCMS_SROM_TXPID5GHA1);
14624 pi->nphy_pwrctrl_info[0].max_pwr_5gh = 14601 pi->nphy_pwrctrl_info[0].max_pwr_5gh =
14625 (s8) wlapi_getintvar(shim, 14602 (s8) wlapi_getintvar(shim,
14626 BRCMS_SROM_MAXP5GHA0); 14603 BRCMS_SROM_MAXP5GHA0);
@@ -27994,20 +27971,11 @@ void wlc_phy_txpwr_fixpower_nphy(struct brcms_phy *pi)
27994 chan_freq_range = wlc_phy_get_chan_freq_range_nphy(pi, 0); 27971 chan_freq_range = wlc_phy_get_chan_freq_range_nphy(pi, 0);
27995 switch (chan_freq_range) { 27972 switch (chan_freq_range) {
27996 case WL_CHAN_FREQ_RANGE_2G: 27973 case WL_CHAN_FREQ_RANGE_2G:
27997 txpi[0] = pi->nphy_txpid2g[0];
27998 txpi[1] = pi->nphy_txpid2g[1];
27999 break;
28000 case WL_CHAN_FREQ_RANGE_5GL: 27974 case WL_CHAN_FREQ_RANGE_5GL:
28001 txpi[0] = pi->nphy_txpid5gl[0];
28002 txpi[1] = pi->nphy_txpid5gl[1];
28003 break;
28004 case WL_CHAN_FREQ_RANGE_5GM: 27975 case WL_CHAN_FREQ_RANGE_5GM:
28005 txpi[0] = pi->nphy_txpid5g[0];
28006 txpi[1] = pi->nphy_txpid5g[1];
28007 break;
28008 case WL_CHAN_FREQ_RANGE_5GH: 27976 case WL_CHAN_FREQ_RANGE_5GH:
28009 txpi[0] = pi->nphy_txpid5gh[0]; 27977 txpi[0] = 0;
28010 txpi[1] = pi->nphy_txpid5gh[1]; 27978 txpi[1] = 0;
28011 break; 27979 break;
28012 default: 27980 default:
28013 txpi[0] = txpi[1] = 91; 27981 txpi[0] = txpi[1] = 91;
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/pmu.c b/drivers/net/wireless/brcm80211/brcmsmac/pmu.c
index 3b36e3acfd74..12ba575f5785 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/pmu.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/pmu.c
@@ -23,6 +23,7 @@
23#include "pub.h" 23#include "pub.h"
24#include "aiutils.h" 24#include "aiutils.h"
25#include "pmu.h" 25#include "pmu.h"
26#include "soc.h"
26 27
27/* 28/*
28 * external LPO crystal frequency 29 * external LPO crystal frequency
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/pub.h b/drivers/net/wireless/brcm80211/brcmsmac/pub.h
index 37bb2dcc113f..21ccf3a03987 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/pub.h
+++ b/drivers/net/wireless/brcm80211/brcmsmac/pub.h
@@ -170,22 +170,6 @@ enum brcms_srom_id {
170 BRCMS_SROM_TSSIPOS2G, 170 BRCMS_SROM_TSSIPOS2G,
171 BRCMS_SROM_TSSIPOS5G, 171 BRCMS_SROM_TSSIPOS5G,
172 BRCMS_SROM_TXCHAIN, 172 BRCMS_SROM_TXCHAIN,
173 BRCMS_SROM_TXPID2GA0,
174 BRCMS_SROM_TXPID2GA1,
175 BRCMS_SROM_TXPID2GA2,
176 BRCMS_SROM_TXPID2GA3,
177 BRCMS_SROM_TXPID5GA0,
178 BRCMS_SROM_TXPID5GA1,
179 BRCMS_SROM_TXPID5GA2,
180 BRCMS_SROM_TXPID5GA3,
181 BRCMS_SROM_TXPID5GHA0,
182 BRCMS_SROM_TXPID5GHA1,
183 BRCMS_SROM_TXPID5GHA2,
184 BRCMS_SROM_TXPID5GHA3,
185 BRCMS_SROM_TXPID5GLA0,
186 BRCMS_SROM_TXPID5GLA1,
187 BRCMS_SROM_TXPID5GLA2,
188 BRCMS_SROM_TXPID5GLA3,
189 /* 173 /*
190 * per-path identifiers (see srom.c) 174 * per-path identifiers (see srom.c)
191 */ 175 */
@@ -225,10 +209,6 @@ enum brcms_srom_id {
225 BRCMS_SROM_PA2GW2A1, 209 BRCMS_SROM_PA2GW2A1,
226 BRCMS_SROM_PA2GW2A2, 210 BRCMS_SROM_PA2GW2A2,
227 BRCMS_SROM_PA2GW2A3, 211 BRCMS_SROM_PA2GW2A3,
228 BRCMS_SROM_PA2GW3A0,
229 BRCMS_SROM_PA2GW3A1,
230 BRCMS_SROM_PA2GW3A2,
231 BRCMS_SROM_PA2GW3A3,
232 BRCMS_SROM_PA5GHW0A0, 212 BRCMS_SROM_PA5GHW0A0,
233 BRCMS_SROM_PA5GHW0A1, 213 BRCMS_SROM_PA5GHW0A1,
234 BRCMS_SROM_PA5GHW0A2, 214 BRCMS_SROM_PA5GHW0A2,
@@ -241,10 +221,6 @@ enum brcms_srom_id {
241 BRCMS_SROM_PA5GHW2A1, 221 BRCMS_SROM_PA5GHW2A1,
242 BRCMS_SROM_PA5GHW2A2, 222 BRCMS_SROM_PA5GHW2A2,
243 BRCMS_SROM_PA5GHW2A3, 223 BRCMS_SROM_PA5GHW2A3,
244 BRCMS_SROM_PA5GHW3A0,
245 BRCMS_SROM_PA5GHW3A1,
246 BRCMS_SROM_PA5GHW3A2,
247 BRCMS_SROM_PA5GHW3A3,
248 BRCMS_SROM_PA5GLW0A0, 224 BRCMS_SROM_PA5GLW0A0,
249 BRCMS_SROM_PA5GLW0A1, 225 BRCMS_SROM_PA5GLW0A1,
250 BRCMS_SROM_PA5GLW0A2, 226 BRCMS_SROM_PA5GLW0A2,
@@ -257,10 +233,6 @@ enum brcms_srom_id {
257 BRCMS_SROM_PA5GLW2A1, 233 BRCMS_SROM_PA5GLW2A1,
258 BRCMS_SROM_PA5GLW2A2, 234 BRCMS_SROM_PA5GLW2A2,
259 BRCMS_SROM_PA5GLW2A3, 235 BRCMS_SROM_PA5GLW2A3,
260 BRCMS_SROM_PA5GLW3A0,
261 BRCMS_SROM_PA5GLW3A1,
262 BRCMS_SROM_PA5GLW3A2,
263 BRCMS_SROM_PA5GLW3A3,
264 BRCMS_SROM_PA5GW0A0, 236 BRCMS_SROM_PA5GW0A0,
265 BRCMS_SROM_PA5GW0A1, 237 BRCMS_SROM_PA5GW0A1,
266 BRCMS_SROM_PA5GW0A2, 238 BRCMS_SROM_PA5GW0A2,
@@ -273,14 +245,9 @@ enum brcms_srom_id {
273 BRCMS_SROM_PA5GW2A1, 245 BRCMS_SROM_PA5GW2A1,
274 BRCMS_SROM_PA5GW2A2, 246 BRCMS_SROM_PA5GW2A2,
275 BRCMS_SROM_PA5GW2A3, 247 BRCMS_SROM_PA5GW2A3,
276 BRCMS_SROM_PA5GW3A0,
277 BRCMS_SROM_PA5GW3A1,
278 BRCMS_SROM_PA5GW3A2,
279 BRCMS_SROM_PA5GW3A3,
280}; 248};
281 249
282#define BRCMS_NUMRATES 16 /* max # of rates in a rateset */ 250#define BRCMS_NUMRATES 16 /* max # of rates in a rateset */
283#define D11_PHY_HDR_LEN 6 /* Phy header length - 6 bytes */
284 251
285/* phy types */ 252/* phy types */
286#define PHY_TYPE_A 0 /* Phy type A */ 253#define PHY_TYPE_A 0 /* Phy type A */
@@ -414,7 +381,6 @@ struct brcms_pub {
414 uint _nbands; /* # bands supported */ 381 uint _nbands; /* # bands supported */
415 uint now; /* # elapsed seconds */ 382 uint now; /* # elapsed seconds */
416 383
417 bool promisc; /* promiscuous destination address */
418 bool delayed_down; /* down delayed */ 384 bool delayed_down; /* down delayed */
419 bool associated; /* true:part of [I]BSS, false: not */ 385 bool associated; /* true:part of [I]BSS, false: not */
420 /* (union of stas_associated, aps_associated) */ 386 /* (union of stas_associated, aps_associated) */
@@ -572,7 +538,7 @@ extern int brcms_c_up(struct brcms_c_info *wlc);
572extern uint brcms_c_down(struct brcms_c_info *wlc); 538extern uint brcms_c_down(struct brcms_c_info *wlc);
573 539
574extern bool brcms_c_chipmatch(u16 vendor, u16 device); 540extern bool brcms_c_chipmatch(u16 vendor, u16 device);
575extern void brcms_c_init(struct brcms_c_info *wlc); 541extern void brcms_c_init(struct brcms_c_info *wlc, bool mute_tx);
576extern void brcms_c_reset(struct brcms_c_info *wlc); 542extern void brcms_c_reset(struct brcms_c_info *wlc);
577 543
578extern void brcms_c_intrson(struct brcms_c_info *wlc); 544extern void brcms_c_intrson(struct brcms_c_info *wlc);
@@ -628,7 +594,7 @@ extern void brcms_c_set_beacon_listen_interval(struct brcms_c_info *wlc,
628 u8 interval); 594 u8 interval);
629extern int brcms_c_set_tx_power(struct brcms_c_info *wlc, int txpwr); 595extern int brcms_c_set_tx_power(struct brcms_c_info *wlc, int txpwr);
630extern int brcms_c_get_tx_power(struct brcms_c_info *wlc); 596extern int brcms_c_get_tx_power(struct brcms_c_info *wlc);
631extern void brcms_c_set_radio_mpc(struct brcms_c_info *wlc, bool mpc);
632extern bool brcms_c_check_radio_disabled(struct brcms_c_info *wlc); 597extern bool brcms_c_check_radio_disabled(struct brcms_c_info *wlc);
598extern void brcms_c_mute(struct brcms_c_info *wlc, bool on);
633 599
634#endif /* _BRCM_PUB_H_ */ 600#endif /* _BRCM_PUB_H_ */
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/rate.h b/drivers/net/wireless/brcm80211/brcmsmac/rate.h
index e7b9dc2f2731..980d578825cc 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/rate.h
+++ b/drivers/net/wireless/brcm80211/brcmsmac/rate.h
@@ -19,6 +19,7 @@
19 19
20#include "types.h" 20#include "types.h"
21#include "d11.h" 21#include "d11.h"
22#include "phy_hal.h"
22 23
23extern const u8 rate_info[]; 24extern const u8 rate_info[];
24extern const struct brcms_c_rateset cck_ofdm_mimo_rates; 25extern const struct brcms_c_rateset cck_ofdm_mimo_rates;
@@ -198,11 +199,9 @@ static inline u8 cck_rspec(u8 cck)
198 199
199/* Convert encoded rate value in plcp header to numerical rates in 500 KHz 200/* Convert encoded rate value in plcp header to numerical rates in 500 KHz
200 * increments */ 201 * increments */
201extern const u8 ofdm_rate_lookup[];
202
203static inline u8 ofdm_phy2mac_rate(u8 rlpt) 202static inline u8 ofdm_phy2mac_rate(u8 rlpt)
204{ 203{
205 return ofdm_rate_lookup[rlpt & 0x7]; 204 return wlc_phy_get_ofdm_rate_lookup()[rlpt & 0x7];
206} 205}
207 206
208static inline u8 cck_phy2mac_rate(u8 signal) 207static inline u8 cck_phy2mac_rate(u8 signal)
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/srom.c b/drivers/net/wireless/brcm80211/brcmsmac/srom.c
index 99f791048e84..b6987ea9fc68 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/srom.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/srom.c
@@ -28,6 +28,7 @@
28#include "aiutils.h" 28#include "aiutils.h"
29#include "otp.h" 29#include "otp.h"
30#include "srom.h" 30#include "srom.h"
31#include "soc.h"
31 32
32/* 33/*
33 * SROM CRC8 polynomial value: 34 * SROM CRC8 polynomial value:
@@ -62,9 +63,6 @@
62#define SROM_MACHI_ET1 42 63#define SROM_MACHI_ET1 42
63#define SROM_MACMID_ET1 43 64#define SROM_MACMID_ET1 43
64#define SROM_MACLO_ET1 44 65#define SROM_MACLO_ET1 44
65#define SROM3_MACHI 37
66#define SROM3_MACMID 38
67#define SROM3_MACLO 39
68 66
69#define SROM_BXARSSI2G 40 67#define SROM_BXARSSI2G 40
70#define SROM_BXARSSI5G 41 68#define SROM_BXARSSI5G 41
@@ -101,7 +99,6 @@
101 99
102#define SROM_BFL 57 100#define SROM_BFL 57
103#define SROM_BFL2 28 101#define SROM_BFL2 28
104#define SROM3_BFL2 61
105 102
106#define SROM_AG10 58 103#define SROM_AG10 58
107 104
@@ -109,99 +106,16 @@
109 106
110#define SROM_OPO 60 107#define SROM_OPO 60
111 108
112#define SROM3_LEDDC 62
113
114#define SROM_CRCREV 63 109#define SROM_CRCREV 63
115 110
116/* SROM Rev 4: Reallocate the software part of the srom to accommodate
117 * MIMO features. It assumes up to two PCIE functions and 440 bytes
118 * of usable srom i.e. the usable storage in chips with OTP that
119 * implements hardware redundancy.
120 */
121
122#define SROM4_WORDS 220 111#define SROM4_WORDS 220
123 112
124#define SROM4_SIGN 32
125#define SROM4_SIGNATURE 0x5372
126
127#define SROM4_BREV 33
128
129#define SROM4_BFL0 34
130#define SROM4_BFL1 35
131#define SROM4_BFL2 36
132#define SROM4_BFL3 37
133#define SROM5_BFL0 37
134#define SROM5_BFL1 38
135#define SROM5_BFL2 39
136#define SROM5_BFL3 40
137
138#define SROM4_MACHI 38
139#define SROM4_MACMID 39
140#define SROM4_MACLO 40
141#define SROM5_MACHI 41
142#define SROM5_MACMID 42
143#define SROM5_MACLO 43
144
145#define SROM4_CCODE 41
146#define SROM4_REGREV 42
147#define SROM5_CCODE 34
148#define SROM5_REGREV 35
149
150#define SROM4_LEDBH10 43
151#define SROM4_LEDBH32 44
152#define SROM5_LEDBH10 59
153#define SROM5_LEDBH32 60
154
155#define SROM4_LEDDC 45
156#define SROM5_LEDDC 45
157
158#define SROM4_AA 46
159
160#define SROM4_AG10 47
161#define SROM4_AG32 48
162
163#define SROM4_TXPID2G 49
164#define SROM4_TXPID5G 51
165#define SROM4_TXPID5GL 53
166#define SROM4_TXPID5GH 55
167
168#define SROM4_TXRXC 61
169#define SROM4_TXCHAIN_MASK 0x000f 113#define SROM4_TXCHAIN_MASK 0x000f
170#define SROM4_TXCHAIN_SHIFT 0
171#define SROM4_RXCHAIN_MASK 0x00f0 114#define SROM4_RXCHAIN_MASK 0x00f0
172#define SROM4_RXCHAIN_SHIFT 4
173#define SROM4_SWITCH_MASK 0xff00 115#define SROM4_SWITCH_MASK 0xff00
174#define SROM4_SWITCH_SHIFT 8
175 116
176/* Per-path fields */ 117/* Per-path fields */
177#define MAX_PATH_SROM 4 118#define MAX_PATH_SROM 4
178#define SROM4_PATH0 64
179#define SROM4_PATH1 87
180#define SROM4_PATH2 110
181#define SROM4_PATH3 133
182
183#define SROM4_2G_ITT_MAXP 0
184#define SROM4_2G_PA 1
185#define SROM4_5G_ITT_MAXP 5
186#define SROM4_5GLH_MAXP 6
187#define SROM4_5G_PA 7
188#define SROM4_5GL_PA 11
189#define SROM4_5GH_PA 15
190
191/* All the miriad power offsets */
192#define SROM4_2G_CCKPO 156
193#define SROM4_2G_OFDMPO 157
194#define SROM4_5G_OFDMPO 159
195#define SROM4_5GL_OFDMPO 161
196#define SROM4_5GH_OFDMPO 163
197#define SROM4_2G_MCSPO 165
198#define SROM4_5G_MCSPO 173
199#define SROM4_5GL_MCSPO 181
200#define SROM4_5GH_MCSPO 189
201#define SROM4_CDDPO 197
202#define SROM4_STBCPO 198
203#define SROM4_BW40PO 199
204#define SROM4_BWDUPPO 200
205 119
206#define SROM4_CRCREV 219 120#define SROM4_CRCREV 219
207 121
@@ -424,103 +338,32 @@ struct brcms_varbuf {
424static const struct brcms_sromvar pci_sromvars[] = { 338static const struct brcms_sromvar pci_sromvars[] = {
425 {BRCMS_SROM_DEVID, 0xffffff00, SRFL_PRHEX | SRFL_NOVAR, PCI_F0DEVID, 339 {BRCMS_SROM_DEVID, 0xffffff00, SRFL_PRHEX | SRFL_NOVAR, PCI_F0DEVID,
426 0xffff}, 340 0xffff},
427 {BRCMS_SROM_BOARDREV, 0x0000000e, SRFL_PRHEX, SROM_AABREV,
428 SROM_BR_MASK},
429 {BRCMS_SROM_BOARDREV, 0x000000f0, SRFL_PRHEX, SROM4_BREV, 0xffff},
430 {BRCMS_SROM_BOARDREV, 0xffffff00, SRFL_PRHEX, SROM8_BREV, 0xffff}, 341 {BRCMS_SROM_BOARDREV, 0xffffff00, SRFL_PRHEX, SROM8_BREV, 0xffff},
431 {BRCMS_SROM_BOARDFLAGS, 0x00000002, SRFL_PRHEX, SROM_BFL, 0xffff},
432 {BRCMS_SROM_BOARDFLAGS, 0x00000004, SRFL_PRHEX | SRFL_MORE, SROM_BFL,
433 0xffff},
434 {BRCMS_SROM_CONT, 0, 0, SROM_BFL2, 0xffff},
435 {BRCMS_SROM_BOARDFLAGS, 0x00000008, SRFL_PRHEX | SRFL_MORE, SROM_BFL,
436 0xffff},
437 {BRCMS_SROM_CONT, 0, 0, SROM3_BFL2, 0xffff},
438 {BRCMS_SROM_BOARDFLAGS, 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL0,
439 0xffff},
440 {BRCMS_SROM_CONT, 0, 0, SROM4_BFL1, 0xffff},
441 {BRCMS_SROM_BOARDFLAGS, 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL0,
442 0xffff},
443 {BRCMS_SROM_CONT, 0, 0, SROM5_BFL1, 0xffff},
444 {BRCMS_SROM_BOARDFLAGS, 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL0, 342 {BRCMS_SROM_BOARDFLAGS, 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL0,
445 0xffff}, 343 0xffff},
446 {BRCMS_SROM_CONT, 0, 0, SROM8_BFL1, 0xffff}, 344 {BRCMS_SROM_CONT, 0, 0, SROM8_BFL1, 0xffff},
447 {BRCMS_SROM_BOARDFLAGS2, 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL2,
448 0xffff},
449 {BRCMS_SROM_CONT, 0, 0, SROM4_BFL3, 0xffff},
450 {BRCMS_SROM_BOARDFLAGS2, 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL2,
451 0xffff},
452 {BRCMS_SROM_CONT, 0, 0, SROM5_BFL3, 0xffff},
453 {BRCMS_SROM_BOARDFLAGS2, 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL2, 345 {BRCMS_SROM_BOARDFLAGS2, 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL2,
454 0xffff}, 346 0xffff},
455 {BRCMS_SROM_CONT, 0, 0, SROM8_BFL3, 0xffff}, 347 {BRCMS_SROM_CONT, 0, 0, SROM8_BFL3, 0xffff},
456 {BRCMS_SROM_BOARDTYPE, 0xfffffffc, SRFL_PRHEX, SROM_SSID, 0xffff}, 348 {BRCMS_SROM_BOARDTYPE, 0xfffffffc, SRFL_PRHEX, SROM_SSID, 0xffff},
457 {BRCMS_SROM_BOARDNUM, 0x00000006, 0, SROM_MACLO_IL0, 0xffff},
458 {BRCMS_SROM_BOARDNUM, 0x00000008, 0, SROM3_MACLO, 0xffff},
459 {BRCMS_SROM_BOARDNUM, 0x00000010, 0, SROM4_MACLO, 0xffff},
460 {BRCMS_SROM_BOARDNUM, 0x000000e0, 0, SROM5_MACLO, 0xffff},
461 {BRCMS_SROM_BOARDNUM, 0xffffff00, 0, SROM8_MACLO, 0xffff}, 349 {BRCMS_SROM_BOARDNUM, 0xffffff00, 0, SROM8_MACLO, 0xffff},
462 {BRCMS_SROM_CC, 0x00000002, 0, SROM_AABREV, SROM_CC_MASK},
463 {BRCMS_SROM_REGREV, 0x00000008, 0, SROM_OPO, 0xff00},
464 {BRCMS_SROM_REGREV, 0x00000010, 0, SROM4_REGREV, 0x00ff},
465 {BRCMS_SROM_REGREV, 0x000000e0, 0, SROM5_REGREV, 0x00ff},
466 {BRCMS_SROM_REGREV, 0xffffff00, 0, SROM8_REGREV, 0x00ff}, 350 {BRCMS_SROM_REGREV, 0xffffff00, 0, SROM8_REGREV, 0x00ff},
467 {BRCMS_SROM_LEDBH0, 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0x00ff},
468 {BRCMS_SROM_LEDBH1, 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0xff00},
469 {BRCMS_SROM_LEDBH2, 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0x00ff},
470 {BRCMS_SROM_LEDBH3, 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0xff00},
471 {BRCMS_SROM_LEDBH0, 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0x00ff},
472 {BRCMS_SROM_LEDBH1, 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0xff00},
473 {BRCMS_SROM_LEDBH2, 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0x00ff},
474 {BRCMS_SROM_LEDBH3, 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0xff00},
475 {BRCMS_SROM_LEDBH0, 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0x00ff},
476 {BRCMS_SROM_LEDBH1, 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0xff00},
477 {BRCMS_SROM_LEDBH2, 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0x00ff},
478 {BRCMS_SROM_LEDBH3, 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0xff00},
479 {BRCMS_SROM_LEDBH0, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0x00ff}, 351 {BRCMS_SROM_LEDBH0, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0x00ff},
480 {BRCMS_SROM_LEDBH1, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0xff00}, 352 {BRCMS_SROM_LEDBH1, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0xff00},
481 {BRCMS_SROM_LEDBH2, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0x00ff}, 353 {BRCMS_SROM_LEDBH2, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0x00ff},
482 {BRCMS_SROM_LEDBH3, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0xff00}, 354 {BRCMS_SROM_LEDBH3, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0xff00},
483 {BRCMS_SROM_PA0B0, 0x0000000e, SRFL_PRHEX, SROM_WL0PAB0, 0xffff},
484 {BRCMS_SROM_PA0B1, 0x0000000e, SRFL_PRHEX, SROM_WL0PAB1, 0xffff},
485 {BRCMS_SROM_PA0B2, 0x0000000e, SRFL_PRHEX, SROM_WL0PAB2, 0xffff},
486 {BRCMS_SROM_PA0ITSSIT, 0x0000000e, 0, SROM_ITT, 0x00ff},
487 {BRCMS_SROM_PA0MAXPWR, 0x0000000e, 0, SROM_WL10MAXP, 0x00ff},
488 {BRCMS_SROM_PA0B0, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB0, 0xffff}, 355 {BRCMS_SROM_PA0B0, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB0, 0xffff},
489 {BRCMS_SROM_PA0B1, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB1, 0xffff}, 356 {BRCMS_SROM_PA0B1, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB1, 0xffff},
490 {BRCMS_SROM_PA0B2, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB2, 0xffff}, 357 {BRCMS_SROM_PA0B2, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB2, 0xffff},
491 {BRCMS_SROM_PA0ITSSIT, 0xffffff00, 0, SROM8_W0_ITTMAXP, 0xff00}, 358 {BRCMS_SROM_PA0ITSSIT, 0xffffff00, 0, SROM8_W0_ITTMAXP, 0xff00},
492 {BRCMS_SROM_PA0MAXPWR, 0xffffff00, 0, SROM8_W0_ITTMAXP, 0x00ff}, 359 {BRCMS_SROM_PA0MAXPWR, 0xffffff00, 0, SROM8_W0_ITTMAXP, 0x00ff},
493 {BRCMS_SROM_OPO, 0x0000000c, 0, SROM_OPO, 0x00ff},
494 {BRCMS_SROM_OPO, 0xffffff00, 0, SROM8_2G_OFDMPO, 0x00ff}, 360 {BRCMS_SROM_OPO, 0xffffff00, 0, SROM8_2G_OFDMPO, 0x00ff},
495 {BRCMS_SROM_AA2G, 0x0000000e, 0, SROM_AABREV, SROM_AA0_MASK},
496 {BRCMS_SROM_AA2G, 0x000000f0, 0, SROM4_AA, 0x00ff},
497 {BRCMS_SROM_AA2G, 0xffffff00, 0, SROM8_AA, 0x00ff}, 361 {BRCMS_SROM_AA2G, 0xffffff00, 0, SROM8_AA, 0x00ff},
498 {BRCMS_SROM_AA5G, 0x0000000e, 0, SROM_AABREV, SROM_AA1_MASK},
499 {BRCMS_SROM_AA5G, 0x000000f0, 0, SROM4_AA, 0xff00},
500 {BRCMS_SROM_AA5G, 0xffffff00, 0, SROM8_AA, 0xff00}, 362 {BRCMS_SROM_AA5G, 0xffffff00, 0, SROM8_AA, 0xff00},
501 {BRCMS_SROM_AG0, 0x0000000e, 0, SROM_AG10, 0x00ff},
502 {BRCMS_SROM_AG1, 0x0000000e, 0, SROM_AG10, 0xff00},
503 {BRCMS_SROM_AG0, 0x000000f0, 0, SROM4_AG10, 0x00ff},
504 {BRCMS_SROM_AG1, 0x000000f0, 0, SROM4_AG10, 0xff00},
505 {BRCMS_SROM_AG2, 0x000000f0, 0, SROM4_AG32, 0x00ff},
506 {BRCMS_SROM_AG3, 0x000000f0, 0, SROM4_AG32, 0xff00},
507 {BRCMS_SROM_AG0, 0xffffff00, 0, SROM8_AG10, 0x00ff}, 363 {BRCMS_SROM_AG0, 0xffffff00, 0, SROM8_AG10, 0x00ff},
508 {BRCMS_SROM_AG1, 0xffffff00, 0, SROM8_AG10, 0xff00}, 364 {BRCMS_SROM_AG1, 0xffffff00, 0, SROM8_AG10, 0xff00},
509 {BRCMS_SROM_AG2, 0xffffff00, 0, SROM8_AG32, 0x00ff}, 365 {BRCMS_SROM_AG2, 0xffffff00, 0, SROM8_AG32, 0x00ff},
510 {BRCMS_SROM_AG3, 0xffffff00, 0, SROM8_AG32, 0xff00}, 366 {BRCMS_SROM_AG3, 0xffffff00, 0, SROM8_AG32, 0xff00},
511 {BRCMS_SROM_PA1B0, 0x0000000e, SRFL_PRHEX, SROM_WL1PAB0, 0xffff},
512 {BRCMS_SROM_PA1B1, 0x0000000e, SRFL_PRHEX, SROM_WL1PAB1, 0xffff},
513 {BRCMS_SROM_PA1B2, 0x0000000e, SRFL_PRHEX, SROM_WL1PAB2, 0xffff},
514 {BRCMS_SROM_PA1LOB0, 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB0, 0xffff},
515 {BRCMS_SROM_PA1LOB1, 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB1, 0xffff},
516 {BRCMS_SROM_PA1LOB2, 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB2, 0xffff},
517 {BRCMS_SROM_PA1HIB0, 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB0, 0xffff},
518 {BRCMS_SROM_PA1HIB1, 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB1, 0xffff},
519 {BRCMS_SROM_PA1HIB2, 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB2, 0xffff},
520 {BRCMS_SROM_PA1ITSSIT, 0x0000000e, 0, SROM_ITT, 0xff00},
521 {BRCMS_SROM_PA1MAXPWR, 0x0000000e, 0, SROM_WL10MAXP, 0xff00},
522 {BRCMS_SROM_PA1LOMAXPWR, 0x0000000c, 0, SROM_WL1LHMAXP, 0xff00},
523 {BRCMS_SROM_PA1HIMAXPWR, 0x0000000c, 0, SROM_WL1LHMAXP, 0x00ff},
524 {BRCMS_SROM_PA1B0, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0, 0xffff}, 367 {BRCMS_SROM_PA1B0, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0, 0xffff},
525 {BRCMS_SROM_PA1B1, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1, 0xffff}, 368 {BRCMS_SROM_PA1B1, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1, 0xffff},
526 {BRCMS_SROM_PA1B2, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2, 0xffff}, 369 {BRCMS_SROM_PA1B2, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2, 0xffff},
@@ -534,40 +377,20 @@ static const struct brcms_sromvar pci_sromvars[] = {
534 {BRCMS_SROM_PA1MAXPWR, 0xffffff00, 0, SROM8_W1_ITTMAXP, 0x00ff}, 377 {BRCMS_SROM_PA1MAXPWR, 0xffffff00, 0, SROM8_W1_ITTMAXP, 0x00ff},
535 {BRCMS_SROM_PA1LOMAXPWR, 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0xff00}, 378 {BRCMS_SROM_PA1LOMAXPWR, 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0xff00},
536 {BRCMS_SROM_PA1HIMAXPWR, 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0x00ff}, 379 {BRCMS_SROM_PA1HIMAXPWR, 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0x00ff},
537 {BRCMS_SROM_BXA2G, 0x00000008, 0, SROM_BXARSSI2G, 0x1800},
538 {BRCMS_SROM_RSSISAV2G, 0x00000008, 0, SROM_BXARSSI2G, 0x0700},
539 {BRCMS_SROM_RSSISMC2G, 0x00000008, 0, SROM_BXARSSI2G, 0x00f0},
540 {BRCMS_SROM_RSSISMF2G, 0x00000008, 0, SROM_BXARSSI2G, 0x000f},
541 {BRCMS_SROM_BXA2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x1800}, 380 {BRCMS_SROM_BXA2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x1800},
542 {BRCMS_SROM_RSSISAV2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x0700}, 381 {BRCMS_SROM_RSSISAV2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x0700},
543 {BRCMS_SROM_RSSISMC2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x00f0}, 382 {BRCMS_SROM_RSSISMC2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x00f0},
544 {BRCMS_SROM_RSSISMF2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x000f}, 383 {BRCMS_SROM_RSSISMF2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x000f},
545 {BRCMS_SROM_BXA5G, 0x00000008, 0, SROM_BXARSSI5G, 0x1800},
546 {BRCMS_SROM_RSSISAV5G, 0x00000008, 0, SROM_BXARSSI5G, 0x0700},
547 {BRCMS_SROM_RSSISMC5G, 0x00000008, 0, SROM_BXARSSI5G, 0x00f0},
548 {BRCMS_SROM_RSSISMF5G, 0x00000008, 0, SROM_BXARSSI5G, 0x000f},
549 {BRCMS_SROM_BXA5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x1800}, 384 {BRCMS_SROM_BXA5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x1800},
550 {BRCMS_SROM_RSSISAV5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x0700}, 385 {BRCMS_SROM_RSSISAV5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x0700},
551 {BRCMS_SROM_RSSISMC5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x00f0}, 386 {BRCMS_SROM_RSSISMC5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x00f0},
552 {BRCMS_SROM_RSSISMF5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x000f}, 387 {BRCMS_SROM_RSSISMF5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x000f},
553 {BRCMS_SROM_TRI2G, 0x00000008, 0, SROM_TRI52G, 0x00ff},
554 {BRCMS_SROM_TRI5G, 0x00000008, 0, SROM_TRI52G, 0xff00},
555 {BRCMS_SROM_TRI5GL, 0x00000008, 0, SROM_TRI5GHL, 0x00ff},
556 {BRCMS_SROM_TRI5GH, 0x00000008, 0, SROM_TRI5GHL, 0xff00},
557 {BRCMS_SROM_TRI2G, 0xffffff00, 0, SROM8_TRI52G, 0x00ff}, 388 {BRCMS_SROM_TRI2G, 0xffffff00, 0, SROM8_TRI52G, 0x00ff},
558 {BRCMS_SROM_TRI5G, 0xffffff00, 0, SROM8_TRI52G, 0xff00}, 389 {BRCMS_SROM_TRI5G, 0xffffff00, 0, SROM8_TRI52G, 0xff00},
559 {BRCMS_SROM_TRI5GL, 0xffffff00, 0, SROM8_TRI5GHL, 0x00ff}, 390 {BRCMS_SROM_TRI5GL, 0xffffff00, 0, SROM8_TRI5GHL, 0x00ff},
560 {BRCMS_SROM_TRI5GH, 0xffffff00, 0, SROM8_TRI5GHL, 0xff00}, 391 {BRCMS_SROM_TRI5GH, 0xffffff00, 0, SROM8_TRI5GHL, 0xff00},
561 {BRCMS_SROM_RXPO2G, 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0x00ff},
562 {BRCMS_SROM_RXPO5G, 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0xff00},
563 {BRCMS_SROM_RXPO2G, 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0x00ff}, 392 {BRCMS_SROM_RXPO2G, 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0x00ff},
564 {BRCMS_SROM_RXPO5G, 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0xff00}, 393 {BRCMS_SROM_RXPO5G, 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0xff00},
565 {BRCMS_SROM_TXCHAIN, 0x000000f0, SRFL_NOFFS, SROM4_TXRXC,
566 SROM4_TXCHAIN_MASK},
567 {BRCMS_SROM_RXCHAIN, 0x000000f0, SRFL_NOFFS, SROM4_TXRXC,
568 SROM4_RXCHAIN_MASK},
569 {BRCMS_SROM_ANTSWITCH, 0x000000f0, SRFL_NOFFS, SROM4_TXRXC,
570 SROM4_SWITCH_MASK},
571 {BRCMS_SROM_TXCHAIN, 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, 394 {BRCMS_SROM_TXCHAIN, 0xffffff00, SRFL_NOFFS, SROM8_TXRXC,
572 SROM4_TXCHAIN_MASK}, 395 SROM4_TXCHAIN_MASK},
573 {BRCMS_SROM_RXCHAIN, 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, 396 {BRCMS_SROM_RXCHAIN, 0xffffff00, SRFL_NOFFS, SROM8_TXRXC,
@@ -594,43 +417,11 @@ static const struct brcms_sromvar pci_sromvars[] = {
594 SROM8_FEM_ANTSWLUT_MASK}, 417 SROM8_FEM_ANTSWLUT_MASK},
595 {BRCMS_SROM_TEMPTHRESH, 0xffffff00, 0, SROM8_THERMAL, 0xff00}, 418 {BRCMS_SROM_TEMPTHRESH, 0xffffff00, 0, SROM8_THERMAL, 0xff00},
596 {BRCMS_SROM_TEMPOFFSET, 0xffffff00, 0, SROM8_THERMAL, 0x00ff}, 419 {BRCMS_SROM_TEMPOFFSET, 0xffffff00, 0, SROM8_THERMAL, 0x00ff},
597 {BRCMS_SROM_TXPID2GA0, 0x000000f0, 0, SROM4_TXPID2G, 0x00ff}, 420
598 {BRCMS_SROM_TXPID2GA1, 0x000000f0, 0, SROM4_TXPID2G, 0xff00},
599 {BRCMS_SROM_TXPID2GA2, 0x000000f0, 0, SROM4_TXPID2G + 1, 0x00ff},
600 {BRCMS_SROM_TXPID2GA3, 0x000000f0, 0, SROM4_TXPID2G + 1, 0xff00},
601 {BRCMS_SROM_TXPID5GA0, 0x000000f0, 0, SROM4_TXPID5G, 0x00ff},
602 {BRCMS_SROM_TXPID5GA1, 0x000000f0, 0, SROM4_TXPID5G, 0xff00},
603 {BRCMS_SROM_TXPID5GA2, 0x000000f0, 0, SROM4_TXPID5G + 1, 0x00ff},
604 {BRCMS_SROM_TXPID5GA3, 0x000000f0, 0, SROM4_TXPID5G + 1, 0xff00},
605 {BRCMS_SROM_TXPID5GLA0, 0x000000f0, 0, SROM4_TXPID5GL, 0x00ff},
606 {BRCMS_SROM_TXPID5GLA1, 0x000000f0, 0, SROM4_TXPID5GL, 0xff00},
607 {BRCMS_SROM_TXPID5GLA2, 0x000000f0, 0, SROM4_TXPID5GL + 1, 0x00ff},
608 {BRCMS_SROM_TXPID5GLA3, 0x000000f0, 0, SROM4_TXPID5GL + 1, 0xff00},
609 {BRCMS_SROM_TXPID5GHA0, 0x000000f0, 0, SROM4_TXPID5GH, 0x00ff},
610 {BRCMS_SROM_TXPID5GHA1, 0x000000f0, 0, SROM4_TXPID5GH, 0xff00},
611 {BRCMS_SROM_TXPID5GHA2, 0x000000f0, 0, SROM4_TXPID5GH + 1, 0x00ff},
612 {BRCMS_SROM_TXPID5GHA3, 0x000000f0, 0, SROM4_TXPID5GH + 1, 0xff00},
613
614 {BRCMS_SROM_CCODE, 0x0000000f, SRFL_CCODE, SROM_CCODE, 0xffff},
615 {BRCMS_SROM_CCODE, 0x00000010, SRFL_CCODE, SROM4_CCODE, 0xffff},
616 {BRCMS_SROM_CCODE, 0x000000e0, SRFL_CCODE, SROM5_CCODE, 0xffff},
617 {BRCMS_SROM_CCODE, 0xffffff00, SRFL_CCODE, SROM8_CCODE, 0xffff}, 421 {BRCMS_SROM_CCODE, 0xffffff00, SRFL_CCODE, SROM8_CCODE, 0xffff},
618 {BRCMS_SROM_MACADDR, 0xffffff00, SRFL_ETHADDR, SROM8_MACHI, 0xffff}, 422 {BRCMS_SROM_MACADDR, 0xffffff00, SRFL_ETHADDR, SROM8_MACHI, 0xffff},
619 {BRCMS_SROM_MACADDR, 0x000000e0, SRFL_ETHADDR, SROM5_MACHI, 0xffff},
620 {BRCMS_SROM_MACADDR, 0x00000010, SRFL_ETHADDR, SROM4_MACHI, 0xffff},
621 {BRCMS_SROM_MACADDR, 0x00000008, SRFL_ETHADDR, SROM3_MACHI, 0xffff},
622 {BRCMS_SROM_IL0MACADDR, 0x00000007, SRFL_ETHADDR, SROM_MACHI_IL0,
623 0xffff},
624 {BRCMS_SROM_ET1MACADDR, 0x00000007, SRFL_ETHADDR, SROM_MACHI_ET1,
625 0xffff},
626 {BRCMS_SROM_LEDDC, 0xffffff00, SRFL_NOFFS | SRFL_LEDDC, SROM8_LEDDC, 423 {BRCMS_SROM_LEDDC, 0xffffff00, SRFL_NOFFS | SRFL_LEDDC, SROM8_LEDDC,
627 0xffff}, 424 0xffff},
628 {BRCMS_SROM_LEDDC, 0x000000e0, SRFL_NOFFS | SRFL_LEDDC, SROM5_LEDDC,
629 0xffff},
630 {BRCMS_SROM_LEDDC, 0x00000010, SRFL_NOFFS | SRFL_LEDDC, SROM4_LEDDC,
631 0xffff},
632 {BRCMS_SROM_LEDDC, 0x00000008, SRFL_NOFFS | SRFL_LEDDC, SROM3_LEDDC,
633 0xffff},
634 {BRCMS_SROM_RAWTEMPSENSE, 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS, 425 {BRCMS_SROM_RAWTEMPSENSE, 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS,
635 0x01ff}, 426 0x01ff},
636 {BRCMS_SROM_MEASPOWER, 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS, 427 {BRCMS_SROM_MEASPOWER, 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS,
@@ -650,16 +441,7 @@ static const struct brcms_sromvar pci_sromvars[] = {
650 {BRCMS_SROM_PHYCAL_TEMPDELTA, 0xffffff00, 0, SROM8_PHYCAL_TEMPDELTA, 441 {BRCMS_SROM_PHYCAL_TEMPDELTA, 0xffffff00, 0, SROM8_PHYCAL_TEMPDELTA,
651 0x00ff}, 442 0x00ff},
652 443
653 {BRCMS_SROM_CCK2GPO, 0x000000f0, 0, SROM4_2G_CCKPO, 0xffff},
654 {BRCMS_SROM_CCK2GPO, 0x00000100, 0, SROM8_2G_CCKPO, 0xffff}, 444 {BRCMS_SROM_CCK2GPO, 0x00000100, 0, SROM8_2G_CCKPO, 0xffff},
655 {BRCMS_SROM_OFDM2GPO, 0x000000f0, SRFL_MORE, SROM4_2G_OFDMPO, 0xffff},
656 {BRCMS_SROM_CONT, 0, 0, SROM4_2G_OFDMPO + 1, 0xffff},
657 {BRCMS_SROM_OFDM5GPO, 0x000000f0, SRFL_MORE, SROM4_5G_OFDMPO, 0xffff},
658 {BRCMS_SROM_CONT, 0, 0, SROM4_5G_OFDMPO + 1, 0xffff},
659 {BRCMS_SROM_OFDM5GLPO, 0x000000f0, SRFL_MORE, SROM4_5GL_OFDMPO, 0xffff},
660 {BRCMS_SROM_CONT, 0, 0, SROM4_5GL_OFDMPO + 1, 0xffff},
661 {BRCMS_SROM_OFDM5GHPO, 0x000000f0, SRFL_MORE, SROM4_5GH_OFDMPO, 0xffff},
662 {BRCMS_SROM_CONT, 0, 0, SROM4_5GH_OFDMPO + 1, 0xffff},
663 {BRCMS_SROM_OFDM2GPO, 0x00000100, SRFL_MORE, SROM8_2G_OFDMPO, 0xffff}, 445 {BRCMS_SROM_OFDM2GPO, 0x00000100, SRFL_MORE, SROM8_2G_OFDMPO, 0xffff},
664 {BRCMS_SROM_CONT, 0, 0, SROM8_2G_OFDMPO + 1, 0xffff}, 446 {BRCMS_SROM_CONT, 0, 0, SROM8_2G_OFDMPO + 1, 0xffff},
665 {BRCMS_SROM_OFDM5GPO, 0x00000100, SRFL_MORE, SROM8_5G_OFDMPO, 0xffff}, 447 {BRCMS_SROM_OFDM5GPO, 0x00000100, SRFL_MORE, SROM8_5G_OFDMPO, 0xffff},
@@ -668,38 +450,6 @@ static const struct brcms_sromvar pci_sromvars[] = {
668 {BRCMS_SROM_CONT, 0, 0, SROM8_5GL_OFDMPO + 1, 0xffff}, 450 {BRCMS_SROM_CONT, 0, 0, SROM8_5GL_OFDMPO + 1, 0xffff},
669 {BRCMS_SROM_OFDM5GHPO, 0x00000100, SRFL_MORE, SROM8_5GH_OFDMPO, 0xffff}, 451 {BRCMS_SROM_OFDM5GHPO, 0x00000100, SRFL_MORE, SROM8_5GH_OFDMPO, 0xffff},
670 {BRCMS_SROM_CONT, 0, 0, SROM8_5GH_OFDMPO + 1, 0xffff}, 452 {BRCMS_SROM_CONT, 0, 0, SROM8_5GH_OFDMPO + 1, 0xffff},
671 {BRCMS_SROM_MCS2GPO0, 0x000000f0, 0, SROM4_2G_MCSPO, 0xffff},
672 {BRCMS_SROM_MCS2GPO1, 0x000000f0, 0, SROM4_2G_MCSPO + 1, 0xffff},
673 {BRCMS_SROM_MCS2GPO2, 0x000000f0, 0, SROM4_2G_MCSPO + 2, 0xffff},
674 {BRCMS_SROM_MCS2GPO3, 0x000000f0, 0, SROM4_2G_MCSPO + 3, 0xffff},
675 {BRCMS_SROM_MCS2GPO4, 0x000000f0, 0, SROM4_2G_MCSPO + 4, 0xffff},
676 {BRCMS_SROM_MCS2GPO5, 0x000000f0, 0, SROM4_2G_MCSPO + 5, 0xffff},
677 {BRCMS_SROM_MCS2GPO6, 0x000000f0, 0, SROM4_2G_MCSPO + 6, 0xffff},
678 {BRCMS_SROM_MCS2GPO7, 0x000000f0, 0, SROM4_2G_MCSPO + 7, 0xffff},
679 {BRCMS_SROM_MCS5GPO0, 0x000000f0, 0, SROM4_5G_MCSPO, 0xffff},
680 {BRCMS_SROM_MCS5GPO1, 0x000000f0, 0, SROM4_5G_MCSPO + 1, 0xffff},
681 {BRCMS_SROM_MCS5GPO2, 0x000000f0, 0, SROM4_5G_MCSPO + 2, 0xffff},
682 {BRCMS_SROM_MCS5GPO3, 0x000000f0, 0, SROM4_5G_MCSPO + 3, 0xffff},
683 {BRCMS_SROM_MCS5GPO4, 0x000000f0, 0, SROM4_5G_MCSPO + 4, 0xffff},
684 {BRCMS_SROM_MCS5GPO5, 0x000000f0, 0, SROM4_5G_MCSPO + 5, 0xffff},
685 {BRCMS_SROM_MCS5GPO6, 0x000000f0, 0, SROM4_5G_MCSPO + 6, 0xffff},
686 {BRCMS_SROM_MCS5GPO7, 0x000000f0, 0, SROM4_5G_MCSPO + 7, 0xffff},
687 {BRCMS_SROM_MCS5GLPO0, 0x000000f0, 0, SROM4_5GL_MCSPO, 0xffff},
688 {BRCMS_SROM_MCS5GLPO1, 0x000000f0, 0, SROM4_5GL_MCSPO + 1, 0xffff},
689 {BRCMS_SROM_MCS5GLPO2, 0x000000f0, 0, SROM4_5GL_MCSPO + 2, 0xffff},
690 {BRCMS_SROM_MCS5GLPO3, 0x000000f0, 0, SROM4_5GL_MCSPO + 3, 0xffff},
691 {BRCMS_SROM_MCS5GLPO4, 0x000000f0, 0, SROM4_5GL_MCSPO + 4, 0xffff},
692 {BRCMS_SROM_MCS5GLPO5, 0x000000f0, 0, SROM4_5GL_MCSPO + 5, 0xffff},
693 {BRCMS_SROM_MCS5GLPO6, 0x000000f0, 0, SROM4_5GL_MCSPO + 6, 0xffff},
694 {BRCMS_SROM_MCS5GLPO7, 0x000000f0, 0, SROM4_5GL_MCSPO + 7, 0xffff},
695 {BRCMS_SROM_MCS5GHPO0, 0x000000f0, 0, SROM4_5GH_MCSPO, 0xffff},
696 {BRCMS_SROM_MCS5GHPO1, 0x000000f0, 0, SROM4_5GH_MCSPO + 1, 0xffff},
697 {BRCMS_SROM_MCS5GHPO2, 0x000000f0, 0, SROM4_5GH_MCSPO + 2, 0xffff},
698 {BRCMS_SROM_MCS5GHPO3, 0x000000f0, 0, SROM4_5GH_MCSPO + 3, 0xffff},
699 {BRCMS_SROM_MCS5GHPO4, 0x000000f0, 0, SROM4_5GH_MCSPO + 4, 0xffff},
700 {BRCMS_SROM_MCS5GHPO5, 0x000000f0, 0, SROM4_5GH_MCSPO + 5, 0xffff},
701 {BRCMS_SROM_MCS5GHPO6, 0x000000f0, 0, SROM4_5GH_MCSPO + 6, 0xffff},
702 {BRCMS_SROM_MCS5GHPO7, 0x000000f0, 0, SROM4_5GH_MCSPO + 7, 0xffff},
703 {BRCMS_SROM_MCS2GPO0, 0x00000100, 0, SROM8_2G_MCSPO, 0xffff}, 453 {BRCMS_SROM_MCS2GPO0, 0x00000100, 0, SROM8_2G_MCSPO, 0xffff},
704 {BRCMS_SROM_MCS2GPO1, 0x00000100, 0, SROM8_2G_MCSPO + 1, 0xffff}, 454 {BRCMS_SROM_MCS2GPO1, 0x00000100, 0, SROM8_2G_MCSPO + 1, 0xffff},
705 {BRCMS_SROM_MCS2GPO2, 0x00000100, 0, SROM8_2G_MCSPO + 2, 0xffff}, 455 {BRCMS_SROM_MCS2GPO2, 0x00000100, 0, SROM8_2G_MCSPO + 2, 0xffff},
@@ -732,10 +482,6 @@ static const struct brcms_sromvar pci_sromvars[] = {
732 {BRCMS_SROM_MCS5GHPO5, 0x00000100, 0, SROM8_5GH_MCSPO + 5, 0xffff}, 482 {BRCMS_SROM_MCS5GHPO5, 0x00000100, 0, SROM8_5GH_MCSPO + 5, 0xffff},
733 {BRCMS_SROM_MCS5GHPO6, 0x00000100, 0, SROM8_5GH_MCSPO + 6, 0xffff}, 483 {BRCMS_SROM_MCS5GHPO6, 0x00000100, 0, SROM8_5GH_MCSPO + 6, 0xffff},
734 {BRCMS_SROM_MCS5GHPO7, 0x00000100, 0, SROM8_5GH_MCSPO + 7, 0xffff}, 484 {BRCMS_SROM_MCS5GHPO7, 0x00000100, 0, SROM8_5GH_MCSPO + 7, 0xffff},
735 {BRCMS_SROM_CDDPO, 0x000000f0, 0, SROM4_CDDPO, 0xffff},
736 {BRCMS_SROM_STBCPO, 0x000000f0, 0, SROM4_STBCPO, 0xffff},
737 {BRCMS_SROM_BW40PO, 0x000000f0, 0, SROM4_BW40PO, 0xffff},
738 {BRCMS_SROM_BWDUPPO, 0x000000f0, 0, SROM4_BWDUPPO, 0xffff},
739 {BRCMS_SROM_CDDPO, 0x00000100, 0, SROM8_CDDPO, 0xffff}, 485 {BRCMS_SROM_CDDPO, 0x00000100, 0, SROM8_CDDPO, 0xffff},
740 {BRCMS_SROM_STBCPO, 0x00000100, 0, SROM8_STBCPO, 0xffff}, 486 {BRCMS_SROM_STBCPO, 0x00000100, 0, SROM8_STBCPO, 0xffff},
741 {BRCMS_SROM_BW40PO, 0x00000100, 0, SROM8_BW40PO, 0xffff}, 487 {BRCMS_SROM_BW40PO, 0x00000100, 0, SROM8_BW40PO, 0xffff},
@@ -811,34 +557,6 @@ static const struct brcms_sromvar pci_sromvars[] = {
811}; 557};
812 558
813static const struct brcms_sromvar perpath_pci_sromvars[] = { 559static const struct brcms_sromvar perpath_pci_sromvars[] = {
814 {BRCMS_SROM_MAXP2GA0, 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0x00ff},
815 {BRCMS_SROM_ITT2GA0, 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0xff00},
816 {BRCMS_SROM_ITT5GA0, 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0xff00},
817 {BRCMS_SROM_PA2GW0A0, 0x000000f0, SRFL_PRHEX, SROM4_2G_PA, 0xffff},
818 {BRCMS_SROM_PA2GW1A0, 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 1, 0xffff},
819 {BRCMS_SROM_PA2GW2A0, 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 2, 0xffff},
820 {BRCMS_SROM_PA2GW3A0, 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 3, 0xffff},
821 {BRCMS_SROM_MAXP5GA0, 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0x00ff},
822 {BRCMS_SROM_MAXP5GHA0, 0x000000f0, 0, SROM4_5GLH_MAXP, 0x00ff},
823 {BRCMS_SROM_MAXP5GLA0, 0x000000f0, 0, SROM4_5GLH_MAXP, 0xff00},
824 {BRCMS_SROM_PA5GW0A0, 0x000000f0, SRFL_PRHEX, SROM4_5G_PA, 0xffff},
825 {BRCMS_SROM_PA5GW1A0, 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 1, 0xffff},
826 {BRCMS_SROM_PA5GW2A0, 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 2, 0xffff},
827 {BRCMS_SROM_PA5GW3A0, 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 3, 0xffff},
828 {BRCMS_SROM_PA5GLW0A0, 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA, 0xffff},
829 {BRCMS_SROM_PA5GLW1A0, 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 1,
830 0xffff},
831 {BRCMS_SROM_PA5GLW2A0, 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 2,
832 0xffff},
833 {BRCMS_SROM_PA5GLW3A0, 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 3,
834 0xffff},
835 {BRCMS_SROM_PA5GHW0A0, 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA, 0xffff},
836 {BRCMS_SROM_PA5GHW1A0, 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 1,
837 0xffff},
838 {BRCMS_SROM_PA5GHW2A0, 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 2,
839 0xffff},
840 {BRCMS_SROM_PA5GHW3A0, 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 3,
841 0xffff},
842 {BRCMS_SROM_MAXP2GA0, 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0x00ff}, 560 {BRCMS_SROM_MAXP2GA0, 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0x00ff},
843 {BRCMS_SROM_ITT2GA0, 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0xff00}, 561 {BRCMS_SROM_ITT2GA0, 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0xff00},
844 {BRCMS_SROM_ITT5GA0, 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0xff00}, 562 {BRCMS_SROM_ITT5GA0, 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0xff00},
@@ -868,24 +586,17 @@ static const struct brcms_sromvar perpath_pci_sromvars[] = {
868 * shared between devices. */ 586 * shared between devices. */
869static u8 brcms_srom_crc8_table[CRC8_TABLE_SIZE]; 587static u8 brcms_srom_crc8_table[CRC8_TABLE_SIZE];
870 588
871static u16 __iomem * 589static u8 __iomem *
872srom_window_address(struct si_pub *sih, u8 __iomem *curmap) 590srom_window_address(struct si_pub *sih, u8 __iomem *curmap)
873{ 591{
874 if (sih->ccrev < 32) 592 if (sih->ccrev < 32)
875 return (u16 __iomem *)(curmap + PCI_BAR0_SPROM_OFFSET); 593 return curmap + PCI_BAR0_SPROM_OFFSET;
876 if (sih->cccaps & CC_CAP_SROM) 594 if (sih->cccaps & CC_CAP_SROM)
877 return (u16 __iomem *) 595 return curmap + PCI_16KB0_CCREGS_OFFSET + CC_SROM_OTP;
878 (curmap + PCI_16KB0_CCREGS_OFFSET + CC_SROM_OTP);
879 596
880 return NULL; 597 return NULL;
881} 598}
882 599
883/* Parse SROM and create name=value pairs. 'srom' points to
884 * the SROM word array. 'off' specifies the offset of the
885 * first word 'srom' points to, which should be either 0 or
886 * SROM3_SWRG_OFF (full SROM or software region).
887 */
888
889static uint mask_shift(u16 mask) 600static uint mask_shift(u16 mask)
890{ 601{
891 uint i; 602 uint i;
@@ -906,18 +617,16 @@ static uint mask_width(u16 mask)
906 return 0; 617 return 0;
907} 618}
908 619
909static inline void ltoh16_buf(u16 *buf, unsigned int size) 620static inline void le16_to_cpu_buf(u16 *buf, uint nwords)
910{ 621{
911 size /= 2; 622 while (nwords--)
912 while (size--) 623 *(buf + nwords) = le16_to_cpu(*(__le16 *)(buf + nwords));
913 *(buf + size) = le16_to_cpu(*(__le16 *)(buf + size));
914} 624}
915 625
916static inline void htol16_buf(u16 *buf, unsigned int size) 626static inline void cpu_to_le16_buf(u16 *buf, uint nwords)
917{ 627{
918 size /= 2; 628 while (nwords--)
919 while (size--) 629 *(__le16 *)(buf + nwords) = cpu_to_le16(*(buf + nwords));
920 *(__le16 *)(buf + size) = cpu_to_le16(*(buf + size));
921} 630}
922 631
923/* 632/*
@@ -929,11 +638,14 @@ _initvars_srom_pci(u8 sromrev, u16 *srom, struct list_head *var_list)
929 struct brcms_srom_list_head *entry; 638 struct brcms_srom_list_head *entry;
930 enum brcms_srom_id id; 639 enum brcms_srom_id id;
931 u16 w; 640 u16 w;
932 u32 val; 641 u32 val = 0;
933 const struct brcms_sromvar *srv; 642 const struct brcms_sromvar *srv;
934 uint width; 643 uint width;
935 uint flags; 644 uint flags;
936 u32 sr = (1 << sromrev); 645 u32 sr = (1 << sromrev);
646 uint p;
647 uint pb = SROM8_PATH0;
648 const uint psz = SROM8_PATH1 - SROM8_PATH0;
937 649
938 /* first store the srom revision */ 650 /* first store the srom revision */
939 entry = kzalloc(sizeof(struct brcms_srom_list_head), GFP_KERNEL); 651 entry = kzalloc(sizeof(struct brcms_srom_list_head), GFP_KERNEL);
@@ -1031,47 +743,34 @@ _initvars_srom_pci(u8 sromrev, u16 *srom, struct list_head *var_list)
1031 list_add(&entry->var_list, var_list); 743 list_add(&entry->var_list, var_list);
1032 } 744 }
1033 745
1034 if (sromrev >= 4) { 746 for (p = 0; p < MAX_PATH_SROM; p++) {
1035 /* Do per-path variables */ 747 for (srv = perpath_pci_sromvars;
1036 uint p, pb, psz; 748 srv->varid != BRCMS_SROM_NULL; srv++) {
1037 749 if ((srv->revmask & sr) == 0)
1038 if (sromrev >= 8) { 750 continue;
1039 pb = SROM8_PATH0;
1040 psz = SROM8_PATH1 - SROM8_PATH0;
1041 } else {
1042 pb = SROM4_PATH0;
1043 psz = SROM4_PATH1 - SROM4_PATH0;
1044 }
1045
1046 for (p = 0; p < MAX_PATH_SROM; p++) {
1047 for (srv = perpath_pci_sromvars;
1048 srv->varid != BRCMS_SROM_NULL; srv++) {
1049 if ((srv->revmask & sr) == 0)
1050 continue;
1051 751
1052 if (srv->flags & SRFL_NOVAR) 752 if (srv->flags & SRFL_NOVAR)
1053 continue; 753 continue;
1054 754
1055 w = srom[pb + srv->off]; 755 w = srom[pb + srv->off];
1056 val = (w & srv->mask) >> mask_shift(srv->mask); 756 val = (w & srv->mask) >> mask_shift(srv->mask);
1057 width = mask_width(srv->mask); 757 width = mask_width(srv->mask);
1058 758
1059 /* Cheating: no per-path var is more than 759 /* Cheating: no per-path var is more than
1060 * 1 word */ 760 * 1 word */
1061 if ((srv->flags & SRFL_NOFFS) 761 if ((srv->flags & SRFL_NOFFS)
1062 && ((int)val == (1 << width) - 1)) 762 && ((int)val == (1 << width) - 1))
1063 continue; 763 continue;
1064 764
1065 entry = 765 entry =
1066 kzalloc(sizeof(struct brcms_srom_list_head), 766 kzalloc(sizeof(struct brcms_srom_list_head),
1067 GFP_KERNEL); 767 GFP_KERNEL);
1068 entry->varid = srv->varid+p; 768 entry->varid = srv->varid+p;
1069 entry->var_type = BRCMS_SROM_UNUMBER; 769 entry->var_type = BRCMS_SROM_UNUMBER;
1070 entry->uval = val; 770 entry->uval = val;
1071 list_add(&entry->var_list, var_list); 771 list_add(&entry->var_list, var_list);
1072 }
1073 pb += psz;
1074 } 772 }
773 pb += psz;
1075 } 774 }
1076} 775}
1077 776
@@ -1080,41 +779,38 @@ _initvars_srom_pci(u8 sromrev, u16 *srom, struct list_head *var_list)
1080 * Return 0 on success, nonzero on error. 779 * Return 0 on success, nonzero on error.
1081 */ 780 */
1082static int 781static int
1083sprom_read_pci(struct si_pub *sih, u16 __iomem *sprom, uint wordoff, 782sprom_read_pci(struct si_pub *sih, u8 __iomem *sprom, uint wordoff,
1084 u16 *buf, uint nwords, bool check_crc) 783 u16 *buf, uint nwords, bool check_crc)
1085{ 784{
1086 int err = 0; 785 int err = 0;
1087 uint i; 786 uint i;
787 u8 *bbuf = (u8 *)buf; /* byte buffer */
788 uint nbytes = nwords << 1;
1088 789
1089 /* read the sprom */ 790 /* read the sprom in bytes */
1090 for (i = 0; i < nwords; i++) 791 for (i = 0; i < nbytes; i++)
1091 buf[i] = R_REG(&sprom[wordoff + i]); 792 bbuf[i] = readb(sprom+i);
1092
1093 if (check_crc) {
1094 793
1095 if (buf[0] == 0xffff) 794 if (buf[0] == 0xffff)
1096 /* 795 /*
1097 * The hardware thinks that an srom that starts with 796 * The hardware thinks that an srom that starts with
1098 * 0xffff is blank, regardless of the rest of the 797 * 0xffff is blank, regardless of the rest of the
1099 * content, so declare it bad. 798 * content, so declare it bad.
1100 */ 799 */
1101 return -ENODATA; 800 return -ENODATA;
1102
1103 /* fixup the endianness so crc8 will pass */
1104 htol16_buf(buf, nwords * 2);
1105 if (crc8(brcms_srom_crc8_table, (u8 *) buf, nwords * 2,
1106 CRC8_INIT_VALUE) !=
1107 CRC8_GOOD_VALUE(brcms_srom_crc8_table))
1108 /* DBG only pci always read srom4 first, then srom8/9 */
1109 err = -EIO;
1110 801
802 if (check_crc &&
803 crc8(brcms_srom_crc8_table, bbuf, nbytes, CRC8_INIT_VALUE) !=
804 CRC8_GOOD_VALUE(brcms_srom_crc8_table))
805 err = -EIO;
806 else
1111 /* now correct the endianness of the byte array */ 807 /* now correct the endianness of the byte array */
1112 ltoh16_buf(buf, nwords * 2); 808 le16_to_cpu_buf(buf, nwords);
1113 } 809
1114 return err; 810 return err;
1115} 811}
1116 812
1117static int otp_read_pci(struct si_pub *sih, u16 *buf, uint bufsz) 813static int otp_read_pci(struct si_pub *sih, u16 *buf, uint nwords)
1118{ 814{
1119 u8 *otp; 815 u8 *otp;
1120 uint sz = OTP_SZ_MAX / 2; /* size in words */ 816 uint sz = OTP_SZ_MAX / 2; /* size in words */
@@ -1126,7 +822,8 @@ static int otp_read_pci(struct si_pub *sih, u16 *buf, uint bufsz)
1126 822
1127 err = otp_read_region(sih, OTP_HW_RGN, (u16 *) otp, &sz); 823 err = otp_read_region(sih, OTP_HW_RGN, (u16 *) otp, &sz);
1128 824
1129 memcpy(buf, otp, bufsz); 825 sz = min_t(uint, sz, nwords);
826 memcpy(buf, otp, sz * 2);
1130 827
1131 kfree(otp); 828 kfree(otp);
1132 829
@@ -1139,13 +836,13 @@ static int otp_read_pci(struct si_pub *sih, u16 *buf, uint bufsz)
1139 return -ENODATA; 836 return -ENODATA;
1140 837
1141 /* fixup the endianness so crc8 will pass */ 838 /* fixup the endianness so crc8 will pass */
1142 htol16_buf(buf, bufsz); 839 cpu_to_le16_buf(buf, sz);
1143 if (crc8(brcms_srom_crc8_table, (u8 *) buf, SROM4_WORDS * 2, 840 if (crc8(brcms_srom_crc8_table, (u8 *) buf, sz * 2,
1144 CRC8_INIT_VALUE) != CRC8_GOOD_VALUE(brcms_srom_crc8_table)) 841 CRC8_INIT_VALUE) != CRC8_GOOD_VALUE(brcms_srom_crc8_table))
1145 err = -EIO; 842 err = -EIO;
1146 843 else
1147 /* now correct the endianness of the byte array */ 844 /* now correct the endianness of the byte array */
1148 ltoh16_buf(buf, bufsz); 845 le16_to_cpu_buf(buf, sz);
1149 846
1150 return err; 847 return err;
1151} 848}
@@ -1157,7 +854,7 @@ static int otp_read_pci(struct si_pub *sih, u16 *buf, uint bufsz)
1157static int initvars_srom_pci(struct si_pub *sih, void __iomem *curmap) 854static int initvars_srom_pci(struct si_pub *sih, void __iomem *curmap)
1158{ 855{
1159 u16 *srom; 856 u16 *srom;
1160 u16 __iomem *sromwindow; 857 u8 __iomem *sromwindow;
1161 u8 sromrev = 0; 858 u8 sromrev = 0;
1162 u32 sr; 859 u32 sr;
1163 int err = 0; 860 int err = 0;
@@ -1173,29 +870,16 @@ static int initvars_srom_pci(struct si_pub *sih, void __iomem *curmap)
1173 870
1174 crc8_populate_lsb(brcms_srom_crc8_table, SROM_CRC8_POLY); 871 crc8_populate_lsb(brcms_srom_crc8_table, SROM_CRC8_POLY);
1175 if (ai_is_sprom_available(sih)) { 872 if (ai_is_sprom_available(sih)) {
1176 err = sprom_read_pci(sih, sromwindow, 0, srom, SROM_WORDS, 873 err = sprom_read_pci(sih, sromwindow, 0, srom,
1177 true); 874 SROM4_WORDS, true);
1178 875
1179 if ((srom[SROM4_SIGN] == SROM4_SIGNATURE) || 876 if (err == 0)
1180 (((sih->buscoretype == PCIE_CORE_ID) 877 /* srom read and passed crc */
1181 && (sih->buscorerev >= 6))
1182 || ((sih->buscoretype == PCI_CORE_ID)
1183 && (sih->buscorerev >= 0xe)))) {
1184 /* sromrev >= 4, read more */
1185 err = sprom_read_pci(sih, sromwindow, 0, srom,
1186 SROM4_WORDS, true);
1187 sromrev = srom[SROM4_CRCREV] & 0xff;
1188 } else if (err == 0) {
1189 /* srom is good and is rev < 4 */
1190 /* top word of sprom contains version and crc8 */ 878 /* top word of sprom contains version and crc8 */
1191 sromrev = srom[SROM_CRCREV] & 0xff; 879 sromrev = srom[SROM4_CRCREV] & 0xff;
1192 /* bcm4401 sroms misprogrammed */
1193 if (sromrev == 0x10)
1194 sromrev = 1;
1195 }
1196 } else { 880 } else {
1197 /* Use OTP if SPROM not available */ 881 /* Use OTP if SPROM not available */
1198 err = otp_read_pci(sih, srom, SROM_MAX); 882 err = otp_read_pci(sih, srom, SROM4_WORDS);
1199 if (err == 0) 883 if (err == 0)
1200 /* OTP only contain SROM rev8/rev9 for now */ 884 /* OTP only contain SROM rev8/rev9 for now */
1201 sromrev = srom[SROM4_CRCREV] & 0xff; 885 sromrev = srom[SROM4_CRCREV] & 0xff;
@@ -1208,10 +892,9 @@ static int initvars_srom_pci(struct si_pub *sih, void __iomem *curmap)
1208 sr = 1 << sromrev; 892 sr = 1 << sromrev;
1209 893
1210 /* 894 /*
1211 * srom version check: Current valid versions: 1, 2, 3, 4, 5, 8, 895 * srom version check: Current valid versions: 8, 9
1212 * 9
1213 */ 896 */
1214 if ((sr & 0x33e) == 0) { 897 if ((sr & 0x300) == 0) {
1215 err = -EINVAL; 898 err = -EINVAL;
1216 goto errout; 899 goto errout;
1217 } 900 }
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/srom.h b/drivers/net/wireless/brcm80211/brcmsmac/srom.h
index 708c43ff51cc..c81df9798e50 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/srom.h
+++ b/drivers/net/wireless/brcm80211/brcmsmac/srom.h
@@ -26,9 +26,4 @@ extern void srom_free_vars(struct si_pub *sih);
26extern int srom_read(struct si_pub *sih, uint bus, void *curmap, 26extern int srom_read(struct si_pub *sih, uint bus, void *curmap,
27 uint byteoff, uint nbytes, u16 *buf, bool check_crc); 27 uint byteoff, uint nbytes, u16 *buf, bool check_crc);
28 28
29/* parse standard PCMCIA cis, normally used by SB/PCMCIA/SDIO/SPI/OTP
30 * and extract from it into name=value pairs
31 */
32extern int srom_parsecis(u8 **pcis, uint ciscnt,
33 char **vars, uint *count);
34#endif /* _BRCM_SROM_H_ */ 29#endif /* _BRCM_SROM_H_ */
diff --git a/drivers/net/wireless/brcm80211/brcmutil/utils.c b/drivers/net/wireless/brcm80211/brcmutil/utils.c
index f27c48910827..b7537f70a795 100644
--- a/drivers/net/wireless/brcm80211/brcmutil/utils.c
+++ b/drivers/net/wireless/brcm80211/brcmutil/utils.c
@@ -16,6 +16,7 @@
16 16
17#include <linux/netdevice.h> 17#include <linux/netdevice.h>
18#include <linux/module.h> 18#include <linux/module.h>
19
19#include <brcmu_utils.h> 20#include <brcmu_utils.h>
20 21
21MODULE_AUTHOR("Broadcom Corporation"); 22MODULE_AUTHOR("Broadcom Corporation");
@@ -40,74 +41,20 @@ EXPORT_SYMBOL(brcmu_pkt_buf_get_skb);
40/* Free the driver packet. Free the tag if present */ 41/* Free the driver packet. Free the tag if present */
41void brcmu_pkt_buf_free_skb(struct sk_buff *skb) 42void brcmu_pkt_buf_free_skb(struct sk_buff *skb)
42{ 43{
43 struct sk_buff *nskb; 44 WARN_ON(skb->next);
44 int nest = 0; 45 if (skb->destructor)
45 46 /* cannot kfree_skb() on hard IRQ (net/core/skbuff.c) if
46 /* perversion: we use skb->next to chain multi-skb packets */ 47 * destructor exists
47 while (skb) { 48 */
48 nskb = skb->next; 49 dev_kfree_skb_any(skb);
49 skb->next = NULL; 50 else
50 51 /* can free immediately (even in_irq()) if destructor
51 if (skb->destructor) 52 * does not exist
52 /* cannot kfree_skb() on hard IRQ (net/core/skbuff.c) if 53 */
53 * destructor exists 54 dev_kfree_skb(skb);
54 */
55 dev_kfree_skb_any(skb);
56 else
57 /* can free immediately (even in_irq()) if destructor
58 * does not exist
59 */
60 dev_kfree_skb(skb);
61
62 nest++;
63 skb = nskb;
64 }
65} 55}
66EXPORT_SYMBOL(brcmu_pkt_buf_free_skb); 56EXPORT_SYMBOL(brcmu_pkt_buf_free_skb);
67 57
68
69/* copy a buffer into a pkt buffer chain */
70uint brcmu_pktfrombuf(struct sk_buff *p, uint offset, int len,
71 unsigned char *buf)
72{
73 uint n, ret = 0;
74
75 /* skip 'offset' bytes */
76 for (; p && offset; p = p->next) {
77 if (offset < (uint) (p->len))
78 break;
79 offset -= p->len;
80 }
81
82 if (!p)
83 return 0;
84
85 /* copy the data */
86 for (; p && len; p = p->next) {
87 n = min((uint) (p->len) - offset, (uint) len);
88 memcpy(p->data + offset, buf, n);
89 buf += n;
90 len -= n;
91 ret += n;
92 offset = 0;
93 }
94
95 return ret;
96}
97EXPORT_SYMBOL(brcmu_pktfrombuf);
98
99/* return total length of buffer chain */
100uint brcmu_pkttotlen(struct sk_buff *p)
101{
102 uint total;
103
104 total = 0;
105 for (; p; p = p->next)
106 total += p->len;
107 return total;
108}
109EXPORT_SYMBOL(brcmu_pkttotlen);
110
111/* 58/*
112 * osl multiple-precedence packet queue 59 * osl multiple-precedence packet queue
113 * hi_prec is always >= the number of the highest non-empty precedence 60 * hi_prec is always >= the number of the highest non-empty precedence
@@ -115,21 +62,13 @@ EXPORT_SYMBOL(brcmu_pkttotlen);
115struct sk_buff *brcmu_pktq_penq(struct pktq *pq, int prec, 62struct sk_buff *brcmu_pktq_penq(struct pktq *pq, int prec,
116 struct sk_buff *p) 63 struct sk_buff *p)
117{ 64{
118 struct pktq_prec *q; 65 struct sk_buff_head *q;
119 66
120 if (pktq_full(pq) || pktq_pfull(pq, prec)) 67 if (pktq_full(pq) || pktq_pfull(pq, prec))
121 return NULL; 68 return NULL;
122 69
123 q = &pq->q[prec]; 70 q = &pq->q[prec].skblist;
124 71 skb_queue_tail(q, p);
125 if (q->head)
126 q->tail->prev = p;
127 else
128 q->head = p;
129
130 q->tail = p;
131 q->len++;
132
133 pq->len++; 72 pq->len++;
134 73
135 if (pq->hi_prec < prec) 74 if (pq->hi_prec < prec)
@@ -142,20 +81,13 @@ EXPORT_SYMBOL(brcmu_pktq_penq);
142struct sk_buff *brcmu_pktq_penq_head(struct pktq *pq, int prec, 81struct sk_buff *brcmu_pktq_penq_head(struct pktq *pq, int prec,
143 struct sk_buff *p) 82 struct sk_buff *p)
144{ 83{
145 struct pktq_prec *q; 84 struct sk_buff_head *q;
146 85
147 if (pktq_full(pq) || pktq_pfull(pq, prec)) 86 if (pktq_full(pq) || pktq_pfull(pq, prec))
148 return NULL; 87 return NULL;
149 88
150 q = &pq->q[prec]; 89 q = &pq->q[prec].skblist;
151 90 skb_queue_head(q, p);
152 if (q->head == NULL)
153 q->tail = p;
154
155 p->prev = q->head;
156 q->head = p;
157 q->len++;
158
159 pq->len++; 91 pq->len++;
160 92
161 if (pq->hi_prec < prec) 93 if (pq->hi_prec < prec)
@@ -167,53 +99,30 @@ EXPORT_SYMBOL(brcmu_pktq_penq_head);
167 99
168struct sk_buff *brcmu_pktq_pdeq(struct pktq *pq, int prec) 100struct sk_buff *brcmu_pktq_pdeq(struct pktq *pq, int prec)
169{ 101{
170 struct pktq_prec *q; 102 struct sk_buff_head *q;
171 struct sk_buff *p; 103 struct sk_buff *p;
172 104
173 q = &pq->q[prec]; 105 q = &pq->q[prec].skblist;
174 106 p = skb_dequeue(q);
175 p = q->head;
176 if (p == NULL) 107 if (p == NULL)
177 return NULL; 108 return NULL;
178 109
179 q->head = p->prev;
180 if (q->head == NULL)
181 q->tail = NULL;
182
183 q->len--;
184
185 pq->len--; 110 pq->len--;
186
187 p->prev = NULL;
188
189 return p; 111 return p;
190} 112}
191EXPORT_SYMBOL(brcmu_pktq_pdeq); 113EXPORT_SYMBOL(brcmu_pktq_pdeq);
192 114
193struct sk_buff *brcmu_pktq_pdeq_tail(struct pktq *pq, int prec) 115struct sk_buff *brcmu_pktq_pdeq_tail(struct pktq *pq, int prec)
194{ 116{
195 struct pktq_prec *q; 117 struct sk_buff_head *q;
196 struct sk_buff *p, *prev; 118 struct sk_buff *p;
197
198 q = &pq->q[prec];
199 119
200 p = q->head; 120 q = &pq->q[prec].skblist;
121 p = skb_dequeue_tail(q);
201 if (p == NULL) 122 if (p == NULL)
202 return NULL; 123 return NULL;
203 124
204 for (prev = NULL; p != q->tail; p = p->prev)
205 prev = p;
206
207 if (prev)
208 prev->prev = NULL;
209 else
210 q->head = NULL;
211
212 q->tail = prev;
213 q->len--;
214
215 pq->len--; 125 pq->len--;
216
217 return p; 126 return p;
218} 127}
219EXPORT_SYMBOL(brcmu_pktq_pdeq_tail); 128EXPORT_SYMBOL(brcmu_pktq_pdeq_tail);
@@ -222,31 +131,17 @@ void
222brcmu_pktq_pflush(struct pktq *pq, int prec, bool dir, 131brcmu_pktq_pflush(struct pktq *pq, int prec, bool dir,
223 bool (*fn)(struct sk_buff *, void *), void *arg) 132 bool (*fn)(struct sk_buff *, void *), void *arg)
224{ 133{
225 struct pktq_prec *q; 134 struct sk_buff_head *q;
226 struct sk_buff *p, *prev = NULL; 135 struct sk_buff *p, *next;
227 136
228 q = &pq->q[prec]; 137 q = &pq->q[prec].skblist;
229 p = q->head; 138 skb_queue_walk_safe(q, p, next) {
230 while (p) {
231 if (fn == NULL || (*fn) (p, arg)) { 139 if (fn == NULL || (*fn) (p, arg)) {
232 bool head = (p == q->head); 140 skb_unlink(p, q);
233 if (head)
234 q->head = p->prev;
235 else
236 prev->prev = p->prev;
237 p->prev = NULL;
238 brcmu_pkt_buf_free_skb(p); 141 brcmu_pkt_buf_free_skb(p);
239 q->len--;
240 pq->len--; 142 pq->len--;
241 p = (head ? q->head : prev->prev);
242 } else {
243 prev = p;
244 p = p->prev;
245 } 143 }
246 } 144 }
247
248 if (q->head == NULL)
249 q->tail = NULL;
250} 145}
251EXPORT_SYMBOL(brcmu_pktq_pflush); 146EXPORT_SYMBOL(brcmu_pktq_pflush);
252 147
@@ -271,8 +166,10 @@ void brcmu_pktq_init(struct pktq *pq, int num_prec, int max_len)
271 166
272 pq->max = (u16) max_len; 167 pq->max = (u16) max_len;
273 168
274 for (prec = 0; prec < num_prec; prec++) 169 for (prec = 0; prec < num_prec; prec++) {
275 pq->q[prec].max = pq->max; 170 pq->q[prec].max = pq->max;
171 skb_queue_head_init(&pq->q[prec].skblist);
172 }
276} 173}
277EXPORT_SYMBOL(brcmu_pktq_init); 174EXPORT_SYMBOL(brcmu_pktq_init);
278 175
@@ -284,13 +181,13 @@ struct sk_buff *brcmu_pktq_peek_tail(struct pktq *pq, int *prec_out)
284 return NULL; 181 return NULL;
285 182
286 for (prec = 0; prec < pq->hi_prec; prec++) 183 for (prec = 0; prec < pq->hi_prec; prec++)
287 if (pq->q[prec].head) 184 if (!skb_queue_empty(&pq->q[prec].skblist))
288 break; 185 break;
289 186
290 if (prec_out) 187 if (prec_out)
291 *prec_out = prec; 188 *prec_out = prec;
292 189
293 return pq->q[prec].tail; 190 return skb_peek_tail(&pq->q[prec].skblist);
294} 191}
295EXPORT_SYMBOL(brcmu_pktq_peek_tail); 192EXPORT_SYMBOL(brcmu_pktq_peek_tail);
296 193
@@ -303,7 +200,7 @@ int brcmu_pktq_mlen(struct pktq *pq, uint prec_bmp)
303 200
304 for (prec = 0; prec <= pq->hi_prec; prec++) 201 for (prec = 0; prec <= pq->hi_prec; prec++)
305 if (prec_bmp & (1 << prec)) 202 if (prec_bmp & (1 << prec))
306 len += pq->q[prec].len; 203 len += pq->q[prec].skblist.qlen;
307 204
308 return len; 205 return len;
309} 206}
@@ -313,39 +210,32 @@ EXPORT_SYMBOL(brcmu_pktq_mlen);
313struct sk_buff *brcmu_pktq_mdeq(struct pktq *pq, uint prec_bmp, 210struct sk_buff *brcmu_pktq_mdeq(struct pktq *pq, uint prec_bmp,
314 int *prec_out) 211 int *prec_out)
315{ 212{
316 struct pktq_prec *q; 213 struct sk_buff_head *q;
317 struct sk_buff *p; 214 struct sk_buff *p;
318 int prec; 215 int prec;
319 216
320 if (pq->len == 0) 217 if (pq->len == 0)
321 return NULL; 218 return NULL;
322 219
323 while ((prec = pq->hi_prec) > 0 && pq->q[prec].head == NULL) 220 while ((prec = pq->hi_prec) > 0 &&
221 skb_queue_empty(&pq->q[prec].skblist))
324 pq->hi_prec--; 222 pq->hi_prec--;
325 223
326 while ((prec_bmp & (1 << prec)) == 0 || pq->q[prec].head == NULL) 224 while ((prec_bmp & (1 << prec)) == 0 ||
225 skb_queue_empty(&pq->q[prec].skblist))
327 if (prec-- == 0) 226 if (prec-- == 0)
328 return NULL; 227 return NULL;
329 228
330 q = &pq->q[prec]; 229 q = &pq->q[prec].skblist;
331 230 p = skb_dequeue(q);
332 p = q->head;
333 if (p == NULL) 231 if (p == NULL)
334 return NULL; 232 return NULL;
335 233
336 q->head = p->prev; 234 pq->len--;
337 if (q->head == NULL)
338 q->tail = NULL;
339
340 q->len--;
341 235
342 if (prec_out) 236 if (prec_out)
343 *prec_out = prec; 237 *prec_out = prec;
344 238
345 pq->len--;
346
347 p->prev = NULL;
348
349 return p; 239 return p;
350} 240}
351EXPORT_SYMBOL(brcmu_pktq_mdeq); 241EXPORT_SYMBOL(brcmu_pktq_mdeq);
@@ -364,23 +254,3 @@ void brcmu_prpkt(const char *msg, struct sk_buff *p0)
364} 254}
365EXPORT_SYMBOL(brcmu_prpkt); 255EXPORT_SYMBOL(brcmu_prpkt);
366#endif /* defined(BCMDBG) */ 256#endif /* defined(BCMDBG) */
367
368#if defined(BCMDBG)
369/*
370 * print bytes formatted as hex to a string. return the resulting
371 * string length
372 */
373int brcmu_format_hex(char *str, const void *bytes, int len)
374{
375 int i;
376 char *p = str;
377 const u8 *src = (const u8 *)bytes;
378
379 for (i = 0; i < len; i++) {
380 p += snprintf(p, 3, "%02X", *src);
381 src++;
382 }
383 return (int)(p - str);
384}
385EXPORT_SYMBOL(brcmu_format_hex);
386#endif /* defined(BCMDBG) */
diff --git a/drivers/net/wireless/brcm80211/include/brcmu_utils.h b/drivers/net/wireless/brcm80211/include/brcmu_utils.h
index 7d0f46e0eb95..ad249a0b4730 100644
--- a/drivers/net/wireless/brcm80211/include/brcmu_utils.h
+++ b/drivers/net/wireless/brcm80211/include/brcmu_utils.h
@@ -65,9 +65,7 @@
65#define ETHER_ADDR_STR_LEN 18 65#define ETHER_ADDR_STR_LEN 18
66 66
67struct pktq_prec { 67struct pktq_prec {
68 struct sk_buff *head; /* first packet to dequeue */ 68 struct sk_buff_head skblist;
69 struct sk_buff *tail; /* last packet to dequeue */
70 u16 len; /* number of queued packets */
71 u16 max; /* maximum number of queued packets */ 69 u16 max; /* maximum number of queued packets */
72}; 70};
73 71
@@ -88,32 +86,32 @@ struct pktq {
88 86
89static inline int pktq_plen(struct pktq *pq, int prec) 87static inline int pktq_plen(struct pktq *pq, int prec)
90{ 88{
91 return pq->q[prec].len; 89 return pq->q[prec].skblist.qlen;
92} 90}
93 91
94static inline int pktq_pavail(struct pktq *pq, int prec) 92static inline int pktq_pavail(struct pktq *pq, int prec)
95{ 93{
96 return pq->q[prec].max - pq->q[prec].len; 94 return pq->q[prec].max - pq->q[prec].skblist.qlen;
97} 95}
98 96
99static inline bool pktq_pfull(struct pktq *pq, int prec) 97static inline bool pktq_pfull(struct pktq *pq, int prec)
100{ 98{
101 return pq->q[prec].len >= pq->q[prec].max; 99 return pq->q[prec].skblist.qlen >= pq->q[prec].max;
102} 100}
103 101
104static inline bool pktq_pempty(struct pktq *pq, int prec) 102static inline bool pktq_pempty(struct pktq *pq, int prec)
105{ 103{
106 return pq->q[prec].len == 0; 104 return skb_queue_empty(&pq->q[prec].skblist);
107} 105}
108 106
109static inline struct sk_buff *pktq_ppeek(struct pktq *pq, int prec) 107static inline struct sk_buff *pktq_ppeek(struct pktq *pq, int prec)
110{ 108{
111 return pq->q[prec].head; 109 return skb_peek(&pq->q[prec].skblist);
112} 110}
113 111
114static inline struct sk_buff *pktq_ppeek_tail(struct pktq *pq, int prec) 112static inline struct sk_buff *pktq_ppeek_tail(struct pktq *pq, int prec)
115{ 113{
116 return pq->q[prec].tail; 114 return skb_peek_tail(&pq->q[prec].skblist);
117} 115}
118 116
119extern struct sk_buff *brcmu_pktq_penq(struct pktq *pq, int prec, 117extern struct sk_buff *brcmu_pktq_penq(struct pktq *pq, int prec,
@@ -172,24 +170,16 @@ extern void brcmu_pktq_flush(struct pktq *pq, bool dir,
172 bool (*fn)(struct sk_buff *, void *), void *arg); 170 bool (*fn)(struct sk_buff *, void *), void *arg);
173 171
174/* externs */ 172/* externs */
175/* packet */
176extern uint brcmu_pktfrombuf(struct sk_buff *p,
177 uint offset, int len, unsigned char *buf);
178extern uint brcmu_pkttotlen(struct sk_buff *p);
179
180/* ip address */ 173/* ip address */
181struct ipv4_addr; 174struct ipv4_addr;
182 175
176
177/* externs */
178/* format/print */
183#ifdef BCMDBG 179#ifdef BCMDBG
184extern void brcmu_prpkt(const char *msg, struct sk_buff *p0); 180extern void brcmu_prpkt(const char *msg, struct sk_buff *p0);
185#else 181#else
186#define brcmu_prpkt(a, b) 182#define brcmu_prpkt(a, b)
187#endif /* BCMDBG */ 183#endif /* BCMDBG */
188 184
189/* externs */
190/* format/print */
191#if defined(BCMDBG)
192extern int brcmu_format_hex(char *str, const void *bytes, int len);
193#endif
194
195#endif /* _BRCMU_UTILS_H_ */ 185#endif /* _BRCMU_UTILS_H_ */
diff --git a/drivers/net/wireless/brcm80211/include/defs.h b/drivers/net/wireless/brcm80211/include/defs.h
index 1e5f310af1e7..f0d8c04a9c8c 100644
--- a/drivers/net/wireless/brcm80211/include/defs.h
+++ b/drivers/net/wireless/brcm80211/include/defs.h
@@ -62,7 +62,6 @@
62 62
63#define WL_RADIO_SW_DISABLE (1<<0) 63#define WL_RADIO_SW_DISABLE (1<<0)
64#define WL_RADIO_HW_DISABLE (1<<1) 64#define WL_RADIO_HW_DISABLE (1<<1)
65#define WL_RADIO_MPC_DISABLE (1<<2)
66/* some countries don't support any channel */ 65/* some countries don't support any channel */
67#define WL_RADIO_COUNTRY_DISABLE (1<<3) 66#define WL_RADIO_COUNTRY_DISABLE (1<<3)
68 67
diff --git a/drivers/net/wireless/brcm80211/include/soc.h b/drivers/net/wireless/brcm80211/include/soc.h
index 4fcb956ad9e0..4e9b7e4827ea 100644
--- a/drivers/net/wireless/brcm80211/include/soc.h
+++ b/drivers/net/wireless/brcm80211/include/soc.h
@@ -77,8 +77,9 @@
77#define DMEMS_CORE_ID 0x835 /* SDR/DDR1 memory controller core */ 77#define DMEMS_CORE_ID 0x835 /* SDR/DDR1 memory controller core */
78#define DEF_SHIM_COMP 0x837 /* SHIM component in ubus/6362 */ 78#define DEF_SHIM_COMP 0x837 /* SHIM component in ubus/6362 */
79#define OOB_ROUTER_CORE_ID 0x367 /* OOB router core ID */ 79#define OOB_ROUTER_CORE_ID 0x367 /* OOB router core ID */
80/* Default component, in ai chips it maps all unused address ranges */ 80#define DEF_AI_COMP 0xfff /* Default component, in ai chips it
81#define DEF_AI_COMP 0xfff 81 * maps all unused address ranges
82 */
82 83
83/* Common core control flags */ 84/* Common core control flags */
84#define SICF_BIST_EN 0x8000 85#define SICF_BIST_EN 0x8000
@@ -87,4 +88,11 @@
87#define SICF_FGC 0x0002 88#define SICF_FGC 0x0002
88#define SICF_CLOCK_EN 0x0001 89#define SICF_CLOCK_EN 0x0001
89 90
91/* Common core status flags */
92#define SISF_BIST_DONE 0x8000
93#define SISF_BIST_ERROR 0x4000
94#define SISF_GATED_CLK 0x2000
95#define SISF_DMA64 0x1000
96#define SISF_CORE_BITS 0x0fff
97
90#endif /* _BRCM_SOC_H */ 98#endif /* _BRCM_SOC_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-07 11:50:26 -0500