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path: root/drivers/net/wireless/brcm80211/brcmsmac/srom.c
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Diffstat (limited to 'drivers/net/wireless/brcm80211/brcmsmac/srom.c')
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/srom.c469
1 files changed, 76 insertions, 393 deletions
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/srom.c b/drivers/net/wireless/brcm80211/brcmsmac/srom.c
index 99f791048e84..b6987ea9fc68 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/srom.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/srom.c
@@ -28,6 +28,7 @@
28#include "aiutils.h" 28#include "aiutils.h"
29#include "otp.h" 29#include "otp.h"
30#include "srom.h" 30#include "srom.h"
31#include "soc.h"
31 32
32/* 33/*
33 * SROM CRC8 polynomial value: 34 * SROM CRC8 polynomial value:
@@ -62,9 +63,6 @@
62#define SROM_MACHI_ET1 42 63#define SROM_MACHI_ET1 42
63#define SROM_MACMID_ET1 43 64#define SROM_MACMID_ET1 43
64#define SROM_MACLO_ET1 44 65#define SROM_MACLO_ET1 44
65#define SROM3_MACHI 37
66#define SROM3_MACMID 38
67#define SROM3_MACLO 39
68 66
69#define SROM_BXARSSI2G 40 67#define SROM_BXARSSI2G 40
70#define SROM_BXARSSI5G 41 68#define SROM_BXARSSI5G 41
@@ -101,7 +99,6 @@
101 99
102#define SROM_BFL 57 100#define SROM_BFL 57
103#define SROM_BFL2 28 101#define SROM_BFL2 28
104#define SROM3_BFL2 61
105 102
106#define SROM_AG10 58 103#define SROM_AG10 58
107 104
@@ -109,99 +106,16 @@
109 106
110#define SROM_OPO 60 107#define SROM_OPO 60
111 108
112#define SROM3_LEDDC 62
113
114#define SROM_CRCREV 63 109#define SROM_CRCREV 63
115 110
116/* SROM Rev 4: Reallocate the software part of the srom to accommodate
117 * MIMO features. It assumes up to two PCIE functions and 440 bytes
118 * of usable srom i.e. the usable storage in chips with OTP that
119 * implements hardware redundancy.
120 */
121
122#define SROM4_WORDS 220 111#define SROM4_WORDS 220
123 112
124#define SROM4_SIGN 32
125#define SROM4_SIGNATURE 0x5372
126
127#define SROM4_BREV 33
128
129#define SROM4_BFL0 34
130#define SROM4_BFL1 35
131#define SROM4_BFL2 36
132#define SROM4_BFL3 37
133#define SROM5_BFL0 37
134#define SROM5_BFL1 38
135#define SROM5_BFL2 39
136#define SROM5_BFL3 40
137
138#define SROM4_MACHI 38
139#define SROM4_MACMID 39
140#define SROM4_MACLO 40
141#define SROM5_MACHI 41
142#define SROM5_MACMID 42
143#define SROM5_MACLO 43
144
145#define SROM4_CCODE 41
146#define SROM4_REGREV 42
147#define SROM5_CCODE 34
148#define SROM5_REGREV 35
149
150#define SROM4_LEDBH10 43
151#define SROM4_LEDBH32 44
152#define SROM5_LEDBH10 59
153#define SROM5_LEDBH32 60
154
155#define SROM4_LEDDC 45
156#define SROM5_LEDDC 45
157
158#define SROM4_AA 46
159
160#define SROM4_AG10 47
161#define SROM4_AG32 48
162
163#define SROM4_TXPID2G 49
164#define SROM4_TXPID5G 51
165#define SROM4_TXPID5GL 53
166#define SROM4_TXPID5GH 55
167
168#define SROM4_TXRXC 61
169#define SROM4_TXCHAIN_MASK 0x000f 113#define SROM4_TXCHAIN_MASK 0x000f
170#define SROM4_TXCHAIN_SHIFT 0
171#define SROM4_RXCHAIN_MASK 0x00f0 114#define SROM4_RXCHAIN_MASK 0x00f0
172#define SROM4_RXCHAIN_SHIFT 4
173#define SROM4_SWITCH_MASK 0xff00 115#define SROM4_SWITCH_MASK 0xff00
174#define SROM4_SWITCH_SHIFT 8
175 116
176/* Per-path fields */ 117/* Per-path fields */
177#define MAX_PATH_SROM 4 118#define MAX_PATH_SROM 4
178#define SROM4_PATH0 64
179#define SROM4_PATH1 87
180#define SROM4_PATH2 110
181#define SROM4_PATH3 133
182
183#define SROM4_2G_ITT_MAXP 0
184#define SROM4_2G_PA 1
185#define SROM4_5G_ITT_MAXP 5
186#define SROM4_5GLH_MAXP 6
187#define SROM4_5G_PA 7
188#define SROM4_5GL_PA 11
189#define SROM4_5GH_PA 15
190
191/* All the miriad power offsets */
192#define SROM4_2G_CCKPO 156
193#define SROM4_2G_OFDMPO 157
194#define SROM4_5G_OFDMPO 159
195#define SROM4_5GL_OFDMPO 161
196#define SROM4_5GH_OFDMPO 163
197#define SROM4_2G_MCSPO 165
198#define SROM4_5G_MCSPO 173
199#define SROM4_5GL_MCSPO 181
200#define SROM4_5GH_MCSPO 189
201#define SROM4_CDDPO 197
202#define SROM4_STBCPO 198
203#define SROM4_BW40PO 199
204#define SROM4_BWDUPPO 200
205 119
206#define SROM4_CRCREV 219 120#define SROM4_CRCREV 219
207 121
@@ -424,103 +338,32 @@ struct brcms_varbuf {
424static const struct brcms_sromvar pci_sromvars[] = { 338static const struct brcms_sromvar pci_sromvars[] = {
425 {BRCMS_SROM_DEVID, 0xffffff00, SRFL_PRHEX | SRFL_NOVAR, PCI_F0DEVID, 339 {BRCMS_SROM_DEVID, 0xffffff00, SRFL_PRHEX | SRFL_NOVAR, PCI_F0DEVID,
426 0xffff}, 340 0xffff},
427 {BRCMS_SROM_BOARDREV, 0x0000000e, SRFL_PRHEX, SROM_AABREV,
428 SROM_BR_MASK},
429 {BRCMS_SROM_BOARDREV, 0x000000f0, SRFL_PRHEX, SROM4_BREV, 0xffff},
430 {BRCMS_SROM_BOARDREV, 0xffffff00, SRFL_PRHEX, SROM8_BREV, 0xffff}, 341 {BRCMS_SROM_BOARDREV, 0xffffff00, SRFL_PRHEX, SROM8_BREV, 0xffff},
431 {BRCMS_SROM_BOARDFLAGS, 0x00000002, SRFL_PRHEX, SROM_BFL, 0xffff},
432 {BRCMS_SROM_BOARDFLAGS, 0x00000004, SRFL_PRHEX | SRFL_MORE, SROM_BFL,
433 0xffff},
434 {BRCMS_SROM_CONT, 0, 0, SROM_BFL2, 0xffff},
435 {BRCMS_SROM_BOARDFLAGS, 0x00000008, SRFL_PRHEX | SRFL_MORE, SROM_BFL,
436 0xffff},
437 {BRCMS_SROM_CONT, 0, 0, SROM3_BFL2, 0xffff},
438 {BRCMS_SROM_BOARDFLAGS, 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL0,
439 0xffff},
440 {BRCMS_SROM_CONT, 0, 0, SROM4_BFL1, 0xffff},
441 {BRCMS_SROM_BOARDFLAGS, 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL0,
442 0xffff},
443 {BRCMS_SROM_CONT, 0, 0, SROM5_BFL1, 0xffff},
444 {BRCMS_SROM_BOARDFLAGS, 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL0, 342 {BRCMS_SROM_BOARDFLAGS, 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL0,
445 0xffff}, 343 0xffff},
446 {BRCMS_SROM_CONT, 0, 0, SROM8_BFL1, 0xffff}, 344 {BRCMS_SROM_CONT, 0, 0, SROM8_BFL1, 0xffff},
447 {BRCMS_SROM_BOARDFLAGS2, 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL2,
448 0xffff},
449 {BRCMS_SROM_CONT, 0, 0, SROM4_BFL3, 0xffff},
450 {BRCMS_SROM_BOARDFLAGS2, 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL2,
451 0xffff},
452 {BRCMS_SROM_CONT, 0, 0, SROM5_BFL3, 0xffff},
453 {BRCMS_SROM_BOARDFLAGS2, 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL2, 345 {BRCMS_SROM_BOARDFLAGS2, 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL2,
454 0xffff}, 346 0xffff},
455 {BRCMS_SROM_CONT, 0, 0, SROM8_BFL3, 0xffff}, 347 {BRCMS_SROM_CONT, 0, 0, SROM8_BFL3, 0xffff},
456 {BRCMS_SROM_BOARDTYPE, 0xfffffffc, SRFL_PRHEX, SROM_SSID, 0xffff}, 348 {BRCMS_SROM_BOARDTYPE, 0xfffffffc, SRFL_PRHEX, SROM_SSID, 0xffff},
457 {BRCMS_SROM_BOARDNUM, 0x00000006, 0, SROM_MACLO_IL0, 0xffff},
458 {BRCMS_SROM_BOARDNUM, 0x00000008, 0, SROM3_MACLO, 0xffff},
459 {BRCMS_SROM_BOARDNUM, 0x00000010, 0, SROM4_MACLO, 0xffff},
460 {BRCMS_SROM_BOARDNUM, 0x000000e0, 0, SROM5_MACLO, 0xffff},
461 {BRCMS_SROM_BOARDNUM, 0xffffff00, 0, SROM8_MACLO, 0xffff}, 349 {BRCMS_SROM_BOARDNUM, 0xffffff00, 0, SROM8_MACLO, 0xffff},
462 {BRCMS_SROM_CC, 0x00000002, 0, SROM_AABREV, SROM_CC_MASK},
463 {BRCMS_SROM_REGREV, 0x00000008, 0, SROM_OPO, 0xff00},
464 {BRCMS_SROM_REGREV, 0x00000010, 0, SROM4_REGREV, 0x00ff},
465 {BRCMS_SROM_REGREV, 0x000000e0, 0, SROM5_REGREV, 0x00ff},
466 {BRCMS_SROM_REGREV, 0xffffff00, 0, SROM8_REGREV, 0x00ff}, 350 {BRCMS_SROM_REGREV, 0xffffff00, 0, SROM8_REGREV, 0x00ff},
467 {BRCMS_SROM_LEDBH0, 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0x00ff},
468 {BRCMS_SROM_LEDBH1, 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0xff00},
469 {BRCMS_SROM_LEDBH2, 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0x00ff},
470 {BRCMS_SROM_LEDBH3, 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0xff00},
471 {BRCMS_SROM_LEDBH0, 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0x00ff},
472 {BRCMS_SROM_LEDBH1, 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0xff00},
473 {BRCMS_SROM_LEDBH2, 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0x00ff},
474 {BRCMS_SROM_LEDBH3, 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0xff00},
475 {BRCMS_SROM_LEDBH0, 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0x00ff},
476 {BRCMS_SROM_LEDBH1, 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0xff00},
477 {BRCMS_SROM_LEDBH2, 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0x00ff},
478 {BRCMS_SROM_LEDBH3, 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0xff00},
479 {BRCMS_SROM_LEDBH0, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0x00ff}, 351 {BRCMS_SROM_LEDBH0, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0x00ff},
480 {BRCMS_SROM_LEDBH1, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0xff00}, 352 {BRCMS_SROM_LEDBH1, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0xff00},
481 {BRCMS_SROM_LEDBH2, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0x00ff}, 353 {BRCMS_SROM_LEDBH2, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0x00ff},
482 {BRCMS_SROM_LEDBH3, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0xff00}, 354 {BRCMS_SROM_LEDBH3, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0xff00},
483 {BRCMS_SROM_PA0B0, 0x0000000e, SRFL_PRHEX, SROM_WL0PAB0, 0xffff},
484 {BRCMS_SROM_PA0B1, 0x0000000e, SRFL_PRHEX, SROM_WL0PAB1, 0xffff},
485 {BRCMS_SROM_PA0B2, 0x0000000e, SRFL_PRHEX, SROM_WL0PAB2, 0xffff},
486 {BRCMS_SROM_PA0ITSSIT, 0x0000000e, 0, SROM_ITT, 0x00ff},
487 {BRCMS_SROM_PA0MAXPWR, 0x0000000e, 0, SROM_WL10MAXP, 0x00ff},
488 {BRCMS_SROM_PA0B0, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB0, 0xffff}, 355 {BRCMS_SROM_PA0B0, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB0, 0xffff},
489 {BRCMS_SROM_PA0B1, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB1, 0xffff}, 356 {BRCMS_SROM_PA0B1, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB1, 0xffff},
490 {BRCMS_SROM_PA0B2, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB2, 0xffff}, 357 {BRCMS_SROM_PA0B2, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB2, 0xffff},
491 {BRCMS_SROM_PA0ITSSIT, 0xffffff00, 0, SROM8_W0_ITTMAXP, 0xff00}, 358 {BRCMS_SROM_PA0ITSSIT, 0xffffff00, 0, SROM8_W0_ITTMAXP, 0xff00},
492 {BRCMS_SROM_PA0MAXPWR, 0xffffff00, 0, SROM8_W0_ITTMAXP, 0x00ff}, 359 {BRCMS_SROM_PA0MAXPWR, 0xffffff00, 0, SROM8_W0_ITTMAXP, 0x00ff},
493 {BRCMS_SROM_OPO, 0x0000000c, 0, SROM_OPO, 0x00ff},
494 {BRCMS_SROM_OPO, 0xffffff00, 0, SROM8_2G_OFDMPO, 0x00ff}, 360 {BRCMS_SROM_OPO, 0xffffff00, 0, SROM8_2G_OFDMPO, 0x00ff},
495 {BRCMS_SROM_AA2G, 0x0000000e, 0, SROM_AABREV, SROM_AA0_MASK},
496 {BRCMS_SROM_AA2G, 0x000000f0, 0, SROM4_AA, 0x00ff},
497 {BRCMS_SROM_AA2G, 0xffffff00, 0, SROM8_AA, 0x00ff}, 361 {BRCMS_SROM_AA2G, 0xffffff00, 0, SROM8_AA, 0x00ff},
498 {BRCMS_SROM_AA5G, 0x0000000e, 0, SROM_AABREV, SROM_AA1_MASK},
499 {BRCMS_SROM_AA5G, 0x000000f0, 0, SROM4_AA, 0xff00},
500 {BRCMS_SROM_AA5G, 0xffffff00, 0, SROM8_AA, 0xff00}, 362 {BRCMS_SROM_AA5G, 0xffffff00, 0, SROM8_AA, 0xff00},
501 {BRCMS_SROM_AG0, 0x0000000e, 0, SROM_AG10, 0x00ff},
502 {BRCMS_SROM_AG1, 0x0000000e, 0, SROM_AG10, 0xff00},
503 {BRCMS_SROM_AG0, 0x000000f0, 0, SROM4_AG10, 0x00ff},
504 {BRCMS_SROM_AG1, 0x000000f0, 0, SROM4_AG10, 0xff00},
505 {BRCMS_SROM_AG2, 0x000000f0, 0, SROM4_AG32, 0x00ff},
506 {BRCMS_SROM_AG3, 0x000000f0, 0, SROM4_AG32, 0xff00},
507 {BRCMS_SROM_AG0, 0xffffff00, 0, SROM8_AG10, 0x00ff}, 363 {BRCMS_SROM_AG0, 0xffffff00, 0, SROM8_AG10, 0x00ff},
508 {BRCMS_SROM_AG1, 0xffffff00, 0, SROM8_AG10, 0xff00}, 364 {BRCMS_SROM_AG1, 0xffffff00, 0, SROM8_AG10, 0xff00},
509 {BRCMS_SROM_AG2, 0xffffff00, 0, SROM8_AG32, 0x00ff}, 365 {BRCMS_SROM_AG2, 0xffffff00, 0, SROM8_AG32, 0x00ff},
510 {BRCMS_SROM_AG3, 0xffffff00, 0, SROM8_AG32, 0xff00}, 366 {BRCMS_SROM_AG3, 0xffffff00, 0, SROM8_AG32, 0xff00},
511 {BRCMS_SROM_PA1B0, 0x0000000e, SRFL_PRHEX, SROM_WL1PAB0, 0xffff},
512 {BRCMS_SROM_PA1B1, 0x0000000e, SRFL_PRHEX, SROM_WL1PAB1, 0xffff},
513 {BRCMS_SROM_PA1B2, 0x0000000e, SRFL_PRHEX, SROM_WL1PAB2, 0xffff},
514 {BRCMS_SROM_PA1LOB0, 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB0, 0xffff},
515 {BRCMS_SROM_PA1LOB1, 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB1, 0xffff},
516 {BRCMS_SROM_PA1LOB2, 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB2, 0xffff},
517 {BRCMS_SROM_PA1HIB0, 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB0, 0xffff},
518 {BRCMS_SROM_PA1HIB1, 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB1, 0xffff},
519 {BRCMS_SROM_PA1HIB2, 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB2, 0xffff},
520 {BRCMS_SROM_PA1ITSSIT, 0x0000000e, 0, SROM_ITT, 0xff00},
521 {BRCMS_SROM_PA1MAXPWR, 0x0000000e, 0, SROM_WL10MAXP, 0xff00},
522 {BRCMS_SROM_PA1LOMAXPWR, 0x0000000c, 0, SROM_WL1LHMAXP, 0xff00},
523 {BRCMS_SROM_PA1HIMAXPWR, 0x0000000c, 0, SROM_WL1LHMAXP, 0x00ff},
524 {BRCMS_SROM_PA1B0, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0, 0xffff}, 367 {BRCMS_SROM_PA1B0, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0, 0xffff},
525 {BRCMS_SROM_PA1B1, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1, 0xffff}, 368 {BRCMS_SROM_PA1B1, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1, 0xffff},
526 {BRCMS_SROM_PA1B2, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2, 0xffff}, 369 {BRCMS_SROM_PA1B2, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2, 0xffff},
@@ -534,40 +377,20 @@ static const struct brcms_sromvar pci_sromvars[] = {
534 {BRCMS_SROM_PA1MAXPWR, 0xffffff00, 0, SROM8_W1_ITTMAXP, 0x00ff}, 377 {BRCMS_SROM_PA1MAXPWR, 0xffffff00, 0, SROM8_W1_ITTMAXP, 0x00ff},
535 {BRCMS_SROM_PA1LOMAXPWR, 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0xff00}, 378 {BRCMS_SROM_PA1LOMAXPWR, 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0xff00},
536 {BRCMS_SROM_PA1HIMAXPWR, 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0x00ff}, 379 {BRCMS_SROM_PA1HIMAXPWR, 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0x00ff},
537 {BRCMS_SROM_BXA2G, 0x00000008, 0, SROM_BXARSSI2G, 0x1800},
538 {BRCMS_SROM_RSSISAV2G, 0x00000008, 0, SROM_BXARSSI2G, 0x0700},
539 {BRCMS_SROM_RSSISMC2G, 0x00000008, 0, SROM_BXARSSI2G, 0x00f0},
540 {BRCMS_SROM_RSSISMF2G, 0x00000008, 0, SROM_BXARSSI2G, 0x000f},
541 {BRCMS_SROM_BXA2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x1800}, 380 {BRCMS_SROM_BXA2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x1800},
542 {BRCMS_SROM_RSSISAV2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x0700}, 381 {BRCMS_SROM_RSSISAV2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x0700},
543 {BRCMS_SROM_RSSISMC2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x00f0}, 382 {BRCMS_SROM_RSSISMC2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x00f0},
544 {BRCMS_SROM_RSSISMF2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x000f}, 383 {BRCMS_SROM_RSSISMF2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x000f},
545 {BRCMS_SROM_BXA5G, 0x00000008, 0, SROM_BXARSSI5G, 0x1800},
546 {BRCMS_SROM_RSSISAV5G, 0x00000008, 0, SROM_BXARSSI5G, 0x0700},
547 {BRCMS_SROM_RSSISMC5G, 0x00000008, 0, SROM_BXARSSI5G, 0x00f0},
548 {BRCMS_SROM_RSSISMF5G, 0x00000008, 0, SROM_BXARSSI5G, 0x000f},
549 {BRCMS_SROM_BXA5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x1800}, 384 {BRCMS_SROM_BXA5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x1800},
550 {BRCMS_SROM_RSSISAV5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x0700}, 385 {BRCMS_SROM_RSSISAV5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x0700},
551 {BRCMS_SROM_RSSISMC5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x00f0}, 386 {BRCMS_SROM_RSSISMC5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x00f0},
552 {BRCMS_SROM_RSSISMF5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x000f}, 387 {BRCMS_SROM_RSSISMF5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x000f},
553 {BRCMS_SROM_TRI2G, 0x00000008, 0, SROM_TRI52G, 0x00ff},
554 {BRCMS_SROM_TRI5G, 0x00000008, 0, SROM_TRI52G, 0xff00},
555 {BRCMS_SROM_TRI5GL, 0x00000008, 0, SROM_TRI5GHL, 0x00ff},
556 {BRCMS_SROM_TRI5GH, 0x00000008, 0, SROM_TRI5GHL, 0xff00},
557 {BRCMS_SROM_TRI2G, 0xffffff00, 0, SROM8_TRI52G, 0x00ff}, 388 {BRCMS_SROM_TRI2G, 0xffffff00, 0, SROM8_TRI52G, 0x00ff},
558 {BRCMS_SROM_TRI5G, 0xffffff00, 0, SROM8_TRI52G, 0xff00}, 389 {BRCMS_SROM_TRI5G, 0xffffff00, 0, SROM8_TRI52G, 0xff00},
559 {BRCMS_SROM_TRI5GL, 0xffffff00, 0, SROM8_TRI5GHL, 0x00ff}, 390 {BRCMS_SROM_TRI5GL, 0xffffff00, 0, SROM8_TRI5GHL, 0x00ff},
560 {BRCMS_SROM_TRI5GH, 0xffffff00, 0, SROM8_TRI5GHL, 0xff00}, 391 {BRCMS_SROM_TRI5GH, 0xffffff00, 0, SROM8_TRI5GHL, 0xff00},
561 {BRCMS_SROM_RXPO2G, 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0x00ff},
562 {BRCMS_SROM_RXPO5G, 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0xff00},
563 {BRCMS_SROM_RXPO2G, 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0x00ff}, 392 {BRCMS_SROM_RXPO2G, 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0x00ff},
564 {BRCMS_SROM_RXPO5G, 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0xff00}, 393 {BRCMS_SROM_RXPO5G, 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0xff00},
565 {BRCMS_SROM_TXCHAIN, 0x000000f0, SRFL_NOFFS, SROM4_TXRXC,
566 SROM4_TXCHAIN_MASK},
567 {BRCMS_SROM_RXCHAIN, 0x000000f0, SRFL_NOFFS, SROM4_TXRXC,
568 SROM4_RXCHAIN_MASK},
569 {BRCMS_SROM_ANTSWITCH, 0x000000f0, SRFL_NOFFS, SROM4_TXRXC,
570 SROM4_SWITCH_MASK},
571 {BRCMS_SROM_TXCHAIN, 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, 394 {BRCMS_SROM_TXCHAIN, 0xffffff00, SRFL_NOFFS, SROM8_TXRXC,
572 SROM4_TXCHAIN_MASK}, 395 SROM4_TXCHAIN_MASK},
573 {BRCMS_SROM_RXCHAIN, 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, 396 {BRCMS_SROM_RXCHAIN, 0xffffff00, SRFL_NOFFS, SROM8_TXRXC,
@@ -594,43 +417,11 @@ static const struct brcms_sromvar pci_sromvars[] = {
594 SROM8_FEM_ANTSWLUT_MASK}, 417 SROM8_FEM_ANTSWLUT_MASK},
595 {BRCMS_SROM_TEMPTHRESH, 0xffffff00, 0, SROM8_THERMAL, 0xff00}, 418 {BRCMS_SROM_TEMPTHRESH, 0xffffff00, 0, SROM8_THERMAL, 0xff00},
596 {BRCMS_SROM_TEMPOFFSET, 0xffffff00, 0, SROM8_THERMAL, 0x00ff}, 419 {BRCMS_SROM_TEMPOFFSET, 0xffffff00, 0, SROM8_THERMAL, 0x00ff},
597 {BRCMS_SROM_TXPID2GA0, 0x000000f0, 0, SROM4_TXPID2G, 0x00ff}, 420
598 {BRCMS_SROM_TXPID2GA1, 0x000000f0, 0, SROM4_TXPID2G, 0xff00},
599 {BRCMS_SROM_TXPID2GA2, 0x000000f0, 0, SROM4_TXPID2G + 1, 0x00ff},
600 {BRCMS_SROM_TXPID2GA3, 0x000000f0, 0, SROM4_TXPID2G + 1, 0xff00},
601 {BRCMS_SROM_TXPID5GA0, 0x000000f0, 0, SROM4_TXPID5G, 0x00ff},
602 {BRCMS_SROM_TXPID5GA1, 0x000000f0, 0, SROM4_TXPID5G, 0xff00},
603 {BRCMS_SROM_TXPID5GA2, 0x000000f0, 0, SROM4_TXPID5G + 1, 0x00ff},
604 {BRCMS_SROM_TXPID5GA3, 0x000000f0, 0, SROM4_TXPID5G + 1, 0xff00},
605 {BRCMS_SROM_TXPID5GLA0, 0x000000f0, 0, SROM4_TXPID5GL, 0x00ff},
606 {BRCMS_SROM_TXPID5GLA1, 0x000000f0, 0, SROM4_TXPID5GL, 0xff00},
607 {BRCMS_SROM_TXPID5GLA2, 0x000000f0, 0, SROM4_TXPID5GL + 1, 0x00ff},
608 {BRCMS_SROM_TXPID5GLA3, 0x000000f0, 0, SROM4_TXPID5GL + 1, 0xff00},
609 {BRCMS_SROM_TXPID5GHA0, 0x000000f0, 0, SROM4_TXPID5GH, 0x00ff},
610 {BRCMS_SROM_TXPID5GHA1, 0x000000f0, 0, SROM4_TXPID5GH, 0xff00},
611 {BRCMS_SROM_TXPID5GHA2, 0x000000f0, 0, SROM4_TXPID5GH + 1, 0x00ff},
612 {BRCMS_SROM_TXPID5GHA3, 0x000000f0, 0, SROM4_TXPID5GH + 1, 0xff00},
613
614 {BRCMS_SROM_CCODE, 0x0000000f, SRFL_CCODE, SROM_CCODE, 0xffff},
615 {BRCMS_SROM_CCODE, 0x00000010, SRFL_CCODE, SROM4_CCODE, 0xffff},
616 {BRCMS_SROM_CCODE, 0x000000e0, SRFL_CCODE, SROM5_CCODE, 0xffff},
617 {BRCMS_SROM_CCODE, 0xffffff00, SRFL_CCODE, SROM8_CCODE, 0xffff}, 421 {BRCMS_SROM_CCODE, 0xffffff00, SRFL_CCODE, SROM8_CCODE, 0xffff},
618 {BRCMS_SROM_MACADDR, 0xffffff00, SRFL_ETHADDR, SROM8_MACHI, 0xffff}, 422 {BRCMS_SROM_MACADDR, 0xffffff00, SRFL_ETHADDR, SROM8_MACHI, 0xffff},
619 {BRCMS_SROM_MACADDR, 0x000000e0, SRFL_ETHADDR, SROM5_MACHI, 0xffff},
620 {BRCMS_SROM_MACADDR, 0x00000010, SRFL_ETHADDR, SROM4_MACHI, 0xffff},
621 {BRCMS_SROM_MACADDR, 0x00000008, SRFL_ETHADDR, SROM3_MACHI, 0xffff},
622 {BRCMS_SROM_IL0MACADDR, 0x00000007, SRFL_ETHADDR, SROM_MACHI_IL0,
623 0xffff},
624 {BRCMS_SROM_ET1MACADDR, 0x00000007, SRFL_ETHADDR, SROM_MACHI_ET1,
625 0xffff},
626 {BRCMS_SROM_LEDDC, 0xffffff00, SRFL_NOFFS | SRFL_LEDDC, SROM8_LEDDC, 423 {BRCMS_SROM_LEDDC, 0xffffff00, SRFL_NOFFS | SRFL_LEDDC, SROM8_LEDDC,
627 0xffff}, 424 0xffff},
628 {BRCMS_SROM_LEDDC, 0x000000e0, SRFL_NOFFS | SRFL_LEDDC, SROM5_LEDDC,
629 0xffff},
630 {BRCMS_SROM_LEDDC, 0x00000010, SRFL_NOFFS | SRFL_LEDDC, SROM4_LEDDC,
631 0xffff},
632 {BRCMS_SROM_LEDDC, 0x00000008, SRFL_NOFFS | SRFL_LEDDC, SROM3_LEDDC,
633 0xffff},
634 {BRCMS_SROM_RAWTEMPSENSE, 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS, 425 {BRCMS_SROM_RAWTEMPSENSE, 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS,
635 0x01ff}, 426 0x01ff},
636 {BRCMS_SROM_MEASPOWER, 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS, 427 {BRCMS_SROM_MEASPOWER, 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS,
@@ -650,16 +441,7 @@ static const struct brcms_sromvar pci_sromvars[] = {
650 {BRCMS_SROM_PHYCAL_TEMPDELTA, 0xffffff00, 0, SROM8_PHYCAL_TEMPDELTA, 441 {BRCMS_SROM_PHYCAL_TEMPDELTA, 0xffffff00, 0, SROM8_PHYCAL_TEMPDELTA,
651 0x00ff}, 442 0x00ff},
652 443
653 {BRCMS_SROM_CCK2GPO, 0x000000f0, 0, SROM4_2G_CCKPO, 0xffff},
654 {BRCMS_SROM_CCK2GPO, 0x00000100, 0, SROM8_2G_CCKPO, 0xffff}, 444 {BRCMS_SROM_CCK2GPO, 0x00000100, 0, SROM8_2G_CCKPO, 0xffff},
655 {BRCMS_SROM_OFDM2GPO, 0x000000f0, SRFL_MORE, SROM4_2G_OFDMPO, 0xffff},
656 {BRCMS_SROM_CONT, 0, 0, SROM4_2G_OFDMPO + 1, 0xffff},
657 {BRCMS_SROM_OFDM5GPO, 0x000000f0, SRFL_MORE, SROM4_5G_OFDMPO, 0xffff},
658 {BRCMS_SROM_CONT, 0, 0, SROM4_5G_OFDMPO + 1, 0xffff},
659 {BRCMS_SROM_OFDM5GLPO, 0x000000f0, SRFL_MORE, SROM4_5GL_OFDMPO, 0xffff},
660 {BRCMS_SROM_CONT, 0, 0, SROM4_5GL_OFDMPO + 1, 0xffff},
661 {BRCMS_SROM_OFDM5GHPO, 0x000000f0, SRFL_MORE, SROM4_5GH_OFDMPO, 0xffff},
662 {BRCMS_SROM_CONT, 0, 0, SROM4_5GH_OFDMPO + 1, 0xffff},
663 {BRCMS_SROM_OFDM2GPO, 0x00000100, SRFL_MORE, SROM8_2G_OFDMPO, 0xffff}, 445 {BRCMS_SROM_OFDM2GPO, 0x00000100, SRFL_MORE, SROM8_2G_OFDMPO, 0xffff},
664 {BRCMS_SROM_CONT, 0, 0, SROM8_2G_OFDMPO + 1, 0xffff}, 446 {BRCMS_SROM_CONT, 0, 0, SROM8_2G_OFDMPO + 1, 0xffff},
665 {BRCMS_SROM_OFDM5GPO, 0x00000100, SRFL_MORE, SROM8_5G_OFDMPO, 0xffff}, 447 {BRCMS_SROM_OFDM5GPO, 0x00000100, SRFL_MORE, SROM8_5G_OFDMPO, 0xffff},
@@ -668,38 +450,6 @@ static const struct brcms_sromvar pci_sromvars[] = {
668 {BRCMS_SROM_CONT, 0, 0, SROM8_5GL_OFDMPO + 1, 0xffff}, 450 {BRCMS_SROM_CONT, 0, 0, SROM8_5GL_OFDMPO + 1, 0xffff},
669 {BRCMS_SROM_OFDM5GHPO, 0x00000100, SRFL_MORE, SROM8_5GH_OFDMPO, 0xffff}, 451 {BRCMS_SROM_OFDM5GHPO, 0x00000100, SRFL_MORE, SROM8_5GH_OFDMPO, 0xffff},
670 {BRCMS_SROM_CONT, 0, 0, SROM8_5GH_OFDMPO + 1, 0xffff}, 452 {BRCMS_SROM_CONT, 0, 0, SROM8_5GH_OFDMPO + 1, 0xffff},
671 {BRCMS_SROM_MCS2GPO0, 0x000000f0, 0, SROM4_2G_MCSPO, 0xffff},
672 {BRCMS_SROM_MCS2GPO1, 0x000000f0, 0, SROM4_2G_MCSPO + 1, 0xffff},
673 {BRCMS_SROM_MCS2GPO2, 0x000000f0, 0, SROM4_2G_MCSPO + 2, 0xffff},
674 {BRCMS_SROM_MCS2GPO3, 0x000000f0, 0, SROM4_2G_MCSPO + 3, 0xffff},
675 {BRCMS_SROM_MCS2GPO4, 0x000000f0, 0, SROM4_2G_MCSPO + 4, 0xffff},
676 {BRCMS_SROM_MCS2GPO5, 0x000000f0, 0, SROM4_2G_MCSPO + 5, 0xffff},
677 {BRCMS_SROM_MCS2GPO6, 0x000000f0, 0, SROM4_2G_MCSPO + 6, 0xffff},
678 {BRCMS_SROM_MCS2GPO7, 0x000000f0, 0, SROM4_2G_MCSPO + 7, 0xffff},
679 {BRCMS_SROM_MCS5GPO0, 0x000000f0, 0, SROM4_5G_MCSPO, 0xffff},
680 {BRCMS_SROM_MCS5GPO1, 0x000000f0, 0, SROM4_5G_MCSPO + 1, 0xffff},
681 {BRCMS_SROM_MCS5GPO2, 0x000000f0, 0, SROM4_5G_MCSPO + 2, 0xffff},
682 {BRCMS_SROM_MCS5GPO3, 0x000000f0, 0, SROM4_5G_MCSPO + 3, 0xffff},
683 {BRCMS_SROM_MCS5GPO4, 0x000000f0, 0, SROM4_5G_MCSPO + 4, 0xffff},
684 {BRCMS_SROM_MCS5GPO5, 0x000000f0, 0, SROM4_5G_MCSPO + 5, 0xffff},
685 {BRCMS_SROM_MCS5GPO6, 0x000000f0, 0, SROM4_5G_MCSPO + 6, 0xffff},
686 {BRCMS_SROM_MCS5GPO7, 0x000000f0, 0, SROM4_5G_MCSPO + 7, 0xffff},
687 {BRCMS_SROM_MCS5GLPO0, 0x000000f0, 0, SROM4_5GL_MCSPO, 0xffff},
688 {BRCMS_SROM_MCS5GLPO1, 0x000000f0, 0, SROM4_5GL_MCSPO + 1, 0xffff},
689 {BRCMS_SROM_MCS5GLPO2, 0x000000f0, 0, SROM4_5GL_MCSPO + 2, 0xffff},
690 {BRCMS_SROM_MCS5GLPO3, 0x000000f0, 0, SROM4_5GL_MCSPO + 3, 0xffff},
691 {BRCMS_SROM_MCS5GLPO4, 0x000000f0, 0, SROM4_5GL_MCSPO + 4, 0xffff},
692 {BRCMS_SROM_MCS5GLPO5, 0x000000f0, 0, SROM4_5GL_MCSPO + 5, 0xffff},
693 {BRCMS_SROM_MCS5GLPO6, 0x000000f0, 0, SROM4_5GL_MCSPO + 6, 0xffff},
694 {BRCMS_SROM_MCS5GLPO7, 0x000000f0, 0, SROM4_5GL_MCSPO + 7, 0xffff},
695 {BRCMS_SROM_MCS5GHPO0, 0x000000f0, 0, SROM4_5GH_MCSPO, 0xffff},
696 {BRCMS_SROM_MCS5GHPO1, 0x000000f0, 0, SROM4_5GH_MCSPO + 1, 0xffff},
697 {BRCMS_SROM_MCS5GHPO2, 0x000000f0, 0, SROM4_5GH_MCSPO + 2, 0xffff},
698 {BRCMS_SROM_MCS5GHPO3, 0x000000f0, 0, SROM4_5GH_MCSPO + 3, 0xffff},
699 {BRCMS_SROM_MCS5GHPO4, 0x000000f0, 0, SROM4_5GH_MCSPO + 4, 0xffff},
700 {BRCMS_SROM_MCS5GHPO5, 0x000000f0, 0, SROM4_5GH_MCSPO + 5, 0xffff},
701 {BRCMS_SROM_MCS5GHPO6, 0x000000f0, 0, SROM4_5GH_MCSPO + 6, 0xffff},
702 {BRCMS_SROM_MCS5GHPO7, 0x000000f0, 0, SROM4_5GH_MCSPO + 7, 0xffff},
703 {BRCMS_SROM_MCS2GPO0, 0x00000100, 0, SROM8_2G_MCSPO, 0xffff}, 453 {BRCMS_SROM_MCS2GPO0, 0x00000100, 0, SROM8_2G_MCSPO, 0xffff},
704 {BRCMS_SROM_MCS2GPO1, 0x00000100, 0, SROM8_2G_MCSPO + 1, 0xffff}, 454 {BRCMS_SROM_MCS2GPO1, 0x00000100, 0, SROM8_2G_MCSPO + 1, 0xffff},
705 {BRCMS_SROM_MCS2GPO2, 0x00000100, 0, SROM8_2G_MCSPO + 2, 0xffff}, 455 {BRCMS_SROM_MCS2GPO2, 0x00000100, 0, SROM8_2G_MCSPO + 2, 0xffff},
@@ -732,10 +482,6 @@ static const struct brcms_sromvar pci_sromvars[] = {
732 {BRCMS_SROM_MCS5GHPO5, 0x00000100, 0, SROM8_5GH_MCSPO + 5, 0xffff}, 482 {BRCMS_SROM_MCS5GHPO5, 0x00000100, 0, SROM8_5GH_MCSPO + 5, 0xffff},
733 {BRCMS_SROM_MCS5GHPO6, 0x00000100, 0, SROM8_5GH_MCSPO + 6, 0xffff}, 483 {BRCMS_SROM_MCS5GHPO6, 0x00000100, 0, SROM8_5GH_MCSPO + 6, 0xffff},
734 {BRCMS_SROM_MCS5GHPO7, 0x00000100, 0, SROM8_5GH_MCSPO + 7, 0xffff}, 484 {BRCMS_SROM_MCS5GHPO7, 0x00000100, 0, SROM8_5GH_MCSPO + 7, 0xffff},
735 {BRCMS_SROM_CDDPO, 0x000000f0, 0, SROM4_CDDPO, 0xffff},
736 {BRCMS_SROM_STBCPO, 0x000000f0, 0, SROM4_STBCPO, 0xffff},
737 {BRCMS_SROM_BW40PO, 0x000000f0, 0, SROM4_BW40PO, 0xffff},
738 {BRCMS_SROM_BWDUPPO, 0x000000f0, 0, SROM4_BWDUPPO, 0xffff},
739 {BRCMS_SROM_CDDPO, 0x00000100, 0, SROM8_CDDPO, 0xffff}, 485 {BRCMS_SROM_CDDPO, 0x00000100, 0, SROM8_CDDPO, 0xffff},
740 {BRCMS_SROM_STBCPO, 0x00000100, 0, SROM8_STBCPO, 0xffff}, 486 {BRCMS_SROM_STBCPO, 0x00000100, 0, SROM8_STBCPO, 0xffff},
741 {BRCMS_SROM_BW40PO, 0x00000100, 0, SROM8_BW40PO, 0xffff}, 487 {BRCMS_SROM_BW40PO, 0x00000100, 0, SROM8_BW40PO, 0xffff},
@@ -811,34 +557,6 @@ static const struct brcms_sromvar pci_sromvars[] = {
811}; 557};
812 558
813static const struct brcms_sromvar perpath_pci_sromvars[] = { 559static const struct brcms_sromvar perpath_pci_sromvars[] = {
814 {BRCMS_SROM_MAXP2GA0, 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0x00ff},
815 {BRCMS_SROM_ITT2GA0, 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0xff00},
816 {BRCMS_SROM_ITT5GA0, 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0xff00},
817 {BRCMS_SROM_PA2GW0A0, 0x000000f0, SRFL_PRHEX, SROM4_2G_PA, 0xffff},
818 {BRCMS_SROM_PA2GW1A0, 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 1, 0xffff},
819 {BRCMS_SROM_PA2GW2A0, 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 2, 0xffff},
820 {BRCMS_SROM_PA2GW3A0, 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 3, 0xffff},
821 {BRCMS_SROM_MAXP5GA0, 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0x00ff},
822 {BRCMS_SROM_MAXP5GHA0, 0x000000f0, 0, SROM4_5GLH_MAXP, 0x00ff},
823 {BRCMS_SROM_MAXP5GLA0, 0x000000f0, 0, SROM4_5GLH_MAXP, 0xff00},
824 {BRCMS_SROM_PA5GW0A0, 0x000000f0, SRFL_PRHEX, SROM4_5G_PA, 0xffff},
825 {BRCMS_SROM_PA5GW1A0, 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 1, 0xffff},
826 {BRCMS_SROM_PA5GW2A0, 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 2, 0xffff},
827 {BRCMS_SROM_PA5GW3A0, 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 3, 0xffff},
828 {BRCMS_SROM_PA5GLW0A0, 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA, 0xffff},
829 {BRCMS_SROM_PA5GLW1A0, 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 1,
830 0xffff},
831 {BRCMS_SROM_PA5GLW2A0, 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 2,
832 0xffff},
833 {BRCMS_SROM_PA5GLW3A0, 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 3,
834 0xffff},
835 {BRCMS_SROM_PA5GHW0A0, 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA, 0xffff},
836 {BRCMS_SROM_PA5GHW1A0, 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 1,
837 0xffff},
838 {BRCMS_SROM_PA5GHW2A0, 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 2,
839 0xffff},
840 {BRCMS_SROM_PA5GHW3A0, 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 3,
841 0xffff},
842 {BRCMS_SROM_MAXP2GA0, 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0x00ff}, 560 {BRCMS_SROM_MAXP2GA0, 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0x00ff},
843 {BRCMS_SROM_ITT2GA0, 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0xff00}, 561 {BRCMS_SROM_ITT2GA0, 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0xff00},
844 {BRCMS_SROM_ITT5GA0, 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0xff00}, 562 {BRCMS_SROM_ITT5GA0, 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0xff00},
@@ -868,24 +586,17 @@ static const struct brcms_sromvar perpath_pci_sromvars[] = {
868 * shared between devices. */ 586 * shared between devices. */
869static u8 brcms_srom_crc8_table[CRC8_TABLE_SIZE]; 587static u8 brcms_srom_crc8_table[CRC8_TABLE_SIZE];
870 588
871static u16 __iomem * 589static u8 __iomem *
872srom_window_address(struct si_pub *sih, u8 __iomem *curmap) 590srom_window_address(struct si_pub *sih, u8 __iomem *curmap)
873{ 591{
874 if (sih->ccrev < 32) 592 if (sih->ccrev < 32)
875 return (u16 __iomem *)(curmap + PCI_BAR0_SPROM_OFFSET); 593 return curmap + PCI_BAR0_SPROM_OFFSET;
876 if (sih->cccaps & CC_CAP_SROM) 594 if (sih->cccaps & CC_CAP_SROM)
877 return (u16 __iomem *) 595 return curmap + PCI_16KB0_CCREGS_OFFSET + CC_SROM_OTP;
878 (curmap + PCI_16KB0_CCREGS_OFFSET + CC_SROM_OTP);
879 596
880 return NULL; 597 return NULL;
881} 598}
882 599
883/* Parse SROM and create name=value pairs. 'srom' points to
884 * the SROM word array. 'off' specifies the offset of the
885 * first word 'srom' points to, which should be either 0 or
886 * SROM3_SWRG_OFF (full SROM or software region).
887 */
888
889static uint mask_shift(u16 mask) 600static uint mask_shift(u16 mask)
890{ 601{
891 uint i; 602 uint i;
@@ -906,18 +617,16 @@ static uint mask_width(u16 mask)
906 return 0; 617 return 0;
907} 618}
908 619
909static inline void ltoh16_buf(u16 *buf, unsigned int size) 620static inline void le16_to_cpu_buf(u16 *buf, uint nwords)
910{ 621{
911 size /= 2; 622 while (nwords--)
912 while (size--) 623 *(buf + nwords) = le16_to_cpu(*(__le16 *)(buf + nwords));
913 *(buf + size) = le16_to_cpu(*(__le16 *)(buf + size));
914} 624}
915 625
916static inline void htol16_buf(u16 *buf, unsigned int size) 626static inline void cpu_to_le16_buf(u16 *buf, uint nwords)
917{ 627{
918 size /= 2; 628 while (nwords--)
919 while (size--) 629 *(__le16 *)(buf + nwords) = cpu_to_le16(*(buf + nwords));
920 *(__le16 *)(buf + size) = cpu_to_le16(*(buf + size));
921} 630}
922 631
923/* 632/*
@@ -929,11 +638,14 @@ _initvars_srom_pci(u8 sromrev, u16 *srom, struct list_head *var_list)
929 struct brcms_srom_list_head *entry; 638 struct brcms_srom_list_head *entry;
930 enum brcms_srom_id id; 639 enum brcms_srom_id id;
931 u16 w; 640 u16 w;
932 u32 val; 641 u32 val = 0;
933 const struct brcms_sromvar *srv; 642 const struct brcms_sromvar *srv;
934 uint width; 643 uint width;
935 uint flags; 644 uint flags;
936 u32 sr = (1 << sromrev); 645 u32 sr = (1 << sromrev);
646 uint p;
647 uint pb = SROM8_PATH0;
648 const uint psz = SROM8_PATH1 - SROM8_PATH0;
937 649
938 /* first store the srom revision */ 650 /* first store the srom revision */
939 entry = kzalloc(sizeof(struct brcms_srom_list_head), GFP_KERNEL); 651 entry = kzalloc(sizeof(struct brcms_srom_list_head), GFP_KERNEL);
@@ -1031,47 +743,34 @@ _initvars_srom_pci(u8 sromrev, u16 *srom, struct list_head *var_list)
1031 list_add(&entry->var_list, var_list); 743 list_add(&entry->var_list, var_list);
1032 } 744 }
1033 745
1034 if (sromrev >= 4) { 746 for (p = 0; p < MAX_PATH_SROM; p++) {
1035 /* Do per-path variables */ 747 for (srv = perpath_pci_sromvars;
1036 uint p, pb, psz; 748 srv->varid != BRCMS_SROM_NULL; srv++) {
1037 749 if ((srv->revmask & sr) == 0)
1038 if (sromrev >= 8) { 750 continue;
1039 pb = SROM8_PATH0;
1040 psz = SROM8_PATH1 - SROM8_PATH0;
1041 } else {
1042 pb = SROM4_PATH0;
1043 psz = SROM4_PATH1 - SROM4_PATH0;
1044 }
1045
1046 for (p = 0; p < MAX_PATH_SROM; p++) {
1047 for (srv = perpath_pci_sromvars;
1048 srv->varid != BRCMS_SROM_NULL; srv++) {
1049 if ((srv->revmask & sr) == 0)
1050 continue;
1051 751
1052 if (srv->flags & SRFL_NOVAR) 752 if (srv->flags & SRFL_NOVAR)
1053 continue; 753 continue;
1054 754
1055 w = srom[pb + srv->off]; 755 w = srom[pb + srv->off];
1056 val = (w & srv->mask) >> mask_shift(srv->mask); 756 val = (w & srv->mask) >> mask_shift(srv->mask);
1057 width = mask_width(srv->mask); 757 width = mask_width(srv->mask);
1058 758
1059 /* Cheating: no per-path var is more than 759 /* Cheating: no per-path var is more than
1060 * 1 word */ 760 * 1 word */
1061 if ((srv->flags & SRFL_NOFFS) 761 if ((srv->flags & SRFL_NOFFS)
1062 && ((int)val == (1 << width) - 1)) 762 && ((int)val == (1 << width) - 1))
1063 continue; 763 continue;
1064 764
1065 entry = 765 entry =
1066 kzalloc(sizeof(struct brcms_srom_list_head), 766 kzalloc(sizeof(struct brcms_srom_list_head),
1067 GFP_KERNEL); 767 GFP_KERNEL);
1068 entry->varid = srv->varid+p; 768 entry->varid = srv->varid+p;
1069 entry->var_type = BRCMS_SROM_UNUMBER; 769 entry->var_type = BRCMS_SROM_UNUMBER;
1070 entry->uval = val; 770 entry->uval = val;
1071 list_add(&entry->var_list, var_list); 771 list_add(&entry->var_list, var_list);
1072 }
1073 pb += psz;
1074 } 772 }
773 pb += psz;
1075 } 774 }
1076} 775}
1077 776
@@ -1080,41 +779,38 @@ _initvars_srom_pci(u8 sromrev, u16 *srom, struct list_head *var_list)
1080 * Return 0 on success, nonzero on error. 779 * Return 0 on success, nonzero on error.
1081 */ 780 */
1082static int 781static int
1083sprom_read_pci(struct si_pub *sih, u16 __iomem *sprom, uint wordoff, 782sprom_read_pci(struct si_pub *sih, u8 __iomem *sprom, uint wordoff,
1084 u16 *buf, uint nwords, bool check_crc) 783 u16 *buf, uint nwords, bool check_crc)
1085{ 784{
1086 int err = 0; 785 int err = 0;
1087 uint i; 786 uint i;
787 u8 *bbuf = (u8 *)buf; /* byte buffer */
788 uint nbytes = nwords << 1;
1088 789
1089 /* read the sprom */ 790 /* read the sprom in bytes */
1090 for (i = 0; i < nwords; i++) 791 for (i = 0; i < nbytes; i++)
1091 buf[i] = R_REG(&sprom[wordoff + i]); 792 bbuf[i] = readb(sprom+i);
1092
1093 if (check_crc) {
1094 793
1095 if (buf[0] == 0xffff) 794 if (buf[0] == 0xffff)
1096 /* 795 /*
1097 * The hardware thinks that an srom that starts with 796 * The hardware thinks that an srom that starts with
1098 * 0xffff is blank, regardless of the rest of the 797 * 0xffff is blank, regardless of the rest of the
1099 * content, so declare it bad. 798 * content, so declare it bad.
1100 */ 799 */
1101 return -ENODATA; 800 return -ENODATA;
1102
1103 /* fixup the endianness so crc8 will pass */
1104 htol16_buf(buf, nwords * 2);
1105 if (crc8(brcms_srom_crc8_table, (u8 *) buf, nwords * 2,
1106 CRC8_INIT_VALUE) !=
1107 CRC8_GOOD_VALUE(brcms_srom_crc8_table))
1108 /* DBG only pci always read srom4 first, then srom8/9 */
1109 err = -EIO;
1110 801
802 if (check_crc &&
803 crc8(brcms_srom_crc8_table, bbuf, nbytes, CRC8_INIT_VALUE) !=
804 CRC8_GOOD_VALUE(brcms_srom_crc8_table))
805 err = -EIO;
806 else
1111 /* now correct the endianness of the byte array */ 807 /* now correct the endianness of the byte array */
1112 ltoh16_buf(buf, nwords * 2); 808 le16_to_cpu_buf(buf, nwords);
1113 } 809
1114 return err; 810 return err;
1115} 811}
1116 812
1117static int otp_read_pci(struct si_pub *sih, u16 *buf, uint bufsz) 813static int otp_read_pci(struct si_pub *sih, u16 *buf, uint nwords)
1118{ 814{
1119 u8 *otp; 815 u8 *otp;
1120 uint sz = OTP_SZ_MAX / 2; /* size in words */ 816 uint sz = OTP_SZ_MAX / 2; /* size in words */
@@ -1126,7 +822,8 @@ static int otp_read_pci(struct si_pub *sih, u16 *buf, uint bufsz)
1126 822
1127 err = otp_read_region(sih, OTP_HW_RGN, (u16 *) otp, &sz); 823 err = otp_read_region(sih, OTP_HW_RGN, (u16 *) otp, &sz);
1128 824
1129 memcpy(buf, otp, bufsz); 825 sz = min_t(uint, sz, nwords);
826 memcpy(buf, otp, sz * 2);
1130 827
1131 kfree(otp); 828 kfree(otp);
1132 829
@@ -1139,13 +836,13 @@ static int otp_read_pci(struct si_pub *sih, u16 *buf, uint bufsz)
1139 return -ENODATA; 836 return -ENODATA;
1140 837
1141 /* fixup the endianness so crc8 will pass */ 838 /* fixup the endianness so crc8 will pass */
1142 htol16_buf(buf, bufsz); 839 cpu_to_le16_buf(buf, sz);
1143 if (crc8(brcms_srom_crc8_table, (u8 *) buf, SROM4_WORDS * 2, 840 if (crc8(brcms_srom_crc8_table, (u8 *) buf, sz * 2,
1144 CRC8_INIT_VALUE) != CRC8_GOOD_VALUE(brcms_srom_crc8_table)) 841 CRC8_INIT_VALUE) != CRC8_GOOD_VALUE(brcms_srom_crc8_table))
1145 err = -EIO; 842 err = -EIO;
1146 843 else
1147 /* now correct the endianness of the byte array */ 844 /* now correct the endianness of the byte array */
1148 ltoh16_buf(buf, bufsz); 845 le16_to_cpu_buf(buf, sz);
1149 846
1150 return err; 847 return err;
1151} 848}
@@ -1157,7 +854,7 @@ static int otp_read_pci(struct si_pub *sih, u16 *buf, uint bufsz)
1157static int initvars_srom_pci(struct si_pub *sih, void __iomem *curmap) 854static int initvars_srom_pci(struct si_pub *sih, void __iomem *curmap)
1158{ 855{
1159 u16 *srom; 856 u16 *srom;
1160 u16 __iomem *sromwindow; 857 u8 __iomem *sromwindow;
1161 u8 sromrev = 0; 858 u8 sromrev = 0;
1162 u32 sr; 859 u32 sr;
1163 int err = 0; 860 int err = 0;
@@ -1173,29 +870,16 @@ static int initvars_srom_pci(struct si_pub *sih, void __iomem *curmap)
1173 870
1174 crc8_populate_lsb(brcms_srom_crc8_table, SROM_CRC8_POLY); 871 crc8_populate_lsb(brcms_srom_crc8_table, SROM_CRC8_POLY);
1175 if (ai_is_sprom_available(sih)) { 872 if (ai_is_sprom_available(sih)) {
1176 err = sprom_read_pci(sih, sromwindow, 0, srom, SROM_WORDS, 873 err = sprom_read_pci(sih, sromwindow, 0, srom,
1177 true); 874 SROM4_WORDS, true);
1178 875
1179 if ((srom[SROM4_SIGN] == SROM4_SIGNATURE) || 876 if (err == 0)
1180 (((sih->buscoretype == PCIE_CORE_ID) 877 /* srom read and passed crc */
1181 && (sih->buscorerev >= 6))
1182 || ((sih->buscoretype == PCI_CORE_ID)
1183 && (sih->buscorerev >= 0xe)))) {
1184 /* sromrev >= 4, read more */
1185 err = sprom_read_pci(sih, sromwindow, 0, srom,
1186 SROM4_WORDS, true);
1187 sromrev = srom[SROM4_CRCREV] & 0xff;
1188 } else if (err == 0) {
1189 /* srom is good and is rev < 4 */
1190 /* top word of sprom contains version and crc8 */ 878 /* top word of sprom contains version and crc8 */
1191 sromrev = srom[SROM_CRCREV] & 0xff; 879 sromrev = srom[SROM4_CRCREV] & 0xff;
1192 /* bcm4401 sroms misprogrammed */
1193 if (sromrev == 0x10)
1194 sromrev = 1;
1195 }
1196 } else { 880 } else {
1197 /* Use OTP if SPROM not available */ 881 /* Use OTP if SPROM not available */
1198 err = otp_read_pci(sih, srom, SROM_MAX); 882 err = otp_read_pci(sih, srom, SROM4_WORDS);
1199 if (err == 0) 883 if (err == 0)
1200 /* OTP only contain SROM rev8/rev9 for now */ 884 /* OTP only contain SROM rev8/rev9 for now */
1201 sromrev = srom[SROM4_CRCREV] & 0xff; 885 sromrev = srom[SROM4_CRCREV] & 0xff;
@@ -1208,10 +892,9 @@ static int initvars_srom_pci(struct si_pub *sih, void __iomem *curmap)
1208 sr = 1 << sromrev; 892 sr = 1 << sromrev;
1209 893
1210 /* 894 /*
1211 * srom version check: Current valid versions: 1, 2, 3, 4, 5, 8, 895 * srom version check: Current valid versions: 8, 9
1212 * 9
1213 */ 896 */
1214 if ((sr & 0x33e) == 0) { 897 if ((sr & 0x300) == 0) {
1215 err = -EINVAL; 898 err = -EINVAL;
1216 goto errout; 899 goto errout;
1217 } 900 }
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-07 08:51:36 -0500