diff options
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/pci.c')
| -rw-r--r-- | drivers/net/wireless/ath/ath9k/pci.c | 48 |
1 files changed, 26 insertions, 22 deletions
diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c index 5685cf11cfe3..891661a61513 100644 --- a/drivers/net/wireless/ath/ath9k/pci.c +++ b/drivers/net/wireless/ath/ath9k/pci.c | |||
| @@ -32,9 +32,11 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = { | |||
| 32 | { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */ | 32 | { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */ |
| 33 | { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */ | 33 | { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */ |
| 34 | { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */ | 34 | { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */ |
| 35 | { PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E AR9580 */ | ||
| 35 | { 0 } | 36 | { 0 } |
| 36 | }; | 37 | }; |
| 37 | 38 | ||
| 39 | |||
| 38 | /* return bus cachesize in 4B word units */ | 40 | /* return bus cachesize in 4B word units */ |
| 39 | static void ath_pci_read_cachesize(struct ath_common *common, int *csz) | 41 | static void ath_pci_read_cachesize(struct ath_common *common, int *csz) |
| 40 | { | 42 | { |
| @@ -88,23 +90,6 @@ static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data) | |||
| 88 | return true; | 90 | return true; |
| 89 | } | 91 | } |
| 90 | 92 | ||
| 91 | /* | ||
| 92 | * Bluetooth coexistance requires disabling ASPM. | ||
| 93 | */ | ||
| 94 | static void ath_pci_bt_coex_prep(struct ath_common *common) | ||
| 95 | { | ||
| 96 | struct ath_softc *sc = (struct ath_softc *) common->priv; | ||
| 97 | struct pci_dev *pdev = to_pci_dev(sc->dev); | ||
| 98 | u8 aspm; | ||
| 99 | |||
| 100 | if (!pci_is_pcie(pdev)) | ||
| 101 | return; | ||
| 102 | |||
| 103 | pci_read_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, &aspm); | ||
| 104 | aspm &= ~(ATH_PCIE_CAP_LINK_L0S | ATH_PCIE_CAP_LINK_L1); | ||
| 105 | pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm); | ||
| 106 | } | ||
| 107 | |||
| 108 | static void ath_pci_extn_synch_enable(struct ath_common *common) | 93 | static void ath_pci_extn_synch_enable(struct ath_common *common) |
| 109 | { | 94 | { |
| 110 | struct ath_softc *sc = (struct ath_softc *) common->priv; | 95 | struct ath_softc *sc = (struct ath_softc *) common->priv; |
| @@ -116,6 +101,7 @@ static void ath_pci_extn_synch_enable(struct ath_common *common) | |||
| 116 | pci_write_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, lnkctl); | 101 | pci_write_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, lnkctl); |
| 117 | } | 102 | } |
| 118 | 103 | ||
| 104 | /* Need to be called after we discover btcoex capabilities */ | ||
| 119 | static void ath_pci_aspm_init(struct ath_common *common) | 105 | static void ath_pci_aspm_init(struct ath_common *common) |
| 120 | { | 106 | { |
| 121 | struct ath_softc *sc = (struct ath_softc *) common->priv; | 107 | struct ath_softc *sc = (struct ath_softc *) common->priv; |
| @@ -125,19 +111,38 @@ static void ath_pci_aspm_init(struct ath_common *common) | |||
| 125 | int pos; | 111 | int pos; |
| 126 | u8 aspm; | 112 | u8 aspm; |
| 127 | 113 | ||
| 128 | if (!pci_is_pcie(pdev)) | 114 | pos = pci_pcie_cap(pdev); |
| 115 | if (!pos) | ||
| 129 | return; | 116 | return; |
| 130 | 117 | ||
| 131 | parent = pdev->bus->self; | 118 | parent = pdev->bus->self; |
| 132 | if (WARN_ON(!parent)) | 119 | if (!parent) |
| 133 | return; | 120 | return; |
| 134 | 121 | ||
| 122 | if (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) { | ||
| 123 | /* Bluetooth coexistance requires disabling ASPM. */ | ||
| 124 | pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &aspm); | ||
| 125 | aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); | ||
| 126 | pci_write_config_byte(pdev, pos + PCI_EXP_LNKCTL, aspm); | ||
| 127 | |||
| 128 | /* | ||
| 129 | * Both upstream and downstream PCIe components should | ||
| 130 | * have the same ASPM settings. | ||
| 131 | */ | ||
| 132 | pos = pci_pcie_cap(parent); | ||
| 133 | pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm); | ||
| 134 | aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); | ||
| 135 | pci_write_config_byte(parent, pos + PCI_EXP_LNKCTL, aspm); | ||
| 136 | |||
| 137 | return; | ||
| 138 | } | ||
| 139 | |||
| 135 | pos = pci_pcie_cap(parent); | 140 | pos = pci_pcie_cap(parent); |
| 136 | pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm); | 141 | pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm); |
| 137 | if (aspm & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) { | 142 | if (aspm & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) { |
| 138 | ah->aspm_enabled = true; | 143 | ah->aspm_enabled = true; |
| 139 | /* Initialize PCIe PM and SERDES registers. */ | 144 | /* Initialize PCIe PM and SERDES registers. */ |
| 140 | ath9k_hw_configpcipowersave(ah, 0, 0); | 145 | ath9k_hw_configpcipowersave(ah, false); |
| 141 | } | 146 | } |
| 142 | } | 147 | } |
| 143 | 148 | ||
| @@ -145,7 +150,6 @@ static const struct ath_bus_ops ath_pci_bus_ops = { | |||
| 145 | .ath_bus_type = ATH_PCI, | 150 | .ath_bus_type = ATH_PCI, |
| 146 | .read_cachesize = ath_pci_read_cachesize, | 151 | .read_cachesize = ath_pci_read_cachesize, |
| 147 | .eeprom_read = ath_pci_eeprom_read, | 152 | .eeprom_read = ath_pci_eeprom_read, |
| 148 | .bt_coex_prep = ath_pci_bt_coex_prep, | ||
| 149 | .extn_synch_en = ath_pci_extn_synch_enable, | 153 | .extn_synch_en = ath_pci_extn_synch_enable, |
| 150 | .aspm_init = ath_pci_aspm_init, | 154 | .aspm_init = ath_pci_aspm_init, |
| 151 | }; | 155 | }; |
| @@ -338,7 +342,7 @@ static int ath_pci_resume(struct device *device) | |||
| 338 | * semi-random values after suspend/resume. | 342 | * semi-random values after suspend/resume. |
| 339 | */ | 343 | */ |
| 340 | ath9k_ps_wakeup(sc); | 344 | ath9k_ps_wakeup(sc); |
| 341 | ath9k_init_crypto(sc); | 345 | ath9k_cmn_init_crypto(sc->sc_ah); |
| 342 | ath9k_ps_restore(sc); | 346 | ath9k_ps_restore(sc); |
| 343 | 347 | ||
| 344 | sc->ps_idle = true; | 348 | sc->ps_idle = true; |
