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-rw-r--r--drivers/net/stmmac/Kconfig5
-rw-r--r--drivers/net/stmmac/common.h61
-rw-r--r--drivers/net/stmmac/dwmac100.h2
-rw-r--r--drivers/net/stmmac/dwmac1000.h4
-rw-r--r--drivers/net/stmmac/dwmac1000_core.c41
-rw-r--r--drivers/net/stmmac/dwmac1000_dma.c20
-rw-r--r--drivers/net/stmmac/dwmac100_core.c31
-rw-r--r--drivers/net/stmmac/dwmac100_dma.c20
-rw-r--r--drivers/net/stmmac/dwmac_dma.h16
-rw-r--r--drivers/net/stmmac/dwmac_lib.c50
-rw-r--r--drivers/net/stmmac/enh_desc.c6
-rw-r--r--drivers/net/stmmac/norm_desc.c23
-rw-r--r--drivers/net/stmmac/stmmac.h42
-rw-r--r--drivers/net/stmmac/stmmac_ethtool.c104
-rw-r--r--drivers/net/stmmac/stmmac_main.c565
-rw-r--r--drivers/net/stmmac/stmmac_mdio.c30
16 files changed, 473 insertions, 547 deletions
diff --git a/drivers/net/stmmac/Kconfig b/drivers/net/stmmac/Kconfig
index eb63d44748a7..7df7df4e79c5 100644
--- a/drivers/net/stmmac/Kconfig
+++ b/drivers/net/stmmac/Kconfig
@@ -3,10 +3,10 @@ config STMMAC_ETH
3 select MII 3 select MII
4 select PHYLIB 4 select PHYLIB
5 select CRC32 5 select CRC32
6 depends on NETDEVICES && CPU_SUBTYPE_ST40 6 depends on NETDEVICES && HAS_IOMEM
7 help 7 help
8 This is the driver for the Ethernet IPs are built around a 8 This is the driver for the Ethernet IPs are built around a
9 Synopsys IP Core and fully tested on the STMicroelectronics 9 Synopsys IP Core and only tested on the STMicroelectronics
10 platforms. 10 platforms.
11 11
12if STMMAC_ETH 12if STMMAC_ETH
@@ -32,6 +32,7 @@ config STMMAC_DUAL_MAC
32config STMMAC_TIMER 32config STMMAC_TIMER
33 bool "STMMAC Timer optimisation" 33 bool "STMMAC Timer optimisation"
34 default n 34 default n
35 depends on RTC_HCTOSYS_DEVICE
35 help 36 help
36 Use an external timer for mitigating the number of network 37 Use an external timer for mitigating the number of network
37 interrupts. Currently, for SH architectures, it is possible 38 interrupts. Currently, for SH architectures, it is possible
diff --git a/drivers/net/stmmac/common.h b/drivers/net/stmmac/common.h
index 66b9da0260fe..375ea193e139 100644
--- a/drivers/net/stmmac/common.h
+++ b/drivers/net/stmmac/common.h
@@ -102,8 +102,6 @@ struct stmmac_extra_stats {
102 102
103#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */ 103#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
104 104
105#define HW_CSUM 1
106#define NO_HW_CSUM 0
107enum rx_frame_status { /* IPC status */ 105enum rx_frame_status { /* IPC status */
108 good_frame = 0, 106 good_frame = 0,
109 discard_frame = 1, 107 discard_frame = 1,
@@ -167,7 +165,7 @@ struct stmmac_desc_ops {
167 int (*get_tx_ls) (struct dma_desc *p); 165 int (*get_tx_ls) (struct dma_desc *p);
168 /* Return the transmit status looking at the TDES1 */ 166 /* Return the transmit status looking at the TDES1 */
169 int (*tx_status) (void *data, struct stmmac_extra_stats *x, 167 int (*tx_status) (void *data, struct stmmac_extra_stats *x,
170 struct dma_desc *p, unsigned long ioaddr); 168 struct dma_desc *p, void __iomem *ioaddr);
171 /* Get the buffer size from the descriptor */ 169 /* Get the buffer size from the descriptor */
172 int (*get_tx_len) (struct dma_desc *p); 170 int (*get_tx_len) (struct dma_desc *p);
173 /* Handle extra events on specific interrupts hw dependent */ 171 /* Handle extra events on specific interrupts hw dependent */
@@ -182,44 +180,46 @@ struct stmmac_desc_ops {
182 180
183struct stmmac_dma_ops { 181struct stmmac_dma_ops {
184 /* DMA core initialization */ 182 /* DMA core initialization */
185 int (*init) (unsigned long ioaddr, int pbl, u32 dma_tx, u32 dma_rx); 183 int (*init) (void __iomem *ioaddr, int pbl, u32 dma_tx, u32 dma_rx);
186 /* Dump DMA registers */ 184 /* Dump DMA registers */
187 void (*dump_regs) (unsigned long ioaddr); 185 void (*dump_regs) (void __iomem *ioaddr);
188 /* Set tx/rx threshold in the csr6 register 186 /* Set tx/rx threshold in the csr6 register
189 * An invalid value enables the store-and-forward mode */ 187 * An invalid value enables the store-and-forward mode */
190 void (*dma_mode) (unsigned long ioaddr, int txmode, int rxmode); 188 void (*dma_mode) (void __iomem *ioaddr, int txmode, int rxmode);
191 /* To track extra statistic (if supported) */ 189 /* To track extra statistic (if supported) */
192 void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x, 190 void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
193 unsigned long ioaddr); 191 void __iomem *ioaddr);
194 void (*enable_dma_transmission) (unsigned long ioaddr); 192 void (*enable_dma_transmission) (void __iomem *ioaddr);
195 void (*enable_dma_irq) (unsigned long ioaddr); 193 void (*enable_dma_irq) (void __iomem *ioaddr);
196 void (*disable_dma_irq) (unsigned long ioaddr); 194 void (*disable_dma_irq) (void __iomem *ioaddr);
197 void (*start_tx) (unsigned long ioaddr); 195 void (*start_tx) (void __iomem *ioaddr);
198 void (*stop_tx) (unsigned long ioaddr); 196 void (*stop_tx) (void __iomem *ioaddr);
199 void (*start_rx) (unsigned long ioaddr); 197 void (*start_rx) (void __iomem *ioaddr);
200 void (*stop_rx) (unsigned long ioaddr); 198 void (*stop_rx) (void __iomem *ioaddr);
201 int (*dma_interrupt) (unsigned long ioaddr, 199 int (*dma_interrupt) (void __iomem *ioaddr,
202 struct stmmac_extra_stats *x); 200 struct stmmac_extra_stats *x);
203}; 201};
204 202
205struct stmmac_ops { 203struct stmmac_ops {
206 /* MAC core initialization */ 204 /* MAC core initialization */
207 void (*core_init) (unsigned long ioaddr) ____cacheline_aligned; 205 void (*core_init) (void __iomem *ioaddr) ____cacheline_aligned;
206 /* Support checksum offload engine */
207 int (*rx_coe) (void __iomem *ioaddr);
208 /* Dump MAC registers */ 208 /* Dump MAC registers */
209 void (*dump_regs) (unsigned long ioaddr); 209 void (*dump_regs) (void __iomem *ioaddr);
210 /* Handle extra events on specific interrupts hw dependent */ 210 /* Handle extra events on specific interrupts hw dependent */
211 void (*host_irq_status) (unsigned long ioaddr); 211 void (*host_irq_status) (void __iomem *ioaddr);
212 /* Multicast filter setting */ 212 /* Multicast filter setting */
213 void (*set_filter) (struct net_device *dev); 213 void (*set_filter) (struct net_device *dev);
214 /* Flow control setting */ 214 /* Flow control setting */
215 void (*flow_ctrl) (unsigned long ioaddr, unsigned int duplex, 215 void (*flow_ctrl) (void __iomem *ioaddr, unsigned int duplex,
216 unsigned int fc, unsigned int pause_time); 216 unsigned int fc, unsigned int pause_time);
217 /* Set power management mode (e.g. magic frame) */ 217 /* Set power management mode (e.g. magic frame) */
218 void (*pmt) (unsigned long ioaddr, unsigned long mode); 218 void (*pmt) (void __iomem *ioaddr, unsigned long mode);
219 /* Set/Get Unicast MAC addresses */ 219 /* Set/Get Unicast MAC addresses */
220 void (*set_umac_addr) (unsigned long ioaddr, unsigned char *addr, 220 void (*set_umac_addr) (void __iomem *ioaddr, unsigned char *addr,
221 unsigned int reg_n); 221 unsigned int reg_n);
222 void (*get_umac_addr) (unsigned long ioaddr, unsigned char *addr, 222 void (*get_umac_addr) (void __iomem *ioaddr, unsigned char *addr,
223 unsigned int reg_n); 223 unsigned int reg_n);
224}; 224};
225 225
@@ -235,19 +235,18 @@ struct mii_regs {
235}; 235};
236 236
237struct mac_device_info { 237struct mac_device_info {
238 struct stmmac_ops *mac; 238 const struct stmmac_ops *mac;
239 struct stmmac_desc_ops *desc; 239 const struct stmmac_desc_ops *desc;
240 struct stmmac_dma_ops *dma; 240 const struct stmmac_dma_ops *dma;
241 unsigned int pmt; /* support Power-Down */
242 struct mii_regs mii; /* MII register Addresses */ 241 struct mii_regs mii; /* MII register Addresses */
243 struct mac_link link; 242 struct mac_link link;
244}; 243};
245 244
246struct mac_device_info *dwmac1000_setup(unsigned long addr); 245struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr);
247struct mac_device_info *dwmac100_setup(unsigned long addr); 246struct mac_device_info *dwmac100_setup(void __iomem *ioaddr);
248 247
249extern void stmmac_set_mac_addr(unsigned long ioaddr, u8 addr[6], 248extern void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
250 unsigned int high, unsigned int low); 249 unsigned int high, unsigned int low);
251extern void stmmac_get_mac_addr(unsigned long ioaddr, unsigned char *addr, 250extern void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
252 unsigned int high, unsigned int low); 251 unsigned int high, unsigned int low);
253extern void dwmac_dma_flush_tx_fifo(unsigned long ioaddr); 252extern void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
diff --git a/drivers/net/stmmac/dwmac100.h b/drivers/net/stmmac/dwmac100.h
index 97956cbf1cb4..7c6d857a9cc7 100644
--- a/drivers/net/stmmac/dwmac100.h
+++ b/drivers/net/stmmac/dwmac100.h
@@ -118,4 +118,4 @@ enum ttc_control {
118#define DMA_MISSED_FRAME_OVE_M 0x00010000 /* Missed Frame Overflow */ 118#define DMA_MISSED_FRAME_OVE_M 0x00010000 /* Missed Frame Overflow */
119#define DMA_MISSED_FRAME_M_CNTR 0x0000ffff /* Missed Frame Couinter */ 119#define DMA_MISSED_FRAME_M_CNTR 0x0000ffff /* Missed Frame Couinter */
120 120
121extern struct stmmac_dma_ops dwmac100_dma_ops; 121extern const struct stmmac_dma_ops dwmac100_dma_ops;
diff --git a/drivers/net/stmmac/dwmac1000.h b/drivers/net/stmmac/dwmac1000.h
index 8b20b19971cb..cfcef0ea0fa5 100644
--- a/drivers/net/stmmac/dwmac1000.h
+++ b/drivers/net/stmmac/dwmac1000.h
@@ -99,7 +99,7 @@ enum inter_frame_gap {
99#define GMAC_CONTROL_RE 0x00000004 /* Receiver Enable */ 99#define GMAC_CONTROL_RE 0x00000004 /* Receiver Enable */
100 100
101#define GMAC_CORE_INIT (GMAC_CONTROL_JD | GMAC_CONTROL_PS | GMAC_CONTROL_ACS | \ 101#define GMAC_CORE_INIT (GMAC_CONTROL_JD | GMAC_CONTROL_PS | GMAC_CONTROL_ACS | \
102 GMAC_CONTROL_IPC | GMAC_CONTROL_JE | GMAC_CONTROL_BE) 102 GMAC_CONTROL_JE | GMAC_CONTROL_BE)
103 103
104/* GMAC Frame Filter defines */ 104/* GMAC Frame Filter defines */
105#define GMAC_FRAME_FILTER_PR 0x00000001 /* Promiscuous Mode */ 105#define GMAC_FRAME_FILTER_PR 0x00000001 /* Promiscuous Mode */
@@ -205,4 +205,4 @@ enum rtc_control {
205#define GMAC_MMC_TX_INTR 0x108 205#define GMAC_MMC_TX_INTR 0x108
206#define GMAC_MMC_RX_CSUM_OFFLOAD 0x208 206#define GMAC_MMC_RX_CSUM_OFFLOAD 0x208
207 207
208extern struct stmmac_dma_ops dwmac1000_dma_ops; 208extern const struct stmmac_dma_ops dwmac1000_dma_ops;
diff --git a/drivers/net/stmmac/dwmac1000_core.c b/drivers/net/stmmac/dwmac1000_core.c
index 2b2f5c8caf1c..f20455cbfbbc 100644
--- a/drivers/net/stmmac/dwmac1000_core.c
+++ b/drivers/net/stmmac/dwmac1000_core.c
@@ -30,7 +30,7 @@
30#include <linux/slab.h> 30#include <linux/slab.h>
31#include "dwmac1000.h" 31#include "dwmac1000.h"
32 32
33static void dwmac1000_core_init(unsigned long ioaddr) 33static void dwmac1000_core_init(void __iomem *ioaddr)
34{ 34{
35 u32 value = readl(ioaddr + GMAC_CONTROL); 35 u32 value = readl(ioaddr + GMAC_CONTROL);
36 value |= GMAC_CORE_INIT; 36 value |= GMAC_CORE_INIT;
@@ -50,10 +50,22 @@ static void dwmac1000_core_init(unsigned long ioaddr)
50#endif 50#endif
51} 51}
52 52
53static void dwmac1000_dump_regs(unsigned long ioaddr) 53static int dwmac1000_rx_coe_supported(void __iomem *ioaddr)
54{
55 u32 value = readl(ioaddr + GMAC_CONTROL);
56
57 value |= GMAC_CONTROL_IPC;
58 writel(value, ioaddr + GMAC_CONTROL);
59
60 value = readl(ioaddr + GMAC_CONTROL);
61
62 return !!(value & GMAC_CONTROL_IPC);
63}
64
65static void dwmac1000_dump_regs(void __iomem *ioaddr)
54{ 66{
55 int i; 67 int i;
56 pr_info("\tDWMAC1000 regs (base addr = 0x%8x)\n", (unsigned int)ioaddr); 68 pr_info("\tDWMAC1000 regs (base addr = 0x%p)\n", ioaddr);
57 69
58 for (i = 0; i < 55; i++) { 70 for (i = 0; i < 55; i++) {
59 int offset = i * 4; 71 int offset = i * 4;
@@ -62,14 +74,14 @@ static void dwmac1000_dump_regs(unsigned long ioaddr)
62 } 74 }
63} 75}
64 76
65static void dwmac1000_set_umac_addr(unsigned long ioaddr, unsigned char *addr, 77static void dwmac1000_set_umac_addr(void __iomem *ioaddr, unsigned char *addr,
66 unsigned int reg_n) 78 unsigned int reg_n)
67{ 79{
68 stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n), 80 stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
69 GMAC_ADDR_LOW(reg_n)); 81 GMAC_ADDR_LOW(reg_n));
70} 82}
71 83
72static void dwmac1000_get_umac_addr(unsigned long ioaddr, unsigned char *addr, 84static void dwmac1000_get_umac_addr(void __iomem *ioaddr, unsigned char *addr,
73 unsigned int reg_n) 85 unsigned int reg_n)
74{ 86{
75 stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n), 87 stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
@@ -78,7 +90,7 @@ static void dwmac1000_get_umac_addr(unsigned long ioaddr, unsigned char *addr,
78 90
79static void dwmac1000_set_filter(struct net_device *dev) 91static void dwmac1000_set_filter(struct net_device *dev)
80{ 92{
81 unsigned long ioaddr = dev->base_addr; 93 void __iomem *ioaddr = (void __iomem *) dev->base_addr;
82 unsigned int value = 0; 94 unsigned int value = 0;
83 95
84 CHIP_DBG(KERN_INFO "%s: # mcasts %d, # unicast %d\n", 96 CHIP_DBG(KERN_INFO "%s: # mcasts %d, # unicast %d\n",
@@ -139,7 +151,7 @@ static void dwmac1000_set_filter(struct net_device *dev)
139 readl(ioaddr + GMAC_HASH_HIGH), readl(ioaddr + GMAC_HASH_LOW)); 151 readl(ioaddr + GMAC_HASH_HIGH), readl(ioaddr + GMAC_HASH_LOW));
140} 152}
141 153
142static void dwmac1000_flow_ctrl(unsigned long ioaddr, unsigned int duplex, 154static void dwmac1000_flow_ctrl(void __iomem *ioaddr, unsigned int duplex,
143 unsigned int fc, unsigned int pause_time) 155 unsigned int fc, unsigned int pause_time)
144{ 156{
145 unsigned int flow = 0; 157 unsigned int flow = 0;
@@ -162,14 +174,15 @@ static void dwmac1000_flow_ctrl(unsigned long ioaddr, unsigned int duplex,
162 writel(flow, ioaddr + GMAC_FLOW_CTRL); 174 writel(flow, ioaddr + GMAC_FLOW_CTRL);
163} 175}
164 176
165static void dwmac1000_pmt(unsigned long ioaddr, unsigned long mode) 177static void dwmac1000_pmt(void __iomem *ioaddr, unsigned long mode)
166{ 178{
167 unsigned int pmt = 0; 179 unsigned int pmt = 0;
168 180
169 if (mode == WAKE_MAGIC) { 181 if (mode & WAKE_MAGIC) {
170 CHIP_DBG(KERN_DEBUG "GMAC: WOL Magic frame\n"); 182 CHIP_DBG(KERN_DEBUG "GMAC: WOL Magic frame\n");
171 pmt |= power_down | magic_pkt_en; 183 pmt |= power_down | magic_pkt_en;
172 } else if (mode == WAKE_UCAST) { 184 }
185 if (mode & WAKE_UCAST) {
173 CHIP_DBG(KERN_DEBUG "GMAC: WOL on global unicast\n"); 186 CHIP_DBG(KERN_DEBUG "GMAC: WOL on global unicast\n");
174 pmt |= global_unicast; 187 pmt |= global_unicast;
175 } 188 }
@@ -178,7 +191,7 @@ static void dwmac1000_pmt(unsigned long ioaddr, unsigned long mode)
178} 191}
179 192
180 193
181static void dwmac1000_irq_status(unsigned long ioaddr) 194static void dwmac1000_irq_status(void __iomem *ioaddr)
182{ 195{
183 u32 intr_status = readl(ioaddr + GMAC_INT_STATUS); 196 u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
184 197
@@ -200,8 +213,9 @@ static void dwmac1000_irq_status(unsigned long ioaddr)
200 } 213 }
201} 214}
202 215
203struct stmmac_ops dwmac1000_ops = { 216static const struct stmmac_ops dwmac1000_ops = {
204 .core_init = dwmac1000_core_init, 217 .core_init = dwmac1000_core_init,
218 .rx_coe = dwmac1000_rx_coe_supported,
205 .dump_regs = dwmac1000_dump_regs, 219 .dump_regs = dwmac1000_dump_regs,
206 .host_irq_status = dwmac1000_irq_status, 220 .host_irq_status = dwmac1000_irq_status,
207 .set_filter = dwmac1000_set_filter, 221 .set_filter = dwmac1000_set_filter,
@@ -211,7 +225,7 @@ struct stmmac_ops dwmac1000_ops = {
211 .get_umac_addr = dwmac1000_get_umac_addr, 225 .get_umac_addr = dwmac1000_get_umac_addr,
212}; 226};
213 227
214struct mac_device_info *dwmac1000_setup(unsigned long ioaddr) 228struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr)
215{ 229{
216 struct mac_device_info *mac; 230 struct mac_device_info *mac;
217 u32 uid = readl(ioaddr + GMAC_VERSION); 231 u32 uid = readl(ioaddr + GMAC_VERSION);
@@ -226,7 +240,6 @@ struct mac_device_info *dwmac1000_setup(unsigned long ioaddr)
226 mac->mac = &dwmac1000_ops; 240 mac->mac = &dwmac1000_ops;
227 mac->dma = &dwmac1000_dma_ops; 241 mac->dma = &dwmac1000_dma_ops;
228 242
229 mac->pmt = PMT_SUPPORTED;
230 mac->link.port = GMAC_CONTROL_PS; 243 mac->link.port = GMAC_CONTROL_PS;
231 mac->link.duplex = GMAC_CONTROL_DM; 244 mac->link.duplex = GMAC_CONTROL_DM;
232 mac->link.speed = GMAC_CONTROL_FES; 245 mac->link.speed = GMAC_CONTROL_FES;
diff --git a/drivers/net/stmmac/dwmac1000_dma.c b/drivers/net/stmmac/dwmac1000_dma.c
index 415805057cb0..2c47712d45d0 100644
--- a/drivers/net/stmmac/dwmac1000_dma.c
+++ b/drivers/net/stmmac/dwmac1000_dma.c
@@ -29,14 +29,22 @@
29#include "dwmac1000.h" 29#include "dwmac1000.h"
30#include "dwmac_dma.h" 30#include "dwmac_dma.h"
31 31
32static int dwmac1000_dma_init(unsigned long ioaddr, int pbl, u32 dma_tx, 32static int dwmac1000_dma_init(void __iomem *ioaddr, int pbl, u32 dma_tx,
33 u32 dma_rx) 33 u32 dma_rx)
34{ 34{
35 u32 value = readl(ioaddr + DMA_BUS_MODE); 35 u32 value = readl(ioaddr + DMA_BUS_MODE);
36 int limit;
37
36 /* DMA SW reset */ 38 /* DMA SW reset */
37 value |= DMA_BUS_MODE_SFT_RESET; 39 value |= DMA_BUS_MODE_SFT_RESET;
38 writel(value, ioaddr + DMA_BUS_MODE); 40 writel(value, ioaddr + DMA_BUS_MODE);
39 do {} while ((readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET)); 41 limit = 15000;
42 while (limit--) {
43 if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET))
44 break;
45 }
46 if (limit < 0)
47 return -EBUSY;
40 48
41 value = /* DMA_BUS_MODE_FB | */ DMA_BUS_MODE_4PBL | 49 value = /* DMA_BUS_MODE_FB | */ DMA_BUS_MODE_4PBL |
42 ((pbl << DMA_BUS_MODE_PBL_SHIFT) | 50 ((pbl << DMA_BUS_MODE_PBL_SHIFT) |
@@ -58,7 +66,7 @@ static int dwmac1000_dma_init(unsigned long ioaddr, int pbl, u32 dma_tx,
58 return 0; 66 return 0;
59} 67}
60 68
61static void dwmac1000_dma_operation_mode(unsigned long ioaddr, int txmode, 69static void dwmac1000_dma_operation_mode(void __iomem *ioaddr, int txmode,
62 int rxmode) 70 int rxmode)
63{ 71{
64 u32 csr6 = readl(ioaddr + DMA_CONTROL); 72 u32 csr6 = readl(ioaddr + DMA_CONTROL);
@@ -111,12 +119,12 @@ static void dwmac1000_dma_operation_mode(unsigned long ioaddr, int txmode,
111 119
112/* Not yet implemented --- no RMON module */ 120/* Not yet implemented --- no RMON module */
113static void dwmac1000_dma_diagnostic_fr(void *data, 121static void dwmac1000_dma_diagnostic_fr(void *data,
114 struct stmmac_extra_stats *x, unsigned long ioaddr) 122 struct stmmac_extra_stats *x, void __iomem *ioaddr)
115{ 123{
116 return; 124 return;
117} 125}
118 126
119static void dwmac1000_dump_dma_regs(unsigned long ioaddr) 127static void dwmac1000_dump_dma_regs(void __iomem *ioaddr)
120{ 128{
121 int i; 129 int i;
122 pr_info(" DMA registers\n"); 130 pr_info(" DMA registers\n");
@@ -130,7 +138,7 @@ static void dwmac1000_dump_dma_regs(unsigned long ioaddr)
130 } 138 }
131} 139}
132 140
133struct stmmac_dma_ops dwmac1000_dma_ops = { 141const struct stmmac_dma_ops dwmac1000_dma_ops = {
134 .init = dwmac1000_dma_init, 142 .init = dwmac1000_dma_init,
135 .dump_regs = dwmac1000_dump_dma_regs, 143 .dump_regs = dwmac1000_dump_dma_regs,
136 .dma_mode = dwmac1000_dma_operation_mode, 144 .dma_mode = dwmac1000_dma_operation_mode,
diff --git a/drivers/net/stmmac/dwmac100_core.c b/drivers/net/stmmac/dwmac100_core.c
index 2fb165fa2ba0..c724fc36a24f 100644
--- a/drivers/net/stmmac/dwmac100_core.c
+++ b/drivers/net/stmmac/dwmac100_core.c
@@ -31,7 +31,7 @@
31#include <linux/crc32.h> 31#include <linux/crc32.h>
32#include "dwmac100.h" 32#include "dwmac100.h"
33 33
34static void dwmac100_core_init(unsigned long ioaddr) 34static void dwmac100_core_init(void __iomem *ioaddr)
35{ 35{
36 u32 value = readl(ioaddr + MAC_CONTROL); 36 u32 value = readl(ioaddr + MAC_CONTROL);
37 37
@@ -42,12 +42,17 @@ static void dwmac100_core_init(unsigned long ioaddr)
42#endif 42#endif
43} 43}
44 44
45static void dwmac100_dump_mac_regs(unsigned long ioaddr) 45static int dwmac100_rx_coe_supported(void __iomem *ioaddr)
46{
47 return 0;
48}
49
50static void dwmac100_dump_mac_regs(void __iomem *ioaddr)
46{ 51{
47 pr_info("\t----------------------------------------------\n" 52 pr_info("\t----------------------------------------------\n"
48 "\t DWMAC 100 CSR (base addr = 0x%8x)\n" 53 "\t DWMAC 100 CSR (base addr = 0x%p)\n"
49 "\t----------------------------------------------\n", 54 "\t----------------------------------------------\n",
50 (unsigned int)ioaddr); 55 ioaddr);
51 pr_info("\tcontrol reg (offset 0x%x): 0x%08x\n", MAC_CONTROL, 56 pr_info("\tcontrol reg (offset 0x%x): 0x%08x\n", MAC_CONTROL,
52 readl(ioaddr + MAC_CONTROL)); 57 readl(ioaddr + MAC_CONTROL));
53 pr_info("\taddr HI (offset 0x%x): 0x%08x\n ", MAC_ADDR_HIGH, 58 pr_info("\taddr HI (offset 0x%x): 0x%08x\n ", MAC_ADDR_HIGH,
@@ -77,18 +82,18 @@ static void dwmac100_dump_mac_regs(unsigned long ioaddr)
77 MMC_LOW_INTR_MASK, readl(ioaddr + MMC_LOW_INTR_MASK)); 82 MMC_LOW_INTR_MASK, readl(ioaddr + MMC_LOW_INTR_MASK));
78} 83}
79 84
80static void dwmac100_irq_status(unsigned long ioaddr) 85static void dwmac100_irq_status(void __iomem *ioaddr)
81{ 86{
82 return; 87 return;
83} 88}
84 89
85static void dwmac100_set_umac_addr(unsigned long ioaddr, unsigned char *addr, 90static void dwmac100_set_umac_addr(void __iomem *ioaddr, unsigned char *addr,
86 unsigned int reg_n) 91 unsigned int reg_n)
87{ 92{
88 stmmac_set_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW); 93 stmmac_set_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
89} 94}
90 95
91static void dwmac100_get_umac_addr(unsigned long ioaddr, unsigned char *addr, 96static void dwmac100_get_umac_addr(void __iomem *ioaddr, unsigned char *addr,
92 unsigned int reg_n) 97 unsigned int reg_n)
93{ 98{
94 stmmac_get_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW); 99 stmmac_get_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
@@ -96,7 +101,7 @@ static void dwmac100_get_umac_addr(unsigned long ioaddr, unsigned char *addr,
96 101
97static void dwmac100_set_filter(struct net_device *dev) 102static void dwmac100_set_filter(struct net_device *dev)
98{ 103{
99 unsigned long ioaddr = dev->base_addr; 104 void __iomem *ioaddr = (void __iomem *) dev->base_addr;
100 u32 value = readl(ioaddr + MAC_CONTROL); 105 u32 value = readl(ioaddr + MAC_CONTROL);
101 106
102 if (dev->flags & IFF_PROMISC) { 107 if (dev->flags & IFF_PROMISC) {
@@ -145,7 +150,7 @@ static void dwmac100_set_filter(struct net_device *dev)
145 readl(ioaddr + MAC_HASH_HIGH), readl(ioaddr + MAC_HASH_LOW)); 150 readl(ioaddr + MAC_HASH_HIGH), readl(ioaddr + MAC_HASH_LOW));
146} 151}
147 152
148static void dwmac100_flow_ctrl(unsigned long ioaddr, unsigned int duplex, 153static void dwmac100_flow_ctrl(void __iomem *ioaddr, unsigned int duplex,
149 unsigned int fc, unsigned int pause_time) 154 unsigned int fc, unsigned int pause_time)
150{ 155{
151 unsigned int flow = MAC_FLOW_CTRL_ENABLE; 156 unsigned int flow = MAC_FLOW_CTRL_ENABLE;
@@ -158,13 +163,14 @@ static void dwmac100_flow_ctrl(unsigned long ioaddr, unsigned int duplex,
158/* No PMT module supported for this Ethernet Controller. 163/* No PMT module supported for this Ethernet Controller.
159 * Tested on ST platforms only. 164 * Tested on ST platforms only.
160 */ 165 */
161static void dwmac100_pmt(unsigned long ioaddr, unsigned long mode) 166static void dwmac100_pmt(void __iomem *ioaddr, unsigned long mode)
162{ 167{
163 return; 168 return;
164} 169}
165 170
166struct stmmac_ops dwmac100_ops = { 171static const struct stmmac_ops dwmac100_ops = {
167 .core_init = dwmac100_core_init, 172 .core_init = dwmac100_core_init,
173 .rx_coe = dwmac100_rx_coe_supported,
168 .dump_regs = dwmac100_dump_mac_regs, 174 .dump_regs = dwmac100_dump_mac_regs,
169 .host_irq_status = dwmac100_irq_status, 175 .host_irq_status = dwmac100_irq_status,
170 .set_filter = dwmac100_set_filter, 176 .set_filter = dwmac100_set_filter,
@@ -174,7 +180,7 @@ struct stmmac_ops dwmac100_ops = {
174 .get_umac_addr = dwmac100_get_umac_addr, 180 .get_umac_addr = dwmac100_get_umac_addr,
175}; 181};
176 182
177struct mac_device_info *dwmac100_setup(unsigned long ioaddr) 183struct mac_device_info *dwmac100_setup(void __iomem *ioaddr)
178{ 184{
179 struct mac_device_info *mac; 185 struct mac_device_info *mac;
180 186
@@ -187,7 +193,6 @@ struct mac_device_info *dwmac100_setup(unsigned long ioaddr)
187 mac->mac = &dwmac100_ops; 193 mac->mac = &dwmac100_ops;
188 mac->dma = &dwmac100_dma_ops; 194 mac->dma = &dwmac100_dma_ops;
189 195
190 mac->pmt = PMT_NOT_SUPPORTED;
191 mac->link.port = MAC_CONTROL_PS; 196 mac->link.port = MAC_CONTROL_PS;
192 mac->link.duplex = MAC_CONTROL_F; 197 mac->link.duplex = MAC_CONTROL_F;
193 mac->link.speed = 0; 198 mac->link.speed = 0;
diff --git a/drivers/net/stmmac/dwmac100_dma.c b/drivers/net/stmmac/dwmac100_dma.c
index 2fece7b72727..e3e224b7d9e2 100644
--- a/drivers/net/stmmac/dwmac100_dma.c
+++ b/drivers/net/stmmac/dwmac100_dma.c
@@ -31,14 +31,22 @@
31#include "dwmac100.h" 31#include "dwmac100.h"
32#include "dwmac_dma.h" 32#include "dwmac_dma.h"
33 33
34static int dwmac100_dma_init(unsigned long ioaddr, int pbl, u32 dma_tx, 34static int dwmac100_dma_init(void __iomem *ioaddr, int pbl, u32 dma_tx,
35 u32 dma_rx) 35 u32 dma_rx)
36{ 36{
37 u32 value = readl(ioaddr + DMA_BUS_MODE); 37 u32 value = readl(ioaddr + DMA_BUS_MODE);
38 int limit;
39
38 /* DMA SW reset */ 40 /* DMA SW reset */
39 value |= DMA_BUS_MODE_SFT_RESET; 41 value |= DMA_BUS_MODE_SFT_RESET;
40 writel(value, ioaddr + DMA_BUS_MODE); 42 writel(value, ioaddr + DMA_BUS_MODE);
41 do {} while ((readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET)); 43 limit = 15000;
44 while (limit--) {
45 if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET))
46 break;
47 }
48 if (limit < 0)
49 return -EBUSY;
42 50
43 /* Enable Application Access by writing to DMA CSR0 */ 51 /* Enable Application Access by writing to DMA CSR0 */
44 writel(DMA_BUS_MODE_DEFAULT | (pbl << DMA_BUS_MODE_PBL_SHIFT), 52 writel(DMA_BUS_MODE_DEFAULT | (pbl << DMA_BUS_MODE_PBL_SHIFT),
@@ -58,7 +66,7 @@ static int dwmac100_dma_init(unsigned long ioaddr, int pbl, u32 dma_tx,
58/* Store and Forward capability is not used at all.. 66/* Store and Forward capability is not used at all..
59 * The transmit threshold can be programmed by 67 * The transmit threshold can be programmed by
60 * setting the TTC bits in the DMA control register.*/ 68 * setting the TTC bits in the DMA control register.*/
61static void dwmac100_dma_operation_mode(unsigned long ioaddr, int txmode, 69static void dwmac100_dma_operation_mode(void __iomem *ioaddr, int txmode,
62 int rxmode) 70 int rxmode)
63{ 71{
64 u32 csr6 = readl(ioaddr + DMA_CONTROL); 72 u32 csr6 = readl(ioaddr + DMA_CONTROL);
@@ -73,7 +81,7 @@ static void dwmac100_dma_operation_mode(unsigned long ioaddr, int txmode,
73 writel(csr6, ioaddr + DMA_CONTROL); 81 writel(csr6, ioaddr + DMA_CONTROL);
74} 82}
75 83
76static void dwmac100_dump_dma_regs(unsigned long ioaddr) 84static void dwmac100_dump_dma_regs(void __iomem *ioaddr)
77{ 85{
78 int i; 86 int i;
79 87
@@ -91,7 +99,7 @@ static void dwmac100_dump_dma_regs(unsigned long ioaddr)
91/* DMA controller has two counters to track the number of 99/* DMA controller has two counters to track the number of
92 * the receive missed frames. */ 100 * the receive missed frames. */
93static void dwmac100_dma_diagnostic_fr(void *data, struct stmmac_extra_stats *x, 101static void dwmac100_dma_diagnostic_fr(void *data, struct stmmac_extra_stats *x,
94 unsigned long ioaddr) 102 void __iomem *ioaddr)
95{ 103{
96 struct net_device_stats *stats = (struct net_device_stats *)data; 104 struct net_device_stats *stats = (struct net_device_stats *)data;
97 u32 csr8 = readl(ioaddr + DMA_MISSED_FRAME_CTR); 105 u32 csr8 = readl(ioaddr + DMA_MISSED_FRAME_CTR);
@@ -118,7 +126,7 @@ static void dwmac100_dma_diagnostic_fr(void *data, struct stmmac_extra_stats *x,
118 } 126 }
119} 127}
120 128
121struct stmmac_dma_ops dwmac100_dma_ops = { 129const struct stmmac_dma_ops dwmac100_dma_ops = {
122 .init = dwmac100_dma_init, 130 .init = dwmac100_dma_init,
123 .dump_regs = dwmac100_dump_dma_regs, 131 .dump_regs = dwmac100_dump_dma_regs,
124 .dma_mode = dwmac100_dma_operation_mode, 132 .dma_mode = dwmac100_dma_operation_mode,
diff --git a/drivers/net/stmmac/dwmac_dma.h b/drivers/net/stmmac/dwmac_dma.h
index 7b815a1b7b8c..da3f5ccf83d3 100644
--- a/drivers/net/stmmac/dwmac_dma.h
+++ b/drivers/net/stmmac/dwmac_dma.h
@@ -97,12 +97,12 @@
97#define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */ 97#define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */
98#define DMA_CONTROL_FTF 0x00100000 /* Flush transmit FIFO */ 98#define DMA_CONTROL_FTF 0x00100000 /* Flush transmit FIFO */
99 99
100extern void dwmac_enable_dma_transmission(unsigned long ioaddr); 100extern void dwmac_enable_dma_transmission(void __iomem *ioaddr);
101extern void dwmac_enable_dma_irq(unsigned long ioaddr); 101extern void dwmac_enable_dma_irq(void __iomem *ioaddr);
102extern void dwmac_disable_dma_irq(unsigned long ioaddr); 102extern void dwmac_disable_dma_irq(void __iomem *ioaddr);
103extern void dwmac_dma_start_tx(unsigned long ioaddr); 103extern void dwmac_dma_start_tx(void __iomem *ioaddr);
104extern void dwmac_dma_stop_tx(unsigned long ioaddr); 104extern void dwmac_dma_stop_tx(void __iomem *ioaddr);
105extern void dwmac_dma_start_rx(unsigned long ioaddr); 105extern void dwmac_dma_start_rx(void __iomem *ioaddr);
106extern void dwmac_dma_stop_rx(unsigned long ioaddr); 106extern void dwmac_dma_stop_rx(void __iomem *ioaddr);
107extern int dwmac_dma_interrupt(unsigned long ioaddr, 107extern int dwmac_dma_interrupt(void __iomem *ioaddr,
108 struct stmmac_extra_stats *x); 108 struct stmmac_extra_stats *x);
diff --git a/drivers/net/stmmac/dwmac_lib.c b/drivers/net/stmmac/dwmac_lib.c
index a85415216ef4..e25093510b0c 100644
--- a/drivers/net/stmmac/dwmac_lib.c
+++ b/drivers/net/stmmac/dwmac_lib.c
@@ -26,49 +26,49 @@
26 26
27#undef DWMAC_DMA_DEBUG 27#undef DWMAC_DMA_DEBUG
28#ifdef DWMAC_DMA_DEBUG 28#ifdef DWMAC_DMA_DEBUG
29#define DBG(fmt, args...) printk(fmt, ## args) 29#define DWMAC_LIB_DBG(fmt, args...) printk(fmt, ## args)
30#else 30#else
31#define DBG(fmt, args...) do { } while (0) 31#define DWMAC_LIB_DBG(fmt, args...) do { } while (0)
32#endif 32#endif
33 33
34/* CSR1 enables the transmit DMA to check for new descriptor */ 34/* CSR1 enables the transmit DMA to check for new descriptor */
35void dwmac_enable_dma_transmission(unsigned long ioaddr) 35void dwmac_enable_dma_transmission(void __iomem *ioaddr)
36{ 36{
37 writel(1, ioaddr + DMA_XMT_POLL_DEMAND); 37 writel(1, ioaddr + DMA_XMT_POLL_DEMAND);
38} 38}
39 39
40void dwmac_enable_dma_irq(unsigned long ioaddr) 40void dwmac_enable_dma_irq(void __iomem *ioaddr)
41{ 41{
42 writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA); 42 writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
43} 43}
44 44
45void dwmac_disable_dma_irq(unsigned long ioaddr) 45void dwmac_disable_dma_irq(void __iomem *ioaddr)
46{ 46{
47 writel(0, ioaddr + DMA_INTR_ENA); 47 writel(0, ioaddr + DMA_INTR_ENA);
48} 48}
49 49
50void dwmac_dma_start_tx(unsigned long ioaddr) 50void dwmac_dma_start_tx(void __iomem *ioaddr)
51{ 51{
52 u32 value = readl(ioaddr + DMA_CONTROL); 52 u32 value = readl(ioaddr + DMA_CONTROL);
53 value |= DMA_CONTROL_ST; 53 value |= DMA_CONTROL_ST;
54 writel(value, ioaddr + DMA_CONTROL); 54 writel(value, ioaddr + DMA_CONTROL);
55} 55}
56 56
57void dwmac_dma_stop_tx(unsigned long ioaddr) 57void dwmac_dma_stop_tx(void __iomem *ioaddr)
58{ 58{
59 u32 value = readl(ioaddr + DMA_CONTROL); 59 u32 value = readl(ioaddr + DMA_CONTROL);
60 value &= ~DMA_CONTROL_ST; 60 value &= ~DMA_CONTROL_ST;
61 writel(value, ioaddr + DMA_CONTROL); 61 writel(value, ioaddr + DMA_CONTROL);
62} 62}
63 63
64void dwmac_dma_start_rx(unsigned long ioaddr) 64void dwmac_dma_start_rx(void __iomem *ioaddr)
65{ 65{
66 u32 value = readl(ioaddr + DMA_CONTROL); 66 u32 value = readl(ioaddr + DMA_CONTROL);
67 value |= DMA_CONTROL_SR; 67 value |= DMA_CONTROL_SR;
68 writel(value, ioaddr + DMA_CONTROL); 68 writel(value, ioaddr + DMA_CONTROL);
69} 69}
70 70
71void dwmac_dma_stop_rx(unsigned long ioaddr) 71void dwmac_dma_stop_rx(void __iomem *ioaddr)
72{ 72{
73 u32 value = readl(ioaddr + DMA_CONTROL); 73 u32 value = readl(ioaddr + DMA_CONTROL);
74 value &= ~DMA_CONTROL_SR; 74 value &= ~DMA_CONTROL_SR;
@@ -145,14 +145,14 @@ static void show_rx_process_state(unsigned int status)
145} 145}
146#endif 146#endif
147 147
148int dwmac_dma_interrupt(unsigned long ioaddr, 148int dwmac_dma_interrupt(void __iomem *ioaddr,
149 struct stmmac_extra_stats *x) 149 struct stmmac_extra_stats *x)
150{ 150{
151 int ret = 0; 151 int ret = 0;
152 /* read the status register (CSR5) */ 152 /* read the status register (CSR5) */
153 u32 intr_status = readl(ioaddr + DMA_STATUS); 153 u32 intr_status = readl(ioaddr + DMA_STATUS);
154 154
155 DBG(INFO, "%s: [CSR5: 0x%08x]\n", __func__, intr_status); 155 DWMAC_LIB_DBG(KERN_INFO "%s: [CSR5: 0x%08x]\n", __func__, intr_status);
156#ifdef DWMAC_DMA_DEBUG 156#ifdef DWMAC_DMA_DEBUG
157 /* It displays the DMA process states (CSR5 register) */ 157 /* It displays the DMA process states (CSR5 register) */
158 show_tx_process_state(intr_status); 158 show_tx_process_state(intr_status);
@@ -160,43 +160,43 @@ int dwmac_dma_interrupt(unsigned long ioaddr,
160#endif 160#endif
161 /* ABNORMAL interrupts */ 161 /* ABNORMAL interrupts */
162 if (unlikely(intr_status & DMA_STATUS_AIS)) { 162 if (unlikely(intr_status & DMA_STATUS_AIS)) {
163 DBG(INFO, "CSR5[15] DMA ABNORMAL IRQ: "); 163 DWMAC_LIB_DBG(KERN_INFO "CSR5[15] DMA ABNORMAL IRQ: ");
164 if (unlikely(intr_status & DMA_STATUS_UNF)) { 164 if (unlikely(intr_status & DMA_STATUS_UNF)) {
165 DBG(INFO, "transmit underflow\n"); 165 DWMAC_LIB_DBG(KERN_INFO "transmit underflow\n");
166 ret = tx_hard_error_bump_tc; 166 ret = tx_hard_error_bump_tc;
167 x->tx_undeflow_irq++; 167 x->tx_undeflow_irq++;
168 } 168 }
169 if (unlikely(intr_status & DMA_STATUS_TJT)) { 169 if (unlikely(intr_status & DMA_STATUS_TJT)) {
170 DBG(INFO, "transmit jabber\n"); 170 DWMAC_LIB_DBG(KERN_INFO "transmit jabber\n");
171 x->tx_jabber_irq++; 171 x->tx_jabber_irq++;
172 } 172 }
173 if (unlikely(intr_status & DMA_STATUS_OVF)) { 173 if (unlikely(intr_status & DMA_STATUS_OVF)) {
174 DBG(INFO, "recv overflow\n"); 174 DWMAC_LIB_DBG(KERN_INFO "recv overflow\n");
175 x->rx_overflow_irq++; 175 x->rx_overflow_irq++;
176 } 176 }
177 if (unlikely(intr_status & DMA_STATUS_RU)) { 177 if (unlikely(intr_status & DMA_STATUS_RU)) {
178 DBG(INFO, "receive buffer unavailable\n"); 178 DWMAC_LIB_DBG(KERN_INFO "receive buffer unavailable\n");
179 x->rx_buf_unav_irq++; 179 x->rx_buf_unav_irq++;
180 } 180 }
181 if (unlikely(intr_status & DMA_STATUS_RPS)) { 181 if (unlikely(intr_status & DMA_STATUS_RPS)) {
182 DBG(INFO, "receive process stopped\n"); 182 DWMAC_LIB_DBG(KERN_INFO "receive process stopped\n");
183 x->rx_process_stopped_irq++; 183 x->rx_process_stopped_irq++;
184 } 184 }
185 if (unlikely(intr_status & DMA_STATUS_RWT)) { 185 if (unlikely(intr_status & DMA_STATUS_RWT)) {
186 DBG(INFO, "receive watchdog\n"); 186 DWMAC_LIB_DBG(KERN_INFO "receive watchdog\n");
187 x->rx_watchdog_irq++; 187 x->rx_watchdog_irq++;
188 } 188 }
189 if (unlikely(intr_status & DMA_STATUS_ETI)) { 189 if (unlikely(intr_status & DMA_STATUS_ETI)) {
190 DBG(INFO, "transmit early interrupt\n"); 190 DWMAC_LIB_DBG(KERN_INFO "transmit early interrupt\n");
191 x->tx_early_irq++; 191 x->tx_early_irq++;
192 } 192 }
193 if (unlikely(intr_status & DMA_STATUS_TPS)) { 193 if (unlikely(intr_status & DMA_STATUS_TPS)) {
194 DBG(INFO, "transmit process stopped\n"); 194 DWMAC_LIB_DBG(KERN_INFO "transmit process stopped\n");
195 x->tx_process_stopped_irq++; 195 x->tx_process_stopped_irq++;
196 ret = tx_hard_error; 196 ret = tx_hard_error;
197 } 197 }
198 if (unlikely(intr_status & DMA_STATUS_FBI)) { 198 if (unlikely(intr_status & DMA_STATUS_FBI)) {
199 DBG(INFO, "fatal bus error\n"); 199 DWMAC_LIB_DBG(KERN_INFO "fatal bus error\n");
200 x->fatal_bus_error_irq++; 200 x->fatal_bus_error_irq++;
201 ret = tx_hard_error; 201 ret = tx_hard_error;
202 } 202 }
@@ -215,11 +215,11 @@ int dwmac_dma_interrupt(unsigned long ioaddr,
215 /* Clear the interrupt by writing a logic 1 to the CSR5[15-0] */ 215 /* Clear the interrupt by writing a logic 1 to the CSR5[15-0] */
216 writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS); 216 writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS);
217 217
218 DBG(INFO, "\n\n"); 218 DWMAC_LIB_DBG(KERN_INFO "\n\n");
219 return ret; 219 return ret;
220} 220}
221 221
222void dwmac_dma_flush_tx_fifo(unsigned long ioaddr) 222void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr)
223{ 223{
224 u32 csr6 = readl(ioaddr + DMA_CONTROL); 224 u32 csr6 = readl(ioaddr + DMA_CONTROL);
225 writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL); 225 writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL);
@@ -227,7 +227,7 @@ void dwmac_dma_flush_tx_fifo(unsigned long ioaddr)
227 do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF)); 227 do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF));
228} 228}
229 229
230void stmmac_set_mac_addr(unsigned long ioaddr, u8 addr[6], 230void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
231 unsigned int high, unsigned int low) 231 unsigned int high, unsigned int low)
232{ 232{
233 unsigned long data; 233 unsigned long data;
@@ -238,7 +238,7 @@ void stmmac_set_mac_addr(unsigned long ioaddr, u8 addr[6],
238 writel(data, ioaddr + low); 238 writel(data, ioaddr + low);
239} 239}
240 240
241void stmmac_get_mac_addr(unsigned long ioaddr, unsigned char *addr, 241void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
242 unsigned int high, unsigned int low) 242 unsigned int high, unsigned int low)
243{ 243{
244 unsigned int hi_addr, lo_addr; 244 unsigned int hi_addr, lo_addr;
diff --git a/drivers/net/stmmac/enh_desc.c b/drivers/net/stmmac/enh_desc.c
index f612f986a7e1..e5dfb6a30182 100644
--- a/drivers/net/stmmac/enh_desc.c
+++ b/drivers/net/stmmac/enh_desc.c
@@ -25,7 +25,7 @@
25#include "common.h" 25#include "common.h"
26 26
27static int enh_desc_get_tx_status(void *data, struct stmmac_extra_stats *x, 27static int enh_desc_get_tx_status(void *data, struct stmmac_extra_stats *x,
28 struct dma_desc *p, unsigned long ioaddr) 28 struct dma_desc *p, void __iomem *ioaddr)
29{ 29{
30 int ret = 0; 30 int ret = 0;
31 struct net_device_stats *stats = (struct net_device_stats *)data; 31 struct net_device_stats *stats = (struct net_device_stats *)data;
@@ -284,7 +284,7 @@ static void enh_desc_release_tx_desc(struct dma_desc *p)
284{ 284{
285 int ter = p->des01.etx.end_ring; 285 int ter = p->des01.etx.end_ring;
286 286
287 memset(p, 0, sizeof(struct dma_desc)); 287 memset(p, 0, offsetof(struct dma_desc, des2));
288 p->des01.etx.end_ring = ter; 288 p->des01.etx.end_ring = ter;
289} 289}
290 290
@@ -318,7 +318,7 @@ static int enh_desc_get_rx_frame_len(struct dma_desc *p)
318 return p->des01.erx.frame_length; 318 return p->des01.erx.frame_length;
319} 319}
320 320
321struct stmmac_desc_ops enh_desc_ops = { 321const struct stmmac_desc_ops enh_desc_ops = {
322 .tx_status = enh_desc_get_tx_status, 322 .tx_status = enh_desc_get_tx_status,
323 .rx_status = enh_desc_get_rx_status, 323 .rx_status = enh_desc_get_rx_status,
324 .get_tx_len = enh_desc_get_tx_len, 324 .get_tx_len = enh_desc_get_tx_len,
diff --git a/drivers/net/stmmac/norm_desc.c b/drivers/net/stmmac/norm_desc.c
index 31ad53643792..029c2a2cf524 100644
--- a/drivers/net/stmmac/norm_desc.c
+++ b/drivers/net/stmmac/norm_desc.c
@@ -25,7 +25,7 @@
25#include "common.h" 25#include "common.h"
26 26
27static int ndesc_get_tx_status(void *data, struct stmmac_extra_stats *x, 27static int ndesc_get_tx_status(void *data, struct stmmac_extra_stats *x,
28 struct dma_desc *p, unsigned long ioaddr) 28 struct dma_desc *p, void __iomem *ioaddr)
29{ 29{
30 int ret = 0; 30 int ret = 0;
31 struct net_device_stats *stats = (struct net_device_stats *)data; 31 struct net_device_stats *stats = (struct net_device_stats *)data;
@@ -67,7 +67,7 @@ static int ndesc_get_tx_len(struct dma_desc *p)
67 67
68/* This function verifies if each incoming frame has some errors 68/* This function verifies if each incoming frame has some errors
69 * and, if required, updates the multicast statistics. 69 * and, if required, updates the multicast statistics.
70 * In case of success, it returns csum_none becasue the device 70 * In case of success, it returns csum_none because the device
71 * is not able to compute the csum in HW. */ 71 * is not able to compute the csum in HW. */
72static int ndesc_get_rx_status(void *data, struct stmmac_extra_stats *x, 72static int ndesc_get_rx_status(void *data, struct stmmac_extra_stats *x,
73 struct dma_desc *p) 73 struct dma_desc *p)
@@ -174,22 +174,7 @@ static void ndesc_release_tx_desc(struct dma_desc *p)
174{ 174{
175 int ter = p->des01.tx.end_ring; 175 int ter = p->des01.tx.end_ring;
176 176
177 /* clean field used within the xmit */ 177 memset(p, 0, offsetof(struct dma_desc, des2));
178 p->des01.tx.first_segment = 0;
179 p->des01.tx.last_segment = 0;
180 p->des01.tx.buffer1_size = 0;
181
182 /* clean status reported */
183 p->des01.tx.error_summary = 0;
184 p->des01.tx.underflow_error = 0;
185 p->des01.tx.no_carrier = 0;
186 p->des01.tx.loss_carrier = 0;
187 p->des01.tx.excessive_deferral = 0;
188 p->des01.tx.excessive_collisions = 0;
189 p->des01.tx.late_collision = 0;
190 p->des01.tx.heartbeat_fail = 0;
191 p->des01.tx.deferred = 0;
192
193 /* set termination field */ 178 /* set termination field */
194 p->des01.tx.end_ring = ter; 179 p->des01.tx.end_ring = ter;
195} 180}
@@ -217,7 +202,7 @@ static int ndesc_get_rx_frame_len(struct dma_desc *p)
217 return p->des01.rx.frame_length; 202 return p->des01.rx.frame_length;
218} 203}
219 204
220struct stmmac_desc_ops ndesc_ops = { 205const struct stmmac_desc_ops ndesc_ops = {
221 .tx_status = ndesc_get_tx_status, 206 .tx_status = ndesc_get_tx_status,
222 .rx_status = ndesc_get_rx_status, 207 .rx_status = ndesc_get_rx_status,
223 .get_tx_len = ndesc_get_tx_len, 208 .get_tx_len = ndesc_get_tx_len,
diff --git a/drivers/net/stmmac/stmmac.h b/drivers/net/stmmac/stmmac.h
index ebebc644b1b8..2b076b313622 100644
--- a/drivers/net/stmmac/stmmac.h
+++ b/drivers/net/stmmac/stmmac.h
@@ -20,7 +20,7 @@
20 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 20 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
21*******************************************************************************/ 21*******************************************************************************/
22 22
23#define DRV_MODULE_VERSION "Apr_2010" 23#define DRV_MODULE_VERSION "Nov_2010"
24#include <linux/stmmac.h> 24#include <linux/stmmac.h>
25 25
26#include "common.h" 26#include "common.h"
@@ -36,7 +36,6 @@ struct stmmac_priv {
36 unsigned int cur_tx; 36 unsigned int cur_tx;
37 unsigned int dirty_tx; 37 unsigned int dirty_tx;
38 unsigned int dma_tx_size; 38 unsigned int dma_tx_size;
39 int tx_coe;
40 int tx_coalesce; 39 int tx_coalesce;
41 40
42 struct dma_desc *dma_rx ; 41 struct dma_desc *dma_rx ;
@@ -47,26 +46,22 @@ struct stmmac_priv {
47 struct sk_buff_head rx_recycle; 46 struct sk_buff_head rx_recycle;
48 47
49 struct net_device *dev; 48 struct net_device *dev;
50 int is_gmac;
51 dma_addr_t dma_rx_phy; 49 dma_addr_t dma_rx_phy;
52 unsigned int dma_rx_size; 50 unsigned int dma_rx_size;
53 int rx_csum;
54 unsigned int dma_buf_sz; 51 unsigned int dma_buf_sz;
55 struct device *device; 52 struct device *device;
56 struct mac_device_info *hw; 53 struct mac_device_info *hw;
54 void __iomem *ioaddr;
57 55
58 struct stmmac_extra_stats xstats; 56 struct stmmac_extra_stats xstats;
59 struct napi_struct napi; 57 struct napi_struct napi;
60 58
61 phy_interface_t phy_interface; 59 phy_interface_t phy_interface;
62 int pbl;
63 int bus_id;
64 int phy_addr; 60 int phy_addr;
65 int phy_mask; 61 int phy_mask;
66 int (*phy_reset) (void *priv); 62 int (*phy_reset) (void *priv);
67 void (*fix_mac_speed) (void *priv, unsigned int speed); 63 int rx_coe;
68 void (*bus_setup)(unsigned long ioaddr); 64 int no_csum_insertion;
69 void *bsp_priv;
70 65
71 int phy_irq; 66 int phy_irq;
72 struct phy_device *phydev; 67 struct phy_device *phydev;
@@ -81,40 +76,17 @@ struct stmmac_priv {
81 spinlock_t lock; 76 spinlock_t lock;
82 int wolopts; 77 int wolopts;
83 int wolenabled; 78 int wolenabled;
84 int shutdown;
85#ifdef CONFIG_STMMAC_TIMER 79#ifdef CONFIG_STMMAC_TIMER
86 struct stmmac_timer *tm; 80 struct stmmac_timer *tm;
87#endif 81#endif
88#ifdef STMMAC_VLAN_TAG_USED 82#ifdef STMMAC_VLAN_TAG_USED
89 struct vlan_group *vlgrp; 83 struct vlan_group *vlgrp;
90#endif 84#endif
91 int enh_desc; 85 struct plat_stmmacenet_data *plat;
92}; 86};
93 87
94#ifdef CONFIG_STM_DRIVERS
95#include <linux/stm/pad.h>
96static inline int stmmac_claim_resource(struct platform_device *pdev)
97{
98 int ret = 0;
99 struct plat_stmmacenet_data *plat_dat = pdev->dev.platform_data;
100
101 /* Pad routing setup */
102 if (IS_ERR(devm_stm_pad_claim(&pdev->dev, plat_dat->pad_config,
103 dev_name(&pdev->dev)))) {
104 printk(KERN_ERR "%s: Failed to request pads!\n", __func__);
105 ret = -ENODEV;
106 }
107 return ret;
108}
109#else
110static inline int stmmac_claim_resource(struct platform_device *pdev)
111{
112 return 0;
113}
114#endif
115
116extern int stmmac_mdio_unregister(struct net_device *ndev); 88extern int stmmac_mdio_unregister(struct net_device *ndev);
117extern int stmmac_mdio_register(struct net_device *ndev); 89extern int stmmac_mdio_register(struct net_device *ndev);
118extern void stmmac_set_ethtool_ops(struct net_device *netdev); 90extern void stmmac_set_ethtool_ops(struct net_device *netdev);
119extern struct stmmac_desc_ops enh_desc_ops; 91extern const struct stmmac_desc_ops enh_desc_ops;
120extern struct stmmac_desc_ops ndesc_ops; 92extern const struct stmmac_desc_ops ndesc_ops;
diff --git a/drivers/net/stmmac/stmmac_ethtool.c b/drivers/net/stmmac/stmmac_ethtool.c
index f080509923f0..ae5213a8c4cd 100644
--- a/drivers/net/stmmac/stmmac_ethtool.c
+++ b/drivers/net/stmmac/stmmac_ethtool.c
@@ -89,12 +89,12 @@ static const struct stmmac_stats stmmac_gstrings_stats[] = {
89}; 89};
90#define STMMAC_STATS_LEN ARRAY_SIZE(stmmac_gstrings_stats) 90#define STMMAC_STATS_LEN ARRAY_SIZE(stmmac_gstrings_stats)
91 91
92void stmmac_ethtool_getdrvinfo(struct net_device *dev, 92static void stmmac_ethtool_getdrvinfo(struct net_device *dev,
93 struct ethtool_drvinfo *info) 93 struct ethtool_drvinfo *info)
94{ 94{
95 struct stmmac_priv *priv = netdev_priv(dev); 95 struct stmmac_priv *priv = netdev_priv(dev);
96 96
97 if (!priv->is_gmac) 97 if (!priv->plat->has_gmac)
98 strcpy(info->driver, MAC100_ETHTOOL_NAME); 98 strcpy(info->driver, MAC100_ETHTOOL_NAME);
99 else 99 else
100 strcpy(info->driver, GMAC_ETHTOOL_NAME); 100 strcpy(info->driver, GMAC_ETHTOOL_NAME);
@@ -104,7 +104,8 @@ void stmmac_ethtool_getdrvinfo(struct net_device *dev,
104 info->n_stats = STMMAC_STATS_LEN; 104 info->n_stats = STMMAC_STATS_LEN;
105} 105}
106 106
107int stmmac_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd) 107static int stmmac_ethtool_getsettings(struct net_device *dev,
108 struct ethtool_cmd *cmd)
108{ 109{
109 struct stmmac_priv *priv = netdev_priv(dev); 110 struct stmmac_priv *priv = netdev_priv(dev);
110 struct phy_device *phy = priv->phydev; 111 struct phy_device *phy = priv->phydev;
@@ -126,7 +127,8 @@ int stmmac_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
126 return rc; 127 return rc;
127} 128}
128 129
129int stmmac_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd) 130static int stmmac_ethtool_setsettings(struct net_device *dev,
131 struct ethtool_cmd *cmd)
130{ 132{
131 struct stmmac_priv *priv = netdev_priv(dev); 133 struct stmmac_priv *priv = netdev_priv(dev);
132 struct phy_device *phy = priv->phydev; 134 struct phy_device *phy = priv->phydev;
@@ -139,32 +141,32 @@ int stmmac_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
139 return rc; 141 return rc;
140} 142}
141 143
142u32 stmmac_ethtool_getmsglevel(struct net_device *dev) 144static u32 stmmac_ethtool_getmsglevel(struct net_device *dev)
143{ 145{
144 struct stmmac_priv *priv = netdev_priv(dev); 146 struct stmmac_priv *priv = netdev_priv(dev);
145 return priv->msg_enable; 147 return priv->msg_enable;
146} 148}
147 149
148void stmmac_ethtool_setmsglevel(struct net_device *dev, u32 level) 150static void stmmac_ethtool_setmsglevel(struct net_device *dev, u32 level)
149{ 151{
150 struct stmmac_priv *priv = netdev_priv(dev); 152 struct stmmac_priv *priv = netdev_priv(dev);
151 priv->msg_enable = level; 153 priv->msg_enable = level;
152 154
153} 155}
154 156
155int stmmac_check_if_running(struct net_device *dev) 157static int stmmac_check_if_running(struct net_device *dev)
156{ 158{
157 if (!netif_running(dev)) 159 if (!netif_running(dev))
158 return -EBUSY; 160 return -EBUSY;
159 return 0; 161 return 0;
160} 162}
161 163
162int stmmac_ethtool_get_regs_len(struct net_device *dev) 164static int stmmac_ethtool_get_regs_len(struct net_device *dev)
163{ 165{
164 return REG_SPACE_SIZE; 166 return REG_SPACE_SIZE;
165} 167}
166 168
167void stmmac_ethtool_gregs(struct net_device *dev, 169static void stmmac_ethtool_gregs(struct net_device *dev,
168 struct ethtool_regs *regs, void *space) 170 struct ethtool_regs *regs, void *space)
169{ 171{
170 int i; 172 int i;
@@ -174,44 +176,27 @@ void stmmac_ethtool_gregs(struct net_device *dev,
174 176
175 memset(reg_space, 0x0, REG_SPACE_SIZE); 177 memset(reg_space, 0x0, REG_SPACE_SIZE);
176 178
177 if (!priv->is_gmac) { 179 if (!priv->plat->has_gmac) {
178 /* MAC registers */ 180 /* MAC registers */
179 for (i = 0; i < 12; i++) 181 for (i = 0; i < 12; i++)
180 reg_space[i] = readl(dev->base_addr + (i * 4)); 182 reg_space[i] = readl(priv->ioaddr + (i * 4));
181 /* DMA registers */ 183 /* DMA registers */
182 for (i = 0; i < 9; i++) 184 for (i = 0; i < 9; i++)
183 reg_space[i + 12] = 185 reg_space[i + 12] =
184 readl(dev->base_addr + (DMA_BUS_MODE + (i * 4))); 186 readl(priv->ioaddr + (DMA_BUS_MODE + (i * 4)));
185 reg_space[22] = readl(dev->base_addr + DMA_CUR_TX_BUF_ADDR); 187 reg_space[22] = readl(priv->ioaddr + DMA_CUR_TX_BUF_ADDR);
186 reg_space[23] = readl(dev->base_addr + DMA_CUR_RX_BUF_ADDR); 188 reg_space[23] = readl(priv->ioaddr + DMA_CUR_RX_BUF_ADDR);
187 } else { 189 } else {
188 /* MAC registers */ 190 /* MAC registers */
189 for (i = 0; i < 55; i++) 191 for (i = 0; i < 55; i++)
190 reg_space[i] = readl(dev->base_addr + (i * 4)); 192 reg_space[i] = readl(priv->ioaddr + (i * 4));
191 /* DMA registers */ 193 /* DMA registers */
192 for (i = 0; i < 22; i++) 194 for (i = 0; i < 22; i++)
193 reg_space[i + 55] = 195 reg_space[i + 55] =
194 readl(dev->base_addr + (DMA_BUS_MODE + (i * 4))); 196 readl(priv->ioaddr + (DMA_BUS_MODE + (i * 4)));
195 } 197 }
196} 198}
197 199
198int stmmac_ethtool_set_tx_csum(struct net_device *netdev, u32 data)
199{
200 if (data)
201 netdev->features |= NETIF_F_HW_CSUM;
202 else
203 netdev->features &= ~NETIF_F_HW_CSUM;
204
205 return 0;
206}
207
208u32 stmmac_ethtool_get_rx_csum(struct net_device *dev)
209{
210 struct stmmac_priv *priv = netdev_priv(dev);
211
212 return priv->rx_csum;
213}
214
215static void 200static void
216stmmac_get_pauseparam(struct net_device *netdev, 201stmmac_get_pauseparam(struct net_device *netdev,
217 struct ethtool_pauseparam *pause) 202 struct ethtool_pauseparam *pause)
@@ -249,25 +234,14 @@ stmmac_set_pauseparam(struct net_device *netdev,
249 new_pause |= FLOW_TX; 234 new_pause |= FLOW_TX;
250 235
251 priv->flow_ctrl = new_pause; 236 priv->flow_ctrl = new_pause;
237 phy->autoneg = pause->autoneg;
252 238
253 if (phy->autoneg) { 239 if (phy->autoneg) {
254 if (netif_running(netdev)) { 240 if (netif_running(netdev))
255 struct ethtool_cmd cmd; 241 ret = phy_start_aneg(phy);
256 /* auto-negotiation automatically restarted */ 242 } else
257 cmd.cmd = ETHTOOL_NWAY_RST; 243 priv->hw->mac->flow_ctrl(priv->ioaddr, phy->duplex,
258 cmd.supported = phy->supported;
259 cmd.advertising = phy->advertising;
260 cmd.autoneg = phy->autoneg;
261 cmd.speed = phy->speed;
262 cmd.duplex = phy->duplex;
263 cmd.phy_address = phy->addr;
264 ret = phy_ethtool_sset(phy, &cmd);
265 }
266 } else {
267 unsigned long ioaddr = netdev->base_addr;
268 priv->hw->mac->flow_ctrl(ioaddr, phy->duplex,
269 priv->flow_ctrl, priv->pause); 244 priv->flow_ctrl, priv->pause);
270 }
271 spin_unlock(&priv->lock); 245 spin_unlock(&priv->lock);
272 return ret; 246 return ret;
273} 247}
@@ -276,12 +250,11 @@ static void stmmac_get_ethtool_stats(struct net_device *dev,
276 struct ethtool_stats *dummy, u64 *data) 250 struct ethtool_stats *dummy, u64 *data)
277{ 251{
278 struct stmmac_priv *priv = netdev_priv(dev); 252 struct stmmac_priv *priv = netdev_priv(dev);
279 unsigned long ioaddr = dev->base_addr;
280 int i; 253 int i;
281 254
282 /* Update HW stats if supported */ 255 /* Update HW stats if supported */
283 priv->hw->dma->dma_diagnostic_fr(&dev->stats, (void *) &priv->xstats, 256 priv->hw->dma->dma_diagnostic_fr(&dev->stats, (void *) &priv->xstats,
284 ioaddr); 257 priv->ioaddr);
285 258
286 for (i = 0; i < STMMAC_STATS_LEN; i++) { 259 for (i = 0; i < STMMAC_STATS_LEN; i++) {
287 char *p = (char *)priv + stmmac_gstrings_stats[i].stat_offset; 260 char *p = (char *)priv + stmmac_gstrings_stats[i].stat_offset;
@@ -325,8 +298,8 @@ static void stmmac_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
325 struct stmmac_priv *priv = netdev_priv(dev); 298 struct stmmac_priv *priv = netdev_priv(dev);
326 299
327 spin_lock_irq(&priv->lock); 300 spin_lock_irq(&priv->lock);
328 if (priv->wolenabled == PMT_SUPPORTED) { 301 if (device_can_wakeup(priv->device)) {
329 wol->supported = WAKE_MAGIC; 302 wol->supported = WAKE_MAGIC | WAKE_UCAST;
330 wol->wolopts = priv->wolopts; 303 wol->wolopts = priv->wolopts;
331 } 304 }
332 spin_unlock_irq(&priv->lock); 305 spin_unlock_irq(&priv->lock);
@@ -335,18 +308,22 @@ static void stmmac_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
335static int stmmac_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 308static int stmmac_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
336{ 309{
337 struct stmmac_priv *priv = netdev_priv(dev); 310 struct stmmac_priv *priv = netdev_priv(dev);
338 u32 support = WAKE_MAGIC; 311 u32 support = WAKE_MAGIC | WAKE_UCAST;
339 312
340 if (priv->wolenabled == PMT_NOT_SUPPORTED) 313 if (!device_can_wakeup(priv->device))
341 return -EINVAL; 314 return -EINVAL;
342 315
343 if (wol->wolopts & ~support) 316 if (wol->wolopts & ~support)
344 return -EINVAL; 317 return -EINVAL;
345 318
346 if (wol->wolopts == 0) 319 if (wol->wolopts) {
347 device_set_wakeup_enable(priv->device, 0); 320 pr_info("stmmac: wakeup enable\n");
348 else
349 device_set_wakeup_enable(priv->device, 1); 321 device_set_wakeup_enable(priv->device, 1);
322 enable_irq_wake(dev->irq);
323 } else {
324 device_set_wakeup_enable(priv->device, 0);
325 disable_irq_wake(dev->irq);
326 }
350 327
351 spin_lock_irq(&priv->lock); 328 spin_lock_irq(&priv->lock);
352 priv->wolopts = wol->wolopts; 329 priv->wolopts = wol->wolopts;
@@ -365,11 +342,6 @@ static struct ethtool_ops stmmac_ethtool_ops = {
365 .get_regs = stmmac_ethtool_gregs, 342 .get_regs = stmmac_ethtool_gregs,
366 .get_regs_len = stmmac_ethtool_get_regs_len, 343 .get_regs_len = stmmac_ethtool_get_regs_len,
367 .get_link = ethtool_op_get_link, 344 .get_link = ethtool_op_get_link,
368 .get_rx_csum = stmmac_ethtool_get_rx_csum,
369 .get_tx_csum = ethtool_op_get_tx_csum,
370 .set_tx_csum = stmmac_ethtool_set_tx_csum,
371 .get_sg = ethtool_op_get_sg,
372 .set_sg = ethtool_op_set_sg,
373 .get_pauseparam = stmmac_get_pauseparam, 345 .get_pauseparam = stmmac_get_pauseparam,
374 .set_pauseparam = stmmac_set_pauseparam, 346 .set_pauseparam = stmmac_set_pauseparam,
375 .get_ethtool_stats = stmmac_get_ethtool_stats, 347 .get_ethtool_stats = stmmac_get_ethtool_stats,
@@ -377,10 +349,6 @@ static struct ethtool_ops stmmac_ethtool_ops = {
377 .get_wol = stmmac_get_wol, 349 .get_wol = stmmac_get_wol,
378 .set_wol = stmmac_set_wol, 350 .set_wol = stmmac_set_wol,
379 .get_sset_count = stmmac_get_sset_count, 351 .get_sset_count = stmmac_get_sset_count,
380#ifdef NETIF_F_TSO
381 .get_tso = ethtool_op_get_tso,
382 .set_tso = ethtool_op_set_tso,
383#endif
384}; 352};
385 353
386void stmmac_set_ethtool_ops(struct net_device *netdev) 354void stmmac_set_ethtool_ops(struct net_device *netdev)
diff --git a/drivers/net/stmmac/stmmac_main.c b/drivers/net/stmmac/stmmac_main.c
index ea0461eb2dbe..e25e44a45c28 100644
--- a/drivers/net/stmmac/stmmac_main.c
+++ b/drivers/net/stmmac/stmmac_main.c
@@ -45,6 +45,7 @@
45#include <linux/if_vlan.h> 45#include <linux/if_vlan.h>
46#include <linux/dma-mapping.h> 46#include <linux/dma-mapping.h>
47#include <linux/slab.h> 47#include <linux/slab.h>
48#include <linux/prefetch.h>
48#include "stmmac.h" 49#include "stmmac.h"
49 50
50#define STMMAC_RESOURCE_NAME "stmmaceth" 51#define STMMAC_RESOURCE_NAME "stmmaceth"
@@ -116,9 +117,6 @@ static int tc = TC_DEFAULT;
116module_param(tc, int, S_IRUGO | S_IWUSR); 117module_param(tc, int, S_IRUGO | S_IWUSR);
117MODULE_PARM_DESC(tc, "DMA threshold control value"); 118MODULE_PARM_DESC(tc, "DMA threshold control value");
118 119
119#define RX_NO_COALESCE 1 /* Always interrupt on completion */
120#define TX_NO_COALESCE -1 /* No moderation by default */
121
122/* Pay attention to tune this parameter; take care of both 120/* Pay attention to tune this parameter; take care of both
123 * hardware capability and network stabitily/performance impact. 121 * hardware capability and network stabitily/performance impact.
124 * Many tests showed that ~4ms latency seems to be good enough. */ 122 * Many tests showed that ~4ms latency seems to be good enough. */
@@ -134,19 +132,11 @@ static int buf_sz = DMA_BUFFER_SIZE;
134module_param(buf_sz, int, S_IRUGO | S_IWUSR); 132module_param(buf_sz, int, S_IRUGO | S_IWUSR);
135MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 133MODULE_PARM_DESC(buf_sz, "DMA buffer size");
136 134
137/* In case of Giga ETH, we can enable/disable the COE for the
138 * transmit HW checksum computation.
139 * Note that, if tx csum is off in HW, SG will be still supported. */
140static int tx_coe = HW_CSUM;
141module_param(tx_coe, int, S_IRUGO | S_IWUSR);
142MODULE_PARM_DESC(tx_coe, "GMAC COE type 2 [on/off]");
143
144static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 135static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
145 NETIF_MSG_LINK | NETIF_MSG_IFUP | 136 NETIF_MSG_LINK | NETIF_MSG_IFUP |
146 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 137 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
147 138
148static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 139static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
149static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev);
150 140
151/** 141/**
152 * stmmac_verify_args - verify the driver parameters. 142 * stmmac_verify_args - verify the driver parameters.
@@ -193,6 +183,18 @@ static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
193 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1; 183 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
194} 184}
195 185
186/* On some ST platforms, some HW system configuraton registers have to be
187 * set according to the link speed negotiated.
188 */
189static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
190{
191 struct phy_device *phydev = priv->phydev;
192
193 if (likely(priv->plat->fix_mac_speed))
194 priv->plat->fix_mac_speed(priv->plat->bsp_priv,
195 phydev->speed);
196}
197
196/** 198/**
197 * stmmac_adjust_link 199 * stmmac_adjust_link
198 * @dev: net device structure 200 * @dev: net device structure
@@ -202,7 +204,6 @@ static void stmmac_adjust_link(struct net_device *dev)
202{ 204{
203 struct stmmac_priv *priv = netdev_priv(dev); 205 struct stmmac_priv *priv = netdev_priv(dev);
204 struct phy_device *phydev = priv->phydev; 206 struct phy_device *phydev = priv->phydev;
205 unsigned long ioaddr = dev->base_addr;
206 unsigned long flags; 207 unsigned long flags;
207 int new_state = 0; 208 int new_state = 0;
208 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause; 209 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
@@ -215,7 +216,7 @@ static void stmmac_adjust_link(struct net_device *dev)
215 216
216 spin_lock_irqsave(&priv->lock, flags); 217 spin_lock_irqsave(&priv->lock, flags);
217 if (phydev->link) { 218 if (phydev->link) {
218 u32 ctrl = readl(ioaddr + MAC_CTRL_REG); 219 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
219 220
220 /* Now we make sure that we can be in full duplex mode. 221 /* Now we make sure that we can be in full duplex mode.
221 * If not, we operate in half-duplex mode. */ 222 * If not, we operate in half-duplex mode. */
@@ -229,19 +230,20 @@ static void stmmac_adjust_link(struct net_device *dev)
229 } 230 }
230 /* Flow Control operation */ 231 /* Flow Control operation */
231 if (phydev->pause) 232 if (phydev->pause)
232 priv->hw->mac->flow_ctrl(ioaddr, phydev->duplex, 233 priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex,
233 fc, pause_time); 234 fc, pause_time);
234 235
235 if (phydev->speed != priv->speed) { 236 if (phydev->speed != priv->speed) {
236 new_state = 1; 237 new_state = 1;
237 switch (phydev->speed) { 238 switch (phydev->speed) {
238 case 1000: 239 case 1000:
239 if (likely(priv->is_gmac)) 240 if (likely(priv->plat->has_gmac))
240 ctrl &= ~priv->hw->link.port; 241 ctrl &= ~priv->hw->link.port;
242 stmmac_hw_fix_mac_speed(priv);
241 break; 243 break;
242 case 100: 244 case 100:
243 case 10: 245 case 10:
244 if (priv->is_gmac) { 246 if (priv->plat->has_gmac) {
245 ctrl |= priv->hw->link.port; 247 ctrl |= priv->hw->link.port;
246 if (phydev->speed == SPEED_100) { 248 if (phydev->speed == SPEED_100) {
247 ctrl |= priv->hw->link.speed; 249 ctrl |= priv->hw->link.speed;
@@ -251,9 +253,7 @@ static void stmmac_adjust_link(struct net_device *dev)
251 } else { 253 } else {
252 ctrl &= ~priv->hw->link.port; 254 ctrl &= ~priv->hw->link.port;
253 } 255 }
254 if (likely(priv->fix_mac_speed)) 256 stmmac_hw_fix_mac_speed(priv);
255 priv->fix_mac_speed(priv->bsp_priv,
256 phydev->speed);
257 break; 257 break;
258 default: 258 default:
259 if (netif_msg_link(priv)) 259 if (netif_msg_link(priv))
@@ -265,7 +265,7 @@ static void stmmac_adjust_link(struct net_device *dev)
265 priv->speed = phydev->speed; 265 priv->speed = phydev->speed;
266 } 266 }
267 267
268 writel(ctrl, ioaddr + MAC_CTRL_REG); 268 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
269 269
270 if (!priv->oldlink) { 270 if (!priv->oldlink) {
271 new_state = 1; 271 new_state = 1;
@@ -310,7 +310,7 @@ static int stmmac_init_phy(struct net_device *dev)
310 return 0; 310 return 0;
311 } 311 }
312 312
313 snprintf(bus_id, MII_BUS_ID_SIZE, "%x", priv->bus_id); 313 snprintf(bus_id, MII_BUS_ID_SIZE, "%x", priv->plat->bus_id);
314 snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, 314 snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
315 priv->phy_addr); 315 priv->phy_addr);
316 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id); 316 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id);
@@ -342,33 +342,19 @@ static int stmmac_init_phy(struct net_device *dev)
342 return 0; 342 return 0;
343} 343}
344 344
345static inline void stmmac_mac_enable_rx(unsigned long ioaddr) 345static inline void stmmac_enable_mac(void __iomem *ioaddr)
346{ 346{
347 u32 value = readl(ioaddr + MAC_CTRL_REG); 347 u32 value = readl(ioaddr + MAC_CTRL_REG);
348 value |= MAC_RNABLE_RX;
349 /* Set the RE (receive enable bit into the MAC CTRL register). */
350 writel(value, ioaddr + MAC_CTRL_REG);
351}
352 348
353static inline void stmmac_mac_enable_tx(unsigned long ioaddr) 349 value |= MAC_RNABLE_RX | MAC_ENABLE_TX;
354{
355 u32 value = readl(ioaddr + MAC_CTRL_REG);
356 value |= MAC_ENABLE_TX;
357 /* Set the TE (transmit enable bit into the MAC CTRL register). */
358 writel(value, ioaddr + MAC_CTRL_REG); 350 writel(value, ioaddr + MAC_CTRL_REG);
359} 351}
360 352
361static inline void stmmac_mac_disable_rx(unsigned long ioaddr) 353static inline void stmmac_disable_mac(void __iomem *ioaddr)
362{ 354{
363 u32 value = readl(ioaddr + MAC_CTRL_REG); 355 u32 value = readl(ioaddr + MAC_CTRL_REG);
364 value &= ~MAC_RNABLE_RX;
365 writel(value, ioaddr + MAC_CTRL_REG);
366}
367 356
368static inline void stmmac_mac_disable_tx(unsigned long ioaddr) 357 value &= ~(MAC_ENABLE_TX | MAC_RNABLE_RX);
369{
370 u32 value = readl(ioaddr + MAC_CTRL_REG);
371 value &= ~MAC_ENABLE_TX;
372 writel(value, ioaddr + MAC_CTRL_REG); 358 writel(value, ioaddr + MAC_CTRL_REG);
373} 359}
374 360
@@ -567,29 +553,22 @@ static void free_dma_desc_resources(struct stmmac_priv *priv)
567 * stmmac_dma_operation_mode - HW DMA operation mode 553 * stmmac_dma_operation_mode - HW DMA operation mode
568 * @priv : pointer to the private device structure. 554 * @priv : pointer to the private device structure.
569 * Description: it sets the DMA operation mode: tx/rx DMA thresholds 555 * Description: it sets the DMA operation mode: tx/rx DMA thresholds
570 * or Store-And-Forward capability. It also verifies the COE for the 556 * or Store-And-Forward capability.
571 * transmission in case of Giga ETH.
572 */ 557 */
573static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 558static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
574{ 559{
575 if (!priv->is_gmac) { 560 if (likely((priv->plat->tx_coe) && (!priv->no_csum_insertion))) {
576 /* MAC 10/100 */ 561 /* In case of GMAC, SF mode has to be enabled
577 priv->hw->dma->dma_mode(priv->dev->base_addr, tc, 0); 562 * to perform the TX COE. This depends on:
578 priv->tx_coe = NO_HW_CSUM; 563 * 1) TX COE if actually supported
579 } else { 564 * 2) There is no bugged Jumbo frame support
580 if ((priv->dev->mtu <= ETH_DATA_LEN) && (tx_coe)) { 565 * that needs to not insert csum in the TDES.
581 priv->hw->dma->dma_mode(priv->dev->base_addr, 566 */
582 SF_DMA_MODE, SF_DMA_MODE); 567 priv->hw->dma->dma_mode(priv->ioaddr,
583 tc = SF_DMA_MODE; 568 SF_DMA_MODE, SF_DMA_MODE);
584 priv->tx_coe = HW_CSUM; 569 tc = SF_DMA_MODE;
585 } else { 570 } else
586 /* Checksum computation is performed in software. */ 571 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
587 priv->hw->dma->dma_mode(priv->dev->base_addr, tc,
588 SF_DMA_MODE);
589 priv->tx_coe = NO_HW_CSUM;
590 }
591 }
592 tx_coe = priv->tx_coe;
593} 572}
594 573
595/** 574/**
@@ -600,7 +579,6 @@ static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
600static void stmmac_tx(struct stmmac_priv *priv) 579static void stmmac_tx(struct stmmac_priv *priv)
601{ 580{
602 unsigned int txsize = priv->dma_tx_size; 581 unsigned int txsize = priv->dma_tx_size;
603 unsigned long ioaddr = priv->dev->base_addr;
604 582
605 while (priv->dirty_tx != priv->cur_tx) { 583 while (priv->dirty_tx != priv->cur_tx) {
606 int last; 584 int last;
@@ -618,7 +596,7 @@ static void stmmac_tx(struct stmmac_priv *priv)
618 int tx_error = 596 int tx_error =
619 priv->hw->desc->tx_status(&priv->dev->stats, 597 priv->hw->desc->tx_status(&priv->dev->stats,
620 &priv->xstats, p, 598 &priv->xstats, p,
621 ioaddr); 599 priv->ioaddr);
622 if (likely(tx_error == 0)) { 600 if (likely(tx_error == 0)) {
623 priv->dev->stats.tx_packets++; 601 priv->dev->stats.tx_packets++;
624 priv->xstats.tx_pkt_n++; 602 priv->xstats.tx_pkt_n++;
@@ -674,7 +652,7 @@ static inline void stmmac_enable_irq(struct stmmac_priv *priv)
674 priv->tm->timer_start(tmrate); 652 priv->tm->timer_start(tmrate);
675 else 653 else
676#endif 654#endif
677 priv->hw->dma->enable_dma_irq(priv->dev->base_addr); 655 priv->hw->dma->enable_dma_irq(priv->ioaddr);
678} 656}
679 657
680static inline void stmmac_disable_irq(struct stmmac_priv *priv) 658static inline void stmmac_disable_irq(struct stmmac_priv *priv)
@@ -684,7 +662,7 @@ static inline void stmmac_disable_irq(struct stmmac_priv *priv)
684 priv->tm->timer_stop(); 662 priv->tm->timer_stop();
685 else 663 else
686#endif 664#endif
687 priv->hw->dma->disable_dma_irq(priv->dev->base_addr); 665 priv->hw->dma->disable_dma_irq(priv->ioaddr);
688} 666}
689 667
690static int stmmac_has_work(struct stmmac_priv *priv) 668static int stmmac_has_work(struct stmmac_priv *priv)
@@ -739,14 +717,15 @@ static void stmmac_no_timer_stopped(void)
739 */ 717 */
740static void stmmac_tx_err(struct stmmac_priv *priv) 718static void stmmac_tx_err(struct stmmac_priv *priv)
741{ 719{
720
742 netif_stop_queue(priv->dev); 721 netif_stop_queue(priv->dev);
743 722
744 priv->hw->dma->stop_tx(priv->dev->base_addr); 723 priv->hw->dma->stop_tx(priv->ioaddr);
745 dma_free_tx_skbufs(priv); 724 dma_free_tx_skbufs(priv);
746 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size); 725 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
747 priv->dirty_tx = 0; 726 priv->dirty_tx = 0;
748 priv->cur_tx = 0; 727 priv->cur_tx = 0;
749 priv->hw->dma->start_tx(priv->dev->base_addr); 728 priv->hw->dma->start_tx(priv->ioaddr);
750 729
751 priv->dev->stats.tx_errors++; 730 priv->dev->stats.tx_errors++;
752 netif_wake_queue(priv->dev); 731 netif_wake_queue(priv->dev);
@@ -755,11 +734,9 @@ static void stmmac_tx_err(struct stmmac_priv *priv)
755 734
756static void stmmac_dma_interrupt(struct stmmac_priv *priv) 735static void stmmac_dma_interrupt(struct stmmac_priv *priv)
757{ 736{
758 unsigned long ioaddr = priv->dev->base_addr;
759 int status; 737 int status;
760 738
761 status = priv->hw->dma->dma_interrupt(priv->dev->base_addr, 739 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
762 &priv->xstats);
763 if (likely(status == handle_tx_rx)) 740 if (likely(status == handle_tx_rx))
764 _stmmac_schedule(priv); 741 _stmmac_schedule(priv);
765 742
@@ -767,10 +744,9 @@ static void stmmac_dma_interrupt(struct stmmac_priv *priv)
767 /* Try to bump up the dma threshold on this failure */ 744 /* Try to bump up the dma threshold on this failure */
768 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) { 745 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
769 tc += 64; 746 tc += 64;
770 priv->hw->dma->dma_mode(ioaddr, tc, SF_DMA_MODE); 747 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
771 priv->xstats.threshold = tc; 748 priv->xstats.threshold = tc;
772 } 749 }
773 stmmac_tx_err(priv);
774 } else if (unlikely(status == tx_hard_error)) 750 } else if (unlikely(status == tx_hard_error))
775 stmmac_tx_err(priv); 751 stmmac_tx_err(priv);
776} 752}
@@ -787,7 +763,6 @@ static void stmmac_dma_interrupt(struct stmmac_priv *priv)
787static int stmmac_open(struct net_device *dev) 763static int stmmac_open(struct net_device *dev)
788{ 764{
789 struct stmmac_priv *priv = netdev_priv(dev); 765 struct stmmac_priv *priv = netdev_priv(dev);
790 unsigned long ioaddr = dev->base_addr;
791 int ret; 766 int ret;
792 767
793 /* Check that the MAC address is valid. If its not, refuse 768 /* Check that the MAC address is valid. If its not, refuse
@@ -802,21 +777,6 @@ static int stmmac_open(struct net_device *dev)
802 777
803 stmmac_verify_args(); 778 stmmac_verify_args();
804 779
805 ret = stmmac_init_phy(dev);
806 if (unlikely(ret)) {
807 pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret);
808 return ret;
809 }
810
811 /* Request the IRQ lines */
812 ret = request_irq(dev->irq, stmmac_interrupt,
813 IRQF_SHARED, dev->name, dev);
814 if (unlikely(ret < 0)) {
815 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
816 __func__, dev->irq, ret);
817 return ret;
818 }
819
820#ifdef CONFIG_STMMAC_TIMER 780#ifdef CONFIG_STMMAC_TIMER
821 priv->tm = kzalloc(sizeof(struct stmmac_timer *), GFP_KERNEL); 781 priv->tm = kzalloc(sizeof(struct stmmac_timer *), GFP_KERNEL);
822 if (unlikely(priv->tm == NULL)) { 782 if (unlikely(priv->tm == NULL)) {
@@ -835,6 +795,11 @@ static int stmmac_open(struct net_device *dev)
835 } else 795 } else
836 priv->tm->enable = 1; 796 priv->tm->enable = 1;
837#endif 797#endif
798 ret = stmmac_init_phy(dev);
799 if (unlikely(ret)) {
800 pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret);
801 goto open_error;
802 }
838 803
839 /* Create and initialize the TX/RX descriptors chains. */ 804 /* Create and initialize the TX/RX descriptors chains. */
840 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize); 805 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
@@ -843,30 +808,43 @@ static int stmmac_open(struct net_device *dev)
843 init_dma_desc_rings(dev); 808 init_dma_desc_rings(dev);
844 809
845 /* DMA initialization and SW reset */ 810 /* DMA initialization and SW reset */
846 if (unlikely(priv->hw->dma->init(ioaddr, priv->pbl, priv->dma_tx_phy, 811 ret = priv->hw->dma->init(priv->ioaddr, priv->plat->pbl,
847 priv->dma_rx_phy) < 0)) { 812 priv->dma_tx_phy, priv->dma_rx_phy);
848 813 if (ret < 0) {
849 pr_err("%s: DMA initialization failed\n", __func__); 814 pr_err("%s: DMA initialization failed\n", __func__);
850 return -1; 815 goto open_error;
851 } 816 }
852 817
853 /* Copy the MAC addr into the HW */ 818 /* Copy the MAC addr into the HW */
854 priv->hw->mac->set_umac_addr(ioaddr, dev->dev_addr, 0); 819 priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
855 /* If required, perform hw setup of the bus. */ 820 /* If required, perform hw setup of the bus. */
856 if (priv->bus_setup) 821 if (priv->plat->bus_setup)
857 priv->bus_setup(ioaddr); 822 priv->plat->bus_setup(priv->ioaddr);
858 /* Initialize the MAC Core */ 823 /* Initialize the MAC Core */
859 priv->hw->mac->core_init(ioaddr); 824 priv->hw->mac->core_init(priv->ioaddr);
860 825
861 priv->shutdown = 0; 826 priv->rx_coe = priv->hw->mac->rx_coe(priv->ioaddr);
827 if (priv->rx_coe)
828 pr_info("stmmac: Rx Checksum Offload Engine supported\n");
829 if (priv->plat->tx_coe)
830 pr_info("\tTX Checksum insertion supported\n");
831 netdev_update_features(dev);
862 832
863 /* Initialise the MMC (if present) to disable all interrupts. */ 833 /* Initialise the MMC (if present) to disable all interrupts. */
864 writel(0xffffffff, ioaddr + MMC_HIGH_INTR_MASK); 834 writel(0xffffffff, priv->ioaddr + MMC_HIGH_INTR_MASK);
865 writel(0xffffffff, ioaddr + MMC_LOW_INTR_MASK); 835 writel(0xffffffff, priv->ioaddr + MMC_LOW_INTR_MASK);
836
837 /* Request the IRQ lines */
838 ret = request_irq(dev->irq, stmmac_interrupt,
839 IRQF_SHARED, dev->name, dev);
840 if (unlikely(ret < 0)) {
841 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
842 __func__, dev->irq, ret);
843 goto open_error;
844 }
866 845
867 /* Enable the MAC Rx/Tx */ 846 /* Enable the MAC Rx/Tx */
868 stmmac_mac_enable_rx(ioaddr); 847 stmmac_enable_mac(priv->ioaddr);
869 stmmac_mac_enable_tx(ioaddr);
870 848
871 /* Set the HW DMA mode and the COE */ 849 /* Set the HW DMA mode and the COE */
872 stmmac_dma_operation_mode(priv); 850 stmmac_dma_operation_mode(priv);
@@ -877,16 +855,16 @@ static int stmmac_open(struct net_device *dev)
877 855
878 /* Start the ball rolling... */ 856 /* Start the ball rolling... */
879 DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name); 857 DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
880 priv->hw->dma->start_tx(ioaddr); 858 priv->hw->dma->start_tx(priv->ioaddr);
881 priv->hw->dma->start_rx(ioaddr); 859 priv->hw->dma->start_rx(priv->ioaddr);
882 860
883#ifdef CONFIG_STMMAC_TIMER 861#ifdef CONFIG_STMMAC_TIMER
884 priv->tm->timer_start(tmrate); 862 priv->tm->timer_start(tmrate);
885#endif 863#endif
886 /* Dump DMA/MAC registers */ 864 /* Dump DMA/MAC registers */
887 if (netif_msg_hw(priv)) { 865 if (netif_msg_hw(priv)) {
888 priv->hw->mac->dump_regs(ioaddr); 866 priv->hw->mac->dump_regs(priv->ioaddr);
889 priv->hw->dma->dump_regs(ioaddr); 867 priv->hw->dma->dump_regs(priv->ioaddr);
890 } 868 }
891 869
892 if (priv->phydev) 870 if (priv->phydev)
@@ -895,7 +873,17 @@ static int stmmac_open(struct net_device *dev)
895 napi_enable(&priv->napi); 873 napi_enable(&priv->napi);
896 skb_queue_head_init(&priv->rx_recycle); 874 skb_queue_head_init(&priv->rx_recycle);
897 netif_start_queue(dev); 875 netif_start_queue(dev);
876
898 return 0; 877 return 0;
878
879open_error:
880#ifdef CONFIG_STMMAC_TIMER
881 kfree(priv->tm);
882#endif
883 if (priv->phydev)
884 phy_disconnect(priv->phydev);
885
886 return ret;
899} 887}
900 888
901/** 889/**
@@ -930,61 +918,20 @@ static int stmmac_release(struct net_device *dev)
930 free_irq(dev->irq, dev); 918 free_irq(dev->irq, dev);
931 919
932 /* Stop TX/RX DMA and clear the descriptors */ 920 /* Stop TX/RX DMA and clear the descriptors */
933 priv->hw->dma->stop_tx(dev->base_addr); 921 priv->hw->dma->stop_tx(priv->ioaddr);
934 priv->hw->dma->stop_rx(dev->base_addr); 922 priv->hw->dma->stop_rx(priv->ioaddr);
935 923
936 /* Release and free the Rx/Tx resources */ 924 /* Release and free the Rx/Tx resources */
937 free_dma_desc_resources(priv); 925 free_dma_desc_resources(priv);
938 926
939 /* Disable the MAC core */ 927 /* Disable the MAC Rx/Tx */
940 stmmac_mac_disable_tx(dev->base_addr); 928 stmmac_disable_mac(priv->ioaddr);
941 stmmac_mac_disable_rx(dev->base_addr);
942 929
943 netif_carrier_off(dev); 930 netif_carrier_off(dev);
944 931
945 return 0; 932 return 0;
946} 933}
947 934
948/*
949 * To perform emulated hardware segmentation on skb.
950 */
951static int stmmac_sw_tso(struct stmmac_priv *priv, struct sk_buff *skb)
952{
953 struct sk_buff *segs, *curr_skb;
954 int gso_segs = skb_shinfo(skb)->gso_segs;
955
956 /* Estimate the number of fragments in the worst case */
957 if (unlikely(stmmac_tx_avail(priv) < gso_segs)) {
958 netif_stop_queue(priv->dev);
959 TX_DBG(KERN_ERR "%s: TSO BUG! Tx Ring full when queue awake\n",
960 __func__);
961 if (stmmac_tx_avail(priv) < gso_segs)
962 return NETDEV_TX_BUSY;
963
964 netif_wake_queue(priv->dev);
965 }
966 TX_DBG("\tstmmac_sw_tso: segmenting: skb %p (len %d)\n",
967 skb, skb->len);
968
969 segs = skb_gso_segment(skb, priv->dev->features & ~NETIF_F_TSO);
970 if (unlikely(IS_ERR(segs)))
971 goto sw_tso_end;
972
973 do {
974 curr_skb = segs;
975 segs = segs->next;
976 TX_DBG("\t\tcurrent skb->len: %d, *curr %p,"
977 "*next %p\n", curr_skb->len, curr_skb, segs);
978 curr_skb->next = NULL;
979 stmmac_xmit(curr_skb, priv->dev);
980 } while (segs);
981
982sw_tso_end:
983 dev_kfree_skb(skb);
984
985 return NETDEV_TX_OK;
986}
987
988static unsigned int stmmac_handle_jumbo_frames(struct sk_buff *skb, 935static unsigned int stmmac_handle_jumbo_frames(struct sk_buff *skb,
989 struct net_device *dev, 936 struct net_device *dev,
990 int csum_insertion) 937 int csum_insertion)
@@ -1062,15 +1009,7 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1062 !skb_is_gso(skb) ? "isn't" : "is"); 1009 !skb_is_gso(skb) ? "isn't" : "is");
1063#endif 1010#endif
1064 1011
1065 if (unlikely(skb_is_gso(skb))) 1012 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1066 return stmmac_sw_tso(priv, skb);
1067
1068 if (likely((skb->ip_summed == CHECKSUM_PARTIAL))) {
1069 if (likely(priv->tx_coe == NO_HW_CSUM))
1070 skb_checksum_help(skb);
1071 else
1072 csum_insertion = 1;
1073 }
1074 1013
1075 desc = priv->dma_tx + entry; 1014 desc = priv->dma_tx + entry;
1076 first = desc; 1015 first = desc;
@@ -1140,7 +1079,7 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1140 1079
1141 dev->stats.tx_bytes += skb->len; 1080 dev->stats.tx_bytes += skb->len;
1142 1081
1143 priv->hw->dma->enable_dma_transmission(dev->base_addr); 1082 priv->hw->dma->enable_dma_transmission(priv->ioaddr);
1144 1083
1145 return NETDEV_TX_OK; 1084 return NETDEV_TX_OK;
1146} 1085}
@@ -1170,7 +1109,7 @@ static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1170 DMA_FROM_DEVICE); 1109 DMA_FROM_DEVICE);
1171 1110
1172 (p + entry)->des2 = priv->rx_skbuff_dma[entry]; 1111 (p + entry)->des2 = priv->rx_skbuff_dma[entry];
1173 if (unlikely(priv->is_gmac)) { 1112 if (unlikely(priv->plat->has_gmac)) {
1174 if (bfsize >= BUF_SIZE_8KiB) 1113 if (bfsize >= BUF_SIZE_8KiB)
1175 (p + entry)->des3 = 1114 (p + entry)->des3 =
1176 (p + entry)->des2 + BUF_SIZE_8KiB; 1115 (p + entry)->des2 + BUF_SIZE_8KiB;
@@ -1256,7 +1195,7 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit)
1256 1195
1257 if (unlikely(status == csum_none)) { 1196 if (unlikely(status == csum_none)) {
1258 /* always for the old mac 10/100 */ 1197 /* always for the old mac 10/100 */
1259 skb->ip_summed = CHECKSUM_NONE; 1198 skb_checksum_none_assert(skb);
1260 netif_receive_skb(skb); 1199 netif_receive_skb(skb);
1261 } else { 1200 } else {
1262 skb->ip_summed = CHECKSUM_UNNECESSARY; 1201 skb->ip_summed = CHECKSUM_UNNECESSARY;
@@ -1380,7 +1319,7 @@ static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
1380 return -EBUSY; 1319 return -EBUSY;
1381 } 1320 }
1382 1321
1383 if (priv->is_gmac) 1322 if (priv->plat->has_gmac)
1384 max_mtu = JUMBO_LEN; 1323 max_mtu = JUMBO_LEN;
1385 else 1324 else
1386 max_mtu = ETH_DATA_LEN; 1325 max_mtu = ETH_DATA_LEN;
@@ -1391,10 +1330,30 @@ static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
1391 } 1330 }
1392 1331
1393 dev->mtu = new_mtu; 1332 dev->mtu = new_mtu;
1333 netdev_update_features(dev);
1394 1334
1395 return 0; 1335 return 0;
1396} 1336}
1397 1337
1338static u32 stmmac_fix_features(struct net_device *dev, u32 features)
1339{
1340 struct stmmac_priv *priv = netdev_priv(dev);
1341
1342 if (!priv->rx_coe)
1343 features &= ~NETIF_F_RXCSUM;
1344 if (!priv->plat->tx_coe)
1345 features &= ~NETIF_F_ALL_CSUM;
1346
1347 /* Some GMAC devices have a bugged Jumbo frame support that
1348 * needs to have the Tx COE disabled for oversized frames
1349 * (due to limited buffer sizes). In this case we disable
1350 * the TX csum insertionin the TDES and not use SF. */
1351 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
1352 features &= ~NETIF_F_ALL_CSUM;
1353
1354 return features;
1355}
1356
1398static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 1357static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
1399{ 1358{
1400 struct net_device *dev = (struct net_device *)dev_id; 1359 struct net_device *dev = (struct net_device *)dev_id;
@@ -1405,11 +1364,9 @@ static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
1405 return IRQ_NONE; 1364 return IRQ_NONE;
1406 } 1365 }
1407 1366
1408 if (priv->is_gmac) { 1367 if (priv->plat->has_gmac)
1409 unsigned long ioaddr = dev->base_addr;
1410 /* To handle GMAC own interrupts */ 1368 /* To handle GMAC own interrupts */
1411 priv->hw->mac->host_irq_status(ioaddr); 1369 priv->hw->mac->host_irq_status((void __iomem *) dev->base_addr);
1412 }
1413 1370
1414 stmmac_dma_interrupt(priv); 1371 stmmac_dma_interrupt(priv);
1415 1372
@@ -1474,6 +1431,7 @@ static const struct net_device_ops stmmac_netdev_ops = {
1474 .ndo_start_xmit = stmmac_xmit, 1431 .ndo_start_xmit = stmmac_xmit,
1475 .ndo_stop = stmmac_release, 1432 .ndo_stop = stmmac_release,
1476 .ndo_change_mtu = stmmac_change_mtu, 1433 .ndo_change_mtu = stmmac_change_mtu,
1434 .ndo_fix_features = stmmac_fix_features,
1477 .ndo_set_multicast_list = stmmac_multicast_list, 1435 .ndo_set_multicast_list = stmmac_multicast_list,
1478 .ndo_tx_timeout = stmmac_tx_timeout, 1436 .ndo_tx_timeout = stmmac_tx_timeout,
1479 .ndo_do_ioctl = stmmac_ioctl, 1437 .ndo_do_ioctl = stmmac_ioctl,
@@ -1504,7 +1462,8 @@ static int stmmac_probe(struct net_device *dev)
1504 dev->netdev_ops = &stmmac_netdev_ops; 1462 dev->netdev_ops = &stmmac_netdev_ops;
1505 stmmac_set_ethtool_ops(dev); 1463 stmmac_set_ethtool_ops(dev);
1506 1464
1507 dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA); 1465 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1466 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
1508 dev->watchdog_timeo = msecs_to_jiffies(watchdog); 1467 dev->watchdog_timeo = msecs_to_jiffies(watchdog);
1509#ifdef STMMAC_VLAN_TAG_USED 1468#ifdef STMMAC_VLAN_TAG_USED
1510 /* Both mac100 and gmac support receive VLAN tag detection */ 1469 /* Both mac100 and gmac support receive VLAN tag detection */
@@ -1512,9 +1471,6 @@ static int stmmac_probe(struct net_device *dev)
1512#endif 1471#endif
1513 priv->msg_enable = netif_msg_init(debug, default_msg_level); 1472 priv->msg_enable = netif_msg_init(debug, default_msg_level);
1514 1473
1515 if (priv->is_gmac)
1516 priv->rx_csum = 1;
1517
1518 if (flow_ctrl) 1474 if (flow_ctrl)
1519 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 1475 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
1520 1476
@@ -1522,12 +1478,15 @@ static int stmmac_probe(struct net_device *dev)
1522 netif_napi_add(dev, &priv->napi, stmmac_poll, 64); 1478 netif_napi_add(dev, &priv->napi, stmmac_poll, 64);
1523 1479
1524 /* Get the MAC address */ 1480 /* Get the MAC address */
1525 priv->hw->mac->get_umac_addr(dev->base_addr, dev->dev_addr, 0); 1481 priv->hw->mac->get_umac_addr((void __iomem *) dev->base_addr,
1482 dev->dev_addr, 0);
1526 1483
1527 if (!is_valid_ether_addr(dev->dev_addr)) 1484 if (!is_valid_ether_addr(dev->dev_addr))
1528 pr_warning("\tno valid MAC address;" 1485 pr_warning("\tno valid MAC address;"
1529 "please, use ifconfig or nwhwconfig!\n"); 1486 "please, use ifconfig or nwhwconfig!\n");
1530 1487
1488 spin_lock_init(&priv->lock);
1489
1531 ret = register_netdev(dev); 1490 ret = register_netdev(dev);
1532 if (ret) { 1491 if (ret) {
1533 pr_err("%s: ERROR %i registering the device\n", 1492 pr_err("%s: ERROR %i registering the device\n",
@@ -1537,9 +1496,7 @@ static int stmmac_probe(struct net_device *dev)
1537 1496
1538 DBG(probe, DEBUG, "%s: Scatter/Gather: %s - HW checksums: %s\n", 1497 DBG(probe, DEBUG, "%s: Scatter/Gather: %s - HW checksums: %s\n",
1539 dev->name, (dev->features & NETIF_F_SG) ? "on" : "off", 1498 dev->name, (dev->features & NETIF_F_SG) ? "on" : "off",
1540 (dev->features & NETIF_F_HW_CSUM) ? "on" : "off"); 1499 (dev->features & NETIF_F_IP_CSUM) ? "on" : "off");
1541
1542 spin_lock_init(&priv->lock);
1543 1500
1544 return ret; 1501 return ret;
1545} 1502}
@@ -1552,19 +1509,18 @@ static int stmmac_probe(struct net_device *dev)
1552static int stmmac_mac_device_setup(struct net_device *dev) 1509static int stmmac_mac_device_setup(struct net_device *dev)
1553{ 1510{
1554 struct stmmac_priv *priv = netdev_priv(dev); 1511 struct stmmac_priv *priv = netdev_priv(dev);
1555 unsigned long ioaddr = dev->base_addr;
1556 1512
1557 struct mac_device_info *device; 1513 struct mac_device_info *device;
1558 1514
1559 if (priv->is_gmac) 1515 if (priv->plat->has_gmac)
1560 device = dwmac1000_setup(ioaddr); 1516 device = dwmac1000_setup(priv->ioaddr);
1561 else 1517 else
1562 device = dwmac100_setup(ioaddr); 1518 device = dwmac100_setup(priv->ioaddr);
1563 1519
1564 if (!device) 1520 if (!device)
1565 return -ENOMEM; 1521 return -ENOMEM;
1566 1522
1567 if (priv->enh_desc) { 1523 if (priv->plat->enh_desc) {
1568 device->desc = &enh_desc_ops; 1524 device->desc = &enh_desc_ops;
1569 pr_info("\tEnhanced descriptor structure\n"); 1525 pr_info("\tEnhanced descriptor structure\n");
1570 } else 1526 } else
@@ -1572,9 +1528,10 @@ static int stmmac_mac_device_setup(struct net_device *dev)
1572 1528
1573 priv->hw = device; 1529 priv->hw = device;
1574 1530
1575 priv->wolenabled = priv->hw->pmt; /* PMT supported */ 1531 if (device_can_wakeup(priv->device)) {
1576 if (priv->wolenabled == PMT_SUPPORTED) 1532 priv->wolopts = WAKE_MAGIC; /* Magic Frame as default */
1577 priv->wolopts = WAKE_MAGIC; /* Magic Frame */ 1533 enable_irq_wake(dev->irq);
1534 }
1578 1535
1579 return 0; 1536 return 0;
1580} 1537}
@@ -1619,7 +1576,7 @@ static int stmmac_associate_phy(struct device *dev, void *data)
1619 plat_dat->bus_id); 1576 plat_dat->bus_id);
1620 1577
1621 /* Check that this phy is for the MAC being initialised */ 1578 /* Check that this phy is for the MAC being initialised */
1622 if (priv->bus_id != plat_dat->bus_id) 1579 if (priv->plat->bus_id != plat_dat->bus_id)
1623 return 0; 1580 return 0;
1624 1581
1625 /* OK, this PHY is connected to the MAC. 1582 /* OK, this PHY is connected to the MAC.
@@ -1653,40 +1610,37 @@ static int stmmac_dvr_probe(struct platform_device *pdev)
1653{ 1610{
1654 int ret = 0; 1611 int ret = 0;
1655 struct resource *res; 1612 struct resource *res;
1656 unsigned int *addr = NULL; 1613 void __iomem *addr = NULL;
1657 struct net_device *ndev = NULL; 1614 struct net_device *ndev = NULL;
1658 struct stmmac_priv *priv; 1615 struct stmmac_priv *priv = NULL;
1659 struct plat_stmmacenet_data *plat_dat; 1616 struct plat_stmmacenet_data *plat_dat;
1660 1617
1661 pr_info("STMMAC driver:\n\tplatform registration... "); 1618 pr_info("STMMAC driver:\n\tplatform registration... ");
1662 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1619 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1663 if (!res) { 1620 if (!res)
1664 ret = -ENODEV; 1621 return -ENODEV;
1665 goto out; 1622 pr_info("\tdone!\n");
1666 }
1667 pr_info("done!\n");
1668 1623
1669 if (!request_mem_region(res->start, resource_size(res), 1624 if (!request_mem_region(res->start, resource_size(res),
1670 pdev->name)) { 1625 pdev->name)) {
1671 pr_err("%s: ERROR: memory allocation failed" 1626 pr_err("%s: ERROR: memory allocation failed"
1672 "cannot get the I/O addr 0x%x\n", 1627 "cannot get the I/O addr 0x%x\n",
1673 __func__, (unsigned int)res->start); 1628 __func__, (unsigned int)res->start);
1674 ret = -EBUSY; 1629 return -EBUSY;
1675 goto out;
1676 } 1630 }
1677 1631
1678 addr = ioremap(res->start, resource_size(res)); 1632 addr = ioremap(res->start, resource_size(res));
1679 if (!addr) { 1633 if (!addr) {
1680 pr_err("%s: ERROR: memory mapping failed\n", __func__); 1634 pr_err("%s: ERROR: memory mapping failed\n", __func__);
1681 ret = -ENOMEM; 1635 ret = -ENOMEM;
1682 goto out; 1636 goto out_release_region;
1683 } 1637 }
1684 1638
1685 ndev = alloc_etherdev(sizeof(struct stmmac_priv)); 1639 ndev = alloc_etherdev(sizeof(struct stmmac_priv));
1686 if (!ndev) { 1640 if (!ndev) {
1687 pr_err("%s: ERROR: allocating the device\n", __func__); 1641 pr_err("%s: ERROR: allocating the device\n", __func__);
1688 ret = -ENOMEM; 1642 ret = -ENOMEM;
1689 goto out; 1643 goto out_unmap;
1690 } 1644 }
1691 1645
1692 SET_NETDEV_DEV(ndev, &pdev->dev); 1646 SET_NETDEV_DEV(ndev, &pdev->dev);
@@ -1696,38 +1650,46 @@ static int stmmac_dvr_probe(struct platform_device *pdev)
1696 if (ndev->irq == -ENXIO) { 1650 if (ndev->irq == -ENXIO) {
1697 pr_err("%s: ERROR: MAC IRQ configuration " 1651 pr_err("%s: ERROR: MAC IRQ configuration "
1698 "information not found\n", __func__); 1652 "information not found\n", __func__);
1699 ret = -ENODEV; 1653 ret = -ENXIO;
1700 goto out; 1654 goto out_free_ndev;
1701 } 1655 }
1702 1656
1703 priv = netdev_priv(ndev); 1657 priv = netdev_priv(ndev);
1704 priv->device = &(pdev->dev); 1658 priv->device = &(pdev->dev);
1705 priv->dev = ndev; 1659 priv->dev = ndev;
1706 plat_dat = pdev->dev.platform_data; 1660 plat_dat = pdev->dev.platform_data;
1707 priv->bus_id = plat_dat->bus_id; 1661
1708 priv->pbl = plat_dat->pbl; /* TLI */ 1662 priv->plat = plat_dat;
1709 priv->is_gmac = plat_dat->has_gmac; /* GMAC is on board */ 1663
1710 priv->enh_desc = plat_dat->enh_desc; 1664 priv->ioaddr = addr;
1665
1666 /* PMT module is not integrated in all the MAC devices. */
1667 if (plat_dat->pmt) {
1668 pr_info("\tPMT module supported\n");
1669 device_set_wakeup_capable(&pdev->dev, 1);
1670 }
1711 1671
1712 platform_set_drvdata(pdev, ndev); 1672 platform_set_drvdata(pdev, ndev);
1713 1673
1714 /* Set the I/O base addr */ 1674 /* Set the I/O base addr */
1715 ndev->base_addr = (unsigned long)addr; 1675 ndev->base_addr = (unsigned long)addr;
1716 1676
1717 /* Verify embedded resource for the platform */ 1677 /* Custom initialisation */
1718 ret = stmmac_claim_resource(pdev); 1678 if (priv->plat->init) {
1719 if (ret < 0) 1679 ret = priv->plat->init(pdev);
1720 goto out; 1680 if (unlikely(ret))
1681 goto out_free_ndev;
1682 }
1721 1683
1722 /* MAC HW revice detection */ 1684 /* MAC HW revice detection */
1723 ret = stmmac_mac_device_setup(ndev); 1685 ret = stmmac_mac_device_setup(ndev);
1724 if (ret < 0) 1686 if (ret < 0)
1725 goto out; 1687 goto out_plat_exit;
1726 1688
1727 /* Network Device Registration */ 1689 /* Network Device Registration */
1728 ret = stmmac_probe(ndev); 1690 ret = stmmac_probe(ndev);
1729 if (ret < 0) 1691 if (ret < 0)
1730 goto out; 1692 goto out_plat_exit;
1731 1693
1732 /* associate a PHY - it is provided by another platform bus */ 1694 /* associate a PHY - it is provided by another platform bus */
1733 if (!driver_for_each_device 1695 if (!driver_for_each_device
@@ -1735,31 +1697,33 @@ static int stmmac_dvr_probe(struct platform_device *pdev)
1735 stmmac_associate_phy)) { 1697 stmmac_associate_phy)) {
1736 pr_err("No PHY device is associated with this MAC!\n"); 1698 pr_err("No PHY device is associated with this MAC!\n");
1737 ret = -ENODEV; 1699 ret = -ENODEV;
1738 goto out; 1700 goto out_unregister;
1739 } 1701 }
1740 1702
1741 priv->fix_mac_speed = plat_dat->fix_mac_speed;
1742 priv->bus_setup = plat_dat->bus_setup;
1743 priv->bsp_priv = plat_dat->bsp_priv;
1744
1745 pr_info("\t%s - (dev. name: %s - id: %d, IRQ #%d\n" 1703 pr_info("\t%s - (dev. name: %s - id: %d, IRQ #%d\n"
1746 "\tIO base addr: 0x%08x)\n", ndev->name, pdev->name, 1704 "\tIO base addr: 0x%p)\n", ndev->name, pdev->name,
1747 pdev->id, ndev->irq, (unsigned int)addr); 1705 pdev->id, ndev->irq, addr);
1748 1706
1749 /* MDIO bus Registration */ 1707 /* MDIO bus Registration */
1750 pr_debug("\tMDIO bus (id: %d)...", priv->bus_id); 1708 pr_debug("\tMDIO bus (id: %d)...", priv->plat->bus_id);
1751 ret = stmmac_mdio_register(ndev); 1709 ret = stmmac_mdio_register(ndev);
1752 if (ret < 0) 1710 if (ret < 0)
1753 goto out; 1711 goto out_unregister;
1754 pr_debug("registered!\n"); 1712 pr_debug("registered!\n");
1713 return 0;
1755 1714
1756out: 1715out_unregister:
1757 if (ret < 0) { 1716 unregister_netdev(ndev);
1758 platform_set_drvdata(pdev, NULL); 1717out_plat_exit:
1759 release_mem_region(res->start, resource_size(res)); 1718 if (priv->plat->exit)
1760 if (addr != NULL) 1719 priv->plat->exit(pdev);
1761 iounmap(addr); 1720out_free_ndev:
1762 } 1721 free_netdev(ndev);
1722 platform_set_drvdata(pdev, NULL);
1723out_unmap:
1724 iounmap(addr);
1725out_release_region:
1726 release_mem_region(res->start, resource_size(res));
1763 1727
1764 return ret; 1728 return ret;
1765} 1729}
@@ -1779,20 +1743,22 @@ static int stmmac_dvr_remove(struct platform_device *pdev)
1779 1743
1780 pr_info("%s:\n\tremoving driver", __func__); 1744 pr_info("%s:\n\tremoving driver", __func__);
1781 1745
1782 priv->hw->dma->stop_rx(ndev->base_addr); 1746 priv->hw->dma->stop_rx(priv->ioaddr);
1783 priv->hw->dma->stop_tx(ndev->base_addr); 1747 priv->hw->dma->stop_tx(priv->ioaddr);
1784 1748
1785 stmmac_mac_disable_rx(ndev->base_addr); 1749 stmmac_disable_mac(priv->ioaddr);
1786 stmmac_mac_disable_tx(ndev->base_addr);
1787 1750
1788 netif_carrier_off(ndev); 1751 netif_carrier_off(ndev);
1789 1752
1790 stmmac_mdio_unregister(ndev); 1753 stmmac_mdio_unregister(ndev);
1791 1754
1755 if (priv->plat->exit)
1756 priv->plat->exit(pdev);
1757
1792 platform_set_drvdata(pdev, NULL); 1758 platform_set_drvdata(pdev, NULL);
1793 unregister_netdev(ndev); 1759 unregister_netdev(ndev);
1794 1760
1795 iounmap((void *)ndev->base_addr); 1761 iounmap((void *)priv->ioaddr);
1796 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1762 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1797 release_mem_region(res->start, resource_size(res)); 1763 release_mem_region(res->start, resource_size(res));
1798 1764
@@ -1802,75 +1768,54 @@ static int stmmac_dvr_remove(struct platform_device *pdev)
1802} 1768}
1803 1769
1804#ifdef CONFIG_PM 1770#ifdef CONFIG_PM
1805static int stmmac_suspend(struct platform_device *pdev, pm_message_t state) 1771static int stmmac_suspend(struct device *dev)
1806{ 1772{
1807 struct net_device *dev = platform_get_drvdata(pdev); 1773 struct net_device *ndev = dev_get_drvdata(dev);
1808 struct stmmac_priv *priv = netdev_priv(dev); 1774 struct stmmac_priv *priv = netdev_priv(ndev);
1809 int dis_ic = 0; 1775 int dis_ic = 0;
1810 1776
1811 if (!dev || !netif_running(dev)) 1777 if (!ndev || !netif_running(ndev))
1812 return 0; 1778 return 0;
1813 1779
1814 spin_lock(&priv->lock); 1780 spin_lock(&priv->lock);
1815 1781
1816 if (state.event == PM_EVENT_SUSPEND) { 1782 netif_device_detach(ndev);
1817 netif_device_detach(dev); 1783 netif_stop_queue(ndev);
1818 netif_stop_queue(dev); 1784 if (priv->phydev)
1819 if (priv->phydev) 1785 phy_stop(priv->phydev);
1820 phy_stop(priv->phydev);
1821 1786
1822#ifdef CONFIG_STMMAC_TIMER 1787#ifdef CONFIG_STMMAC_TIMER
1823 priv->tm->timer_stop(); 1788 priv->tm->timer_stop();
1824 if (likely(priv->tm->enable)) 1789 if (likely(priv->tm->enable))
1825 dis_ic = 1; 1790 dis_ic = 1;
1826#endif 1791#endif
1827 napi_disable(&priv->napi); 1792 napi_disable(&priv->napi);
1828 1793
1829 /* Stop TX/RX DMA */ 1794 /* Stop TX/RX DMA */
1830 priv->hw->dma->stop_tx(dev->base_addr); 1795 priv->hw->dma->stop_tx(priv->ioaddr);
1831 priv->hw->dma->stop_rx(dev->base_addr); 1796 priv->hw->dma->stop_rx(priv->ioaddr);
1832 /* Clear the Rx/Tx descriptors */ 1797 /* Clear the Rx/Tx descriptors */
1833 priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size, 1798 priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size,
1834 dis_ic); 1799 dis_ic);
1835 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size); 1800 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
1836 1801
1837 stmmac_mac_disable_tx(dev->base_addr); 1802 /* Enable Power down mode by programming the PMT regs */
1838 1803 if (device_may_wakeup(priv->device))
1839 if (device_may_wakeup(&(pdev->dev))) { 1804 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
1840 /* Enable Power down mode by programming the PMT regs */ 1805 else
1841 if (priv->wolenabled == PMT_SUPPORTED) 1806 stmmac_disable_mac(priv->ioaddr);
1842 priv->hw->mac->pmt(dev->base_addr,
1843 priv->wolopts);
1844 } else {
1845 stmmac_mac_disable_rx(dev->base_addr);
1846 }
1847 } else {
1848 priv->shutdown = 1;
1849 /* Although this can appear slightly redundant it actually
1850 * makes fast the standby operation and guarantees the driver
1851 * working if hibernation is on media. */
1852 stmmac_release(dev);
1853 }
1854 1807
1855 spin_unlock(&priv->lock); 1808 spin_unlock(&priv->lock);
1856 return 0; 1809 return 0;
1857} 1810}
1858 1811
1859static int stmmac_resume(struct platform_device *pdev) 1812static int stmmac_resume(struct device *dev)
1860{ 1813{
1861 struct net_device *dev = platform_get_drvdata(pdev); 1814 struct net_device *ndev = dev_get_drvdata(dev);
1862 struct stmmac_priv *priv = netdev_priv(dev); 1815 struct stmmac_priv *priv = netdev_priv(ndev);
1863 unsigned long ioaddr = dev->base_addr;
1864
1865 if (!netif_running(dev))
1866 return 0;
1867 1816
1868 if (priv->shutdown) { 1817 if (!netif_running(ndev))
1869 /* Re-open the interface and re-init the MAC/DMA
1870 and the rings (i.e. on hibernation stage) */
1871 stmmac_open(dev);
1872 return 0; 1818 return 0;
1873 }
1874 1819
1875 spin_lock(&priv->lock); 1820 spin_lock(&priv->lock);
1876 1821
@@ -1879,44 +1824,70 @@ static int stmmac_resume(struct platform_device *pdev)
1879 * is received. Anyway, it's better to manually clear 1824 * is received. Anyway, it's better to manually clear
1880 * this bit because it can generate problems while resuming 1825 * this bit because it can generate problems while resuming
1881 * from another devices (e.g. serial console). */ 1826 * from another devices (e.g. serial console). */
1882 if (device_may_wakeup(&(pdev->dev))) 1827 if (device_may_wakeup(priv->device))
1883 if (priv->wolenabled == PMT_SUPPORTED) 1828 priv->hw->mac->pmt(priv->ioaddr, 0);
1884 priv->hw->mac->pmt(dev->base_addr, 0);
1885 1829
1886 netif_device_attach(dev); 1830 netif_device_attach(ndev);
1887 1831
1888 /* Enable the MAC and DMA */ 1832 /* Enable the MAC and DMA */
1889 stmmac_mac_enable_rx(ioaddr); 1833 stmmac_enable_mac(priv->ioaddr);
1890 stmmac_mac_enable_tx(ioaddr); 1834 priv->hw->dma->start_tx(priv->ioaddr);
1891 priv->hw->dma->start_tx(ioaddr); 1835 priv->hw->dma->start_rx(priv->ioaddr);
1892 priv->hw->dma->start_rx(ioaddr);
1893 1836
1894#ifdef CONFIG_STMMAC_TIMER 1837#ifdef CONFIG_STMMAC_TIMER
1895 priv->tm->timer_start(tmrate); 1838 if (likely(priv->tm->enable))
1839 priv->tm->timer_start(tmrate);
1896#endif 1840#endif
1897 napi_enable(&priv->napi); 1841 napi_enable(&priv->napi);
1898 1842
1899 if (priv->phydev) 1843 if (priv->phydev)
1900 phy_start(priv->phydev); 1844 phy_start(priv->phydev);
1901 1845
1902 netif_start_queue(dev); 1846 netif_start_queue(ndev);
1903 1847
1904 spin_unlock(&priv->lock); 1848 spin_unlock(&priv->lock);
1905 return 0; 1849 return 0;
1906} 1850}
1907#endif
1908 1851
1909static struct platform_driver stmmac_driver = { 1852static int stmmac_freeze(struct device *dev)
1910 .driver = { 1853{
1911 .name = STMMAC_RESOURCE_NAME, 1854 struct net_device *ndev = dev_get_drvdata(dev);
1912 }, 1855
1913 .probe = stmmac_dvr_probe, 1856 if (!ndev || !netif_running(ndev))
1914 .remove = stmmac_dvr_remove, 1857 return 0;
1915#ifdef CONFIG_PM 1858
1859 return stmmac_release(ndev);
1860}
1861
1862static int stmmac_restore(struct device *dev)
1863{
1864 struct net_device *ndev = dev_get_drvdata(dev);
1865
1866 if (!ndev || !netif_running(ndev))
1867 return 0;
1868
1869 return stmmac_open(ndev);
1870}
1871
1872static const struct dev_pm_ops stmmac_pm_ops = {
1916 .suspend = stmmac_suspend, 1873 .suspend = stmmac_suspend,
1917 .resume = stmmac_resume, 1874 .resume = stmmac_resume,
1918#endif 1875 .freeze = stmmac_freeze,
1876 .thaw = stmmac_restore,
1877 .restore = stmmac_restore,
1878};
1879#else
1880static const struct dev_pm_ops stmmac_pm_ops;
1881#endif /* CONFIG_PM */
1919 1882
1883static struct platform_driver stmmac_driver = {
1884 .probe = stmmac_dvr_probe,
1885 .remove = stmmac_dvr_remove,
1886 .driver = {
1887 .name = STMMAC_RESOURCE_NAME,
1888 .owner = THIS_MODULE,
1889 .pm = &stmmac_pm_ops,
1890 },
1920}; 1891};
1921 1892
1922/** 1893/**
@@ -1968,8 +1939,6 @@ static int __init stmmac_cmdline_opt(char *str)
1968 strict_strtoul(opt + 7, 0, (unsigned long *)&buf_sz); 1939 strict_strtoul(opt + 7, 0, (unsigned long *)&buf_sz);
1969 else if (!strncmp(opt, "tc:", 3)) 1940 else if (!strncmp(opt, "tc:", 3))
1970 strict_strtoul(opt + 3, 0, (unsigned long *)&tc); 1941 strict_strtoul(opt + 3, 0, (unsigned long *)&tc);
1971 else if (!strncmp(opt, "tx_coe:", 7))
1972 strict_strtoul(opt + 7, 0, (unsigned long *)&tx_coe);
1973 else if (!strncmp(opt, "watchdog:", 9)) 1942 else if (!strncmp(opt, "watchdog:", 9))
1974 strict_strtoul(opt + 9, 0, (unsigned long *)&watchdog); 1943 strict_strtoul(opt + 9, 0, (unsigned long *)&watchdog);
1975 else if (!strncmp(opt, "flow_ctrl:", 10)) 1944 else if (!strncmp(opt, "flow_ctrl:", 10))
diff --git a/drivers/net/stmmac/stmmac_mdio.c b/drivers/net/stmmac/stmmac_mdio.c
index 40b2c7929719..234b4068a1fc 100644
--- a/drivers/net/stmmac/stmmac_mdio.c
+++ b/drivers/net/stmmac/stmmac_mdio.c
@@ -47,21 +47,20 @@ static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
47{ 47{
48 struct net_device *ndev = bus->priv; 48 struct net_device *ndev = bus->priv;
49 struct stmmac_priv *priv = netdev_priv(ndev); 49 struct stmmac_priv *priv = netdev_priv(ndev);
50 unsigned long ioaddr = ndev->base_addr;
51 unsigned int mii_address = priv->hw->mii.addr; 50 unsigned int mii_address = priv->hw->mii.addr;
52 unsigned int mii_data = priv->hw->mii.data; 51 unsigned int mii_data = priv->hw->mii.data;
53 52
54 int data; 53 int data;
55 u16 regValue = (((phyaddr << 11) & (0x0000F800)) | 54 u16 regValue = (((phyaddr << 11) & (0x0000F800)) |
56 ((phyreg << 6) & (0x000007C0))); 55 ((phyreg << 6) & (0x000007C0)));
57 regValue |= MII_BUSY; /* in case of GMAC */ 56 regValue |= MII_BUSY | ((priv->plat->clk_csr & 7) << 2);
58 57
59 do {} while (((readl(ioaddr + mii_address)) & MII_BUSY) == 1); 58 do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1);
60 writel(regValue, ioaddr + mii_address); 59 writel(regValue, priv->ioaddr + mii_address);
61 do {} while (((readl(ioaddr + mii_address)) & MII_BUSY) == 1); 60 do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1);
62 61
63 /* Read the data from the MII data register */ 62 /* Read the data from the MII data register */
64 data = (int)readl(ioaddr + mii_data); 63 data = (int)readl(priv->ioaddr + mii_data);
65 64
66 return data; 65 return data;
67} 66}
@@ -79,7 +78,6 @@ static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
79{ 78{
80 struct net_device *ndev = bus->priv; 79 struct net_device *ndev = bus->priv;
81 struct stmmac_priv *priv = netdev_priv(ndev); 80 struct stmmac_priv *priv = netdev_priv(ndev);
82 unsigned long ioaddr = ndev->base_addr;
83 unsigned int mii_address = priv->hw->mii.addr; 81 unsigned int mii_address = priv->hw->mii.addr;
84 unsigned int mii_data = priv->hw->mii.data; 82 unsigned int mii_data = priv->hw->mii.data;
85 83
@@ -87,17 +85,18 @@ static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
87 (((phyaddr << 11) & (0x0000F800)) | ((phyreg << 6) & (0x000007C0))) 85 (((phyaddr << 11) & (0x0000F800)) | ((phyreg << 6) & (0x000007C0)))
88 | MII_WRITE; 86 | MII_WRITE;
89 87
90 value |= MII_BUSY; 88 value |= MII_BUSY | ((priv->plat->clk_csr & 7) << 2);
89
91 90
92 /* Wait until any existing MII operation is complete */ 91 /* Wait until any existing MII operation is complete */
93 do {} while (((readl(ioaddr + mii_address)) & MII_BUSY) == 1); 92 do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1);
94 93
95 /* Set the MII address register to write */ 94 /* Set the MII address register to write */
96 writel(phydata, ioaddr + mii_data); 95 writel(phydata, priv->ioaddr + mii_data);
97 writel(value, ioaddr + mii_address); 96 writel(value, priv->ioaddr + mii_address);
98 97
99 /* Wait until any existing MII operation is complete */ 98 /* Wait until any existing MII operation is complete */
100 do {} while (((readl(ioaddr + mii_address)) & MII_BUSY) == 1); 99 do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1);
101 100
102 return 0; 101 return 0;
103} 102}
@@ -111,19 +110,18 @@ static int stmmac_mdio_reset(struct mii_bus *bus)
111{ 110{
112 struct net_device *ndev = bus->priv; 111 struct net_device *ndev = bus->priv;
113 struct stmmac_priv *priv = netdev_priv(ndev); 112 struct stmmac_priv *priv = netdev_priv(ndev);
114 unsigned long ioaddr = ndev->base_addr;
115 unsigned int mii_address = priv->hw->mii.addr; 113 unsigned int mii_address = priv->hw->mii.addr;
116 114
117 if (priv->phy_reset) { 115 if (priv->phy_reset) {
118 pr_debug("stmmac_mdio_reset: calling phy_reset\n"); 116 pr_debug("stmmac_mdio_reset: calling phy_reset\n");
119 priv->phy_reset(priv->bsp_priv); 117 priv->phy_reset(priv->plat->bsp_priv);
120 } 118 }
121 119
122 /* This is a workaround for problems with the STE101P PHY. 120 /* This is a workaround for problems with the STE101P PHY.
123 * It doesn't complete its reset until at least one clock cycle 121 * It doesn't complete its reset until at least one clock cycle
124 * on MDC, so perform a dummy mdio read. 122 * on MDC, so perform a dummy mdio read.
125 */ 123 */
126 writel(0, ioaddr + mii_address); 124 writel(0, priv->ioaddr + mii_address);
127 125
128 return 0; 126 return 0;
129} 127}
@@ -159,7 +157,7 @@ int stmmac_mdio_register(struct net_device *ndev)
159 new_bus->read = &stmmac_mdio_read; 157 new_bus->read = &stmmac_mdio_read;
160 new_bus->write = &stmmac_mdio_write; 158 new_bus->write = &stmmac_mdio_write;
161 new_bus->reset = &stmmac_mdio_reset; 159 new_bus->reset = &stmmac_mdio_reset;
162 snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", priv->bus_id); 160 snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", priv->plat->bus_id);
163 new_bus->priv = ndev; 161 new_bus->priv = ndev;
164 new_bus->irq = irqlist; 162 new_bus->irq = irqlist;
165 new_bus->phy_mask = priv->phy_mask; 163 new_bus->phy_mask = priv->phy_mask;
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-02 20:31:34 -0400