1 files changed, 14 insertions, 16 deletions

diff --git a/drivers/net/stmmac/stmmac_mdio.c b/drivers/net/stmmac/stmmac_mdio.c
index 40b2c7929719..234b4068a1fc 100644
--- a/drivers/net/stmmac/stmmac_mdio.c
+++ b/drivers/net/stmmac/stmmac_mdio.c
@@ -47,21 +47,20 @@ static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
 {
         struct net_device *ndev = bus->priv;
         struct stmmac_priv *priv = netdev_priv(ndev);
-        unsigned long ioaddr = ndev->base_addr;
         unsigned int mii_address = priv->hw->mii.addr;
         unsigned int mii_data = priv->hw->mii.data;
 
         int data;
         u16 regValue = (((phyaddr << 11) & (0x0000F800)) |
                         ((phyreg << 6) & (0x000007C0)));
-        regValue |= MII_BUSY;   /* in case of GMAC */
+        regValue |= MII_BUSY | ((priv->plat->clk_csr & 7) << 2);
 
-        do {} while (((readl(ioaddr + mii_address)) & MII_BUSY) == 1);
-        writel(regValue, ioaddr + mii_address);
-        do {} while (((readl(ioaddr + mii_address)) & MII_BUSY) == 1);
+        do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1);
+        writel(regValue, priv->ioaddr + mii_address);
+        do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1);
 
         /* Read the data from the MII data register */
-        data = (int)readl(ioaddr + mii_data);
+        data = (int)readl(priv->ioaddr + mii_data);
 
         return data;
 }
@@ -79,7 +78,6 @@ static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
 {
         struct net_device *ndev = bus->priv;
         struct stmmac_priv *priv = netdev_priv(ndev);
-        unsigned long ioaddr = ndev->base_addr;
         unsigned int mii_address = priv->hw->mii.addr;
         unsigned int mii_data = priv->hw->mii.data;
 
@@ -87,17 +85,18 @@ static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
             (((phyaddr << 11) & (0x0000F800)) | ((phyreg << 6) & (0x000007C0)))
             | MII_WRITE;
 
-        value |= MII_BUSY;
+        value |= MII_BUSY | ((priv->plat->clk_csr & 7) << 2);
+
 
         /* Wait until any existing MII operation is complete */
-        do {} while (((readl(ioaddr + mii_address)) & MII_BUSY) == 1);
+        do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1);
 
         /* Set the MII address register to write */
-        writel(phydata, ioaddr + mii_data);
-        writel(value, ioaddr + mii_address);
+        writel(phydata, priv->ioaddr + mii_data);
+        writel(value, priv->ioaddr + mii_address);
 
         /* Wait until any existing MII operation is complete */
-        do {} while (((readl(ioaddr + mii_address)) & MII_BUSY) == 1);
+        do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1);
 
         return 0;
 }
@@ -111,19 +110,18 @@ static int stmmac_mdio_reset(struct mii_bus *bus)
 {
         struct net_device *ndev = bus->priv;
         struct stmmac_priv *priv = netdev_priv(ndev);
-        unsigned long ioaddr = ndev->base_addr;
         unsigned int mii_address = priv->hw->mii.addr;
 
         if (priv->phy_reset) {
                 pr_debug("stmmac_mdio_reset: calling phy_reset\n");
-                priv->phy_reset(priv->bsp_priv);
+                priv->phy_reset(priv->plat->bsp_priv);
         }
 
         /* This is a workaround for problems with the STE101P PHY.
          * It doesn't complete its reset until at least one clock cycle
          * on MDC, so perform a dummy mdio read.
          */
-        writel(0, ioaddr + mii_address);
+        writel(0, priv->ioaddr + mii_address);
 
         return 0;
 }
@@ -159,7 +157,7 @@ int stmmac_mdio_register(struct net_device *ndev)
         new_bus->read = &stmmac_mdio_read;
         new_bus->write = &stmmac_mdio_write;
         new_bus->reset = &stmmac_mdio_reset;
-        snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", priv->bus_id);
+        snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", priv->plat->bus_id);
         new_bus->priv = ndev;
         new_bus->irq = irqlist;
         new_bus->phy_mask = priv->phy_mask;