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path: root/drivers/infiniband/hw/cxgb4/qp.c
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Diffstat (limited to 'drivers/infiniband/hw/cxgb4/qp.c')
-rw-r--r--drivers/infiniband/hw/cxgb4/qp.c317
1 files changed, 161 insertions, 156 deletions
diff --git a/drivers/infiniband/hw/cxgb4/qp.c b/drivers/infiniband/hw/cxgb4/qp.c
index 93f6e5bf0ec5..a41578e48c7b 100644
--- a/drivers/infiniband/hw/cxgb4/qp.c
+++ b/drivers/infiniband/hw/cxgb4/qp.c
@@ -31,6 +31,63 @@
31 */ 31 */
32#include "iw_cxgb4.h" 32#include "iw_cxgb4.h"
33 33
34static int ocqp_support = 1;
35module_param(ocqp_support, int, 0644);
36MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)");
37
38static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state)
39{
40 unsigned long flag;
41 spin_lock_irqsave(&qhp->lock, flag);
42 qhp->attr.state = state;
43 spin_unlock_irqrestore(&qhp->lock, flag);
44}
45
46static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
47{
48 c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize);
49}
50
51static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
52{
53 dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,
54 pci_unmap_addr(sq, mapping));
55}
56
57static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
58{
59 if (t4_sq_onchip(sq))
60 dealloc_oc_sq(rdev, sq);
61 else
62 dealloc_host_sq(rdev, sq);
63}
64
65static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
66{
67 if (!ocqp_support || !t4_ocqp_supported())
68 return -ENOSYS;
69 sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize);
70 if (!sq->dma_addr)
71 return -ENOMEM;
72 sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr -
73 rdev->lldi.vr->ocq.start;
74 sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr -
75 rdev->lldi.vr->ocq.start);
76 sq->flags |= T4_SQ_ONCHIP;
77 return 0;
78}
79
80static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
81{
82 sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize,
83 &(sq->dma_addr), GFP_KERNEL);
84 if (!sq->queue)
85 return -ENOMEM;
86 sq->phys_addr = virt_to_phys(sq->queue);
87 pci_unmap_addr_set(sq, mapping, sq->dma_addr);
88 return 0;
89}
90
34static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq, 91static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
35 struct c4iw_dev_ucontext *uctx) 92 struct c4iw_dev_ucontext *uctx)
36{ 93{
@@ -41,9 +98,7 @@ static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
41 dma_free_coherent(&(rdev->lldi.pdev->dev), 98 dma_free_coherent(&(rdev->lldi.pdev->dev),
42 wq->rq.memsize, wq->rq.queue, 99 wq->rq.memsize, wq->rq.queue,
43 dma_unmap_addr(&wq->rq, mapping)); 100 dma_unmap_addr(&wq->rq, mapping));
44 dma_free_coherent(&(rdev->lldi.pdev->dev), 101 dealloc_sq(rdev, &wq->sq);
45 wq->sq.memsize, wq->sq.queue,
46 dma_unmap_addr(&wq->sq, mapping));
47 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size); 102 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
48 kfree(wq->rq.sw_rq); 103 kfree(wq->rq.sw_rq);
49 kfree(wq->sq.sw_sq); 104 kfree(wq->sq.sw_sq);
@@ -93,11 +148,12 @@ static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
93 if (!wq->rq.rqt_hwaddr) 148 if (!wq->rq.rqt_hwaddr)
94 goto err4; 149 goto err4;
95 150
96 wq->sq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), 151 if (user) {
97 wq->sq.memsize, &(wq->sq.dma_addr), 152 if (alloc_oc_sq(rdev, &wq->sq) && alloc_host_sq(rdev, &wq->sq))
98 GFP_KERNEL); 153 goto err5;
99 if (!wq->sq.queue) 154 } else
100 goto err5; 155 if (alloc_host_sq(rdev, &wq->sq))
156 goto err5;
101 memset(wq->sq.queue, 0, wq->sq.memsize); 157 memset(wq->sq.queue, 0, wq->sq.memsize);
102 dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr); 158 dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
103 159
@@ -144,7 +200,7 @@ static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
144 V_FW_RI_RES_WR_NRES(2) | 200 V_FW_RI_RES_WR_NRES(2) |
145 FW_WR_COMPL(1)); 201 FW_WR_COMPL(1));
146 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16)); 202 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
147 res_wr->cookie = (u64)&wr_wait; 203 res_wr->cookie = (unsigned long) &wr_wait;
148 res = res_wr->res; 204 res = res_wr->res;
149 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ; 205 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
150 res->u.sqrq.op = FW_RI_RES_OP_WRITE; 206 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
@@ -158,12 +214,13 @@ static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
158 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */ 214 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
159 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */ 215 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
160 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */ 216 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
217 (t4_sq_onchip(&wq->sq) ? F_FW_RI_RES_WR_ONCHIP : 0) |
161 V_FW_RI_RES_WR_IQID(scq->cqid)); 218 V_FW_RI_RES_WR_IQID(scq->cqid));
162 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32( 219 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
163 V_FW_RI_RES_WR_DCAEN(0) | 220 V_FW_RI_RES_WR_DCAEN(0) |
164 V_FW_RI_RES_WR_DCACPU(0) | 221 V_FW_RI_RES_WR_DCACPU(0) |
165 V_FW_RI_RES_WR_FBMIN(2) | 222 V_FW_RI_RES_WR_FBMIN(2) |
166 V_FW_RI_RES_WR_FBMAX(3) | 223 V_FW_RI_RES_WR_FBMAX(2) |
167 V_FW_RI_RES_WR_CIDXFTHRESHO(0) | 224 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
168 V_FW_RI_RES_WR_CIDXFTHRESH(0) | 225 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
169 V_FW_RI_RES_WR_EQSIZE(eqsize)); 226 V_FW_RI_RES_WR_EQSIZE(eqsize));
@@ -186,7 +243,7 @@ static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
186 V_FW_RI_RES_WR_DCAEN(0) | 243 V_FW_RI_RES_WR_DCAEN(0) |
187 V_FW_RI_RES_WR_DCACPU(0) | 244 V_FW_RI_RES_WR_DCACPU(0) |
188 V_FW_RI_RES_WR_FBMIN(2) | 245 V_FW_RI_RES_WR_FBMIN(2) |
189 V_FW_RI_RES_WR_FBMAX(3) | 246 V_FW_RI_RES_WR_FBMAX(2) |
190 V_FW_RI_RES_WR_CIDXFTHRESHO(0) | 247 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
191 V_FW_RI_RES_WR_CIDXFTHRESH(0) | 248 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
192 V_FW_RI_RES_WR_EQSIZE(eqsize)); 249 V_FW_RI_RES_WR_EQSIZE(eqsize));
@@ -198,14 +255,7 @@ static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
198 ret = c4iw_ofld_send(rdev, skb); 255 ret = c4iw_ofld_send(rdev, skb);
199 if (ret) 256 if (ret)
200 goto err7; 257 goto err7;
201 wait_event_timeout(wr_wait.wait, wr_wait.done, C4IW_WR_TO); 258 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__);
202 if (!wr_wait.done) {
203 printk(KERN_ERR MOD "Device %s not responding!\n",
204 pci_name(rdev->lldi.pdev));
205 rdev->flags = T4_FATAL_ERROR;
206 ret = -EIO;
207 } else
208 ret = wr_wait.ret;
209 if (ret) 259 if (ret)
210 goto err7; 260 goto err7;
211 261
@@ -219,9 +269,7 @@ err7:
219 wq->rq.memsize, wq->rq.queue, 269 wq->rq.memsize, wq->rq.queue,
220 dma_unmap_addr(&wq->rq, mapping)); 270 dma_unmap_addr(&wq->rq, mapping));
221err6: 271err6:
222 dma_free_coherent(&(rdev->lldi.pdev->dev), 272 dealloc_sq(rdev, &wq->sq);
223 wq->sq.memsize, wq->sq.queue,
224 dma_unmap_addr(&wq->sq, mapping));
225err5: 273err5:
226 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size); 274 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
227err4: 275err4:
@@ -263,6 +311,9 @@ static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
263 rem -= len; 311 rem -= len;
264 } 312 }
265 } 313 }
314 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
315 if (len)
316 memset(dstp, 0, len);
266 immdp->op = FW_RI_DATA_IMMD; 317 immdp->op = FW_RI_DATA_IMMD;
267 immdp->r1 = 0; 318 immdp->r1 = 0;
268 immdp->r2 = 0; 319 immdp->r2 = 0;
@@ -292,6 +343,7 @@ static int build_isgl(__be64 *queue_start, __be64 *queue_end,
292 if (++flitp == queue_end) 343 if (++flitp == queue_end)
293 flitp = queue_start; 344 flitp = queue_start;
294 } 345 }
346 *flitp = (__force __be64)0;
295 isglp->op = FW_RI_DATA_ISGL; 347 isglp->op = FW_RI_DATA_ISGL;
296 isglp->r1 = 0; 348 isglp->r1 = 0;
297 isglp->nsge = cpu_to_be16(num_sge); 349 isglp->nsge = cpu_to_be16(num_sge);
@@ -453,13 +505,15 @@ static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
453 return 0; 505 return 0;
454} 506}
455 507
456static int build_fastreg(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16) 508static int build_fastreg(struct t4_sq *sq, union t4_wr *wqe,
509 struct ib_send_wr *wr, u8 *len16)
457{ 510{
458 511
459 struct fw_ri_immd *imdp; 512 struct fw_ri_immd *imdp;
460 __be64 *p; 513 __be64 *p;
461 int i; 514 int i;
462 int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32); 515 int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32);
516 int rem;
463 517
464 if (wr->wr.fast_reg.page_list_len > T4_MAX_FR_DEPTH) 518 if (wr->wr.fast_reg.page_list_len > T4_MAX_FR_DEPTH)
465 return -EINVAL; 519 return -EINVAL;
@@ -474,32 +528,28 @@ static int build_fastreg(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
474 wqe->fr.va_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32); 528 wqe->fr.va_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32);
475 wqe->fr.va_lo_fbo = cpu_to_be32(wr->wr.fast_reg.iova_start & 529 wqe->fr.va_lo_fbo = cpu_to_be32(wr->wr.fast_reg.iova_start &
476 0xffffffff); 530 0xffffffff);
477 if (pbllen > T4_MAX_FR_IMMD) { 531 WARN_ON(pbllen > T4_MAX_FR_IMMD);
478 struct c4iw_fr_page_list *c4pl = 532 imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
479 to_c4iw_fr_page_list(wr->wr.fast_reg.page_list); 533 imdp->op = FW_RI_DATA_IMMD;
480 struct fw_ri_dsgl *sglp; 534 imdp->r1 = 0;
481 535 imdp->r2 = 0;
482 sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1); 536 imdp->immdlen = cpu_to_be32(pbllen);
483 sglp->op = FW_RI_DATA_DSGL; 537 p = (__be64 *)(imdp + 1);
484 sglp->r1 = 0; 538 rem = pbllen;
485 sglp->nsge = cpu_to_be16(1); 539 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
486 sglp->addr0 = cpu_to_be64(c4pl->dma_addr); 540 *p = cpu_to_be64((u64)wr->wr.fast_reg.page_list->page_list[i]);
487 sglp->len0 = cpu_to_be32(pbllen); 541 rem -= sizeof *p;
488 542 if (++p == (__be64 *)&sq->queue[sq->size])
489 *len16 = DIV_ROUND_UP(sizeof wqe->fr + sizeof *sglp, 16); 543 p = (__be64 *)sq->queue;
490 } else {
491 imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
492 imdp->op = FW_RI_DATA_IMMD;
493 imdp->r1 = 0;
494 imdp->r2 = 0;
495 imdp->immdlen = cpu_to_be32(pbllen);
496 p = (__be64 *)(imdp + 1);
497 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++, p++)
498 *p = cpu_to_be64(
499 (u64)wr->wr.fast_reg.page_list->page_list[i]);
500 *len16 = DIV_ROUND_UP(sizeof wqe->fr + sizeof *imdp + pbllen,
501 16);
502 } 544 }
545 BUG_ON(rem < 0);
546 while (rem) {
547 *p = 0;
548 rem -= sizeof *p;
549 if (++p == (__be64 *)&sq->queue[sq->size])
550 p = (__be64 *)sq->queue;
551 }
552 *len16 = DIV_ROUND_UP(sizeof wqe->fr + sizeof *imdp + pbllen, 16);
503 return 0; 553 return 0;
504} 554}
505 555
@@ -587,7 +637,7 @@ int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
587 fw_opcode = FW_RI_RDMA_READ_WR; 637 fw_opcode = FW_RI_RDMA_READ_WR;
588 swsqe->opcode = FW_RI_READ_REQ; 638 swsqe->opcode = FW_RI_READ_REQ;
589 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV) 639 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
590 fw_flags |= FW_RI_RDMA_READ_INVALIDATE; 640 fw_flags = FW_RI_RDMA_READ_INVALIDATE;
591 else 641 else
592 fw_flags = 0; 642 fw_flags = 0;
593 err = build_rdma_read(wqe, wr, &len16); 643 err = build_rdma_read(wqe, wr, &len16);
@@ -600,7 +650,7 @@ int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
600 case IB_WR_FAST_REG_MR: 650 case IB_WR_FAST_REG_MR:
601 fw_opcode = FW_RI_FR_NSMR_WR; 651 fw_opcode = FW_RI_FR_NSMR_WR;
602 swsqe->opcode = FW_RI_FAST_REGISTER; 652 swsqe->opcode = FW_RI_FAST_REGISTER;
603 err = build_fastreg(wqe, wr, &len16); 653 err = build_fastreg(&qhp->wq.sq, wqe, wr, &len16);
604 break; 654 break;
605 case IB_WR_LOCAL_INV: 655 case IB_WR_LOCAL_INV:
606 if (wr->send_flags & IB_SEND_FENCE) 656 if (wr->send_flags & IB_SEND_FENCE)
@@ -842,36 +892,6 @@ static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
842 } 892 }
843} 893}
844 894
845int c4iw_post_zb_read(struct c4iw_qp *qhp)
846{
847 union t4_wr *wqe;
848 struct sk_buff *skb;
849 u8 len16;
850
851 PDBG("%s enter\n", __func__);
852 skb = alloc_skb(40, GFP_KERNEL);
853 if (!skb) {
854 printk(KERN_ERR "%s cannot send zb_read!!\n", __func__);
855 return -ENOMEM;
856 }
857 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
858
859 wqe = (union t4_wr *)skb_put(skb, sizeof wqe->read);
860 memset(wqe, 0, sizeof wqe->read);
861 wqe->read.r2 = cpu_to_be64(0);
862 wqe->read.stag_sink = cpu_to_be32(1);
863 wqe->read.to_sink_hi = cpu_to_be32(0);
864 wqe->read.to_sink_lo = cpu_to_be32(1);
865 wqe->read.stag_src = cpu_to_be32(1);
866 wqe->read.plen = cpu_to_be32(0);
867 wqe->read.to_src_hi = cpu_to_be32(0);
868 wqe->read.to_src_lo = cpu_to_be32(1);
869 len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
870 init_wr_hdr(wqe, 0, FW_RI_RDMA_READ_WR, FW_RI_COMPLETION_FLAG, len16);
871
872 return c4iw_ofld_send(&qhp->rhp->rdev, skb);
873}
874
875static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe, 895static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
876 gfp_t gfp) 896 gfp_t gfp)
877{ 897{
@@ -905,46 +925,38 @@ static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
905 * Assumes qhp lock is held. 925 * Assumes qhp lock is held.
906 */ 926 */
907static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp, 927static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
908 struct c4iw_cq *schp, unsigned long *flag) 928 struct c4iw_cq *schp)
909{ 929{
910 int count; 930 int count;
911 int flushed; 931 int flushed;
932 unsigned long flag;
912 933
913 PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp); 934 PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
914 /* take a ref on the qhp since we must release the lock */
915 atomic_inc(&qhp->refcnt);
916 spin_unlock_irqrestore(&qhp->lock, *flag);
917 935
918 /* locking hierarchy: cq lock first, then qp lock. */ 936 /* locking hierarchy: cq lock first, then qp lock. */
919 spin_lock_irqsave(&rchp->lock, *flag); 937 spin_lock_irqsave(&rchp->lock, flag);
920 spin_lock(&qhp->lock); 938 spin_lock(&qhp->lock);
921 c4iw_flush_hw_cq(&rchp->cq); 939 c4iw_flush_hw_cq(&rchp->cq);
922 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count); 940 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
923 flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count); 941 flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
924 spin_unlock(&qhp->lock); 942 spin_unlock(&qhp->lock);
925 spin_unlock_irqrestore(&rchp->lock, *flag); 943 spin_unlock_irqrestore(&rchp->lock, flag);
926 if (flushed) 944 if (flushed)
927 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context); 945 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
928 946
929 /* locking hierarchy: cq lock first, then qp lock. */ 947 /* locking hierarchy: cq lock first, then qp lock. */
930 spin_lock_irqsave(&schp->lock, *flag); 948 spin_lock_irqsave(&schp->lock, flag);
931 spin_lock(&qhp->lock); 949 spin_lock(&qhp->lock);
932 c4iw_flush_hw_cq(&schp->cq); 950 c4iw_flush_hw_cq(&schp->cq);
933 c4iw_count_scqes(&schp->cq, &qhp->wq, &count); 951 c4iw_count_scqes(&schp->cq, &qhp->wq, &count);
934 flushed = c4iw_flush_sq(&qhp->wq, &schp->cq, count); 952 flushed = c4iw_flush_sq(&qhp->wq, &schp->cq, count);
935 spin_unlock(&qhp->lock); 953 spin_unlock(&qhp->lock);
936 spin_unlock_irqrestore(&schp->lock, *flag); 954 spin_unlock_irqrestore(&schp->lock, flag);
937 if (flushed) 955 if (flushed)
938 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context); 956 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context);
939
940 /* deref */
941 if (atomic_dec_and_test(&qhp->refcnt))
942 wake_up(&qhp->wait);
943
944 spin_lock_irqsave(&qhp->lock, *flag);
945} 957}
946 958
947static void flush_qp(struct c4iw_qp *qhp, unsigned long *flag) 959static void flush_qp(struct c4iw_qp *qhp)
948{ 960{
949 struct c4iw_cq *rchp, *schp; 961 struct c4iw_cq *rchp, *schp;
950 962
@@ -958,7 +970,7 @@ static void flush_qp(struct c4iw_qp *qhp, unsigned long *flag)
958 t4_set_cq_in_error(&schp->cq); 970 t4_set_cq_in_error(&schp->cq);
959 return; 971 return;
960 } 972 }
961 __flush_qp(qhp, rchp, schp, flag); 973 __flush_qp(qhp, rchp, schp);
962} 974}
963 975
964static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp, 976static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
@@ -966,7 +978,6 @@ static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
966{ 978{
967 struct fw_ri_wr *wqe; 979 struct fw_ri_wr *wqe;
968 int ret; 980 int ret;
969 struct c4iw_wr_wait wr_wait;
970 struct sk_buff *skb; 981 struct sk_buff *skb;
971 982
972 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid, 983 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
@@ -985,28 +996,15 @@ static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
985 wqe->flowid_len16 = cpu_to_be32( 996 wqe->flowid_len16 = cpu_to_be32(
986 FW_WR_FLOWID(ep->hwtid) | 997 FW_WR_FLOWID(ep->hwtid) |
987 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16))); 998 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
988 wqe->cookie = (u64)&wr_wait; 999 wqe->cookie = (unsigned long) &ep->com.wr_wait;
989 1000
990 wqe->u.fini.type = FW_RI_TYPE_FINI; 1001 wqe->u.fini.type = FW_RI_TYPE_FINI;
991 c4iw_init_wr_wait(&wr_wait);
992 ret = c4iw_ofld_send(&rhp->rdev, skb); 1002 ret = c4iw_ofld_send(&rhp->rdev, skb);
993 if (ret) 1003 if (ret)
994 goto out; 1004 goto out;
995 1005
996 wait_event_timeout(wr_wait.wait, wr_wait.done, C4IW_WR_TO); 1006 ret = c4iw_wait_for_reply(&rhp->rdev, &ep->com.wr_wait, qhp->ep->hwtid,
997 if (!wr_wait.done) { 1007 qhp->wq.sq.qid, __func__);
998 printk(KERN_ERR MOD "Device %s not responding!\n",
999 pci_name(rhp->rdev.lldi.pdev));
1000 rhp->rdev.flags = T4_FATAL_ERROR;
1001 ret = -EIO;
1002 } else {
1003 ret = wr_wait.ret;
1004 if (ret)
1005 printk(KERN_WARNING MOD
1006 "%s: Abnormal close qpid %d ret %u\n",
1007 pci_name(rhp->rdev.lldi.pdev), qhp->wq.sq.qid,
1008 ret);
1009 }
1010out: 1008out:
1011 PDBG("%s ret %d\n", __func__, ret); 1009 PDBG("%s ret %d\n", __func__, ret);
1012 return ret; 1010 return ret;
@@ -1040,7 +1038,6 @@ static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1040{ 1038{
1041 struct fw_ri_wr *wqe; 1039 struct fw_ri_wr *wqe;
1042 int ret; 1040 int ret;
1043 struct c4iw_wr_wait wr_wait;
1044 struct sk_buff *skb; 1041 struct sk_buff *skb;
1045 1042
1046 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid, 1043 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
@@ -1060,7 +1057,7 @@ static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1060 FW_WR_FLOWID(qhp->ep->hwtid) | 1057 FW_WR_FLOWID(qhp->ep->hwtid) |
1061 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16))); 1058 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1062 1059
1063 wqe->cookie = (u64)&wr_wait; 1060 wqe->cookie = (unsigned long) &qhp->ep->com.wr_wait;
1064 1061
1065 wqe->u.init.type = FW_RI_TYPE_INIT; 1062 wqe->u.init.type = FW_RI_TYPE_INIT;
1066 wqe->u.init.mpareqbit_p2ptype = 1063 wqe->u.init.mpareqbit_p2ptype =
@@ -1097,19 +1094,12 @@ static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1097 if (qhp->attr.mpa_attr.initiator) 1094 if (qhp->attr.mpa_attr.initiator)
1098 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init); 1095 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1099 1096
1100 c4iw_init_wr_wait(&wr_wait);
1101 ret = c4iw_ofld_send(&rhp->rdev, skb); 1097 ret = c4iw_ofld_send(&rhp->rdev, skb);
1102 if (ret) 1098 if (ret)
1103 goto out; 1099 goto out;
1104 1100
1105 wait_event_timeout(wr_wait.wait, wr_wait.done, C4IW_WR_TO); 1101 ret = c4iw_wait_for_reply(&rhp->rdev, &qhp->ep->com.wr_wait,
1106 if (!wr_wait.done) { 1102 qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
1107 printk(KERN_ERR MOD "Device %s not responding!\n",
1108 pci_name(rhp->rdev.lldi.pdev));
1109 rhp->rdev.flags = T4_FATAL_ERROR;
1110 ret = -EIO;
1111 } else
1112 ret = wr_wait.ret;
1113out: 1103out:
1114 PDBG("%s ret %d\n", __func__, ret); 1104 PDBG("%s ret %d\n", __func__, ret);
1115 return ret; 1105 return ret;
@@ -1122,7 +1112,6 @@ int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1122{ 1112{
1123 int ret = 0; 1113 int ret = 0;
1124 struct c4iw_qp_attributes newattr = qhp->attr; 1114 struct c4iw_qp_attributes newattr = qhp->attr;
1125 unsigned long flag;
1126 int disconnect = 0; 1115 int disconnect = 0;
1127 int terminate = 0; 1116 int terminate = 0;
1128 int abort = 0; 1117 int abort = 0;
@@ -1133,7 +1122,7 @@ int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1133 qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state, 1122 qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state,
1134 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1); 1123 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1135 1124
1136 spin_lock_irqsave(&qhp->lock, flag); 1125 mutex_lock(&qhp->mutex);
1137 1126
1138 /* Process attr changes if in IDLE */ 1127 /* Process attr changes if in IDLE */
1139 if (mask & C4IW_QP_ATTR_VALID_MODIFY) { 1128 if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
@@ -1184,7 +1173,7 @@ int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1184 qhp->attr.mpa_attr = attrs->mpa_attr; 1173 qhp->attr.mpa_attr = attrs->mpa_attr;
1185 qhp->attr.llp_stream_handle = attrs->llp_stream_handle; 1174 qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1186 qhp->ep = qhp->attr.llp_stream_handle; 1175 qhp->ep = qhp->attr.llp_stream_handle;
1187 qhp->attr.state = C4IW_QP_STATE_RTS; 1176 set_state(qhp, C4IW_QP_STATE_RTS);
1188 1177
1189 /* 1178 /*
1190 * Ref the endpoint here and deref when we 1179 * Ref the endpoint here and deref when we
@@ -1193,15 +1182,13 @@ int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1193 * transition. 1182 * transition.
1194 */ 1183 */
1195 c4iw_get_ep(&qhp->ep->com); 1184 c4iw_get_ep(&qhp->ep->com);
1196 spin_unlock_irqrestore(&qhp->lock, flag);
1197 ret = rdma_init(rhp, qhp); 1185 ret = rdma_init(rhp, qhp);
1198 spin_lock_irqsave(&qhp->lock, flag);
1199 if (ret) 1186 if (ret)
1200 goto err; 1187 goto err;
1201 break; 1188 break;
1202 case C4IW_QP_STATE_ERROR: 1189 case C4IW_QP_STATE_ERROR:
1203 qhp->attr.state = C4IW_QP_STATE_ERROR; 1190 set_state(qhp, C4IW_QP_STATE_ERROR);
1204 flush_qp(qhp, &flag); 1191 flush_qp(qhp);
1205 break; 1192 break;
1206 default: 1193 default:
1207 ret = -EINVAL; 1194 ret = -EINVAL;
@@ -1212,38 +1199,34 @@ int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1212 switch (attrs->next_state) { 1199 switch (attrs->next_state) {
1213 case C4IW_QP_STATE_CLOSING: 1200 case C4IW_QP_STATE_CLOSING:
1214 BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2); 1201 BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2);
1215 qhp->attr.state = C4IW_QP_STATE_CLOSING; 1202 set_state(qhp, C4IW_QP_STATE_CLOSING);
1216 ep = qhp->ep; 1203 ep = qhp->ep;
1217 if (!internal) { 1204 if (!internal) {
1218 abort = 0; 1205 abort = 0;
1219 disconnect = 1; 1206 disconnect = 1;
1220 c4iw_get_ep(&ep->com); 1207 c4iw_get_ep(&qhp->ep->com);
1221 } 1208 }
1222 spin_unlock_irqrestore(&qhp->lock, flag);
1223 ret = rdma_fini(rhp, qhp, ep); 1209 ret = rdma_fini(rhp, qhp, ep);
1224 spin_lock_irqsave(&qhp->lock, flag); 1210 if (ret)
1225 if (ret) {
1226 c4iw_get_ep(&ep->com);
1227 disconnect = abort = 1;
1228 goto err; 1211 goto err;
1229 }
1230 break; 1212 break;
1231 case C4IW_QP_STATE_TERMINATE: 1213 case C4IW_QP_STATE_TERMINATE:
1232 qhp->attr.state = C4IW_QP_STATE_TERMINATE; 1214 set_state(qhp, C4IW_QP_STATE_TERMINATE);
1233 if (qhp->ibqp.uobject) 1215 if (qhp->ibqp.uobject)
1234 t4_set_wq_in_error(&qhp->wq); 1216 t4_set_wq_in_error(&qhp->wq);
1235 ep = qhp->ep; 1217 ep = qhp->ep;
1236 c4iw_get_ep(&ep->com); 1218 if (!internal)
1237 terminate = 1; 1219 terminate = 1;
1238 disconnect = 1; 1220 disconnect = 1;
1221 c4iw_get_ep(&qhp->ep->com);
1239 break; 1222 break;
1240 case C4IW_QP_STATE_ERROR: 1223 case C4IW_QP_STATE_ERROR:
1241 qhp->attr.state = C4IW_QP_STATE_ERROR; 1224 set_state(qhp, C4IW_QP_STATE_ERROR);
1242 if (!internal) { 1225 if (!internal) {
1243 abort = 1; 1226 abort = 1;
1244 disconnect = 1; 1227 disconnect = 1;
1245 ep = qhp->ep; 1228 ep = qhp->ep;
1246 c4iw_get_ep(&ep->com); 1229 c4iw_get_ep(&qhp->ep->com);
1247 } 1230 }
1248 goto err; 1231 goto err;
1249 break; 1232 break;
@@ -1259,8 +1242,8 @@ int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1259 } 1242 }
1260 switch (attrs->next_state) { 1243 switch (attrs->next_state) {
1261 case C4IW_QP_STATE_IDLE: 1244 case C4IW_QP_STATE_IDLE:
1262 flush_qp(qhp, &flag); 1245 flush_qp(qhp);
1263 qhp->attr.state = C4IW_QP_STATE_IDLE; 1246 set_state(qhp, C4IW_QP_STATE_IDLE);
1264 qhp->attr.llp_stream_handle = NULL; 1247 qhp->attr.llp_stream_handle = NULL;
1265 c4iw_put_ep(&qhp->ep->com); 1248 c4iw_put_ep(&qhp->ep->com);
1266 qhp->ep = NULL; 1249 qhp->ep = NULL;
@@ -1282,7 +1265,7 @@ int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1282 ret = -EINVAL; 1265 ret = -EINVAL;
1283 goto out; 1266 goto out;
1284 } 1267 }
1285 qhp->attr.state = C4IW_QP_STATE_IDLE; 1268 set_state(qhp, C4IW_QP_STATE_IDLE);
1286 break; 1269 break;
1287 case C4IW_QP_STATE_TERMINATE: 1270 case C4IW_QP_STATE_TERMINATE:
1288 if (!internal) { 1271 if (!internal) {
@@ -1305,15 +1288,16 @@ err:
1305 1288
1306 /* disassociate the LLP connection */ 1289 /* disassociate the LLP connection */
1307 qhp->attr.llp_stream_handle = NULL; 1290 qhp->attr.llp_stream_handle = NULL;
1308 ep = qhp->ep; 1291 if (!ep)
1292 ep = qhp->ep;
1309 qhp->ep = NULL; 1293 qhp->ep = NULL;
1310 qhp->attr.state = C4IW_QP_STATE_ERROR; 1294 set_state(qhp, C4IW_QP_STATE_ERROR);
1311 free = 1; 1295 free = 1;
1312 wake_up(&qhp->wait); 1296 wake_up(&qhp->wait);
1313 BUG_ON(!ep); 1297 BUG_ON(!ep);
1314 flush_qp(qhp, &flag); 1298 flush_qp(qhp);
1315out: 1299out:
1316 spin_unlock_irqrestore(&qhp->lock, flag); 1300 mutex_unlock(&qhp->mutex);
1317 1301
1318 if (terminate) 1302 if (terminate)
1319 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL); 1303 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
@@ -1335,7 +1319,6 @@ out:
1335 */ 1319 */
1336 if (free) 1320 if (free)
1337 c4iw_put_ep(&ep->com); 1321 c4iw_put_ep(&ep->com);
1338
1339 PDBG("%s exit state %d\n", __func__, qhp->attr.state); 1322 PDBG("%s exit state %d\n", __func__, qhp->attr.state);
1340 return ret; 1323 return ret;
1341} 1324}
@@ -1380,7 +1363,7 @@ struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1380 int sqsize, rqsize; 1363 int sqsize, rqsize;
1381 struct c4iw_ucontext *ucontext; 1364 struct c4iw_ucontext *ucontext;
1382 int ret; 1365 int ret;
1383 struct c4iw_mm_entry *mm1, *mm2, *mm3, *mm4; 1366 struct c4iw_mm_entry *mm1, *mm2, *mm3, *mm4, *mm5 = NULL;
1384 1367
1385 PDBG("%s ib_pd %p\n", __func__, pd); 1368 PDBG("%s ib_pd %p\n", __func__, pd);
1386 1369
@@ -1450,6 +1433,7 @@ struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1450 qhp->attr.max_ord = 1; 1433 qhp->attr.max_ord = 1;
1451 qhp->attr.max_ird = 1; 1434 qhp->attr.max_ird = 1;
1452 spin_lock_init(&qhp->lock); 1435 spin_lock_init(&qhp->lock);
1436 mutex_init(&qhp->mutex);
1453 init_waitqueue_head(&qhp->wait); 1437 init_waitqueue_head(&qhp->wait);
1454 atomic_set(&qhp->refcnt, 1); 1438 atomic_set(&qhp->refcnt, 1);
1455 1439
@@ -1478,7 +1462,15 @@ struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1478 ret = -ENOMEM; 1462 ret = -ENOMEM;
1479 goto err6; 1463 goto err6;
1480 } 1464 }
1481 1465 if (t4_sq_onchip(&qhp->wq.sq)) {
1466 mm5 = kmalloc(sizeof *mm5, GFP_KERNEL);
1467 if (!mm5) {
1468 ret = -ENOMEM;
1469 goto err7;
1470 }
1471 uresp.flags = C4IW_QPF_ONCHIP;
1472 } else
1473 uresp.flags = 0;
1482 uresp.qid_mask = rhp->rdev.qpmask; 1474 uresp.qid_mask = rhp->rdev.qpmask;
1483 uresp.sqid = qhp->wq.sq.qid; 1475 uresp.sqid = qhp->wq.sq.qid;
1484 uresp.sq_size = qhp->wq.sq.size; 1476 uresp.sq_size = qhp->wq.sq.size;
@@ -1487,6 +1479,10 @@ struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1487 uresp.rq_size = qhp->wq.rq.size; 1479 uresp.rq_size = qhp->wq.rq.size;
1488 uresp.rq_memsize = qhp->wq.rq.memsize; 1480 uresp.rq_memsize = qhp->wq.rq.memsize;
1489 spin_lock(&ucontext->mmap_lock); 1481 spin_lock(&ucontext->mmap_lock);
1482 if (mm5) {
1483 uresp.ma_sync_key = ucontext->key;
1484 ucontext->key += PAGE_SIZE;
1485 }
1490 uresp.sq_key = ucontext->key; 1486 uresp.sq_key = ucontext->key;
1491 ucontext->key += PAGE_SIZE; 1487 ucontext->key += PAGE_SIZE;
1492 uresp.rq_key = ucontext->key; 1488 uresp.rq_key = ucontext->key;
@@ -1498,9 +1494,9 @@ struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1498 spin_unlock(&ucontext->mmap_lock); 1494 spin_unlock(&ucontext->mmap_lock);
1499 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp); 1495 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
1500 if (ret) 1496 if (ret)
1501 goto err7; 1497 goto err8;
1502 mm1->key = uresp.sq_key; 1498 mm1->key = uresp.sq_key;
1503 mm1->addr = virt_to_phys(qhp->wq.sq.queue); 1499 mm1->addr = qhp->wq.sq.phys_addr;
1504 mm1->len = PAGE_ALIGN(qhp->wq.sq.memsize); 1500 mm1->len = PAGE_ALIGN(qhp->wq.sq.memsize);
1505 insert_mmap(ucontext, mm1); 1501 insert_mmap(ucontext, mm1);
1506 mm2->key = uresp.rq_key; 1502 mm2->key = uresp.rq_key;
@@ -1515,6 +1511,13 @@ struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1515 mm4->addr = qhp->wq.rq.udb; 1511 mm4->addr = qhp->wq.rq.udb;
1516 mm4->len = PAGE_SIZE; 1512 mm4->len = PAGE_SIZE;
1517 insert_mmap(ucontext, mm4); 1513 insert_mmap(ucontext, mm4);
1514 if (mm5) {
1515 mm5->key = uresp.ma_sync_key;
1516 mm5->addr = (pci_resource_start(rhp->rdev.lldi.pdev, 0)
1517 + A_PCIE_MA_SYNC) & PAGE_MASK;
1518 mm5->len = PAGE_SIZE;
1519 insert_mmap(ucontext, mm5);
1520 }
1518 } 1521 }
1519 qhp->ibqp.qp_num = qhp->wq.sq.qid; 1522 qhp->ibqp.qp_num = qhp->wq.sq.qid;
1520 init_timer(&(qhp->timer)); 1523 init_timer(&(qhp->timer));
@@ -1522,6 +1525,8 @@ struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1522 __func__, qhp, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries, 1525 __func__, qhp, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries,
1523 qhp->wq.sq.qid); 1526 qhp->wq.sq.qid);
1524 return &qhp->ibqp; 1527 return &qhp->ibqp;
1528err8:
1529 kfree(mm5);
1525err7: 1530err7:
1526 kfree(mm4); 1531 kfree(mm4);
1527err6: 1532err6: