diff options
Diffstat (limited to 'drivers/gpu/drm')
59 files changed, 487 insertions, 273 deletions
diff --git a/drivers/gpu/drm/ast/ast_tables.h b/drivers/gpu/drm/ast/ast_tables.h index 4c761dcea972..05c01ea85294 100644 --- a/drivers/gpu/drm/ast/ast_tables.h +++ b/drivers/gpu/drm/ast/ast_tables.h | |||
@@ -99,6 +99,7 @@ static struct ast_vbios_dclk_info dclk_table[] = { | |||
99 | {0x25, 0x65, 0x80}, /* 16: VCLK88.75 */ | 99 | {0x25, 0x65, 0x80}, /* 16: VCLK88.75 */ |
100 | {0x77, 0x58, 0x80}, /* 17: VCLK119 */ | 100 | {0x77, 0x58, 0x80}, /* 17: VCLK119 */ |
101 | {0x32, 0x67, 0x80}, /* 18: VCLK85_5 */ | 101 | {0x32, 0x67, 0x80}, /* 18: VCLK85_5 */ |
102 | {0x6a, 0x6d, 0x80}, /* 19: VCLK97_75 */ | ||
102 | }; | 103 | }; |
103 | 104 | ||
104 | static struct ast_vbios_stdtable vbios_stdtable[] = { | 105 | static struct ast_vbios_stdtable vbios_stdtable[] = { |
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index fa2be249999c..90e773019eac 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c | |||
@@ -4696,8 +4696,9 @@ int drm_mode_create_dumb_ioctl(struct drm_device *dev, | |||
4696 | return -EINVAL; | 4696 | return -EINVAL; |
4697 | 4697 | ||
4698 | /* overflow checks for 32bit size calculations */ | 4698 | /* overflow checks for 32bit size calculations */ |
4699 | /* NOTE: DIV_ROUND_UP() can overflow */ | ||
4699 | cpp = DIV_ROUND_UP(args->bpp, 8); | 4700 | cpp = DIV_ROUND_UP(args->bpp, 8); |
4700 | if (cpp > 0xffffffffU / args->width) | 4701 | if (!cpp || cpp > 0xffffffffU / args->width) |
4701 | return -EINVAL; | 4702 | return -EINVAL; |
4702 | stride = cpp * args->width; | 4703 | stride = cpp * args->width; |
4703 | if (args->height > 0xffffffffU / stride) | 4704 | if (args->height > 0xffffffffU / stride) |
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index ec96f9a9724c..e27cdbe9d524 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c | |||
@@ -494,6 +494,36 @@ bool i915_semaphore_is_enabled(struct drm_device *dev) | |||
494 | return true; | 494 | return true; |
495 | } | 495 | } |
496 | 496 | ||
497 | void intel_hpd_cancel_work(struct drm_i915_private *dev_priv) | ||
498 | { | ||
499 | spin_lock_irq(&dev_priv->irq_lock); | ||
500 | |||
501 | dev_priv->long_hpd_port_mask = 0; | ||
502 | dev_priv->short_hpd_port_mask = 0; | ||
503 | dev_priv->hpd_event_bits = 0; | ||
504 | |||
505 | spin_unlock_irq(&dev_priv->irq_lock); | ||
506 | |||
507 | cancel_work_sync(&dev_priv->dig_port_work); | ||
508 | cancel_work_sync(&dev_priv->hotplug_work); | ||
509 | cancel_delayed_work_sync(&dev_priv->hotplug_reenable_work); | ||
510 | } | ||
511 | |||
512 | static void intel_suspend_encoders(struct drm_i915_private *dev_priv) | ||
513 | { | ||
514 | struct drm_device *dev = dev_priv->dev; | ||
515 | struct drm_encoder *encoder; | ||
516 | |||
517 | drm_modeset_lock_all(dev); | ||
518 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | ||
519 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | ||
520 | |||
521 | if (intel_encoder->suspend) | ||
522 | intel_encoder->suspend(intel_encoder); | ||
523 | } | ||
524 | drm_modeset_unlock_all(dev); | ||
525 | } | ||
526 | |||
497 | static int i915_drm_freeze(struct drm_device *dev) | 527 | static int i915_drm_freeze(struct drm_device *dev) |
498 | { | 528 | { |
499 | struct drm_i915_private *dev_priv = dev->dev_private; | 529 | struct drm_i915_private *dev_priv = dev->dev_private; |
@@ -538,6 +568,9 @@ static int i915_drm_freeze(struct drm_device *dev) | |||
538 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); | 568 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
539 | 569 | ||
540 | intel_runtime_pm_disable_interrupts(dev); | 570 | intel_runtime_pm_disable_interrupts(dev); |
571 | intel_hpd_cancel_work(dev_priv); | ||
572 | |||
573 | intel_suspend_encoders(dev_priv); | ||
541 | 574 | ||
542 | intel_suspend_gt_powersave(dev); | 575 | intel_suspend_gt_powersave(dev); |
543 | 576 | ||
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 4412f6a4383b..7a830eac5ba3 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h | |||
@@ -1458,7 +1458,7 @@ struct drm_i915_private { | |||
1458 | } hpd_mark; | 1458 | } hpd_mark; |
1459 | } hpd_stats[HPD_NUM_PINS]; | 1459 | } hpd_stats[HPD_NUM_PINS]; |
1460 | u32 hpd_event_bits; | 1460 | u32 hpd_event_bits; |
1461 | struct timer_list hotplug_reenable_timer; | 1461 | struct delayed_work hotplug_reenable_work; |
1462 | 1462 | ||
1463 | struct i915_fbc fbc; | 1463 | struct i915_fbc fbc; |
1464 | struct i915_drrs drrs; | 1464 | struct i915_drrs drrs; |
@@ -2178,6 +2178,7 @@ extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |||
2178 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | 2178 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); |
2179 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | 2179 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); |
2180 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); | 2180 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); |
2181 | void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); | ||
2181 | 2182 | ||
2182 | extern void intel_console_resume(struct work_struct *work); | 2183 | extern void intel_console_resume(struct work_struct *work); |
2183 | 2184 | ||
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 390ccc2a3096..0050ee9470f1 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c | |||
@@ -1189,8 +1189,8 @@ static void i915_hotplug_work_func(struct work_struct *work) | |||
1189 | * some connectors */ | 1189 | * some connectors */ |
1190 | if (hpd_disabled) { | 1190 | if (hpd_disabled) { |
1191 | drm_kms_helper_poll_enable(dev); | 1191 | drm_kms_helper_poll_enable(dev); |
1192 | mod_timer(&dev_priv->hotplug_reenable_timer, | 1192 | mod_delayed_work(system_wq, &dev_priv->hotplug_reenable_work, |
1193 | jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY)); | 1193 | msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY)); |
1194 | } | 1194 | } |
1195 | 1195 | ||
1196 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | 1196 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
@@ -1213,11 +1213,6 @@ static void i915_hotplug_work_func(struct work_struct *work) | |||
1213 | drm_kms_helper_hotplug_event(dev); | 1213 | drm_kms_helper_hotplug_event(dev); |
1214 | } | 1214 | } |
1215 | 1215 | ||
1216 | static void intel_hpd_irq_uninstall(struct drm_i915_private *dev_priv) | ||
1217 | { | ||
1218 | del_timer_sync(&dev_priv->hotplug_reenable_timer); | ||
1219 | } | ||
1220 | |||
1221 | static void ironlake_rps_change_irq_handler(struct drm_device *dev) | 1216 | static void ironlake_rps_change_irq_handler(struct drm_device *dev) |
1222 | { | 1217 | { |
1223 | struct drm_i915_private *dev_priv = dev->dev_private; | 1218 | struct drm_i915_private *dev_priv = dev->dev_private; |
@@ -3892,8 +3887,6 @@ static void gen8_irq_uninstall(struct drm_device *dev) | |||
3892 | if (!dev_priv) | 3887 | if (!dev_priv) |
3893 | return; | 3888 | return; |
3894 | 3889 | ||
3895 | intel_hpd_irq_uninstall(dev_priv); | ||
3896 | |||
3897 | gen8_irq_reset(dev); | 3890 | gen8_irq_reset(dev); |
3898 | } | 3891 | } |
3899 | 3892 | ||
@@ -3908,8 +3901,6 @@ static void valleyview_irq_uninstall(struct drm_device *dev) | |||
3908 | 3901 | ||
3909 | I915_WRITE(VLV_MASTER_IER, 0); | 3902 | I915_WRITE(VLV_MASTER_IER, 0); |
3910 | 3903 | ||
3911 | intel_hpd_irq_uninstall(dev_priv); | ||
3912 | |||
3913 | for_each_pipe(pipe) | 3904 | for_each_pipe(pipe) |
3914 | I915_WRITE(PIPESTAT(pipe), 0xffff); | 3905 | I915_WRITE(PIPESTAT(pipe), 0xffff); |
3915 | 3906 | ||
@@ -3988,8 +3979,6 @@ static void ironlake_irq_uninstall(struct drm_device *dev) | |||
3988 | if (!dev_priv) | 3979 | if (!dev_priv) |
3989 | return; | 3980 | return; |
3990 | 3981 | ||
3991 | intel_hpd_irq_uninstall(dev_priv); | ||
3992 | |||
3993 | ironlake_irq_reset(dev); | 3982 | ironlake_irq_reset(dev); |
3994 | } | 3983 | } |
3995 | 3984 | ||
@@ -4360,8 +4349,6 @@ static void i915_irq_uninstall(struct drm_device * dev) | |||
4360 | struct drm_i915_private *dev_priv = dev->dev_private; | 4349 | struct drm_i915_private *dev_priv = dev->dev_private; |
4361 | int pipe; | 4350 | int pipe; |
4362 | 4351 | ||
4363 | intel_hpd_irq_uninstall(dev_priv); | ||
4364 | |||
4365 | if (I915_HAS_HOTPLUG(dev)) { | 4352 | if (I915_HAS_HOTPLUG(dev)) { |
4366 | I915_WRITE(PORT_HOTPLUG_EN, 0); | 4353 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
4367 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | 4354 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
@@ -4598,8 +4585,6 @@ static void i965_irq_uninstall(struct drm_device * dev) | |||
4598 | if (!dev_priv) | 4585 | if (!dev_priv) |
4599 | return; | 4586 | return; |
4600 | 4587 | ||
4601 | intel_hpd_irq_uninstall(dev_priv); | ||
4602 | |||
4603 | I915_WRITE(PORT_HOTPLUG_EN, 0); | 4588 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
4604 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | 4589 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
4605 | 4590 | ||
@@ -4615,14 +4600,18 @@ static void i965_irq_uninstall(struct drm_device * dev) | |||
4615 | I915_WRITE(IIR, I915_READ(IIR)); | 4600 | I915_WRITE(IIR, I915_READ(IIR)); |
4616 | } | 4601 | } |
4617 | 4602 | ||
4618 | static void intel_hpd_irq_reenable(unsigned long data) | 4603 | static void intel_hpd_irq_reenable(struct work_struct *work) |
4619 | { | 4604 | { |
4620 | struct drm_i915_private *dev_priv = (struct drm_i915_private *)data; | 4605 | struct drm_i915_private *dev_priv = |
4606 | container_of(work, typeof(*dev_priv), | ||
4607 | hotplug_reenable_work.work); | ||
4621 | struct drm_device *dev = dev_priv->dev; | 4608 | struct drm_device *dev = dev_priv->dev; |
4622 | struct drm_mode_config *mode_config = &dev->mode_config; | 4609 | struct drm_mode_config *mode_config = &dev->mode_config; |
4623 | unsigned long irqflags; | 4610 | unsigned long irqflags; |
4624 | int i; | 4611 | int i; |
4625 | 4612 | ||
4613 | intel_runtime_pm_get(dev_priv); | ||
4614 | |||
4626 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | 4615 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
4627 | for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) { | 4616 | for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) { |
4628 | struct drm_connector *connector; | 4617 | struct drm_connector *connector; |
@@ -4648,6 +4637,8 @@ static void intel_hpd_irq_reenable(unsigned long data) | |||
4648 | if (dev_priv->display.hpd_irq_setup) | 4637 | if (dev_priv->display.hpd_irq_setup) |
4649 | dev_priv->display.hpd_irq_setup(dev); | 4638 | dev_priv->display.hpd_irq_setup(dev); |
4650 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | 4639 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
4640 | |||
4641 | intel_runtime_pm_put(dev_priv); | ||
4651 | } | 4642 | } |
4652 | 4643 | ||
4653 | void intel_irq_init(struct drm_device *dev) | 4644 | void intel_irq_init(struct drm_device *dev) |
@@ -4670,8 +4661,8 @@ void intel_irq_init(struct drm_device *dev) | |||
4670 | setup_timer(&dev_priv->gpu_error.hangcheck_timer, | 4661 | setup_timer(&dev_priv->gpu_error.hangcheck_timer, |
4671 | i915_hangcheck_elapsed, | 4662 | i915_hangcheck_elapsed, |
4672 | (unsigned long) dev); | 4663 | (unsigned long) dev); |
4673 | setup_timer(&dev_priv->hotplug_reenable_timer, intel_hpd_irq_reenable, | 4664 | INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work, |
4674 | (unsigned long) dev_priv); | 4665 | intel_hpd_irq_reenable); |
4675 | 4666 | ||
4676 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); | 4667 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); |
4677 | 4668 | ||
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index a66955037e4e..eee79e1c3222 100644 --- a/drivers/gpu/drm/i915/intel_bios.c +++ b/drivers/gpu/drm/i915/intel_bios.c | |||
@@ -1123,7 +1123,7 @@ init_vbt_defaults(struct drm_i915_private *dev_priv) | |||
1123 | } | 1123 | } |
1124 | } | 1124 | } |
1125 | 1125 | ||
1126 | static int __init intel_no_opregion_vbt_callback(const struct dmi_system_id *id) | 1126 | static int intel_no_opregion_vbt_callback(const struct dmi_system_id *id) |
1127 | { | 1127 | { |
1128 | DRM_DEBUG_KMS("Falling back to manually reading VBT from " | 1128 | DRM_DEBUG_KMS("Falling back to manually reading VBT from " |
1129 | "VBIOS ROM for %s\n", | 1129 | "VBIOS ROM for %s\n", |
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index 2efaf8e8d9c4..9212e6504e0f 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c | |||
@@ -699,16 +699,21 @@ intel_crt_detect(struct drm_connector *connector, bool force) | |||
699 | goto out; | 699 | goto out; |
700 | } | 700 | } |
701 | 701 | ||
702 | drm_modeset_acquire_init(&ctx, 0); | ||
703 | |||
702 | /* for pre-945g platforms use load detect */ | 704 | /* for pre-945g platforms use load detect */ |
703 | if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) { | 705 | if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) { |
704 | if (intel_crt_detect_ddc(connector)) | 706 | if (intel_crt_detect_ddc(connector)) |
705 | status = connector_status_connected; | 707 | status = connector_status_connected; |
706 | else | 708 | else |
707 | status = intel_crt_load_detect(crt); | 709 | status = intel_crt_load_detect(crt); |
708 | intel_release_load_detect_pipe(connector, &tmp, &ctx); | 710 | intel_release_load_detect_pipe(connector, &tmp); |
709 | } else | 711 | } else |
710 | status = connector_status_unknown; | 712 | status = connector_status_unknown; |
711 | 713 | ||
714 | drm_modeset_drop_locks(&ctx); | ||
715 | drm_modeset_acquire_fini(&ctx); | ||
716 | |||
712 | out: | 717 | out: |
713 | intel_display_power_put(dev_priv, power_domain); | 718 | intel_display_power_put(dev_priv, power_domain); |
714 | return status; | 719 | return status; |
@@ -799,7 +804,7 @@ static const struct drm_encoder_funcs intel_crt_enc_funcs = { | |||
799 | .destroy = intel_encoder_destroy, | 804 | .destroy = intel_encoder_destroy, |
800 | }; | 805 | }; |
801 | 806 | ||
802 | static int __init intel_no_crt_dmi_callback(const struct dmi_system_id *id) | 807 | static int intel_no_crt_dmi_callback(const struct dmi_system_id *id) |
803 | { | 808 | { |
804 | DRM_INFO("Skipping CRT initialization for %s\n", id->ident); | 809 | DRM_INFO("Skipping CRT initialization for %s\n", id->ident); |
805 | return 1; | 810 | return 1; |
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 018fb7222f60..d8324c69fa86 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -2233,6 +2233,15 @@ intel_pin_and_fence_fb_obj(struct drm_device *dev, | |||
2233 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | 2233 | if (need_vtd_wa(dev) && alignment < 256 * 1024) |
2234 | alignment = 256 * 1024; | 2234 | alignment = 256 * 1024; |
2235 | 2235 | ||
2236 | /* | ||
2237 | * Global gtt pte registers are special registers which actually forward | ||
2238 | * writes to a chunk of system memory. Which means that there is no risk | ||
2239 | * that the register values disappear as soon as we call | ||
2240 | * intel_runtime_pm_put(), so it is correct to wrap only the | ||
2241 | * pin/unpin/fence and not more. | ||
2242 | */ | ||
2243 | intel_runtime_pm_get(dev_priv); | ||
2244 | |||
2236 | dev_priv->mm.interruptible = false; | 2245 | dev_priv->mm.interruptible = false; |
2237 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); | 2246 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
2238 | if (ret) | 2247 | if (ret) |
@@ -2250,12 +2259,14 @@ intel_pin_and_fence_fb_obj(struct drm_device *dev, | |||
2250 | i915_gem_object_pin_fence(obj); | 2259 | i915_gem_object_pin_fence(obj); |
2251 | 2260 | ||
2252 | dev_priv->mm.interruptible = true; | 2261 | dev_priv->mm.interruptible = true; |
2262 | intel_runtime_pm_put(dev_priv); | ||
2253 | return 0; | 2263 | return 0; |
2254 | 2264 | ||
2255 | err_unpin: | 2265 | err_unpin: |
2256 | i915_gem_object_unpin_from_display_plane(obj); | 2266 | i915_gem_object_unpin_from_display_plane(obj); |
2257 | err_interruptible: | 2267 | err_interruptible: |
2258 | dev_priv->mm.interruptible = true; | 2268 | dev_priv->mm.interruptible = true; |
2269 | intel_runtime_pm_put(dev_priv); | ||
2259 | return ret; | 2270 | return ret; |
2260 | } | 2271 | } |
2261 | 2272 | ||
@@ -4188,10 +4199,6 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc) | |||
4188 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); | 4199 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); |
4189 | 4200 | ||
4190 | intel_disable_pipe(dev_priv, pipe); | 4201 | intel_disable_pipe(dev_priv, pipe); |
4191 | |||
4192 | if (intel_crtc->config.dp_encoder_is_mst) | ||
4193 | intel_ddi_set_vc_payload_alloc(crtc, false); | ||
4194 | |||
4195 | ironlake_pfit_disable(intel_crtc); | 4202 | ironlake_pfit_disable(intel_crtc); |
4196 | 4203 | ||
4197 | for_each_encoder_on_crtc(dev, crtc, encoder) | 4204 | for_each_encoder_on_crtc(dev, crtc, encoder) |
@@ -4256,6 +4263,9 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) | |||
4256 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); | 4263 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); |
4257 | intel_disable_pipe(dev_priv, pipe); | 4264 | intel_disable_pipe(dev_priv, pipe); |
4258 | 4265 | ||
4266 | if (intel_crtc->config.dp_encoder_is_mst) | ||
4267 | intel_ddi_set_vc_payload_alloc(crtc, false); | ||
4268 | |||
4259 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); | 4269 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4260 | 4270 | ||
4261 | ironlake_pfit_disable(intel_crtc); | 4271 | ironlake_pfit_disable(intel_crtc); |
@@ -8240,6 +8250,15 @@ static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc, | |||
8240 | goto fail_locked; | 8250 | goto fail_locked; |
8241 | } | 8251 | } |
8242 | 8252 | ||
8253 | /* | ||
8254 | * Global gtt pte registers are special registers which actually | ||
8255 | * forward writes to a chunk of system memory. Which means that | ||
8256 | * there is no risk that the register values disappear as soon | ||
8257 | * as we call intel_runtime_pm_put(), so it is correct to wrap | ||
8258 | * only the pin/unpin/fence and not more. | ||
8259 | */ | ||
8260 | intel_runtime_pm_get(dev_priv); | ||
8261 | |||
8243 | /* Note that the w/a also requires 2 PTE of padding following | 8262 | /* Note that the w/a also requires 2 PTE of padding following |
8244 | * the bo. We currently fill all unused PTE with the shadow | 8263 | * the bo. We currently fill all unused PTE with the shadow |
8245 | * page and so we should always have valid PTE following the | 8264 | * page and so we should always have valid PTE following the |
@@ -8252,16 +8271,20 @@ static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc, | |||
8252 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); | 8271 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); |
8253 | if (ret) { | 8272 | if (ret) { |
8254 | DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n"); | 8273 | DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n"); |
8274 | intel_runtime_pm_put(dev_priv); | ||
8255 | goto fail_locked; | 8275 | goto fail_locked; |
8256 | } | 8276 | } |
8257 | 8277 | ||
8258 | ret = i915_gem_object_put_fence(obj); | 8278 | ret = i915_gem_object_put_fence(obj); |
8259 | if (ret) { | 8279 | if (ret) { |
8260 | DRM_DEBUG_KMS("failed to release fence for cursor"); | 8280 | DRM_DEBUG_KMS("failed to release fence for cursor"); |
8281 | intel_runtime_pm_put(dev_priv); | ||
8261 | goto fail_unpin; | 8282 | goto fail_unpin; |
8262 | } | 8283 | } |
8263 | 8284 | ||
8264 | addr = i915_gem_obj_ggtt_offset(obj); | 8285 | addr = i915_gem_obj_ggtt_offset(obj); |
8286 | |||
8287 | intel_runtime_pm_put(dev_priv); | ||
8265 | } else { | 8288 | } else { |
8266 | int align = IS_I830(dev) ? 16 * 1024 : 256; | 8289 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
8267 | ret = i915_gem_object_attach_phys(obj, align); | 8290 | ret = i915_gem_object_attach_phys(obj, align); |
@@ -8462,8 +8485,6 @@ bool intel_get_load_detect_pipe(struct drm_connector *connector, | |||
8462 | connector->base.id, connector->name, | 8485 | connector->base.id, connector->name, |
8463 | encoder->base.id, encoder->name); | 8486 | encoder->base.id, encoder->name); |
8464 | 8487 | ||
8465 | drm_modeset_acquire_init(ctx, 0); | ||
8466 | |||
8467 | retry: | 8488 | retry: |
8468 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | 8489 | ret = drm_modeset_lock(&config->connection_mutex, ctx); |
8469 | if (ret) | 8490 | if (ret) |
@@ -8502,10 +8523,14 @@ retry: | |||
8502 | i++; | 8523 | i++; |
8503 | if (!(encoder->possible_crtcs & (1 << i))) | 8524 | if (!(encoder->possible_crtcs & (1 << i))) |
8504 | continue; | 8525 | continue; |
8505 | if (!possible_crtc->enabled) { | 8526 | if (possible_crtc->enabled) |
8506 | crtc = possible_crtc; | 8527 | continue; |
8507 | break; | 8528 | /* This can occur when applying the pipe A quirk on resume. */ |
8508 | } | 8529 | if (to_intel_crtc(possible_crtc)->new_enabled) |
8530 | continue; | ||
8531 | |||
8532 | crtc = possible_crtc; | ||
8533 | break; | ||
8509 | } | 8534 | } |
8510 | 8535 | ||
8511 | /* | 8536 | /* |
@@ -8574,15 +8599,11 @@ fail_unlock: | |||
8574 | goto retry; | 8599 | goto retry; |
8575 | } | 8600 | } |
8576 | 8601 | ||
8577 | drm_modeset_drop_locks(ctx); | ||
8578 | drm_modeset_acquire_fini(ctx); | ||
8579 | |||
8580 | return false; | 8602 | return false; |
8581 | } | 8603 | } |
8582 | 8604 | ||
8583 | void intel_release_load_detect_pipe(struct drm_connector *connector, | 8605 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
8584 | struct intel_load_detect_pipe *old, | 8606 | struct intel_load_detect_pipe *old) |
8585 | struct drm_modeset_acquire_ctx *ctx) | ||
8586 | { | 8607 | { |
8587 | struct intel_encoder *intel_encoder = | 8608 | struct intel_encoder *intel_encoder = |
8588 | intel_attached_encoder(connector); | 8609 | intel_attached_encoder(connector); |
@@ -8606,17 +8627,12 @@ void intel_release_load_detect_pipe(struct drm_connector *connector, | |||
8606 | drm_framebuffer_unreference(old->release_fb); | 8627 | drm_framebuffer_unreference(old->release_fb); |
8607 | } | 8628 | } |
8608 | 8629 | ||
8609 | goto unlock; | ||
8610 | return; | 8630 | return; |
8611 | } | 8631 | } |
8612 | 8632 | ||
8613 | /* Switch crtc and encoder back off if necessary */ | 8633 | /* Switch crtc and encoder back off if necessary */ |
8614 | if (old->dpms_mode != DRM_MODE_DPMS_ON) | 8634 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
8615 | connector->funcs->dpms(connector, old->dpms_mode); | 8635 | connector->funcs->dpms(connector, old->dpms_mode); |
8616 | |||
8617 | unlock: | ||
8618 | drm_modeset_drop_locks(ctx); | ||
8619 | drm_modeset_acquire_fini(ctx); | ||
8620 | } | 8636 | } |
8621 | 8637 | ||
8622 | static int i9xx_pll_refclk(struct drm_device *dev, | 8638 | static int i9xx_pll_refclk(struct drm_device *dev, |
@@ -11700,8 +11716,8 @@ intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, | |||
11700 | }; | 11716 | }; |
11701 | const struct drm_rect clip = { | 11717 | const struct drm_rect clip = { |
11702 | /* integer pixels */ | 11718 | /* integer pixels */ |
11703 | .x2 = intel_crtc->config.pipe_src_w, | 11719 | .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0, |
11704 | .y2 = intel_crtc->config.pipe_src_h, | 11720 | .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0, |
11705 | }; | 11721 | }; |
11706 | bool visible; | 11722 | bool visible; |
11707 | int ret; | 11723 | int ret; |
@@ -12488,6 +12504,9 @@ static struct intel_quirk intel_quirks[] = { | |||
12488 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | 12504 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ |
12489 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | 12505 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, |
12490 | 12506 | ||
12507 | /* Acer C720 Chromebook (Core i3 4005U) */ | ||
12508 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | ||
12509 | |||
12491 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ | 12510 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
12492 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | 12511 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, |
12493 | 12512 | ||
@@ -12659,7 +12678,7 @@ static void intel_enable_pipe_a(struct drm_device *dev) | |||
12659 | struct intel_connector *connector; | 12678 | struct intel_connector *connector; |
12660 | struct drm_connector *crt = NULL; | 12679 | struct drm_connector *crt = NULL; |
12661 | struct intel_load_detect_pipe load_detect_temp; | 12680 | struct intel_load_detect_pipe load_detect_temp; |
12662 | struct drm_modeset_acquire_ctx ctx; | 12681 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
12663 | 12682 | ||
12664 | /* We can't just switch on the pipe A, we need to set things up with a | 12683 | /* We can't just switch on the pipe A, we need to set things up with a |
12665 | * proper mode and output configuration. As a gross hack, enable pipe A | 12684 | * proper mode and output configuration. As a gross hack, enable pipe A |
@@ -12676,10 +12695,8 @@ static void intel_enable_pipe_a(struct drm_device *dev) | |||
12676 | if (!crt) | 12695 | if (!crt) |
12677 | return; | 12696 | return; |
12678 | 12697 | ||
12679 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, &ctx)) | 12698 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
12680 | intel_release_load_detect_pipe(crt, &load_detect_temp, &ctx); | 12699 | intel_release_load_detect_pipe(crt, &load_detect_temp); |
12681 | |||
12682 | |||
12683 | } | 12700 | } |
12684 | 12701 | ||
12685 | static bool | 12702 | static bool |
@@ -13112,7 +13129,7 @@ void intel_modeset_cleanup(struct drm_device *dev) | |||
13112 | * experience fancy races otherwise. | 13129 | * experience fancy races otherwise. |
13113 | */ | 13130 | */ |
13114 | drm_irq_uninstall(dev); | 13131 | drm_irq_uninstall(dev); |
13115 | cancel_work_sync(&dev_priv->hotplug_work); | 13132 | intel_hpd_cancel_work(dev_priv); |
13116 | dev_priv->pm._irqs_disabled = true; | 13133 | dev_priv->pm._irqs_disabled = true; |
13117 | 13134 | ||
13118 | /* | 13135 | /* |
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index ee3942f0b068..81d7681faa63 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c | |||
@@ -3553,6 +3553,9 @@ intel_dp_check_link_status(struct intel_dp *intel_dp) | |||
3553 | if (WARN_ON(!intel_encoder->base.crtc)) | 3553 | if (WARN_ON(!intel_encoder->base.crtc)) |
3554 | return; | 3554 | return; |
3555 | 3555 | ||
3556 | if (!to_intel_crtc(intel_encoder->base.crtc)->active) | ||
3557 | return; | ||
3558 | |||
3556 | /* Try to read receiver status if the link appears to be up */ | 3559 | /* Try to read receiver status if the link appears to be up */ |
3557 | if (!intel_dp_get_link_status(intel_dp, link_status)) { | 3560 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
3558 | return; | 3561 | return; |
@@ -3658,24 +3661,12 @@ ironlake_dp_detect(struct intel_dp *intel_dp) | |||
3658 | return intel_dp_detect_dpcd(intel_dp); | 3661 | return intel_dp_detect_dpcd(intel_dp); |
3659 | } | 3662 | } |
3660 | 3663 | ||
3661 | static enum drm_connector_status | 3664 | static int g4x_digital_port_connected(struct drm_device *dev, |
3662 | g4x_dp_detect(struct intel_dp *intel_dp) | 3665 | struct intel_digital_port *intel_dig_port) |
3663 | { | 3666 | { |
3664 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | ||
3665 | struct drm_i915_private *dev_priv = dev->dev_private; | 3667 | struct drm_i915_private *dev_priv = dev->dev_private; |
3666 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | ||
3667 | uint32_t bit; | 3668 | uint32_t bit; |
3668 | 3669 | ||
3669 | /* Can't disconnect eDP, but you can close the lid... */ | ||
3670 | if (is_edp(intel_dp)) { | ||
3671 | enum drm_connector_status status; | ||
3672 | |||
3673 | status = intel_panel_detect(dev); | ||
3674 | if (status == connector_status_unknown) | ||
3675 | status = connector_status_connected; | ||
3676 | return status; | ||
3677 | } | ||
3678 | |||
3679 | if (IS_VALLEYVIEW(dev)) { | 3670 | if (IS_VALLEYVIEW(dev)) { |
3680 | switch (intel_dig_port->port) { | 3671 | switch (intel_dig_port->port) { |
3681 | case PORT_B: | 3672 | case PORT_B: |
@@ -3688,7 +3679,7 @@ g4x_dp_detect(struct intel_dp *intel_dp) | |||
3688 | bit = PORTD_HOTPLUG_LIVE_STATUS_VLV; | 3679 | bit = PORTD_HOTPLUG_LIVE_STATUS_VLV; |
3689 | break; | 3680 | break; |
3690 | default: | 3681 | default: |
3691 | return connector_status_unknown; | 3682 | return -EINVAL; |
3692 | } | 3683 | } |
3693 | } else { | 3684 | } else { |
3694 | switch (intel_dig_port->port) { | 3685 | switch (intel_dig_port->port) { |
@@ -3702,11 +3693,36 @@ g4x_dp_detect(struct intel_dp *intel_dp) | |||
3702 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; | 3693 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; |
3703 | break; | 3694 | break; |
3704 | default: | 3695 | default: |
3705 | return connector_status_unknown; | 3696 | return -EINVAL; |
3706 | } | 3697 | } |
3707 | } | 3698 | } |
3708 | 3699 | ||
3709 | if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) | 3700 | if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) |
3701 | return 0; | ||
3702 | return 1; | ||
3703 | } | ||
3704 | |||
3705 | static enum drm_connector_status | ||
3706 | g4x_dp_detect(struct intel_dp *intel_dp) | ||
3707 | { | ||
3708 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | ||
3709 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | ||
3710 | int ret; | ||
3711 | |||
3712 | /* Can't disconnect eDP, but you can close the lid... */ | ||
3713 | if (is_edp(intel_dp)) { | ||
3714 | enum drm_connector_status status; | ||
3715 | |||
3716 | status = intel_panel_detect(dev); | ||
3717 | if (status == connector_status_unknown) | ||
3718 | status = connector_status_connected; | ||
3719 | return status; | ||
3720 | } | ||
3721 | |||
3722 | ret = g4x_digital_port_connected(dev, intel_dig_port); | ||
3723 | if (ret == -EINVAL) | ||
3724 | return connector_status_unknown; | ||
3725 | else if (ret == 0) | ||
3710 | return connector_status_disconnected; | 3726 | return connector_status_disconnected; |
3711 | 3727 | ||
3712 | return intel_dp_detect_dpcd(intel_dp); | 3728 | return intel_dp_detect_dpcd(intel_dp); |
@@ -4003,6 +4019,16 @@ void intel_dp_encoder_destroy(struct drm_encoder *encoder) | |||
4003 | kfree(intel_dig_port); | 4019 | kfree(intel_dig_port); |
4004 | } | 4020 | } |
4005 | 4021 | ||
4022 | static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) | ||
4023 | { | ||
4024 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | ||
4025 | |||
4026 | if (!is_edp(intel_dp)) | ||
4027 | return; | ||
4028 | |||
4029 | edp_panel_vdd_off_sync(intel_dp); | ||
4030 | } | ||
4031 | |||
4006 | static void intel_dp_encoder_reset(struct drm_encoder *encoder) | 4032 | static void intel_dp_encoder_reset(struct drm_encoder *encoder) |
4007 | { | 4033 | { |
4008 | intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder)); | 4034 | intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder)); |
@@ -4037,18 +4063,30 @@ bool | |||
4037 | intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) | 4063 | intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) |
4038 | { | 4064 | { |
4039 | struct intel_dp *intel_dp = &intel_dig_port->dp; | 4065 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
4066 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | ||
4040 | struct drm_device *dev = intel_dig_port->base.base.dev; | 4067 | struct drm_device *dev = intel_dig_port->base.base.dev; |
4041 | struct drm_i915_private *dev_priv = dev->dev_private; | 4068 | struct drm_i915_private *dev_priv = dev->dev_private; |
4042 | int ret; | 4069 | enum intel_display_power_domain power_domain; |
4070 | bool ret = true; | ||
4071 | |||
4043 | if (intel_dig_port->base.type != INTEL_OUTPUT_EDP) | 4072 | if (intel_dig_port->base.type != INTEL_OUTPUT_EDP) |
4044 | intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT; | 4073 | intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT; |
4045 | 4074 | ||
4046 | DRM_DEBUG_KMS("got hpd irq on port %d - %s\n", intel_dig_port->port, | 4075 | DRM_DEBUG_KMS("got hpd irq on port %d - %s\n", intel_dig_port->port, |
4047 | long_hpd ? "long" : "short"); | 4076 | long_hpd ? "long" : "short"); |
4048 | 4077 | ||
4078 | power_domain = intel_display_port_power_domain(intel_encoder); | ||
4079 | intel_display_power_get(dev_priv, power_domain); | ||
4080 | |||
4049 | if (long_hpd) { | 4081 | if (long_hpd) { |
4050 | if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) | 4082 | |
4051 | goto mst_fail; | 4083 | if (HAS_PCH_SPLIT(dev)) { |
4084 | if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) | ||
4085 | goto mst_fail; | ||
4086 | } else { | ||
4087 | if (g4x_digital_port_connected(dev, intel_dig_port) != 1) | ||
4088 | goto mst_fail; | ||
4089 | } | ||
4052 | 4090 | ||
4053 | if (!intel_dp_get_dpcd(intel_dp)) { | 4091 | if (!intel_dp_get_dpcd(intel_dp)) { |
4054 | goto mst_fail; | 4092 | goto mst_fail; |
@@ -4061,8 +4099,7 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) | |||
4061 | 4099 | ||
4062 | } else { | 4100 | } else { |
4063 | if (intel_dp->is_mst) { | 4101 | if (intel_dp->is_mst) { |
4064 | ret = intel_dp_check_mst_status(intel_dp); | 4102 | if (intel_dp_check_mst_status(intel_dp) == -EINVAL) |
4065 | if (ret == -EINVAL) | ||
4066 | goto mst_fail; | 4103 | goto mst_fail; |
4067 | } | 4104 | } |
4068 | 4105 | ||
@@ -4076,7 +4113,8 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) | |||
4076 | drm_modeset_unlock(&dev->mode_config.connection_mutex); | 4113 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
4077 | } | 4114 | } |
4078 | } | 4115 | } |
4079 | return false; | 4116 | ret = false; |
4117 | goto put_power; | ||
4080 | mst_fail: | 4118 | mst_fail: |
4081 | /* if we were in MST mode, and device is not there get out of MST mode */ | 4119 | /* if we were in MST mode, and device is not there get out of MST mode */ |
4082 | if (intel_dp->is_mst) { | 4120 | if (intel_dp->is_mst) { |
@@ -4084,7 +4122,10 @@ mst_fail: | |||
4084 | intel_dp->is_mst = false; | 4122 | intel_dp->is_mst = false; |
4085 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); | 4123 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
4086 | } | 4124 | } |
4087 | return true; | 4125 | put_power: |
4126 | intel_display_power_put(dev_priv, power_domain); | ||
4127 | |||
4128 | return ret; | ||
4088 | } | 4129 | } |
4089 | 4130 | ||
4090 | /* Return which DP Port should be selected for Transcoder DP control */ | 4131 | /* Return which DP Port should be selected for Transcoder DP control */ |
@@ -4722,6 +4763,7 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port) | |||
4722 | intel_encoder->disable = intel_disable_dp; | 4763 | intel_encoder->disable = intel_disable_dp; |
4723 | intel_encoder->get_hw_state = intel_dp_get_hw_state; | 4764 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
4724 | intel_encoder->get_config = intel_dp_get_config; | 4765 | intel_encoder->get_config = intel_dp_get_config; |
4766 | intel_encoder->suspend = intel_dp_encoder_suspend; | ||
4725 | if (IS_CHERRYVIEW(dev)) { | 4767 | if (IS_CHERRYVIEW(dev)) { |
4726 | intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; | 4768 | intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; |
4727 | intel_encoder->pre_enable = chv_pre_enable_dp; | 4769 | intel_encoder->pre_enable = chv_pre_enable_dp; |
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 4b2664bd5b81..b8c8bbd8e5f9 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h | |||
@@ -153,6 +153,12 @@ struct intel_encoder { | |||
153 | * be set correctly before calling this function. */ | 153 | * be set correctly before calling this function. */ |
154 | void (*get_config)(struct intel_encoder *, | 154 | void (*get_config)(struct intel_encoder *, |
155 | struct intel_crtc_config *pipe_config); | 155 | struct intel_crtc_config *pipe_config); |
156 | /* | ||
157 | * Called during system suspend after all pending requests for the | ||
158 | * encoder are flushed (for example for DP AUX transactions) and | ||
159 | * device interrupts are disabled. | ||
160 | */ | ||
161 | void (*suspend)(struct intel_encoder *); | ||
156 | int crtc_mask; | 162 | int crtc_mask; |
157 | enum hpd_pin hpd_pin; | 163 | enum hpd_pin hpd_pin; |
158 | }; | 164 | }; |
@@ -830,8 +836,7 @@ bool intel_get_load_detect_pipe(struct drm_connector *connector, | |||
830 | struct intel_load_detect_pipe *old, | 836 | struct intel_load_detect_pipe *old, |
831 | struct drm_modeset_acquire_ctx *ctx); | 837 | struct drm_modeset_acquire_ctx *ctx); |
832 | void intel_release_load_detect_pipe(struct drm_connector *connector, | 838 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
833 | struct intel_load_detect_pipe *old, | 839 | struct intel_load_detect_pipe *old); |
834 | struct drm_modeset_acquire_ctx *ctx); | ||
835 | int intel_pin_and_fence_fb_obj(struct drm_device *dev, | 840 | int intel_pin_and_fence_fb_obj(struct drm_device *dev, |
836 | struct drm_i915_gem_object *obj, | 841 | struct drm_i915_gem_object *obj, |
837 | struct intel_engine_cs *pipelined); | 842 | struct intel_engine_cs *pipelined); |
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index 881361c0f27e..fdf40267249c 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c | |||
@@ -538,7 +538,7 @@ static const struct drm_encoder_funcs intel_lvds_enc_funcs = { | |||
538 | .destroy = intel_encoder_destroy, | 538 | .destroy = intel_encoder_destroy, |
539 | }; | 539 | }; |
540 | 540 | ||
541 | static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id) | 541 | static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id) |
542 | { | 542 | { |
543 | DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); | 543 | DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); |
544 | return 1; | 544 | return 1; |
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index 59b028f0b1e8..8e374449c6b5 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c | |||
@@ -801,7 +801,7 @@ static void pch_enable_backlight(struct intel_connector *connector) | |||
801 | 801 | ||
802 | cpu_ctl2 = I915_READ(BLC_PWM_CPU_CTL2); | 802 | cpu_ctl2 = I915_READ(BLC_PWM_CPU_CTL2); |
803 | if (cpu_ctl2 & BLM_PWM_ENABLE) { | 803 | if (cpu_ctl2 & BLM_PWM_ENABLE) { |
804 | WARN(1, "cpu backlight already enabled\n"); | 804 | DRM_DEBUG_KMS("cpu backlight already enabled\n"); |
805 | cpu_ctl2 &= ~BLM_PWM_ENABLE; | 805 | cpu_ctl2 &= ~BLM_PWM_ENABLE; |
806 | I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2); | 806 | I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2); |
807 | } | 807 | } |
@@ -845,7 +845,7 @@ static void i9xx_enable_backlight(struct intel_connector *connector) | |||
845 | 845 | ||
846 | ctl = I915_READ(BLC_PWM_CTL); | 846 | ctl = I915_READ(BLC_PWM_CTL); |
847 | if (ctl & BACKLIGHT_DUTY_CYCLE_MASK_PNV) { | 847 | if (ctl & BACKLIGHT_DUTY_CYCLE_MASK_PNV) { |
848 | WARN(1, "backlight already enabled\n"); | 848 | DRM_DEBUG_KMS("backlight already enabled\n"); |
849 | I915_WRITE(BLC_PWM_CTL, 0); | 849 | I915_WRITE(BLC_PWM_CTL, 0); |
850 | } | 850 | } |
851 | 851 | ||
@@ -876,7 +876,7 @@ static void i965_enable_backlight(struct intel_connector *connector) | |||
876 | 876 | ||
877 | ctl2 = I915_READ(BLC_PWM_CTL2); | 877 | ctl2 = I915_READ(BLC_PWM_CTL2); |
878 | if (ctl2 & BLM_PWM_ENABLE) { | 878 | if (ctl2 & BLM_PWM_ENABLE) { |
879 | WARN(1, "backlight already enabled\n"); | 879 | DRM_DEBUG_KMS("backlight already enabled\n"); |
880 | ctl2 &= ~BLM_PWM_ENABLE; | 880 | ctl2 &= ~BLM_PWM_ENABLE; |
881 | I915_WRITE(BLC_PWM_CTL2, ctl2); | 881 | I915_WRITE(BLC_PWM_CTL2, ctl2); |
882 | } | 882 | } |
@@ -910,7 +910,7 @@ static void vlv_enable_backlight(struct intel_connector *connector) | |||
910 | 910 | ||
911 | ctl2 = I915_READ(VLV_BLC_PWM_CTL2(pipe)); | 911 | ctl2 = I915_READ(VLV_BLC_PWM_CTL2(pipe)); |
912 | if (ctl2 & BLM_PWM_ENABLE) { | 912 | if (ctl2 & BLM_PWM_ENABLE) { |
913 | WARN(1, "backlight already enabled\n"); | 913 | DRM_DEBUG_KMS("backlight already enabled\n"); |
914 | ctl2 &= ~BLM_PWM_ENABLE; | 914 | ctl2 &= ~BLM_PWM_ENABLE; |
915 | I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2); | 915 | I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2); |
916 | } | 916 | } |
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c index e211eef4b7e4..c69d3ce1b3d6 100644 --- a/drivers/gpu/drm/i915/intel_tv.c +++ b/drivers/gpu/drm/i915/intel_tv.c | |||
@@ -1311,6 +1311,7 @@ intel_tv_detect(struct drm_connector *connector, bool force) | |||
1311 | { | 1311 | { |
1312 | struct drm_display_mode mode; | 1312 | struct drm_display_mode mode; |
1313 | struct intel_tv *intel_tv = intel_attached_tv(connector); | 1313 | struct intel_tv *intel_tv = intel_attached_tv(connector); |
1314 | enum drm_connector_status status; | ||
1314 | int type; | 1315 | int type; |
1315 | 1316 | ||
1316 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", | 1317 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", |
@@ -1323,16 +1324,24 @@ intel_tv_detect(struct drm_connector *connector, bool force) | |||
1323 | struct intel_load_detect_pipe tmp; | 1324 | struct intel_load_detect_pipe tmp; |
1324 | struct drm_modeset_acquire_ctx ctx; | 1325 | struct drm_modeset_acquire_ctx ctx; |
1325 | 1326 | ||
1327 | drm_modeset_acquire_init(&ctx, 0); | ||
1328 | |||
1326 | if (intel_get_load_detect_pipe(connector, &mode, &tmp, &ctx)) { | 1329 | if (intel_get_load_detect_pipe(connector, &mode, &tmp, &ctx)) { |
1327 | type = intel_tv_detect_type(intel_tv, connector); | 1330 | type = intel_tv_detect_type(intel_tv, connector); |
1328 | intel_release_load_detect_pipe(connector, &tmp, &ctx); | 1331 | intel_release_load_detect_pipe(connector, &tmp); |
1332 | status = type < 0 ? | ||
1333 | connector_status_disconnected : | ||
1334 | connector_status_connected; | ||
1329 | } else | 1335 | } else |
1330 | return connector_status_unknown; | 1336 | status = connector_status_unknown; |
1337 | |||
1338 | drm_modeset_drop_locks(&ctx); | ||
1339 | drm_modeset_acquire_fini(&ctx); | ||
1331 | } else | 1340 | } else |
1332 | return connector->status; | 1341 | return connector->status; |
1333 | 1342 | ||
1334 | if (type < 0) | 1343 | if (status != connector_status_connected) |
1335 | return connector_status_disconnected; | 1344 | return status; |
1336 | 1345 | ||
1337 | intel_tv->type = type; | 1346 | intel_tv->type = type; |
1338 | intel_tv_find_better_format(connector); | 1347 | intel_tv_find_better_format(connector); |
diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c index 74cebb51e8c2..c6c80ea28c35 100644 --- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c +++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c | |||
@@ -397,6 +397,7 @@ static void mdp4_crtc_prepare(struct drm_crtc *crtc) | |||
397 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); | 397 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); |
398 | DBG("%s", mdp4_crtc->name); | 398 | DBG("%s", mdp4_crtc->name); |
399 | /* make sure we hold a ref to mdp clks while setting up mode: */ | 399 | /* make sure we hold a ref to mdp clks while setting up mode: */ |
400 | drm_crtc_vblank_get(crtc); | ||
400 | mdp4_enable(get_kms(crtc)); | 401 | mdp4_enable(get_kms(crtc)); |
401 | mdp4_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); | 402 | mdp4_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
402 | } | 403 | } |
@@ -407,6 +408,7 @@ static void mdp4_crtc_commit(struct drm_crtc *crtc) | |||
407 | crtc_flush(crtc); | 408 | crtc_flush(crtc); |
408 | /* drop the ref to mdp clk's that we got in prepare: */ | 409 | /* drop the ref to mdp clk's that we got in prepare: */ |
409 | mdp4_disable(get_kms(crtc)); | 410 | mdp4_disable(get_kms(crtc)); |
411 | drm_crtc_vblank_put(crtc); | ||
410 | } | 412 | } |
411 | 413 | ||
412 | static int mdp4_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, | 414 | static int mdp4_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, |
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index b447c01ad89c..26ee80db17af 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c | |||
@@ -974,12 +974,11 @@ static int msm_pdev_probe(struct platform_device *pdev) | |||
974 | 974 | ||
975 | for (i = 0; i < ARRAY_SIZE(devnames); i++) { | 975 | for (i = 0; i < ARRAY_SIZE(devnames); i++) { |
976 | struct device *dev; | 976 | struct device *dev; |
977 | int ret; | ||
978 | 977 | ||
979 | dev = bus_find_device_by_name(&platform_bus_type, | 978 | dev = bus_find_device_by_name(&platform_bus_type, |
980 | NULL, devnames[i]); | 979 | NULL, devnames[i]); |
981 | if (!dev) { | 980 | if (!dev) { |
982 | dev_info(master, "still waiting for %s\n", devnames[i]); | 981 | dev_info(&pdev->dev, "still waiting for %s\n", devnames[i]); |
983 | return -EPROBE_DEFER; | 982 | return -EPROBE_DEFER; |
984 | } | 983 | } |
985 | 984 | ||
diff --git a/drivers/gpu/drm/msm/msm_fbdev.c b/drivers/gpu/drm/msm/msm_fbdev.c index 9c5221ce391a..ab5bfd2d0ebf 100644 --- a/drivers/gpu/drm/msm/msm_fbdev.c +++ b/drivers/gpu/drm/msm/msm_fbdev.c | |||
@@ -143,7 +143,7 @@ static int msm_fbdev_create(struct drm_fb_helper *helper, | |||
143 | ret = msm_gem_get_iova_locked(fbdev->bo, 0, &paddr); | 143 | ret = msm_gem_get_iova_locked(fbdev->bo, 0, &paddr); |
144 | if (ret) { | 144 | if (ret) { |
145 | dev_err(dev->dev, "failed to get buffer obj iova: %d\n", ret); | 145 | dev_err(dev->dev, "failed to get buffer obj iova: %d\n", ret); |
146 | goto fail; | 146 | goto fail_unlock; |
147 | } | 147 | } |
148 | 148 | ||
149 | fbi = framebuffer_alloc(0, dev->dev); | 149 | fbi = framebuffer_alloc(0, dev->dev); |
diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c index 099af483fdf0..7acdaa5688b7 100644 --- a/drivers/gpu/drm/msm/msm_iommu.c +++ b/drivers/gpu/drm/msm/msm_iommu.c | |||
@@ -27,8 +27,8 @@ struct msm_iommu { | |||
27 | static int msm_fault_handler(struct iommu_domain *iommu, struct device *dev, | 27 | static int msm_fault_handler(struct iommu_domain *iommu, struct device *dev, |
28 | unsigned long iova, int flags, void *arg) | 28 | unsigned long iova, int flags, void *arg) |
29 | { | 29 | { |
30 | DBG("*** fault: iova=%08lx, flags=%d", iova, flags); | 30 | pr_warn_ratelimited("*** fault: iova=%08lx, flags=%d\n", iova, flags); |
31 | return -ENOSYS; | 31 | return 0; |
32 | } | 32 | } |
33 | 33 | ||
34 | static int msm_iommu_attach(struct msm_mmu *mmu, const char **names, int cnt) | 34 | static int msm_iommu_attach(struct msm_mmu *mmu, const char **names, int cnt) |
diff --git a/drivers/gpu/drm/nouveau/core/core/parent.c b/drivers/gpu/drm/nouveau/core/core/parent.c index 8701968a9743..30a2911878f8 100644 --- a/drivers/gpu/drm/nouveau/core/core/parent.c +++ b/drivers/gpu/drm/nouveau/core/core/parent.c | |||
@@ -86,7 +86,7 @@ nouveau_parent_lclass(struct nouveau_object *parent, u32 *lclass, int size) | |||
86 | sclass = nv_parent(parent)->sclass; | 86 | sclass = nv_parent(parent)->sclass; |
87 | while (sclass) { | 87 | while (sclass) { |
88 | if (++nr < size) | 88 | if (++nr < size) |
89 | lclass[nr] = sclass->oclass->handle; | 89 | lclass[nr] = sclass->oclass->handle & 0xffff; |
90 | sclass = sclass->sclass; | 90 | sclass = sclass->sclass; |
91 | } | 91 | } |
92 | 92 | ||
@@ -96,7 +96,7 @@ nouveau_parent_lclass(struct nouveau_object *parent, u32 *lclass, int size) | |||
96 | if (engine && (oclass = engine->sclass)) { | 96 | if (engine && (oclass = engine->sclass)) { |
97 | while (oclass->ofuncs) { | 97 | while (oclass->ofuncs) { |
98 | if (++nr < size) | 98 | if (++nr < size) |
99 | lclass[nr] = oclass->handle; | 99 | lclass[nr] = oclass->handle & 0xffff; |
100 | oclass++; | 100 | oclass++; |
101 | } | 101 | } |
102 | } | 102 | } |
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile index 0013ad0db9ef..f77b7135ee4c 100644 --- a/drivers/gpu/drm/radeon/Makefile +++ b/drivers/gpu/drm/radeon/Makefile | |||
@@ -76,7 +76,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \ | |||
76 | evergreen.o evergreen_cs.o evergreen_blit_shaders.o \ | 76 | evergreen.o evergreen_cs.o evergreen_blit_shaders.o \ |
77 | evergreen_hdmi.o radeon_trace_points.o ni.o cayman_blit_shaders.o \ | 77 | evergreen_hdmi.o radeon_trace_points.o ni.o cayman_blit_shaders.o \ |
78 | atombios_encoders.o radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o \ | 78 | atombios_encoders.o radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o \ |
79 | si_blit_shaders.o radeon_prime.o radeon_uvd.o cik.o cik_blit_shaders.o \ | 79 | si_blit_shaders.o radeon_prime.o cik.o cik_blit_shaders.o \ |
80 | r600_dpm.o rs780_dpm.o rv6xx_dpm.o rv770_dpm.o rv730_dpm.o rv740_dpm.o \ | 80 | r600_dpm.o rs780_dpm.o rv6xx_dpm.o rv770_dpm.o rv730_dpm.o rv740_dpm.o \ |
81 | rv770_smc.o cypress_dpm.o btc_dpm.o sumo_dpm.o sumo_smc.o trinity_dpm.o \ | 81 | rv770_smc.o cypress_dpm.o btc_dpm.o sumo_dpm.o sumo_smc.o trinity_dpm.o \ |
82 | trinity_smc.o ni_dpm.o si_smc.o si_dpm.o kv_smc.o kv_dpm.o ci_smc.o \ | 82 | trinity_smc.o ni_dpm.o si_smc.o si_dpm.o kv_smc.o kv_dpm.o ci_smc.o \ |
diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c index 022561e28707..d416bb2ff48d 100644 --- a/drivers/gpu/drm/radeon/ci_dpm.c +++ b/drivers/gpu/drm/radeon/ci_dpm.c | |||
@@ -869,6 +869,9 @@ static int ci_set_thermal_temperature_range(struct radeon_device *rdev, | |||
869 | WREG32_SMC(CG_THERMAL_CTRL, tmp); | 869 | WREG32_SMC(CG_THERMAL_CTRL, tmp); |
870 | #endif | 870 | #endif |
871 | 871 | ||
872 | rdev->pm.dpm.thermal.min_temp = low_temp; | ||
873 | rdev->pm.dpm.thermal.max_temp = high_temp; | ||
874 | |||
872 | return 0; | 875 | return 0; |
873 | } | 876 | } |
874 | 877 | ||
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index b625646bf3e2..fa9565957f9d 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c | |||
@@ -3483,7 +3483,7 @@ static void cik_gpu_init(struct radeon_device *rdev) | |||
3483 | u32 mc_shared_chmap, mc_arb_ramcfg; | 3483 | u32 mc_shared_chmap, mc_arb_ramcfg; |
3484 | u32 hdp_host_path_cntl; | 3484 | u32 hdp_host_path_cntl; |
3485 | u32 tmp; | 3485 | u32 tmp; |
3486 | int i, j, k; | 3486 | int i, j; |
3487 | 3487 | ||
3488 | switch (rdev->family) { | 3488 | switch (rdev->family) { |
3489 | case CHIP_BONAIRE: | 3489 | case CHIP_BONAIRE: |
@@ -3544,6 +3544,7 @@ static void cik_gpu_init(struct radeon_device *rdev) | |||
3544 | (rdev->pdev->device == 0x130B) || | 3544 | (rdev->pdev->device == 0x130B) || |
3545 | (rdev->pdev->device == 0x130E) || | 3545 | (rdev->pdev->device == 0x130E) || |
3546 | (rdev->pdev->device == 0x1315) || | 3546 | (rdev->pdev->device == 0x1315) || |
3547 | (rdev->pdev->device == 0x1318) || | ||
3547 | (rdev->pdev->device == 0x131B)) { | 3548 | (rdev->pdev->device == 0x131B)) { |
3548 | rdev->config.cik.max_cu_per_sh = 4; | 3549 | rdev->config.cik.max_cu_per_sh = 4; |
3549 | rdev->config.cik.max_backends_per_se = 1; | 3550 | rdev->config.cik.max_backends_per_se = 1; |
@@ -3672,12 +3673,11 @@ static void cik_gpu_init(struct radeon_device *rdev) | |||
3672 | rdev->config.cik.max_sh_per_se, | 3673 | rdev->config.cik.max_sh_per_se, |
3673 | rdev->config.cik.max_backends_per_se); | 3674 | rdev->config.cik.max_backends_per_se); |
3674 | 3675 | ||
3676 | rdev->config.cik.active_cus = 0; | ||
3675 | for (i = 0; i < rdev->config.cik.max_shader_engines; i++) { | 3677 | for (i = 0; i < rdev->config.cik.max_shader_engines; i++) { |
3676 | for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) { | 3678 | for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) { |
3677 | for (k = 0; k < rdev->config.cik.max_cu_per_sh; k++) { | 3679 | rdev->config.cik.active_cus += |
3678 | rdev->config.cik.active_cus += | 3680 | hweight32(cik_get_cu_active_bitmap(rdev, i, j)); |
3679 | hweight32(cik_get_cu_active_bitmap(rdev, i, j)); | ||
3680 | } | ||
3681 | } | 3681 | } |
3682 | } | 3682 | } |
3683 | 3683 | ||
@@ -3801,7 +3801,7 @@ int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) | |||
3801 | radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); | 3801 | radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); |
3802 | radeon_ring_write(ring, ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2)); | 3802 | radeon_ring_write(ring, ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2)); |
3803 | radeon_ring_write(ring, 0xDEADBEEF); | 3803 | radeon_ring_write(ring, 0xDEADBEEF); |
3804 | radeon_ring_unlock_commit(rdev, ring); | 3804 | radeon_ring_unlock_commit(rdev, ring, false); |
3805 | 3805 | ||
3806 | for (i = 0; i < rdev->usec_timeout; i++) { | 3806 | for (i = 0; i < rdev->usec_timeout; i++) { |
3807 | tmp = RREG32(scratch); | 3807 | tmp = RREG32(scratch); |
@@ -3920,6 +3920,17 @@ void cik_fence_compute_ring_emit(struct radeon_device *rdev, | |||
3920 | radeon_ring_write(ring, 0); | 3920 | radeon_ring_write(ring, 0); |
3921 | } | 3921 | } |
3922 | 3922 | ||
3923 | /** | ||
3924 | * cik_semaphore_ring_emit - emit a semaphore on the CP ring | ||
3925 | * | ||
3926 | * @rdev: radeon_device pointer | ||
3927 | * @ring: radeon ring buffer object | ||
3928 | * @semaphore: radeon semaphore object | ||
3929 | * @emit_wait: Is this a sempahore wait? | ||
3930 | * | ||
3931 | * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP | ||
3932 | * from running ahead of semaphore waits. | ||
3933 | */ | ||
3923 | bool cik_semaphore_ring_emit(struct radeon_device *rdev, | 3934 | bool cik_semaphore_ring_emit(struct radeon_device *rdev, |
3924 | struct radeon_ring *ring, | 3935 | struct radeon_ring *ring, |
3925 | struct radeon_semaphore *semaphore, | 3936 | struct radeon_semaphore *semaphore, |
@@ -3932,6 +3943,12 @@ bool cik_semaphore_ring_emit(struct radeon_device *rdev, | |||
3932 | radeon_ring_write(ring, lower_32_bits(addr)); | 3943 | radeon_ring_write(ring, lower_32_bits(addr)); |
3933 | radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel); | 3944 | radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel); |
3934 | 3945 | ||
3946 | if (emit_wait && ring->idx == RADEON_RING_TYPE_GFX_INDEX) { | ||
3947 | /* Prevent the PFP from running ahead of the semaphore wait */ | ||
3948 | radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); | ||
3949 | radeon_ring_write(ring, 0x0); | ||
3950 | } | ||
3951 | |||
3935 | return true; | 3952 | return true; |
3936 | } | 3953 | } |
3937 | 3954 | ||
@@ -4004,7 +4021,7 @@ int cik_copy_cpdma(struct radeon_device *rdev, | |||
4004 | return r; | 4021 | return r; |
4005 | } | 4022 | } |
4006 | 4023 | ||
4007 | radeon_ring_unlock_commit(rdev, ring); | 4024 | radeon_ring_unlock_commit(rdev, ring, false); |
4008 | radeon_semaphore_free(rdev, &sem, *fence); | 4025 | radeon_semaphore_free(rdev, &sem, *fence); |
4009 | 4026 | ||
4010 | return r; | 4027 | return r; |
@@ -4103,7 +4120,7 @@ int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) | |||
4103 | ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2); | 4120 | ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2); |
4104 | ib.ptr[2] = 0xDEADBEEF; | 4121 | ib.ptr[2] = 0xDEADBEEF; |
4105 | ib.length_dw = 3; | 4122 | ib.length_dw = 3; |
4106 | r = radeon_ib_schedule(rdev, &ib, NULL); | 4123 | r = radeon_ib_schedule(rdev, &ib, NULL, false); |
4107 | if (r) { | 4124 | if (r) { |
4108 | radeon_scratch_free(rdev, scratch); | 4125 | radeon_scratch_free(rdev, scratch); |
4109 | radeon_ib_free(rdev, &ib); | 4126 | radeon_ib_free(rdev, &ib); |
@@ -4324,7 +4341,7 @@ static int cik_cp_gfx_start(struct radeon_device *rdev) | |||
4324 | radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ | 4341 | radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ |
4325 | radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ | 4342 | radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ |
4326 | 4343 | ||
4327 | radeon_ring_unlock_commit(rdev, ring); | 4344 | radeon_ring_unlock_commit(rdev, ring, false); |
4328 | 4345 | ||
4329 | return 0; | 4346 | return 0; |
4330 | } | 4347 | } |
@@ -5732,20 +5749,17 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev) | |||
5732 | WREG32(0x15D8, 0); | 5749 | WREG32(0x15D8, 0); |
5733 | WREG32(0x15DC, 0); | 5750 | WREG32(0x15DC, 0); |
5734 | 5751 | ||
5735 | /* empty context1-15 */ | 5752 | /* restore context1-15 */ |
5736 | /* FIXME start with 4G, once using 2 level pt switch to full | ||
5737 | * vm size space | ||
5738 | */ | ||
5739 | /* set vm size, must be a multiple of 4 */ | 5753 | /* set vm size, must be a multiple of 4 */ |
5740 | WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); | 5754 | WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); |
5741 | WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn); | 5755 | WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn); |
5742 | for (i = 1; i < 16; i++) { | 5756 | for (i = 1; i < 16; i++) { |
5743 | if (i < 8) | 5757 | if (i < 8) |
5744 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), | 5758 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), |
5745 | rdev->gart.table_addr >> 12); | 5759 | rdev->vm_manager.saved_table_addr[i]); |
5746 | else | 5760 | else |
5747 | WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2), | 5761 | WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2), |
5748 | rdev->gart.table_addr >> 12); | 5762 | rdev->vm_manager.saved_table_addr[i]); |
5749 | } | 5763 | } |
5750 | 5764 | ||
5751 | /* enable context1-15 */ | 5765 | /* enable context1-15 */ |
@@ -5810,6 +5824,17 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev) | |||
5810 | */ | 5824 | */ |
5811 | static void cik_pcie_gart_disable(struct radeon_device *rdev) | 5825 | static void cik_pcie_gart_disable(struct radeon_device *rdev) |
5812 | { | 5826 | { |
5827 | unsigned i; | ||
5828 | |||
5829 | for (i = 1; i < 16; ++i) { | ||
5830 | uint32_t reg; | ||
5831 | if (i < 8) | ||
5832 | reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2); | ||
5833 | else | ||
5834 | reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2); | ||
5835 | rdev->vm_manager.saved_table_addr[i] = RREG32(reg); | ||
5836 | } | ||
5837 | |||
5813 | /* Disable all tables */ | 5838 | /* Disable all tables */ |
5814 | WREG32(VM_CONTEXT0_CNTL, 0); | 5839 | WREG32(VM_CONTEXT0_CNTL, 0); |
5815 | WREG32(VM_CONTEXT1_CNTL, 0); | 5840 | WREG32(VM_CONTEXT1_CNTL, 0); |
@@ -5958,14 +5983,14 @@ void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) | |||
5958 | 5983 | ||
5959 | /* update SH_MEM_* regs */ | 5984 | /* update SH_MEM_* regs */ |
5960 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); | 5985 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); |
5961 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | | 5986 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | |
5962 | WRITE_DATA_DST_SEL(0))); | 5987 | WRITE_DATA_DST_SEL(0))); |
5963 | radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); | 5988 | radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); |
5964 | radeon_ring_write(ring, 0); | 5989 | radeon_ring_write(ring, 0); |
5965 | radeon_ring_write(ring, VMID(vm->id)); | 5990 | radeon_ring_write(ring, VMID(vm->id)); |
5966 | 5991 | ||
5967 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6)); | 5992 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6)); |
5968 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | | 5993 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | |
5969 | WRITE_DATA_DST_SEL(0))); | 5994 | WRITE_DATA_DST_SEL(0))); |
5970 | radeon_ring_write(ring, SH_MEM_BASES >> 2); | 5995 | radeon_ring_write(ring, SH_MEM_BASES >> 2); |
5971 | radeon_ring_write(ring, 0); | 5996 | radeon_ring_write(ring, 0); |
@@ -5976,7 +6001,7 @@ void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) | |||
5976 | radeon_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */ | 6001 | radeon_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */ |
5977 | 6002 | ||
5978 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); | 6003 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); |
5979 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | | 6004 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | |
5980 | WRITE_DATA_DST_SEL(0))); | 6005 | WRITE_DATA_DST_SEL(0))); |
5981 | radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); | 6006 | radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); |
5982 | radeon_ring_write(ring, 0); | 6007 | radeon_ring_write(ring, 0); |
@@ -5987,7 +6012,7 @@ void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) | |||
5987 | 6012 | ||
5988 | /* bits 0-15 are the VM contexts0-15 */ | 6013 | /* bits 0-15 are the VM contexts0-15 */ |
5989 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); | 6014 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); |
5990 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | | 6015 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | |
5991 | WRITE_DATA_DST_SEL(0))); | 6016 | WRITE_DATA_DST_SEL(0))); |
5992 | radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); | 6017 | radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); |
5993 | radeon_ring_write(ring, 0); | 6018 | radeon_ring_write(ring, 0); |
@@ -9538,6 +9563,9 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) | |||
9538 | int ret, i; | 9563 | int ret, i; |
9539 | u16 tmp16; | 9564 | u16 tmp16; |
9540 | 9565 | ||
9566 | if (pci_is_root_bus(rdev->pdev->bus)) | ||
9567 | return; | ||
9568 | |||
9541 | if (radeon_pcie_gen2 == 0) | 9569 | if (radeon_pcie_gen2 == 0) |
9542 | return; | 9570 | return; |
9543 | 9571 | ||
@@ -9764,7 +9792,8 @@ static void cik_program_aspm(struct radeon_device *rdev) | |||
9764 | if (orig != data) | 9792 | if (orig != data) |
9765 | WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data); | 9793 | WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data); |
9766 | 9794 | ||
9767 | if (!disable_clkreq) { | 9795 | if (!disable_clkreq && |
9796 | !pci_is_root_bus(rdev->pdev->bus)) { | ||
9768 | struct pci_dev *root = rdev->pdev->bus->self; | 9797 | struct pci_dev *root = rdev->pdev->bus->self; |
9769 | u32 lnkcap; | 9798 | u32 lnkcap; |
9770 | 9799 | ||
diff --git a/drivers/gpu/drm/radeon/cik_sdma.c b/drivers/gpu/drm/radeon/cik_sdma.c index bcf480510ac2..192278bc993c 100644 --- a/drivers/gpu/drm/radeon/cik_sdma.c +++ b/drivers/gpu/drm/radeon/cik_sdma.c | |||
@@ -596,7 +596,7 @@ int cik_copy_dma(struct radeon_device *rdev, | |||
596 | return r; | 596 | return r; |
597 | } | 597 | } |
598 | 598 | ||
599 | radeon_ring_unlock_commit(rdev, ring); | 599 | radeon_ring_unlock_commit(rdev, ring, false); |
600 | radeon_semaphore_free(rdev, &sem, *fence); | 600 | radeon_semaphore_free(rdev, &sem, *fence); |
601 | 601 | ||
602 | return r; | 602 | return r; |
@@ -638,7 +638,7 @@ int cik_sdma_ring_test(struct radeon_device *rdev, | |||
638 | radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr)); | 638 | radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr)); |
639 | radeon_ring_write(ring, 1); /* number of DWs to follow */ | 639 | radeon_ring_write(ring, 1); /* number of DWs to follow */ |
640 | radeon_ring_write(ring, 0xDEADBEEF); | 640 | radeon_ring_write(ring, 0xDEADBEEF); |
641 | radeon_ring_unlock_commit(rdev, ring); | 641 | radeon_ring_unlock_commit(rdev, ring, false); |
642 | 642 | ||
643 | for (i = 0; i < rdev->usec_timeout; i++) { | 643 | for (i = 0; i < rdev->usec_timeout; i++) { |
644 | tmp = readl(ptr); | 644 | tmp = readl(ptr); |
@@ -695,7 +695,7 @@ int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) | |||
695 | ib.ptr[4] = 0xDEADBEEF; | 695 | ib.ptr[4] = 0xDEADBEEF; |
696 | ib.length_dw = 5; | 696 | ib.length_dw = 5; |
697 | 697 | ||
698 | r = radeon_ib_schedule(rdev, &ib, NULL); | 698 | r = radeon_ib_schedule(rdev, &ib, NULL, false); |
699 | if (r) { | 699 | if (r) { |
700 | radeon_ib_free(rdev, &ib); | 700 | radeon_ib_free(rdev, &ib); |
701 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); | 701 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); |
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 4fedd14e670a..dbca60c7d097 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c | |||
@@ -2869,7 +2869,7 @@ static int evergreen_cp_start(struct radeon_device *rdev) | |||
2869 | radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); | 2869 | radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); |
2870 | radeon_ring_write(ring, 0); | 2870 | radeon_ring_write(ring, 0); |
2871 | radeon_ring_write(ring, 0); | 2871 | radeon_ring_write(ring, 0); |
2872 | radeon_ring_unlock_commit(rdev, ring); | 2872 | radeon_ring_unlock_commit(rdev, ring, false); |
2873 | 2873 | ||
2874 | cp_me = 0xff; | 2874 | cp_me = 0xff; |
2875 | WREG32(CP_ME_CNTL, cp_me); | 2875 | WREG32(CP_ME_CNTL, cp_me); |
@@ -2912,7 +2912,7 @@ static int evergreen_cp_start(struct radeon_device *rdev) | |||
2912 | radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ | 2912 | radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ |
2913 | radeon_ring_write(ring, 0x00000010); /* */ | 2913 | radeon_ring_write(ring, 0x00000010); /* */ |
2914 | 2914 | ||
2915 | radeon_ring_unlock_commit(rdev, ring); | 2915 | radeon_ring_unlock_commit(rdev, ring, false); |
2916 | 2916 | ||
2917 | return 0; | 2917 | return 0; |
2918 | } | 2918 | } |
diff --git a/drivers/gpu/drm/radeon/evergreen_dma.c b/drivers/gpu/drm/radeon/evergreen_dma.c index 478caefe0fef..afaba388c36d 100644 --- a/drivers/gpu/drm/radeon/evergreen_dma.c +++ b/drivers/gpu/drm/radeon/evergreen_dma.c | |||
@@ -155,7 +155,7 @@ int evergreen_copy_dma(struct radeon_device *rdev, | |||
155 | return r; | 155 | return r; |
156 | } | 156 | } |
157 | 157 | ||
158 | radeon_ring_unlock_commit(rdev, ring); | 158 | radeon_ring_unlock_commit(rdev, ring, false); |
159 | radeon_semaphore_free(rdev, &sem, *fence); | 159 | radeon_semaphore_free(rdev, &sem, *fence); |
160 | 160 | ||
161 | return r; | 161 | return r; |
diff --git a/drivers/gpu/drm/radeon/kv_dpm.c b/drivers/gpu/drm/radeon/kv_dpm.c index 9ef8c38f2d66..8b58e11b64fa 100644 --- a/drivers/gpu/drm/radeon/kv_dpm.c +++ b/drivers/gpu/drm/radeon/kv_dpm.c | |||
@@ -1438,14 +1438,14 @@ static int kv_update_uvd_dpm(struct radeon_device *rdev, bool gate) | |||
1438 | return kv_enable_uvd_dpm(rdev, !gate); | 1438 | return kv_enable_uvd_dpm(rdev, !gate); |
1439 | } | 1439 | } |
1440 | 1440 | ||
1441 | static u8 kv_get_vce_boot_level(struct radeon_device *rdev) | 1441 | static u8 kv_get_vce_boot_level(struct radeon_device *rdev, u32 evclk) |
1442 | { | 1442 | { |
1443 | u8 i; | 1443 | u8 i; |
1444 | struct radeon_vce_clock_voltage_dependency_table *table = | 1444 | struct radeon_vce_clock_voltage_dependency_table *table = |
1445 | &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; | 1445 | &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; |
1446 | 1446 | ||
1447 | for (i = 0; i < table->count; i++) { | 1447 | for (i = 0; i < table->count; i++) { |
1448 | if (table->entries[i].evclk >= 0) /* XXX */ | 1448 | if (table->entries[i].evclk >= evclk) |
1449 | break; | 1449 | break; |
1450 | } | 1450 | } |
1451 | 1451 | ||
@@ -1468,7 +1468,7 @@ static int kv_update_vce_dpm(struct radeon_device *rdev, | |||
1468 | if (pi->caps_stable_p_state) | 1468 | if (pi->caps_stable_p_state) |
1469 | pi->vce_boot_level = table->count - 1; | 1469 | pi->vce_boot_level = table->count - 1; |
1470 | else | 1470 | else |
1471 | pi->vce_boot_level = kv_get_vce_boot_level(rdev); | 1471 | pi->vce_boot_level = kv_get_vce_boot_level(rdev, radeon_new_state->evclk); |
1472 | 1472 | ||
1473 | ret = kv_copy_bytes_to_smc(rdev, | 1473 | ret = kv_copy_bytes_to_smc(rdev, |
1474 | pi->dpm_table_start + | 1474 | pi->dpm_table_start + |
@@ -2726,7 +2726,10 @@ int kv_dpm_init(struct radeon_device *rdev) | |||
2726 | pi->caps_sclk_ds = true; | 2726 | pi->caps_sclk_ds = true; |
2727 | pi->enable_auto_thermal_throttling = true; | 2727 | pi->enable_auto_thermal_throttling = true; |
2728 | pi->disable_nb_ps3_in_battery = false; | 2728 | pi->disable_nb_ps3_in_battery = false; |
2729 | pi->bapm_enable = true; | 2729 | if (radeon_bapm == 0) |
2730 | pi->bapm_enable = false; | ||
2731 | else | ||
2732 | pi->bapm_enable = true; | ||
2730 | pi->voltage_drop_t = 0; | 2733 | pi->voltage_drop_t = 0; |
2731 | pi->caps_sclk_throttle_low_notification = false; | 2734 | pi->caps_sclk_throttle_low_notification = false; |
2732 | pi->caps_fps = false; /* true? */ | 2735 | pi->caps_fps = false; /* true? */ |
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c index 327b85f7fd0d..3faee58946dd 100644 --- a/drivers/gpu/drm/radeon/ni.c +++ b/drivers/gpu/drm/radeon/ni.c | |||
@@ -1271,7 +1271,7 @@ static int cayman_pcie_gart_enable(struct radeon_device *rdev) | |||
1271 | WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0); | 1271 | WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0); |
1272 | WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), rdev->vm_manager.max_pfn); | 1272 | WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), rdev->vm_manager.max_pfn); |
1273 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), | 1273 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), |
1274 | rdev->gart.table_addr >> 12); | 1274 | rdev->vm_manager.saved_table_addr[i]); |
1275 | } | 1275 | } |
1276 | 1276 | ||
1277 | /* enable context1-7 */ | 1277 | /* enable context1-7 */ |
@@ -1303,6 +1303,13 @@ static int cayman_pcie_gart_enable(struct radeon_device *rdev) | |||
1303 | 1303 | ||
1304 | static void cayman_pcie_gart_disable(struct radeon_device *rdev) | 1304 | static void cayman_pcie_gart_disable(struct radeon_device *rdev) |
1305 | { | 1305 | { |
1306 | unsigned i; | ||
1307 | |||
1308 | for (i = 1; i < 8; ++i) { | ||
1309 | rdev->vm_manager.saved_table_addr[i] = RREG32( | ||
1310 | VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2)); | ||
1311 | } | ||
1312 | |||
1306 | /* Disable all tables */ | 1313 | /* Disable all tables */ |
1307 | WREG32(VM_CONTEXT0_CNTL, 0); | 1314 | WREG32(VM_CONTEXT0_CNTL, 0); |
1308 | WREG32(VM_CONTEXT1_CNTL, 0); | 1315 | WREG32(VM_CONTEXT1_CNTL, 0); |
@@ -1505,7 +1512,7 @@ static int cayman_cp_start(struct radeon_device *rdev) | |||
1505 | radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); | 1512 | radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); |
1506 | radeon_ring_write(ring, 0); | 1513 | radeon_ring_write(ring, 0); |
1507 | radeon_ring_write(ring, 0); | 1514 | radeon_ring_write(ring, 0); |
1508 | radeon_ring_unlock_commit(rdev, ring); | 1515 | radeon_ring_unlock_commit(rdev, ring, false); |
1509 | 1516 | ||
1510 | cayman_cp_enable(rdev, true); | 1517 | cayman_cp_enable(rdev, true); |
1511 | 1518 | ||
@@ -1547,7 +1554,7 @@ static int cayman_cp_start(struct radeon_device *rdev) | |||
1547 | radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ | 1554 | radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ |
1548 | radeon_ring_write(ring, 0x00000010); /* */ | 1555 | radeon_ring_write(ring, 0x00000010); /* */ |
1549 | 1556 | ||
1550 | radeon_ring_unlock_commit(rdev, ring); | 1557 | radeon_ring_unlock_commit(rdev, ring, false); |
1551 | 1558 | ||
1552 | /* XXX init other rings */ | 1559 | /* XXX init other rings */ |
1553 | 1560 | ||
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index 04b5940b8923..4c5ec44ff328 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c | |||
@@ -925,7 +925,7 @@ int r100_copy_blit(struct radeon_device *rdev, | |||
925 | if (fence) { | 925 | if (fence) { |
926 | r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX); | 926 | r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX); |
927 | } | 927 | } |
928 | radeon_ring_unlock_commit(rdev, ring); | 928 | radeon_ring_unlock_commit(rdev, ring, false); |
929 | return r; | 929 | return r; |
930 | } | 930 | } |
931 | 931 | ||
@@ -958,7 +958,7 @@ void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) | |||
958 | RADEON_ISYNC_ANY3D_IDLE2D | | 958 | RADEON_ISYNC_ANY3D_IDLE2D | |
959 | RADEON_ISYNC_WAIT_IDLEGUI | | 959 | RADEON_ISYNC_WAIT_IDLEGUI | |
960 | RADEON_ISYNC_CPSCRATCH_IDLEGUI); | 960 | RADEON_ISYNC_CPSCRATCH_IDLEGUI); |
961 | radeon_ring_unlock_commit(rdev, ring); | 961 | radeon_ring_unlock_commit(rdev, ring, false); |
962 | } | 962 | } |
963 | 963 | ||
964 | 964 | ||
@@ -3638,7 +3638,7 @@ int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) | |||
3638 | } | 3638 | } |
3639 | radeon_ring_write(ring, PACKET0(scratch, 0)); | 3639 | radeon_ring_write(ring, PACKET0(scratch, 0)); |
3640 | radeon_ring_write(ring, 0xDEADBEEF); | 3640 | radeon_ring_write(ring, 0xDEADBEEF); |
3641 | radeon_ring_unlock_commit(rdev, ring); | 3641 | radeon_ring_unlock_commit(rdev, ring, false); |
3642 | for (i = 0; i < rdev->usec_timeout; i++) { | 3642 | for (i = 0; i < rdev->usec_timeout; i++) { |
3643 | tmp = RREG32(scratch); | 3643 | tmp = RREG32(scratch); |
3644 | if (tmp == 0xDEADBEEF) { | 3644 | if (tmp == 0xDEADBEEF) { |
@@ -3700,7 +3700,7 @@ int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) | |||
3700 | ib.ptr[6] = PACKET2(0); | 3700 | ib.ptr[6] = PACKET2(0); |
3701 | ib.ptr[7] = PACKET2(0); | 3701 | ib.ptr[7] = PACKET2(0); |
3702 | ib.length_dw = 8; | 3702 | ib.length_dw = 8; |
3703 | r = radeon_ib_schedule(rdev, &ib, NULL); | 3703 | r = radeon_ib_schedule(rdev, &ib, NULL, false); |
3704 | if (r) { | 3704 | if (r) { |
3705 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); | 3705 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); |
3706 | goto free_ib; | 3706 | goto free_ib; |
diff --git a/drivers/gpu/drm/radeon/r200.c b/drivers/gpu/drm/radeon/r200.c index 58f0473aa73f..67780374a652 100644 --- a/drivers/gpu/drm/radeon/r200.c +++ b/drivers/gpu/drm/radeon/r200.c | |||
@@ -121,7 +121,7 @@ int r200_copy_dma(struct radeon_device *rdev, | |||
121 | if (fence) { | 121 | if (fence) { |
122 | r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX); | 122 | r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX); |
123 | } | 123 | } |
124 | radeon_ring_unlock_commit(rdev, ring); | 124 | radeon_ring_unlock_commit(rdev, ring, false); |
125 | return r; | 125 | return r; |
126 | } | 126 | } |
127 | 127 | ||
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c index 75b30338c226..1bc4704034ce 100644 --- a/drivers/gpu/drm/radeon/r300.c +++ b/drivers/gpu/drm/radeon/r300.c | |||
@@ -295,7 +295,7 @@ void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) | |||
295 | radeon_ring_write(ring, | 295 | radeon_ring_write(ring, |
296 | R300_GEOMETRY_ROUND_NEAREST | | 296 | R300_GEOMETRY_ROUND_NEAREST | |
297 | R300_COLOR_ROUND_NEAREST); | 297 | R300_COLOR_ROUND_NEAREST); |
298 | radeon_ring_unlock_commit(rdev, ring); | 298 | radeon_ring_unlock_commit(rdev, ring, false); |
299 | } | 299 | } |
300 | 300 | ||
301 | static void r300_errata(struct radeon_device *rdev) | 301 | static void r300_errata(struct radeon_device *rdev) |
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c index 802b19220a21..2828605aef3f 100644 --- a/drivers/gpu/drm/radeon/r420.c +++ b/drivers/gpu/drm/radeon/r420.c | |||
@@ -219,7 +219,7 @@ static void r420_cp_errata_init(struct radeon_device *rdev) | |||
219 | radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1)); | 219 | radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1)); |
220 | radeon_ring_write(ring, rdev->config.r300.resync_scratch); | 220 | radeon_ring_write(ring, rdev->config.r300.resync_scratch); |
221 | radeon_ring_write(ring, 0xDEADBEEF); | 221 | radeon_ring_write(ring, 0xDEADBEEF); |
222 | radeon_ring_unlock_commit(rdev, ring); | 222 | radeon_ring_unlock_commit(rdev, ring, false); |
223 | } | 223 | } |
224 | 224 | ||
225 | static void r420_cp_errata_fini(struct radeon_device *rdev) | 225 | static void r420_cp_errata_fini(struct radeon_device *rdev) |
@@ -232,7 +232,7 @@ static void r420_cp_errata_fini(struct radeon_device *rdev) | |||
232 | radeon_ring_lock(rdev, ring, 8); | 232 | radeon_ring_lock(rdev, ring, 8); |
233 | radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); | 233 | radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
234 | radeon_ring_write(ring, R300_RB3D_DC_FINISH); | 234 | radeon_ring_write(ring, R300_RB3D_DC_FINISH); |
235 | radeon_ring_unlock_commit(rdev, ring); | 235 | radeon_ring_unlock_commit(rdev, ring, false); |
236 | radeon_scratch_free(rdev, rdev->config.r300.resync_scratch); | 236 | radeon_scratch_free(rdev, rdev->config.r300.resync_scratch); |
237 | } | 237 | } |
238 | 238 | ||
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index c70a504d96af..e616eb5f6e7a 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c | |||
@@ -1812,7 +1812,6 @@ static void r600_gpu_init(struct radeon_device *rdev) | |||
1812 | { | 1812 | { |
1813 | u32 tiling_config; | 1813 | u32 tiling_config; |
1814 | u32 ramcfg; | 1814 | u32 ramcfg; |
1815 | u32 cc_rb_backend_disable; | ||
1816 | u32 cc_gc_shader_pipe_config; | 1815 | u32 cc_gc_shader_pipe_config; |
1817 | u32 tmp; | 1816 | u32 tmp; |
1818 | int i, j; | 1817 | int i, j; |
@@ -1939,29 +1938,20 @@ static void r600_gpu_init(struct radeon_device *rdev) | |||
1939 | } | 1938 | } |
1940 | tiling_config |= BANK_SWAPS(1); | 1939 | tiling_config |= BANK_SWAPS(1); |
1941 | 1940 | ||
1942 | cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; | ||
1943 | tmp = R6XX_MAX_BACKENDS - | ||
1944 | r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK); | ||
1945 | if (tmp < rdev->config.r600.max_backends) { | ||
1946 | rdev->config.r600.max_backends = tmp; | ||
1947 | } | ||
1948 | |||
1949 | cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00; | 1941 | cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00; |
1950 | tmp = R6XX_MAX_PIPES - | ||
1951 | r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R6XX_MAX_PIPES_MASK); | ||
1952 | if (tmp < rdev->config.r600.max_pipes) { | ||
1953 | rdev->config.r600.max_pipes = tmp; | ||
1954 | } | ||
1955 | tmp = R6XX_MAX_SIMDS - | ||
1956 | r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK); | ||
1957 | if (tmp < rdev->config.r600.max_simds) { | ||
1958 | rdev->config.r600.max_simds = tmp; | ||
1959 | } | ||
1960 | tmp = rdev->config.r600.max_simds - | 1942 | tmp = rdev->config.r600.max_simds - |
1961 | r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK); | 1943 | r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK); |
1962 | rdev->config.r600.active_simds = tmp; | 1944 | rdev->config.r600.active_simds = tmp; |
1963 | 1945 | ||
1964 | disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK; | 1946 | disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK; |
1947 | tmp = 0; | ||
1948 | for (i = 0; i < rdev->config.r600.max_backends; i++) | ||
1949 | tmp |= (1 << i); | ||
1950 | /* if all the backends are disabled, fix it up here */ | ||
1951 | if ((disabled_rb_mask & tmp) == tmp) { | ||
1952 | for (i = 0; i < rdev->config.r600.max_backends; i++) | ||
1953 | disabled_rb_mask &= ~(1 << i); | ||
1954 | } | ||
1965 | tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; | 1955 | tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; |
1966 | tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends, | 1956 | tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends, |
1967 | R6XX_MAX_BACKENDS, disabled_rb_mask); | 1957 | R6XX_MAX_BACKENDS, disabled_rb_mask); |
@@ -2547,7 +2537,7 @@ int r600_cp_start(struct radeon_device *rdev) | |||
2547 | radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); | 2537 | radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); |
2548 | radeon_ring_write(ring, 0); | 2538 | radeon_ring_write(ring, 0); |
2549 | radeon_ring_write(ring, 0); | 2539 | radeon_ring_write(ring, 0); |
2550 | radeon_ring_unlock_commit(rdev, ring); | 2540 | radeon_ring_unlock_commit(rdev, ring, false); |
2551 | 2541 | ||
2552 | cp_me = 0xff; | 2542 | cp_me = 0xff; |
2553 | WREG32(R_0086D8_CP_ME_CNTL, cp_me); | 2543 | WREG32(R_0086D8_CP_ME_CNTL, cp_me); |
@@ -2683,7 +2673,7 @@ int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) | |||
2683 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); | 2673 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
2684 | radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); | 2674 | radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); |
2685 | radeon_ring_write(ring, 0xDEADBEEF); | 2675 | radeon_ring_write(ring, 0xDEADBEEF); |
2686 | radeon_ring_unlock_commit(rdev, ring); | 2676 | radeon_ring_unlock_commit(rdev, ring, false); |
2687 | for (i = 0; i < rdev->usec_timeout; i++) { | 2677 | for (i = 0; i < rdev->usec_timeout; i++) { |
2688 | tmp = RREG32(scratch); | 2678 | tmp = RREG32(scratch); |
2689 | if (tmp == 0xDEADBEEF) | 2679 | if (tmp == 0xDEADBEEF) |
@@ -2753,6 +2743,17 @@ void r600_fence_ring_emit(struct radeon_device *rdev, | |||
2753 | } | 2743 | } |
2754 | } | 2744 | } |
2755 | 2745 | ||
2746 | /** | ||
2747 | * r600_semaphore_ring_emit - emit a semaphore on the CP ring | ||
2748 | * | ||
2749 | * @rdev: radeon_device pointer | ||
2750 | * @ring: radeon ring buffer object | ||
2751 | * @semaphore: radeon semaphore object | ||
2752 | * @emit_wait: Is this a sempahore wait? | ||
2753 | * | ||
2754 | * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP | ||
2755 | * from running ahead of semaphore waits. | ||
2756 | */ | ||
2756 | bool r600_semaphore_ring_emit(struct radeon_device *rdev, | 2757 | bool r600_semaphore_ring_emit(struct radeon_device *rdev, |
2757 | struct radeon_ring *ring, | 2758 | struct radeon_ring *ring, |
2758 | struct radeon_semaphore *semaphore, | 2759 | struct radeon_semaphore *semaphore, |
@@ -2768,6 +2769,13 @@ bool r600_semaphore_ring_emit(struct radeon_device *rdev, | |||
2768 | radeon_ring_write(ring, lower_32_bits(addr)); | 2769 | radeon_ring_write(ring, lower_32_bits(addr)); |
2769 | radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); | 2770 | radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); |
2770 | 2771 | ||
2772 | /* PFP_SYNC_ME packet only exists on 7xx+ */ | ||
2773 | if (emit_wait && (rdev->family >= CHIP_RV770)) { | ||
2774 | /* Prevent the PFP from running ahead of the semaphore wait */ | ||
2775 | radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); | ||
2776 | radeon_ring_write(ring, 0x0); | ||
2777 | } | ||
2778 | |||
2771 | return true; | 2779 | return true; |
2772 | } | 2780 | } |
2773 | 2781 | ||
@@ -2845,7 +2853,7 @@ int r600_copy_cpdma(struct radeon_device *rdev, | |||
2845 | return r; | 2853 | return r; |
2846 | } | 2854 | } |
2847 | 2855 | ||
2848 | radeon_ring_unlock_commit(rdev, ring); | 2856 | radeon_ring_unlock_commit(rdev, ring, false); |
2849 | radeon_semaphore_free(rdev, &sem, *fence); | 2857 | radeon_semaphore_free(rdev, &sem, *fence); |
2850 | 2858 | ||
2851 | return r; | 2859 | return r; |
@@ -3165,7 +3173,7 @@ int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) | |||
3165 | ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); | 3173 | ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
3166 | ib.ptr[2] = 0xDEADBEEF; | 3174 | ib.ptr[2] = 0xDEADBEEF; |
3167 | ib.length_dw = 3; | 3175 | ib.length_dw = 3; |
3168 | r = radeon_ib_schedule(rdev, &ib, NULL); | 3176 | r = radeon_ib_schedule(rdev, &ib, NULL, false); |
3169 | if (r) { | 3177 | if (r) { |
3170 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); | 3178 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); |
3171 | goto free_ib; | 3179 | goto free_ib; |
diff --git a/drivers/gpu/drm/radeon/r600_dma.c b/drivers/gpu/drm/radeon/r600_dma.c index 4969cef44a19..51fd98553eaf 100644 --- a/drivers/gpu/drm/radeon/r600_dma.c +++ b/drivers/gpu/drm/radeon/r600_dma.c | |||
@@ -261,7 +261,7 @@ int r600_dma_ring_test(struct radeon_device *rdev, | |||
261 | radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc); | 261 | radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc); |
262 | radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff); | 262 | radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff); |
263 | radeon_ring_write(ring, 0xDEADBEEF); | 263 | radeon_ring_write(ring, 0xDEADBEEF); |
264 | radeon_ring_unlock_commit(rdev, ring); | 264 | radeon_ring_unlock_commit(rdev, ring, false); |
265 | 265 | ||
266 | for (i = 0; i < rdev->usec_timeout; i++) { | 266 | for (i = 0; i < rdev->usec_timeout; i++) { |
267 | tmp = readl(ptr); | 267 | tmp = readl(ptr); |
@@ -368,7 +368,7 @@ int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) | |||
368 | ib.ptr[3] = 0xDEADBEEF; | 368 | ib.ptr[3] = 0xDEADBEEF; |
369 | ib.length_dw = 4; | 369 | ib.length_dw = 4; |
370 | 370 | ||
371 | r = radeon_ib_schedule(rdev, &ib, NULL); | 371 | r = radeon_ib_schedule(rdev, &ib, NULL, false); |
372 | if (r) { | 372 | if (r) { |
373 | radeon_ib_free(rdev, &ib); | 373 | radeon_ib_free(rdev, &ib); |
374 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); | 374 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); |
@@ -493,7 +493,7 @@ int r600_copy_dma(struct radeon_device *rdev, | |||
493 | return r; | 493 | return r; |
494 | } | 494 | } |
495 | 495 | ||
496 | radeon_ring_unlock_commit(rdev, ring); | 496 | radeon_ring_unlock_commit(rdev, ring, false); |
497 | radeon_semaphore_free(rdev, &sem, *fence); | 497 | radeon_semaphore_free(rdev, &sem, *fence); |
498 | 498 | ||
499 | return r; | 499 | return r; |
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h index f94e7a9afe75..0c4a7d8d93e0 100644 --- a/drivers/gpu/drm/radeon/r600d.h +++ b/drivers/gpu/drm/radeon/r600d.h | |||
@@ -1597,6 +1597,7 @@ | |||
1597 | */ | 1597 | */ |
1598 | # define PACKET3_CP_DMA_CMD_SAIC (1 << 28) | 1598 | # define PACKET3_CP_DMA_CMD_SAIC (1 << 28) |
1599 | # define PACKET3_CP_DMA_CMD_DAIC (1 << 29) | 1599 | # define PACKET3_CP_DMA_CMD_DAIC (1 << 29) |
1600 | #define PACKET3_PFP_SYNC_ME 0x42 /* r7xx+ only */ | ||
1600 | #define PACKET3_SURFACE_SYNC 0x43 | 1601 | #define PACKET3_SURFACE_SYNC 0x43 |
1601 | # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) | 1602 | # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) |
1602 | # define PACKET3_FULL_CACHE_ENA (1 << 20) /* r7xx+ only */ | 1603 | # define PACKET3_FULL_CACHE_ENA (1 << 20) /* r7xx+ only */ |
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 9e1732eb402c..5f05b4c84338 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h | |||
@@ -105,6 +105,7 @@ extern int radeon_vm_size; | |||
105 | extern int radeon_vm_block_size; | 105 | extern int radeon_vm_block_size; |
106 | extern int radeon_deep_color; | 106 | extern int radeon_deep_color; |
107 | extern int radeon_use_pflipirq; | 107 | extern int radeon_use_pflipirq; |
108 | extern int radeon_bapm; | ||
108 | 109 | ||
109 | /* | 110 | /* |
110 | * Copy from radeon_drv.h so we don't have to include both and have conflicting | 111 | * Copy from radeon_drv.h so we don't have to include both and have conflicting |
@@ -914,6 +915,8 @@ struct radeon_vm_manager { | |||
914 | u64 vram_base_offset; | 915 | u64 vram_base_offset; |
915 | /* is vm enabled? */ | 916 | /* is vm enabled? */ |
916 | bool enabled; | 917 | bool enabled; |
918 | /* for hw to save the PD addr on suspend/resume */ | ||
919 | uint32_t saved_table_addr[RADEON_NUM_VM]; | ||
917 | }; | 920 | }; |
918 | 921 | ||
919 | /* | 922 | /* |
@@ -967,7 +970,7 @@ int radeon_ib_get(struct radeon_device *rdev, int ring, | |||
967 | unsigned size); | 970 | unsigned size); |
968 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); | 971 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); |
969 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, | 972 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, |
970 | struct radeon_ib *const_ib); | 973 | struct radeon_ib *const_ib, bool hdp_flush); |
971 | int radeon_ib_pool_init(struct radeon_device *rdev); | 974 | int radeon_ib_pool_init(struct radeon_device *rdev); |
972 | void radeon_ib_pool_fini(struct radeon_device *rdev); | 975 | void radeon_ib_pool_fini(struct radeon_device *rdev); |
973 | int radeon_ib_ring_tests(struct radeon_device *rdev); | 976 | int radeon_ib_ring_tests(struct radeon_device *rdev); |
@@ -977,8 +980,10 @@ bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, | |||
977 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); | 980 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); |
978 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); | 981 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); |
979 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); | 982 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); |
980 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp); | 983 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, |
981 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp); | 984 | bool hdp_flush); |
985 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, | ||
986 | bool hdp_flush); | ||
982 | void radeon_ring_undo(struct radeon_ring *ring); | 987 | void radeon_ring_undo(struct radeon_ring *ring); |
983 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); | 988 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); |
984 | int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); | 989 | int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c index ee712c199b25..83f382e8e40e 100644 --- a/drivers/gpu/drm/radeon/radeon_cs.c +++ b/drivers/gpu/drm/radeon/radeon_cs.c | |||
@@ -132,7 +132,8 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p) | |||
132 | * the buffers used for read only, which doubles the range | 132 | * the buffers used for read only, which doubles the range |
133 | * to 0 to 31. 32 is reserved for the kernel driver. | 133 | * to 0 to 31. 32 is reserved for the kernel driver. |
134 | */ | 134 | */ |
135 | priority = (r->flags & 0xf) * 2 + !!r->write_domain; | 135 | priority = (r->flags & RADEON_RELOC_PRIO_MASK) * 2 |
136 | + !!r->write_domain; | ||
136 | 137 | ||
137 | /* the first reloc of an UVD job is the msg and that must be in | 138 | /* the first reloc of an UVD job is the msg and that must be in |
138 | VRAM, also but everything into VRAM on AGP cards to avoid | 139 | VRAM, also but everything into VRAM on AGP cards to avoid |
@@ -450,7 +451,7 @@ static int radeon_cs_ib_chunk(struct radeon_device *rdev, | |||
450 | radeon_vce_note_usage(rdev); | 451 | radeon_vce_note_usage(rdev); |
451 | 452 | ||
452 | radeon_cs_sync_rings(parser); | 453 | radeon_cs_sync_rings(parser); |
453 | r = radeon_ib_schedule(rdev, &parser->ib, NULL); | 454 | r = radeon_ib_schedule(rdev, &parser->ib, NULL, true); |
454 | if (r) { | 455 | if (r) { |
455 | DRM_ERROR("Failed to schedule IB !\n"); | 456 | DRM_ERROR("Failed to schedule IB !\n"); |
456 | } | 457 | } |
@@ -541,9 +542,9 @@ static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev, | |||
541 | 542 | ||
542 | if ((rdev->family >= CHIP_TAHITI) && | 543 | if ((rdev->family >= CHIP_TAHITI) && |
543 | (parser->chunk_const_ib_idx != -1)) { | 544 | (parser->chunk_const_ib_idx != -1)) { |
544 | r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib); | 545 | r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib, true); |
545 | } else { | 546 | } else { |
546 | r = radeon_ib_schedule(rdev, &parser->ib, NULL); | 547 | r = radeon_ib_schedule(rdev, &parser->ib, NULL, true); |
547 | } | 548 | } |
548 | 549 | ||
549 | out: | 550 | out: |
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index c8ea050c8fa4..6a219bcee66d 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c | |||
@@ -1680,8 +1680,8 @@ int radeon_gpu_reset(struct radeon_device *rdev) | |||
1680 | radeon_save_bios_scratch_regs(rdev); | 1680 | radeon_save_bios_scratch_regs(rdev); |
1681 | /* block TTM */ | 1681 | /* block TTM */ |
1682 | resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); | 1682 | resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); |
1683 | radeon_pm_suspend(rdev); | ||
1684 | radeon_suspend(rdev); | 1683 | radeon_suspend(rdev); |
1684 | radeon_hpd_fini(rdev); | ||
1685 | 1685 | ||
1686 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { | 1686 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
1687 | ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i], | 1687 | ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i], |
@@ -1726,9 +1726,39 @@ retry: | |||
1726 | } | 1726 | } |
1727 | } | 1727 | } |
1728 | 1728 | ||
1729 | radeon_pm_resume(rdev); | 1729 | if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { |
1730 | /* do dpm late init */ | ||
1731 | r = radeon_pm_late_init(rdev); | ||
1732 | if (r) { | ||
1733 | rdev->pm.dpm_enabled = false; | ||
1734 | DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); | ||
1735 | } | ||
1736 | } else { | ||
1737 | /* resume old pm late */ | ||
1738 | radeon_pm_resume(rdev); | ||
1739 | } | ||
1740 | |||
1741 | /* init dig PHYs, disp eng pll */ | ||
1742 | if (rdev->is_atom_bios) { | ||
1743 | radeon_atom_encoder_init(rdev); | ||
1744 | radeon_atom_disp_eng_pll_init(rdev); | ||
1745 | /* turn on the BL */ | ||
1746 | if (rdev->mode_info.bl_encoder) { | ||
1747 | u8 bl_level = radeon_get_backlight_level(rdev, | ||
1748 | rdev->mode_info.bl_encoder); | ||
1749 | radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder, | ||
1750 | bl_level); | ||
1751 | } | ||
1752 | } | ||
1753 | /* reset hpd state */ | ||
1754 | radeon_hpd_init(rdev); | ||
1755 | |||
1730 | drm_helper_resume_force_mode(rdev->ddev); | 1756 | drm_helper_resume_force_mode(rdev->ddev); |
1731 | 1757 | ||
1758 | /* set the power state here in case we are a PX system or headless */ | ||
1759 | if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) | ||
1760 | radeon_pm_compute_clocks(rdev); | ||
1761 | |||
1732 | ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); | 1762 | ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); |
1733 | if (r) { | 1763 | if (r) { |
1734 | /* bad news, how to tell it to userspace ? */ | 1764 | /* bad news, how to tell it to userspace ? */ |
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c index 092d067f93e1..8df888908833 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.c +++ b/drivers/gpu/drm/radeon/radeon_drv.c | |||
@@ -180,6 +180,7 @@ int radeon_vm_size = 8; | |||
180 | int radeon_vm_block_size = -1; | 180 | int radeon_vm_block_size = -1; |
181 | int radeon_deep_color = 0; | 181 | int radeon_deep_color = 0; |
182 | int radeon_use_pflipirq = 2; | 182 | int radeon_use_pflipirq = 2; |
183 | int radeon_bapm = -1; | ||
183 | 184 | ||
184 | MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); | 185 | MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); |
185 | module_param_named(no_wb, radeon_no_wb, int, 0444); | 186 | module_param_named(no_wb, radeon_no_wb, int, 0444); |
@@ -259,6 +260,9 @@ module_param_named(deep_color, radeon_deep_color, int, 0444); | |||
259 | MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))"); | 260 | MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))"); |
260 | module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444); | 261 | module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444); |
261 | 262 | ||
263 | MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); | ||
264 | module_param_named(bapm, radeon_bapm, int, 0444); | ||
265 | |||
262 | static struct pci_device_id pciidlist[] = { | 266 | static struct pci_device_id pciidlist[] = { |
263 | radeon_PCI_IDS | 267 | radeon_PCI_IDS |
264 | }; | 268 | }; |
diff --git a/drivers/gpu/drm/radeon/radeon_ib.c b/drivers/gpu/drm/radeon/radeon_ib.c index 65b0c213488d..5bf2c0a05827 100644 --- a/drivers/gpu/drm/radeon/radeon_ib.c +++ b/drivers/gpu/drm/radeon/radeon_ib.c | |||
@@ -107,6 +107,7 @@ void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib) | |||
107 | * @rdev: radeon_device pointer | 107 | * @rdev: radeon_device pointer |
108 | * @ib: IB object to schedule | 108 | * @ib: IB object to schedule |
109 | * @const_ib: Const IB to schedule (SI only) | 109 | * @const_ib: Const IB to schedule (SI only) |
110 | * @hdp_flush: Whether or not to perform an HDP cache flush | ||
110 | * | 111 | * |
111 | * Schedule an IB on the associated ring (all asics). | 112 | * Schedule an IB on the associated ring (all asics). |
112 | * Returns 0 on success, error on failure. | 113 | * Returns 0 on success, error on failure. |
@@ -122,7 +123,7 @@ void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib) | |||
122 | * to SI there was just a DE IB. | 123 | * to SI there was just a DE IB. |
123 | */ | 124 | */ |
124 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, | 125 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, |
125 | struct radeon_ib *const_ib) | 126 | struct radeon_ib *const_ib, bool hdp_flush) |
126 | { | 127 | { |
127 | struct radeon_ring *ring = &rdev->ring[ib->ring]; | 128 | struct radeon_ring *ring = &rdev->ring[ib->ring]; |
128 | int r = 0; | 129 | int r = 0; |
@@ -176,7 +177,7 @@ int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, | |||
176 | if (ib->vm) | 177 | if (ib->vm) |
177 | radeon_vm_fence(rdev, ib->vm, ib->fence); | 178 | radeon_vm_fence(rdev, ib->vm, ib->fence); |
178 | 179 | ||
179 | radeon_ring_unlock_commit(rdev, ring); | 180 | radeon_ring_unlock_commit(rdev, ring, hdp_flush); |
180 | return 0; | 181 | return 0; |
181 | } | 182 | } |
182 | 183 | ||
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c index 23314be49480..164898b0010c 100644 --- a/drivers/gpu/drm/radeon/radeon_pm.c +++ b/drivers/gpu/drm/radeon/radeon_pm.c | |||
@@ -460,10 +460,6 @@ static ssize_t radeon_get_dpm_state(struct device *dev, | |||
460 | struct radeon_device *rdev = ddev->dev_private; | 460 | struct radeon_device *rdev = ddev->dev_private; |
461 | enum radeon_pm_state_type pm = rdev->pm.dpm.user_state; | 461 | enum radeon_pm_state_type pm = rdev->pm.dpm.user_state; |
462 | 462 | ||
463 | if ((rdev->flags & RADEON_IS_PX) && | ||
464 | (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) | ||
465 | return snprintf(buf, PAGE_SIZE, "off\n"); | ||
466 | |||
467 | return snprintf(buf, PAGE_SIZE, "%s\n", | 463 | return snprintf(buf, PAGE_SIZE, "%s\n", |
468 | (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : | 464 | (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : |
469 | (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); | 465 | (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); |
@@ -477,11 +473,6 @@ static ssize_t radeon_set_dpm_state(struct device *dev, | |||
477 | struct drm_device *ddev = dev_get_drvdata(dev); | 473 | struct drm_device *ddev = dev_get_drvdata(dev); |
478 | struct radeon_device *rdev = ddev->dev_private; | 474 | struct radeon_device *rdev = ddev->dev_private; |
479 | 475 | ||
480 | /* Can't set dpm state when the card is off */ | ||
481 | if ((rdev->flags & RADEON_IS_PX) && | ||
482 | (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) | ||
483 | return -EINVAL; | ||
484 | |||
485 | mutex_lock(&rdev->pm.mutex); | 476 | mutex_lock(&rdev->pm.mutex); |
486 | if (strncmp("battery", buf, strlen("battery")) == 0) | 477 | if (strncmp("battery", buf, strlen("battery")) == 0) |
487 | rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY; | 478 | rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY; |
@@ -495,7 +486,12 @@ static ssize_t radeon_set_dpm_state(struct device *dev, | |||
495 | goto fail; | 486 | goto fail; |
496 | } | 487 | } |
497 | mutex_unlock(&rdev->pm.mutex); | 488 | mutex_unlock(&rdev->pm.mutex); |
498 | radeon_pm_compute_clocks(rdev); | 489 | |
490 | /* Can't set dpm state when the card is off */ | ||
491 | if (!(rdev->flags & RADEON_IS_PX) || | ||
492 | (ddev->switch_power_state == DRM_SWITCH_POWER_ON)) | ||
493 | radeon_pm_compute_clocks(rdev); | ||
494 | |||
499 | fail: | 495 | fail: |
500 | return count; | 496 | return count; |
501 | } | 497 | } |
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c index 5b4e0cf231a0..d65607902537 100644 --- a/drivers/gpu/drm/radeon/radeon_ring.c +++ b/drivers/gpu/drm/radeon/radeon_ring.c | |||
@@ -177,16 +177,18 @@ int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsig | |||
177 | * | 177 | * |
178 | * @rdev: radeon_device pointer | 178 | * @rdev: radeon_device pointer |
179 | * @ring: radeon_ring structure holding ring information | 179 | * @ring: radeon_ring structure holding ring information |
180 | * @hdp_flush: Whether or not to perform an HDP cache flush | ||
180 | * | 181 | * |
181 | * Update the wptr (write pointer) to tell the GPU to | 182 | * Update the wptr (write pointer) to tell the GPU to |
182 | * execute new commands on the ring buffer (all asics). | 183 | * execute new commands on the ring buffer (all asics). |
183 | */ | 184 | */ |
184 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring) | 185 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring, |
186 | bool hdp_flush) | ||
185 | { | 187 | { |
186 | /* If we are emitting the HDP flush via the ring buffer, we need to | 188 | /* If we are emitting the HDP flush via the ring buffer, we need to |
187 | * do it before padding. | 189 | * do it before padding. |
188 | */ | 190 | */ |
189 | if (rdev->asic->ring[ring->idx]->hdp_flush) | 191 | if (hdp_flush && rdev->asic->ring[ring->idx]->hdp_flush) |
190 | rdev->asic->ring[ring->idx]->hdp_flush(rdev, ring); | 192 | rdev->asic->ring[ring->idx]->hdp_flush(rdev, ring); |
191 | /* We pad to match fetch size */ | 193 | /* We pad to match fetch size */ |
192 | while (ring->wptr & ring->align_mask) { | 194 | while (ring->wptr & ring->align_mask) { |
@@ -196,7 +198,7 @@ void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring) | |||
196 | /* If we are emitting the HDP flush via MMIO, we need to do it after | 198 | /* If we are emitting the HDP flush via MMIO, we need to do it after |
197 | * all CPU writes to VRAM finished. | 199 | * all CPU writes to VRAM finished. |
198 | */ | 200 | */ |
199 | if (rdev->asic->mmio_hdp_flush) | 201 | if (hdp_flush && rdev->asic->mmio_hdp_flush) |
200 | rdev->asic->mmio_hdp_flush(rdev); | 202 | rdev->asic->mmio_hdp_flush(rdev); |
201 | radeon_ring_set_wptr(rdev, ring); | 203 | radeon_ring_set_wptr(rdev, ring); |
202 | } | 204 | } |
@@ -207,12 +209,14 @@ void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring) | |||
207 | * | 209 | * |
208 | * @rdev: radeon_device pointer | 210 | * @rdev: radeon_device pointer |
209 | * @ring: radeon_ring structure holding ring information | 211 | * @ring: radeon_ring structure holding ring information |
212 | * @hdp_flush: Whether or not to perform an HDP cache flush | ||
210 | * | 213 | * |
211 | * Call radeon_ring_commit() then unlock the ring (all asics). | 214 | * Call radeon_ring_commit() then unlock the ring (all asics). |
212 | */ | 215 | */ |
213 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring) | 216 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring, |
217 | bool hdp_flush) | ||
214 | { | 218 | { |
215 | radeon_ring_commit(rdev, ring); | 219 | radeon_ring_commit(rdev, ring, hdp_flush); |
216 | mutex_unlock(&rdev->ring_lock); | 220 | mutex_unlock(&rdev->ring_lock); |
217 | } | 221 | } |
218 | 222 | ||
@@ -372,7 +376,7 @@ int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, | |||
372 | radeon_ring_write(ring, data[i]); | 376 | radeon_ring_write(ring, data[i]); |
373 | } | 377 | } |
374 | 378 | ||
375 | radeon_ring_unlock_commit(rdev, ring); | 379 | radeon_ring_unlock_commit(rdev, ring, false); |
376 | kfree(data); | 380 | kfree(data); |
377 | return 0; | 381 | return 0; |
378 | } | 382 | } |
@@ -400,9 +404,7 @@ int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsig | |||
400 | /* Allocate ring buffer */ | 404 | /* Allocate ring buffer */ |
401 | if (ring->ring_obj == NULL) { | 405 | if (ring->ring_obj == NULL) { |
402 | r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true, | 406 | r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true, |
403 | RADEON_GEM_DOMAIN_GTT, | 407 | RADEON_GEM_DOMAIN_GTT, 0, |
404 | (rdev->flags & RADEON_IS_PCIE) ? | ||
405 | RADEON_GEM_GTT_WC : 0, | ||
406 | NULL, &ring->ring_obj); | 408 | NULL, &ring->ring_obj); |
407 | if (r) { | 409 | if (r) { |
408 | dev_err(rdev->dev, "(%d) ring create failed\n", r); | 410 | dev_err(rdev->dev, "(%d) ring create failed\n", r); |
diff --git a/drivers/gpu/drm/radeon/radeon_semaphore.c b/drivers/gpu/drm/radeon/radeon_semaphore.c index dbd6bcde92de..56d9fd66d8ae 100644 --- a/drivers/gpu/drm/radeon/radeon_semaphore.c +++ b/drivers/gpu/drm/radeon/radeon_semaphore.c | |||
@@ -179,7 +179,7 @@ int radeon_semaphore_sync_rings(struct radeon_device *rdev, | |||
179 | continue; | 179 | continue; |
180 | } | 180 | } |
181 | 181 | ||
182 | radeon_ring_commit(rdev, &rdev->ring[i]); | 182 | radeon_ring_commit(rdev, &rdev->ring[i], false); |
183 | radeon_fence_note_sync(fence, ring); | 183 | radeon_fence_note_sync(fence, ring); |
184 | 184 | ||
185 | semaphore->gpu_addr += 8; | 185 | semaphore->gpu_addr += 8; |
diff --git a/drivers/gpu/drm/radeon/radeon_test.c b/drivers/gpu/drm/radeon/radeon_test.c index 5adf4207453d..17bc3dced9f1 100644 --- a/drivers/gpu/drm/radeon/radeon_test.c +++ b/drivers/gpu/drm/radeon/radeon_test.c | |||
@@ -288,7 +288,7 @@ static int radeon_test_create_and_emit_fence(struct radeon_device *rdev, | |||
288 | return r; | 288 | return r; |
289 | } | 289 | } |
290 | radeon_fence_emit(rdev, fence, ring->idx); | 290 | radeon_fence_emit(rdev, fence, ring->idx); |
291 | radeon_ring_unlock_commit(rdev, ring); | 291 | radeon_ring_unlock_commit(rdev, ring, false); |
292 | } | 292 | } |
293 | return 0; | 293 | return 0; |
294 | } | 294 | } |
@@ -313,7 +313,7 @@ void radeon_test_ring_sync(struct radeon_device *rdev, | |||
313 | goto out_cleanup; | 313 | goto out_cleanup; |
314 | } | 314 | } |
315 | radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore); | 315 | radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore); |
316 | radeon_ring_unlock_commit(rdev, ringA); | 316 | radeon_ring_unlock_commit(rdev, ringA, false); |
317 | 317 | ||
318 | r = radeon_test_create_and_emit_fence(rdev, ringA, &fence1); | 318 | r = radeon_test_create_and_emit_fence(rdev, ringA, &fence1); |
319 | if (r) | 319 | if (r) |
@@ -325,7 +325,7 @@ void radeon_test_ring_sync(struct radeon_device *rdev, | |||
325 | goto out_cleanup; | 325 | goto out_cleanup; |
326 | } | 326 | } |
327 | radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore); | 327 | radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore); |
328 | radeon_ring_unlock_commit(rdev, ringA); | 328 | radeon_ring_unlock_commit(rdev, ringA, false); |
329 | 329 | ||
330 | r = radeon_test_create_and_emit_fence(rdev, ringA, &fence2); | 330 | r = radeon_test_create_and_emit_fence(rdev, ringA, &fence2); |
331 | if (r) | 331 | if (r) |
@@ -344,7 +344,7 @@ void radeon_test_ring_sync(struct radeon_device *rdev, | |||
344 | goto out_cleanup; | 344 | goto out_cleanup; |
345 | } | 345 | } |
346 | radeon_semaphore_emit_signal(rdev, ringB->idx, semaphore); | 346 | radeon_semaphore_emit_signal(rdev, ringB->idx, semaphore); |
347 | radeon_ring_unlock_commit(rdev, ringB); | 347 | radeon_ring_unlock_commit(rdev, ringB, false); |
348 | 348 | ||
349 | r = radeon_fence_wait(fence1, false); | 349 | r = radeon_fence_wait(fence1, false); |
350 | if (r) { | 350 | if (r) { |
@@ -365,7 +365,7 @@ void radeon_test_ring_sync(struct radeon_device *rdev, | |||
365 | goto out_cleanup; | 365 | goto out_cleanup; |
366 | } | 366 | } |
367 | radeon_semaphore_emit_signal(rdev, ringB->idx, semaphore); | 367 | radeon_semaphore_emit_signal(rdev, ringB->idx, semaphore); |
368 | radeon_ring_unlock_commit(rdev, ringB); | 368 | radeon_ring_unlock_commit(rdev, ringB, false); |
369 | 369 | ||
370 | r = radeon_fence_wait(fence2, false); | 370 | r = radeon_fence_wait(fence2, false); |
371 | if (r) { | 371 | if (r) { |
@@ -408,7 +408,7 @@ static void radeon_test_ring_sync2(struct radeon_device *rdev, | |||
408 | goto out_cleanup; | 408 | goto out_cleanup; |
409 | } | 409 | } |
410 | radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore); | 410 | radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore); |
411 | radeon_ring_unlock_commit(rdev, ringA); | 411 | radeon_ring_unlock_commit(rdev, ringA, false); |
412 | 412 | ||
413 | r = radeon_test_create_and_emit_fence(rdev, ringA, &fenceA); | 413 | r = radeon_test_create_and_emit_fence(rdev, ringA, &fenceA); |
414 | if (r) | 414 | if (r) |
@@ -420,7 +420,7 @@ static void radeon_test_ring_sync2(struct radeon_device *rdev, | |||
420 | goto out_cleanup; | 420 | goto out_cleanup; |
421 | } | 421 | } |
422 | radeon_semaphore_emit_wait(rdev, ringB->idx, semaphore); | 422 | radeon_semaphore_emit_wait(rdev, ringB->idx, semaphore); |
423 | radeon_ring_unlock_commit(rdev, ringB); | 423 | radeon_ring_unlock_commit(rdev, ringB, false); |
424 | r = radeon_test_create_and_emit_fence(rdev, ringB, &fenceB); | 424 | r = radeon_test_create_and_emit_fence(rdev, ringB, &fenceB); |
425 | if (r) | 425 | if (r) |
426 | goto out_cleanup; | 426 | goto out_cleanup; |
@@ -442,7 +442,7 @@ static void radeon_test_ring_sync2(struct radeon_device *rdev, | |||
442 | goto out_cleanup; | 442 | goto out_cleanup; |
443 | } | 443 | } |
444 | radeon_semaphore_emit_signal(rdev, ringC->idx, semaphore); | 444 | radeon_semaphore_emit_signal(rdev, ringC->idx, semaphore); |
445 | radeon_ring_unlock_commit(rdev, ringC); | 445 | radeon_ring_unlock_commit(rdev, ringC, false); |
446 | 446 | ||
447 | for (i = 0; i < 30; ++i) { | 447 | for (i = 0; i < 30; ++i) { |
448 | mdelay(100); | 448 | mdelay(100); |
@@ -468,7 +468,7 @@ static void radeon_test_ring_sync2(struct radeon_device *rdev, | |||
468 | goto out_cleanup; | 468 | goto out_cleanup; |
469 | } | 469 | } |
470 | radeon_semaphore_emit_signal(rdev, ringC->idx, semaphore); | 470 | radeon_semaphore_emit_signal(rdev, ringC->idx, semaphore); |
471 | radeon_ring_unlock_commit(rdev, ringC); | 471 | radeon_ring_unlock_commit(rdev, ringC, false); |
472 | 472 | ||
473 | mdelay(1000); | 473 | mdelay(1000); |
474 | 474 | ||
diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c b/drivers/gpu/drm/radeon/radeon_uvd.c index 6bf55ec85b62..341848a14376 100644 --- a/drivers/gpu/drm/radeon/radeon_uvd.c +++ b/drivers/gpu/drm/radeon/radeon_uvd.c | |||
@@ -646,7 +646,7 @@ static int radeon_uvd_send_msg(struct radeon_device *rdev, | |||
646 | ib.ptr[i] = PACKET2(0); | 646 | ib.ptr[i] = PACKET2(0); |
647 | ib.length_dw = 16; | 647 | ib.length_dw = 16; |
648 | 648 | ||
649 | r = radeon_ib_schedule(rdev, &ib, NULL); | 649 | r = radeon_ib_schedule(rdev, &ib, NULL, false); |
650 | if (r) | 650 | if (r) |
651 | goto err; | 651 | goto err; |
652 | ttm_eu_fence_buffer_objects(&ticket, &head, ib.fence); | 652 | ttm_eu_fence_buffer_objects(&ticket, &head, ib.fence); |
diff --git a/drivers/gpu/drm/radeon/radeon_vce.c b/drivers/gpu/drm/radeon/radeon_vce.c index f9b70a43aa52..c7190aadbd89 100644 --- a/drivers/gpu/drm/radeon/radeon_vce.c +++ b/drivers/gpu/drm/radeon/radeon_vce.c | |||
@@ -368,7 +368,7 @@ int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, | |||
368 | for (i = ib.length_dw; i < ib_size_dw; ++i) | 368 | for (i = ib.length_dw; i < ib_size_dw; ++i) |
369 | ib.ptr[i] = 0x0; | 369 | ib.ptr[i] = 0x0; |
370 | 370 | ||
371 | r = radeon_ib_schedule(rdev, &ib, NULL); | 371 | r = radeon_ib_schedule(rdev, &ib, NULL, false); |
372 | if (r) { | 372 | if (r) { |
373 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); | 373 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); |
374 | } | 374 | } |
@@ -425,7 +425,7 @@ int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, | |||
425 | for (i = ib.length_dw; i < ib_size_dw; ++i) | 425 | for (i = ib.length_dw; i < ib_size_dw; ++i) |
426 | ib.ptr[i] = 0x0; | 426 | ib.ptr[i] = 0x0; |
427 | 427 | ||
428 | r = radeon_ib_schedule(rdev, &ib, NULL); | 428 | r = radeon_ib_schedule(rdev, &ib, NULL, false); |
429 | if (r) { | 429 | if (r) { |
430 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); | 430 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); |
431 | } | 431 | } |
@@ -715,7 +715,7 @@ int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) | |||
715 | return r; | 715 | return r; |
716 | } | 716 | } |
717 | radeon_ring_write(ring, VCE_CMD_END); | 717 | radeon_ring_write(ring, VCE_CMD_END); |
718 | radeon_ring_unlock_commit(rdev, ring); | 718 | radeon_ring_unlock_commit(rdev, ring, false); |
719 | 719 | ||
720 | for (i = 0; i < rdev->usec_timeout; i++) { | 720 | for (i = 0; i < rdev->usec_timeout; i++) { |
721 | if (vce_v1_0_get_rptr(rdev, ring) != rptr) | 721 | if (vce_v1_0_get_rptr(rdev, ring) != rptr) |
diff --git a/drivers/gpu/drm/radeon/radeon_vm.c b/drivers/gpu/drm/radeon/radeon_vm.c index ccae4d9dc3de..088ffdc2f577 100644 --- a/drivers/gpu/drm/radeon/radeon_vm.c +++ b/drivers/gpu/drm/radeon/radeon_vm.c | |||
@@ -420,7 +420,7 @@ static int radeon_vm_clear_bo(struct radeon_device *rdev, | |||
420 | radeon_asic_vm_pad_ib(rdev, &ib); | 420 | radeon_asic_vm_pad_ib(rdev, &ib); |
421 | WARN_ON(ib.length_dw > 64); | 421 | WARN_ON(ib.length_dw > 64); |
422 | 422 | ||
423 | r = radeon_ib_schedule(rdev, &ib, NULL); | 423 | r = radeon_ib_schedule(rdev, &ib, NULL, false); |
424 | if (r) | 424 | if (r) |
425 | goto error; | 425 | goto error; |
426 | 426 | ||
@@ -483,6 +483,10 @@ int radeon_vm_bo_set_addr(struct radeon_device *rdev, | |||
483 | /* add a clone of the bo_va to clear the old address */ | 483 | /* add a clone of the bo_va to clear the old address */ |
484 | struct radeon_bo_va *tmp; | 484 | struct radeon_bo_va *tmp; |
485 | tmp = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL); | 485 | tmp = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL); |
486 | if (!tmp) { | ||
487 | mutex_unlock(&vm->mutex); | ||
488 | return -ENOMEM; | ||
489 | } | ||
486 | tmp->it.start = bo_va->it.start; | 490 | tmp->it.start = bo_va->it.start; |
487 | tmp->it.last = bo_va->it.last; | 491 | tmp->it.last = bo_va->it.last; |
488 | tmp->vm = vm; | 492 | tmp->vm = vm; |
@@ -693,7 +697,7 @@ int radeon_vm_update_page_directory(struct radeon_device *rdev, | |||
693 | radeon_semaphore_sync_to(ib.semaphore, pd->tbo.sync_obj); | 697 | radeon_semaphore_sync_to(ib.semaphore, pd->tbo.sync_obj); |
694 | radeon_semaphore_sync_to(ib.semaphore, vm->last_id_use); | 698 | radeon_semaphore_sync_to(ib.semaphore, vm->last_id_use); |
695 | WARN_ON(ib.length_dw > ndw); | 699 | WARN_ON(ib.length_dw > ndw); |
696 | r = radeon_ib_schedule(rdev, &ib, NULL); | 700 | r = radeon_ib_schedule(rdev, &ib, NULL, false); |
697 | if (r) { | 701 | if (r) { |
698 | radeon_ib_free(rdev, &ib); | 702 | radeon_ib_free(rdev, &ib); |
699 | return r; | 703 | return r; |
@@ -957,7 +961,7 @@ int radeon_vm_bo_update(struct radeon_device *rdev, | |||
957 | WARN_ON(ib.length_dw > ndw); | 961 | WARN_ON(ib.length_dw > ndw); |
958 | 962 | ||
959 | radeon_semaphore_sync_to(ib.semaphore, vm->fence); | 963 | radeon_semaphore_sync_to(ib.semaphore, vm->fence); |
960 | r = radeon_ib_schedule(rdev, &ib, NULL); | 964 | r = radeon_ib_schedule(rdev, &ib, NULL, false); |
961 | if (r) { | 965 | if (r) { |
962 | radeon_ib_free(rdev, &ib); | 966 | radeon_ib_free(rdev, &ib); |
963 | return r; | 967 | return r; |
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c index 3e21e869015f..8a477bf1fdb3 100644 --- a/drivers/gpu/drm/radeon/rv515.c +++ b/drivers/gpu/drm/radeon/rv515.c | |||
@@ -124,7 +124,7 @@ void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) | |||
124 | radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); | 124 | radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); |
125 | radeon_ring_write(ring, PACKET0(0x20C8, 0)); | 125 | radeon_ring_write(ring, PACKET0(0x20C8, 0)); |
126 | radeon_ring_write(ring, 0); | 126 | radeon_ring_write(ring, 0); |
127 | radeon_ring_unlock_commit(rdev, ring); | 127 | radeon_ring_unlock_commit(rdev, ring, false); |
128 | } | 128 | } |
129 | 129 | ||
130 | int rv515_mc_wait_for_idle(struct radeon_device *rdev) | 130 | int rv515_mc_wait_for_idle(struct radeon_device *rdev) |
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index 2983f17ea1b3..d9f5ce715c9b 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c | |||
@@ -1177,7 +1177,6 @@ static void rv770_gpu_init(struct radeon_device *rdev) | |||
1177 | u32 hdp_host_path_cntl; | 1177 | u32 hdp_host_path_cntl; |
1178 | u32 sq_dyn_gpr_size_simd_ab_0; | 1178 | u32 sq_dyn_gpr_size_simd_ab_0; |
1179 | u32 gb_tiling_config = 0; | 1179 | u32 gb_tiling_config = 0; |
1180 | u32 cc_rb_backend_disable = 0; | ||
1181 | u32 cc_gc_shader_pipe_config = 0; | 1180 | u32 cc_gc_shader_pipe_config = 0; |
1182 | u32 mc_arb_ramcfg; | 1181 | u32 mc_arb_ramcfg; |
1183 | u32 db_debug4, tmp; | 1182 | u32 db_debug4, tmp; |
@@ -1311,21 +1310,7 @@ static void rv770_gpu_init(struct radeon_device *rdev) | |||
1311 | WREG32(SPI_CONFIG_CNTL, 0); | 1310 | WREG32(SPI_CONFIG_CNTL, 0); |
1312 | } | 1311 | } |
1313 | 1312 | ||
1314 | cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; | ||
1315 | tmp = R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_rb_backend_disable >> 16); | ||
1316 | if (tmp < rdev->config.rv770.max_backends) { | ||
1317 | rdev->config.rv770.max_backends = tmp; | ||
1318 | } | ||
1319 | |||
1320 | cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; | 1313 | cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; |
1321 | tmp = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R7XX_MAX_PIPES_MASK); | ||
1322 | if (tmp < rdev->config.rv770.max_pipes) { | ||
1323 | rdev->config.rv770.max_pipes = tmp; | ||
1324 | } | ||
1325 | tmp = R7XX_MAX_SIMDS - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R7XX_MAX_SIMDS_MASK); | ||
1326 | if (tmp < rdev->config.rv770.max_simds) { | ||
1327 | rdev->config.rv770.max_simds = tmp; | ||
1328 | } | ||
1329 | tmp = rdev->config.rv770.max_simds - | 1314 | tmp = rdev->config.rv770.max_simds - |
1330 | r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R7XX_MAX_SIMDS_MASK); | 1315 | r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R7XX_MAX_SIMDS_MASK); |
1331 | rdev->config.rv770.active_simds = tmp; | 1316 | rdev->config.rv770.active_simds = tmp; |
@@ -1348,6 +1333,14 @@ static void rv770_gpu_init(struct radeon_device *rdev) | |||
1348 | rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes; | 1333 | rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes; |
1349 | 1334 | ||
1350 | disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R7XX_MAX_BACKENDS_MASK; | 1335 | disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R7XX_MAX_BACKENDS_MASK; |
1336 | tmp = 0; | ||
1337 | for (i = 0; i < rdev->config.rv770.max_backends; i++) | ||
1338 | tmp |= (1 << i); | ||
1339 | /* if all the backends are disabled, fix it up here */ | ||
1340 | if ((disabled_rb_mask & tmp) == tmp) { | ||
1341 | for (i = 0; i < rdev->config.rv770.max_backends; i++) | ||
1342 | disabled_rb_mask &= ~(1 << i); | ||
1343 | } | ||
1351 | tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; | 1344 | tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; |
1352 | tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends, | 1345 | tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends, |
1353 | R7XX_MAX_BACKENDS, disabled_rb_mask); | 1346 | R7XX_MAX_BACKENDS, disabled_rb_mask); |
diff --git a/drivers/gpu/drm/radeon/rv770_dma.c b/drivers/gpu/drm/radeon/rv770_dma.c index bbf2e076ee45..74426ac2bb5c 100644 --- a/drivers/gpu/drm/radeon/rv770_dma.c +++ b/drivers/gpu/drm/radeon/rv770_dma.c | |||
@@ -90,7 +90,7 @@ int rv770_copy_dma(struct radeon_device *rdev, | |||
90 | return r; | 90 | return r; |
91 | } | 91 | } |
92 | 92 | ||
93 | radeon_ring_unlock_commit(rdev, ring); | 93 | radeon_ring_unlock_commit(rdev, ring, false); |
94 | radeon_semaphore_free(rdev, &sem, *fence); | 94 | radeon_semaphore_free(rdev, &sem, *fence); |
95 | 95 | ||
96 | return r; | 96 | return r; |
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index 011779bd2b3d..6bce40847753 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c | |||
@@ -3057,7 +3057,7 @@ static void si_gpu_init(struct radeon_device *rdev) | |||
3057 | u32 sx_debug_1; | 3057 | u32 sx_debug_1; |
3058 | u32 hdp_host_path_cntl; | 3058 | u32 hdp_host_path_cntl; |
3059 | u32 tmp; | 3059 | u32 tmp; |
3060 | int i, j, k; | 3060 | int i, j; |
3061 | 3061 | ||
3062 | switch (rdev->family) { | 3062 | switch (rdev->family) { |
3063 | case CHIP_TAHITI: | 3063 | case CHIP_TAHITI: |
@@ -3255,12 +3255,11 @@ static void si_gpu_init(struct radeon_device *rdev) | |||
3255 | rdev->config.si.max_sh_per_se, | 3255 | rdev->config.si.max_sh_per_se, |
3256 | rdev->config.si.max_cu_per_sh); | 3256 | rdev->config.si.max_cu_per_sh); |
3257 | 3257 | ||
3258 | rdev->config.si.active_cus = 0; | ||
3258 | for (i = 0; i < rdev->config.si.max_shader_engines; i++) { | 3259 | for (i = 0; i < rdev->config.si.max_shader_engines; i++) { |
3259 | for (j = 0; j < rdev->config.si.max_sh_per_se; j++) { | 3260 | for (j = 0; j < rdev->config.si.max_sh_per_se; j++) { |
3260 | for (k = 0; k < rdev->config.si.max_cu_per_sh; k++) { | 3261 | rdev->config.si.active_cus += |
3261 | rdev->config.si.active_cus += | 3262 | hweight32(si_get_cu_active_bitmap(rdev, i, j)); |
3262 | hweight32(si_get_cu_active_bitmap(rdev, i, j)); | ||
3263 | } | ||
3264 | } | 3263 | } |
3265 | } | 3264 | } |
3266 | 3265 | ||
@@ -3541,7 +3540,7 @@ static int si_cp_start(struct radeon_device *rdev) | |||
3541 | radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); | 3540 | radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); |
3542 | radeon_ring_write(ring, 0xc000); | 3541 | radeon_ring_write(ring, 0xc000); |
3543 | radeon_ring_write(ring, 0xe000); | 3542 | radeon_ring_write(ring, 0xe000); |
3544 | radeon_ring_unlock_commit(rdev, ring); | 3543 | radeon_ring_unlock_commit(rdev, ring, false); |
3545 | 3544 | ||
3546 | si_cp_enable(rdev, true); | 3545 | si_cp_enable(rdev, true); |
3547 | 3546 | ||
@@ -3570,7 +3569,7 @@ static int si_cp_start(struct radeon_device *rdev) | |||
3570 | radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ | 3569 | radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ |
3571 | radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ | 3570 | radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ |
3572 | 3571 | ||
3573 | radeon_ring_unlock_commit(rdev, ring); | 3572 | radeon_ring_unlock_commit(rdev, ring, false); |
3574 | 3573 | ||
3575 | for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) { | 3574 | for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) { |
3576 | ring = &rdev->ring[i]; | 3575 | ring = &rdev->ring[i]; |
@@ -3580,7 +3579,7 @@ static int si_cp_start(struct radeon_device *rdev) | |||
3580 | radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0)); | 3579 | radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0)); |
3581 | radeon_ring_write(ring, 0); | 3580 | radeon_ring_write(ring, 0); |
3582 | 3581 | ||
3583 | radeon_ring_unlock_commit(rdev, ring); | 3582 | radeon_ring_unlock_commit(rdev, ring, false); |
3584 | } | 3583 | } |
3585 | 3584 | ||
3586 | return 0; | 3585 | return 0; |
@@ -4291,10 +4290,10 @@ static int si_pcie_gart_enable(struct radeon_device *rdev) | |||
4291 | for (i = 1; i < 16; i++) { | 4290 | for (i = 1; i < 16; i++) { |
4292 | if (i < 8) | 4291 | if (i < 8) |
4293 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), | 4292 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), |
4294 | rdev->gart.table_addr >> 12); | 4293 | rdev->vm_manager.saved_table_addr[i]); |
4295 | else | 4294 | else |
4296 | WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2), | 4295 | WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2), |
4297 | rdev->gart.table_addr >> 12); | 4296 | rdev->vm_manager.saved_table_addr[i]); |
4298 | } | 4297 | } |
4299 | 4298 | ||
4300 | /* enable context1-15 */ | 4299 | /* enable context1-15 */ |
@@ -4326,6 +4325,17 @@ static int si_pcie_gart_enable(struct radeon_device *rdev) | |||
4326 | 4325 | ||
4327 | static void si_pcie_gart_disable(struct radeon_device *rdev) | 4326 | static void si_pcie_gart_disable(struct radeon_device *rdev) |
4328 | { | 4327 | { |
4328 | unsigned i; | ||
4329 | |||
4330 | for (i = 1; i < 16; ++i) { | ||
4331 | uint32_t reg; | ||
4332 | if (i < 8) | ||
4333 | reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2); | ||
4334 | else | ||
4335 | reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2); | ||
4336 | rdev->vm_manager.saved_table_addr[i] = RREG32(reg); | ||
4337 | } | ||
4338 | |||
4329 | /* Disable all tables */ | 4339 | /* Disable all tables */ |
4330 | WREG32(VM_CONTEXT0_CNTL, 0); | 4340 | WREG32(VM_CONTEXT0_CNTL, 0); |
4331 | WREG32(VM_CONTEXT1_CNTL, 0); | 4341 | WREG32(VM_CONTEXT1_CNTL, 0); |
@@ -5028,7 +5038,7 @@ void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) | |||
5028 | 5038 | ||
5029 | /* flush hdp cache */ | 5039 | /* flush hdp cache */ |
5030 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); | 5040 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); |
5031 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | | 5041 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | |
5032 | WRITE_DATA_DST_SEL(0))); | 5042 | WRITE_DATA_DST_SEL(0))); |
5033 | radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2); | 5043 | radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2); |
5034 | radeon_ring_write(ring, 0); | 5044 | radeon_ring_write(ring, 0); |
@@ -5036,7 +5046,7 @@ void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) | |||
5036 | 5046 | ||
5037 | /* bits 0-15 are the VM contexts0-15 */ | 5047 | /* bits 0-15 are the VM contexts0-15 */ |
5038 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); | 5048 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); |
5039 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | | 5049 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | |
5040 | WRITE_DATA_DST_SEL(0))); | 5050 | WRITE_DATA_DST_SEL(0))); |
5041 | radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); | 5051 | radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); |
5042 | radeon_ring_write(ring, 0); | 5052 | radeon_ring_write(ring, 0); |
@@ -7178,6 +7188,9 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) | |||
7178 | int ret, i; | 7188 | int ret, i; |
7179 | u16 tmp16; | 7189 | u16 tmp16; |
7180 | 7190 | ||
7191 | if (pci_is_root_bus(rdev->pdev->bus)) | ||
7192 | return; | ||
7193 | |||
7181 | if (radeon_pcie_gen2 == 0) | 7194 | if (radeon_pcie_gen2 == 0) |
7182 | return; | 7195 | return; |
7183 | 7196 | ||
@@ -7455,7 +7468,8 @@ static void si_program_aspm(struct radeon_device *rdev) | |||
7455 | if (orig != data) | 7468 | if (orig != data) |
7456 | WREG32_PIF_PHY1(PB1_PIF_CNTL, data); | 7469 | WREG32_PIF_PHY1(PB1_PIF_CNTL, data); |
7457 | 7470 | ||
7458 | if (!disable_clkreq) { | 7471 | if (!disable_clkreq && |
7472 | !pci_is_root_bus(rdev->pdev->bus)) { | ||
7459 | struct pci_dev *root = rdev->pdev->bus->self; | 7473 | struct pci_dev *root = rdev->pdev->bus->self; |
7460 | u32 lnkcap; | 7474 | u32 lnkcap; |
7461 | 7475 | ||
diff --git a/drivers/gpu/drm/radeon/si_dma.c b/drivers/gpu/drm/radeon/si_dma.c index 716505129450..7c22baaf94db 100644 --- a/drivers/gpu/drm/radeon/si_dma.c +++ b/drivers/gpu/drm/radeon/si_dma.c | |||
@@ -275,7 +275,7 @@ int si_copy_dma(struct radeon_device *rdev, | |||
275 | return r; | 275 | return r; |
276 | } | 276 | } |
277 | 277 | ||
278 | radeon_ring_unlock_commit(rdev, ring); | 278 | radeon_ring_unlock_commit(rdev, ring, false); |
279 | radeon_semaphore_free(rdev, &sem, *fence); | 279 | radeon_semaphore_free(rdev, &sem, *fence); |
280 | 280 | ||
281 | return r; | 281 | return r; |
diff --git a/drivers/gpu/drm/radeon/trinity_dpm.c b/drivers/gpu/drm/radeon/trinity_dpm.c index 32e50be9c4ac..57f780053b3e 100644 --- a/drivers/gpu/drm/radeon/trinity_dpm.c +++ b/drivers/gpu/drm/radeon/trinity_dpm.c | |||
@@ -1874,16 +1874,22 @@ int trinity_dpm_init(struct radeon_device *rdev) | |||
1874 | for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) | 1874 | for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) |
1875 | pi->at[i] = TRINITY_AT_DFLT; | 1875 | pi->at[i] = TRINITY_AT_DFLT; |
1876 | 1876 | ||
1877 | /* There are stability issues reported on with | 1877 | if (radeon_bapm == -1) { |
1878 | * bapm enabled when switching between AC and battery | 1878 | /* There are stability issues reported on with |
1879 | * power. At the same time, some MSI boards hang | 1879 | * bapm enabled when switching between AC and battery |
1880 | * if it's not enabled and dpm is enabled. Just enable | 1880 | * power. At the same time, some MSI boards hang |
1881 | * it for MSI boards right now. | 1881 | * if it's not enabled and dpm is enabled. Just enable |
1882 | */ | 1882 | * it for MSI boards right now. |
1883 | if (rdev->pdev->subsystem_vendor == 0x1462) | 1883 | */ |
1884 | pi->enable_bapm = true; | 1884 | if (rdev->pdev->subsystem_vendor == 0x1462) |
1885 | else | 1885 | pi->enable_bapm = true; |
1886 | else | ||
1887 | pi->enable_bapm = false; | ||
1888 | } else if (radeon_bapm == 0) { | ||
1886 | pi->enable_bapm = false; | 1889 | pi->enable_bapm = false; |
1890 | } else { | ||
1891 | pi->enable_bapm = true; | ||
1892 | } | ||
1887 | pi->enable_nbps_policy = true; | 1893 | pi->enable_nbps_policy = true; |
1888 | pi->enable_sclk_ds = true; | 1894 | pi->enable_sclk_ds = true; |
1889 | pi->enable_gfx_power_gating = true; | 1895 | pi->enable_gfx_power_gating = true; |
diff --git a/drivers/gpu/drm/radeon/uvd_v1_0.c b/drivers/gpu/drm/radeon/uvd_v1_0.c index be42c8125203..cda391347286 100644 --- a/drivers/gpu/drm/radeon/uvd_v1_0.c +++ b/drivers/gpu/drm/radeon/uvd_v1_0.c | |||
@@ -124,7 +124,7 @@ int uvd_v1_0_init(struct radeon_device *rdev) | |||
124 | radeon_ring_write(ring, PACKET0(UVD_SEMA_CNTL, 0)); | 124 | radeon_ring_write(ring, PACKET0(UVD_SEMA_CNTL, 0)); |
125 | radeon_ring_write(ring, 3); | 125 | radeon_ring_write(ring, 3); |
126 | 126 | ||
127 | radeon_ring_unlock_commit(rdev, ring); | 127 | radeon_ring_unlock_commit(rdev, ring, false); |
128 | 128 | ||
129 | done: | 129 | done: |
130 | /* lower clocks again */ | 130 | /* lower clocks again */ |
@@ -331,7 +331,7 @@ int uvd_v1_0_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) | |||
331 | } | 331 | } |
332 | radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); | 332 | radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); |
333 | radeon_ring_write(ring, 0xDEADBEEF); | 333 | radeon_ring_write(ring, 0xDEADBEEF); |
334 | radeon_ring_unlock_commit(rdev, ring); | 334 | radeon_ring_unlock_commit(rdev, ring, false); |
335 | for (i = 0; i < rdev->usec_timeout; i++) { | 335 | for (i = 0; i < rdev->usec_timeout; i++) { |
336 | tmp = RREG32(UVD_CONTEXT_ID); | 336 | tmp = RREG32(UVD_CONTEXT_ID); |
337 | if (tmp == 0xDEADBEEF) | 337 | if (tmp == 0xDEADBEEF) |
diff --git a/drivers/gpu/drm/sti/Kconfig b/drivers/gpu/drm/sti/Kconfig index 2d9d4252d598..ae8850f3e63b 100644 --- a/drivers/gpu/drm/sti/Kconfig +++ b/drivers/gpu/drm/sti/Kconfig | |||
@@ -1,6 +1,7 @@ | |||
1 | config DRM_STI | 1 | config DRM_STI |
2 | tristate "DRM Support for STMicroelectronics SoC stiH41x Series" | 2 | tristate "DRM Support for STMicroelectronics SoC stiH41x Series" |
3 | depends on DRM && (SOC_STIH415 || SOC_STIH416 || ARCH_MULTIPLATFORM) | 3 | depends on DRM && (SOC_STIH415 || SOC_STIH416 || ARCH_MULTIPLATFORM) |
4 | select RESET_CONTROLLER | ||
4 | select DRM_KMS_HELPER | 5 | select DRM_KMS_HELPER |
5 | select DRM_GEM_CMA_HELPER | 6 | select DRM_GEM_CMA_HELPER |
6 | select DRM_KMS_CMA_HELPER | 7 | select DRM_KMS_CMA_HELPER |
diff --git a/drivers/gpu/drm/sti/sti_drm_drv.c b/drivers/gpu/drm/sti/sti_drm_drv.c index a7cc24917a96..223d93c3a05d 100644 --- a/drivers/gpu/drm/sti/sti_drm_drv.c +++ b/drivers/gpu/drm/sti/sti_drm_drv.c | |||
@@ -201,8 +201,8 @@ static int sti_drm_platform_probe(struct platform_device *pdev) | |||
201 | master = platform_device_register_resndata(dev, | 201 | master = platform_device_register_resndata(dev, |
202 | DRIVER_NAME "__master", -1, | 202 | DRIVER_NAME "__master", -1, |
203 | NULL, 0, NULL, 0); | 203 | NULL, 0, NULL, 0); |
204 | if (!master) | 204 | if (IS_ERR(master)) |
205 | return -EINVAL; | 205 | return PTR_ERR(master); |
206 | 206 | ||
207 | platform_set_drvdata(pdev, master); | 207 | platform_set_drvdata(pdev, master); |
208 | return 0; | 208 | return 0; |
diff --git a/drivers/gpu/drm/sti/sti_hda.c b/drivers/gpu/drm/sti/sti_hda.c index 72d957f81c05..2ae9a9b73666 100644 --- a/drivers/gpu/drm/sti/sti_hda.c +++ b/drivers/gpu/drm/sti/sti_hda.c | |||
@@ -730,16 +730,16 @@ static int sti_hda_probe(struct platform_device *pdev) | |||
730 | return -ENOMEM; | 730 | return -ENOMEM; |
731 | } | 731 | } |
732 | hda->regs = devm_ioremap_nocache(dev, res->start, resource_size(res)); | 732 | hda->regs = devm_ioremap_nocache(dev, res->start, resource_size(res)); |
733 | if (IS_ERR(hda->regs)) | 733 | if (!hda->regs) |
734 | return PTR_ERR(hda->regs); | 734 | return -ENOMEM; |
735 | 735 | ||
736 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, | 736 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
737 | "video-dacs-ctrl"); | 737 | "video-dacs-ctrl"); |
738 | if (res) { | 738 | if (res) { |
739 | hda->video_dacs_ctrl = devm_ioremap_nocache(dev, res->start, | 739 | hda->video_dacs_ctrl = devm_ioremap_nocache(dev, res->start, |
740 | resource_size(res)); | 740 | resource_size(res)); |
741 | if (IS_ERR(hda->video_dacs_ctrl)) | 741 | if (!hda->video_dacs_ctrl) |
742 | return PTR_ERR(hda->video_dacs_ctrl); | 742 | return -ENOMEM; |
743 | } else { | 743 | } else { |
744 | /* If no existing video-dacs-ctrl resource continue the probe */ | 744 | /* If no existing video-dacs-ctrl resource continue the probe */ |
745 | DRM_DEBUG_DRIVER("No video-dacs-ctrl resource\n"); | 745 | DRM_DEBUG_DRIVER("No video-dacs-ctrl resource\n"); |
@@ -770,7 +770,7 @@ static int sti_hda_remove(struct platform_device *pdev) | |||
770 | return 0; | 770 | return 0; |
771 | } | 771 | } |
772 | 772 | ||
773 | static struct of_device_id hda_of_match[] = { | 773 | static const struct of_device_id hda_of_match[] = { |
774 | { .compatible = "st,stih416-hda", }, | 774 | { .compatible = "st,stih416-hda", }, |
775 | { .compatible = "st,stih407-hda", }, | 775 | { .compatible = "st,stih407-hda", }, |
776 | { /* end node */ } | 776 | { /* end node */ } |
diff --git a/drivers/gpu/drm/sti/sti_hdmi.c b/drivers/gpu/drm/sti/sti_hdmi.c index 284e541d970d..ef93156a69c6 100644 --- a/drivers/gpu/drm/sti/sti_hdmi.c +++ b/drivers/gpu/drm/sti/sti_hdmi.c | |||
@@ -677,7 +677,7 @@ static const struct component_ops sti_hdmi_ops = { | |||
677 | .unbind = sti_hdmi_unbind, | 677 | .unbind = sti_hdmi_unbind, |
678 | }; | 678 | }; |
679 | 679 | ||
680 | static struct of_device_id hdmi_of_match[] = { | 680 | static const struct of_device_id hdmi_of_match[] = { |
681 | { | 681 | { |
682 | .compatible = "st,stih416-hdmi", | 682 | .compatible = "st,stih416-hdmi", |
683 | .data = &tx3g0c55phy_ops, | 683 | .data = &tx3g0c55phy_ops, |
@@ -713,8 +713,8 @@ static int sti_hdmi_probe(struct platform_device *pdev) | |||
713 | return -ENOMEM; | 713 | return -ENOMEM; |
714 | } | 714 | } |
715 | hdmi->regs = devm_ioremap_nocache(dev, res->start, resource_size(res)); | 715 | hdmi->regs = devm_ioremap_nocache(dev, res->start, resource_size(res)); |
716 | if (IS_ERR(hdmi->regs)) | 716 | if (!hdmi->regs) |
717 | return PTR_ERR(hdmi->regs); | 717 | return -ENOMEM; |
718 | 718 | ||
719 | if (of_device_is_compatible(np, "st,stih416-hdmi")) { | 719 | if (of_device_is_compatible(np, "st,stih416-hdmi")) { |
720 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, | 720 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
@@ -725,8 +725,8 @@ static int sti_hdmi_probe(struct platform_device *pdev) | |||
725 | } | 725 | } |
726 | hdmi->syscfg = devm_ioremap_nocache(dev, res->start, | 726 | hdmi->syscfg = devm_ioremap_nocache(dev, res->start, |
727 | resource_size(res)); | 727 | resource_size(res)); |
728 | if (IS_ERR(hdmi->syscfg)) | 728 | if (!hdmi->syscfg) |
729 | return PTR_ERR(hdmi->syscfg); | 729 | return -ENOMEM; |
730 | 730 | ||
731 | } | 731 | } |
732 | 732 | ||
diff --git a/drivers/gpu/drm/sti/sti_tvout.c b/drivers/gpu/drm/sti/sti_tvout.c index b69e26fee76e..b8afe490356a 100644 --- a/drivers/gpu/drm/sti/sti_tvout.c +++ b/drivers/gpu/drm/sti/sti_tvout.c | |||
@@ -591,8 +591,8 @@ static int sti_tvout_probe(struct platform_device *pdev) | |||
591 | return -ENOMEM; | 591 | return -ENOMEM; |
592 | } | 592 | } |
593 | tvout->regs = devm_ioremap_nocache(dev, res->start, resource_size(res)); | 593 | tvout->regs = devm_ioremap_nocache(dev, res->start, resource_size(res)); |
594 | if (IS_ERR(tvout->regs)) | 594 | if (!tvout->regs) |
595 | return PTR_ERR(tvout->regs); | 595 | return -ENOMEM; |
596 | 596 | ||
597 | /* get reset resources */ | 597 | /* get reset resources */ |
598 | tvout->reset = devm_reset_control_get(dev, "tvout"); | 598 | tvout->reset = devm_reset_control_get(dev, "tvout"); |
@@ -624,7 +624,7 @@ static int sti_tvout_remove(struct platform_device *pdev) | |||
624 | return 0; | 624 | return 0; |
625 | } | 625 | } |
626 | 626 | ||
627 | static struct of_device_id tvout_of_match[] = { | 627 | static const struct of_device_id tvout_of_match[] = { |
628 | { .compatible = "st,stih416-tvout", }, | 628 | { .compatible = "st,stih416-tvout", }, |
629 | { .compatible = "st,stih407-tvout", }, | 629 | { .compatible = "st,stih407-tvout", }, |
630 | { /* end node */ } | 630 | { /* end node */ } |
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c index 7bfdaa163a33..36b871686d3c 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c | |||
@@ -450,11 +450,11 @@ static int vmw_cmd_res_reloc_add(struct vmw_private *dev_priv, | |||
450 | res, | 450 | res, |
451 | id_loc - sw_context->buf_start); | 451 | id_loc - sw_context->buf_start); |
452 | if (unlikely(ret != 0)) | 452 | if (unlikely(ret != 0)) |
453 | goto out_err; | 453 | return ret; |
454 | 454 | ||
455 | ret = vmw_resource_val_add(sw_context, res, &node); | 455 | ret = vmw_resource_val_add(sw_context, res, &node); |
456 | if (unlikely(ret != 0)) | 456 | if (unlikely(ret != 0)) |
457 | goto out_err; | 457 | return ret; |
458 | 458 | ||
459 | if (res_type == vmw_res_context && dev_priv->has_mob && | 459 | if (res_type == vmw_res_context && dev_priv->has_mob && |
460 | node->first_usage) { | 460 | node->first_usage) { |
@@ -468,13 +468,13 @@ static int vmw_cmd_res_reloc_add(struct vmw_private *dev_priv, | |||
468 | 468 | ||
469 | ret = vmw_resource_context_res_add(dev_priv, sw_context, res); | 469 | ret = vmw_resource_context_res_add(dev_priv, sw_context, res); |
470 | if (unlikely(ret != 0)) | 470 | if (unlikely(ret != 0)) |
471 | goto out_err; | 471 | return ret; |
472 | node->staged_bindings = | 472 | node->staged_bindings = |
473 | kzalloc(sizeof(*node->staged_bindings), GFP_KERNEL); | 473 | kzalloc(sizeof(*node->staged_bindings), GFP_KERNEL); |
474 | if (node->staged_bindings == NULL) { | 474 | if (node->staged_bindings == NULL) { |
475 | DRM_ERROR("Failed to allocate context binding " | 475 | DRM_ERROR("Failed to allocate context binding " |
476 | "information.\n"); | 476 | "information.\n"); |
477 | goto out_err; | 477 | return -ENOMEM; |
478 | } | 478 | } |
479 | INIT_LIST_HEAD(&node->staged_bindings->list); | 479 | INIT_LIST_HEAD(&node->staged_bindings->list); |
480 | } | 480 | } |
@@ -482,8 +482,7 @@ static int vmw_cmd_res_reloc_add(struct vmw_private *dev_priv, | |||
482 | if (p_val) | 482 | if (p_val) |
483 | *p_val = node; | 483 | *p_val = node; |
484 | 484 | ||
485 | out_err: | 485 | return 0; |
486 | return ret; | ||
487 | } | 486 | } |
488 | 487 | ||
489 | 488 | ||
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c b/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c index 6ccd993e26bf..6eae14d2a3f7 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c | |||
@@ -180,8 +180,9 @@ void vmw_fifo_release(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo) | |||
180 | 180 | ||
181 | mutex_lock(&dev_priv->hw_mutex); | 181 | mutex_lock(&dev_priv->hw_mutex); |
182 | 182 | ||
183 | vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC); | ||
183 | while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0) | 184 | while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0) |
184 | vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC); | 185 | ; |
185 | 186 | ||
186 | dev_priv->last_read_seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE); | 187 | dev_priv->last_read_seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE); |
187 | 188 | ||