146 files changed, 5671 insertions, 2691 deletions

diff --git a/drivers/gpu/drm/ati_pcigart.c b/drivers/gpu/drm/ati_pcigart.c
index 628eae3e9b83..a1fce68e3bbe 100644
--- a/drivers/gpu/drm/ati_pcigart.c
+++ b/drivers/gpu/drm/ati_pcigart.c
@@ -39,8 +39,7 @@ static int drm_ati_alloc_pcigart_table(struct drm_device *dev,
                                        struct drm_ati_pcigart_info *gart_info)
 {
         gart_info->table_handle = drm_pci_alloc(dev, gart_info->table_size,
-                                                PAGE_SIZE,
-                                                gart_info->table_mask);
+                                                PAGE_SIZE);
         if (gart_info->table_handle == NULL)
                 return -ENOMEM;
 
@@ -112,6 +111,13 @@ int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *ga
         if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
                 DRM_DEBUG("PCI: no table in VRAM: using normal RAM\n");
 
+                if (pci_set_dma_mask(dev->pdev, gart_info->table_mask)) {
+                        DRM_ERROR("fail to set dma mask to 0x%Lx\n",
+                                  gart_info->table_mask);
+                        ret = 1;
+                        goto done;
+                }
+
                 ret = drm_ati_alloc_pcigart_table(dev, gart_info);
                 if (ret) {
                         DRM_ERROR("cannot allocate PCI GART page!\n");
diff --git a/drivers/gpu/drm/drm_bufs.c b/drivers/gpu/drm/drm_bufs.c
index 3d09e304f6f4..8417cc4c43f1 100644
--- a/drivers/gpu/drm/drm_bufs.c
+++ b/drivers/gpu/drm/drm_bufs.c
@@ -326,7 +326,7 @@ static int drm_addmap_core(struct drm_device * dev, resource_size_t offset,
                  * As we're limiting the address to 2^32-1 (or less),
                  * casting it down to 32 bits is no problem, but we
                  * need to point to a 64bit variable first. */
-                dmah = drm_pci_alloc(dev, map->size, map->size, 0xffffffffUL);
+                dmah = drm_pci_alloc(dev, map->size, map->size);
                 if (!dmah) {
                         kfree(map);
                         return -ENOMEM;
@@ -885,7 +885,7 @@ int drm_addbufs_pci(struct drm_device * dev, struct drm_buf_desc * request)
 
         while (entry->buf_count < count) {
 
-                dmah = drm_pci_alloc(dev, PAGE_SIZE << page_order, 0x1000, 0xfffffffful);
+                dmah = drm_pci_alloc(dev, PAGE_SIZE << page_order, 0x1000);
 
                 if (!dmah) {
                         /* Set count correctly so we free the proper amount. */
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 5124401f266a..d91fb8c0b7b3 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -158,6 +158,7 @@ static struct drm_conn_prop_enum_list drm_connector_enum_list[] =
         { DRM_MODE_CONNECTOR_HDMIA, "HDMI Type A", 0 },
         { DRM_MODE_CONNECTOR_HDMIB, "HDMI Type B", 0 },
         { DRM_MODE_CONNECTOR_TV, "TV", 0 },
+        { DRM_MODE_CONNECTOR_eDP, "Embedded DisplayPort", 0 },
 };
 
 static struct drm_prop_enum_list drm_encoder_enum_list[] =
diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
index 4231d6db72ec..077313f0d47f 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -216,7 +216,7 @@ bool drm_helper_crtc_in_use(struct drm_crtc *crtc)
 EXPORT_SYMBOL(drm_helper_crtc_in_use);
 
 /**
- * drm_disable_unused_functions - disable unused objects
+ * drm_helper_disable_unused_functions - disable unused objects
  * @dev: DRM device
  *
  * LOCKING:
@@ -1032,7 +1032,7 @@ bool drm_helper_initial_config(struct drm_device *dev)
         /*
          * we shouldn't end up with no modes here.
          */
-        WARN(!count, "No connectors reported connected with modes\n");
+        printk(KERN_INFO "No connectors reported conncted with modes\n");
 
         drm_setup_crtcs(dev);
 
@@ -1162,6 +1162,9 @@ EXPORT_SYMBOL(drm_helper_mode_fill_fb_struct);
 int drm_helper_resume_force_mode(struct drm_device *dev)
 {
         struct drm_crtc *crtc;
+        struct drm_encoder *encoder;
+        struct drm_encoder_helper_funcs *encoder_funcs;
+        struct drm_crtc_helper_funcs *crtc_funcs;
         int ret;
 
         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
@@ -1174,6 +1177,25 @@ int drm_helper_resume_force_mode(struct drm_device *dev)
 
                 if (ret == false)
                         DRM_ERROR("failed to set mode on crtc %p\n", crtc);
+
+                /* Turn off outputs that were already powered off */
+                if (drm_helper_choose_crtc_dpms(crtc)) {
+                        list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+
+                                if(encoder->crtc != crtc)
+                                        continue;
+
+                                encoder_funcs = encoder->helper_private;
+                                if (encoder_funcs->dpms)
+                                        (*encoder_funcs->dpms) (encoder,
+                                                                drm_helper_choose_encoder_dpms(encoder));
+
+                                crtc_funcs = crtc->helper_private;
+                                if (crtc_funcs->dpms)
+                                        (*crtc_funcs->dpms) (crtc,
+                                                             drm_helper_choose_crtc_dpms(crtc));
+                        }
+                }
         }
         /* disable the unused connectors while restoring the modesetting */
         drm_helper_disable_unused_functions(dev);
diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index ff2f1042cb44..766c46875a20 100644
--- a/drivers/gpu/drm/drm_drv.c
+++ b/drivers/gpu/drm/drm_drv.c
@@ -434,11 +434,11 @@ static int drm_version(struct drm_device *dev, void *data,
  * Looks up the ioctl function in the ::ioctls table, checking for root
  * previleges if so required, and dispatches to the respective function.
  */
-int drm_ioctl(struct inode *inode, struct file *filp,
+long drm_ioctl(struct file *filp,
               unsigned int cmd, unsigned long arg)
 {
         struct drm_file *file_priv = filp->private_data;
-        struct drm_device *dev = file_priv->minor->dev;
+        struct drm_device *dev;
         struct drm_ioctl_desc *ioctl;
         drm_ioctl_t *func;
         unsigned int nr = DRM_IOCTL_NR(cmd);
@@ -446,6 +446,7 @@ int drm_ioctl(struct inode *inode, struct file *filp,
         char stack_kdata[128];
         char *kdata = NULL;
 
+        dev = file_priv->minor->dev;
         atomic_inc(&dev->ioctl_count);
         atomic_inc(&dev->counts[_DRM_STAT_IOCTLS]);
         ++file_priv->ioctl_count;
@@ -501,7 +502,13 @@ int drm_ioctl(struct inode *inode, struct file *filp,
                                 goto err_i1;
                         }
                 }
-                retcode = func(dev, kdata, file_priv);
+                if (ioctl->flags & DRM_UNLOCKED)
+                        retcode = func(dev, kdata, file_priv);
+                else {
+                        lock_kernel();
+                        retcode = func(dev, kdata, file_priv);
+                        unlock_kernel();
+                }
 
                 if (cmd & IOC_OUT) {
                         if (copy_to_user((void __user *)arg, kdata,
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index c39b26f1abed..defcaf108460 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -911,23 +911,27 @@ static int drm_cvt_modes(struct drm_connector *connector,
         struct drm_device *dev = connector->dev;
         struct cvt_timing *cvt;
         const int rates[] = { 60, 85, 75, 60, 50 };
+        const u8 empty[3] = { 0, 0, 0 };
 
         for (i = 0; i < 4; i++) {
-                int width, height;
+                int uninitialized_var(width), height;
                 cvt = &(timing->data.other_data.data.cvt[i]);
 
-                height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 8) + 1) * 2;
-                switch (cvt->code[1] & 0xc0) {
+                if (!memcmp(cvt->code, empty, 3))
+                        continue;
+
+                height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
+                switch (cvt->code[1] & 0x0c) {
                 case 0x00:
                         width = height * 4 / 3;
                         break;
-                case 0x40:
+                case 0x04:
                         width = height * 16 / 9;
                         break;
-                case 0x80:
+                case 0x08:
                         width = height * 16 / 10;
                         break;
-                case 0xc0:
+                case 0x0c:
                         width = height * 15 / 9;
                         break;
                 }
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 1b49fa055f4f..1c2b7d44ec05 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -156,7 +156,7 @@ static bool drm_fb_helper_connector_parse_command_line(struct drm_connector *con
                         force = DRM_FORCE_ON;
                         break;
                 case 'D':
-                        if ((connector->connector_type != DRM_MODE_CONNECTOR_DVII) ||
+                        if ((connector->connector_type != DRM_MODE_CONNECTOR_DVII) &&
                             (connector->connector_type != DRM_MODE_CONNECTOR_HDMIB))
                                 force = DRM_FORCE_ON;
                         else
@@ -606,11 +606,10 @@ int drm_fb_helper_check_var(struct fb_var_screeninfo *var,
                 return -EINVAL;
 
         /* Need to resize the fb object !!! */
-        if (var->xres > fb->width || var->yres > fb->height) {
-                DRM_ERROR("Requested width/height is greater than current fb "
-                           "object %dx%d > %dx%d\n", var->xres, var->yres,
-                           fb->width, fb->height);
-                DRM_ERROR("Need resizing code.\n");
+        if (var->bits_per_pixel > fb->bits_per_pixel || var->xres > fb->width || var->yres > fb->height) {
+                DRM_DEBUG("fb userspace requested width/height/bpp is greater than current fb "
+                          "object %dx%d-%d > %dx%d-%d\n", var->xres, var->yres, var->bits_per_pixel,
+                          fb->width, fb->height, fb->bits_per_pixel);
                 return -EINVAL;
         }
 
diff --git a/drivers/gpu/drm/drm_ioc32.c b/drivers/gpu/drm/drm_ioc32.c
index 282d9fdf9f4e..d61d185cf040 100644
--- a/drivers/gpu/drm/drm_ioc32.c
+++ b/drivers/gpu/drm/drm_ioc32.c
@@ -104,7 +104,7 @@ static int compat_drm_version(struct file *file, unsigned int cmd,
                           &version->desc))
                 return -EFAULT;
 
-        err = drm_ioctl(file->f_path.dentry->d_inode, file,
+        err = drm_ioctl(file,
                         DRM_IOCTL_VERSION, (unsigned long)version);
         if (err)
                 return err;
@@ -145,8 +145,7 @@ static int compat_drm_getunique(struct file *file, unsigned int cmd,
                           &u->unique))
                 return -EFAULT;
 
-        err = drm_ioctl(file->f_path.dentry->d_inode, file,
-                        DRM_IOCTL_GET_UNIQUE, (unsigned long)u);
+        err = drm_ioctl(file, DRM_IOCTL_GET_UNIQUE, (unsigned long)u);
         if (err)
                 return err;
 
@@ -174,8 +173,7 @@ static int compat_drm_setunique(struct file *file, unsigned int cmd,
                           &u->unique))
                 return -EFAULT;
 
-        return drm_ioctl(file->f_path.dentry->d_inode, file,
-                         DRM_IOCTL_SET_UNIQUE, (unsigned long)u);
+        return drm_ioctl(file, DRM_IOCTL_SET_UNIQUE, (unsigned long)u);
 }
 
 typedef struct drm_map32 {
@@ -205,8 +203,7 @@ static int compat_drm_getmap(struct file *file, unsigned int cmd,
         if (__put_user(idx, &map->offset))
                 return -EFAULT;
 
-        err = drm_ioctl(file->f_path.dentry->d_inode, file,
-                        DRM_IOCTL_GET_MAP, (unsigned long)map);
+        err = drm_ioctl(file, DRM_IOCTL_GET_MAP, (unsigned long)map);
         if (err)
                 return err;
 
@@ -246,8 +243,7 @@ static int compat_drm_addmap(struct file *file, unsigned int cmd,
             || __put_user(m32.flags, &map->flags))
                 return -EFAULT;
 
-        err = drm_ioctl(file->f_path.dentry->d_inode, file,
-                        DRM_IOCTL_ADD_MAP, (unsigned long)map);
+        err = drm_ioctl(file, DRM_IOCTL_ADD_MAP, (unsigned long)map);
         if (err)
                 return err;
 
@@ -284,8 +280,7 @@ static int compat_drm_rmmap(struct file *file, unsigned int cmd,
         if (__put_user((void *)(unsigned long)handle, &map->handle))
                 return -EFAULT;
 
-        return drm_ioctl(file->f_path.dentry->d_inode, file,
-                         DRM_IOCTL_RM_MAP, (unsigned long)map);
+        return drm_ioctl(file, DRM_IOCTL_RM_MAP, (unsigned long)map);
 }
 
 typedef struct drm_client32 {
@@ -314,8 +309,7 @@ static int compat_drm_getclient(struct file *file, unsigned int cmd,
         if (__put_user(idx, &client->idx))
                 return -EFAULT;
 
-        err = drm_ioctl(file->f_path.dentry->d_inode, file,
-                        DRM_IOCTL_GET_CLIENT, (unsigned long)client);
+        err = drm_ioctl(file, DRM_IOCTL_GET_CLIENT, (unsigned long)client);
         if (err)
                 return err;
 
@@ -351,8 +345,7 @@ static int compat_drm_getstats(struct file *file, unsigned int cmd,
         if (!access_ok(VERIFY_WRITE, stats, sizeof(*stats)))
                 return -EFAULT;
 
-        err = drm_ioctl(file->f_path.dentry->d_inode, file,
-                        DRM_IOCTL_GET_STATS, (unsigned long)stats);
+        err = drm_ioctl(file, DRM_IOCTL_GET_STATS, (unsigned long)stats);
         if (err)
                 return err;
 
@@ -395,8 +388,7 @@ static int compat_drm_addbufs(struct file *file, unsigned int cmd,
             || __put_user(agp_start, &buf->agp_start))
                 return -EFAULT;
 
-        err = drm_ioctl(file->f_path.dentry->d_inode, file,
-                        DRM_IOCTL_ADD_BUFS, (unsigned long)buf);
+        err = drm_ioctl(file, DRM_IOCTL_ADD_BUFS, (unsigned long)buf);
         if (err)
                 return err;
 
@@ -427,8 +419,7 @@ static int compat_drm_markbufs(struct file *file, unsigned int cmd,
             || __put_user(b32.high_mark, &buf->high_mark))
                 return -EFAULT;
 
-        return drm_ioctl(file->f_path.dentry->d_inode, file,
-                         DRM_IOCTL_MARK_BUFS, (unsigned long)buf);
+        return drm_ioctl(file, DRM_IOCTL_MARK_BUFS, (unsigned long)buf);
 }
 
 typedef struct drm_buf_info32 {
@@ -469,8 +460,7 @@ static int compat_drm_infobufs(struct file *file, unsigned int cmd,
             || __put_user(list, &request->list))
                 return -EFAULT;
 
-        err = drm_ioctl(file->f_path.dentry->d_inode, file,
-                        DRM_IOCTL_INFO_BUFS, (unsigned long)request);
+        err = drm_ioctl(file, DRM_IOCTL_INFO_BUFS, (unsigned long)request);
         if (err)
                 return err;
 
@@ -531,8 +521,7 @@ static int compat_drm_mapbufs(struct file *file, unsigned int cmd,
             || __put_user(list, &request->list))
                 return -EFAULT;
 
-        err = drm_ioctl(file->f_path.dentry->d_inode, file,
-                        DRM_IOCTL_MAP_BUFS, (unsigned long)request);
+        err = drm_ioctl(file, DRM_IOCTL_MAP_BUFS, (unsigned long)request);
         if (err)
                 return err;
 
@@ -578,8 +567,7 @@ static int compat_drm_freebufs(struct file *file, unsigned int cmd,
                           &request->list))
                 return -EFAULT;
 
-        return drm_ioctl(file->f_path.dentry->d_inode, file,
-                         DRM_IOCTL_FREE_BUFS, (unsigned long)request);
+        return drm_ioctl(file, DRM_IOCTL_FREE_BUFS, (unsigned long)request);
 }
 
 typedef struct drm_ctx_priv_map32 {
@@ -605,8 +593,7 @@ static int compat_drm_setsareactx(struct file *file, unsigned int cmd,
                           &request->handle))
                 return -EFAULT;
 
-        return drm_ioctl(file->f_path.dentry->d_inode, file,
-                         DRM_IOCTL_SET_SAREA_CTX, (unsigned long)request);
+        return drm_ioctl(file, DRM_IOCTL_SET_SAREA_CTX, (unsigned long)request);
 }
 
 static int compat_drm_getsareactx(struct file *file, unsigned int cmd,
@@ -628,8 +615,7 @@ static int compat_drm_getsareactx(struct file *file, unsigned int cmd,
         if (__put_user(ctx_id, &request->ctx_id))
                 return -EFAULT;
 
-        err = drm_ioctl(file->f_path.dentry->d_inode, file,
-                        DRM_IOCTL_GET_SAREA_CTX, (unsigned long)request);
+        err = drm_ioctl(file, DRM_IOCTL_GET_SAREA_CTX, (unsigned long)request);
         if (err)
                 return err;
 
@@ -664,8 +650,7 @@ static int compat_drm_resctx(struct file *file, unsigned int cmd,
                           &res->contexts))
                 return -EFAULT;
 
-        err = drm_ioctl(file->f_path.dentry->d_inode, file,
-                        DRM_IOCTL_RES_CTX, (unsigned long)res);
+        err = drm_ioctl(file, DRM_IOCTL_RES_CTX, (unsigned long)res);
         if (err)
                 return err;
 
@@ -718,8 +703,7 @@ static int compat_drm_dma(struct file *file, unsigned int cmd,
                           &d->request_sizes))
                 return -EFAULT;
 
-        err = drm_ioctl(file->f_path.dentry->d_inode, file,
-                        DRM_IOCTL_DMA, (unsigned long)d);
+        err = drm_ioctl(file, DRM_IOCTL_DMA, (unsigned long)d);
         if (err)
                 return err;
 
@@ -751,8 +735,7 @@ static int compat_drm_agp_enable(struct file *file, unsigned int cmd,
         if (put_user(m32.mode, &mode->mode))
                 return -EFAULT;
 
-        return drm_ioctl(file->f_path.dentry->d_inode, file,
-                         DRM_IOCTL_AGP_ENABLE, (unsigned long)mode);
+        return drm_ioctl(file, DRM_IOCTL_AGP_ENABLE, (unsigned long)mode);
 }
 
 typedef struct drm_agp_info32 {
@@ -781,8 +764,7 @@ static int compat_drm_agp_info(struct file *file, unsigned int cmd,
         if (!access_ok(VERIFY_WRITE, info, sizeof(*info)))
                 return -EFAULT;
 
-        err = drm_ioctl(file->f_path.dentry->d_inode, file,
-                        DRM_IOCTL_AGP_INFO, (unsigned long)info);
+        err = drm_ioctl(file, DRM_IOCTL_AGP_INFO, (unsigned long)info);
         if (err)
                 return err;
 
@@ -827,16 +809,14 @@ static int compat_drm_agp_alloc(struct file *file, unsigned int cmd,
             || __put_user(req32.type, &request->type))
                 return -EFAULT;
 
-        err = drm_ioctl(file->f_path.dentry->d_inode, file,
-                        DRM_IOCTL_AGP_ALLOC, (unsigned long)request);
+        err = drm_ioctl(file, DRM_IOCTL_AGP_ALLOC, (unsigned long)request);
         if (err)
                 return err;
 
         if (__get_user(req32.handle, &request->handle)
             || __get_user(req32.physical, &request->physical)
             || copy_to_user(argp, &req32, sizeof(req32))) {
-                drm_ioctl(file->f_path.dentry->d_inode, file,
-                          DRM_IOCTL_AGP_FREE, (unsigned long)request);
+                drm_ioctl(file, DRM_IOCTL_AGP_FREE, (unsigned long)request);
                 return -EFAULT;
         }
 
@@ -856,8 +836,7 @@ static int compat_drm_agp_free(struct file *file, unsigned int cmd,
             || __put_user(handle, &request->handle))
                 return -EFAULT;
 
-        return drm_ioctl(file->f_path.dentry->d_inode, file,
-                         DRM_IOCTL_AGP_FREE, (unsigned long)request);
+        return drm_ioctl(file, DRM_IOCTL_AGP_FREE, (unsigned long)request);
 }
 
 typedef struct drm_agp_binding32 {
@@ -881,8 +860,7 @@ static int compat_drm_agp_bind(struct file *file, unsigned int cmd,
             || __put_user(req32.offset, &request->offset))
                 return -EFAULT;
 
-        return drm_ioctl(file->f_path.dentry->d_inode, file,
-                         DRM_IOCTL_AGP_BIND, (unsigned long)request);
+        return drm_ioctl(file, DRM_IOCTL_AGP_BIND, (unsigned long)request);
 }
 
 static int compat_drm_agp_unbind(struct file *file, unsigned int cmd,
@@ -898,8 +876,7 @@ static int compat_drm_agp_unbind(struct file *file, unsigned int cmd,
             || __put_user(handle, &request->handle))
                 return -EFAULT;
 
-        return drm_ioctl(file->f_path.dentry->d_inode, file,
-                         DRM_IOCTL_AGP_UNBIND, (unsigned long)request);
+        return drm_ioctl(file, DRM_IOCTL_AGP_UNBIND, (unsigned long)request);
 }
 #endif                          /* __OS_HAS_AGP */
 
@@ -923,8 +900,7 @@ static int compat_drm_sg_alloc(struct file *file, unsigned int cmd,
             || __put_user(x, &request->size))
                 return -EFAULT;
 
-        err = drm_ioctl(file->f_path.dentry->d_inode, file,
-                        DRM_IOCTL_SG_ALLOC, (unsigned long)request);
+        err = drm_ioctl(file, DRM_IOCTL_SG_ALLOC, (unsigned long)request);
         if (err)
                 return err;
 
@@ -950,8 +926,7 @@ static int compat_drm_sg_free(struct file *file, unsigned int cmd,
             || __put_user(x << PAGE_SHIFT, &request->handle))
                 return -EFAULT;
 
-        return drm_ioctl(file->f_path.dentry->d_inode, file,
-                         DRM_IOCTL_SG_FREE, (unsigned long)request);
+        return drm_ioctl(file, DRM_IOCTL_SG_FREE, (unsigned long)request);
 }
 
 #if defined(CONFIG_X86) || defined(CONFIG_IA64)
@@ -981,8 +956,7 @@ static int compat_drm_update_draw(struct file *file, unsigned int cmd,
             __put_user(update32.data, &request->data))
                 return -EFAULT;
 
-        err = drm_ioctl(file->f_path.dentry->d_inode, file,
-                        DRM_IOCTL_UPDATE_DRAW, (unsigned long)request);
+        err = drm_ioctl(file, DRM_IOCTL_UPDATE_DRAW, (unsigned long)request);
         return err;
 }
 #endif
@@ -1023,8 +997,7 @@ static int compat_drm_wait_vblank(struct file *file, unsigned int cmd,
             || __put_user(req32.request.signal, &request->request.signal))
                 return -EFAULT;
 
-        err = drm_ioctl(file->f_path.dentry->d_inode, file,
-                        DRM_IOCTL_WAIT_VBLANK, (unsigned long)request);
+        err = drm_ioctl(file, DRM_IOCTL_WAIT_VBLANK, (unsigned long)request);
         if (err)
                 return err;
 
@@ -1094,16 +1067,14 @@ long drm_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
          * than always failing.
          */
         if (nr >= ARRAY_SIZE(drm_compat_ioctls))
-                return drm_ioctl(filp->f_dentry->d_inode, filp, cmd, arg);
+                return drm_ioctl(filp, cmd, arg);
 
         fn = drm_compat_ioctls[nr];
 
-        lock_kernel();          /* XXX for now */
         if (fn != NULL)
                 ret = (*fn) (filp, cmd, arg);
         else
-                ret = drm_ioctl(filp->f_path.dentry->d_inode, filp, cmd, arg);
-        unlock_kernel();
+                ret = drm_ioctl(filp, cmd, arg);
 
         return ret;
 }
diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c
index 7998ee66b317..b98384dbd9a7 100644
--- a/drivers/gpu/drm/drm_irq.c
+++ b/drivers/gpu/drm/drm_irq.c
@@ -115,6 +115,7 @@ void drm_vblank_cleanup(struct drm_device *dev)
 
         dev->num_crtcs = 0;
 }
+EXPORT_SYMBOL(drm_vblank_cleanup);
 
 int drm_vblank_init(struct drm_device *dev, int num_crtcs)
 {
@@ -163,7 +164,6 @@ int drm_vblank_init(struct drm_device *dev, int num_crtcs)
         }
 
         dev->vblank_disable_allowed = 0;
-
         return 0;
 
 err:
@@ -493,6 +493,9 @@ EXPORT_SYMBOL(drm_vblank_off);
  */
 void drm_vblank_pre_modeset(struct drm_device *dev, int crtc)
 {
+        /* vblank is not initialized (IRQ not installed ?) */
+        if (!dev->num_crtcs)
+                return;
         /*
          * To avoid all the problems that might happen if interrupts
          * were enabled/disabled around or between these calls, we just
diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c
index d7d7eac3ddd2..cdec32977129 100644
--- a/drivers/gpu/drm/drm_mm.c
+++ b/drivers/gpu/drm/drm_mm.c
@@ -358,7 +358,7 @@ struct drm_mm_node *drm_mm_search_free(const struct drm_mm *mm,
                 if (entry->size >= size + wasted) {
                         if (!best_match)
                                 return entry;
-                        if (size < best_size) {
+                        if (entry->size < best_size) {
                                 best = entry;
                                 best_size = entry->size;
                         }
@@ -408,7 +408,7 @@ struct drm_mm_node *drm_mm_search_free_in_range(const struct drm_mm *mm,
                 if (entry->size >= size + wasted) {
                         if (!best_match)
                                 return entry;
-                        if (size < best_size) {
+                        if (entry->size < best_size) {
                                 best = entry;
                                 best_size = entry->size;
                         }
diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index 6d81a02463a3..76d63394c776 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -1,9 +1,4 @@
 /*
- * The list_sort function is (presumably) licensed under the GPL (see the
- * top level "COPYING" file for details).
- *
- * The remainder of this file is:
- *
  * Copyright © 1997-2003 by The XFree86 Project, Inc.
  * Copyright © 2007 Dave Airlie
  * Copyright © 2007-2008 Intel Corporation
@@ -36,6 +31,7 @@
  */
 
 #include <linux/list.h>
+#include <linux/list_sort.h>
 #include "drmP.h"
 #include "drm.h"
 #include "drm_crtc.h"
@@ -855,6 +851,7 @@ EXPORT_SYMBOL(drm_mode_prune_invalid);
 
 /**
  * drm_mode_compare - compare modes for favorability
+ * @priv: unused
  * @lh_a: list_head for first mode
  * @lh_b: list_head for second mode
  *
@@ -868,7 +865,7 @@ EXPORT_SYMBOL(drm_mode_prune_invalid);
  * Negative if @lh_a is better than @lh_b, zero if they're equivalent, or
  * positive if @lh_b is better than @lh_a.
  */
-static int drm_mode_compare(struct list_head *lh_a, struct list_head *lh_b)
+static int drm_mode_compare(void *priv, struct list_head *lh_a, struct list_head *lh_b)
 {
         struct drm_display_mode *a = list_entry(lh_a, struct drm_display_mode, head);
         struct drm_display_mode *b = list_entry(lh_b, struct drm_display_mode, head);
@@ -885,85 +882,6 @@ static int drm_mode_compare(struct list_head *lh_a, struct list_head *lh_b)
         return diff;
 }
 
-/* FIXME: what we don't have a list sort function? */
-/* list sort from Mark J Roberts (mjr@znex.org) */
-void list_sort(struct list_head *head,
-               int (*cmp)(struct list_head *a, struct list_head *b))
-{
-        struct list_head *p, *q, *e, *list, *tail, *oldhead;
-        int insize, nmerges, psize, qsize, i;
-
-        list = head->next;
-        list_del(head);
-        insize = 1;
-        for (;;) {
-                p = oldhead = list;
-                list = tail = NULL;
-                nmerges = 0;
-
-                while (p) {
-                        nmerges++;
-                        q = p;
-                        psize = 0;
-                        for (i = 0; i < insize; i++) {
-                                psize++;
-                                q = q->next == oldhead ? NULL : q->next;
-                                if (!q)
-                                        break;
-                        }
-
-                        qsize = insize;
-                        while (psize > 0 || (qsize > 0 && q)) {
-                                if (!psize) {
-                                        e = q;
-                                        q = q->next;
-                                        qsize--;
-                                        if (q == oldhead)
-                                                q = NULL;
-                                } else if (!qsize || !q) {
-                                        e = p;
-                                        p = p->next;
-                                        psize--;
-                                        if (p == oldhead)
-                                                p = NULL;
-                                } else if (cmp(p, q) <= 0) {
-                                        e = p;
-                                        p = p->next;
-                                        psize--;
-                                        if (p == oldhead)
-                                                p = NULL;
-                                } else {
-                                        e = q;
-                                        q = q->next;
-                                        qsize--;
-                                        if (q == oldhead)
-                                                q = NULL;
-                                }
-                                if (tail)
-                                        tail->next = e;
-                                else
-                                        list = e;
-                                e->prev = tail;
-                                tail = e;
-                        }
-                        p = q;
-                }
-
-                tail->next = list;
-                list->prev = tail;
-
-                if (nmerges <= 1)
-                        break;
-
-                insize *= 2;
-        }
-
-        head->next = list;
-        head->prev = list->prev;
-        list->prev->next = head;
-        list->prev = head;
-}
-
 /**
  * drm_mode_sort - sort mode list
  * @mode_list: list to sort
@@ -975,7 +893,7 @@ void list_sort(struct list_head *head,
  */
 void drm_mode_sort(struct list_head *mode_list)
 {
-        list_sort(mode_list, drm_mode_compare);
+        list_sort(NULL, mode_list, drm_mode_compare);
 }
 EXPORT_SYMBOL(drm_mode_sort);
 
diff --git a/drivers/gpu/drm/drm_pci.c b/drivers/gpu/drm/drm_pci.c
index 577094fb1995..e68ebf92fa2a 100644
--- a/drivers/gpu/drm/drm_pci.c
+++ b/drivers/gpu/drm/drm_pci.c
@@ -47,8 +47,7 @@
 /**
  * \brief Allocate a PCI consistent memory block, for DMA.
  */
-drm_dma_handle_t *drm_pci_alloc(struct drm_device * dev, size_t size, size_t align,
-                                dma_addr_t maxaddr)
+drm_dma_handle_t *drm_pci_alloc(struct drm_device * dev, size_t size, size_t align)
 {
         drm_dma_handle_t *dmah;
 #if 1
@@ -63,11 +62,6 @@ drm_dma_handle_t *drm_pci_alloc(struct drm_device * dev, size_t size, size_t ali
         if (align > size)
                 return NULL;
 
-        if (pci_set_dma_mask(dev->pdev, maxaddr) != 0) {
-                DRM_ERROR("Setting pci dma mask failed\n");
-                return NULL;
-        }
-
         dmah = kmalloc(sizeof(drm_dma_handle_t), GFP_KERNEL);
         if (!dmah)
                 return NULL;
diff --git a/drivers/gpu/drm/i2c/ch7006_drv.c b/drivers/gpu/drm/i2c/ch7006_drv.c
index 9422a74c8b54..81681a07a806 100644
--- a/drivers/gpu/drm/i2c/ch7006_drv.c
+++ b/drivers/gpu/drm/i2c/ch7006_drv.c
@@ -408,6 +408,11 @@ static int ch7006_probe(struct i2c_client *client, const struct i2c_device_id *i
 
         ch7006_info(client, "Detected version ID: %x\n", val);
 
+        /* I don't know what this is for, but otherwise I get no
+         * signal.
+         */
+        ch7006_write(client, 0x3d, 0x0);
+
         return 0;
 
 fail:
diff --git a/drivers/gpu/drm/i2c/ch7006_mode.c b/drivers/gpu/drm/i2c/ch7006_mode.c
index 87f5445092e8..e447dfb63890 100644
--- a/drivers/gpu/drm/i2c/ch7006_mode.c
+++ b/drivers/gpu/drm/i2c/ch7006_mode.c
@@ -427,11 +427,6 @@ void ch7006_state_load(struct i2c_client *client,
         ch7006_load_reg(client, state, CH7006_SUBC_INC7);
         ch7006_load_reg(client, state, CH7006_PLL_CONTROL);
         ch7006_load_reg(client, state, CH7006_CALC_SUBC_INC0);
-
-        /* I don't know what this is for, but otherwise I get no
-         * signal.
-         */
-        ch7006_write(client, 0x3d, 0x0);
 }
 
 void ch7006_state_save(struct i2c_client *client,
diff --git a/drivers/gpu/drm/i810/i810_dma.c b/drivers/gpu/drm/i810/i810_dma.c
index 7d1d88cdf2dc..de32d22a8c39 100644
--- a/drivers/gpu/drm/i810/i810_dma.c
+++ b/drivers/gpu/drm/i810/i810_dma.c
@@ -115,7 +115,7 @@ static int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
 static const struct file_operations i810_buffer_fops = {
         .open = drm_open,
         .release = drm_release,
-        .ioctl = drm_ioctl,
+        .unlocked_ioctl = drm_ioctl,
         .mmap = i810_mmap_buffers,
         .fasync = drm_fasync,
 };
diff --git a/drivers/gpu/drm/i810/i810_drv.c b/drivers/gpu/drm/i810/i810_drv.c
index fabb9a817966..c1e02752e023 100644
--- a/drivers/gpu/drm/i810/i810_drv.c
+++ b/drivers/gpu/drm/i810/i810_drv.c
@@ -59,7 +59,7 @@ static struct drm_driver driver = {
                  .owner = THIS_MODULE,
                  .open = drm_open,
                  .release = drm_release,
-                 .ioctl = drm_ioctl,
+                 .unlocked_ioctl = drm_ioctl,
                  .mmap = drm_mmap,
                  .poll = drm_poll,
                  .fasync = drm_fasync,
diff --git a/drivers/gpu/drm/i830/i830_dma.c b/drivers/gpu/drm/i830/i830_dma.c
index 877bf6cb14a4..06bd732e6463 100644
--- a/drivers/gpu/drm/i830/i830_dma.c
+++ b/drivers/gpu/drm/i830/i830_dma.c
@@ -117,7 +117,7 @@ static int i830_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
 static const struct file_operations i830_buffer_fops = {
         .open = drm_open,
         .release = drm_release,
-        .ioctl = drm_ioctl,
+        .unlocked_ioctl = drm_ioctl,
         .mmap = i830_mmap_buffers,
         .fasync = drm_fasync,
 };
diff --git a/drivers/gpu/drm/i830/i830_drv.c b/drivers/gpu/drm/i830/i830_drv.c
index 389597e4a623..44f990bed8f4 100644
--- a/drivers/gpu/drm/i830/i830_drv.c
+++ b/drivers/gpu/drm/i830/i830_drv.c
@@ -70,7 +70,7 @@ static struct drm_driver driver = {
                  .owner = THIS_MODULE,
                  .open = drm_open,
                  .release = drm_release,
-                 .ioctl = drm_ioctl,
+                 .unlocked_ioctl = drm_ioctl,
                  .mmap = drm_mmap,
                  .poll = drm_poll,
                  .fasync = drm_fasync,
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 18476bf0b580..9c9998c4dceb 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -272,7 +272,7 @@ static void i915_dump_pages(struct seq_file *m, struct page **pages, int page_co
                 mem = kmap_atomic(pages[page], KM_USER0);
                 for (i = 0; i < PAGE_SIZE; i += 4)
                         seq_printf(m, "%08x :  %08x\n", i, mem[i / 4]);
-                kunmap_atomic(pages[page], KM_USER0);
+                kunmap_atomic(mem, KM_USER0);
         }
 }
 
@@ -386,34 +386,6 @@ out:
         return 0;
 }
 
-static int i915_registers_info(struct seq_file *m, void *data) {
-        struct drm_info_node *node = (struct drm_info_node *) m->private;
-        struct drm_device *dev = node->minor->dev;
-        drm_i915_private_t *dev_priv = dev->dev_private;
-        uint32_t reg;
-
-#define DUMP_RANGE(start, end) \
-        for (reg=start; reg < end; reg += 4) \
-        seq_printf(m, "%08x\t%08x\n", reg, I915_READ(reg));
-
-        DUMP_RANGE(0x00000, 0x00fff);   /* VGA registers */
-        DUMP_RANGE(0x02000, 0x02fff);   /* instruction, memory, interrupt control registers */
-        DUMP_RANGE(0x03000, 0x031ff);   /* FENCE and PPGTT control registers */
-        DUMP_RANGE(0x03200, 0x03fff);   /* frame buffer compression registers */
-        DUMP_RANGE(0x05000, 0x05fff);   /* I/O control registers */
-        DUMP_RANGE(0x06000, 0x06fff);   /* clock control registers */
-        DUMP_RANGE(0x07000, 0x07fff);   /* 3D internal debug registers */
-        DUMP_RANGE(0x07400, 0x088ff);   /* GPE debug registers */
-        DUMP_RANGE(0x0a000, 0x0afff);   /* display palette registers */
-        DUMP_RANGE(0x10000, 0x13fff);   /* MMIO MCHBAR */
-        DUMP_RANGE(0x30000, 0x3ffff);   /* overlay registers */
-        DUMP_RANGE(0x60000, 0x6ffff);   /* display engine pipeline registers */
-        DUMP_RANGE(0x70000, 0x72fff);   /* display and cursor registers */
-        DUMP_RANGE(0x73000, 0x73fff);   /* performance counters */
-
-        return 0;
-}
-
 static int
 i915_wedged_open(struct inode *inode,
                  struct file *filp)
@@ -519,7 +491,6 @@ static int i915_wedged_create(struct dentry *root, struct drm_minor *minor)
 }
 
 static struct drm_info_list i915_debugfs_list[] = {
-        {"i915_regs", i915_registers_info, 0},
         {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
         {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},
         {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 701bfeac7f57..bbe47812e4b6 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -123,7 +123,7 @@ static int i915_init_phys_hws(struct drm_device *dev)
         drm_i915_private_t *dev_priv = dev->dev_private;
         /* Program Hardware Status Page */
         dev_priv->status_page_dmah =
-                drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
+                drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
 
         if (!dev_priv->status_page_dmah) {
                 DRM_ERROR("Can not allocate hardware status page\n");
@@ -813,9 +813,13 @@ static int i915_getparam(struct drm_device *dev, void *data,
         case I915_PARAM_HAS_PAGEFLIPPING:
                 value = 1;
                 break;
+        case I915_PARAM_HAS_EXECBUF2:
+                /* depends on GEM */
+                value = dev_priv->has_gem;
+                break;
         default:
                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
-                                        param->param);
+                                 param->param);
                 return -EINVAL;
         }
 
@@ -1117,7 +1121,8 @@ static void i915_setup_compression(struct drm_device *dev, int size)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
         struct drm_mm_node *compressed_fb, *compressed_llb;
-        unsigned long cfb_base, ll_base;
+        unsigned long cfb_base;
+        unsigned long ll_base = 0;
 
         /* Leave 1M for line length buffer & misc. */
         compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0);
@@ -1200,14 +1205,6 @@ static int i915_load_modeset_init(struct drm_device *dev,
         dev->mode_config.fb_base = drm_get_resource_start(dev, fb_bar) &
                 0xff000000;
 
-        if (IS_MOBILE(dev) || IS_I9XX(dev))
-                dev_priv->cursor_needs_physical = true;
-        else
-                dev_priv->cursor_needs_physical = false;
-
-        if (IS_I965G(dev) || IS_G33(dev))
-                dev_priv->cursor_needs_physical = false;
-
         /* Basic memrange allocator for stolen space (aka vram) */
         drm_mm_init(&dev_priv->vram, 0, prealloc_size);
         DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024));
@@ -1257,6 +1254,8 @@ static int i915_load_modeset_init(struct drm_device *dev,
         if (ret)
                 goto destroy_ringbuffer;
 
+        intel_modeset_init(dev);
+
         ret = drm_irq_install(dev);
         if (ret)
                 goto destroy_ringbuffer;
@@ -1271,8 +1270,6 @@ static int i915_load_modeset_init(struct drm_device *dev,
 
         I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
 
-        intel_modeset_init(dev);
-
         drm_helper_initial_config(dev);
 
         return 0;
@@ -1360,7 +1357,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
         resource_size_t base, size;
-        int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1;
+        int ret = 0, mmio_bar;
         uint32_t agp_size, prealloc_size, prealloc_start;
 
         /* i915 has 4 more counters */
@@ -1376,8 +1373,10 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 
         dev->dev_private = (void *)dev_priv;
         dev_priv->dev = dev;
+        dev_priv->info = (struct intel_device_info *) flags;
 
         /* Add register map (needed for suspend/resume) */
+        mmio_bar = IS_I9XX(dev) ? 0 : 1;
         base = drm_get_resource_start(dev, mmio_bar);
         size = drm_get_resource_len(dev, mmio_bar);
 
@@ -1652,6 +1651,7 @@ struct drm_ioctl_desc i915_ioctls[] = {
         DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
         DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
+        DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH),
         DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
         DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
         DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH),
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 2fa217862058..be631cc3e4dc 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -33,7 +33,6 @@
 #include "i915_drm.h"
 #include "i915_drv.h"
 
-#include "drm_pciids.h"
 #include <linux/console.h>
 #include "drm_crtc_helper.h"
 
@@ -48,8 +47,124 @@ module_param_named(powersave, i915_powersave, int, 0400);
 
 static struct drm_driver driver;
 
-static struct pci_device_id pciidlist[] = {
-        i915_PCI_IDS
+#define INTEL_VGA_DEVICE(id, info) {            \
+        .class = PCI_CLASS_DISPLAY_VGA << 8,    \
+        .class_mask = 0xffff00,                 \
+        .vendor = 0x8086,                       \
+        .device = id,                           \
+        .subvendor = PCI_ANY_ID,                \
+        .subdevice = PCI_ANY_ID,                \
+        .driver_data = (unsigned long) info }
+
+const static struct intel_device_info intel_i830_info = {
+        .is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1,
+};
+
+const static struct intel_device_info intel_845g_info = {
+        .is_i8xx = 1,
+};
+
+const static struct intel_device_info intel_i85x_info = {
+        .is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1,
+};
+
+const static struct intel_device_info intel_i865g_info = {
+        .is_i8xx = 1,
+};
+
+const static struct intel_device_info intel_i915g_info = {
+        .is_i915g = 1, .is_i9xx = 1, .cursor_needs_physical = 1,
+};
+const static struct intel_device_info intel_i915gm_info = {
+        .is_i9xx = 1,  .is_mobile = 1, .has_fbc = 1,
+        .cursor_needs_physical = 1,
+};
+const static struct intel_device_info intel_i945g_info = {
+        .is_i9xx = 1, .has_hotplug = 1, .cursor_needs_physical = 1,
+};
+const static struct intel_device_info intel_i945gm_info = {
+        .is_i945gm = 1, .is_i9xx = 1, .is_mobile = 1, .has_fbc = 1,
+        .has_hotplug = 1, .cursor_needs_physical = 1,
+};
+
+const static struct intel_device_info intel_i965g_info = {
+        .is_i965g = 1, .is_i9xx = 1, .has_hotplug = 1,
+};
+
+const static struct intel_device_info intel_i965gm_info = {
+        .is_i965g = 1, .is_mobile = 1, .is_i965gm = 1, .is_i9xx = 1,
+        .is_mobile = 1, .has_fbc = 1, .has_rc6 = 1,
+        .has_hotplug = 1,
+};
+
+const static struct intel_device_info intel_g33_info = {
+        .is_g33 = 1, .is_i9xx = 1, .need_gfx_hws = 1,
+        .has_hotplug = 1,
+};
+
+const static struct intel_device_info intel_g45_info = {
+        .is_i965g = 1, .is_g4x = 1, .is_i9xx = 1, .need_gfx_hws = 1,
+        .has_pipe_cxsr = 1,
+        .has_hotplug = 1,
+};
+
+const static struct intel_device_info intel_gm45_info = {
+        .is_i965g = 1, .is_mobile = 1, .is_g4x = 1, .is_i9xx = 1,
+        .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1,
+        .has_pipe_cxsr = 1,
+        .has_hotplug = 1,
+};
+
+const static struct intel_device_info intel_pineview_info = {
+        .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .is_i9xx = 1,
+        .has_pipe_cxsr = 1,
+        .has_hotplug = 1,
+};
+
+const static struct intel_device_info intel_ironlake_d_info = {
+        .is_ironlake = 1, .is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1,
+        .has_pipe_cxsr = 1,
+        .has_hotplug = 1,
+};
+
+const static struct intel_device_info intel_ironlake_m_info = {
+        .is_ironlake = 1, .is_mobile = 1, .is_i965g = 1, .is_i9xx = 1,
+        .need_gfx_hws = 1, .has_rc6 = 1,
+        .has_hotplug = 1,
+};
+
+const static struct pci_device_id pciidlist[] = {
+        INTEL_VGA_DEVICE(0x3577, &intel_i830_info),
+        INTEL_VGA_DEVICE(0x2562, &intel_845g_info),
+        INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),
+        INTEL_VGA_DEVICE(0x35e8, &intel_i85x_info),
+        INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),
+        INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),
+        INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),
+        INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),
+        INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),
+        INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),
+        INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),
+        INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),
+        INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),
+        INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),
+        INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),
+        INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),
+        INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),
+        INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),
+        INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),
+        INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),
+        INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),
+        INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),
+        INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),
+        INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),
+        INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),
+        INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),
+        INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
+        INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
+        INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
+        INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
+        {0, 0, 0}
 };
 
 #if defined(CONFIG_DRM_I915_KMS)
@@ -284,6 +399,52 @@ i915_pci_resume(struct pci_dev *pdev)
         return i915_resume(dev);
 }
 
+static int
+i915_pm_suspend(struct device *dev)
+{
+        return i915_pci_suspend(to_pci_dev(dev), PMSG_SUSPEND);
+}
+
+static int
+i915_pm_resume(struct device *dev)
+{
+        return i915_pci_resume(to_pci_dev(dev));
+}
+
+static int
+i915_pm_freeze(struct device *dev)
+{
+        return i915_pci_suspend(to_pci_dev(dev), PMSG_FREEZE);
+}
+
+static int
+i915_pm_thaw(struct device *dev)
+{
+        /* thaw during hibernate, do nothing! */
+        return 0;
+}
+
+static int
+i915_pm_poweroff(struct device *dev)
+{
+        return i915_pci_suspend(to_pci_dev(dev), PMSG_HIBERNATE);
+}
+
+static int
+i915_pm_restore(struct device *dev)
+{
+        return i915_pci_resume(to_pci_dev(dev));
+}
+
+const struct dev_pm_ops i915_pm_ops = {
+     .suspend = i915_pm_suspend,
+     .resume = i915_pm_resume,
+     .freeze = i915_pm_freeze,
+     .thaw = i915_pm_thaw,
+     .poweroff = i915_pm_poweroff,
+     .restore = i915_pm_restore,
+};
+
 static struct vm_operations_struct i915_gem_vm_ops = {
         .fault = i915_gem_fault,
         .open = drm_gem_vm_open,
@@ -329,7 +490,7 @@ static struct drm_driver driver = {
                  .owner = THIS_MODULE,
                  .open = drm_open,
                  .release = drm_release,
-                 .ioctl = drm_ioctl,
+                 .unlocked_ioctl = drm_ioctl,
                  .mmap = drm_gem_mmap,
                  .poll = drm_poll,
                  .fasync = drm_fasync,
@@ -344,10 +505,7 @@ static struct drm_driver driver = {
                  .id_table = pciidlist,
                  .probe = i915_pci_probe,
                  .remove = i915_pci_remove,
-#ifdef CONFIG_PM
-                 .resume = i915_pci_resume,
-                 .suspend = i915_pci_suspend,
-#endif
+                 .driver.pm = &i915_pm_ops,
         },
 
         .name = DRIVER_NAME,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fbecac72f5bb..29dd67626967 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -172,9 +172,31 @@ struct drm_i915_display_funcs {
 
 struct intel_overlay;
 
+struct intel_device_info {
+        u8 is_mobile : 1;
+        u8 is_i8xx : 1;
+        u8 is_i915g : 1;
+        u8 is_i9xx : 1;
+        u8 is_i945gm : 1;
+        u8 is_i965g : 1;
+        u8 is_i965gm : 1;
+        u8 is_g33 : 1;
+        u8 need_gfx_hws : 1;
+        u8 is_g4x : 1;
+        u8 is_pineview : 1;
+        u8 is_ironlake : 1;
+        u8 has_fbc : 1;
+        u8 has_rc6 : 1;
+        u8 has_pipe_cxsr : 1;
+        u8 has_hotplug : 1;
+        u8 cursor_needs_physical : 1;
+};
+
 typedef struct drm_i915_private {
         struct drm_device *dev;
 
+        const struct intel_device_info *info;
+
         int has_gem;
 
         void __iomem *regs;
@@ -232,8 +254,6 @@ typedef struct drm_i915_private {
         int hangcheck_count;
         uint32_t last_acthd;
 
-        bool cursor_needs_physical;
-
         struct drm_mm vram;
 
         unsigned long cfb_size;
@@ -287,8 +307,6 @@ typedef struct drm_i915_private {
         u32 saveDSPACNTR;
         u32 saveDSPBCNTR;
         u32 saveDSPARB;
-        u32 saveRENDERSTANDBY;
-        u32 savePWRCTXA;
         u32 saveHWS;
         u32 savePIPEACONF;
         u32 savePIPEBCONF;
@@ -561,6 +579,7 @@ typedef struct drm_i915_private {
         u16 orig_clock;
         int child_dev_num;
         struct child_device_config *child_dev;
+        struct drm_connector *int_lvds_connector;
 } drm_i915_private_t;
 
 /** driver private structure attached to each drm_gem_object */
@@ -794,6 +813,8 @@ int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
                              struct drm_file *file_priv);
 int i915_gem_execbuffer(struct drm_device *dev, void *data,
                         struct drm_file *file_priv);
+int i915_gem_execbuffer2(struct drm_device *dev, void *data,
+                         struct drm_file *file_priv);
 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
                        struct drm_file *file_priv);
 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
@@ -860,6 +881,9 @@ void i915_gem_shrinker_exit(void);
 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
+bool i915_tiling_ok(struct drm_device *dev, int stride, int size,
+                    int tiling_mode);
+bool i915_obj_fenceable(struct drm_device *dev, struct drm_gem_object *obj);
 
 /* i915_gem_debug.c */
 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
@@ -982,67 +1006,33 @@ extern void g4x_disable_fbc(struct drm_device *dev);
 extern int i915_wrap_ring(struct drm_device * dev);
 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
 
-#define IS_I830(dev) ((dev)->pci_device == 0x3577)
-#define IS_845G(dev) ((dev)->pci_device == 0x2562)
-#define IS_I85X(dev) ((dev)->pci_device == 0x3582)
-#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
-#define IS_I8XX(dev) (IS_I830(dev) || IS_845G(dev) || IS_I85X(dev) || IS_I865G(dev))
-
-#define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
-#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
-#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
-#define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
-                        (dev)->pci_device == 0x27AE)
-#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
-                       (dev)->pci_device == 0x2982 || \
-                       (dev)->pci_device == 0x2992 || \
-                       (dev)->pci_device == 0x29A2 || \
-                       (dev)->pci_device == 0x2A02 || \
-                       (dev)->pci_device == 0x2A12 || \
-                       (dev)->pci_device == 0x2A42 || \
-                       (dev)->pci_device == 0x2E02 || \
-                       (dev)->pci_device == 0x2E12 || \
-                       (dev)->pci_device == 0x2E22 || \
-                       (dev)->pci_device == 0x2E32 || \
-                       (dev)->pci_device == 0x2E42 || \
-                       (dev)->pci_device == 0x0042 || \
-                       (dev)->pci_device == 0x0046)
-
-#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \
-                        (dev)->pci_device == 0x2A12)
-
-#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
-
-#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
-                     (dev)->pci_device == 0x2E12 || \
-                     (dev)->pci_device == 0x2E22 || \
-                     (dev)->pci_device == 0x2E32 || \
-                     (dev)->pci_device == 0x2E42 || \
-                     IS_GM45(dev))
-
-#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
-#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
-#define IS_PINEVIEW(dev) (IS_PINEVIEW_G(dev) || IS_PINEVIEW_M(dev))
-
-#define IS_G33(dev)    ((dev)->pci_device == 0x29C2 ||  \
-                        (dev)->pci_device == 0x29B2 ||  \
-                        (dev)->pci_device == 0x29D2 ||  \
-                        (IS_PINEVIEW(dev)))
-
+#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
+
+#define IS_I830(dev)            ((dev)->pci_device == 0x3577)
+#define IS_845G(dev)            ((dev)->pci_device == 0x2562)
+#define IS_I85X(dev)            ((dev)->pci_device == 0x3582)
+#define IS_I865G(dev)           ((dev)->pci_device == 0x2572)
+#define IS_I8XX(dev)            (INTEL_INFO(dev)->is_i8xx)
+#define IS_I915G(dev)           (INTEL_INFO(dev)->is_i915g)
+#define IS_I915GM(dev)          ((dev)->pci_device == 0x2592)
+#define IS_I945G(dev)           ((dev)->pci_device == 0x2772)
+#define IS_I945GM(dev)          (INTEL_INFO(dev)->is_i945gm)
+#define IS_I965G(dev)           (INTEL_INFO(dev)->is_i965g)
+#define IS_I965GM(dev)          (INTEL_INFO(dev)->is_i965gm)
+#define IS_GM45(dev)            ((dev)->pci_device == 0x2A42)
+#define IS_G4X(dev)             (INTEL_INFO(dev)->is_g4x)
+#define IS_PINEVIEW_G(dev)      ((dev)->pci_device == 0xa001)
+#define IS_PINEVIEW_M(dev)      ((dev)->pci_device == 0xa011)
+#define IS_PINEVIEW(dev)        (INTEL_INFO(dev)->is_pineview)
+#define IS_G33(dev)             (INTEL_INFO(dev)->is_g33)
 #define IS_IRONLAKE_D(dev)      ((dev)->pci_device == 0x0042)
 #define IS_IRONLAKE_M(dev)      ((dev)->pci_device == 0x0046)
-#define IS_IRONLAKE(dev)        (IS_IRONLAKE_D(dev) || IS_IRONLAKE_M(dev))
-
-#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
-                      IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \
-                      IS_IRONLAKE(dev))
+#define IS_IRONLAKE(dev)        (INTEL_INFO(dev)->is_ironlake)
+#define IS_I9XX(dev)            (INTEL_INFO(dev)->is_i9xx)
+#define IS_MOBILE(dev)          (INTEL_INFO(dev)->is_mobile)
 
-#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
-                        IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
-                        IS_PINEVIEW(dev) || IS_IRONLAKE_M(dev))
+#define I915_NEED_GFX_HWS(dev)  (INTEL_INFO(dev)->need_gfx_hws)
 
-#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev) || \
-                                IS_IRONLAKE(dev))
 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
  * rows, which changed the alignment requirements and fence programming.
  */
@@ -1054,17 +1044,14 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
 #define SUPPORTS_EDP(dev)               (IS_IRONLAKE_M(dev))
 #define SUPPORTS_TV(dev)                (IS_I9XX(dev) && IS_MOBILE(dev) && \
                                         !IS_IRONLAKE(dev) && !IS_PINEVIEW(dev))
-#define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev) || IS_I965G(dev))
+#define I915_HAS_HOTPLUG(dev)            (INTEL_INFO(dev)->has_hotplug)
 /* dsparb controlled by hw only */
 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
 
 #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev))
-#define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
-#define I915_HAS_FBC(dev) (IS_MOBILE(dev) && \
-                           (IS_I9XX(dev) || IS_GM45(dev)) && \
-                           !IS_PINEVIEW(dev) && \
-                           !IS_IRONLAKE(dev))
-#define I915_HAS_RC6(dev) (IS_I965GM(dev) || IS_GM45(dev) || IS_IRONLAKE_M(dev))
+#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
+#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
+#define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
 
 #define PRIMARY_RINGBUFFER_SIZE         (128*1024)
 
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 8c463cf2050a..2748609f05b3 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2021,9 +2021,6 @@ i915_gem_object_unbind(struct drm_gem_object *obj)
         /* blow away mappings if mapped through GTT */
         i915_gem_release_mmap(obj);
 
-        if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
-                i915_gem_clear_fence_reg(obj);
-
         /* Move the object to the CPU domain to ensure that
          * any possible CPU writes while it's not in the GTT
          * are flushed when we go to remap it. This will
@@ -2039,6 +2036,10 @@ i915_gem_object_unbind(struct drm_gem_object *obj)
 
         BUG_ON(obj_priv->active);
 
+        /* release the fence reg _after_ flushing */
+        if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
+                i915_gem_clear_fence_reg(obj);
+
         if (obj_priv->agp_mem != NULL) {
                 drm_unbind_agp(obj_priv->agp_mem);
                 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
@@ -2581,9 +2582,6 @@ i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
         bool retry_alloc = false;
         int ret;
 
-        if (dev_priv->mm.suspended)
-                return -EBUSY;
-
         if (obj_priv->madv != I915_MADV_WILLNEED) {
                 DRM_ERROR("Attempting to bind a purgeable object\n");
                 return -EINVAL;
@@ -3198,7 +3196,7 @@ i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
 static int
 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
                                  struct drm_file *file_priv,
-                                 struct drm_i915_gem_exec_object *entry,
+                                 struct drm_i915_gem_exec_object2 *entry,
                                  struct drm_i915_gem_relocation_entry *relocs)
 {
         struct drm_device *dev = obj->dev;
@@ -3206,12 +3204,35 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
         struct drm_i915_gem_object *obj_priv = obj->driver_private;
         int i, ret;
         void __iomem *reloc_page;
+        bool need_fence;
+
+        need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
+                     obj_priv->tiling_mode != I915_TILING_NONE;
+
+        /* Check fence reg constraints and rebind if necessary */
+        if (need_fence && !i915_obj_fenceable(dev, obj))
+                i915_gem_object_unbind(obj);
 
         /* Choose the GTT offset for our buffer and put it there. */
         ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
         if (ret)
                 return ret;
 
+        /*
+         * Pre-965 chips need a fence register set up in order to
+         * properly handle blits to/from tiled surfaces.
+         */
+        if (need_fence) {
+                ret = i915_gem_object_get_fence_reg(obj);
+                if (ret != 0) {
+                        if (ret != -EBUSY && ret != -ERESTARTSYS)
+                                DRM_ERROR("Failure to install fence: %d\n",
+                                          ret);
+                        i915_gem_object_unpin(obj);
+                        return ret;
+                }
+        }
+
         entry->offset = obj_priv->gtt_offset;
 
         /* Apply the relocations, using the GTT aperture to avoid cache
@@ -3373,7 +3394,7 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
  */
 static int
 i915_dispatch_gem_execbuffer(struct drm_device *dev,
-                              struct drm_i915_gem_execbuffer *exec,
+                              struct drm_i915_gem_execbuffer2 *exec,
                               struct drm_clip_rect *cliprects,
                               uint64_t exec_offset)
 {
@@ -3463,7 +3484,7 @@ i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
 }
 
 static int
-i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object *exec_list,
+i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
                               uint32_t buffer_count,
                               struct drm_i915_gem_relocation_entry **relocs)
 {
@@ -3478,8 +3499,10 @@ i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object *exec_list,
         }
 
         *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
-        if (*relocs == NULL)
+        if (*relocs == NULL) {
+                DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
                 return -ENOMEM;
+        }
 
         for (i = 0; i < buffer_count; i++) {
                 struct drm_i915_gem_relocation_entry __user *user_relocs;
@@ -3503,7 +3526,7 @@ i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object *exec_list,
 }
 
 static int
-i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object *exec_list,
+i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
                             uint32_t buffer_count,
                             struct drm_i915_gem_relocation_entry *relocs)
 {
@@ -3536,7 +3559,7 @@ err:
 }
 
 static int
-i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer *exec,
+i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
                            uint64_t exec_offset)
 {
         uint32_t exec_start, exec_len;
@@ -3589,18 +3612,18 @@ i915_gem_wait_for_pending_flip(struct drm_device *dev,
 }
 
 int
-i915_gem_execbuffer(struct drm_device *dev, void *data,
-                    struct drm_file *file_priv)
+i915_gem_do_execbuffer(struct drm_device *dev, void *data,
+                       struct drm_file *file_priv,
+                       struct drm_i915_gem_execbuffer2 *args,
+                       struct drm_i915_gem_exec_object2 *exec_list)
 {
         drm_i915_private_t *dev_priv = dev->dev_private;
-        struct drm_i915_gem_execbuffer *args = data;
-        struct drm_i915_gem_exec_object *exec_list = NULL;
         struct drm_gem_object **object_list = NULL;
         struct drm_gem_object *batch_obj;
         struct drm_i915_gem_object *obj_priv;
         struct drm_clip_rect *cliprects = NULL;
         struct drm_i915_gem_relocation_entry *relocs;
-        int ret, ret2, i, pinned = 0;
+        int ret = 0, ret2, i, pinned = 0;
         uint64_t exec_offset;
         uint32_t seqno, flush_domains, reloc_index;
         int pin_tries, flips;
@@ -3614,25 +3637,13 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
                 return -EINVAL;
         }
-        /* Copy in the exec list from userland */
-        exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
         object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
-        if (exec_list == NULL || object_list == NULL) {
-                DRM_ERROR("Failed to allocate exec or object list "
-                          "for %d buffers\n",
+        if (object_list == NULL) {
+                DRM_ERROR("Failed to allocate object list for %d buffers\n",
                           args->buffer_count);
                 ret = -ENOMEM;
                 goto pre_mutex_err;
         }
-        ret = copy_from_user(exec_list,
-                             (struct drm_i915_relocation_entry __user *)
-                             (uintptr_t) args->buffers_ptr,
-                             sizeof(*exec_list) * args->buffer_count);
-        if (ret != 0) {
-                DRM_ERROR("copy %d exec entries failed %d\n",
-                          args->buffer_count, ret);
-                goto pre_mutex_err;
-        }
 
         if (args->num_cliprects != 0) {
                 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
@@ -3884,20 +3895,6 @@ err:
 
         mutex_unlock(&dev->struct_mutex);
 
-        if (!ret) {
-                /* Copy the new buffer offsets back to the user's exec list. */
-                ret = copy_to_user((struct drm_i915_relocation_entry __user *)
-                                   (uintptr_t) args->buffers_ptr,
-                                   exec_list,
-                                   sizeof(*exec_list) * args->buffer_count);
-                if (ret) {
-                        ret = -EFAULT;
-                        DRM_ERROR("failed to copy %d exec entries "
-                                  "back to user (%d)\n",
-                                  args->buffer_count, ret);
-                }
-        }
-
         /* Copy the updated relocations out regardless of current error
          * state.  Failure to update the relocs would mean that the next
          * time userland calls execbuf, it would do so with presumed offset
@@ -3914,12 +3911,158 @@ err:
 
 pre_mutex_err:
         drm_free_large(object_list);
-        drm_free_large(exec_list);
         kfree(cliprects);
 
         return ret;
 }
 
+/*
+ * Legacy execbuffer just creates an exec2 list from the original exec object
+ * list array and passes it to the real function.
+ */
+int
+i915_gem_execbuffer(struct drm_device *dev, void *data,
+                    struct drm_file *file_priv)
+{
+        struct drm_i915_gem_execbuffer *args = data;
+        struct drm_i915_gem_execbuffer2 exec2;
+        struct drm_i915_gem_exec_object *exec_list = NULL;
+        struct drm_i915_gem_exec_object2 *exec2_list = NULL;
+        int ret, i;
+
+#if WATCH_EXEC
+        DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
+                  (int) args->buffers_ptr, args->buffer_count, args->batch_len);
+#endif
+
+        if (args->buffer_count < 1) {
+                DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
+                return -EINVAL;
+        }
+
+        /* Copy in the exec list from userland */
+        exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
+        exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
+        if (exec_list == NULL || exec2_list == NULL) {
+                DRM_ERROR("Failed to allocate exec list for %d buffers\n",
+                          args->buffer_count);
+                drm_free_large(exec_list);
+                drm_free_large(exec2_list);
+                return -ENOMEM;
+        }
+        ret = copy_from_user(exec_list,
+                             (struct drm_i915_relocation_entry __user *)
+                             (uintptr_t) args->buffers_ptr,
+                             sizeof(*exec_list) * args->buffer_count);
+        if (ret != 0) {
+                DRM_ERROR("copy %d exec entries failed %d\n",
+                          args->buffer_count, ret);
+                drm_free_large(exec_list);
+                drm_free_large(exec2_list);
+                return -EFAULT;
+        }
+
+        for (i = 0; i < args->buffer_count; i++) {
+                exec2_list[i].handle = exec_list[i].handle;
+                exec2_list[i].relocation_count = exec_list[i].relocation_count;
+                exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
+                exec2_list[i].alignment = exec_list[i].alignment;
+                exec2_list[i].offset = exec_list[i].offset;
+                if (!IS_I965G(dev))
+                        exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
+                else
+                        exec2_list[i].flags = 0;
+        }
+
+        exec2.buffers_ptr = args->buffers_ptr;
+        exec2.buffer_count = args->buffer_count;
+        exec2.batch_start_offset = args->batch_start_offset;
+        exec2.batch_len = args->batch_len;
+        exec2.DR1 = args->DR1;
+        exec2.DR4 = args->DR4;
+        exec2.num_cliprects = args->num_cliprects;
+        exec2.cliprects_ptr = args->cliprects_ptr;
+        exec2.flags = 0;
+
+        ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
+        if (!ret) {
+                /* Copy the new buffer offsets back to the user's exec list. */
+                for (i = 0; i < args->buffer_count; i++)
+                        exec_list[i].offset = exec2_list[i].offset;
+                /* ... and back out to userspace */
+                ret = copy_to_user((struct drm_i915_relocation_entry __user *)
+                                   (uintptr_t) args->buffers_ptr,
+                                   exec_list,
+                                   sizeof(*exec_list) * args->buffer_count);
+                if (ret) {
+                        ret = -EFAULT;
+                        DRM_ERROR("failed to copy %d exec entries "
+                                  "back to user (%d)\n",
+                                  args->buffer_count, ret);
+                }
+        } else {
+                DRM_ERROR("i915_gem_do_execbuffer returns %d\n", ret);
+        }
+
+        drm_free_large(exec_list);
+        drm_free_large(exec2_list);
+        return ret;
+}
+
+int
+i915_gem_execbuffer2(struct drm_device *dev, void *data,
+                     struct drm_file *file_priv)
+{
+        struct drm_i915_gem_execbuffer2 *args = data;
+        struct drm_i915_gem_exec_object2 *exec2_list = NULL;
+        int ret;
+
+#if WATCH_EXEC
+        DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
+                  (int) args->buffers_ptr, args->buffer_count, args->batch_len);
+#endif
+
+        if (args->buffer_count < 1) {
+                DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
+                return -EINVAL;
+        }
+
+        exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
+        if (exec2_list == NULL) {
+                DRM_ERROR("Failed to allocate exec list for %d buffers\n",
+                          args->buffer_count);
+                return -ENOMEM;
+        }
+        ret = copy_from_user(exec2_list,
+                             (struct drm_i915_relocation_entry __user *)
+                             (uintptr_t) args->buffers_ptr,
+                             sizeof(*exec2_list) * args->buffer_count);
+        if (ret != 0) {
+                DRM_ERROR("copy %d exec entries failed %d\n",
+                          args->buffer_count, ret);
+                drm_free_large(exec2_list);
+                return -EFAULT;
+        }
+
+        ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
+        if (!ret) {
+                /* Copy the new buffer offsets back to the user's exec list. */
+                ret = copy_to_user((struct drm_i915_relocation_entry __user *)
+                                   (uintptr_t) args->buffers_ptr,
+                                   exec2_list,
+                                   sizeof(*exec2_list) * args->buffer_count);
+                if (ret) {
+                        ret = -EFAULT;
+                        DRM_ERROR("failed to copy %d exec entries "
+                                  "back to user (%d)\n",
+                                  args->buffer_count, ret);
+                }
+        }
+
+        drm_free_large(exec2_list);
+        return ret;
+}
+
 int
 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
 {
@@ -3933,19 +4076,7 @@ i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
                 if (ret)
                         return ret;
         }
-        /*
-         * Pre-965 chips need a fence register set up in order to
-         * properly handle tiled surfaces.
-         */
-        if (!IS_I965G(dev) && obj_priv->tiling_mode != I915_TILING_NONE) {
-                ret = i915_gem_object_get_fence_reg(obj);
-                if (ret != 0) {
-                        if (ret != -EBUSY && ret != -ERESTARTSYS)
-                                DRM_ERROR("Failure to install fence: %d\n",
-                                          ret);
-                        return ret;
-                }
-        }
+
         obj_priv->pin_count++;
 
         /* If the object is not active and not pending a flush,
@@ -4708,7 +4839,7 @@ int i915_gem_init_phys_object(struct drm_device *dev,
 
         phys_obj->id = id;
 
-        phys_obj->handle = drm_pci_alloc(dev, size, 0, 0xffffffff);
+        phys_obj->handle = drm_pci_alloc(dev, size, 0);
         if (!phys_obj->handle) {
                 ret = -ENOMEM;
                 goto kfree_obj;
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 30d6af6c09bb..df278b2685bf 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -304,35 +304,39 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
 
 
 /**
- * Returns the size of the fence for a tiled object of the given size.
+ * Returns whether an object is currently fenceable.  If not, it may need
+ * to be unbound and have its pitch adjusted.
  */
-static int
-i915_get_fence_size(struct drm_device *dev, int size)
+bool
+i915_obj_fenceable(struct drm_device *dev, struct drm_gem_object *obj)
 {
-        int i;
-        int start;
+        struct drm_i915_gem_object *obj_priv = obj->driver_private;
 
         if (IS_I965G(dev)) {
                 /* The 965 can have fences at any page boundary. */
-                return ALIGN(size, 4096);
+                if (obj->size & 4095)
+                        return false;
+                return true;
+        } else if (IS_I9XX(dev)) {
+                if (obj_priv->gtt_offset & ~I915_FENCE_START_MASK)
+                        return false;
         } else {
-                /* Align the size to a power of two greater than the smallest
-                 * fence size.
-                 */
-                if (IS_I9XX(dev))
-                        start = 1024 * 1024;
-                else
-                        start = 512 * 1024;
+                if (obj_priv->gtt_offset & ~I830_FENCE_START_MASK)
+                        return false;
+        }
 
-                for (i = start; i < size; i <<= 1)
-                        ;
+        /* Power of two sized... */
+        if (obj->size & (obj->size - 1))
+                return false;
 
-                return i;
-        }
+        /* Objects must be size aligned as well */
+        if (obj_priv->gtt_offset & (obj->size - 1))
+                return false;
+        return true;
 }
 
 /* Check pitch constriants for all chips & tiling formats */
-static bool
+bool
 i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
 {
         int tile_width;
@@ -384,12 +388,6 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
         if (stride & (stride - 1))
                 return false;
 
-        /* We don't 0handle the aperture area covered by the fence being bigger
-         * than the object size.
-         */
-        if (i915_get_fence_size(dev, size) != size)
-                return false;
-
         return true;
 }
 
diff --git a/drivers/gpu/drm/i915/i915_ioc32.c b/drivers/gpu/drm/i915/i915_ioc32.c
index 1fe68a251b75..13b028994b2b 100644
--- a/drivers/gpu/drm/i915/i915_ioc32.c
+++ b/drivers/gpu/drm/i915/i915_ioc32.c
@@ -66,8 +66,7 @@ static int compat_i915_batchbuffer(struct file *file, unsigned int cmd,
                           &batchbuffer->cliprects))
                 return -EFAULT;
 
-        return drm_ioctl(file->f_path.dentry->d_inode, file,
-                         DRM_IOCTL_I915_BATCHBUFFER,
+        return drm_ioctl(file, DRM_IOCTL_I915_BATCHBUFFER,
                          (unsigned long)batchbuffer);
 }
 
@@ -102,8 +101,8 @@ static int compat_i915_cmdbuffer(struct file *file, unsigned int cmd,
                           &cmdbuffer->cliprects))
                 return -EFAULT;
 
-        return drm_ioctl(file->f_path.dentry->d_inode, file,
-                         DRM_IOCTL_I915_CMDBUFFER, (unsigned long)cmdbuffer);
+        return drm_ioctl(file, DRM_IOCTL_I915_CMDBUFFER,
+                         (unsigned long)cmdbuffer);
 }
 
 typedef struct drm_i915_irq_emit32 {
@@ -125,8 +124,8 @@ static int compat_i915_irq_emit(struct file *file, unsigned int cmd,
                           &request->irq_seq))
                 return -EFAULT;
 
-        return drm_ioctl(file->f_path.dentry->d_inode, file,
-                         DRM_IOCTL_I915_IRQ_EMIT, (unsigned long)request);
+        return drm_ioctl(file, DRM_IOCTL_I915_IRQ_EMIT,
+                         (unsigned long)request);
 }
 typedef struct drm_i915_getparam32 {
         int param;
@@ -149,8 +148,8 @@ static int compat_i915_getparam(struct file *file, unsigned int cmd,
                           &request->value))
                 return -EFAULT;
 
-        return drm_ioctl(file->f_path.dentry->d_inode, file,
-                         DRM_IOCTL_I915_GETPARAM, (unsigned long)request);
+        return drm_ioctl(file, DRM_IOCTL_I915_GETPARAM,
+                         (unsigned long)request);
 }
 
 typedef struct drm_i915_mem_alloc32 {
@@ -178,8 +177,8 @@ static int compat_i915_alloc(struct file *file, unsigned int cmd,
                           &request->region_offset))
                 return -EFAULT;
 
-        return drm_ioctl(file->f_path.dentry->d_inode, file,
-                         DRM_IOCTL_I915_ALLOC, (unsigned long)request);
+        return drm_ioctl(file, DRM_IOCTL_I915_ALLOC,
+                         (unsigned long)request);
 }
 
 drm_ioctl_compat_t *i915_compat_ioctls[] = {
@@ -211,12 +210,10 @@ long i915_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
         if (nr < DRM_COMMAND_BASE + DRM_ARRAY_SIZE(i915_compat_ioctls))
                 fn = i915_compat_ioctls[nr - DRM_COMMAND_BASE];
 
-        lock_kernel();          /* XXX for now */
         if (fn != NULL)
                 ret = (*fn) (filp, cmd, arg);
         else
-                ret = drm_ioctl(filp->f_path.dentry->d_inode, filp, cmd, arg);
-        unlock_kernel();
+                ret = drm_ioctl(filp, cmd, arg);
 
         return ret;
 }
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 85f4c5de97e2..7cd8110051b6 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -313,6 +313,8 @@ irqreturn_t ironlake_irq_handler(struct drm_device *dev)
                         dev_priv->mm.irq_gem_seqno = seqno;
                         trace_i915_gem_request_complete(dev, seqno);
                         DRM_WAKEUP(&dev_priv->irq_queue);
+                        dev_priv->hangcheck_count = 0;
+                        mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
                 }
 
                 if (de_iir & DE_GSE)
@@ -1084,6 +1086,10 @@ void i915_driver_irq_preinstall(struct drm_device * dev)
         (void) I915_READ(IER);
 }
 
+/*
+ * Must be called after intel_modeset_init or hotplug interrupts won't be
+ * enabled correctly.
+ */
 int i915_driver_irq_postinstall(struct drm_device *dev)
 {
         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -1106,19 +1112,23 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
         if (I915_HAS_HOTPLUG(dev)) {
                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
 
-                /* Leave other bits alone */
-                hotplug_en |= HOTPLUG_EN_MASK;
+                /* Note HDMI and DP share bits */
+                if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
+                        hotplug_en |= HDMIB_HOTPLUG_INT_EN;
+                if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
+                        hotplug_en |= HDMIC_HOTPLUG_INT_EN;
+                if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
+                        hotplug_en |= HDMID_HOTPLUG_INT_EN;
+                if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
+                        hotplug_en |= SDVOC_HOTPLUG_INT_EN;
+                if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
+                        hotplug_en |= SDVOB_HOTPLUG_INT_EN;
+                if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS)
+                        hotplug_en |= CRT_HOTPLUG_INT_EN;
+                /* Ignore TV since it's buggy */
+
                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
 
-                dev_priv->hotplug_supported_mask = CRT_HOTPLUG_INT_STATUS |
-                        TV_HOTPLUG_INT_STATUS | SDVOC_HOTPLUG_INT_STATUS |
-                        SDVOB_HOTPLUG_INT_STATUS;
-                if (IS_G4X(dev)) {
-                        dev_priv->hotplug_supported_mask |=
-                                HDMIB_HOTPLUG_INT_STATUS |
-                                HDMIC_HOTPLUG_INT_STATUS |
-                                HDMID_HOTPLUG_INT_STATUS;
-                }
                 /* Enable in IER... */
                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
                 /* and unmask in IMR */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 974b3cf70618..149d360d64a3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -879,13 +879,6 @@
 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV        (1 << 2)
 #define CRT_HOTPLUG_MASK                        (0x3fc) /* Bits 9-2 */
 #define CRT_FORCE_HOTPLUG_MASK                  0xfffffe1f
-#define HOTPLUG_EN_MASK (HDMIB_HOTPLUG_INT_EN | \
-                         HDMIC_HOTPLUG_INT_EN |   \
-                         HDMID_HOTPLUG_INT_EN |   \
-                         SDVOB_HOTPLUG_INT_EN |   \
-                         SDVOC_HOTPLUG_INT_EN |   \
-                         CRT_HOTPLUG_INT_EN)
-
 
 #define PORT_HOTPLUG_STAT       0x61114
 #define   HDMIB_HOTPLUG_INT_STATUS              (1 << 29)
@@ -982,6 +975,8 @@
 #define   LVDS_PORT_EN                  (1 << 31)
 /* Selects pipe B for LVDS data.  Must be set on pre-965. */
 #define   LVDS_PIPEB_SELECT             (1 << 30)
+/* LVDS dithering flag on 965/g4x platform */
+#define   LVDS_ENABLE_DITHER            (1 << 25)
 /* Enable border for unscaled (or aspect-scaled) display */
 #define   LVDS_BORDER_ENABLE            (1 << 15)
 /*
@@ -1751,6 +1746,8 @@
 
 /* Display & cursor control */
 
+/* dithering flag on Ironlake */
+#define PIPE_ENABLE_DITHER      (1 << 4)
 /* Pipe A */
 #define PIPEADSL                0x70000
 #define PIPEACONF               0x70008
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index d5ebb00a9d49..a3b90c9561dc 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -732,12 +732,6 @@ int i915_save_state(struct drm_device *dev)
 
         pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
 
-        /* Render Standby */
-        if (I915_HAS_RC6(dev)) {
-                dev_priv->saveRENDERSTANDBY = I915_READ(MCHBAR_RENDER_STANDBY);
-                dev_priv->savePWRCTXA = I915_READ(PWRCTXA);
-        }
-
         /* Hardware status page */
         dev_priv->saveHWS = I915_READ(HWS_PGA);
 
@@ -793,12 +787,6 @@ int i915_restore_state(struct drm_device *dev)
 
         pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
 
-        /* Render Standby */
-        if (I915_HAS_RC6(dev)) {
-                I915_WRITE(MCHBAR_RENDER_STANDBY, dev_priv->saveRENDERSTANDBY);
-                I915_WRITE(PWRCTXA, dev_priv->savePWRCTXA);
-        }
-
         /* Hardware status page */
         I915_WRITE(HWS_PGA, dev_priv->saveHWS);
 
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 9f3d3e563414..ddefc871edfe 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -548,4 +548,6 @@ void intel_crt_init(struct drm_device *dev)
         drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
 
         drm_sysfs_connector_add(connector);
+
+        dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS;
 }
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 52cd9b006da2..002612fae717 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -262,6 +262,14 @@ struct intel_limit {
 #define IRONLAKE_P2_LVDS_FAST    7  /* double channel */
 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 
+#define IRONLAKE_P_DISPLAY_PORT_MIN     10
+#define IRONLAKE_P_DISPLAY_PORT_MAX     20
+#define IRONLAKE_P2_DISPLAY_PORT_FAST   10
+#define IRONLAKE_P2_DISPLAY_PORT_SLOW   10
+#define IRONLAKE_P2_DISPLAY_PORT_LIMIT  0
+#define IRONLAKE_P1_DISPLAY_PORT_MIN    1
+#define IRONLAKE_P1_DISPLAY_PORT_MAX    2
+
 static bool
 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
                     int target, int refclk, intel_clock_t *best_clock);
@@ -271,9 +279,6 @@ intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 static bool
 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
                         int target, int refclk, intel_clock_t *best_clock);
-static bool
-intel_ironlake_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
-                             int target, int refclk, intel_clock_t *best_clock);
 
 static bool
 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
@@ -496,7 +501,7 @@ static const intel_limit_t intel_limits_ironlake_sdvo = {
         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
                  .p2_slow = IRONLAKE_P2_SDVO_DAC_SLOW,
                  .p2_fast = IRONLAKE_P2_SDVO_DAC_FAST },
-        .find_pll = intel_ironlake_find_best_PLL,
+        .find_pll = intel_g4x_find_best_PLL,
 };
 
 static const intel_limit_t intel_limits_ironlake_lvds = {
@@ -511,7 +516,30 @@ static const intel_limit_t intel_limits_ironlake_lvds = {
         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
                  .p2_slow = IRONLAKE_P2_LVDS_SLOW,
                  .p2_fast = IRONLAKE_P2_LVDS_FAST },
-        .find_pll = intel_ironlake_find_best_PLL,
+        .find_pll = intel_g4x_find_best_PLL,
+};
+
+static const intel_limit_t intel_limits_ironlake_display_port = {
+        .dot = { .min = IRONLAKE_DOT_MIN,
+                 .max = IRONLAKE_DOT_MAX },
+        .vco = { .min = IRONLAKE_VCO_MIN,
+                 .max = IRONLAKE_VCO_MAX},
+        .n   = { .min = IRONLAKE_N_MIN,
+                 .max = IRONLAKE_N_MAX },
+        .m   = { .min = IRONLAKE_M_MIN,
+                 .max = IRONLAKE_M_MAX },
+        .m1  = { .min = IRONLAKE_M1_MIN,
+                 .max = IRONLAKE_M1_MAX },
+        .m2  = { .min = IRONLAKE_M2_MIN,
+                 .max = IRONLAKE_M2_MAX },
+        .p   = { .min = IRONLAKE_P_DISPLAY_PORT_MIN,
+                 .max = IRONLAKE_P_DISPLAY_PORT_MAX },
+        .p1  = { .min = IRONLAKE_P1_DISPLAY_PORT_MIN,
+                 .max = IRONLAKE_P1_DISPLAY_PORT_MAX},
+        .p2  = { .dot_limit = IRONLAKE_P2_DISPLAY_PORT_LIMIT,
+                 .p2_slow = IRONLAKE_P2_DISPLAY_PORT_SLOW,
+                 .p2_fast = IRONLAKE_P2_DISPLAY_PORT_FAST },
+        .find_pll = intel_find_pll_ironlake_dp,
 };
 
 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
@@ -519,6 +547,9 @@ static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
         const intel_limit_t *limit;
         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
                 limit = &intel_limits_ironlake_lvds;
+        else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
+                        HAS_eDP)
+                limit = &intel_limits_ironlake_display_port;
         else
                 limit = &intel_limits_ironlake_sdvo;
 
@@ -791,7 +822,13 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
         found = false;
 
         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
-                if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
+                int lvds_reg;
+
+                if (IS_IRONLAKE(dev))
+                        lvds_reg = PCH_LVDS;
+                else
+                        lvds_reg = LVDS;
+                if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
                     LVDS_CLKB_POWER_UP)
                         clock.p2 = limit->p2.p2_fast;
                 else
@@ -839,6 +876,11 @@ intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 {
         struct drm_device *dev = crtc->dev;
         intel_clock_t clock;
+
+        /* return directly when it is eDP */
+        if (HAS_eDP)
+                return true;
+
         if (target < 200000) {
                 clock.n = 1;
                 clock.p1 = 2;
@@ -857,68 +899,6 @@ intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
         return true;
 }
 
-static bool
-intel_ironlake_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
-                             int target, int refclk, intel_clock_t *best_clock)
-{
-        struct drm_device *dev = crtc->dev;
-        struct drm_i915_private *dev_priv = dev->dev_private;
-        intel_clock_t clock;
-        int err_most = 47;
-        int err_min = 10000;
-
-        /* eDP has only 2 clock choice, no n/m/p setting */
-        if (HAS_eDP)
-                return true;
-
-        if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
-                return intel_find_pll_ironlake_dp(limit, crtc, target,
-                                               refclk, best_clock);
-
-        if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
-                if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
-                    LVDS_CLKB_POWER_UP)
-                        clock.p2 = limit->p2.p2_fast;
-                else
-                        clock.p2 = limit->p2.p2_slow;
-        } else {
-                if (target < limit->p2.dot_limit)
-                        clock.p2 = limit->p2.p2_slow;
-                else
-                        clock.p2 = limit->p2.p2_fast;
-        }
-
-        memset(best_clock, 0, sizeof(*best_clock));
-        for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
-                /* based on hardware requriment prefer smaller n to precision */
-                for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++) {
-                        /* based on hardware requirment prefere larger m1,m2 */
-                        for (clock.m1 = limit->m1.max;
-                             clock.m1 >= limit->m1.min; clock.m1--) {
-                                for (clock.m2 = limit->m2.max;
-                                     clock.m2 >= limit->m2.min; clock.m2--) {
-                                        int this_err;
-
-                                        intel_clock(dev, refclk, &clock);
-                                        if (!intel_PLL_is_valid(crtc, &clock))
-                                                continue;
-                                        this_err = abs((10000 - (target*10000/clock.dot)));
-                                        if (this_err < err_most) {
-                                                *best_clock = clock;
-                                                /* found on first matching */
-                                                goto out;
-                                        } else if (this_err < err_min) {
-                                                *best_clock = clock;
-                                                err_min = this_err;
-                                        }
-                                }
-                        }
-                }
-        }
-out:
-        return true;
-}
-
 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 static bool
 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
@@ -1493,6 +1473,10 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
         u32 temp;
         int tries = 5, j, n;
+        u32 pipe_bpc;
+
+        temp = I915_READ(pipeconf_reg);
+        pipe_bpc = temp & PIPE_BPC_MASK;
 
         /* XXX: When our outputs are all unaware of DPMS modes other than off
          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
@@ -1524,6 +1508,12 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
 
                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
                         temp = I915_READ(fdi_rx_reg);
+                        /*
+                         * make the BPC in FDI Rx be consistent with that in
+                         * pipeconf reg.
+                         */
+                        temp &= ~(0x7 << 16);
+                        temp |= (pipe_bpc << 11);
                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
                                         FDI_SEL_PCDCLK |
                                         FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
@@ -1666,6 +1656,12 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
 
                         /* enable PCH transcoder */
                         temp = I915_READ(transconf_reg);
+                        /*
+                         * make the BPC in transcoder be consistent with
+                         * that in pipeconf reg.
+                         */
+                        temp &= ~PIPE_BPC_MASK;
+                        temp |= pipe_bpc;
                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
                         I915_READ(transconf_reg);
 
@@ -1745,6 +1741,9 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
                 I915_READ(fdi_tx_reg);
 
                 temp = I915_READ(fdi_rx_reg);
+                /* BPC in FDI rx is consistent with that in pipeconf */
+                temp &= ~(0x07 << 16);
+                temp |= (pipe_bpc << 11);
                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
                 I915_READ(fdi_rx_reg);
 
@@ -1789,7 +1788,12 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
                                 }
                         }
                 }
-
+                temp = I915_READ(transconf_reg);
+                /* BPC in transcoder is consistent with that in pipeconf */
+                temp &= ~PIPE_BPC_MASK;
+                temp |= pipe_bpc;
+                I915_WRITE(transconf_reg, temp);
+                I915_READ(transconf_reg);
                 udelay(100);
 
                 /* disable PCH DPLL */
@@ -2448,7 +2452,7 @@ static void pineview_enable_cxsr(struct drm_device *dev, unsigned long clock,
  * A value of 5us seems to be a good balance; safe for very low end
  * platforms but not overly aggressive on lower latency configs.
  */
-const static int latency_ns = 5000;
+static const int latency_ns = 5000;
 
 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 {
@@ -2559,7 +2563,7 @@ static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
         /* Calc sr entries for one plane configs */
         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
                 /* self-refresh has much higher latency */
-                const static int sr_latency_ns = 12000;
+                static const int sr_latency_ns = 12000;
 
                 sr_clock = planea_clock ? planea_clock : planeb_clock;
                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
@@ -2598,7 +2602,7 @@ static void i965_update_wm(struct drm_device *dev, int planea_clock,
         /* Calc sr entries for one plane configs */
         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
                 /* self-refresh has much higher latency */
-                const static int sr_latency_ns = 12000;
+                static const int sr_latency_ns = 12000;
 
                 sr_clock = planea_clock ? planea_clock : planeb_clock;
                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
@@ -2667,7 +2671,7 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
         if (HAS_FW_BLC(dev) && sr_hdisplay &&
             (!planea_clock || !planeb_clock)) {
                 /* self-refresh has much higher latency */
-                const static int sr_latency_ns = 6000;
+                static const int sr_latency_ns = 6000;
 
                 sr_clock = planea_clock ? planea_clock : planeb_clock;
                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
@@ -2969,6 +2973,18 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
 
                 /* determine panel color depth */
                 temp = I915_READ(pipeconf_reg);
+                temp &= ~PIPE_BPC_MASK;
+                if (is_lvds) {
+                        int lvds_reg = I915_READ(PCH_LVDS);
+                        /* the BPC will be 6 if it is 18-bit LVDS panel */
+                        if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
+                                temp |= PIPE_8BPC;
+                        else
+                                temp |= PIPE_6BPC;
+                } else
+                        temp |= PIPE_8BPC;
+                I915_WRITE(pipeconf_reg, temp);
+                I915_READ(pipeconf_reg);
 
                 switch (temp & PIPE_BPC_MASK) {
                 case PIPE_8BPC:
@@ -3195,7 +3211,20 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
                  * appropriately here, but we need to look more thoroughly into how
                  * panels behave in the two modes.
                  */
-
+                /* set the dithering flag */
+                if (IS_I965G(dev)) {
+                        if (dev_priv->lvds_dither) {
+                                if (IS_IRONLAKE(dev))
+                                        pipeconf |= PIPE_ENABLE_DITHER;
+                                else
+                                        lvds |= LVDS_ENABLE_DITHER;
+                        } else {
+                                if (IS_IRONLAKE(dev))
+                                        pipeconf &= ~PIPE_ENABLE_DITHER;
+                                else
+                                        lvds &= ~LVDS_ENABLE_DITHER;
+                        }
+                }
                 I915_WRITE(lvds_reg, lvds);
                 I915_READ(lvds_reg);
         }
@@ -3385,7 +3414,7 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
 
         /* we only need to pin inside GTT if cursor is non-phy */
         mutex_lock(&dev->struct_mutex);
-        if (!dev_priv->cursor_needs_physical) {
+        if (!dev_priv->info->cursor_needs_physical) {
                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
                 if (ret) {
                         DRM_ERROR("failed to pin cursor bo\n");
@@ -3420,7 +3449,7 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
         I915_WRITE(base, addr);
 
         if (intel_crtc->cursor_bo) {
-                if (dev_priv->cursor_needs_physical) {
+                if (dev_priv->info->cursor_needs_physical) {
                         if (intel_crtc->cursor_bo != bo)
                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
                 } else
@@ -3779,125 +3808,6 @@ static void intel_gpu_idle_timer(unsigned long arg)
         queue_work(dev_priv->wq, &dev_priv->idle_work);
 }
 
-void intel_increase_renderclock(struct drm_device *dev, bool schedule)
-{
-        drm_i915_private_t *dev_priv = dev->dev_private;
-
-        if (IS_IRONLAKE(dev))
-                return;
-
-        if (!dev_priv->render_reclock_avail) {
-                DRM_DEBUG_DRIVER("not reclocking render clock\n");
-                return;
-        }
-
-        /* Restore render clock frequency to original value */
-        if (IS_G4X(dev) || IS_I9XX(dev))
-                pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock);
-        else if (IS_I85X(dev))
-                pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock);
-        DRM_DEBUG_DRIVER("increasing render clock frequency\n");
-
-        /* Schedule downclock */
-        if (schedule)
-                mod_timer(&dev_priv->idle_timer, jiffies +
-                          msecs_to_jiffies(GPU_IDLE_TIMEOUT));
-}
-
-void intel_decrease_renderclock(struct drm_device *dev)
-{
-        drm_i915_private_t *dev_priv = dev->dev_private;
-
-        if (IS_IRONLAKE(dev))
-                return;
-
-        if (!dev_priv->render_reclock_avail) {
-                DRM_DEBUG_DRIVER("not reclocking render clock\n");
-                return;
-        }
-
-        if (IS_G4X(dev)) {
-                u16 gcfgc;
-
-                /* Adjust render clock... */
-                pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
-
-                /* Down to minimum... */
-                gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK;
-                gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ;
-
-                pci_write_config_word(dev->pdev, GCFGC, gcfgc);
-        } else if (IS_I965G(dev)) {
-                u16 gcfgc;
-
-                /* Adjust render clock... */
-                pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
-
-                /* Down to minimum... */
-                gcfgc &= ~I965_GC_RENDER_CLOCK_MASK;
-                gcfgc |= I965_GC_RENDER_CLOCK_267_MHZ;
-
-                pci_write_config_word(dev->pdev, GCFGC, gcfgc);
-        } else if (IS_I945G(dev) || IS_I945GM(dev)) {
-                u16 gcfgc;
-
-                /* Adjust render clock... */
-                pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
-
-                /* Down to minimum... */
-                gcfgc &= ~I945_GC_RENDER_CLOCK_MASK;
-                gcfgc |= I945_GC_RENDER_CLOCK_166_MHZ;
-
-                pci_write_config_word(dev->pdev, GCFGC, gcfgc);
-        } else if (IS_I915G(dev)) {
-                u16 gcfgc;
-
-                /* Adjust render clock... */
-                pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
-
-                /* Down to minimum... */
-                gcfgc &= ~I915_GC_RENDER_CLOCK_MASK;
-                gcfgc |= I915_GC_RENDER_CLOCK_166_MHZ;
-
-                pci_write_config_word(dev->pdev, GCFGC, gcfgc);
-        } else if (IS_I85X(dev)) {
-                u16 hpllcc;
-
-                /* Adjust render clock... */
-                pci_read_config_word(dev->pdev, HPLLCC, &hpllcc);
-
-                /* Up to maximum... */
-                hpllcc &= ~GC_CLOCK_CONTROL_MASK;
-                hpllcc |= GC_CLOCK_133_200;
-
-                pci_write_config_word(dev->pdev, HPLLCC, hpllcc);
-        }
-        DRM_DEBUG_DRIVER("decreasing render clock frequency\n");
-}
-
-/* Note that no increase function is needed for this - increase_renderclock()
- *  will also rewrite these bits
- */
-void intel_decrease_displayclock(struct drm_device *dev)
-{
-        if (IS_IRONLAKE(dev))
-                return;
-
-        if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) ||
-            IS_I915GM(dev)) {
-                u16 gcfgc;
-
-                /* Adjust render clock... */
-                pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
-
-                /* Down to minimum... */
-                gcfgc &= ~0xf0;
-                gcfgc |= 0x80;
-
-                pci_write_config_word(dev->pdev, GCFGC, gcfgc);
-        }
-}
-
 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
 
 static void intel_crtc_idle_timer(unsigned long arg)
@@ -4011,12 +3921,6 @@ static void intel_idle_update(struct work_struct *work)
 
         mutex_lock(&dev->struct_mutex);
 
-        /* GPU isn't processing, downclock it. */
-        if (!dev_priv->busy) {
-                intel_decrease_renderclock(dev);
-                intel_decrease_displayclock(dev);
-        }
-
         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
                 /* Skip inactive CRTCs */
                 if (!crtc->fb)
@@ -4050,13 +3954,11 @@ void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
         if (!drm_core_check_feature(dev, DRIVER_MODESET))
                 return;
 
-        if (!dev_priv->busy) {
+        if (!dev_priv->busy)
                 dev_priv->busy = true;
-                intel_increase_renderclock(dev, true);
-        } else {
+        else
                 mod_timer(&dev_priv->idle_timer, jiffies +
                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
-        }
 
         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
                 if (!crtc->fb)
@@ -4400,29 +4302,43 @@ static void intel_setup_outputs(struct drm_device *dev)
                 bool found = false;
 
                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
+                        DRM_DEBUG_KMS("probing SDVOB\n");
                         found = intel_sdvo_init(dev, SDVOB);
-                        if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
+                        if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
+                                DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
                                 intel_hdmi_init(dev, SDVOB);
+                        }
 
-                        if (!found && SUPPORTS_INTEGRATED_DP(dev))
+                        if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
+                                DRM_DEBUG_KMS("probing DP_B\n");
                                 intel_dp_init(dev, DP_B);
+                        }
                 }
 
                 /* Before G4X SDVOC doesn't have its own detect register */
 
-                if (I915_READ(SDVOB) & SDVO_DETECTED)
+                if (I915_READ(SDVOB) & SDVO_DETECTED) {
+                        DRM_DEBUG_KMS("probing SDVOC\n");
                         found = intel_sdvo_init(dev, SDVOC);
+                }
 
                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
 
-                        if (SUPPORTS_INTEGRATED_HDMI(dev))
+                        if (SUPPORTS_INTEGRATED_HDMI(dev)) {
+                                DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
                                 intel_hdmi_init(dev, SDVOC);
-                        if (SUPPORTS_INTEGRATED_DP(dev))
+                        }
+                        if (SUPPORTS_INTEGRATED_DP(dev)) {
+                                DRM_DEBUG_KMS("probing DP_C\n");
                                 intel_dp_init(dev, DP_C);
+                        }
                 }
 
-                if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
+                if (SUPPORTS_INTEGRATED_DP(dev) &&
+                    (I915_READ(DP_D) & DP_DETECTED)) {
+                        DRM_DEBUG_KMS("probing DP_D\n");
                         intel_dp_init(dev, DP_D);
+                }
         } else if (IS_I8XX(dev))
                 intel_dvo_init(dev);
 
@@ -4527,6 +4443,42 @@ static const struct drm_mode_config_funcs intel_mode_funcs = {
         .fb_changed = intelfb_probe,
 };
 
+static struct drm_gem_object *
+intel_alloc_power_context(struct drm_device *dev)
+{
+        struct drm_gem_object *pwrctx;
+        int ret;
+
+        pwrctx = drm_gem_object_alloc(dev, 4096);
+        if (!pwrctx) {
+                DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
+                return NULL;
+        }
+
+        mutex_lock(&dev->struct_mutex);
+        ret = i915_gem_object_pin(pwrctx, 4096);
+        if (ret) {
+                DRM_ERROR("failed to pin power context: %d\n", ret);
+                goto err_unref;
+        }
+
+        ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
+        if (ret) {
+                DRM_ERROR("failed to set-domain on power context: %d\n", ret);
+                goto err_unpin;
+        }
+        mutex_unlock(&dev->struct_mutex);
+
+        return pwrctx;
+
+err_unpin:
+        i915_gem_object_unpin(pwrctx);
+err_unref:
+        drm_gem_object_unreference(pwrctx);
+        mutex_unlock(&dev->struct_mutex);
+        return NULL;
+}
+
 void intel_init_clock_gating(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
@@ -4579,42 +4531,27 @@ void intel_init_clock_gating(struct drm_device *dev)
          * GPU can automatically power down the render unit if given a page
          * to save state.
          */
-        if (I915_HAS_RC6(dev)) {
-                struct drm_gem_object *pwrctx;
-                struct drm_i915_gem_object *obj_priv;
-                int ret;
+        if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
+                struct drm_i915_gem_object *obj_priv = NULL;
 
                 if (dev_priv->pwrctx) {
                         obj_priv = dev_priv->pwrctx->driver_private;
                 } else {
-                        pwrctx = drm_gem_object_alloc(dev, 4096);
-                        if (!pwrctx) {
-                                DRM_DEBUG("failed to alloc power context, "
-                                          "RC6 disabled\n");
-                                goto out;
-                        }
+                        struct drm_gem_object *pwrctx;
 
-                        ret = i915_gem_object_pin(pwrctx, 4096);
-                        if (ret) {
-                                DRM_ERROR("failed to pin power context: %d\n",
-                                          ret);
-                                drm_gem_object_unreference(pwrctx);
-                                goto out;
+                        pwrctx = intel_alloc_power_context(dev);
+                        if (pwrctx) {
+                                dev_priv->pwrctx = pwrctx;
+                                obj_priv = pwrctx->driver_private;
                         }
-
-                        i915_gem_object_set_to_gtt_domain(pwrctx, 1);
-
-                        dev_priv->pwrctx = pwrctx;
-                        obj_priv = pwrctx->driver_private;
                 }
 
-                I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
-                I915_WRITE(MCHBAR_RENDER_STANDBY,
-                           I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
+                if (obj_priv) {
+                        I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
+                        I915_WRITE(MCHBAR_RENDER_STANDBY,
+                                   I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
+                }
         }
-
-out:
-        return;
 }
 
 /* Set up chip specific display functions */
@@ -4770,7 +4707,6 @@ void intel_modeset_cleanup(struct drm_device *dev)
                 del_timer_sync(&intel_crtc->idle_timer);
         }
 
-        intel_increase_renderclock(dev, false);
         del_timer_sync(&dev_priv->idle_timer);
 
         if (dev_priv->display.disable_fbc)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4e7aa8b7b938..1349d9fd01c4 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1402,14 +1402,20 @@ intel_dp_init(struct drm_device *dev, int output_reg)
                         break;
                 case DP_B:
                 case PCH_DP_B:
+                        dev_priv->hotplug_supported_mask |=
+                                HDMIB_HOTPLUG_INT_STATUS;
                         name = "DPDDC-B";
                         break;
                 case DP_C:
                 case PCH_DP_C:
+                        dev_priv->hotplug_supported_mask |=
+                                HDMIC_HOTPLUG_INT_STATUS;
                         name = "DPDDC-C";
                         break;
                 case DP_D:
                 case PCH_DP_D:
+                        dev_priv->hotplug_supported_mask |=
+                                HDMID_HOTPLUG_INT_STATUS;
                         name = "DPDDC-D";
                         break;
         }
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index f04dbbe7d400..06431941b233 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -303,21 +303,26 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
         if (sdvox_reg == SDVOB) {
                 intel_output->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
                 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "HDMIB");
+                dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
         } else if (sdvox_reg == SDVOC) {
                 intel_output->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
                 intel_output->ddc_bus = intel_i2c_create(dev, GPIOD, "HDMIC");
+                dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
         } else if (sdvox_reg == HDMIB) {
                 intel_output->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
                 intel_output->ddc_bus = intel_i2c_create(dev, PCH_GPIOE,
                                                                 "HDMIB");
+                dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
         } else if (sdvox_reg == HDMIC) {
                 intel_output->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT);
                 intel_output->ddc_bus = intel_i2c_create(dev, PCH_GPIOD,
                                                                 "HDMIC");
+                dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
         } else if (sdvox_reg == HDMID) {
                 intel_output->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
                 intel_output->ddc_bus = intel_i2c_create(dev, PCH_GPIOF,
                                                                 "HDMID");
+                dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
         }
         if (!intel_output->ddc_bus)
                 goto err_connector;
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 3118ce274e67..f4b4aa242df1 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -608,6 +608,13 @@ static const struct dmi_system_id bad_lid_status[] = {
                         DMI_MATCH(DMI_PRODUCT_NAME, "Aspire one"),
                 },
         },
+        {
+                .ident = "PC-81005",
+                .matches = {
+                        DMI_MATCH(DMI_SYS_VENDOR, "MALATA"),
+                        DMI_MATCH(DMI_PRODUCT_NAME, "PC-81005"),
+                },
+        },
         { }
 };
 
@@ -679,7 +686,14 @@ static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
         struct drm_i915_private *dev_priv =
                 container_of(nb, struct drm_i915_private, lid_notifier);
         struct drm_device *dev = dev_priv->dev;
+        struct drm_connector *connector = dev_priv->int_lvds_connector;
 
+        /*
+         * check and update the status of LVDS connector after receiving
+         * the LID nofication event.
+         */
+        if (connector)
+                connector->status = connector->funcs->detect(connector);
         if (!acpi_lid_open()) {
                 dev_priv->modeset_on_lid = 1;
                 return NOTIFY_OK;
@@ -854,65 +868,6 @@ static const struct dmi_system_id intel_no_lvds[] = {
         { }     /* terminating entry */
 };
 
-#ifdef CONFIG_ACPI
-/*
- * check_lid_device -- check whether @handle is an ACPI LID device.
- * @handle: ACPI device handle
- * @level : depth in the ACPI namespace tree
- * @context: the number of LID device when we find the device
- * @rv: a return value to fill if desired (Not use)
- */
-static acpi_status
-check_lid_device(acpi_handle handle, u32 level, void *context,
-                        void **return_value)
-{
-        struct acpi_device *acpi_dev;
-        int *lid_present = context;
-
-        acpi_dev = NULL;
-        /* Get the acpi device for device handle */
-        if (acpi_bus_get_device(handle, &acpi_dev) || !acpi_dev) {
-                /* If there is no ACPI device for handle, return */
-                return AE_OK;
-        }
-
-        if (!strncmp(acpi_device_hid(acpi_dev), "PNP0C0D", 7))
-                *lid_present = 1;
-
-        return AE_OK;
-}
-
-/**
- * check whether there exists the ACPI LID device by enumerating the ACPI
- * device tree.
- */
-static int intel_lid_present(void)
-{
-        int lid_present = 0;
-
-        if (acpi_disabled) {
-                /* If ACPI is disabled, there is no ACPI device tree to
-                 * check, so assume the LID device would have been present.
-                 */
-                return 1;
-        }
-
-        acpi_walk_namespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT,
-                                ACPI_UINT32_MAX,
-                                check_lid_device, NULL, &lid_present, NULL);
-
-        return lid_present;
-}
-#else
-static int intel_lid_present(void)
-{
-        /* In the absence of ACPI built in, assume that the LID device would
-         * have been present.
-         */
-        return 1;
-}
-#endif
-
 /**
  * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID
  * @dev: drm device
@@ -1031,12 +986,8 @@ void intel_lvds_init(struct drm_device *dev)
         if (dmi_check_system(intel_no_lvds))
                 return;
 
-        /*
-         * Assume LVDS is present if there's an ACPI lid device or if the
-         * device is present in the VBT.
-         */
-        if (!lvds_is_present_in_vbt(dev) && !intel_lid_present()) {
-                DRM_DEBUG_KMS("LVDS is not present in VBT and no lid detected\n");
+        if (!lvds_is_present_in_vbt(dev)) {
+                DRM_DEBUG_KMS("LVDS is not present in VBT\n");
                 return;
         }
 
@@ -1180,6 +1131,8 @@ out:
                 DRM_DEBUG_KMS("lid notifier registration failed\n");
                 dev_priv->lid_notifier.notifier_call = NULL;
         }
+        /* keep the LVDS connector */
+        dev_priv->int_lvds_connector = connector;
         drm_sysfs_connector_add(connector);
         return;
 
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 24a3dc99716c..de5144c8c153 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -2662,6 +2662,7 @@ static void intel_sdvo_create_enhance_property(struct drm_connector *connector)
 
 bool intel_sdvo_init(struct drm_device *dev, int output_device)
 {
+        struct drm_i915_private *dev_priv = dev->dev_private;
         struct drm_connector *connector;
         struct intel_output *intel_output;
         struct intel_sdvo_priv *sdvo_priv;
@@ -2708,10 +2709,12 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device)
                 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS");
                 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA,
                                                 "SDVOB/VGA DDC BUS");
+                dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
         } else {
                 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOC DDC BUS");
                 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA,
                                                 "SDVOC/VGA DDC BUS");
+                dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
         }
 
         if (intel_output->ddc_bus == NULL)
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 552ec110b741..1d5b9b7b033f 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -1840,6 +1840,8 @@ intel_tv_init(struct drm_device *dev)
         drm_connector_attach_property(connector,
                                    dev->mode_config.tv_bottom_margin_property,
                                    tv_priv->margin[TV_MARGIN_BOTTOM]);
+
+        dev_priv->hotplug_supported_mask |= TV_HOTPLUG_INT_STATUS;
 out:
         drm_sysfs_connector_add(connector);
 }
diff --git a/drivers/gpu/drm/mga/mga_drv.c b/drivers/gpu/drm/mga/mga_drv.c
index 97ee566ef749..ddfe16197b59 100644
--- a/drivers/gpu/drm/mga/mga_drv.c
+++ b/drivers/gpu/drm/mga/mga_drv.c
@@ -68,7 +68,7 @@ static struct drm_driver driver = {
                 .owner = THIS_MODULE,
                 .open = drm_open,
                 .release = drm_release,
-                .ioctl = drm_ioctl,
+                .unlocked_ioctl = drm_ioctl,
                 .mmap = drm_mmap,
                 .poll = drm_poll,
                 .fasync = drm_fasync,
diff --git a/drivers/gpu/drm/mga/mga_ioc32.c b/drivers/gpu/drm/mga/mga_ioc32.c
index 30d00478ddee..c1f877b7bac1 100644
--- a/drivers/gpu/drm/mga/mga_ioc32.c
+++ b/drivers/gpu/drm/mga/mga_ioc32.c
@@ -100,8 +100,7 @@ static int compat_mga_init(struct file *file, unsigned int cmd,
         if (err)
                 return -EFAULT;
 
-        return drm_ioctl(file->f_path.dentry->d_inode, file,
-                         DRM_IOCTL_MGA_INIT, (unsigned long)init);
+        return drm_ioctl(file, DRM_IOCTL_MGA_INIT, (unsigned long)init);
 }
 
 typedef struct drm_mga_getparam32 {
@@ -125,8 +124,7 @@ static int compat_mga_getparam(struct file *file, unsigned int cmd,
                           &getparam->value))
                 return -EFAULT;
 
-        return drm_ioctl(file->f_path.dentry->d_inode, file,
-                         DRM_IOCTL_MGA_GETPARAM, (unsigned long)getparam);
+        return drm_ioctl(file, DRM_IOCTL_MGA_GETPARAM, (unsigned long)getparam);
 }
 
 typedef struct drm_mga_drm_bootstrap32 {
@@ -166,8 +164,7 @@ static int compat_mga_dma_bootstrap(struct file *file, unsigned int cmd,
             || __put_user(dma_bootstrap32.agp_size, &dma_bootstrap->agp_size))
                 return -EFAULT;
 
-        err = drm_ioctl(file->f_path.dentry->d_inode, file,
-                        DRM_IOCTL_MGA_DMA_BOOTSTRAP,
+        err = drm_ioctl(file, DRM_IOCTL_MGA_DMA_BOOTSTRAP,
                         (unsigned long)dma_bootstrap);
         if (err)
                 return err;
@@ -220,12 +217,10 @@ long mga_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
         if (nr < DRM_COMMAND_BASE + DRM_ARRAY_SIZE(mga_compat_ioctls))
                 fn = mga_compat_ioctls[nr - DRM_COMMAND_BASE];
 
-        lock_kernel();          /* XXX for now */
         if (fn != NULL)
                 ret = (*fn) (filp, cmd, arg);
         else
-                ret = drm_ioctl(filp->f_path.dentry->d_inode, filp, cmd, arg);
-        unlock_kernel();
+                ret = drm_ioctl(filp, cmd, arg);
 
         return ret;
 }
diff --git a/drivers/gpu/drm/nouveau/Kconfig b/drivers/gpu/drm/nouveau/Kconfig
index b1bc1ea182b8..1175429da102 100644
--- a/drivers/gpu/drm/nouveau/Kconfig
+++ b/drivers/gpu/drm/nouveau/Kconfig
@@ -30,12 +30,11 @@ config DRM_NOUVEAU_DEBUG
           via debugfs.
 
 menu "I2C encoder or helper chips"
-     depends on DRM && I2C
+     depends on DRM && DRM_KMS_HELPER && I2C
 
 config DRM_I2C_CH7006
         tristate "Chrontel ch7006 TV encoder"
-        depends on DRM_NOUVEAU
-        default m
+        default m if DRM_NOUVEAU
         help
           Support for Chrontel ch7006 and similar TV encoders, found
           on some nVidia video cards.
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index 1d90d4d0144f..48c290b5da8c 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -8,14 +8,15 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
              nouveau_sgdma.o nouveau_dma.o \
              nouveau_bo.o nouveau_fence.o nouveau_gem.o nouveau_ttm.o \
              nouveau_hw.o nouveau_calc.o nouveau_bios.o nouveau_i2c.o \
-             nouveau_display.o nouveau_connector.o nouveau_fbcon.o \
-             nouveau_dp.o \
+             nouveau_display.o nouveau_connector.o nouveau_fbcon.o \
+             nouveau_dp.o nouveau_grctx.o \
              nv04_timer.o \
              nv04_mc.o nv40_mc.o nv50_mc.o \
              nv04_fb.o nv10_fb.o nv40_fb.o \
              nv04_fifo.o nv10_fifo.o nv40_fifo.o nv50_fifo.o \
              nv04_graph.o nv10_graph.o nv20_graph.o \
              nv40_graph.o nv50_graph.o \
+             nv40_grctx.o \
              nv04_instmem.o nv50_instmem.o \
              nv50_crtc.o nv50_dac.o nv50_sor.o \
              nv50_cursor.o nv50_display.o nv50_fbcon.o \
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
index 5eec5ed69489..ba143972769f 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
@@ -181,43 +181,42 @@ struct methods {
         const char desc[8];
         void (*loadbios)(struct drm_device *, uint8_t *);
         const bool rw;
-        int score;
 };
 
 static struct methods nv04_methods[] = {
         { "PROM", load_vbios_prom, false },
         { "PRAMIN", load_vbios_pramin, true },
         { "PCIROM", load_vbios_pci, true },
-        { }
 };
 
 static struct methods nv50_methods[] = {
         { "PRAMIN", load_vbios_pramin, true },
         { "PROM", load_vbios_prom, false },
         { "PCIROM", load_vbios_pci, true },
-        { }
 };
 
+#define METHODCNT 3
+
 static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
 {
         struct drm_nouveau_private *dev_priv = dev->dev_private;
-        struct methods *methods, *method;
+        struct methods *methods;
+        int i;
         int testscore = 3;
+        int scores[METHODCNT];
 
         if (nouveau_vbios) {
-                method = nv04_methods;
-                while (method->loadbios) {
-                        if (!strcasecmp(nouveau_vbios, method->desc))
+                methods = nv04_methods;
+                for (i = 0; i < METHODCNT; i++)
+                        if (!strcasecmp(nouveau_vbios, methods[i].desc))
                                 break;
-                        method++;
-                }
 
-                if (method->loadbios) {
+                if (i < METHODCNT) {
                         NV_INFO(dev, "Attempting to use BIOS image from %s\n",
-                                method->desc);
+                                methods[i].desc);
 
-                        method->loadbios(dev, data);
-                        if (score_vbios(dev, data, method->rw))
+                        methods[i].loadbios(dev, data);
+                        if (score_vbios(dev, data, methods[i].rw))
                                 return true;
                 }
 
@@ -229,28 +228,24 @@ static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
         else
                 methods = nv50_methods;
 
-        method = methods;
-        while (method->loadbios) {
+        for (i = 0; i < METHODCNT; i++) {
                 NV_TRACE(dev, "Attempting to load BIOS image from %s\n",
-                         method->desc);
+                         methods[i].desc);
                 data[0] = data[1] = 0;  /* avoid reuse of previous image */
-                method->loadbios(dev, data);
-                method->score = score_vbios(dev, data, method->rw);
-                if (method->score == testscore)
+                methods[i].loadbios(dev, data);
+                scores[i] = score_vbios(dev, data, methods[i].rw);
+                if (scores[i] == testscore)
                         return true;
-                method++;
         }
 
         while (--testscore > 0) {
-                method = methods;
-                while (method->loadbios) {
-                        if (method->score == testscore) {
+                for (i = 0; i < METHODCNT; i++) {
+                        if (scores[i] == testscore) {
                                 NV_TRACE(dev, "Using BIOS image from %s\n",
-                                         method->desc);
-                                method->loadbios(dev, data);
+                                         methods[i].desc);
+                                methods[i].loadbios(dev, data);
                                 return true;
                         }
-                        method++;
                 }
         }
 
@@ -261,10 +256,7 @@ static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
 struct init_tbl_entry {
         char *name;
         uint8_t id;
-        int length;
-        int length_offset;
-        int length_multiplier;
-        bool (*handler)(struct nvbios *, uint16_t, struct init_exec *);
+        int (*handler)(struct nvbios *, uint16_t, struct init_exec *);
 };
 
 struct bit_entry {
@@ -820,7 +812,7 @@ static uint32_t get_tmds_index_reg(struct drm_device *dev, uint8_t mlv)
         }
 }
 
-static bool
+static int
 init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
                       struct init_exec *iexec)
 {
@@ -852,9 +844,10 @@ init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
         uint32_t reg = ROM32(bios->data[offset + 7]);
         uint8_t config;
         uint32_t configval;
+        int len = 11 + count * 4;
 
         if (!iexec->execute)
-                return true;
+                return len;
 
         BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
                       "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
@@ -865,7 +858,7 @@ init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
                 NV_ERROR(bios->dev,
                          "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
                          offset, config, count);
-                return false;
+                return 0;
         }
 
         configval = ROM32(bios->data[offset + 11 + config * 4]);
@@ -874,10 +867,10 @@ init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
 
         bios_wr32(bios, reg, configval);
 
-        return true;
+        return len;
 }
 
-static bool
+static int
 init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -912,10 +905,10 @@ init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 
         iexec->repeat = false;
 
-        return true;
+        return 2;
 }
 
-static bool
+static int
 init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
                      struct init_exec *iexec)
 {
@@ -951,9 +944,10 @@ init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
         uint32_t reg = ROM32(bios->data[offset + 8]);
         uint8_t config;
         uint16_t freq;
+        int len = 12 + count * 2;
 
         if (!iexec->execute)
-                return true;
+                return len;
 
         BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
                       "Shift: 0x%02X, IO Flag Condition: 0x%02X, "
@@ -966,7 +960,7 @@ init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
                 NV_ERROR(bios->dev,
                          "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
                          offset, config, count);
-                return false;
+                return 0;
         }
 
         freq = ROM16(bios->data[offset + 12 + config * 2]);
@@ -986,10 +980,10 @@ init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
 
         setPLL(bios, reg, freq * 10);
 
-        return true;
+        return len;
 }
 
-static bool
+static int
 init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -1007,12 +1001,12 @@ init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
          * we're not in repeat mode
          */
         if (iexec->repeat)
-                return false;
+                return 0;
 
-        return true;
+        return 1;
 }
 
-static bool
+static int
 init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -1041,7 +1035,7 @@ init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
         uint8_t crtcdata;
 
         if (!iexec->execute)
-                return true;
+                return 11;
 
         BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, "
                       "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
@@ -1060,10 +1054,10 @@ init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
         crtcdata |= (uint8_t)data;
         bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata);
 
-        return true;
+        return 11;
 }
 
-static bool
+static int
 init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -1079,10 +1073,10 @@ init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
                 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset);
 
         iexec->execute = !iexec->execute;
-        return true;
+        return 1;
 }
 
-static bool
+static int
 init_io_flag_condition(struct nvbios *bios, uint16_t offset,
                        struct init_exec *iexec)
 {
@@ -1100,7 +1094,7 @@ init_io_flag_condition(struct nvbios *bios, uint16_t offset,
         uint8_t cond = bios->data[offset + 1];
 
         if (!iexec->execute)
-                return true;
+                return 2;
 
         if (io_flag_condition_met(bios, offset, cond))
                 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
@@ -1109,10 +1103,10 @@ init_io_flag_condition(struct nvbios *bios, uint16_t offset,
                 iexec->execute = false;
         }
 
-        return true;
+        return 2;
 }
 
-static bool
+static int
 init_idx_addr_latched(struct nvbios *bios, uint16_t offset,
                       struct init_exec *iexec)
 {
@@ -1140,11 +1134,12 @@ init_idx_addr_latched(struct nvbios *bios, uint16_t offset,
         uint32_t mask = ROM32(bios->data[offset + 9]);
         uint32_t data = ROM32(bios->data[offset + 13]);
         uint8_t count = bios->data[offset + 17];
+        int len = 18 + count * 2;
         uint32_t value;
         int i;
 
         if (!iexec->execute)
-                return true;
+                return len;
 
         BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, "
                       "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
@@ -1164,10 +1159,10 @@ init_idx_addr_latched(struct nvbios *bios, uint16_t offset,
                 bios_wr32(bios, controlreg, value);
         }
 
-        return true;
+        return len;
 }
 
-static bool
+static int
 init_io_restrict_pll2(struct nvbios *bios, uint16_t offset,
                       struct init_exec *iexec)
 {
@@ -1196,25 +1191,26 @@ init_io_restrict_pll2(struct nvbios *bios, uint16_t offset,
         uint8_t shift = bios->data[offset + 5];
         uint8_t count = bios->data[offset + 6];
         uint32_t reg = ROM32(bios->data[offset + 7]);
+        int len = 11 + count * 4;
         uint8_t config;
         uint32_t freq;
 
         if (!iexec->execute)
-                return true;
+                return len;
 
         BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
                       "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
                 offset, crtcport, crtcindex, mask, shift, count, reg);
 
         if (!reg)
-                return true;
+                return len;
 
         config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
         if (config > count) {
                 NV_ERROR(bios->dev,
                          "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
                          offset, config, count);
-                return false;
+                return 0;
         }
 
         freq = ROM32(bios->data[offset + 11 + config * 4]);
@@ -1224,10 +1220,10 @@ init_io_restrict_pll2(struct nvbios *bios, uint16_t offset,
 
         setPLL(bios, reg, freq);
 
-        return true;
+        return len;
 }
 
-static bool
+static int
 init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -1244,16 +1240,16 @@ init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
         uint32_t freq = ROM32(bios->data[offset + 5]);
 
         if (!iexec->execute)
-                return true;
+                return 9;
 
         BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
                 offset, reg, freq);
 
         setPLL(bios, reg, freq);
-        return true;
+        return 9;
 }
 
-static bool
+static int
 init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -1277,12 +1273,13 @@ init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
         uint8_t i2c_index = bios->data[offset + 1];
         uint8_t i2c_address = bios->data[offset + 2];
         uint8_t count = bios->data[offset + 3];
+        int len = 4 + count * 3;
         struct nouveau_i2c_chan *chan;
         struct i2c_msg msg;
         int i;
 
         if (!iexec->execute)
-                return true;
+                return len;
 
         BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
                       "Count: 0x%02X\n",
@@ -1290,7 +1287,7 @@ init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 
         chan = init_i2c_device_find(bios->dev, i2c_index);
         if (!chan)
-                return false;
+                return 0;
 
         for (i = 0; i < count; i++) {
                 uint8_t i2c_reg = bios->data[offset + 4 + i * 3];
@@ -1303,7 +1300,7 @@ init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
                 msg.len = 1;
                 msg.buf = &value;
                 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
-                        return false;
+                        return 0;
 
                 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
                               "Mask: 0x%02X, Data: 0x%02X\n",
@@ -1317,14 +1314,14 @@ init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
                         msg.len = 1;
                         msg.buf = &value;
                         if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
-                                return false;
+                                return 0;
                 }
         }
 
-        return true;
+        return len;
 }
 
-static bool
+static int
 init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -1346,12 +1343,13 @@ init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
         uint8_t i2c_index = bios->data[offset + 1];
         uint8_t i2c_address = bios->data[offset + 2];
         uint8_t count = bios->data[offset + 3];
+        int len = 4 + count * 2;
         struct nouveau_i2c_chan *chan;
         struct i2c_msg msg;
         int i;
 
         if (!iexec->execute)
-                return true;
+                return len;
 
         BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
                       "Count: 0x%02X\n",
@@ -1359,7 +1357,7 @@ init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 
         chan = init_i2c_device_find(bios->dev, i2c_index);
         if (!chan)
-                return false;
+                return 0;
 
         for (i = 0; i < count; i++) {
                 uint8_t i2c_reg = bios->data[offset + 4 + i * 2];
@@ -1374,14 +1372,14 @@ init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
                         msg.len = 1;
                         msg.buf = &data;
                         if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
-                                return false;
+                                return 0;
                 }
         }
 
-        return true;
+        return len;
 }
 
-static bool
+static int
 init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -1401,13 +1399,14 @@ init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
         uint8_t i2c_index = bios->data[offset + 1];
         uint8_t i2c_address = bios->data[offset + 2];
         uint8_t count = bios->data[offset + 3];
+        int len = 4 + count;
         struct nouveau_i2c_chan *chan;
         struct i2c_msg msg;
         uint8_t data[256];
         int i;
 
         if (!iexec->execute)
-                return true;
+                return len;
 
         BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
                       "Count: 0x%02X\n",
@@ -1415,7 +1414,7 @@ init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 
         chan = init_i2c_device_find(bios->dev, i2c_index);
         if (!chan)
-                return false;
+                return 0;
 
         for (i = 0; i < count; i++) {
                 data[i] = bios->data[offset + 4 + i];
@@ -1429,13 +1428,13 @@ init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
                 msg.len = count;
                 msg.buf = data;
                 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
-                        return false;
+                        return 0;
         }
 
-        return true;
+        return len;
 }
 
-static bool
+static int
 init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -1460,7 +1459,7 @@ init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
         uint32_t reg, value;
 
         if (!iexec->execute)
-                return true;
+                return 5;
 
         BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, "
                       "Mask: 0x%02X, Data: 0x%02X\n",
@@ -1468,7 +1467,7 @@ init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 
         reg = get_tmds_index_reg(bios->dev, mlv);
         if (!reg)
-                return false;
+                return 0;
 
         bios_wr32(bios, reg,
                   tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
@@ -1476,10 +1475,10 @@ init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
         bios_wr32(bios, reg + 4, value);
         bios_wr32(bios, reg, tmdsaddr);
 
-        return true;
+        return 5;
 }
 
-static bool
+static int
 init_zm_tmds_group(struct nvbios *bios, uint16_t offset,
                    struct init_exec *iexec)
 {
@@ -1500,18 +1499,19 @@ init_zm_tmds_group(struct nvbios *bios, uint16_t offset,
 
         uint8_t mlv = bios->data[offset + 1];
         uint8_t count = bios->data[offset + 2];
+        int len = 3 + count * 2;
         uint32_t reg;
         int i;
 
         if (!iexec->execute)
-                return true;
+                return len;
 
         BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
                 offset, mlv, count);
 
         reg = get_tmds_index_reg(bios->dev, mlv);
         if (!reg)
-                return false;
+                return 0;
 
         for (i = 0; i < count; i++) {
                 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
@@ -1521,10 +1521,10 @@ init_zm_tmds_group(struct nvbios *bios, uint16_t offset,
                 bios_wr32(bios, reg, tmdsaddr);
         }
 
-        return true;
+        return len;
 }
 
-static bool
+static int
 init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset,
                       struct init_exec *iexec)
 {
@@ -1547,11 +1547,12 @@ init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset,
         uint8_t crtcindex2 = bios->data[offset + 2];
         uint8_t baseaddr = bios->data[offset + 3];
         uint8_t count = bios->data[offset + 4];
+        int len = 5 + count;
         uint8_t oldaddr, data;
         int i;
 
         if (!iexec->execute)
-                return true;
+                return len;
 
         BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, "
                       "BaseAddr: 0x%02X, Count: 0x%02X\n",
@@ -1568,10 +1569,10 @@ init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset,
 
         bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr);
 
-        return true;
+        return len;
 }
 
-static bool
+static int
 init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -1592,7 +1593,7 @@ init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
         uint8_t value;
 
         if (!iexec->execute)
-                return true;
+                return 4;
 
         BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
                 offset, crtcindex, mask, data);
@@ -1601,10 +1602,10 @@ init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
         value |= data;
         bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value);
 
-        return true;
+        return 4;
 }
 
-static bool
+static int
 init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -1621,14 +1622,14 @@ init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
         uint8_t data = bios->data[offset + 2];
 
         if (!iexec->execute)
-                return true;
+                return 3;
 
         bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data);
 
-        return true;
+        return 3;
 }
 
-static bool
+static int
 init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -1645,18 +1646,19 @@ init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
          */
 
         uint8_t count = bios->data[offset + 1];
+        int len = 2 + count * 2;
         int i;
 
         if (!iexec->execute)
-                return true;
+                return len;
 
         for (i = 0; i < count; i++)
                 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec);
 
-        return true;
+        return len;
 }
 
-static bool
+static int
 init_condition_time(struct nvbios *bios, uint16_t offset,
                     struct init_exec *iexec)
 {
@@ -1680,7 +1682,7 @@ init_condition_time(struct nvbios *bios, uint16_t offset,
         unsigned cnt;
 
         if (!iexec->execute)
-                return true;
+                return 3;
 
         if (retries > 100)
                 retries = 100;
@@ -1711,10 +1713,10 @@ init_condition_time(struct nvbios *bios, uint16_t offset,
                 iexec->execute = false;
         }
 
-        return true;
+        return 3;
 }
 
-static bool
+static int
 init_zm_reg_sequence(struct nvbios *bios, uint16_t offset,
                      struct init_exec *iexec)
 {
@@ -1734,10 +1736,11 @@ init_zm_reg_sequence(struct nvbios *bios, uint16_t offset,
 
         uint32_t basereg = ROM32(bios->data[offset + 1]);
         uint32_t count = bios->data[offset + 5];
+        int len = 6 + count * 4;
         int i;
 
         if (!iexec->execute)
-                return true;
+                return len;
 
         BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
                 offset, basereg, count);
@@ -1749,10 +1752,10 @@ init_zm_reg_sequence(struct nvbios *bios, uint16_t offset,
                 bios_wr32(bios, reg, data);
         }
 
-        return true;
+        return len;
 }
 
-static bool
+static int
 init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -1768,7 +1771,7 @@ init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
         uint16_t sub_offset = ROM16(bios->data[offset + 1]);
 
         if (!iexec->execute)
-                return true;
+                return 3;
 
         BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n",
                 offset, sub_offset);
@@ -1777,10 +1780,10 @@ init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 
         BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset);
 
-        return true;
+        return 3;
 }
 
-static bool
+static int
 init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -1808,7 +1811,7 @@ init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
         uint32_t srcvalue, dstvalue;
 
         if (!iexec->execute)
-                return true;
+                return 22;
 
         BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, "
                       "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
@@ -1827,10 +1830,10 @@ init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 
         bios_wr32(bios, dstreg, dstvalue | srcvalue);
 
-        return true;
+        return 22;
 }
 
-static bool
+static int
 init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -1848,14 +1851,14 @@ init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
         uint8_t data = bios->data[offset + 4];
 
         if (!iexec->execute)
-                return true;
+                return 5;
 
         bios_idxprt_wr(bios, crtcport, crtcindex, data);
 
-        return true;
+        return 5;
 }
 
-static bool
+static int
 init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -1904,7 +1907,7 @@ init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
         struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
 
         if (dev_priv->card_type >= NV_50)
-                return true;
+                return 1;
 
         /*
          * On every card I've seen, this step gets done for us earlier in
@@ -1922,10 +1925,10 @@ init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
         /* write back the saved configuration value */
         bios_wr32(bios, NV_PFB_CFG0, bios->state.saved_nv_pfb_cfg0);
 
-        return true;
+        return 1;
 }
 
-static bool
+static int
 init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -1959,10 +1962,10 @@ init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
         pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;     /* 0xfffffffe */
         bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20);
 
-        return true;
+        return 13;
 }
 
-static bool
+static int
 init_configure_mem(struct nvbios *bios, uint16_t offset,
                    struct init_exec *iexec)
 {
@@ -1983,7 +1986,7 @@ init_configure_mem(struct nvbios *bios, uint16_t offset,
         uint32_t reg, data;
 
         if (bios->major_version > 2)
-                return false;
+                return 0;
 
         bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd(
                        bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20);
@@ -2015,10 +2018,10 @@ init_configure_mem(struct nvbios *bios, uint16_t offset,
                 bios_wr32(bios, reg, data);
         }
 
-        return true;
+        return 1;
 }
 
-static bool
+static int
 init_configure_clk(struct nvbios *bios, uint16_t offset,
                    struct init_exec *iexec)
 {
@@ -2038,7 +2041,7 @@ init_configure_clk(struct nvbios *bios, uint16_t offset,
         int clock;
 
         if (bios->major_version > 2)
-                return false;
+                return 0;
 
         clock = ROM16(bios->data[meminitoffs + 4]) * 10;
         setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock);
@@ -2048,10 +2051,10 @@ init_configure_clk(struct nvbios *bios, uint16_t offset,
                 clock *= 2;
         setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock);
 
-        return true;
+        return 1;
 }
 
-static bool
+static int
 init_configure_preinit(struct nvbios *bios, uint16_t offset,
                        struct init_exec *iexec)
 {
@@ -2071,15 +2074,15 @@ init_configure_preinit(struct nvbios *bios, uint16_t offset,
         uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & (1 << 6));
 
         if (bios->major_version > 2)
-                return false;
+                return 0;
 
         bios_idxprt_wr(bios, NV_CIO_CRX__COLOR,
                              NV_CIO_CRE_SCRATCH4__INDEX, cr3c);
 
-        return true;
+        return 1;
 }
 
-static bool
+static int
 init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -2099,7 +2102,7 @@ init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
         uint8_t data = bios->data[offset + 4];
 
         if (!iexec->execute)
-                return true;
+                return 5;
 
         BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
                 offset, crtcport, mask, data);
@@ -2158,15 +2161,15 @@ init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
                 for (i = 0; i < 2; i++)
                         bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32(
                                   bios, 0x614108 + (i*0x800)) & 0x0fffffff);
-                return true;
+                return 5;
         }
 
         bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) |
                                                                         data);
-        return true;
+        return 5;
 }
 
-static bool
+static int
 init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -2181,7 +2184,7 @@ init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
         uint8_t sub = bios->data[offset + 1];
 
         if (!iexec->execute)
-                return true;
+                return 2;
 
         BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub);
 
@@ -2191,10 +2194,10 @@ init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 
         BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub);
 
-        return true;
+        return 2;
 }
 
-static bool
+static int
 init_ram_condition(struct nvbios *bios, uint16_t offset,
                    struct init_exec *iexec)
 {
@@ -2215,7 +2218,7 @@ init_ram_condition(struct nvbios *bios, uint16_t offset,
         uint8_t data;
 
         if (!iexec->execute)
-                return true;
+                return 3;
 
         data = bios_rd32(bios, NV_PFB_BOOT_0) & mask;
 
@@ -2229,10 +2232,10 @@ init_ram_condition(struct nvbios *bios, uint16_t offset,
                 iexec->execute = false;
         }
 
-        return true;
+        return 3;
 }
 
-static bool
+static int
 init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -2251,17 +2254,17 @@ init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
         uint32_t data = ROM32(bios->data[offset + 9]);
 
         if (!iexec->execute)
-                return true;
+                return 13;
 
         BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
                 offset, reg, mask, data);
 
         bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data);
 
-        return true;
+        return 13;
 }
 
-static bool
+static int
 init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -2285,7 +2288,7 @@ init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
         int i;
 
         if (!iexec->execute)
-                return true;
+                return 2;
 
         BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, "
                       "Count: 0x%02X\n",
@@ -2300,10 +2303,10 @@ init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
                 bios_wr32(bios, reg, data);
         }
 
-        return true;
+        return 2;
 }
 
-static bool
+static int
 init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -2315,10 +2318,10 @@ init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
          */
 
         /* mild retval abuse to stop parsing this table */
-        return false;
+        return 0;
 }
 
-static bool
+static int
 init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -2330,15 +2333,15 @@ init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
          */
 
         if (iexec->execute)
-                return true;
+                return 1;
 
         iexec->execute = true;
         BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset);
 
-        return true;
+        return 1;
 }
 
-static bool
+static int
 init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -2353,7 +2356,7 @@ init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
         unsigned time = ROM16(bios->data[offset + 1]);
 
         if (!iexec->execute)
-                return true;
+                return 3;
 
         BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n",
                 offset, time);
@@ -2363,10 +2366,10 @@ init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
         else
                 msleep((time + 900) / 1000);
 
-        return true;
+        return 3;
 }
 
-static bool
+static int
 init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -2383,7 +2386,7 @@ init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
         uint8_t cond = bios->data[offset + 1];
 
         if (!iexec->execute)
-                return true;
+                return 2;
 
         BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond);
 
@@ -2394,10 +2397,10 @@ init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
                 iexec->execute = false;
         }
 
-        return true;
+        return 2;
 }
 
-static bool
+static int
 init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -2414,7 +2417,7 @@ init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
         uint8_t cond = bios->data[offset + 1];
 
         if (!iexec->execute)
-                return true;
+                return 2;
 
         BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond);
 
@@ -2425,10 +2428,10 @@ init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
                 iexec->execute = false;
         }
 
-        return true;
+        return 2;
 }
 
-static bool
+static int
 init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -2451,7 +2454,7 @@ init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
         uint8_t value;
 
         if (!iexec->execute)
-                return true;
+                return 6;
 
         BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
                       "Data: 0x%02X\n",
@@ -2460,10 +2463,10 @@ init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
         value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data;
         bios_idxprt_wr(bios, crtcport, crtcindex, value);
 
-        return true;
+        return 6;
 }
 
-static bool
+static int
 init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -2481,16 +2484,16 @@ init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
         uint16_t freq = ROM16(bios->data[offset + 5]);
 
         if (!iexec->execute)
-                return true;
+                return 7;
 
         BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq);
 
         setPLL(bios, reg, freq * 10);
 
-        return true;
+        return 7;
 }
 
-static bool
+static int
 init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -2507,17 +2510,17 @@ init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
         uint32_t value = ROM32(bios->data[offset + 5]);
 
         if (!iexec->execute)
-                return true;
+                return 9;
 
         if (reg == 0x000200)
                 value |= 1;
 
         bios_wr32(bios, reg, value);
 
-        return true;
+        return 9;
 }
 
-static bool
+static int
 init_ram_restrict_pll(struct nvbios *bios, uint16_t offset,
                       struct init_exec *iexec)
 {
@@ -2543,14 +2546,15 @@ init_ram_restrict_pll(struct nvbios *bios, uint16_t offset,
         uint8_t type = bios->data[offset + 1];
         uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]);
         uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry;
+        int len = 2 + bios->ram_restrict_group_count * 4;
         int i;
 
         if (!iexec->execute)
-                return true;
+                return len;
 
         if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) {
                 NV_ERROR(dev, "PLL limits table not version 3.x\n");
-                return true; /* deliberate, allow default clocks to remain */
+                return len; /* deliberate, allow default clocks to remain */
         }
 
         entry = pll_limits + pll_limits[1];
@@ -2563,15 +2567,15 @@ init_ram_restrict_pll(struct nvbios *bios, uint16_t offset,
                                 offset, type, reg, freq);
 
                         setPLL(bios, reg, freq);
-                        return true;
+                        return len;
                 }
         }
 
         NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type);
-        return true;
+        return len;
 }
 
-static bool
+static int
 init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -2581,10 +2585,10 @@ init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
          *
          */
 
-        return true;
+        return 1;
 }
 
-static bool
+static int
 init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -2594,10 +2598,10 @@ init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
          *
          */
 
-        return true;
+        return 1;
 }
 
-static bool
+static int
 init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -2615,14 +2619,17 @@ init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
         const uint8_t *gpio_entry;
         int i;
 
+        if (!iexec->execute)
+                return 1;
+
         if (bios->bdcb.version != 0x40) {
                 NV_ERROR(bios->dev, "DCB table not version 4.0\n");
-                return false;
+                return 0;
         }
 
         if (!bios->bdcb.gpio_table_ptr) {
                 NV_WARN(bios->dev, "Invalid pointer to INIT_8E table\n");
-                return false;
+                return 0;
         }
 
         gpio_entry = gpio_table + gpio_table[1];
@@ -2660,13 +2667,10 @@ init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
                 bios_wr32(bios, r, v);
         }
 
-        return true;
+        return 1;
 }
 
-/* hack to avoid moving the itbl_entry array before this function */
-int init_ram_restrict_zm_reg_group_blocklen;
-
-static bool
+static int
 init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset,
                                struct init_exec *iexec)
 {
@@ -2692,21 +2696,21 @@ init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset,
         uint8_t regincrement = bios->data[offset + 5];
         uint8_t count = bios->data[offset + 6];
         uint32_t strap_ramcfg, data;
-        uint16_t blocklen;
+        /* previously set by 'M' BIT table */
+        uint16_t blocklen = bios->ram_restrict_group_count * 4;
+        int len = 7 + count * blocklen;
         uint8_t index;
         int i;
 
-        /* previously set by 'M' BIT table */
-        blocklen = init_ram_restrict_zm_reg_group_blocklen;
 
         if (!iexec->execute)
-                return true;
+                return len;
 
         if (!blocklen) {
                 NV_ERROR(bios->dev,
                          "0x%04X: Zero block length - has the M table "
                          "been parsed?\n", offset);
-                return false;
+                return 0;
         }
 
         strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
@@ -2724,10 +2728,10 @@ init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset,
                 reg += regincrement;
         }
 
-        return true;
+        return len;
 }
 
-static bool
+static int
 init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -2744,14 +2748,14 @@ init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
         uint32_t dstreg = ROM32(bios->data[offset + 5]);
 
         if (!iexec->execute)
-                return true;
+                return 9;
 
         bios_wr32(bios, dstreg, bios_rd32(bios, srcreg));
 
-        return true;
+        return 9;
 }
 
-static bool
+static int
 init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset,
                                struct init_exec *iexec)
 {
@@ -2769,20 +2773,21 @@ init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset,
 
         uint32_t reg = ROM32(bios->data[offset + 1]);
         uint8_t count = bios->data[offset + 5];
+        int len = 6 + count * 4;
         int i;
 
         if (!iexec->execute)
-                return true;
+                return len;
 
         for (i = 0; i < count; i++) {
                 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]);
                 bios_wr32(bios, reg, data);
         }
 
-        return true;
+        return len;
 }
 
-static bool
+static int
 init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -2793,10 +2798,10 @@ init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
          * Seemingly does nothing
          */
 
-        return true;
+        return 1;
 }
 
-static bool
+static int
 init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -2829,13 +2834,13 @@ init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
         val <<= bios->data[offset + 16];
 
         if (!iexec->execute)
-                return true;
+                return 17;
 
         bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val);
-        return true;
+        return 17;
 }
 
-static bool
+static int
 init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -2859,13 +2864,13 @@ init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
         val = (val & mask) | ((val + add) & ~mask);
 
         if (!iexec->execute)
-                return true;
+                return 13;
 
         bios_wr32(bios, reg, val);
-        return true;
+        return 13;
 }
 
-static bool
+static int
 init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -2883,32 +2888,33 @@ init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
         struct drm_device *dev = bios->dev;
         struct nouveau_i2c_chan *auxch;
         uint32_t addr = ROM32(bios->data[offset + 1]);
-        uint8_t len = bios->data[offset + 5];
+        uint8_t count = bios->data[offset + 5];
+        int len = 6 + count * 2;
         int ret, i;
 
         if (!bios->display.output) {
                 NV_ERROR(dev, "INIT_AUXCH: no active output\n");
-                return false;
+                return 0;
         }
 
         auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
         if (!auxch) {
                 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n",
                          bios->display.output->i2c_index);
-                return false;
+                return 0;
         }
 
         if (!iexec->execute)
-                return true;
+                return len;
 
         offset += 6;
-        for (i = 0; i < len; i++, offset += 2) {
+        for (i = 0; i < count; i++, offset += 2) {
                 uint8_t data;
 
                 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1);
                 if (ret) {
                         NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret);
-                        return false;
+                        return 0;
                 }
 
                 data &= bios->data[offset + 0];
@@ -2917,14 +2923,14 @@ init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
                 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1);
                 if (ret) {
                         NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret);
-                        return false;
+                        return 0;
                 }
         }
 
-        return true;
+        return len;
 }
 
-static bool
+static int
 init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -2941,106 +2947,99 @@ init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
         struct drm_device *dev = bios->dev;
         struct nouveau_i2c_chan *auxch;
         uint32_t addr = ROM32(bios->data[offset + 1]);
-        uint8_t len = bios->data[offset + 5];
+        uint8_t count = bios->data[offset + 5];
+        int len = 6 + count;
         int ret, i;
 
         if (!bios->display.output) {
                 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n");
-                return false;
+                return 0;
         }
 
         auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
         if (!auxch) {
                 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n",
                          bios->display.output->i2c_index);
-                return false;
+                return 0;
         }
 
         if (!iexec->execute)
-                return true;
+                return len;
 
         offset += 6;
-        for (i = 0; i < len; i++, offset++) {
+        for (i = 0; i < count; i++, offset++) {
                 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1);
                 if (ret) {
                         NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret);
-                        return false;
+                        return 0;
                 }
         }
 
-        return true;
+        return len;
 }
 
 static struct init_tbl_entry itbl_entry[] = {
         /* command name                       , id  , length  , offset  , mult    , command handler                 */
         /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */
-        { "INIT_IO_RESTRICT_PROG"             , 0x32, 11      , 6       , 4       , init_io_restrict_prog           },
-        { "INIT_REPEAT"                       , 0x33, 2       , 0       , 0       , init_repeat                     },
-        { "INIT_IO_RESTRICT_PLL"              , 0x34, 12      , 7       , 2       , init_io_restrict_pll            },
-        { "INIT_END_REPEAT"                   , 0x36, 1       , 0       , 0       , init_end_repeat                 },
-        { "INIT_COPY"                         , 0x37, 11      , 0       , 0       , init_copy                       },
-        { "INIT_NOT"                          , 0x38, 1       , 0       , 0       , init_not                        },
-        { "INIT_IO_FLAG_CONDITION"            , 0x39, 2       , 0       , 0       , init_io_flag_condition          },
-        { "INIT_INDEX_ADDRESS_LATCHED"        , 0x49, 18      , 17      , 2       , init_idx_addr_latched           },
-        { "INIT_IO_RESTRICT_PLL2"             , 0x4A, 11      , 6       , 4       , init_io_restrict_pll2           },
-        { "INIT_PLL2"                         , 0x4B, 9       , 0       , 0       , init_pll2                       },
-        { "INIT_I2C_BYTE"                     , 0x4C, 4       , 3       , 3       , init_i2c_byte                   },
-        { "INIT_ZM_I2C_BYTE"                  , 0x4D, 4       , 3       , 2       , init_zm_i2c_byte                },
-        { "INIT_ZM_I2C"                       , 0x4E, 4       , 3       , 1       , init_zm_i2c                     },
-        { "INIT_TMDS"                         , 0x4F, 5       , 0       , 0       , init_tmds                       },
-        { "INIT_ZM_TMDS_GROUP"                , 0x50, 3       , 2       , 2       , init_zm_tmds_group              },
-        { "INIT_CR_INDEX_ADDRESS_LATCHED"     , 0x51, 5       , 4       , 1       , init_cr_idx_adr_latch           },
-        { "INIT_CR"                           , 0x52, 4       , 0       , 0       , init_cr                         },
-        { "INIT_ZM_CR"                        , 0x53, 3       , 0       , 0       , init_zm_cr                      },
-        { "INIT_ZM_CR_GROUP"                  , 0x54, 2       , 1       , 2       , init_zm_cr_group                },
-        { "INIT_CONDITION_TIME"               , 0x56, 3       , 0       , 0       , init_condition_time             },
-        { "INIT_ZM_REG_SEQUENCE"              , 0x58, 6       , 5       , 4       , init_zm_reg_sequence            },
+        { "INIT_IO_RESTRICT_PROG"             , 0x32, init_io_restrict_prog           },
+        { "INIT_REPEAT"                       , 0x33, init_repeat                     },
+        { "INIT_IO_RESTRICT_PLL"              , 0x34, init_io_restrict_pll            },
+        { "INIT_END_REPEAT"                   , 0x36, init_end_repeat                 },
+        { "INIT_COPY"                         , 0x37, init_copy                       },
+        { "INIT_NOT"                          , 0x38, init_not                        },
+        { "INIT_IO_FLAG_CONDITION"            , 0x39, init_io_flag_condition          },
+        { "INIT_INDEX_ADDRESS_LATCHED"        , 0x49, init_idx_addr_latched           },
+        { "INIT_IO_RESTRICT_PLL2"             , 0x4A, init_io_restrict_pll2           },
+        { "INIT_PLL2"                         , 0x4B, init_pll2                       },
+        { "INIT_I2C_BYTE"                     , 0x4C, init_i2c_byte                   },
+        { "INIT_ZM_I2C_BYTE"                  , 0x4D, init_zm_i2c_byte                },
+        { "INIT_ZM_I2C"                       , 0x4E, init_zm_i2c                     },
+        { "INIT_TMDS"                         , 0x4F, init_tmds                       },
+        { "INIT_ZM_TMDS_GROUP"                , 0x50, init_zm_tmds_group              },
+        { "INIT_CR_INDEX_ADDRESS_LATCHED"     , 0x51, init_cr_idx_adr_latch           },
+        { "INIT_CR"                           , 0x52, init_cr                         },
+        { "INIT_ZM_CR"                        , 0x53, init_zm_cr                      },
+        { "INIT_ZM_CR_GROUP"                  , 0x54, init_zm_cr_group                },
+        { "INIT_CONDITION_TIME"               , 0x56, init_condition_time             },
+        { "INIT_ZM_REG_SEQUENCE"              , 0x58, init_zm_reg_sequence            },
         /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */
-        { "INIT_SUB_DIRECT"                   , 0x5B, 3       , 0       , 0       , init_sub_direct                 },
-        { "INIT_COPY_NV_REG"                  , 0x5F, 22      , 0       , 0       , init_copy_nv_reg                },
-        { "INIT_ZM_INDEX_IO"                  , 0x62, 5       , 0       , 0       , init_zm_index_io                },
-        { "INIT_COMPUTE_MEM"                  , 0x63, 1       , 0       , 0       , init_compute_mem                },
-        { "INIT_RESET"                        , 0x65, 13      , 0       , 0       , init_reset                      },
-        { "INIT_CONFIGURE_MEM"                , 0x66, 1       , 0       , 0       , init_configure_mem              },
-        { "INIT_CONFIGURE_CLK"                , 0x67, 1       , 0       , 0       , init_configure_clk              },
-        { "INIT_CONFIGURE_PREINIT"            , 0x68, 1       , 0       , 0       , init_configure_preinit          },
-        { "INIT_IO"                           , 0x69, 5       , 0       , 0       , init_io                         },
-        { "INIT_SUB"                          , 0x6B, 2       , 0       , 0       , init_sub                        },
-        { "INIT_RAM_CONDITION"                , 0x6D, 3       , 0       , 0       , init_ram_condition              },
-        { "INIT_NV_REG"                       , 0x6E, 13      , 0       , 0       , init_nv_reg                     },
-        { "INIT_MACRO"                        , 0x6F, 2       , 0       , 0       , init_macro                      },
-        { "INIT_DONE"                         , 0x71, 1       , 0       , 0       , init_done                       },
-        { "INIT_RESUME"                       , 0x72, 1       , 0       , 0       , init_resume                     },
+        { "INIT_SUB_DIRECT"                   , 0x5B, init_sub_direct                 },
+        { "INIT_COPY_NV_REG"                  , 0x5F, init_copy_nv_reg                },
+        { "INIT_ZM_INDEX_IO"                  , 0x62, init_zm_index_io                },
+        { "INIT_COMPUTE_MEM"                  , 0x63, init_compute_mem                },
+        { "INIT_RESET"                        , 0x65, init_reset                      },
+        { "INIT_CONFIGURE_MEM"                , 0x66, init_configure_mem              },
+        { "INIT_CONFIGURE_CLK"                , 0x67, init_configure_clk              },
+        { "INIT_CONFIGURE_PREINIT"            , 0x68, init_configure_preinit          },
+        { "INIT_IO"                           , 0x69, init_io                         },
+        { "INIT_SUB"                          , 0x6B, init_sub                        },
+        { "INIT_RAM_CONDITION"                , 0x6D, init_ram_condition              },
+        { "INIT_NV_REG"                       , 0x6E, init_nv_reg                     },
+        { "INIT_MACRO"                        , 0x6F, init_macro                      },
+        { "INIT_DONE"                         , 0x71, init_done                       },
+        { "INIT_RESUME"                       , 0x72, init_resume                     },
         /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */
-        { "INIT_TIME"                         , 0x74, 3       , 0       , 0       , init_time                       },
-        { "INIT_CONDITION"                    , 0x75, 2       , 0       , 0       , init_condition                  },
-        { "INIT_IO_CONDITION"                 , 0x76, 2       , 0       , 0       , init_io_condition               },
-        { "INIT_INDEX_IO"                     , 0x78, 6       , 0       , 0       , init_index_io                   },
-        { "INIT_PLL"                          , 0x79, 7       , 0       , 0       , init_pll                        },
-        { "INIT_ZM_REG"                       , 0x7A, 9       , 0       , 0       , init_zm_reg                     },
-        /* INIT_RAM_RESTRICT_PLL's length is adjusted by the BIT M table */
-        { "INIT_RAM_RESTRICT_PLL"             , 0x87, 2       , 0       , 0       , init_ram_restrict_pll           },
-        { "INIT_8C"                           , 0x8C, 1       , 0       , 0       , init_8c                         },
-        { "INIT_8D"                           , 0x8D, 1       , 0       , 0       , init_8d                         },
-        { "INIT_GPIO"                         , 0x8E, 1       , 0       , 0       , init_gpio                       },
-        /* INIT_RAM_RESTRICT_ZM_REG_GROUP's mult is loaded by M table in BIT */
-        { "INIT_RAM_RESTRICT_ZM_REG_GROUP"    , 0x8F, 7       , 6       , 0       , init_ram_restrict_zm_reg_group  },
-        { "INIT_COPY_ZM_REG"                  , 0x90, 9       , 0       , 0       , init_copy_zm_reg                },
-        { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, 6       , 5       , 4       , init_zm_reg_group_addr_latched  },
-        { "INIT_RESERVED"                     , 0x92, 1       , 0       , 0       , init_reserved                   },
-        { "INIT_96"                           , 0x96, 17      , 0       , 0       , init_96                         },
-        { "INIT_97"                           , 0x97, 13      , 0       , 0       , init_97                         },
-        { "INIT_AUXCH"                        , 0x98, 6       , 5       , 2       , init_auxch                      },
-        { "INIT_ZM_AUXCH"                     , 0x99, 6       , 5       , 1       , init_zm_auxch                   },
-        { NULL                                , 0   , 0       , 0       , 0       , NULL                            }
+        { "INIT_TIME"                         , 0x74, init_time                       },
+        { "INIT_CONDITION"                    , 0x75, init_condition                  },
+        { "INIT_IO_CONDITION"                 , 0x76, init_io_condition               },
+        { "INIT_INDEX_IO"                     , 0x78, init_index_io                   },
+        { "INIT_PLL"                          , 0x79, init_pll                        },
+        { "INIT_ZM_REG"                       , 0x7A, init_zm_reg                     },
+        { "INIT_RAM_RESTRICT_PLL"             , 0x87, init_ram_restrict_pll           },
+        { "INIT_8C"                           , 0x8C, init_8c                         },
+        { "INIT_8D"                           , 0x8D, init_8d                         },
+        { "INIT_GPIO"                         , 0x8E, init_gpio                       },
+        { "INIT_RAM_RESTRICT_ZM_REG_GROUP"    , 0x8F, init_ram_restrict_zm_reg_group  },
+        { "INIT_COPY_ZM_REG"                  , 0x90, init_copy_zm_reg                },
+        { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched  },
+        { "INIT_RESERVED"                     , 0x92, init_reserved                   },
+        { "INIT_96"                           , 0x96, init_96                         },
+        { "INIT_97"                           , 0x97, init_97                         },
+        { "INIT_AUXCH"                        , 0x98, init_auxch                      },
+        { "INIT_ZM_AUXCH"                     , 0x99, init_zm_auxch                   },
+        { NULL                                , 0   , NULL                            }
 };
 
-static unsigned int get_init_table_entry_length(struct nvbios *bios, unsigned int offset, int i)
-{
-        /* Calculates the length of a given init table entry. */
-        return itbl_entry[i].length + bios->data[offset + itbl_entry[i].length_offset]*itbl_entry[i].length_multiplier;
-}
-
 #define MAX_TABLE_OPS 1000
 
 static int
@@ -3056,7 +3055,7 @@ parse_init_table(struct nvbios *bios, unsigned int offset,
          * is changed back to EXECUTE.
          */
 
-        int count = 0, i;
+        int count = 0, i, res;
         uint8_t id;
 
         /*
@@ -3076,22 +3075,21 @@ parse_init_table(struct nvbios *bios, unsigned int offset,
                                 offset, itbl_entry[i].id, itbl_entry[i].name);
 
                         /* execute eventual command handler */
-                        if (itbl_entry[i].handler)
-                                if (!(*itbl_entry[i].handler)(bios, offset, iexec))
-                                        break;
+                        res = (*itbl_entry[i].handler)(bios, offset, iexec);
+                        if (!res)
+                                break;
+                        /*
+                         * Add the offset of the current command including all data
+                         * of that command. The offset will then be pointing on the
+                         * next op code.
+                         */
+                        offset += res;
                 } else {
                         NV_ERROR(bios->dev,
                                  "0x%04X: Init table command not found: "
                                  "0x%02X\n", offset, id);
                         return -ENOENT;
                 }
-
-                /*
-                 * Add the offset of the current command including all data
-                 * of that command. The offset will then be pointing on the
-                 * next op code.
-                 */
-                offset += get_init_table_entry_length(bios, offset, i);
         }
 
         if (offset >= bios->length)
@@ -3854,7 +3852,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
          * script tables is a pointer to the script to execute.
          */
 
-        NV_DEBUG(dev, "Searching for output entry for %d %d %d\n",
+        NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n",
                         dcbent->type, dcbent->location, dcbent->or);
         otable = bios_output_config_match(dev, dcbent, table[1] +
                                           bios->display.script_table_ptr,
@@ -3884,7 +3882,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
         if (pxclk == 0) {
                 script = ROM16(otable[6]);
                 if (!script) {
-                        NV_DEBUG(dev, "output script 0 not found\n");
+                        NV_DEBUG_KMS(dev, "output script 0 not found\n");
                         return 1;
                 }
 
@@ -3894,7 +3892,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
         if (pxclk == -1) {
                 script = ROM16(otable[8]);
                 if (!script) {
-                        NV_DEBUG(dev, "output script 1 not found\n");
+                        NV_DEBUG_KMS(dev, "output script 1 not found\n");
                         return 1;
                 }
 
@@ -3907,7 +3905,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
                 else
                         script = 0;
                 if (!script) {
-                        NV_DEBUG(dev, "output script 2 not found\n");
+                        NV_DEBUG_KMS(dev, "output script 2 not found\n");
                         return 1;
                 }
 
@@ -3931,7 +3929,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
                 if (script)
                         script = clkcmptable(bios, script, -pxclk);
                 if (!script) {
-                        NV_DEBUG(dev, "clock script 1 not found\n");
+                        NV_DEBUG_KMS(dev, "clock script 1 not found\n");
                         return 1;
                 }
 
@@ -4606,10 +4604,6 @@ parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios,
          * stuff that we don't use - their use currently unknown
          */
 
-        uint16_t rr_strap_xlat;
-        uint8_t rr_group_count;
-        int i;
-
         /*
          * Older bios versions don't have a sufficiently long table for
          * what we want
@@ -4618,24 +4612,13 @@ parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios,
                 return 0;
 
         if (bitentry->id[1] < 2) {
-                rr_group_count = bios->data[bitentry->offset + 2];
-                rr_strap_xlat = ROM16(bios->data[bitentry->offset + 3]);
+                bios->ram_restrict_group_count = bios->data[bitentry->offset + 2];
+                bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]);
         } else {
-                rr_group_count = bios->data[bitentry->offset + 0];
-                rr_strap_xlat = ROM16(bios->data[bitentry->offset + 1]);
+                bios->ram_restrict_group_count = bios->data[bitentry->offset + 0];
+                bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]);
         }
 
-        /* adjust length of INIT_87 */
-        for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != 0x87); i++);
-        itbl_entry[i].length += rr_group_count * 4;
-
-        /* set up multiplier for INIT_RAM_RESTRICT_ZM_REG_GROUP */
-        for (; itbl_entry[i].name && (itbl_entry[i].id != 0x8f); i++);
-        itbl_entry[i].length_multiplier = rr_group_count * 4;
-
-        init_ram_restrict_zm_reg_group_blocklen = itbl_entry[i].length_multiplier;
-        bios->ram_restrict_tbl_ptr = rr_strap_xlat;
-
         return 0;
 }
 
@@ -5234,7 +5217,7 @@ parse_dcb_connector_table(struct nvbios *bios)
         int i;
 
         if (!bios->bdcb.connector_table_ptr) {
-                NV_DEBUG(dev, "No DCB connector table present\n");
+                NV_DEBUG_KMS(dev, "No DCB connector table present\n");
                 return;
         }
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.h b/drivers/gpu/drm/nouveau/nouveau_bios.h
index 1d5f10bd78ed..058e98c76d89 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.h
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.h
@@ -227,6 +227,7 @@ struct nvbios {
 
         uint16_t pll_limit_tbl_ptr;
         uint16_t ram_restrict_tbl_ptr;
+        uint8_t ram_restrict_group_count;
 
         uint16_t some_script_ptr; /* BIT I + 14 */
         uint16_t init96_tbl_ptr; /* BIT I + 16 */
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
index aa2dfbc3e351..e342a418d434 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -33,10 +33,13 @@
 #include "nouveau_drv.h"
 #include "nouveau_dma.h"
 
+#include <linux/log2.h>
+
 static void
 nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
 {
         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
+        struct drm_device *dev = dev_priv->dev;
         struct nouveau_bo *nvbo = nouveau_bo(bo);
 
         ttm_bo_kunmap(&nvbo->kmap);
@@ -44,12 +47,87 @@ nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
         if (unlikely(nvbo->gem))
                 DRM_ERROR("bo %p still attached to GEM object\n", bo);
 
+        if (nvbo->tile)
+                nv10_mem_expire_tiling(dev, nvbo->tile, NULL);
+
         spin_lock(&dev_priv->ttm.bo_list_lock);
         list_del(&nvbo->head);
         spin_unlock(&dev_priv->ttm.bo_list_lock);
         kfree(nvbo);
 }
 
+static void
+nouveau_bo_fixup_align(struct drm_device *dev,
+                       uint32_t tile_mode, uint32_t tile_flags,
+                       int *align, int *size)
+{
+        struct drm_nouveau_private *dev_priv = dev->dev_private;
+
+        /*
+         * Some of the tile_flags have a periodic structure of N*4096 bytes,
+         * align to to that as well as the page size. Overallocate memory to
+         * avoid corruption of other buffer objects.
+         */
+        if (dev_priv->card_type == NV_50) {
+                uint32_t block_size = nouveau_mem_fb_amount(dev) >> 15;
+                int i;
+
+                switch (tile_flags) {
+                case 0x1800:
+                case 0x2800:
+                case 0x4800:
+                case 0x7a00:
+                        *size = roundup(*size, block_size);
+                        if (is_power_of_2(block_size)) {
+                                *size += 3 * block_size;
+                                for (i = 1; i < 10; i++) {
+                                        *align = 12 * i * block_size;
+                                        if (!(*align % 65536))
+                                                break;
+                                }
+                        } else {
+                                *size += 6 * block_size;
+                                for (i = 1; i < 10; i++) {
+                                        *align = 8 * i * block_size;
+                                        if (!(*align % 65536))
+                                                break;
+                                }
+                        }
+                        break;
+                default:
+                        break;
+                }
+
+        } else {
+                if (tile_mode) {
+                        if (dev_priv->chipset >= 0x40) {
+                                *align = 65536;
+                                *size = roundup(*size, 64 * tile_mode);
+
+                        } else if (dev_priv->chipset >= 0x30) {
+                                *align = 32768;
+                                *size = roundup(*size, 64 * tile_mode);
+
+                        } else if (dev_priv->chipset >= 0x20) {
+                                *align = 16384;
+                                *size = roundup(*size, 64 * tile_mode);
+
+                        } else if (dev_priv->chipset >= 0x10) {
+                                *align = 16384;
+                                *size = roundup(*size, 32 * tile_mode);
+                        }
+                }
+        }
+
+        /* ALIGN works only on powers of two. */
+        *size = roundup(*size, PAGE_SIZE);
+
+        if (dev_priv->card_type == NV_50) {
+                *size = roundup(*size, 65536);
+                *align = max(65536, *align);
+        }
+}
+
 int
 nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan,
                int size, int align, uint32_t flags, uint32_t tile_mode,
@@ -58,7 +136,7 @@ nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan,
 {
         struct drm_nouveau_private *dev_priv = dev->dev_private;
         struct nouveau_bo *nvbo;
-        int ret, n = 0;
+        int ret = 0;
 
         nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
         if (!nvbo)
@@ -70,59 +148,14 @@ nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan,
         nvbo->tile_mode = tile_mode;
         nvbo->tile_flags = tile_flags;
 
-        /*
-         * Some of the tile_flags have a periodic structure of N*4096 bytes,
-         * align to to that as well as the page size. Overallocate memory to
-         * avoid corruption of other buffer objects.
-         */
-        switch (tile_flags) {
-        case 0x1800:
-        case 0x2800:
-        case 0x4800:
-        case 0x7a00:
-                if (dev_priv->chipset >= 0xA0) {
-                        /* This is based on high end cards with 448 bits
-                         * memory bus, could be different elsewhere.*/
-                        size += 6 * 28672;
-                        /* 8 * 28672 is the actual alignment requirement,
-                         * but we must also align to page size. */
-                        align = 2 * 8 * 28672;
-                } else if (dev_priv->chipset >= 0x90) {
-                        size += 3 * 16384;
-                        align = 12 * 16834;
-                } else {
-                        size += 3 * 8192;
-                        /* 12 * 8192 is the actual alignment requirement,
-                         * but we must also align to page size. */
-                        align = 2 * 12 * 8192;
-                }
-                break;
-        default:
-                break;
-        }
-
+        nouveau_bo_fixup_align(dev, tile_mode, tile_flags, &align, &size);
         align >>= PAGE_SHIFT;
 
-        size = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
-        if (dev_priv->card_type == NV_50) {
-                size = (size + 65535) & ~65535;
-                if (align < (65536 / PAGE_SIZE))
-                        align = (65536 / PAGE_SIZE);
-        }
-
-        if (flags & TTM_PL_FLAG_VRAM)
-                nvbo->placements[n++] = TTM_PL_FLAG_VRAM | TTM_PL_MASK_CACHING;
-        if (flags & TTM_PL_FLAG_TT)
-                nvbo->placements[n++] = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
         nvbo->placement.fpfn = 0;
         nvbo->placement.lpfn = mappable ? dev_priv->fb_mappable_pages : 0;
-        nvbo->placement.placement = nvbo->placements;
-        nvbo->placement.busy_placement = nvbo->placements;
-        nvbo->placement.num_placement = n;
-        nvbo->placement.num_busy_placement = n;
+        nouveau_bo_placement_set(nvbo, flags);
 
         nvbo->channel = chan;
-        nouveau_bo_placement_set(nvbo, flags);
         ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size,
                           ttm_bo_type_device, &nvbo->placement, align, 0,
                           false, NULL, size, nouveau_bo_del_ttm);
@@ -154,6 +187,11 @@ nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t memtype)
         nvbo->placement.busy_placement = nvbo->placements;
         nvbo->placement.num_placement = n;
         nvbo->placement.num_busy_placement = n;
+
+        if (nvbo->pin_refcnt) {
+                while (n--)
+                        nvbo->placements[n] |= TTM_PL_FLAG_NO_EVICT;
+        }
 }
 
 int
@@ -400,16 +438,23 @@ nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
         struct nouveau_bo *nvbo = nouveau_bo(bo);
 
         switch (bo->mem.mem_type) {
+        case TTM_PL_VRAM:
+                nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT |
+                                         TTM_PL_FLAG_SYSTEM);
+                break;
         default:
                 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM);
                 break;
         }
+
+        *pl = nvbo->placement;
 }
 
 
 /* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
  * TTM_PL_{VRAM,TT} directly.
  */
+
 static int
 nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
                               struct nouveau_bo *nvbo, bool evict, bool no_wait,
@@ -444,22 +489,20 @@ nouveau_bo_mem_ctxdma(struct nouveau_bo *nvbo, struct nouveau_channel *chan,
 }
 
 static int
-nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, int no_wait,
-                     struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
+nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
+                     int no_wait, struct ttm_mem_reg *new_mem)
 {
         struct nouveau_bo *nvbo = nouveau_bo(bo);
         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
+        struct ttm_mem_reg *old_mem = &bo->mem;
         struct nouveau_channel *chan;
         uint64_t src_offset, dst_offset;
         uint32_t page_count;
         int ret;
 
         chan = nvbo->channel;
-        if (!chan || nvbo->tile_flags || nvbo->no_vm) {
+        if (!chan || nvbo->tile_flags || nvbo->no_vm)
                 chan = dev_priv->channel;
-                if (!chan)
-                        return -EINVAL;
-        }
 
         src_offset = old_mem->mm_node->start << PAGE_SHIFT;
         dst_offset = new_mem->mm_node->start << PAGE_SHIFT;
@@ -539,7 +582,7 @@ nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
 
         placement.fpfn = placement.lpfn = 0;
         placement.num_placement = placement.num_busy_placement = 1;
-        placement.placement = &placement_memtype;
+        placement.placement = placement.busy_placement = &placement_memtype;
 
         tmp_mem = *new_mem;
         tmp_mem.mm_node = NULL;
@@ -551,7 +594,7 @@ nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
         if (ret)
                 goto out;
 
-        ret = nouveau_bo_move_m2mf(bo, true, no_wait, &bo->mem, &tmp_mem);
+        ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait, &tmp_mem);
         if (ret)
                 goto out;
 
@@ -577,7 +620,7 @@ nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
 
         placement.fpfn = placement.lpfn = 0;
         placement.num_placement = placement.num_busy_placement = 1;
-        placement.placement = &placement_memtype;
+        placement.placement = placement.busy_placement = &placement_memtype;
 
         tmp_mem = *new_mem;
         tmp_mem.mm_node = NULL;
@@ -589,7 +632,7 @@ nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
         if (ret)
                 goto out;
 
-        ret = nouveau_bo_move_m2mf(bo, true, no_wait, &bo->mem, new_mem);
+        ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait, new_mem);
         if (ret)
                 goto out;
 
@@ -604,51 +647,106 @@ out:
 }
 
 static int
-nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
-                bool no_wait, struct ttm_mem_reg *new_mem)
+nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
+                   struct nouveau_tile_reg **new_tile)
 {
         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
-        struct nouveau_bo *nvbo = nouveau_bo(bo);
         struct drm_device *dev = dev_priv->dev;
-        struct ttm_mem_reg *old_mem = &bo->mem;
+        struct nouveau_bo *nvbo = nouveau_bo(bo);
+        uint64_t offset;
         int ret;
 
-        if (dev_priv->card_type == NV_50 && new_mem->mem_type == TTM_PL_VRAM &&
-            !nvbo->no_vm) {
-                uint64_t offset = new_mem->mm_node->start << PAGE_SHIFT;
+        if (nvbo->no_vm || new_mem->mem_type != TTM_PL_VRAM) {
+                /* Nothing to do. */
+                *new_tile = NULL;
+                return 0;
+        }
 
+        offset = new_mem->mm_node->start << PAGE_SHIFT;
+
+        if (dev_priv->card_type == NV_50) {
                 ret = nv50_mem_vm_bind_linear(dev,
                                               offset + dev_priv->vm_vram_base,
                                               new_mem->size, nvbo->tile_flags,
                                               offset);
                 if (ret)
                         return ret;
+
+        } else if (dev_priv->card_type >= NV_10) {
+                *new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size,
+                                                nvbo->tile_mode);
         }
 
-        if (dev_priv->init_state != NOUVEAU_CARD_INIT_DONE)
-                return ttm_bo_move_memcpy(bo, evict, no_wait, new_mem);
+        return 0;
+}
+
+static void
+nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
+                      struct nouveau_tile_reg *new_tile,
+                      struct nouveau_tile_reg **old_tile)
+{
+        struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
+        struct drm_device *dev = dev_priv->dev;
 
+        if (dev_priv->card_type >= NV_10 &&
+            dev_priv->card_type < NV_50) {
+                if (*old_tile)
+                        nv10_mem_expire_tiling(dev, *old_tile, bo->sync_obj);
+
+                *old_tile = new_tile;
+        }
+}
+
+static int
+nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
+                bool no_wait, struct ttm_mem_reg *new_mem)
+{
+        struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
+        struct nouveau_bo *nvbo = nouveau_bo(bo);
+        struct ttm_mem_reg *old_mem = &bo->mem;
+        struct nouveau_tile_reg *new_tile = NULL;
+        int ret = 0;
+
+        ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
+        if (ret)
+                return ret;
+
+        /* Software copy if the card isn't up and running yet. */
+        if (dev_priv->init_state != NOUVEAU_CARD_INIT_DONE ||
+            !dev_priv->channel) {
+                ret = ttm_bo_move_memcpy(bo, evict, no_wait, new_mem);
+                goto out;
+        }
+
+        /* Fake bo copy. */
         if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
                 BUG_ON(bo->mem.mm_node != NULL);
                 bo->mem = *new_mem;
                 new_mem->mm_node = NULL;
-                return 0;
+                goto out;
         }
 
-        if (new_mem->mem_type == TTM_PL_SYSTEM) {
-                if (old_mem->mem_type == TTM_PL_SYSTEM)
-                        return ttm_bo_move_memcpy(bo, evict, no_wait, new_mem);
-                if (nouveau_bo_move_flipd(bo, evict, intr, no_wait, new_mem))
-                        return ttm_bo_move_memcpy(bo, evict, no_wait, new_mem);
-        } else if (old_mem->mem_type == TTM_PL_SYSTEM) {
-                if (nouveau_bo_move_flips(bo, evict, intr, no_wait, new_mem))
-                        return ttm_bo_move_memcpy(bo, evict, no_wait, new_mem);
-        } else {
-                if (nouveau_bo_move_m2mf(bo, evict, no_wait, old_mem, new_mem))
-                        return ttm_bo_move_memcpy(bo, evict, no_wait, new_mem);
-        }
+        /* Hardware assisted copy. */
+        if (new_mem->mem_type == TTM_PL_SYSTEM)
+                ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait, new_mem);
+        else if (old_mem->mem_type == TTM_PL_SYSTEM)
+                ret = nouveau_bo_move_flips(bo, evict, intr, no_wait, new_mem);
+        else
+                ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait, new_mem);
 
-        return 0;
+        if (!ret)
+                goto out;
+
+        /* Fallback to software copy. */
+        ret = ttm_bo_move_memcpy(bo, evict, no_wait, new_mem);
+
+out:
+        if (ret)
+                nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
+        else
+                nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
+
+        return ret;
 }
 
 static int
diff --git a/drivers/gpu/drm/nouveau/nouveau_channel.c b/drivers/gpu/drm/nouveau/nouveau_channel.c
index 9aaa972f8822..343d718a9667 100644
--- a/drivers/gpu/drm/nouveau/nouveau_channel.c
+++ b/drivers/gpu/drm/nouveau/nouveau_channel.c
@@ -158,6 +158,8 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
                 return ret;
         }
 
+        nouveau_dma_pre_init(chan);
+
         /* Locate channel's user control regs */
         if (dev_priv->card_type < NV_40)
                 user = NV03_USER(channel);
@@ -235,47 +237,6 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
         return 0;
 }
 
-int
-nouveau_channel_idle(struct nouveau_channel *chan)
-{
-        struct drm_device *dev = chan->dev;
-        struct drm_nouveau_private *dev_priv = dev->dev_private;
-        struct nouveau_engine *engine = &dev_priv->engine;
-        uint32_t caches;
-        int idle;
-
-        if (!chan) {
-                NV_ERROR(dev, "no channel...\n");
-                return 1;
-        }
-
-        caches = nv_rd32(dev, NV03_PFIFO_CACHES);
-        nv_wr32(dev, NV03_PFIFO_CACHES, caches & ~1);
-
-        if (engine->fifo.channel_id(dev) != chan->id) {
-                struct nouveau_gpuobj *ramfc =
-                        chan->ramfc ? chan->ramfc->gpuobj : NULL;
-
-                if (!ramfc) {
-                        NV_ERROR(dev, "No RAMFC for channel %d\n", chan->id);
-                        return 1;
-                }
-
-                engine->instmem.prepare_access(dev, false);
-                if (nv_ro32(dev, ramfc, 0) != nv_ro32(dev, ramfc, 1))
-                        idle = 0;
-                else
-                        idle = 1;
-                engine->instmem.finish_access(dev);
-        } else {
-                idle = (nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET) ==
-                        nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUT));
-        }
-
-        nv_wr32(dev, NV03_PFIFO_CACHES, caches);
-        return idle;
-}
-
 /* stops a fifo */
 void
 nouveau_channel_free(struct nouveau_channel *chan)
@@ -414,7 +375,9 @@ nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data,
                 init->subchan[0].grclass = 0x0039;
         else
                 init->subchan[0].grclass = 0x5039;
-        init->nr_subchan = 1;
+        init->subchan[1].handle = NvSw;
+        init->subchan[1].grclass = NV_SW;
+        init->nr_subchan = 2;
 
         /* Named memory object area */
         ret = drm_gem_handle_create(file_priv, chan->notifier_bo->gem,
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c
index 032cf098fa1c..5a10deb8bdbd 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -86,7 +86,7 @@ nouveau_connector_destroy(struct drm_connector *drm_connector)
         struct nouveau_connector *connector = nouveau_connector(drm_connector);
         struct drm_device *dev = connector->base.dev;
 
-        NV_DEBUG(dev, "\n");
+        NV_DEBUG_KMS(dev, "\n");
 
         if (!connector)
                 return;
@@ -420,7 +420,7 @@ nouveau_connector_native_mode(struct nouveau_connector *connector)
         /* Use preferred mode if there is one.. */
         list_for_each_entry(mode, &connector->base.probed_modes, head) {
                 if (mode->type & DRM_MODE_TYPE_PREFERRED) {
-                        NV_DEBUG(dev, "native mode from preferred\n");
+                        NV_DEBUG_KMS(dev, "native mode from preferred\n");
                         return drm_mode_duplicate(dev, mode);
                 }
         }
@@ -445,7 +445,7 @@ nouveau_connector_native_mode(struct nouveau_connector *connector)
                 largest = mode;
         }
 
-        NV_DEBUG(dev, "native mode from largest: %dx%d@%d\n",
+        NV_DEBUG_KMS(dev, "native mode from largest: %dx%d@%d\n",
                       high_w, high_h, high_v);
         return largest ? drm_mode_duplicate(dev, largest) : NULL;
 }
@@ -725,7 +725,7 @@ nouveau_connector_create(struct drm_device *dev, int index, int type)
         struct drm_encoder *encoder;
         int ret;
 
-        NV_DEBUG(dev, "\n");
+        NV_DEBUG_KMS(dev, "\n");
 
         nv_connector = kzalloc(sizeof(*nv_connector), GFP_KERNEL);
         if (!nv_connector)
diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.c b/drivers/gpu/drm/nouveau/nouveau_dma.c
index 703553687b20..7afbe8b40d51 100644
--- a/drivers/gpu/drm/nouveau/nouveau_dma.c
+++ b/drivers/gpu/drm/nouveau/nouveau_dma.c
@@ -29,12 +29,22 @@
 #include "nouveau_drv.h"
 #include "nouveau_dma.h"
 
+void
+nouveau_dma_pre_init(struct nouveau_channel *chan)
+{
+        chan->dma.max  = (chan->pushbuf_bo->bo.mem.size >> 2) - 2;
+        chan->dma.put  = 0;
+        chan->dma.cur  = chan->dma.put;
+        chan->dma.free = chan->dma.max - chan->dma.cur;
+}
+
 int
 nouveau_dma_init(struct nouveau_channel *chan)
 {
         struct drm_device *dev = chan->dev;
         struct drm_nouveau_private *dev_priv = dev->dev_private;
         struct nouveau_gpuobj *m2mf = NULL;
+        struct nouveau_gpuobj *nvsw = NULL;
         int ret, i;
 
         /* Create NV_MEMORY_TO_MEMORY_FORMAT for buffer moves */
@@ -47,6 +57,15 @@ nouveau_dma_init(struct nouveau_channel *chan)
         if (ret)
                 return ret;
 
+        /* Create an NV_SW object for various sync purposes */
+        ret = nouveau_gpuobj_sw_new(chan, NV_SW, &nvsw);
+        if (ret)
+                return ret;
+
+        ret = nouveau_gpuobj_ref_add(dev, chan, NvSw, nvsw, NULL);
+        if (ret)
+                return ret;
+
         /* NV_MEMORY_TO_MEMORY_FORMAT requires a notifier object */
         ret = nouveau_notifier_alloc(chan, NvNotify0, 32, &chan->m2mf_ntfy);
         if (ret)
@@ -64,12 +83,6 @@ nouveau_dma_init(struct nouveau_channel *chan)
                         return ret;
         }
 
-        /* Initialise DMA vars */
-        chan->dma.max  = (chan->pushbuf_bo->bo.mem.size >> 2) - 2;
-        chan->dma.put  = 0;
-        chan->dma.cur  = chan->dma.put;
-        chan->dma.free = chan->dma.max - chan->dma.cur;
-
         /* Insert NOPS for NOUVEAU_DMA_SKIPS */
         ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS);
         if (ret)
@@ -87,6 +100,13 @@ nouveau_dma_init(struct nouveau_channel *chan)
         BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1);
         OUT_RING(chan, NvNotify0);
 
+        /* Initialise NV_SW */
+        ret = RING_SPACE(chan, 2);
+        if (ret)
+                return ret;
+        BEGIN_RING(chan, NvSubSw, 0, 1);
+        OUT_RING(chan, NvSw);
+
         /* Sit back and pray the channel works.. */
         FIRE_RING(chan);
 
@@ -113,7 +133,7 @@ READ_GET(struct nouveau_channel *chan, uint32_t *get)
 
         val = nvchan_rd32(chan, chan->user_get);
         if (val < chan->pushbuf_base ||
-            val >= chan->pushbuf_base + chan->pushbuf_bo->bo.mem.size) {
+            val > chan->pushbuf_base + (chan->dma.max << 2)) {
                 /* meaningless to dma_wait() except to know whether the
                  * GPU has stalled or not
                  */
diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h
index 04e85d8f757e..dabfd655f93e 100644
--- a/drivers/gpu/drm/nouveau/nouveau_dma.h
+++ b/drivers/gpu/drm/nouveau/nouveau_dma.h
@@ -46,10 +46,11 @@
 /* Hardcoded object assignments to subchannels (subchannel id). */
 enum {
         NvSubM2MF       = 0,
-        NvSub2D         = 1,
-        NvSubCtxSurf2D  = 1,
-        NvSubGdiRect    = 2,
-        NvSubImageBlit  = 3
+        NvSubSw         = 1,
+        NvSub2D         = 2,
+        NvSubCtxSurf2D  = 2,
+        NvSubGdiRect    = 3,
+        NvSubImageBlit  = 4
 };
 
 /* Object handles. */
@@ -67,6 +68,7 @@ enum {
         NvClipRect      = 0x8000000b,
         NvGdiRect       = 0x8000000c,
         NvImageBlit     = 0x8000000d,
+        NvSw            = 0x8000000e,
 
         /* G80+ display objects */
         NvEvoVRAM       = 0x01000000,
diff --git a/drivers/gpu/drm/nouveau/nouveau_dp.c b/drivers/gpu/drm/nouveau/nouveau_dp.c
index de61f4640e12..9e2926c48579 100644
--- a/drivers/gpu/drm/nouveau/nouveau_dp.c
+++ b/drivers/gpu/drm/nouveau/nouveau_dp.c
@@ -187,7 +187,7 @@ nouveau_dp_link_train_adjust(struct drm_encoder *encoder, uint8_t *config)
         if (ret)
                 return false;
 
-        NV_DEBUG(dev, "\t\tadjust 0x%02x 0x%02x\n", request[0], request[1]);
+        NV_DEBUG_KMS(dev, "\t\tadjust 0x%02x 0x%02x\n", request[0], request[1]);
 
         /* Keep all lanes at the same level.. */
         for (i = 0; i < nv_encoder->dp.link_nr; i++) {
@@ -228,7 +228,7 @@ nouveau_dp_link_train_commit(struct drm_encoder *encoder, uint8_t *config)
         int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1);
         int dpe_headerlen, ret, i;
 
-        NV_DEBUG(dev, "\t\tconfig 0x%02x 0x%02x 0x%02x 0x%02x\n",
+        NV_DEBUG_KMS(dev, "\t\tconfig 0x%02x 0x%02x 0x%02x 0x%02x\n",
                  config[0], config[1], config[2], config[3]);
 
         dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
@@ -276,12 +276,12 @@ nouveau_dp_link_train(struct drm_encoder *encoder)
         bool cr_done, cr_max_vs, eq_done;
         int ret = 0, i, tries, voltage;
 
-        NV_DEBUG(dev, "link training!!\n");
+        NV_DEBUG_KMS(dev, "link training!!\n");
 train:
         cr_done = eq_done = false;
 
         /* set link configuration */
-        NV_DEBUG(dev, "\tbegin train: bw %d, lanes %d\n",
+        NV_DEBUG_KMS(dev, "\tbegin train: bw %d, lanes %d\n",
                  nv_encoder->dp.link_bw, nv_encoder->dp.link_nr);
 
         ret = nouveau_dp_link_bw_set(encoder, nv_encoder->dp.link_bw);
@@ -297,7 +297,7 @@ train:
                 return false;
 
         /* clock recovery */
-        NV_DEBUG(dev, "\tbegin cr\n");
+        NV_DEBUG_KMS(dev, "\tbegin cr\n");
         ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_1);
         if (ret)
                 goto stop;
@@ -314,7 +314,7 @@ train:
                 ret = auxch_rd(encoder, DP_LANE0_1_STATUS, status, 2);
                 if (ret)
                         break;
-                NV_DEBUG(dev, "\t\tstatus: 0x%02x 0x%02x\n",
+                NV_DEBUG_KMS(dev, "\t\tstatus: 0x%02x 0x%02x\n",
                          status[0], status[1]);
 
                 cr_done = true;
@@ -346,7 +346,7 @@ train:
                 goto stop;
 
         /* channel equalisation */
-        NV_DEBUG(dev, "\tbegin eq\n");
+        NV_DEBUG_KMS(dev, "\tbegin eq\n");
         ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_2);
         if (ret)
                 goto stop;
@@ -357,7 +357,7 @@ train:
                 ret = auxch_rd(encoder, DP_LANE0_1_STATUS, status, 3);
                 if (ret)
                         break;
-                NV_DEBUG(dev, "\t\tstatus: 0x%02x 0x%02x\n",
+                NV_DEBUG_KMS(dev, "\t\tstatus: 0x%02x 0x%02x\n",
                          status[0], status[1]);
 
                 eq_done = true;
@@ -395,9 +395,9 @@ stop:
 
         /* retry at a lower setting, if possible */
         if (!ret && !(eq_done && cr_done)) {
-                NV_DEBUG(dev, "\twe failed\n");
+                NV_DEBUG_KMS(dev, "\twe failed\n");
                 if (nv_encoder->dp.link_bw != DP_LINK_BW_1_62) {
-                        NV_DEBUG(dev, "retry link training at low rate\n");
+                        NV_DEBUG_KMS(dev, "retry link training at low rate\n");
                         nv_encoder->dp.link_bw = DP_LINK_BW_1_62;
                         goto train;
                 }
@@ -418,7 +418,7 @@ nouveau_dp_detect(struct drm_encoder *encoder)
         if (ret)
                 return false;
 
-        NV_DEBUG(dev, "encoder: link_bw %d, link_nr %d\n"
+        NV_DEBUG_KMS(dev, "encoder: link_bw %d, link_nr %d\n"
                       "display: link_bw %d, link_nr %d version 0x%02x\n",
                  nv_encoder->dcb->dpconf.link_bw,
                  nv_encoder->dcb->dpconf.link_nr,
@@ -446,7 +446,7 @@ nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
         uint32_t tmp, ctrl, stat = 0, data32[4] = {};
         int ret = 0, i, index = auxch->rd;
 
-        NV_DEBUG(dev, "ch %d cmd %d addr 0x%x len %d\n", index, cmd, addr, data_nr);
+        NV_DEBUG_KMS(dev, "ch %d cmd %d addr 0x%x len %d\n", index, cmd, addr, data_nr);
 
         tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd));
         nv_wr32(dev, NV50_AUXCH_CTRL(auxch->rd), tmp | 0x00100000);
@@ -472,7 +472,7 @@ nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
         if (!(cmd & 1)) {
                 memcpy(data32, data, data_nr);
                 for (i = 0; i < 4; i++) {
-                        NV_DEBUG(dev, "wr %d: 0x%08x\n", i, data32[i]);
+                        NV_DEBUG_KMS(dev, "wr %d: 0x%08x\n", i, data32[i]);
                         nv_wr32(dev, NV50_AUXCH_DATA_OUT(index, i), data32[i]);
                 }
         }
@@ -504,7 +504,7 @@ nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
         if (cmd & 1) {
                 for (i = 0; i < 4; i++) {
                         data32[i] = nv_rd32(dev, NV50_AUXCH_DATA_IN(index, i));
-                        NV_DEBUG(dev, "rd %d: 0x%08x\n", i, data32[i]);
+                        NV_DEBUG_KMS(dev, "rd %d: 0x%08x\n", i, data32[i]);
                 }
                 memcpy(data, data32, data_nr);
         }
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.c b/drivers/gpu/drm/nouveau/nouveau_drv.c
index 35249c35118f..06eb993e0883 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.c
@@ -35,6 +35,10 @@
 
 #include "drm_pciids.h"
 
+MODULE_PARM_DESC(ctxfw, "Use external firmware blob for grctx init (NV40)");
+int nouveau_ctxfw = 0;
+module_param_named(ctxfw, nouveau_ctxfw, int, 0400);
+
 MODULE_PARM_DESC(noagp, "Disable AGP");
 int nouveau_noagp;
 module_param_named(noagp, nouveau_noagp, int, 0400);
@@ -273,7 +277,7 @@ nouveau_pci_resume(struct pci_dev *pdev)
 
                 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
                         chan = dev_priv->fifos[i];
-                        if (!chan)
+                        if (!chan || !chan->pushbuf_bo)
                                 continue;
 
                         for (j = 0; j < NOUVEAU_DMA_SKIPS; j++)
@@ -341,7 +345,7 @@ static struct drm_driver driver = {
                 .owner = THIS_MODULE,
                 .open = drm_open,
                 .release = drm_release,
-                .ioctl = drm_ioctl,
+                .unlocked_ioctl = drm_ioctl,
                 .mmap = nouveau_ttm_mmap,
                 .poll = drm_poll,
                 .fasync = drm_fasync,
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index 88b4c7b77e7f..026419fe8791 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -54,15 +54,24 @@ struct nouveau_fpriv {
 #include "nouveau_drm.h"
 #include "nouveau_reg.h"
 #include "nouveau_bios.h"
+struct nouveau_grctx;
 
 #define MAX_NUM_DCB_ENTRIES 16
 
 #define NOUVEAU_MAX_CHANNEL_NR 128
+#define NOUVEAU_MAX_TILE_NR 15
 
 #define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
 #define NV50_VM_BLOCK    (512*1024*1024ULL)
 #define NV50_VM_VRAM_NR  (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
 
+struct nouveau_tile_reg {
+        struct nouveau_fence *fence;
+        uint32_t addr;
+        uint32_t size;
+        bool used;
+};
+
 struct nouveau_bo {
         struct ttm_buffer_object bo;
         struct ttm_placement placement;
@@ -82,6 +91,7 @@ struct nouveau_bo {
 
         uint32_t tile_mode;
         uint32_t tile_flags;
+        struct nouveau_tile_reg *tile;
 
         struct drm_gem_object *gem;
         struct drm_file *cpu_filp;
@@ -276,8 +286,13 @@ struct nouveau_timer_engine {
 };
 
 struct nouveau_fb_engine {
+        int num_tiles;
+
         int  (*init)(struct drm_device *dev);
         void (*takedown)(struct drm_device *dev);
+
+        void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
+                                 uint32_t size, uint32_t pitch);
 };
 
 struct nouveau_fifo_engine {
@@ -291,6 +306,8 @@ struct nouveau_fifo_engine {
         void (*disable)(struct drm_device *);
         void (*enable)(struct drm_device *);
         bool (*reassign)(struct drm_device *, bool enable);
+        bool (*cache_flush)(struct drm_device *dev);
+        bool (*cache_pull)(struct drm_device *dev, bool enable);
 
         int  (*channel_id)(struct drm_device *);
 
@@ -317,6 +334,7 @@ struct nouveau_pgraph_engine {
         bool accel_blocked;
         void *ctxprog;
         void *ctxvals;
+        int grctx_size;
 
         int  (*init)(struct drm_device *);
         void (*takedown)(struct drm_device *);
@@ -328,6 +346,9 @@ struct nouveau_pgraph_engine {
         void (*destroy_context)(struct nouveau_channel *);
         int  (*load_context)(struct nouveau_channel *);
         int  (*unload_context)(struct drm_device *);
+
+        void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
+                                  uint32_t size, uint32_t pitch);
 };
 
 struct nouveau_engine {
@@ -546,6 +567,12 @@ struct drm_nouveau_private {
                 unsigned long sg_handle;
         } gart_info;
 
+        /* nv10-nv40 tiling regions */
+        struct {
+                struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
+                spinlock_t lock;
+        } tile;
+
         /* G8x/G9x virtual address space */
         uint64_t vm_gart_base;
         uint64_t vm_gart_size;
@@ -647,6 +674,7 @@ extern int nouveau_fbpercrtc;
 extern char *nouveau_tv_norm;
 extern int nouveau_reg_debug;
 extern char *nouveau_vbios;
+extern int nouveau_ctxfw;
 
 /* nouveau_state.c */
 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
@@ -682,6 +710,13 @@ extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap);
 extern int  nouveau_mem_init(struct drm_device *);
 extern int  nouveau_mem_init_agp(struct drm_device *);
 extern void nouveau_mem_close(struct drm_device *);
+extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev,
+                                                    uint32_t addr,
+                                                    uint32_t size,
+                                                    uint32_t pitch);
+extern void nv10_mem_expire_tiling(struct drm_device *dev,
+                                   struct nouveau_tile_reg *tile,
+                                   struct nouveau_fence *fence);
 extern int  nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
                                     uint32_t size, uint32_t flags,
                                     uint64_t phys);
@@ -710,7 +745,6 @@ extern int  nouveau_channel_alloc(struct drm_device *dev,
                                   struct drm_file *file_priv,
                                   uint32_t fb_ctxdma, uint32_t tt_ctxdma);
 extern void nouveau_channel_free(struct nouveau_channel *);
-extern int  nouveau_channel_idle(struct nouveau_channel *chan);
 
 /* nouveau_object.c */
 extern int  nouveau_gpuobj_early_init(struct drm_device *);
@@ -753,6 +787,8 @@ extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
                                        uint32_t *o_ret);
 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
                                  struct nouveau_gpuobj **);
+extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class,
+                                 struct nouveau_gpuobj **);
 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
                                      struct drm_file *);
 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
@@ -801,6 +837,7 @@ nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
 #endif
 
 /* nouveau_dma.c */
+extern void nouveau_dma_pre_init(struct nouveau_channel *);
 extern int  nouveau_dma_init(struct nouveau_channel *);
 extern int  nouveau_dma_wait(struct nouveau_channel *, int size);
 
@@ -876,16 +913,22 @@ extern void nv04_fb_takedown(struct drm_device *);
 /* nv10_fb.c */
 extern int  nv10_fb_init(struct drm_device *);
 extern void nv10_fb_takedown(struct drm_device *);
+extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,
+                                      uint32_t, uint32_t);
 
 /* nv40_fb.c */
 extern int  nv40_fb_init(struct drm_device *);
 extern void nv40_fb_takedown(struct drm_device *);
+extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
+                                      uint32_t, uint32_t);
 
 /* nv04_fifo.c */
 extern int  nv04_fifo_init(struct drm_device *);
 extern void nv04_fifo_disable(struct drm_device *);
 extern void nv04_fifo_enable(struct drm_device *);
 extern bool nv04_fifo_reassign(struct drm_device *, bool);
+extern bool nv04_fifo_cache_flush(struct drm_device *);
+extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
 extern int  nv04_fifo_channel_id(struct drm_device *);
 extern int  nv04_fifo_create_context(struct nouveau_channel *);
 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
@@ -938,6 +981,8 @@ extern void nv10_graph_destroy_context(struct nouveau_channel *);
 extern int  nv10_graph_load_context(struct nouveau_channel *);
 extern int  nv10_graph_unload_context(struct drm_device *);
 extern void nv10_graph_context_switch(struct drm_device *);
+extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,
+                                         uint32_t, uint32_t);
 
 /* nv20_graph.c */
 extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
@@ -949,6 +994,8 @@ extern int  nv20_graph_unload_context(struct drm_device *);
 extern int  nv20_graph_init(struct drm_device *);
 extern void nv20_graph_takedown(struct drm_device *);
 extern int  nv30_graph_init(struct drm_device *);
+extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,
+                                         uint32_t, uint32_t);
 
 /* nv40_graph.c */
 extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
@@ -959,9 +1006,9 @@ extern int  nv40_graph_create_context(struct nouveau_channel *);
 extern void nv40_graph_destroy_context(struct nouveau_channel *);
 extern int  nv40_graph_load_context(struct nouveau_channel *);
 extern int  nv40_graph_unload_context(struct drm_device *);
-extern int  nv40_grctx_init(struct drm_device *);
-extern void nv40_grctx_fini(struct drm_device *);
-extern void nv40_grctx_vals_load(struct drm_device *, struct nouveau_gpuobj *);
+extern void nv40_grctx_init(struct nouveau_grctx *);
+extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,
+                                         uint32_t, uint32_t);
 
 /* nv50_graph.c */
 extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
@@ -975,6 +1022,12 @@ extern int  nv50_graph_load_context(struct nouveau_channel *);
 extern int  nv50_graph_unload_context(struct drm_device *);
 extern void nv50_graph_context_switch(struct drm_device *);
 
+/* nouveau_grctx.c */
+extern int  nouveau_grctx_prog_load(struct drm_device *);
+extern void nouveau_grctx_vals_load(struct drm_device *,
+                                    struct nouveau_gpuobj *);
+extern void nouveau_grctx_fini(struct drm_device *);
+
 /* nv04_instmem.c */
 extern int  nv04_instmem_init(struct drm_device *);
 extern void nv04_instmem_takedown(struct drm_device *);
@@ -1023,8 +1076,7 @@ extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
 
 /* nv04_dac.c */
 extern int nv04_dac_create(struct drm_device *dev, struct dcb_entry *entry);
-extern enum drm_connector_status nv17_dac_detect(struct drm_encoder *encoder,
-                                                 struct drm_connector *connector);
+extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
 extern int nv04_dac_output_offset(struct drm_encoder *encoder);
 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
 
@@ -1042,9 +1094,6 @@ extern int nv04_tv_create(struct drm_device *dev, struct dcb_entry *entry);
 
 /* nv17_tv.c */
 extern int nv17_tv_create(struct drm_device *dev, struct dcb_entry *entry);
-extern enum drm_connector_status nv17_tv_detect(struct drm_encoder *encoder,
-                                                struct drm_connector *connector,
-                                                uint32_t pin_mask);
 
 /* nv04_display.c */
 extern int nv04_display_create(struct drm_device *);
@@ -1207,14 +1256,24 @@ static inline void nv_wo32(struct drm_device *dev, struct nouveau_gpuobj *obj,
                                         pci_name(d->pdev), ##arg)
 #ifndef NV_DEBUG_NOTRACE
 #define NV_DEBUG(d, fmt, arg...) do {                                          \
-        if (drm_debug) {                                                       \
+        if (drm_debug & DRM_UT_DRIVER) {                                       \
+                NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__,             \
+                          __LINE__, ##arg);                                    \
+        }                                                                      \
+} while (0)
+#define NV_DEBUG_KMS(d, fmt, arg...) do {                                      \
+        if (drm_debug & DRM_UT_KMS) {                                          \
                 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__,             \
                           __LINE__, ##arg);                                    \
         }                                                                      \
 } while (0)
 #else
 #define NV_DEBUG(d, fmt, arg...) do {                                          \
-        if (drm_debug)                                                         \
+        if (drm_debug & DRM_UT_DRIVER)                                         \
+                NV_PRINTK(KERN_DEBUG, d, fmt, ##arg);                          \
+} while (0)
+#define NV_DEBUG_KMS(d, fmt, arg...) do {                                      \
+        if (drm_debug & DRM_UT_KMS)                                            \
                 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg);                          \
 } while (0)
 #endif
@@ -1273,14 +1332,14 @@ nv_two_reg_pll(struct drm_device *dev)
         return false;
 }
 
-#define NV50_NVSW                                                    0x0000506e
-#define NV50_NVSW_DMA_SEMAPHORE                                      0x00000060
-#define NV50_NVSW_SEMAPHORE_OFFSET                                   0x00000064
-#define NV50_NVSW_SEMAPHORE_ACQUIRE                                  0x00000068
-#define NV50_NVSW_SEMAPHORE_RELEASE                                  0x0000006c
-#define NV50_NVSW_DMA_VBLSEM                                         0x0000018c
-#define NV50_NVSW_VBLSEM_OFFSET                                      0x00000400
-#define NV50_NVSW_VBLSEM_RELEASE_VALUE                               0x00000404
-#define NV50_NVSW_VBLSEM_RELEASE                                     0x00000408
+#define NV_SW                                                        0x0000506e
+#define NV_SW_DMA_SEMAPHORE                                          0x00000060
+#define NV_SW_SEMAPHORE_OFFSET                                       0x00000064
+#define NV_SW_SEMAPHORE_ACQUIRE                                      0x00000068
+#define NV_SW_SEMAPHORE_RELEASE                                      0x0000006c
+#define NV_SW_DMA_VBLSEM                                             0x0000018c
+#define NV_SW_VBLSEM_OFFSET                                          0x00000400
+#define NV_SW_VBLSEM_RELEASE_VALUE                                   0x00000404
+#define NV_SW_VBLSEM_RELEASE                                         0x00000408
 
 #endif /* __NOUVEAU_DRV_H__ */
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
index 36e8c5e4503a..0b05c869e0e7 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
@@ -58,14 +58,13 @@ nouveau_fbcon_sync(struct fb_info *info)
         struct nouveau_channel *chan = dev_priv->channel;
         int ret, i;
 
-        if (!chan->accel_done ||
+        if (!chan || !chan->accel_done ||
             info->state != FBINFO_STATE_RUNNING ||
             info->flags & FBINFO_HWACCEL_DISABLED)
                 return 0;
 
         if (RING_SPACE(chan, 4)) {
-                NV_ERROR(dev, "GPU lockup - switching to software fbcon\n");
-                info->flags |= FBINFO_HWACCEL_DISABLED;
+                nouveau_fbcon_gpu_lockup(info);
                 return 0;
         }
 
@@ -86,8 +85,7 @@ nouveau_fbcon_sync(struct fb_info *info)
         }
 
         if (ret) {
-                NV_ERROR(dev, "GPU lockup - switching to software fbcon\n");
-                info->flags |= FBINFO_HWACCEL_DISABLED;
+                nouveau_fbcon_gpu_lockup(info);
                 return 0;
         }
 
@@ -212,11 +210,11 @@ nouveau_fbcon_create(struct drm_device *dev, uint32_t fb_width,
 
         mode_cmd.bpp = surface_bpp;
         mode_cmd.pitch = mode_cmd.width * (mode_cmd.bpp >> 3);
-        mode_cmd.pitch = ALIGN(mode_cmd.pitch, 256);
+        mode_cmd.pitch = roundup(mode_cmd.pitch, 256);
         mode_cmd.depth = surface_depth;
 
         size = mode_cmd.pitch * mode_cmd.height;
-        size = ALIGN(size, PAGE_SIZE);
+        size = roundup(size, PAGE_SIZE);
 
         ret = nouveau_gem_new(dev, dev_priv->channel, size, 0, TTM_PL_FLAG_VRAM,
                               0, 0x0000, false, true, &nvbo);
@@ -318,14 +316,16 @@ nouveau_fbcon_create(struct drm_device *dev, uint32_t fb_width,
         par->nouveau_fb = nouveau_fb;
         par->dev = dev;
 
-        switch (dev_priv->card_type) {
-        case NV_50:
-                nv50_fbcon_accel_init(info);
-                break;
-        default:
-                nv04_fbcon_accel_init(info);
-                break;
-        };
+        if (dev_priv->channel) {
+                switch (dev_priv->card_type) {
+                case NV_50:
+                        nv50_fbcon_accel_init(info);
+                        break;
+                default:
+                        nv04_fbcon_accel_init(info);
+                        break;
+                };
+        }
 
         nouveau_fbcon_zfill(dev);
 
@@ -347,7 +347,7 @@ out:
 int
 nouveau_fbcon_probe(struct drm_device *dev)
 {
-        NV_DEBUG(dev, "\n");
+        NV_DEBUG_KMS(dev, "\n");
 
         return drm_fb_helper_single_fb_probe(dev, 32, nouveau_fbcon_create);
 }
@@ -378,3 +378,12 @@ nouveau_fbcon_remove(struct drm_device *dev, struct drm_framebuffer *fb)
 
         return 0;
 }
+
+void nouveau_fbcon_gpu_lockup(struct fb_info *info)
+{
+        struct nouveau_fbcon_par *par = info->par;
+        struct drm_device *dev = par->dev;
+
+        NV_ERROR(dev, "GPU lockup - switching to software fbcon\n");
+        info->flags |= FBINFO_HWACCEL_DISABLED;
+}
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.h b/drivers/gpu/drm/nouveau/nouveau_fbcon.h
index 8531140fedbc..462e0b87b4bd 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.h
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.h
@@ -43,5 +43,6 @@ void nouveau_fbcon_zfill(struct drm_device *dev);
 int nv04_fbcon_accel_init(struct fb_info *info);
 int nv50_fbcon_accel_init(struct fb_info *info);
 
+void nouveau_fbcon_gpu_lockup(struct fb_info *info);
 #endif /* __NV50_FBCON_H__ */
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c b/drivers/gpu/drm/nouveau/nouveau_fence.c
index dacac9a0842a..faddf53ff9ed 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fence.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fence.c
@@ -142,7 +142,7 @@ nouveau_fence_emit(struct nouveau_fence *fence)
         list_add_tail(&fence->entry, &chan->fence.pending);
         spin_unlock_irqrestore(&chan->fence.lock, flags);
 
-        BEGIN_RING(chan, NvSubM2MF, USE_REFCNT ? 0x0050 : 0x0150, 1);
+        BEGIN_RING(chan, NvSubSw, USE_REFCNT ? 0x0050 : 0x0150, 1);
         OUT_RING(chan, fence->sequence);
         FIRE_RING(chan);
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c
index 18fd8ac9fca7..2009db2426c3 100644
--- a/drivers/gpu/drm/nouveau/nouveau_gem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_gem.c
@@ -220,7 +220,6 @@ nouveau_gem_set_domain(struct drm_gem_object *gem, uint32_t read_domains,
 }
 
 struct validate_op {
-        struct nouveau_fence *fence;
         struct list_head vram_list;
         struct list_head gart_list;
         struct list_head both_list;
@@ -252,17 +251,11 @@ validate_fini_list(struct list_head *list, struct nouveau_fence *fence)
 }
 
 static void
-validate_fini(struct validate_op *op, bool success)
+validate_fini(struct validate_op *op, struct nouveau_fence* fence)
 {
-        struct nouveau_fence *fence = op->fence;
-
-        if (unlikely(!success))
-                op->fence = NULL;
-
-        validate_fini_list(&op->vram_list, op->fence);
-        validate_fini_list(&op->gart_list, op->fence);
-        validate_fini_list(&op->both_list, op->fence);
-        nouveau_fence_unref((void *)&fence);
+        validate_fini_list(&op->vram_list, fence);
+        validate_fini_list(&op->gart_list, fence);
+        validate_fini_list(&op->both_list, fence);
 }
 
 static int
@@ -420,10 +413,6 @@ nouveau_gem_pushbuf_validate(struct nouveau_channel *chan,
         INIT_LIST_HEAD(&op->gart_list);
         INIT_LIST_HEAD(&op->both_list);
 
-        ret = nouveau_fence_new(chan, &op->fence, false);
-        if (ret)
-                return ret;
-
         if (nr_buffers == 0)
                 return 0;
 
@@ -541,6 +530,7 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data,
         struct drm_nouveau_gem_pushbuf_bo *bo = NULL;
         struct nouveau_channel *chan;
         struct validate_op op;
+        struct nouveau_fence* fence = 0;
         uint32_t *pushbuf = NULL;
         int ret = 0, do_reloc = 0, i;
 
@@ -597,7 +587,7 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data,
 
         OUT_RINGp(chan, pushbuf, req->nr_dwords);
 
-        ret = nouveau_fence_emit(op.fence);
+        ret = nouveau_fence_new(chan, &fence, true);
         if (ret) {
                 NV_ERROR(dev, "error fencing pushbuf: %d\n", ret);
                 WIND_RING(chan);
@@ -605,7 +595,7 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data,
         }
 
         if (nouveau_gem_pushbuf_sync(chan)) {
-                ret = nouveau_fence_wait(op.fence, NULL, false, false);
+                ret = nouveau_fence_wait(fence, NULL, false, false);
                 if (ret) {
                         for (i = 0; i < req->nr_dwords; i++)
                                 NV_ERROR(dev, "0x%08x\n", pushbuf[i]);
@@ -614,7 +604,8 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data,
         }
 
 out:
-        validate_fini(&op, ret == 0);
+        validate_fini(&op, fence);
+        nouveau_fence_unref((void**)&fence);
         mutex_unlock(&dev->struct_mutex);
         kfree(pushbuf);
         kfree(bo);
@@ -634,6 +625,7 @@ nouveau_gem_ioctl_pushbuf_call(struct drm_device *dev, void *data,
         struct drm_gem_object *gem;
         struct nouveau_bo *pbbo;
         struct validate_op op;
+        struct nouveau_fence* fence = 0;
         int i, ret = 0, do_reloc = 0;
 
         NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
@@ -772,7 +764,7 @@ nouveau_gem_ioctl_pushbuf_call(struct drm_device *dev, void *data,
                         OUT_RING(chan, 0);
         }
 
-        ret = nouveau_fence_emit(op.fence);
+        ret = nouveau_fence_new(chan, &fence, true);
         if (ret) {
                 NV_ERROR(dev, "error fencing pushbuf: %d\n", ret);
                 WIND_RING(chan);
@@ -780,7 +772,8 @@ nouveau_gem_ioctl_pushbuf_call(struct drm_device *dev, void *data,
         }
 
 out:
-        validate_fini(&op, ret == 0);
+        validate_fini(&op, fence);
+        nouveau_fence_unref((void**)&fence);
         mutex_unlock(&dev->struct_mutex);
         kfree(bo);
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_grctx.c b/drivers/gpu/drm/nouveau/nouveau_grctx.c
new file mode 100644
index 000000000000..419f4c2b3b89
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_grctx.c
@@ -0,0 +1,161 @@
+/*
+ * Copyright 2009 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#include <linux/firmware.h>
+
+#include "drmP.h"
+#include "nouveau_drv.h"
+
+struct nouveau_ctxprog {
+        uint32_t signature;
+        uint8_t  version;
+        uint16_t length;
+        uint32_t data[];
+} __attribute__ ((packed));
+
+struct nouveau_ctxvals {
+        uint32_t signature;
+        uint8_t  version;
+        uint32_t length;
+        struct {
+                uint32_t offset;
+                uint32_t value;
+        } data[];
+} __attribute__ ((packed));
+
+int
+nouveau_grctx_prog_load(struct drm_device *dev)
+{
+        struct drm_nouveau_private *dev_priv = dev->dev_private;
+        struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
+        const int chipset = dev_priv->chipset;
+        const struct firmware *fw;
+        const struct nouveau_ctxprog *cp;
+        const struct nouveau_ctxvals *cv;
+        char name[32];
+        int ret, i;
+
+        if (pgraph->accel_blocked)
+                return -ENODEV;
+
+        if (!pgraph->ctxprog) {
+                sprintf(name, "nouveau/nv%02x.ctxprog", chipset);
+                ret = request_firmware(&fw, name, &dev->pdev->dev);
+                if (ret) {
+                        NV_ERROR(dev, "No ctxprog for NV%02x\n", chipset);
+                        return ret;
+                }
+
+                pgraph->ctxprog = kmalloc(fw->size, GFP_KERNEL);
+                if (!pgraph->ctxprog) {
+                        NV_ERROR(dev, "OOM copying ctxprog\n");
+                        release_firmware(fw);
+                        return -ENOMEM;
+                }
+                memcpy(pgraph->ctxprog, fw->data, fw->size);
+
+                cp = pgraph->ctxprog;
+                if (le32_to_cpu(cp->signature) != 0x5043564e ||
+                    cp->version != 0 ||
+                    le16_to_cpu(cp->length) != ((fw->size - 7) / 4)) {
+                        NV_ERROR(dev, "ctxprog invalid\n");
+                        release_firmware(fw);
+                        nouveau_grctx_fini(dev);
+                        return -EINVAL;
+                }
+                release_firmware(fw);
+        }
+
+        if (!pgraph->ctxvals) {
+                sprintf(name, "nouveau/nv%02x.ctxvals", chipset);
+                ret = request_firmware(&fw, name, &dev->pdev->dev);
+                if (ret) {
+                        NV_ERROR(dev, "No ctxvals for NV%02x\n", chipset);
+                        nouveau_grctx_fini(dev);
+                        return ret;
+                }
+
+                pgraph->ctxvals = kmalloc(fw->size, GFP_KERNEL);
+                if (!pgraph->ctxprog) {
+                        NV_ERROR(dev, "OOM copying ctxprog\n");
+                        release_firmware(fw);
+                        nouveau_grctx_fini(dev);
+                        return -ENOMEM;
+                }
+                memcpy(pgraph->ctxvals, fw->data, fw->size);
+
+                cv = (void *)pgraph->ctxvals;
+                if (le32_to_cpu(cv->signature) != 0x5643564e ||
+                    cv->version != 0 ||
+                    le32_to_cpu(cv->length) != ((fw->size - 9) / 8)) {
+                        NV_ERROR(dev, "ctxvals invalid\n");
+                        release_firmware(fw);
+                        nouveau_grctx_fini(dev);
+                        return -EINVAL;
+                }
+                release_firmware(fw);
+        }
+
+        cp = pgraph->ctxprog;
+
+        nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
+        for (i = 0; i < le16_to_cpu(cp->length); i++)
+                nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA,
+                        le32_to_cpu(cp->data[i]));
+
+        return 0;
+}
+
+void
+nouveau_grctx_fini(struct drm_device *dev)
+{
+        struct drm_nouveau_private *dev_priv = dev->dev_private;
+        struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
+
+        if (pgraph->ctxprog) {
+                kfree(pgraph->ctxprog);
+                pgraph->ctxprog = NULL;
+        }
+
+        if (pgraph->ctxvals) {
+                kfree(pgraph->ctxprog);
+                pgraph->ctxvals = NULL;
+        }
+}
+
+void
+nouveau_grctx_vals_load(struct drm_device *dev, struct nouveau_gpuobj *ctx)
+{
+        struct drm_nouveau_private *dev_priv = dev->dev_private;
+        struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
+        struct nouveau_ctxvals *cv = pgraph->ctxvals;
+        int i;
+
+        if (!cv)
+                return;
+
+        for (i = 0; i < le32_to_cpu(cv->length); i++)
+                nv_wo32(dev, ctx, le32_to_cpu(cv->data[i].offset),
+                        le32_to_cpu(cv->data[i].value));
+}
diff --git a/drivers/gpu/drm/nouveau/nouveau_grctx.h b/drivers/gpu/drm/nouveau/nouveau_grctx.h
new file mode 100644
index 000000000000..5d39c4ce8006
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_grctx.h
@@ -0,0 +1,133 @@
+#ifndef __NOUVEAU_GRCTX_H__
+#define __NOUVEAU_GRCTX_H__
+
+struct nouveau_grctx {
+        struct drm_device *dev;
+
+        enum {
+                NOUVEAU_GRCTX_PROG,
+                NOUVEAU_GRCTX_VALS
+        } mode;
+        void *data;
+
+        uint32_t ctxprog_max;
+        uint32_t ctxprog_len;
+        uint32_t ctxprog_reg;
+        int      ctxprog_label[32];
+        uint32_t ctxvals_pos;
+        uint32_t ctxvals_base;
+};
+
+#ifdef CP_CTX
+static inline void
+cp_out(struct nouveau_grctx *ctx, uint32_t inst)
+{
+        uint32_t *ctxprog = ctx->data;
+
+        if (ctx->mode != NOUVEAU_GRCTX_PROG)
+                return;
+
+        BUG_ON(ctx->ctxprog_len == ctx->ctxprog_max);
+        ctxprog[ctx->ctxprog_len++] = inst;
+}
+
+static inline void
+cp_lsr(struct nouveau_grctx *ctx, uint32_t val)
+{
+        cp_out(ctx, CP_LOAD_SR | val);
+}
+
+static inline void
+cp_ctx(struct nouveau_grctx *ctx, uint32_t reg, uint32_t length)
+{
+        ctx->ctxprog_reg = (reg - 0x00400000) >> 2;
+
+        ctx->ctxvals_base = ctx->ctxvals_pos;
+        ctx->ctxvals_pos = ctx->ctxvals_base + length;
+
+        if (length > (CP_CTX_COUNT >> CP_CTX_COUNT_SHIFT)) {
+                cp_lsr(ctx, length);
+                length = 0;
+        }
+
+        cp_out(ctx, CP_CTX | (length << CP_CTX_COUNT_SHIFT) | ctx->ctxprog_reg);
+}
+
+static inline void
+cp_name(struct nouveau_grctx *ctx, int name)
+{
+        uint32_t *ctxprog = ctx->data;
+        int i;
+
+        if (ctx->mode != NOUVEAU_GRCTX_PROG)
+                return;
+
+        ctx->ctxprog_label[name] = ctx->ctxprog_len;
+        for (i = 0; i < ctx->ctxprog_len; i++) {
+                if ((ctxprog[i] & 0xfff00000) != 0xff400000)
+                        continue;
+                if ((ctxprog[i] & CP_BRA_IP) != ((name) << CP_BRA_IP_SHIFT))
+                        continue;
+                ctxprog[i] = (ctxprog[i] & 0x00ff00ff) |
+                             (ctx->ctxprog_len << CP_BRA_IP_SHIFT);
+        }
+}
+
+static inline void
+_cp_bra(struct nouveau_grctx *ctx, u32 mod, int flag, int state, int name)
+{
+        int ip = 0;
+
+        if (mod != 2) {
+                ip = ctx->ctxprog_label[name] << CP_BRA_IP_SHIFT;
+                if (ip == 0)
+                        ip = 0xff000000 | (name << CP_BRA_IP_SHIFT);
+        }
+
+        cp_out(ctx, CP_BRA | (mod << 18) | ip | flag |
+                    (state ? 0 : CP_BRA_IF_CLEAR));
+}
+#define cp_bra(c,f,s,n) _cp_bra((c), 0, CP_FLAG_##f, CP_FLAG_##f##_##s, n)
+#ifdef CP_BRA_MOD
+#define cp_cal(c,f,s,n) _cp_bra((c), 1, CP_FLAG_##f, CP_FLAG_##f##_##s, n)
+#define cp_ret(c,f,s) _cp_bra((c), 2, CP_FLAG_##f, CP_FLAG_##f##_##s, 0)
+#endif
+
+static inline void
+_cp_wait(struct nouveau_grctx *ctx, int flag, int state)
+{
+        cp_out(ctx, CP_WAIT | flag | (state ? CP_WAIT_SET : 0));
+}
+#define cp_wait(c,f,s) _cp_wait((c), CP_FLAG_##f, CP_FLAG_##f##_##s)
+
+static inline void
+_cp_set(struct nouveau_grctx *ctx, int flag, int state)
+{
+        cp_out(ctx, CP_SET | flag | (state ? CP_SET_1 : 0));
+}
+#define cp_set(c,f,s) _cp_set((c), CP_FLAG_##f, CP_FLAG_##f##_##s)
+
+static inline void
+cp_pos(struct nouveau_grctx *ctx, int offset)
+{
+        ctx->ctxvals_pos = offset;
+        ctx->ctxvals_base = ctx->ctxvals_pos;
+
+        cp_lsr(ctx, ctx->ctxvals_pos);
+        cp_out(ctx, CP_SET_CONTEXT_POINTER);
+}
+
+static inline void
+gr_def(struct nouveau_grctx *ctx, uint32_t reg, uint32_t val)
+{
+        if (ctx->mode != NOUVEAU_GRCTX_VALS)
+                return;
+
+        reg = (reg - 0x00400000) / 4;
+        reg = (reg - ctx->ctxprog_reg) + ctx->ctxvals_base;
+
+        nv_wo32(ctx->dev, ctx->data, reg, val);
+}
+#endif
+
+#endif
diff --git a/drivers/gpu/drm/nouveau/nouveau_ioc32.c b/drivers/gpu/drm/nouveau/nouveau_ioc32.c
index a2c30f4611ba..475ba810bba3 100644
--- a/drivers/gpu/drm/nouveau/nouveau_ioc32.c
+++ b/drivers/gpu/drm/nouveau/nouveau_ioc32.c
@@ -61,12 +61,10 @@ long nouveau_compat_ioctl(struct file *filp, unsigned int cmd,
         if (nr < DRM_COMMAND_BASE + DRM_ARRAY_SIZE(mga_compat_ioctls))
                 fn = nouveau_compat_ioctls[nr - DRM_COMMAND_BASE];
 #endif
-        lock_kernel();    /* XXX for now */
         if (fn != NULL)
                 ret = (*fn)(filp, cmd, arg);
         else
-                ret = drm_ioctl(filp->f_dentry->d_inode, filp, cmd, arg);
-        unlock_kernel();
+                ret = drm_ioctl(filp, cmd, arg);
 
         return ret;
 }
diff --git a/drivers/gpu/drm/nouveau/nouveau_irq.c b/drivers/gpu/drm/nouveau/nouveau_irq.c
index 370c72c968d1..919a619ca7fa 100644
--- a/drivers/gpu/drm/nouveau/nouveau_irq.c
+++ b/drivers/gpu/drm/nouveau/nouveau_irq.c
@@ -635,6 +635,7 @@ nv50_pgraph_irq_handler(struct drm_device *dev)
 
                 if ((nv_rd32(dev, 0x400500) & isb) != isb)
                         nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) | isb);
+                nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31));
         }
 
         nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
index 5158a12f7844..fb9bdd6edf1f 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
@@ -192,6 +192,92 @@ void nouveau_mem_release(struct drm_file *file_priv, struct mem_block *heap)
 }
 
 /*
+ * NV10-NV40 tiling helpers
+ */
+
+static void
+nv10_mem_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
+                           uint32_t size, uint32_t pitch)
+{
+        struct drm_nouveau_private *dev_priv = dev->dev_private;
+        struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
+        struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
+        struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
+        struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
+
+        tile->addr = addr;
+        tile->size = size;
+        tile->used = !!pitch;
+        nouveau_fence_unref((void **)&tile->fence);
+
+        if (!pfifo->cache_flush(dev))
+                return;
+
+        pfifo->reassign(dev, false);
+        pfifo->cache_flush(dev);
+        pfifo->cache_pull(dev, false);
+
+        nouveau_wait_for_idle(dev);
+
+        pgraph->set_region_tiling(dev, i, addr, size, pitch);
+        pfb->set_region_tiling(dev, i, addr, size, pitch);
+
+        pfifo->cache_pull(dev, true);
+        pfifo->reassign(dev, true);
+}
+
+struct nouveau_tile_reg *
+nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size,
+                    uint32_t pitch)
+{
+        struct drm_nouveau_private *dev_priv = dev->dev_private;
+        struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
+        struct nouveau_tile_reg *tile = dev_priv->tile.reg, *found = NULL;
+        int i;
+
+        spin_lock(&dev_priv->tile.lock);
+
+        for (i = 0; i < pfb->num_tiles; i++) {
+                if (tile[i].used)
+                        /* Tile region in use. */
+                        continue;
+
+                if (tile[i].fence &&
+                    !nouveau_fence_signalled(tile[i].fence, NULL))
+                        /* Pending tile region. */
+                        continue;
+
+                if (max(tile[i].addr, addr) <
+                    min(tile[i].addr + tile[i].size, addr + size))
+                        /* Kill an intersecting tile region. */
+                        nv10_mem_set_region_tiling(dev, i, 0, 0, 0);
+
+                if (pitch && !found) {
+                        /* Free tile region. */
+                        nv10_mem_set_region_tiling(dev, i, addr, size, pitch);
+                        found = &tile[i];
+                }
+        }
+
+        spin_unlock(&dev_priv->tile.lock);
+
+        return found;
+}
+
+void
+nv10_mem_expire_tiling(struct drm_device *dev, struct nouveau_tile_reg *tile,
+                       struct nouveau_fence *fence)
+{
+        if (fence) {
+                /* Mark it as pending. */
+                tile->fence = fence;
+                nouveau_fence_ref(fence);
+        }
+
+        tile->used = false;
+}
+
+/*
  * NV50 VM helpers
  */
 int
@@ -513,6 +599,7 @@ nouveau_mem_init(struct drm_device *dev)
 
         INIT_LIST_HEAD(&dev_priv->ttm.bo_list);
         spin_lock_init(&dev_priv->ttm.bo_list_lock);
+        spin_lock_init(&dev_priv->tile.lock);
 
         dev_priv->fb_available_size = nouveau_mem_fb_amount(dev);
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_object.c b/drivers/gpu/drm/nouveau/nouveau_object.c
index 93379bb81bea..6c2cf81716df 100644
--- a/drivers/gpu/drm/nouveau/nouveau_object.c
+++ b/drivers/gpu/drm/nouveau/nouveau_object.c
@@ -881,7 +881,7 @@ nouveau_gpuobj_gr_new(struct nouveau_channel *chan, int class,
         return 0;
 }
 
-static int
+int
 nouveau_gpuobj_sw_new(struct nouveau_channel *chan, int class,
                       struct nouveau_gpuobj **gpuobj_ret)
 {
diff --git a/drivers/gpu/drm/nouveau/nouveau_reg.h b/drivers/gpu/drm/nouveau/nouveau_reg.h
index fa1b0e7165b9..251f1b3b38b9 100644
--- a/drivers/gpu/drm/nouveau/nouveau_reg.h
+++ b/drivers/gpu/drm/nouveau/nouveau_reg.h
@@ -349,19 +349,19 @@
 #define NV04_PGRAPH_BLEND                                  0x00400824
 #define NV04_PGRAPH_STORED_FMT                             0x00400830
 #define NV04_PGRAPH_PATT_COLORRAM                          0x00400900
-#define NV40_PGRAPH_TILE0(i)                               (0x00400900 + (i*16))
-#define NV40_PGRAPH_TLIMIT0(i)                             (0x00400904 + (i*16))
-#define NV40_PGRAPH_TSIZE0(i)                              (0x00400908 + (i*16))
-#define NV40_PGRAPH_TSTATUS0(i)                            (0x0040090C + (i*16))
+#define NV20_PGRAPH_TILE(i)                                (0x00400900 + (i*16))
+#define NV20_PGRAPH_TLIMIT(i)                              (0x00400904 + (i*16))
+#define NV20_PGRAPH_TSIZE(i)                               (0x00400908 + (i*16))
+#define NV20_PGRAPH_TSTATUS(i)                             (0x0040090C + (i*16))
 #define NV10_PGRAPH_TILE(i)                                (0x00400B00 + (i*16))
 #define NV10_PGRAPH_TLIMIT(i)                              (0x00400B04 + (i*16))
 #define NV10_PGRAPH_TSIZE(i)                               (0x00400B08 + (i*16))
 #define NV10_PGRAPH_TSTATUS(i)                             (0x00400B0C + (i*16))
 #define NV04_PGRAPH_U_RAM                                  0x00400D00
-#define NV47_PGRAPH_TILE0(i)                               (0x00400D00 + (i*16))
-#define NV47_PGRAPH_TLIMIT0(i)                             (0x00400D04 + (i*16))
-#define NV47_PGRAPH_TSIZE0(i)                              (0x00400D08 + (i*16))
-#define NV47_PGRAPH_TSTATUS0(i)                            (0x00400D0C + (i*16))
+#define NV47_PGRAPH_TILE(i)                                (0x00400D00 + (i*16))
+#define NV47_PGRAPH_TLIMIT(i)                              (0x00400D04 + (i*16))
+#define NV47_PGRAPH_TSIZE(i)                               (0x00400D08 + (i*16))
+#define NV47_PGRAPH_TSTATUS(i)                             (0x00400D0C + (i*16))
 #define NV04_PGRAPH_V_RAM                                  0x00400D40
 #define NV04_PGRAPH_W_RAM                                  0x00400D80
 #define NV10_PGRAPH_COMBINER0_IN_ALPHA                     0x00400E40
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
index 2ed41d339f6a..09b9a46dfc0e 100644
--- a/drivers/gpu/drm/nouveau/nouveau_state.c
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
@@ -76,6 +76,8 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
                 engine->fifo.disable            = nv04_fifo_disable;
                 engine->fifo.enable             = nv04_fifo_enable;
                 engine->fifo.reassign           = nv04_fifo_reassign;
+                engine->fifo.cache_flush        = nv04_fifo_cache_flush;
+                engine->fifo.cache_pull         = nv04_fifo_cache_pull;
                 engine->fifo.channel_id         = nv04_fifo_channel_id;
                 engine->fifo.create_context     = nv04_fifo_create_context;
                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
@@ -100,6 +102,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
                 engine->timer.takedown          = nv04_timer_takedown;
                 engine->fb.init                 = nv10_fb_init;
                 engine->fb.takedown             = nv10_fb_takedown;
+                engine->fb.set_region_tiling    = nv10_fb_set_region_tiling;
                 engine->graph.grclass           = nv10_graph_grclass;
                 engine->graph.init              = nv10_graph_init;
                 engine->graph.takedown          = nv10_graph_takedown;
@@ -109,12 +112,15 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
                 engine->graph.fifo_access       = nv04_graph_fifo_access;
                 engine->graph.load_context      = nv10_graph_load_context;
                 engine->graph.unload_context    = nv10_graph_unload_context;
+                engine->graph.set_region_tiling = nv10_graph_set_region_tiling;
                 engine->fifo.channels           = 32;
                 engine->fifo.init               = nv10_fifo_init;
                 engine->fifo.takedown           = nouveau_stub_takedown;
                 engine->fifo.disable            = nv04_fifo_disable;
                 engine->fifo.enable             = nv04_fifo_enable;
                 engine->fifo.reassign           = nv04_fifo_reassign;
+                engine->fifo.cache_flush        = nv04_fifo_cache_flush;
+                engine->fifo.cache_pull         = nv04_fifo_cache_pull;
                 engine->fifo.channel_id         = nv10_fifo_channel_id;
                 engine->fifo.create_context     = nv10_fifo_create_context;
                 engine->fifo.destroy_context    = nv10_fifo_destroy_context;
@@ -139,6 +145,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
                 engine->timer.takedown          = nv04_timer_takedown;
                 engine->fb.init                 = nv10_fb_init;
                 engine->fb.takedown             = nv10_fb_takedown;
+                engine->fb.set_region_tiling    = nv10_fb_set_region_tiling;
                 engine->graph.grclass           = nv20_graph_grclass;
                 engine->graph.init              = nv20_graph_init;
                 engine->graph.takedown          = nv20_graph_takedown;
@@ -148,12 +155,15 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
                 engine->graph.fifo_access       = nv04_graph_fifo_access;
                 engine->graph.load_context      = nv20_graph_load_context;
                 engine->graph.unload_context    = nv20_graph_unload_context;
+                engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
                 engine->fifo.channels           = 32;
                 engine->fifo.init               = nv10_fifo_init;
                 engine->fifo.takedown           = nouveau_stub_takedown;
                 engine->fifo.disable            = nv04_fifo_disable;
                 engine->fifo.enable             = nv04_fifo_enable;
                 engine->fifo.reassign           = nv04_fifo_reassign;
+                engine->fifo.cache_flush        = nv04_fifo_cache_flush;
+                engine->fifo.cache_pull         = nv04_fifo_cache_pull;
                 engine->fifo.channel_id         = nv10_fifo_channel_id;
                 engine->fifo.create_context     = nv10_fifo_create_context;
                 engine->fifo.destroy_context    = nv10_fifo_destroy_context;
@@ -178,6 +188,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
                 engine->timer.takedown          = nv04_timer_takedown;
                 engine->fb.init                 = nv10_fb_init;
                 engine->fb.takedown             = nv10_fb_takedown;
+                engine->fb.set_region_tiling    = nv10_fb_set_region_tiling;
                 engine->graph.grclass           = nv30_graph_grclass;
                 engine->graph.init              = nv30_graph_init;
                 engine->graph.takedown          = nv20_graph_takedown;
@@ -187,12 +198,15 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
                 engine->graph.destroy_context   = nv20_graph_destroy_context;
                 engine->graph.load_context      = nv20_graph_load_context;
                 engine->graph.unload_context    = nv20_graph_unload_context;
+                engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
                 engine->fifo.channels           = 32;
                 engine->fifo.init               = nv10_fifo_init;
                 engine->fifo.takedown           = nouveau_stub_takedown;
                 engine->fifo.disable            = nv04_fifo_disable;
                 engine->fifo.enable             = nv04_fifo_enable;
                 engine->fifo.reassign           = nv04_fifo_reassign;
+                engine->fifo.cache_flush        = nv04_fifo_cache_flush;
+                engine->fifo.cache_pull         = nv04_fifo_cache_pull;
                 engine->fifo.channel_id         = nv10_fifo_channel_id;
                 engine->fifo.create_context     = nv10_fifo_create_context;
                 engine->fifo.destroy_context    = nv10_fifo_destroy_context;
@@ -218,6 +232,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
                 engine->timer.takedown          = nv04_timer_takedown;
                 engine->fb.init                 = nv40_fb_init;
                 engine->fb.takedown             = nv40_fb_takedown;
+                engine->fb.set_region_tiling    = nv40_fb_set_region_tiling;
                 engine->graph.grclass           = nv40_graph_grclass;
                 engine->graph.init              = nv40_graph_init;
                 engine->graph.takedown          = nv40_graph_takedown;
@@ -227,12 +242,15 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
                 engine->graph.destroy_context   = nv40_graph_destroy_context;
                 engine->graph.load_context      = nv40_graph_load_context;
                 engine->graph.unload_context    = nv40_graph_unload_context;
+                engine->graph.set_region_tiling = nv40_graph_set_region_tiling;
                 engine->fifo.channels           = 32;
                 engine->fifo.init               = nv40_fifo_init;
                 engine->fifo.takedown           = nouveau_stub_takedown;
                 engine->fifo.disable            = nv04_fifo_disable;
                 engine->fifo.enable             = nv04_fifo_enable;
                 engine->fifo.reassign           = nv04_fifo_reassign;
+                engine->fifo.cache_flush        = nv04_fifo_cache_flush;
+                engine->fifo.cache_pull         = nv04_fifo_cache_pull;
                 engine->fifo.channel_id         = nv10_fifo_channel_id;
                 engine->fifo.create_context     = nv40_fifo_create_context;
                 engine->fifo.destroy_context    = nv40_fifo_destroy_context;
@@ -299,12 +317,57 @@ nouveau_vga_set_decode(void *priv, bool state)
                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 }
 
+static int
+nouveau_card_init_channel(struct drm_device *dev)
+{
+        struct drm_nouveau_private *dev_priv = dev->dev_private;
+        struct nouveau_gpuobj *gpuobj;
+        int ret;
+
+        ret = nouveau_channel_alloc(dev, &dev_priv->channel,
+                                    (struct drm_file *)-2,
+                                    NvDmaFB, NvDmaTT);
+        if (ret)
+                return ret;
+
+        gpuobj = NULL;
+        ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY,
+                                     0, nouveau_mem_fb_amount(dev),
+                                     NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM,
+                                     &gpuobj);
+        if (ret)
+                goto out_err;
+
+        ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaVRAM,
+                                     gpuobj, NULL);
+        if (ret)
+                goto out_err;
+
+        gpuobj = NULL;
+        ret = nouveau_gpuobj_gart_dma_new(dev_priv->channel, 0,
+                                          dev_priv->gart_info.aper_size,
+                                          NV_DMA_ACCESS_RW, &gpuobj, NULL);
+        if (ret)
+                goto out_err;
+
+        ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaGART,
+                                     gpuobj, NULL);
+        if (ret)
+                goto out_err;
+
+        return 0;
+out_err:
+        nouveau_gpuobj_del(dev, &gpuobj);
+        nouveau_channel_free(dev_priv->channel);
+        dev_priv->channel = NULL;
+        return ret;
+}
+
 int
 nouveau_card_init(struct drm_device *dev)
 {
         struct drm_nouveau_private *dev_priv = dev->dev_private;
         struct nouveau_engine *engine;
-        struct nouveau_gpuobj *gpuobj;
         int ret;
 
         NV_DEBUG(dev, "prev state = %d\n", dev_priv->init_state);
@@ -317,7 +380,7 @@ nouveau_card_init(struct drm_device *dev)
         /* Initialise internal driver API hooks */
         ret = nouveau_init_engine_ptrs(dev);
         if (ret)
-                return ret;
+                goto out;
         engine = &dev_priv->engine;
         dev_priv->init_state = NOUVEAU_CARD_INIT_FAILED;
 
@@ -325,12 +388,12 @@ nouveau_card_init(struct drm_device *dev)
         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
                 ret = nouveau_bios_init(dev);
                 if (ret)
-                        return ret;
+                        goto out;
         }
 
         ret = nouveau_gpuobj_early_init(dev);
         if (ret)
-                return ret;
+                goto out_bios;
 
         /* Initialise instance memory, must happen before mem_init so we
          * know exactly how much VRAM we're able to use for "normal"
@@ -338,100 +401,68 @@ nouveau_card_init(struct drm_device *dev)
          */
         ret = engine->instmem.init(dev);
         if (ret)
-                return ret;
+                goto out_gpuobj_early;
 
         /* Setup the memory manager */
         ret = nouveau_mem_init(dev);
         if (ret)
-                return ret;
+                goto out_instmem;
 
         ret = nouveau_gpuobj_init(dev);
         if (ret)
-                return ret;
+                goto out_mem;
 
         /* PMC */
         ret = engine->mc.init(dev);
         if (ret)
-                return ret;
+                goto out_gpuobj;
 
         /* PTIMER */
         ret = engine->timer.init(dev);
         if (ret)
-                return ret;
+                goto out_mc;
 
         /* PFB */
         ret = engine->fb.init(dev);
         if (ret)
-                return ret;
+                goto out_timer;
 
         /* PGRAPH */
         ret = engine->graph.init(dev);
         if (ret)
-                return ret;
+                goto out_fb;
 
         /* PFIFO */
         ret = engine->fifo.init(dev);
         if (ret)
-                return ret;
+                goto out_graph;
 
         /* this call irq_preinstall, register irq handler and
          * call irq_postinstall
          */
         ret = drm_irq_install(dev);
         if (ret)
-                return ret;
+                goto out_fifo;
 
         ret = drm_vblank_init(dev, 0);
         if (ret)
-                return ret;
+                goto out_irq;
 
         /* what about PVIDEO/PCRTC/PRAMDAC etc? */
 
-        ret = nouveau_channel_alloc(dev, &dev_priv->channel,
-                                    (struct drm_file *)-2,
-                                    NvDmaFB, NvDmaTT);
-        if (ret)
-                return ret;
-
-        gpuobj = NULL;
-        ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY,
-                                     0, nouveau_mem_fb_amount(dev),
-                                     NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM,
-                                     &gpuobj);
-        if (ret)
-                return ret;
-
-        ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaVRAM,
-                                     gpuobj, NULL);
-        if (ret) {
-                nouveau_gpuobj_del(dev, &gpuobj);
-                return ret;
-        }
-
-        gpuobj = NULL;
-        ret = nouveau_gpuobj_gart_dma_new(dev_priv->channel, 0,
-                                          dev_priv->gart_info.aper_size,
-                                          NV_DMA_ACCESS_RW, &gpuobj, NULL);
-        if (ret)
-                return ret;
-
-        ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaGART,
-                                     gpuobj, NULL);
-        if (ret) {
-                nouveau_gpuobj_del(dev, &gpuobj);
-                return ret;
+        if (!engine->graph.accel_blocked) {
+                ret = nouveau_card_init_channel(dev);
+                if (ret)
+                        goto out_irq;
         }
 
         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
-                if (dev_priv->card_type >= NV_50) {
+                if (dev_priv->card_type >= NV_50)
                         ret = nv50_display_create(dev);
-                        if (ret)
-                                return ret;
-                } else {
+                else
                         ret = nv04_display_create(dev);
-                        if (ret)
-                                return ret;
-                }
+                if (ret)
+                        goto out_irq;
         }
 
         ret = nouveau_backlight_init(dev);
@@ -444,6 +475,32 @@ nouveau_card_init(struct drm_device *dev)
                 drm_helper_initial_config(dev);
 
         return 0;
+
+out_irq:
+        drm_irq_uninstall(dev);
+out_fifo:
+        engine->fifo.takedown(dev);
+out_graph:
+        engine->graph.takedown(dev);
+out_fb:
+        engine->fb.takedown(dev);
+out_timer:
+        engine->timer.takedown(dev);
+out_mc:
+        engine->mc.takedown(dev);
+out_gpuobj:
+        nouveau_gpuobj_takedown(dev);
+out_mem:
+        nouveau_mem_close(dev);
+out_instmem:
+        engine->instmem.takedown(dev);
+out_gpuobj_early:
+        nouveau_gpuobj_late_takedown(dev);
+out_bios:
+        nouveau_bios_takedown(dev);
+out:
+        vga_client_register(dev->pdev, NULL, NULL, NULL);
+        return ret;
 }
 
 static void nouveau_card_takedown(struct drm_device *dev)
@@ -585,7 +642,10 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
                 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
         /* NV04 or NV05 */
         } else if ((reg0 & 0xff00fff0) == 0x20004000) {
-                dev_priv->chipset = 0x04;
+                if (reg0 & 0x00f00000)
+                        dev_priv->chipset = 0x05;
+                else
+                        dev_priv->chipset = 0x04;
         } else
                 dev_priv->chipset = 0xff;
 
@@ -665,8 +725,8 @@ static void nouveau_close(struct drm_device *dev)
 {
         struct drm_nouveau_private *dev_priv = dev->dev_private;
 
-        /* In the case of an error dev_priv may not be be allocated yet */
-        if (dev_priv && dev_priv->card_type)
+        /* In the case of an error dev_priv may not be allocated yet */
+        if (dev_priv)
                 nouveau_card_takedown(dev);
 }
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c b/drivers/gpu/drm/nouveau/nouveau_ttm.c
index 187eb84e4da5..c385d50f041b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_ttm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c
@@ -28,45 +28,17 @@
 
 #include "nouveau_drv.h"
 
-static struct vm_operations_struct nouveau_ttm_vm_ops;
-static const struct vm_operations_struct *ttm_vm_ops;
-
-static int
-nouveau_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
-{
-        struct ttm_buffer_object *bo = vma->vm_private_data;
-        int ret;
-
-        if (unlikely(bo == NULL))
-                return VM_FAULT_NOPAGE;
-
-        ret = ttm_vm_ops->fault(vma, vmf);
-        return ret;
-}
-
 int
 nouveau_ttm_mmap(struct file *filp, struct vm_area_struct *vma)
 {
         struct drm_file *file_priv = filp->private_data;
         struct drm_nouveau_private *dev_priv =
                 file_priv->minor->dev->dev_private;
-        int ret;
 
         if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
                 return drm_mmap(filp, vma);
 
-        ret = ttm_bo_mmap(filp, vma, &dev_priv->ttm.bdev);
-        if (unlikely(ret != 0))
-                return ret;
-
-        if (unlikely(ttm_vm_ops == NULL)) {
-                ttm_vm_ops = vma->vm_ops;
-                nouveau_ttm_vm_ops = *ttm_vm_ops;
-                nouveau_ttm_vm_ops.fault = &nouveau_ttm_fault;
-        }
-
-        vma->vm_ops = &nouveau_ttm_vm_ops;
-        return 0;
+        return ttm_bo_mmap(filp, vma, &dev_priv->ttm.bdev);
 }
 
 static int
diff --git a/drivers/gpu/drm/nouveau/nv04_crtc.c b/drivers/gpu/drm/nouveau/nv04_crtc.c
index b91363606055..d2f143ed97c1 100644
--- a/drivers/gpu/drm/nouveau/nv04_crtc.c
+++ b/drivers/gpu/drm/nouveau/nv04_crtc.c
@@ -143,10 +143,10 @@ static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mod
         state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK;
 
         if (pv->NM2)
-                NV_TRACE(dev, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n",
+                NV_DEBUG_KMS(dev, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n",
                          pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P);
         else
-                NV_TRACE(dev, "vpll: n %d m %d log2p %d\n",
+                NV_DEBUG_KMS(dev, "vpll: n %d m %d log2p %d\n",
                          pv->N1, pv->M1, pv->log2P);
 
         nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset);
@@ -160,7 +160,7 @@ nv_crtc_dpms(struct drm_crtc *crtc, int mode)
         unsigned char seq1 = 0, crtc17 = 0;
         unsigned char crtc1A;
 
-        NV_TRACE(dev, "Setting dpms mode %d on CRTC %d\n", mode,
+        NV_DEBUG_KMS(dev, "Setting dpms mode %d on CRTC %d\n", mode,
                                                         nv_crtc->index);
 
         if (nv_crtc->last_dpms == mode) /* Don't do unnecesary mode changes. */
@@ -603,7 +603,7 @@ nv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
         struct drm_nouveau_private *dev_priv = dev->dev_private;
 
-        NV_DEBUG(dev, "CTRC mode on CRTC %d:\n", nv_crtc->index);
+        NV_DEBUG_KMS(dev, "CTRC mode on CRTC %d:\n", nv_crtc->index);
         drm_mode_debug_printmodeline(adjusted_mode);
 
         /* unlock must come after turning off FP_TG_CONTROL in output_prepare */
@@ -703,7 +703,7 @@ static void nv_crtc_destroy(struct drm_crtc *crtc)
 {
         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 
-        NV_DEBUG(crtc->dev, "\n");
+        NV_DEBUG_KMS(crtc->dev, "\n");
 
         if (!nv_crtc)
                 return;
diff --git a/drivers/gpu/drm/nouveau/nv04_dac.c b/drivers/gpu/drm/nouveau/nv04_dac.c
index a5fa51714e87..d0e038d28948 100644
--- a/drivers/gpu/drm/nouveau/nv04_dac.c
+++ b/drivers/gpu/drm/nouveau/nv04_dac.c
@@ -205,23 +205,22 @@ out:
         NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1);
 
         if (blue == 0x18) {
-                NV_TRACE(dev, "Load detected on head A\n");
+                NV_INFO(dev, "Load detected on head A\n");
                 return connector_status_connected;
         }
 
         return connector_status_disconnected;
 }
 
-enum drm_connector_status nv17_dac_detect(struct drm_encoder *encoder,
-                                          struct drm_connector *connector)
+uint32_t nv17_dac_sample_load(struct drm_encoder *encoder)
 {
         struct drm_device *dev = encoder->dev;
         struct drm_nouveau_private *dev_priv = dev->dev_private;
         struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb;
-        uint32_t testval, regoffset = nv04_dac_output_offset(encoder);
+        uint32_t sample, testval, regoffset = nv04_dac_output_offset(encoder);
         uint32_t saved_powerctrl_2 = 0, saved_powerctrl_4 = 0, saved_routput,
                 saved_rtest_ctrl, saved_gpio0, saved_gpio1, temp, routput;
-        int head, present = 0;
+        int head;
 
 #define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20)
         if (dcb->type == OUTPUT_TV) {
@@ -287,13 +286,7 @@ enum drm_connector_status nv17_dac_detect(struct drm_encoder *encoder,
                       temp | NV_PRAMDAC_TEST_CONTROL_TP_INS_EN_ASSERTED);
         msleep(5);
 
-        temp = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
-
-        if (dcb->type == OUTPUT_TV)
-                present = (nv17_tv_detect(encoder, connector, temp)
-                           == connector_status_connected);
-        else
-                present = temp & NV_PRAMDAC_TEST_CONTROL_SENSEB_ALLHI;
+        sample = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
 
         temp = NVReadRAMDAC(dev, head, NV_PRAMDAC_TEST_CONTROL);
         NVWriteRAMDAC(dev, head, NV_PRAMDAC_TEST_CONTROL,
@@ -310,15 +303,25 @@ enum drm_connector_status nv17_dac_detect(struct drm_encoder *encoder,
         nv17_gpio_set(dev, DCB_GPIO_TVDAC1, saved_gpio1);
         nv17_gpio_set(dev, DCB_GPIO_TVDAC0, saved_gpio0);
 
-        if (present) {
-                NV_INFO(dev, "Load detected on output %c\n", '@' + ffs(dcb->or));
+        return sample;
+}
+
+static enum drm_connector_status
+nv17_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
+{
+        struct drm_device *dev = encoder->dev;
+        struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb;
+        uint32_t sample = nv17_dac_sample_load(encoder);
+
+        if (sample & NV_PRAMDAC_TEST_CONTROL_SENSEB_ALLHI) {
+                NV_INFO(dev, "Load detected on output %c\n",
+                        '@' + ffs(dcb->or));
                 return connector_status_connected;
+        } else {
+                return connector_status_disconnected;
         }
-
-        return connector_status_disconnected;
 }
 
-
 static bool nv04_dac_mode_fixup(struct drm_encoder *encoder,
                                 struct drm_display_mode *mode,
                                 struct drm_display_mode *adjusted_mode)
@@ -350,14 +353,10 @@ static void nv04_dac_mode_set(struct drm_encoder *encoder,
                               struct drm_display_mode *mode,
                               struct drm_display_mode *adjusted_mode)
 {
-        struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
         struct drm_device *dev = encoder->dev;
         struct drm_nouveau_private *dev_priv = dev->dev_private;
         int head = nouveau_crtc(encoder->crtc)->index;
 
-        NV_TRACE(dev, "%s called for encoder %d\n", __func__,
-                      nv_encoder->dcb->index);
-
         if (nv_gf4_disp_arch(dev)) {
                 struct drm_encoder *rebind;
                 uint32_t dac_offset = nv04_dac_output_offset(encoder);
@@ -466,7 +465,7 @@ static void nv04_dac_destroy(struct drm_encoder *encoder)
 {
         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 
-        NV_DEBUG(encoder->dev, "\n");
+        NV_DEBUG_KMS(encoder->dev, "\n");
 
         drm_encoder_cleanup(encoder);
         kfree(nv_encoder);
diff --git a/drivers/gpu/drm/nouveau/nv04_dfp.c b/drivers/gpu/drm/nouveau/nv04_dfp.c
index e5b33339d595..483f875bdb6a 100644
--- a/drivers/gpu/drm/nouveau/nv04_dfp.c
+++ b/drivers/gpu/drm/nouveau/nv04_dfp.c
@@ -261,7 +261,7 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder,
         struct drm_display_mode *output_mode = &nv_encoder->mode;
         uint32_t mode_ratio, panel_ratio;
 
-        NV_DEBUG(dev, "Output mode on CRTC %d:\n", nv_crtc->index);
+        NV_DEBUG_KMS(dev, "Output mode on CRTC %d:\n", nv_crtc->index);
         drm_mode_debug_printmodeline(output_mode);
 
         /* Initialize the FP registers in this CRTC. */
@@ -413,7 +413,9 @@ static void nv04_dfp_commit(struct drm_encoder *encoder)
         struct dcb_entry *dcbe = nv_encoder->dcb;
         int head = nouveau_crtc(encoder->crtc)->index;
 
-        NV_TRACE(dev, "%s called for encoder %d\n", __func__, nv_encoder->dcb->index);
+        NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n",
+                drm_get_connector_name(&nouveau_encoder_connector_get(nv_encoder)->base),
+                nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
 
         if (dcbe->type == OUTPUT_TMDS)
                 run_tmds_table(dev, dcbe, head, nv_encoder->mode.clock);
@@ -550,7 +552,7 @@ static void nv04_dfp_destroy(struct drm_encoder *encoder)
 {
         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 
-        NV_DEBUG(encoder->dev, "\n");
+        NV_DEBUG_KMS(encoder->dev, "\n");
 
         drm_encoder_cleanup(encoder);
         kfree(nv_encoder);
diff --git a/drivers/gpu/drm/nouveau/nv04_display.c b/drivers/gpu/drm/nouveau/nv04_display.c
index b47c757ff48b..ef77215fa5b9 100644
--- a/drivers/gpu/drm/nouveau/nv04_display.c
+++ b/drivers/gpu/drm/nouveau/nv04_display.c
@@ -99,10 +99,11 @@ nv04_display_create(struct drm_device *dev)
         uint16_t connector[16] = { 0 };
         int i, ret;
 
-        NV_DEBUG(dev, "\n");
+        NV_DEBUG_KMS(dev, "\n");
 
         if (nv_two_heads(dev))
                 nv04_display_store_initial_head_owner(dev);
+        nouveau_hw_save_vga_fonts(dev, 1);
 
         drm_mode_config_init(dev);
         drm_mode_create_scaling_mode_property(dev);
@@ -203,8 +204,6 @@ nv04_display_create(struct drm_device *dev)
         /* Save previous state */
         NVLockVgaCrtcs(dev, false);
 
-        nouveau_hw_save_vga_fonts(dev, 1);
-
         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
                 crtc->funcs->save(crtc);
 
@@ -223,7 +222,7 @@ nv04_display_destroy(struct drm_device *dev)
         struct drm_encoder *encoder;
         struct drm_crtc *crtc;
 
-        NV_DEBUG(dev, "\n");
+        NV_DEBUG_KMS(dev, "\n");
 
         /* Turn every CRTC off. */
         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
@@ -246,9 +245,9 @@ nv04_display_destroy(struct drm_device *dev)
         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
                 crtc->funcs->restore(crtc);
 
-        nouveau_hw_save_vga_fonts(dev, 0);
-
         drm_mode_config_cleanup(dev);
+
+        nouveau_hw_save_vga_fonts(dev, 0);
 }
 
 void
diff --git a/drivers/gpu/drm/nouveau/nv04_fbcon.c b/drivers/gpu/drm/nouveau/nv04_fbcon.c
index 09a31071ee58..d910873c1368 100644
--- a/drivers/gpu/drm/nouveau/nv04_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nv04_fbcon.c
@@ -39,8 +39,7 @@ nv04_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region)
                 return;
 
         if (!(info->flags & FBINFO_HWACCEL_DISABLED) && RING_SPACE(chan, 4)) {
-                NV_ERROR(dev, "GPU lockup - switching to software fbcon\n");
-                info->flags |= FBINFO_HWACCEL_DISABLED;
+                nouveau_fbcon_gpu_lockup(info);
         }
 
         if (info->flags & FBINFO_HWACCEL_DISABLED) {
@@ -62,14 +61,12 @@ nv04_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
         struct drm_device *dev = par->dev;
         struct drm_nouveau_private *dev_priv = dev->dev_private;
         struct nouveau_channel *chan = dev_priv->channel;
-        uint32_t color = ((uint32_t *) info->pseudo_palette)[rect->color];
 
         if (info->state != FBINFO_STATE_RUNNING)
                 return;
 
         if (!(info->flags & FBINFO_HWACCEL_DISABLED) && RING_SPACE(chan, 7)) {
-                NV_ERROR(dev, "GPU lockup - switching to software fbcon\n");
-                info->flags |= FBINFO_HWACCEL_DISABLED;
+                nouveau_fbcon_gpu_lockup(info);
         }
 
         if (info->flags & FBINFO_HWACCEL_DISABLED) {
@@ -80,7 +77,11 @@ nv04_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
         BEGIN_RING(chan, NvSubGdiRect, 0x02fc, 1);
         OUT_RING(chan, (rect->rop != ROP_COPY) ? 1 : 3);
         BEGIN_RING(chan, NvSubGdiRect, 0x03fc, 1);
-        OUT_RING(chan, color);
+        if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
+            info->fix.visual == FB_VISUAL_DIRECTCOLOR)
+                OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]);
+        else
+                OUT_RING(chan, rect->color);
         BEGIN_RING(chan, NvSubGdiRect, 0x0400, 2);
         OUT_RING(chan, (rect->dx << 16) | rect->dy);
         OUT_RING(chan, (rect->width << 16) | rect->height);
@@ -109,8 +110,7 @@ nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
         }
 
         if (!(info->flags & FBINFO_HWACCEL_DISABLED) && RING_SPACE(chan, 8)) {
-                NV_ERROR(dev, "GPU lockup - switching to software fbcon\n");
-                info->flags |= FBINFO_HWACCEL_DISABLED;
+                nouveau_fbcon_gpu_lockup(info);
         }
 
         if (info->flags & FBINFO_HWACCEL_DISABLED) {
@@ -144,8 +144,7 @@ nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
                 int iter_len = dsize > 128 ? 128 : dsize;
 
                 if (RING_SPACE(chan, iter_len + 1)) {
-                        NV_ERROR(dev, "GPU lockup - switching to software fbcon\n");
-                        info->flags |= FBINFO_HWACCEL_DISABLED;
+                        nouveau_fbcon_gpu_lockup(info);
                         cfb_imageblit(info, image);
                         return;
                 }
@@ -184,6 +183,7 @@ nv04_fbcon_accel_init(struct fb_info *info)
         struct drm_device *dev = par->dev;
         struct drm_nouveau_private *dev_priv = dev->dev_private;
         struct nouveau_channel *chan = dev_priv->channel;
+        const int sub = NvSubCtxSurf2D;
         int surface_fmt, pattern_fmt, rect_fmt;
         int ret;
 
@@ -242,30 +242,29 @@ nv04_fbcon_accel_init(struct fb_info *info)
                 return ret;
 
         if (RING_SPACE(chan, 49)) {
-                NV_ERROR(dev, "GPU lockup - switching to software fbcon\n");
-                info->flags |= FBINFO_HWACCEL_DISABLED;
+                nouveau_fbcon_gpu_lockup(info);
                 return 0;
         }
 
-        BEGIN_RING(chan, 1, 0x0000, 1);
+        BEGIN_RING(chan, sub, 0x0000, 1);
         OUT_RING(chan, NvCtxSurf2D);
-        BEGIN_RING(chan, 1, 0x0184, 2);
+        BEGIN_RING(chan, sub, 0x0184, 2);
         OUT_RING(chan, NvDmaFB);
         OUT_RING(chan, NvDmaFB);
-        BEGIN_RING(chan, 1, 0x0300, 4);
+        BEGIN_RING(chan, sub, 0x0300, 4);
         OUT_RING(chan, surface_fmt);
         OUT_RING(chan, info->fix.line_length | (info->fix.line_length << 16));
         OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base);
         OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base);
 
-        BEGIN_RING(chan, 1, 0x0000, 1);
+        BEGIN_RING(chan, sub, 0x0000, 1);
         OUT_RING(chan, NvRop);
-        BEGIN_RING(chan, 1, 0x0300, 1);
+        BEGIN_RING(chan, sub, 0x0300, 1);
         OUT_RING(chan, 0x55);
 
-        BEGIN_RING(chan, 1, 0x0000, 1);
+        BEGIN_RING(chan, sub, 0x0000, 1);
         OUT_RING(chan, NvImagePatt);
-        BEGIN_RING(chan, 1, 0x0300, 8);
+        BEGIN_RING(chan, sub, 0x0300, 8);
         OUT_RING(chan, pattern_fmt);
 #ifdef __BIG_ENDIAN
         OUT_RING(chan, 2);
@@ -279,9 +278,9 @@ nv04_fbcon_accel_init(struct fb_info *info)
         OUT_RING(chan, ~0);
         OUT_RING(chan, ~0);
 
-        BEGIN_RING(chan, 1, 0x0000, 1);
+        BEGIN_RING(chan, sub, 0x0000, 1);
         OUT_RING(chan, NvClipRect);
-        BEGIN_RING(chan, 1, 0x0300, 2);
+        BEGIN_RING(chan, sub, 0x0300, 2);
         OUT_RING(chan, 0);
         OUT_RING(chan, (info->var.yres_virtual << 16) | info->var.xres_virtual);
 
diff --git a/drivers/gpu/drm/nouveau/nv04_fifo.c b/drivers/gpu/drm/nouveau/nv04_fifo.c
index 0c3cd53c7313..f31347b8c9b0 100644
--- a/drivers/gpu/drm/nouveau/nv04_fifo.c
+++ b/drivers/gpu/drm/nouveau/nv04_fifo.c
@@ -71,6 +71,40 @@ nv04_fifo_reassign(struct drm_device *dev, bool enable)
         return (reassign == 1);
 }
 
+bool
+nv04_fifo_cache_flush(struct drm_device *dev)
+{
+        struct drm_nouveau_private *dev_priv = dev->dev_private;
+        struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
+        uint64_t start = ptimer->read(dev);
+
+        do {
+                if (nv_rd32(dev, NV03_PFIFO_CACHE1_GET) ==
+                    nv_rd32(dev, NV03_PFIFO_CACHE1_PUT))
+                        return true;
+
+        } while (ptimer->read(dev) - start < 100000000);
+
+        NV_ERROR(dev, "Timeout flushing the PFIFO cache.\n");
+
+        return false;
+}
+
+bool
+nv04_fifo_cache_pull(struct drm_device *dev, bool enable)
+{
+        uint32_t pull = nv_rd32(dev, NV04_PFIFO_CACHE1_PULL0);
+
+        if (enable) {
+                nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, pull | 1);
+        } else {
+                nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, pull & ~1);
+                nv_wr32(dev, NV04_PFIFO_CACHE1_HASH, 0);
+        }
+
+        return !!(pull & 1);
+}
+
 int
 nv04_fifo_channel_id(struct drm_device *dev)
 {
diff --git a/drivers/gpu/drm/nouveau/nv04_graph.c b/drivers/gpu/drm/nouveau/nv04_graph.c
index 396ee92118f6..e260986ea65a 100644
--- a/drivers/gpu/drm/nouveau/nv04_graph.c
+++ b/drivers/gpu/drm/nouveau/nv04_graph.c
@@ -28,6 +28,10 @@
 #include "nouveau_drv.h"
 
 static uint32_t nv04_graph_ctx_regs[] = {
+        0x0040053c,
+        0x00400544,
+        0x00400540,
+        0x00400548,
         NV04_PGRAPH_CTX_SWITCH1,
         NV04_PGRAPH_CTX_SWITCH2,
         NV04_PGRAPH_CTX_SWITCH3,
@@ -102,69 +106,69 @@ static uint32_t nv04_graph_ctx_regs[] = {
         NV04_PGRAPH_PATT_COLOR0,
         NV04_PGRAPH_PATT_COLOR1,
         NV04_PGRAPH_PATT_COLORRAM+0x00,
-        NV04_PGRAPH_PATT_COLORRAM+0x01,
-        NV04_PGRAPH_PATT_COLORRAM+0x02,
-        NV04_PGRAPH_PATT_COLORRAM+0x03,
         NV04_PGRAPH_PATT_COLORRAM+0x04,
-        NV04_PGRAPH_PATT_COLORRAM+0x05,
-        NV04_PGRAPH_PATT_COLORRAM+0x06,
-        NV04_PGRAPH_PATT_COLORRAM+0x07,
         NV04_PGRAPH_PATT_COLORRAM+0x08,
-        NV04_PGRAPH_PATT_COLORRAM+0x09,
-        NV04_PGRAPH_PATT_COLORRAM+0x0A,
-        NV04_PGRAPH_PATT_COLORRAM+0x0B,
-        NV04_PGRAPH_PATT_COLORRAM+0x0C,
-        NV04_PGRAPH_PATT_COLORRAM+0x0D,
-        NV04_PGRAPH_PATT_COLORRAM+0x0E,
-        NV04_PGRAPH_PATT_COLORRAM+0x0F,
+        NV04_PGRAPH_PATT_COLORRAM+0x0c,
         NV04_PGRAPH_PATT_COLORRAM+0x10,
-        NV04_PGRAPH_PATT_COLORRAM+0x11,
-        NV04_PGRAPH_PATT_COLORRAM+0x12,
-        NV04_PGRAPH_PATT_COLORRAM+0x13,
         NV04_PGRAPH_PATT_COLORRAM+0x14,
-        NV04_PGRAPH_PATT_COLORRAM+0x15,
-        NV04_PGRAPH_PATT_COLORRAM+0x16,
-        NV04_PGRAPH_PATT_COLORRAM+0x17,
         NV04_PGRAPH_PATT_COLORRAM+0x18,
-        NV04_PGRAPH_PATT_COLORRAM+0x19,
-        NV04_PGRAPH_PATT_COLORRAM+0x1A,
-        NV04_PGRAPH_PATT_COLORRAM+0x1B,
-        NV04_PGRAPH_PATT_COLORRAM+0x1C,
-        NV04_PGRAPH_PATT_COLORRAM+0x1D,
-        NV04_PGRAPH_PATT_COLORRAM+0x1E,
-        NV04_PGRAPH_PATT_COLORRAM+0x1F,
+        NV04_PGRAPH_PATT_COLORRAM+0x1c,
         NV04_PGRAPH_PATT_COLORRAM+0x20,
-        NV04_PGRAPH_PATT_COLORRAM+0x21,
-        NV04_PGRAPH_PATT_COLORRAM+0x22,
-        NV04_PGRAPH_PATT_COLORRAM+0x23,
         NV04_PGRAPH_PATT_COLORRAM+0x24,
-        NV04_PGRAPH_PATT_COLORRAM+0x25,
-        NV04_PGRAPH_PATT_COLORRAM+0x26,
-        NV04_PGRAPH_PATT_COLORRAM+0x27,
         NV04_PGRAPH_PATT_COLORRAM+0x28,
-        NV04_PGRAPH_PATT_COLORRAM+0x29,
-        NV04_PGRAPH_PATT_COLORRAM+0x2A,
-        NV04_PGRAPH_PATT_COLORRAM+0x2B,
-        NV04_PGRAPH_PATT_COLORRAM+0x2C,
-        NV04_PGRAPH_PATT_COLORRAM+0x2D,
-        NV04_PGRAPH_PATT_COLORRAM+0x2E,
-        NV04_PGRAPH_PATT_COLORRAM+0x2F,
+        NV04_PGRAPH_PATT_COLORRAM+0x2c,
         NV04_PGRAPH_PATT_COLORRAM+0x30,
-        NV04_PGRAPH_PATT_COLORRAM+0x31,
-        NV04_PGRAPH_PATT_COLORRAM+0x32,
-        NV04_PGRAPH_PATT_COLORRAM+0x33,
         NV04_PGRAPH_PATT_COLORRAM+0x34,
-        NV04_PGRAPH_PATT_COLORRAM+0x35,
-        NV04_PGRAPH_PATT_COLORRAM+0x36,
-        NV04_PGRAPH_PATT_COLORRAM+0x37,
         NV04_PGRAPH_PATT_COLORRAM+0x38,
-        NV04_PGRAPH_PATT_COLORRAM+0x39,
-        NV04_PGRAPH_PATT_COLORRAM+0x3A,
-        NV04_PGRAPH_PATT_COLORRAM+0x3B,
-        NV04_PGRAPH_PATT_COLORRAM+0x3C,
-        NV04_PGRAPH_PATT_COLORRAM+0x3D,
-        NV04_PGRAPH_PATT_COLORRAM+0x3E,
-        NV04_PGRAPH_PATT_COLORRAM+0x3F,
+        NV04_PGRAPH_PATT_COLORRAM+0x3c,
+        NV04_PGRAPH_PATT_COLORRAM+0x40,
+        NV04_PGRAPH_PATT_COLORRAM+0x44,
+        NV04_PGRAPH_PATT_COLORRAM+0x48,
+        NV04_PGRAPH_PATT_COLORRAM+0x4c,
+        NV04_PGRAPH_PATT_COLORRAM+0x50,
+        NV04_PGRAPH_PATT_COLORRAM+0x54,
+        NV04_PGRAPH_PATT_COLORRAM+0x58,
+        NV04_PGRAPH_PATT_COLORRAM+0x5c,
+        NV04_PGRAPH_PATT_COLORRAM+0x60,
+        NV04_PGRAPH_PATT_COLORRAM+0x64,
+        NV04_PGRAPH_PATT_COLORRAM+0x68,
+        NV04_PGRAPH_PATT_COLORRAM+0x6c,
+        NV04_PGRAPH_PATT_COLORRAM+0x70,
+        NV04_PGRAPH_PATT_COLORRAM+0x74,
+        NV04_PGRAPH_PATT_COLORRAM+0x78,
+        NV04_PGRAPH_PATT_COLORRAM+0x7c,
+        NV04_PGRAPH_PATT_COLORRAM+0x80,
+        NV04_PGRAPH_PATT_COLORRAM+0x84,
+        NV04_PGRAPH_PATT_COLORRAM+0x88,
+        NV04_PGRAPH_PATT_COLORRAM+0x8c,
+        NV04_PGRAPH_PATT_COLORRAM+0x90,
+        NV04_PGRAPH_PATT_COLORRAM+0x94,
+        NV04_PGRAPH_PATT_COLORRAM+0x98,
+        NV04_PGRAPH_PATT_COLORRAM+0x9c,
+        NV04_PGRAPH_PATT_COLORRAM+0xa0,
+        NV04_PGRAPH_PATT_COLORRAM+0xa4,
+        NV04_PGRAPH_PATT_COLORRAM+0xa8,
+        NV04_PGRAPH_PATT_COLORRAM+0xac,
+        NV04_PGRAPH_PATT_COLORRAM+0xb0,
+        NV04_PGRAPH_PATT_COLORRAM+0xb4,
+        NV04_PGRAPH_PATT_COLORRAM+0xb8,
+        NV04_PGRAPH_PATT_COLORRAM+0xbc,
+        NV04_PGRAPH_PATT_COLORRAM+0xc0,
+        NV04_PGRAPH_PATT_COLORRAM+0xc4,
+        NV04_PGRAPH_PATT_COLORRAM+0xc8,
+        NV04_PGRAPH_PATT_COLORRAM+0xcc,
+        NV04_PGRAPH_PATT_COLORRAM+0xd0,
+        NV04_PGRAPH_PATT_COLORRAM+0xd4,
+        NV04_PGRAPH_PATT_COLORRAM+0xd8,
+        NV04_PGRAPH_PATT_COLORRAM+0xdc,
+        NV04_PGRAPH_PATT_COLORRAM+0xe0,
+        NV04_PGRAPH_PATT_COLORRAM+0xe4,
+        NV04_PGRAPH_PATT_COLORRAM+0xe8,
+        NV04_PGRAPH_PATT_COLORRAM+0xec,
+        NV04_PGRAPH_PATT_COLORRAM+0xf0,
+        NV04_PGRAPH_PATT_COLORRAM+0xf4,
+        NV04_PGRAPH_PATT_COLORRAM+0xf8,
+        NV04_PGRAPH_PATT_COLORRAM+0xfc,
         NV04_PGRAPH_PATTERN,
         0x0040080c,
         NV04_PGRAPH_PATTERN_SHAPE,
@@ -247,14 +251,6 @@ static uint32_t nv04_graph_ctx_regs[] = {
         0x004004f8,
         0x0040047c,
         0x004004fc,
-        0x0040053c,
-        0x00400544,
-        0x00400540,
-        0x00400548,
-        0x00400560,
-        0x00400568,
-        0x00400564,
-        0x0040056c,
         0x00400534,
         0x00400538,
         0x00400514,
@@ -341,9 +337,8 @@ static uint32_t nv04_graph_ctx_regs[] = {
         0x00400500,
         0x00400504,
         NV04_PGRAPH_VALID1,
-        NV04_PGRAPH_VALID2
-
-
+        NV04_PGRAPH_VALID2,
+        NV04_PGRAPH_DEBUG_3
 };
 
 struct graph_state {
@@ -388,6 +383,18 @@ nv04_graph_context_switch(struct drm_device *dev)
         pgraph->fifo_access(dev, true);
 }
 
+static uint32_t *ctx_reg(struct graph_state *ctx, uint32_t reg)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++) {
+                if (nv04_graph_ctx_regs[i] == reg)
+                        return &ctx->nv04[i];
+        }
+
+        return NULL;
+}
+
 int nv04_graph_create_context(struct nouveau_channel *chan)
 {
         struct graph_state *pgraph_ctx;
@@ -398,15 +405,8 @@ int nv04_graph_create_context(struct nouveau_channel *chan)
         if (pgraph_ctx == NULL)
                 return -ENOMEM;
 
-        /* dev_priv->fifos[channel].pgraph_ctx_user = channel << 24; */
-        pgraph_ctx->nv04[0] = 0x0001ffff;
-        /* is it really needed ??? */
-#if 0
-        dev_priv->fifos[channel].pgraph_ctx[1] =
-                                        nv_rd32(dev, NV_PGRAPH_DEBUG_4);
-        dev_priv->fifos[channel].pgraph_ctx[2] =
-                                        nv_rd32(dev, 0x004006b0);
-#endif
+        *ctx_reg(pgraph_ctx, NV04_PGRAPH_DEBUG_3) = 0xfad4ff31;
+
         return 0;
 }
 
@@ -429,9 +429,13 @@ int nv04_graph_load_context(struct nouveau_channel *chan)
                 nv_wr32(dev, nv04_graph_ctx_regs[i], pgraph_ctx->nv04[i]);
 
         nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL, 0x10010100);
-        nv_wr32(dev, NV04_PGRAPH_CTX_USER, chan->id << 24);
+
+        tmp  = nv_rd32(dev, NV04_PGRAPH_CTX_USER) & 0x00ffffff;
+        nv_wr32(dev, NV04_PGRAPH_CTX_USER, tmp | chan->id << 24);
+
         tmp = nv_rd32(dev, NV04_PGRAPH_FFINTFC_ST2);
         nv_wr32(dev, NV04_PGRAPH_FFINTFC_ST2, tmp & 0x000fffff);
+
         return 0;
 }
 
@@ -494,7 +498,7 @@ int nv04_graph_init(struct drm_device *dev)
         nv_wr32(dev, NV04_PGRAPH_STATE        , 0xFFFFFFFF);
         nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL  , 0x10000100);
         tmp  = nv_rd32(dev, NV04_PGRAPH_CTX_USER) & 0x00ffffff;
-        tmp |= dev_priv->engine.fifo.channels << 24;
+        tmp |= (dev_priv->engine.fifo.channels - 1) << 24;
         nv_wr32(dev, NV04_PGRAPH_CTX_USER, tmp);
 
         /* These don't belong here, they're part of a per-channel context */
@@ -533,7 +537,7 @@ nv04_graph_mthd_set_operation(struct nouveau_channel *chan, int grclass,
                               int mthd, uint32_t data)
 {
         struct drm_device *dev = chan->dev;
-        uint32_t instance = nv_rd32(dev, NV04_PGRAPH_CTX_SWITCH4) & 0xffff;
+        uint32_t instance = (nv_rd32(dev, NV04_PGRAPH_CTX_SWITCH4) & 0xffff) << 4;
         int subc = (nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7;
         uint32_t tmp;
 
@@ -543,11 +547,11 @@ nv04_graph_mthd_set_operation(struct nouveau_channel *chan, int grclass,
 
         nv_wi32(dev, instance, tmp);
         nv_wr32(dev, NV04_PGRAPH_CTX_SWITCH1, tmp);
-        nv_wr32(dev, NV04_PGRAPH_CTX_CACHE1 + subc, tmp);
+        nv_wr32(dev, NV04_PGRAPH_CTX_CACHE1 + (subc<<2), tmp);
         return 0;
 }
 
-static struct nouveau_pgraph_object_method nv04_graph_mthds_m2mf[] = {
+static struct nouveau_pgraph_object_method nv04_graph_mthds_sw[] = {
         { 0x0150, nv04_graph_mthd_set_ref },
         {}
 };
@@ -558,7 +562,7 @@ static struct nouveau_pgraph_object_method nv04_graph_mthds_set_operation[] = {
 };
 
 struct nouveau_pgraph_object_class nv04_graph_grclass[] = {
-        { 0x0039, false, nv04_graph_mthds_m2mf },
+        { 0x0039, false, NULL },
         { 0x004a, false, nv04_graph_mthds_set_operation }, /* gdirect */
         { 0x005f, false, nv04_graph_mthds_set_operation }, /* imageblit */
         { 0x0061, false, nv04_graph_mthds_set_operation }, /* ifc */
@@ -574,6 +578,7 @@ struct nouveau_pgraph_object_class nv04_graph_grclass[] = {
         { 0x0053, false, NULL }, /* surf3d */
         { 0x0054, false, NULL }, /* tex_tri */
         { 0x0055, false, NULL }, /* multitex_tri */
+        { 0x506e, true, nv04_graph_mthds_sw },
         {}
 };
 
diff --git a/drivers/gpu/drm/nouveau/nv10_fb.c b/drivers/gpu/drm/nouveau/nv10_fb.c
index 79e2d104d70a..cc5cda44e501 100644
--- a/drivers/gpu/drm/nouveau/nv10_fb.c
+++ b/drivers/gpu/drm/nouveau/nv10_fb.c
@@ -3,17 +3,37 @@
 #include "nouveau_drv.h"
 #include "nouveau_drm.h"
 
+void
+nv10_fb_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
+                          uint32_t size, uint32_t pitch)
+{
+        struct drm_nouveau_private *dev_priv = dev->dev_private;
+        uint32_t limit = max(1u, addr + size) - 1;
+
+        if (pitch) {
+                if (dev_priv->card_type >= NV_20)
+                        addr |= 1;
+                else
+                        addr |= 1 << 31;
+        }
+
+        nv_wr32(dev, NV10_PFB_TLIMIT(i), limit);
+        nv_wr32(dev, NV10_PFB_TSIZE(i), pitch);
+        nv_wr32(dev, NV10_PFB_TILE(i), addr);
+}
+
 int
 nv10_fb_init(struct drm_device *dev)
 {
-        uint32_t fb_bar_size;
+        struct drm_nouveau_private *dev_priv = dev->dev_private;
+        struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
         int i;
 
-        fb_bar_size = drm_get_resource_len(dev, 0) - 1;
-        for (i = 0; i < NV10_PFB_TILE__SIZE; i++) {
-                nv_wr32(dev, NV10_PFB_TILE(i), 0);
-                nv_wr32(dev, NV10_PFB_TLIMIT(i), fb_bar_size);
-        }
+        pfb->num_tiles = NV10_PFB_TILE__SIZE;
+
+        /* Turn all the tiling regions off. */
+        for (i = 0; i < pfb->num_tiles; i++)
+                pfb->set_region_tiling(dev, i, 0, 0, 0);
 
         return 0;
 }
diff --git a/drivers/gpu/drm/nouveau/nv10_graph.c b/drivers/gpu/drm/nouveau/nv10_graph.c
index 6bf6804bb0ef..fcf2cdd19493 100644
--- a/drivers/gpu/drm/nouveau/nv10_graph.c
+++ b/drivers/gpu/drm/nouveau/nv10_graph.c
@@ -389,49 +389,50 @@ struct graph_state {
         int nv10[ARRAY_SIZE(nv10_graph_ctx_regs)];
         int nv17[ARRAY_SIZE(nv17_graph_ctx_regs)];
         struct pipe_state pipe_state;
+        uint32_t lma_window[4];
 };
 
+#define PIPE_SAVE(dev, state, addr)                                     \
+        do {                                                            \
+                int __i;                                                \
+                nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, addr);           \
+                for (__i = 0; __i < ARRAY_SIZE(state); __i++)           \
+                        state[__i] = nv_rd32(dev, NV10_PGRAPH_PIPE_DATA); \
+        } while (0)
+
+#define PIPE_RESTORE(dev, state, addr)                                  \
+        do {                                                            \
+                int __i;                                                \
+                nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, addr);           \
+                for (__i = 0; __i < ARRAY_SIZE(state); __i++)           \
+                        nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, state[__i]); \
+        } while (0)
+
 static void nv10_graph_save_pipe(struct nouveau_channel *chan)
 {
         struct drm_device *dev = chan->dev;
         struct graph_state *pgraph_ctx = chan->pgraph_ctx;
-        struct pipe_state *fifo_pipe_state = &pgraph_ctx->pipe_state;
-        int i;
-#define PIPE_SAVE(addr) \
-        do { \
-                nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, addr); \
-                for (i = 0; i < ARRAY_SIZE(fifo_pipe_state->pipe_##addr); i++) \
-                        fifo_pipe_state->pipe_##addr[i] = nv_rd32(dev, NV10_PGRAPH_PIPE_DATA); \
-        } while (0)
-
-        PIPE_SAVE(0x4400);
-        PIPE_SAVE(0x0200);
-        PIPE_SAVE(0x6400);
-        PIPE_SAVE(0x6800);
-        PIPE_SAVE(0x6c00);
-        PIPE_SAVE(0x7000);
-        PIPE_SAVE(0x7400);
-        PIPE_SAVE(0x7800);
-        PIPE_SAVE(0x0040);
-        PIPE_SAVE(0x0000);
-
-#undef PIPE_SAVE
+        struct pipe_state *pipe = &pgraph_ctx->pipe_state;
+
+        PIPE_SAVE(dev, pipe->pipe_0x4400, 0x4400);
+        PIPE_SAVE(dev, pipe->pipe_0x0200, 0x0200);
+        PIPE_SAVE(dev, pipe->pipe_0x6400, 0x6400);
+        PIPE_SAVE(dev, pipe->pipe_0x6800, 0x6800);
+        PIPE_SAVE(dev, pipe->pipe_0x6c00, 0x6c00);
+        PIPE_SAVE(dev, pipe->pipe_0x7000, 0x7000);
+        PIPE_SAVE(dev, pipe->pipe_0x7400, 0x7400);
+        PIPE_SAVE(dev, pipe->pipe_0x7800, 0x7800);
+        PIPE_SAVE(dev, pipe->pipe_0x0040, 0x0040);
+        PIPE_SAVE(dev, pipe->pipe_0x0000, 0x0000);
 }
 
 static void nv10_graph_load_pipe(struct nouveau_channel *chan)
 {
         struct drm_device *dev = chan->dev;
         struct graph_state *pgraph_ctx = chan->pgraph_ctx;
-        struct pipe_state *fifo_pipe_state = &pgraph_ctx->pipe_state;
-        int i;
+        struct pipe_state *pipe = &pgraph_ctx->pipe_state;
         uint32_t xfmode0, xfmode1;
-#define PIPE_RESTORE(addr) \
-        do { \
-                nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, addr); \
-                for (i = 0; i < ARRAY_SIZE(fifo_pipe_state->pipe_##addr); i++) \
-                        nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, fifo_pipe_state->pipe_##addr[i]); \
-        } while (0)
-
+        int i;
 
         nouveau_wait_for_idle(dev);
         /* XXX check haiku comments */
@@ -457,24 +458,22 @@ static void nv10_graph_load_pipe(struct nouveau_channel *chan)
         nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x00000008);
 
 
-        PIPE_RESTORE(0x0200);
+        PIPE_RESTORE(dev, pipe->pipe_0x0200, 0x0200);
         nouveau_wait_for_idle(dev);
 
         /* restore XFMODE */
         nv_wr32(dev, NV10_PGRAPH_XFMODE0, xfmode0);
         nv_wr32(dev, NV10_PGRAPH_XFMODE1, xfmode1);
-        PIPE_RESTORE(0x6400);
-        PIPE_RESTORE(0x6800);
-        PIPE_RESTORE(0x6c00);
-        PIPE_RESTORE(0x7000);
-        PIPE_RESTORE(0x7400);
-        PIPE_RESTORE(0x7800);
-        PIPE_RESTORE(0x4400);
-        PIPE_RESTORE(0x0000);
-        PIPE_RESTORE(0x0040);
+        PIPE_RESTORE(dev, pipe->pipe_0x6400, 0x6400);
+        PIPE_RESTORE(dev, pipe->pipe_0x6800, 0x6800);
+        PIPE_RESTORE(dev, pipe->pipe_0x6c00, 0x6c00);
+        PIPE_RESTORE(dev, pipe->pipe_0x7000, 0x7000);
+        PIPE_RESTORE(dev, pipe->pipe_0x7400, 0x7400);
+        PIPE_RESTORE(dev, pipe->pipe_0x7800, 0x7800);
+        PIPE_RESTORE(dev, pipe->pipe_0x4400, 0x4400);
+        PIPE_RESTORE(dev, pipe->pipe_0x0000, 0x0000);
+        PIPE_RESTORE(dev, pipe->pipe_0x0040, 0x0040);
         nouveau_wait_for_idle(dev);
-
-#undef PIPE_RESTORE
 }
 
 static void nv10_graph_create_pipe(struct nouveau_channel *chan)
@@ -808,6 +807,20 @@ void nv10_graph_destroy_context(struct nouveau_channel *chan)
         chan->pgraph_ctx = NULL;
 }
 
+void
+nv10_graph_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
+                             uint32_t size, uint32_t pitch)
+{
+        uint32_t limit = max(1u, addr + size) - 1;
+
+        if (pitch)
+                addr |= 1 << 31;
+
+        nv_wr32(dev, NV10_PGRAPH_TLIMIT(i), limit);
+        nv_wr32(dev, NV10_PGRAPH_TSIZE(i), pitch);
+        nv_wr32(dev, NV10_PGRAPH_TILE(i), addr);
+}
+
 int nv10_graph_init(struct drm_device *dev)
 {
         struct drm_nouveau_private *dev_priv = dev->dev_private;
@@ -832,21 +845,16 @@ int nv10_graph_init(struct drm_device *dev)
                                       (1<<31));
         if (dev_priv->chipset >= 0x17) {
                 nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x1f000000);
+                nv_wr32(dev, 0x400a10, 0x3ff3fb6);
+                nv_wr32(dev, 0x400838, 0x2f8684);
+                nv_wr32(dev, 0x40083c, 0x115f3f);
                 nv_wr32(dev, 0x004006b0, 0x40000020);
         } else
                 nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00000000);
 
-        /* copy tile info from PFB */
-        for (i = 0; i < NV10_PFB_TILE__SIZE; i++) {
-                nv_wr32(dev, NV10_PGRAPH_TILE(i),
-                                        nv_rd32(dev, NV10_PFB_TILE(i)));
-                nv_wr32(dev, NV10_PGRAPH_TLIMIT(i),
-                                        nv_rd32(dev, NV10_PFB_TLIMIT(i)));
-                nv_wr32(dev, NV10_PGRAPH_TSIZE(i),
-                                        nv_rd32(dev, NV10_PFB_TSIZE(i)));
-                nv_wr32(dev, NV10_PGRAPH_TSTATUS(i),
-                                        nv_rd32(dev, NV10_PFB_TSTATUS(i)));
-        }
+        /* Turn all the tiling regions off. */
+        for (i = 0; i < NV10_PFB_TILE__SIZE; i++)
+                nv10_graph_set_region_tiling(dev, i, 0, 0, 0);
 
         nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH1, 0x00000000);
         nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH2, 0x00000000);
@@ -867,6 +875,115 @@ void nv10_graph_takedown(struct drm_device *dev)
 {
 }
 
+static int
+nv17_graph_mthd_lma_window(struct nouveau_channel *chan, int grclass,
+                           int mthd, uint32_t data)
+{
+        struct drm_device *dev = chan->dev;
+        struct graph_state *ctx = chan->pgraph_ctx;
+        struct pipe_state *pipe = &ctx->pipe_state;
+        struct drm_nouveau_private *dev_priv = dev->dev_private;
+        struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
+        uint32_t pipe_0x0040[1], pipe_0x64c0[8], pipe_0x6a80[3], pipe_0x6ab0[3];
+        uint32_t xfmode0, xfmode1;
+        int i;
+
+        ctx->lma_window[(mthd - 0x1638) / 4] = data;
+
+        if (mthd != 0x1644)
+                return 0;
+
+        nouveau_wait_for_idle(dev);
+
+        PIPE_SAVE(dev, pipe_0x0040, 0x0040);
+        PIPE_SAVE(dev, pipe->pipe_0x0200, 0x0200);
+
+        PIPE_RESTORE(dev, ctx->lma_window, 0x6790);
+
+        nouveau_wait_for_idle(dev);
+
+        xfmode0 = nv_rd32(dev, NV10_PGRAPH_XFMODE0);
+        xfmode1 = nv_rd32(dev, NV10_PGRAPH_XFMODE1);
+
+        PIPE_SAVE(dev, pipe->pipe_0x4400, 0x4400);
+        PIPE_SAVE(dev, pipe_0x64c0, 0x64c0);
+        PIPE_SAVE(dev, pipe_0x6ab0, 0x6ab0);
+        PIPE_SAVE(dev, pipe_0x6a80, 0x6a80);
+
+        nouveau_wait_for_idle(dev);
+
+        nv_wr32(dev, NV10_PGRAPH_XFMODE0, 0x10000000);
+        nv_wr32(dev, NV10_PGRAPH_XFMODE1, 0x00000000);
+        nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0);
+        for (i = 0; i < 4; i++)
+                nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x3f800000);
+        for (i = 0; i < 4; i++)
+                nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x00000000);
+
+        nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0);
+        for (i = 0; i < 3; i++)
+                nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x3f800000);
+
+        nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80);
+        for (i = 0; i < 3; i++)
+                nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x00000000);
+
+        nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040);
+        nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x00000008);
+
+        PIPE_RESTORE(dev, pipe->pipe_0x0200, 0x0200);
+
+        nouveau_wait_for_idle(dev);
+
+        PIPE_RESTORE(dev, pipe_0x0040, 0x0040);
+
+        nv_wr32(dev, NV10_PGRAPH_XFMODE0, xfmode0);
+        nv_wr32(dev, NV10_PGRAPH_XFMODE1, xfmode1);
+
+        PIPE_RESTORE(dev, pipe_0x64c0, 0x64c0);
+        PIPE_RESTORE(dev, pipe_0x6ab0, 0x6ab0);
+        PIPE_RESTORE(dev, pipe_0x6a80, 0x6a80);
+        PIPE_RESTORE(dev, pipe->pipe_0x4400, 0x4400);
+
+        nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, 0x000000c0);
+        nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x00000000);
+
+        nouveau_wait_for_idle(dev);
+
+        pgraph->fifo_access(dev, true);
+
+        return 0;
+}
+
+static int
+nv17_graph_mthd_lma_enable(struct nouveau_channel *chan, int grclass,
+                           int mthd, uint32_t data)
+{
+        struct drm_device *dev = chan->dev;
+        struct drm_nouveau_private *dev_priv = dev->dev_private;
+        struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
+
+        nouveau_wait_for_idle(dev);
+
+        nv_wr32(dev, NV10_PGRAPH_DEBUG_4,
+                nv_rd32(dev, NV10_PGRAPH_DEBUG_4) | 0x1 << 8);
+        nv_wr32(dev, 0x004006b0,
+                nv_rd32(dev, 0x004006b0) | 0x8 << 24);
+
+        pgraph->fifo_access(dev, true);
+
+        return 0;
+}
+
+static struct nouveau_pgraph_object_method nv17_graph_celsius_mthds[] = {
+        { 0x1638, nv17_graph_mthd_lma_window },
+        { 0x163c, nv17_graph_mthd_lma_window },
+        { 0x1640, nv17_graph_mthd_lma_window },
+        { 0x1644, nv17_graph_mthd_lma_window },
+        { 0x1658, nv17_graph_mthd_lma_enable },
+        {}
+};
+
 struct nouveau_pgraph_object_class nv10_graph_grclass[] = {
         { 0x0030, false, NULL }, /* null */
         { 0x0039, false, NULL }, /* m2mf */
@@ -887,6 +1004,6 @@ struct nouveau_pgraph_object_class nv10_graph_grclass[] = {
         { 0x0095, false, NULL }, /* multitex_tri */
         { 0x0056, false, NULL }, /* celcius (nv10) */
         { 0x0096, false, NULL }, /* celcius (nv11) */
-        { 0x0099, false, NULL }, /* celcius (nv17) */
+        { 0x0099, false, nv17_graph_celsius_mthds }, /* celcius (nv17) */
         {}
 };
diff --git a/drivers/gpu/drm/nouveau/nv17_tv.c b/drivers/gpu/drm/nouveau/nv17_tv.c
index 46cfd9c60478..58b917c3341b 100644
--- a/drivers/gpu/drm/nouveau/nv17_tv.c
+++ b/drivers/gpu/drm/nouveau/nv17_tv.c
@@ -33,13 +33,103 @@
 #include "nouveau_hw.h"
 #include "nv17_tv.h"
 
-enum drm_connector_status nv17_tv_detect(struct drm_encoder *encoder,
-                                         struct drm_connector *connector,
-                                         uint32_t pin_mask)
+static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder)
 {
+        struct drm_device *dev = encoder->dev;
+        struct drm_nouveau_private *dev_priv = dev->dev_private;
+        uint32_t testval, regoffset = nv04_dac_output_offset(encoder);
+        uint32_t gpio0, gpio1, fp_htotal, fp_hsync_start, fp_hsync_end,
+                fp_control, test_ctrl, dacclk, ctv_14, ctv_1c, ctv_6c;
+        uint32_t sample = 0;
+        int head;
+
+#define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20)
+        testval = RGB_TEST_DATA(0x82, 0xeb, 0x82);
+        if (dev_priv->vbios->tvdactestval)
+                testval = dev_priv->vbios->tvdactestval;
+
+        dacclk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset);
+        head = (dacclk & 0x100) >> 8;
+
+        /* Save the previous state. */
+        gpio1 = nv17_gpio_get(dev, DCB_GPIO_TVDAC1);
+        gpio0 = nv17_gpio_get(dev, DCB_GPIO_TVDAC0);
+        fp_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL);
+        fp_hsync_start = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START);
+        fp_hsync_end = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END);
+        fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
+        test_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
+        ctv_1c = NVReadRAMDAC(dev, head, 0x680c1c);
+        ctv_14 = NVReadRAMDAC(dev, head, 0x680c14);
+        ctv_6c = NVReadRAMDAC(dev, head, 0x680c6c);
+
+        /* Prepare the DAC for load detection.  */
+        nv17_gpio_set(dev, DCB_GPIO_TVDAC1, true);
+        nv17_gpio_set(dev, DCB_GPIO_TVDAC0, true);
+
+        NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, 1343);
+        NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, 1047);
+        NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, 1183);
+        NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL,
+                      NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
+                      NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12 |
+                      NV_PRAMDAC_FP_TG_CONTROL_READ_PROG |
+                      NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS |
+                      NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS);
+
+        NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, 0);
+
+        NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,
+                      (dacclk & ~0xff) | 0x22);
+        msleep(1);
+        NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,
+                      (dacclk & ~0xff) | 0x21);
+
+        NVWriteRAMDAC(dev, head, 0x680c1c, 1 << 20);
+        NVWriteRAMDAC(dev, head, 0x680c14, 4 << 16);
+
+        /* Sample pin 0x4 (usually S-video luma). */
+        NVWriteRAMDAC(dev, head, 0x680c6c, testval >> 10 & 0x3ff);
+        msleep(20);
+        sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
+                & 0x4 << 28;
+
+        /* Sample the remaining pins. */
+        NVWriteRAMDAC(dev, head, 0x680c6c, testval & 0x3ff);
+        msleep(20);
+        sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
+                & 0xa << 28;
+
+        /* Restore the previous state. */
+        NVWriteRAMDAC(dev, head, 0x680c1c, ctv_1c);
+        NVWriteRAMDAC(dev, head, 0x680c14, ctv_14);
+        NVWriteRAMDAC(dev, head, 0x680c6c, ctv_6c);
+        NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, dacclk);
+        NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, test_ctrl);
+        NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, fp_control);
+        NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, fp_hsync_end);
+        NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, fp_hsync_start);
+        NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, fp_htotal);
+        nv17_gpio_set(dev, DCB_GPIO_TVDAC1, gpio1);
+        nv17_gpio_set(dev, DCB_GPIO_TVDAC0, gpio0);
+
+        return sample;
+}
+
+static enum drm_connector_status
+nv17_tv_detect(struct drm_encoder *encoder, struct drm_connector *connector)
+{
+        struct drm_device *dev = encoder->dev;
+        struct drm_nouveau_private *dev_priv = dev->dev_private;
+        struct drm_mode_config *conf = &dev->mode_config;
         struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
+        struct dcb_entry *dcb = tv_enc->base.dcb;
 
-        tv_enc->pin_mask = pin_mask >> 28 & 0xe;
+        if (dev_priv->chipset == 0x42 ||
+            dev_priv->chipset == 0x43)
+                tv_enc->pin_mask = nv42_tv_sample_load(encoder) >> 28 & 0xe;
+        else
+                tv_enc->pin_mask = nv17_dac_sample_load(encoder) >> 28 & 0xe;
 
         switch (tv_enc->pin_mask) {
         case 0x2:
@@ -50,7 +140,7 @@ enum drm_connector_status nv17_tv_detect(struct drm_encoder *encoder,
                 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SVIDEO;
                 break;
         case 0xe:
-                if (nouveau_encoder(encoder)->dcb->tvconf.has_component_output)
+                if (dcb->tvconf.has_component_output)
                         tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Component;
                 else
                         tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SCART;
@@ -61,11 +151,16 @@ enum drm_connector_status nv17_tv_detect(struct drm_encoder *encoder,
         }
 
         drm_connector_property_set_value(connector,
-                        encoder->dev->mode_config.tv_subconnector_property,
-                                                        tv_enc->subconnector);
+                                         conf->tv_subconnector_property,
+                                         tv_enc->subconnector);
 
-        return tv_enc->subconnector ? connector_status_connected :
-                                        connector_status_disconnected;
+        if (tv_enc->subconnector) {
+                NV_INFO(dev, "Load detected on output %c\n",
+                        '@' + ffs(dcb->or));
+                return connector_status_connected;
+        } else {
+                return connector_status_disconnected;
+        }
 }
 
 static const struct {
@@ -219,7 +314,7 @@ static void  nv17_tv_dpms(struct drm_encoder *encoder, int mode)
                 return;
         nouveau_encoder(encoder)->last_dpms = mode;
 
-        NV_TRACE(dev, "Setting dpms mode %d on TV encoder (output %d)\n",
+        NV_INFO(dev, "Setting dpms mode %d on TV encoder (output %d)\n",
                  mode, nouveau_encoder(encoder)->dcb->index);
 
         regs->ptv_200 &= ~1;
@@ -619,7 +714,7 @@ static void nv17_tv_destroy(struct drm_encoder *encoder)
 {
         struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
 
-        NV_DEBUG(encoder->dev, "\n");
+        NV_DEBUG_KMS(encoder->dev, "\n");
 
         drm_encoder_cleanup(encoder);
         kfree(tv_enc);
@@ -633,7 +728,7 @@ static struct drm_encoder_helper_funcs nv17_tv_helper_funcs = {
         .prepare = nv17_tv_prepare,
         .commit = nv17_tv_commit,
         .mode_set = nv17_tv_mode_set,
-        .detect = nv17_dac_detect,
+        .detect = nv17_tv_detect,
 };
 
 static struct drm_encoder_slave_funcs nv17_tv_slave_funcs = {
diff --git a/drivers/gpu/drm/nouveau/nv20_graph.c b/drivers/gpu/drm/nouveau/nv20_graph.c
index 18ba74f19703..d6fc0a82f03d 100644
--- a/drivers/gpu/drm/nouveau/nv20_graph.c
+++ b/drivers/gpu/drm/nouveau/nv20_graph.c
@@ -514,6 +514,27 @@ nv20_graph_rdi(struct drm_device *dev)
         nouveau_wait_for_idle(dev);
 }
 
+void
+nv20_graph_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
+                             uint32_t size, uint32_t pitch)
+{
+        uint32_t limit = max(1u, addr + size) - 1;
+
+        if (pitch)
+                addr |= 1;
+
+        nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), limit);
+        nv_wr32(dev, NV20_PGRAPH_TSIZE(i), pitch);
+        nv_wr32(dev, NV20_PGRAPH_TILE(i), addr);
+
+        nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i);
+        nv_wr32(dev, NV10_PGRAPH_RDI_DATA, limit);
+        nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i);
+        nv_wr32(dev, NV10_PGRAPH_RDI_DATA, pitch);
+        nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i);
+        nv_wr32(dev, NV10_PGRAPH_RDI_DATA, addr);
+}
+
 int
 nv20_graph_init(struct drm_device *dev)
 {
@@ -572,27 +593,10 @@ nv20_graph_init(struct drm_device *dev)
                 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00000030);
         }
 
-        /* copy tile info from PFB */
-        for (i = 0; i < NV10_PFB_TILE__SIZE; i++) {
-                nv_wr32(dev, 0x00400904 + i * 0x10,
-                                        nv_rd32(dev, NV10_PFB_TLIMIT(i)));
-                        /* which is NV40_PGRAPH_TLIMIT0(i) ?? */
-                nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + i * 4);
-                nv_wr32(dev, NV10_PGRAPH_RDI_DATA,
-                                        nv_rd32(dev, NV10_PFB_TLIMIT(i)));
-                nv_wr32(dev, 0x00400908 + i * 0x10,
-                                        nv_rd32(dev, NV10_PFB_TSIZE(i)));
-                        /* which is NV40_PGRAPH_TSIZE0(i) ?? */
-                nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + i * 4);
-                nv_wr32(dev, NV10_PGRAPH_RDI_DATA,
-                                        nv_rd32(dev, NV10_PFB_TSIZE(i)));
-                nv_wr32(dev, 0x00400900 + i * 0x10,
-                                        nv_rd32(dev, NV10_PFB_TILE(i)));
-                        /* which is NV40_PGRAPH_TILE0(i) ?? */
-                nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + i * 4);
-                nv_wr32(dev, NV10_PGRAPH_RDI_DATA,
-                                        nv_rd32(dev, NV10_PFB_TILE(i)));
-        }
+        /* Turn all the tiling regions off. */
+        for (i = 0; i < NV10_PFB_TILE__SIZE; i++)
+                nv20_graph_set_region_tiling(dev, i, 0, 0, 0);
+
         for (i = 0; i < 8; i++) {
                 nv_wr32(dev, 0x400980 + i * 4, nv_rd32(dev, 0x100300 + i * 4));
                 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0090 + i * 4);
@@ -704,18 +708,9 @@ nv30_graph_init(struct drm_device *dev)
 
         nv_wr32(dev, 0x4000c0, 0x00000016);
 
-        /* copy tile info from PFB */
-        for (i = 0; i < NV10_PFB_TILE__SIZE; i++) {
-                nv_wr32(dev, 0x00400904 + i * 0x10,
-                                        nv_rd32(dev, NV10_PFB_TLIMIT(i)));
-                        /* which is NV40_PGRAPH_TLIMIT0(i) ?? */
-                nv_wr32(dev, 0x00400908 + i * 0x10,
-                                        nv_rd32(dev, NV10_PFB_TSIZE(i)));
-                        /* which is NV40_PGRAPH_TSIZE0(i) ?? */
-                nv_wr32(dev, 0x00400900 + i * 0x10,
-                                        nv_rd32(dev, NV10_PFB_TILE(i)));
-                        /* which is NV40_PGRAPH_TILE0(i) ?? */
-        }
+        /* Turn all the tiling regions off. */
+        for (i = 0; i < NV10_PFB_TILE__SIZE; i++)
+                nv20_graph_set_region_tiling(dev, i, 0, 0, 0);
 
         nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
         nv_wr32(dev, NV10_PGRAPH_STATE      , 0xFFFFFFFF);
diff --git a/drivers/gpu/drm/nouveau/nv40_fb.c b/drivers/gpu/drm/nouveau/nv40_fb.c
index ca1d27107a8e..3cd07d8d5bd7 100644
--- a/drivers/gpu/drm/nouveau/nv40_fb.c
+++ b/drivers/gpu/drm/nouveau/nv40_fb.c
@@ -3,12 +3,37 @@
 #include "nouveau_drv.h"
 #include "nouveau_drm.h"
 
+void
+nv40_fb_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
+                          uint32_t size, uint32_t pitch)
+{
+        struct drm_nouveau_private *dev_priv = dev->dev_private;
+        uint32_t limit = max(1u, addr + size) - 1;
+
+        if (pitch)
+                addr |= 1;
+
+        switch (dev_priv->chipset) {
+        case 0x40:
+                nv_wr32(dev, NV10_PFB_TLIMIT(i), limit);
+                nv_wr32(dev, NV10_PFB_TSIZE(i), pitch);
+                nv_wr32(dev, NV10_PFB_TILE(i), addr);
+                break;
+
+        default:
+                nv_wr32(dev, NV40_PFB_TLIMIT(i), limit);
+                nv_wr32(dev, NV40_PFB_TSIZE(i), pitch);
+                nv_wr32(dev, NV40_PFB_TILE(i), addr);
+                break;
+        }
+}
+
 int
 nv40_fb_init(struct drm_device *dev)
 {
         struct drm_nouveau_private *dev_priv = dev->dev_private;
-        uint32_t fb_bar_size, tmp;
-        int num_tiles;
+        struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
+        uint32_t tmp;
         int i;
 
         /* This is strictly a NV4x register (don't know about NV5x). */
@@ -23,35 +48,23 @@ nv40_fb_init(struct drm_device *dev)
         case 0x45:
                 tmp = nv_rd32(dev, NV10_PFB_CLOSE_PAGE2);
                 nv_wr32(dev, NV10_PFB_CLOSE_PAGE2, tmp & ~(1 << 15));
-                num_tiles = NV10_PFB_TILE__SIZE;
+                pfb->num_tiles = NV10_PFB_TILE__SIZE;
                 break;
         case 0x46: /* G72 */
         case 0x47: /* G70 */
         case 0x49: /* G71 */
         case 0x4b: /* G73 */
         case 0x4c: /* C51 (G7X version) */
-                num_tiles = NV40_PFB_TILE__SIZE_1;
+                pfb->num_tiles = NV40_PFB_TILE__SIZE_1;
                 break;
         default:
-                num_tiles = NV40_PFB_TILE__SIZE_0;
+                pfb->num_tiles = NV40_PFB_TILE__SIZE_0;
                 break;
         }
 
-        fb_bar_size = drm_get_resource_len(dev, 0) - 1;
-        switch (dev_priv->chipset) {
-        case 0x40:
-                for (i = 0; i < num_tiles; i++) {
-                        nv_wr32(dev, NV10_PFB_TILE(i), 0);
-                        nv_wr32(dev, NV10_PFB_TLIMIT(i), fb_bar_size);
-                }
-                break;
-        default:
-                for (i = 0; i < num_tiles; i++) {
-                        nv_wr32(dev, NV40_PFB_TILE(i), 0);
-                        nv_wr32(dev, NV40_PFB_TLIMIT(i), fb_bar_size);
-                }
-                break;
-        }
+        /* Turn all the tiling regions off. */
+        for (i = 0; i < pfb->num_tiles; i++)
+                pfb->set_region_tiling(dev, i, 0, 0, 0);
 
         return 0;
 }
diff --git a/drivers/gpu/drm/nouveau/nv40_graph.c b/drivers/gpu/drm/nouveau/nv40_graph.c
index 7e8547cb5833..53e8afe1dcd1 100644
--- a/drivers/gpu/drm/nouveau/nv40_graph.c
+++ b/drivers/gpu/drm/nouveau/nv40_graph.c
@@ -24,36 +24,10 @@
  *
  */
 
-#include <linux/firmware.h>
-
 #include "drmP.h"
 #include "drm.h"
 #include "nouveau_drv.h"
-
-MODULE_FIRMWARE("nouveau/nv40.ctxprog");
-MODULE_FIRMWARE("nouveau/nv40.ctxvals");
-MODULE_FIRMWARE("nouveau/nv41.ctxprog");
-MODULE_FIRMWARE("nouveau/nv41.ctxvals");
-MODULE_FIRMWARE("nouveau/nv42.ctxprog");
-MODULE_FIRMWARE("nouveau/nv42.ctxvals");
-MODULE_FIRMWARE("nouveau/nv43.ctxprog");
-MODULE_FIRMWARE("nouveau/nv43.ctxvals");
-MODULE_FIRMWARE("nouveau/nv44.ctxprog");
-MODULE_FIRMWARE("nouveau/nv44.ctxvals");
-MODULE_FIRMWARE("nouveau/nv46.ctxprog");
-MODULE_FIRMWARE("nouveau/nv46.ctxvals");
-MODULE_FIRMWARE("nouveau/nv47.ctxprog");
-MODULE_FIRMWARE("nouveau/nv47.ctxvals");
-MODULE_FIRMWARE("nouveau/nv49.ctxprog");
-MODULE_FIRMWARE("nouveau/nv49.ctxvals");
-MODULE_FIRMWARE("nouveau/nv4a.ctxprog");
-MODULE_FIRMWARE("nouveau/nv4a.ctxvals");
-MODULE_FIRMWARE("nouveau/nv4b.ctxprog");
-MODULE_FIRMWARE("nouveau/nv4b.ctxvals");
-MODULE_FIRMWARE("nouveau/nv4c.ctxprog");
-MODULE_FIRMWARE("nouveau/nv4c.ctxvals");
-MODULE_FIRMWARE("nouveau/nv4e.ctxprog");
-MODULE_FIRMWARE("nouveau/nv4e.ctxvals");
+#include "nouveau_grctx.h"
 
 struct nouveau_channel *
 nv40_graph_channel(struct drm_device *dev)
@@ -83,27 +57,30 @@ nv40_graph_create_context(struct nouveau_channel *chan)
 {
         struct drm_device *dev = chan->dev;
         struct drm_nouveau_private *dev_priv = dev->dev_private;
-        struct nouveau_gpuobj *ctx;
+        struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
         int ret;
 
-        /* Allocate a 175KiB block of PRAMIN to store the context.  This
-         * is massive overkill for a lot of chipsets, but it should be safe
-         * until we're able to implement this properly (will happen at more
-         * or less the same time we're able to write our own context programs.
-         */
-        ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 175*1024, 16,
-                                          NVOBJ_FLAG_ZERO_ALLOC,
-                                          &chan->ramin_grctx);
+        ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pgraph->grctx_size,
+                                     16, NVOBJ_FLAG_ZERO_ALLOC,
+                                     &chan->ramin_grctx);
         if (ret)
                 return ret;
-        ctx = chan->ramin_grctx->gpuobj;
 
         /* Initialise default context values */
         dev_priv->engine.instmem.prepare_access(dev, true);
-        nv40_grctx_vals_load(dev, ctx);
-        nv_wo32(dev, ctx, 0, ctx->im_pramin->start);
-        dev_priv->engine.instmem.finish_access(dev);
+        if (!pgraph->ctxprog) {
+                struct nouveau_grctx ctx = {};
 
+                ctx.dev = chan->dev;
+                ctx.mode = NOUVEAU_GRCTX_VALS;
+                ctx.data = chan->ramin_grctx->gpuobj;
+                nv40_grctx_init(&ctx);
+        } else {
+                nouveau_grctx_vals_load(dev, chan->ramin_grctx->gpuobj);
+        }
+        nv_wo32(dev, chan->ramin_grctx->gpuobj, 0,
+                     chan->ramin_grctx->gpuobj->im_pramin->start);
+        dev_priv->engine.instmem.finish_access(dev);
         return 0;
 }
 
@@ -204,137 +181,46 @@ nv40_graph_unload_context(struct drm_device *dev)
         return ret;
 }
 
-struct nouveau_ctxprog {
-        uint32_t signature;
-        uint8_t  version;
-        uint16_t length;
-        uint32_t data[];
-} __attribute__ ((packed));
-
-struct nouveau_ctxvals {
-        uint32_t signature;
-        uint8_t  version;
-        uint32_t length;
-        struct {
-                uint32_t offset;
-                uint32_t value;
-        } data[];
-} __attribute__ ((packed));
-
-int
-nv40_grctx_init(struct drm_device *dev)
-{
-        struct drm_nouveau_private *dev_priv = dev->dev_private;
-        struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
-        const int chipset = dev_priv->chipset;
-        const struct firmware *fw;
-        const struct nouveau_ctxprog *cp;
-        const struct nouveau_ctxvals *cv;
-        char name[32];
-        int ret, i;
-
-        pgraph->accel_blocked = true;
-
-        if (!pgraph->ctxprog) {
-                sprintf(name, "nouveau/nv%02x.ctxprog", chipset);
-                ret = request_firmware(&fw, name, &dev->pdev->dev);
-                if (ret) {
-                        NV_ERROR(dev, "No ctxprog for NV%02x\n", chipset);
-                        return ret;
-                }
-
-                pgraph->ctxprog = kmalloc(fw->size, GFP_KERNEL);
-                if (!pgraph->ctxprog) {
-                        NV_ERROR(dev, "OOM copying ctxprog\n");
-                        release_firmware(fw);
-                        return -ENOMEM;
-                }
-                memcpy(pgraph->ctxprog, fw->data, fw->size);
-
-                cp = pgraph->ctxprog;
-                if (le32_to_cpu(cp->signature) != 0x5043564e ||
-                    cp->version != 0 ||
-                    le16_to_cpu(cp->length) != ((fw->size - 7) / 4)) {
-                        NV_ERROR(dev, "ctxprog invalid\n");
-                        release_firmware(fw);
-                        nv40_grctx_fini(dev);
-                        return -EINVAL;
-                }
-                release_firmware(fw);
-        }
-
-        if (!pgraph->ctxvals) {
-                sprintf(name, "nouveau/nv%02x.ctxvals", chipset);
-                ret = request_firmware(&fw, name, &dev->pdev->dev);
-                if (ret) {
-                        NV_ERROR(dev, "No ctxvals for NV%02x\n", chipset);
-                        nv40_grctx_fini(dev);
-                        return ret;
-                }
-
-                pgraph->ctxvals = kmalloc(fw->size, GFP_KERNEL);
-                if (!pgraph->ctxprog) {
-                        NV_ERROR(dev, "OOM copying ctxprog\n");
-                        release_firmware(fw);
-                        nv40_grctx_fini(dev);
-                        return -ENOMEM;
-                }
-                memcpy(pgraph->ctxvals, fw->data, fw->size);
-
-                cv = (void *)pgraph->ctxvals;
-                if (le32_to_cpu(cv->signature) != 0x5643564e ||
-                    cv->version != 0 ||
-                    le32_to_cpu(cv->length) != ((fw->size - 9) / 8)) {
-                        NV_ERROR(dev, "ctxvals invalid\n");
-                        release_firmware(fw);
-                        nv40_grctx_fini(dev);
-                        return -EINVAL;
-                }
-                release_firmware(fw);
-        }
-
-        cp = pgraph->ctxprog;
-
-        nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
-        for (i = 0; i < le16_to_cpu(cp->length); i++)
-                nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA,
-                        le32_to_cpu(cp->data[i]));
-
-        pgraph->accel_blocked = false;
-        return 0;
-}
-
 void
-nv40_grctx_fini(struct drm_device *dev)
+nv40_graph_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
+                             uint32_t size, uint32_t pitch)
 {
         struct drm_nouveau_private *dev_priv = dev->dev_private;
-        struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
-
-        if (pgraph->ctxprog) {
-                kfree(pgraph->ctxprog);
-                pgraph->ctxprog = NULL;
-        }
+        uint32_t limit = max(1u, addr + size) - 1;
 
-        if (pgraph->ctxvals) {
-                kfree(pgraph->ctxprog);
-                pgraph->ctxvals = NULL;
-        }
-}
+        if (pitch)
+                addr |= 1;
 
-void
-nv40_grctx_vals_load(struct drm_device *dev, struct nouveau_gpuobj *ctx)
-{
-        struct drm_nouveau_private *dev_priv = dev->dev_private;
-        struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
-        struct nouveau_ctxvals *cv = pgraph->ctxvals;
-        int i;
+        switch (dev_priv->chipset) {
+        case 0x44:
+        case 0x4a:
+        case 0x4e:
+                nv_wr32(dev, NV20_PGRAPH_TSIZE(i), pitch);
+                nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), limit);
+                nv_wr32(dev, NV20_PGRAPH_TILE(i), addr);
+                break;
 
-        if (!cv)
-                return;
+        case 0x46:
+        case 0x47:
+        case 0x49:
+        case 0x4b:
+                nv_wr32(dev, NV47_PGRAPH_TSIZE(i), pitch);
+                nv_wr32(dev, NV47_PGRAPH_TLIMIT(i), limit);
+                nv_wr32(dev, NV47_PGRAPH_TILE(i), addr);
+                nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), pitch);
+                nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), limit);
+                nv_wr32(dev, NV40_PGRAPH_TILE1(i), addr);
+                break;
 
-        for (i = 0; i < le32_to_cpu(cv->length); i++)
-                nv_wo32(dev, ctx, le32_to_cpu(cv->data[i].offset),
-                        le32_to_cpu(cv->data[i].value));
+        default:
+                nv_wr32(dev, NV20_PGRAPH_TSIZE(i), pitch);
+                nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), limit);
+                nv_wr32(dev, NV20_PGRAPH_TILE(i), addr);
+                nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), pitch);
+                nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), limit);
+                nv_wr32(dev, NV40_PGRAPH_TILE1(i), addr);
+                break;
+        }
 }
 
 /*
@@ -351,7 +237,8 @@ nv40_graph_init(struct drm_device *dev)
 {
         struct drm_nouveau_private *dev_priv =
                 (struct drm_nouveau_private *)dev->dev_private;
-        uint32_t vramsz, tmp;
+        struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
+        uint32_t vramsz;
         int i, j;
 
         nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
@@ -359,7 +246,26 @@ nv40_graph_init(struct drm_device *dev)
         nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
                          NV_PMC_ENABLE_PGRAPH);
 
-        nv40_grctx_init(dev);
+        if (nouveau_ctxfw) {
+                nouveau_grctx_prog_load(dev);
+                dev_priv->engine.graph.grctx_size = 175 * 1024;
+        }
+
+        if (!dev_priv->engine.graph.ctxprog) {
+                struct nouveau_grctx ctx = {};
+                uint32_t cp[256];
+
+                ctx.dev = dev;
+                ctx.mode = NOUVEAU_GRCTX_PROG;
+                ctx.data = cp;
+                ctx.ctxprog_max = 256;
+                nv40_grctx_init(&ctx);
+                dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;
+
+                nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
+                for (i = 0; i < ctx.ctxprog_len; i++)
+                        nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
+        }
 
         /* No context present currently */
         nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
@@ -429,74 +335,9 @@ nv40_graph_init(struct drm_device *dev)
         nv_wr32(dev, 0x400b38, 0x2ffff800);
         nv_wr32(dev, 0x400b3c, 0x00006000);
 
-        /* copy tile info from PFB */
-        switch (dev_priv->chipset) {
-        case 0x40: /* vanilla NV40 */
-                for (i = 0; i < NV10_PFB_TILE__SIZE; i++) {
-                        tmp = nv_rd32(dev, NV10_PFB_TILE(i));
-                        nv_wr32(dev, NV40_PGRAPH_TILE0(i), tmp);
-                        nv_wr32(dev, NV40_PGRAPH_TILE1(i), tmp);
-                        tmp = nv_rd32(dev, NV10_PFB_TLIMIT(i));
-                        nv_wr32(dev, NV40_PGRAPH_TLIMIT0(i), tmp);
-                        nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tmp);
-                        tmp = nv_rd32(dev, NV10_PFB_TSIZE(i));
-                        nv_wr32(dev, NV40_PGRAPH_TSIZE0(i), tmp);
-                        nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tmp);
-                        tmp = nv_rd32(dev, NV10_PFB_TSTATUS(i));
-                        nv_wr32(dev, NV40_PGRAPH_TSTATUS0(i), tmp);
-                        nv_wr32(dev, NV40_PGRAPH_TSTATUS1(i), tmp);
-                }
-                break;
-        case 0x44:
-        case 0x4a:
-        case 0x4e: /* NV44-based cores don't have 0x406900? */
-                for (i = 0; i < NV40_PFB_TILE__SIZE_0; i++) {
-                        tmp = nv_rd32(dev, NV40_PFB_TILE(i));
-                        nv_wr32(dev, NV40_PGRAPH_TILE0(i), tmp);
-                        tmp = nv_rd32(dev, NV40_PFB_TLIMIT(i));
-                        nv_wr32(dev, NV40_PGRAPH_TLIMIT0(i), tmp);
-                        tmp = nv_rd32(dev, NV40_PFB_TSIZE(i));
-                        nv_wr32(dev, NV40_PGRAPH_TSIZE0(i), tmp);
-                        tmp = nv_rd32(dev, NV40_PFB_TSTATUS(i));
-                        nv_wr32(dev, NV40_PGRAPH_TSTATUS0(i), tmp);
-                }
-                break;
-        case 0x46:
-        case 0x47:
-        case 0x49:
-        case 0x4b: /* G7X-based cores */
-                for (i = 0; i < NV40_PFB_TILE__SIZE_1; i++) {
-                        tmp = nv_rd32(dev, NV40_PFB_TILE(i));
-                        nv_wr32(dev, NV47_PGRAPH_TILE0(i), tmp);
-                        nv_wr32(dev, NV40_PGRAPH_TILE1(i), tmp);
-                        tmp = nv_rd32(dev, NV40_PFB_TLIMIT(i));
-                        nv_wr32(dev, NV47_PGRAPH_TLIMIT0(i), tmp);
-                        nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tmp);
-                        tmp = nv_rd32(dev, NV40_PFB_TSIZE(i));
-                        nv_wr32(dev, NV47_PGRAPH_TSIZE0(i), tmp);
-                        nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tmp);
-                        tmp = nv_rd32(dev, NV40_PFB_TSTATUS(i));
-                        nv_wr32(dev, NV47_PGRAPH_TSTATUS0(i), tmp);
-                        nv_wr32(dev, NV40_PGRAPH_TSTATUS1(i), tmp);
-                }
-                break;
-        default: /* everything else */
-                for (i = 0; i < NV40_PFB_TILE__SIZE_0; i++) {
-                        tmp = nv_rd32(dev, NV40_PFB_TILE(i));
-                        nv_wr32(dev, NV40_PGRAPH_TILE0(i), tmp);
-                        nv_wr32(dev, NV40_PGRAPH_TILE1(i), tmp);
-                        tmp = nv_rd32(dev, NV40_PFB_TLIMIT(i));
-                        nv_wr32(dev, NV40_PGRAPH_TLIMIT0(i), tmp);
-                        nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tmp);
-                        tmp = nv_rd32(dev, NV40_PFB_TSIZE(i));
-                        nv_wr32(dev, NV40_PGRAPH_TSIZE0(i), tmp);
-                        nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tmp);
-                        tmp = nv_rd32(dev, NV40_PFB_TSTATUS(i));
-                        nv_wr32(dev, NV40_PGRAPH_TSTATUS0(i), tmp);
-                        nv_wr32(dev, NV40_PGRAPH_TSTATUS1(i), tmp);
-                }
-                break;
-        }
+        /* Turn all the tiling regions off. */
+        for (i = 0; i < pfb->num_tiles; i++)
+                nv40_graph_set_region_tiling(dev, i, 0, 0, 0);
 
         /* begin RAM config */
         vramsz = drm_get_resource_len(dev, 0) - 1;
@@ -539,6 +380,7 @@ nv40_graph_init(struct drm_device *dev)
 
 void nv40_graph_takedown(struct drm_device *dev)
 {
+        nouveau_grctx_fini(dev);
 }
 
 struct nouveau_pgraph_object_class nv40_graph_grclass[] = {
diff --git a/drivers/gpu/drm/nouveau/nv40_grctx.c b/drivers/gpu/drm/nouveau/nv40_grctx.c
new file mode 100644
index 000000000000..11b11c31f543
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv40_grctx.c
@@ -0,0 +1,678 @@
+/*
+ * Copyright 2009 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+/* NVIDIA context programs handle a number of other conditions which are
+ * not implemented in our versions.  It's not clear why NVIDIA context
+ * programs have this code, nor whether it's strictly necessary for
+ * correct operation.  We'll implement additional handling if/when we
+ * discover it's necessary.
+ *
+ * - On context save, NVIDIA set 0x400314 bit 0 to 1 if the "3D state"
+ *   flag is set, this gets saved into the context.
+ * - On context save, the context program for all cards load nsource
+ *   into a flag register and check for ILLEGAL_MTHD.  If it's set,
+ *   opcode 0x60000d is called before resuming normal operation.
+ * - Some context programs check more conditions than the above.  NV44
+ *   checks: ((nsource & 0x0857) || (0x400718 & 0x0100) || (intr & 0x0001))
+ *   and calls 0x60000d before resuming normal operation.
+ * - At the very beginning of NVIDIA's context programs, flag 9 is checked
+ *   and if true 0x800001 is called with count=0, pos=0, the flag is cleared
+ *   and then the ctxprog is aborted.  It looks like a complicated NOP,
+ *   its purpose is unknown.
+ * - In the section of code that loads the per-vs state, NVIDIA check
+ *   flag 10.  If it's set, they only transfer the small 0x300 byte block
+ *   of state + the state for a single vs as opposed to the state for
+ *   all vs units.  It doesn't seem likely that it'll occur in normal
+ *   operation, especially seeing as it appears NVIDIA may have screwed
+ *   up the ctxprogs for some cards and have an invalid instruction
+ *   rather than a cp_lsr(ctx, dwords_for_1_vs_unit) instruction.
+ * - There's a number of places where context offset 0 (where we place
+ *   the PRAMIN offset of the context) is loaded into either 0x408000,
+ *   0x408004 or 0x408008.  Not sure what's up there either.
+ * - The ctxprogs for some cards save 0x400a00 again during the cleanup
+ *   path for auto-loadctx.
+ */
+
+#define CP_FLAG_CLEAR                 0
+#define CP_FLAG_SET                   1
+#define CP_FLAG_SWAP_DIRECTION        ((0 * 32) + 0)
+#define CP_FLAG_SWAP_DIRECTION_LOAD   0
+#define CP_FLAG_SWAP_DIRECTION_SAVE   1
+#define CP_FLAG_USER_SAVE             ((0 * 32) + 5)
+#define CP_FLAG_USER_SAVE_NOT_PENDING 0
+#define CP_FLAG_USER_SAVE_PENDING     1
+#define CP_FLAG_USER_LOAD             ((0 * 32) + 6)
+#define CP_FLAG_USER_LOAD_NOT_PENDING 0
+#define CP_FLAG_USER_LOAD_PENDING     1
+#define CP_FLAG_STATUS                ((3 * 32) + 0)
+#define CP_FLAG_STATUS_IDLE           0
+#define CP_FLAG_STATUS_BUSY           1
+#define CP_FLAG_AUTO_SAVE             ((3 * 32) + 4)
+#define CP_FLAG_AUTO_SAVE_NOT_PENDING 0
+#define CP_FLAG_AUTO_SAVE_PENDING     1
+#define CP_FLAG_AUTO_LOAD             ((3 * 32) + 5)
+#define CP_FLAG_AUTO_LOAD_NOT_PENDING 0
+#define CP_FLAG_AUTO_LOAD_PENDING     1
+#define CP_FLAG_UNK54                 ((3 * 32) + 6)
+#define CP_FLAG_UNK54_CLEAR           0
+#define CP_FLAG_UNK54_SET             1
+#define CP_FLAG_ALWAYS                ((3 * 32) + 8)
+#define CP_FLAG_ALWAYS_FALSE          0
+#define CP_FLAG_ALWAYS_TRUE           1
+#define CP_FLAG_UNK57                 ((3 * 32) + 9)
+#define CP_FLAG_UNK57_CLEAR           0
+#define CP_FLAG_UNK57_SET             1
+
+#define CP_CTX                   0x00100000
+#define CP_CTX_COUNT             0x000fc000
+#define CP_CTX_COUNT_SHIFT               14
+#define CP_CTX_REG               0x00003fff
+#define CP_LOAD_SR               0x00200000
+#define CP_LOAD_SR_VALUE         0x000fffff
+#define CP_BRA                   0x00400000
+#define CP_BRA_IP                0x0000ff00
+#define CP_BRA_IP_SHIFT                   8
+#define CP_BRA_IF_CLEAR          0x00000080
+#define CP_BRA_FLAG              0x0000007f
+#define CP_WAIT                  0x00500000
+#define CP_WAIT_SET              0x00000080
+#define CP_WAIT_FLAG             0x0000007f
+#define CP_SET                   0x00700000
+#define CP_SET_1                 0x00000080
+#define CP_SET_FLAG              0x0000007f
+#define CP_NEXT_TO_SWAP          0x00600007
+#define CP_NEXT_TO_CURRENT       0x00600009
+#define CP_SET_CONTEXT_POINTER   0x0060000a
+#define CP_END                   0x0060000e
+#define CP_LOAD_MAGIC_UNK01      0x00800001 /* unknown */
+#define CP_LOAD_MAGIC_NV44TCL    0x00800029 /* per-vs state (0x4497) */
+#define CP_LOAD_MAGIC_NV40TCL    0x00800041 /* per-vs state (0x4097) */
+
+#include "drmP.h"
+#include "nouveau_drv.h"
+#include "nouveau_grctx.h"
+
+/* TODO:
+ *  - get vs count from 0x1540
+ *  - document unimplemented bits compared to nvidia
+ *    - nsource handling
+ *    - R0 & 0x0200 handling
+ *    - single-vs handling
+ *    - 400314 bit 0
+ */
+
+static int
+nv40_graph_4097(struct drm_device *dev)
+{
+        struct drm_nouveau_private *dev_priv = dev->dev_private;
+
+        if ((dev_priv->chipset & 0xf0) == 0x60)
+                return 0;
+
+        return !!(0x0baf & (1 << dev_priv->chipset));
+}
+
+static int
+nv40_graph_vs_count(struct drm_device *dev)
+{
+        struct drm_nouveau_private *dev_priv = dev->dev_private;
+
+        switch (dev_priv->chipset) {
+        case 0x47:
+        case 0x49:
+        case 0x4b:
+                return 8;
+        case 0x40:
+                return 6;
+        case 0x41:
+        case 0x42:
+                return 5;
+        case 0x43:
+        case 0x44:
+        case 0x46:
+        case 0x4a:
+                return 3;
+        case 0x4c:
+        case 0x4e:
+        case 0x67:
+        default:
+                return 1;
+        }
+}
+
+
+enum cp_label {
+        cp_check_load = 1,
+        cp_setup_auto_load,
+        cp_setup_load,
+        cp_setup_save,
+        cp_swap_state,
+        cp_swap_state3d_3_is_save,
+        cp_prepare_exit,
+        cp_exit,
+};
+
+static void
+nv40_graph_construct_general(struct nouveau_grctx *ctx)
+{
+        struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
+        int i;
+
+        cp_ctx(ctx, 0x4000a4, 1);
+        gr_def(ctx, 0x4000a4, 0x00000008);
+        cp_ctx(ctx, 0x400144, 58);
+        gr_def(ctx, 0x400144, 0x00000001);
+        cp_ctx(ctx, 0x400314, 1);
+        gr_def(ctx, 0x400314, 0x00000000);
+        cp_ctx(ctx, 0x400400, 10);
+        cp_ctx(ctx, 0x400480, 10);
+        cp_ctx(ctx, 0x400500, 19);
+        gr_def(ctx, 0x400514, 0x00040000);
+        gr_def(ctx, 0x400524, 0x55555555);
+        gr_def(ctx, 0x400528, 0x55555555);
+        gr_def(ctx, 0x40052c, 0x55555555);
+        gr_def(ctx, 0x400530, 0x55555555);
+        cp_ctx(ctx, 0x400560, 6);
+        gr_def(ctx, 0x400568, 0x0000ffff);
+        gr_def(ctx, 0x40056c, 0x0000ffff);
+        cp_ctx(ctx, 0x40057c, 5);
+        cp_ctx(ctx, 0x400710, 3);
+        gr_def(ctx, 0x400710, 0x20010001);
+        gr_def(ctx, 0x400714, 0x0f73ef00);
+        cp_ctx(ctx, 0x400724, 1);
+        gr_def(ctx, 0x400724, 0x02008821);
+        cp_ctx(ctx, 0x400770, 3);
+        if (dev_priv->chipset == 0x40) {
+                cp_ctx(ctx, 0x400814, 4);
+                cp_ctx(ctx, 0x400828, 5);
+                cp_ctx(ctx, 0x400840, 5);
+                gr_def(ctx, 0x400850, 0x00000040);
+                cp_ctx(ctx, 0x400858, 4);
+                gr_def(ctx, 0x400858, 0x00000040);
+                gr_def(ctx, 0x40085c, 0x00000040);
+                gr_def(ctx, 0x400864, 0x80000000);
+                cp_ctx(ctx, 0x40086c, 9);
+                gr_def(ctx, 0x40086c, 0x80000000);
+                gr_def(ctx, 0x400870, 0x80000000);
+                gr_def(ctx, 0x400874, 0x80000000);
+                gr_def(ctx, 0x400878, 0x80000000);
+                gr_def(ctx, 0x400888, 0x00000040);
+                gr_def(ctx, 0x40088c, 0x80000000);
+                cp_ctx(ctx, 0x4009c0, 8);
+                gr_def(ctx, 0x4009cc, 0x80000000);
+                gr_def(ctx, 0x4009dc, 0x80000000);
+        } else {
+                cp_ctx(ctx, 0x400840, 20);
+                if (!nv40_graph_4097(ctx->dev)) {
+                        for (i = 0; i < 8; i++)
+                                gr_def(ctx, 0x400860 + (i * 4), 0x00000001);
+                }
+                gr_def(ctx, 0x400880, 0x00000040);
+                gr_def(ctx, 0x400884, 0x00000040);
+                gr_def(ctx, 0x400888, 0x00000040);
+                cp_ctx(ctx, 0x400894, 11);
+                gr_def(ctx, 0x400894, 0x00000040);
+                if (nv40_graph_4097(ctx->dev)) {
+                        for (i = 0; i < 8; i++)
+                                gr_def(ctx, 0x4008a0 + (i * 4), 0x80000000);
+                }
+                cp_ctx(ctx, 0x4008e0, 2);
+                cp_ctx(ctx, 0x4008f8, 2);
+                if (dev_priv->chipset == 0x4c ||
+                    (dev_priv->chipset & 0xf0) == 0x60)
+                        cp_ctx(ctx, 0x4009f8, 1);
+        }
+        cp_ctx(ctx, 0x400a00, 73);
+        gr_def(ctx, 0x400b0c, 0x0b0b0b0c);
+        cp_ctx(ctx, 0x401000, 4);
+        cp_ctx(ctx, 0x405004, 1);
+        switch (dev_priv->chipset) {
+        case 0x47:
+        case 0x49:
+        case 0x4b:
+                cp_ctx(ctx, 0x403448, 1);
+                gr_def(ctx, 0x403448, 0x00001010);
+                break;
+        default:
+                cp_ctx(ctx, 0x403440, 1);
+                switch (dev_priv->chipset) {
+                case 0x40:
+                        gr_def(ctx, 0x403440, 0x00000010);
+                        break;
+                case 0x44:
+                case 0x46:
+                case 0x4a:
+                        gr_def(ctx, 0x403440, 0x00003010);
+                        break;
+                case 0x41:
+                case 0x42:
+                case 0x43:
+                case 0x4c:
+                case 0x4e:
+                case 0x67:
+                default:
+                        gr_def(ctx, 0x403440, 0x00001010);
+                        break;
+                }
+                break;
+        }
+}
+
+static void
+nv40_graph_construct_state3d(struct nouveau_grctx *ctx)
+{
+        struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
+        int i;
+
+        if (dev_priv->chipset == 0x40) {
+                cp_ctx(ctx, 0x401880, 51);
+                gr_def(ctx, 0x401940, 0x00000100);
+        } else
+        if (dev_priv->chipset == 0x46 || dev_priv->chipset == 0x47 ||
+            dev_priv->chipset == 0x49 || dev_priv->chipset == 0x4b) {
+                cp_ctx(ctx, 0x401880, 32);
+                for (i = 0; i < 16; i++)
+                        gr_def(ctx, 0x401880 + (i * 4), 0x00000111);
+                if (dev_priv->chipset == 0x46)
+                        cp_ctx(ctx, 0x401900, 16);
+                cp_ctx(ctx, 0x401940, 3);
+        }
+        cp_ctx(ctx, 0x40194c, 18);
+        gr_def(ctx, 0x401954, 0x00000111);
+        gr_def(ctx, 0x401958, 0x00080060);
+        gr_def(ctx, 0x401974, 0x00000080);
+        gr_def(ctx, 0x401978, 0xffff0000);
+        gr_def(ctx, 0x40197c, 0x00000001);
+        gr_def(ctx, 0x401990, 0x46400000);
+        if (dev_priv->chipset == 0x40) {
+                cp_ctx(ctx, 0x4019a0, 2);
+                cp_ctx(ctx, 0x4019ac, 5);
+        } else {
+                cp_ctx(ctx, 0x4019a0, 1);
+                cp_ctx(ctx, 0x4019b4, 3);
+        }
+        gr_def(ctx, 0x4019bc, 0xffff0000);
+        switch (dev_priv->chipset) {
+        case 0x46:
+        case 0x47:
+        case 0x49:
+        case 0x4b:
+                cp_ctx(ctx, 0x4019c0, 18);
+                for (i = 0; i < 16; i++)
+                        gr_def(ctx, 0x4019c0 + (i * 4), 0x88888888);
+                break;
+        }
+        cp_ctx(ctx, 0x401a08, 8);
+        gr_def(ctx, 0x401a10, 0x0fff0000);
+        gr_def(ctx, 0x401a14, 0x0fff0000);
+        gr_def(ctx, 0x401a1c, 0x00011100);
+        cp_ctx(ctx, 0x401a2c, 4);
+        cp_ctx(ctx, 0x401a44, 26);
+        for (i = 0; i < 16; i++)
+                gr_def(ctx, 0x401a44 + (i * 4), 0x07ff0000);
+        gr_def(ctx, 0x401a8c, 0x4b7fffff);
+        if (dev_priv->chipset == 0x40) {
+                cp_ctx(ctx, 0x401ab8, 3);
+        } else {
+                cp_ctx(ctx, 0x401ab8, 1);
+                cp_ctx(ctx, 0x401ac0, 1);
+        }
+        cp_ctx(ctx, 0x401ad0, 8);
+        gr_def(ctx, 0x401ad0, 0x30201000);
+        gr_def(ctx, 0x401ad4, 0x70605040);
+        gr_def(ctx, 0x401ad8, 0xb8a89888);
+        gr_def(ctx, 0x401adc, 0xf8e8d8c8);
+        cp_ctx(ctx, 0x401b10, dev_priv->chipset == 0x40 ? 2 : 1);
+        gr_def(ctx, 0x401b10, 0x40100000);
+        cp_ctx(ctx, 0x401b18, dev_priv->chipset == 0x40 ? 6 : 5);
+        gr_def(ctx, 0x401b28, dev_priv->chipset == 0x40 ?
+                              0x00000004 : 0x00000000);
+        cp_ctx(ctx, 0x401b30, 25);
+        gr_def(ctx, 0x401b34, 0x0000ffff);
+        gr_def(ctx, 0x401b68, 0x435185d6);
+        gr_def(ctx, 0x401b6c, 0x2155b699);
+        gr_def(ctx, 0x401b70, 0xfedcba98);
+        gr_def(ctx, 0x401b74, 0x00000098);
+        gr_def(ctx, 0x401b84, 0xffffffff);
+        gr_def(ctx, 0x401b88, 0x00ff7000);
+        gr_def(ctx, 0x401b8c, 0x0000ffff);
+        if (dev_priv->chipset != 0x44 && dev_priv->chipset != 0x4a &&
+            dev_priv->chipset != 0x4e)
+                cp_ctx(ctx, 0x401b94, 1);
+        cp_ctx(ctx, 0x401b98, 8);
+        gr_def(ctx, 0x401b9c, 0x00ff0000);
+        cp_ctx(ctx, 0x401bc0, 9);
+        gr_def(ctx, 0x401be0, 0x00ffff00);
+        cp_ctx(ctx, 0x401c00, 192);
+        for (i = 0; i < 16; i++) { /* fragment texture units */
+                gr_def(ctx, 0x401c40 + (i * 4), 0x00018488);
+                gr_def(ctx, 0x401c80 + (i * 4), 0x00028202);
+                gr_def(ctx, 0x401d00 + (i * 4), 0x0000aae4);
+                gr_def(ctx, 0x401d40 + (i * 4), 0x01012000);
+                gr_def(ctx, 0x401d80 + (i * 4), 0x00080008);
+                gr_def(ctx, 0x401e00 + (i * 4), 0x00100008);
+        }
+        for (i = 0; i < 4; i++) { /* vertex texture units */
+                gr_def(ctx, 0x401e90 + (i * 4), 0x0001bc80);
+                gr_def(ctx, 0x401ea0 + (i * 4), 0x00000202);
+                gr_def(ctx, 0x401ec0 + (i * 4), 0x00000008);
+                gr_def(ctx, 0x401ee0 + (i * 4), 0x00080008);
+        }
+        cp_ctx(ctx, 0x400f5c, 3);
+        gr_def(ctx, 0x400f5c, 0x00000002);
+        cp_ctx(ctx, 0x400f84, 1);
+}
+
+static void
+nv40_graph_construct_state3d_2(struct nouveau_grctx *ctx)
+{
+        struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
+        int i;
+
+        cp_ctx(ctx, 0x402000, 1);
+        cp_ctx(ctx, 0x402404, dev_priv->chipset == 0x40 ? 1 : 2);
+        switch (dev_priv->chipset) {
+        case 0x40:
+                gr_def(ctx, 0x402404, 0x00000001);
+                break;
+        case 0x4c:
+        case 0x4e:
+        case 0x67:
+                gr_def(ctx, 0x402404, 0x00000020);
+                break;
+        case 0x46:
+        case 0x49:
+        case 0x4b:
+                gr_def(ctx, 0x402404, 0x00000421);
+                break;
+        default:
+                gr_def(ctx, 0x402404, 0x00000021);
+        }
+        if (dev_priv->chipset != 0x40)
+                gr_def(ctx, 0x402408, 0x030c30c3);
+        switch (dev_priv->chipset) {
+        case 0x44:
+        case 0x46:
+        case 0x4a:
+        case 0x4c:
+        case 0x4e:
+        case 0x67:
+                cp_ctx(ctx, 0x402440, 1);
+                gr_def(ctx, 0x402440, 0x00011001);
+                break;
+        default:
+                break;
+        }
+        cp_ctx(ctx, 0x402480, dev_priv->chipset == 0x40 ? 8 : 9);
+        gr_def(ctx, 0x402488, 0x3e020200);
+        gr_def(ctx, 0x40248c, 0x00ffffff);
+        switch (dev_priv->chipset) {
+        case 0x40:
+                gr_def(ctx, 0x402490, 0x60103f00);
+                break;
+        case 0x47:
+                gr_def(ctx, 0x402490, 0x40103f00);
+                break;
+        case 0x41:
+        case 0x42:
+        case 0x49:
+        case 0x4b:
+                gr_def(ctx, 0x402490, 0x20103f00);
+                break;
+        default:
+                gr_def(ctx, 0x402490, 0x0c103f00);
+                break;
+        }
+        gr_def(ctx, 0x40249c, dev_priv->chipset <= 0x43 ?
+                              0x00020000 : 0x00040000);
+        cp_ctx(ctx, 0x402500, 31);
+        gr_def(ctx, 0x402530, 0x00008100);
+        if (dev_priv->chipset == 0x40)
+                cp_ctx(ctx, 0x40257c, 6);
+        cp_ctx(ctx, 0x402594, 16);
+        cp_ctx(ctx, 0x402800, 17);
+        gr_def(ctx, 0x402800, 0x00000001);
+        switch (dev_priv->chipset) {
+        case 0x47:
+        case 0x49:
+        case 0x4b:
+                cp_ctx(ctx, 0x402864, 1);
+                gr_def(ctx, 0x402864, 0x00001001);
+                cp_ctx(ctx, 0x402870, 3);
+                gr_def(ctx, 0x402878, 0x00000003);
+                if (dev_priv->chipset != 0x47) { /* belong at end!! */
+                        cp_ctx(ctx, 0x402900, 1);
+                        cp_ctx(ctx, 0x402940, 1);
+                        cp_ctx(ctx, 0x402980, 1);
+                        cp_ctx(ctx, 0x4029c0, 1);
+                        cp_ctx(ctx, 0x402a00, 1);
+                        cp_ctx(ctx, 0x402a40, 1);
+                        cp_ctx(ctx, 0x402a80, 1);
+                        cp_ctx(ctx, 0x402ac0, 1);
+                }
+                break;
+        case 0x40:
+                cp_ctx(ctx, 0x402844, 1);
+                gr_def(ctx, 0x402844, 0x00000001);
+                cp_ctx(ctx, 0x402850, 1);
+                break;
+        default:
+                cp_ctx(ctx, 0x402844, 1);
+                gr_def(ctx, 0x402844, 0x00001001);
+                cp_ctx(ctx, 0x402850, 2);
+                gr_def(ctx, 0x402854, 0x00000003);
+                break;
+        }
+
+        cp_ctx(ctx, 0x402c00, 4);
+        gr_def(ctx, 0x402c00, dev_priv->chipset == 0x40 ?
+                              0x80800001 : 0x00888001);
+        switch (dev_priv->chipset) {
+        case 0x47:
+        case 0x49:
+        case 0x4b:
+                cp_ctx(ctx, 0x402c20, 40);
+                for (i = 0; i < 32; i++)
+                        gr_def(ctx, 0x402c40 + (i * 4), 0xffffffff);
+                cp_ctx(ctx, 0x4030b8, 13);
+                gr_def(ctx, 0x4030dc, 0x00000005);
+                gr_def(ctx, 0x4030e8, 0x0000ffff);
+                break;
+        default:
+                cp_ctx(ctx, 0x402c10, 4);
+                if (dev_priv->chipset == 0x40)
+                        cp_ctx(ctx, 0x402c20, 36);
+                else
+                if (dev_priv->chipset <= 0x42)
+                        cp_ctx(ctx, 0x402c20, 24);
+                else
+                if (dev_priv->chipset <= 0x4a)
+                        cp_ctx(ctx, 0x402c20, 16);
+                else
+                        cp_ctx(ctx, 0x402c20, 8);
+                cp_ctx(ctx, 0x402cb0, dev_priv->chipset == 0x40 ? 12 : 13);
+                gr_def(ctx, 0x402cd4, 0x00000005);
+                if (dev_priv->chipset != 0x40)
+                        gr_def(ctx, 0x402ce0, 0x0000ffff);
+                break;
+        }
+
+        cp_ctx(ctx, 0x403400, dev_priv->chipset == 0x40 ? 4 : 3);
+        cp_ctx(ctx, 0x403410, dev_priv->chipset == 0x40 ? 4 : 3);
+        cp_ctx(ctx, 0x403420, nv40_graph_vs_count(ctx->dev));
+        for (i = 0; i < nv40_graph_vs_count(ctx->dev); i++)
+                gr_def(ctx, 0x403420 + (i * 4), 0x00005555);
+
+        if (dev_priv->chipset != 0x40) {
+                cp_ctx(ctx, 0x403600, 1);
+                gr_def(ctx, 0x403600, 0x00000001);
+        }
+        cp_ctx(ctx, 0x403800, 1);
+
+        cp_ctx(ctx, 0x403c18, 1);
+        gr_def(ctx, 0x403c18, 0x00000001);
+        switch (dev_priv->chipset) {
+        case 0x46:
+        case 0x47:
+        case 0x49:
+        case 0x4b:
+                cp_ctx(ctx, 0x405018, 1);
+                gr_def(ctx, 0x405018, 0x08e00001);
+                cp_ctx(ctx, 0x405c24, 1);
+                gr_def(ctx, 0x405c24, 0x000e3000);
+                break;
+        }
+        if (dev_priv->chipset != 0x4e)
+                cp_ctx(ctx, 0x405800, 11);
+        cp_ctx(ctx, 0x407000, 1);
+}
+
+static void
+nv40_graph_construct_state3d_3(struct nouveau_grctx *ctx)
+{
+        int len = nv40_graph_4097(ctx->dev) ? 0x0684 : 0x0084;
+
+        cp_out (ctx, 0x300000);
+        cp_lsr (ctx, len - 4);
+        cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_swap_state3d_3_is_save);
+        cp_lsr (ctx, len);
+        cp_name(ctx, cp_swap_state3d_3_is_save);
+        cp_out (ctx, 0x800001);
+
+        ctx->ctxvals_pos += len;
+}
+
+static void
+nv40_graph_construct_shader(struct nouveau_grctx *ctx)
+{
+        struct drm_device *dev = ctx->dev;
+        struct drm_nouveau_private *dev_priv = dev->dev_private;
+        struct nouveau_gpuobj *obj = ctx->data;
+        int vs, vs_nr, vs_len, vs_nr_b0, vs_nr_b1, b0_offset, b1_offset;
+        int offset, i;
+
+        vs_nr    = nv40_graph_vs_count(ctx->dev);
+        vs_nr_b0 = 363;
+        vs_nr_b1 = dev_priv->chipset == 0x40 ? 128 : 64;
+        if (dev_priv->chipset == 0x40) {
+                b0_offset = 0x2200/4; /* 33a0 */
+                b1_offset = 0x55a0/4; /* 1500 */
+                vs_len = 0x6aa0/4;
+        } else
+        if (dev_priv->chipset == 0x41 || dev_priv->chipset == 0x42) {
+                b0_offset = 0x2200/4; /* 2200 */
+                b1_offset = 0x4400/4; /* 0b00 */
+                vs_len = 0x4f00/4;
+        } else {
+                b0_offset = 0x1d40/4; /* 2200 */
+                b1_offset = 0x3f40/4; /* 0b00 : 0a40 */
+                vs_len = nv40_graph_4097(dev) ? 0x4a40/4 : 0x4980/4;
+        }
+
+        cp_lsr(ctx, vs_len * vs_nr + 0x300/4);
+        cp_out(ctx, nv40_graph_4097(dev) ? 0x800041 : 0x800029);
+
+        offset = ctx->ctxvals_pos;
+        ctx->ctxvals_pos += (0x0300/4 + (vs_nr * vs_len));
+
+        if (ctx->mode != NOUVEAU_GRCTX_VALS)
+                return;
+
+        offset += 0x0280/4;
+        for (i = 0; i < 16; i++, offset += 2)
+                nv_wo32(dev, obj, offset, 0x3f800000);
+
+        for (vs = 0; vs < vs_nr; vs++, offset += vs_len) {
+                for (i = 0; i < vs_nr_b0 * 6; i += 6)
+                        nv_wo32(dev, obj, offset + b0_offset + i, 0x00000001);
+                for (i = 0; i < vs_nr_b1 * 4; i += 4)
+                        nv_wo32(dev, obj, offset + b1_offset + i, 0x3f800000);
+        }
+}
+
+void
+nv40_grctx_init(struct nouveau_grctx *ctx)
+{
+        /* decide whether we're loading/unloading the context */
+        cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save);
+        cp_bra (ctx, USER_SAVE, PENDING, cp_setup_save);
+
+        cp_name(ctx, cp_check_load);
+        cp_bra (ctx, AUTO_LOAD, PENDING, cp_setup_auto_load);
+        cp_bra (ctx, USER_LOAD, PENDING, cp_setup_load);
+        cp_bra (ctx, ALWAYS, TRUE, cp_exit);
+
+        /* setup for context load */
+        cp_name(ctx, cp_setup_auto_load);
+        cp_wait(ctx, STATUS, IDLE);
+        cp_out (ctx, CP_NEXT_TO_SWAP);
+        cp_name(ctx, cp_setup_load);
+        cp_wait(ctx, STATUS, IDLE);
+        cp_set (ctx, SWAP_DIRECTION, LOAD);
+        cp_out (ctx, 0x00910880); /* ?? */
+        cp_out (ctx, 0x00901ffe); /* ?? */
+        cp_out (ctx, 0x01940000); /* ?? */
+        cp_lsr (ctx, 0x20);
+        cp_out (ctx, 0x0060000b); /* ?? */
+        cp_wait(ctx, UNK57, CLEAR);
+        cp_out (ctx, 0x0060000c); /* ?? */
+        cp_bra (ctx, ALWAYS, TRUE, cp_swap_state);
+
+        /* setup for context save */
+        cp_name(ctx, cp_setup_save);
+        cp_set (ctx, SWAP_DIRECTION, SAVE);
+
+        /* general PGRAPH state */
+        cp_name(ctx, cp_swap_state);
+        cp_pos (ctx, 0x00020/4);
+        nv40_graph_construct_general(ctx);
+        cp_wait(ctx, STATUS, IDLE);
+
+        /* 3D state, block 1 */
+        cp_bra (ctx, UNK54, CLEAR, cp_prepare_exit);
+        nv40_graph_construct_state3d(ctx);
+        cp_wait(ctx, STATUS, IDLE);
+
+        /* 3D state, block 2 */
+        nv40_graph_construct_state3d_2(ctx);
+
+        /* Some other block of "random" state */
+        nv40_graph_construct_state3d_3(ctx);
+
+        /* Per-vertex shader state */
+        cp_pos (ctx, ctx->ctxvals_pos);
+        nv40_graph_construct_shader(ctx);
+
+        /* pre-exit state updates */
+        cp_name(ctx, cp_prepare_exit);
+        cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_check_load);
+        cp_bra (ctx, USER_SAVE, PENDING, cp_exit);
+        cp_out (ctx, CP_NEXT_TO_CURRENT);
+
+        cp_name(ctx, cp_exit);
+        cp_set (ctx, USER_SAVE, NOT_PENDING);
+        cp_set (ctx, USER_LOAD, NOT_PENDING);
+        cp_out (ctx, CP_END);
+}
+
diff --git a/drivers/gpu/drm/nouveau/nv50_crtc.c b/drivers/gpu/drm/nouveau/nv50_crtc.c
index f8e28a1e44e7..118d3285fd8c 100644
--- a/drivers/gpu/drm/nouveau/nv50_crtc.c
+++ b/drivers/gpu/drm/nouveau/nv50_crtc.c
@@ -45,7 +45,7 @@ nv50_crtc_lut_load(struct drm_crtc *crtc)
         void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
         int i;
 
-        NV_DEBUG(crtc->dev, "\n");
+        NV_DEBUG_KMS(crtc->dev, "\n");
 
         for (i = 0; i < 256; i++) {
                 writew(nv_crtc->lut.r[i] >> 2, lut + 8*i + 0);
@@ -68,8 +68,8 @@ nv50_crtc_blank(struct nouveau_crtc *nv_crtc, bool blanked)
         struct nouveau_channel *evo = dev_priv->evo;
         int index = nv_crtc->index, ret;
 
-        NV_DEBUG(dev, "index %d\n", nv_crtc->index);
-        NV_DEBUG(dev, "%s\n", blanked ? "blanked" : "unblanked");
+        NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
+        NV_DEBUG_KMS(dev, "%s\n", blanked ? "blanked" : "unblanked");
 
         if (blanked) {
                 nv_crtc->cursor.hide(nv_crtc, false);
@@ -139,7 +139,7 @@ nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool on, bool update)
         struct nouveau_channel *evo = dev_priv->evo;
         int ret;
 
-        NV_DEBUG(dev, "\n");
+        NV_DEBUG_KMS(dev, "\n");
 
         ret = RING_SPACE(evo, 2 + (update ? 2 : 0));
         if (ret) {
@@ -193,7 +193,7 @@ nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, int scaling_mode, bool update)
         uint32_t outX, outY, horiz, vert;
         int ret;
 
-        NV_DEBUG(dev, "\n");
+        NV_DEBUG_KMS(dev, "\n");
 
         switch (scaling_mode) {
         case DRM_MODE_SCALE_NONE:
@@ -301,7 +301,7 @@ nv50_crtc_destroy(struct drm_crtc *crtc)
         struct drm_device *dev = crtc->dev;
         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 
-        NV_DEBUG(dev, "\n");
+        NV_DEBUG_KMS(dev, "\n");
 
         if (!crtc)
                 return;
@@ -433,7 +433,7 @@ nv50_crtc_prepare(struct drm_crtc *crtc)
         struct drm_device *dev = crtc->dev;
         struct drm_encoder *encoder;
 
-        NV_DEBUG(dev, "index %d\n", nv_crtc->index);
+        NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
 
         /* Disconnect all unused encoders. */
         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
@@ -458,7 +458,7 @@ nv50_crtc_commit(struct drm_crtc *crtc)
         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
         int ret;
 
-        NV_DEBUG(dev, "index %d\n", nv_crtc->index);
+        NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
 
         nv50_crtc_blank(nv_crtc, false);
 
@@ -497,7 +497,7 @@ nv50_crtc_do_mode_set_base(struct drm_crtc *crtc, int x, int y,
         struct nouveau_framebuffer *fb = nouveau_framebuffer(drm_fb);
         int ret, format;
 
-        NV_DEBUG(dev, "index %d\n", nv_crtc->index);
+        NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
 
         switch (drm_fb->depth) {
         case  8:
@@ -612,7 +612,7 @@ nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
 
         *nv_crtc->mode = *adjusted_mode;
 
-        NV_DEBUG(dev, "index %d\n", nv_crtc->index);
+        NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
 
         hsync_dur = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
         vsync_dur = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
@@ -706,7 +706,7 @@ nv50_crtc_create(struct drm_device *dev, int index)
         struct nouveau_crtc *nv_crtc = NULL;
         int ret, i;
 
-        NV_DEBUG(dev, "\n");
+        NV_DEBUG_KMS(dev, "\n");
 
         nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL);
         if (!nv_crtc)
diff --git a/drivers/gpu/drm/nouveau/nv50_cursor.c b/drivers/gpu/drm/nouveau/nv50_cursor.c
index e2e79a8f220d..753e723adb3a 100644
--- a/drivers/gpu/drm/nouveau/nv50_cursor.c
+++ b/drivers/gpu/drm/nouveau/nv50_cursor.c
@@ -41,7 +41,7 @@ nv50_cursor_show(struct nouveau_crtc *nv_crtc, bool update)
         struct drm_device *dev = nv_crtc->base.dev;
         int ret;
 
-        NV_DEBUG(dev, "\n");
+        NV_DEBUG_KMS(dev, "\n");
 
         if (update && nv_crtc->cursor.visible)
                 return;
@@ -76,7 +76,7 @@ nv50_cursor_hide(struct nouveau_crtc *nv_crtc, bool update)
         struct drm_device *dev = nv_crtc->base.dev;
         int ret;
 
-        NV_DEBUG(dev, "\n");
+        NV_DEBUG_KMS(dev, "\n");
 
         if (update && !nv_crtc->cursor.visible)
                 return;
@@ -116,7 +116,7 @@ nv50_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y)
 static void
 nv50_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset)
 {
-        NV_DEBUG(nv_crtc->base.dev, "\n");
+        NV_DEBUG_KMS(nv_crtc->base.dev, "\n");
         if (offset == nv_crtc->cursor.offset)
                 return;
 
@@ -143,7 +143,7 @@ nv50_cursor_fini(struct nouveau_crtc *nv_crtc)
         struct drm_device *dev = nv_crtc->base.dev;
         int idx = nv_crtc->index;
 
-        NV_DEBUG(dev, "\n");
+        NV_DEBUG_KMS(dev, "\n");
 
         nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(idx), 0);
         if (!nv_wait(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(idx),
diff --git a/drivers/gpu/drm/nouveau/nv50_dac.c b/drivers/gpu/drm/nouveau/nv50_dac.c
index fb5838e3be24..f08f042a8e10 100644
--- a/drivers/gpu/drm/nouveau/nv50_dac.c
+++ b/drivers/gpu/drm/nouveau/nv50_dac.c
@@ -44,7 +44,7 @@ nv50_dac_disconnect(struct nouveau_encoder *nv_encoder)
         struct nouveau_channel *evo = dev_priv->evo;
         int ret;
 
-        NV_DEBUG(dev, "Disconnecting DAC %d\n", nv_encoder->or);
+        NV_DEBUG_KMS(dev, "Disconnecting DAC %d\n", nv_encoder->or);
 
         ret = RING_SPACE(evo, 2);
         if (ret) {
@@ -81,11 +81,11 @@ nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
         /* Use bios provided value if possible. */
         if (dev_priv->vbios->dactestval) {
                 load_pattern = dev_priv->vbios->dactestval;
-                NV_DEBUG(dev, "Using bios provided load_pattern of %d\n",
+                NV_DEBUG_KMS(dev, "Using bios provided load_pattern of %d\n",
                           load_pattern);
         } else {
                 load_pattern = 340;
-                NV_DEBUG(dev, "Using default load_pattern of %d\n",
+                NV_DEBUG_KMS(dev, "Using default load_pattern of %d\n",
                          load_pattern);
         }
 
@@ -103,9 +103,9 @@ nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
                 status = connector_status_connected;
 
         if (status == connector_status_connected)
-                NV_DEBUG(dev, "Load was detected on output with or %d\n", or);
+                NV_DEBUG_KMS(dev, "Load was detected on output with or %d\n", or);
         else
-                NV_DEBUG(dev, "Load was not detected on output with or %d\n", or);
+                NV_DEBUG_KMS(dev, "Load was not detected on output with or %d\n", or);
 
         return status;
 }
@@ -118,7 +118,7 @@ nv50_dac_dpms(struct drm_encoder *encoder, int mode)
         uint32_t val;
         int or = nv_encoder->or;
 
-        NV_DEBUG(dev, "or %d mode %d\n", or, mode);
+        NV_DEBUG_KMS(dev, "or %d mode %d\n", or, mode);
 
         /* wait for it to be done */
         if (!nv_wait(NV50_PDISPLAY_DAC_DPMS_CTRL(or),
@@ -173,7 +173,7 @@ nv50_dac_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
         struct nouveau_connector *connector;
 
-        NV_DEBUG(encoder->dev, "or %d\n", nv_encoder->or);
+        NV_DEBUG_KMS(encoder->dev, "or %d\n", nv_encoder->or);
 
         connector = nouveau_encoder_connector_get(nv_encoder);
         if (!connector) {
@@ -213,7 +213,7 @@ nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
         uint32_t mode_ctl = 0, mode_ctl2 = 0;
         int ret;
 
-        NV_DEBUG(dev, "or %d\n", nv_encoder->or);
+        NV_DEBUG_KMS(dev, "or %d\n", nv_encoder->or);
 
         nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON);
 
@@ -264,7 +264,7 @@ nv50_dac_destroy(struct drm_encoder *encoder)
         if (!encoder)
                 return;
 
-        NV_DEBUG(encoder->dev, "\n");
+        NV_DEBUG_KMS(encoder->dev, "\n");
 
         drm_encoder_cleanup(encoder);
         kfree(nv_encoder);
@@ -280,7 +280,7 @@ nv50_dac_create(struct drm_device *dev, struct dcb_entry *entry)
         struct nouveau_encoder *nv_encoder;
         struct drm_encoder *encoder;
 
-        NV_DEBUG(dev, "\n");
+        NV_DEBUG_KMS(dev, "\n");
         NV_INFO(dev, "Detected a DAC output\n");
 
         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index 12c5ee63495b..90f0bf59fbcd 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -188,7 +188,7 @@ nv50_display_init(struct drm_device *dev)
         uint64_t start;
         int ret, i;
 
-        NV_DEBUG(dev, "\n");
+        NV_DEBUG_KMS(dev, "\n");
 
         nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004));
         /*
@@ -232,7 +232,7 @@ nv50_display_init(struct drm_device *dev)
         nv_wr32(dev, NV50_PDISPLAY_UNK_380, 0);
         /* RAM is clamped to 256 MiB. */
         ram_amount = nouveau_mem_fb_amount(dev);
-        NV_DEBUG(dev, "ram_amount %d\n", ram_amount);
+        NV_DEBUG_KMS(dev, "ram_amount %d\n", ram_amount);
         if (ram_amount > 256*1024*1024)
                 ram_amount = 256*1024*1024;
         nv_wr32(dev, NV50_PDISPLAY_RAM_AMOUNT, ram_amount - 1);
@@ -398,7 +398,7 @@ static int nv50_display_disable(struct drm_device *dev)
         struct drm_crtc *drm_crtc;
         int ret, i;
 
-        NV_DEBUG(dev, "\n");
+        NV_DEBUG_KMS(dev, "\n");
 
         list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
                 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
@@ -469,7 +469,7 @@ int nv50_display_create(struct drm_device *dev)
         uint32_t connector[16] = {};
         int ret, i;
 
-        NV_DEBUG(dev, "\n");
+        NV_DEBUG_KMS(dev, "\n");
 
         /* init basic kernel modesetting */
         drm_mode_config_init(dev);
@@ -573,7 +573,7 @@ int nv50_display_destroy(struct drm_device *dev)
 {
         struct drm_nouveau_private *dev_priv = dev->dev_private;
 
-        NV_DEBUG(dev, "\n");
+        NV_DEBUG_KMS(dev, "\n");
 
         drm_mode_config_cleanup(dev);
 
@@ -617,7 +617,7 @@ nv50_display_irq_head(struct drm_device *dev, int *phead,
          * CRTC separately, and submission will be blocked by the GPU
          * until we handle each in turn.
          */
-        NV_DEBUG(dev, "0x610030: 0x%08x\n", unk30);
+        NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
         head = ffs((unk30 >> 9) & 3) - 1;
         if (head < 0)
                 return -EINVAL;
@@ -661,7 +661,7 @@ nv50_display_irq_head(struct drm_device *dev, int *phead,
                 or = i;
         }
 
-        NV_DEBUG(dev, "type %d, or %d\n", type, or);
+        NV_DEBUG_KMS(dev, "type %d, or %d\n", type, or);
         if (type == OUTPUT_ANY) {
                 NV_ERROR(dev, "unknown encoder!!\n");
                 return -1;
@@ -690,9 +690,21 @@ nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcbent,
                            int pxclk)
 {
         struct drm_nouveau_private *dev_priv = dev->dev_private;
+        struct nouveau_connector *nv_connector = NULL;
+        struct drm_encoder *encoder;
         struct nvbios *bios = &dev_priv->VBIOS;
         uint32_t mc, script = 0, or;
 
+        list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+                struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
+
+                if (nv_encoder->dcb != dcbent)
+                        continue;
+
+                nv_connector = nouveau_encoder_connector_get(nv_encoder);
+                break;
+        }
+
         or = ffs(dcbent->or) - 1;
         mc = nv50_display_mode_ctrl(dev, dcbent->type != OUTPUT_ANALOG, or);
         switch (dcbent->type) {
@@ -711,6 +723,11 @@ nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcbent,
                         } else
                         if (bios->fp.strapless_is_24bit & 1)
                                 script |= 0x0200;
+
+                        if (nv_connector && nv_connector->edid &&
+                            (nv_connector->edid->revision >= 4) &&
+                            (nv_connector->edid->input & 0x70) >= 0x20)
+                                script |= 0x0200;
                 }
 
                 if (nouveau_uscript_lvds >= 0) {
@@ -811,7 +828,7 @@ nv50_display_unk20_handler(struct drm_device *dev)
         pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(head, CLOCK)) & 0x3fffff;
         script = nv50_display_script_select(dev, dcbent, pclk);
 
-        NV_DEBUG(dev, "head %d pxclk: %dKHz\n", head, pclk);
+        NV_DEBUG_KMS(dev, "head %d pxclk: %dKHz\n", head, pclk);
 
         if (dcbent->type != OUTPUT_DP)
                 nouveau_bios_run_display_table(dev, dcbent, 0, -2);
@@ -870,7 +887,7 @@ nv50_display_irq_handler_bh(struct work_struct *work)
                 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
                 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
 
-                NV_DEBUG(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1);
+                NV_DEBUG_KMS(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1);
 
                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10)
                         nv50_display_unk10_handler(dev);
@@ -974,7 +991,7 @@ nv50_display_irq_handler(struct drm_device *dev)
                 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
                 uint32_t clock;
 
-                NV_DEBUG(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1);
+                NV_DEBUG_KMS(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1);
 
                 if (!intr0 && !(intr1 & ~delayed))
                         break;
diff --git a/drivers/gpu/drm/nouveau/nv50_fbcon.c b/drivers/gpu/drm/nouveau/nv50_fbcon.c
index 6bcc6d39e9b0..e4f279ee61cf 100644
--- a/drivers/gpu/drm/nouveau/nv50_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nv50_fbcon.c
@@ -16,9 +16,7 @@ nv50_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
 
         if (!(info->flags & FBINFO_HWACCEL_DISABLED) &&
              RING_SPACE(chan, rect->rop == ROP_COPY ? 7 : 11)) {
-                NV_ERROR(dev, "GPU lockup - switching to software fbcon\n");
-
-                info->flags |= FBINFO_HWACCEL_DISABLED;
+                nouveau_fbcon_gpu_lockup(info);
         }
 
         if (info->flags & FBINFO_HWACCEL_DISABLED) {
@@ -31,7 +29,11 @@ nv50_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
                 OUT_RING(chan, 1);
         }
         BEGIN_RING(chan, NvSub2D, 0x0588, 1);
-        OUT_RING(chan, rect->color);
+        if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
+            info->fix.visual == FB_VISUAL_DIRECTCOLOR)
+                OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]);
+        else
+                OUT_RING(chan, rect->color);
         BEGIN_RING(chan, NvSub2D, 0x0600, 4);
         OUT_RING(chan, rect->dx);
         OUT_RING(chan, rect->dy);
@@ -56,9 +58,7 @@ nv50_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region)
                 return;
 
         if (!(info->flags & FBINFO_HWACCEL_DISABLED) && RING_SPACE(chan, 12)) {
-                NV_ERROR(dev, "GPU lockup - switching to software fbcon\n");
-
-                info->flags |= FBINFO_HWACCEL_DISABLED;
+                nouveau_fbcon_gpu_lockup(info);
         }
 
         if (info->flags & FBINFO_HWACCEL_DISABLED) {
@@ -101,8 +101,7 @@ nv50_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
         }
 
         if (!(info->flags & FBINFO_HWACCEL_DISABLED) && RING_SPACE(chan, 11)) {
-                NV_ERROR(dev, "GPU lockup - switching to software fbcon\n");
-                info->flags |= FBINFO_HWACCEL_DISABLED;
+                nouveau_fbcon_gpu_lockup(info);
         }
 
         if (info->flags & FBINFO_HWACCEL_DISABLED) {
@@ -135,9 +134,7 @@ nv50_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
                 int push = dwords > 2047 ? 2047 : dwords;
 
                 if (RING_SPACE(chan, push + 1)) {
-                        NV_ERROR(dev,
-                                 "GPU lockup - switching to software fbcon\n");
-                        info->flags |= FBINFO_HWACCEL_DISABLED;
+                        nouveau_fbcon_gpu_lockup(info);
                         cfb_imageblit(info, image);
                         return;
                 }
@@ -199,7 +196,7 @@ nv50_fbcon_accel_init(struct fb_info *info)
 
         ret = RING_SPACE(chan, 59);
         if (ret) {
-                NV_ERROR(dev, "GPU lockup - switching to software fbcon\n");
+                nouveau_fbcon_gpu_lockup(info);
                 return ret;
         }
 
diff --git a/drivers/gpu/drm/nouveau/nv50_fifo.c b/drivers/gpu/drm/nouveau/nv50_fifo.c
index 77ae1aaa0bce..39caf167587d 100644
--- a/drivers/gpu/drm/nouveau/nv50_fifo.c
+++ b/drivers/gpu/drm/nouveau/nv50_fifo.c
@@ -384,8 +384,8 @@ nv50_fifo_load_context(struct nouveau_channel *chan)
                 nv_wr32(dev, NV40_PFIFO_CACHE1_DATA(ptr),
                         nv_ro32(dev, cache, (ptr * 2) + 1));
         }
-        nv_wr32(dev, 0x3210, cnt << 2);
-        nv_wr32(dev, 0x3270, 0);
+        nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, cnt << 2);
+        nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0);
 
         /* guessing that all the 0x34xx regs aren't on NV50 */
         if (!IS_G80) {
@@ -398,8 +398,6 @@ nv50_fifo_load_context(struct nouveau_channel *chan)
 
         dev_priv->engine.instmem.finish_access(dev);
 
-        nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0);
-        nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, 0);
         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, chan->id | (1<<16));
         return 0;
 }
@@ -416,7 +414,7 @@ nv50_fifo_unload_context(struct drm_device *dev)
         NV_DEBUG(dev, "\n");
 
         chid = pfifo->channel_id(dev);
-        if (chid < 0 || chid >= dev_priv->engine.fifo.channels)
+        if (chid < 1 || chid >= dev_priv->engine.fifo.channels - 1)
                 return 0;
 
         chan = dev_priv->fifos[chid];
diff --git a/drivers/gpu/drm/nouveau/nv50_graph.c b/drivers/gpu/drm/nouveau/nv50_graph.c
index 177d8229336f..ca79f32be44c 100644
--- a/drivers/gpu/drm/nouveau/nv50_graph.c
+++ b/drivers/gpu/drm/nouveau/nv50_graph.c
@@ -107,9 +107,13 @@ nv50_graph_init_regs(struct drm_device *dev)
 static int
 nv50_graph_init_ctxctl(struct drm_device *dev)
 {
+        struct drm_nouveau_private *dev_priv = dev->dev_private;
+
         NV_DEBUG(dev, "\n");
 
-        nv40_grctx_init(dev);
+        nouveau_grctx_prog_load(dev);
+        if (!dev_priv->engine.graph.ctxprog)
+                dev_priv->engine.graph.accel_blocked = true;
 
         nv_wr32(dev, 0x400320, 4);
         nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0);
@@ -140,7 +144,7 @@ void
 nv50_graph_takedown(struct drm_device *dev)
 {
         NV_DEBUG(dev, "\n");
-        nv40_grctx_fini(dev);
+        nouveau_grctx_fini(dev);
 }
 
 void
@@ -207,7 +211,7 @@ nv50_graph_create_context(struct nouveau_channel *chan)
         dev_priv->engine.instmem.finish_access(dev);
 
         dev_priv->engine.instmem.prepare_access(dev, true);
-        nv40_grctx_vals_load(dev, ctx);
+        nouveau_grctx_vals_load(dev, ctx);
         nv_wo32(dev, ctx, 0x00000/4, chan->ramin->instance >> 12);
         if ((dev_priv->chipset & 0xf0) == 0xa0)
                 nv_wo32(dev, ctx, 0x00004/4, 0x00000000);
diff --git a/drivers/gpu/drm/nouveau/nv50_sor.c b/drivers/gpu/drm/nouveau/nv50_sor.c
index 8c280463a664..e395c16d30f5 100644
--- a/drivers/gpu/drm/nouveau/nv50_sor.c
+++ b/drivers/gpu/drm/nouveau/nv50_sor.c
@@ -44,7 +44,7 @@ nv50_sor_disconnect(struct nouveau_encoder *nv_encoder)
         struct nouveau_channel *evo = dev_priv->evo;
         int ret;
 
-        NV_DEBUG(dev, "Disconnecting SOR %d\n", nv_encoder->or);
+        NV_DEBUG_KMS(dev, "Disconnecting SOR %d\n", nv_encoder->or);
 
         ret = RING_SPACE(evo, 2);
         if (ret) {
@@ -70,7 +70,7 @@ nv50_sor_dp_link_train(struct drm_encoder *encoder)
         }
 
         if (dpe->script0) {
-                NV_DEBUG(dev, "SOR-%d: running DP script 0\n", nv_encoder->or);
+                NV_DEBUG_KMS(dev, "SOR-%d: running DP script 0\n", nv_encoder->or);
                 nouveau_bios_run_init_table(dev, le16_to_cpu(dpe->script0),
                                             nv_encoder->dcb);
         }
@@ -79,7 +79,7 @@ nv50_sor_dp_link_train(struct drm_encoder *encoder)
                 NV_ERROR(dev, "SOR-%d: link training failed\n", nv_encoder->or);
 
         if (dpe->script1) {
-                NV_DEBUG(dev, "SOR-%d: running DP script 1\n", nv_encoder->or);
+                NV_DEBUG_KMS(dev, "SOR-%d: running DP script 1\n", nv_encoder->or);
                 nouveau_bios_run_init_table(dev, le16_to_cpu(dpe->script1),
                                             nv_encoder->dcb);
         }
@@ -93,7 +93,7 @@ nv50_sor_dpms(struct drm_encoder *encoder, int mode)
         uint32_t val;
         int or = nv_encoder->or;
 
-        NV_DEBUG(dev, "or %d mode %d\n", or, mode);
+        NV_DEBUG_KMS(dev, "or %d mode %d\n", or, mode);
 
         /* wait for it to be done */
         if (!nv_wait(NV50_PDISPLAY_SOR_DPMS_CTRL(or),
@@ -142,7 +142,7 @@ nv50_sor_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
         struct nouveau_connector *connector;
 
-        NV_DEBUG(encoder->dev, "or %d\n", nv_encoder->or);
+        NV_DEBUG_KMS(encoder->dev, "or %d\n", nv_encoder->or);
 
         connector = nouveau_encoder_connector_get(nv_encoder);
         if (!connector) {
@@ -182,7 +182,7 @@ nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
         uint32_t mode_ctl = 0;
         int ret;
 
-        NV_DEBUG(dev, "or %d\n", nv_encoder->or);
+        NV_DEBUG_KMS(dev, "or %d\n", nv_encoder->or);
 
         nv50_sor_dpms(encoder, DRM_MODE_DPMS_ON);
 
@@ -246,7 +246,7 @@ nv50_sor_destroy(struct drm_encoder *encoder)
         if (!encoder)
                 return;
 
-        NV_DEBUG(encoder->dev, "\n");
+        NV_DEBUG_KMS(encoder->dev, "\n");
 
         drm_encoder_cleanup(encoder);
 
@@ -265,7 +265,7 @@ nv50_sor_create(struct drm_device *dev, struct dcb_entry *entry)
         bool dum;
         int type;
 
-        NV_DEBUG(dev, "\n");
+        NV_DEBUG_KMS(dev, "\n");
 
         switch (entry->type) {
         case OUTPUT_TMDS:
diff --git a/drivers/gpu/drm/r128/r128_drv.c b/drivers/gpu/drm/r128/r128_drv.c
index 601f4c0e5da5..b806fdcc7170 100644
--- a/drivers/gpu/drm/r128/r128_drv.c
+++ b/drivers/gpu/drm/r128/r128_drv.c
@@ -64,7 +64,7 @@ static struct drm_driver driver = {
                 .owner = THIS_MODULE,
                 .open = drm_open,
                 .release = drm_release,
-                .ioctl = drm_ioctl,
+                .unlocked_ioctl = drm_ioctl,
                 .mmap = drm_mmap,
                 .poll = drm_poll,
                 .fasync = drm_fasync,
diff --git a/drivers/gpu/drm/r128/r128_ioc32.c b/drivers/gpu/drm/r128/r128_ioc32.c
index d3cb676eee84..51c99fc4dd38 100644
--- a/drivers/gpu/drm/r128/r128_ioc32.c
+++ b/drivers/gpu/drm/r128/r128_ioc32.c
@@ -95,8 +95,7 @@ static int compat_r128_init(struct file *file, unsigned int cmd,
                           &init->agp_textures_offset))
                 return -EFAULT;
 
-        return drm_ioctl(file->f_path.dentry->d_inode, file,
-                         DRM_IOCTL_R128_INIT, (unsigned long)init);
+        return drm_ioctl(file, DRM_IOCTL_R128_INIT, (unsigned long)init);
 }
 
 typedef struct drm_r128_depth32 {
@@ -129,8 +128,7 @@ static int compat_r128_depth(struct file *file, unsigned int cmd,
                           &depth->mask))
                 return -EFAULT;
 
-        return drm_ioctl(file->f_path.dentry->d_inode, file,
-                         DRM_IOCTL_R128_DEPTH, (unsigned long)depth);
+        return drm_ioctl(file, DRM_IOCTL_R128_DEPTH, (unsigned long)depth);
 
 }
 
@@ -153,8 +151,7 @@ static int compat_r128_stipple(struct file *file, unsigned int cmd,
                           &stipple->mask))
                 return -EFAULT;
 
-        return drm_ioctl(file->f_path.dentry->d_inode, file,
-                         DRM_IOCTL_R128_STIPPLE, (unsigned long)stipple);
+        return drm_ioctl(file, DRM_IOCTL_R128_STIPPLE, (unsigned long)stipple);
 }
 
 typedef struct drm_r128_getparam32 {
@@ -178,8 +175,7 @@ static int compat_r128_getparam(struct file *file, unsigned int cmd,
                           &getparam->value))
                 return -EFAULT;
 
-        return drm_ioctl(file->f_path.dentry->d_inode, file,
-                         DRM_IOCTL_R128_GETPARAM, (unsigned long)getparam);
+        return drm_ioctl(file, DRM_IOCTL_R128_GETPARAM, (unsigned long)getparam);
 }
 
 drm_ioctl_compat_t *r128_compat_ioctls[] = {
@@ -210,12 +206,10 @@ long r128_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
         if (nr < DRM_COMMAND_BASE + DRM_ARRAY_SIZE(r128_compat_ioctls))
                 fn = r128_compat_ioctls[nr - DRM_COMMAND_BASE];
 
-        lock_kernel();          /* XXX for now */
         if (fn != NULL)
                 ret = (*fn) (filp, cmd, arg);
         else
-                ret = drm_ioctl(filp->f_path.dentry->d_inode, filp, cmd, arg);
-        unlock_kernel();
+                ret = drm_ioctl(filp, cmd, arg);
 
         return ret;
 }
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index b5f5fe75e6af..1cc7b937b1ea 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -24,6 +24,9 @@ $(obj)/rv515_reg_safe.h: $(src)/reg_srcs/rv515 $(obj)/mkregtable
 $(obj)/r300_reg_safe.h: $(src)/reg_srcs/r300 $(obj)/mkregtable
         $(call if_changed,mkregtable)
 
+$(obj)/r420_reg_safe.h: $(src)/reg_srcs/r420 $(obj)/mkregtable
+        $(call if_changed,mkregtable)
+
 $(obj)/rs600_reg_safe.h: $(src)/reg_srcs/rs600 $(obj)/mkregtable
         $(call if_changed,mkregtable)
 
@@ -35,6 +38,8 @@ $(obj)/rv515.o: $(obj)/rv515_reg_safe.h
 
 $(obj)/r300.o: $(obj)/r300_reg_safe.h
 
+$(obj)/r420.o: $(obj)/r420_reg_safe.h
+
 $(obj)/rs600.o: $(obj)/rs600_reg_safe.h
 
 radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o \
diff --git a/drivers/gpu/drm/radeon/ObjectID.h b/drivers/gpu/drm/radeon/ObjectID.h
index 6d0183c61d3b..c714179d1bfa 100644
--- a/drivers/gpu/drm/radeon/ObjectID.h
+++ b/drivers/gpu/drm/radeon/ObjectID.h
@@ -1,5 +1,5 @@
 /*
-* Copyright 2006-2007 Advanced Micro Devices, Inc.
+* Copyright 2006-2007 Advanced Micro Devices, Inc.  
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -41,14 +41,14 @@
 /****************************************************/
 /* Encoder Object ID Definition                     */
 /****************************************************/
-#define ENCODER_OBJECT_ID_NONE                    0x00
+#define ENCODER_OBJECT_ID_NONE                    0x00 
 
 /* Radeon Class Display Hardware */
 #define ENCODER_OBJECT_ID_INTERNAL_LVDS           0x01
 #define ENCODER_OBJECT_ID_INTERNAL_TMDS1          0x02
 #define ENCODER_OBJECT_ID_INTERNAL_TMDS2          0x03
 #define ENCODER_OBJECT_ID_INTERNAL_DAC1           0x04
-#define ENCODER_OBJECT_ID_INTERNAL_DAC2           0x05  /* TV/CV DAC */
+#define ENCODER_OBJECT_ID_INTERNAL_DAC2           0x05     /* TV/CV DAC */
 #define ENCODER_OBJECT_ID_INTERNAL_SDVOA          0x06
 #define ENCODER_OBJECT_ID_INTERNAL_SDVOB          0x07
 
@@ -56,11 +56,11 @@
 #define ENCODER_OBJECT_ID_SI170B                  0x08
 #define ENCODER_OBJECT_ID_CH7303                  0x09
 #define ENCODER_OBJECT_ID_CH7301                  0x0A
-#define ENCODER_OBJECT_ID_INTERNAL_DVO1           0x0B  /* This belongs to Radeon Class Display Hardware */
+#define ENCODER_OBJECT_ID_INTERNAL_DVO1           0x0B    /* This belongs to Radeon Class Display Hardware */
 #define ENCODER_OBJECT_ID_EXTERNAL_SDVOA          0x0C
 #define ENCODER_OBJECT_ID_EXTERNAL_SDVOB          0x0D
 #define ENCODER_OBJECT_ID_TITFP513                0x0E
-#define ENCODER_OBJECT_ID_INTERNAL_LVTM1          0x0F  /* not used for Radeon */
+#define ENCODER_OBJECT_ID_INTERNAL_LVTM1          0x0F    /* not used for Radeon */
 #define ENCODER_OBJECT_ID_VT1623                  0x10
 #define ENCODER_OBJECT_ID_HDMI_SI1930             0x11
 #define ENCODER_OBJECT_ID_HDMI_INTERNAL           0x12
@@ -68,9 +68,9 @@
 #define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1   0x13
 #define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1    0x14
 #define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1    0x15
-#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2    0x16  /* Shared with CV/TV and CRT */
-#define ENCODER_OBJECT_ID_SI178                   0X17  /* External TMDS (dual link, no HDCP.) */
-#define ENCODER_OBJECT_ID_MVPU_FPGA               0x18  /* MVPU FPGA chip */
+#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2    0x16  /* Shared with CV/TV and CRT */
+#define ENCODER_OBJECT_ID_SI178                   0X17  /* External TMDS (dual link, no HDCP.) */
+#define ENCODER_OBJECT_ID_MVPU_FPGA               0x18  /* MVPU FPGA chip */
 #define ENCODER_OBJECT_ID_INTERNAL_DDI            0x19
 #define ENCODER_OBJECT_ID_VT1625                  0x1A
 #define ENCODER_OBJECT_ID_HDMI_SI1932             0x1B
@@ -86,7 +86,7 @@
 /****************************************************/
 /* Connector Object ID Definition                   */
 /****************************************************/
-#define CONNECTOR_OBJECT_ID_NONE                  0x00
+#define CONNECTOR_OBJECT_ID_NONE                  0x00 
 #define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I     0x01
 #define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I       0x02
 #define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D     0x03
@@ -96,7 +96,7 @@
 #define CONNECTOR_OBJECT_ID_SVIDEO                0x07
 #define CONNECTOR_OBJECT_ID_YPbPr                 0x08
 #define CONNECTOR_OBJECT_ID_D_CONNECTOR           0x09
-#define CONNECTOR_OBJECT_ID_9PIN_DIN              0x0A  /* Supports both CV & TV */
+#define CONNECTOR_OBJECT_ID_9PIN_DIN              0x0A  /* Supports both CV & TV */
 #define CONNECTOR_OBJECT_ID_SCART                 0x0B
 #define CONNECTOR_OBJECT_ID_HDMI_TYPE_A           0x0C
 #define CONNECTOR_OBJECT_ID_HDMI_TYPE_B           0x0D
@@ -106,6 +106,8 @@
 #define CONNECTOR_OBJECT_ID_CROSSFIRE             0x11
 #define CONNECTOR_OBJECT_ID_HARDCODE_DVI          0x12
 #define CONNECTOR_OBJECT_ID_DISPLAYPORT           0x13
+#define CONNECTOR_OBJECT_ID_eDP                   0x14
+#define CONNECTOR_OBJECT_ID_MXM                   0x15
 
 /* deleted */
 
@@ -116,6 +118,14 @@
 #define ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL                              0x01
 
 /****************************************************/
+/* Generic Object ID Definition                     */
+/****************************************************/
+#define GENERIC_OBJECT_ID_NONE                    0x00
+#define GENERIC_OBJECT_ID_GLSYNC                  0x01
+#define GENERIC_OBJECT_ID_PX2_NON_DRIVABLE        0x02
+#define GENERIC_OBJECT_ID_MXM_OPM                 0x03
+
+/****************************************************/
 /* Graphics Object ENUM ID Definition               */
 /****************************************************/
 #define GRAPH_OBJECT_ENUM_ID1                     0x01
@@ -124,6 +134,7 @@
 #define GRAPH_OBJECT_ENUM_ID4                     0x04
 #define GRAPH_OBJECT_ENUM_ID5                     0x05
 #define GRAPH_OBJECT_ENUM_ID6                     0x06
+#define GRAPH_OBJECT_ENUM_ID7                     0x07
 
 /****************************************************/
 /* Graphics Object ID Bit definition                */
@@ -133,35 +144,35 @@
 #define RESERVED1_ID_MASK                         0x0800
 #define OBJECT_TYPE_MASK                          0x7000
 #define RESERVED2_ID_MASK                         0x8000
-
+                                                  
 #define OBJECT_ID_SHIFT                           0x00
 #define ENUM_ID_SHIFT                             0x08
 #define OBJECT_TYPE_SHIFT                         0x0C
 
+
 /****************************************************/
 /* Graphics Object family definition                */
 /****************************************************/
-#define CONSTRUCTOBJECTFAMILYID(GRAPHICS_OBJECT_TYPE, GRAPHICS_OBJECT_ID) \
-        (GRAPHICS_OBJECT_TYPE << OBJECT_TYPE_SHIFT | \
-         GRAPHICS_OBJECT_ID   << OBJECT_ID_SHIFT)
+#define CONSTRUCTOBJECTFAMILYID(GRAPHICS_OBJECT_TYPE, GRAPHICS_OBJECT_ID) (GRAPHICS_OBJECT_TYPE << OBJECT_TYPE_SHIFT | \
+                                                                           GRAPHICS_OBJECT_ID   << OBJECT_ID_SHIFT)
 /****************************************************/
 /* GPU Object ID definition - Shared with BIOS      */
 /****************************************************/
-#define GPU_ENUM_ID1    (GRAPH_OBJECT_TYPE_GPU << OBJECT_TYPE_SHIFT |\
-                         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT)
+#define GPU_ENUM_ID1                            ( GRAPH_OBJECT_TYPE_GPU << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT)
 
 /****************************************************/
 /* Encoder Object ID definition - Shared with BIOS  */
 /****************************************************/
 /*
-#define ENCODER_INTERNAL_LVDS_ENUM_ID1        0x2101
+#define ENCODER_INTERNAL_LVDS_ENUM_ID1        0x2101      
 #define ENCODER_INTERNAL_TMDS1_ENUM_ID1       0x2102
 #define ENCODER_INTERNAL_TMDS2_ENUM_ID1       0x2103
 #define ENCODER_INTERNAL_DAC1_ENUM_ID1        0x2104
 #define ENCODER_INTERNAL_DAC2_ENUM_ID1        0x2105
 #define ENCODER_INTERNAL_SDVOA_ENUM_ID1       0x2106
 #define ENCODER_INTERNAL_SDVOB_ENUM_ID1       0x2107
-#define ENCODER_SIL170B_ENUM_ID1              0x2108
+#define ENCODER_SIL170B_ENUM_ID1              0x2108  
 #define ENCODER_CH7303_ENUM_ID1               0x2109
 #define ENCODER_CH7301_ENUM_ID1               0x210A
 #define ENCODER_INTERNAL_DVO1_ENUM_ID1        0x210B
@@ -175,8 +186,8 @@
 #define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1   0x2113
 #define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1    0x2114
 #define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1    0x2115
-#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1    0x2116
-#define ENCODER_SI178_ENUM_ID1                   0x2117
+#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1    0x2116  
+#define ENCODER_SI178_ENUM_ID1                   0x2117 
 #define ENCODER_MVPU_FPGA_ENUM_ID1               0x2118
 #define ENCODER_INTERNAL_DDI_ENUM_ID1            0x2119
 #define ENCODER_VT1625_ENUM_ID1                  0x211A
@@ -185,205 +196,169 @@
 #define ENCODER_DP_DP501_ENUM_ID1                0x211D
 #define ENCODER_INTERNAL_UNIPHY_ENUM_ID1         0x211E
 */
-#define ENCODER_INTERNAL_LVDS_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_LVDS << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_TMDS1 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_TMDS2 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_DAC1_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_DAC1 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_DAC2_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_DAC2 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_SDVOA_ENUM_ID2 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_SDVOB << OBJECT_ID_SHIFT)
-
-#define ENCODER_SIL170B_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_SI170B << OBJECT_ID_SHIFT)
-
-#define ENCODER_CH7303_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_CH7303 << OBJECT_ID_SHIFT)
-
-#define ENCODER_CH7301_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_CH7301 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_DVO1_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_DVO1 << OBJECT_ID_SHIFT)
-
-#define ENCODER_EXTERNAL_SDVOA_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT)
-
-#define ENCODER_EXTERNAL_SDVOA_ENUM_ID2 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT)
-
-#define ENCODER_EXTERNAL_SDVOB_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_EXTERNAL_SDVOB << OBJECT_ID_SHIFT)
-
-#define ENCODER_TITFP513_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_TITFP513 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_LVTM1_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_LVTM1 << OBJECT_ID_SHIFT)
-
-#define ENCODER_VT1623_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_VT1623 << OBJECT_ID_SHIFT)
-
-#define ENCODER_HDMI_SI1930_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_HDMI_SI1930 << OBJECT_ID_SHIFT)
-
-#define ENCODER_HDMI_INTERNAL_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_HDMI_INTERNAL << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID2 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 << OBJECT_ID_SHIFT) /* Shared with CV/TV and CRT */
-
-#define ENCODER_SI178_ENUM_ID1  \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT)
-
-#define ENCODER_MVPU_FPGA_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_MVPU_FPGA << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_DDI_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT)
-
-#define ENCODER_VT1625_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_VT1625 << OBJECT_ID_SHIFT)
-
-#define ENCODER_HDMI_SI1932_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_HDMI_SI1932 << OBJECT_ID_SHIFT)
-
-#define ENCODER_DP_DP501_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_DP_DP501 << OBJECT_ID_SHIFT)
-
-#define ENCODER_DP_AN9801_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_DP_AN9801 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_UNIPHY_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_UNIPHY_ENUM_ID2 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_KLDSCP_LVTMA_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID2 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_UNIPHY2_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_UNIPHY2_ENUM_ID2 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT)
-
-#define ENCODER_GENERAL_EXTERNAL_DVO_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO << OBJECT_ID_SHIFT)
+#define ENCODER_INTERNAL_LVDS_ENUM_ID1     ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_INTERNAL_LVDS << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_TMDS1_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_INTERNAL_TMDS1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_TMDS2_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_INTERNAL_TMDS2 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_DAC1_ENUM_ID1     ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_INTERNAL_DAC1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_DAC2_ENUM_ID1     ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_INTERNAL_DAC2 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_SDVOA_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_SDVOA_ENUM_ID2    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_SDVOB_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_INTERNAL_SDVOB << OBJECT_ID_SHIFT)
+
+#define ENCODER_SIL170B_ENUM_ID1           ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_SI170B << OBJECT_ID_SHIFT)
+
+#define ENCODER_CH7303_ENUM_ID1            ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_CH7303 << OBJECT_ID_SHIFT)
+
+#define ENCODER_CH7301_ENUM_ID1            ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_CH7301 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_DVO1_ENUM_ID1     ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_INTERNAL_DVO1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_EXTERNAL_SDVOA_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT)
+
+#define ENCODER_EXTERNAL_SDVOA_ENUM_ID2    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT)
+
+
+#define ENCODER_EXTERNAL_SDVOB_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_EXTERNAL_SDVOB << OBJECT_ID_SHIFT)
+
+
+#define ENCODER_TITFP513_ENUM_ID1          ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_TITFP513 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_LVTM1_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_INTERNAL_LVTM1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_VT1623_ENUM_ID1            ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_VT1623 << OBJECT_ID_SHIFT)
+
+#define ENCODER_HDMI_SI1930_ENUM_ID1       ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_HDMI_SI1930 << OBJECT_ID_SHIFT)
+
+#define ENCODER_HDMI_INTERNAL_ENUM_ID1     ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_HDMI_INTERNAL << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1   ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                   GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                   ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT)
+
+
+#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID2   ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                   GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                   ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT)
+
+
+#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                   GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                   ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                   GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                   ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                   GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                   ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 << OBJECT_ID_SHIFT)  // Shared with CV/TV and CRT
+
+#define ENCODER_SI178_ENUM_ID1                    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                   GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                   ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT)  
+
+#define ENCODER_MVPU_FPGA_ENUM_ID1                ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                   GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                   ENCODER_OBJECT_ID_MVPU_FPGA << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_DDI_ENUM_ID1     (  GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT) 
+
+#define ENCODER_VT1625_ENUM_ID1            ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_VT1625 << OBJECT_ID_SHIFT)
+
+#define ENCODER_HDMI_SI1932_ENUM_ID1       ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_HDMI_SI1932 << OBJECT_ID_SHIFT)
+
+#define ENCODER_DP_DP501_ENUM_ID1            ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_DP_DP501 << OBJECT_ID_SHIFT)
+
+#define ENCODER_DP_AN9801_ENUM_ID1            ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_DP_AN9801 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_UNIPHY_ENUM_ID1         ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_UNIPHY_ENUM_ID2         ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_KLDSCP_LVTMA_ENUM_ID1   ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT)  
+
+#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID1         ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID2         ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_UNIPHY2_ENUM_ID1         ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_UNIPHY2_ENUM_ID2         ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT)
+
+#define ENCODER_GENERAL_EXTERNAL_DVO_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                  GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                  ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO << OBJECT_ID_SHIFT)
 
 /****************************************************/
 /* Connector Object ID definition - Shared with BIOS */
@@ -406,167 +381,253 @@
 #define CONNECTOR_7PIN_DIN_ENUM_ID1                 0x310F
 #define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1           0x3110
 */
-#define CONNECTOR_LVDS_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_LVDS << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID2 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID2 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID2 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_VGA_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_VGA_ENUM_ID2 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_COMPOSITE_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_COMPOSITE << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_SVIDEO_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_SVIDEO << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_YPbPr_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_YPbPr << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_D_CONNECTOR_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_D_CONNECTOR << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_9PIN_DIN_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_9PIN_DIN << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_SCART_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_SCART << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_HDMI_TYPE_B << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_7PIN_DIN_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID2 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_CROSSFIRE_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_CROSSFIRE_ENUM_ID2 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_HARDCODE_DVI_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_HARDCODE_DVI_ENUM_ID2 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_DISPLAYPORT_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_DISPLAYPORT_ENUM_ID2 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_DISPLAYPORT_ENUM_ID3 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_DISPLAYPORT_ENUM_ID4 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
+#define CONNECTOR_LVDS_ENUM_ID1                ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_LVDS << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_LVDS_ENUM_ID2                ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_LVDS << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_eDP_ENUM_ID1                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_eDP << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_eDP_ENUM_ID2                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_eDP << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1   ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID2   ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1     ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID2     ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1   ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID2   ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1     ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID2     ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID3     ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_VGA_ENUM_ID1                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_VGA_ENUM_ID2                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_COMPOSITE_ENUM_ID1           ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_COMPOSITE << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_COMPOSITE_ENUM_ID2           ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_COMPOSITE << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SVIDEO_ENUM_ID1              ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_SVIDEO << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SVIDEO_ENUM_ID2              ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_SVIDEO << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_YPbPr_ENUM_ID1               ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_YPbPr << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_YPbPr_ENUM_ID2               ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_YPbPr << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_D_CONNECTOR_ENUM_ID1         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_D_CONNECTOR << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_D_CONNECTOR_ENUM_ID2         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_D_CONNECTOR << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_9PIN_DIN_ENUM_ID1            ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_9PIN_DIN << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_9PIN_DIN_ENUM_ID2            ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_9PIN_DIN << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SCART_ENUM_ID1               ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_SCART << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SCART_ENUM_ID2               ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_SCART << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_HDMI_TYPE_A_ENUM_ID2         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_HDMI_TYPE_A_ENUM_ID3         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_HDMI_TYPE_B << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_HDMI_TYPE_B_ENUM_ID2         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_HDMI_TYPE_B << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_7PIN_DIN_ENUM_ID1            ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT)
+#define CONNECTOR_7PIN_DIN_ENUM_ID2            ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1      ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID2      ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_CROSSFIRE_ENUM_ID1           ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_CROSSFIRE_ENUM_ID2           ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT)
+
+
+#define CONNECTOR_HARDCODE_DVI_ENUM_ID1        ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_HARDCODE_DVI_ENUM_ID2        ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DISPLAYPORT_ENUM_ID1         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DISPLAYPORT_ENUM_ID2         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DISPLAYPORT_ENUM_ID3         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DISPLAYPORT_ENUM_ID4         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DISPLAYPORT_ENUM_ID5         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID5 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DISPLAYPORT_ENUM_ID6         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID6 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_MXM_ENUM_ID1                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT)          //Mapping to MXM_DP_A
+
+#define CONNECTOR_MXM_ENUM_ID2                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT)          //Mapping to MXM_DP_B
+
+#define CONNECTOR_MXM_ENUM_ID3                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT)          //Mapping to MXM_DP_C
+
+#define CONNECTOR_MXM_ENUM_ID4                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT)          //Mapping to MXM_DP_D
+
+#define CONNECTOR_MXM_ENUM_ID5                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID5 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT)          //Mapping to MXM_LVDS_TXxx
+
+#define CONNECTOR_MXM_ENUM_ID6                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID6 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT)          //Mapping to MXM_LVDS_UXxx
+
+#define CONNECTOR_MXM_ENUM_ID7                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID7 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT)          //Mapping to MXM_DAC
 
 /****************************************************/
 /* Router Object ID definition - Shared with BIOS   */
 /****************************************************/
-#define ROUTER_I2C_EXTENDER_CNTL_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ROUTER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL << OBJECT_ID_SHIFT)
+#define ROUTER_I2C_EXTENDER_CNTL_ENUM_ID1      ( GRAPH_OBJECT_TYPE_ROUTER << OBJECT_TYPE_SHIFT |\
+                                                GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL << OBJECT_ID_SHIFT)
 
 /* deleted */
 
 /****************************************************/
+/* Generic Object ID definition - Shared with BIOS  */
+/****************************************************/
+#define GENERICOBJECT_GLSYNC_ENUM_ID1           (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 GENERIC_OBJECT_ID_GLSYNC << OBJECT_ID_SHIFT)
+
+#define GENERICOBJECT_PX2_NON_DRIVABLE_ID1       (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 GENERIC_OBJECT_ID_PX2_NON_DRIVABLE<< OBJECT_ID_SHIFT)
+
+#define GENERICOBJECT_PX2_NON_DRIVABLE_ID2       (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 GENERIC_OBJECT_ID_PX2_NON_DRIVABLE<< OBJECT_ID_SHIFT)
+
+#define GENERICOBJECT_MXM_OPM_ENUM_ID1           (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 GENERIC_OBJECT_ID_MXM_OPM << OBJECT_ID_SHIFT)
+
+/****************************************************/
 /* Object Cap definition - Shared with BIOS         */
 /****************************************************/
 #define GRAPHICS_OBJECT_CAP_I2C                 0x00000001L
 #define GRAPHICS_OBJECT_CAP_TABLE_ID            0x00000002L
 
+
 #define GRAPHICS_OBJECT_I2CCOMMAND_TABLE_ID                   0x01
 #define GRAPHICS_OBJECT_HOTPLUGDETECTIONINTERUPT_TABLE_ID     0x02
 #define GRAPHICS_OBJECT_ENCODER_OUTPUT_PROTECTION_TABLE_ID    0x03
@@ -575,4 +636,8 @@
 #pragma pack()
 #endif
 
-#endif /*GRAPHICTYPE */
+#endif  /*GRAPHICTYPE */
+
+
+
+
diff --git a/drivers/gpu/drm/radeon/atom.c b/drivers/gpu/drm/radeon/atom.c
index 6578d19dff93..388140a7e651 100644
--- a/drivers/gpu/drm/radeon/atom.c
+++ b/drivers/gpu/drm/radeon/atom.c
@@ -58,6 +58,7 @@ typedef struct {
 } atom_exec_context;
 
 int atom_debug = 0;
+static void atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params);
 void atom_execute_table(struct atom_context *ctx, int index, uint32_t * params);
 
 static uint32_t atom_arg_mask[8] =
@@ -573,7 +574,7 @@ static void atom_op_calltable(atom_exec_context *ctx, int *ptr, int arg)
         else
                 SDEBUG("   table: %d\n", idx);
         if (U16(ctx->ctx->cmd_table + 4 + 2 * idx))
-                atom_execute_table(ctx->ctx, idx, ctx->ps + ctx->ps_shift);
+                atom_execute_table_locked(ctx->ctx, idx, ctx->ps + ctx->ps_shift);
 }
 
 static void atom_op_clear(atom_exec_context *ctx, int *ptr, int arg)
@@ -1040,7 +1041,7 @@ static struct {
         atom_op_shr, ATOM_ARG_MC}, {
 atom_op_debug, 0},};
 
-void atom_execute_table(struct atom_context *ctx, int index, uint32_t * params)
+static void atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params)
 {
         int base = CU16(ctx->cmd_table + 4 + 2 * index);
         int len, ws, ps, ptr;
@@ -1092,6 +1093,13 @@ void atom_execute_table(struct atom_context *ctx, int index, uint32_t * params)
                 kfree(ectx.ws);
 }
 
+void atom_execute_table(struct atom_context *ctx, int index, uint32_t * params)
+{
+        mutex_lock(&ctx->mutex);
+        atom_execute_table_locked(ctx, index, params);
+        mutex_unlock(&ctx->mutex);
+}
+
 static int atom_iio_len[] = { 1, 2, 3, 3, 3, 3, 4, 4, 4, 3 };
 
 static void atom_index_iio(struct atom_context *ctx, int base)
diff --git a/drivers/gpu/drm/radeon/atom.h b/drivers/gpu/drm/radeon/atom.h
index 6671848e5ea1..47fd943f6d14 100644
--- a/drivers/gpu/drm/radeon/atom.h
+++ b/drivers/gpu/drm/radeon/atom.h
@@ -120,6 +120,7 @@ struct card_info {
 
 struct atom_context {
         struct card_info *card;
+        struct mutex mutex;
         void *bios;
         uint32_t cmd_table, data_table;
         uint16_t *iio;
diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h
index 5f48515c77a7..91ad0d1c1b17 100644
--- a/drivers/gpu/drm/radeon/atombios.h
+++ b/drivers/gpu/drm/radeon/atombios.h
@@ -4690,6 +4690,205 @@ typedef struct _ATOM_POWERPLAY_INFO_V3 {
         ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
 } ATOM_POWERPLAY_INFO_V3;
 
+/* New PPlib */
+/**************************************************************************/
+typedef struct _ATOM_PPLIB_THERMALCONTROLLER
+
+{
+    UCHAR ucType;           // one of ATOM_PP_THERMALCONTROLLER_*
+    UCHAR ucI2cLine;        // as interpreted by DAL I2C
+    UCHAR ucI2cAddress;
+    UCHAR ucFanParameters;  // Fan Control Parameters.
+    UCHAR ucFanMinRPM;      // Fan Minimum RPM (hundreds) -- for display purposes only.
+    UCHAR ucFanMaxRPM;      // Fan Maximum RPM (hundreds) -- for display purposes only.
+    UCHAR ucReserved;       // ----
+    UCHAR ucFlags;          // to be defined
+} ATOM_PPLIB_THERMALCONTROLLER;
+
+#define ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK 0x0f
+#define ATOM_PP_FANPARAMETERS_NOFAN                                 0x80    // No fan is connected to this controller.
+
+#define ATOM_PP_THERMALCONTROLLER_NONE      0
+#define ATOM_PP_THERMALCONTROLLER_LM63      1  // Not used by PPLib
+#define ATOM_PP_THERMALCONTROLLER_ADM1032   2  // Not used by PPLib
+#define ATOM_PP_THERMALCONTROLLER_ADM1030   3  // Not used by PPLib
+#define ATOM_PP_THERMALCONTROLLER_MUA6649   4  // Not used by PPLib
+#define ATOM_PP_THERMALCONTROLLER_LM64      5
+#define ATOM_PP_THERMALCONTROLLER_F75375    6  // Not used by PPLib
+#define ATOM_PP_THERMALCONTROLLER_RV6xx     7
+#define ATOM_PP_THERMALCONTROLLER_RV770     8
+#define ATOM_PP_THERMALCONTROLLER_ADT7473   9
+
+typedef struct _ATOM_PPLIB_STATE
+{
+    UCHAR ucNonClockStateIndex;
+    UCHAR ucClockStateIndices[1]; // variable-sized
+} ATOM_PPLIB_STATE;
+
+//// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps
+#define ATOM_PP_PLATFORM_CAP_BACKBIAS 1
+#define ATOM_PP_PLATFORM_CAP_POWERPLAY 2
+#define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 4
+#define ATOM_PP_PLATFORM_CAP_ASPM_L0s 8
+#define ATOM_PP_PLATFORM_CAP_ASPM_L1 16
+#define ATOM_PP_PLATFORM_CAP_HARDWAREDC 32
+#define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY 64
+#define ATOM_PP_PLATFORM_CAP_STEPVDDC 128
+#define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL 256
+#define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512
+#define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024
+#define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048
+
+typedef struct _ATOM_PPLIB_POWERPLAYTABLE
+{
+      ATOM_COMMON_TABLE_HEADER sHeader;
+
+      UCHAR ucDataRevision;
+
+      UCHAR ucNumStates;
+      UCHAR ucStateEntrySize;
+      UCHAR ucClockInfoSize;
+      UCHAR ucNonClockSize;
+
+      // offset from start of this table to array of ucNumStates ATOM_PPLIB_STATE structures
+      USHORT usStateArrayOffset;
+
+      // offset from start of this table to array of ASIC-specific structures,
+      // currently ATOM_PPLIB_CLOCK_INFO.
+      USHORT usClockInfoArrayOffset;
+
+      // offset from start of this table to array of ATOM_PPLIB_NONCLOCK_INFO
+      USHORT usNonClockInfoArrayOffset;
+
+      USHORT usBackbiasTime;    // in microseconds
+      USHORT usVoltageTime;     // in microseconds
+      USHORT usTableSize;       //the size of this structure, or the extended structure
+
+      ULONG ulPlatformCaps;            // See ATOM_PPLIB_CAPS_*
+
+      ATOM_PPLIB_THERMALCONTROLLER    sThermalController;
+
+      USHORT usBootClockInfoOffset;
+      USHORT usBootNonClockInfoOffset;
+
+} ATOM_PPLIB_POWERPLAYTABLE;
+
+//// ATOM_PPLIB_NONCLOCK_INFO::usClassification
+#define ATOM_PPLIB_CLASSIFICATION_UI_MASK          0x0007
+#define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT         0
+#define ATOM_PPLIB_CLASSIFICATION_UI_NONE          0
+#define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY       1
+#define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED      3
+#define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE   5
+// 2, 4, 6, 7 are reserved
+
+#define ATOM_PPLIB_CLASSIFICATION_BOOT                   0x0008
+#define ATOM_PPLIB_CLASSIFICATION_THERMAL                0x0010
+#define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE     0x0020
+#define ATOM_PPLIB_CLASSIFICATION_REST                   0x0040
+#define ATOM_PPLIB_CLASSIFICATION_FORCED                 0x0080
+#define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE          0x0100
+#define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE      0x0200
+#define ATOM_PPLIB_CLASSIFICATION_UVDSTATE               0x0400
+#define ATOM_PPLIB_CLASSIFICATION_3DLOW                  0x0800
+#define ATOM_PPLIB_CLASSIFICATION_ACPI                   0x1000
+// remaining 3 bits are reserved
+
+//// ATOM_PPLIB_NONCLOCK_INFO::ulCapsAndSettings
+#define ATOM_PPLIB_SINGLE_DISPLAY_ONLY           0x00000001
+#define ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK         0x00000002
+
+// 0 is 2.5Gb/s, 1 is 5Gb/s
+#define ATOM_PPLIB_PCIE_LINK_SPEED_MASK            0x00000004
+#define ATOM_PPLIB_PCIE_LINK_SPEED_SHIFT           2
+
+// lanes - 1: 1, 2, 4, 8, 12, 16 permitted by PCIE spec
+#define ATOM_PPLIB_PCIE_LINK_WIDTH_MASK            0x000000F8
+#define ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT           3
+
+// lookup into reduced refresh-rate table
+#define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK  0x00000F00
+#define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT 8
+
+#define ATOM_PPLIB_LIMITED_REFRESHRATE_UNLIMITED    0
+#define ATOM_PPLIB_LIMITED_REFRESHRATE_50HZ         1
+// 2-15 TBD as needed.
+
+#define ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING        0x00001000
+#define ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS  0x00002000
+#define ATOM_PPLIB_ENABLE_VARIBRIGHT                     0x00008000
+
+#define ATOM_PPLIB_DISALLOW_ON_DC                       0x00004000
+
+// Contained in an array starting at the offset
+// in ATOM_PPLIB_POWERPLAYTABLE::usNonClockInfoArrayOffset.
+// referenced from ATOM_PPLIB_STATE_INFO::ucNonClockStateIndex
+typedef struct _ATOM_PPLIB_NONCLOCK_INFO
+{
+      USHORT usClassification;
+      UCHAR  ucMinTemperature;
+      UCHAR  ucMaxTemperature;
+      ULONG  ulCapsAndSettings;
+      UCHAR  ucRequiredPower;
+      UCHAR  ucUnused1[3];
+} ATOM_PPLIB_NONCLOCK_INFO;
+
+// Contained in an array starting at the offset
+// in ATOM_PPLIB_POWERPLAYTABLE::usClockInfoArrayOffset.
+// referenced from ATOM_PPLIB_STATE::ucClockStateIndices
+typedef struct _ATOM_PPLIB_R600_CLOCK_INFO
+{
+      USHORT usEngineClockLow;
+      UCHAR ucEngineClockHigh;
+
+      USHORT usMemoryClockLow;
+      UCHAR ucMemoryClockHigh;
+
+      USHORT usVDDC;
+      USHORT usUnused1;
+      USHORT usUnused2;
+
+      ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_*
+
+} ATOM_PPLIB_R600_CLOCK_INFO;
+
+// ulFlags in ATOM_PPLIB_R600_CLOCK_INFO
+#define ATOM_PPLIB_R600_FLAGS_PCIEGEN2          1
+#define ATOM_PPLIB_R600_FLAGS_UVDSAFE           2
+#define ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE    4
+#define ATOM_PPLIB_R600_FLAGS_MEMORY_ODT_OFF    8
+#define ATOM_PPLIB_R600_FLAGS_MEMORY_DLL_OFF    16
+
+typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO
+
+{
+      USHORT usLowEngineClockLow;         // Low Engine clock in MHz (the same way as on the R600).
+      UCHAR  ucLowEngineClockHigh;
+      USHORT usHighEngineClockLow;        // High Engine clock in MHz.
+      UCHAR  ucHighEngineClockHigh;
+      USHORT usMemoryClockLow;            // For now one of the ATOM_PPLIB_RS780_SPMCLK_XXXX constants.
+      UCHAR  ucMemoryClockHigh;           // Currentyl unused.
+      UCHAR  ucPadding;                   // For proper alignment and size.
+      USHORT usVDDC;                      // For the 780, use: None, Low, High, Variable
+      UCHAR  ucMaxHTLinkWidth;            // From SBIOS - {2, 4, 8, 16}
+      UCHAR  ucMinHTLinkWidth;            // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could be bigger as display BW requriement.
+      USHORT usHTLinkFreq;                // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200).
+      ULONG  ulFlags;
+} ATOM_PPLIB_RS780_CLOCK_INFO;
+
+#define ATOM_PPLIB_RS780_VOLTAGE_NONE       0
+#define ATOM_PPLIB_RS780_VOLTAGE_LOW        1
+#define ATOM_PPLIB_RS780_VOLTAGE_HIGH       2
+#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE   3
+
+#define ATOM_PPLIB_RS780_SPMCLK_NONE        0   // We cannot change the side port memory clock, leave it as it is.
+#define ATOM_PPLIB_RS780_SPMCLK_LOW         1
+#define ATOM_PPLIB_RS780_SPMCLK_HIGH        2
+
+#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE       0
+#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW        1
+#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH       2
+
 /**************************************************************************/
 
 /*  Following definitions are for compatiblity issue in different SW components. */
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index 0d63c4436e7c..3eb0ca5b3d73 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -468,7 +468,8 @@ void radeon_dp_set_link_config(struct drm_connector *connector,
         struct radeon_connector *radeon_connector;
         struct radeon_connector_atom_dig *dig_connector;
 
-        if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
+        if ((connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) ||
+            (connector->connector_type != DRM_MODE_CONNECTOR_eDP))
                 return;
 
         radeon_connector = to_radeon_connector(connector);
@@ -582,7 +583,8 @@ void dp_link_train(struct drm_encoder *encoder,
         u8 train_set[4];
         int i;
 
-        if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
+        if ((connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) ||
+            (connector->connector_type != DRM_MODE_CONNECTOR_eDP))
                 return;
 
         if (!radeon_encoder->enc_priv)
diff --git a/drivers/gpu/drm/radeon/mkregtable.c b/drivers/gpu/drm/radeon/mkregtable.c
index 0d79577c1576..607241c6a8a9 100644
--- a/drivers/gpu/drm/radeon/mkregtable.c
+++ b/drivers/gpu/drm/radeon/mkregtable.c
@@ -661,8 +661,10 @@ static int parser_auth(struct table *t, const char *filename)
         fseek(file, 0, SEEK_SET);
 
         /* get header */
-        if (fgets(buf, 1024, file) == NULL)
+        if (fgets(buf, 1024, file) == NULL) {
+                fclose(file);
                 return -1;
+        }
 
         /* first line will contain the last register
          * and gpu name */
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 84e5df766d3f..8760d66e058a 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -131,7 +131,8 @@ void r100_hpd_init(struct radeon_device *rdev)
                         break;
                 }
         }
-        r100_irq_set(rdev);
+        if (rdev->irq.installed)
+                r100_irq_set(rdev);
 }
 
 void r100_hpd_fini(struct radeon_device *rdev)
@@ -243,6 +244,11 @@ int r100_irq_set(struct radeon_device *rdev)
 {
         uint32_t tmp = 0;
 
+        if (!rdev->irq.installed) {
+                WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
+                WREG32(R_000040_GEN_INT_CNTL, 0);
+                return -EINVAL;
+        }
         if (rdev->irq.sw_int) {
                 tmp |= RADEON_SW_INT_ENABLE;
         }
@@ -356,6 +362,11 @@ void r100_fence_ring_emit(struct radeon_device *rdev,
         /* Wait until IDLE & CLEAN */
         radeon_ring_write(rdev, PACKET0(0x1720, 0));
         radeon_ring_write(rdev, (1 << 16) | (1 << 17));
+        radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
+        radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
+                                RADEON_HDP_READ_BUFFER_INVALIDATE);
+        radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
+        radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
         /* Emit fence sequence & fire IRQ */
         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
         radeon_ring_write(rdev, fence->seq);
@@ -1713,14 +1724,6 @@ void r100_gpu_init(struct radeon_device *rdev)
         r100_hdp_reset(rdev);
 }
 
-void r100_hdp_flush(struct radeon_device *rdev)
-{
-        u32 tmp;
-        tmp = RREG32(RADEON_HOST_PATH_CNTL);
-        tmp |= RADEON_HDP_READ_BUFFER_INVALIDATE;
-        WREG32(RADEON_HOST_PATH_CNTL, tmp);
-}
-
 void r100_hdp_reset(struct radeon_device *rdev)
 {
         uint32_t tmp;
@@ -2881,6 +2884,10 @@ int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
 
         for (i = 0; i < track->num_cb; i++) {
                 if (track->cb[i].robj == NULL) {
+                        if (!(track->fastfill || track->color_channel_mask ||
+                              track->blend_read_enable)) {
+                                continue;
+                        }
                         DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
                         return -EINVAL;
                 }
@@ -3309,6 +3316,7 @@ static int r100_startup(struct radeon_device *rdev)
         }
         /* Enable IRQ */
         r100_irq_set(rdev);
+        rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
         /* 1M ring buffer */
         r = r100_cp_init(rdev, 1024 * 1024);
         if (r) {
@@ -3367,6 +3375,7 @@ void r100_fini(struct radeon_device *rdev)
         radeon_gem_fini(rdev);
         if (rdev->flags & RADEON_IS_PCI)
                 r100_pci_gart_fini(rdev);
+        radeon_agp_fini(rdev);
         radeon_irq_kms_fini(rdev);
         radeon_fence_driver_fini(rdev);
         radeon_bo_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/r100_track.h b/drivers/gpu/drm/radeon/r100_track.h
index 7188c3778ee2..b27a6999d219 100644
--- a/drivers/gpu/drm/radeon/r100_track.h
+++ b/drivers/gpu/drm/radeon/r100_track.h
@@ -67,13 +67,15 @@ struct r100_cs_track {
         unsigned                        immd_dwords;
         unsigned                        num_arrays;
         unsigned                        max_indx;
+        unsigned                        color_channel_mask;
         struct r100_cs_track_array      arrays[11];
         struct r100_cs_track_cb         cb[R300_MAX_CB];
         struct r100_cs_track_cb         zb;
         struct r100_cs_track_texture    textures[R300_TRACK_MAX_TEXTURE];
         bool                            z_enabled;
         bool                            separate_cube;
-
+        bool                            fastfill;
+        bool                            blend_read_enable;
 };
 
 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track);
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 83490c2b5061..0051d11b907c 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -36,7 +36,15 @@
 #include "rv350d.h"
 #include "r300_reg_safe.h"
 
-/* This files gather functions specifics to: r300,r350,rv350,rv370,rv380 */
+/* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
+ *
+ * GPU Errata:
+ * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
+ *   using MMIO to flush host path read cache, this lead to HARDLOCKUP.
+ *   However, scheduling such write to the ring seems harmless, i suspect
+ *   the CP read collide with the flush somehow, or maybe the MC, hard to
+ *   tell. (Jerome Glisse)
+ */
 
 /*
  * rv370,rv380 PCIE GART
@@ -178,6 +186,11 @@ void r300_fence_ring_emit(struct radeon_device *rdev,
         /* Wait until IDLE & CLEAN */
         radeon_ring_write(rdev, PACKET0(0x1720, 0));
         radeon_ring_write(rdev, (1 << 17) | (1 << 16)  | (1 << 9));
+        radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
+        radeon_ring_write(rdev, rdev->config.r300.hdp_cntl |
+                                RADEON_HDP_READ_BUFFER_INVALIDATE);
+        radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
+        radeon_ring_write(rdev, rdev->config.r300.hdp_cntl);
         /* Emit fence sequence & fire IRQ */
         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
         radeon_ring_write(rdev, fence->seq);
@@ -887,6 +900,14 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
                         track->textures[i].cpp = 1;
                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
                         break;
+                case R300_TX_FORMAT_ATI2N:
+                        if (p->rdev->family < CHIP_R420) {
+                                DRM_ERROR("Invalid texture format %u\n",
+                                          (idx_value & 0x1F));
+                                return -EINVAL;
+                        }
+                        /* The same rules apply as for DXT3/5. */
+                        /* Pass through. */
                 case R300_TX_FORMAT_DXT3:
                 case R300_TX_FORMAT_DXT5:
                         track->textures[i].cpp = 1;
@@ -951,6 +972,16 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
                         track->textures[i].width_11 = tmp;
                         tmp = ((idx_value >> 16) & 1) << 11;
                         track->textures[i].height_11 = tmp;
+
+                        /* ATI1N */
+                        if (idx_value & (1 << 14)) {
+                                /* The same rules apply as for DXT1. */
+                                track->textures[i].compress_format =
+                                        R100_TRACK_COMP_DXT1;
+                        }
+                } else if (idx_value & (1 << 14)) {
+                        DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
+                        return -EINVAL;
                 }
                 break;
         case 0x4480:
@@ -992,6 +1023,18 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
                 }
                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
                 break;
+        case 0x4e0c:
+                /* RB3D_COLOR_CHANNEL_MASK */
+                track->color_channel_mask = idx_value;
+                break;
+        case 0x4d1c:
+                /* ZB_BW_CNTL */
+                track->fastfill = !!(idx_value & (1 << 2));
+                break;
+        case 0x4e04:
+                /* RB3D_BLENDCNTL */
+                track->blend_read_enable = !!(idx_value & (1 << 2));
+                break;
         case 0x4be8:
                 /* valid register only on RV530 */
                 if (p->rdev->family == CHIP_RV530)
@@ -1228,6 +1271,7 @@ static int r300_startup(struct radeon_device *rdev)
         }
         /* Enable IRQ */
         r100_irq_set(rdev);
+        rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
         /* 1M ring buffer */
         r = r100_cp_init(rdev, 1024 * 1024);
         if (r) {
@@ -1292,6 +1336,7 @@ void r300_fini(struct radeon_device *rdev)
                 rv370_pcie_gart_fini(rdev);
         if (rdev->flags & RADEON_IS_PCI)
                 r100_pci_gart_fini(rdev);
+        radeon_agp_fini(rdev);
         radeon_irq_kms_fini(rdev);
         radeon_fence_driver_fini(rdev);
         radeon_bo_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/r300_cmdbuf.c b/drivers/gpu/drm/radeon/r300_cmdbuf.c
index cb2e470f97d4..34bffa0e4b73 100644
--- a/drivers/gpu/drm/radeon/r300_cmdbuf.c
+++ b/drivers/gpu/drm/radeon/r300_cmdbuf.c
@@ -990,7 +990,7 @@ static inline int r300_emit_r500fp(drm_radeon_private_t *dev_priv,
         int sz;
         int addr;
         int type;
-        int clamp;
+        int isclamp;
         int stride;
         RING_LOCALS;
 
@@ -999,10 +999,10 @@ static inline int r300_emit_r500fp(drm_radeon_private_t *dev_priv,
         addr = ((header.r500fp.adrhi_flags & 1) << 8) | header.r500fp.adrlo;
 
         type = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
-        clamp = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
+        isclamp = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
 
         addr |= (type << 16);
-        addr |= (clamp << 17);
+        addr |= (isclamp << 17);
 
         stride = type ? 4 : 6;
 
diff --git a/drivers/gpu/drm/radeon/r300_reg.h b/drivers/gpu/drm/radeon/r300_reg.h
index 4b7afef35a65..1735a2b69580 100644
--- a/drivers/gpu/drm/radeon/r300_reg.h
+++ b/drivers/gpu/drm/radeon/r300_reg.h
@@ -900,6 +900,7 @@
 #       define R300_TX_FORMAT_FL_I32                0x1B
 #       define R300_TX_FORMAT_FL_I32A32             0x1C
 #       define R300_TX_FORMAT_FL_R32G32B32A32       0x1D
+#       define R300_TX_FORMAT_ATI2N                 0x1F
         /* alpha modes, convenience mostly */
         /* if you have alpha, pick constant appropriate to the
            number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index c05a7270cf0c..053404e71a9d 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -30,7 +30,15 @@
 #include "radeon_reg.h"
 #include "radeon.h"
 #include "atom.h"
+#include "r100d.h"
 #include "r420d.h"
+#include "r420_reg_safe.h"
+
+static void r420_set_reg_safe(struct radeon_device *rdev)
+{
+        rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
+        rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
+}
 
 int r420_mc_init(struct radeon_device *rdev)
 {
@@ -165,6 +173,34 @@ static void r420_clock_resume(struct radeon_device *rdev)
         WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
 }
 
+static void r420_cp_errata_init(struct radeon_device *rdev)
+{
+        /* RV410 and R420 can lock up if CP DMA to host memory happens
+         * while the 2D engine is busy.
+         *
+         * The proper workaround is to queue a RESYNC at the beginning
+         * of the CP init, apparently.
+         */
+        radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
+        radeon_ring_lock(rdev, 8);
+        radeon_ring_write(rdev, PACKET0(R300_CP_RESYNC_ADDR, 1));
+        radeon_ring_write(rdev, rdev->config.r300.resync_scratch);
+        radeon_ring_write(rdev, 0xDEADBEEF);
+        radeon_ring_unlock_commit(rdev);
+}
+
+static void r420_cp_errata_fini(struct radeon_device *rdev)
+{
+        /* Catch the RESYNC we dispatched all the way back,
+         * at the very beginning of the CP init.
+         */
+        radeon_ring_lock(rdev, 8);
+        radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
+        radeon_ring_write(rdev, R300_RB3D_DC_FINISH);
+        radeon_ring_unlock_commit(rdev);
+        radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
+}
+
 static int r420_startup(struct radeon_device *rdev)
 {
         int r;
@@ -190,12 +226,14 @@ static int r420_startup(struct radeon_device *rdev)
         r420_pipes_init(rdev);
         /* Enable IRQ */
         r100_irq_set(rdev);
+        rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
         /* 1M ring buffer */
         r = r100_cp_init(rdev, 1024 * 1024);
         if (r) {
                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
                 return r;
         }
+        r420_cp_errata_init(rdev);
         r = r100_wb_init(rdev);
         if (r) {
                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
@@ -238,6 +276,7 @@ int r420_resume(struct radeon_device *rdev)
 
 int r420_suspend(struct radeon_device *rdev)
 {
+        r420_cp_errata_fini(rdev);
         r100_cp_disable(rdev);
         r100_wb_disable(rdev);
         r100_irq_disable(rdev);
@@ -346,7 +385,7 @@ int r420_init(struct radeon_device *rdev)
                 if (r)
                         return r;
         }
-        r300_set_reg_safe(rdev);
+        r420_set_reg_safe(rdev);
         rdev->accel_working = true;
         r = r420_startup(rdev);
         if (r) {
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c
index 0f3843b6dac7..9a189072f2b9 100644
--- a/drivers/gpu/drm/radeon/r520.c
+++ b/drivers/gpu/drm/radeon/r520.c
@@ -186,6 +186,7 @@ static int r520_startup(struct radeon_device *rdev)
         }
         /* Enable IRQ */
         rs600_irq_set(rdev);
+        rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
         /* 1M ring buffer */
         r = r100_cp_init(rdev, 1024 * 1024);
         if (r) {
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index a0ac3c134b1b..c0651991c3e4 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -285,7 +285,8 @@ void r600_hpd_init(struct radeon_device *rdev)
                         }
                 }
         }
-        r600_irq_set(rdev);
+        if (rdev->irq.installed)
+                r600_irq_set(rdev);
 }
 
 void r600_hpd_fini(struct radeon_device *rdev)
@@ -726,6 +727,10 @@ int r600_mc_init(struct radeon_device *rdev)
         a.full = rfixed_const(100);
         rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
         rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
+
+        if (rdev->flags & RADEON_IS_IGP)
+                rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
+
         return 0;
 }
 
@@ -1384,11 +1389,6 @@ void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
         (void)RREG32(PCIE_PORT_DATA);
 }
 
-void r600_hdp_flush(struct radeon_device *rdev)
-{
-        WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
-}
-
 /*
  * CP & Ring
  */
@@ -1785,6 +1785,8 @@ void r600_fence_ring_emit(struct radeon_device *rdev,
         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
         radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
         radeon_ring_write(rdev, fence->seq);
+        radeon_ring_write(rdev, PACKET0(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
+        radeon_ring_write(rdev, 1);
         /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
         radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
         radeon_ring_write(rdev, RB_INT_STAT);
@@ -2089,8 +2091,7 @@ void r600_fini(struct radeon_device *rdev)
         radeon_gem_fini(rdev);
         radeon_fence_driver_fini(rdev);
         radeon_clocks_fini(rdev);
-        if (rdev->flags & RADEON_IS_AGP)
-                radeon_agp_fini(rdev);
+        radeon_agp_fini(rdev);
         radeon_bo_fini(rdev);
         radeon_atombios_fini(rdev);
         kfree(rdev->bios);
@@ -2461,6 +2462,10 @@ int r600_irq_set(struct radeon_device *rdev)
         u32 mode_int = 0;
         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
 
+        if (!rdev->irq.installed) {
+                WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
+                return -EINVAL;
+        }
         /* don't enable anything if the ih is disabled */
         if (!rdev->ih.enabled)
                 return 0;
diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c
index 9aecafb51b66..8787ea89dc6e 100644
--- a/drivers/gpu/drm/radeon/r600_blit_kms.c
+++ b/drivers/gpu/drm/radeon/r600_blit_kms.c
@@ -577,9 +577,9 @@ int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
         ring_size = num_loops * dwords_per_loop;
         /* set default  + shaders */
         ring_size += 40; /* shaders + def state */
-        ring_size += 5; /* fence emit for VB IB */
+        ring_size += 7; /* fence emit for VB IB */
         ring_size += 5; /* done copy */
-        ring_size += 5; /* fence emit for done copy */
+        ring_size += 7; /* fence emit for done copy */
         r = radeon_ring_lock(rdev, ring_size);
         WARN_ON(r);
 
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 0d820764f340..44060b92d9e6 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -170,7 +170,7 @@ static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
                           idx, relocs_chunk->length_dw);
                 return -EINVAL;
         }
-        *cs_reloc = &p->relocs[0];
+        *cs_reloc = p->relocs;
         (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
         (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
         return 0;
@@ -717,7 +717,7 @@ static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
         if (p->chunk_relocs_idx == -1) {
                 return 0;
         }
-        p->relocs = kcalloc(1, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
+        p->relocs = kzalloc(sizeof(struct radeon_cs_reloc), GFP_KERNEL);
         if (p->relocs == NULL) {
                 return -ENOMEM;
         }
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index cd650fd3964e..eb5f99b9469d 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -162,6 +162,7 @@ struct radeon_fence_driver {
         struct list_head                created;
         struct list_head                emited;
         struct list_head                signaled;
+        bool                            initialized;
 };
 
 struct radeon_fence {
@@ -202,8 +203,9 @@ struct radeon_surface_reg {
 struct radeon_mman {
         struct ttm_bo_global_ref        bo_global_ref;
         struct ttm_global_reference     mem_global_ref;
-        bool                            mem_global_referenced;
         struct ttm_bo_device            bdev;
+        bool                            mem_global_referenced;
+        bool                            initialized;
 };
 
 struct radeon_bo {
@@ -317,10 +319,12 @@ struct radeon_mc {
         u64                     real_vram_size;
         int                     vram_mtrr;
         bool                    vram_is_ddr;
+        bool                    igp_sideport_enabled;
 };
 
 int radeon_mc_setup(struct radeon_device *rdev);
-
+bool radeon_combios_sideport_present(struct radeon_device *rdev);
+bool radeon_atombios_sideport_present(struct radeon_device *rdev);
 
 /*
  * GPU scratch registers structures, functions & helpers
@@ -652,7 +656,6 @@ struct radeon_asic {
                                uint32_t offset, uint32_t obj_size);
         int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
         void (*bandwidth_update)(struct radeon_device *rdev);
-        void (*hdp_flush)(struct radeon_device *rdev);
         void (*hpd_init)(struct radeon_device *rdev);
         void (*hpd_fini)(struct radeon_device *rdev);
         bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
@@ -665,11 +668,14 @@ struct radeon_asic {
 struct r100_asic {
         const unsigned  *reg_safe_bm;
         unsigned        reg_safe_bm_size;
+        u32             hdp_cntl;
 };
 
 struct r300_asic {
         const unsigned  *reg_safe_bm;
         unsigned        reg_safe_bm_size;
+        u32             resync_scratch;
+        u32             hdp_cntl;
 };
 
 struct r600_asic {
@@ -1005,7 +1011,6 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
-#define radeon_hdp_flush(rdev) (rdev)->asic->hdp_flush((rdev))
 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
diff --git a/drivers/gpu/drm/radeon/radeon_agp.c b/drivers/gpu/drm/radeon/radeon_agp.c
index 54bf49a6d676..220f454ea9fa 100644
--- a/drivers/gpu/drm/radeon/radeon_agp.c
+++ b/drivers/gpu/drm/radeon/radeon_agp.c
@@ -252,10 +252,8 @@ void radeon_agp_resume(struct radeon_device *rdev)
 void radeon_agp_fini(struct radeon_device *rdev)
 {
 #if __OS_HAS_AGP
-        if (rdev->flags & RADEON_IS_AGP) {
-                if (rdev->ddev->agp && rdev->ddev->agp->acquired) {
-                        drm_agp_release(rdev->ddev);
-                }
+        if (rdev->ddev->agp && rdev->ddev->agp->acquired) {
+                drm_agp_release(rdev->ddev);
         }
 #endif
 }
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 636116bedcb4..f2fbd2e4e9df 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -33,6 +33,7 @@
  */
 uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
 void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
+uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
 
 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
@@ -76,7 +77,6 @@ int r100_clear_surface_reg(struct radeon_device *rdev, int reg);
 void r100_bandwidth_update(struct radeon_device *rdev);
 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 int r100_ring_test(struct radeon_device *rdev);
-void r100_hdp_flush(struct radeon_device *rdev);
 void r100_hpd_init(struct radeon_device *rdev);
 void r100_hpd_fini(struct radeon_device *rdev);
 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
@@ -106,14 +106,13 @@ static struct radeon_asic r100_asic = {
         .copy = &r100_copy_blit,
         .get_engine_clock = &radeon_legacy_get_engine_clock,
         .set_engine_clock = &radeon_legacy_set_engine_clock,
-        .get_memory_clock = NULL,
+        .get_memory_clock = &radeon_legacy_get_memory_clock,
         .set_memory_clock = NULL,
         .set_pcie_lanes = NULL,
         .set_clock_gating = &radeon_legacy_set_clock_gating,
         .set_surface_reg = r100_set_surface_reg,
         .clear_surface_reg = r100_clear_surface_reg,
         .bandwidth_update = &r100_bandwidth_update,
-        .hdp_flush = &r100_hdp_flush,
         .hpd_init = &r100_hpd_init,
         .hpd_fini = &r100_hpd_fini,
         .hpd_sense = &r100_hpd_sense,
@@ -166,14 +165,13 @@ static struct radeon_asic r300_asic = {
         .copy = &r100_copy_blit,
         .get_engine_clock = &radeon_legacy_get_engine_clock,
         .set_engine_clock = &radeon_legacy_set_engine_clock,
-        .get_memory_clock = NULL,
+        .get_memory_clock = &radeon_legacy_get_memory_clock,
         .set_memory_clock = NULL,
         .set_pcie_lanes = &rv370_set_pcie_lanes,
         .set_clock_gating = &radeon_legacy_set_clock_gating,
         .set_surface_reg = r100_set_surface_reg,
         .clear_surface_reg = r100_clear_surface_reg,
         .bandwidth_update = &r100_bandwidth_update,
-        .hdp_flush = &r100_hdp_flush,
         .hpd_init = &r100_hpd_init,
         .hpd_fini = &r100_hpd_fini,
         .hpd_sense = &r100_hpd_sense,
@@ -217,7 +215,6 @@ static struct radeon_asic r420_asic = {
         .set_surface_reg = r100_set_surface_reg,
         .clear_surface_reg = r100_clear_surface_reg,
         .bandwidth_update = &r100_bandwidth_update,
-        .hdp_flush = &r100_hdp_flush,
         .hpd_init = &r100_hpd_init,
         .hpd_fini = &r100_hpd_fini,
         .hpd_sense = &r100_hpd_sense,
@@ -259,14 +256,13 @@ static struct radeon_asic rs400_asic = {
         .copy = &r100_copy_blit,
         .get_engine_clock = &radeon_legacy_get_engine_clock,
         .set_engine_clock = &radeon_legacy_set_engine_clock,
-        .get_memory_clock = NULL,
+        .get_memory_clock = &radeon_legacy_get_memory_clock,
         .set_memory_clock = NULL,
         .set_pcie_lanes = NULL,
         .set_clock_gating = &radeon_legacy_set_clock_gating,
         .set_surface_reg = r100_set_surface_reg,
         .clear_surface_reg = r100_clear_surface_reg,
         .bandwidth_update = &r100_bandwidth_update,
-        .hdp_flush = &r100_hdp_flush,
         .hpd_init = &r100_hpd_init,
         .hpd_fini = &r100_hpd_fini,
         .hpd_sense = &r100_hpd_sense,
@@ -323,7 +319,6 @@ static struct radeon_asic rs600_asic = {
         .set_pcie_lanes = NULL,
         .set_clock_gating = &radeon_atom_set_clock_gating,
         .bandwidth_update = &rs600_bandwidth_update,
-        .hdp_flush = &r100_hdp_flush,
         .hpd_init = &rs600_hpd_init,
         .hpd_fini = &rs600_hpd_fini,
         .hpd_sense = &rs600_hpd_sense,
@@ -371,7 +366,6 @@ static struct radeon_asic rs690_asic = {
         .set_surface_reg = r100_set_surface_reg,
         .clear_surface_reg = r100_clear_surface_reg,
         .bandwidth_update = &rs690_bandwidth_update,
-        .hdp_flush = &r100_hdp_flush,
         .hpd_init = &rs600_hpd_init,
         .hpd_fini = &rs600_hpd_fini,
         .hpd_sense = &rs600_hpd_sense,
@@ -423,7 +417,6 @@ static struct radeon_asic rv515_asic = {
         .set_surface_reg = r100_set_surface_reg,
         .clear_surface_reg = r100_clear_surface_reg,
         .bandwidth_update = &rv515_bandwidth_update,
-        .hdp_flush = &r100_hdp_flush,
         .hpd_init = &rs600_hpd_init,
         .hpd_fini = &rs600_hpd_fini,
         .hpd_sense = &rs600_hpd_sense,
@@ -466,7 +459,6 @@ static struct radeon_asic r520_asic = {
         .set_surface_reg = r100_set_surface_reg,
         .clear_surface_reg = r100_clear_surface_reg,
         .bandwidth_update = &rv515_bandwidth_update,
-        .hdp_flush = &r100_hdp_flush,
         .hpd_init = &rs600_hpd_init,
         .hpd_fini = &rs600_hpd_fini,
         .hpd_sense = &rs600_hpd_sense,
@@ -507,7 +499,6 @@ int r600_ring_test(struct radeon_device *rdev);
 int r600_copy_blit(struct radeon_device *rdev,
                    uint64_t src_offset, uint64_t dst_offset,
                    unsigned num_pages, struct radeon_fence *fence);
-void r600_hdp_flush(struct radeon_device *rdev);
 void r600_hpd_init(struct radeon_device *rdev);
 void r600_hpd_fini(struct radeon_device *rdev);
 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
@@ -543,7 +534,6 @@ static struct radeon_asic r600_asic = {
         .set_surface_reg = r600_set_surface_reg,
         .clear_surface_reg = r600_clear_surface_reg,
         .bandwidth_update = &rv515_bandwidth_update,
-        .hdp_flush = &r600_hdp_flush,
         .hpd_init = &r600_hpd_init,
         .hpd_fini = &r600_hpd_fini,
         .hpd_sense = &r600_hpd_sense,
@@ -588,7 +578,6 @@ static struct radeon_asic rv770_asic = {
         .set_surface_reg = r600_set_surface_reg,
         .clear_surface_reg = r600_clear_surface_reg,
         .bandwidth_update = &rv515_bandwidth_update,
-        .hdp_flush = &r600_hdp_flush,
         .hpd_init = &r600_hpd_init,
         .hpd_fini = &r600_hpd_fini,
         .hpd_sense = &r600_hpd_sense,
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 12a0c760e7ff..fa82ca74324e 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -114,6 +114,7 @@ static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_dev
                         i2c.i2c_id = gpio->sucI2cId.ucAccess;
 
                         i2c.valid = true;
+                        break;
                 }
         }
 
@@ -345,7 +346,9 @@ const int object_connector_convert[] = {
         DRM_MODE_CONNECTOR_Unknown,
         DRM_MODE_CONNECTOR_Unknown,
         DRM_MODE_CONNECTOR_Unknown,
-        DRM_MODE_CONNECTOR_DisplayPort
+        DRM_MODE_CONNECTOR_DisplayPort,
+        DRM_MODE_CONNECTOR_eDP,
+        DRM_MODE_CONNECTOR_Unknown
 };
 
 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
@@ -745,8 +748,7 @@ bool radeon_get_atom_connector_info_from_supported_devices_table(struct
                 else
                         radeon_add_legacy_encoder(dev,
                                                   radeon_get_encoder_id(dev,
-                                                                        (1 <<
-                                                                         i),
+                                                                        (1 << i),
                                                                         dac),
                                                   (1 << i));
         }
@@ -758,32 +760,30 @@ bool radeon_get_atom_connector_info_from_supported_devices_table(struct
                                 if (bios_connectors[j].valid && (i != j)) {
                                         if (bios_connectors[i].line_mux ==
                                             bios_connectors[j].line_mux) {
-                                                if (((bios_connectors[i].
-                                                      devices &
-                                                      (ATOM_DEVICE_DFP_SUPPORT))
-                                                     && (bios_connectors[j].
-                                                         devices &
-                                                         (ATOM_DEVICE_CRT_SUPPORT)))
-                                                    ||
-                                                    ((bios_connectors[j].
-                                                      devices &
-                                                      (ATOM_DEVICE_DFP_SUPPORT))
-                                                     && (bios_connectors[i].
-                                                         devices &
-                                                         (ATOM_DEVICE_CRT_SUPPORT)))) {
-                                                        bios_connectors[i].
-                                                            devices |=
-                                                            bios_connectors[j].
-                                                            devices;
-                                                        bios_connectors[i].
-                                                            connector_type =
-                                                            DRM_MODE_CONNECTOR_DVII;
-                                                        if (bios_connectors[j].devices &
-                                                            (ATOM_DEVICE_DFP_SUPPORT))
+                                                /* make sure not to combine LVDS */
+                                                if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
+                                                        bios_connectors[i].line_mux = 53;
+                                                        bios_connectors[i].ddc_bus.valid = false;
+                                                        continue;
+                                                }
+                                                if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
+                                                        bios_connectors[j].line_mux = 53;
+                                                        bios_connectors[j].ddc_bus.valid = false;
+                                                        continue;
+                                                }
+                                                /* combine analog and digital for DVI-I */
+                                                if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
+                                                     (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
+                                                    ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
+                                                     (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
+                                                        bios_connectors[i].devices |=
+                                                                bios_connectors[j].devices;
+                                                        bios_connectors[i].connector_type =
+                                                                DRM_MODE_CONNECTOR_DVII;
+                                                        if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
                                                                 bios_connectors[i].hpd =
                                                                         bios_connectors[j].hpd;
-                                                        bios_connectors[j].
-                                                            valid = false;
+                                                        bios_connectors[j].valid = false;
                                                 }
                                         }
                                 }
@@ -938,6 +938,43 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
         return false;
 }
 
+union igp_info {
+        struct _ATOM_INTEGRATED_SYSTEM_INFO info;
+        struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
+};
+
+bool radeon_atombios_sideport_present(struct radeon_device *rdev)
+{
+        struct radeon_mode_info *mode_info = &rdev->mode_info;
+        int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
+        union igp_info *igp_info;
+        u8 frev, crev;
+        u16 data_offset;
+
+        atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
+                               &crev, &data_offset);
+
+        igp_info = (union igp_info *)(mode_info->atom_context->bios +
+                                      data_offset);
+
+        if (igp_info) {
+                switch (crev) {
+                case 1:
+                        if (igp_info->info.ucMemoryType & 0xf0)
+                                return true;
+                        break;
+                case 2:
+                        if (igp_info->info_2.ucMemoryType & 0x0f)
+                                return true;
+                        break;
+                default:
+                        DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
+                        break;
+                }
+        }
+        return false;
+}
+
 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
                                    struct radeon_encoder_int_tmds *tmds)
 {
@@ -1029,6 +1066,7 @@ static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
                                 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
                                 ss->range = ss_info->asSS_Info[i].ucSS_Range;
                                 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
+                                break;
                         }
                 }
         }
@@ -1234,6 +1272,61 @@ bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
         return true;
 }
 
+enum radeon_tv_std
+radeon_atombios_get_tv_info(struct radeon_device *rdev)
+{
+        struct radeon_mode_info *mode_info = &rdev->mode_info;
+        int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
+        uint16_t data_offset;
+        uint8_t frev, crev;
+        struct _ATOM_ANALOG_TV_INFO *tv_info;
+        enum radeon_tv_std tv_std = TV_STD_NTSC;
+
+        atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
+
+        tv_info = (struct _ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
+
+        switch (tv_info->ucTV_BootUpDefaultStandard) {
+        case ATOM_TV_NTSC:
+                tv_std = TV_STD_NTSC;
+                DRM_INFO("Default TV standard: NTSC\n");
+                break;
+        case ATOM_TV_NTSCJ:
+                tv_std = TV_STD_NTSC_J;
+                DRM_INFO("Default TV standard: NTSC-J\n");
+                break;
+        case ATOM_TV_PAL:
+                tv_std = TV_STD_PAL;
+                DRM_INFO("Default TV standard: PAL\n");
+                break;
+        case ATOM_TV_PALM:
+                tv_std = TV_STD_PAL_M;
+                DRM_INFO("Default TV standard: PAL-M\n");
+                break;
+        case ATOM_TV_PALN:
+                tv_std = TV_STD_PAL_N;
+                DRM_INFO("Default TV standard: PAL-N\n");
+                break;
+        case ATOM_TV_PALCN:
+                tv_std = TV_STD_PAL_CN;
+                DRM_INFO("Default TV standard: PAL-CN\n");
+                break;
+        case ATOM_TV_PAL60:
+                tv_std = TV_STD_PAL_60;
+                DRM_INFO("Default TV standard: PAL-60\n");
+                break;
+        case ATOM_TV_SECAM:
+                tv_std = TV_STD_SECAM;
+                DRM_INFO("Default TV standard: SECAM\n");
+                break;
+        default:
+                tv_std = TV_STD_NTSC;
+                DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
+                break;
+        }
+        return tv_std;
+}
+
 struct radeon_encoder_tv_dac *
 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
 {
@@ -1269,6 +1362,7 @@ radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
                 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
                 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
 
+                tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
         }
         return tv_dac;
 }
diff --git a/drivers/gpu/drm/radeon/radeon_clocks.c b/drivers/gpu/drm/radeon/radeon_clocks.c
index b062109efbee..812f24dbc2a8 100644
--- a/drivers/gpu/drm/radeon/radeon_clocks.c
+++ b/drivers/gpu/drm/radeon/radeon_clocks.c
@@ -62,7 +62,7 @@ uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev)
 }
 
 /* 10 khz */
-static uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev)
+uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev)
 {
         struct radeon_pll *mpll = &rdev->clock.mpll;
         uint32_t fb_div, ref_div, post_div, mclk;
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index c5021a3445de..7914455c96ca 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -595,6 +595,48 @@ bool radeon_combios_get_clock_info(struct drm_device *dev)
         return false;
 }
 
+bool radeon_combios_sideport_present(struct radeon_device *rdev)
+{
+        struct drm_device *dev = rdev->ddev;
+        u16 igp_info;
+
+        igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
+
+        if (igp_info) {
+                if (RBIOS16(igp_info + 0x4))
+                        return true;
+        }
+        return false;
+}
+
+static const uint32_t default_primarydac_adj[CHIP_LAST] = {
+        0x00000808,             /* r100  */
+        0x00000808,             /* rv100 */
+        0x00000808,             /* rs100 */
+        0x00000808,             /* rv200 */
+        0x00000808,             /* rs200 */
+        0x00000808,             /* r200  */
+        0x00000808,             /* rv250 */
+        0x00000000,             /* rs300 */
+        0x00000808,             /* rv280 */
+        0x00000808,             /* r300  */
+        0x00000808,             /* r350  */
+        0x00000808,             /* rv350 */
+        0x00000808,             /* rv380 */
+        0x00000808,             /* r420  */
+        0x00000808,             /* r423  */
+        0x00000808,             /* rv410 */
+        0x00000000,             /* rs400 */
+        0x00000000,             /* rs480 */
+};
+
+static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
+                                                          struct radeon_encoder_primary_dac *p_dac)
+{
+        p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
+        return;
+}
+
 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
                                                                        radeon_encoder
                                                                        *encoder)
@@ -604,20 +646,20 @@ struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
         uint16_t dac_info;
         uint8_t rev, bg, dac;
         struct radeon_encoder_primary_dac *p_dac = NULL;
+        int found = 0;
 
-        if (rdev->bios == NULL)
+        p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
+                        GFP_KERNEL);
+
+        if (!p_dac)
                 return NULL;
 
+        if (rdev->bios == NULL)
+                goto out;
+
         /* check CRT table */
         dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
         if (dac_info) {
-                p_dac =
-                    kzalloc(sizeof(struct radeon_encoder_primary_dac),
-                            GFP_KERNEL);
-
-                if (!p_dac)
-                        return NULL;
-
                 rev = RBIOS8(dac_info) & 0x3;
                 if (rev < 2) {
                         bg = RBIOS8(dac_info + 0x2) & 0xf;
@@ -628,17 +670,20 @@ struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
                         dac = RBIOS8(dac_info + 0x3) & 0xf;
                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
                 }
-
+                found = 1;
         }
 
+out:
+        if (!found) /* fallback to defaults */
+                radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
+
         return p_dac;
 }
 
-static enum radeon_tv_std
-radeon_combios_get_tv_info(struct radeon_encoder *encoder)
+enum radeon_tv_std
+radeon_combios_get_tv_info(struct radeon_device *rdev)
 {
-        struct drm_device *dev = encoder->base.dev;
-        struct radeon_device *rdev = dev->dev_private;
+        struct drm_device *dev = rdev->ddev;
         uint16_t tv_info;
         enum radeon_tv_std tv_std = TV_STD_NTSC;
 
@@ -779,7 +824,7 @@ struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
                         found = 1;
                 }
-                tv_dac->tv_std = radeon_combios_get_tv_info(encoder);
+                tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
         }
         if (!found) {
                 /* then check CRT table */
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 5eece186e03c..9da10dd5df80 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -49,8 +49,10 @@ void radeon_connector_hotplug(struct drm_connector *connector)
         if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 
-        if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
-                if (radeon_dp_getsinktype(radeon_connector) == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
+        if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
+            (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
+                if ((radeon_dp_getsinktype(radeon_connector) == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
+                    (radeon_dp_getsinktype(radeon_connector) == CONNECTOR_OBJECT_ID_eDP)) {
                         if (radeon_dp_needs_link_train(radeon_connector)) {
                                 if (connector->encoder)
                                         dp_link_train(connector->encoder, connector);
@@ -208,6 +210,18 @@ static struct drm_display_mode *radeon_fp_native_mode(struct drm_encoder *encode
                 drm_mode_set_name(mode);
 
                 DRM_DEBUG("Adding native panel mode %s\n", mode->name);
+        } else if (native_mode->hdisplay != 0 &&
+                   native_mode->vdisplay != 0) {
+                /* mac laptops without an edid */
+                /* Note that this is not necessarily the exact panel mode,
+                 * but an approximation based on the cvt formula.  For these
+                 * systems we should ideally read the mode info out of the
+                 * registers or add a mode table, but this works and is much
+                 * simpler.
+                 */
+                mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);
+                mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
+                DRM_DEBUG("Adding cvt approximation of native panel mode %s\n", mode->name);
         }
         return mode;
 }
@@ -603,7 +617,7 @@ static enum drm_connector_status radeon_vga_detect(struct drm_connector *connect
                                 ret = connector_status_connected;
                 }
         } else {
-                if (radeon_connector->dac_load_detect) {
+                if (radeon_connector->dac_load_detect && encoder) {
                         encoder_funcs = encoder->helper_private;
                         ret = encoder_funcs->detect(encoder, connector);
                 }
@@ -955,7 +969,8 @@ static enum drm_connector_status radeon_dp_detect(struct drm_connector *connecto
         }
 
         sink_type = radeon_dp_getsinktype(radeon_connector);
-        if (sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
+        if ((sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
+            (sink_type == CONNECTOR_OBJECT_ID_eDP)) {
                 if (radeon_dp_getdpcd(radeon_connector)) {
                         radeon_dig_connector->dp_sink_type = sink_type;
                         ret = connector_status_connected;
@@ -980,7 +995,8 @@ static int radeon_dp_mode_valid(struct drm_connector *connector,
 
         /* XXX check mode bandwidth */
 
-        if (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
+        if ((radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
+            (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
                 return radeon_dp_mode_valid_helper(radeon_connector, mode);
         else
                 return MODE_OK;
@@ -1133,6 +1149,7 @@ radeon_add_atom_connector(struct drm_device *dev,
                 subpixel_order = SubPixelHorizontalRGB;
                 break;
         case DRM_MODE_CONNECTOR_DisplayPort:
+        case DRM_MODE_CONNECTOR_eDP:
                 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
                 if (!radeon_dig_connector)
                         goto failed;
@@ -1145,10 +1162,16 @@ radeon_add_atom_connector(struct drm_device *dev,
                         goto failed;
                 if (i2c_bus->valid) {
                         /* add DP i2c bus */
-                        radeon_dig_connector->dp_i2c_bus = radeon_i2c_create_dp(dev, i2c_bus, "DP-auxch");
+                        if (connector_type == DRM_MODE_CONNECTOR_eDP)
+                                radeon_dig_connector->dp_i2c_bus = radeon_i2c_create_dp(dev, i2c_bus, "eDP-auxch");
+                        else
+                                radeon_dig_connector->dp_i2c_bus = radeon_i2c_create_dp(dev, i2c_bus, "DP-auxch");
                         if (!radeon_dig_connector->dp_i2c_bus)
                                 goto failed;
-                        radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DP");
+                        if (connector_type == DRM_MODE_CONNECTOR_eDP)
+                                radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "eDP");
+                        else
+                                radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DP");
                         if (!radeon_connector->ddc_bus)
                                 goto failed;
                 }
@@ -1171,7 +1194,7 @@ radeon_add_atom_connector(struct drm_device *dev,
                                                       1);
                         drm_connector_attach_property(&radeon_connector->base,
                                                       rdev->mode_info.tv_std_property,
-                                                      1);
+                                                      radeon_atombios_get_tv_info(rdev));
                 }
                 break;
         case DRM_MODE_CONNECTOR_LVDS:
@@ -1315,7 +1338,7 @@ radeon_add_legacy_connector(struct drm_device *dev,
                                                       1);
                         drm_connector_attach_property(&radeon_connector->base,
                                                       rdev->mode_info.tv_std_property,
-                                                      1);
+                                                      radeon_combios_get_tv_info(rdev));
                 }
                 break;
         case DRM_MODE_CONNECTOR_LVDS:
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
index 0b2f9c2ad2c1..06123ba31d31 100644
--- a/drivers/gpu/drm/radeon/radeon_cp.c
+++ b/drivers/gpu/drm/radeon/radeon_cp.c
@@ -2145,6 +2145,7 @@ int radeon_master_create(struct drm_device *dev, struct drm_master *master)
                          &master_priv->sarea);
         if (ret) {
                 DRM_ERROR("SAREA setup failed\n");
+                kfree(master_priv);
                 return ret;
         }
         master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 02bcdb1240c0..0c51f8e46613 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -391,6 +391,12 @@ int radeon_asic_init(struct radeon_device *rdev)
                 /* FIXME: not supported yet */
                 return -EINVAL;
         }
+
+        if (rdev->flags & RADEON_IS_IGP) {
+                rdev->asic->get_memory_clock = NULL;
+                rdev->asic->set_memory_clock = NULL;
+        }
+
         return 0;
 }
 
@@ -481,6 +487,7 @@ int radeon_atombios_init(struct radeon_device *rdev)
         atom_card_info->pll_write = cail_pll_write;
 
         rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
+        mutex_init(&rdev->mode_info.atom_context->mutex);
         radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
         atom_allocate_fb_scratch(rdev->mode_info.atom_context);
         return 0;
@@ -539,9 +546,72 @@ void radeon_agp_disable(struct radeon_device *rdev)
         }
 }
 
-/*
- * Radeon device.
- */
+void radeon_check_arguments(struct radeon_device *rdev)
+{
+        /* vramlimit must be a power of two */
+        switch (radeon_vram_limit) {
+        case 0:
+        case 4:
+        case 8:
+        case 16:
+        case 32:
+        case 64:
+        case 128:
+        case 256:
+        case 512:
+        case 1024:
+        case 2048:
+        case 4096:
+                break;
+        default:
+                dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
+                                radeon_vram_limit);
+                radeon_vram_limit = 0;
+                break;
+        }
+        radeon_vram_limit = radeon_vram_limit << 20;
+        /* gtt size must be power of two and greater or equal to 32M */
+        switch (radeon_gart_size) {
+        case 4:
+        case 8:
+        case 16:
+                dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
+                                radeon_gart_size);
+                radeon_gart_size = 512;
+                break;
+        case 32:
+        case 64:
+        case 128:
+        case 256:
+        case 512:
+        case 1024:
+        case 2048:
+        case 4096:
+                break;
+        default:
+                dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
+                                radeon_gart_size);
+                radeon_gart_size = 512;
+                break;
+        }
+        rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
+        /* AGP mode can only be -1, 1, 2, 4, 8 */
+        switch (radeon_agpmode) {
+        case -1:
+        case 0:
+        case 1:
+        case 2:
+        case 4:
+        case 8:
+                break;
+        default:
+                dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
+                                "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
+                radeon_agpmode = 0;
+                break;
+        }
+}
+
 int radeon_device_init(struct radeon_device *rdev,
                        struct drm_device *ddev,
                        struct pci_dev *pdev,
@@ -580,9 +650,9 @@ int radeon_device_init(struct radeon_device *rdev,
 
         /* Set asic functions */
         r = radeon_asic_init(rdev);
-        if (r) {
+        if (r)
                 return r;
-        }
+        radeon_check_arguments(rdev);
 
         if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
                 radeon_agp_disable(rdev);
@@ -663,16 +733,18 @@ void radeon_device_fini(struct radeon_device *rdev)
  */
 int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
 {
-        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_device *rdev;
         struct drm_crtc *crtc;
         int r;
 
-        if (dev == NULL || rdev == NULL) {
+        if (dev == NULL || dev->dev_private == NULL) {
                 return -ENODEV;
         }
         if (state.event == PM_EVENT_PRETHAW) {
                 return 0;
         }
+        rdev = dev->dev_private;
+
         /* unpin the front buffers */
         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
                 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index a133b833e45d..0ec491ead2ff 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -234,7 +234,7 @@ static const char *encoder_names[34] = {
         "INTERNAL_UNIPHY2",
 };
 
-static const char *connector_names[13] = {
+static const char *connector_names[15] = {
         "Unknown",
         "VGA",
         "DVI-I",
@@ -248,6 +248,8 @@ static const char *connector_names[13] = {
         "DisplayPort",
         "HDMI-A",
         "HDMI-B",
+        "TV",
+        "eDP",
 };
 
 static const char *hpd_names[7] = {
@@ -329,8 +331,11 @@ static bool radeon_setup_enc_conn(struct drm_device *dev)
                                 ret = radeon_get_atom_connector_info_from_object_table(dev);
                         else
                                 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
-                } else
+                } else {
                         ret = radeon_get_legacy_connector_info_from_bios(dev);
+                        if (ret == false)
+                                ret = radeon_get_legacy_connector_info_from_table(dev);
+                }
         } else {
                 if (!ASIC_IS_AVIVO(rdev))
                         ret = radeon_get_legacy_connector_info_from_table(dev);
@@ -349,7 +354,8 @@ int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
 {
         int ret = 0;
 
-        if (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
+        if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
+            (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
                 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
                 if (dig->dp_i2c_bus)
                         radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter);
@@ -739,7 +745,7 @@ static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
         { TV_STD_SECAM, "secam" },
 };
 
-int radeon_modeset_create_props(struct radeon_device *rdev)
+static int radeon_modeset_create_props(struct radeon_device *rdev)
 {
         int i, sz;
 
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index dbd56ef82f9c..8ba3de7994d4 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -196,7 +196,7 @@ static struct drm_driver driver_old = {
                  .owner = THIS_MODULE,
                  .open = drm_open,
                  .release = drm_release,
-                 .ioctl = drm_ioctl,
+                 .unlocked_ioctl = drm_ioctl,
                  .mmap = drm_mmap,
                  .poll = drm_poll,
                  .fasync = drm_fasync,
@@ -284,7 +284,7 @@ static struct drm_driver kms_driver = {
                  .owner = THIS_MODULE,
                  .open = drm_open,
                  .release = drm_release,
-                 .ioctl = drm_ioctl,
+                 .unlocked_ioctl = drm_ioctl,
                  .mmap = radeon_mmap,
                  .poll = drm_poll,
                  .fasync = drm_fasync,
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index 0d1d908e5225..82eb551970b9 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -233,6 +233,8 @@ static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
                 if (!ASIC_IS_AVIVO(rdev)) {
                         adjusted_mode->hdisplay = mode->hdisplay;
                         adjusted_mode->vdisplay = mode->vdisplay;
+                        adjusted_mode->crtc_hdisplay = mode->hdisplay;
+                        adjusted_mode->crtc_vdisplay = mode->vdisplay;
                 }
                 adjusted_mode->base.id = mode_id;
         }
@@ -495,9 +497,9 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
-                                if (dig->lvds_misc & (1 << 0))
+                                if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
-                                if (dig->lvds_misc & (1 << 1))
+                                if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
                                         args.v1.ucMisc |= (1 << 1);
                         } else {
                                 if (dig_connector->linkb)
@@ -524,18 +526,18 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
                         args.v2.ucTemporal = 0;
                         args.v2.ucFRC = 0;
                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
-                                if (dig->lvds_misc & (1 << 0))
+                                if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
-                                if (dig->lvds_misc & (1 << 5)) {
+                                if (dig->lvds_misc & ATOM_PANEL_MISC_SPATIAL) {
                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
-                                        if (dig->lvds_misc & (1 << 1))
+                                        if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
                                 }
-                                if (dig->lvds_misc & (1 << 6)) {
+                                if (dig->lvds_misc & ATOM_PANEL_MISC_TEMPORAL) {
                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
-                                        if (dig->lvds_misc & (1 << 1))
+                                        if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
-                                        if (((dig->lvds_misc >> 2) & 0x3) == 2)
+                                        if (((dig->lvds_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
                                 }
                         } else {
@@ -594,21 +596,23 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
                 return ATOM_ENCODER_MODE_LVDS;
                 break;
         case DRM_MODE_CONNECTOR_DisplayPort:
+        case DRM_MODE_CONNECTOR_eDP:
                 radeon_dig_connector = radeon_connector->con_priv;
-                if (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
+                if ((radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
+                    (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
                         return ATOM_ENCODER_MODE_DP;
                 else if (drm_detect_hdmi_monitor(radeon_connector->edid))
                         return ATOM_ENCODER_MODE_HDMI;
                 else
                         return ATOM_ENCODER_MODE_DVI;
                 break;
-        case CONNECTOR_DVI_A:
-        case CONNECTOR_VGA:
+        case DRM_MODE_CONNECTOR_DVIA:
+        case DRM_MODE_CONNECTOR_VGA:
                 return ATOM_ENCODER_MODE_CRT;
                 break;
-        case CONNECTOR_STV:
-        case CONNECTOR_CTV:
-        case CONNECTOR_DIN:
+        case DRM_MODE_CONNECTOR_Composite:
+        case DRM_MODE_CONNECTOR_SVIDEO:
+        case DRM_MODE_CONNECTOR_9PinDIN:
                 /* fix me */
                 return ATOM_ENCODER_MODE_TV;
                 /*return ATOM_ENCODER_MODE_CV;*/
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
index cb4cd97ae39f..8495d4e32e18 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -140,16 +140,15 @@ int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence)
 
 bool radeon_fence_signaled(struct radeon_fence *fence)
 {
-        struct radeon_device *rdev = fence->rdev;
         unsigned long irq_flags;
         bool signaled = false;
 
-        if (rdev->gpu_lockup) {
+        if (!fence)
                 return true;
-        }
-        if (fence == NULL) {
+
+        if (fence->rdev->gpu_lockup)
                 return true;
-        }
+
         write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags);
         signaled = fence->signaled;
         /* if we are shuting down report all fence as signaled */
@@ -324,7 +323,7 @@ int radeon_fence_driver_init(struct radeon_device *rdev)
         write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
         r = radeon_scratch_get(rdev, &rdev->fence_drv.scratch_reg);
         if (r) {
-                DRM_ERROR("Fence failed to get a scratch register.");
+                dev_err(rdev->dev, "fence failed to get scratch register\n");
                 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
                 return r;
         }
@@ -335,9 +334,10 @@ int radeon_fence_driver_init(struct radeon_device *rdev)
         INIT_LIST_HEAD(&rdev->fence_drv.signaled);
         rdev->fence_drv.count_timeout = 0;
         init_waitqueue_head(&rdev->fence_drv.queue);
+        rdev->fence_drv.initialized = true;
         write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
         if (radeon_debugfs_fence_init(rdev)) {
-                DRM_ERROR("Failed to register debugfs file for fence !\n");
+                dev_err(rdev->dev, "fence debugfs file creation failed\n");
         }
         return 0;
 }
@@ -346,11 +346,13 @@ void radeon_fence_driver_fini(struct radeon_device *rdev)
 {
         unsigned long irq_flags;
 
+        if (!rdev->fence_drv.initialized)
+                return;
         wake_up_all(&rdev->fence_drv.queue);
         write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
         radeon_scratch_free(rdev, rdev->fence_drv.scratch_reg);
         write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
-        DRM_INFO("radeon: fence finalized\n");
+        rdev->fence_drv.initialized = false;
 }
 
 
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
index 60df2d7e7e4c..0e1325e18534 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -131,7 +131,6 @@ int radeon_gem_set_domain(struct drm_gem_object *gobj,
                         printk(KERN_ERR "Failed to wait for object !\n");
                         return r;
                 }
-                radeon_hdp_flush(robj->rdev);
         }
         return 0;
 }
@@ -312,7 +311,6 @@ int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
         mutex_lock(&dev->struct_mutex);
         drm_gem_object_unreference(gobj);
         mutex_unlock(&dev->struct_mutex);
-        radeon_hdp_flush(robj->rdev);
         return r;
 }
 
diff --git a/drivers/gpu/drm/radeon/radeon_ioc32.c b/drivers/gpu/drm/radeon/radeon_ioc32.c
index a1bf11de308a..48b7cea31e08 100644
--- a/drivers/gpu/drm/radeon/radeon_ioc32.c
+++ b/drivers/gpu/drm/radeon/radeon_ioc32.c
@@ -92,8 +92,7 @@ static int compat_radeon_cp_init(struct file *file, unsigned int cmd,
                           &init->gart_textures_offset))
                 return -EFAULT;
 
-        return drm_ioctl(file->f_path.dentry->d_inode, file,
-                         DRM_IOCTL_RADEON_CP_INIT, (unsigned long)init);
+        return drm_ioctl(file, DRM_IOCTL_RADEON_CP_INIT, (unsigned long)init);
 }
 
 typedef struct drm_radeon_clear32 {
@@ -125,8 +124,7 @@ static int compat_radeon_cp_clear(struct file *file, unsigned int cmd,
                           &clr->depth_boxes))
                 return -EFAULT;
 
-        return drm_ioctl(file->f_path.dentry->d_inode, file,
-                         DRM_IOCTL_RADEON_CLEAR, (unsigned long)clr);
+        return drm_ioctl(file, DRM_IOCTL_RADEON_CLEAR, (unsigned long)clr);
 }
 
 typedef struct drm_radeon_stipple32 {
@@ -149,8 +147,7 @@ static int compat_radeon_cp_stipple(struct file *file, unsigned int cmd,
                           &request->mask))
                 return -EFAULT;
 
-        return drm_ioctl(file->f_path.dentry->d_inode, file,
-                         DRM_IOCTL_RADEON_STIPPLE, (unsigned long)request);
+        return drm_ioctl(file, DRM_IOCTL_RADEON_STIPPLE, (unsigned long)request);
 }
 
 typedef struct drm_radeon_tex_image32 {
@@ -204,8 +201,7 @@ static int compat_radeon_cp_texture(struct file *file, unsigned int cmd,
                           &image->data))
                 return -EFAULT;
 
-        return drm_ioctl(file->f_path.dentry->d_inode, file,
-                         DRM_IOCTL_RADEON_TEXTURE, (unsigned long)request);
+        return drm_ioctl(file, DRM_IOCTL_RADEON_TEXTURE, (unsigned long)request);
 }
 
 typedef struct drm_radeon_vertex2_32 {
@@ -238,8 +234,7 @@ static int compat_radeon_cp_vertex2(struct file *file, unsigned int cmd,
                           &request->prim))
                 return -EFAULT;
 
-        return drm_ioctl(file->f_path.dentry->d_inode, file,
-                         DRM_IOCTL_RADEON_VERTEX2, (unsigned long)request);
+        return drm_ioctl(file, DRM_IOCTL_RADEON_VERTEX2, (unsigned long)request);
 }
 
 typedef struct drm_radeon_cmd_buffer32 {
@@ -268,8 +263,7 @@ static int compat_radeon_cp_cmdbuf(struct file *file, unsigned int cmd,
                           &request->boxes))
                 return -EFAULT;
 
-        return drm_ioctl(file->f_path.dentry->d_inode, file,
-                         DRM_IOCTL_RADEON_CMDBUF, (unsigned long)request);
+        return drm_ioctl(file, DRM_IOCTL_RADEON_CMDBUF, (unsigned long)request);
 }
 
 typedef struct drm_radeon_getparam32 {
@@ -293,8 +287,7 @@ static int compat_radeon_cp_getparam(struct file *file, unsigned int cmd,
                           &request->value))
                 return -EFAULT;
 
-        return drm_ioctl(file->f_path.dentry->d_inode, file,
-                         DRM_IOCTL_RADEON_GETPARAM, (unsigned long)request);
+        return drm_ioctl(file, DRM_IOCTL_RADEON_GETPARAM, (unsigned long)request);
 }
 
 typedef struct drm_radeon_mem_alloc32 {
@@ -322,8 +315,7 @@ static int compat_radeon_mem_alloc(struct file *file, unsigned int cmd,
                           &request->region_offset))
                 return -EFAULT;
 
-        return drm_ioctl(file->f_path.dentry->d_inode, file,
-                         DRM_IOCTL_RADEON_ALLOC, (unsigned long)request);
+        return drm_ioctl(file, DRM_IOCTL_RADEON_ALLOC, (unsigned long)request);
 }
 
 typedef struct drm_radeon_irq_emit32 {
@@ -345,8 +337,7 @@ static int compat_radeon_irq_emit(struct file *file, unsigned int cmd,
                           &request->irq_seq))
                 return -EFAULT;
 
-        return drm_ioctl(file->f_path.dentry->d_inode, file,
-                         DRM_IOCTL_RADEON_IRQ_EMIT, (unsigned long)request);
+        return drm_ioctl(file, DRM_IOCTL_RADEON_IRQ_EMIT, (unsigned long)request);
 }
 
 /* The two 64-bit arches where alignof(u64)==4 in 32-bit code */
@@ -372,8 +363,7 @@ static int compat_radeon_cp_setparam(struct file *file, unsigned int cmd,
                           &request->value))
                 return -EFAULT;
 
-        return drm_ioctl(file->f_dentry->d_inode, file,
-                         DRM_IOCTL_RADEON_SETPARAM, (unsigned long) request);
+        return drm_ioctl(file, DRM_IOCTL_RADEON_SETPARAM, (unsigned long) request);
 }
 #else
 #define compat_radeon_cp_setparam NULL
@@ -413,12 +403,10 @@ long radeon_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
         if (nr < DRM_COMMAND_BASE + DRM_ARRAY_SIZE(radeon_compat_ioctls))
                 fn = radeon_compat_ioctls[nr - DRM_COMMAND_BASE];
 
-        lock_kernel();          /* XXX for now */
         if (fn != NULL)
                 ret = (*fn) (filp, cmd, arg);
         else
-                ret = drm_ioctl(filp->f_path.dentry->d_inode, filp, cmd, arg);
-        unlock_kernel();
+                ret = drm_ioctl(filp, cmd, arg);
 
         return ret;
 }
@@ -431,9 +419,7 @@ long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long
         if (nr < DRM_COMMAND_BASE)
                 return drm_compat_ioctl(filp, cmd, arg);
 
-        lock_kernel();          /* XXX for now */
-        ret = drm_ioctl(filp->f_path.dentry->d_inode, filp, cmd, arg);
-        unlock_kernel();
+        ret = drm_ioctl(filp, cmd, arg);
 
         return ret;
 }
diff --git a/drivers/gpu/drm/radeon/radeon_irq.c b/drivers/gpu/drm/radeon/radeon_irq.c
index b79ecc4a7cc4..2f349a300195 100644
--- a/drivers/gpu/drm/radeon/radeon_irq.c
+++ b/drivers/gpu/drm/radeon/radeon_irq.c
@@ -289,16 +289,16 @@ int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_pr
         drm_radeon_irq_emit_t *emit = data;
         int result;
 
-        if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
-                return -EINVAL;
-
-        LOCK_TEST_WITH_RETURN(dev, file_priv);
-
         if (!dev_priv) {
                 DRM_ERROR("called with no initialization\n");
                 return -EINVAL;
         }
 
+        if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+                return -EINVAL;
+
+        LOCK_TEST_WITH_RETURN(dev, file_priv);
+
         result = radeon_emit_irq(dev);
 
         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c
index 9223296fe37b..3cfd60fd0083 100644
--- a/drivers/gpu/drm/radeon/radeon_irq_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c
@@ -97,6 +97,7 @@ void radeon_driver_irq_uninstall_kms(struct drm_device *dev)
         rdev->irq.sw_int = false;
         for (i = 0; i < 2; i++) {
                 rdev->irq.crtc_vblank_int[i] = false;
+                rdev->irq.hpd[i] = false;
         }
         radeon_irq_set(rdev);
 }
@@ -128,17 +129,22 @@ int radeon_irq_kms_init(struct radeon_device *rdev)
                         DRM_INFO("radeon: using MSI.\n");
                 }
         }
-        drm_irq_install(rdev->ddev);
         rdev->irq.installed = true;
+        r = drm_irq_install(rdev->ddev);
+        if (r) {
+                rdev->irq.installed = false;
+                return r;
+        }
         DRM_INFO("radeon: irq initialized.\n");
         return 0;
 }
 
 void radeon_irq_kms_fini(struct radeon_device *rdev)
 {
+        drm_vblank_cleanup(rdev->ddev);
         if (rdev->irq.installed) {
-                rdev->irq.installed = false;
                 drm_irq_uninstall(rdev->ddev);
+                rdev->irq.installed = false;
                 if (rdev->msi_enabled)
                         pci_disable_msi(rdev->pdev);
         }
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index b82ede98e152..cc27485a07ad 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -43,8 +43,7 @@ static void radeon_overscan_setup(struct drm_crtc *crtc,
 }
 
 static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
-                                       struct drm_display_mode *mode,
-                                       struct drm_display_mode *adjusted_mode)
+                                       struct drm_display_mode *mode)
 {
         struct drm_device *dev = crtc->dev;
         struct radeon_device *rdev = dev->dev_private;
@@ -1059,7 +1058,7 @@ static int radeon_crtc_mode_set(struct drm_crtc *crtc,
         radeon_set_pll(crtc, adjusted_mode);
         radeon_overscan_setup(crtc, adjusted_mode);
         if (radeon_crtc->crtc_id == 0) {
-                radeon_legacy_rmx_mode_set(crtc, mode, adjusted_mode);
+                radeon_legacy_rmx_mode_set(crtc, adjusted_mode);
         } else {
                 if (radeon_crtc->rmx_type != RMX_OFF) {
                         /* FIXME: only first crtc has rmx what should we
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
index df00515e81fa..981508ff7037 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
@@ -207,6 +207,8 @@ static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder,
                 *adjusted_mode = *native_mode;
                 adjusted_mode->hdisplay = mode->hdisplay;
                 adjusted_mode->vdisplay = mode->vdisplay;
+                adjusted_mode->crtc_hdisplay = mode->hdisplay;
+                adjusted_mode->crtc_vdisplay = mode->vdisplay;
                 adjusted_mode->base.id = mode_id;
         }
 
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_tv.c b/drivers/gpu/drm/radeon/radeon_legacy_tv.c
index 3a12bb0c0563..417684daef4c 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_tv.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_tv.c
@@ -77,7 +77,7 @@ struct radeon_tv_mode_constants {
         unsigned pix_to_tv;
 };
 
-static const uint16_t hor_timing_NTSC[] = {
+static const uint16_t hor_timing_NTSC[MAX_H_CODE_TIMING_LEN] = {
         0x0007,
         0x003f,
         0x0263,
@@ -98,7 +98,7 @@ static const uint16_t hor_timing_NTSC[] = {
         0
 };
 
-static const uint16_t vert_timing_NTSC[] = {
+static const uint16_t vert_timing_NTSC[MAX_V_CODE_TIMING_LEN] = {
         0x2001,
         0x200d,
         0x1006,
@@ -115,7 +115,7 @@ static const uint16_t vert_timing_NTSC[] = {
         0
 };
 
-static const uint16_t hor_timing_PAL[] = {
+static const uint16_t hor_timing_PAL[MAX_H_CODE_TIMING_LEN] = {
         0x0007,
         0x0058,
         0x027c,
@@ -136,7 +136,7 @@ static const uint16_t hor_timing_PAL[] = {
         0
 };
 
-static const uint16_t vert_timing_PAL[] =       {
+static const uint16_t vert_timing_PAL[MAX_V_CODE_TIMING_LEN] = {
         0x2001,
         0x200c,
         0x1005,
@@ -623,9 +623,9 @@ void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
         }
         flicker_removal = (tmp + 500) / 1000;
 
-        if (flicker_removal < 3)
-                flicker_removal = 3;
-        for (i = 0; i < 6; ++i) {
+        if (flicker_removal < 2)
+                flicker_removal = 2;
+        for (i = 0; i < ARRAY_SIZE(SLOPE_limit); ++i) {
                 if (flicker_removal == SLOPE_limit[i])
                         break;
         }
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 3dcbe130c422..91cb041cb40d 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -46,32 +46,6 @@ struct radeon_device;
 #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
 #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
 
-enum radeon_connector_type {
-        CONNECTOR_NONE,
-        CONNECTOR_VGA,
-        CONNECTOR_DVI_I,
-        CONNECTOR_DVI_D,
-        CONNECTOR_DVI_A,
-        CONNECTOR_STV,
-        CONNECTOR_CTV,
-        CONNECTOR_LVDS,
-        CONNECTOR_DIGITAL,
-        CONNECTOR_SCART,
-        CONNECTOR_HDMI_TYPE_A,
-        CONNECTOR_HDMI_TYPE_B,
-        CONNECTOR_0XC,
-        CONNECTOR_0XD,
-        CONNECTOR_DIN,
-        CONNECTOR_DISPLAY_PORT,
-        CONNECTOR_UNSUPPORTED
-};
-
-enum radeon_dvi_type {
-        DVI_AUTO,
-        DVI_DIGITAL,
-        DVI_ANALOG
-};
-
 enum radeon_rmx_type {
         RMX_OFF,
         RMX_FULL,
@@ -88,6 +62,7 @@ enum radeon_tv_std {
         TV_STD_SCART_PAL,
         TV_STD_SECAM,
         TV_STD_PAL_CN,
+        TV_STD_PAL_N,
 };
 
 /* radeon gpio-based i2c
@@ -395,6 +370,11 @@ struct radeon_framebuffer {
         struct drm_gem_object *obj;
 };
 
+extern enum radeon_tv_std
+radeon_combios_get_tv_info(struct radeon_device *rdev);
+extern enum radeon_tv_std
+radeon_atombios_get_tv_info(struct radeon_device *rdev);
+
 extern void radeon_connector_hotplug(struct drm_connector *connector);
 extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
 extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector,
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index d9ffe1f56e8f..4e636de877b2 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -221,8 +221,9 @@ int radeon_bo_unpin(struct radeon_bo *bo)
 int radeon_bo_evict_vram(struct radeon_device *rdev)
 {
         if (rdev->flags & RADEON_IS_IGP) {
-                /* Useless to evict on IGP chips */
-                return 0;
+                if (rdev->mc.igp_sideport_enabled == false)
+                        /* Useless to evict on IGP chips */
+                        return 0;
         }
         return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
 }
diff --git a/drivers/gpu/drm/radeon/radeon_test.c b/drivers/gpu/drm/radeon/radeon_test.c
index 391c973ec4db..9f5e2f929da9 100644
--- a/drivers/gpu/drm/radeon/radeon_test.c
+++ b/drivers/gpu/drm/radeon/radeon_test.c
@@ -42,8 +42,8 @@ void radeon_test_moves(struct radeon_device *rdev)
         /* Number of tests =
          * (Total GTT - IB pool - writeback page - ring buffer) / test size
          */
-        n = (rdev->mc.gtt_size - RADEON_IB_POOL_SIZE*64*1024 - RADEON_GPU_PAGE_SIZE -
-             rdev->cp.ring_size) / size;
+        n = ((u32)(rdev->mc.gtt_size - RADEON_IB_POOL_SIZE*64*1024 - RADEON_GPU_PAGE_SIZE -
+             rdev->cp.ring_size)) / size;
 
         gtt_obj = kzalloc(n * sizeof(*gtt_obj), GFP_KERNEL);
         if (!gtt_obj) {
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
index d7fd160cc671..3b0c07b444a2 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -494,6 +494,7 @@ int radeon_ttm_init(struct radeon_device *rdev)
                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
                 return r;
         }
+        rdev->mman.initialized = true;
         r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM,
                                 rdev->mc.real_vram_size >> PAGE_SHIFT);
         if (r) {
@@ -541,6 +542,8 @@ void radeon_ttm_fini(struct radeon_device *rdev)
 {
         int r;
 
+        if (!rdev->mman.initialized)
+                return;
         if (rdev->stollen_vga_memory) {
                 r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
                 if (r == 0) {
@@ -554,6 +557,7 @@ void radeon_ttm_fini(struct radeon_device *rdev)
         ttm_bo_device_release(&rdev->mman.bdev);
         radeon_gart_fini(rdev);
         radeon_ttm_global_fini(rdev);
+        rdev->mman.initialized = false;
         DRM_INFO("radeon: ttm finalized\n");
 }
 
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r420 b/drivers/gpu/drm/radeon/reg_srcs/r420
new file mode 100644
index 000000000000..989f7a020832
--- /dev/null
+++ b/drivers/gpu/drm/radeon/reg_srcs/r420
@@ -0,0 +1,795 @@
+r420 0x4f60
+0x1434 SRC_Y_X
+0x1438 DST_Y_X
+0x143C DST_HEIGHT_WIDTH
+0x146C DP_GUI_MASTER_CNTL
+0x1474 BRUSH_Y_X
+0x1478 DP_BRUSH_BKGD_CLR
+0x147C DP_BRUSH_FRGD_CLR
+0x1480 BRUSH_DATA0
+0x1484 BRUSH_DATA1
+0x1598 DST_WIDTH_HEIGHT
+0x15C0 CLR_CMP_CNTL
+0x15C4 CLR_CMP_CLR_SRC
+0x15C8 CLR_CMP_CLR_DST
+0x15CC CLR_CMP_MSK
+0x15D8 DP_SRC_FRGD_CLR
+0x15DC DP_SRC_BKGD_CLR
+0x1600 DST_LINE_START
+0x1604 DST_LINE_END
+0x1608 DST_LINE_PATCOUNT
+0x16C0 DP_CNTL
+0x16CC DP_WRITE_MSK
+0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR
+0x16E8 DEFAULT_SC_BOTTOM_RIGHT
+0x16EC SC_TOP_LEFT
+0x16F0 SC_BOTTOM_RIGHT
+0x16F4 SRC_SC_BOTTOM_RIGHT
+0x1714 DSTCACHE_CTLSTAT
+0x1720 WAIT_UNTIL
+0x172C RBBM_GUICNTL
+0x1D98 VAP_VPORT_XSCALE
+0x1D9C VAP_VPORT_XOFFSET
+0x1DA0 VAP_VPORT_YSCALE
+0x1DA4 VAP_VPORT_YOFFSET
+0x1DA8 VAP_VPORT_ZSCALE
+0x1DAC VAP_VPORT_ZOFFSET
+0x2080 VAP_CNTL
+0x2090 VAP_OUT_VTX_FMT_0
+0x2094 VAP_OUT_VTX_FMT_1
+0x20B0 VAP_VTE_CNTL
+0x2138 VAP_VF_MIN_VTX_INDX
+0x2140 VAP_CNTL_STATUS
+0x2150 VAP_PROG_STREAM_CNTL_0
+0x2154 VAP_PROG_STREAM_CNTL_1
+0x2158 VAP_PROG_STREAM_CNTL_2
+0x215C VAP_PROG_STREAM_CNTL_3
+0x2160 VAP_PROG_STREAM_CNTL_4
+0x2164 VAP_PROG_STREAM_CNTL_5
+0x2168 VAP_PROG_STREAM_CNTL_6
+0x216C VAP_PROG_STREAM_CNTL_7
+0x2180 VAP_VTX_STATE_CNTL
+0x2184 VAP_VSM_VTX_ASSM
+0x2188 VAP_VTX_STATE_IND_REG_0
+0x218C VAP_VTX_STATE_IND_REG_1
+0x2190 VAP_VTX_STATE_IND_REG_2
+0x2194 VAP_VTX_STATE_IND_REG_3
+0x2198 VAP_VTX_STATE_IND_REG_4
+0x219C VAP_VTX_STATE_IND_REG_5
+0x21A0 VAP_VTX_STATE_IND_REG_6
+0x21A4 VAP_VTX_STATE_IND_REG_7
+0x21A8 VAP_VTX_STATE_IND_REG_8
+0x21AC VAP_VTX_STATE_IND_REG_9
+0x21B0 VAP_VTX_STATE_IND_REG_10
+0x21B4 VAP_VTX_STATE_IND_REG_11
+0x21B8 VAP_VTX_STATE_IND_REG_12
+0x21BC VAP_VTX_STATE_IND_REG_13
+0x21C0 VAP_VTX_STATE_IND_REG_14
+0x21C4 VAP_VTX_STATE_IND_REG_15
+0x21DC VAP_PSC_SGN_NORM_CNTL
+0x21E0 VAP_PROG_STREAM_CNTL_EXT_0
+0x21E4 VAP_PROG_STREAM_CNTL_EXT_1
+0x21E8 VAP_PROG_STREAM_CNTL_EXT_2
+0x21EC VAP_PROG_STREAM_CNTL_EXT_3
+0x21F0 VAP_PROG_STREAM_CNTL_EXT_4
+0x21F4 VAP_PROG_STREAM_CNTL_EXT_5
+0x21F8 VAP_PROG_STREAM_CNTL_EXT_6
+0x21FC VAP_PROG_STREAM_CNTL_EXT_7
+0x2200 VAP_PVS_VECTOR_INDX_REG
+0x2204 VAP_PVS_VECTOR_DATA_REG
+0x2208 VAP_PVS_VECTOR_DATA_REG_128
+0x221C VAP_CLIP_CNTL
+0x2220 VAP_GB_VERT_CLIP_ADJ
+0x2224 VAP_GB_VERT_DISC_ADJ
+0x2228 VAP_GB_HORZ_CLIP_ADJ
+0x222C VAP_GB_HORZ_DISC_ADJ
+0x2230 VAP_PVS_FLOW_CNTL_ADDRS_0
+0x2234 VAP_PVS_FLOW_CNTL_ADDRS_1
+0x2238 VAP_PVS_FLOW_CNTL_ADDRS_2
+0x223C VAP_PVS_FLOW_CNTL_ADDRS_3
+0x2240 VAP_PVS_FLOW_CNTL_ADDRS_4
+0x2244 VAP_PVS_FLOW_CNTL_ADDRS_5
+0x2248 VAP_PVS_FLOW_CNTL_ADDRS_6
+0x224C VAP_PVS_FLOW_CNTL_ADDRS_7
+0x2250 VAP_PVS_FLOW_CNTL_ADDRS_8
+0x2254 VAP_PVS_FLOW_CNTL_ADDRS_9
+0x2258 VAP_PVS_FLOW_CNTL_ADDRS_10
+0x225C VAP_PVS_FLOW_CNTL_ADDRS_11
+0x2260 VAP_PVS_FLOW_CNTL_ADDRS_12
+0x2264 VAP_PVS_FLOW_CNTL_ADDRS_13
+0x2268 VAP_PVS_FLOW_CNTL_ADDRS_14
+0x226C VAP_PVS_FLOW_CNTL_ADDRS_15
+0x2284 VAP_PVS_STATE_FLUSH_REG
+0x2288 VAP_PVS_VTX_TIMEOUT_REG
+0x2290 VAP_PVS_FLOW_CNTL_LOOP_INDEX_0
+0x2294 VAP_PVS_FLOW_CNTL_LOOP_INDEX_1
+0x2298 VAP_PVS_FLOW_CNTL_LOOP_INDEX_2
+0x229C VAP_PVS_FLOW_CNTL_LOOP_INDEX_3
+0x22A0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_4
+0x22A4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_5
+0x22A8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_6
+0x22AC VAP_PVS_FLOW_CNTL_LOOP_INDEX_7
+0x22B0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_8
+0x22B4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_9
+0x22B8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_10
+0x22BC VAP_PVS_FLOW_CNTL_LOOP_INDEX_11
+0x22C0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_12
+0x22C4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_13
+0x22C8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_14
+0x22CC VAP_PVS_FLOW_CNTL_LOOP_INDEX_15
+0x22D0 VAP_PVS_CODE_CNTL_0
+0x22D4 VAP_PVS_CONST_CNTL
+0x22D8 VAP_PVS_CODE_CNTL_1
+0x22DC VAP_PVS_FLOW_CNTL_OPC
+0x342C RB2D_DSTCACHE_CTLSTAT
+0x4000 GB_VAP_RASTER_VTX_FMT_0
+0x4004 GB_VAP_RASTER_VTX_FMT_1
+0x4008 GB_ENABLE
+0x401C GB_SELECT
+0x4020 GB_AA_CONFIG
+0x4024 GB_FIFO_SIZE
+0x4100 TX_INVALTAGS
+0x4200 GA_POINT_S0
+0x4204 GA_POINT_T0
+0x4208 GA_POINT_S1
+0x420C GA_POINT_T1
+0x4214 GA_TRIANGLE_STIPPLE
+0x421C GA_POINT_SIZE
+0x4230 GA_POINT_MINMAX
+0x4234 GA_LINE_CNTL
+0x4238 GA_LINE_STIPPLE_CONFIG
+0x4260 GA_LINE_STIPPLE_VALUE
+0x4264 GA_LINE_S0
+0x4268 GA_LINE_S1
+0x4278 GA_COLOR_CONTROL
+0x427C GA_SOLID_RG
+0x4280 GA_SOLID_BA
+0x4288 GA_POLY_MODE
+0x428C GA_ROUND_MODE
+0x4290 GA_OFFSET
+0x4294 GA_FOG_SCALE
+0x4298 GA_FOG_OFFSET
+0x42A0 SU_TEX_WRAP
+0x42A4 SU_POLY_OFFSET_FRONT_SCALE
+0x42A8 SU_POLY_OFFSET_FRONT_OFFSET
+0x42AC SU_POLY_OFFSET_BACK_SCALE
+0x42B0 SU_POLY_OFFSET_BACK_OFFSET
+0x42B4 SU_POLY_OFFSET_ENABLE
+0x42B8 SU_CULL_MODE
+0x42C0 SU_DEPTH_SCALE
+0x42C4 SU_DEPTH_OFFSET
+0x42C8 SU_REG_DEST
+0x4300 RS_COUNT
+0x4304 RS_INST_COUNT
+0x4310 RS_IP_0
+0x4314 RS_IP_1
+0x4318 RS_IP_2
+0x431C RS_IP_3
+0x4320 RS_IP_4
+0x4324 RS_IP_5
+0x4328 RS_IP_6
+0x432C RS_IP_7
+0x4330 RS_INST_0
+0x4334 RS_INST_1
+0x4338 RS_INST_2
+0x433C RS_INST_3
+0x4340 RS_INST_4
+0x4344 RS_INST_5
+0x4348 RS_INST_6
+0x434C RS_INST_7
+0x4350 RS_INST_8
+0x4354 RS_INST_9
+0x4358 RS_INST_10
+0x435C RS_INST_11
+0x4360 RS_INST_12
+0x4364 RS_INST_13
+0x4368 RS_INST_14
+0x436C RS_INST_15
+0x43A4 SC_HYPERZ_EN
+0x43A8 SC_EDGERULE
+0x43B0 SC_CLIP_0_A
+0x43B4 SC_CLIP_0_B
+0x43B8 SC_CLIP_1_A
+0x43BC SC_CLIP_1_B
+0x43C0 SC_CLIP_2_A
+0x43C4 SC_CLIP_2_B
+0x43C8 SC_CLIP_3_A
+0x43CC SC_CLIP_3_B
+0x43D0 SC_CLIP_RULE
+0x43E0 SC_SCISSOR0
+0x43E8 SC_SCREENDOOR
+0x4440 TX_FILTER1_0
+0x4444 TX_FILTER1_1
+0x4448 TX_FILTER1_2
+0x444C TX_FILTER1_3
+0x4450 TX_FILTER1_4
+0x4454 TX_FILTER1_5
+0x4458 TX_FILTER1_6
+0x445C TX_FILTER1_7
+0x4460 TX_FILTER1_8
+0x4464 TX_FILTER1_9
+0x4468 TX_FILTER1_10
+0x446C TX_FILTER1_11
+0x4470 TX_FILTER1_12
+0x4474 TX_FILTER1_13
+0x4478 TX_FILTER1_14
+0x447C TX_FILTER1_15
+0x4580 TX_CHROMA_KEY_0
+0x4584 TX_CHROMA_KEY_1
+0x4588 TX_CHROMA_KEY_2
+0x458C TX_CHROMA_KEY_3
+0x4590 TX_CHROMA_KEY_4
+0x4594 TX_CHROMA_KEY_5
+0x4598 TX_CHROMA_KEY_6
+0x459C TX_CHROMA_KEY_7
+0x45A0 TX_CHROMA_KEY_8
+0x45A4 TX_CHROMA_KEY_9
+0x45A8 TX_CHROMA_KEY_10
+0x45AC TX_CHROMA_KEY_11
+0x45B0 TX_CHROMA_KEY_12
+0x45B4 TX_CHROMA_KEY_13
+0x45B8 TX_CHROMA_KEY_14
+0x45BC TX_CHROMA_KEY_15
+0x45C0 TX_BORDER_COLOR_0
+0x45C4 TX_BORDER_COLOR_1
+0x45C8 TX_BORDER_COLOR_2
+0x45CC TX_BORDER_COLOR_3
+0x45D0 TX_BORDER_COLOR_4
+0x45D4 TX_BORDER_COLOR_5
+0x45D8 TX_BORDER_COLOR_6
+0x45DC TX_BORDER_COLOR_7
+0x45E0 TX_BORDER_COLOR_8
+0x45E4 TX_BORDER_COLOR_9
+0x45E8 TX_BORDER_COLOR_10
+0x45EC TX_BORDER_COLOR_11
+0x45F0 TX_BORDER_COLOR_12
+0x45F4 TX_BORDER_COLOR_13
+0x45F8 TX_BORDER_COLOR_14
+0x45FC TX_BORDER_COLOR_15
+0x4600 US_CONFIG
+0x4604 US_PIXSIZE
+0x4608 US_CODE_OFFSET
+0x460C US_RESET
+0x4610 US_CODE_ADDR_0
+0x4614 US_CODE_ADDR_1
+0x4618 US_CODE_ADDR_2
+0x461C US_CODE_ADDR_3
+0x4620 US_TEX_INST_0
+0x4624 US_TEX_INST_1
+0x4628 US_TEX_INST_2
+0x462C US_TEX_INST_3
+0x4630 US_TEX_INST_4
+0x4634 US_TEX_INST_5
+0x4638 US_TEX_INST_6
+0x463C US_TEX_INST_7
+0x4640 US_TEX_INST_8
+0x4644 US_TEX_INST_9
+0x4648 US_TEX_INST_10
+0x464C US_TEX_INST_11
+0x4650 US_TEX_INST_12
+0x4654 US_TEX_INST_13
+0x4658 US_TEX_INST_14
+0x465C US_TEX_INST_15
+0x4660 US_TEX_INST_16
+0x4664 US_TEX_INST_17
+0x4668 US_TEX_INST_18
+0x466C US_TEX_INST_19
+0x4670 US_TEX_INST_20
+0x4674 US_TEX_INST_21
+0x4678 US_TEX_INST_22
+0x467C US_TEX_INST_23
+0x4680 US_TEX_INST_24
+0x4684 US_TEX_INST_25
+0x4688 US_TEX_INST_26
+0x468C US_TEX_INST_27
+0x4690 US_TEX_INST_28
+0x4694 US_TEX_INST_29
+0x4698 US_TEX_INST_30
+0x469C US_TEX_INST_31
+0x46A4 US_OUT_FMT_0
+0x46A8 US_OUT_FMT_1
+0x46AC US_OUT_FMT_2
+0x46B0 US_OUT_FMT_3
+0x46B4 US_W_FMT
+0x46B8 US_CODE_BANK
+0x46BC US_CODE_EXT
+0x46C0 US_ALU_RGB_ADDR_0
+0x46C4 US_ALU_RGB_ADDR_1
+0x46C8 US_ALU_RGB_ADDR_2
+0x46CC US_ALU_RGB_ADDR_3
+0x46D0 US_ALU_RGB_ADDR_4
+0x46D4 US_ALU_RGB_ADDR_5
+0x46D8 US_ALU_RGB_ADDR_6
+0x46DC US_ALU_RGB_ADDR_7
+0x46E0 US_ALU_RGB_ADDR_8
+0x46E4 US_ALU_RGB_ADDR_9
+0x46E8 US_ALU_RGB_ADDR_10
+0x46EC US_ALU_RGB_ADDR_11
+0x46F0 US_ALU_RGB_ADDR_12
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+0x46F8 US_ALU_RGB_ADDR_14
+0x46FC US_ALU_RGB_ADDR_15
+0x4700 US_ALU_RGB_ADDR_16
+0x4704 US_ALU_RGB_ADDR_17
+0x4708 US_ALU_RGB_ADDR_18
+0x470C US_ALU_RGB_ADDR_19
+0x4710 US_ALU_RGB_ADDR_20
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+0x4718 US_ALU_RGB_ADDR_22
+0x471C US_ALU_RGB_ADDR_23
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+0x4724 US_ALU_RGB_ADDR_25
+0x4728 US_ALU_RGB_ADDR_26
+0x472C US_ALU_RGB_ADDR_27
+0x4730 US_ALU_RGB_ADDR_28
+0x4734 US_ALU_RGB_ADDR_29
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+0x4744 US_ALU_RGB_ADDR_33
+0x4748 US_ALU_RGB_ADDR_34
+0x474C US_ALU_RGB_ADDR_35
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+0x4768 US_ALU_RGB_ADDR_42
+0x476C US_ALU_RGB_ADDR_43
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+0x47B8 US_ALU_RGB_ADDR_62
+0x47BC US_ALU_RGB_ADDR_63
+0x47C0 US_ALU_ALPHA_ADDR_0
+0x47C4 US_ALU_ALPHA_ADDR_1
+0x47C8 US_ALU_ALPHA_ADDR_2
+0x47CC US_ALU_ALPHA_ADDR_3
+0x47D0 US_ALU_ALPHA_ADDR_4
+0x47D4 US_ALU_ALPHA_ADDR_5
+0x47D8 US_ALU_ALPHA_ADDR_6
+0x47DC US_ALU_ALPHA_ADDR_7
+0x47E0 US_ALU_ALPHA_ADDR_8
+0x47E4 US_ALU_ALPHA_ADDR_9
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+0x47EC US_ALU_ALPHA_ADDR_11
+0x47F0 US_ALU_ALPHA_ADDR_12
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+0x47F8 US_ALU_ALPHA_ADDR_14
+0x47FC US_ALU_ALPHA_ADDR_15
+0x4800 US_ALU_ALPHA_ADDR_16
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+0x4ABC US_ALU_ALPHA_INST_63
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+0x4B20 US_ALU_EXT_ADDR_24
+0x4B24 US_ALU_EXT_ADDR_25
+0x4B28 US_ALU_EXT_ADDR_26
+0x4B2C US_ALU_EXT_ADDR_27
+0x4B30 US_ALU_EXT_ADDR_28
+0x4B34 US_ALU_EXT_ADDR_29
+0x4B38 US_ALU_EXT_ADDR_30
+0x4B3C US_ALU_EXT_ADDR_31
+0x4B40 US_ALU_EXT_ADDR_32
+0x4B44 US_ALU_EXT_ADDR_33
+0x4B48 US_ALU_EXT_ADDR_34
+0x4B4C US_ALU_EXT_ADDR_35
+0x4B50 US_ALU_EXT_ADDR_36
+0x4B54 US_ALU_EXT_ADDR_37
+0x4B58 US_ALU_EXT_ADDR_38
+0x4B5C US_ALU_EXT_ADDR_39
+0x4B60 US_ALU_EXT_ADDR_40
+0x4B64 US_ALU_EXT_ADDR_41
+0x4B68 US_ALU_EXT_ADDR_42
+0x4B6C US_ALU_EXT_ADDR_43
+0x4B70 US_ALU_EXT_ADDR_44
+0x4B74 US_ALU_EXT_ADDR_45
+0x4B78 US_ALU_EXT_ADDR_46
+0x4B7C US_ALU_EXT_ADDR_47
+0x4B80 US_ALU_EXT_ADDR_48
+0x4B84 US_ALU_EXT_ADDR_49
+0x4B88 US_ALU_EXT_ADDR_50
+0x4B8C US_ALU_EXT_ADDR_51
+0x4B90 US_ALU_EXT_ADDR_52
+0x4B94 US_ALU_EXT_ADDR_53
+0x4B98 US_ALU_EXT_ADDR_54
+0x4B9C US_ALU_EXT_ADDR_55
+0x4BA0 US_ALU_EXT_ADDR_56
+0x4BA4 US_ALU_EXT_ADDR_57
+0x4BA8 US_ALU_EXT_ADDR_58
+0x4BAC US_ALU_EXT_ADDR_59
+0x4BB0 US_ALU_EXT_ADDR_60
+0x4BB4 US_ALU_EXT_ADDR_61
+0x4BB8 US_ALU_EXT_ADDR_62
+0x4BBC US_ALU_EXT_ADDR_63
+0x4BC0 FG_FOG_BLEND
+0x4BC4 FG_FOG_FACTOR
+0x4BC8 FG_FOG_COLOR_R
+0x4BCC FG_FOG_COLOR_G
+0x4BD0 FG_FOG_COLOR_B
+0x4BD4 FG_ALPHA_FUNC
+0x4BD8 FG_DEPTH_SRC
+0x4C00 US_ALU_CONST_R_0
+0x4C04 US_ALU_CONST_G_0
+0x4C08 US_ALU_CONST_B_0
+0x4C0C US_ALU_CONST_A_0
+0x4C10 US_ALU_CONST_R_1
+0x4C14 US_ALU_CONST_G_1
+0x4C18 US_ALU_CONST_B_1
+0x4C1C US_ALU_CONST_A_1
+0x4C20 US_ALU_CONST_R_2
+0x4C24 US_ALU_CONST_G_2
+0x4C28 US_ALU_CONST_B_2
+0x4C2C US_ALU_CONST_A_2
+0x4C30 US_ALU_CONST_R_3
+0x4C34 US_ALU_CONST_G_3
+0x4C38 US_ALU_CONST_B_3
+0x4C3C US_ALU_CONST_A_3
+0x4C40 US_ALU_CONST_R_4
+0x4C44 US_ALU_CONST_G_4
+0x4C48 US_ALU_CONST_B_4
+0x4C4C US_ALU_CONST_A_4
+0x4C50 US_ALU_CONST_R_5
+0x4C54 US_ALU_CONST_G_5
+0x4C58 US_ALU_CONST_B_5
+0x4C5C US_ALU_CONST_A_5
+0x4C60 US_ALU_CONST_R_6
+0x4C64 US_ALU_CONST_G_6
+0x4C68 US_ALU_CONST_B_6
+0x4C6C US_ALU_CONST_A_6
+0x4C70 US_ALU_CONST_R_7
+0x4C74 US_ALU_CONST_G_7
+0x4C78 US_ALU_CONST_B_7
+0x4C7C US_ALU_CONST_A_7
+0x4C80 US_ALU_CONST_R_8
+0x4C84 US_ALU_CONST_G_8
+0x4C88 US_ALU_CONST_B_8
+0x4C8C US_ALU_CONST_A_8
+0x4C90 US_ALU_CONST_R_9
+0x4C94 US_ALU_CONST_G_9
+0x4C98 US_ALU_CONST_B_9
+0x4C9C US_ALU_CONST_A_9
+0x4CA0 US_ALU_CONST_R_10
+0x4CA4 US_ALU_CONST_G_10
+0x4CA8 US_ALU_CONST_B_10
+0x4CAC US_ALU_CONST_A_10
+0x4CB0 US_ALU_CONST_R_11
+0x4CB4 US_ALU_CONST_G_11
+0x4CB8 US_ALU_CONST_B_11
+0x4CBC US_ALU_CONST_A_11
+0x4CC0 US_ALU_CONST_R_12
+0x4CC4 US_ALU_CONST_G_12
+0x4CC8 US_ALU_CONST_B_12
+0x4CCC US_ALU_CONST_A_12
+0x4CD0 US_ALU_CONST_R_13
+0x4CD4 US_ALU_CONST_G_13
+0x4CD8 US_ALU_CONST_B_13
+0x4CDC US_ALU_CONST_A_13
+0x4CE0 US_ALU_CONST_R_14
+0x4CE4 US_ALU_CONST_G_14
+0x4CE8 US_ALU_CONST_B_14
+0x4CEC US_ALU_CONST_A_14
+0x4CF0 US_ALU_CONST_R_15
+0x4CF4 US_ALU_CONST_G_15
+0x4CF8 US_ALU_CONST_B_15
+0x4CFC US_ALU_CONST_A_15
+0x4D00 US_ALU_CONST_R_16
+0x4D04 US_ALU_CONST_G_16
+0x4D08 US_ALU_CONST_B_16
+0x4D0C US_ALU_CONST_A_16
+0x4D10 US_ALU_CONST_R_17
+0x4D14 US_ALU_CONST_G_17
+0x4D18 US_ALU_CONST_B_17
+0x4D1C US_ALU_CONST_A_17
+0x4D20 US_ALU_CONST_R_18
+0x4D24 US_ALU_CONST_G_18
+0x4D28 US_ALU_CONST_B_18
+0x4D2C US_ALU_CONST_A_18
+0x4D30 US_ALU_CONST_R_19
+0x4D34 US_ALU_CONST_G_19
+0x4D38 US_ALU_CONST_B_19
+0x4D3C US_ALU_CONST_A_19
+0x4D40 US_ALU_CONST_R_20
+0x4D44 US_ALU_CONST_G_20
+0x4D48 US_ALU_CONST_B_20
+0x4D4C US_ALU_CONST_A_20
+0x4D50 US_ALU_CONST_R_21
+0x4D54 US_ALU_CONST_G_21
+0x4D58 US_ALU_CONST_B_21
+0x4D5C US_ALU_CONST_A_21
+0x4D60 US_ALU_CONST_R_22
+0x4D64 US_ALU_CONST_G_22
+0x4D68 US_ALU_CONST_B_22
+0x4D6C US_ALU_CONST_A_22
+0x4D70 US_ALU_CONST_R_23
+0x4D74 US_ALU_CONST_G_23
+0x4D78 US_ALU_CONST_B_23
+0x4D7C US_ALU_CONST_A_23
+0x4D80 US_ALU_CONST_R_24
+0x4D84 US_ALU_CONST_G_24
+0x4D88 US_ALU_CONST_B_24
+0x4D8C US_ALU_CONST_A_24
+0x4D90 US_ALU_CONST_R_25
+0x4D94 US_ALU_CONST_G_25
+0x4D98 US_ALU_CONST_B_25
+0x4D9C US_ALU_CONST_A_25
+0x4DA0 US_ALU_CONST_R_26
+0x4DA4 US_ALU_CONST_G_26
+0x4DA8 US_ALU_CONST_B_26
+0x4DAC US_ALU_CONST_A_26
+0x4DB0 US_ALU_CONST_R_27
+0x4DB4 US_ALU_CONST_G_27
+0x4DB8 US_ALU_CONST_B_27
+0x4DBC US_ALU_CONST_A_27
+0x4DC0 US_ALU_CONST_R_28
+0x4DC4 US_ALU_CONST_G_28
+0x4DC8 US_ALU_CONST_B_28
+0x4DCC US_ALU_CONST_A_28
+0x4DD0 US_ALU_CONST_R_29
+0x4DD4 US_ALU_CONST_G_29
+0x4DD8 US_ALU_CONST_B_29
+0x4DDC US_ALU_CONST_A_29
+0x4DE0 US_ALU_CONST_R_30
+0x4DE4 US_ALU_CONST_G_30
+0x4DE8 US_ALU_CONST_B_30
+0x4DEC US_ALU_CONST_A_30
+0x4DF0 US_ALU_CONST_R_31
+0x4DF4 US_ALU_CONST_G_31
+0x4DF8 US_ALU_CONST_B_31
+0x4DFC US_ALU_CONST_A_31
+0x4E04 RB3D_BLENDCNTL_R3
+0x4E08 RB3D_ABLENDCNTL_R3
+0x4E0C RB3D_COLOR_CHANNEL_MASK
+0x4E10 RB3D_CONSTANT_COLOR
+0x4E14 RB3D_COLOR_CLEAR_VALUE
+0x4E18 RB3D_ROPCNTL_R3
+0x4E1C RB3D_CLRCMP_FLIPE_R3
+0x4E20 RB3D_CLRCMP_CLR_R3
+0x4E24 RB3D_CLRCMP_MSK_R3
+0x4E48 RB3D_DEBUG_CTL
+0x4E4C RB3D_DSTCACHE_CTLSTAT_R3
+0x4E50 RB3D_DITHER_CTL
+0x4E54 RB3D_CMASK_OFFSET0
+0x4E58 RB3D_CMASK_OFFSET1
+0x4E5C RB3D_CMASK_OFFSET2
+0x4E60 RB3D_CMASK_OFFSET3
+0x4E64 RB3D_CMASK_PITCH0
+0x4E68 RB3D_CMASK_PITCH1
+0x4E6C RB3D_CMASK_PITCH2
+0x4E70 RB3D_CMASK_PITCH3
+0x4E74 RB3D_CMASK_WRINDEX
+0x4E78 RB3D_CMASK_DWORD
+0x4E7C RB3D_CMASK_RDINDEX
+0x4E80 RB3D_AARESOLVE_OFFSET
+0x4E84 RB3D_AARESOLVE_PITCH
+0x4E88 RB3D_AARESOLVE_CTL
+0x4EA0 RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD
+0x4EA4 RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD
+0x4F04 ZB_ZSTENCILCNTL
+0x4F08 ZB_STENCILREFMASK
+0x4F14 ZB_ZTOP
+0x4F18 ZB_ZCACHE_CTLSTAT
+0x4F1C ZB_BW_CNTL
+0x4F28 ZB_DEPTHCLEARVALUE
+0x4F30 ZB_ZMASK_OFFSET
+0x4F34 ZB_ZMASK_PITCH
+0x4F38 ZB_ZMASK_WRINDEX
+0x4F3C ZB_ZMASK_DWORD
+0x4F40 ZB_ZMASK_RDINDEX
+0x4F44 ZB_HIZ_OFFSET
+0x4F48 ZB_HIZ_WRINDEX
+0x4F4C ZB_HIZ_DWORD
+0x4F50 ZB_HIZ_RDINDEX
+0x4F54 ZB_HIZ_PITCH
+0x4F58 ZB_ZPASS_DATA
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rs600 b/drivers/gpu/drm/radeon/reg_srcs/rs600
index 8e3c0b807add..6801b865d1c4 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/rs600
+++ b/drivers/gpu/drm/radeon/reg_srcs/rs600
@@ -153,7 +153,7 @@ rs600 0x6d40
 0x42A4 SU_POLY_OFFSET_FRONT_SCALE
 0x42A8 SU_POLY_OFFSET_FRONT_OFFSET
 0x42AC SU_POLY_OFFSET_BACK_SCALE
-0x42B0 SU_POLY_OFFSET_BACK_OFFSET 
+0x42B0 SU_POLY_OFFSET_BACK_OFFSET
 0x42B4 SU_POLY_OFFSET_ENABLE
 0x42B8 SU_CULL_MODE
 0x42C0 SU_DEPTH_SCALE
@@ -291,6 +291,8 @@ rs600 0x6d40
 0x46AC US_OUT_FMT_2
 0x46B0 US_OUT_FMT_3
 0x46B4 US_W_FMT
+0x46B8 US_CODE_BANK
+0x46BC US_CODE_EXT
 0x46C0 US_ALU_RGB_ADDR_0
 0x46C4 US_ALU_RGB_ADDR_1
 0x46C8 US_ALU_RGB_ADDR_2
@@ -547,6 +549,70 @@ rs600 0x6d40
 0x4AB4 US_ALU_ALPHA_INST_61
 0x4AB8 US_ALU_ALPHA_INST_62
 0x4ABC US_ALU_ALPHA_INST_63
+0x4AC0 US_ALU_EXT_ADDR_0
+0x4AC4 US_ALU_EXT_ADDR_1
+0x4AC8 US_ALU_EXT_ADDR_2
+0x4ACC US_ALU_EXT_ADDR_3
+0x4AD0 US_ALU_EXT_ADDR_4
+0x4AD4 US_ALU_EXT_ADDR_5
+0x4AD8 US_ALU_EXT_ADDR_6
+0x4ADC US_ALU_EXT_ADDR_7
+0x4AE0 US_ALU_EXT_ADDR_8
+0x4AE4 US_ALU_EXT_ADDR_9
+0x4AE8 US_ALU_EXT_ADDR_10
+0x4AEC US_ALU_EXT_ADDR_11
+0x4AF0 US_ALU_EXT_ADDR_12
+0x4AF4 US_ALU_EXT_ADDR_13
+0x4AF8 US_ALU_EXT_ADDR_14
+0x4AFC US_ALU_EXT_ADDR_15
+0x4B00 US_ALU_EXT_ADDR_16
+0x4B04 US_ALU_EXT_ADDR_17
+0x4B08 US_ALU_EXT_ADDR_18
+0x4B0C US_ALU_EXT_ADDR_19
+0x4B10 US_ALU_EXT_ADDR_20
+0x4B14 US_ALU_EXT_ADDR_21
+0x4B18 US_ALU_EXT_ADDR_22
+0x4B1C US_ALU_EXT_ADDR_23
+0x4B20 US_ALU_EXT_ADDR_24
+0x4B24 US_ALU_EXT_ADDR_25
+0x4B28 US_ALU_EXT_ADDR_26
+0x4B2C US_ALU_EXT_ADDR_27
+0x4B30 US_ALU_EXT_ADDR_28
+0x4B34 US_ALU_EXT_ADDR_29
+0x4B38 US_ALU_EXT_ADDR_30
+0x4B3C US_ALU_EXT_ADDR_31
+0x4B40 US_ALU_EXT_ADDR_32
+0x4B44 US_ALU_EXT_ADDR_33
+0x4B48 US_ALU_EXT_ADDR_34
+0x4B4C US_ALU_EXT_ADDR_35
+0x4B50 US_ALU_EXT_ADDR_36
+0x4B54 US_ALU_EXT_ADDR_37
+0x4B58 US_ALU_EXT_ADDR_38
+0x4B5C US_ALU_EXT_ADDR_39
+0x4B60 US_ALU_EXT_ADDR_40
+0x4B64 US_ALU_EXT_ADDR_41
+0x4B68 US_ALU_EXT_ADDR_42
+0x4B6C US_ALU_EXT_ADDR_43
+0x4B70 US_ALU_EXT_ADDR_44
+0x4B74 US_ALU_EXT_ADDR_45
+0x4B78 US_ALU_EXT_ADDR_46
+0x4B7C US_ALU_EXT_ADDR_47
+0x4B80 US_ALU_EXT_ADDR_48
+0x4B84 US_ALU_EXT_ADDR_49
+0x4B88 US_ALU_EXT_ADDR_50
+0x4B8C US_ALU_EXT_ADDR_51
+0x4B90 US_ALU_EXT_ADDR_52
+0x4B94 US_ALU_EXT_ADDR_53
+0x4B98 US_ALU_EXT_ADDR_54
+0x4B9C US_ALU_EXT_ADDR_55
+0x4BA0 US_ALU_EXT_ADDR_56
+0x4BA4 US_ALU_EXT_ADDR_57
+0x4BA8 US_ALU_EXT_ADDR_58
+0x4BAC US_ALU_EXT_ADDR_59
+0x4BB0 US_ALU_EXT_ADDR_60
+0x4BB4 US_ALU_EXT_ADDR_61
+0x4BB8 US_ALU_EXT_ADDR_62
+0x4BBC US_ALU_EXT_ADDR_63
 0x4BC0 FG_FOG_BLEND
 0x4BC4 FG_FOG_FACTOR
 0x4BC8 FG_FOG_COLOR_R
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rv515 b/drivers/gpu/drm/radeon/reg_srcs/rv515
index 0102a0d5735c..38abf63bf2cd 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/rv515
+++ b/drivers/gpu/drm/radeon/reg_srcs/rv515
@@ -161,7 +161,12 @@ rv515 0x6d40
 0x401C GB_SELECT
 0x4020 GB_AA_CONFIG
 0x4024 GB_FIFO_SIZE
+0x4028 GB_Z_PEQ_CONFIG
 0x4100 TX_INVALTAGS
+0x4114 SU_TEX_WRAP_PS3
+0x4118 PS3_ENABLE
+0x411c PS3_VTX_FMT
+0x4120 PS3_TEX_SOURCE
 0x4200 GA_POINT_S0
 0x4204 GA_POINT_T0
 0x4208 GA_POINT_S1
@@ -171,6 +176,7 @@ rv515 0x6d40
 0x4230 GA_POINT_MINMAX
 0x4234 GA_LINE_CNTL
 0x4238 GA_LINE_STIPPLE_CONFIG
+0x4258 GA_COLOR_CONTROL_PS3
 0x4260 GA_LINE_STIPPLE_VALUE
 0x4264 GA_LINE_S0
 0x4268 GA_LINE_S1
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
index 368415df5f3a..9f5418983e2a 100644
--- a/drivers/gpu/drm/radeon/rs400.c
+++ b/drivers/gpu/drm/radeon/rs400.c
@@ -356,6 +356,7 @@ static int rs400_mc_init(struct radeon_device *rdev)
         rdev->mc.vram_location = G_00015C_MC_FB_START(tmp) << 16;
         rdev->mc.gtt_location = 0xFFFFFFFFUL;
         r = radeon_mc_setup(rdev);
+        rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev);
         if (r)
                 return r;
         return 0;
@@ -395,6 +396,7 @@ static int rs400_startup(struct radeon_device *rdev)
                 return r;
         /* Enable IRQ */
         r100_irq_set(rdev);
+        rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
         /* 1M ring buffer */
         r = r100_cp_init(rdev, 1024 * 1024);
         if (r) {
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 4f8ea4260572..d5255751e7b3 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -56,6 +56,7 @@ int rs600_mc_init(struct radeon_device *rdev)
         rdev->mc.vram_location = G_000004_MC_FB_START(tmp) << 16;
         rdev->mc.gtt_location = 0xffffffffUL;
         r = radeon_mc_setup(rdev);
+        rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
         if (r)
                 return r;
         return 0;
@@ -134,7 +135,8 @@ void rs600_hpd_init(struct radeon_device *rdev)
                         break;
                 }
         }
-        rs600_irq_set(rdev);
+        if (rdev->irq.installed)
+                rs600_irq_set(rdev);
 }
 
 void rs600_hpd_fini(struct radeon_device *rdev)
@@ -315,6 +317,11 @@ int rs600_irq_set(struct radeon_device *rdev)
         u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
                 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
 
+        if (!rdev->irq.installed) {
+                WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
+                WREG32(R_000040_GEN_INT_CNTL, 0);
+                return -EINVAL;
+        }
         if (rdev->irq.sw_int) {
                 tmp |= S_000040_SW_INT_EN(1);
         }
@@ -396,7 +403,7 @@ int rs600_irq_process(struct radeon_device *rdev)
         }
         while (status || r500_disp_int) {
                 /* SW interrupt */
-                if (G_000040_SW_INT_EN(status))
+                if (G_000044_SW_INT(status))
                         radeon_fence_process(rdev);
                 /* Vertical blank interrupts */
                 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int))
@@ -553,6 +560,7 @@ static int rs600_startup(struct radeon_device *rdev)
                 return r;
         /* Enable IRQ */
         rs600_irq_set(rdev);
+        rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
         /* 1M ring buffer */
         r = r100_cp_init(rdev, 1024 * 1024);
         if (r) {
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index 1e22f52d6039..cd31da913771 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -172,6 +172,7 @@ static int rs690_mc_init(struct radeon_device *rdev)
         rdev->mc.vram_location = G_000100_MC_FB_START(tmp) << 16;
         rdev->mc.gtt_location = 0xFFFFFFFFUL;
         r = radeon_mc_setup(rdev);
+        rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
         if (r)
                 return r;
         return 0;
@@ -625,6 +626,7 @@ static int rs690_startup(struct radeon_device *rdev)
                 return r;
         /* Enable IRQ */
         rs600_irq_set(rdev);
+        rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
         /* 1M ring buffer */
         r = r100_cp_init(rdev, 1024 * 1024);
         if (r) {
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 59632a506b46..62756717b044 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -479,6 +479,7 @@ static int rv515_startup(struct radeon_device *rdev)
         }
         /* Enable IRQ */
         rs600_irq_set(rdev);
+        rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
         /* 1M ring buffer */
         r = r100_cp_init(rdev, 1024 * 1024);
         if (r) {
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 3bcb66e52786..59c71245fb91 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -1096,8 +1096,7 @@ void rv770_fini(struct radeon_device *rdev)
         radeon_gem_fini(rdev);
         radeon_fence_driver_fini(rdev);
         radeon_clocks_fini(rdev);
-        if (rdev->flags & RADEON_IS_AGP)
-                radeon_agp_fini(rdev);
+        radeon_agp_fini(rdev);
         radeon_bo_fini(rdev);
         radeon_atombios_fini(rdev);
         kfree(rdev->bios);
diff --git a/drivers/gpu/drm/savage/savage_drv.c b/drivers/gpu/drm/savage/savage_drv.c
index eee52aa92a7c..021de44c15ab 100644
--- a/drivers/gpu/drm/savage/savage_drv.c
+++ b/drivers/gpu/drm/savage/savage_drv.c
@@ -50,7 +50,7 @@ static struct drm_driver driver = {
                  .owner = THIS_MODULE,
                  .open = drm_open,
                  .release = drm_release,
-                 .ioctl = drm_ioctl,
+                 .unlocked_ioctl = drm_ioctl,
                  .mmap = drm_mmap,
                  .poll = drm_poll,
                  .fasync = drm_fasync,
diff --git a/drivers/gpu/drm/sis/sis_drv.c b/drivers/gpu/drm/sis/sis_drv.c
index e725cc0b1155..4fd1f067d380 100644
--- a/drivers/gpu/drm/sis/sis_drv.c
+++ b/drivers/gpu/drm/sis/sis_drv.c
@@ -80,7 +80,7 @@ static struct drm_driver driver = {
                  .owner = THIS_MODULE,
                  .open = drm_open,
                  .release = drm_release,
-                 .ioctl = drm_ioctl,
+                 .unlocked_ioctl = drm_ioctl,
                  .mmap = drm_mmap,
                  .poll = drm_poll,
                  .fasync = drm_fasync,
diff --git a/drivers/gpu/drm/tdfx/tdfx_drv.c b/drivers/gpu/drm/tdfx/tdfx_drv.c
index 012ff2e356b2..ec5a43e65722 100644
--- a/drivers/gpu/drm/tdfx/tdfx_drv.c
+++ b/drivers/gpu/drm/tdfx/tdfx_drv.c
@@ -48,7 +48,7 @@ static struct drm_driver driver = {
                  .owner = THIS_MODULE,
                  .open = drm_open,
                  .release = drm_release,
-                 .ioctl = drm_ioctl,
+                 .unlocked_ioctl = drm_ioctl,
                  .mmap = drm_mmap,
                  .poll = drm_poll,
                  .fasync = drm_fasync,
diff --git a/drivers/gpu/drm/via/via_drv.c b/drivers/gpu/drm/via/via_drv.c
index bc2f51843005..7a1b210401e0 100644
--- a/drivers/gpu/drm/via/via_drv.c
+++ b/drivers/gpu/drm/via/via_drv.c
@@ -58,7 +58,7 @@ static struct drm_driver driver = {
                 .owner = THIS_MODULE,
                 .open = drm_open,
                 .release = drm_release,
-                .ioctl = drm_ioctl,
+                .unlocked_ioctl = drm_ioctl,
                 .mmap = drm_mmap,
                 .poll = drm_poll,
                 .fasync = drm_fasync,
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
index 7b48bb3b63b2..1db1ef30be2b 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
@@ -103,37 +103,39 @@
  */
 
 static struct drm_ioctl_desc vmw_ioctls[] = {
-        VMW_IOCTL_DEF(DRM_IOCTL_VMW_GET_PARAM, vmw_getparam_ioctl, 0),
+        VMW_IOCTL_DEF(DRM_IOCTL_VMW_GET_PARAM, vmw_getparam_ioctl,
+                      DRM_AUTH | DRM_UNLOCKED),
         VMW_IOCTL_DEF(DRM_IOCTL_VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
-                      0),
+                      DRM_AUTH | DRM_UNLOCKED),
         VMW_IOCTL_DEF(DRM_IOCTL_VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
-                      0),
+                      DRM_AUTH | DRM_UNLOCKED),
         VMW_IOCTL_DEF(DRM_IOCTL_VMW_CURSOR_BYPASS,
-                      vmw_kms_cursor_bypass_ioctl, 0),
+                      vmw_kms_cursor_bypass_ioctl,
+                      DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
 
         VMW_IOCTL_DEF(DRM_IOCTL_VMW_CONTROL_STREAM, vmw_overlay_ioctl,
-                      0),
+                      DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
         VMW_IOCTL_DEF(DRM_IOCTL_VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
-                      0),
+                      DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
         VMW_IOCTL_DEF(DRM_IOCTL_VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
-                      0),
+                      DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
 
         VMW_IOCTL_DEF(DRM_IOCTL_VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
-                      0),
+                      DRM_AUTH | DRM_UNLOCKED),
         VMW_IOCTL_DEF(DRM_IOCTL_VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
-                      0),
+                      DRM_AUTH | DRM_UNLOCKED),
         VMW_IOCTL_DEF(DRM_IOCTL_VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
-                      0),
+                      DRM_AUTH | DRM_UNLOCKED),
         VMW_IOCTL_DEF(DRM_IOCTL_VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
-                      0),
+                      DRM_AUTH | DRM_UNLOCKED),
         VMW_IOCTL_DEF(DRM_IOCTL_VMW_REF_SURFACE, vmw_surface_reference_ioctl,
-                      0),
+                      DRM_AUTH | DRM_UNLOCKED),
         VMW_IOCTL_DEF(DRM_IOCTL_VMW_EXECBUF, vmw_execbuf_ioctl,
-                      0),
+                      DRM_AUTH | DRM_UNLOCKED),
         VMW_IOCTL_DEF(DRM_IOCTL_VMW_FIFO_DEBUG, vmw_fifo_debug_ioctl,
-                      0),
+                      DRM_AUTH | DRM_ROOT_ONLY | DRM_MASTER | DRM_UNLOCKED),
         VMW_IOCTL_DEF(DRM_IOCTL_VMW_FENCE_WAIT, vmw_fence_wait_ioctl,
-                      0)
+                      DRM_AUTH | DRM_UNLOCKED)
 };
 
 static struct pci_device_id vmw_pci_id_list[] = {
@@ -460,11 +462,9 @@ static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
         struct drm_file *file_priv = filp->private_data;
         struct drm_device *dev = file_priv->minor->dev;
         unsigned int nr = DRM_IOCTL_NR(cmd);
-        long ret;
 
         /*
-         * The driver private ioctls and TTM ioctls should be
-         * thread-safe.
+         * Do extra checking on driver private ioctls.
          */
 
         if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
@@ -477,18 +477,9 @@ static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
                                   nr - DRM_COMMAND_BASE);
                         return -EINVAL;
                 }
-                return drm_ioctl(filp->f_path.dentry->d_inode,
-                                 filp, cmd, arg);
         }
 
-        /*
-         * Not all old drm ioctls are thread-safe.
-         */
-
-        lock_kernel();
-        ret = drm_ioctl(filp->f_path.dentry->d_inode, filp, cmd, arg);
-        unlock_kernel();
-        return ret;
+        return drm_ioctl(filp, cmd, arg);
 }
 
 static int vmw_firstopen(struct drm_device *dev)
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
index 43546d09d1b0..e61bd85b6975 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
@@ -123,6 +123,7 @@ struct vmw_sw_context{
         uint32_t last_cid;
         bool cid_valid;
         uint32_t last_sid;
+        uint32_t sid_translation;
         bool sid_valid;
         struct ttm_object_file *tfile;
         struct list_head validate_nodes;
@@ -317,9 +318,10 @@ extern void vmw_surface_res_free(struct vmw_resource *res);
 extern int vmw_surface_init(struct vmw_private *dev_priv,
                             struct vmw_surface *srf,
                             void (*res_free) (struct vmw_resource *res));
-extern int vmw_user_surface_lookup(struct vmw_private *dev_priv,
-                                   struct ttm_object_file *tfile,
-                                   int sid, struct vmw_surface **out);
+extern int vmw_user_surface_lookup_handle(struct vmw_private *dev_priv,
+                                          struct ttm_object_file *tfile,
+                                          uint32_t handle,
+                                          struct vmw_surface **out);
 extern int vmw_surface_destroy_ioctl(struct drm_device *dev, void *data,
                                      struct drm_file *file_priv);
 extern int vmw_surface_define_ioctl(struct drm_device *dev, void *data,
@@ -328,7 +330,7 @@ extern int vmw_surface_reference_ioctl(struct drm_device *dev, void *data,
                                        struct drm_file *file_priv);
 extern int vmw_surface_check(struct vmw_private *dev_priv,
                              struct ttm_object_file *tfile,
-                             int id);
+                             uint32_t handle, int *id);
 extern void vmw_dmabuf_bo_free(struct ttm_buffer_object *bo);
 extern int vmw_dmabuf_init(struct vmw_private *dev_priv,
                            struct vmw_dma_buffer *vmw_bo,
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
index 7a39f3e6dc2c..2e92da567403 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
@@ -73,21 +73,32 @@ static int vmw_cmd_cid_check(struct vmw_private *dev_priv,
 
 static int vmw_cmd_sid_check(struct vmw_private *dev_priv,
                              struct vmw_sw_context *sw_context,
-                             uint32_t sid)
+                             uint32_t *sid)
 {
-        if (unlikely((!sw_context->sid_valid || sid != sw_context->last_sid) &&
-                     sid != SVGA3D_INVALID_ID)) {
-                int ret = vmw_surface_check(dev_priv, sw_context->tfile, sid);
+        if (*sid == SVGA3D_INVALID_ID)
+                return 0;
+
+        if (unlikely((!sw_context->sid_valid  ||
+                      *sid != sw_context->last_sid))) {
+                int real_id;
+                int ret = vmw_surface_check(dev_priv, sw_context->tfile,
+                                            *sid, &real_id);
 
                 if (unlikely(ret != 0)) {
-                        DRM_ERROR("Could ot find or use surface %u\n",
-                                  (unsigned) sid);
+                        DRM_ERROR("Could ot find or use surface 0x%08x "
+                                  "address 0x%08lx\n",
+                                  (unsigned int) *sid,
+                                  (unsigned long) sid);
                         return ret;
                 }
 
-                sw_context->last_sid = sid;
+                sw_context->last_sid = *sid;
                 sw_context->sid_valid = true;
-        }
+                *sid = real_id;
+                sw_context->sid_translation = real_id;
+        } else
+                *sid = sw_context->sid_translation;
+
         return 0;
 }
 
@@ -107,7 +118,8 @@ static int vmw_cmd_set_render_target_check(struct vmw_private *dev_priv,
                 return ret;
 
         cmd = container_of(header, struct vmw_sid_cmd, header);
-        return vmw_cmd_sid_check(dev_priv, sw_context, cmd->body.target.sid);
+        ret = vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.target.sid);
+        return ret;
 }
 
 static int vmw_cmd_surface_copy_check(struct vmw_private *dev_priv,
@@ -121,10 +133,10 @@ static int vmw_cmd_surface_copy_check(struct vmw_private *dev_priv,
         int ret;
 
         cmd = container_of(header, struct vmw_sid_cmd, header);
-        ret = vmw_cmd_sid_check(dev_priv, sw_context, cmd->body.src.sid);
+        ret = vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.src.sid);
         if (unlikely(ret != 0))
                 return ret;
-        return vmw_cmd_sid_check(dev_priv, sw_context, cmd->body.dest.sid);
+        return vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.dest.sid);
 }
 
 static int vmw_cmd_stretch_blt_check(struct vmw_private *dev_priv,
@@ -138,10 +150,10 @@ static int vmw_cmd_stretch_blt_check(struct vmw_private *dev_priv,
         int ret;
 
         cmd = container_of(header, struct vmw_sid_cmd, header);
-        ret = vmw_cmd_sid_check(dev_priv, sw_context, cmd->body.src.sid);
+        ret = vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.src.sid);
         if (unlikely(ret != 0))
                 return ret;
-        return vmw_cmd_sid_check(dev_priv, sw_context, cmd->body.dest.sid);
+        return vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.dest.sid);
 }
 
 static int vmw_cmd_blt_surf_screen_check(struct vmw_private *dev_priv,
@@ -154,7 +166,7 @@ static int vmw_cmd_blt_surf_screen_check(struct vmw_private *dev_priv,
         } *cmd;
 
         cmd = container_of(header, struct vmw_sid_cmd, header);
-        return vmw_cmd_sid_check(dev_priv, sw_context, cmd->body.srcImage.sid);
+        return vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.srcImage.sid);
 }
 
 static int vmw_cmd_present_check(struct vmw_private *dev_priv,
@@ -167,7 +179,7 @@ static int vmw_cmd_present_check(struct vmw_private *dev_priv,
         } *cmd;
 
         cmd = container_of(header, struct vmw_sid_cmd, header);
-        return vmw_cmd_sid_check(dev_priv, sw_context, cmd->body.sid);
+        return vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.sid);
 }
 
 static int vmw_cmd_dma(struct vmw_private *dev_priv,
@@ -187,12 +199,7 @@ static int vmw_cmd_dma(struct vmw_private *dev_priv,
         uint32_t cur_validate_node;
         struct ttm_validate_buffer *val_buf;
 
-
         cmd = container_of(header, struct vmw_dma_cmd, header);
-        ret = vmw_cmd_sid_check(dev_priv, sw_context, cmd->dma.host.sid);
-        if (unlikely(ret != 0))
-                return ret;
-
         handle = cmd->dma.guest.ptr.gmrId;
         ret = vmw_user_dmabuf_lookup(sw_context->tfile, handle, &vmw_bo);
         if (unlikely(ret != 0)) {
@@ -228,14 +235,23 @@ static int vmw_cmd_dma(struct vmw_private *dev_priv,
                 ++sw_context->cur_val_buf;
         }
 
-        ret = vmw_user_surface_lookup(dev_priv, sw_context->tfile,
-                                      cmd->dma.host.sid, &srf);
+        ret = vmw_user_surface_lookup_handle(dev_priv, sw_context->tfile,
+                                             cmd->dma.host.sid, &srf);
         if (ret) {
                 DRM_ERROR("could not find surface\n");
                 goto out_no_reloc;
         }
 
+        /**
+         * Patch command stream with device SID.
+         */
+
+        cmd->dma.host.sid = srf->res.id;
         vmw_kms_cursor_snoop(srf, sw_context->tfile, bo, header);
+        /**
+         * FIXME: May deadlock here when called from the
+         * command parsing code.
+         */
         vmw_surface_unreference(&srf);
 
 out_no_reloc:
@@ -243,6 +259,90 @@ out_no_reloc:
         return ret;
 }
 
+static int vmw_cmd_draw(struct vmw_private *dev_priv,
+                        struct vmw_sw_context *sw_context,
+                        SVGA3dCmdHeader *header)
+{
+        struct vmw_draw_cmd {
+                SVGA3dCmdHeader header;
+                SVGA3dCmdDrawPrimitives body;
+        } *cmd;
+        SVGA3dVertexDecl *decl = (SVGA3dVertexDecl *)(
+                (unsigned long)header + sizeof(*cmd));
+        SVGA3dPrimitiveRange *range;
+        uint32_t i;
+        uint32_t maxnum;
+        int ret;
+
+        ret = vmw_cmd_cid_check(dev_priv, sw_context, header);
+        if (unlikely(ret != 0))
+                return ret;
+
+        cmd = container_of(header, struct vmw_draw_cmd, header);
+        maxnum = (header->size - sizeof(cmd->body)) / sizeof(*decl);
+
+        if (unlikely(cmd->body.numVertexDecls > maxnum)) {
+                DRM_ERROR("Illegal number of vertex declarations.\n");
+                return -EINVAL;
+        }
+
+        for (i = 0; i < cmd->body.numVertexDecls; ++i, ++decl) {
+                ret = vmw_cmd_sid_check(dev_priv, sw_context,
+                                        &decl->array.surfaceId);
+                if (unlikely(ret != 0))
+                        return ret;
+        }
+
+        maxnum = (header->size - sizeof(cmd->body) -
+                  cmd->body.numVertexDecls * sizeof(*decl)) / sizeof(*range);
+        if (unlikely(cmd->body.numRanges > maxnum)) {
+                DRM_ERROR("Illegal number of index ranges.\n");
+                return -EINVAL;
+        }
+
+        range = (SVGA3dPrimitiveRange *) decl;
+        for (i = 0; i < cmd->body.numRanges; ++i, ++range) {
+                ret = vmw_cmd_sid_check(dev_priv, sw_context,
+                                        &range->indexArray.surfaceId);
+                if (unlikely(ret != 0))
+                        return ret;
+        }
+        return 0;
+}
+
+
+static int vmw_cmd_tex_state(struct vmw_private *dev_priv,
+                             struct vmw_sw_context *sw_context,
+                             SVGA3dCmdHeader *header)
+{
+        struct vmw_tex_state_cmd {
+                SVGA3dCmdHeader header;
+                SVGA3dCmdSetTextureState state;
+        };
+
+        SVGA3dTextureState *last_state = (SVGA3dTextureState *)
+          ((unsigned long) header + header->size + sizeof(header));
+        SVGA3dTextureState *cur_state = (SVGA3dTextureState *)
+                ((unsigned long) header + sizeof(struct vmw_tex_state_cmd));
+        int ret;
+
+        ret = vmw_cmd_cid_check(dev_priv, sw_context, header);
+        if (unlikely(ret != 0))
+                return ret;
+
+        for (; cur_state < last_state; ++cur_state) {
+                if (likely(cur_state->name != SVGA3D_TS_BIND_TEXTURE))
+                        continue;
+
+                ret = vmw_cmd_sid_check(dev_priv, sw_context,
+                                        &cur_state->value);
+                if (unlikely(ret != 0))
+                        return ret;
+        }
+
+        return 0;
+}
+
 
 typedef int (*vmw_cmd_func) (struct vmw_private *,
                              struct vmw_sw_context *,
@@ -264,7 +364,7 @@ static vmw_cmd_func vmw_cmd_funcs[SVGA_3D_CMD_MAX] = {
         VMW_CMD_DEF(SVGA_3D_CMD_SETRENDERSTATE, &vmw_cmd_cid_check),
         VMW_CMD_DEF(SVGA_3D_CMD_SETRENDERTARGET,
                     &vmw_cmd_set_render_target_check),
-        VMW_CMD_DEF(SVGA_3D_CMD_SETTEXTURESTATE, &vmw_cmd_cid_check),
+        VMW_CMD_DEF(SVGA_3D_CMD_SETTEXTURESTATE, &vmw_cmd_tex_state),
         VMW_CMD_DEF(SVGA_3D_CMD_SETMATERIAL, &vmw_cmd_cid_check),
         VMW_CMD_DEF(SVGA_3D_CMD_SETLIGHTDATA, &vmw_cmd_cid_check),
         VMW_CMD_DEF(SVGA_3D_CMD_SETLIGHTENABLED, &vmw_cmd_cid_check),
@@ -276,7 +376,7 @@ static vmw_cmd_func vmw_cmd_funcs[SVGA_3D_CMD_MAX] = {
         VMW_CMD_DEF(SVGA_3D_CMD_SHADER_DESTROY, &vmw_cmd_cid_check),
         VMW_CMD_DEF(SVGA_3D_CMD_SET_SHADER, &vmw_cmd_cid_check),
         VMW_CMD_DEF(SVGA_3D_CMD_SET_SHADER_CONST, &vmw_cmd_cid_check),
-        VMW_CMD_DEF(SVGA_3D_CMD_DRAW_PRIMITIVES, &vmw_cmd_cid_check),
+        VMW_CMD_DEF(SVGA_3D_CMD_DRAW_PRIMITIVES, &vmw_cmd_draw),
         VMW_CMD_DEF(SVGA_3D_CMD_SETSCISSORRECT, &vmw_cmd_cid_check),
         VMW_CMD_DEF(SVGA_3D_CMD_BEGIN_QUERY, &vmw_cmd_cid_check),
         VMW_CMD_DEF(SVGA_3D_CMD_END_QUERY, &vmw_cmd_cid_check),
@@ -291,6 +391,7 @@ static int vmw_cmd_check(struct vmw_private *dev_priv,
                          void *buf, uint32_t *size)
 {
         uint32_t cmd_id;
+        uint32_t size_remaining = *size;
         SVGA3dCmdHeader *header = (SVGA3dCmdHeader *) buf;
         int ret;
 
@@ -304,6 +405,9 @@ static int vmw_cmd_check(struct vmw_private *dev_priv,
         *size = le32_to_cpu(header->size) + sizeof(SVGA3dCmdHeader);
 
         cmd_id -= SVGA_3D_CMD_BASE;
+        if (unlikely(*size > size_remaining))
+                goto out_err;
+
         if (unlikely(cmd_id >= SVGA_3D_CMD_MAX - SVGA_3D_CMD_BASE))
                 goto out_err;
 
@@ -326,6 +430,7 @@ static int vmw_cmd_check_all(struct vmw_private *dev_priv,
         int ret;
 
         while (cur_size > 0) {
+                size = cur_size;
                 ret = vmw_cmd_check(dev_priv, sw_context, buf, &size);
                 if (unlikely(ret != 0))
                         return ret;
@@ -386,7 +491,7 @@ static int vmw_validate_single_buffer(struct vmw_private *dev_priv,
                 return 0;
 
         ret = vmw_gmr_bind(dev_priv, bo);
-        if (likely(ret == 0 || ret == -ERESTART))
+        if (likely(ret == 0 || ret == -ERESTARTSYS))
                 return ret;
 
 
@@ -429,7 +534,7 @@ int vmw_execbuf_ioctl(struct drm_device *dev, void *data,
 
         ret = mutex_lock_interruptible(&dev_priv->cmdbuf_mutex);
         if (unlikely(ret != 0)) {
-                ret = -ERESTART;
+                ret = -ERESTARTSYS;
                 goto out_no_cmd_mutex;
         }
 
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c b/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c
index 76b0693e2458..01feb48af333 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c
@@ -191,7 +191,7 @@ static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv,
                 }
                 schedule_timeout(1);
                 if (interruptible && signal_pending(current)) {
-                        ret = -ERESTART;
+                        ret = -ERESTARTSYS;
                         break;
                 }
         }
@@ -237,9 +237,7 @@ static int vmw_fifo_wait(struct vmw_private *dev_priv,
                     (dev_priv->fifo_queue,
                      !vmw_fifo_is_full(dev_priv, bytes), timeout);
 
-        if (unlikely(ret == -ERESTARTSYS))
-                ret = -ERESTART;
-        else if (unlikely(ret == 0))
+        if (unlikely(ret == 0))
                 ret = -EBUSY;
         else if (likely(ret > 0))
                 ret = 0;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_irq.c b/drivers/gpu/drm/vmwgfx/vmwgfx_irq.c
index 9e0f0306eedb..d40086fc8647 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_irq.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_irq.c
@@ -155,7 +155,7 @@ int vmw_fallback_wait(struct vmw_private *dev_priv,
                                             TASK_UNINTERRUPTIBLE);
                 }
                 if (interruptible && signal_pending(current)) {
-                        ret = -ERESTART;
+                        ret = -ERESTARTSYS;
                         break;
                 }
         }
@@ -218,9 +218,7 @@ int vmw_wait_fence(struct vmw_private *dev_priv,
                      vmw_fence_signaled(dev_priv, sequence),
                      timeout);
 
-        if (unlikely(ret == -ERESTARTSYS))
-                ret = -ERESTART;
-        else if (unlikely(ret == 0))
+        if (unlikely(ret == 0))
                 ret = -EBUSY;
         else if (likely(ret > 0))
                 ret = 0;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
index e9403be446fe..b1af76e371c3 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
@@ -106,8 +106,8 @@ int vmw_du_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
         int ret;
 
         if (handle) {
-                ret = vmw_user_surface_lookup(dev_priv, tfile,
-                                              handle, &surface);
+                ret = vmw_user_surface_lookup_handle(dev_priv, tfile,
+                                                     handle, &surface);
                 if (!ret) {
                         if (!surface->snooper.image) {
                                 DRM_ERROR("surface not suitable for cursor\n");
@@ -704,8 +704,8 @@ static struct drm_framebuffer *vmw_kms_fb_create(struct drm_device *dev,
         struct vmw_dma_buffer *bo = NULL;
         int ret;
 
-        ret = vmw_user_surface_lookup(dev_priv, tfile,
-                                      mode_cmd->handle, &surface);
+        ret = vmw_user_surface_lookup_handle(dev_priv, tfile,
+                                             mode_cmd->handle, &surface);
         if (ret)
                 goto try_dmabuf;
 
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
index a1ceed0c8e07..c012d5927f65 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
@@ -488,28 +488,44 @@ static void vmw_user_surface_free(struct vmw_resource *res)
         kfree(user_srf);
 }
 
-int vmw_user_surface_lookup(struct vmw_private *dev_priv,
-                            struct ttm_object_file *tfile,
-                            int sid, struct vmw_surface **out)
+int vmw_user_surface_lookup_handle(struct vmw_private *dev_priv,
+                                   struct ttm_object_file *tfile,
+                                   uint32_t handle, struct vmw_surface **out)
 {
         struct vmw_resource *res;
         struct vmw_surface *srf;
         struct vmw_user_surface *user_srf;
+        struct ttm_base_object *base;
+        int ret = -EINVAL;
 
-        res = vmw_resource_lookup(dev_priv, &dev_priv->surface_idr, sid);
-        if (unlikely(res == NULL))
+        base = ttm_base_object_lookup(tfile, handle);
+        if (unlikely(base == NULL))
                 return -EINVAL;
 
-        if (res->res_free != &vmw_user_surface_free)
-                return -EINVAL;
+        if (unlikely(base->object_type != VMW_RES_SURFACE))
+                goto out_bad_resource;
 
-        srf = container_of(res, struct vmw_surface, res);
-        user_srf = container_of(srf, struct vmw_user_surface, srf);
-        if (user_srf->base.tfile != tfile && !user_srf->base.shareable)
-                return -EPERM;
+        user_srf = container_of(base, struct vmw_user_surface, base);
+        srf = &user_srf->srf;
+        res = &srf->res;
+
+        read_lock(&dev_priv->resource_lock);
+
+        if (!res->avail || res->res_free != &vmw_user_surface_free) {
+                read_unlock(&dev_priv->resource_lock);
+                goto out_bad_resource;
+        }
+
+        kref_get(&res->kref);
+        read_unlock(&dev_priv->resource_lock);
 
         *out = srf;
-        return 0;
+        ret = 0;
+
+out_bad_resource:
+        ttm_base_object_unref(&base);
+
+        return ret;
 }
 
 static void vmw_user_surface_base_release(struct ttm_base_object **p_base)
@@ -526,35 +542,10 @@ static void vmw_user_surface_base_release(struct ttm_base_object **p_base)
 int vmw_surface_destroy_ioctl(struct drm_device *dev, void *data,
                               struct drm_file *file_priv)
 {
-        struct vmw_private *dev_priv = vmw_priv(dev);
-        struct vmw_resource *res;
-        struct vmw_surface *srf;
-        struct vmw_user_surface *user_srf;
         struct drm_vmw_surface_arg *arg = (struct drm_vmw_surface_arg *)data;
         struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
-        int ret = 0;
-
-        res = vmw_resource_lookup(dev_priv, &dev_priv->surface_idr, arg->sid);
-        if (unlikely(res == NULL))
-                return -EINVAL;
-
-        if (res->res_free != &vmw_user_surface_free) {
-                ret = -EINVAL;
-                goto out;
-        }
 
-        srf = container_of(res, struct vmw_surface, res);
-        user_srf = container_of(srf, struct vmw_user_surface, srf);
-        if (user_srf->base.tfile != tfile && !user_srf->base.shareable) {
-                ret = -EPERM;
-                goto out;
-        }
-
-        ttm_ref_object_base_unref(tfile, user_srf->base.hash.key,
-                                  TTM_REF_USAGE);
-out:
-        vmw_resource_unreference(&res);
-        return ret;
+        return ttm_ref_object_base_unref(tfile, arg->sid, TTM_REF_USAGE);
 }
 
 int vmw_surface_define_ioctl(struct drm_device *dev, void *data,
@@ -649,7 +640,10 @@ int vmw_surface_define_ioctl(struct drm_device *dev, void *data,
         }
         srf->snooper.crtc = NULL;
 
-        rep->sid = res->id;
+        rep->sid = user_srf->base.hash.key;
+        if (rep->sid == SVGA3D_INVALID_ID)
+                DRM_ERROR("Created bad Surface ID.\n");
+
         vmw_resource_unreference(&res);
         return 0;
 out_err1:
@@ -662,39 +656,33 @@ out_err0:
 int vmw_surface_reference_ioctl(struct drm_device *dev, void *data,
                                 struct drm_file *file_priv)
 {
-        struct vmw_private *dev_priv = vmw_priv(dev);
         union drm_vmw_surface_reference_arg *arg =
             (union drm_vmw_surface_reference_arg *)data;
         struct drm_vmw_surface_arg *req = &arg->req;
         struct drm_vmw_surface_create_req *rep = &arg->rep;
         struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
-        struct vmw_resource *res;
         struct vmw_surface *srf;
         struct vmw_user_surface *user_srf;
         struct drm_vmw_size __user *user_sizes;
-        int ret;
+        struct ttm_base_object *base;
+        int ret = -EINVAL;
 
-        res = vmw_resource_lookup(dev_priv, &dev_priv->surface_idr, req->sid);
-        if (unlikely(res == NULL))
+        base = ttm_base_object_lookup(tfile, req->sid);
+        if (unlikely(base == NULL)) {
+                DRM_ERROR("Could not find surface to reference.\n");
                 return -EINVAL;
-
-        if (res->res_free != &vmw_user_surface_free) {
-                ret = -EINVAL;
-                goto out;
         }
 
-        srf = container_of(res, struct vmw_surface, res);
-        user_srf = container_of(srf, struct vmw_user_surface, srf);
-        if (user_srf->base.tfile != tfile && !user_srf->base.shareable) {
-                DRM_ERROR("Tried to reference none shareable surface\n");
-                ret = -EPERM;
-                goto out;
-        }
+        if (unlikely(base->object_type != VMW_RES_SURFACE))
+                goto out_bad_resource;
+
+        user_srf = container_of(base, struct vmw_user_surface, base);
+        srf = &user_srf->srf;
 
         ret = ttm_ref_object_add(tfile, &user_srf->base, TTM_REF_USAGE, NULL);
         if (unlikely(ret != 0)) {
                 DRM_ERROR("Could not add a reference to a surface.\n");
-                goto out;
+                goto out_no_reference;
         }
 
         rep->flags = srf->flags;
@@ -706,40 +694,43 @@ int vmw_surface_reference_ioctl(struct drm_device *dev, void *data,
         if (user_sizes)
                 ret = copy_to_user(user_sizes, srf->sizes,
                                    srf->num_sizes * sizeof(*srf->sizes));
-        if (unlikely(ret != 0)) {
+        if (unlikely(ret != 0))
                 DRM_ERROR("copy_to_user failed %p %u\n",
                           user_sizes, srf->num_sizes);
-                /**
-                 * FIXME: Unreference surface here?
-                 */
-                goto out;
-        }
-out:
-        vmw_resource_unreference(&res);
+out_bad_resource:
+out_no_reference:
+        ttm_base_object_unref(&base);
+
         return ret;
 }
 
 int vmw_surface_check(struct vmw_private *dev_priv,
                       struct ttm_object_file *tfile,
-                      int id)
+                      uint32_t handle, int *id)
 {
-        struct vmw_resource *res;
-        int ret = 0;
+        struct ttm_base_object *base;
+        struct vmw_user_surface *user_srf;
 
-        read_lock(&dev_priv->resource_lock);
-        res = idr_find(&dev_priv->surface_idr, id);
-        if (res && res->avail) {
-                struct vmw_surface *srf =
-                        container_of(res, struct vmw_surface, res);
-                struct vmw_user_surface *usrf =
-                        container_of(srf, struct vmw_user_surface, srf);
+        int ret = -EPERM;
 
-                if (usrf->base.tfile != tfile && !usrf->base.shareable)
-                        ret = -EPERM;
-        } else
-                ret = -EINVAL;
-        read_unlock(&dev_priv->resource_lock);
+        base = ttm_base_object_lookup(tfile, handle);
+        if (unlikely(base == NULL))
+                return -EINVAL;
+
+        if (unlikely(base->object_type != VMW_RES_SURFACE))
+                goto out_bad_surface;
 
+        user_srf = container_of(base, struct vmw_user_surface, base);
+        *id = user_srf->srf.res.id;
+        ret = 0;
+
+out_bad_surface:
+        /**
+         * FIXME: May deadlock here when called from the
+         * command parsing code.
+         */
+
+        ttm_base_object_unref(&base);
         return ret;
 }