diff options
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv50_display.c')
-rw-r--r-- | drivers/gpu/drm/nouveau/nv50_display.c | 37 |
1 files changed, 27 insertions, 10 deletions
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c index 12c5ee63495b..90f0bf59fbcd 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.c +++ b/drivers/gpu/drm/nouveau/nv50_display.c | |||
@@ -188,7 +188,7 @@ nv50_display_init(struct drm_device *dev) | |||
188 | uint64_t start; | 188 | uint64_t start; |
189 | int ret, i; | 189 | int ret, i; |
190 | 190 | ||
191 | NV_DEBUG(dev, "\n"); | 191 | NV_DEBUG_KMS(dev, "\n"); |
192 | 192 | ||
193 | nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004)); | 193 | nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004)); |
194 | /* | 194 | /* |
@@ -232,7 +232,7 @@ nv50_display_init(struct drm_device *dev) | |||
232 | nv_wr32(dev, NV50_PDISPLAY_UNK_380, 0); | 232 | nv_wr32(dev, NV50_PDISPLAY_UNK_380, 0); |
233 | /* RAM is clamped to 256 MiB. */ | 233 | /* RAM is clamped to 256 MiB. */ |
234 | ram_amount = nouveau_mem_fb_amount(dev); | 234 | ram_amount = nouveau_mem_fb_amount(dev); |
235 | NV_DEBUG(dev, "ram_amount %d\n", ram_amount); | 235 | NV_DEBUG_KMS(dev, "ram_amount %d\n", ram_amount); |
236 | if (ram_amount > 256*1024*1024) | 236 | if (ram_amount > 256*1024*1024) |
237 | ram_amount = 256*1024*1024; | 237 | ram_amount = 256*1024*1024; |
238 | nv_wr32(dev, NV50_PDISPLAY_RAM_AMOUNT, ram_amount - 1); | 238 | nv_wr32(dev, NV50_PDISPLAY_RAM_AMOUNT, ram_amount - 1); |
@@ -398,7 +398,7 @@ static int nv50_display_disable(struct drm_device *dev) | |||
398 | struct drm_crtc *drm_crtc; | 398 | struct drm_crtc *drm_crtc; |
399 | int ret, i; | 399 | int ret, i; |
400 | 400 | ||
401 | NV_DEBUG(dev, "\n"); | 401 | NV_DEBUG_KMS(dev, "\n"); |
402 | 402 | ||
403 | list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) { | 403 | list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) { |
404 | struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc); | 404 | struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc); |
@@ -469,7 +469,7 @@ int nv50_display_create(struct drm_device *dev) | |||
469 | uint32_t connector[16] = {}; | 469 | uint32_t connector[16] = {}; |
470 | int ret, i; | 470 | int ret, i; |
471 | 471 | ||
472 | NV_DEBUG(dev, "\n"); | 472 | NV_DEBUG_KMS(dev, "\n"); |
473 | 473 | ||
474 | /* init basic kernel modesetting */ | 474 | /* init basic kernel modesetting */ |
475 | drm_mode_config_init(dev); | 475 | drm_mode_config_init(dev); |
@@ -573,7 +573,7 @@ int nv50_display_destroy(struct drm_device *dev) | |||
573 | { | 573 | { |
574 | struct drm_nouveau_private *dev_priv = dev->dev_private; | 574 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
575 | 575 | ||
576 | NV_DEBUG(dev, "\n"); | 576 | NV_DEBUG_KMS(dev, "\n"); |
577 | 577 | ||
578 | drm_mode_config_cleanup(dev); | 578 | drm_mode_config_cleanup(dev); |
579 | 579 | ||
@@ -617,7 +617,7 @@ nv50_display_irq_head(struct drm_device *dev, int *phead, | |||
617 | * CRTC separately, and submission will be blocked by the GPU | 617 | * CRTC separately, and submission will be blocked by the GPU |
618 | * until we handle each in turn. | 618 | * until we handle each in turn. |
619 | */ | 619 | */ |
620 | NV_DEBUG(dev, "0x610030: 0x%08x\n", unk30); | 620 | NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30); |
621 | head = ffs((unk30 >> 9) & 3) - 1; | 621 | head = ffs((unk30 >> 9) & 3) - 1; |
622 | if (head < 0) | 622 | if (head < 0) |
623 | return -EINVAL; | 623 | return -EINVAL; |
@@ -661,7 +661,7 @@ nv50_display_irq_head(struct drm_device *dev, int *phead, | |||
661 | or = i; | 661 | or = i; |
662 | } | 662 | } |
663 | 663 | ||
664 | NV_DEBUG(dev, "type %d, or %d\n", type, or); | 664 | NV_DEBUG_KMS(dev, "type %d, or %d\n", type, or); |
665 | if (type == OUTPUT_ANY) { | 665 | if (type == OUTPUT_ANY) { |
666 | NV_ERROR(dev, "unknown encoder!!\n"); | 666 | NV_ERROR(dev, "unknown encoder!!\n"); |
667 | return -1; | 667 | return -1; |
@@ -690,9 +690,21 @@ nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcbent, | |||
690 | int pxclk) | 690 | int pxclk) |
691 | { | 691 | { |
692 | struct drm_nouveau_private *dev_priv = dev->dev_private; | 692 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
693 | struct nouveau_connector *nv_connector = NULL; | ||
694 | struct drm_encoder *encoder; | ||
693 | struct nvbios *bios = &dev_priv->VBIOS; | 695 | struct nvbios *bios = &dev_priv->VBIOS; |
694 | uint32_t mc, script = 0, or; | 696 | uint32_t mc, script = 0, or; |
695 | 697 | ||
698 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | ||
699 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | ||
700 | |||
701 | if (nv_encoder->dcb != dcbent) | ||
702 | continue; | ||
703 | |||
704 | nv_connector = nouveau_encoder_connector_get(nv_encoder); | ||
705 | break; | ||
706 | } | ||
707 | |||
696 | or = ffs(dcbent->or) - 1; | 708 | or = ffs(dcbent->or) - 1; |
697 | mc = nv50_display_mode_ctrl(dev, dcbent->type != OUTPUT_ANALOG, or); | 709 | mc = nv50_display_mode_ctrl(dev, dcbent->type != OUTPUT_ANALOG, or); |
698 | switch (dcbent->type) { | 710 | switch (dcbent->type) { |
@@ -711,6 +723,11 @@ nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcbent, | |||
711 | } else | 723 | } else |
712 | if (bios->fp.strapless_is_24bit & 1) | 724 | if (bios->fp.strapless_is_24bit & 1) |
713 | script |= 0x0200; | 725 | script |= 0x0200; |
726 | |||
727 | if (nv_connector && nv_connector->edid && | ||
728 | (nv_connector->edid->revision >= 4) && | ||
729 | (nv_connector->edid->input & 0x70) >= 0x20) | ||
730 | script |= 0x0200; | ||
714 | } | 731 | } |
715 | 732 | ||
716 | if (nouveau_uscript_lvds >= 0) { | 733 | if (nouveau_uscript_lvds >= 0) { |
@@ -811,7 +828,7 @@ nv50_display_unk20_handler(struct drm_device *dev) | |||
811 | pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(head, CLOCK)) & 0x3fffff; | 828 | pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(head, CLOCK)) & 0x3fffff; |
812 | script = nv50_display_script_select(dev, dcbent, pclk); | 829 | script = nv50_display_script_select(dev, dcbent, pclk); |
813 | 830 | ||
814 | NV_DEBUG(dev, "head %d pxclk: %dKHz\n", head, pclk); | 831 | NV_DEBUG_KMS(dev, "head %d pxclk: %dKHz\n", head, pclk); |
815 | 832 | ||
816 | if (dcbent->type != OUTPUT_DP) | 833 | if (dcbent->type != OUTPUT_DP) |
817 | nouveau_bios_run_display_table(dev, dcbent, 0, -2); | 834 | nouveau_bios_run_display_table(dev, dcbent, 0, -2); |
@@ -870,7 +887,7 @@ nv50_display_irq_handler_bh(struct work_struct *work) | |||
870 | uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0); | 887 | uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0); |
871 | uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1); | 888 | uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1); |
872 | 889 | ||
873 | NV_DEBUG(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1); | 890 | NV_DEBUG_KMS(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1); |
874 | 891 | ||
875 | if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10) | 892 | if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10) |
876 | nv50_display_unk10_handler(dev); | 893 | nv50_display_unk10_handler(dev); |
@@ -974,7 +991,7 @@ nv50_display_irq_handler(struct drm_device *dev) | |||
974 | uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1); | 991 | uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1); |
975 | uint32_t clock; | 992 | uint32_t clock; |
976 | 993 | ||
977 | NV_DEBUG(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1); | 994 | NV_DEBUG_KMS(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1); |
978 | 995 | ||
979 | if (!intr0 && !(intr1 & ~delayed)) | 996 | if (!intr0 && !(intr1 & ~delayed)) |
980 | break; | 997 | break; |