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path: root/drivers/gpu/drm/radeon/evergreen_hdmi.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen_hdmi.c')
-rw-r--r--drivers/gpu/drm/radeon/evergreen_hdmi.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
index f71ce390aebe..fe1de855775e 100644
--- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
+++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
@@ -67,6 +67,9 @@ static void dce4_afmt_write_speaker_allocation(struct drm_encoder *encoder)
67 u8 *sadb; 67 u8 *sadb;
68 int sad_count; 68 int sad_count;
69 69
70 /* XXX: setting this register causes hangs on some asics */
71 return;
72
70 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 73 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
71 if (connector->encoder == encoder) 74 if (connector->encoder == encoder)
72 radeon_connector = to_radeon_connector(connector); 75 radeon_connector = to_radeon_connector(connector);
@@ -288,8 +291,7 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
288 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */ 291 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
289 292
290 WREG32(HDMI_ACR_PACKET_CONTROL + offset, 293 WREG32(HDMI_ACR_PACKET_CONTROL + offset,
291 HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */ 294 HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
292 HDMI_ACR_SOURCE); /* select SW CTS value */
293 295
294 evergreen_hdmi_update_ACR(encoder, mode->clock); 296 evergreen_hdmi_update_ACR(encoder, mode->clock);
295 297