diff options
Diffstat (limited to 'drivers/gpu/drm/nouveau')
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c | 7 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/disp/hdminv84.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c | 14 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/include/core/class.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_display.c | 13 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nv50_display.c | 4 |
6 files changed, 26 insertions, 18 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c index d0817d94454c..f02fd9f443ff 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c | |||
@@ -50,11 +50,16 @@ nv50_dac_sense(struct nv50_disp_priv *priv, int or, u32 loadval) | |||
50 | { | 50 | { |
51 | const u32 doff = (or * 0x800); | 51 | const u32 doff = (or * 0x800); |
52 | int load = -EINVAL; | 52 | int load = -EINVAL; |
53 | nv_mask(priv, 0x61a004 + doff, 0x807f0000, 0x80150000); | ||
54 | nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000); | ||
53 | nv_wr32(priv, 0x61a00c + doff, 0x00100000 | loadval); | 55 | nv_wr32(priv, 0x61a00c + doff, 0x00100000 | loadval); |
54 | udelay(9500); | 56 | mdelay(9); |
57 | udelay(500); | ||
55 | nv_wr32(priv, 0x61a00c + doff, 0x80000000); | 58 | nv_wr32(priv, 0x61a00c + doff, 0x80000000); |
56 | load = (nv_rd32(priv, 0x61a00c + doff) & 0x38000000) >> 27; | 59 | load = (nv_rd32(priv, 0x61a00c + doff) & 0x38000000) >> 27; |
57 | nv_wr32(priv, 0x61a00c + doff, 0x00000000); | 60 | nv_wr32(priv, 0x61a00c + doff, 0x00000000); |
61 | nv_mask(priv, 0x61a004 + doff, 0x807f0000, 0x80550000); | ||
62 | nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000); | ||
58 | return load; | 63 | return load; |
59 | } | 64 | } |
60 | 65 | ||
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdminv84.c b/drivers/gpu/drm/nouveau/core/engine/disp/hdminv84.c index 0d36bdc51417..7fdade6e604d 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/hdminv84.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/hdminv84.c | |||
@@ -55,6 +55,10 @@ nv84_hdmi_ctrl(struct nv50_disp_priv *priv, int head, int or, u32 data) | |||
55 | nv_wr32(priv, 0x616510 + hoff, 0x00000000); | 55 | nv_wr32(priv, 0x616510 + hoff, 0x00000000); |
56 | nv_mask(priv, 0x616500 + hoff, 0x00000001, 0x00000001); | 56 | nv_mask(priv, 0x616500 + hoff, 0x00000001, 0x00000001); |
57 | 57 | ||
58 | nv_mask(priv, 0x6165d0 + hoff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */ | ||
59 | nv_mask(priv, 0x616568 + hoff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */ | ||
60 | nv_mask(priv, 0x616578 + hoff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */ | ||
61 | |||
58 | /* ??? */ | 62 | /* ??? */ |
59 | nv_mask(priv, 0x61733c, 0x00100000, 0x00100000); /* RESETF */ | 63 | nv_mask(priv, 0x61733c, 0x00100000, 0x00100000); /* RESETF */ |
60 | nv_mask(priv, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */ | 64 | nv_mask(priv, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */ |
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c index 89bf459d584b..e9b8217d0075 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c | |||
@@ -40,14 +40,13 @@ | |||
40 | * FIFO channel objects | 40 | * FIFO channel objects |
41 | ******************************************************************************/ | 41 | ******************************************************************************/ |
42 | 42 | ||
43 | void | 43 | static void |
44 | nv50_fifo_playlist_update(struct nv50_fifo_priv *priv) | 44 | nv50_fifo_playlist_update_locked(struct nv50_fifo_priv *priv) |
45 | { | 45 | { |
46 | struct nouveau_bar *bar = nouveau_bar(priv); | 46 | struct nouveau_bar *bar = nouveau_bar(priv); |
47 | struct nouveau_gpuobj *cur; | 47 | struct nouveau_gpuobj *cur; |
48 | int i, p; | 48 | int i, p; |
49 | 49 | ||
50 | mutex_lock(&nv_subdev(priv)->mutex); | ||
51 | cur = priv->playlist[priv->cur_playlist]; | 50 | cur = priv->playlist[priv->cur_playlist]; |
52 | priv->cur_playlist = !priv->cur_playlist; | 51 | priv->cur_playlist = !priv->cur_playlist; |
53 | 52 | ||
@@ -61,6 +60,13 @@ nv50_fifo_playlist_update(struct nv50_fifo_priv *priv) | |||
61 | nv_wr32(priv, 0x0032f4, cur->addr >> 12); | 60 | nv_wr32(priv, 0x0032f4, cur->addr >> 12); |
62 | nv_wr32(priv, 0x0032ec, p); | 61 | nv_wr32(priv, 0x0032ec, p); |
63 | nv_wr32(priv, 0x002500, 0x00000101); | 62 | nv_wr32(priv, 0x002500, 0x00000101); |
63 | } | ||
64 | |||
65 | void | ||
66 | nv50_fifo_playlist_update(struct nv50_fifo_priv *priv) | ||
67 | { | ||
68 | mutex_lock(&nv_subdev(priv)->mutex); | ||
69 | nv50_fifo_playlist_update_locked(priv); | ||
64 | mutex_unlock(&nv_subdev(priv)->mutex); | 70 | mutex_unlock(&nv_subdev(priv)->mutex); |
65 | } | 71 | } |
66 | 72 | ||
@@ -489,7 +495,7 @@ nv50_fifo_init(struct nouveau_object *object) | |||
489 | 495 | ||
490 | for (i = 0; i < 128; i++) | 496 | for (i = 0; i < 128; i++) |
491 | nv_wr32(priv, 0x002600 + (i * 4), 0x00000000); | 497 | nv_wr32(priv, 0x002600 + (i * 4), 0x00000000); |
492 | nv50_fifo_playlist_update(priv); | 498 | nv50_fifo_playlist_update_locked(priv); |
493 | 499 | ||
494 | nv_wr32(priv, 0x003200, 0x00000001); | 500 | nv_wr32(priv, 0x003200, 0x00000001); |
495 | nv_wr32(priv, 0x003250, 0x00000001); | 501 | nv_wr32(priv, 0x003250, 0x00000001); |
diff --git a/drivers/gpu/drm/nouveau/core/include/core/class.h b/drivers/gpu/drm/nouveau/core/include/core/class.h index 0a393f7f055f..5a5961b6a6a3 100644 --- a/drivers/gpu/drm/nouveau/core/include/core/class.h +++ b/drivers/gpu/drm/nouveau/core/include/core/class.h | |||
@@ -218,7 +218,7 @@ struct nv04_display_class { | |||
218 | #define NV50_DISP_DAC_PWR_STATE 0x00000040 | 218 | #define NV50_DISP_DAC_PWR_STATE 0x00000040 |
219 | #define NV50_DISP_DAC_PWR_STATE_ON 0x00000000 | 219 | #define NV50_DISP_DAC_PWR_STATE_ON 0x00000000 |
220 | #define NV50_DISP_DAC_PWR_STATE_OFF 0x00000040 | 220 | #define NV50_DISP_DAC_PWR_STATE_OFF 0x00000040 |
221 | #define NV50_DISP_DAC_LOAD 0x0002000c | 221 | #define NV50_DISP_DAC_LOAD 0x00020100 |
222 | #define NV50_DISP_DAC_LOAD_VALUE 0x00000007 | 222 | #define NV50_DISP_DAC_LOAD_VALUE 0x00000007 |
223 | 223 | ||
224 | #define NV50_DISP_PIOR_MTHD 0x00030000 | 224 | #define NV50_DISP_PIOR_MTHD 0x00030000 |
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c index 7bf22d4a3d96..f17dc2ab03ec 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.c +++ b/drivers/gpu/drm/nouveau/nouveau_display.c | |||
@@ -638,17 +638,8 @@ nouveau_finish_page_flip(struct nouveau_channel *chan, | |||
638 | } | 638 | } |
639 | 639 | ||
640 | s = list_first_entry(&fctx->flip, struct nouveau_page_flip_state, head); | 640 | s = list_first_entry(&fctx->flip, struct nouveau_page_flip_state, head); |
641 | if (s->event) { | 641 | if (s->event) |
642 | struct drm_pending_vblank_event *e = s->event; | 642 | drm_send_vblank_event(dev, -1, s->event); |
643 | struct timeval now; | ||
644 | |||
645 | do_gettimeofday(&now); | ||
646 | e->event.sequence = 0; | ||
647 | e->event.tv_sec = now.tv_sec; | ||
648 | e->event.tv_usec = now.tv_usec; | ||
649 | list_add_tail(&e->base.link, &e->base.file_priv->event_list); | ||
650 | wake_up_interruptible(&e->base.file_priv->event_wait); | ||
651 | } | ||
652 | 643 | ||
653 | list_del(&s->head); | 644 | list_del(&s->head); |
654 | if (ps) | 645 | if (ps) |
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c index ebf0a683305e..dd5e01f89f28 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.c +++ b/drivers/gpu/drm/nouveau/nv50_display.c | |||
@@ -1554,7 +1554,9 @@ nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) | |||
1554 | { | 1554 | { |
1555 | struct nv50_disp *disp = nv50_disp(encoder->dev); | 1555 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
1556 | int ret, or = nouveau_encoder(encoder)->or; | 1556 | int ret, or = nouveau_encoder(encoder)->or; |
1557 | u32 load = 0; | 1557 | u32 load = nouveau_drm(encoder->dev)->vbios.dactestval; |
1558 | if (load == 0) | ||
1559 | load = 340; | ||
1558 | 1560 | ||
1559 | ret = nv_exec(disp->core, NV50_DISP_DAC_LOAD + or, &load, sizeof(load)); | 1561 | ret = nv_exec(disp->core, NV50_DISP_DAC_LOAD + or, &load, sizeof(load)); |
1560 | if (ret || load != 7) | 1562 | if (ret || load != 7) |