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path: root/drivers/clk/tegra/clk-periph-gate.c
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-rw-r--r--drivers/clk/tegra/clk-periph-gate.c179
1 files changed, 179 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c
new file mode 100644
index 000000000000..6dd533251e7b
--- /dev/null
+++ b/drivers/clk/tegra/clk-periph-gate.c
@@ -0,0 +1,179 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/clk.h>
18#include <linux/clk-provider.h>
19#include <linux/slab.h>
20#include <linux/io.h>
21#include <linux/delay.h>
22#include <linux/err.h>
23#include <linux/tegra-soc.h>
24
25#include "clk.h"
26
27static DEFINE_SPINLOCK(periph_ref_lock);
28
29/* Macros to assist peripheral gate clock */
30#define read_enb(gate) \
31 readl_relaxed(gate->clk_base + (gate->regs->enb_reg))
32#define write_enb_set(val, gate) \
33 writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg))
34#define write_enb_clr(val, gate) \
35 writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg))
36
37#define read_rst(gate) \
38 readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
39#define write_rst_set(val, gate) \
40 writel_relaxed(val, gate->clk_base + (gate->regs->rst_set_reg))
41#define write_rst_clr(val, gate) \
42 writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
43
44#define periph_clk_to_bit(periph) (1 << (gate->clk_num % 32))
45
46/* Peripheral gate clock ops */
47static int clk_periph_is_enabled(struct clk_hw *hw)
48{
49 struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
50 int state = 1;
51
52 if (!(read_enb(gate) & periph_clk_to_bit(gate)))
53 state = 0;
54
55 if (!(gate->flags & TEGRA_PERIPH_NO_RESET))
56 if (read_rst(gate) & periph_clk_to_bit(gate))
57 state = 0;
58
59 return state;
60}
61
62static int clk_periph_enable(struct clk_hw *hw)
63{
64 struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
65 unsigned long flags = 0;
66
67 spin_lock_irqsave(&periph_ref_lock, flags);
68
69 gate->enable_refcnt[gate->clk_num]++;
70 if (gate->enable_refcnt[gate->clk_num] > 1) {
71 spin_unlock_irqrestore(&periph_ref_lock, flags);
72 return 0;
73 }
74
75 write_enb_set(periph_clk_to_bit(gate), gate);
76 udelay(2);
77
78 if (!(gate->flags & TEGRA_PERIPH_NO_RESET) &&
79 !(gate->flags & TEGRA_PERIPH_MANUAL_RESET)) {
80 if (read_rst(gate) & periph_clk_to_bit(gate)) {
81 udelay(5); /* reset propogation delay */
82 write_rst_clr(periph_clk_to_bit(gate), gate);
83 }
84 }
85
86 spin_unlock_irqrestore(&periph_ref_lock, flags);
87
88 return 0;
89}
90
91static void clk_periph_disable(struct clk_hw *hw)
92{
93 struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
94 unsigned long flags = 0;
95
96 spin_lock_irqsave(&periph_ref_lock, flags);
97
98 gate->enable_refcnt[gate->clk_num]--;
99 if (gate->enable_refcnt[gate->clk_num] > 0) {
100 spin_unlock_irqrestore(&periph_ref_lock, flags);
101 return;
102 }
103
104 /*
105 * If peripheral is in the APB bus then read the APB bus to
106 * flush the write operation in apb bus. This will avoid the
107 * peripheral access after disabling clock
108 */
109 if (gate->flags & TEGRA_PERIPH_ON_APB)
110 tegra_read_chipid();
111
112 write_enb_clr(periph_clk_to_bit(gate), gate);
113
114 spin_unlock_irqrestore(&periph_ref_lock, flags);
115}
116
117void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert)
118{
119 if (gate->flags & TEGRA_PERIPH_NO_RESET)
120 return;
121
122 if (assert) {
123 /*
124 * If peripheral is in the APB bus then read the APB bus to
125 * flush the write operation in apb bus. This will avoid the
126 * peripheral access after disabling clock
127 */
128 if (gate->flags & TEGRA_PERIPH_ON_APB)
129 tegra_read_chipid();
130
131 write_rst_set(periph_clk_to_bit(gate), gate);
132 } else {
133 write_rst_clr(periph_clk_to_bit(gate), gate);
134 }
135}
136
137const struct clk_ops tegra_clk_periph_gate_ops = {
138 .is_enabled = clk_periph_is_enabled,
139 .enable = clk_periph_enable,
140 .disable = clk_periph_disable,
141};
142
143struct clk *tegra_clk_register_periph_gate(const char *name,
144 const char *parent_name, u8 gate_flags, void __iomem *clk_base,
145 unsigned long flags, int clk_num,
146 struct tegra_clk_periph_regs *pregs, int *enable_refcnt)
147{
148 struct tegra_clk_periph_gate *gate;
149 struct clk *clk;
150 struct clk_init_data init;
151
152 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
153 if (!gate) {
154 pr_err("%s: could not allocate periph gate clk\n", __func__);
155 return ERR_PTR(-ENOMEM);
156 }
157
158 init.name = name;
159 init.flags = flags;
160 init.parent_names = parent_name ? &parent_name : NULL;
161 init.num_parents = parent_name ? 1 : 0;
162 init.ops = &tegra_clk_periph_gate_ops;
163
164 gate->magic = TEGRA_CLK_PERIPH_GATE_MAGIC;
165 gate->clk_base = clk_base;
166 gate->clk_num = clk_num;
167 gate->flags = gate_flags;
168 gate->enable_refcnt = enable_refcnt;
169 gate->regs = pregs;
170
171 /* Data in .init is copied by clk_register(), so stack variable OK */
172 gate->hw.init = &init;
173
174 clk = clk_register(NULL, &gate->hw);
175 if (IS_ERR(clk))
176 kfree(gate);
177
178 return clk;
179}
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-12 22:02:53 -0400