aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt205
-rw-r--r--Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt262
-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/boot/dts/tegra20-paz00.dts2
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi50
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi62
-rw-r--r--arch/arm/mach-tegra/Kconfig4
-rw-r--r--arch/arm/mach-tegra/Makefile11
-rw-r--r--arch/arm/mach-tegra/apbio.c2
-rw-r--r--arch/arm/mach-tegra/board-dt-tegra20.c67
-rw-r--r--arch/arm/mach-tegra/board-dt-tegra30.c65
-rw-r--r--arch/arm/mach-tegra/board.h1
-rw-r--r--arch/arm/mach-tegra/clock.c166
-rw-r--r--arch/arm/mach-tegra/clock.h153
-rw-r--r--arch/arm/mach-tegra/common.c47
-rw-r--r--arch/arm/mach-tegra/common.h1
-rw-r--r--arch/arm/mach-tegra/cpu-tegra.c40
-rw-r--r--arch/arm/mach-tegra/cpuidle-tegra30.c8
-rw-r--r--arch/arm/mach-tegra/flowctrl.c4
-rw-r--r--arch/arm/mach-tegra/fuse.c8
-rw-r--r--arch/arm/mach-tegra/headsmp.S221
-rw-r--r--arch/arm/mach-tegra/hotplug.c23
-rw-r--r--arch/arm/mach-tegra/include/mach/clk.h44
-rw-r--r--arch/arm/mach-tegra/pcie.c2
-rw-r--r--arch/arm/mach-tegra/platsmp.c45
-rw-r--r--arch/arm/mach-tegra/pm.c6
-rw-r--r--arch/arm/mach-tegra/powergate.c2
-rw-r--r--arch/arm/mach-tegra/reset-handler.S239
-rw-r--r--arch/arm/mach-tegra/reset.c2
-rw-r--r--arch/arm/mach-tegra/sleep-tegra20.S3
-rw-r--r--arch/arm/mach-tegra/sleep-tegra30.S3
-rw-r--r--arch/arm/mach-tegra/sleep.S4
-rw-r--r--arch/arm/mach-tegra/sleep.h1
-rw-r--r--arch/arm/mach-tegra/tegra20_clocks.c1623
-rw-r--r--arch/arm/mach-tegra/tegra20_clocks.h42
-rw-r--r--arch/arm/mach-tegra/tegra20_clocks_data.c1143
-rw-r--r--arch/arm/mach-tegra/tegra30_clocks.c2506
-rw-r--r--arch/arm/mach-tegra/tegra30_clocks.h54
-rw-r--r--arch/arm/mach-tegra/tegra30_clocks_data.c1425
-rw-r--r--drivers/clk/Makefile1
-rw-r--r--drivers/clk/tegra/Makefile11
-rw-r--r--drivers/clk/tegra/clk-audio-sync.c87
-rw-r--r--drivers/clk/tegra/clk-divider.c187
-rw-r--r--drivers/clk/tegra/clk-periph-gate.c179
-rw-r--r--drivers/clk/tegra/clk-periph.c218
-rw-r--r--drivers/clk/tegra/clk-pll-out.c123
-rw-r--r--drivers/clk/tegra/clk-pll.c648
-rw-r--r--drivers/clk/tegra/clk-super.c154
-rw-r--r--drivers/clk/tegra/clk-tegra20.c1256
-rw-r--r--drivers/clk/tegra/clk-tegra30.c1987
-rw-r--r--drivers/clk/tegra/clk.c85
-rw-r--r--drivers/clk/tegra/clk.h502
-rw-r--r--drivers/clocksource/Makefile1
-rw-r--r--drivers/clocksource/tegra20_timer.c (renamed from arch/arm/mach-tegra/timer.c)9
-rw-r--r--drivers/dma/tegra20-apb-dma.c2
-rw-r--r--drivers/gpu/drm/tegra/dc.c3
-rw-r--r--drivers/gpu/drm/tegra/drm.c1
-rw-r--r--drivers/gpu/drm/tegra/hdmi.c3
-rw-r--r--drivers/i2c/busses/i2c-tegra.c3
-rw-r--r--drivers/input/keyboard/tegra-kbc.c2
-rw-r--r--drivers/spi/spi-tegra20-sflash.c4
-rw-r--r--drivers/spi/spi-tegra20-slink.c4
-rw-r--r--drivers/staging/nvec/TODO4
-rw-r--r--drivers/staging/nvec/nvec.c5
-rw-r--r--include/linux/clk/tegra.h (renamed from arch/arm/mach-tegra/tegra_cpu_car.h)13
-rw-r--r--include/linux/tegra-soc.h22
-rw-r--r--sound/soc/tegra/tegra30_ahub.c16
67 files changed, 6426 insertions, 7651 deletions
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
new file mode 100644
index 000000000000..0921fac73528
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
@@ -0,0 +1,205 @@
1NVIDIA Tegra20 Clock And Reset Controller
2
3This binding uses the common clock binding:
4Documentation/devicetree/bindings/clock/clock-bindings.txt
5
6The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
7for muxing and gating Tegra's clocks, and setting their rates.
8
9Required properties :
10- compatible : Should be "nvidia,tegra20-car"
11- reg : Should contain CAR registers location and length
12- clocks : Should contain phandle and clock specifiers for two clocks:
13 the 32 KHz "32k_in", and the board-specific oscillator "osc".
14- #clock-cells : Should be 1.
15 In clock consumers, this cell represents the clock ID exposed by the CAR.
16
17 The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
18 registers. These IDs often match those in the CAR's RST_DEVICES registers,
19 but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
20 this case, those clocks are assigned IDs above 95 in order to highlight
21 this issue. Implementations that interpret these clock IDs as bit values
22 within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
23 explicitly handle these special cases.
24
25 The balance of the clocks controlled by the CAR are assigned IDs of 96 and
26 above.
27
28 0 cpu
29 1 unassigned
30 2 unassigned
31 3 ac97
32 4 rtc
33 5 tmr
34 6 uart1
35 7 unassigned (register bit affects uart2 and vfir)
36 8 gpio
37 9 sdmmc2
38 10 unassigned (register bit affects spdif_in and spdif_out)
39 11 i2s1
40 12 i2c1
41 13 ndflash
42 14 sdmmc1
43 15 sdmmc4
44 16 twc
45 17 pwm
46 18 i2s2
47 19 epp
48 20 unassigned (register bit affects vi and vi_sensor)
49 21 2d
50 22 usbd
51 23 isp
52 24 3d
53 25 ide
54 26 disp2
55 27 disp1
56 28 host1x
57 29 vcp
58 30 unassigned
59 31 cache2
60
61 32 mem
62 33 ahbdma
63 34 apbdma
64 35 unassigned
65 36 kbc
66 37 stat_mon
67 38 pmc
68 39 fuse
69 40 kfuse
70 41 sbc1
71 42 snor
72 43 spi1
73 44 sbc2
74 45 xio
75 46 sbc3
76 47 dvc
77 48 dsi
78 49 unassigned (register bit affects tvo and cve)
79 50 mipi
80 51 hdmi
81 52 csi
82 53 tvdac
83 54 i2c2
84 55 uart3
85 56 unassigned
86 57 emc
87 58 usb2
88 59 usb3
89 60 mpe
90 61 vde
91 62 bsea
92 63 bsev
93
94 64 speedo
95 65 uart4
96 66 uart5
97 67 i2c3
98 68 sbc4
99 69 sdmmc3
100 70 pcie
101 71 owr
102 72 afi
103 73 csite
104 74 unassigned
105 75 avpucq
106 76 la
107 77 unassigned
108 78 unassigned
109 79 unassigned
110 80 unassigned
111 81 unassigned
112 82 unassigned
113 83 unassigned
114 84 irama
115 85 iramb
116 86 iramc
117 87 iramd
118 88 cram2
119 89 audio_2x a/k/a audio_2x_sync_clk
120 90 clk_d
121 91 unassigned
122 92 sus
123 93 cdev1
124 94 cdev2
125 95 unassigned
126
127 96 uart2
128 97 vfir
129 98 spdif_in
130 99 spdif_out
131 100 vi
132 101 vi_sensor
133 102 tvo
134 103 cve
135 104 osc
136 105 clk_32k a/k/a clk_s
137 106 clk_m
138 107 sclk
139 108 cclk
140 109 hclk
141 110 pclk
142 111 blink
143 112 pll_a
144 113 pll_a_out0
145 114 pll_c
146 115 pll_c_out1
147 116 pll_d
148 117 pll_d_out0
149 118 pll_e
150 119 pll_m
151 120 pll_m_out1
152 121 pll_p
153 122 pll_p_out1
154 123 pll_p_out2
155 124 pll_p_out3
156 125 pll_p_out4
157 126 pll_s
158 127 pll_u
159 128 pll_x
160 129 cop a/k/a avp
161 130 audio a/k/a audio_sync_clk
162 131 pll_ref
163 132 twd
164
165Example SoC include file:
166
167/ {
168 tegra_car: clock {
169 compatible = "nvidia,tegra20-car";
170 reg = <0x60006000 0x1000>;
171 #clock-cells = <1>;
172 };
173
174 usb@c5004000 {
175 clocks = <&tegra_car 58>; /* usb2 */
176 };
177};
178
179Example board file:
180
181/ {
182 clocks {
183 compatible = "simple-bus";
184 #address-cells = <1>;
185 #size-cells = <0>;
186
187 osc: clock@0 {
188 compatible = "fixed-clock";
189 reg = <0>;
190 #clock-cells = <0>;
191 clock-frequency = <12000000>;
192 };
193
194 clk_32k: clock@1 {
195 compatible = "fixed-clock";
196 reg = <1>;
197 #clock-cells = <0>;
198 clock-frequency = <32768>;
199 };
200 };
201
202 &tegra_car {
203 clocks = <&clk_32k> <&osc>;
204 };
205};
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
new file mode 100644
index 000000000000..f3da3be5fcad
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
@@ -0,0 +1,262 @@
1NVIDIA Tegra30 Clock And Reset Controller
2
3This binding uses the common clock binding:
4Documentation/devicetree/bindings/clock/clock-bindings.txt
5
6The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
7for muxing and gating Tegra's clocks, and setting their rates.
8
9Required properties :
10- compatible : Should be "nvidia,tegra30-car"
11- reg : Should contain CAR registers location and length
12- clocks : Should contain phandle and clock specifiers for two clocks:
13 the 32 KHz "32k_in", and the board-specific oscillator "osc".
14- #clock-cells : Should be 1.
15 In clock consumers, this cell represents the clock ID exposed by the CAR.
16
17 The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
18 registers. These IDs often match those in the CAR's RST_DEVICES registers,
19 but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
20 this case, those clocks are assigned IDs above 160 in order to highlight
21 this issue. Implementations that interpret these clock IDs as bit values
22 within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
23 explicitly handle these special cases.
24
25 The balance of the clocks controlled by the CAR are assigned IDs of 160 and
26 above.
27
28 0 cpu
29 1 unassigned
30 2 unassigned
31 3 unassigned
32 4 rtc
33 5 timer
34 6 uarta
35 7 unassigned (register bit affects uartb and vfir)
36 8 gpio
37 9 sdmmc2
38 10 unassigned (register bit affects spdif_in and spdif_out)
39 11 i2s1
40 12 i2c1
41 13 ndflash
42 14 sdmmc1
43 15 sdmmc4
44 16 unassigned
45 17 pwm
46 18 i2s2
47 19 epp
48 20 unassigned (register bit affects vi and vi_sensor)
49 21 2d
50 22 usbd
51 23 isp
52 24 3d
53 25 unassigned
54 26 disp2
55 27 disp1
56 28 host1x
57 29 vcp
58 30 i2s0
59 31 cop_cache
60
61 32 mc
62 33 ahbdma
63 34 apbdma
64 35 unassigned
65 36 kbc
66 37 statmon
67 38 pmc
68 39 unassigned (register bit affects fuse and fuse_burn)
69 40 kfuse
70 41 sbc1
71 42 nor
72 43 unassigned
73 44 sbc2
74 45 unassigned
75 46 sbc3
76 47 i2c5
77 48 dsia
78 49 unassigned (register bit affects cve and tvo)
79 50 mipi
80 51 hdmi
81 52 csi
82 53 tvdac
83 54 i2c2
84 55 uartc
85 56 unassigned
86 57 emc
87 58 usb2
88 59 usb3
89 60 mpe
90 61 vde
91 62 bsea
92 63 bsev
93
94 64 speedo
95 65 uartd
96 66 uarte
97 67 i2c3
98 68 sbc4
99 69 sdmmc3
100 70 pcie
101 71 owr
102 72 afi
103 73 csite
104 74 pciex
105 75 avpucq
106 76 la
107 77 unassigned
108 78 unassigned
109 79 dtv
110 80 ndspeed
111 81 i2cslow
112 82 dsib
113 83 unassigned
114 84 irama
115 85 iramb
116 86 iramc
117 87 iramd
118 88 cram2
119 89 unassigned
120 90 audio_2x a/k/a audio_2x_sync_clk
121 91 unassigned
122 92 csus
123 93 cdev2
124 94 cdev1
125 95 unassigned
126
127 96 cpu_g
128 97 cpu_lp
129 98 3d2
130 99 mselect
131 100 tsensor
132 101 i2s3
133 102 i2s4
134 103 i2c4
135 104 sbc5
136 105 sbc6
137 106 d_audio
138 107 apbif
139 108 dam0
140 109 dam1
141 110 dam2
142 111 hda2codec_2x
143 112 atomics
144 113 audio0_2x
145 114 audio1_2x
146 115 audio2_2x
147 116 audio3_2x
148 117 audio4_2x
149 118 audio5_2x
150 119 actmon
151 120 extern1
152 121 extern2
153 122 extern3
154 123 sata_oob
155 124 sata
156 125 hda
157 127 se
158 128 hda2hdmi
159 129 sata_cold
160
161 160 uartb
162 161 vfir
163 162 spdif_in
164 163 spdif_out
165 164 vi
166 165 vi_sensor
167 166 fuse
168 167 fuse_burn
169 168 cve
170 169 tvo
171
172 170 clk_32k
173 171 clk_m
174 172 clk_m_div2
175 173 clk_m_div4
176 174 pll_ref
177 175 pll_c
178 176 pll_c_out1
179 177 pll_m
180 178 pll_m_out1
181 179 pll_p
182 180 pll_p_out1
183 181 pll_p_out2
184 182 pll_p_out3
185 183 pll_p_out4
186 184 pll_a
187 185 pll_a_out0
188 186 pll_d
189 187 pll_d_out0
190 188 pll_d2
191 189 pll_d2_out0
192 190 pll_u
193 191 pll_x
194 192 pll_x_out0
195 193 pll_e
196 194 spdif_in_sync
197 195 i2s0_sync
198 196 i2s1_sync
199 197 i2s2_sync
200 198 i2s3_sync
201 199 i2s4_sync
202 200 vimclk
203 201 audio0
204 202 audio1
205 203 audio2
206 204 audio3
207 205 audio4
208 206 audio5
209 207 clk_out_1 (extern1)
210 208 clk_out_2 (extern2)
211 209 clk_out_3 (extern3)
212 210 sclk
213 211 blink
214 212 cclk_g
215 213 cclk_lp
216 214 twd
217 215 cml0
218 216 cml1
219 217 hclk
220 218 pclk
221
222Example SoC include file:
223
224/ {
225 tegra_car: clock {
226 compatible = "nvidia,tegra30-car";
227 reg = <0x60006000 0x1000>;
228 #clock-cells = <1>;
229 };
230
231 usb@c5004000 {
232 clocks = <&tegra_car 58>; /* usb2 */
233 };
234};
235
236Example board file:
237
238/ {
239 clocks {
240 compatible = "simple-bus";
241 #address-cells = <1>;
242 #size-cells = <0>;
243
244 osc: clock@0 {
245 compatible = "fixed-clock";
246 reg = <0>;
247 #clock-cells = <0>;
248 clock-frequency = <12000000>;
249 };
250
251 clk_32k: clock@1 {
252 compatible = "fixed-clock";
253 reg = <1>;
254 #clock-cells = <0>;
255 clock-frequency = <32768>;
256 };
257 };
258
259 &tegra_car {
260 clocks = <&clk_32k> <&osc>;
261 };
262};
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a3ffd1a391a7..22bfac3e6975 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -643,6 +643,7 @@ config ARCH_TEGRA
643 select ARCH_HAS_CPUFREQ 643 select ARCH_HAS_CPUFREQ
644 select CLKDEV_LOOKUP 644 select CLKDEV_LOOKUP
645 select CLKSRC_MMIO 645 select CLKSRC_MMIO
646 select CLKSRC_OF
646 select COMMON_CLK 647 select COMMON_CLK
647 select GENERIC_CLOCKEVENTS 648 select GENERIC_CLOCKEVENTS
648 select GENERIC_GPIO 649 select GENERIC_GPIO
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 6a93d1404c76..a965fe9c7aa1 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -266,6 +266,8 @@
266 clock-frequency = <80000>; 266 clock-frequency = <80000>;
267 request-gpios = <&gpio 170 0>; /* gpio PV2 */ 267 request-gpios = <&gpio 170 0>; /* gpio PV2 */
268 slave-addr = <138>; 268 slave-addr = <138>;
269 clocks = <&tegra_car 67>, <&tegra_car 124>;
270 clock-names = "div-clk", "fast-clk";
269 }; 271 };
270 272
271 i2c@7000d000 { 273 i2c@7000d000 {
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index b8effa1cbda7..d665a67d4358 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -9,6 +9,7 @@
9 reg = <0x50000000 0x00024000>; 9 reg = <0x50000000 0x00024000>;
10 interrupts = <0 65 0x04 /* mpcore syncpt */ 10 interrupts = <0 65 0x04 /* mpcore syncpt */
11 0 67 0x04>; /* mpcore general */ 11 0 67 0x04>; /* mpcore general */
12 clocks = <&tegra_car 28>;
12 13
13 #address-cells = <1>; 14 #address-cells = <1>;
14 #size-cells = <1>; 15 #size-cells = <1>;
@@ -19,41 +20,49 @@
19 compatible = "nvidia,tegra20-mpe"; 20 compatible = "nvidia,tegra20-mpe";
20 reg = <0x54040000 0x00040000>; 21 reg = <0x54040000 0x00040000>;
21 interrupts = <0 68 0x04>; 22 interrupts = <0 68 0x04>;
23 clocks = <&tegra_car 60>;
22 }; 24 };
23 25
24 vi { 26 vi {
25 compatible = "nvidia,tegra20-vi"; 27 compatible = "nvidia,tegra20-vi";
26 reg = <0x54080000 0x00040000>; 28 reg = <0x54080000 0x00040000>;
27 interrupts = <0 69 0x04>; 29 interrupts = <0 69 0x04>;
30 clocks = <&tegra_car 100>;
28 }; 31 };
29 32
30 epp { 33 epp {
31 compatible = "nvidia,tegra20-epp"; 34 compatible = "nvidia,tegra20-epp";
32 reg = <0x540c0000 0x00040000>; 35 reg = <0x540c0000 0x00040000>;
33 interrupts = <0 70 0x04>; 36 interrupts = <0 70 0x04>;
37 clocks = <&tegra_car 19>;
34 }; 38 };
35 39
36 isp { 40 isp {
37 compatible = "nvidia,tegra20-isp"; 41 compatible = "nvidia,tegra20-isp";
38 reg = <0x54100000 0x00040000>; 42 reg = <0x54100000 0x00040000>;
39 interrupts = <0 71 0x04>; 43 interrupts = <0 71 0x04>;
44 clocks = <&tegra_car 23>;
40 }; 45 };
41 46
42 gr2d { 47 gr2d {
43 compatible = "nvidia,tegra20-gr2d"; 48 compatible = "nvidia,tegra20-gr2d";
44 reg = <0x54140000 0x00040000>; 49 reg = <0x54140000 0x00040000>;
45 interrupts = <0 72 0x04>; 50 interrupts = <0 72 0x04>;
51 clocks = <&tegra_car 21>;
46 }; 52 };
47 53
48 gr3d { 54 gr3d {
49 compatible = "nvidia,tegra20-gr3d"; 55 compatible = "nvidia,tegra20-gr3d";
50 reg = <0x54180000 0x00040000>; 56 reg = <0x54180000 0x00040000>;
57 clocks = <&tegra_car 24>;
51 }; 58 };
52 59
53 dc@54200000 { 60 dc@54200000 {
54 compatible = "nvidia,tegra20-dc"; 61 compatible = "nvidia,tegra20-dc";
55 reg = <0x54200000 0x00040000>; 62 reg = <0x54200000 0x00040000>;
56 interrupts = <0 73 0x04>; 63 interrupts = <0 73 0x04>;
64 clocks = <&tegra_car 27>, <&tegra_car 121>;
65 clock-names = "disp1", "parent";
57 66
58 rgb { 67 rgb {
59 status = "disabled"; 68 status = "disabled";
@@ -64,6 +73,8 @@
64 compatible = "nvidia,tegra20-dc"; 73 compatible = "nvidia,tegra20-dc";
65 reg = <0x54240000 0x00040000>; 74 reg = <0x54240000 0x00040000>;
66 interrupts = <0 74 0x04>; 75 interrupts = <0 74 0x04>;
76 clocks = <&tegra_car 26>, <&tegra_car 121>;
77 clock-names = "disp2", "parent";
67 78
68 rgb { 79 rgb {
69 status = "disabled"; 80 status = "disabled";
@@ -74,6 +85,8 @@
74 compatible = "nvidia,tegra20-hdmi"; 85 compatible = "nvidia,tegra20-hdmi";
75 reg = <0x54280000 0x00040000>; 86 reg = <0x54280000 0x00040000>;
76 interrupts = <0 75 0x04>; 87 interrupts = <0 75 0x04>;
88 clocks = <&tegra_car 51>, <&tegra_car 117>;
89 clock-names = "hdmi", "parent";
77 status = "disabled"; 90 status = "disabled";
78 }; 91 };
79 92
@@ -81,12 +94,14 @@
81 compatible = "nvidia,tegra20-tvo"; 94 compatible = "nvidia,tegra20-tvo";
82 reg = <0x542c0000 0x00040000>; 95 reg = <0x542c0000 0x00040000>;
83 interrupts = <0 76 0x04>; 96 interrupts = <0 76 0x04>;
97 clocks = <&tegra_car 102>;
84 status = "disabled"; 98 status = "disabled";
85 }; 99 };
86 100
87 dsi { 101 dsi {
88 compatible = "nvidia,tegra20-dsi"; 102 compatible = "nvidia,tegra20-dsi";
89 reg = <0x54300000 0x00040000>; 103 reg = <0x54300000 0x00040000>;
104 clocks = <&tegra_car 48>;
90 status = "disabled"; 105 status = "disabled";
91 }; 106 };
92 }; 107 };
@@ -123,6 +138,12 @@
123 0 42 0x04>; 138 0 42 0x04>;
124 }; 139 };
125 140
141 tegra_car: clock {
142 compatible = "nvidia,tegra20-car";
143 reg = <0x60006000 0x1000>;
144 #clock-cells = <1>;
145 };
146
126 apbdma: dma { 147 apbdma: dma {
127 compatible = "nvidia,tegra20-apbdma"; 148 compatible = "nvidia,tegra20-apbdma";
128 reg = <0x6000a000 0x1200>; 149 reg = <0x6000a000 0x1200>;
@@ -142,6 +163,7 @@
142 0 117 0x04 163 0 117 0x04
143 0 118 0x04 164 0 118 0x04
144 0 119 0x04>; 165 0 119 0x04>;
166 clocks = <&tegra_car 34>;
145 }; 167 };
146 168
147 ahb { 169 ahb {
@@ -183,6 +205,7 @@
183 reg = <0x70002800 0x200>; 205 reg = <0x70002800 0x200>;
184 interrupts = <0 13 0x04>; 206 interrupts = <0 13 0x04>;
185 nvidia,dma-request-selector = <&apbdma 2>; 207 nvidia,dma-request-selector = <&apbdma 2>;
208 clocks = <&tegra_car 11>;
186 status = "disabled"; 209 status = "disabled";
187 }; 210 };
188 211
@@ -191,6 +214,7 @@
191 reg = <0x70002a00 0x200>; 214 reg = <0x70002a00 0x200>;
192 interrupts = <0 3 0x04>; 215 interrupts = <0 3 0x04>;
193 nvidia,dma-request-selector = <&apbdma 1>; 216 nvidia,dma-request-selector = <&apbdma 1>;
217 clocks = <&tegra_car 18>;
194 status = "disabled"; 218 status = "disabled";
195 }; 219 };
196 220
@@ -199,6 +223,7 @@
199 reg = <0x70006000 0x40>; 223 reg = <0x70006000 0x40>;
200 reg-shift = <2>; 224 reg-shift = <2>;
201 interrupts = <0 36 0x04>; 225 interrupts = <0 36 0x04>;
226 clocks = <&tegra_car 6>;
202 status = "disabled"; 227 status = "disabled";
203 }; 228 };
204 229
@@ -207,6 +232,7 @@
207 reg = <0x70006040 0x40>; 232 reg = <0x70006040 0x40>;
208 reg-shift = <2>; 233 reg-shift = <2>;
209 interrupts = <0 37 0x04>; 234 interrupts = <0 37 0x04>;
235 clocks = <&tegra_car 96>;
210 status = "disabled"; 236 status = "disabled";
211 }; 237 };
212 238
@@ -215,6 +241,7 @@
215 reg = <0x70006200 0x100>; 241 reg = <0x70006200 0x100>;
216 reg-shift = <2>; 242 reg-shift = <2>;
217 interrupts = <0 46 0x04>; 243 interrupts = <0 46 0x04>;
244 clocks = <&tegra_car 55>;
218 status = "disabled"; 245 status = "disabled";
219 }; 246 };
220 247
@@ -223,6 +250,7 @@
223 reg = <0x70006300 0x100>; 250 reg = <0x70006300 0x100>;
224 reg-shift = <2>; 251 reg-shift = <2>;
225 interrupts = <0 90 0x04>; 252 interrupts = <0 90 0x04>;
253 clocks = <&tegra_car 65>;
226 status = "disabled"; 254 status = "disabled";
227 }; 255 };
228 256
@@ -231,6 +259,7 @@
231 reg = <0x70006400 0x100>; 259 reg = <0x70006400 0x100>;
232 reg-shift = <2>; 260 reg-shift = <2>;
233 interrupts = <0 91 0x04>; 261 interrupts = <0 91 0x04>;
262 clocks = <&tegra_car 66>;
234 status = "disabled"; 263 status = "disabled";
235 }; 264 };
236 265
@@ -238,6 +267,7 @@
238 compatible = "nvidia,tegra20-pwm"; 267 compatible = "nvidia,tegra20-pwm";
239 reg = <0x7000a000 0x100>; 268 reg = <0x7000a000 0x100>;
240 #pwm-cells = <2>; 269 #pwm-cells = <2>;
270 clocks = <&tegra_car 17>;
241 }; 271 };
242 272
243 rtc { 273 rtc {
@@ -252,6 +282,8 @@
252 interrupts = <0 38 0x04>; 282 interrupts = <0 38 0x04>;
253 #address-cells = <1>; 283 #address-cells = <1>;
254 #size-cells = <0>; 284 #size-cells = <0>;
285 clocks = <&tegra_car 12>, <&tegra_car 124>;
286 clock-names = "div-clk", "fast-clk";
255 status = "disabled"; 287 status = "disabled";
256 }; 288 };
257 289
@@ -262,6 +294,7 @@
262 nvidia,dma-request-selector = <&apbdma 11>; 294 nvidia,dma-request-selector = <&apbdma 11>;
263 #address-cells = <1>; 295 #address-cells = <1>;
264 #size-cells = <0>; 296 #size-cells = <0>;
297 clocks = <&tegra_car 43>;
265 status = "disabled"; 298 status = "disabled";
266 }; 299 };
267 300
@@ -271,6 +304,8 @@
271 interrupts = <0 84 0x04>; 304 interrupts = <0 84 0x04>;
272 #address-cells = <1>; 305 #address-cells = <1>;
273 #size-cells = <0>; 306 #size-cells = <0>;
307 clocks = <&tegra_car 54>, <&tegra_car 124>;
308 clock-names = "div-clk", "fast-clk";
274 status = "disabled"; 309 status = "disabled";
275 }; 310 };
276 311
@@ -280,6 +315,8 @@
280 interrupts = <0 92 0x04>; 315 interrupts = <0 92 0x04>;
281 #address-cells = <1>; 316 #address-cells = <1>;
282 #size-cells = <0>; 317 #size-cells = <0>;
318 clocks = <&tegra_car 67>, <&tegra_car 124>;
319 clock-names = "div-clk", "fast-clk";
283 status = "disabled"; 320 status = "disabled";
284 }; 321 };
285 322
@@ -289,6 +326,8 @@
289 interrupts = <0 53 0x04>; 326 interrupts = <0 53 0x04>;
290 #address-cells = <1>; 327 #address-cells = <1>;
291 #size-cells = <0>; 328 #size-cells = <0>;
329 clocks = <&tegra_car 47>, <&tegra_car 124>;
330 clock-names = "div-clk", "fast-clk";
292 status = "disabled"; 331 status = "disabled";
293 }; 332 };
294 333
@@ -299,6 +338,7 @@
299 nvidia,dma-request-selector = <&apbdma 15>; 338 nvidia,dma-request-selector = <&apbdma 15>;
300 #address-cells = <1>; 339 #address-cells = <1>;
301 #size-cells = <0>; 340 #size-cells = <0>;
341 clocks = <&tegra_car 41>;
302 status = "disabled"; 342 status = "disabled";
303 }; 343 };
304 344
@@ -309,6 +349,7 @@
309 nvidia,dma-request-selector = <&apbdma 16>; 349 nvidia,dma-request-selector = <&apbdma 16>;
310 #address-cells = <1>; 350 #address-cells = <1>;
311 #size-cells = <0>; 351 #size-cells = <0>;
352 clocks = <&tegra_car 44>;
312 status = "disabled"; 353 status = "disabled";
313 }; 354 };
314 355
@@ -319,6 +360,7 @@
319 nvidia,dma-request-selector = <&apbdma 17>; 360 nvidia,dma-request-selector = <&apbdma 17>;
320 #address-cells = <1>; 361 #address-cells = <1>;
321 #size-cells = <0>; 362 #size-cells = <0>;
363 clocks = <&tegra_car 46>;
322 status = "disabled"; 364 status = "disabled";
323 }; 365 };
324 366
@@ -329,6 +371,7 @@
329 nvidia,dma-request-selector = <&apbdma 18>; 371 nvidia,dma-request-selector = <&apbdma 18>;
330 #address-cells = <1>; 372 #address-cells = <1>;
331 #size-cells = <0>; 373 #size-cells = <0>;
374 clocks = <&tegra_car 68>;
332 status = "disabled"; 375 status = "disabled";
333 }; 376 };
334 377
@@ -363,6 +406,7 @@
363 interrupts = <0 20 0x04>; 406 interrupts = <0 20 0x04>;
364 phy_type = "utmi"; 407 phy_type = "utmi";
365 nvidia,has-legacy-mode; 408 nvidia,has-legacy-mode;
409 clocks = <&tegra_car 22>;
366 status = "disabled"; 410 status = "disabled";
367 }; 411 };
368 412
@@ -371,6 +415,7 @@
371 reg = <0xc5004000 0x4000>; 415 reg = <0xc5004000 0x4000>;
372 interrupts = <0 21 0x04>; 416 interrupts = <0 21 0x04>;
373 phy_type = "ulpi"; 417 phy_type = "ulpi";
418 clocks = <&tegra_car 58>;
374 status = "disabled"; 419 status = "disabled";
375 }; 420 };
376 421
@@ -379,6 +424,7 @@
379 reg = <0xc5008000 0x4000>; 424 reg = <0xc5008000 0x4000>;
380 interrupts = <0 97 0x04>; 425 interrupts = <0 97 0x04>;
381 phy_type = "utmi"; 426 phy_type = "utmi";
427 clocks = <&tegra_car 59>;
382 status = "disabled"; 428 status = "disabled";
383 }; 429 };
384 430
@@ -386,6 +432,7 @@
386 compatible = "nvidia,tegra20-sdhci"; 432 compatible = "nvidia,tegra20-sdhci";
387 reg = <0xc8000000 0x200>; 433 reg = <0xc8000000 0x200>;
388 interrupts = <0 14 0x04>; 434 interrupts = <0 14 0x04>;
435 clocks = <&tegra_car 14>;
389 status = "disabled"; 436 status = "disabled";
390 }; 437 };
391 438
@@ -393,6 +440,7 @@
393 compatible = "nvidia,tegra20-sdhci"; 440 compatible = "nvidia,tegra20-sdhci";
394 reg = <0xc8000200 0x200>; 441 reg = <0xc8000200 0x200>;
395 interrupts = <0 15 0x04>; 442 interrupts = <0 15 0x04>;
443 clocks = <&tegra_car 9>;
396 status = "disabled"; 444 status = "disabled";
397 }; 445 };
398 446
@@ -400,6 +448,7 @@
400 compatible = "nvidia,tegra20-sdhci"; 448 compatible = "nvidia,tegra20-sdhci";
401 reg = <0xc8000400 0x200>; 449 reg = <0xc8000400 0x200>;
402 interrupts = <0 19 0x04>; 450 interrupts = <0 19 0x04>;
451 clocks = <&tegra_car 69>;
403 status = "disabled"; 452 status = "disabled";
404 }; 453 };
405 454
@@ -407,6 +456,7 @@
407 compatible = "nvidia,tegra20-sdhci"; 456 compatible = "nvidia,tegra20-sdhci";
408 reg = <0xc8000600 0x200>; 457 reg = <0xc8000600 0x200>;
409 interrupts = <0 31 0x04>; 458 interrupts = <0 31 0x04>;
459 clocks = <&tegra_car 15>;
410 status = "disabled"; 460 status = "disabled";
411 }; 461 };
412 462
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 529fdb82dfdb..b1483d925878 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -9,6 +9,7 @@
9 reg = <0x50000000 0x00024000>; 9 reg = <0x50000000 0x00024000>;
10 interrupts = <0 65 0x04 /* mpcore syncpt */ 10 interrupts = <0 65 0x04 /* mpcore syncpt */
11 0 67 0x04>; /* mpcore general */ 11 0 67 0x04>; /* mpcore general */
12 clocks = <&tegra_car 28>;
12 13
13 #address-cells = <1>; 14 #address-cells = <1>;
14 #size-cells = <1>; 15 #size-cells = <1>;
@@ -19,41 +20,50 @@
19 compatible = "nvidia,tegra30-mpe"; 20 compatible = "nvidia,tegra30-mpe";
20 reg = <0x54040000 0x00040000>; 21 reg = <0x54040000 0x00040000>;
21 interrupts = <0 68 0x04>; 22 interrupts = <0 68 0x04>;
23 clocks = <&tegra_car 60>;
22 }; 24 };
23 25
24 vi { 26 vi {
25 compatible = "nvidia,tegra30-vi"; 27 compatible = "nvidia,tegra30-vi";
26 reg = <0x54080000 0x00040000>; 28 reg = <0x54080000 0x00040000>;
27 interrupts = <0 69 0x04>; 29 interrupts = <0 69 0x04>;
30 clocks = <&tegra_car 164>;
28 }; 31 };
29 32
30 epp { 33 epp {
31 compatible = "nvidia,tegra30-epp"; 34 compatible = "nvidia,tegra30-epp";
32 reg = <0x540c0000 0x00040000>; 35 reg = <0x540c0000 0x00040000>;
33 interrupts = <0 70 0x04>; 36 interrupts = <0 70 0x04>;
37 clocks = <&tegra_car 19>;
34 }; 38 };
35 39
36 isp { 40 isp {
37 compatible = "nvidia,tegra30-isp"; 41 compatible = "nvidia,tegra30-isp";
38 reg = <0x54100000 0x00040000>; 42 reg = <0x54100000 0x00040000>;
39 interrupts = <0 71 0x04>; 43 interrupts = <0 71 0x04>;
44 clocks = <&tegra_car 23>;
40 }; 45 };
41 46
42 gr2d { 47 gr2d {
43 compatible = "nvidia,tegra30-gr2d"; 48 compatible = "nvidia,tegra30-gr2d";
44 reg = <0x54140000 0x00040000>; 49 reg = <0x54140000 0x00040000>;
45 interrupts = <0 72 0x04>; 50 interrupts = <0 72 0x04>;
51 clocks = <&tegra_car 21>;
46 }; 52 };
47 53
48 gr3d { 54 gr3d {
49 compatible = "nvidia,tegra30-gr3d"; 55 compatible = "nvidia,tegra30-gr3d";
50 reg = <0x54180000 0x00040000>; 56 reg = <0x54180000 0x00040000>;
57 clocks = <&tegra_car 24 &tegra_car 98>;
58 clock-names = "3d", "3d2";
51 }; 59 };
52 60
53 dc@54200000 { 61 dc@54200000 {
54 compatible = "nvidia,tegra30-dc"; 62 compatible = "nvidia,tegra30-dc";
55 reg = <0x54200000 0x00040000>; 63 reg = <0x54200000 0x00040000>;
56 interrupts = <0 73 0x04>; 64 interrupts = <0 73 0x04>;
65 clocks = <&tegra_car 27>, <&tegra_car 179>;
66 clock-names = "disp1", "parent";
57 67
58 rgb { 68 rgb {
59 status = "disabled"; 69 status = "disabled";
@@ -64,6 +74,8 @@
64 compatible = "nvidia,tegra30-dc"; 74 compatible = "nvidia,tegra30-dc";
65 reg = <0x54240000 0x00040000>; 75 reg = <0x54240000 0x00040000>;
66 interrupts = <0 74 0x04>; 76 interrupts = <0 74 0x04>;
77 clocks = <&tegra_car 26>, <&tegra_car 179>;
78 clock-names = "disp2", "parent";
67 79
68 rgb { 80 rgb {
69 status = "disabled"; 81 status = "disabled";
@@ -74,6 +86,8 @@
74 compatible = "nvidia,tegra30-hdmi"; 86 compatible = "nvidia,tegra30-hdmi";
75 reg = <0x54280000 0x00040000>; 87 reg = <0x54280000 0x00040000>;
76 interrupts = <0 75 0x04>; 88 interrupts = <0 75 0x04>;
89 clocks = <&tegra_car 51>, <&tegra_car 189>;
90 clock-names = "hdmi", "parent";
77 status = "disabled"; 91 status = "disabled";
78 }; 92 };
79 93
@@ -81,12 +95,14 @@
81 compatible = "nvidia,tegra30-tvo"; 95 compatible = "nvidia,tegra30-tvo";
82 reg = <0x542c0000 0x00040000>; 96 reg = <0x542c0000 0x00040000>;
83 interrupts = <0 76 0x04>; 97 interrupts = <0 76 0x04>;
98 clocks = <&tegra_car 169>;
84 status = "disabled"; 99 status = "disabled";
85 }; 100 };
86 101
87 dsi { 102 dsi {
88 compatible = "nvidia,tegra30-dsi"; 103 compatible = "nvidia,tegra30-dsi";
89 reg = <0x54300000 0x00040000>; 104 reg = <0x54300000 0x00040000>;
105 clocks = <&tegra_car 48>;
90 status = "disabled"; 106 status = "disabled";
91 }; 107 };
92 }; 108 };
@@ -125,6 +141,12 @@
125 0 122 0x04>; 141 0 122 0x04>;
126 }; 142 };
127 143
144 tegra_car: clock {
145 compatible = "nvidia,tegra30-car";
146 reg = <0x60006000 0x1000>;
147 #clock-cells = <1>;
148 };
149
128 apbdma: dma { 150 apbdma: dma {
129 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; 151 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
130 reg = <0x6000a000 0x1400>; 152 reg = <0x6000a000 0x1400>;
@@ -160,6 +182,7 @@
160 0 141 0x04 182 0 141 0x04
161 0 142 0x04 183 0 142 0x04
162 0 143 0x04>; 184 0 143 0x04>;
185 clocks = <&tegra_car 34>;
163 }; 186 };
164 187
165 ahb: ahb { 188 ahb: ahb {
@@ -195,6 +218,7 @@
195 reg = <0x70006000 0x40>; 218 reg = <0x70006000 0x40>;
196 reg-shift = <2>; 219 reg-shift = <2>;
197 interrupts = <0 36 0x04>; 220 interrupts = <0 36 0x04>;
221 clocks = <&tegra_car 6>;
198 status = "disabled"; 222 status = "disabled";
199 }; 223 };
200 224
@@ -203,6 +227,7 @@
203 reg = <0x70006040 0x40>; 227 reg = <0x70006040 0x40>;
204 reg-shift = <2>; 228 reg-shift = <2>;
205 interrupts = <0 37 0x04>; 229 interrupts = <0 37 0x04>;
230 clocks = <&tegra_car 160>;
206 status = "disabled"; 231 status = "disabled";
207 }; 232 };
208 233
@@ -211,6 +236,7 @@
211 reg = <0x70006200 0x100>; 236 reg = <0x70006200 0x100>;
212 reg-shift = <2>; 237 reg-shift = <2>;
213 interrupts = <0 46 0x04>; 238 interrupts = <0 46 0x04>;
239 clocks = <&tegra_car 55>;
214 status = "disabled"; 240 status = "disabled";
215 }; 241 };
216 242
@@ -219,6 +245,7 @@
219 reg = <0x70006300 0x100>; 245 reg = <0x70006300 0x100>;
220 reg-shift = <2>; 246 reg-shift = <2>;
221 interrupts = <0 90 0x04>; 247 interrupts = <0 90 0x04>;
248 clocks = <&tegra_car 65>;
222 status = "disabled"; 249 status = "disabled";
223 }; 250 };
224 251
@@ -227,6 +254,7 @@
227 reg = <0x70006400 0x100>; 254 reg = <0x70006400 0x100>;
228 reg-shift = <2>; 255 reg-shift = <2>;
229 interrupts = <0 91 0x04>; 256 interrupts = <0 91 0x04>;
257 clocks = <&tegra_car 66>;
230 status = "disabled"; 258 status = "disabled";
231 }; 259 };
232 260
@@ -234,6 +262,7 @@
234 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; 262 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
235 reg = <0x7000a000 0x100>; 263 reg = <0x7000a000 0x100>;
236 #pwm-cells = <2>; 264 #pwm-cells = <2>;
265 clocks = <&tegra_car 17>;
237 }; 266 };
238 267
239 rtc { 268 rtc {
@@ -248,6 +277,8 @@
248 interrupts = <0 38 0x04>; 277 interrupts = <0 38 0x04>;
249 #address-cells = <1>; 278 #address-cells = <1>;
250 #size-cells = <0>; 279 #size-cells = <0>;
280 clocks = <&tegra_car 12>, <&tegra_car 182>;
281 clock-names = "div-clk", "fast-clk";
251 status = "disabled"; 282 status = "disabled";
252 }; 283 };
253 284
@@ -257,6 +288,8 @@
257 interrupts = <0 84 0x04>; 288 interrupts = <0 84 0x04>;
258 #address-cells = <1>; 289 #address-cells = <1>;
259 #size-cells = <0>; 290 #size-cells = <0>;
291 clocks = <&tegra_car 54>, <&tegra_car 182>;
292 clock-names = "div-clk", "fast-clk";
260 status = "disabled"; 293 status = "disabled";
261 }; 294 };
262 295
@@ -266,6 +299,8 @@
266 interrupts = <0 92 0x04>; 299 interrupts = <0 92 0x04>;
267 #address-cells = <1>; 300 #address-cells = <1>;
268 #size-cells = <0>; 301 #size-cells = <0>;
302 clocks = <&tegra_car 67>, <&tegra_car 182>;
303 clock-names = "div-clk", "fast-clk";
269 status = "disabled"; 304 status = "disabled";
270 }; 305 };
271 306
@@ -275,6 +310,8 @@
275 interrupts = <0 120 0x04>; 310 interrupts = <0 120 0x04>;
276 #address-cells = <1>; 311 #address-cells = <1>;
277 #size-cells = <0>; 312 #size-cells = <0>;
313 clocks = <&tegra_car 103>, <&tegra_car 182>;
314 clock-names = "div-clk", "fast-clk";
278 status = "disabled"; 315 status = "disabled";
279 }; 316 };
280 317
@@ -284,6 +321,8 @@
284 interrupts = <0 53 0x04>; 321 interrupts = <0 53 0x04>;
285 #address-cells = <1>; 322 #address-cells = <1>;
286 #size-cells = <0>; 323 #size-cells = <0>;
324 clocks = <&tegra_car 47>, <&tegra_car 182>;
325 clock-names = "div-clk", "fast-clk";
287 status = "disabled"; 326 status = "disabled";
288 }; 327 };
289 328
@@ -294,6 +333,7 @@
294 nvidia,dma-request-selector = <&apbdma 15>; 333 nvidia,dma-request-selector = <&apbdma 15>;
295 #address-cells = <1>; 334 #address-cells = <1>;
296 #size-cells = <0>; 335 #size-cells = <0>;
336 clocks = <&tegra_car 41>;
297 status = "disabled"; 337 status = "disabled";
298 }; 338 };
299 339
@@ -304,6 +344,7 @@
304 nvidia,dma-request-selector = <&apbdma 16>; 344 nvidia,dma-request-selector = <&apbdma 16>;
305 #address-cells = <1>; 345 #address-cells = <1>;
306 #size-cells = <0>; 346 #size-cells = <0>;
347 clocks = <&tegra_car 44>;
307 status = "disabled"; 348 status = "disabled";
308 }; 349 };
309 350
@@ -314,6 +355,7 @@
314 nvidia,dma-request-selector = <&apbdma 17>; 355 nvidia,dma-request-selector = <&apbdma 17>;
315 #address-cells = <1>; 356 #address-cells = <1>;
316 #size-cells = <0>; 357 #size-cells = <0>;
358 clocks = <&tegra_car 46>;
317 status = "disabled"; 359 status = "disabled";
318 }; 360 };
319 361
@@ -324,6 +366,7 @@
324 nvidia,dma-request-selector = <&apbdma 18>; 366 nvidia,dma-request-selector = <&apbdma 18>;
325 #address-cells = <1>; 367 #address-cells = <1>;
326 #size-cells = <0>; 368 #size-cells = <0>;
369 clocks = <&tegra_car 68>;
327 status = "disabled"; 370 status = "disabled";
328 }; 371 };
329 372
@@ -334,6 +377,7 @@
334 nvidia,dma-request-selector = <&apbdma 27>; 377 nvidia,dma-request-selector = <&apbdma 27>;
335 #address-cells = <1>; 378 #address-cells = <1>;
336 #size-cells = <0>; 379 #size-cells = <0>;
380 clocks = <&tegra_car 104>;
337 status = "disabled"; 381 status = "disabled";
338 }; 382 };
339 383
@@ -344,6 +388,7 @@
344 nvidia,dma-request-selector = <&apbdma 28>; 388 nvidia,dma-request-selector = <&apbdma 28>;
345 #address-cells = <1>; 389 #address-cells = <1>;
346 #size-cells = <0>; 390 #size-cells = <0>;
391 clocks = <&tegra_car 105>;
347 status = "disabled"; 392 status = "disabled";
348 }; 393 };
349 394
@@ -377,7 +422,13 @@
377 0x70080200 0x100>; 422 0x70080200 0x100>;
378 interrupts = <0 103 0x04>; 423 interrupts = <0 103 0x04>;
379 nvidia,dma-request-selector = <&apbdma 1>; 424 nvidia,dma-request-selector = <&apbdma 1>;
380 425 clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
426 <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
427 <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
428 <&tegra_car 110>, <&tegra_car 162>;
429 clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
430 "i2s3", "i2s4", "dam0", "dam1", "dam2",
431 "spdif_in";
381 ranges; 432 ranges;
382 #address-cells = <1>; 433 #address-cells = <1>;
383 #size-cells = <1>; 434 #size-cells = <1>;
@@ -386,6 +437,7 @@
386 compatible = "nvidia,tegra30-i2s"; 437 compatible = "nvidia,tegra30-i2s";
387 reg = <0x70080300 0x100>; 438 reg = <0x70080300 0x100>;
388 nvidia,ahub-cif-ids = <4 4>; 439 nvidia,ahub-cif-ids = <4 4>;
440 clocks = <&tegra_car 30>;
389 status = "disabled"; 441 status = "disabled";
390 }; 442 };
391 443
@@ -393,6 +445,7 @@
393 compatible = "nvidia,tegra30-i2s"; 445 compatible = "nvidia,tegra30-i2s";
394 reg = <0x70080400 0x100>; 446 reg = <0x70080400 0x100>;
395 nvidia,ahub-cif-ids = <5 5>; 447 nvidia,ahub-cif-ids = <5 5>;
448 clocks = <&tegra_car 11>;
396 status = "disabled"; 449 status = "disabled";
397 }; 450 };
398 451
@@ -400,6 +453,7 @@
400 compatible = "nvidia,tegra30-i2s"; 453 compatible = "nvidia,tegra30-i2s";
401 reg = <0x70080500 0x100>; 454 reg = <0x70080500 0x100>;
402 nvidia,ahub-cif-ids = <6 6>; 455 nvidia,ahub-cif-ids = <6 6>;
456 clocks = <&tegra_car 18>;
403 status = "disabled"; 457 status = "disabled";
404 }; 458 };
405 459
@@ -407,6 +461,7 @@
407 compatible = "nvidia,tegra30-i2s"; 461 compatible = "nvidia,tegra30-i2s";
408 reg = <0x70080600 0x100>; 462 reg = <0x70080600 0x100>;
409 nvidia,ahub-cif-ids = <7 7>; 463 nvidia,ahub-cif-ids = <7 7>;
464 clocks = <&tegra_car 101>;
410 status = "disabled"; 465 status = "disabled";
411 }; 466 };
412 467
@@ -414,6 +469,7 @@
414 compatible = "nvidia,tegra30-i2s"; 469 compatible = "nvidia,tegra30-i2s";
415 reg = <0x70080700 0x100>; 470 reg = <0x70080700 0x100>;
416 nvidia,ahub-cif-ids = <8 8>; 471 nvidia,ahub-cif-ids = <8 8>;
472 clocks = <&tegra_car 102>;
417 status = "disabled"; 473 status = "disabled";
418 }; 474 };
419 }; 475 };
@@ -422,6 +478,7 @@
422 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 478 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
423 reg = <0x78000000 0x200>; 479 reg = <0x78000000 0x200>;
424 interrupts = <0 14 0x04>; 480 interrupts = <0 14 0x04>;
481 clocks = <&tegra_car 14>;
425 status = "disabled"; 482 status = "disabled";
426 }; 483 };
427 484
@@ -429,6 +486,7 @@
429 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 486 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
430 reg = <0x78000200 0x200>; 487 reg = <0x78000200 0x200>;
431 interrupts = <0 15 0x04>; 488 interrupts = <0 15 0x04>;
489 clocks = <&tegra_car 9>;
432 status = "disabled"; 490 status = "disabled";
433 }; 491 };
434 492
@@ -436,6 +494,7 @@
436 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 494 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
437 reg = <0x78000400 0x200>; 495 reg = <0x78000400 0x200>;
438 interrupts = <0 19 0x04>; 496 interrupts = <0 19 0x04>;
497 clocks = <&tegra_car 69>;
439 status = "disabled"; 498 status = "disabled";
440 }; 499 };
441 500
@@ -443,6 +502,7 @@
443 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 502 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
444 reg = <0x78000600 0x200>; 503 reg = <0x78000600 0x200>;
445 interrupts = <0 31 0x04>; 504 interrupts = <0 31 0x04>;
505 clocks = <&tegra_car 15>;
446 status = "disabled"; 506 status = "disabled";
447 }; 507 };
448 508
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index b442f15fd01a..1ec7f80e2af5 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -6,9 +6,9 @@ config ARCH_TEGRA_2x_SOC
6 bool "Enable support for Tegra20 family" 6 bool "Enable support for Tegra20 family"
7 select ARCH_REQUIRE_GPIOLIB 7 select ARCH_REQUIRE_GPIOLIB
8 select ARM_ERRATA_720789 8 select ARM_ERRATA_720789
9 select ARM_ERRATA_742230 9 select ARM_ERRATA_742230 if SMP
10 select ARM_ERRATA_751472 10 select ARM_ERRATA_751472
11 select ARM_ERRATA_754327 11 select ARM_ERRATA_754327 if SMP
12 select ARM_ERRATA_764369 if SMP 12 select ARM_ERRATA_764369 if SMP
13 select ARM_GIC 13 select ARM_GIC
14 select CPU_FREQ_TABLE if CPU_FREQ 14 select CPU_FREQ_TABLE if CPU_FREQ
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 0979e8bba78a..6018a05e808c 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,33 +1,28 @@
1obj-y += common.o 1obj-y += common.o
2obj-y += io.o 2obj-y += io.o
3obj-y += irq.o 3obj-y += irq.o
4obj-y += clock.o
5obj-y += timer.o
6obj-y += fuse.o 4obj-y += fuse.o
7obj-y += pmc.o 5obj-y += pmc.o
8obj-y += flowctrl.o 6obj-y += flowctrl.o
9obj-y += powergate.o 7obj-y += powergate.o
10obj-y += apbio.o 8obj-y += apbio.o
11obj-y += pm.o 9obj-y += pm.o
10obj-y += reset.o
11obj-y += reset-handler.o
12obj-y += sleep.o
12obj-$(CONFIG_CPU_IDLE) += cpuidle.o 13obj-$(CONFIG_CPU_IDLE) += cpuidle.o
13obj-$(CONFIG_CPU_IDLE) += sleep.o
14obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks.o
15obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks_data.o
16obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_speedo.o 14obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_speedo.o
17obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o 15obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o
18obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-tegra20.o 16obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-tegra20.o
19ifeq ($(CONFIG_CPU_IDLE),y) 17ifeq ($(CONFIG_CPU_IDLE),y)
20obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += cpuidle-tegra20.o 18obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += cpuidle-tegra20.o
21endif 19endif
22obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o
23obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks_data.o
24obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_speedo.o 20obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_speedo.o
25obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-tegra30.o 21obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-tegra30.o
26ifeq ($(CONFIG_CPU_IDLE),y) 22ifeq ($(CONFIG_CPU_IDLE),y)
27obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o 23obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o
28endif 24endif
29obj-$(CONFIG_SMP) += platsmp.o headsmp.o 25obj-$(CONFIG_SMP) += platsmp.o headsmp.o
30obj-$(CONFIG_SMP) += reset.o
31obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 26obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
32obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o 27obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o
33obj-$(CONFIG_TEGRA_PCI) += pcie.o 28obj-$(CONFIG_TEGRA_PCI) += pcie.o
diff --git a/arch/arm/mach-tegra/apbio.c b/arch/arm/mach-tegra/apbio.c
index d091675ba376..d7aa52ea6cfc 100644
--- a/arch/arm/mach-tegra/apbio.c
+++ b/arch/arm/mach-tegra/apbio.c
@@ -38,7 +38,7 @@ static void tegra_apb_writel_direct(u32 value, unsigned long offset);
38static struct dma_chan *tegra_apb_dma_chan; 38static struct dma_chan *tegra_apb_dma_chan;
39static struct dma_slave_config dma_sconfig; 39static struct dma_slave_config dma_sconfig;
40 40
41bool tegra_apb_dma_init(void) 41static bool tegra_apb_dma_init(void)
42{ 42{
43 dma_cap_mask_t mask; 43 dma_cap_mask_t mask;
44 44
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index 5ed81bab2d4b..abdbe9e658f9 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -15,6 +15,7 @@
15 * 15 *
16 */ 16 */
17 17
18#include <linux/clocksource.h>
18#include <linux/kernel.h> 19#include <linux/kernel.h>
19#include <linux/init.h> 20#include <linux/init.h>
20#include <linux/platform_device.h> 21#include <linux/platform_device.h>
@@ -39,99 +40,45 @@
39#include <asm/setup.h> 40#include <asm/setup.h>
40 41
41#include "board.h" 42#include "board.h"
42#include "clock.h"
43#include "common.h" 43#include "common.h"
44#include "iomap.h" 44#include "iomap.h"
45 45
46struct tegra_ehci_platform_data tegra_ehci1_pdata = { 46static struct tegra_ehci_platform_data tegra_ehci1_pdata = {
47 .operating_mode = TEGRA_USB_OTG, 47 .operating_mode = TEGRA_USB_OTG,
48 .power_down_on_bus_suspend = 1, 48 .power_down_on_bus_suspend = 1,
49 .vbus_gpio = -1, 49 .vbus_gpio = -1,
50}; 50};
51 51
52struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = { 52static struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
53 .reset_gpio = -1, 53 .reset_gpio = -1,
54 .clk = "cdev2", 54 .clk = "cdev2",
55}; 55};
56 56
57struct tegra_ehci_platform_data tegra_ehci2_pdata = { 57static struct tegra_ehci_platform_data tegra_ehci2_pdata = {
58 .phy_config = &tegra_ehci2_ulpi_phy_config, 58 .phy_config = &tegra_ehci2_ulpi_phy_config,
59 .operating_mode = TEGRA_USB_HOST, 59 .operating_mode = TEGRA_USB_HOST,
60 .power_down_on_bus_suspend = 1, 60 .power_down_on_bus_suspend = 1,
61 .vbus_gpio = -1, 61 .vbus_gpio = -1,
62}; 62};
63 63
64struct tegra_ehci_platform_data tegra_ehci3_pdata = { 64static struct tegra_ehci_platform_data tegra_ehci3_pdata = {
65 .operating_mode = TEGRA_USB_HOST, 65 .operating_mode = TEGRA_USB_HOST,
66 .power_down_on_bus_suspend = 1, 66 .power_down_on_bus_suspend = 1,
67 .vbus_gpio = -1, 67 .vbus_gpio = -1,
68}; 68};
69 69
70struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { 70static struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
71 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL),
72 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL),
73 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL),
74 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC4_BASE, "sdhci-tegra.3", NULL),
75 OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C_BASE, "tegra-i2c.0", NULL),
76 OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C2_BASE, "tegra-i2c.1", NULL),
77 OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C3_BASE, "tegra-i2c.2", NULL),
78 OF_DEV_AUXDATA("nvidia,tegra20-i2c-dvc", TEGRA_DVC_BASE, "tegra-i2c.3", NULL),
79 OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra20-i2s.0", NULL),
80 OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S2_BASE, "tegra20-i2s.1", NULL),
81 OF_DEV_AUXDATA("nvidia,tegra20-das", TEGRA_APB_MISC_DAS_BASE, "tegra20-das", NULL),
82 OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB_BASE, "tegra-ehci.0", 71 OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB_BASE, "tegra-ehci.0",
83 &tegra_ehci1_pdata), 72 &tegra_ehci1_pdata),
84 OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB2_BASE, "tegra-ehci.1", 73 OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB2_BASE, "tegra-ehci.1",
85 &tegra_ehci2_pdata), 74 &tegra_ehci2_pdata),
86 OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB3_BASE, "tegra-ehci.2", 75 OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB3_BASE, "tegra-ehci.2",
87 &tegra_ehci3_pdata), 76 &tegra_ehci3_pdata),
88 OF_DEV_AUXDATA("nvidia,tegra20-apbdma", TEGRA_APB_DMA_BASE, "tegra-apbdma", NULL),
89 OF_DEV_AUXDATA("nvidia,tegra20-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
90 OF_DEV_AUXDATA("nvidia,tegra20-sflash", 0x7000c380, "spi", NULL),
91 OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D400, "spi_tegra.0", NULL),
92 OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D600, "spi_tegra.1", NULL),
93 OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D800, "spi_tegra.2", NULL),
94 OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000DA00, "spi_tegra.3", NULL),
95 OF_DEV_AUXDATA("nvidia,tegra20-host1x", 0x50000000, "host1x", NULL),
96 OF_DEV_AUXDATA("nvidia,tegra20-dc", 0x54200000, "tegradc.0", NULL),
97 OF_DEV_AUXDATA("nvidia,tegra20-dc", 0x54240000, "tegradc.1", NULL),
98 OF_DEV_AUXDATA("nvidia,tegra20-hdmi", 0x54280000, "hdmi", NULL),
99 OF_DEV_AUXDATA("nvidia,tegra20-dsi", 0x54300000, "dsi", NULL),
100 OF_DEV_AUXDATA("nvidia,tegra20-tvo", 0x542c0000, "tvo", NULL),
101 {} 77 {}
102}; 78};
103 79
104static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
105 /* name parent rate enabled */
106 { "uarta", "pll_p", 216000000, true },
107 { "uartd", "pll_p", 216000000, true },
108 { "usbd", "clk_m", 12000000, false },
109 { "usb2", "clk_m", 12000000, false },
110 { "usb3", "clk_m", 12000000, false },
111 { "pll_a", "pll_p_out1", 56448000, true },
112 { "pll_a_out0", "pll_a", 11289600, true },
113 { "cdev1", NULL, 0, true },
114 { "blink", "clk_32k", 32768, true },
115 { "i2s1", "pll_a_out0", 11289600, false},
116 { "i2s2", "pll_a_out0", 11289600, false},
117 { "sdmmc1", "pll_p", 48000000, false},
118 { "sdmmc3", "pll_p", 48000000, false},
119 { "sdmmc4", "pll_p", 48000000, false},
120 { "spi", "pll_p", 20000000, false },
121 { "sbc1", "pll_p", 100000000, false },
122 { "sbc2", "pll_p", 100000000, false },
123 { "sbc3", "pll_p", 100000000, false },
124 { "sbc4", "pll_p", 100000000, false },
125 { "host1x", "pll_c", 150000000, false },
126 { "disp1", "pll_p", 600000000, false },
127 { "disp2", "pll_p", 600000000, false },
128 { NULL, NULL, 0, 0},
129};
130
131static void __init tegra_dt_init(void) 80static void __init tegra_dt_init(void)
132{ 81{
133 tegra_clk_init_from_table(tegra_dt_clk_init_table);
134
135 /* 82 /*
136 * Finished with the static registrations now; fill in the missing 83 * Finished with the static registrations now; fill in the missing
137 * devices 84 * devices
@@ -200,7 +147,7 @@ DT_MACHINE_START(TEGRA_DT, "nVidia Tegra20 (Flattened Device Tree)")
200 .smp = smp_ops(tegra_smp_ops), 147 .smp = smp_ops(tegra_smp_ops),
201 .init_early = tegra20_init_early, 148 .init_early = tegra20_init_early,
202 .init_irq = tegra_dt_init_irq, 149 .init_irq = tegra_dt_init_irq,
203 .init_time = tegra_init_timer, 150 .init_time = clocksource_of_init,
204 .init_machine = tegra_dt_init, 151 .init_machine = tegra_dt_init,
205 .init_late = tegra_dt_init_late, 152 .init_late = tegra_dt_init_late,
206 .restart = tegra_assert_system_reset, 153 .restart = tegra_assert_system_reset,
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c
index 12dc2ddeca64..bf68567e549d 100644
--- a/arch/arm/mach-tegra/board-dt-tegra30.c
+++ b/arch/arm/mach-tegra/board-dt-tegra30.c
@@ -23,6 +23,7 @@
23 * 23 *
24 */ 24 */
25 25
26#include <linux/clocksource.h>
26#include <linux/kernel.h> 27#include <linux/kernel.h>
27#include <linux/of.h> 28#include <linux/of.h>
28#include <linux/of_address.h> 29#include <linux/of_address.h>
@@ -33,72 +34,12 @@
33#include <asm/mach/arch.h> 34#include <asm/mach/arch.h>
34 35
35#include "board.h" 36#include "board.h"
36#include "clock.h"
37#include "common.h" 37#include "common.h"
38#include "iomap.h" 38#include "iomap.h"
39 39
40struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
41 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000000, "sdhci-tegra.0", NULL),
42 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000200, "sdhci-tegra.1", NULL),
43 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000400, "sdhci-tegra.2", NULL),
44 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000600, "sdhci-tegra.3", NULL),
45 OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C000, "tegra-i2c.0", NULL),
46 OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C400, "tegra-i2c.1", NULL),
47 OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C500, "tegra-i2c.2", NULL),
48 OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C700, "tegra-i2c.3", NULL),
49 OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000D000, "tegra-i2c.4", NULL),
50 OF_DEV_AUXDATA("nvidia,tegra30-ahub", 0x70080000, "tegra30-ahub", NULL),
51 OF_DEV_AUXDATA("nvidia,tegra30-apbdma", 0x6000a000, "tegra-apbdma", NULL),
52 OF_DEV_AUXDATA("nvidia,tegra30-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
53 OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D400, "spi_tegra.0", NULL),
54 OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D600, "spi_tegra.1", NULL),
55 OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D800, "spi_tegra.2", NULL),
56 OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DA00, "spi_tegra.3", NULL),
57 OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DC00, "spi_tegra.4", NULL),
58 OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DE00, "spi_tegra.5", NULL),
59 OF_DEV_AUXDATA("nvidia,tegra30-host1x", 0x50000000, "host1x", NULL),
60 OF_DEV_AUXDATA("nvidia,tegra30-dc", 0x54200000, "tegradc.0", NULL),
61 OF_DEV_AUXDATA("nvidia,tegra30-dc", 0x54240000, "tegradc.1", NULL),
62 OF_DEV_AUXDATA("nvidia,tegra30-hdmi", 0x54280000, "hdmi", NULL),
63 OF_DEV_AUXDATA("nvidia,tegra30-dsi", 0x54300000, "dsi", NULL),
64 OF_DEV_AUXDATA("nvidia,tegra30-tvo", 0x542c0000, "tvo", NULL),
65 {}
66};
67
68static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
69 /* name parent rate enabled */
70 { "uarta", "pll_p", 408000000, true },
71 { "pll_a", "pll_p_out1", 564480000, true },
72 { "pll_a_out0", "pll_a", 11289600, true },
73 { "extern1", "pll_a_out0", 0, true },
74 { "clk_out_1", "extern1", 0, true },
75 { "blink", "clk_32k", 32768, true },
76 { "i2s0", "pll_a_out0", 11289600, false},
77 { "i2s1", "pll_a_out0", 11289600, false},
78 { "i2s2", "pll_a_out0", 11289600, false},
79 { "i2s3", "pll_a_out0", 11289600, false},
80 { "i2s4", "pll_a_out0", 11289600, false},
81 { "sdmmc1", "pll_p", 48000000, false},
82 { "sdmmc3", "pll_p", 48000000, false},
83 { "sdmmc4", "pll_p", 48000000, false},
84 { "sbc1", "pll_p", 100000000, false},
85 { "sbc2", "pll_p", 100000000, false},
86 { "sbc3", "pll_p", 100000000, false},
87 { "sbc4", "pll_p", 100000000, false},
88 { "sbc5", "pll_p", 100000000, false},
89 { "sbc6", "pll_p", 100000000, false},
90 { "host1x", "pll_c", 150000000, false},
91 { "disp1", "pll_p", 600000000, false},
92 { "disp2", "pll_p", 600000000, false},
93 { NULL, NULL, 0, 0},
94};
95
96static void __init tegra30_dt_init(void) 40static void __init tegra30_dt_init(void)
97{ 41{
98 tegra_clk_init_from_table(tegra_dt_clk_init_table); 42 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
99
100 of_platform_populate(NULL, of_default_bus_match_table,
101 tegra30_auxdata_lookup, NULL);
102} 43}
103 44
104static const char *tegra30_dt_board_compat[] = { 45static const char *tegra30_dt_board_compat[] = {
@@ -111,7 +52,7 @@ DT_MACHINE_START(TEGRA30_DT, "NVIDIA Tegra30 (Flattened Device Tree)")
111 .map_io = tegra_map_common_io, 52 .map_io = tegra_map_common_io,
112 .init_early = tegra30_init_early, 53 .init_early = tegra30_init_early,
113 .init_irq = tegra_dt_init_irq, 54 .init_irq = tegra_dt_init_irq,
114 .init_time = tegra_init_timer, 55 .init_time = clocksource_of_init,
115 .init_machine = tegra30_dt_init, 56 .init_machine = tegra30_dt_init,
116 .init_late = tegra_init_late, 57 .init_late = tegra_init_late,
117 .restart = tegra_assert_system_reset, 58 .restart = tegra_assert_system_reset,
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
index 744cdd246f6a..da8f5a3c4240 100644
--- a/arch/arm/mach-tegra/board.h
+++ b/arch/arm/mach-tegra/board.h
@@ -55,5 +55,4 @@ static inline int harmony_pcie_init(void) { return 0; }
55 55
56void __init tegra_paz00_wifikill_init(void); 56void __init tegra_paz00_wifikill_init(void);
57 57
58extern void tegra_init_timer(void);
59#endif 58#endif
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
deleted file mode 100644
index 867bf8bf5561..000000000000
--- a/arch/arm/mach-tegra/clock.c
+++ /dev/null
@@ -1,166 +0,0 @@
1/*
2 *
3 * Copyright (C) 2010 Google, Inc.
4 * Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#include <linux/kernel.h>
21#include <linux/clk.h>
22#include <linux/clkdev.h>
23#include <linux/init.h>
24#include <linux/list.h>
25#include <linux/module.h>
26#include <linux/sched.h>
27#include <linux/seq_file.h>
28#include <linux/slab.h>
29
30#include "board.h"
31#include "clock.h"
32#include "tegra_cpu_car.h"
33
34/* Global data of Tegra CPU CAR ops */
35struct tegra_cpu_car_ops *tegra_cpu_car_ops;
36
37/*
38 * Locking:
39 *
40 * An additional mutex, clock_list_lock, is used to protect the list of all
41 * clocks.
42 *
43 */
44static DEFINE_MUTEX(clock_list_lock);
45static LIST_HEAD(clocks);
46
47void tegra_clk_add(struct clk *clk)
48{
49 struct clk_tegra *c = to_clk_tegra(__clk_get_hw(clk));
50
51 mutex_lock(&clock_list_lock);
52 list_add(&c->node, &clocks);
53 mutex_unlock(&clock_list_lock);
54}
55
56struct clk *tegra_get_clock_by_name(const char *name)
57{
58 struct clk_tegra *c;
59 struct clk *ret = NULL;
60 mutex_lock(&clock_list_lock);
61 list_for_each_entry(c, &clocks, node) {
62 if (strcmp(__clk_get_name(c->hw.clk), name) == 0) {
63 ret = c->hw.clk;
64 break;
65 }
66 }
67 mutex_unlock(&clock_list_lock);
68 return ret;
69}
70
71static int tegra_clk_init_one_from_table(struct tegra_clk_init_table *table)
72{
73 struct clk *c;
74 struct clk *p;
75 struct clk *parent;
76
77 int ret = 0;
78
79 c = tegra_get_clock_by_name(table->name);
80
81 if (!c) {
82 pr_warn("Unable to initialize clock %s\n",
83 table->name);
84 return -ENODEV;
85 }
86
87 parent = clk_get_parent(c);
88
89 if (table->parent) {
90 p = tegra_get_clock_by_name(table->parent);
91 if (!p) {
92 pr_warn("Unable to find parent %s of clock %s\n",
93 table->parent, table->name);
94 return -ENODEV;
95 }
96
97 if (parent != p) {
98 ret = clk_set_parent(c, p);
99 if (ret) {
100 pr_warn("Unable to set parent %s of clock %s: %d\n",
101 table->parent, table->name, ret);
102 return -EINVAL;
103 }
104 }
105 }
106
107 if (table->rate && table->rate != clk_get_rate(c)) {
108 ret = clk_set_rate(c, table->rate);
109 if (ret) {
110 pr_warn("Unable to set clock %s to rate %lu: %d\n",
111 table->name, table->rate, ret);
112 return -EINVAL;
113 }
114 }
115
116 if (table->enabled) {
117 ret = clk_prepare_enable(c);
118 if (ret) {
119 pr_warn("Unable to enable clock %s: %d\n",
120 table->name, ret);
121 return -EINVAL;
122 }
123 }
124
125 return 0;
126}
127
128void tegra_clk_init_from_table(struct tegra_clk_init_table *table)
129{
130 for (; table->name; table++)
131 tegra_clk_init_one_from_table(table);
132}
133
134void tegra_periph_reset_deassert(struct clk *c)
135{
136 struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
137 BUG_ON(!clk->reset);
138 clk->reset(__clk_get_hw(c), false);
139}
140EXPORT_SYMBOL(tegra_periph_reset_deassert);
141
142void tegra_periph_reset_assert(struct clk *c)
143{
144 struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
145 BUG_ON(!clk->reset);
146 clk->reset(__clk_get_hw(c), true);
147}
148EXPORT_SYMBOL(tegra_periph_reset_assert);
149
150/* Several extended clock configuration bits (e.g., clock routing, clock
151 * phase control) are included in PLL and peripheral clock source
152 * registers. */
153int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
154{
155 int ret = 0;
156 struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
157
158 if (!clk->clk_cfg_ex) {
159 ret = -ENOSYS;
160 goto out;
161 }
162 ret = clk->clk_cfg_ex(__clk_get_hw(c), p, setting);
163
164out:
165 return ret;
166}
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h
deleted file mode 100644
index 2aa37f5c44c0..000000000000
--- a/arch/arm/mach-tegra/clock.h
+++ /dev/null
@@ -1,153 +0,0 @@
1/*
2 * arch/arm/mach-tegra/include/mach/clock.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved.
6 *
7 * Author:
8 * Colin Cross <ccross@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#ifndef __MACH_TEGRA_CLOCK_H
22#define __MACH_TEGRA_CLOCK_H
23
24#include <linux/clk-provider.h>
25#include <linux/clkdev.h>
26#include <linux/list.h>
27
28#include <mach/clk.h>
29
30#define DIV_BUS (1 << 0)
31#define DIV_U71 (1 << 1)
32#define DIV_U71_FIXED (1 << 2)
33#define DIV_2 (1 << 3)
34#define DIV_U16 (1 << 4)
35#define PLL_FIXED (1 << 5)
36#define PLL_HAS_CPCON (1 << 6)
37#define MUX (1 << 7)
38#define PLLD (1 << 8)
39#define PERIPH_NO_RESET (1 << 9)
40#define PERIPH_NO_ENB (1 << 10)
41#define PERIPH_EMC_ENB (1 << 11)
42#define PERIPH_MANUAL_RESET (1 << 12)
43#define PLL_ALT_MISC_REG (1 << 13)
44#define PLLU (1 << 14)
45#define PLLX (1 << 15)
46#define MUX_PWM (1 << 16)
47#define MUX8 (1 << 17)
48#define DIV_U71_UART (1 << 18)
49#define MUX_CLK_OUT (1 << 19)
50#define PLLM (1 << 20)
51#define DIV_U71_INT (1 << 21)
52#define DIV_U71_IDLE (1 << 22)
53#define ENABLE_ON_INIT (1 << 28)
54#define PERIPH_ON_APB (1 << 29)
55
56struct clk_tegra;
57#define to_clk_tegra(_hw) container_of(_hw, struct clk_tegra, hw)
58
59struct clk_mux_sel {
60 struct clk *input;
61 u32 value;
62};
63
64struct clk_pll_freq_table {
65 unsigned long input_rate;
66 unsigned long output_rate;
67 u16 n;
68 u16 m;
69 u8 p;
70 u8 cpcon;
71};
72
73enum clk_state {
74 UNINITIALIZED = 0,
75 ON,
76 OFF,
77};
78
79struct clk_tegra {
80 /* node for master clocks list */
81 struct list_head node; /* node for list of all clocks */
82 struct clk_lookup lookup;
83 struct clk_hw hw;
84
85 bool set;
86 unsigned long fixed_rate;
87 unsigned long max_rate;
88 unsigned long min_rate;
89 u32 flags;
90 const char *name;
91
92 enum clk_state state;
93 u32 div;
94 u32 mul;
95
96 u32 reg;
97 u32 reg_shift;
98
99 struct list_head shared_bus_list;
100
101 union {
102 struct {
103 unsigned int clk_num;
104 } periph;
105 struct {
106 unsigned long input_min;
107 unsigned long input_max;
108 unsigned long cf_min;
109 unsigned long cf_max;
110 unsigned long vco_min;
111 unsigned long vco_max;
112 const struct clk_pll_freq_table *freq_table;
113 int lock_delay;
114 unsigned long fixed_rate;
115 } pll;
116 struct {
117 u32 sel;
118 u32 reg_mask;
119 } mux;
120 struct {
121 struct clk *main;
122 struct clk *backup;
123 } cpu;
124 struct {
125 struct list_head node;
126 bool enabled;
127 unsigned long rate;
128 } shared_bus_user;
129 } u;
130
131 void (*reset)(struct clk_hw *, bool);
132 int (*clk_cfg_ex)(struct clk_hw *, enum tegra_clk_ex_param, u32);
133};
134
135struct clk_duplicate {
136 const char *name;
137 struct clk_lookup lookup;
138};
139
140struct tegra_clk_init_table {
141 const char *name;
142 const char *parent;
143 unsigned long rate;
144 bool enabled;
145};
146
147void tegra_clk_add(struct clk *c);
148void tegra2_init_clocks(void);
149void tegra30_init_clocks(void);
150struct clk *tegra_get_clock_by_name(const char *name);
151void tegra_clk_init_from_table(struct tegra_clk_init_table *table);
152
153#endif
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 3599959517b3..46c071861c4e 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -22,13 +22,13 @@
22#include <linux/clk.h> 22#include <linux/clk.h>
23#include <linux/delay.h> 23#include <linux/delay.h>
24#include <linux/irqchip.h> 24#include <linux/irqchip.h>
25#include <linux/clk/tegra.h>
25 26
26#include <asm/hardware/cache-l2x0.h> 27#include <asm/hardware/cache-l2x0.h>
27 28
28#include <mach/powergate.h> 29#include <mach/powergate.h>
29 30
30#include "board.h" 31#include "board.h"
31#include "clock.h"
32#include "common.h" 32#include "common.h"
33#include "fuse.h" 33#include "fuse.h"
34#include "iomap.h" 34#include "iomap.h"
@@ -36,6 +36,7 @@
36#include "apbio.h" 36#include "apbio.h"
37#include "sleep.h" 37#include "sleep.h"
38#include "pm.h" 38#include "pm.h"
39#include "reset.h"
39 40
40/* 41/*
41 * Storage for debug-macro.S's state. 42 * Storage for debug-macro.S's state.
@@ -58,6 +59,7 @@ u32 tegra_uart_config[4] = {
58#ifdef CONFIG_OF 59#ifdef CONFIG_OF
59void __init tegra_dt_init_irq(void) 60void __init tegra_dt_init_irq(void)
60{ 61{
62 tegra_clocks_init();
61 tegra_init_irq(); 63 tegra_init_irq();
62 irqchip_init(); 64 irqchip_init();
63} 65}
@@ -73,43 +75,6 @@ void tegra_assert_system_reset(char mode, const char *cmd)
73 writel_relaxed(reg, reset); 75 writel_relaxed(reg, reset);
74} 76}
75 77
76#ifdef CONFIG_ARCH_TEGRA_2x_SOC
77static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
78 /* name parent rate enabled */
79 { "clk_m", NULL, 0, true },
80 { "pll_p", "clk_m", 216000000, true },
81 { "pll_p_out1", "pll_p", 28800000, true },
82 { "pll_p_out2", "pll_p", 48000000, true },
83 { "pll_p_out3", "pll_p", 72000000, true },
84 { "pll_p_out4", "pll_p", 24000000, true },
85 { "pll_c", "clk_m", 600000000, true },
86 { "pll_c_out1", "pll_c", 120000000, true },
87 { "sclk", "pll_c_out1", 120000000, true },
88 { "hclk", "sclk", 120000000, true },
89 { "pclk", "hclk", 60000000, true },
90 { "csite", NULL, 0, true },
91 { "emc", NULL, 0, true },
92 { "cpu", NULL, 0, true },
93 { NULL, NULL, 0, 0},
94};
95#endif
96
97#ifdef CONFIG_ARCH_TEGRA_3x_SOC
98static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = {
99 /* name parent rate enabled */
100 { "clk_m", NULL, 0, true },
101 { "pll_p", "pll_ref", 408000000, true },
102 { "pll_p_out1", "pll_p", 9600000, true },
103 { "pll_p_out4", "pll_p", 102000000, true },
104 { "sclk", "pll_p_out4", 102000000, true },
105 { "hclk", "sclk", 102000000, true },
106 { "pclk", "hclk", 51000000, true },
107 { "csite", NULL, 0, true },
108 { NULL, NULL, 0, 0},
109};
110#endif
111
112
113static void __init tegra_init_cache(void) 78static void __init tegra_init_cache(void)
114{ 79{
115#ifdef CONFIG_CACHE_L2X0 80#ifdef CONFIG_CACHE_L2X0
@@ -131,10 +96,9 @@ static void __init tegra_init_cache(void)
131#ifdef CONFIG_ARCH_TEGRA_2x_SOC 96#ifdef CONFIG_ARCH_TEGRA_2x_SOC
132void __init tegra20_init_early(void) 97void __init tegra20_init_early(void)
133{ 98{
99 tegra_cpu_reset_handler_init();
134 tegra_apb_io_init(); 100 tegra_apb_io_init();
135 tegra_init_fuse(); 101 tegra_init_fuse();
136 tegra2_init_clocks();
137 tegra_clk_init_from_table(tegra20_clk_init_table);
138 tegra_init_cache(); 102 tegra_init_cache();
139 tegra_pmc_init(); 103 tegra_pmc_init();
140 tegra_powergate_init(); 104 tegra_powergate_init();
@@ -144,10 +108,9 @@ void __init tegra20_init_early(void)
144#ifdef CONFIG_ARCH_TEGRA_3x_SOC 108#ifdef CONFIG_ARCH_TEGRA_3x_SOC
145void __init tegra30_init_early(void) 109void __init tegra30_init_early(void)
146{ 110{
111 tegra_cpu_reset_handler_init();
147 tegra_apb_io_init(); 112 tegra_apb_io_init();
148 tegra_init_fuse(); 113 tegra_init_fuse();
149 tegra30_init_clocks();
150 tegra_clk_init_from_table(tegra30_clk_init_table);
151 tegra_init_cache(); 114 tegra_init_cache();
152 tegra_pmc_init(); 115 tegra_pmc_init();
153 tegra_powergate_init(); 116 tegra_powergate_init();
diff --git a/arch/arm/mach-tegra/common.h b/arch/arm/mach-tegra/common.h
index 02f71b4f1e51..32f8eb3fe344 100644
--- a/arch/arm/mach-tegra/common.h
+++ b/arch/arm/mach-tegra/common.h
@@ -1,4 +1,5 @@
1extern struct smp_operations tegra_smp_ops; 1extern struct smp_operations tegra_smp_ops;
2 2
3extern int tegra_cpu_kill(unsigned int cpu);
3extern void tegra_cpu_die(unsigned int cpu); 4extern void tegra_cpu_die(unsigned int cpu);
4extern int tegra_cpu_disable(unsigned int cpu); 5extern int tegra_cpu_disable(unsigned int cpu);
diff --git a/arch/arm/mach-tegra/cpu-tegra.c b/arch/arm/mach-tegra/cpu-tegra.c
index a74d3c7d2e26..ebffed67e2f5 100644
--- a/arch/arm/mach-tegra/cpu-tegra.c
+++ b/arch/arm/mach-tegra/cpu-tegra.c
@@ -214,24 +214,6 @@ static int tegra_cpu_init(struct cpufreq_policy *policy)
214 if (policy->cpu >= NUM_CPUS) 214 if (policy->cpu >= NUM_CPUS)
215 return -EINVAL; 215 return -EINVAL;
216 216
217 cpu_clk = clk_get_sys(NULL, "cpu");
218 if (IS_ERR(cpu_clk))
219 return PTR_ERR(cpu_clk);
220
221 pll_x_clk = clk_get_sys(NULL, "pll_x");
222 if (IS_ERR(pll_x_clk))
223 return PTR_ERR(pll_x_clk);
224
225 pll_p_clk = clk_get_sys(NULL, "pll_p");
226 if (IS_ERR(pll_p_clk))
227 return PTR_ERR(pll_p_clk);
228
229 emc_clk = clk_get_sys("cpu", "emc");
230 if (IS_ERR(emc_clk)) {
231 clk_put(cpu_clk);
232 return PTR_ERR(emc_clk);
233 }
234
235 clk_prepare_enable(emc_clk); 217 clk_prepare_enable(emc_clk);
236 clk_prepare_enable(cpu_clk); 218 clk_prepare_enable(cpu_clk);
237 219
@@ -256,8 +238,6 @@ static int tegra_cpu_exit(struct cpufreq_policy *policy)
256{ 238{
257 cpufreq_frequency_table_cpuinfo(policy, freq_table); 239 cpufreq_frequency_table_cpuinfo(policy, freq_table);
258 clk_disable_unprepare(emc_clk); 240 clk_disable_unprepare(emc_clk);
259 clk_put(emc_clk);
260 clk_put(cpu_clk);
261 return 0; 241 return 0;
262} 242}
263 243
@@ -278,12 +258,32 @@ static struct cpufreq_driver tegra_cpufreq_driver = {
278 258
279static int __init tegra_cpufreq_init(void) 259static int __init tegra_cpufreq_init(void)
280{ 260{
261 cpu_clk = clk_get_sys(NULL, "cpu");
262 if (IS_ERR(cpu_clk))
263 return PTR_ERR(cpu_clk);
264
265 pll_x_clk = clk_get_sys(NULL, "pll_x");
266 if (IS_ERR(pll_x_clk))
267 return PTR_ERR(pll_x_clk);
268
269 pll_p_clk = clk_get_sys(NULL, "pll_p_cclk");
270 if (IS_ERR(pll_p_clk))
271 return PTR_ERR(pll_p_clk);
272
273 emc_clk = clk_get_sys("cpu", "emc");
274 if (IS_ERR(emc_clk)) {
275 clk_put(cpu_clk);
276 return PTR_ERR(emc_clk);
277 }
278
281 return cpufreq_register_driver(&tegra_cpufreq_driver); 279 return cpufreq_register_driver(&tegra_cpufreq_driver);
282} 280}
283 281
284static void __exit tegra_cpufreq_exit(void) 282static void __exit tegra_cpufreq_exit(void)
285{ 283{
286 cpufreq_unregister_driver(&tegra_cpufreq_driver); 284 cpufreq_unregister_driver(&tegra_cpufreq_driver);
285 clk_put(emc_clk);
286 clk_put(cpu_clk);
287} 287}
288 288
289 289
diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c
index 5e8cbf5b799f..8b50cf4ddd6f 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra30.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra30.c
@@ -24,6 +24,7 @@
24#include <linux/cpuidle.h> 24#include <linux/cpuidle.h>
25#include <linux/cpu_pm.h> 25#include <linux/cpu_pm.h>
26#include <linux/clockchips.h> 26#include <linux/clockchips.h>
27#include <linux/clk/tegra.h>
27 28
28#include <asm/cpuidle.h> 29#include <asm/cpuidle.h>
29#include <asm/proc-fns.h> 30#include <asm/proc-fns.h>
@@ -32,7 +33,6 @@
32 33
33#include "pm.h" 34#include "pm.h"
34#include "sleep.h" 35#include "sleep.h"
35#include "tegra_cpu_car.h"
36 36
37#ifdef CONFIG_PM_SLEEP 37#ifdef CONFIG_PM_SLEEP
38static int tegra30_idle_lp2(struct cpuidle_device *dev, 38static int tegra30_idle_lp2(struct cpuidle_device *dev,
@@ -121,9 +121,9 @@ static inline bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
121} 121}
122#endif 122#endif
123 123
124static int __cpuinit tegra30_idle_lp2(struct cpuidle_device *dev, 124static int tegra30_idle_lp2(struct cpuidle_device *dev,
125 struct cpuidle_driver *drv, 125 struct cpuidle_driver *drv,
126 int index) 126 int index)
127{ 127{
128 u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu; 128 u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
129 bool entered_lp2 = false; 129 bool entered_lp2 = false;
diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c
index a2250ddae797..5393eb2cae21 100644
--- a/arch/arm/mach-tegra/flowctrl.c
+++ b/arch/arm/mach-tegra/flowctrl.c
@@ -26,14 +26,14 @@
26#include "flowctrl.h" 26#include "flowctrl.h"
27#include "iomap.h" 27#include "iomap.h"
28 28
29u8 flowctrl_offset_halt_cpu[] = { 29static u8 flowctrl_offset_halt_cpu[] = {
30 FLOW_CTRL_HALT_CPU0_EVENTS, 30 FLOW_CTRL_HALT_CPU0_EVENTS,
31 FLOW_CTRL_HALT_CPU1_EVENTS, 31 FLOW_CTRL_HALT_CPU1_EVENTS,
32 FLOW_CTRL_HALT_CPU1_EVENTS + 8, 32 FLOW_CTRL_HALT_CPU1_EVENTS + 8,
33 FLOW_CTRL_HALT_CPU1_EVENTS + 16, 33 FLOW_CTRL_HALT_CPU1_EVENTS + 16,
34}; 34};
35 35
36u8 flowctrl_offset_cpu_csr[] = { 36static u8 flowctrl_offset_cpu_csr[] = {
37 FLOW_CTRL_CPU0_CSR, 37 FLOW_CTRL_CPU0_CSR,
38 FLOW_CTRL_CPU1_CSR, 38 FLOW_CTRL_CPU1_CSR,
39 FLOW_CTRL_CPU1_CSR + 8, 39 FLOW_CTRL_CPU1_CSR + 8,
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index 8121742711fe..f7db0782a6b6 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -20,6 +20,7 @@
20#include <linux/kernel.h> 20#include <linux/kernel.h>
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/export.h> 22#include <linux/export.h>
23#include <linux/tegra-soc.h>
23 24
24#include "fuse.h" 25#include "fuse.h"
25#include "iomap.h" 26#include "iomap.h"
@@ -105,6 +106,11 @@ static void tegra_get_process_id(void)
105 tegra_core_process_id = (reg >> 12) & 3; 106 tegra_core_process_id = (reg >> 12) & 3;
106} 107}
107 108
109u32 tegra_read_chipid(void)
110{
111 return readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
112}
113
108void tegra_init_fuse(void) 114void tegra_init_fuse(void)
109{ 115{
110 u32 id; 116 u32 id;
@@ -119,7 +125,7 @@ void tegra_init_fuse(void)
119 reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT); 125 reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
120 tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT; 126 tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
121 127
122 id = readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804); 128 id = tegra_read_chipid();
123 tegra_chip_id = (id >> 8) & 0xff; 129 tegra_chip_id = (id >> 8) & 0xff;
124 130
125 switch (tegra_chip_id) { 131 switch (tegra_chip_id) {
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index 4a317fae6860..b2834810b02b 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -1,22 +1,9 @@
1#include <linux/linkage.h> 1#include <linux/linkage.h>
2#include <linux/init.h> 2#include <linux/init.h>
3 3
4#include <asm/cache.h>
5#include <asm/asm-offsets.h>
6#include <asm/hardware/cache-l2x0.h>
7
8#include "flowctrl.h"
9#include "iomap.h"
10#include "reset.h"
11#include "sleep.h" 4#include "sleep.h"
12 5
13#define APB_MISC_GP_HIDREV 0x804
14#define PMC_SCRATCH41 0x140
15
16#define RESET_DATA(x) ((TEGRA_RESET_##x)*4)
17
18 .section ".text.head", "ax" 6 .section ".text.head", "ax"
19 __CPUINIT
20 7
21/* 8/*
22 * Tegra specific entry point for secondary CPUs. 9 * Tegra specific entry point for secondary CPUs.
@@ -61,7 +48,6 @@ ENTRY(v7_invalidate_l1)
61 mov pc, lr 48 mov pc, lr
62ENDPROC(v7_invalidate_l1) 49ENDPROC(v7_invalidate_l1)
63 50
64
65ENTRY(tegra_secondary_startup) 51ENTRY(tegra_secondary_startup)
66 bl v7_invalidate_l1 52 bl v7_invalidate_l1
67 /* Enable coresight */ 53 /* Enable coresight */
@@ -69,210 +55,3 @@ ENTRY(tegra_secondary_startup)
69 mcr p14, 0, r0, c7, c12, 6 55 mcr p14, 0, r0, c7, c12, 6
70 b secondary_startup 56 b secondary_startup
71ENDPROC(tegra_secondary_startup) 57ENDPROC(tegra_secondary_startup)
72
73#ifdef CONFIG_PM_SLEEP
74/*
75 * tegra_resume
76 *
77 * CPU boot vector when restarting the a CPU following
78 * an LP2 transition. Also branched to by LP0 and LP1 resume after
79 * re-enabling sdram.
80 */
81ENTRY(tegra_resume)
82 bl v7_invalidate_l1
83 /* Enable coresight */
84 mov32 r0, 0xC5ACCE55
85 mcr p14, 0, r0, c7, c12, 6
86
87 cpu_id r0
88 cmp r0, #0 @ CPU0?
89 bne cpu_resume @ no
90
91#ifdef CONFIG_ARCH_TEGRA_3x_SOC
92 /* Are we on Tegra20? */
93 mov32 r6, TEGRA_APB_MISC_BASE
94 ldr r0, [r6, #APB_MISC_GP_HIDREV]
95 and r0, r0, #0xff00
96 cmp r0, #(0x20 << 8)
97 beq 1f @ Yes
98 /* Clear the flow controller flags for this CPU. */
99 mov32 r2, TEGRA_FLOW_CTRL_BASE + FLOW_CTRL_CPU0_CSR @ CPU0 CSR
100 ldr r1, [r2]
101 /* Clear event & intr flag */
102 orr r1, r1, \
103 #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
104 movw r0, #0x0FFD @ enable, cluster_switch, immed, & bitmaps
105 bic r1, r1, r0
106 str r1, [r2]
1071:
108#endif
109
110#ifdef CONFIG_HAVE_ARM_SCU
111 /* enable SCU */
112 mov32 r0, TEGRA_ARM_PERIF_BASE
113 ldr r1, [r0]
114 orr r1, r1, #1
115 str r1, [r0]
116#endif
117
118 /* L2 cache resume & re-enable */
119 l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr
120
121 b cpu_resume
122ENDPROC(tegra_resume)
123#endif
124
125#ifdef CONFIG_CACHE_L2X0
126 .globl l2x0_saved_regs_addr
127l2x0_saved_regs_addr:
128 .long 0
129#endif
130
131 .align L1_CACHE_SHIFT
132ENTRY(__tegra_cpu_reset_handler_start)
133
134/*
135 * __tegra_cpu_reset_handler:
136 *
137 * Common handler for all CPU reset events.
138 *
139 * Register usage within the reset handler:
140 *
141 * R7 = CPU present (to the OS) mask
142 * R8 = CPU in LP1 state mask
143 * R9 = CPU in LP2 state mask
144 * R10 = CPU number
145 * R11 = CPU mask
146 * R12 = pointer to reset handler data
147 *
148 * NOTE: This code is copied to IRAM. All code and data accesses
149 * must be position-independent.
150 */
151
152 .align L1_CACHE_SHIFT
153ENTRY(__tegra_cpu_reset_handler)
154
155 cpsid aif, 0x13 @ SVC mode, interrupts disabled
156 mrc p15, 0, r10, c0, c0, 5 @ MPIDR
157 and r10, r10, #0x3 @ R10 = CPU number
158 mov r11, #1
159 mov r11, r11, lsl r10 @ R11 = CPU mask
160 adr r12, __tegra_cpu_reset_handler_data
161
162#ifdef CONFIG_SMP
163 /* Does the OS know about this CPU? */
164 ldr r7, [r12, #RESET_DATA(MASK_PRESENT)]
165 tst r7, r11 @ if !present
166 bleq __die @ CPU not present (to OS)
167#endif
168
169#ifdef CONFIG_ARCH_TEGRA_2x_SOC
170 /* Are we on Tegra20? */
171 mov32 r6, TEGRA_APB_MISC_BASE
172 ldr r0, [r6, #APB_MISC_GP_HIDREV]
173 and r0, r0, #0xff00
174 cmp r0, #(0x20 << 8)
175 bne 1f
176 /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
177 mov32 r6, TEGRA_PMC_BASE
178 mov r0, #0
179 cmp r10, #0
180 strne r0, [r6, #PMC_SCRATCH41]
1811:
182#endif
183
184 /* Waking up from LP2? */
185 ldr r9, [r12, #RESET_DATA(MASK_LP2)]
186 tst r9, r11 @ if in_lp2
187 beq __is_not_lp2
188 ldr lr, [r12, #RESET_DATA(STARTUP_LP2)]
189 cmp lr, #0
190 bleq __die @ no LP2 startup handler
191 bx lr
192
193__is_not_lp2:
194
195#ifdef CONFIG_SMP
196 /*
197 * Can only be secondary boot (initial or hotplug) but CPU 0
198 * cannot be here.
199 */
200 cmp r10, #0
201 bleq __die @ CPU0 cannot be here
202 ldr lr, [r12, #RESET_DATA(STARTUP_SECONDARY)]
203 cmp lr, #0
204 bleq __die @ no secondary startup handler
205 bx lr
206#endif
207
208/*
209 * We don't know why the CPU reset. Just kill it.
210 * The LR register will contain the address we died at + 4.
211 */
212
213__die:
214 sub lr, lr, #4
215 mov32 r7, TEGRA_PMC_BASE
216 str lr, [r7, #PMC_SCRATCH41]
217
218 mov32 r7, TEGRA_CLK_RESET_BASE
219
220 /* Are we on Tegra20? */
221 mov32 r6, TEGRA_APB_MISC_BASE
222 ldr r0, [r6, #APB_MISC_GP_HIDREV]
223 and r0, r0, #0xff00
224 cmp r0, #(0x20 << 8)
225 bne 1f
226
227#ifdef CONFIG_ARCH_TEGRA_2x_SOC
228 mov32 r0, 0x1111
229 mov r1, r0, lsl r10
230 str r1, [r7, #0x340] @ CLK_RST_CPU_CMPLX_SET
231#endif
2321:
233#ifdef CONFIG_ARCH_TEGRA_3x_SOC
234 mov32 r6, TEGRA_FLOW_CTRL_BASE
235
236 cmp r10, #0
237 moveq r1, #FLOW_CTRL_HALT_CPU0_EVENTS
238 moveq r2, #FLOW_CTRL_CPU0_CSR
239 movne r1, r10, lsl #3
240 addne r2, r1, #(FLOW_CTRL_CPU1_CSR-8)
241 addne r1, r1, #(FLOW_CTRL_HALT_CPU1_EVENTS-8)
242
243 /* Clear CPU "event" and "interrupt" flags and power gate
244 it when halting but not before it is in the "WFI" state. */
245 ldr r0, [r6, +r2]
246 orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
247 orr r0, r0, #FLOW_CTRL_CSR_ENABLE
248 str r0, [r6, +r2]
249
250 /* Unconditionally halt this CPU */
251 mov r0, #FLOW_CTRL_WAITEVENT
252 str r0, [r6, +r1]
253 ldr r0, [r6, +r1] @ memory barrier
254
255 dsb
256 isb
257 wfi @ CPU should be power gated here
258
259 /* If the CPU didn't power gate above just kill it's clock. */
260
261 mov r0, r11, lsl #8
262 str r0, [r7, #348] @ CLK_CPU_CMPLX_SET
263#endif
264
265 /* If the CPU still isn't dead, just spin here. */
266 b .
267ENDPROC(__tegra_cpu_reset_handler)
268
269 .align L1_CACHE_SHIFT
270 .type __tegra_cpu_reset_handler_data, %object
271 .globl __tegra_cpu_reset_handler_data
272__tegra_cpu_reset_handler_data:
273 .rept TEGRA_RESET_DATA_SIZE
274 .long 0
275 .endr
276 .align L1_CACHE_SHIFT
277
278ENTRY(__tegra_cpu_reset_handler_end)
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index dca5141a2c31..a599f6e36dea 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -10,15 +10,26 @@
10 */ 10 */
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/smp.h> 12#include <linux/smp.h>
13#include <linux/clk/tegra.h>
13 14
14#include <asm/cacheflush.h> 15#include <asm/cacheflush.h>
15#include <asm/smp_plat.h> 16#include <asm/smp_plat.h>
16 17
17#include "sleep.h" 18#include "sleep.h"
18#include "tegra_cpu_car.h"
19 19
20static void (*tegra_hotplug_shutdown)(void); 20static void (*tegra_hotplug_shutdown)(void);
21 21
22int tegra_cpu_kill(unsigned cpu)
23{
24 cpu = cpu_logical_map(cpu);
25
26 /* Clock gate the CPU */
27 tegra_wait_cpu_in_reset(cpu);
28 tegra_disable_cpu_clock(cpu);
29
30 return 1;
31}
32
22/* 33/*
23 * platform-specific code to shutdown a CPU 34 * platform-specific code to shutdown a CPU
24 * 35 *
@@ -26,18 +37,12 @@ static void (*tegra_hotplug_shutdown)(void);
26 */ 37 */
27void __ref tegra_cpu_die(unsigned int cpu) 38void __ref tegra_cpu_die(unsigned int cpu)
28{ 39{
29 cpu = cpu_logical_map(cpu); 40 /* Clean L1 data cache */
30 41 tegra_disable_clean_inv_dcache();
31 /* Flush the L1 data cache. */
32 flush_cache_all();
33 42
34 /* Shut down the current CPU. */ 43 /* Shut down the current CPU. */
35 tegra_hotplug_shutdown(); 44 tegra_hotplug_shutdown();
36 45
37 /* Clock gate the CPU */
38 tegra_wait_cpu_in_reset(cpu);
39 tegra_disable_cpu_clock(cpu);
40
41 /* Should never return here. */ 46 /* Should never return here. */
42 BUG(); 47 BUG();
43} 48}
diff --git a/arch/arm/mach-tegra/include/mach/clk.h b/arch/arm/mach-tegra/include/mach/clk.h
deleted file mode 100644
index 95f3a547c770..000000000000
--- a/arch/arm/mach-tegra/include/mach/clk.h
+++ /dev/null
@@ -1,44 +0,0 @@
1/*
2 * arch/arm/mach-tegra/include/mach/clk.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Erik Gilling <konkers@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#ifndef __MACH_CLK_H
21#define __MACH_CLK_H
22
23struct clk;
24
25enum tegra_clk_ex_param {
26 TEGRA_CLK_VI_INP_SEL,
27 TEGRA_CLK_DTV_INVERT,
28 TEGRA_CLK_NAND_PAD_DIV2_ENB,
29 TEGRA_CLK_PLLD_CSI_OUT_ENB,
30 TEGRA_CLK_PLLD_DSI_OUT_ENB,
31 TEGRA_CLK_PLLD_MIPI_MUX_SEL,
32};
33
34void tegra_periph_reset_deassert(struct clk *c);
35void tegra_periph_reset_assert(struct clk *c);
36
37#ifndef CONFIG_COMMON_CLK
38unsigned long clk_get_rate_all_locked(struct clk *c);
39#endif
40
41void tegra2_sdmmc_tap_delay(struct clk *c, int delay);
42int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting);
43
44#endif
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index bffcd643d7a3..b60165f1ca02 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -33,11 +33,11 @@
33#include <linux/clk.h> 33#include <linux/clk.h>
34#include <linux/delay.h> 34#include <linux/delay.h>
35#include <linux/export.h> 35#include <linux/export.h>
36#include <linux/clk/tegra.h>
36 37
37#include <asm/sizes.h> 38#include <asm/sizes.h>
38#include <asm/mach/pci.h> 39#include <asm/mach/pci.h>
39 40
40#include <mach/clk.h>
41#include <mach/powergate.h> 41#include <mach/powergate.h>
42 42
43#include "board.h" 43#include "board.h"
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 18d7290cf93b..c72e249e33b0 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -19,23 +19,25 @@
19#include <linux/smp.h> 19#include <linux/smp.h>
20#include <linux/io.h> 20#include <linux/io.h>
21#include <linux/irqchip/arm-gic.h> 21#include <linux/irqchip/arm-gic.h>
22#include <linux/clk/tegra.h>
22 23
23#include <asm/cacheflush.h> 24#include <asm/cacheflush.h>
24#include <asm/mach-types.h> 25#include <asm/mach-types.h>
25#include <asm/smp_scu.h> 26#include <asm/smp_scu.h>
27#include <asm/smp_plat.h>
26 28
27#include <mach/powergate.h> 29#include <mach/powergate.h>
28 30
29#include "fuse.h" 31#include "fuse.h"
30#include "flowctrl.h" 32#include "flowctrl.h"
31#include "reset.h" 33#include "reset.h"
32#include "tegra_cpu_car.h"
33 34
34#include "common.h" 35#include "common.h"
35#include "iomap.h" 36#include "iomap.h"
36 37
37extern void tegra_secondary_startup(void); 38extern void tegra_secondary_startup(void);
38 39
40static cpumask_t tegra_cpu_init_mask;
39static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE); 41static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
40 42
41#define EVP_CPU_RESET_VECTOR \ 43#define EVP_CPU_RESET_VECTOR \
@@ -50,6 +52,7 @@ static void __cpuinit tegra_secondary_init(unsigned int cpu)
50 */ 52 */
51 gic_secondary_init(0); 53 gic_secondary_init(0);
52 54
55 cpumask_set_cpu(cpu, &tegra_cpu_init_mask);
53} 56}
54 57
55static int tegra20_power_up_cpu(unsigned int cpu) 58static int tegra20_power_up_cpu(unsigned int cpu)
@@ -72,14 +75,42 @@ static int tegra30_power_up_cpu(unsigned int cpu)
72 if (pwrgateid < 0) 75 if (pwrgateid < 0)
73 return pwrgateid; 76 return pwrgateid;
74 77
75 /* If this is the first boot, toggle powergates directly. */ 78 /*
79 * The power up sequence of cold boot CPU and warm boot CPU
80 * was different.
81 *
82 * For warm boot CPU that was resumed from CPU hotplug, the
83 * power will be resumed automatically after un-halting the
84 * flow controller of the warm boot CPU. We need to wait for
85 * the confirmaiton that the CPU is powered then removing
86 * the IO clamps.
87 * For cold boot CPU, do not wait. After the cold boot CPU be
88 * booted, it will run to tegra_secondary_init() and set
89 * tegra_cpu_init_mask which influences what tegra30_power_up_cpu()
90 * next time around.
91 */
92 if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) {
93 timeout = jiffies + msecs_to_jiffies(50);
94 do {
95 if (!tegra_powergate_is_powered(pwrgateid))
96 goto remove_clamps;
97 udelay(10);
98 } while (time_before(jiffies, timeout));
99 }
100
101 /*
102 * The power status of the cold boot CPU is power gated as
103 * default. To power up the cold boot CPU, the power should
104 * be un-gated by un-toggling the power gate register
105 * manually.
106 */
76 if (!tegra_powergate_is_powered(pwrgateid)) { 107 if (!tegra_powergate_is_powered(pwrgateid)) {
77 ret = tegra_powergate_power_on(pwrgateid); 108 ret = tegra_powergate_power_on(pwrgateid);
78 if (ret) 109 if (ret)
79 return ret; 110 return ret;
80 111
81 /* Wait for the power to come up. */ 112 /* Wait for the power to come up. */
82 timeout = jiffies + 10*HZ; 113 timeout = jiffies + msecs_to_jiffies(100);
83 while (tegra_powergate_is_powered(pwrgateid)) { 114 while (tegra_powergate_is_powered(pwrgateid)) {
84 if (time_after(jiffies, timeout)) 115 if (time_after(jiffies, timeout))
85 return -ETIMEDOUT; 116 return -ETIMEDOUT;
@@ -87,6 +118,7 @@ static int tegra30_power_up_cpu(unsigned int cpu)
87 } 118 }
88 } 119 }
89 120
121remove_clamps:
90 /* CPU partition is powered. Enable the CPU clock. */ 122 /* CPU partition is powered. Enable the CPU clock. */
91 tegra_enable_cpu_clock(cpu); 123 tegra_enable_cpu_clock(cpu);
92 udelay(10); 124 udelay(10);
@@ -105,6 +137,8 @@ static int __cpuinit tegra_boot_secondary(unsigned int cpu, struct task_struct *
105{ 137{
106 int status; 138 int status;
107 139
140 cpu = cpu_logical_map(cpu);
141
108 /* 142 /*
109 * Force the CPU into reset. The CPU must remain in reset when the 143 * Force the CPU into reset. The CPU must remain in reset when the
110 * flow controller state is cleared (which will cause the flow 144 * flow controller state is cleared (which will cause the flow
@@ -163,7 +197,9 @@ static void __init tegra_smp_init_cpus(void)
163 197
164static void __init tegra_smp_prepare_cpus(unsigned int max_cpus) 198static void __init tegra_smp_prepare_cpus(unsigned int max_cpus)
165{ 199{
166 tegra_cpu_reset_handler_init(); 200 /* Always mark the boot CPU (CPU0) as initialized. */
201 cpumask_set_cpu(0, &tegra_cpu_init_mask);
202
167 scu_enable(scu_base); 203 scu_enable(scu_base);
168} 204}
169 205
@@ -173,6 +209,7 @@ struct smp_operations tegra_smp_ops __initdata = {
173 .smp_secondary_init = tegra_secondary_init, 209 .smp_secondary_init = tegra_secondary_init,
174 .smp_boot_secondary = tegra_boot_secondary, 210 .smp_boot_secondary = tegra_boot_secondary,
175#ifdef CONFIG_HOTPLUG_CPU 211#ifdef CONFIG_HOTPLUG_CPU
212 .cpu_kill = tegra_cpu_kill,
176 .cpu_die = tegra_cpu_die, 213 .cpu_die = tegra_cpu_die,
177 .cpu_disable = tegra_cpu_disable, 214 .cpu_disable = tegra_cpu_disable,
178#endif 215#endif
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 1b11707eaca0..abfe9b93cc0c 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -24,6 +24,7 @@
24#include <linux/cpu_pm.h> 24#include <linux/cpu_pm.h>
25#include <linux/clk.h> 25#include <linux/clk.h>
26#include <linux/err.h> 26#include <linux/err.h>
27#include <linux/clk/tegra.h>
27 28
28#include <asm/smp_plat.h> 29#include <asm/smp_plat.h>
29#include <asm/cacheflush.h> 30#include <asm/cacheflush.h>
@@ -36,7 +37,6 @@
36#include "reset.h" 37#include "reset.h"
37#include "flowctrl.h" 38#include "flowctrl.h"
38#include "sleep.h" 39#include "sleep.h"
39#include "tegra_cpu_car.h"
40 40
41#define TEGRA_POWER_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */ 41#define TEGRA_POWER_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */
42 42
@@ -148,7 +148,7 @@ static void suspend_cpu_complex(void)
148 save_cpu_arch_register(); 148 save_cpu_arch_register();
149} 149}
150 150
151void __cpuinit tegra_clear_cpu_in_lp2(int phy_cpu_id) 151void tegra_clear_cpu_in_lp2(int phy_cpu_id)
152{ 152{
153 u32 *cpu_in_lp2 = tegra_cpu_lp2_mask; 153 u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
154 154
@@ -160,7 +160,7 @@ void __cpuinit tegra_clear_cpu_in_lp2(int phy_cpu_id)
160 spin_unlock(&tegra_lp2_lock); 160 spin_unlock(&tegra_lp2_lock);
161} 161}
162 162
163bool __cpuinit tegra_set_cpu_in_lp2(int phy_cpu_id) 163bool tegra_set_cpu_in_lp2(int phy_cpu_id)
164{ 164{
165 bool last_cpu = false; 165 bool last_cpu = false;
166 cpumask_t *cpu_lp2_mask = tegra_cpu_lp2_mask; 166 cpumask_t *cpu_lp2_mask = tegra_cpu_lp2_mask;
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index 2cc1185d902e..c6bc8f85759c 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -26,8 +26,8 @@
26#include <linux/io.h> 26#include <linux/io.h>
27#include <linux/seq_file.h> 27#include <linux/seq_file.h>
28#include <linux/spinlock.h> 28#include <linux/spinlock.h>
29#include <linux/clk/tegra.h>
29 30
30#include <mach/clk.h>
31#include <mach/powergate.h> 31#include <mach/powergate.h>
32 32
33#include "fuse.h" 33#include "fuse.h"
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
new file mode 100644
index 000000000000..54382ceade4a
--- /dev/null
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -0,0 +1,239 @@
1/*
2 * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/linkage.h>
18#include <linux/init.h>
19
20#include <asm/cache.h>
21#include <asm/asm-offsets.h>
22#include <asm/hardware/cache-l2x0.h>
23
24#include "flowctrl.h"
25#include "iomap.h"
26#include "reset.h"
27#include "sleep.h"
28
29#define APB_MISC_GP_HIDREV 0x804
30#define PMC_SCRATCH41 0x140
31
32#define RESET_DATA(x) ((TEGRA_RESET_##x)*4)
33
34#ifdef CONFIG_PM_SLEEP
35/*
36 * tegra_resume
37 *
38 * CPU boot vector when restarting the a CPU following
39 * an LP2 transition. Also branched to by LP0 and LP1 resume after
40 * re-enabling sdram.
41 */
42ENTRY(tegra_resume)
43 bl v7_invalidate_l1
44 /* Enable coresight */
45 mov32 r0, 0xC5ACCE55
46 mcr p14, 0, r0, c7, c12, 6
47
48 cpu_id r0
49 cmp r0, #0 @ CPU0?
50 bne cpu_resume @ no
51
52#ifdef CONFIG_ARCH_TEGRA_3x_SOC
53 /* Are we on Tegra20? */
54 mov32 r6, TEGRA_APB_MISC_BASE
55 ldr r0, [r6, #APB_MISC_GP_HIDREV]
56 and r0, r0, #0xff00
57 cmp r0, #(0x20 << 8)
58 beq 1f @ Yes
59 /* Clear the flow controller flags for this CPU. */
60 mov32 r2, TEGRA_FLOW_CTRL_BASE + FLOW_CTRL_CPU0_CSR @ CPU0 CSR
61 ldr r1, [r2]
62 /* Clear event & intr flag */
63 orr r1, r1, \
64 #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
65 movw r0, #0x0FFD @ enable, cluster_switch, immed, & bitmaps
66 bic r1, r1, r0
67 str r1, [r2]
681:
69#endif
70
71#ifdef CONFIG_HAVE_ARM_SCU
72 /* enable SCU */
73 mov32 r0, TEGRA_ARM_PERIF_BASE
74 ldr r1, [r0]
75 orr r1, r1, #1
76 str r1, [r0]
77#endif
78
79 /* L2 cache resume & re-enable */
80 l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr
81
82 b cpu_resume
83ENDPROC(tegra_resume)
84#endif
85
86#ifdef CONFIG_CACHE_L2X0
87 .globl l2x0_saved_regs_addr
88l2x0_saved_regs_addr:
89 .long 0
90#endif
91
92 .align L1_CACHE_SHIFT
93ENTRY(__tegra_cpu_reset_handler_start)
94
95/*
96 * __tegra_cpu_reset_handler:
97 *
98 * Common handler for all CPU reset events.
99 *
100 * Register usage within the reset handler:
101 *
102 * R7 = CPU present (to the OS) mask
103 * R8 = CPU in LP1 state mask
104 * R9 = CPU in LP2 state mask
105 * R10 = CPU number
106 * R11 = CPU mask
107 * R12 = pointer to reset handler data
108 *
109 * NOTE: This code is copied to IRAM. All code and data accesses
110 * must be position-independent.
111 */
112
113 .align L1_CACHE_SHIFT
114ENTRY(__tegra_cpu_reset_handler)
115
116 cpsid aif, 0x13 @ SVC mode, interrupts disabled
117 mrc p15, 0, r10, c0, c0, 5 @ MPIDR
118 and r10, r10, #0x3 @ R10 = CPU number
119 mov r11, #1
120 mov r11, r11, lsl r10 @ R11 = CPU mask
121 adr r12, __tegra_cpu_reset_handler_data
122
123#ifdef CONFIG_SMP
124 /* Does the OS know about this CPU? */
125 ldr r7, [r12, #RESET_DATA(MASK_PRESENT)]
126 tst r7, r11 @ if !present
127 bleq __die @ CPU not present (to OS)
128#endif
129
130#ifdef CONFIG_ARCH_TEGRA_2x_SOC
131 /* Are we on Tegra20? */
132 mov32 r6, TEGRA_APB_MISC_BASE
133 ldr r0, [r6, #APB_MISC_GP_HIDREV]
134 and r0, r0, #0xff00
135 cmp r0, #(0x20 << 8)
136 bne 1f
137 /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
138 mov32 r6, TEGRA_PMC_BASE
139 mov r0, #0
140 cmp r10, #0
141 strne r0, [r6, #PMC_SCRATCH41]
1421:
143#endif
144
145 /* Waking up from LP2? */
146 ldr r9, [r12, #RESET_DATA(MASK_LP2)]
147 tst r9, r11 @ if in_lp2
148 beq __is_not_lp2
149 ldr lr, [r12, #RESET_DATA(STARTUP_LP2)]
150 cmp lr, #0
151 bleq __die @ no LP2 startup handler
152 bx lr
153
154__is_not_lp2:
155
156#ifdef CONFIG_SMP
157 /*
158 * Can only be secondary boot (initial or hotplug) but CPU 0
159 * cannot be here.
160 */
161 cmp r10, #0
162 bleq __die @ CPU0 cannot be here
163 ldr lr, [r12, #RESET_DATA(STARTUP_SECONDARY)]
164 cmp lr, #0
165 bleq __die @ no secondary startup handler
166 bx lr
167#endif
168
169/*
170 * We don't know why the CPU reset. Just kill it.
171 * The LR register will contain the address we died at + 4.
172 */
173
174__die:
175 sub lr, lr, #4
176 mov32 r7, TEGRA_PMC_BASE
177 str lr, [r7, #PMC_SCRATCH41]
178
179 mov32 r7, TEGRA_CLK_RESET_BASE
180
181 /* Are we on Tegra20? */
182 mov32 r6, TEGRA_APB_MISC_BASE
183 ldr r0, [r6, #APB_MISC_GP_HIDREV]
184 and r0, r0, #0xff00
185 cmp r0, #(0x20 << 8)
186 bne 1f
187
188#ifdef CONFIG_ARCH_TEGRA_2x_SOC
189 mov32 r0, 0x1111
190 mov r1, r0, lsl r10
191 str r1, [r7, #0x340] @ CLK_RST_CPU_CMPLX_SET
192#endif
1931:
194#ifdef CONFIG_ARCH_TEGRA_3x_SOC
195 mov32 r6, TEGRA_FLOW_CTRL_BASE
196
197 cmp r10, #0
198 moveq r1, #FLOW_CTRL_HALT_CPU0_EVENTS
199 moveq r2, #FLOW_CTRL_CPU0_CSR
200 movne r1, r10, lsl #3
201 addne r2, r1, #(FLOW_CTRL_CPU1_CSR-8)
202 addne r1, r1, #(FLOW_CTRL_HALT_CPU1_EVENTS-8)
203
204 /* Clear CPU "event" and "interrupt" flags and power gate
205 it when halting but not before it is in the "WFI" state. */
206 ldr r0, [r6, +r2]
207 orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
208 orr r0, r0, #FLOW_CTRL_CSR_ENABLE
209 str r0, [r6, +r2]
210
211 /* Unconditionally halt this CPU */
212 mov r0, #FLOW_CTRL_WAITEVENT
213 str r0, [r6, +r1]
214 ldr r0, [r6, +r1] @ memory barrier
215
216 dsb
217 isb
218 wfi @ CPU should be power gated here
219
220 /* If the CPU didn't power gate above just kill it's clock. */
221
222 mov r0, r11, lsl #8
223 str r0, [r7, #348] @ CLK_CPU_CMPLX_SET
224#endif
225
226 /* If the CPU still isn't dead, just spin here. */
227 b .
228ENDPROC(__tegra_cpu_reset_handler)
229
230 .align L1_CACHE_SHIFT
231 .type __tegra_cpu_reset_handler_data, %object
232 .globl __tegra_cpu_reset_handler_data
233__tegra_cpu_reset_handler_data:
234 .rept TEGRA_RESET_DATA_SIZE
235 .long 0
236 .endr
237 .align L1_CACHE_SHIFT
238
239ENTRY(__tegra_cpu_reset_handler_end)
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c
index 3fd89ecd158e..1ac434e0068f 100644
--- a/arch/arm/mach-tegra/reset.c
+++ b/arch/arm/mach-tegra/reset.c
@@ -75,7 +75,7 @@ void __init tegra_cpu_reset_handler_init(void)
75 75
76#ifdef CONFIG_SMP 76#ifdef CONFIG_SMP
77 __tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] = 77 __tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] =
78 *((u32 *)cpu_present_mask); 78 *((u32 *)cpu_possible_mask);
79 __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] = 79 __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] =
80 virt_to_phys((void *)tegra_secondary_startup); 80 virt_to_phys((void *)tegra_secondary_startup);
81#endif 81#endif
diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S
index 72ce709799da..ad2ca07d0578 100644
--- a/arch/arm/mach-tegra/sleep-tegra20.S
+++ b/arch/arm/mach-tegra/sleep-tegra20.S
@@ -33,9 +33,6 @@
33 * should never return 33 * should never return
34 */ 34 */
35ENTRY(tegra20_hotplug_shutdown) 35ENTRY(tegra20_hotplug_shutdown)
36 /* Turn off SMP coherency */
37 exit_smp r4, r5
38
39 /* Put this CPU down */ 36 /* Put this CPU down */
40 cpu_id r0 37 cpu_id r0
41 bl tegra20_cpu_shutdown 38 bl tegra20_cpu_shutdown
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index 562a8e7e413d..63a15bd9b653 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -32,9 +32,6 @@
32 * Should never return. 32 * Should never return.
33 */ 33 */
34ENTRY(tegra30_hotplug_shutdown) 34ENTRY(tegra30_hotplug_shutdown)
35 /* Turn off SMP coherency */
36 exit_smp r4, r5
37
38 /* Powergate this CPU */ 35 /* Powergate this CPU */
39 mov r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN 36 mov r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
40 bl tegra30_cpu_shutdown 37 bl tegra30_cpu_shutdown
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index 26afa7cbed11..addae357da3f 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -34,7 +34,7 @@
34#include "flowctrl.h" 34#include "flowctrl.h"
35#include "sleep.h" 35#include "sleep.h"
36 36
37#ifdef CONFIG_PM_SLEEP 37#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
38/* 38/*
39 * tegra_disable_clean_inv_dcache 39 * tegra_disable_clean_inv_dcache
40 * 40 *
@@ -60,7 +60,9 @@ ENTRY(tegra_disable_clean_inv_dcache)
60 60
61 ldmfd sp!, {r0, r4-r5, r7, r9-r11, pc} 61 ldmfd sp!, {r0, r4-r5, r7, r9-r11, pc}
62ENDPROC(tegra_disable_clean_inv_dcache) 62ENDPROC(tegra_disable_clean_inv_dcache)
63#endif
63 64
65#ifdef CONFIG_PM_SLEEP
64/* 66/*
65 * tegra_sleep_cpu_finish(unsigned long v2p) 67 * tegra_sleep_cpu_finish(unsigned long v2p)
66 * 68 *
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index 9821ee725420..56505c381ea8 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -106,6 +106,7 @@ exit_l2_resume:
106#else 106#else
107void tegra_resume(void); 107void tegra_resume(void);
108int tegra_sleep_cpu_finish(unsigned long); 108int tegra_sleep_cpu_finish(unsigned long);
109void tegra_disable_clean_inv_dcache(void);
109 110
110#ifdef CONFIG_HOTPLUG_CPU 111#ifdef CONFIG_HOTPLUG_CPU
111void tegra20_hotplug_init(void); 112void tegra20_hotplug_init(void);
diff --git a/arch/arm/mach-tegra/tegra20_clocks.c b/arch/arm/mach-tegra/tegra20_clocks.c
deleted file mode 100644
index 4eb6bc81a87b..000000000000
--- a/arch/arm/mach-tegra/tegra20_clocks.c
+++ /dev/null
@@ -1,1623 +0,0 @@
1/*
2 * arch/arm/mach-tegra/tegra20_clocks.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved.
6 *
7 * Author:
8 * Colin Cross <ccross@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/list.h>
24#include <linux/spinlock.h>
25#include <linux/delay.h>
26#include <linux/io.h>
27#include <linux/clkdev.h>
28#include <linux/clk.h>
29
30#include "clock.h"
31#include "fuse.h"
32#include "iomap.h"
33#include "tegra2_emc.h"
34#include "tegra_cpu_car.h"
35
36#define RST_DEVICES 0x004
37#define RST_DEVICES_SET 0x300
38#define RST_DEVICES_CLR 0x304
39#define RST_DEVICES_NUM 3
40
41#define CLK_OUT_ENB 0x010
42#define CLK_OUT_ENB_SET 0x320
43#define CLK_OUT_ENB_CLR 0x324
44#define CLK_OUT_ENB_NUM 3
45
46#define CLK_MASK_ARM 0x44
47#define MISC_CLK_ENB 0x48
48
49#define OSC_CTRL 0x50
50#define OSC_CTRL_OSC_FREQ_MASK (3<<30)
51#define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
52#define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)
53#define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
54#define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)
55#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
56
57#define OSC_FREQ_DET 0x58
58#define OSC_FREQ_DET_TRIG (1<<31)
59
60#define OSC_FREQ_DET_STATUS 0x5C
61#define OSC_FREQ_DET_BUSY (1<<31)
62#define OSC_FREQ_DET_CNT_MASK 0xFFFF
63
64#define PERIPH_CLK_SOURCE_I2S1 0x100
65#define PERIPH_CLK_SOURCE_EMC 0x19c
66#define PERIPH_CLK_SOURCE_OSC 0x1fc
67#define PERIPH_CLK_SOURCE_NUM \
68 ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
69
70#define PERIPH_CLK_SOURCE_MASK (3<<30)
71#define PERIPH_CLK_SOURCE_SHIFT 30
72#define PERIPH_CLK_SOURCE_PWM_MASK (7<<28)
73#define PERIPH_CLK_SOURCE_PWM_SHIFT 28
74#define PERIPH_CLK_SOURCE_ENABLE (1<<28)
75#define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
76#define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
77#define PERIPH_CLK_SOURCE_DIV_SHIFT 0
78
79#define SDMMC_CLK_INT_FB_SEL (1 << 23)
80#define SDMMC_CLK_INT_FB_DLY_SHIFT 16
81#define SDMMC_CLK_INT_FB_DLY_MASK (0xF << SDMMC_CLK_INT_FB_DLY_SHIFT)
82
83#define PLL_BASE 0x0
84#define PLL_BASE_BYPASS (1<<31)
85#define PLL_BASE_ENABLE (1<<30)
86#define PLL_BASE_REF_ENABLE (1<<29)
87#define PLL_BASE_OVERRIDE (1<<28)
88#define PLL_BASE_DIVP_MASK (0x7<<20)
89#define PLL_BASE_DIVP_SHIFT 20
90#define PLL_BASE_DIVN_MASK (0x3FF<<8)
91#define PLL_BASE_DIVN_SHIFT 8
92#define PLL_BASE_DIVM_MASK (0x1F)
93#define PLL_BASE_DIVM_SHIFT 0
94
95#define PLL_OUT_RATIO_MASK (0xFF<<8)
96#define PLL_OUT_RATIO_SHIFT 8
97#define PLL_OUT_OVERRIDE (1<<2)
98#define PLL_OUT_CLKEN (1<<1)
99#define PLL_OUT_RESET_DISABLE (1<<0)
100
101#define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
102
103#define PLL_MISC_DCCON_SHIFT 20
104#define PLL_MISC_CPCON_SHIFT 8
105#define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)
106#define PLL_MISC_LFCON_SHIFT 4
107#define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)
108#define PLL_MISC_VCOCON_SHIFT 0
109#define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)
110
111#define PLLU_BASE_POST_DIV (1<<20)
112
113#define PLLD_MISC_CLKENABLE (1<<30)
114#define PLLD_MISC_DIV_RST (1<<23)
115#define PLLD_MISC_DCCON_SHIFT 12
116
117#define PLLE_MISC_READY (1 << 15)
118
119#define PERIPH_CLK_TO_ENB_REG(c) ((c->u.periph.clk_num / 32) * 4)
120#define PERIPH_CLK_TO_ENB_SET_REG(c) ((c->u.periph.clk_num / 32) * 8)
121#define PERIPH_CLK_TO_ENB_BIT(c) (1 << (c->u.periph.clk_num % 32))
122
123#define SUPER_CLK_MUX 0x00
124#define SUPER_STATE_SHIFT 28
125#define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)
126#define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)
127#define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)
128#define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)
129#define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)
130#define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)
131#define SUPER_SOURCE_MASK 0xF
132#define SUPER_FIQ_SOURCE_SHIFT 12
133#define SUPER_IRQ_SOURCE_SHIFT 8
134#define SUPER_RUN_SOURCE_SHIFT 4
135#define SUPER_IDLE_SOURCE_SHIFT 0
136
137#define SUPER_CLK_DIVIDER 0x04
138
139#define BUS_CLK_DISABLE (1<<3)
140#define BUS_CLK_DIV_MASK 0x3
141
142#define PMC_CTRL 0x0
143 #define PMC_CTRL_BLINK_ENB (1 << 7)
144
145#define PMC_DPD_PADS_ORIDE 0x1c
146 #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20)
147
148#define PMC_BLINK_TIMER_DATA_ON_SHIFT 0
149#define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff
150#define PMC_BLINK_TIMER_ENB (1 << 15)
151#define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16
152#define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff
153
154/* Tegra CPU clock and reset control regs */
155#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
156#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
157#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344
158
159#define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
160#define CPU_RESET(cpu) (0x1111ul << (cpu))
161
162static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
163static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
164
165/*
166 * Some clocks share a register with other clocks. Any clock op that
167 * non-atomically modifies a register used by another clock must lock
168 * clock_register_lock first.
169 */
170static DEFINE_SPINLOCK(clock_register_lock);
171
172/*
173 * Some peripheral clocks share an enable bit, so refcount the enable bits
174 * in registers CLK_ENABLE_L, CLK_ENABLE_H, and CLK_ENABLE_U
175 */
176static int tegra_periph_clk_enable_refcount[3 * 32];
177
178#define clk_writel(value, reg) \
179 __raw_writel(value, reg_clk_base + (reg))
180#define clk_readl(reg) \
181 __raw_readl(reg_clk_base + (reg))
182#define pmc_writel(value, reg) \
183 __raw_writel(value, reg_pmc_base + (reg))
184#define pmc_readl(reg) \
185 __raw_readl(reg_pmc_base + (reg))
186
187static unsigned long clk_measure_input_freq(void)
188{
189 u32 clock_autodetect;
190 clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
191 do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
192 clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
193 if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
194 return 12000000;
195 } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
196 return 13000000;
197 } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
198 return 19200000;
199 } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
200 return 26000000;
201 } else {
202 pr_err("%s: Unexpected clock autodetect value %d",
203 __func__, clock_autodetect);
204 BUG();
205 return 0;
206 }
207}
208
209static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate)
210{
211 s64 divider_u71 = parent_rate * 2;
212 divider_u71 += rate - 1;
213 do_div(divider_u71, rate);
214
215 if (divider_u71 - 2 < 0)
216 return 0;
217
218 if (divider_u71 - 2 > 255)
219 return -EINVAL;
220
221 return divider_u71 - 2;
222}
223
224static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
225{
226 s64 divider_u16;
227
228 divider_u16 = parent_rate;
229 divider_u16 += rate - 1;
230 do_div(divider_u16, rate);
231
232 if (divider_u16 - 1 < 0)
233 return 0;
234
235 if (divider_u16 - 1 > 0xFFFF)
236 return -EINVAL;
237
238 return divider_u16 - 1;
239}
240
241static unsigned long tegra_clk_fixed_recalc_rate(struct clk_hw *hw,
242 unsigned long parent_rate)
243{
244 return to_clk_tegra(hw)->fixed_rate;
245}
246
247struct clk_ops tegra_clk_32k_ops = {
248 .recalc_rate = tegra_clk_fixed_recalc_rate,
249};
250
251/* clk_m functions */
252static unsigned long tegra20_clk_m_recalc_rate(struct clk_hw *hw,
253 unsigned long prate)
254{
255 if (!to_clk_tegra(hw)->fixed_rate)
256 to_clk_tegra(hw)->fixed_rate = clk_measure_input_freq();
257 return to_clk_tegra(hw)->fixed_rate;
258}
259
260static void tegra20_clk_m_init(struct clk_hw *hw)
261{
262 struct clk_tegra *c = to_clk_tegra(hw);
263 u32 osc_ctrl = clk_readl(OSC_CTRL);
264 u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK;
265
266 switch (c->fixed_rate) {
267 case 12000000:
268 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
269 break;
270 case 13000000:
271 auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
272 break;
273 case 19200000:
274 auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
275 break;
276 case 26000000:
277 auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
278 break;
279 default:
280 BUG();
281 }
282 clk_writel(auto_clock_control, OSC_CTRL);
283}
284
285struct clk_ops tegra_clk_m_ops = {
286 .init = tegra20_clk_m_init,
287 .recalc_rate = tegra20_clk_m_recalc_rate,
288};
289
290/* super clock functions */
291/* "super clocks" on tegra have two-stage muxes and a clock skipping
292 * super divider. We will ignore the clock skipping divider, since we
293 * can't lower the voltage when using the clock skip, but we can if we
294 * lower the PLL frequency.
295 */
296static int tegra20_super_clk_is_enabled(struct clk_hw *hw)
297{
298 struct clk_tegra *c = to_clk_tegra(hw);
299 u32 val;
300
301 val = clk_readl(c->reg + SUPER_CLK_MUX);
302 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
303 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
304 c->state = ON;
305 return c->state;
306}
307
308static int tegra20_super_clk_enable(struct clk_hw *hw)
309{
310 struct clk_tegra *c = to_clk_tegra(hw);
311 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
312 return 0;
313}
314
315static void tegra20_super_clk_disable(struct clk_hw *hw)
316{
317 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
318
319 /* oops - don't disable the CPU clock! */
320 BUG();
321}
322
323static u8 tegra20_super_clk_get_parent(struct clk_hw *hw)
324{
325 struct clk_tegra *c = to_clk_tegra(hw);
326 int val = clk_readl(c->reg + SUPER_CLK_MUX);
327 int source;
328 int shift;
329
330 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
331 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
332 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
333 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
334 source = (val >> shift) & SUPER_SOURCE_MASK;
335 return source;
336}
337
338static int tegra20_super_clk_set_parent(struct clk_hw *hw, u8 index)
339{
340 struct clk_tegra *c = to_clk_tegra(hw);
341 u32 val = clk_readl(c->reg + SUPER_CLK_MUX);
342 int shift;
343
344 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
345 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
346 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
347 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
348 val &= ~(SUPER_SOURCE_MASK << shift);
349 val |= index << shift;
350
351 clk_writel(val, c->reg);
352
353 return 0;
354}
355
356/* FIX ME: Need to switch parents to change the source PLL rate */
357static unsigned long tegra20_super_clk_recalc_rate(struct clk_hw *hw,
358 unsigned long prate)
359{
360 return prate;
361}
362
363static long tegra20_super_clk_round_rate(struct clk_hw *hw, unsigned long rate,
364 unsigned long *prate)
365{
366 return *prate;
367}
368
369static int tegra20_super_clk_set_rate(struct clk_hw *hw, unsigned long rate,
370 unsigned long parent_rate)
371{
372 return 0;
373}
374
375struct clk_ops tegra_super_ops = {
376 .is_enabled = tegra20_super_clk_is_enabled,
377 .enable = tegra20_super_clk_enable,
378 .disable = tegra20_super_clk_disable,
379 .set_parent = tegra20_super_clk_set_parent,
380 .get_parent = tegra20_super_clk_get_parent,
381 .set_rate = tegra20_super_clk_set_rate,
382 .round_rate = tegra20_super_clk_round_rate,
383 .recalc_rate = tegra20_super_clk_recalc_rate,
384};
385
386static unsigned long tegra20_twd_clk_recalc_rate(struct clk_hw *hw,
387 unsigned long parent_rate)
388{
389 struct clk_tegra *c = to_clk_tegra(hw);
390 u64 rate = parent_rate;
391
392 if (c->mul != 0 && c->div != 0) {
393 rate *= c->mul;
394 rate += c->div - 1; /* round up */
395 do_div(rate, c->div);
396 }
397
398 return rate;
399}
400
401struct clk_ops tegra_twd_ops = {
402 .recalc_rate = tegra20_twd_clk_recalc_rate,
403};
404
405static u8 tegra20_cop_clk_get_parent(struct clk_hw *hw)
406{
407 return 0;
408}
409
410struct clk_ops tegra_cop_ops = {
411 .get_parent = tegra20_cop_clk_get_parent,
412};
413
414/* virtual cop clock functions. Used to acquire the fake 'cop' clock to
415 * reset the COP block (i.e. AVP) */
416void tegra2_cop_clk_reset(struct clk_hw *hw, bool assert)
417{
418 unsigned long reg = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
419
420 pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert");
421 clk_writel(1 << 1, reg);
422}
423
424/* bus clock functions */
425static int tegra20_bus_clk_is_enabled(struct clk_hw *hw)
426{
427 struct clk_tegra *c = to_clk_tegra(hw);
428 u32 val = clk_readl(c->reg);
429
430 c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
431 return c->state;
432}
433
434static int tegra20_bus_clk_enable(struct clk_hw *hw)
435{
436 struct clk_tegra *c = to_clk_tegra(hw);
437 unsigned long flags;
438 u32 val;
439
440 spin_lock_irqsave(&clock_register_lock, flags);
441
442 val = clk_readl(c->reg);
443 val &= ~(BUS_CLK_DISABLE << c->reg_shift);
444 clk_writel(val, c->reg);
445
446 spin_unlock_irqrestore(&clock_register_lock, flags);
447
448 return 0;
449}
450
451static void tegra20_bus_clk_disable(struct clk_hw *hw)
452{
453 struct clk_tegra *c = to_clk_tegra(hw);
454 unsigned long flags;
455 u32 val;
456
457 spin_lock_irqsave(&clock_register_lock, flags);
458
459 val = clk_readl(c->reg);
460 val |= BUS_CLK_DISABLE << c->reg_shift;
461 clk_writel(val, c->reg);
462
463 spin_unlock_irqrestore(&clock_register_lock, flags);
464}
465
466static unsigned long tegra20_bus_clk_recalc_rate(struct clk_hw *hw,
467 unsigned long prate)
468{
469 struct clk_tegra *c = to_clk_tegra(hw);
470 u32 val = clk_readl(c->reg);
471 u64 rate = prate;
472
473 c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
474 c->mul = 1;
475
476 if (c->mul != 0 && c->div != 0) {
477 rate *= c->mul;
478 rate += c->div - 1; /* round up */
479 do_div(rate, c->div);
480 }
481 return rate;
482}
483
484static int tegra20_bus_clk_set_rate(struct clk_hw *hw, unsigned long rate,
485 unsigned long parent_rate)
486{
487 struct clk_tegra *c = to_clk_tegra(hw);
488 int ret = -EINVAL;
489 unsigned long flags;
490 u32 val;
491 int i;
492
493 spin_lock_irqsave(&clock_register_lock, flags);
494
495 val = clk_readl(c->reg);
496 for (i = 1; i <= 4; i++) {
497 if (rate == parent_rate / i) {
498 val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
499 val |= (i - 1) << c->reg_shift;
500 clk_writel(val, c->reg);
501 c->div = i;
502 c->mul = 1;
503 ret = 0;
504 break;
505 }
506 }
507
508 spin_unlock_irqrestore(&clock_register_lock, flags);
509
510 return ret;
511}
512
513static long tegra20_bus_clk_round_rate(struct clk_hw *hw, unsigned long rate,
514 unsigned long *prate)
515{
516 unsigned long parent_rate = *prate;
517 s64 divider;
518
519 if (rate >= parent_rate)
520 return rate;
521
522 divider = parent_rate;
523 divider += rate - 1;
524 do_div(divider, rate);
525
526 if (divider < 0)
527 return divider;
528
529 if (divider > 4)
530 divider = 4;
531 do_div(parent_rate, divider);
532
533 return parent_rate;
534}
535
536struct clk_ops tegra_bus_ops = {
537 .is_enabled = tegra20_bus_clk_is_enabled,
538 .enable = tegra20_bus_clk_enable,
539 .disable = tegra20_bus_clk_disable,
540 .set_rate = tegra20_bus_clk_set_rate,
541 .round_rate = tegra20_bus_clk_round_rate,
542 .recalc_rate = tegra20_bus_clk_recalc_rate,
543};
544
545/* Blink output functions */
546static int tegra20_blink_clk_is_enabled(struct clk_hw *hw)
547{
548 struct clk_tegra *c = to_clk_tegra(hw);
549 u32 val;
550
551 val = pmc_readl(PMC_CTRL);
552 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
553 return c->state;
554}
555
556static unsigned long tegra20_blink_clk_recalc_rate(struct clk_hw *hw,
557 unsigned long prate)
558{
559 struct clk_tegra *c = to_clk_tegra(hw);
560 u64 rate = prate;
561 u32 val;
562
563 c->mul = 1;
564 val = pmc_readl(c->reg);
565
566 if (val & PMC_BLINK_TIMER_ENB) {
567 unsigned int on_off;
568
569 on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
570 PMC_BLINK_TIMER_DATA_ON_MASK;
571 val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
572 val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
573 on_off += val;
574 /* each tick in the blink timer is 4 32KHz clocks */
575 c->div = on_off * 4;
576 } else {
577 c->div = 1;
578 }
579
580 if (c->mul != 0 && c->div != 0) {
581 rate *= c->mul;
582 rate += c->div - 1; /* round up */
583 do_div(rate, c->div);
584 }
585 return rate;
586}
587
588static int tegra20_blink_clk_enable(struct clk_hw *hw)
589{
590 u32 val;
591
592 val = pmc_readl(PMC_DPD_PADS_ORIDE);
593 pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
594
595 val = pmc_readl(PMC_CTRL);
596 pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
597
598 return 0;
599}
600
601static void tegra20_blink_clk_disable(struct clk_hw *hw)
602{
603 u32 val;
604
605 val = pmc_readl(PMC_CTRL);
606 pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
607
608 val = pmc_readl(PMC_DPD_PADS_ORIDE);
609 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
610}
611
612static int tegra20_blink_clk_set_rate(struct clk_hw *hw, unsigned long rate,
613 unsigned long parent_rate)
614{
615 struct clk_tegra *c = to_clk_tegra(hw);
616
617 if (rate >= parent_rate) {
618 c->div = 1;
619 pmc_writel(0, c->reg);
620 } else {
621 unsigned int on_off;
622 u32 val;
623
624 on_off = DIV_ROUND_UP(parent_rate / 8, rate);
625 c->div = on_off * 8;
626
627 val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
628 PMC_BLINK_TIMER_DATA_ON_SHIFT;
629 on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
630 on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
631 val |= on_off;
632 val |= PMC_BLINK_TIMER_ENB;
633 pmc_writel(val, c->reg);
634 }
635
636 return 0;
637}
638
639static long tegra20_blink_clk_round_rate(struct clk_hw *hw, unsigned long rate,
640 unsigned long *prate)
641{
642 int div;
643 int mul;
644 long round_rate = *prate;
645
646 mul = 1;
647
648 if (rate >= *prate) {
649 div = 1;
650 } else {
651 div = DIV_ROUND_UP(*prate / 8, rate);
652 div *= 8;
653 }
654
655 round_rate *= mul;
656 round_rate += div - 1;
657 do_div(round_rate, div);
658
659 return round_rate;
660}
661
662struct clk_ops tegra_blink_clk_ops = {
663 .is_enabled = tegra20_blink_clk_is_enabled,
664 .enable = tegra20_blink_clk_enable,
665 .disable = tegra20_blink_clk_disable,
666 .set_rate = tegra20_blink_clk_set_rate,
667 .round_rate = tegra20_blink_clk_round_rate,
668 .recalc_rate = tegra20_blink_clk_recalc_rate,
669};
670
671/* PLL Functions */
672static int tegra20_pll_clk_wait_for_lock(struct clk_tegra *c)
673{
674 udelay(c->u.pll.lock_delay);
675 return 0;
676}
677
678static int tegra20_pll_clk_is_enabled(struct clk_hw *hw)
679{
680 struct clk_tegra *c = to_clk_tegra(hw);
681 u32 val = clk_readl(c->reg + PLL_BASE);
682
683 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
684 return c->state;
685}
686
687static unsigned long tegra20_pll_clk_recalc_rate(struct clk_hw *hw,
688 unsigned long prate)
689{
690 struct clk_tegra *c = to_clk_tegra(hw);
691 u32 val = clk_readl(c->reg + PLL_BASE);
692 u64 rate = prate;
693
694 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
695 const struct clk_pll_freq_table *sel;
696 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
697 if (sel->input_rate == prate &&
698 sel->output_rate == c->u.pll.fixed_rate) {
699 c->mul = sel->n;
700 c->div = sel->m * sel->p;
701 break;
702 }
703 }
704 pr_err("Clock %s has unknown fixed frequency\n",
705 __clk_get_name(hw->clk));
706 BUG();
707 } else if (val & PLL_BASE_BYPASS) {
708 c->mul = 1;
709 c->div = 1;
710 } else {
711 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
712 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
713 if (c->flags & PLLU)
714 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
715 else
716 c->div *= (val & PLL_BASE_DIVP_MASK) ? 2 : 1;
717 }
718
719 if (c->mul != 0 && c->div != 0) {
720 rate *= c->mul;
721 rate += c->div - 1; /* round up */
722 do_div(rate, c->div);
723 }
724 return rate;
725}
726
727static int tegra20_pll_clk_enable(struct clk_hw *hw)
728{
729 struct clk_tegra *c = to_clk_tegra(hw);
730 u32 val;
731 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
732
733 val = clk_readl(c->reg + PLL_BASE);
734 val &= ~PLL_BASE_BYPASS;
735 val |= PLL_BASE_ENABLE;
736 clk_writel(val, c->reg + PLL_BASE);
737
738 tegra20_pll_clk_wait_for_lock(c);
739
740 return 0;
741}
742
743static void tegra20_pll_clk_disable(struct clk_hw *hw)
744{
745 struct clk_tegra *c = to_clk_tegra(hw);
746 u32 val;
747 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
748
749 val = clk_readl(c->reg);
750 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
751 clk_writel(val, c->reg);
752}
753
754static int tegra20_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
755 unsigned long parent_rate)
756{
757 struct clk_tegra *c = to_clk_tegra(hw);
758 unsigned long input_rate = parent_rate;
759 const struct clk_pll_freq_table *sel;
760 u32 val;
761
762 pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
763
764 if (c->flags & PLL_FIXED) {
765 int ret = 0;
766 if (rate != c->u.pll.fixed_rate) {
767 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
768 __func__, __clk_get_name(hw->clk),
769 c->u.pll.fixed_rate, rate);
770 ret = -EINVAL;
771 }
772 return ret;
773 }
774
775 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
776 if (sel->input_rate == input_rate && sel->output_rate == rate) {
777 c->mul = sel->n;
778 c->div = sel->m * sel->p;
779
780 val = clk_readl(c->reg + PLL_BASE);
781 if (c->flags & PLL_FIXED)
782 val |= PLL_BASE_OVERRIDE;
783 val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK |
784 PLL_BASE_DIVM_MASK);
785 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
786 (sel->n << PLL_BASE_DIVN_SHIFT);
787 BUG_ON(sel->p < 1 || sel->p > 2);
788 if (c->flags & PLLU) {
789 if (sel->p == 1)
790 val |= PLLU_BASE_POST_DIV;
791 } else {
792 if (sel->p == 2)
793 val |= 1 << PLL_BASE_DIVP_SHIFT;
794 }
795 clk_writel(val, c->reg + PLL_BASE);
796
797 if (c->flags & PLL_HAS_CPCON) {
798 val = clk_readl(c->reg + PLL_MISC(c));
799 val &= ~PLL_MISC_CPCON_MASK;
800 val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
801 clk_writel(val, c->reg + PLL_MISC(c));
802 }
803
804 if (c->state == ON)
805 tegra20_pll_clk_enable(hw);
806 return 0;
807 }
808 }
809 return -EINVAL;
810}
811
812static long tegra20_pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
813 unsigned long *prate)
814{
815 struct clk_tegra *c = to_clk_tegra(hw);
816 const struct clk_pll_freq_table *sel;
817 unsigned long input_rate = *prate;
818 u64 output_rate = *prate;
819 int mul;
820 int div;
821
822 if (c->flags & PLL_FIXED)
823 return c->u.pll.fixed_rate;
824
825 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++)
826 if (sel->input_rate == input_rate && sel->output_rate == rate) {
827 mul = sel->n;
828 div = sel->m * sel->p;
829 break;
830 }
831
832 if (sel->input_rate == 0)
833 return -EINVAL;
834
835 output_rate *= mul;
836 output_rate += div - 1; /* round up */
837 do_div(output_rate, div);
838
839 return output_rate;
840}
841
842struct clk_ops tegra_pll_ops = {
843 .is_enabled = tegra20_pll_clk_is_enabled,
844 .enable = tegra20_pll_clk_enable,
845 .disable = tegra20_pll_clk_disable,
846 .set_rate = tegra20_pll_clk_set_rate,
847 .recalc_rate = tegra20_pll_clk_recalc_rate,
848 .round_rate = tegra20_pll_clk_round_rate,
849};
850
851static void tegra20_pllx_clk_init(struct clk_hw *hw)
852{
853 struct clk_tegra *c = to_clk_tegra(hw);
854
855 if (tegra_sku_id == 7)
856 c->max_rate = 750000000;
857}
858
859struct clk_ops tegra_pllx_ops = {
860 .init = tegra20_pllx_clk_init,
861 .is_enabled = tegra20_pll_clk_is_enabled,
862 .enable = tegra20_pll_clk_enable,
863 .disable = tegra20_pll_clk_disable,
864 .set_rate = tegra20_pll_clk_set_rate,
865 .recalc_rate = tegra20_pll_clk_recalc_rate,
866 .round_rate = tegra20_pll_clk_round_rate,
867};
868
869static int tegra20_plle_clk_enable(struct clk_hw *hw)
870{
871 struct clk_tegra *c = to_clk_tegra(hw);
872 u32 val;
873
874 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
875
876 mdelay(1);
877
878 val = clk_readl(c->reg + PLL_BASE);
879 if (!(val & PLLE_MISC_READY))
880 return -EBUSY;
881
882 val = clk_readl(c->reg + PLL_BASE);
883 val |= PLL_BASE_ENABLE | PLL_BASE_BYPASS;
884 clk_writel(val, c->reg + PLL_BASE);
885
886 return 0;
887}
888
889struct clk_ops tegra_plle_ops = {
890 .is_enabled = tegra20_pll_clk_is_enabled,
891 .enable = tegra20_plle_clk_enable,
892 .set_rate = tegra20_pll_clk_set_rate,
893 .recalc_rate = tegra20_pll_clk_recalc_rate,
894 .round_rate = tegra20_pll_clk_round_rate,
895};
896
897/* Clock divider ops */
898static int tegra20_pll_div_clk_is_enabled(struct clk_hw *hw)
899{
900 struct clk_tegra *c = to_clk_tegra(hw);
901 u32 val = clk_readl(c->reg);
902
903 val >>= c->reg_shift;
904 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
905 if (!(val & PLL_OUT_RESET_DISABLE))
906 c->state = OFF;
907 return c->state;
908}
909
910static unsigned long tegra20_pll_div_clk_recalc_rate(struct clk_hw *hw,
911 unsigned long prate)
912{
913 struct clk_tegra *c = to_clk_tegra(hw);
914 u64 rate = prate;
915 u32 val = clk_readl(c->reg);
916 u32 divu71;
917
918 val >>= c->reg_shift;
919
920 if (c->flags & DIV_U71) {
921 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
922 c->div = (divu71 + 2);
923 c->mul = 2;
924 } else if (c->flags & DIV_2) {
925 c->div = 2;
926 c->mul = 1;
927 } else {
928 c->div = 1;
929 c->mul = 1;
930 }
931
932 rate *= c->mul;
933 rate += c->div - 1; /* round up */
934 do_div(rate, c->div);
935
936 return rate;
937}
938
939static int tegra20_pll_div_clk_enable(struct clk_hw *hw)
940{
941 struct clk_tegra *c = to_clk_tegra(hw);
942 unsigned long flags;
943 u32 new_val;
944 u32 val;
945
946 pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
947
948 if (c->flags & DIV_U71) {
949 spin_lock_irqsave(&clock_register_lock, flags);
950 val = clk_readl(c->reg);
951 new_val = val >> c->reg_shift;
952 new_val &= 0xFFFF;
953
954 new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
955
956 val &= ~(0xFFFF << c->reg_shift);
957 val |= new_val << c->reg_shift;
958 clk_writel(val, c->reg);
959 spin_unlock_irqrestore(&clock_register_lock, flags);
960 return 0;
961 } else if (c->flags & DIV_2) {
962 BUG_ON(!(c->flags & PLLD));
963 spin_lock_irqsave(&clock_register_lock, flags);
964 val = clk_readl(c->reg);
965 val &= ~PLLD_MISC_DIV_RST;
966 clk_writel(val, c->reg);
967 spin_unlock_irqrestore(&clock_register_lock, flags);
968 return 0;
969 }
970 return -EINVAL;
971}
972
973static void tegra20_pll_div_clk_disable(struct clk_hw *hw)
974{
975 struct clk_tegra *c = to_clk_tegra(hw);
976 unsigned long flags;
977 u32 new_val;
978 u32 val;
979
980 pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
981
982 if (c->flags & DIV_U71) {
983 spin_lock_irqsave(&clock_register_lock, flags);
984 val = clk_readl(c->reg);
985 new_val = val >> c->reg_shift;
986 new_val &= 0xFFFF;
987
988 new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
989
990 val &= ~(0xFFFF << c->reg_shift);
991 val |= new_val << c->reg_shift;
992 clk_writel(val, c->reg);
993 spin_unlock_irqrestore(&clock_register_lock, flags);
994 } else if (c->flags & DIV_2) {
995 BUG_ON(!(c->flags & PLLD));
996 spin_lock_irqsave(&clock_register_lock, flags);
997 val = clk_readl(c->reg);
998 val |= PLLD_MISC_DIV_RST;
999 clk_writel(val, c->reg);
1000 spin_unlock_irqrestore(&clock_register_lock, flags);
1001 }
1002}
1003
1004static int tegra20_pll_div_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1005 unsigned long parent_rate)
1006{
1007 struct clk_tegra *c = to_clk_tegra(hw);
1008 unsigned long flags;
1009 int divider_u71;
1010 u32 new_val;
1011 u32 val;
1012
1013 pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
1014
1015 if (c->flags & DIV_U71) {
1016 divider_u71 = clk_div71_get_divider(parent_rate, rate);
1017 if (divider_u71 >= 0) {
1018 spin_lock_irqsave(&clock_register_lock, flags);
1019 val = clk_readl(c->reg);
1020 new_val = val >> c->reg_shift;
1021 new_val &= 0xFFFF;
1022 if (c->flags & DIV_U71_FIXED)
1023 new_val |= PLL_OUT_OVERRIDE;
1024 new_val &= ~PLL_OUT_RATIO_MASK;
1025 new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
1026
1027 val &= ~(0xFFFF << c->reg_shift);
1028 val |= new_val << c->reg_shift;
1029 clk_writel(val, c->reg);
1030 c->div = divider_u71 + 2;
1031 c->mul = 2;
1032 spin_unlock_irqrestore(&clock_register_lock, flags);
1033 return 0;
1034 }
1035 } else if (c->flags & DIV_2) {
1036 if (parent_rate == rate * 2)
1037 return 0;
1038 }
1039 return -EINVAL;
1040}
1041
1042static long tegra20_pll_div_clk_round_rate(struct clk_hw *hw, unsigned long rate,
1043 unsigned long *prate)
1044{
1045 struct clk_tegra *c = to_clk_tegra(hw);
1046 unsigned long parent_rate = *prate;
1047 int divider;
1048
1049 pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
1050
1051 if (c->flags & DIV_U71) {
1052 divider = clk_div71_get_divider(parent_rate, rate);
1053 if (divider < 0)
1054 return divider;
1055 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
1056 } else if (c->flags & DIV_2) {
1057 return DIV_ROUND_UP(parent_rate, 2);
1058 }
1059 return -EINVAL;
1060}
1061
1062struct clk_ops tegra_pll_div_ops = {
1063 .is_enabled = tegra20_pll_div_clk_is_enabled,
1064 .enable = tegra20_pll_div_clk_enable,
1065 .disable = tegra20_pll_div_clk_disable,
1066 .set_rate = tegra20_pll_div_clk_set_rate,
1067 .round_rate = tegra20_pll_div_clk_round_rate,
1068 .recalc_rate = tegra20_pll_div_clk_recalc_rate,
1069};
1070
1071/* Periph clk ops */
1072
1073static int tegra20_periph_clk_is_enabled(struct clk_hw *hw)
1074{
1075 struct clk_tegra *c = to_clk_tegra(hw);
1076
1077 c->state = ON;
1078
1079 if (!c->u.periph.clk_num)
1080 goto out;
1081
1082 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1083 PERIPH_CLK_TO_ENB_BIT(c)))
1084 c->state = OFF;
1085
1086 if (!(c->flags & PERIPH_NO_RESET))
1087 if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) &
1088 PERIPH_CLK_TO_ENB_BIT(c))
1089 c->state = OFF;
1090
1091out:
1092 return c->state;
1093}
1094
1095static int tegra20_periph_clk_enable(struct clk_hw *hw)
1096{
1097 struct clk_tegra *c = to_clk_tegra(hw);
1098 unsigned long flags;
1099 u32 val;
1100
1101 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
1102
1103 if (!c->u.periph.clk_num)
1104 return 0;
1105
1106 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
1107 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1)
1108 return 0;
1109
1110 spin_lock_irqsave(&clock_register_lock, flags);
1111
1112 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1113 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
1114 if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET))
1115 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1116 RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1117 if (c->flags & PERIPH_EMC_ENB) {
1118 /* The EMC peripheral clock has 2 extra enable bits */
1119 /* FIXME: Do they need to be disabled? */
1120 val = clk_readl(c->reg);
1121 val |= 0x3 << 24;
1122 clk_writel(val, c->reg);
1123 }
1124
1125 spin_unlock_irqrestore(&clock_register_lock, flags);
1126
1127 return 0;
1128}
1129
1130static void tegra20_periph_clk_disable(struct clk_hw *hw)
1131{
1132 struct clk_tegra *c = to_clk_tegra(hw);
1133 unsigned long flags;
1134
1135 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
1136
1137 if (!c->u.periph.clk_num)
1138 return;
1139
1140 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
1141
1142 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 0)
1143 return;
1144
1145 spin_lock_irqsave(&clock_register_lock, flags);
1146
1147 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1148 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1149
1150 spin_unlock_irqrestore(&clock_register_lock, flags);
1151}
1152
1153void tegra2_periph_clk_reset(struct clk_hw *hw, bool assert)
1154{
1155 struct clk_tegra *c = to_clk_tegra(hw);
1156 unsigned long base = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
1157
1158 pr_debug("%s %s on clock %s\n", __func__,
1159 assert ? "assert" : "deassert", __clk_get_name(hw->clk));
1160
1161 BUG_ON(!c->u.periph.clk_num);
1162
1163 if (!(c->flags & PERIPH_NO_RESET))
1164 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1165 base + PERIPH_CLK_TO_ENB_SET_REG(c));
1166}
1167
1168static int tegra20_periph_clk_set_parent(struct clk_hw *hw, u8 index)
1169{
1170 struct clk_tegra *c = to_clk_tegra(hw);
1171 u32 val;
1172 u32 mask;
1173 u32 shift;
1174
1175 pr_debug("%s: %s %d\n", __func__, __clk_get_name(hw->clk), index);
1176
1177 if (c->flags & MUX_PWM) {
1178 shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
1179 mask = PERIPH_CLK_SOURCE_PWM_MASK;
1180 } else {
1181 shift = PERIPH_CLK_SOURCE_SHIFT;
1182 mask = PERIPH_CLK_SOURCE_MASK;
1183 }
1184
1185 val = clk_readl(c->reg);
1186 val &= ~mask;
1187 val |= (index) << shift;
1188
1189 clk_writel(val, c->reg);
1190
1191 return 0;
1192}
1193
1194static u8 tegra20_periph_clk_get_parent(struct clk_hw *hw)
1195{
1196 struct clk_tegra *c = to_clk_tegra(hw);
1197 u32 val = clk_readl(c->reg);
1198 u32 mask;
1199 u32 shift;
1200
1201 if (c->flags & MUX_PWM) {
1202 shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
1203 mask = PERIPH_CLK_SOURCE_PWM_MASK;
1204 } else {
1205 shift = PERIPH_CLK_SOURCE_SHIFT;
1206 mask = PERIPH_CLK_SOURCE_MASK;
1207 }
1208
1209 if (c->flags & MUX)
1210 return (val & mask) >> shift;
1211 else
1212 return 0;
1213}
1214
1215static unsigned long tegra20_periph_clk_recalc_rate(struct clk_hw *hw,
1216 unsigned long prate)
1217{
1218 struct clk_tegra *c = to_clk_tegra(hw);
1219 unsigned long rate = prate;
1220 u32 val = clk_readl(c->reg);
1221
1222 if (c->flags & DIV_U71) {
1223 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
1224 c->div = divu71 + 2;
1225 c->mul = 2;
1226 } else if (c->flags & DIV_U16) {
1227 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
1228 c->div = divu16 + 1;
1229 c->mul = 1;
1230 } else {
1231 c->div = 1;
1232 c->mul = 1;
1233 return rate;
1234 }
1235
1236 if (c->mul != 0 && c->div != 0) {
1237 rate *= c->mul;
1238 rate += c->div - 1; /* round up */
1239 do_div(rate, c->div);
1240 }
1241
1242 return rate;
1243}
1244
1245static int tegra20_periph_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1246 unsigned long parent_rate)
1247{
1248 struct clk_tegra *c = to_clk_tegra(hw);
1249 u32 val;
1250 int divider;
1251
1252 val = clk_readl(c->reg);
1253
1254 if (c->flags & DIV_U71) {
1255 divider = clk_div71_get_divider(parent_rate, rate);
1256
1257 if (divider >= 0) {
1258 val = clk_readl(c->reg);
1259 val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
1260 val |= divider;
1261 clk_writel(val, c->reg);
1262 c->div = divider + 2;
1263 c->mul = 2;
1264 return 0;
1265 }
1266 } else if (c->flags & DIV_U16) {
1267 divider = clk_div16_get_divider(parent_rate, rate);
1268 if (divider >= 0) {
1269 val = clk_readl(c->reg);
1270 val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
1271 val |= divider;
1272 clk_writel(val, c->reg);
1273 c->div = divider + 1;
1274 c->mul = 1;
1275 return 0;
1276 }
1277 } else if (parent_rate <= rate) {
1278 c->div = 1;
1279 c->mul = 1;
1280 return 0;
1281 }
1282
1283 return -EINVAL;
1284}
1285
1286static long tegra20_periph_clk_round_rate(struct clk_hw *hw,
1287 unsigned long rate, unsigned long *prate)
1288{
1289 struct clk_tegra *c = to_clk_tegra(hw);
1290 unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
1291 int divider;
1292
1293 pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
1294
1295 if (prate)
1296 parent_rate = *prate;
1297
1298 if (c->flags & DIV_U71) {
1299 divider = clk_div71_get_divider(parent_rate, rate);
1300 if (divider < 0)
1301 return divider;
1302
1303 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
1304 } else if (c->flags & DIV_U16) {
1305 divider = clk_div16_get_divider(parent_rate, rate);
1306 if (divider < 0)
1307 return divider;
1308 return DIV_ROUND_UP(parent_rate, divider + 1);
1309 }
1310 return -EINVAL;
1311}
1312
1313struct clk_ops tegra_periph_clk_ops = {
1314 .is_enabled = tegra20_periph_clk_is_enabled,
1315 .enable = tegra20_periph_clk_enable,
1316 .disable = tegra20_periph_clk_disable,
1317 .set_parent = tegra20_periph_clk_set_parent,
1318 .get_parent = tegra20_periph_clk_get_parent,
1319 .set_rate = tegra20_periph_clk_set_rate,
1320 .round_rate = tegra20_periph_clk_round_rate,
1321 .recalc_rate = tegra20_periph_clk_recalc_rate,
1322};
1323
1324/* External memory controller clock ops */
1325static void tegra20_emc_clk_init(struct clk_hw *hw)
1326{
1327 struct clk_tegra *c = to_clk_tegra(hw);
1328 c->max_rate = __clk_get_rate(hw->clk);
1329}
1330
1331static long tegra20_emc_clk_round_rate(struct clk_hw *hw, unsigned long rate,
1332 unsigned long *prate)
1333{
1334 struct clk_tegra *c = to_clk_tegra(hw);
1335 long emc_rate;
1336 long clk_rate;
1337
1338 /*
1339 * The slowest entry in the EMC clock table that is at least as
1340 * fast as rate.
1341 */
1342 emc_rate = tegra_emc_round_rate(rate);
1343 if (emc_rate < 0)
1344 return c->max_rate;
1345
1346 /*
1347 * The fastest rate the PLL will generate that is at most the
1348 * requested rate.
1349 */
1350 clk_rate = tegra20_periph_clk_round_rate(hw, emc_rate, NULL);
1351
1352 /*
1353 * If this fails, and emc_rate > clk_rate, it's because the maximum
1354 * rate in the EMC tables is larger than the maximum rate of the EMC
1355 * clock. The EMC clock's max rate is the rate it was running when the
1356 * kernel booted. Such a mismatch is probably due to using the wrong
1357 * BCT, i.e. using a Tegra20 BCT with an EMC table written for Tegra25.
1358 */
1359 WARN_ONCE(emc_rate != clk_rate,
1360 "emc_rate %ld != clk_rate %ld",
1361 emc_rate, clk_rate);
1362
1363 return emc_rate;
1364}
1365
1366static int tegra20_emc_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1367 unsigned long parent_rate)
1368{
1369 int ret;
1370
1371 /*
1372 * The Tegra2 memory controller has an interlock with the clock
1373 * block that allows memory shadowed registers to be updated,
1374 * and then transfer them to the main registers at the same
1375 * time as the clock update without glitches.
1376 */
1377 ret = tegra_emc_set_rate(rate);
1378 if (ret < 0)
1379 return ret;
1380
1381 ret = tegra20_periph_clk_set_rate(hw, rate, parent_rate);
1382 udelay(1);
1383
1384 return ret;
1385}
1386
1387struct clk_ops tegra_emc_clk_ops = {
1388 .init = tegra20_emc_clk_init,
1389 .is_enabled = tegra20_periph_clk_is_enabled,
1390 .enable = tegra20_periph_clk_enable,
1391 .disable = tegra20_periph_clk_disable,
1392 .set_parent = tegra20_periph_clk_set_parent,
1393 .get_parent = tegra20_periph_clk_get_parent,
1394 .set_rate = tegra20_emc_clk_set_rate,
1395 .round_rate = tegra20_emc_clk_round_rate,
1396 .recalc_rate = tegra20_periph_clk_recalc_rate,
1397};
1398
1399/* Clock doubler ops */
1400static int tegra20_clk_double_is_enabled(struct clk_hw *hw)
1401{
1402 struct clk_tegra *c = to_clk_tegra(hw);
1403
1404 c->state = ON;
1405
1406 if (!c->u.periph.clk_num)
1407 goto out;
1408
1409 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1410 PERIPH_CLK_TO_ENB_BIT(c)))
1411 c->state = OFF;
1412
1413out:
1414 return c->state;
1415};
1416
1417static unsigned long tegra20_clk_double_recalc_rate(struct clk_hw *hw,
1418 unsigned long prate)
1419{
1420 struct clk_tegra *c = to_clk_tegra(hw);
1421 u64 rate = prate;
1422
1423 c->mul = 2;
1424 c->div = 1;
1425
1426 rate *= c->mul;
1427 rate += c->div - 1; /* round up */
1428 do_div(rate, c->div);
1429
1430 return rate;
1431}
1432
1433static long tegra20_clk_double_round_rate(struct clk_hw *hw, unsigned long rate,
1434 unsigned long *prate)
1435{
1436 unsigned long output_rate = *prate;
1437
1438 do_div(output_rate, 2);
1439 return output_rate;
1440}
1441
1442static int tegra20_clk_double_set_rate(struct clk_hw *hw, unsigned long rate,
1443 unsigned long parent_rate)
1444{
1445 if (rate != 2 * parent_rate)
1446 return -EINVAL;
1447 return 0;
1448}
1449
1450struct clk_ops tegra_clk_double_ops = {
1451 .is_enabled = tegra20_clk_double_is_enabled,
1452 .enable = tegra20_periph_clk_enable,
1453 .disable = tegra20_periph_clk_disable,
1454 .set_rate = tegra20_clk_double_set_rate,
1455 .recalc_rate = tegra20_clk_double_recalc_rate,
1456 .round_rate = tegra20_clk_double_round_rate,
1457};
1458
1459/* Audio sync clock ops */
1460static int tegra20_audio_sync_clk_is_enabled(struct clk_hw *hw)
1461{
1462 struct clk_tegra *c = to_clk_tegra(hw);
1463 u32 val = clk_readl(c->reg);
1464
1465 c->state = (val & (1<<4)) ? OFF : ON;
1466 return c->state;
1467}
1468
1469static int tegra20_audio_sync_clk_enable(struct clk_hw *hw)
1470{
1471 struct clk_tegra *c = to_clk_tegra(hw);
1472
1473 clk_writel(0, c->reg);
1474 return 0;
1475}
1476
1477static void tegra20_audio_sync_clk_disable(struct clk_hw *hw)
1478{
1479 struct clk_tegra *c = to_clk_tegra(hw);
1480 clk_writel(1, c->reg);
1481}
1482
1483static u8 tegra20_audio_sync_clk_get_parent(struct clk_hw *hw)
1484{
1485 struct clk_tegra *c = to_clk_tegra(hw);
1486 u32 val = clk_readl(c->reg);
1487 int source;
1488
1489 source = val & 0xf;
1490 return source;
1491}
1492
1493static int tegra20_audio_sync_clk_set_parent(struct clk_hw *hw, u8 index)
1494{
1495 struct clk_tegra *c = to_clk_tegra(hw);
1496 u32 val;
1497
1498 val = clk_readl(c->reg);
1499 val &= ~0xf;
1500 val |= index;
1501
1502 clk_writel(val, c->reg);
1503
1504 return 0;
1505}
1506
1507struct clk_ops tegra_audio_sync_clk_ops = {
1508 .is_enabled = tegra20_audio_sync_clk_is_enabled,
1509 .enable = tegra20_audio_sync_clk_enable,
1510 .disable = tegra20_audio_sync_clk_disable,
1511 .set_parent = tegra20_audio_sync_clk_set_parent,
1512 .get_parent = tegra20_audio_sync_clk_get_parent,
1513};
1514
1515/* cdev1 and cdev2 (dap_mclk1 and dap_mclk2) ops */
1516
1517static int tegra20_cdev_clk_is_enabled(struct clk_hw *hw)
1518{
1519 struct clk_tegra *c = to_clk_tegra(hw);
1520 /* We could un-tristate the cdev1 or cdev2 pingroup here; this is
1521 * currently done in the pinmux code. */
1522 c->state = ON;
1523
1524 BUG_ON(!c->u.periph.clk_num);
1525
1526 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1527 PERIPH_CLK_TO_ENB_BIT(c)))
1528 c->state = OFF;
1529 return c->state;
1530}
1531
1532static int tegra20_cdev_clk_enable(struct clk_hw *hw)
1533{
1534 struct clk_tegra *c = to_clk_tegra(hw);
1535 BUG_ON(!c->u.periph.clk_num);
1536
1537 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1538 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
1539 return 0;
1540}
1541
1542static void tegra20_cdev_clk_disable(struct clk_hw *hw)
1543{
1544 struct clk_tegra *c = to_clk_tegra(hw);
1545 BUG_ON(!c->u.periph.clk_num);
1546
1547 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1548 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1549}
1550
1551static unsigned long tegra20_cdev_recalc_rate(struct clk_hw *hw,
1552 unsigned long prate)
1553{
1554 return to_clk_tegra(hw)->fixed_rate;
1555}
1556
1557struct clk_ops tegra_cdev_clk_ops = {
1558 .is_enabled = tegra20_cdev_clk_is_enabled,
1559 .enable = tegra20_cdev_clk_enable,
1560 .disable = tegra20_cdev_clk_disable,
1561 .recalc_rate = tegra20_cdev_recalc_rate,
1562};
1563
1564/* Tegra20 CPU clock and reset control functions */
1565static void tegra20_wait_cpu_in_reset(u32 cpu)
1566{
1567 unsigned int reg;
1568
1569 do {
1570 reg = readl(reg_clk_base +
1571 TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
1572 cpu_relax();
1573 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
1574
1575 return;
1576}
1577
1578static void tegra20_put_cpu_in_reset(u32 cpu)
1579{
1580 writel(CPU_RESET(cpu),
1581 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
1582 dmb();
1583}
1584
1585static void tegra20_cpu_out_of_reset(u32 cpu)
1586{
1587 writel(CPU_RESET(cpu),
1588 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
1589 wmb();
1590}
1591
1592static void tegra20_enable_cpu_clock(u32 cpu)
1593{
1594 unsigned int reg;
1595
1596 reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1597 writel(reg & ~CPU_CLOCK(cpu),
1598 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1599 barrier();
1600 reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1601}
1602
1603static void tegra20_disable_cpu_clock(u32 cpu)
1604{
1605 unsigned int reg;
1606
1607 reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1608 writel(reg | CPU_CLOCK(cpu),
1609 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1610}
1611
1612static struct tegra_cpu_car_ops tegra20_cpu_car_ops = {
1613 .wait_for_reset = tegra20_wait_cpu_in_reset,
1614 .put_in_reset = tegra20_put_cpu_in_reset,
1615 .out_of_reset = tegra20_cpu_out_of_reset,
1616 .enable_clock = tegra20_enable_cpu_clock,
1617 .disable_clock = tegra20_disable_cpu_clock,
1618};
1619
1620void __init tegra20_cpu_car_ops_init(void)
1621{
1622 tegra_cpu_car_ops = &tegra20_cpu_car_ops;
1623}
diff --git a/arch/arm/mach-tegra/tegra20_clocks.h b/arch/arm/mach-tegra/tegra20_clocks.h
deleted file mode 100644
index 8bfd31bcc490..000000000000
--- a/arch/arm/mach-tegra/tegra20_clocks.h
+++ /dev/null
@@ -1,42 +0,0 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef __MACH_TEGRA20_CLOCK_H
18#define __MACH_TEGRA20_CLOCK_H
19
20extern struct clk_ops tegra_clk_32k_ops;
21extern struct clk_ops tegra_pll_ops;
22extern struct clk_ops tegra_clk_m_ops;
23extern struct clk_ops tegra_pll_div_ops;
24extern struct clk_ops tegra_pllx_ops;
25extern struct clk_ops tegra_plle_ops;
26extern struct clk_ops tegra_clk_double_ops;
27extern struct clk_ops tegra_cdev_clk_ops;
28extern struct clk_ops tegra_audio_sync_clk_ops;
29extern struct clk_ops tegra_super_ops;
30extern struct clk_ops tegra_cpu_ops;
31extern struct clk_ops tegra_twd_ops;
32extern struct clk_ops tegra_cop_ops;
33extern struct clk_ops tegra_bus_ops;
34extern struct clk_ops tegra_blink_clk_ops;
35extern struct clk_ops tegra_emc_clk_ops;
36extern struct clk_ops tegra_periph_clk_ops;
37extern struct clk_ops tegra_clk_shared_bus_ops;
38
39void tegra2_periph_clk_reset(struct clk_hw *hw, bool assert);
40void tegra2_cop_clk_reset(struct clk_hw *hw, bool assert);
41
42#endif
diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
deleted file mode 100644
index a23a0734e352..000000000000
--- a/arch/arm/mach-tegra/tegra20_clocks_data.c
+++ /dev/null
@@ -1,1143 +0,0 @@
1/*
2 * arch/arm/mach-tegra/tegra2_clocks.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved.
6 *
7 * Author:
8 * Colin Cross <ccross@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#include <linux/clk-private.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/list.h>
25#include <linux/spinlock.h>
26#include <linux/delay.h>
27#include <linux/io.h>
28#include <linux/clk.h>
29
30#include "clock.h"
31#include "fuse.h"
32#include "tegra2_emc.h"
33#include "tegra20_clocks.h"
34#include "tegra_cpu_car.h"
35
36/* Clock definitions */
37
38#define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags, \
39 _parent_names, _parents, _parent) \
40 static struct clk tegra_##_name = { \
41 .hw = &tegra_##_name##_hw.hw, \
42 .name = #_name, \
43 .rate = _rate, \
44 .ops = _ops, \
45 .flags = _flags, \
46 .parent_names = _parent_names, \
47 .parents = _parents, \
48 .num_parents = ARRAY_SIZE(_parent_names), \
49 .parent = _parent, \
50 };
51
52static struct clk tegra_clk_32k;
53static struct clk_tegra tegra_clk_32k_hw = {
54 .hw = {
55 .clk = &tegra_clk_32k,
56 },
57 .fixed_rate = 32768,
58};
59
60static struct clk tegra_clk_32k = {
61 .name = "clk_32k",
62 .rate = 32768,
63 .ops = &tegra_clk_32k_ops,
64 .hw = &tegra_clk_32k_hw.hw,
65 .flags = CLK_IS_ROOT,
66};
67
68static struct clk tegra_clk_m;
69static struct clk_tegra tegra_clk_m_hw = {
70 .hw = {
71 .clk = &tegra_clk_m,
72 },
73 .flags = ENABLE_ON_INIT,
74 .reg = 0x1fc,
75 .reg_shift = 28,
76 .max_rate = 26000000,
77 .fixed_rate = 0,
78};
79
80static struct clk tegra_clk_m = {
81 .name = "clk_m",
82 .ops = &tegra_clk_m_ops,
83 .hw = &tegra_clk_m_hw.hw,
84 .flags = CLK_IS_ROOT,
85};
86
87#define DEFINE_PLL(_name, _flags, _reg, _max_rate, _input_min, \
88 _input_max, _cf_min, _cf_max, _vco_min, \
89 _vco_max, _freq_table, _lock_delay, _ops, \
90 _fixed_rate, _parent) \
91 static const char *tegra_##_name##_parent_names[] = { \
92 #_parent, \
93 }; \
94 static struct clk *tegra_##_name##_parents[] = { \
95 &tegra_##_parent, \
96 }; \
97 static struct clk tegra_##_name; \
98 static struct clk_tegra tegra_##_name##_hw = { \
99 .hw = { \
100 .clk = &tegra_##_name, \
101 }, \
102 .flags = _flags, \
103 .reg = _reg, \
104 .max_rate = _max_rate, \
105 .u.pll = { \
106 .input_min = _input_min, \
107 .input_max = _input_max, \
108 .cf_min = _cf_min, \
109 .cf_max = _cf_max, \
110 .vco_min = _vco_min, \
111 .vco_max = _vco_max, \
112 .freq_table = _freq_table, \
113 .lock_delay = _lock_delay, \
114 .fixed_rate = _fixed_rate, \
115 }, \
116 }; \
117 static struct clk tegra_##_name = { \
118 .name = #_name, \
119 .ops = &_ops, \
120 .hw = &tegra_##_name##_hw.hw, \
121 .parent = &tegra_##_parent, \
122 .parent_names = tegra_##_name##_parent_names, \
123 .parents = tegra_##_name##_parents, \
124 .num_parents = 1, \
125 };
126
127#define DEFINE_PLL_OUT(_name, _flags, _reg, _reg_shift, \
128 _max_rate, _ops, _parent, _clk_flags) \
129 static const char *tegra_##_name##_parent_names[] = { \
130 #_parent, \
131 }; \
132 static struct clk *tegra_##_name##_parents[] = { \
133 &tegra_##_parent, \
134 }; \
135 static struct clk tegra_##_name; \
136 static struct clk_tegra tegra_##_name##_hw = { \
137 .hw = { \
138 .clk = &tegra_##_name, \
139 }, \
140 .flags = _flags, \
141 .reg = _reg, \
142 .max_rate = _max_rate, \
143 .reg_shift = _reg_shift, \
144 }; \
145 static struct clk tegra_##_name = { \
146 .name = #_name, \
147 .ops = &tegra_pll_div_ops, \
148 .hw = &tegra_##_name##_hw.hw, \
149 .parent = &tegra_##_parent, \
150 .parent_names = tegra_##_name##_parent_names, \
151 .parents = tegra_##_name##_parents, \
152 .num_parents = 1, \
153 .flags = _clk_flags, \
154 };
155
156
157static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
158 {32768, 12000000, 366, 1, 1, 0},
159 {32768, 13000000, 397, 1, 1, 0},
160 {32768, 19200000, 586, 1, 1, 0},
161 {32768, 26000000, 793, 1, 1, 0},
162 {0, 0, 0, 0, 0, 0},
163};
164
165DEFINE_PLL(pll_s, PLL_ALT_MISC_REG, 0xf0, 26000000, 32768, 32768, 0,
166 0, 12000000, 26000000, tegra_pll_s_freq_table, 300,
167 tegra_pll_ops, 0, clk_32k);
168
169static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
170 { 12000000, 600000000, 600, 12, 1, 8 },
171 { 13000000, 600000000, 600, 13, 1, 8 },
172 { 19200000, 600000000, 500, 16, 1, 6 },
173 { 26000000, 600000000, 600, 26, 1, 8 },
174 { 0, 0, 0, 0, 0, 0 },
175};
176
177DEFINE_PLL(pll_c, PLL_HAS_CPCON, 0x80, 600000000, 2000000, 31000000, 1000000,
178 6000000, 20000000, 1400000000, tegra_pll_c_freq_table, 300,
179 tegra_pll_ops, 0, clk_m);
180
181DEFINE_PLL_OUT(pll_c_out1, DIV_U71, 0x84, 0, 600000000,
182 tegra_pll_div_ops, pll_c, 0);
183
184static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
185 { 12000000, 666000000, 666, 12, 1, 8},
186 { 13000000, 666000000, 666, 13, 1, 8},
187 { 19200000, 666000000, 555, 16, 1, 8},
188 { 26000000, 666000000, 666, 26, 1, 8},
189 { 12000000, 600000000, 600, 12, 1, 8},
190 { 13000000, 600000000, 600, 13, 1, 8},
191 { 19200000, 600000000, 375, 12, 1, 6},
192 { 26000000, 600000000, 600, 26, 1, 8},
193 { 0, 0, 0, 0, 0, 0 },
194};
195
196DEFINE_PLL(pll_m, PLL_HAS_CPCON, 0x90, 800000000, 2000000, 31000000, 1000000,
197 6000000, 20000000, 1200000000, tegra_pll_m_freq_table, 300,
198 tegra_pll_ops, 0, clk_m);
199
200DEFINE_PLL_OUT(pll_m_out1, DIV_U71, 0x94, 0, 600000000,
201 tegra_pll_div_ops, pll_m, 0);
202
203static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
204 { 12000000, 216000000, 432, 12, 2, 8},
205 { 13000000, 216000000, 432, 13, 2, 8},
206 { 19200000, 216000000, 90, 4, 2, 1},
207 { 26000000, 216000000, 432, 26, 2, 8},
208 { 12000000, 432000000, 432, 12, 1, 8},
209 { 13000000, 432000000, 432, 13, 1, 8},
210 { 19200000, 432000000, 90, 4, 1, 1},
211 { 26000000, 432000000, 432, 26, 1, 8},
212 { 0, 0, 0, 0, 0, 0 },
213};
214
215
216DEFINE_PLL(pll_p, ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, 0xa0, 432000000,
217 2000000, 31000000, 1000000, 6000000, 20000000, 1400000000,
218 tegra_pll_p_freq_table, 300, tegra_pll_ops, 216000000, clk_m);
219
220DEFINE_PLL_OUT(pll_p_out1, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4, 0,
221 432000000, tegra_pll_div_ops, pll_p, 0);
222DEFINE_PLL_OUT(pll_p_out2, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4, 16,
223 432000000, tegra_pll_div_ops, pll_p, 0);
224DEFINE_PLL_OUT(pll_p_out3, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8, 0,
225 432000000, tegra_pll_div_ops, pll_p, 0);
226DEFINE_PLL_OUT(pll_p_out4, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8, 16,
227 432000000, tegra_pll_div_ops, pll_p, 0);
228
229static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
230 { 28800000, 56448000, 49, 25, 1, 1},
231 { 28800000, 73728000, 64, 25, 1, 1},
232 { 28800000, 24000000, 5, 6, 1, 1},
233 { 0, 0, 0, 0, 0, 0 },
234};
235
236DEFINE_PLL(pll_a, PLL_HAS_CPCON, 0xb0, 73728000, 2000000, 31000000, 1000000,
237 6000000, 20000000, 1400000000, tegra_pll_a_freq_table, 300,
238 tegra_pll_ops, 0, pll_p_out1);
239
240DEFINE_PLL_OUT(pll_a_out0, DIV_U71, 0xb4, 0, 73728000,
241 tegra_pll_div_ops, pll_a, 0);
242
243static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
244 { 12000000, 216000000, 216, 12, 1, 4},
245 { 13000000, 216000000, 216, 13, 1, 4},
246 { 19200000, 216000000, 135, 12, 1, 3},
247 { 26000000, 216000000, 216, 26, 1, 4},
248
249 { 12000000, 297000000, 99, 4, 1, 4 },
250 { 12000000, 339000000, 113, 4, 1, 4 },
251
252 { 12000000, 594000000, 594, 12, 1, 8},
253 { 13000000, 594000000, 594, 13, 1, 8},
254 { 19200000, 594000000, 495, 16, 1, 8},
255 { 26000000, 594000000, 594, 26, 1, 8},
256
257 { 12000000, 616000000, 616, 12, 1, 8},
258
259 { 12000000, 1000000000, 1000, 12, 1, 12},
260 { 13000000, 1000000000, 1000, 13, 1, 12},
261 { 19200000, 1000000000, 625, 12, 1, 8},
262 { 26000000, 1000000000, 1000, 26, 1, 12},
263
264 { 0, 0, 0, 0, 0, 0 },
265};
266
267DEFINE_PLL(pll_d, PLL_HAS_CPCON | PLLD, 0xd0, 1000000000, 2000000, 40000000,
268 1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table,
269 1000, tegra_pll_ops, 0, clk_m);
270
271DEFINE_PLL_OUT(pll_d_out0, DIV_2 | PLLD, 0, 0, 500000000,
272 tegra_pll_div_ops, pll_d, CLK_SET_RATE_PARENT);
273
274static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
275 { 12000000, 480000000, 960, 12, 2, 0},
276 { 13000000, 480000000, 960, 13, 2, 0},
277 { 19200000, 480000000, 200, 4, 2, 0},
278 { 26000000, 480000000, 960, 26, 2, 0},
279 { 0, 0, 0, 0, 0, 0 },
280};
281
282DEFINE_PLL(pll_u, PLLU, 0xc0, 480000000, 2000000, 40000000, 1000000, 6000000,
283 48000000, 960000000, tegra_pll_u_freq_table, 1000,
284 tegra_pll_ops, 0, clk_m);
285
286static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
287 /* 1 GHz */
288 { 12000000, 1000000000, 1000, 12, 1, 12},
289 { 13000000, 1000000000, 1000, 13, 1, 12},
290 { 19200000, 1000000000, 625, 12, 1, 8},
291 { 26000000, 1000000000, 1000, 26, 1, 12},
292
293 /* 912 MHz */
294 { 12000000, 912000000, 912, 12, 1, 12},
295 { 13000000, 912000000, 912, 13, 1, 12},
296 { 19200000, 912000000, 760, 16, 1, 8},
297 { 26000000, 912000000, 912, 26, 1, 12},
298
299 /* 816 MHz */
300 { 12000000, 816000000, 816, 12, 1, 12},
301 { 13000000, 816000000, 816, 13, 1, 12},
302 { 19200000, 816000000, 680, 16, 1, 8},
303 { 26000000, 816000000, 816, 26, 1, 12},
304
305 /* 760 MHz */
306 { 12000000, 760000000, 760, 12, 1, 12},
307 { 13000000, 760000000, 760, 13, 1, 12},
308 { 19200000, 760000000, 950, 24, 1, 8},
309 { 26000000, 760000000, 760, 26, 1, 12},
310
311 /* 750 MHz */
312 { 12000000, 750000000, 750, 12, 1, 12},
313 { 13000000, 750000000, 750, 13, 1, 12},
314 { 19200000, 750000000, 625, 16, 1, 8},
315 { 26000000, 750000000, 750, 26, 1, 12},
316
317 /* 608 MHz */
318 { 12000000, 608000000, 608, 12, 1, 12},
319 { 13000000, 608000000, 608, 13, 1, 12},
320 { 19200000, 608000000, 380, 12, 1, 8},
321 { 26000000, 608000000, 608, 26, 1, 12},
322
323 /* 456 MHz */
324 { 12000000, 456000000, 456, 12, 1, 12},
325 { 13000000, 456000000, 456, 13, 1, 12},
326 { 19200000, 456000000, 380, 16, 1, 8},
327 { 26000000, 456000000, 456, 26, 1, 12},
328
329 /* 312 MHz */
330 { 12000000, 312000000, 312, 12, 1, 12},
331 { 13000000, 312000000, 312, 13, 1, 12},
332 { 19200000, 312000000, 260, 16, 1, 8},
333 { 26000000, 312000000, 312, 26, 1, 12},
334
335 { 0, 0, 0, 0, 0, 0 },
336};
337
338DEFINE_PLL(pll_x, PLL_HAS_CPCON | PLL_ALT_MISC_REG, 0xe0, 1000000000, 2000000,
339 31000000, 1000000, 6000000, 20000000, 1200000000,
340 tegra_pll_x_freq_table, 300, tegra_pllx_ops, 0, clk_m);
341
342static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
343 { 12000000, 100000000, 200, 24, 1, 0 },
344 { 0, 0, 0, 0, 0, 0 },
345};
346
347DEFINE_PLL(pll_e, PLL_ALT_MISC_REG, 0xe8, 100000000, 12000000, 12000000, 0, 0,
348 0, 0, tegra_pll_e_freq_table, 0, tegra_plle_ops, 0, clk_m);
349
350static const char *tegra_common_parent_names[] = {
351 "clk_m",
352};
353
354static struct clk *tegra_common_parents[] = {
355 &tegra_clk_m,
356};
357
358static struct clk tegra_clk_d;
359static struct clk_tegra tegra_clk_d_hw = {
360 .hw = {
361 .clk = &tegra_clk_d,
362 },
363 .flags = PERIPH_NO_RESET,
364 .reg = 0x34,
365 .reg_shift = 12,
366 .max_rate = 52000000,
367 .u.periph = {
368 .clk_num = 90,
369 },
370};
371
372static struct clk tegra_clk_d = {
373 .name = "clk_d",
374 .hw = &tegra_clk_d_hw.hw,
375 .ops = &tegra_clk_double_ops,
376 .parent = &tegra_clk_m,
377 .parent_names = tegra_common_parent_names,
378 .parents = tegra_common_parents,
379 .num_parents = ARRAY_SIZE(tegra_common_parent_names),
380};
381
382static struct clk tegra_cdev1;
383static struct clk_tegra tegra_cdev1_hw = {
384 .hw = {
385 .clk = &tegra_cdev1,
386 },
387 .fixed_rate = 26000000,
388 .u.periph = {
389 .clk_num = 94,
390 },
391};
392static struct clk tegra_cdev1 = {
393 .name = "cdev1",
394 .hw = &tegra_cdev1_hw.hw,
395 .ops = &tegra_cdev_clk_ops,
396 .flags = CLK_IS_ROOT,
397};
398
399/* dap_mclk2, belongs to the cdev2 pingroup. */
400static struct clk tegra_cdev2;
401static struct clk_tegra tegra_cdev2_hw = {
402 .hw = {
403 .clk = &tegra_cdev2,
404 },
405 .fixed_rate = 26000000,
406 .u.periph = {
407 .clk_num = 93,
408 },
409};
410static struct clk tegra_cdev2 = {
411 .name = "cdev2",
412 .hw = &tegra_cdev2_hw.hw,
413 .ops = &tegra_cdev_clk_ops,
414 .flags = CLK_IS_ROOT,
415};
416
417/* initialized before peripheral clocks */
418static struct clk_mux_sel mux_audio_sync_clk[8+1];
419static const struct audio_sources {
420 const char *name;
421 int value;
422} mux_audio_sync_clk_sources[] = {
423 { .name = "spdif_in", .value = 0 },
424 { .name = "i2s1", .value = 1 },
425 { .name = "i2s2", .value = 2 },
426 { .name = "pll_a_out0", .value = 4 },
427#if 0 /* FIXME: not implemented */
428 { .name = "ac97", .value = 3 },
429 { .name = "ext_audio_clk2", .value = 5 },
430 { .name = "ext_audio_clk1", .value = 6 },
431 { .name = "ext_vimclk", .value = 7 },
432#endif
433 { NULL, 0 }
434};
435
436static const char *audio_parent_names[] = {
437 "spdif_in",
438 "i2s1",
439 "i2s2",
440 "dummy",
441 "pll_a_out0",
442 "dummy",
443 "dummy",
444 "dummy",
445};
446
447static struct clk *audio_parents[] = {
448 NULL,
449 NULL,
450 NULL,
451 NULL,
452 NULL,
453 NULL,
454 NULL,
455 NULL,
456};
457
458static struct clk tegra_audio;
459static struct clk_tegra tegra_audio_hw = {
460 .hw = {
461 .clk = &tegra_audio,
462 },
463 .reg = 0x38,
464 .max_rate = 73728000,
465};
466DEFINE_CLK_TEGRA(audio, 0, &tegra_audio_sync_clk_ops, 0, audio_parent_names,
467 audio_parents, NULL);
468
469static const char *audio_2x_parent_names[] = {
470 "audio",
471};
472
473static struct clk *audio_2x_parents[] = {
474 &tegra_audio,
475};
476
477static struct clk tegra_audio_2x;
478static struct clk_tegra tegra_audio_2x_hw = {
479 .hw = {
480 .clk = &tegra_audio_2x,
481 },
482 .flags = PERIPH_NO_RESET,
483 .max_rate = 48000000,
484 .reg = 0x34,
485 .reg_shift = 8,
486 .u.periph = {
487 .clk_num = 89,
488 },
489};
490DEFINE_CLK_TEGRA(audio_2x, 0, &tegra_clk_double_ops, 0, audio_2x_parent_names,
491 audio_2x_parents, &tegra_audio);
492
493static struct clk_lookup tegra_audio_clk_lookups[] = {
494 { .con_id = "audio", .clk = &tegra_audio },
495 { .con_id = "audio_2x", .clk = &tegra_audio_2x }
496};
497
498/* This is called after peripheral clocks are initialized, as the
499 * audio_sync clock depends on some of the peripheral clocks.
500 */
501
502static void init_audio_sync_clock_mux(void)
503{
504 int i;
505 struct clk_mux_sel *sel = mux_audio_sync_clk;
506 const struct audio_sources *src = mux_audio_sync_clk_sources;
507 struct clk_lookup *lookup;
508
509 for (i = 0; src->name; i++, sel++, src++) {
510 sel->input = tegra_get_clock_by_name(src->name);
511 if (!sel->input)
512 pr_err("%s: could not find clk %s\n", __func__,
513 src->name);
514 audio_parents[src->value] = sel->input;
515 sel->value = src->value;
516 }
517
518 lookup = tegra_audio_clk_lookups;
519 for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
520 struct clk *c = lookup->clk;
521 struct clk_tegra *clk = to_clk_tegra(c->hw);
522 __clk_init(NULL, c);
523 INIT_LIST_HEAD(&clk->shared_bus_list);
524 clk->lookup.con_id = lookup->con_id;
525 clk->lookup.clk = c;
526 clkdev_add(&clk->lookup);
527 tegra_clk_add(c);
528 }
529}
530
531static const char *mux_cclk[] = {
532 "clk_m",
533 "pll_c",
534 "clk_32k",
535 "pll_m",
536 "pll_p",
537 "pll_p_out4",
538 "pll_p_out3",
539 "clk_d",
540 "pll_x",
541};
542
543
544static struct clk *mux_cclk_p[] = {
545 &tegra_clk_m,
546 &tegra_pll_c,
547 &tegra_clk_32k,
548 &tegra_pll_m,
549 &tegra_pll_p,
550 &tegra_pll_p_out4,
551 &tegra_pll_p_out3,
552 &tegra_clk_d,
553 &tegra_pll_x,
554};
555
556static const char *mux_sclk[] = {
557 "clk_m",
558 "pll_c_out1",
559 "pll_p_out4",
560 "pllp_p_out3",
561 "pll_p_out2",
562 "clk_d",
563 "clk_32k",
564 "pll_m_out1",
565};
566
567static struct clk *mux_sclk_p[] = {
568 &tegra_clk_m,
569 &tegra_pll_c_out1,
570 &tegra_pll_p_out4,
571 &tegra_pll_p_out3,
572 &tegra_pll_p_out2,
573 &tegra_clk_d,
574 &tegra_clk_32k,
575 &tegra_pll_m_out1,
576};
577
578static struct clk tegra_cclk;
579static struct clk_tegra tegra_cclk_hw = {
580 .hw = {
581 .clk = &tegra_cclk,
582 },
583 .reg = 0x20,
584 .max_rate = 1000000000,
585};
586DEFINE_CLK_TEGRA(cclk, 0, &tegra_super_ops, 0, mux_cclk,
587 mux_cclk_p, NULL);
588
589static const char *mux_twd[] = {
590 "cclk",
591};
592
593static struct clk *mux_twd_p[] = {
594 &tegra_cclk,
595};
596
597static struct clk tegra_clk_twd;
598static struct clk_tegra tegra_clk_twd_hw = {
599 .hw = {
600 .clk = &tegra_clk_twd,
601 },
602 .max_rate = 1000000000,
603 .mul = 1,
604 .div = 4,
605};
606
607static struct clk tegra_clk_twd = {
608 .name = "twd",
609 .ops = &tegra_twd_ops,
610 .hw = &tegra_clk_twd_hw.hw,
611 .parent = &tegra_cclk,
612 .parent_names = mux_twd,
613 .parents = mux_twd_p,
614 .num_parents = ARRAY_SIZE(mux_twd),
615};
616
617static struct clk tegra_sclk;
618static struct clk_tegra tegra_sclk_hw = {
619 .hw = {
620 .clk = &tegra_sclk,
621 },
622 .reg = 0x28,
623 .max_rate = 240000000,
624 .min_rate = 120000000,
625};
626DEFINE_CLK_TEGRA(sclk, 0, &tegra_super_ops, 0, mux_sclk,
627 mux_sclk_p, NULL);
628
629static const char *tegra_cop_parent_names[] = {
630 "tegra_sclk",
631};
632
633static struct clk *tegra_cop_parents[] = {
634 &tegra_sclk,
635};
636
637static struct clk tegra_cop;
638static struct clk_tegra tegra_cop_hw = {
639 .hw = {
640 .clk = &tegra_cop,
641 },
642 .max_rate = 240000000,
643 .reset = &tegra2_cop_clk_reset,
644};
645DEFINE_CLK_TEGRA(cop, 0, &tegra_cop_ops, CLK_SET_RATE_PARENT,
646 tegra_cop_parent_names, tegra_cop_parents, &tegra_sclk);
647
648static const char *tegra_hclk_parent_names[] = {
649 "tegra_sclk",
650};
651
652static struct clk *tegra_hclk_parents[] = {
653 &tegra_sclk,
654};
655
656static struct clk tegra_hclk;
657static struct clk_tegra tegra_hclk_hw = {
658 .hw = {
659 .clk = &tegra_hclk,
660 },
661 .flags = DIV_BUS,
662 .reg = 0x30,
663 .reg_shift = 4,
664 .max_rate = 240000000,
665};
666DEFINE_CLK_TEGRA(hclk, 0, &tegra_bus_ops, 0, tegra_hclk_parent_names,
667 tegra_hclk_parents, &tegra_sclk);
668
669static const char *tegra_pclk_parent_names[] = {
670 "tegra_hclk",
671};
672
673static struct clk *tegra_pclk_parents[] = {
674 &tegra_hclk,
675};
676
677static struct clk tegra_pclk;
678static struct clk_tegra tegra_pclk_hw = {
679 .hw = {
680 .clk = &tegra_pclk,
681 },
682 .flags = DIV_BUS,
683 .reg = 0x30,
684 .reg_shift = 0,
685 .max_rate = 120000000,
686};
687DEFINE_CLK_TEGRA(pclk, 0, &tegra_bus_ops, 0, tegra_pclk_parent_names,
688 tegra_pclk_parents, &tegra_hclk);
689
690static const char *tegra_blink_parent_names[] = {
691 "clk_32k",
692};
693
694static struct clk *tegra_blink_parents[] = {
695 &tegra_clk_32k,
696};
697
698static struct clk tegra_blink;
699static struct clk_tegra tegra_blink_hw = {
700 .hw = {
701 .clk = &tegra_blink,
702 },
703 .reg = 0x40,
704 .max_rate = 32768,
705};
706DEFINE_CLK_TEGRA(blink, 0, &tegra_blink_clk_ops, 0, tegra_blink_parent_names,
707 tegra_blink_parents, &tegra_clk_32k);
708
709static const char *mux_pllm_pllc_pllp_plla[] = {
710 "pll_m",
711 "pll_c",
712 "pll_p",
713 "pll_a_out0",
714};
715
716static struct clk *mux_pllm_pllc_pllp_plla_p[] = {
717 &tegra_pll_m,
718 &tegra_pll_c,
719 &tegra_pll_p,
720 &tegra_pll_a_out0,
721};
722
723static const char *mux_pllm_pllc_pllp_clkm[] = {
724 "pll_m",
725 "pll_c",
726 "pll_p",
727 "clk_m",
728};
729
730static struct clk *mux_pllm_pllc_pllp_clkm_p[] = {
731 &tegra_pll_m,
732 &tegra_pll_c,
733 &tegra_pll_p,
734 &tegra_clk_m,
735};
736
737static const char *mux_pllp_pllc_pllm_clkm[] = {
738 "pll_p",
739 "pll_c",
740 "pll_m",
741 "clk_m",
742};
743
744static struct clk *mux_pllp_pllc_pllm_clkm_p[] = {
745 &tegra_pll_p,
746 &tegra_pll_c,
747 &tegra_pll_m,
748 &tegra_clk_m,
749};
750
751static const char *mux_pllaout0_audio2x_pllp_clkm[] = {
752 "pll_a_out0",
753 "audio_2x",
754 "pll_p",
755 "clk_m",
756};
757
758static struct clk *mux_pllaout0_audio2x_pllp_clkm_p[] = {
759 &tegra_pll_a_out0,
760 &tegra_audio_2x,
761 &tegra_pll_p,
762 &tegra_clk_m,
763};
764
765static const char *mux_pllp_plld_pllc_clkm[] = {
766 "pllp",
767 "pll_d_out0",
768 "pll_c",
769 "clk_m",
770};
771
772static struct clk *mux_pllp_plld_pllc_clkm_p[] = {
773 &tegra_pll_p,
774 &tegra_pll_d_out0,
775 &tegra_pll_c,
776 &tegra_clk_m,
777};
778
779static const char *mux_pllp_pllc_audio_clkm_clk32[] = {
780 "pll_p",
781 "pll_c",
782 "audio",
783 "clk_m",
784 "clk_32k",
785};
786
787static struct clk *mux_pllp_pllc_audio_clkm_clk32_p[] = {
788 &tegra_pll_p,
789 &tegra_pll_c,
790 &tegra_audio,
791 &tegra_clk_m,
792 &tegra_clk_32k,
793};
794
795static const char *mux_pllp_pllc_pllm[] = {
796 "pll_p",
797 "pll_c",
798 "pll_m"
799};
800
801static struct clk *mux_pllp_pllc_pllm_p[] = {
802 &tegra_pll_p,
803 &tegra_pll_c,
804 &tegra_pll_m,
805};
806
807static const char *mux_clk_m[] = {
808 "clk_m",
809};
810
811static struct clk *mux_clk_m_p[] = {
812 &tegra_clk_m,
813};
814
815static const char *mux_pllp_out3[] = {
816 "pll_p_out3",
817};
818
819static struct clk *mux_pllp_out3_p[] = {
820 &tegra_pll_p_out3,
821};
822
823static const char *mux_plld[] = {
824 "pll_d",
825};
826
827static struct clk *mux_plld_p[] = {
828 &tegra_pll_d,
829};
830
831static const char *mux_clk_32k[] = {
832 "clk_32k",
833};
834
835static struct clk *mux_clk_32k_p[] = {
836 &tegra_clk_32k,
837};
838
839static const char *mux_pclk[] = {
840 "pclk",
841};
842
843static struct clk *mux_pclk_p[] = {
844 &tegra_pclk,
845};
846
847static struct clk tegra_emc;
848static struct clk_tegra tegra_emc_hw = {
849 .hw = {
850 .clk = &tegra_emc,
851 },
852 .reg = 0x19c,
853 .max_rate = 800000000,
854 .flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
855 .reset = &tegra2_periph_clk_reset,
856 .u.periph = {
857 .clk_num = 57,
858 },
859};
860DEFINE_CLK_TEGRA(emc, 0, &tegra_emc_clk_ops, 0, mux_pllm_pllc_pllp_clkm,
861 mux_pllm_pllc_pllp_clkm_p, NULL);
862
863#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, \
864 _max, _inputs, _flags) \
865 static struct clk tegra_##_name; \
866 static struct clk_tegra tegra_##_name##_hw = { \
867 .hw = { \
868 .clk = &tegra_##_name, \
869 }, \
870 .lookup = { \
871 .dev_id = _dev, \
872 .con_id = _con, \
873 }, \
874 .reg = _reg, \
875 .flags = _flags, \
876 .max_rate = _max, \
877 .u.periph = { \
878 .clk_num = _clk_num, \
879 }, \
880 .reset = tegra2_periph_clk_reset, \
881 }; \
882 static struct clk tegra_##_name = { \
883 .name = #_name, \
884 .ops = &tegra_periph_clk_ops, \
885 .hw = &tegra_##_name##_hw.hw, \
886 .parent_names = _inputs, \
887 .parents = _inputs##_p, \
888 .num_parents = ARRAY_SIZE(_inputs), \
889 };
890
891PERIPH_CLK(apbdma, "tegra-apbdma", NULL, 34, 0, 108000000, mux_pclk, 0);
892PERIPH_CLK(rtc, "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET);
893PERIPH_CLK(timer, "timer", NULL, 5, 0, 26000000, mux_clk_m, 0);
894PERIPH_CLK(i2s1, "tegra20-i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71);
895PERIPH_CLK(i2s2, "tegra20-i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71);
896PERIPH_CLK(spdif_out, "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71);
897PERIPH_CLK(spdif_in, "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71);
898PERIPH_CLK(pwm, "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71 | MUX_PWM);
899PERIPH_CLK(spi, "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
900PERIPH_CLK(xio, "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
901PERIPH_CLK(twc, "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
902PERIPH_CLK(sbc1, "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
903PERIPH_CLK(sbc2, "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
904PERIPH_CLK(sbc3, "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
905PERIPH_CLK(sbc4, "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
906PERIPH_CLK(ide, "ide", NULL, 25, 0x144, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */
907PERIPH_CLK(ndflash, "tegra_nand", NULL, 13, 0x160, 164000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
908PERIPH_CLK(vfir, "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
909PERIPH_CLK(sdmmc1, "sdhci-tegra.0", NULL, 14, 0x150, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
910PERIPH_CLK(sdmmc2, "sdhci-tegra.1", NULL, 9, 0x154, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
911PERIPH_CLK(sdmmc3, "sdhci-tegra.2", NULL, 69, 0x1bc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
912PERIPH_CLK(sdmmc4, "sdhci-tegra.3", NULL, 15, 0x164, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
913PERIPH_CLK(vcp, "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0);
914PERIPH_CLK(bsea, "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0);
915PERIPH_CLK(bsev, "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0);
916PERIPH_CLK(vde, "tegra-avp", "vde", 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage and process_id */
917PERIPH_CLK(csite, "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* max rate ??? */
918/* FIXME: what is la? */
919PERIPH_CLK(la, "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
920PERIPH_CLK(owr, "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
921PERIPH_CLK(nor, "nor", NULL, 42, 0x1d0, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */
922PERIPH_CLK(mipi, "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
923PERIPH_CLK(i2c1, "tegra-i2c.0", "div-clk", 12, 0x124, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
924PERIPH_CLK(i2c2, "tegra-i2c.1", "div-clk", 54, 0x198, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
925PERIPH_CLK(i2c3, "tegra-i2c.2", "div-clk", 67, 0x1b8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
926PERIPH_CLK(dvc, "tegra-i2c.3", "div-clk", 47, 0x128, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
927PERIPH_CLK(uarta, "tegra-uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
928PERIPH_CLK(uartb, "tegra-uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
929PERIPH_CLK(uartc, "tegra-uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
930PERIPH_CLK(uartd, "tegra-uart.3", NULL, 65, 0x1c0, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
931PERIPH_CLK(uarte, "tegra-uart.4", NULL, 66, 0x1c4, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
932PERIPH_CLK(3d, "3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET); /* scales with voltage and process_id */
933PERIPH_CLK(2d, "2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
934PERIPH_CLK(vi, "tegra_camera", "vi", 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
935PERIPH_CLK(vi_sensor, "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET); /* scales with voltage and process_id */
936PERIPH_CLK(epp, "epp", NULL, 19, 0x16c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
937PERIPH_CLK(mpe, "mpe", NULL, 60, 0x170, 250000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
938PERIPH_CLK(host1x, "host1x", NULL, 28, 0x180, 166000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
939PERIPH_CLK(cve, "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
940PERIPH_CLK(tvo, "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
941PERIPH_CLK(hdmi, "hdmi", NULL, 51, 0x18c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
942PERIPH_CLK(tvdac, "tvdac", NULL, 53, 0x194, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
943PERIPH_CLK(disp1, "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_plld_pllc_clkm, MUX); /* scales with voltage and process_id */
944PERIPH_CLK(disp2, "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_plld_pllc_clkm, MUX); /* scales with voltage and process_id */
945PERIPH_CLK(usbd, "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
946PERIPH_CLK(usb2, "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
947PERIPH_CLK(usb3, "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
948PERIPH_CLK(dsi, "dsi", NULL, 48, 0, 500000000, mux_plld, 0); /* scales with voltage */
949PERIPH_CLK(csi, "tegra_camera", "csi", 52, 0, 72000000, mux_pllp_out3, 0);
950PERIPH_CLK(isp, "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0); /* same frequency as VI */
951PERIPH_CLK(csus, "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET);
952PERIPH_CLK(pex, NULL, "pex", 70, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET);
953PERIPH_CLK(afi, NULL, "afi", 72, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET);
954PERIPH_CLK(pcie_xclk, NULL, "pcie_xclk", 74, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET);
955
956static struct clk *tegra_list_clks[] = {
957 &tegra_apbdma,
958 &tegra_rtc,
959 &tegra_timer,
960 &tegra_i2s1,
961 &tegra_i2s2,
962 &tegra_spdif_out,
963 &tegra_spdif_in,
964 &tegra_pwm,
965 &tegra_spi,
966 &tegra_xio,
967 &tegra_twc,
968 &tegra_sbc1,
969 &tegra_sbc2,
970 &tegra_sbc3,
971 &tegra_sbc4,
972 &tegra_ide,
973 &tegra_ndflash,
974 &tegra_vfir,
975 &tegra_sdmmc1,
976 &tegra_sdmmc2,
977 &tegra_sdmmc3,
978 &tegra_sdmmc4,
979 &tegra_vcp,
980 &tegra_bsea,
981 &tegra_bsev,
982 &tegra_vde,
983 &tegra_csite,
984 &tegra_la,
985 &tegra_owr,
986 &tegra_nor,
987 &tegra_mipi,
988 &tegra_i2c1,
989 &tegra_i2c2,
990 &tegra_i2c3,
991 &tegra_dvc,
992 &tegra_uarta,
993 &tegra_uartb,
994 &tegra_uartc,
995 &tegra_uartd,
996 &tegra_uarte,
997 &tegra_3d,
998 &tegra_2d,
999 &tegra_vi,
1000 &tegra_vi_sensor,
1001 &tegra_epp,
1002 &tegra_mpe,
1003 &tegra_host1x,
1004 &tegra_cve,
1005 &tegra_tvo,
1006 &tegra_hdmi,
1007 &tegra_tvdac,
1008 &tegra_disp1,
1009 &tegra_disp2,
1010 &tegra_usbd,
1011 &tegra_usb2,
1012 &tegra_usb3,
1013 &tegra_dsi,
1014 &tegra_csi,
1015 &tegra_isp,
1016 &tegra_csus,
1017 &tegra_pex,
1018 &tegra_afi,
1019 &tegra_pcie_xclk,
1020};
1021
1022#define CLK_DUPLICATE(_name, _dev, _con) \
1023 { \
1024 .name = _name, \
1025 .lookup = { \
1026 .dev_id = _dev, \
1027 .con_id = _con, \
1028 }, \
1029 }
1030
1031/* Some clocks may be used by different drivers depending on the board
1032 * configuration. List those here to register them twice in the clock lookup
1033 * table under two names.
1034 */
1035static struct clk_duplicate tegra_clk_duplicates[] = {
1036 CLK_DUPLICATE("uarta", "serial8250.0", NULL),
1037 CLK_DUPLICATE("uartb", "serial8250.1", NULL),
1038 CLK_DUPLICATE("uartc", "serial8250.2", NULL),
1039 CLK_DUPLICATE("uartd", "serial8250.3", NULL),
1040 CLK_DUPLICATE("uarte", "serial8250.4", NULL),
1041 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
1042 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
1043 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
1044 CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
1045 CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
1046 CLK_DUPLICATE("epp", "tegra_grhost", "epp"),
1047 CLK_DUPLICATE("mpe", "tegra_grhost", "mpe"),
1048 CLK_DUPLICATE("cop", "tegra-avp", "cop"),
1049 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
1050 CLK_DUPLICATE("cclk", NULL, "cpu"),
1051 CLK_DUPLICATE("twd", "smp_twd", NULL),
1052 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.0", "fast-clk"),
1053 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.1", "fast-clk"),
1054 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.2", "fast-clk"),
1055 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.3", "fast-clk"),
1056 CLK_DUPLICATE("pll_p", "tegradc.0", "parent"),
1057 CLK_DUPLICATE("pll_p", "tegradc.1", "parent"),
1058 CLK_DUPLICATE("pll_d_out0", "hdmi", "parent"),
1059};
1060
1061#define CLK(dev, con, ck) \
1062 { \
1063 .dev_id = dev, \
1064 .con_id = con, \
1065 .clk = ck, \
1066 }
1067
1068static struct clk *tegra_ptr_clks[] = {
1069 &tegra_clk_32k,
1070 &tegra_pll_s,
1071 &tegra_clk_m,
1072 &tegra_pll_m,
1073 &tegra_pll_m_out1,
1074 &tegra_pll_c,
1075 &tegra_pll_c_out1,
1076 &tegra_pll_p,
1077 &tegra_pll_p_out1,
1078 &tegra_pll_p_out2,
1079 &tegra_pll_p_out3,
1080 &tegra_pll_p_out4,
1081 &tegra_pll_a,
1082 &tegra_pll_a_out0,
1083 &tegra_pll_d,
1084 &tegra_pll_d_out0,
1085 &tegra_pll_u,
1086 &tegra_pll_x,
1087 &tegra_pll_e,
1088 &tegra_cclk,
1089 &tegra_clk_twd,
1090 &tegra_sclk,
1091 &tegra_hclk,
1092 &tegra_pclk,
1093 &tegra_clk_d,
1094 &tegra_cdev1,
1095 &tegra_cdev2,
1096 &tegra_blink,
1097 &tegra_cop,
1098 &tegra_emc,
1099};
1100
1101static void tegra2_init_one_clock(struct clk *c)
1102{
1103 struct clk_tegra *clk = to_clk_tegra(c->hw);
1104 int ret;
1105
1106 ret = __clk_init(NULL, c);
1107 if (ret)
1108 pr_err("clk init failed %s\n", __clk_get_name(c));
1109
1110 INIT_LIST_HEAD(&clk->shared_bus_list);
1111 if (!clk->lookup.dev_id && !clk->lookup.con_id)
1112 clk->lookup.con_id = c->name;
1113 clk->lookup.clk = c;
1114 clkdev_add(&clk->lookup);
1115 tegra_clk_add(c);
1116}
1117
1118void __init tegra2_init_clocks(void)
1119{
1120 int i;
1121 struct clk *c;
1122
1123 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
1124 tegra2_init_one_clock(tegra_ptr_clks[i]);
1125
1126 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
1127 tegra2_init_one_clock(tegra_list_clks[i]);
1128
1129 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
1130 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
1131 if (!c) {
1132 pr_err("%s: Unknown duplicate clock %s\n", __func__,
1133 tegra_clk_duplicates[i].name);
1134 continue;
1135 }
1136
1137 tegra_clk_duplicates[i].lookup.clk = c;
1138 clkdev_add(&tegra_clk_duplicates[i].lookup);
1139 }
1140
1141 init_audio_sync_clock_mux();
1142 tegra20_cpu_car_ops_init();
1143}
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
deleted file mode 100644
index d7147779f8ea..000000000000
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ /dev/null
@@ -1,2506 +0,0 @@
1/*
2 * arch/arm/mach-tegra/tegra30_clocks.c
3 *
4 * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
18 *
19 */
20
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/list.h>
24#include <linux/spinlock.h>
25#include <linux/delay.h>
26#include <linux/err.h>
27#include <linux/io.h>
28#include <linux/clk.h>
29#include <linux/cpufreq.h>
30#include <linux/syscore_ops.h>
31
32#include <asm/clkdev.h>
33
34#include <mach/powergate.h>
35
36#include "clock.h"
37#include "fuse.h"
38#include "iomap.h"
39#include "tegra_cpu_car.h"
40
41#define USE_PLL_LOCK_BITS 0
42
43#define RST_DEVICES_L 0x004
44#define RST_DEVICES_H 0x008
45#define RST_DEVICES_U 0x00C
46#define RST_DEVICES_V 0x358
47#define RST_DEVICES_W 0x35C
48#define RST_DEVICES_SET_L 0x300
49#define RST_DEVICES_CLR_L 0x304
50#define RST_DEVICES_SET_V 0x430
51#define RST_DEVICES_CLR_V 0x434
52#define RST_DEVICES_NUM 5
53
54#define CLK_OUT_ENB_L 0x010
55#define CLK_OUT_ENB_H 0x014
56#define CLK_OUT_ENB_U 0x018
57#define CLK_OUT_ENB_V 0x360
58#define CLK_OUT_ENB_W 0x364
59#define CLK_OUT_ENB_SET_L 0x320
60#define CLK_OUT_ENB_CLR_L 0x324
61#define CLK_OUT_ENB_SET_V 0x440
62#define CLK_OUT_ENB_CLR_V 0x444
63#define CLK_OUT_ENB_NUM 5
64
65#define RST_DEVICES_V_SWR_CPULP_RST_DIS (0x1 << 1)
66#define CLK_OUT_ENB_V_CLK_ENB_CPULP_EN (0x1 << 1)
67
68#define PERIPH_CLK_TO_BIT(c) (1 << (c->u.periph.clk_num % 32))
69#define PERIPH_CLK_TO_RST_REG(c) \
70 periph_clk_to_reg((c), RST_DEVICES_L, RST_DEVICES_V, 4)
71#define PERIPH_CLK_TO_RST_SET_REG(c) \
72 periph_clk_to_reg((c), RST_DEVICES_SET_L, RST_DEVICES_SET_V, 8)
73#define PERIPH_CLK_TO_RST_CLR_REG(c) \
74 periph_clk_to_reg((c), RST_DEVICES_CLR_L, RST_DEVICES_CLR_V, 8)
75
76#define PERIPH_CLK_TO_ENB_REG(c) \
77 periph_clk_to_reg((c), CLK_OUT_ENB_L, CLK_OUT_ENB_V, 4)
78#define PERIPH_CLK_TO_ENB_SET_REG(c) \
79 periph_clk_to_reg((c), CLK_OUT_ENB_SET_L, CLK_OUT_ENB_SET_V, 8)
80#define PERIPH_CLK_TO_ENB_CLR_REG(c) \
81 periph_clk_to_reg((c), CLK_OUT_ENB_CLR_L, CLK_OUT_ENB_CLR_V, 8)
82
83#define CLK_MASK_ARM 0x44
84#define MISC_CLK_ENB 0x48
85
86#define OSC_CTRL 0x50
87#define OSC_CTRL_OSC_FREQ_MASK (0xF<<28)
88#define OSC_CTRL_OSC_FREQ_13MHZ (0x0<<28)
89#define OSC_CTRL_OSC_FREQ_19_2MHZ (0x4<<28)
90#define OSC_CTRL_OSC_FREQ_12MHZ (0x8<<28)
91#define OSC_CTRL_OSC_FREQ_26MHZ (0xC<<28)
92#define OSC_CTRL_OSC_FREQ_16_8MHZ (0x1<<28)
93#define OSC_CTRL_OSC_FREQ_38_4MHZ (0x5<<28)
94#define OSC_CTRL_OSC_FREQ_48MHZ (0x9<<28)
95#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
96
97#define OSC_CTRL_PLL_REF_DIV_MASK (3<<26)
98#define OSC_CTRL_PLL_REF_DIV_1 (0<<26)
99#define OSC_CTRL_PLL_REF_DIV_2 (1<<26)
100#define OSC_CTRL_PLL_REF_DIV_4 (2<<26)
101
102#define OSC_FREQ_DET 0x58
103#define OSC_FREQ_DET_TRIG (1<<31)
104
105#define OSC_FREQ_DET_STATUS 0x5C
106#define OSC_FREQ_DET_BUSY (1<<31)
107#define OSC_FREQ_DET_CNT_MASK 0xFFFF
108
109#define PERIPH_CLK_SOURCE_I2S1 0x100
110#define PERIPH_CLK_SOURCE_EMC 0x19c
111#define PERIPH_CLK_SOURCE_OSC 0x1fc
112#define PERIPH_CLK_SOURCE_NUM1 \
113 ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
114
115#define PERIPH_CLK_SOURCE_G3D2 0x3b0
116#define PERIPH_CLK_SOURCE_SE 0x42c
117#define PERIPH_CLK_SOURCE_NUM2 \
118 ((PERIPH_CLK_SOURCE_SE - PERIPH_CLK_SOURCE_G3D2) / 4 + 1)
119
120#define AUDIO_DLY_CLK 0x49c
121#define AUDIO_SYNC_CLK_SPDIF 0x4b4
122#define PERIPH_CLK_SOURCE_NUM3 \
123 ((AUDIO_SYNC_CLK_SPDIF - AUDIO_DLY_CLK) / 4 + 1)
124
125#define PERIPH_CLK_SOURCE_NUM (PERIPH_CLK_SOURCE_NUM1 + \
126 PERIPH_CLK_SOURCE_NUM2 + \
127 PERIPH_CLK_SOURCE_NUM3)
128
129#define CPU_SOFTRST_CTRL 0x380
130
131#define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
132#define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
133#define PERIPH_CLK_SOURCE_DIV_SHIFT 0
134#define PERIPH_CLK_SOURCE_DIVIDLE_SHIFT 8
135#define PERIPH_CLK_SOURCE_DIVIDLE_VAL 50
136#define PERIPH_CLK_UART_DIV_ENB (1<<24)
137#define PERIPH_CLK_VI_SEL_EX_SHIFT 24
138#define PERIPH_CLK_VI_SEL_EX_MASK (0x3<<PERIPH_CLK_VI_SEL_EX_SHIFT)
139#define PERIPH_CLK_NAND_DIV_EX_ENB (1<<8)
140#define PERIPH_CLK_DTV_POLARITY_INV (1<<25)
141
142#define AUDIO_SYNC_SOURCE_MASK 0x0F
143#define AUDIO_SYNC_DISABLE_BIT 0x10
144#define AUDIO_SYNC_TAP_NIBBLE_SHIFT(c) ((c->reg_shift - 24) * 4)
145
146#define PLL_BASE 0x0
147#define PLL_BASE_BYPASS (1<<31)
148#define PLL_BASE_ENABLE (1<<30)
149#define PLL_BASE_REF_ENABLE (1<<29)
150#define PLL_BASE_OVERRIDE (1<<28)
151#define PLL_BASE_LOCK (1<<27)
152#define PLL_BASE_DIVP_MASK (0x7<<20)
153#define PLL_BASE_DIVP_SHIFT 20
154#define PLL_BASE_DIVN_MASK (0x3FF<<8)
155#define PLL_BASE_DIVN_SHIFT 8
156#define PLL_BASE_DIVM_MASK (0x1F)
157#define PLL_BASE_DIVM_SHIFT 0
158
159#define PLL_OUT_RATIO_MASK (0xFF<<8)
160#define PLL_OUT_RATIO_SHIFT 8
161#define PLL_OUT_OVERRIDE (1<<2)
162#define PLL_OUT_CLKEN (1<<1)
163#define PLL_OUT_RESET_DISABLE (1<<0)
164
165#define PLL_MISC(c) \
166 (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
167#define PLL_MISC_LOCK_ENABLE(c) \
168 (((c)->flags & (PLLU | PLLD)) ? (1<<22) : (1<<18))
169
170#define PLL_MISC_DCCON_SHIFT 20
171#define PLL_MISC_CPCON_SHIFT 8
172#define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)
173#define PLL_MISC_LFCON_SHIFT 4
174#define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)
175#define PLL_MISC_VCOCON_SHIFT 0
176#define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)
177#define PLLD_MISC_CLKENABLE (1<<30)
178
179#define PLLU_BASE_POST_DIV (1<<20)
180
181#define PLLD_BASE_DSIB_MUX_SHIFT 25
182#define PLLD_BASE_DSIB_MUX_MASK (1<<PLLD_BASE_DSIB_MUX_SHIFT)
183#define PLLD_BASE_CSI_CLKENABLE (1<<26)
184#define PLLD_MISC_DSI_CLKENABLE (1<<30)
185#define PLLD_MISC_DIV_RST (1<<23)
186#define PLLD_MISC_DCCON_SHIFT 12
187
188#define PLLDU_LFCON_SET_DIVN 600
189
190/* FIXME: OUT_OF_TABLE_CPCON per pll */
191#define OUT_OF_TABLE_CPCON 0x8
192
193#define SUPER_CLK_MUX 0x00
194#define SUPER_STATE_SHIFT 28
195#define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)
196#define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)
197#define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)
198#define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)
199#define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)
200#define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)
201#define SUPER_LP_DIV2_BYPASS (0x1 << 16)
202#define SUPER_SOURCE_MASK 0xF
203#define SUPER_FIQ_SOURCE_SHIFT 12
204#define SUPER_IRQ_SOURCE_SHIFT 8
205#define SUPER_RUN_SOURCE_SHIFT 4
206#define SUPER_IDLE_SOURCE_SHIFT 0
207
208#define SUPER_CLK_DIVIDER 0x04
209#define SUPER_CLOCK_DIV_U71_SHIFT 16
210#define SUPER_CLOCK_DIV_U71_MASK (0xff << SUPER_CLOCK_DIV_U71_SHIFT)
211/* guarantees safe cpu backup */
212#define SUPER_CLOCK_DIV_U71_MIN 0x2
213
214#define BUS_CLK_DISABLE (1<<3)
215#define BUS_CLK_DIV_MASK 0x3
216
217#define PMC_CTRL 0x0
218 #define PMC_CTRL_BLINK_ENB (1 << 7)
219
220#define PMC_DPD_PADS_ORIDE 0x1c
221 #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20)
222
223#define PMC_BLINK_TIMER_DATA_ON_SHIFT 0
224#define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff
225#define PMC_BLINK_TIMER_ENB (1 << 15)
226#define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16
227#define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff
228
229#define PMC_PLLP_WB0_OVERRIDE 0xf8
230#define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE (1 << 12)
231
232#define UTMIP_PLL_CFG2 0x488
233#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
234#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
235#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN (1 << 0)
236#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN (1 << 2)
237#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN (1 << 4)
238
239#define UTMIP_PLL_CFG1 0x484
240#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
241#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
242#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN (1 << 14)
243#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN (1 << 12)
244#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN (1 << 16)
245
246#define PLLE_BASE_CML_ENABLE (1<<31)
247#define PLLE_BASE_ENABLE (1<<30)
248#define PLLE_BASE_DIVCML_SHIFT 24
249#define PLLE_BASE_DIVCML_MASK (0xf<<PLLE_BASE_DIVCML_SHIFT)
250#define PLLE_BASE_DIVP_SHIFT 16
251#define PLLE_BASE_DIVP_MASK (0x3f<<PLLE_BASE_DIVP_SHIFT)
252#define PLLE_BASE_DIVN_SHIFT 8
253#define PLLE_BASE_DIVN_MASK (0xFF<<PLLE_BASE_DIVN_SHIFT)
254#define PLLE_BASE_DIVM_SHIFT 0
255#define PLLE_BASE_DIVM_MASK (0xFF<<PLLE_BASE_DIVM_SHIFT)
256#define PLLE_BASE_DIV_MASK \
257 (PLLE_BASE_DIVCML_MASK | PLLE_BASE_DIVP_MASK | \
258 PLLE_BASE_DIVN_MASK | PLLE_BASE_DIVM_MASK)
259#define PLLE_BASE_DIV(m, n, p, cml) \
260 (((cml)<<PLLE_BASE_DIVCML_SHIFT) | ((p)<<PLLE_BASE_DIVP_SHIFT) | \
261 ((n)<<PLLE_BASE_DIVN_SHIFT) | ((m)<<PLLE_BASE_DIVM_SHIFT))
262
263#define PLLE_MISC_SETUP_BASE_SHIFT 16
264#define PLLE_MISC_SETUP_BASE_MASK (0xFFFF<<PLLE_MISC_SETUP_BASE_SHIFT)
265#define PLLE_MISC_READY (1<<15)
266#define PLLE_MISC_LOCK (1<<11)
267#define PLLE_MISC_LOCK_ENABLE (1<<9)
268#define PLLE_MISC_SETUP_EX_SHIFT 2
269#define PLLE_MISC_SETUP_EX_MASK (0x3<<PLLE_MISC_SETUP_EX_SHIFT)
270#define PLLE_MISC_SETUP_MASK \
271 (PLLE_MISC_SETUP_BASE_MASK | PLLE_MISC_SETUP_EX_MASK)
272#define PLLE_MISC_SETUP_VALUE \
273 ((0x7<<PLLE_MISC_SETUP_BASE_SHIFT) | (0x0<<PLLE_MISC_SETUP_EX_SHIFT))
274
275#define PLLE_SS_CTRL 0x68
276#define PLLE_SS_INCINTRV_SHIFT 24
277#define PLLE_SS_INCINTRV_MASK (0x3f<<PLLE_SS_INCINTRV_SHIFT)
278#define PLLE_SS_INC_SHIFT 16
279#define PLLE_SS_INC_MASK (0xff<<PLLE_SS_INC_SHIFT)
280#define PLLE_SS_MAX_SHIFT 0
281#define PLLE_SS_MAX_MASK (0x1ff<<PLLE_SS_MAX_SHIFT)
282#define PLLE_SS_COEFFICIENTS_MASK \
283 (PLLE_SS_INCINTRV_MASK | PLLE_SS_INC_MASK | PLLE_SS_MAX_MASK)
284#define PLLE_SS_COEFFICIENTS_12MHZ \
285 ((0x18<<PLLE_SS_INCINTRV_SHIFT) | (0x1<<PLLE_SS_INC_SHIFT) | \
286 (0x24<<PLLE_SS_MAX_SHIFT))
287#define PLLE_SS_DISABLE ((1<<12) | (1<<11) | (1<<10))
288
289#define PLLE_AUX 0x48c
290#define PLLE_AUX_PLLP_SEL (1<<2)
291#define PLLE_AUX_CML_SATA_ENABLE (1<<1)
292#define PLLE_AUX_CML_PCIE_ENABLE (1<<0)
293
294#define PMC_SATA_PWRGT 0x1ac
295#define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE (1<<5)
296#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1<<4)
297
298#define ROUND_DIVIDER_UP 0
299#define ROUND_DIVIDER_DOWN 1
300
301/* FIXME: recommended safety delay after lock is detected */
302#define PLL_POST_LOCK_DELAY 100
303
304/* Tegra CPU clock and reset control regs */
305#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
306#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
307#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344
308#define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c
309#define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
310
311#define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
312#define CPU_RESET(cpu) (0x1111ul << (cpu))
313
314#define CLK_RESET_CCLK_BURST 0x20
315#define CLK_RESET_CCLK_DIVIDER 0x24
316#define CLK_RESET_PLLX_BASE 0xe0
317#define CLK_RESET_PLLX_MISC 0xe4
318
319#define CLK_RESET_SOURCE_CSITE 0x1d4
320
321#define CLK_RESET_CCLK_BURST_POLICY_SHIFT 28
322#define CLK_RESET_CCLK_RUN_POLICY_SHIFT 4
323#define CLK_RESET_CCLK_IDLE_POLICY_SHIFT 0
324#define CLK_RESET_CCLK_IDLE_POLICY 1
325#define CLK_RESET_CCLK_RUN_POLICY 2
326#define CLK_RESET_CCLK_BURST_POLICY_PLLX 8
327
328#ifdef CONFIG_PM_SLEEP
329static struct cpu_clk_suspend_context {
330 u32 pllx_misc;
331 u32 pllx_base;
332
333 u32 cpu_burst;
334 u32 clk_csite_src;
335 u32 cclk_divider;
336} tegra30_cpu_clk_sctx;
337#endif
338
339/**
340* Structure defining the fields for USB UTMI clocks Parameters.
341*/
342struct utmi_clk_param {
343 /* Oscillator Frequency in KHz */
344 u32 osc_frequency;
345 /* UTMIP PLL Enable Delay Count */
346 u8 enable_delay_count;
347 /* UTMIP PLL Stable count */
348 u8 stable_count;
349 /* UTMIP PLL Active delay count */
350 u8 active_delay_count;
351 /* UTMIP PLL Xtal frequency count */
352 u8 xtal_freq_count;
353};
354
355static const struct utmi_clk_param utmi_parameters[] = {
356 {
357 .osc_frequency = 13000000,
358 .enable_delay_count = 0x02,
359 .stable_count = 0x33,
360 .active_delay_count = 0x05,
361 .xtal_freq_count = 0x7F
362 },
363 {
364 .osc_frequency = 19200000,
365 .enable_delay_count = 0x03,
366 .stable_count = 0x4B,
367 .active_delay_count = 0x06,
368 .xtal_freq_count = 0xBB},
369 {
370 .osc_frequency = 12000000,
371 .enable_delay_count = 0x02,
372 .stable_count = 0x2F,
373 .active_delay_count = 0x04,
374 .xtal_freq_count = 0x76
375 },
376 {
377 .osc_frequency = 26000000,
378 .enable_delay_count = 0x04,
379 .stable_count = 0x66,
380 .active_delay_count = 0x09,
381 .xtal_freq_count = 0xFE
382 },
383 {
384 .osc_frequency = 16800000,
385 .enable_delay_count = 0x03,
386 .stable_count = 0x41,
387 .active_delay_count = 0x0A,
388 .xtal_freq_count = 0xA4
389 },
390};
391
392static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
393static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
394static void __iomem *misc_gp_hidrev_base = IO_ADDRESS(TEGRA_APB_MISC_BASE);
395
396#define MISC_GP_HIDREV 0x804
397
398/*
399 * Some peripheral clocks share an enable bit, so refcount the enable bits
400 * in registers CLK_ENABLE_L, ... CLK_ENABLE_W
401 */
402static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32];
403
404#define clk_writel(value, reg) \
405 __raw_writel(value, reg_clk_base + (reg))
406#define clk_readl(reg) \
407 __raw_readl(reg_clk_base + (reg))
408#define pmc_writel(value, reg) \
409 __raw_writel(value, reg_pmc_base + (reg))
410#define pmc_readl(reg) \
411 __raw_readl(reg_pmc_base + (reg))
412#define chipid_readl() \
413 __raw_readl(misc_gp_hidrev_base + MISC_GP_HIDREV)
414
415#define clk_writel_delay(value, reg) \
416 do { \
417 __raw_writel((value), reg_clk_base + (reg)); \
418 udelay(2); \
419 } while (0)
420
421static inline int clk_set_div(struct clk_tegra *c, u32 n)
422{
423 struct clk *clk = c->hw.clk;
424
425 return clk_set_rate(clk,
426 (__clk_get_rate(__clk_get_parent(clk)) + n - 1) / n);
427}
428
429static inline u32 periph_clk_to_reg(
430 struct clk_tegra *c, u32 reg_L, u32 reg_V, int offs)
431{
432 u32 reg = c->u.periph.clk_num / 32;
433 BUG_ON(reg >= RST_DEVICES_NUM);
434 if (reg < 3)
435 reg = reg_L + (reg * offs);
436 else
437 reg = reg_V + ((reg - 3) * offs);
438 return reg;
439}
440
441static unsigned long clk_measure_input_freq(void)
442{
443 u32 clock_autodetect;
444 clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
445 do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
446 clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
447 if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
448 return 12000000;
449 } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
450 return 13000000;
451 } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
452 return 19200000;
453 } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
454 return 26000000;
455 } else if (clock_autodetect >= 1025 - 3 && clock_autodetect <= 1025 + 3) {
456 return 16800000;
457 } else if (clock_autodetect >= 2344 - 3 && clock_autodetect <= 2344 + 3) {
458 return 38400000;
459 } else if (clock_autodetect >= 2928 - 3 && clock_autodetect <= 2928 + 3) {
460 return 48000000;
461 } else {
462 pr_err("%s: Unexpected clock autodetect value %d", __func__,
463 clock_autodetect);
464 BUG();
465 return 0;
466 }
467}
468
469static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate,
470 u32 flags, u32 round_mode)
471{
472 s64 divider_u71 = parent_rate;
473 if (!rate)
474 return -EINVAL;
475
476 if (!(flags & DIV_U71_INT))
477 divider_u71 *= 2;
478 if (round_mode == ROUND_DIVIDER_UP)
479 divider_u71 += rate - 1;
480 do_div(divider_u71, rate);
481 if (flags & DIV_U71_INT)
482 divider_u71 *= 2;
483
484 if (divider_u71 - 2 < 0)
485 return 0;
486
487 if (divider_u71 - 2 > 255)
488 return -EINVAL;
489
490 return divider_u71 - 2;
491}
492
493static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
494{
495 s64 divider_u16;
496
497 divider_u16 = parent_rate;
498 if (!rate)
499 return -EINVAL;
500 divider_u16 += rate - 1;
501 do_div(divider_u16, rate);
502
503 if (divider_u16 - 1 < 0)
504 return 0;
505
506 if (divider_u16 - 1 > 0xFFFF)
507 return -EINVAL;
508
509 return divider_u16 - 1;
510}
511
512static unsigned long tegra30_clk_fixed_recalc_rate(struct clk_hw *hw,
513 unsigned long parent_rate)
514{
515 return to_clk_tegra(hw)->fixed_rate;
516}
517
518struct clk_ops tegra30_clk_32k_ops = {
519 .recalc_rate = tegra30_clk_fixed_recalc_rate,
520};
521
522/* clk_m functions */
523static unsigned long tegra30_clk_m_recalc_rate(struct clk_hw *hw,
524 unsigned long parent_rate)
525{
526 if (!to_clk_tegra(hw)->fixed_rate)
527 to_clk_tegra(hw)->fixed_rate = clk_measure_input_freq();
528 return to_clk_tegra(hw)->fixed_rate;
529}
530
531static void tegra30_clk_m_init(struct clk_hw *hw)
532{
533 u32 osc_ctrl = clk_readl(OSC_CTRL);
534 u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK;
535 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
536
537 switch (to_clk_tegra(hw)->fixed_rate) {
538 case 12000000:
539 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
540 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
541 break;
542 case 13000000:
543 auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
544 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
545 break;
546 case 19200000:
547 auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
548 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
549 break;
550 case 26000000:
551 auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
552 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
553 break;
554 case 16800000:
555 auto_clock_control |= OSC_CTRL_OSC_FREQ_16_8MHZ;
556 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
557 break;
558 case 38400000:
559 auto_clock_control |= OSC_CTRL_OSC_FREQ_38_4MHZ;
560 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_2);
561 break;
562 case 48000000:
563 auto_clock_control |= OSC_CTRL_OSC_FREQ_48MHZ;
564 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4);
565 break;
566 default:
567 pr_err("%s: Unexpected clock rate %ld", __func__,
568 to_clk_tegra(hw)->fixed_rate);
569 BUG();
570 }
571 clk_writel(auto_clock_control, OSC_CTRL);
572}
573
574struct clk_ops tegra30_clk_m_ops = {
575 .init = tegra30_clk_m_init,
576 .recalc_rate = tegra30_clk_m_recalc_rate,
577};
578
579static unsigned long tegra30_clk_m_div_recalc_rate(struct clk_hw *hw,
580 unsigned long parent_rate)
581{
582 struct clk_tegra *c = to_clk_tegra(hw);
583 u64 rate = parent_rate;
584
585 if (c->mul != 0 && c->div != 0) {
586 rate *= c->mul;
587 rate += c->div - 1; /* round up */
588 do_div(rate, c->div);
589 }
590
591 return rate;
592}
593
594struct clk_ops tegra_clk_m_div_ops = {
595 .recalc_rate = tegra30_clk_m_div_recalc_rate,
596};
597
598/* PLL reference divider functions */
599static unsigned long tegra30_pll_ref_recalc_rate(struct clk_hw *hw,
600 unsigned long parent_rate)
601{
602 struct clk_tegra *c = to_clk_tegra(hw);
603 unsigned long rate = parent_rate;
604 u32 pll_ref_div = clk_readl(OSC_CTRL) & OSC_CTRL_PLL_REF_DIV_MASK;
605
606 switch (pll_ref_div) {
607 case OSC_CTRL_PLL_REF_DIV_1:
608 c->div = 1;
609 break;
610 case OSC_CTRL_PLL_REF_DIV_2:
611 c->div = 2;
612 break;
613 case OSC_CTRL_PLL_REF_DIV_4:
614 c->div = 4;
615 break;
616 default:
617 pr_err("%s: Invalid pll ref divider %d", __func__, pll_ref_div);
618 BUG();
619 }
620 c->mul = 1;
621
622 if (c->mul != 0 && c->div != 0) {
623 rate *= c->mul;
624 rate += c->div - 1; /* round up */
625 do_div(rate, c->div);
626 }
627
628 return rate;
629}
630
631struct clk_ops tegra_pll_ref_ops = {
632 .recalc_rate = tegra30_pll_ref_recalc_rate,
633};
634
635/* super clock functions */
636/* "super clocks" on tegra30 have two-stage muxes, fractional 7.1 divider and
637 * clock skipping super divider. We will ignore the clock skipping divider,
638 * since we can't lower the voltage when using the clock skip, but we can if
639 * we lower the PLL frequency. We will use 7.1 divider for CPU super-clock
640 * only when its parent is a fixed rate PLL, since we can't change PLL rate
641 * in this case.
642 */
643static void tegra30_super_clk_init(struct clk_hw *hw)
644{
645 struct clk_tegra *c = to_clk_tegra(hw);
646 struct clk_tegra *p =
647 to_clk_tegra(__clk_get_hw(__clk_get_parent(hw->clk)));
648
649 c->state = ON;
650 if (c->flags & DIV_U71) {
651 /* Init safe 7.1 divider value (does not affect PLLX path) */
652 clk_writel(SUPER_CLOCK_DIV_U71_MIN << SUPER_CLOCK_DIV_U71_SHIFT,
653 c->reg + SUPER_CLK_DIVIDER);
654 c->mul = 2;
655 c->div = 2;
656 if (!(p->flags & PLLX))
657 c->div += SUPER_CLOCK_DIV_U71_MIN;
658 } else
659 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
660}
661
662static u8 tegra30_super_clk_get_parent(struct clk_hw *hw)
663{
664 struct clk_tegra *c = to_clk_tegra(hw);
665 u32 val;
666 int source;
667 int shift;
668
669 val = clk_readl(c->reg + SUPER_CLK_MUX);
670 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
671 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
672 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
673 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
674 source = (val >> shift) & SUPER_SOURCE_MASK;
675 if (c->flags & DIV_2)
676 source |= val & SUPER_LP_DIV2_BYPASS;
677
678 return source;
679}
680
681static int tegra30_super_clk_set_parent(struct clk_hw *hw, u8 index)
682{
683 struct clk_tegra *c = to_clk_tegra(hw);
684 struct clk_tegra *p =
685 to_clk_tegra(__clk_get_hw(clk_get_parent(hw->clk)));
686 u32 val;
687 int shift;
688
689 val = clk_readl(c->reg + SUPER_CLK_MUX);
690 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
691 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
692 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
693 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
694
695 /* For LP mode super-clock switch between PLLX direct
696 and divided-by-2 outputs is allowed only when other
697 than PLLX clock source is current parent */
698 if ((c->flags & DIV_2) && (p->flags & PLLX) &&
699 ((index ^ val) & SUPER_LP_DIV2_BYPASS)) {
700 if (p->flags & PLLX)
701 return -EINVAL;
702 val ^= SUPER_LP_DIV2_BYPASS;
703 clk_writel_delay(val, c->reg);
704 }
705 val &= ~(SUPER_SOURCE_MASK << shift);
706 val |= (index & SUPER_SOURCE_MASK) << shift;
707
708 /* 7.1 divider for CPU super-clock does not affect
709 PLLX path */
710 if (c->flags & DIV_U71) {
711 u32 div = 0;
712 if (!(p->flags & PLLX)) {
713 div = clk_readl(c->reg +
714 SUPER_CLK_DIVIDER);
715 div &= SUPER_CLOCK_DIV_U71_MASK;
716 div >>= SUPER_CLOCK_DIV_U71_SHIFT;
717 }
718 c->div = div + 2;
719 c->mul = 2;
720 }
721 clk_writel_delay(val, c->reg);
722
723 return 0;
724}
725
726/*
727 * Do not use super clocks "skippers", since dividing using a clock skipper
728 * does not allow the voltage to be scaled down. Instead adjust the rate of
729 * the parent clock. This requires that the parent of a super clock have no
730 * other children, otherwise the rate will change underneath the other
731 * children. Special case: if fixed rate PLL is CPU super clock parent the
732 * rate of this PLL can't be changed, and it has many other children. In
733 * this case use 7.1 fractional divider to adjust the super clock rate.
734 */
735static int tegra30_super_clk_set_rate(struct clk_hw *hw, unsigned long rate,
736 unsigned long parent_rate)
737{
738 struct clk_tegra *c = to_clk_tegra(hw);
739 struct clk *parent = __clk_get_parent(hw->clk);
740 struct clk_tegra *cparent = to_clk_tegra(__clk_get_hw(parent));
741
742 if ((c->flags & DIV_U71) && (cparent->flags & PLL_FIXED)) {
743 int div = clk_div71_get_divider(parent_rate,
744 rate, c->flags, ROUND_DIVIDER_DOWN);
745 div = max(div, SUPER_CLOCK_DIV_U71_MIN);
746
747 clk_writel(div << SUPER_CLOCK_DIV_U71_SHIFT,
748 c->reg + SUPER_CLK_DIVIDER);
749 c->div = div + 2;
750 c->mul = 2;
751 return 0;
752 }
753 return 0;
754}
755
756static unsigned long tegra30_super_clk_recalc_rate(struct clk_hw *hw,
757 unsigned long parent_rate)
758{
759 struct clk_tegra *c = to_clk_tegra(hw);
760 u64 rate = parent_rate;
761
762 if (c->mul != 0 && c->div != 0) {
763 rate *= c->mul;
764 rate += c->div - 1; /* round up */
765 do_div(rate, c->div);
766 }
767
768 return rate;
769}
770
771static long tegra30_super_clk_round_rate(struct clk_hw *hw, unsigned long rate,
772 unsigned long *prate)
773{
774 struct clk_tegra *c = to_clk_tegra(hw);
775 struct clk *parent = __clk_get_parent(hw->clk);
776 struct clk_tegra *cparent = to_clk_tegra(__clk_get_hw(parent));
777 int mul = 2;
778 int div;
779
780 if ((c->flags & DIV_U71) && (cparent->flags & PLL_FIXED)) {
781 div = clk_div71_get_divider(*prate,
782 rate, c->flags, ROUND_DIVIDER_DOWN);
783 div = max(div, SUPER_CLOCK_DIV_U71_MIN) + 2;
784 rate = *prate * mul;
785 rate += div - 1; /* round up */
786 do_div(rate, c->div);
787
788 return rate;
789 }
790 return *prate;
791}
792
793struct clk_ops tegra30_super_ops = {
794 .init = tegra30_super_clk_init,
795 .set_parent = tegra30_super_clk_set_parent,
796 .get_parent = tegra30_super_clk_get_parent,
797 .recalc_rate = tegra30_super_clk_recalc_rate,
798 .round_rate = tegra30_super_clk_round_rate,
799 .set_rate = tegra30_super_clk_set_rate,
800};
801
802static unsigned long tegra30_twd_clk_recalc_rate(struct clk_hw *hw,
803 unsigned long parent_rate)
804{
805 struct clk_tegra *c = to_clk_tegra(hw);
806 u64 rate = parent_rate;
807
808 if (c->mul != 0 && c->div != 0) {
809 rate *= c->mul;
810 rate += c->div - 1; /* round up */
811 do_div(rate, c->div);
812 }
813
814 return rate;
815}
816
817struct clk_ops tegra30_twd_ops = {
818 .recalc_rate = tegra30_twd_clk_recalc_rate,
819};
820
821/* bus clock functions */
822static int tegra30_bus_clk_is_enabled(struct clk_hw *hw)
823{
824 struct clk_tegra *c = to_clk_tegra(hw);
825 u32 val = clk_readl(c->reg);
826
827 c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
828 return c->state;
829}
830
831static int tegra30_bus_clk_enable(struct clk_hw *hw)
832{
833 struct clk_tegra *c = to_clk_tegra(hw);
834 u32 val;
835
836 val = clk_readl(c->reg);
837 val &= ~(BUS_CLK_DISABLE << c->reg_shift);
838 clk_writel(val, c->reg);
839
840 return 0;
841}
842
843static void tegra30_bus_clk_disable(struct clk_hw *hw)
844{
845 struct clk_tegra *c = to_clk_tegra(hw);
846 u32 val;
847
848 val = clk_readl(c->reg);
849 val |= BUS_CLK_DISABLE << c->reg_shift;
850 clk_writel(val, c->reg);
851}
852
853static unsigned long tegra30_bus_clk_recalc_rate(struct clk_hw *hw,
854 unsigned long prate)
855{
856 struct clk_tegra *c = to_clk_tegra(hw);
857 u32 val = clk_readl(c->reg);
858 u64 rate = prate;
859
860 c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
861 c->mul = 1;
862
863 if (c->mul != 0 && c->div != 0) {
864 rate *= c->mul;
865 rate += c->div - 1; /* round up */
866 do_div(rate, c->div);
867 }
868 return rate;
869}
870
871static int tegra30_bus_clk_set_rate(struct clk_hw *hw, unsigned long rate,
872 unsigned long parent_rate)
873{
874 struct clk_tegra *c = to_clk_tegra(hw);
875 int ret = -EINVAL;
876 u32 val;
877 int i;
878
879 val = clk_readl(c->reg);
880 for (i = 1; i <= 4; i++) {
881 if (rate == parent_rate / i) {
882 val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
883 val |= (i - 1) << c->reg_shift;
884 clk_writel(val, c->reg);
885 c->div = i;
886 c->mul = 1;
887 ret = 0;
888 break;
889 }
890 }
891
892 return ret;
893}
894
895static long tegra30_bus_clk_round_rate(struct clk_hw *hw, unsigned long rate,
896 unsigned long *prate)
897{
898 unsigned long parent_rate = *prate;
899 s64 divider;
900
901 if (rate >= parent_rate)
902 return parent_rate;
903
904 divider = parent_rate;
905 divider += rate - 1;
906 do_div(divider, rate);
907
908 if (divider < 0)
909 return divider;
910
911 if (divider > 4)
912 divider = 4;
913 do_div(parent_rate, divider);
914
915 return parent_rate;
916}
917
918struct clk_ops tegra30_bus_ops = {
919 .is_enabled = tegra30_bus_clk_is_enabled,
920 .enable = tegra30_bus_clk_enable,
921 .disable = tegra30_bus_clk_disable,
922 .set_rate = tegra30_bus_clk_set_rate,
923 .round_rate = tegra30_bus_clk_round_rate,
924 .recalc_rate = tegra30_bus_clk_recalc_rate,
925};
926
927/* Blink output functions */
928static int tegra30_blink_clk_is_enabled(struct clk_hw *hw)
929{
930 struct clk_tegra *c = to_clk_tegra(hw);
931 u32 val;
932
933 val = pmc_readl(PMC_CTRL);
934 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
935 return c->state;
936}
937
938static int tegra30_blink_clk_enable(struct clk_hw *hw)
939{
940 u32 val;
941
942 val = pmc_readl(PMC_DPD_PADS_ORIDE);
943 pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
944
945 val = pmc_readl(PMC_CTRL);
946 pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
947
948 return 0;
949}
950
951static void tegra30_blink_clk_disable(struct clk_hw *hw)
952{
953 u32 val;
954
955 val = pmc_readl(PMC_CTRL);
956 pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
957
958 val = pmc_readl(PMC_DPD_PADS_ORIDE);
959 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
960}
961
962static int tegra30_blink_clk_set_rate(struct clk_hw *hw, unsigned long rate,
963 unsigned long parent_rate)
964{
965 struct clk_tegra *c = to_clk_tegra(hw);
966
967 if (rate >= parent_rate) {
968 c->div = 1;
969 pmc_writel(0, c->reg);
970 } else {
971 unsigned int on_off;
972 u32 val;
973
974 on_off = DIV_ROUND_UP(parent_rate / 8, rate);
975 c->div = on_off * 8;
976
977 val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
978 PMC_BLINK_TIMER_DATA_ON_SHIFT;
979 on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
980 on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
981 val |= on_off;
982 val |= PMC_BLINK_TIMER_ENB;
983 pmc_writel(val, c->reg);
984 }
985
986 return 0;
987}
988
989static unsigned long tegra30_blink_clk_recalc_rate(struct clk_hw *hw,
990 unsigned long parent_rate)
991{
992 struct clk_tegra *c = to_clk_tegra(hw);
993 u64 rate = parent_rate;
994 u32 val;
995 u32 mul;
996 u32 div;
997 u32 on_off;
998
999 mul = 1;
1000 val = pmc_readl(c->reg);
1001
1002 if (val & PMC_BLINK_TIMER_ENB) {
1003 on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
1004 PMC_BLINK_TIMER_DATA_ON_MASK;
1005 val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
1006 val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
1007 on_off += val;
1008 /* each tick in the blink timer is 4 32KHz clocks */
1009 div = on_off * 4;
1010 } else {
1011 div = 1;
1012 }
1013
1014 if (mul != 0 && div != 0) {
1015 rate *= mul;
1016 rate += div - 1; /* round up */
1017 do_div(rate, div);
1018 }
1019 return rate;
1020}
1021
1022static long tegra30_blink_clk_round_rate(struct clk_hw *hw, unsigned long rate,
1023 unsigned long *prate)
1024{
1025 int div;
1026 int mul;
1027 long round_rate = *prate;
1028
1029 mul = 1;
1030
1031 if (rate >= *prate) {
1032 div = 1;
1033 } else {
1034 div = DIV_ROUND_UP(*prate / 8, rate);
1035 div *= 8;
1036 }
1037
1038 round_rate *= mul;
1039 round_rate += div - 1;
1040 do_div(round_rate, div);
1041
1042 return round_rate;
1043}
1044
1045struct clk_ops tegra30_blink_clk_ops = {
1046 .is_enabled = tegra30_blink_clk_is_enabled,
1047 .enable = tegra30_blink_clk_enable,
1048 .disable = tegra30_blink_clk_disable,
1049 .recalc_rate = tegra30_blink_clk_recalc_rate,
1050 .round_rate = tegra30_blink_clk_round_rate,
1051 .set_rate = tegra30_blink_clk_set_rate,
1052};
1053
1054static void tegra30_utmi_param_configure(struct clk_hw *hw)
1055{
1056 unsigned long main_rate =
1057 __clk_get_rate(__clk_get_parent(__clk_get_parent(hw->clk)));
1058 u32 reg;
1059 int i;
1060
1061 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1062 if (main_rate == utmi_parameters[i].osc_frequency)
1063 break;
1064 }
1065
1066 if (i >= ARRAY_SIZE(utmi_parameters)) {
1067 pr_err("%s: Unexpected main rate %lu\n", __func__, main_rate);
1068 return;
1069 }
1070
1071 reg = clk_readl(UTMIP_PLL_CFG2);
1072
1073 /* Program UTMIP PLL stable and active counts */
1074 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
1075 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1076 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(
1077 utmi_parameters[i].stable_count);
1078
1079 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1080
1081 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(
1082 utmi_parameters[i].active_delay_count);
1083
1084 /* Remove power downs from UTMIP PLL control bits */
1085 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1086 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1087 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1088
1089 clk_writel(reg, UTMIP_PLL_CFG2);
1090
1091 /* Program UTMIP PLL delay and oscillator frequency counts */
1092 reg = clk_readl(UTMIP_PLL_CFG1);
1093 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1094
1095 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(
1096 utmi_parameters[i].enable_delay_count);
1097
1098 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1099 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(
1100 utmi_parameters[i].xtal_freq_count);
1101
1102 /* Remove power downs from UTMIP PLL control bits */
1103 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1104 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1105 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1106
1107 clk_writel(reg, UTMIP_PLL_CFG1);
1108}
1109
1110/* PLL Functions */
1111static int tegra30_pll_clk_wait_for_lock(struct clk_tegra *c, u32 lock_reg,
1112 u32 lock_bit)
1113{
1114 int ret = 0;
1115
1116#if USE_PLL_LOCK_BITS
1117 int i;
1118 for (i = 0; i < c->u.pll.lock_delay; i++) {
1119 if (clk_readl(lock_reg) & lock_bit) {
1120 udelay(PLL_POST_LOCK_DELAY);
1121 return 0;
1122 }
1123 udelay(2); /* timeout = 2 * lock time */
1124 }
1125 pr_err("Timed out waiting for lock bit on pll %s",
1126 __clk_get_name(hw->clk));
1127 ret = -1;
1128#else
1129 udelay(c->u.pll.lock_delay);
1130#endif
1131 return ret;
1132}
1133
1134static int tegra30_pll_clk_is_enabled(struct clk_hw *hw)
1135{
1136 struct clk_tegra *c = to_clk_tegra(hw);
1137 u32 val = clk_readl(c->reg + PLL_BASE);
1138
1139 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
1140 return c->state;
1141}
1142
1143static void tegra30_pll_clk_init(struct clk_hw *hw)
1144{
1145 struct clk_tegra *c = to_clk_tegra(hw);
1146
1147 if (c->flags & PLLU)
1148 tegra30_utmi_param_configure(hw);
1149}
1150
1151static int tegra30_pll_clk_enable(struct clk_hw *hw)
1152{
1153 struct clk_tegra *c = to_clk_tegra(hw);
1154 u32 val;
1155 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
1156
1157#if USE_PLL_LOCK_BITS
1158 val = clk_readl(c->reg + PLL_MISC(c));
1159 val |= PLL_MISC_LOCK_ENABLE(c);
1160 clk_writel(val, c->reg + PLL_MISC(c));
1161#endif
1162 val = clk_readl(c->reg + PLL_BASE);
1163 val &= ~PLL_BASE_BYPASS;
1164 val |= PLL_BASE_ENABLE;
1165 clk_writel(val, c->reg + PLL_BASE);
1166
1167 if (c->flags & PLLM) {
1168 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
1169 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
1170 pmc_writel(val, PMC_PLLP_WB0_OVERRIDE);
1171 }
1172
1173 tegra30_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK);
1174
1175 return 0;
1176}
1177
1178static void tegra30_pll_clk_disable(struct clk_hw *hw)
1179{
1180 struct clk_tegra *c = to_clk_tegra(hw);
1181 u32 val;
1182 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
1183
1184 val = clk_readl(c->reg);
1185 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
1186 clk_writel(val, c->reg);
1187
1188 if (c->flags & PLLM) {
1189 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
1190 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
1191 pmc_writel(val, PMC_PLLP_WB0_OVERRIDE);
1192 }
1193}
1194
1195static int tegra30_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1196 unsigned long parent_rate)
1197{
1198 struct clk_tegra *c = to_clk_tegra(hw);
1199 u32 val, p_div, old_base;
1200 unsigned long input_rate;
1201 const struct clk_pll_freq_table *sel;
1202 struct clk_pll_freq_table cfg;
1203
1204 if (c->flags & PLL_FIXED) {
1205 int ret = 0;
1206 if (rate != c->u.pll.fixed_rate) {
1207 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
1208 __func__, __clk_get_name(hw->clk),
1209 c->u.pll.fixed_rate, rate);
1210 ret = -EINVAL;
1211 }
1212 return ret;
1213 }
1214
1215 if (c->flags & PLLM) {
1216 if (rate != __clk_get_rate(hw->clk)) {
1217 pr_err("%s: Can not change memory %s rate in flight\n",
1218 __func__, __clk_get_name(hw->clk));
1219 return -EINVAL;
1220 }
1221 }
1222
1223 p_div = 0;
1224 input_rate = parent_rate;
1225
1226 /* Check if the target rate is tabulated */
1227 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
1228 if (sel->input_rate == input_rate && sel->output_rate == rate) {
1229 if (c->flags & PLLU) {
1230 BUG_ON(sel->p < 1 || sel->p > 2);
1231 if (sel->p == 1)
1232 p_div = PLLU_BASE_POST_DIV;
1233 } else {
1234 BUG_ON(sel->p < 1);
1235 for (val = sel->p; val > 1; val >>= 1)
1236 p_div++;
1237 p_div <<= PLL_BASE_DIVP_SHIFT;
1238 }
1239 break;
1240 }
1241 }
1242
1243 /* Configure out-of-table rate */
1244 if (sel->input_rate == 0) {
1245 unsigned long cfreq;
1246 BUG_ON(c->flags & PLLU);
1247 sel = &cfg;
1248
1249 switch (input_rate) {
1250 case 12000000:
1251 case 26000000:
1252 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
1253 break;
1254 case 13000000:
1255 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
1256 break;
1257 case 16800000:
1258 case 19200000:
1259 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
1260 break;
1261 default:
1262 pr_err("%s: Unexpected reference rate %lu\n",
1263 __func__, input_rate);
1264 BUG();
1265 }
1266
1267 /* Raise VCO to guarantee 0.5% accuracy */
1268 for (cfg.output_rate = rate; cfg.output_rate < 200 * cfreq;
1269 cfg.output_rate <<= 1)
1270 p_div++;
1271
1272 cfg.p = 0x1 << p_div;
1273 cfg.m = input_rate / cfreq;
1274 cfg.n = cfg.output_rate / cfreq;
1275 cfg.cpcon = OUT_OF_TABLE_CPCON;
1276
1277 if ((cfg.m > (PLL_BASE_DIVM_MASK >> PLL_BASE_DIVM_SHIFT)) ||
1278 (cfg.n > (PLL_BASE_DIVN_MASK >> PLL_BASE_DIVN_SHIFT)) ||
1279 (p_div > (PLL_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) ||
1280 (cfg.output_rate > c->u.pll.vco_max)) {
1281 pr_err("%s: Failed to set %s out-of-table rate %lu\n",
1282 __func__, __clk_get_name(hw->clk), rate);
1283 return -EINVAL;
1284 }
1285 p_div <<= PLL_BASE_DIVP_SHIFT;
1286 }
1287
1288 c->mul = sel->n;
1289 c->div = sel->m * sel->p;
1290
1291 old_base = val = clk_readl(c->reg + PLL_BASE);
1292 val &= ~(PLL_BASE_DIVM_MASK | PLL_BASE_DIVN_MASK |
1293 ((c->flags & PLLU) ? PLLU_BASE_POST_DIV : PLL_BASE_DIVP_MASK));
1294 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
1295 (sel->n << PLL_BASE_DIVN_SHIFT) | p_div;
1296 if (val == old_base)
1297 return 0;
1298
1299 if (c->state == ON) {
1300 tegra30_pll_clk_disable(hw);
1301 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
1302 }
1303 clk_writel(val, c->reg + PLL_BASE);
1304
1305 if (c->flags & PLL_HAS_CPCON) {
1306 val = clk_readl(c->reg + PLL_MISC(c));
1307 val &= ~PLL_MISC_CPCON_MASK;
1308 val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
1309 if (c->flags & (PLLU | PLLD)) {
1310 val &= ~PLL_MISC_LFCON_MASK;
1311 if (sel->n >= PLLDU_LFCON_SET_DIVN)
1312 val |= 0x1 << PLL_MISC_LFCON_SHIFT;
1313 } else if (c->flags & (PLLX | PLLM)) {
1314 val &= ~(0x1 << PLL_MISC_DCCON_SHIFT);
1315 if (rate >= (c->u.pll.vco_max >> 1))
1316 val |= 0x1 << PLL_MISC_DCCON_SHIFT;
1317 }
1318 clk_writel(val, c->reg + PLL_MISC(c));
1319 }
1320
1321 if (c->state == ON)
1322 tegra30_pll_clk_enable(hw);
1323
1324 c->u.pll.fixed_rate = rate;
1325
1326 return 0;
1327}
1328
1329static long tegra30_pll_round_rate(struct clk_hw *hw, unsigned long rate,
1330 unsigned long *prate)
1331{
1332 struct clk_tegra *c = to_clk_tegra(hw);
1333 unsigned long input_rate = *prate;
1334 u64 output_rate = *prate;
1335 const struct clk_pll_freq_table *sel;
1336 struct clk_pll_freq_table cfg;
1337 int mul;
1338 int div;
1339 u32 p_div;
1340 u32 val;
1341
1342 if (c->flags & PLL_FIXED)
1343 return c->u.pll.fixed_rate;
1344
1345 if (c->flags & PLLM)
1346 return __clk_get_rate(hw->clk);
1347
1348 p_div = 0;
1349 /* Check if the target rate is tabulated */
1350 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
1351 if (sel->input_rate == input_rate && sel->output_rate == rate) {
1352 if (c->flags & PLLU) {
1353 BUG_ON(sel->p < 1 || sel->p > 2);
1354 if (sel->p == 1)
1355 p_div = PLLU_BASE_POST_DIV;
1356 } else {
1357 BUG_ON(sel->p < 1);
1358 for (val = sel->p; val > 1; val >>= 1)
1359 p_div++;
1360 p_div <<= PLL_BASE_DIVP_SHIFT;
1361 }
1362 break;
1363 }
1364 }
1365
1366 if (sel->input_rate == 0) {
1367 unsigned long cfreq;
1368 BUG_ON(c->flags & PLLU);
1369 sel = &cfg;
1370
1371 switch (input_rate) {
1372 case 12000000:
1373 case 26000000:
1374 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
1375 break;
1376 case 13000000:
1377 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
1378 break;
1379 case 16800000:
1380 case 19200000:
1381 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
1382 break;
1383 default:
1384 pr_err("%s: Unexpected reference rate %lu\n",
1385 __func__, input_rate);
1386 BUG();
1387 }
1388
1389 /* Raise VCO to guarantee 0.5% accuracy */
1390 for (cfg.output_rate = rate; cfg.output_rate < 200 * cfreq;
1391 cfg.output_rate <<= 1)
1392 p_div++;
1393
1394 cfg.p = 0x1 << p_div;
1395 cfg.m = input_rate / cfreq;
1396 cfg.n = cfg.output_rate / cfreq;
1397 }
1398
1399 mul = sel->n;
1400 div = sel->m * sel->p;
1401
1402 output_rate *= mul;
1403 output_rate += div - 1; /* round up */
1404 do_div(output_rate, div);
1405
1406 return output_rate;
1407}
1408
1409static unsigned long tegra30_pll_recalc_rate(struct clk_hw *hw,
1410 unsigned long parent_rate)
1411{
1412 struct clk_tegra *c = to_clk_tegra(hw);
1413 u64 rate = parent_rate;
1414 u32 val = clk_readl(c->reg + PLL_BASE);
1415
1416 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
1417 const struct clk_pll_freq_table *sel;
1418 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
1419 if (sel->input_rate == parent_rate &&
1420 sel->output_rate == c->u.pll.fixed_rate) {
1421 c->mul = sel->n;
1422 c->div = sel->m * sel->p;
1423 break;
1424 }
1425 }
1426 pr_err("Clock %s has unknown fixed frequency\n",
1427 __clk_get_name(hw->clk));
1428 BUG();
1429 } else if (val & PLL_BASE_BYPASS) {
1430 c->mul = 1;
1431 c->div = 1;
1432 } else {
1433 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
1434 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
1435 if (c->flags & PLLU)
1436 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
1437 else
1438 c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >>
1439 PLL_BASE_DIVP_SHIFT));
1440 }
1441
1442 if (c->mul != 0 && c->div != 0) {
1443 rate *= c->mul;
1444 rate += c->div - 1; /* round up */
1445 do_div(rate, c->div);
1446 }
1447
1448 return rate;
1449}
1450
1451struct clk_ops tegra30_pll_ops = {
1452 .is_enabled = tegra30_pll_clk_is_enabled,
1453 .init = tegra30_pll_clk_init,
1454 .enable = tegra30_pll_clk_enable,
1455 .disable = tegra30_pll_clk_disable,
1456 .recalc_rate = tegra30_pll_recalc_rate,
1457 .round_rate = tegra30_pll_round_rate,
1458 .set_rate = tegra30_pll_clk_set_rate,
1459};
1460
1461int tegra30_plld_clk_cfg_ex(struct clk_hw *hw,
1462 enum tegra_clk_ex_param p, u32 setting)
1463{
1464 struct clk_tegra *c = to_clk_tegra(hw);
1465 u32 val, mask, reg;
1466
1467 switch (p) {
1468 case TEGRA_CLK_PLLD_CSI_OUT_ENB:
1469 mask = PLLD_BASE_CSI_CLKENABLE;
1470 reg = c->reg + PLL_BASE;
1471 break;
1472 case TEGRA_CLK_PLLD_DSI_OUT_ENB:
1473 mask = PLLD_MISC_DSI_CLKENABLE;
1474 reg = c->reg + PLL_MISC(c);
1475 break;
1476 case TEGRA_CLK_PLLD_MIPI_MUX_SEL:
1477 if (!(c->flags & PLL_ALT_MISC_REG)) {
1478 mask = PLLD_BASE_DSIB_MUX_MASK;
1479 reg = c->reg + PLL_BASE;
1480 break;
1481 }
1482 /* fall through - error since PLLD2 does not have MUX_SEL control */
1483 default:
1484 return -EINVAL;
1485 }
1486
1487 val = clk_readl(reg);
1488 if (setting)
1489 val |= mask;
1490 else
1491 val &= ~mask;
1492 clk_writel(val, reg);
1493 return 0;
1494}
1495
1496static int tegra30_plle_clk_is_enabled(struct clk_hw *hw)
1497{
1498 struct clk_tegra *c = to_clk_tegra(hw);
1499 u32 val;
1500
1501 val = clk_readl(c->reg + PLL_BASE);
1502 c->state = (val & PLLE_BASE_ENABLE) ? ON : OFF;
1503 return c->state;
1504}
1505
1506static void tegra30_plle_clk_disable(struct clk_hw *hw)
1507{
1508 struct clk_tegra *c = to_clk_tegra(hw);
1509 u32 val;
1510
1511 val = clk_readl(c->reg + PLL_BASE);
1512 val &= ~(PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE);
1513 clk_writel(val, c->reg + PLL_BASE);
1514}
1515
1516static void tegra30_plle_training(struct clk_tegra *c)
1517{
1518 u32 val;
1519
1520 /* PLLE is already disabled, and setup cleared;
1521 * create falling edge on PLLE IDDQ input */
1522 val = pmc_readl(PMC_SATA_PWRGT);
1523 val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
1524 pmc_writel(val, PMC_SATA_PWRGT);
1525
1526 val = pmc_readl(PMC_SATA_PWRGT);
1527 val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
1528 pmc_writel(val, PMC_SATA_PWRGT);
1529
1530 val = pmc_readl(PMC_SATA_PWRGT);
1531 val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
1532 pmc_writel(val, PMC_SATA_PWRGT);
1533
1534 do {
1535 val = clk_readl(c->reg + PLL_MISC(c));
1536 } while (!(val & PLLE_MISC_READY));
1537}
1538
1539static int tegra30_plle_configure(struct clk_hw *hw, bool force_training)
1540{
1541 struct clk_tegra *c = to_clk_tegra(hw);
1542 struct clk *parent = __clk_get_parent(hw->clk);
1543 const struct clk_pll_freq_table *sel;
1544 u32 val;
1545
1546 unsigned long rate = c->u.pll.fixed_rate;
1547 unsigned long input_rate = __clk_get_rate(parent);
1548
1549 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
1550 if (sel->input_rate == input_rate && sel->output_rate == rate)
1551 break;
1552 }
1553
1554 if (sel->input_rate == 0)
1555 return -ENOSYS;
1556
1557 /* disable PLLE, clear setup fiels */
1558 tegra30_plle_clk_disable(hw);
1559
1560 val = clk_readl(c->reg + PLL_MISC(c));
1561 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
1562 clk_writel(val, c->reg + PLL_MISC(c));
1563
1564 /* training */
1565 val = clk_readl(c->reg + PLL_MISC(c));
1566 if (force_training || (!(val & PLLE_MISC_READY)))
1567 tegra30_plle_training(c);
1568
1569 /* configure dividers, setup, disable SS */
1570 val = clk_readl(c->reg + PLL_BASE);
1571 val &= ~PLLE_BASE_DIV_MASK;
1572 val |= PLLE_BASE_DIV(sel->m, sel->n, sel->p, sel->cpcon);
1573 clk_writel(val, c->reg + PLL_BASE);
1574 c->mul = sel->n;
1575 c->div = sel->m * sel->p;
1576
1577 val = clk_readl(c->reg + PLL_MISC(c));
1578 val |= PLLE_MISC_SETUP_VALUE;
1579 val |= PLLE_MISC_LOCK_ENABLE;
1580 clk_writel(val, c->reg + PLL_MISC(c));
1581
1582 val = clk_readl(PLLE_SS_CTRL);
1583 val |= PLLE_SS_DISABLE;
1584 clk_writel(val, PLLE_SS_CTRL);
1585
1586 /* enable and lock PLLE*/
1587 val = clk_readl(c->reg + PLL_BASE);
1588 val |= (PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE);
1589 clk_writel(val, c->reg + PLL_BASE);
1590
1591 tegra30_pll_clk_wait_for_lock(c, c->reg + PLL_MISC(c), PLLE_MISC_LOCK);
1592
1593 return 0;
1594}
1595
1596static int tegra30_plle_clk_enable(struct clk_hw *hw)
1597{
1598 struct clk_tegra *c = to_clk_tegra(hw);
1599
1600 return tegra30_plle_configure(hw, !c->set);
1601}
1602
1603static unsigned long tegra30_plle_clk_recalc_rate(struct clk_hw *hw,
1604 unsigned long parent_rate)
1605{
1606 struct clk_tegra *c = to_clk_tegra(hw);
1607 unsigned long rate = parent_rate;
1608 u32 val;
1609
1610 val = clk_readl(c->reg + PLL_BASE);
1611 c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLLE_BASE_DIVN_SHIFT;
1612 c->div = (val & PLLE_BASE_DIVM_MASK) >> PLLE_BASE_DIVM_SHIFT;
1613 c->div *= (val & PLLE_BASE_DIVP_MASK) >> PLLE_BASE_DIVP_SHIFT;
1614
1615 if (c->mul != 0 && c->div != 0) {
1616 rate *= c->mul;
1617 rate += c->div - 1; /* round up */
1618 do_div(rate, c->div);
1619 }
1620 return rate;
1621}
1622
1623struct clk_ops tegra30_plle_ops = {
1624 .is_enabled = tegra30_plle_clk_is_enabled,
1625 .enable = tegra30_plle_clk_enable,
1626 .disable = tegra30_plle_clk_disable,
1627 .recalc_rate = tegra30_plle_clk_recalc_rate,
1628};
1629
1630/* Clock divider ops */
1631static int tegra30_pll_div_clk_is_enabled(struct clk_hw *hw)
1632{
1633 struct clk_tegra *c = to_clk_tegra(hw);
1634
1635 if (c->flags & DIV_U71) {
1636 u32 val = clk_readl(c->reg);
1637 val >>= c->reg_shift;
1638 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
1639 if (!(val & PLL_OUT_RESET_DISABLE))
1640 c->state = OFF;
1641 } else {
1642 c->state = ON;
1643 }
1644 return c->state;
1645}
1646
1647static int tegra30_pll_div_clk_enable(struct clk_hw *hw)
1648{
1649 struct clk_tegra *c = to_clk_tegra(hw);
1650 u32 val;
1651 u32 new_val;
1652
1653 pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
1654 if (c->flags & DIV_U71) {
1655 val = clk_readl(c->reg);
1656 new_val = val >> c->reg_shift;
1657 new_val &= 0xFFFF;
1658
1659 new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
1660
1661 val &= ~(0xFFFF << c->reg_shift);
1662 val |= new_val << c->reg_shift;
1663 clk_writel_delay(val, c->reg);
1664 return 0;
1665 } else if (c->flags & DIV_2) {
1666 return 0;
1667 }
1668 return -EINVAL;
1669}
1670
1671static void tegra30_pll_div_clk_disable(struct clk_hw *hw)
1672{
1673 struct clk_tegra *c = to_clk_tegra(hw);
1674 u32 val;
1675 u32 new_val;
1676
1677 pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
1678 if (c->flags & DIV_U71) {
1679 val = clk_readl(c->reg);
1680 new_val = val >> c->reg_shift;
1681 new_val &= 0xFFFF;
1682
1683 new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
1684
1685 val &= ~(0xFFFF << c->reg_shift);
1686 val |= new_val << c->reg_shift;
1687 clk_writel_delay(val, c->reg);
1688 }
1689}
1690
1691static int tegra30_pll_div_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1692 unsigned long parent_rate)
1693{
1694 struct clk_tegra *c = to_clk_tegra(hw);
1695 u32 val;
1696 u32 new_val;
1697 int divider_u71;
1698
1699 if (c->flags & DIV_U71) {
1700 divider_u71 = clk_div71_get_divider(
1701 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
1702 if (divider_u71 >= 0) {
1703 val = clk_readl(c->reg);
1704 new_val = val >> c->reg_shift;
1705 new_val &= 0xFFFF;
1706 if (c->flags & DIV_U71_FIXED)
1707 new_val |= PLL_OUT_OVERRIDE;
1708 new_val &= ~PLL_OUT_RATIO_MASK;
1709 new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
1710
1711 val &= ~(0xFFFF << c->reg_shift);
1712 val |= new_val << c->reg_shift;
1713 clk_writel_delay(val, c->reg);
1714 c->div = divider_u71 + 2;
1715 c->mul = 2;
1716 c->fixed_rate = rate;
1717 return 0;
1718 }
1719 } else if (c->flags & DIV_2) {
1720 c->fixed_rate = rate;
1721 return 0;
1722 }
1723
1724 return -EINVAL;
1725}
1726
1727static unsigned long tegra30_pll_div_clk_recalc_rate(struct clk_hw *hw,
1728 unsigned long parent_rate)
1729{
1730 struct clk_tegra *c = to_clk_tegra(hw);
1731 u64 rate = parent_rate;
1732
1733 if (c->flags & DIV_U71) {
1734 u32 divu71;
1735 u32 val = clk_readl(c->reg);
1736 val >>= c->reg_shift;
1737
1738 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
1739 c->div = (divu71 + 2);
1740 c->mul = 2;
1741 } else if (c->flags & DIV_2) {
1742 if (c->flags & (PLLD | PLLX)) {
1743 c->div = 2;
1744 c->mul = 1;
1745 } else
1746 BUG();
1747 } else {
1748 c->div = 1;
1749 c->mul = 1;
1750 }
1751 if (c->mul != 0 && c->div != 0) {
1752 rate *= c->mul;
1753 rate += c->div - 1; /* round up */
1754 do_div(rate, c->div);
1755 }
1756
1757 return rate;
1758}
1759
1760static long tegra30_pll_div_clk_round_rate(struct clk_hw *hw,
1761 unsigned long rate, unsigned long *prate)
1762{
1763 struct clk_tegra *c = to_clk_tegra(hw);
1764 unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
1765 int divider;
1766
1767 if (prate)
1768 parent_rate = *prate;
1769
1770 if (c->flags & DIV_U71) {
1771 divider = clk_div71_get_divider(
1772 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
1773 if (divider < 0)
1774 return divider;
1775 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
1776 } else if (c->flags & DIV_2) {
1777 *prate = rate * 2;
1778 return rate;
1779 }
1780
1781 return -EINVAL;
1782}
1783
1784struct clk_ops tegra30_pll_div_ops = {
1785 .is_enabled = tegra30_pll_div_clk_is_enabled,
1786 .enable = tegra30_pll_div_clk_enable,
1787 .disable = tegra30_pll_div_clk_disable,
1788 .set_rate = tegra30_pll_div_clk_set_rate,
1789 .recalc_rate = tegra30_pll_div_clk_recalc_rate,
1790 .round_rate = tegra30_pll_div_clk_round_rate,
1791};
1792
1793/* Periph clk ops */
1794static inline u32 periph_clk_source_mask(struct clk_tegra *c)
1795{
1796 if (c->flags & MUX8)
1797 return 7 << 29;
1798 else if (c->flags & MUX_PWM)
1799 return 3 << 28;
1800 else if (c->flags & MUX_CLK_OUT)
1801 return 3 << (c->u.periph.clk_num + 4);
1802 else if (c->flags & PLLD)
1803 return PLLD_BASE_DSIB_MUX_MASK;
1804 else
1805 return 3 << 30;
1806}
1807
1808static inline u32 periph_clk_source_shift(struct clk_tegra *c)
1809{
1810 if (c->flags & MUX8)
1811 return 29;
1812 else if (c->flags & MUX_PWM)
1813 return 28;
1814 else if (c->flags & MUX_CLK_OUT)
1815 return c->u.periph.clk_num + 4;
1816 else if (c->flags & PLLD)
1817 return PLLD_BASE_DSIB_MUX_SHIFT;
1818 else
1819 return 30;
1820}
1821
1822static int tegra30_periph_clk_is_enabled(struct clk_hw *hw)
1823{
1824 struct clk_tegra *c = to_clk_tegra(hw);
1825
1826 c->state = ON;
1827 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
1828 c->state = OFF;
1829 if (!(c->flags & PERIPH_NO_RESET))
1830 if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c))
1831 c->state = OFF;
1832 return c->state;
1833}
1834
1835static int tegra30_periph_clk_enable(struct clk_hw *hw)
1836{
1837 struct clk_tegra *c = to_clk_tegra(hw);
1838
1839 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
1840 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1)
1841 return 0;
1842
1843 clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_SET_REG(c));
1844 if (!(c->flags & PERIPH_NO_RESET) &&
1845 !(c->flags & PERIPH_MANUAL_RESET)) {
1846 if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) &
1847 PERIPH_CLK_TO_BIT(c)) {
1848 udelay(5); /* reset propagation delay */
1849 clk_writel(PERIPH_CLK_TO_BIT(c),
1850 PERIPH_CLK_TO_RST_CLR_REG(c));
1851 }
1852 }
1853 return 0;
1854}
1855
1856static void tegra30_periph_clk_disable(struct clk_hw *hw)
1857{
1858 struct clk_tegra *c = to_clk_tegra(hw);
1859 unsigned long val;
1860
1861 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
1862
1863 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 0)
1864 return;
1865
1866 /* If peripheral is in the APB bus then read the APB bus to
1867 * flush the write operation in apb bus. This will avoid the
1868 * peripheral access after disabling clock*/
1869 if (c->flags & PERIPH_ON_APB)
1870 val = chipid_readl();
1871
1872 clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c));
1873}
1874
1875void tegra30_periph_clk_reset(struct clk_hw *hw, bool assert)
1876{
1877 struct clk_tegra *c = to_clk_tegra(hw);
1878 unsigned long val;
1879
1880 if (!(c->flags & PERIPH_NO_RESET)) {
1881 if (assert) {
1882 /* If peripheral is in the APB bus then read the APB
1883 * bus to flush the write operation in apb bus. This
1884 * will avoid the peripheral access after disabling
1885 * clock */
1886 if (c->flags & PERIPH_ON_APB)
1887 val = chipid_readl();
1888
1889 clk_writel(PERIPH_CLK_TO_BIT(c),
1890 PERIPH_CLK_TO_RST_SET_REG(c));
1891 } else
1892 clk_writel(PERIPH_CLK_TO_BIT(c),
1893 PERIPH_CLK_TO_RST_CLR_REG(c));
1894 }
1895}
1896
1897static int tegra30_periph_clk_set_parent(struct clk_hw *hw, u8 index)
1898{
1899 struct clk_tegra *c = to_clk_tegra(hw);
1900 u32 val;
1901
1902 if (!(c->flags & MUX))
1903 return (index == 0) ? 0 : (-EINVAL);
1904
1905 val = clk_readl(c->reg);
1906 val &= ~periph_clk_source_mask(c);
1907 val |= (index << periph_clk_source_shift(c));
1908 clk_writel_delay(val, c->reg);
1909 return 0;
1910}
1911
1912static u8 tegra30_periph_clk_get_parent(struct clk_hw *hw)
1913{
1914 struct clk_tegra *c = to_clk_tegra(hw);
1915 u32 val = clk_readl(c->reg);
1916 int source = (val & periph_clk_source_mask(c)) >>
1917 periph_clk_source_shift(c);
1918
1919 if (!(c->flags & MUX))
1920 return 0;
1921
1922 return source;
1923}
1924
1925static int tegra30_periph_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1926 unsigned long parent_rate)
1927{
1928 struct clk_tegra *c = to_clk_tegra(hw);
1929 u32 val;
1930 int divider;
1931
1932 if (c->flags & DIV_U71) {
1933 divider = clk_div71_get_divider(
1934 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
1935 if (divider >= 0) {
1936 val = clk_readl(c->reg);
1937 val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
1938 val |= divider;
1939 if (c->flags & DIV_U71_UART) {
1940 if (divider)
1941 val |= PERIPH_CLK_UART_DIV_ENB;
1942 else
1943 val &= ~PERIPH_CLK_UART_DIV_ENB;
1944 }
1945 clk_writel_delay(val, c->reg);
1946 c->div = divider + 2;
1947 c->mul = 2;
1948 return 0;
1949 }
1950 } else if (c->flags & DIV_U16) {
1951 divider = clk_div16_get_divider(parent_rate, rate);
1952 if (divider >= 0) {
1953 val = clk_readl(c->reg);
1954 val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
1955 val |= divider;
1956 clk_writel_delay(val, c->reg);
1957 c->div = divider + 1;
1958 c->mul = 1;
1959 return 0;
1960 }
1961 } else if (parent_rate <= rate) {
1962 c->div = 1;
1963 c->mul = 1;
1964 return 0;
1965 }
1966 return -EINVAL;
1967}
1968
1969static long tegra30_periph_clk_round_rate(struct clk_hw *hw, unsigned long rate,
1970 unsigned long *prate)
1971{
1972 struct clk_tegra *c = to_clk_tegra(hw);
1973 unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
1974 int divider;
1975
1976 if (prate)
1977 parent_rate = *prate;
1978
1979 if (c->flags & DIV_U71) {
1980 divider = clk_div71_get_divider(
1981 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
1982 if (divider < 0)
1983 return divider;
1984
1985 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
1986 } else if (c->flags & DIV_U16) {
1987 divider = clk_div16_get_divider(parent_rate, rate);
1988 if (divider < 0)
1989 return divider;
1990 return DIV_ROUND_UP(parent_rate, divider + 1);
1991 }
1992 return -EINVAL;
1993}
1994
1995static unsigned long tegra30_periph_clk_recalc_rate(struct clk_hw *hw,
1996 unsigned long parent_rate)
1997{
1998 struct clk_tegra *c = to_clk_tegra(hw);
1999 u64 rate = parent_rate;
2000 u32 val = clk_readl(c->reg);
2001
2002 if (c->flags & DIV_U71) {
2003 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
2004 if ((c->flags & DIV_U71_UART) &&
2005 (!(val & PERIPH_CLK_UART_DIV_ENB))) {
2006 divu71 = 0;
2007 }
2008 if (c->flags & DIV_U71_IDLE) {
2009 val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK <<
2010 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
2011 val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL <<
2012 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
2013 clk_writel(val, c->reg);
2014 }
2015 c->div = divu71 + 2;
2016 c->mul = 2;
2017 } else if (c->flags & DIV_U16) {
2018 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
2019 c->div = divu16 + 1;
2020 c->mul = 1;
2021 } else {
2022 c->div = 1;
2023 c->mul = 1;
2024 }
2025
2026 if (c->mul != 0 && c->div != 0) {
2027 rate *= c->mul;
2028 rate += c->div - 1; /* round up */
2029 do_div(rate, c->div);
2030 }
2031 return rate;
2032}
2033
2034struct clk_ops tegra30_periph_clk_ops = {
2035 .is_enabled = tegra30_periph_clk_is_enabled,
2036 .enable = tegra30_periph_clk_enable,
2037 .disable = tegra30_periph_clk_disable,
2038 .set_parent = tegra30_periph_clk_set_parent,
2039 .get_parent = tegra30_periph_clk_get_parent,
2040 .set_rate = tegra30_periph_clk_set_rate,
2041 .round_rate = tegra30_periph_clk_round_rate,
2042 .recalc_rate = tegra30_periph_clk_recalc_rate,
2043};
2044
2045static int tegra30_dsib_clk_set_parent(struct clk_hw *hw, u8 index)
2046{
2047 struct clk *d = clk_get_sys(NULL, "pll_d");
2048 /* The DSIB parent selection bit is in PLLD base register */
2049 tegra_clk_cfg_ex(
2050 d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, index);
2051
2052 return 0;
2053}
2054
2055struct clk_ops tegra30_dsib_clk_ops = {
2056 .is_enabled = tegra30_periph_clk_is_enabled,
2057 .enable = &tegra30_periph_clk_enable,
2058 .disable = &tegra30_periph_clk_disable,
2059 .set_parent = &tegra30_dsib_clk_set_parent,
2060 .get_parent = &tegra30_periph_clk_get_parent,
2061 .set_rate = &tegra30_periph_clk_set_rate,
2062 .round_rate = &tegra30_periph_clk_round_rate,
2063 .recalc_rate = &tegra30_periph_clk_recalc_rate,
2064};
2065
2066/* Periph extended clock configuration ops */
2067int tegra30_vi_clk_cfg_ex(struct clk_hw *hw,
2068 enum tegra_clk_ex_param p, u32 setting)
2069{
2070 struct clk_tegra *c = to_clk_tegra(hw);
2071
2072 if (p == TEGRA_CLK_VI_INP_SEL) {
2073 u32 val = clk_readl(c->reg);
2074 val &= ~PERIPH_CLK_VI_SEL_EX_MASK;
2075 val |= (setting << PERIPH_CLK_VI_SEL_EX_SHIFT) &
2076 PERIPH_CLK_VI_SEL_EX_MASK;
2077 clk_writel(val, c->reg);
2078 return 0;
2079 }
2080 return -EINVAL;
2081}
2082
2083int tegra30_nand_clk_cfg_ex(struct clk_hw *hw,
2084 enum tegra_clk_ex_param p, u32 setting)
2085{
2086 struct clk_tegra *c = to_clk_tegra(hw);
2087
2088 if (p == TEGRA_CLK_NAND_PAD_DIV2_ENB) {
2089 u32 val = clk_readl(c->reg);
2090 if (setting)
2091 val |= PERIPH_CLK_NAND_DIV_EX_ENB;
2092 else
2093 val &= ~PERIPH_CLK_NAND_DIV_EX_ENB;
2094 clk_writel(val, c->reg);
2095 return 0;
2096 }
2097 return -EINVAL;
2098}
2099
2100int tegra30_dtv_clk_cfg_ex(struct clk_hw *hw,
2101 enum tegra_clk_ex_param p, u32 setting)
2102{
2103 struct clk_tegra *c = to_clk_tegra(hw);
2104
2105 if (p == TEGRA_CLK_DTV_INVERT) {
2106 u32 val = clk_readl(c->reg);
2107 if (setting)
2108 val |= PERIPH_CLK_DTV_POLARITY_INV;
2109 else
2110 val &= ~PERIPH_CLK_DTV_POLARITY_INV;
2111 clk_writel(val, c->reg);
2112 return 0;
2113 }
2114 return -EINVAL;
2115}
2116
2117/* Output clock ops */
2118
2119static DEFINE_SPINLOCK(clk_out_lock);
2120
2121static int tegra30_clk_out_is_enabled(struct clk_hw *hw)
2122{
2123 struct clk_tegra *c = to_clk_tegra(hw);
2124 u32 val = pmc_readl(c->reg);
2125
2126 c->state = (val & (0x1 << c->u.periph.clk_num)) ? ON : OFF;
2127 c->mul = 1;
2128 c->div = 1;
2129 return c->state;
2130}
2131
2132static int tegra30_clk_out_enable(struct clk_hw *hw)
2133{
2134 struct clk_tegra *c = to_clk_tegra(hw);
2135 u32 val;
2136 unsigned long flags;
2137
2138 spin_lock_irqsave(&clk_out_lock, flags);
2139 val = pmc_readl(c->reg);
2140 val |= (0x1 << c->u.periph.clk_num);
2141 pmc_writel(val, c->reg);
2142 spin_unlock_irqrestore(&clk_out_lock, flags);
2143
2144 return 0;
2145}
2146
2147static void tegra30_clk_out_disable(struct clk_hw *hw)
2148{
2149 struct clk_tegra *c = to_clk_tegra(hw);
2150 u32 val;
2151 unsigned long flags;
2152
2153 spin_lock_irqsave(&clk_out_lock, flags);
2154 val = pmc_readl(c->reg);
2155 val &= ~(0x1 << c->u.periph.clk_num);
2156 pmc_writel(val, c->reg);
2157 spin_unlock_irqrestore(&clk_out_lock, flags);
2158}
2159
2160static int tegra30_clk_out_set_parent(struct clk_hw *hw, u8 index)
2161{
2162 struct clk_tegra *c = to_clk_tegra(hw);
2163 u32 val;
2164 unsigned long flags;
2165
2166 spin_lock_irqsave(&clk_out_lock, flags);
2167 val = pmc_readl(c->reg);
2168 val &= ~periph_clk_source_mask(c);
2169 val |= (index << periph_clk_source_shift(c));
2170 pmc_writel(val, c->reg);
2171 spin_unlock_irqrestore(&clk_out_lock, flags);
2172
2173 return 0;
2174}
2175
2176static u8 tegra30_clk_out_get_parent(struct clk_hw *hw)
2177{
2178 struct clk_tegra *c = to_clk_tegra(hw);
2179 u32 val = pmc_readl(c->reg);
2180 int source;
2181
2182 source = (val & periph_clk_source_mask(c)) >>
2183 periph_clk_source_shift(c);
2184 return source;
2185}
2186
2187struct clk_ops tegra_clk_out_ops = {
2188 .is_enabled = tegra30_clk_out_is_enabled,
2189 .enable = tegra30_clk_out_enable,
2190 .disable = tegra30_clk_out_disable,
2191 .set_parent = tegra30_clk_out_set_parent,
2192 .get_parent = tegra30_clk_out_get_parent,
2193 .recalc_rate = tegra30_clk_fixed_recalc_rate,
2194};
2195
2196/* Clock doubler ops */
2197static int tegra30_clk_double_is_enabled(struct clk_hw *hw)
2198{
2199 struct clk_tegra *c = to_clk_tegra(hw);
2200
2201 c->state = ON;
2202 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
2203 c->state = OFF;
2204 return c->state;
2205};
2206
2207static int tegra30_clk_double_set_rate(struct clk_hw *hw, unsigned long rate,
2208 unsigned long parent_rate)
2209{
2210 struct clk_tegra *c = to_clk_tegra(hw);
2211 u32 val;
2212
2213 if (rate == parent_rate) {
2214 val = clk_readl(c->reg) | (0x1 << c->reg_shift);
2215 clk_writel(val, c->reg);
2216 c->mul = 1;
2217 c->div = 1;
2218 return 0;
2219 } else if (rate == 2 * parent_rate) {
2220 val = clk_readl(c->reg) & (~(0x1 << c->reg_shift));
2221 clk_writel(val, c->reg);
2222 c->mul = 2;
2223 c->div = 1;
2224 return 0;
2225 }
2226 return -EINVAL;
2227}
2228
2229static unsigned long tegra30_clk_double_recalc_rate(struct clk_hw *hw,
2230 unsigned long parent_rate)
2231{
2232 struct clk_tegra *c = to_clk_tegra(hw);
2233 u64 rate = parent_rate;
2234
2235 u32 val = clk_readl(c->reg);
2236 c->mul = val & (0x1 << c->reg_shift) ? 1 : 2;
2237 c->div = 1;
2238
2239 if (c->mul != 0 && c->div != 0) {
2240 rate *= c->mul;
2241 rate += c->div - 1; /* round up */
2242 do_div(rate, c->div);
2243 }
2244
2245 return rate;
2246}
2247
2248static long tegra30_clk_double_round_rate(struct clk_hw *hw, unsigned long rate,
2249 unsigned long *prate)
2250{
2251 unsigned long output_rate = *prate;
2252
2253 do_div(output_rate, 2);
2254 return output_rate;
2255}
2256
2257struct clk_ops tegra30_clk_double_ops = {
2258 .is_enabled = tegra30_clk_double_is_enabled,
2259 .enable = tegra30_periph_clk_enable,
2260 .disable = tegra30_periph_clk_disable,
2261 .recalc_rate = tegra30_clk_double_recalc_rate,
2262 .round_rate = tegra30_clk_double_round_rate,
2263 .set_rate = tegra30_clk_double_set_rate,
2264};
2265
2266/* Audio sync clock ops */
2267struct clk_ops tegra_sync_source_ops = {
2268 .recalc_rate = tegra30_clk_fixed_recalc_rate,
2269};
2270
2271static int tegra30_audio_sync_clk_is_enabled(struct clk_hw *hw)
2272{
2273 struct clk_tegra *c = to_clk_tegra(hw);
2274 u32 val = clk_readl(c->reg);
2275 c->state = (val & AUDIO_SYNC_DISABLE_BIT) ? OFF : ON;
2276 return c->state;
2277}
2278
2279static int tegra30_audio_sync_clk_enable(struct clk_hw *hw)
2280{
2281 struct clk_tegra *c = to_clk_tegra(hw);
2282 u32 val = clk_readl(c->reg);
2283 clk_writel((val & (~AUDIO_SYNC_DISABLE_BIT)), c->reg);
2284 return 0;
2285}
2286
2287static void tegra30_audio_sync_clk_disable(struct clk_hw *hw)
2288{
2289 struct clk_tegra *c = to_clk_tegra(hw);
2290 u32 val = clk_readl(c->reg);
2291 clk_writel((val | AUDIO_SYNC_DISABLE_BIT), c->reg);
2292}
2293
2294static int tegra30_audio_sync_clk_set_parent(struct clk_hw *hw, u8 index)
2295{
2296 struct clk_tegra *c = to_clk_tegra(hw);
2297 u32 val;
2298
2299 val = clk_readl(c->reg);
2300 val &= ~AUDIO_SYNC_SOURCE_MASK;
2301 val |= index;
2302
2303 clk_writel(val, c->reg);
2304 return 0;
2305}
2306
2307static u8 tegra30_audio_sync_clk_get_parent(struct clk_hw *hw)
2308{
2309 struct clk_tegra *c = to_clk_tegra(hw);
2310 u32 val = clk_readl(c->reg);
2311 int source;
2312
2313 source = val & AUDIO_SYNC_SOURCE_MASK;
2314 return source;
2315}
2316
2317struct clk_ops tegra30_audio_sync_clk_ops = {
2318 .is_enabled = tegra30_audio_sync_clk_is_enabled,
2319 .enable = tegra30_audio_sync_clk_enable,
2320 .disable = tegra30_audio_sync_clk_disable,
2321 .set_parent = tegra30_audio_sync_clk_set_parent,
2322 .get_parent = tegra30_audio_sync_clk_get_parent,
2323 .recalc_rate = tegra30_clk_fixed_recalc_rate,
2324};
2325
2326/* cml0 (pcie), and cml1 (sata) clock ops */
2327static int tegra30_cml_clk_is_enabled(struct clk_hw *hw)
2328{
2329 struct clk_tegra *c = to_clk_tegra(hw);
2330 u32 val = clk_readl(c->reg);
2331 c->state = val & (0x1 << c->u.periph.clk_num) ? ON : OFF;
2332 return c->state;
2333}
2334
2335static int tegra30_cml_clk_enable(struct clk_hw *hw)
2336{
2337 struct clk_tegra *c = to_clk_tegra(hw);
2338
2339 u32 val = clk_readl(c->reg);
2340 val |= (0x1 << c->u.periph.clk_num);
2341 clk_writel(val, c->reg);
2342
2343 return 0;
2344}
2345
2346static void tegra30_cml_clk_disable(struct clk_hw *hw)
2347{
2348 struct clk_tegra *c = to_clk_tegra(hw);
2349
2350 u32 val = clk_readl(c->reg);
2351 val &= ~(0x1 << c->u.periph.clk_num);
2352 clk_writel(val, c->reg);
2353}
2354
2355struct clk_ops tegra_cml_clk_ops = {
2356 .is_enabled = tegra30_cml_clk_is_enabled,
2357 .enable = tegra30_cml_clk_enable,
2358 .disable = tegra30_cml_clk_disable,
2359 .recalc_rate = tegra30_clk_fixed_recalc_rate,
2360};
2361
2362struct clk_ops tegra_pciex_clk_ops = {
2363 .recalc_rate = tegra30_clk_fixed_recalc_rate,
2364};
2365
2366/* Tegra30 CPU clock and reset control functions */
2367static void tegra30_wait_cpu_in_reset(u32 cpu)
2368{
2369 unsigned int reg;
2370
2371 do {
2372 reg = readl(reg_clk_base +
2373 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
2374 cpu_relax();
2375 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
2376
2377 return;
2378}
2379
2380static void tegra30_put_cpu_in_reset(u32 cpu)
2381{
2382 writel(CPU_RESET(cpu),
2383 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
2384 dmb();
2385}
2386
2387static void tegra30_cpu_out_of_reset(u32 cpu)
2388{
2389 writel(CPU_RESET(cpu),
2390 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
2391 wmb();
2392}
2393
2394static void tegra30_enable_cpu_clock(u32 cpu)
2395{
2396 unsigned int reg;
2397
2398 writel(CPU_CLOCK(cpu),
2399 reg_clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
2400 reg = readl(reg_clk_base +
2401 TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
2402}
2403
2404static void tegra30_disable_cpu_clock(u32 cpu)
2405{
2406
2407 unsigned int reg;
2408
2409 reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
2410 writel(reg | CPU_CLOCK(cpu),
2411 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
2412}
2413
2414#ifdef CONFIG_PM_SLEEP
2415static bool tegra30_cpu_rail_off_ready(void)
2416{
2417 unsigned int cpu_rst_status;
2418 int cpu_pwr_status;
2419
2420 cpu_rst_status = readl(reg_clk_base +
2421 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
2422 cpu_pwr_status = tegra_powergate_is_powered(TEGRA_POWERGATE_CPU1) ||
2423 tegra_powergate_is_powered(TEGRA_POWERGATE_CPU2) ||
2424 tegra_powergate_is_powered(TEGRA_POWERGATE_CPU3);
2425
2426 if (((cpu_rst_status & 0xE) != 0xE) || cpu_pwr_status)
2427 return false;
2428
2429 return true;
2430}
2431
2432static void tegra30_cpu_clock_suspend(void)
2433{
2434 /* switch coresite to clk_m, save off original source */
2435 tegra30_cpu_clk_sctx.clk_csite_src =
2436 readl(reg_clk_base + CLK_RESET_SOURCE_CSITE);
2437 writel(3<<30, reg_clk_base + CLK_RESET_SOURCE_CSITE);
2438
2439 tegra30_cpu_clk_sctx.cpu_burst =
2440 readl(reg_clk_base + CLK_RESET_CCLK_BURST);
2441 tegra30_cpu_clk_sctx.pllx_base =
2442 readl(reg_clk_base + CLK_RESET_PLLX_BASE);
2443 tegra30_cpu_clk_sctx.pllx_misc =
2444 readl(reg_clk_base + CLK_RESET_PLLX_MISC);
2445 tegra30_cpu_clk_sctx.cclk_divider =
2446 readl(reg_clk_base + CLK_RESET_CCLK_DIVIDER);
2447}
2448
2449static void tegra30_cpu_clock_resume(void)
2450{
2451 unsigned int reg, policy;
2452
2453 /* Is CPU complex already running on PLLX? */
2454 reg = readl(reg_clk_base + CLK_RESET_CCLK_BURST);
2455 policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF;
2456
2457 if (policy == CLK_RESET_CCLK_IDLE_POLICY)
2458 reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF;
2459 else if (policy == CLK_RESET_CCLK_RUN_POLICY)
2460 reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF;
2461 else
2462 BUG();
2463
2464 if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) {
2465 /* restore PLLX settings if CPU is on different PLL */
2466 writel(tegra30_cpu_clk_sctx.pllx_misc,
2467 reg_clk_base + CLK_RESET_PLLX_MISC);
2468 writel(tegra30_cpu_clk_sctx.pllx_base,
2469 reg_clk_base + CLK_RESET_PLLX_BASE);
2470
2471 /* wait for PLL stabilization if PLLX was enabled */
2472 if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30))
2473 udelay(300);
2474 }
2475
2476 /*
2477 * Restore original burst policy setting for calls resulting from CPU
2478 * LP2 in idle or system suspend.
2479 */
2480 writel(tegra30_cpu_clk_sctx.cclk_divider,
2481 reg_clk_base + CLK_RESET_CCLK_DIVIDER);
2482 writel(tegra30_cpu_clk_sctx.cpu_burst,
2483 reg_clk_base + CLK_RESET_CCLK_BURST);
2484
2485 writel(tegra30_cpu_clk_sctx.clk_csite_src,
2486 reg_clk_base + CLK_RESET_SOURCE_CSITE);
2487}
2488#endif
2489
2490static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
2491 .wait_for_reset = tegra30_wait_cpu_in_reset,
2492 .put_in_reset = tegra30_put_cpu_in_reset,
2493 .out_of_reset = tegra30_cpu_out_of_reset,
2494 .enable_clock = tegra30_enable_cpu_clock,
2495 .disable_clock = tegra30_disable_cpu_clock,
2496#ifdef CONFIG_PM_SLEEP
2497 .rail_off_ready = tegra30_cpu_rail_off_ready,
2498 .suspend = tegra30_cpu_clock_suspend,
2499 .resume = tegra30_cpu_clock_resume,
2500#endif
2501};
2502
2503void __init tegra30_cpu_car_ops_init(void)
2504{
2505 tegra_cpu_car_ops = &tegra30_cpu_car_ops;
2506}
diff --git a/arch/arm/mach-tegra/tegra30_clocks.h b/arch/arm/mach-tegra/tegra30_clocks.h
deleted file mode 100644
index 7a34adb2f72d..000000000000
--- a/arch/arm/mach-tegra/tegra30_clocks.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef __MACH_TEGRA30_CLOCK_H
18#define __MACH_TEGRA30_CLOCK_H
19
20extern struct clk_ops tegra30_clk_32k_ops;
21extern struct clk_ops tegra30_clk_m_ops;
22extern struct clk_ops tegra_clk_m_div_ops;
23extern struct clk_ops tegra_pll_ref_ops;
24extern struct clk_ops tegra30_pll_ops;
25extern struct clk_ops tegra30_pll_div_ops;
26extern struct clk_ops tegra_plld_ops;
27extern struct clk_ops tegra30_plle_ops;
28extern struct clk_ops tegra_cml_clk_ops;
29extern struct clk_ops tegra_pciex_clk_ops;
30extern struct clk_ops tegra_sync_source_ops;
31extern struct clk_ops tegra30_audio_sync_clk_ops;
32extern struct clk_ops tegra30_clk_double_ops;
33extern struct clk_ops tegra_clk_out_ops;
34extern struct clk_ops tegra30_super_ops;
35extern struct clk_ops tegra30_blink_clk_ops;
36extern struct clk_ops tegra30_twd_ops;
37extern struct clk_ops tegra30_bus_ops;
38extern struct clk_ops tegra30_periph_clk_ops;
39extern struct clk_ops tegra30_dsib_clk_ops;
40extern struct clk_ops tegra_nand_clk_ops;
41extern struct clk_ops tegra_vi_clk_ops;
42extern struct clk_ops tegra_dtv_clk_ops;
43extern struct clk_ops tegra_clk_shared_bus_ops;
44
45int tegra30_plld_clk_cfg_ex(struct clk_hw *hw,
46 enum tegra_clk_ex_param p, u32 setting);
47void tegra30_periph_clk_reset(struct clk_hw *hw, bool assert);
48int tegra30_vi_clk_cfg_ex(struct clk_hw *hw,
49 enum tegra_clk_ex_param p, u32 setting);
50int tegra30_nand_clk_cfg_ex(struct clk_hw *hw,
51 enum tegra_clk_ex_param p, u32 setting);
52int tegra30_dtv_clk_cfg_ex(struct clk_hw *hw,
53 enum tegra_clk_ex_param p, u32 setting);
54#endif
diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c
deleted file mode 100644
index 6942c7add3bb..000000000000
--- a/arch/arm/mach-tegra/tegra30_clocks_data.c
+++ /dev/null
@@ -1,1425 +0,0 @@
1/*
2 * arch/arm/mach-tegra/tegra30_clocks.c
3 *
4 * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
18 *
19 */
20
21#include <linux/clk-private.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/list.h>
25#include <linux/spinlock.h>
26#include <linux/delay.h>
27#include <linux/err.h>
28#include <linux/io.h>
29#include <linux/clk.h>
30#include <linux/cpufreq.h>
31
32#include "clock.h"
33#include "fuse.h"
34#include "tegra30_clocks.h"
35#include "tegra_cpu_car.h"
36
37#define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags, \
38 _parent_names, _parents, _parent) \
39 static struct clk tegra_##_name = { \
40 .hw = &tegra_##_name##_hw.hw, \
41 .name = #_name, \
42 .rate = _rate, \
43 .ops = _ops, \
44 .flags = _flags, \
45 .parent_names = _parent_names, \
46 .parents = _parents, \
47 .num_parents = ARRAY_SIZE(_parent_names), \
48 .parent = _parent, \
49 };
50
51static struct clk tegra_clk_32k;
52static struct clk_tegra tegra_clk_32k_hw = {
53 .hw = {
54 .clk = &tegra_clk_32k,
55 },
56 .fixed_rate = 32768,
57};
58static struct clk tegra_clk_32k = {
59 .name = "clk_32k",
60 .hw = &tegra_clk_32k_hw.hw,
61 .ops = &tegra30_clk_32k_ops,
62 .flags = CLK_IS_ROOT,
63};
64
65static struct clk tegra_clk_m;
66static struct clk_tegra tegra_clk_m_hw = {
67 .hw = {
68 .clk = &tegra_clk_m,
69 },
70 .flags = ENABLE_ON_INIT,
71 .reg = 0x1fc,
72 .reg_shift = 28,
73 .max_rate = 48000000,
74};
75static struct clk tegra_clk_m = {
76 .name = "clk_m",
77 .hw = &tegra_clk_m_hw.hw,
78 .ops = &tegra30_clk_m_ops,
79 .flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED,
80};
81
82static const char *clk_m_div_parent_names[] = {
83 "clk_m",
84};
85
86static struct clk *clk_m_div_parents[] = {
87 &tegra_clk_m,
88};
89
90static struct clk tegra_clk_m_div2;
91static struct clk_tegra tegra_clk_m_div2_hw = {
92 .hw = {
93 .clk = &tegra_clk_m_div2,
94 },
95 .mul = 1,
96 .div = 2,
97 .max_rate = 24000000,
98};
99DEFINE_CLK_TEGRA(clk_m_div2, 0, &tegra_clk_m_div_ops, 0,
100 clk_m_div_parent_names, clk_m_div_parents, &tegra_clk_m);
101
102static struct clk tegra_clk_m_div4;
103static struct clk_tegra tegra_clk_m_div4_hw = {
104 .hw = {
105 .clk = &tegra_clk_m_div4,
106 },
107 .mul = 1,
108 .div = 4,
109 .max_rate = 12000000,
110};
111DEFINE_CLK_TEGRA(clk_m_div4, 0, &tegra_clk_m_div_ops, 0,
112 clk_m_div_parent_names, clk_m_div_parents, &tegra_clk_m);
113
114static struct clk tegra_pll_ref;
115static struct clk_tegra tegra_pll_ref_hw = {
116 .hw = {
117 .clk = &tegra_pll_ref,
118 },
119 .flags = ENABLE_ON_INIT,
120 .max_rate = 26000000,
121};
122DEFINE_CLK_TEGRA(pll_ref, 0, &tegra_pll_ref_ops, 0, clk_m_div_parent_names,
123 clk_m_div_parents, &tegra_clk_m);
124
125#define DEFINE_PLL(_name, _flags, _reg, _max_rate, _input_min, \
126 _input_max, _cf_min, _cf_max, _vco_min, \
127 _vco_max, _freq_table, _lock_delay, _ops, \
128 _fixed_rate, _clk_cfg_ex, _parent) \
129 static struct clk tegra_##_name; \
130 static const char *_name##_parent_names[] = { \
131 #_parent, \
132 }; \
133 static struct clk *_name##_parents[] = { \
134 &tegra_##_parent, \
135 }; \
136 static struct clk_tegra tegra_##_name##_hw = { \
137 .hw = { \
138 .clk = &tegra_##_name, \
139 }, \
140 .flags = _flags, \
141 .reg = _reg, \
142 .max_rate = _max_rate, \
143 .u.pll = { \
144 .input_min = _input_min, \
145 .input_max = _input_max, \
146 .cf_min = _cf_min, \
147 .cf_max = _cf_max, \
148 .vco_min = _vco_min, \
149 .vco_max = _vco_max, \
150 .freq_table = _freq_table, \
151 .lock_delay = _lock_delay, \
152 .fixed_rate = _fixed_rate, \
153 }, \
154 .clk_cfg_ex = _clk_cfg_ex, \
155 }; \
156 DEFINE_CLK_TEGRA(_name, 0, &_ops, CLK_IGNORE_UNUSED, \
157 _name##_parent_names, _name##_parents, \
158 &tegra_##_parent);
159
160#define DEFINE_PLL_OUT(_name, _flags, _reg, _reg_shift, \
161 _max_rate, _ops, _parent, _clk_flags) \
162 static const char *_name##_parent_names[] = { \
163 #_parent, \
164 }; \
165 static struct clk *_name##_parents[] = { \
166 &tegra_##_parent, \
167 }; \
168 static struct clk tegra_##_name; \
169 static struct clk_tegra tegra_##_name##_hw = { \
170 .hw = { \
171 .clk = &tegra_##_name, \
172 }, \
173 .flags = _flags, \
174 .reg = _reg, \
175 .max_rate = _max_rate, \
176 .reg_shift = _reg_shift, \
177 }; \
178 DEFINE_CLK_TEGRA(_name, 0, &tegra30_pll_div_ops, \
179 _clk_flags, _name##_parent_names, \
180 _name##_parents, &tegra_##_parent);
181
182static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
183 { 12000000, 1040000000, 520, 6, 1, 8},
184 { 13000000, 1040000000, 480, 6, 1, 8},
185 { 16800000, 1040000000, 495, 8, 1, 8}, /* actual: 1039.5 MHz */
186 { 19200000, 1040000000, 325, 6, 1, 6},
187 { 26000000, 1040000000, 520, 13, 1, 8},
188
189 { 12000000, 832000000, 416, 6, 1, 8},
190 { 13000000, 832000000, 832, 13, 1, 8},
191 { 16800000, 832000000, 396, 8, 1, 8}, /* actual: 831.6 MHz */
192 { 19200000, 832000000, 260, 6, 1, 8},
193 { 26000000, 832000000, 416, 13, 1, 8},
194
195 { 12000000, 624000000, 624, 12, 1, 8},
196 { 13000000, 624000000, 624, 13, 1, 8},
197 { 16800000, 600000000, 520, 14, 1, 8},
198 { 19200000, 624000000, 520, 16, 1, 8},
199 { 26000000, 624000000, 624, 26, 1, 8},
200
201 { 12000000, 600000000, 600, 12, 1, 8},
202 { 13000000, 600000000, 600, 13, 1, 8},
203 { 16800000, 600000000, 500, 14, 1, 8},
204 { 19200000, 600000000, 375, 12, 1, 6},
205 { 26000000, 600000000, 600, 26, 1, 8},
206
207 { 12000000, 520000000, 520, 12, 1, 8},
208 { 13000000, 520000000, 520, 13, 1, 8},
209 { 16800000, 520000000, 495, 16, 1, 8}, /* actual: 519.75 MHz */
210 { 19200000, 520000000, 325, 12, 1, 6},
211 { 26000000, 520000000, 520, 26, 1, 8},
212
213 { 12000000, 416000000, 416, 12, 1, 8},
214 { 13000000, 416000000, 416, 13, 1, 8},
215 { 16800000, 416000000, 396, 16, 1, 8}, /* actual: 415.8 MHz */
216 { 19200000, 416000000, 260, 12, 1, 6},
217 { 26000000, 416000000, 416, 26, 1, 8},
218 { 0, 0, 0, 0, 0, 0 },
219};
220
221DEFINE_PLL(pll_c, PLL_HAS_CPCON, 0x80, 1400000000, 2000000, 31000000, 1000000,
222 6000000, 20000000, 1400000000, tegra_pll_c_freq_table, 300,
223 tegra30_pll_ops, 0, NULL, pll_ref);
224
225DEFINE_PLL_OUT(pll_c_out1, DIV_U71, 0x84, 0, 700000000,
226 tegra30_pll_div_ops, pll_c, CLK_IGNORE_UNUSED);
227
228static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
229 { 12000000, 666000000, 666, 12, 1, 8},
230 { 13000000, 666000000, 666, 13, 1, 8},
231 { 16800000, 666000000, 555, 14, 1, 8},
232 { 19200000, 666000000, 555, 16, 1, 8},
233 { 26000000, 666000000, 666, 26, 1, 8},
234 { 12000000, 600000000, 600, 12, 1, 8},
235 { 13000000, 600000000, 600, 13, 1, 8},
236 { 16800000, 600000000, 500, 14, 1, 8},
237 { 19200000, 600000000, 375, 12, 1, 6},
238 { 26000000, 600000000, 600, 26, 1, 8},
239 { 0, 0, 0, 0, 0, 0 },
240};
241
242DEFINE_PLL(pll_m, PLL_HAS_CPCON | PLLM, 0x90, 800000000, 2000000, 31000000,
243 1000000, 6000000, 20000000, 1200000000, tegra_pll_m_freq_table,
244 300, tegra30_pll_ops, 0, NULL, pll_ref);
245
246DEFINE_PLL_OUT(pll_m_out1, DIV_U71, 0x94, 0, 600000000,
247 tegra30_pll_div_ops, pll_m, CLK_IGNORE_UNUSED);
248
249static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
250 { 12000000, 216000000, 432, 12, 2, 8},
251 { 13000000, 216000000, 432, 13, 2, 8},
252 { 16800000, 216000000, 360, 14, 2, 8},
253 { 19200000, 216000000, 360, 16, 2, 8},
254 { 26000000, 216000000, 432, 26, 2, 8},
255 { 0, 0, 0, 0, 0, 0 },
256};
257
258DEFINE_PLL(pll_p, ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, 0xa0, 432000000,
259 2000000, 31000000, 1000000, 6000000, 20000000, 1400000000,
260 tegra_pll_p_freq_table, 300, tegra30_pll_ops, 408000000, NULL,
261 pll_ref);
262
263DEFINE_PLL_OUT(pll_p_out1, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4,
264 0, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
265DEFINE_PLL_OUT(pll_p_out2, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4,
266 16, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
267DEFINE_PLL_OUT(pll_p_out3, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8,
268 0, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
269DEFINE_PLL_OUT(pll_p_out4, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8,
270 16, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
271
272static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
273 { 9600000, 564480000, 294, 5, 1, 4},
274 { 9600000, 552960000, 288, 5, 1, 4},
275 { 9600000, 24000000, 5, 2, 1, 1},
276
277 { 28800000, 56448000, 49, 25, 1, 1},
278 { 28800000, 73728000, 64, 25, 1, 1},
279 { 28800000, 24000000, 5, 6, 1, 1},
280 { 0, 0, 0, 0, 0, 0 },
281};
282
283DEFINE_PLL(pll_a, PLL_HAS_CPCON, 0xb0, 700000000, 2000000, 31000000, 1000000,
284 6000000, 20000000, 1400000000, tegra_pll_a_freq_table,
285 300, tegra30_pll_ops, 0, NULL, pll_p_out1);
286
287DEFINE_PLL_OUT(pll_a_out0, DIV_U71, 0xb4, 0, 100000000, tegra30_pll_div_ops,
288 pll_a, CLK_IGNORE_UNUSED);
289
290static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
291 { 12000000, 216000000, 216, 12, 1, 4},
292 { 13000000, 216000000, 216, 13, 1, 4},
293 { 16800000, 216000000, 180, 14, 1, 4},
294 { 19200000, 216000000, 180, 16, 1, 4},
295 { 26000000, 216000000, 216, 26, 1, 4},
296
297 { 12000000, 594000000, 594, 12, 1, 8},
298 { 13000000, 594000000, 594, 13, 1, 8},
299 { 16800000, 594000000, 495, 14, 1, 8},
300 { 19200000, 594000000, 495, 16, 1, 8},
301 { 26000000, 594000000, 594, 26, 1, 8},
302
303 { 12000000, 1000000000, 1000, 12, 1, 12},
304 { 13000000, 1000000000, 1000, 13, 1, 12},
305 { 19200000, 1000000000, 625, 12, 1, 8},
306 { 26000000, 1000000000, 1000, 26, 1, 12},
307
308 { 0, 0, 0, 0, 0, 0 },
309};
310
311DEFINE_PLL(pll_d, PLL_HAS_CPCON | PLLD, 0xd0, 1000000000, 2000000, 40000000,
312 1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table,
313 1000, tegra30_pll_ops, 0, tegra30_plld_clk_cfg_ex, pll_ref);
314
315DEFINE_PLL_OUT(pll_d_out0, DIV_2 | PLLD, 0, 0, 500000000, tegra30_pll_div_ops,
316 pll_d, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
317
318DEFINE_PLL(pll_d2, PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD, 0x4b8, 1000000000,
319 2000000, 40000000, 1000000, 6000000, 40000000, 1000000000,
320 tegra_pll_d_freq_table, 1000, tegra30_pll_ops, 0, NULL,
321 pll_ref);
322
323DEFINE_PLL_OUT(pll_d2_out0, DIV_2 | PLLD, 0, 0, 500000000, tegra30_pll_div_ops,
324 pll_d2, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
325
326static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
327 { 12000000, 480000000, 960, 12, 2, 12},
328 { 13000000, 480000000, 960, 13, 2, 12},
329 { 16800000, 480000000, 400, 7, 2, 5},
330 { 19200000, 480000000, 200, 4, 2, 3},
331 { 26000000, 480000000, 960, 26, 2, 12},
332 { 0, 0, 0, 0, 0, 0 },
333};
334
335DEFINE_PLL(pll_u, PLL_HAS_CPCON | PLLU, 0xc0, 480000000, 2000000, 40000000,
336 1000000, 6000000, 48000000, 960000000, tegra_pll_u_freq_table,
337 1000, tegra30_pll_ops, 0, NULL, pll_ref);
338
339static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
340 /* 1.7 GHz */
341 { 12000000, 1700000000, 850, 6, 1, 8},
342 { 13000000, 1700000000, 915, 7, 1, 8}, /* actual: 1699.2 MHz */
343 { 16800000, 1700000000, 708, 7, 1, 8}, /* actual: 1699.2 MHz */
344 { 19200000, 1700000000, 885, 10, 1, 8}, /* actual: 1699.2 MHz */
345 { 26000000, 1700000000, 850, 13, 1, 8},
346
347 /* 1.6 GHz */
348 { 12000000, 1600000000, 800, 6, 1, 8},
349 { 13000000, 1600000000, 738, 6, 1, 8}, /* actual: 1599.0 MHz */
350 { 16800000, 1600000000, 857, 9, 1, 8}, /* actual: 1599.7 MHz */
351 { 19200000, 1600000000, 500, 6, 1, 8},
352 { 26000000, 1600000000, 800, 13, 1, 8},
353
354 /* 1.5 GHz */
355 { 12000000, 1500000000, 750, 6, 1, 8},
356 { 13000000, 1500000000, 923, 8, 1, 8}, /* actual: 1499.8 MHz */
357 { 16800000, 1500000000, 625, 7, 1, 8},
358 { 19200000, 1500000000, 625, 8, 1, 8},
359 { 26000000, 1500000000, 750, 13, 1, 8},
360
361 /* 1.4 GHz */
362 { 12000000, 1400000000, 700, 6, 1, 8},
363 { 13000000, 1400000000, 969, 9, 1, 8}, /* actual: 1399.7 MHz */
364 { 16800000, 1400000000, 1000, 12, 1, 8},
365 { 19200000, 1400000000, 875, 12, 1, 8},
366 { 26000000, 1400000000, 700, 13, 1, 8},
367
368 /* 1.3 GHz */
369 { 12000000, 1300000000, 975, 9, 1, 8},
370 { 13000000, 1300000000, 1000, 10, 1, 8},
371 { 16800000, 1300000000, 928, 12, 1, 8}, /* actual: 1299.2 MHz */
372 { 19200000, 1300000000, 812, 12, 1, 8}, /* actual: 1299.2 MHz */
373 { 26000000, 1300000000, 650, 13, 1, 8},
374
375 /* 1.2 GHz */
376 { 12000000, 1200000000, 1000, 10, 1, 8},
377 { 13000000, 1200000000, 923, 10, 1, 8}, /* actual: 1199.9 MHz */
378 { 16800000, 1200000000, 1000, 14, 1, 8},
379 { 19200000, 1200000000, 1000, 16, 1, 8},
380 { 26000000, 1200000000, 600, 13, 1, 8},
381
382 /* 1.1 GHz */
383 { 12000000, 1100000000, 825, 9, 1, 8},
384 { 13000000, 1100000000, 846, 10, 1, 8}, /* actual: 1099.8 MHz */
385 { 16800000, 1100000000, 982, 15, 1, 8}, /* actual: 1099.8 MHz */
386 { 19200000, 1100000000, 859, 15, 1, 8}, /* actual: 1099.5 MHz */
387 { 26000000, 1100000000, 550, 13, 1, 8},
388
389 /* 1 GHz */
390 { 12000000, 1000000000, 1000, 12, 1, 8},
391 { 13000000, 1000000000, 1000, 13, 1, 8},
392 { 16800000, 1000000000, 833, 14, 1, 8}, /* actual: 999.6 MHz */
393 { 19200000, 1000000000, 625, 12, 1, 8},
394 { 26000000, 1000000000, 1000, 26, 1, 8},
395
396 { 0, 0, 0, 0, 0, 0 },
397};
398
399DEFINE_PLL(pll_x, PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX, 0xe0, 1700000000,
400 2000000, 31000000, 1000000, 6000000, 20000000, 1700000000,
401 tegra_pll_x_freq_table, 300, tegra30_pll_ops, 0, NULL, pll_ref);
402
403DEFINE_PLL_OUT(pll_x_out0, DIV_2 | PLLX, 0, 0, 850000000, tegra30_pll_div_ops,
404 pll_x, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
405
406static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
407 /* PLLE special case: use cpcon field to store cml divider value */
408 { 12000000, 100000000, 150, 1, 18, 11},
409 { 216000000, 100000000, 200, 18, 24, 13},
410 { 0, 0, 0, 0, 0, 0 },
411};
412
413DEFINE_PLL(pll_e, PLL_ALT_MISC_REG, 0xe8, 100000000, 2000000, 216000000,
414 12000000, 12000000, 1200000000, 2400000000U,
415 tegra_pll_e_freq_table, 300, tegra30_plle_ops, 100000000, NULL,
416 pll_ref);
417
418static const char *mux_plle[] = {
419 "pll_e",
420};
421
422static struct clk *mux_plle_p[] = {
423 &tegra_pll_e,
424};
425
426static struct clk tegra_cml0;
427static struct clk_tegra tegra_cml0_hw = {
428 .hw = {
429 .clk = &tegra_cml0,
430 },
431 .reg = 0x48c,
432 .fixed_rate = 100000000,
433 .u.periph = {
434 .clk_num = 0,
435 },
436};
437DEFINE_CLK_TEGRA(cml0, 0, &tegra_cml_clk_ops, 0, mux_plle,
438 mux_plle_p, &tegra_pll_e);
439
440static struct clk tegra_cml1;
441static struct clk_tegra tegra_cml1_hw = {
442 .hw = {
443 .clk = &tegra_cml1,
444 },
445 .reg = 0x48c,
446 .fixed_rate = 100000000,
447 .u.periph = {
448 .clk_num = 1,
449 },
450};
451DEFINE_CLK_TEGRA(cml1, 0, &tegra_cml_clk_ops, 0, mux_plle,
452 mux_plle_p, &tegra_pll_e);
453
454static struct clk tegra_pciex;
455static struct clk_tegra tegra_pciex_hw = {
456 .hw = {
457 .clk = &tegra_pciex,
458 },
459 .reg = 0x48c,
460 .fixed_rate = 100000000,
461 .reset = tegra30_periph_clk_reset,
462 .u.periph = {
463 .clk_num = 74,
464 },
465};
466DEFINE_CLK_TEGRA(pciex, 0, &tegra_pciex_clk_ops, 0, mux_plle,
467 mux_plle_p, &tegra_pll_e);
468
469#define SYNC_SOURCE(_name) \
470 static struct clk tegra_##_name##_sync; \
471 static struct clk_tegra tegra_##_name##_sync_hw = { \
472 .hw = { \
473 .clk = &tegra_##_name##_sync, \
474 }, \
475 .max_rate = 24000000, \
476 .fixed_rate = 24000000, \
477 }; \
478 static struct clk tegra_##_name##_sync = { \
479 .name = #_name "_sync", \
480 .hw = &tegra_##_name##_sync_hw.hw, \
481 .ops = &tegra_sync_source_ops, \
482 .flags = CLK_IS_ROOT, \
483 };
484
485SYNC_SOURCE(spdif_in);
486SYNC_SOURCE(i2s0);
487SYNC_SOURCE(i2s1);
488SYNC_SOURCE(i2s2);
489SYNC_SOURCE(i2s3);
490SYNC_SOURCE(i2s4);
491SYNC_SOURCE(vimclk);
492
493static struct clk *tegra_sync_source_list[] = {
494 &tegra_spdif_in_sync,
495 &tegra_i2s0_sync,
496 &tegra_i2s1_sync,
497 &tegra_i2s2_sync,
498 &tegra_i2s3_sync,
499 &tegra_i2s4_sync,
500 &tegra_vimclk_sync,
501};
502
503static const char *mux_audio_sync_clk[] = {
504 "spdif_in_sync",
505 "i2s0_sync",
506 "i2s1_sync",
507 "i2s2_sync",
508 "i2s3_sync",
509 "i2s4_sync",
510 "vimclk_sync",
511};
512
513#define AUDIO_SYNC_CLK(_name, _index) \
514 static struct clk tegra_##_name; \
515 static struct clk_tegra tegra_##_name##_hw = { \
516 .hw = { \
517 .clk = &tegra_##_name, \
518 }, \
519 .max_rate = 24000000, \
520 .reg = 0x4A0 + (_index) * 4, \
521 }; \
522 static struct clk tegra_##_name = { \
523 .name = #_name, \
524 .ops = &tegra30_audio_sync_clk_ops, \
525 .hw = &tegra_##_name##_hw.hw, \
526 .parent_names = mux_audio_sync_clk, \
527 .parents = tegra_sync_source_list, \
528 .num_parents = ARRAY_SIZE(mux_audio_sync_clk), \
529 };
530
531AUDIO_SYNC_CLK(audio0, 0);
532AUDIO_SYNC_CLK(audio1, 1);
533AUDIO_SYNC_CLK(audio2, 2);
534AUDIO_SYNC_CLK(audio3, 3);
535AUDIO_SYNC_CLK(audio4, 4);
536AUDIO_SYNC_CLK(audio5, 5);
537
538static struct clk *tegra_clk_audio_list[] = {
539 &tegra_audio0,
540 &tegra_audio1,
541 &tegra_audio2,
542 &tegra_audio3,
543 &tegra_audio4,
544 &tegra_audio5, /* SPDIF */
545};
546
547#define AUDIO_SYNC_2X_CLK(_name, _index) \
548 static const char *_name##_parent_names[] = { \
549 "tegra_" #_name, \
550 }; \
551 static struct clk *_name##_parents[] = { \
552 &tegra_##_name, \
553 }; \
554 static struct clk tegra_##_name##_2x; \
555 static struct clk_tegra tegra_##_name##_2x_hw = { \
556 .hw = { \
557 .clk = &tegra_##_name##_2x, \
558 }, \
559 .flags = PERIPH_NO_RESET, \
560 .max_rate = 48000000, \
561 .reg = 0x49C, \
562 .reg_shift = 24 + (_index), \
563 .u.periph = { \
564 .clk_num = 113 + (_index), \
565 }, \
566 }; \
567 static struct clk tegra_##_name##_2x = { \
568 .name = #_name "_2x", \
569 .ops = &tegra30_clk_double_ops, \
570 .hw = &tegra_##_name##_2x_hw.hw, \
571 .parent_names = _name##_parent_names, \
572 .parents = _name##_parents, \
573 .parent = &tegra_##_name, \
574 .num_parents = 1, \
575 };
576
577AUDIO_SYNC_2X_CLK(audio0, 0);
578AUDIO_SYNC_2X_CLK(audio1, 1);
579AUDIO_SYNC_2X_CLK(audio2, 2);
580AUDIO_SYNC_2X_CLK(audio3, 3);
581AUDIO_SYNC_2X_CLK(audio4, 4);
582AUDIO_SYNC_2X_CLK(audio5, 5); /* SPDIF */
583
584static struct clk *tegra_clk_audio_2x_list[] = {
585 &tegra_audio0_2x,
586 &tegra_audio1_2x,
587 &tegra_audio2_2x,
588 &tegra_audio3_2x,
589 &tegra_audio4_2x,
590 &tegra_audio5_2x, /* SPDIF */
591};
592
593#define MUX_I2S_SPDIF(_id) \
594static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { \
595 "pll_a_out0", \
596 #_id "_2x", \
597 "pll_p", \
598 "clk_m", \
599}; \
600static struct clk *mux_pllaout0_##_id##_2x_pllp_clkm_p[] = { \
601 &tegra_pll_a_out0, \
602 &tegra_##_id##_2x, \
603 &tegra_pll_p, \
604 &tegra_clk_m, \
605};
606
607MUX_I2S_SPDIF(audio0);
608MUX_I2S_SPDIF(audio1);
609MUX_I2S_SPDIF(audio2);
610MUX_I2S_SPDIF(audio3);
611MUX_I2S_SPDIF(audio4);
612MUX_I2S_SPDIF(audio5); /* SPDIF */
613
614static struct clk tegra_extern1;
615static struct clk tegra_extern2;
616static struct clk tegra_extern3;
617
618/* External clock outputs (through PMC) */
619#define MUX_EXTERN_OUT(_id) \
620static const char *mux_clkm_clkm2_clkm4_extern##_id[] = { \
621 "clk_m", \
622 "clk_m_div2", \
623 "clk_m_div4", \
624 "extern" #_id, \
625}; \
626static struct clk *mux_clkm_clkm2_clkm4_extern##_id##_p[] = { \
627 &tegra_clk_m, \
628 &tegra_clk_m_div2, \
629 &tegra_clk_m_div4, \
630 &tegra_extern##_id, \
631};
632
633MUX_EXTERN_OUT(1);
634MUX_EXTERN_OUT(2);
635MUX_EXTERN_OUT(3);
636
637#define CLK_OUT_CLK(_name, _index) \
638 static struct clk tegra_##_name; \
639 static struct clk_tegra tegra_##_name##_hw = { \
640 .hw = { \
641 .clk = &tegra_##_name, \
642 }, \
643 .lookup = { \
644 .dev_id = #_name, \
645 .con_id = "extern" #_index, \
646 }, \
647 .flags = MUX_CLK_OUT, \
648 .fixed_rate = 216000000, \
649 .reg = 0x1a8, \
650 .u.periph = { \
651 .clk_num = (_index - 1) * 8 + 2, \
652 }, \
653 }; \
654 static struct clk tegra_##_name = { \
655 .name = #_name, \
656 .ops = &tegra_clk_out_ops, \
657 .hw = &tegra_##_name##_hw.hw, \
658 .parent_names = mux_clkm_clkm2_clkm4_extern##_index, \
659 .parents = mux_clkm_clkm2_clkm4_extern##_index##_p, \
660 .num_parents = ARRAY_SIZE(mux_clkm_clkm2_clkm4_extern##_index),\
661 };
662
663CLK_OUT_CLK(clk_out_1, 1);
664CLK_OUT_CLK(clk_out_2, 2);
665CLK_OUT_CLK(clk_out_3, 3);
666
667static struct clk *tegra_clk_out_list[] = {
668 &tegra_clk_out_1,
669 &tegra_clk_out_2,
670 &tegra_clk_out_3,
671};
672
673static const char *mux_sclk[] = {
674 "clk_m",
675 "pll_c_out1",
676 "pll_p_out4",
677 "pll_p_out3",
678 "pll_p_out2",
679 "dummy",
680 "clk_32k",
681 "pll_m_out1",
682};
683
684static struct clk *mux_sclk_p[] = {
685 &tegra_clk_m,
686 &tegra_pll_c_out1,
687 &tegra_pll_p_out4,
688 &tegra_pll_p_out3,
689 &tegra_pll_p_out2,
690 NULL,
691 &tegra_clk_32k,
692 &tegra_pll_m_out1,
693};
694
695static struct clk tegra_clk_sclk;
696static struct clk_tegra tegra_clk_sclk_hw = {
697 .hw = {
698 .clk = &tegra_clk_sclk,
699 },
700 .reg = 0x28,
701 .max_rate = 334000000,
702 .min_rate = 40000000,
703};
704
705static struct clk tegra_clk_sclk = {
706 .name = "sclk",
707 .ops = &tegra30_super_ops,
708 .hw = &tegra_clk_sclk_hw.hw,
709 .parent_names = mux_sclk,
710 .parents = mux_sclk_p,
711 .num_parents = ARRAY_SIZE(mux_sclk),
712};
713
714static const char *tegra_hclk_parent_names[] = {
715 "tegra_sclk",
716};
717
718static struct clk *tegra_hclk_parents[] = {
719 &tegra_clk_sclk,
720};
721
722static struct clk tegra_hclk;
723static struct clk_tegra tegra_hclk_hw = {
724 .hw = {
725 .clk = &tegra_hclk,
726 },
727 .flags = DIV_BUS,
728 .reg = 0x30,
729 .reg_shift = 4,
730 .max_rate = 378000000,
731 .min_rate = 12000000,
732};
733DEFINE_CLK_TEGRA(hclk, 0, &tegra30_bus_ops, 0, tegra_hclk_parent_names,
734 tegra_hclk_parents, &tegra_clk_sclk);
735
736static const char *tegra_pclk_parent_names[] = {
737 "tegra_hclk",
738};
739
740static struct clk *tegra_pclk_parents[] = {
741 &tegra_hclk,
742};
743
744static struct clk tegra_pclk;
745static struct clk_tegra tegra_pclk_hw = {
746 .hw = {
747 .clk = &tegra_pclk,
748 },
749 .flags = DIV_BUS,
750 .reg = 0x30,
751 .reg_shift = 0,
752 .max_rate = 167000000,
753 .min_rate = 12000000,
754};
755DEFINE_CLK_TEGRA(pclk, 0, &tegra30_bus_ops, 0, tegra_pclk_parent_names,
756 tegra_pclk_parents, &tegra_hclk);
757
758static const char *mux_blink[] = {
759 "clk_32k",
760};
761
762static struct clk *mux_blink_p[] = {
763 &tegra_clk_32k,
764};
765
766static struct clk tegra_clk_blink;
767static struct clk_tegra tegra_clk_blink_hw = {
768 .hw = {
769 .clk = &tegra_clk_blink,
770 },
771 .reg = 0x40,
772 .max_rate = 32768,
773};
774static struct clk tegra_clk_blink = {
775 .name = "blink",
776 .ops = &tegra30_blink_clk_ops,
777 .hw = &tegra_clk_blink_hw.hw,
778 .parent = &tegra_clk_32k,
779 .parent_names = mux_blink,
780 .parents = mux_blink_p,
781 .num_parents = ARRAY_SIZE(mux_blink),
782};
783
784static const char *mux_pllm_pllc_pllp_plla[] = {
785 "pll_m",
786 "pll_c",
787 "pll_p",
788 "pll_a_out0",
789};
790
791static const char *mux_pllp_pllc_pllm_clkm[] = {
792 "pll_p",
793 "pll_c",
794 "pll_m",
795 "clk_m",
796};
797
798static const char *mux_pllp_clkm[] = {
799 "pll_p",
800 "dummy",
801 "dummy",
802 "clk_m",
803};
804
805static const char *mux_pllp_plld_pllc_clkm[] = {
806 "pll_p",
807 "pll_d_out0",
808 "pll_c",
809 "clk_m",
810};
811
812static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
813 "pll_p",
814 "pll_m",
815 "pll_d_out0",
816 "pll_a_out0",
817 "pll_c",
818 "pll_d2_out0",
819 "clk_m",
820};
821
822static const char *mux_plla_pllc_pllp_clkm[] = {
823 "pll_a_out0",
824 "dummy",
825 "pll_p",
826 "clk_m"
827};
828
829static const char *mux_pllp_pllc_clk32_clkm[] = {
830 "pll_p",
831 "pll_c",
832 "clk_32k",
833 "clk_m",
834};
835
836static const char *mux_pllp_pllc_clkm_clk32[] = {
837 "pll_p",
838 "pll_c",
839 "clk_m",
840 "clk_32k",
841};
842
843static const char *mux_pllp_pllc_pllm[] = {
844 "pll_p",
845 "pll_c",
846 "pll_m",
847};
848
849static const char *mux_clk_m[] = {
850 "clk_m",
851};
852
853static const char *mux_pllp_out3[] = {
854 "pll_p_out3",
855};
856
857static const char *mux_plld_out0[] = {
858 "pll_d_out0",
859};
860
861static const char *mux_plld_out0_plld2_out0[] = {
862 "pll_d_out0",
863 "pll_d2_out0",
864};
865
866static const char *mux_clk_32k[] = {
867 "clk_32k",
868};
869
870static const char *mux_plla_clk32_pllp_clkm_plle[] = {
871 "pll_a_out0",
872 "clk_32k",
873 "pll_p",
874 "clk_m",
875 "pll_e",
876};
877
878static const char *mux_cclk_g[] = {
879 "clk_m",
880 "pll_c",
881 "clk_32k",
882 "pll_m",
883 "pll_p",
884 "pll_p_out4",
885 "pll_p_out3",
886 "dummy",
887 "pll_x",
888};
889
890static struct clk *mux_pllm_pllc_pllp_plla_p[] = {
891 &tegra_pll_m,
892 &tegra_pll_c,
893 &tegra_pll_p,
894 &tegra_pll_a_out0,
895};
896
897static struct clk *mux_pllp_pllc_pllm_clkm_p[] = {
898 &tegra_pll_p,
899 &tegra_pll_c,
900 &tegra_pll_m,
901 &tegra_clk_m,
902};
903
904static struct clk *mux_pllp_clkm_p[] = {
905 &tegra_pll_p,
906 NULL,
907 NULL,
908 &tegra_clk_m,
909};
910
911static struct clk *mux_pllp_plld_pllc_clkm_p[] = {
912 &tegra_pll_p,
913 &tegra_pll_d_out0,
914 &tegra_pll_c,
915 &tegra_clk_m,
916};
917
918static struct clk *mux_pllp_pllm_plld_plla_pllc_plld2_clkm_p[] = {
919 &tegra_pll_p,
920 &tegra_pll_m,
921 &tegra_pll_d_out0,
922 &tegra_pll_a_out0,
923 &tegra_pll_c,
924 &tegra_pll_d2_out0,
925 &tegra_clk_m,
926};
927
928static struct clk *mux_plla_pllc_pllp_clkm_p[] = {
929 &tegra_pll_a_out0,
930 NULL,
931 &tegra_pll_p,
932 &tegra_clk_m,
933};
934
935static struct clk *mux_pllp_pllc_clk32_clkm_p[] = {
936 &tegra_pll_p,
937 &tegra_pll_c,
938 &tegra_clk_32k,
939 &tegra_clk_m,
940};
941
942static struct clk *mux_pllp_pllc_clkm_clk32_p[] = {
943 &tegra_pll_p,
944 &tegra_pll_c,
945 &tegra_clk_m,
946 &tegra_clk_32k,
947};
948
949static struct clk *mux_pllp_pllc_pllm_p[] = {
950 &tegra_pll_p,
951 &tegra_pll_c,
952 &tegra_pll_m,
953};
954
955static struct clk *mux_clk_m_p[] = {
956 &tegra_clk_m,
957};
958
959static struct clk *mux_pllp_out3_p[] = {
960 &tegra_pll_p_out3,
961};
962
963static struct clk *mux_plld_out0_p[] = {
964 &tegra_pll_d_out0,
965};
966
967static struct clk *mux_plld_out0_plld2_out0_p[] = {
968 &tegra_pll_d_out0,
969 &tegra_pll_d2_out0,
970};
971
972static struct clk *mux_clk_32k_p[] = {
973 &tegra_clk_32k,
974};
975
976static struct clk *mux_plla_clk32_pllp_clkm_plle_p[] = {
977 &tegra_pll_a_out0,
978 &tegra_clk_32k,
979 &tegra_pll_p,
980 &tegra_clk_m,
981 &tegra_pll_e,
982};
983
984static struct clk *mux_cclk_g_p[] = {
985 &tegra_clk_m,
986 &tegra_pll_c,
987 &tegra_clk_32k,
988 &tegra_pll_m,
989 &tegra_pll_p,
990 &tegra_pll_p_out4,
991 &tegra_pll_p_out3,
992 NULL,
993 &tegra_pll_x,
994};
995
996static struct clk tegra_clk_cclk_g;
997static struct clk_tegra tegra_clk_cclk_g_hw = {
998 .hw = {
999 .clk = &tegra_clk_cclk_g,
1000 },
1001 .flags = DIV_U71 | DIV_U71_INT,
1002 .reg = 0x368,
1003 .max_rate = 1700000000,
1004};
1005static struct clk tegra_clk_cclk_g = {
1006 .name = "cclk_g",
1007 .ops = &tegra30_super_ops,
1008 .hw = &tegra_clk_cclk_g_hw.hw,
1009 .parent_names = mux_cclk_g,
1010 .parents = mux_cclk_g_p,
1011 .num_parents = ARRAY_SIZE(mux_cclk_g),
1012};
1013
1014static const char *mux_twd[] = {
1015 "cclk_g",
1016};
1017
1018static struct clk *mux_twd_p[] = {
1019 &tegra_clk_cclk_g,
1020};
1021
1022static struct clk tegra30_clk_twd;
1023static struct clk_tegra tegra30_clk_twd_hw = {
1024 .hw = {
1025 .clk = &tegra30_clk_twd,
1026 },
1027 .max_rate = 1400000000,
1028 .mul = 1,
1029 .div = 2,
1030};
1031
1032static struct clk tegra30_clk_twd = {
1033 .name = "twd",
1034 .ops = &tegra30_twd_ops,
1035 .hw = &tegra30_clk_twd_hw.hw,
1036 .parent = &tegra_clk_cclk_g,
1037 .parent_names = mux_twd,
1038 .parents = mux_twd_p,
1039 .num_parents = ARRAY_SIZE(mux_twd),
1040};
1041
1042#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, \
1043 _max, _inputs, _flags) \
1044 static struct clk tegra_##_name; \
1045 static struct clk_tegra tegra_##_name##_hw = { \
1046 .hw = { \
1047 .clk = &tegra_##_name, \
1048 }, \
1049 .lookup = { \
1050 .dev_id = _dev, \
1051 .con_id = _con, \
1052 }, \
1053 .reg = _reg, \
1054 .flags = _flags, \
1055 .max_rate = _max, \
1056 .u.periph = { \
1057 .clk_num = _clk_num, \
1058 }, \
1059 .reset = &tegra30_periph_clk_reset, \
1060 }; \
1061 static struct clk tegra_##_name = { \
1062 .name = #_name, \
1063 .ops = &tegra30_periph_clk_ops, \
1064 .hw = &tegra_##_name##_hw.hw, \
1065 .parent_names = _inputs, \
1066 .parents = _inputs##_p, \
1067 .num_parents = ARRAY_SIZE(_inputs), \
1068 };
1069
1070PERIPH_CLK(apbdma, "tegra-apbdma", NULL, 34, 0, 26000000, mux_clk_m, 0);
1071PERIPH_CLK(rtc, "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB);
1072PERIPH_CLK(kbc, "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB);
1073PERIPH_CLK(timer, "timer", NULL, 5, 0, 26000000, mux_clk_m, 0);
1074PERIPH_CLK(kfuse, "kfuse-tegra", NULL, 40, 0, 26000000, mux_clk_m, 0);
1075PERIPH_CLK(fuse, "fuse-tegra", "fuse", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB);
1076PERIPH_CLK(fuse_burn, "fuse-tegra", "fuse_burn", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB);
1077PERIPH_CLK(apbif, "tegra30-ahub", "apbif", 107, 0, 26000000, mux_clk_m, 0);
1078PERIPH_CLK(i2s0, "tegra30-i2s.0", NULL, 30, 0x1d8, 26000000, mux_pllaout0_audio0_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1079PERIPH_CLK(i2s1, "tegra30-i2s.1", NULL, 11, 0x100, 26000000, mux_pllaout0_audio1_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1080PERIPH_CLK(i2s2, "tegra30-i2s.2", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1081PERIPH_CLK(i2s3, "tegra30-i2s.3", NULL, 101, 0x3bc, 26000000, mux_pllaout0_audio3_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1082PERIPH_CLK(i2s4, "tegra30-i2s.4", NULL, 102, 0x3c0, 26000000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1083PERIPH_CLK(spdif_out, "tegra30-spdif", "spdif_out", 10, 0x108, 100000000, mux_pllaout0_audio5_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1084PERIPH_CLK(spdif_in, "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB);
1085PERIPH_CLK(pwm, "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_clk32_clkm, MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB);
1086PERIPH_CLK(d_audio, "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71);
1087PERIPH_CLK(dam0, "tegra30-dam.0", NULL, 108, 0x3d8, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71);
1088PERIPH_CLK(dam1, "tegra30-dam.1", NULL, 109, 0x3dc, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71);
1089PERIPH_CLK(dam2, "tegra30-dam.2", NULL, 110, 0x3e0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71);
1090PERIPH_CLK(hda, "tegra30-hda", "hda", 125, 0x428, 108000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1091PERIPH_CLK(hda2codec_2x, "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1092PERIPH_CLK(hda2hdmi, "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, 0);
1093PERIPH_CLK(sbc1, "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1094PERIPH_CLK(sbc2, "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1095PERIPH_CLK(sbc3, "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1096PERIPH_CLK(sbc4, "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1097PERIPH_CLK(sbc5, "spi_tegra.4", NULL, 104, 0x3c8, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1098PERIPH_CLK(sbc6, "spi_tegra.5", NULL, 105, 0x3cc, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1099PERIPH_CLK(sata_oob, "tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1100PERIPH_CLK(sata, "tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1101PERIPH_CLK(sata_cold, "tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, 0);
1102PERIPH_CLK(ndflash, "tegra_nand", NULL, 13, 0x160, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1103PERIPH_CLK(ndspeed, "tegra_nand_speed", NULL, 80, 0x3f8, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1104PERIPH_CLK(vfir, "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1105PERIPH_CLK(sdmmc1, "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
1106PERIPH_CLK(sdmmc2, "sdhci-tegra.1", NULL, 9, 0x154, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
1107PERIPH_CLK(sdmmc3, "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
1108PERIPH_CLK(sdmmc4, "sdhci-tegra.3", NULL, 15, 0x164, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
1109PERIPH_CLK(vcp, "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0);
1110PERIPH_CLK(bsea, "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0);
1111PERIPH_CLK(bsev, "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0);
1112PERIPH_CLK(vde, "vde", NULL, 61, 0x1c8, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT);
1113PERIPH_CLK(csite, "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* max rate ??? */
1114PERIPH_CLK(la, "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1115PERIPH_CLK(owr, "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1116PERIPH_CLK(nor, "nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */
1117PERIPH_CLK(mipi, "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB); /* scales with voltage */
1118PERIPH_CLK(i2c1, "tegra-i2c.0", "div-clk", 12, 0x124, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1119PERIPH_CLK(i2c2, "tegra-i2c.1", "div-clk", 54, 0x198, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1120PERIPH_CLK(i2c3, "tegra-i2c.2", "div-clk", 67, 0x1b8, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1121PERIPH_CLK(i2c4, "tegra-i2c.3", "div-clk", 103, 0x3c4, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1122PERIPH_CLK(i2c5, "tegra-i2c.4", "div-clk", 47, 0x128, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1123PERIPH_CLK(uarta, "tegra-uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1124PERIPH_CLK(uartb, "tegra-uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1125PERIPH_CLK(uartc, "tegra-uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1126PERIPH_CLK(uartd, "tegra-uart.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1127PERIPH_CLK(uarte, "tegra-uart.4", NULL, 66, 0x1c4, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1128PERIPH_CLK(vi, "tegra_camera", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT);
1129PERIPH_CLK(3d, "3d", NULL, 24, 0x158, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET);
1130PERIPH_CLK(3d2, "3d2", NULL, 98, 0x3b0, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET);
1131PERIPH_CLK(2d, "2d", NULL, 21, 0x15c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE);
1132PERIPH_CLK(vi_sensor, "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET);
1133PERIPH_CLK(epp, "epp", NULL, 19, 0x16c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT);
1134PERIPH_CLK(mpe, "mpe", NULL, 60, 0x170, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT);
1135PERIPH_CLK(host1x, "host1x", NULL, 28, 0x180, 260000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT);
1136PERIPH_CLK(cve, "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
1137PERIPH_CLK(tvo, "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
1138PERIPH_CLK(dtv, "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, 0);
1139PERIPH_CLK(hdmi, "hdmi", NULL, 51, 0x18c, 148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8 | DIV_U71);
1140PERIPH_CLK(tvdac, "tvdac", NULL, 53, 0x194, 220000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
1141PERIPH_CLK(disp1, "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8);
1142PERIPH_CLK(disp2, "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8);
1143PERIPH_CLK(usbd, "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
1144PERIPH_CLK(usb2, "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
1145PERIPH_CLK(usb3, "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
1146PERIPH_CLK(dsia, "tegradc.0", "dsia", 48, 0, 500000000, mux_plld_out0, 0);
1147PERIPH_CLK(csi, "tegra_camera", "csi", 52, 0, 102000000, mux_pllp_out3, 0);
1148PERIPH_CLK(isp, "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0); /* same frequency as VI */
1149PERIPH_CLK(csus, "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET);
1150PERIPH_CLK(tsensor, "tegra-tsensor", NULL, 100, 0x3b8, 216000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71);
1151PERIPH_CLK(actmon, "actmon", NULL, 119, 0x3e8, 216000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71);
1152PERIPH_CLK(extern1, "extern1", NULL, 120, 0x3ec, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71);
1153PERIPH_CLK(extern2, "extern2", NULL, 121, 0x3f0, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71);
1154PERIPH_CLK(extern3, "extern3", NULL, 122, 0x3f4, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71);
1155PERIPH_CLK(i2cslow, "i2cslow", NULL, 81, 0x3fc, 26000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1156PERIPH_CLK(pcie, "tegra-pcie", "pcie", 70, 0, 250000000, mux_clk_m, 0);
1157PERIPH_CLK(afi, "tegra-pcie", "afi", 72, 0, 250000000, mux_clk_m, 0);
1158PERIPH_CLK(se, "se", NULL, 127, 0x42c, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT);
1159
1160static struct clk tegra_dsib;
1161static struct clk_tegra tegra_dsib_hw = {
1162 .hw = {
1163 .clk = &tegra_dsib,
1164 },
1165 .lookup = {
1166 .dev_id = "tegradc.1",
1167 .con_id = "dsib",
1168 },
1169 .reg = 0xd0,
1170 .flags = MUX | PLLD,
1171 .max_rate = 500000000,
1172 .u.periph = {
1173 .clk_num = 82,
1174 },
1175 .reset = &tegra30_periph_clk_reset,
1176};
1177static struct clk tegra_dsib = {
1178 .name = "dsib",
1179 .ops = &tegra30_dsib_clk_ops,
1180 .hw = &tegra_dsib_hw.hw,
1181 .parent_names = mux_plld_out0_plld2_out0,
1182 .parents = mux_plld_out0_plld2_out0_p,
1183 .num_parents = ARRAY_SIZE(mux_plld_out0_plld2_out0),
1184};
1185
1186struct clk *tegra_list_clks[] = {
1187 &tegra_apbdma,
1188 &tegra_rtc,
1189 &tegra_kbc,
1190 &tegra_timer,
1191 &tegra_kfuse,
1192 &tegra_fuse,
1193 &tegra_fuse_burn,
1194 &tegra_apbif,
1195 &tegra_i2s0,
1196 &tegra_i2s1,
1197 &tegra_i2s2,
1198 &tegra_i2s3,
1199 &tegra_i2s4,
1200 &tegra_spdif_out,
1201 &tegra_spdif_in,
1202 &tegra_pwm,
1203 &tegra_d_audio,
1204 &tegra_dam0,
1205 &tegra_dam1,
1206 &tegra_dam2,
1207 &tegra_hda,
1208 &tegra_hda2codec_2x,
1209 &tegra_hda2hdmi,
1210 &tegra_sbc1,
1211 &tegra_sbc2,
1212 &tegra_sbc3,
1213 &tegra_sbc4,
1214 &tegra_sbc5,
1215 &tegra_sbc6,
1216 &tegra_sata_oob,
1217 &tegra_sata,
1218 &tegra_sata_cold,
1219 &tegra_ndflash,
1220 &tegra_ndspeed,
1221 &tegra_vfir,
1222 &tegra_sdmmc1,
1223 &tegra_sdmmc2,
1224 &tegra_sdmmc3,
1225 &tegra_sdmmc4,
1226 &tegra_vcp,
1227 &tegra_bsea,
1228 &tegra_bsev,
1229 &tegra_vde,
1230 &tegra_csite,
1231 &tegra_la,
1232 &tegra_owr,
1233 &tegra_nor,
1234 &tegra_mipi,
1235 &tegra_i2c1,
1236 &tegra_i2c2,
1237 &tegra_i2c3,
1238 &tegra_i2c4,
1239 &tegra_i2c5,
1240 &tegra_uarta,
1241 &tegra_uartb,
1242 &tegra_uartc,
1243 &tegra_uartd,
1244 &tegra_uarte,
1245 &tegra_vi,
1246 &tegra_3d,
1247 &tegra_3d2,
1248 &tegra_2d,
1249 &tegra_vi_sensor,
1250 &tegra_epp,
1251 &tegra_mpe,
1252 &tegra_host1x,
1253 &tegra_cve,
1254 &tegra_tvo,
1255 &tegra_dtv,
1256 &tegra_hdmi,
1257 &tegra_tvdac,
1258 &tegra_disp1,
1259 &tegra_disp2,
1260 &tegra_usbd,
1261 &tegra_usb2,
1262 &tegra_usb3,
1263 &tegra_dsia,
1264 &tegra_dsib,
1265 &tegra_csi,
1266 &tegra_isp,
1267 &tegra_csus,
1268 &tegra_tsensor,
1269 &tegra_actmon,
1270 &tegra_extern1,
1271 &tegra_extern2,
1272 &tegra_extern3,
1273 &tegra_i2cslow,
1274 &tegra_pcie,
1275 &tegra_afi,
1276 &tegra_se,
1277};
1278
1279#define CLK_DUPLICATE(_name, _dev, _con) \
1280 { \
1281 .name = _name, \
1282 .lookup = { \
1283 .dev_id = _dev, \
1284 .con_id = _con, \
1285 }, \
1286 }
1287
1288/* Some clocks may be used by different drivers depending on the board
1289 * configuration. List those here to register them twice in the clock lookup
1290 * table under two names.
1291 */
1292struct clk_duplicate tegra_clk_duplicates[] = {
1293 CLK_DUPLICATE("uarta", "serial8250.0", NULL),
1294 CLK_DUPLICATE("uartb", "serial8250.1", NULL),
1295 CLK_DUPLICATE("uartc", "serial8250.2", NULL),
1296 CLK_DUPLICATE("uartd", "serial8250.3", NULL),
1297 CLK_DUPLICATE("uarte", "serial8250.4", NULL),
1298 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
1299 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
1300 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
1301 CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
1302 CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
1303 CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
1304 CLK_DUPLICATE("bsev", "nvavp", "bsev"),
1305 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
1306 CLK_DUPLICATE("bsea", "tegra-aes", "bsea"),
1307 CLK_DUPLICATE("bsea", "nvavp", "bsea"),
1308 CLK_DUPLICATE("cml1", "tegra_sata_cml", NULL),
1309 CLK_DUPLICATE("cml0", "tegra_pcie", "cml"),
1310 CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"),
1311 CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL),
1312 CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL),
1313 CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
1314 CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
1315 CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
1316 CLK_DUPLICATE("sbc1", "spi_slave_tegra.0", NULL),
1317 CLK_DUPLICATE("sbc2", "spi_slave_tegra.1", NULL),
1318 CLK_DUPLICATE("sbc3", "spi_slave_tegra.2", NULL),
1319 CLK_DUPLICATE("sbc4", "spi_slave_tegra.3", NULL),
1320 CLK_DUPLICATE("sbc5", "spi_slave_tegra.4", NULL),
1321 CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL),
1322 CLK_DUPLICATE("twd", "smp_twd", NULL),
1323 CLK_DUPLICATE("vcp", "nvavp", "vcp"),
1324 CLK_DUPLICATE("i2s0", NULL, "i2s0"),
1325 CLK_DUPLICATE("i2s1", NULL, "i2s1"),
1326 CLK_DUPLICATE("i2s2", NULL, "i2s2"),
1327 CLK_DUPLICATE("i2s3", NULL, "i2s3"),
1328 CLK_DUPLICATE("i2s4", NULL, "i2s4"),
1329 CLK_DUPLICATE("dam0", NULL, "dam0"),
1330 CLK_DUPLICATE("dam1", NULL, "dam1"),
1331 CLK_DUPLICATE("dam2", NULL, "dam2"),
1332 CLK_DUPLICATE("spdif_in", NULL, "spdif_in"),
1333 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.0", "fast-clk"),
1334 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.1", "fast-clk"),
1335 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.2", "fast-clk"),
1336 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.3", "fast-clk"),
1337 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.4", "fast-clk"),
1338 CLK_DUPLICATE("pll_p", "tegradc.0", "parent"),
1339 CLK_DUPLICATE("pll_p", "tegradc.1", "parent"),
1340 CLK_DUPLICATE("pll_d2_out0", "hdmi", "parent"),
1341};
1342
1343struct clk *tegra_ptr_clks[] = {
1344 &tegra_clk_32k,
1345 &tegra_clk_m,
1346 &tegra_clk_m_div2,
1347 &tegra_clk_m_div4,
1348 &tegra_pll_ref,
1349 &tegra_pll_m,
1350 &tegra_pll_m_out1,
1351 &tegra_pll_c,
1352 &tegra_pll_c_out1,
1353 &tegra_pll_p,
1354 &tegra_pll_p_out1,
1355 &tegra_pll_p_out2,
1356 &tegra_pll_p_out3,
1357 &tegra_pll_p_out4,
1358 &tegra_pll_a,
1359 &tegra_pll_a_out0,
1360 &tegra_pll_d,
1361 &tegra_pll_d_out0,
1362 &tegra_pll_d2,
1363 &tegra_pll_d2_out0,
1364 &tegra_pll_u,
1365 &tegra_pll_x,
1366 &tegra_pll_x_out0,
1367 &tegra_pll_e,
1368 &tegra_clk_cclk_g,
1369 &tegra_cml0,
1370 &tegra_cml1,
1371 &tegra_pciex,
1372 &tegra_clk_sclk,
1373 &tegra_hclk,
1374 &tegra_pclk,
1375 &tegra_clk_blink,
1376 &tegra30_clk_twd,
1377};
1378
1379static void tegra30_init_one_clock(struct clk *c)
1380{
1381 struct clk_tegra *clk = to_clk_tegra(c->hw);
1382 __clk_init(NULL, c);
1383 INIT_LIST_HEAD(&clk->shared_bus_list);
1384 if (!clk->lookup.dev_id && !clk->lookup.con_id)
1385 clk->lookup.con_id = c->name;
1386 clk->lookup.clk = c;
1387 clkdev_add(&clk->lookup);
1388 tegra_clk_add(c);
1389}
1390
1391void __init tegra30_init_clocks(void)
1392{
1393 int i;
1394 struct clk *c;
1395
1396 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
1397 tegra30_init_one_clock(tegra_ptr_clks[i]);
1398
1399 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
1400 tegra30_init_one_clock(tegra_list_clks[i]);
1401
1402 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
1403 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
1404 if (!c) {
1405 pr_err("%s: Unknown duplicate clock %s\n", __func__,
1406 tegra_clk_duplicates[i].name);
1407 continue;
1408 }
1409
1410 tegra_clk_duplicates[i].lookup.clk = c;
1411 clkdev_add(&tegra_clk_duplicates[i].lookup);
1412 }
1413
1414 for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
1415 tegra30_init_one_clock(tegra_sync_source_list[i]);
1416 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
1417 tegra30_init_one_clock(tegra_clk_audio_list[i]);
1418 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
1419 tegra30_init_one_clock(tegra_clk_audio_2x_list[i]);
1420
1421 for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
1422 tegra30_init_one_clock(tegra_clk_out_list[i]);
1423
1424 tegra30_cpu_car_ops_init();
1425}
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index ee90e87e7675..f0b269a2058d 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_ARCH_U8500) += ux500/
22obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o 22obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
23obj-$(CONFIG_ARCH_SUNXI) += clk-sunxi.o 23obj-$(CONFIG_ARCH_SUNXI) += clk-sunxi.o
24obj-$(CONFIG_ARCH_ZYNQ) += clk-zynq.o 24obj-$(CONFIG_ARCH_ZYNQ) += clk-zynq.o
25obj-$(CONFIG_ARCH_TEGRA) += tegra/
25 26
26# Chip specific 27# Chip specific
27obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o 28obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
new file mode 100644
index 000000000000..2b41b0f4f731
--- /dev/null
+++ b/drivers/clk/tegra/Makefile
@@ -0,0 +1,11 @@
1obj-y += clk.o
2obj-y += clk-audio-sync.o
3obj-y += clk-divider.o
4obj-y += clk-periph.o
5obj-y += clk-periph-gate.o
6obj-y += clk-pll.o
7obj-y += clk-pll-out.o
8obj-y += clk-super.o
9
10obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o
11obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o
diff --git a/drivers/clk/tegra/clk-audio-sync.c b/drivers/clk/tegra/clk-audio-sync.c
new file mode 100644
index 000000000000..c0f7843e80e6
--- /dev/null
+++ b/drivers/clk/tegra/clk-audio-sync.c
@@ -0,0 +1,87 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/clk-provider.h>
18#include <linux/slab.h>
19#include <linux/err.h>
20
21#include "clk.h"
22
23static unsigned long clk_sync_source_recalc_rate(struct clk_hw *hw,
24 unsigned long parent_rate)
25{
26 struct tegra_clk_sync_source *sync = to_clk_sync_source(hw);
27
28 return sync->rate;
29}
30
31static long clk_sync_source_round_rate(struct clk_hw *hw, unsigned long rate,
32 unsigned long *prate)
33{
34 struct tegra_clk_sync_source *sync = to_clk_sync_source(hw);
35
36 if (rate > sync->max_rate)
37 return -EINVAL;
38 else
39 return rate;
40}
41
42static int clk_sync_source_set_rate(struct clk_hw *hw, unsigned long rate,
43 unsigned long parent_rate)
44{
45 struct tegra_clk_sync_source *sync = to_clk_sync_source(hw);
46
47 sync->rate = rate;
48 return 0;
49}
50
51const struct clk_ops tegra_clk_sync_source_ops = {
52 .round_rate = clk_sync_source_round_rate,
53 .set_rate = clk_sync_source_set_rate,
54 .recalc_rate = clk_sync_source_recalc_rate,
55};
56
57struct clk *tegra_clk_register_sync_source(const char *name,
58 unsigned long rate, unsigned long max_rate)
59{
60 struct tegra_clk_sync_source *sync;
61 struct clk_init_data init;
62 struct clk *clk;
63
64 sync = kzalloc(sizeof(*sync), GFP_KERNEL);
65 if (!sync) {
66 pr_err("%s: could not allocate sync source clk\n", __func__);
67 return ERR_PTR(-ENOMEM);
68 }
69
70 sync->rate = rate;
71 sync->max_rate = max_rate;
72
73 init.ops = &tegra_clk_sync_source_ops;
74 init.name = name;
75 init.flags = CLK_IS_ROOT;
76 init.parent_names = NULL;
77 init.num_parents = 0;
78
79 /* Data in .init is copied by clk_register(), so stack variable OK */
80 sync->hw.init = &init;
81
82 clk = clk_register(NULL, &sync->hw);
83 if (IS_ERR(clk))
84 kfree(sync);
85
86 return clk;
87}
diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c
new file mode 100644
index 000000000000..4d75b1f37e3a
--- /dev/null
+++ b/drivers/clk/tegra/clk-divider.c
@@ -0,0 +1,187 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/kernel.h>
18#include <linux/io.h>
19#include <linux/err.h>
20#include <linux/slab.h>
21#include <linux/clk-provider.h>
22#include <linux/clk.h>
23
24#include "clk.h"
25
26#define pll_out_override(p) (BIT((p->shift - 6)))
27#define div_mask(d) ((1 << (d->width)) - 1)
28#define get_mul(d) (1 << d->frac_width)
29#define get_max_div(d) div_mask(d)
30
31#define PERIPH_CLK_UART_DIV_ENB BIT(24)
32
33static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate,
34 unsigned long parent_rate)
35{
36 s64 divider_ux1 = parent_rate;
37 u8 flags = divider->flags;
38 int mul;
39
40 if (!rate)
41 return 0;
42
43 mul = get_mul(divider);
44
45 if (!(flags & TEGRA_DIVIDER_INT))
46 divider_ux1 *= mul;
47
48 if (flags & TEGRA_DIVIDER_ROUND_UP)
49 divider_ux1 += rate - 1;
50
51 do_div(divider_ux1, rate);
52
53 if (flags & TEGRA_DIVIDER_INT)
54 divider_ux1 *= mul;
55
56 divider_ux1 -= mul;
57
58 if (divider_ux1 < 0)
59 return 0;
60
61 if (divider_ux1 > get_max_div(divider))
62 return -EINVAL;
63
64 return divider_ux1;
65}
66
67static unsigned long clk_frac_div_recalc_rate(struct clk_hw *hw,
68 unsigned long parent_rate)
69{
70 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw);
71 u32 reg;
72 int div, mul;
73 u64 rate = parent_rate;
74
75 reg = readl_relaxed(divider->reg) >> divider->shift;
76 div = reg & div_mask(divider);
77
78 mul = get_mul(divider);
79 div += mul;
80
81 rate *= mul;
82 rate += div - 1;
83 do_div(rate, div);
84
85 return rate;
86}
87
88static long clk_frac_div_round_rate(struct clk_hw *hw, unsigned long rate,
89 unsigned long *prate)
90{
91 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw);
92 int div, mul;
93 unsigned long output_rate = *prate;
94
95 if (!rate)
96 return output_rate;
97
98 div = get_div(divider, rate, output_rate);
99 if (div < 0)
100 return *prate;
101
102 mul = get_mul(divider);
103
104 return DIV_ROUND_UP(output_rate * mul, div + mul);
105}
106
107static int clk_frac_div_set_rate(struct clk_hw *hw, unsigned long rate,
108 unsigned long parent_rate)
109{
110 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw);
111 int div;
112 unsigned long flags = 0;
113 u32 val;
114
115 div = get_div(divider, rate, parent_rate);
116 if (div < 0)
117 return div;
118
119 if (divider->lock)
120 spin_lock_irqsave(divider->lock, flags);
121
122 val = readl_relaxed(divider->reg);
123 val &= ~(div_mask(divider) << divider->shift);
124 val |= div << divider->shift;
125
126 if (divider->flags & TEGRA_DIVIDER_UART) {
127 if (div)
128 val |= PERIPH_CLK_UART_DIV_ENB;
129 else
130 val &= ~PERIPH_CLK_UART_DIV_ENB;
131 }
132
133 if (divider->flags & TEGRA_DIVIDER_FIXED)
134 val |= pll_out_override(divider);
135
136 writel_relaxed(val, divider->reg);
137
138 if (divider->lock)
139 spin_unlock_irqrestore(divider->lock, flags);
140
141 return 0;
142}
143
144const struct clk_ops tegra_clk_frac_div_ops = {
145 .recalc_rate = clk_frac_div_recalc_rate,
146 .set_rate = clk_frac_div_set_rate,
147 .round_rate = clk_frac_div_round_rate,
148};
149
150struct clk *tegra_clk_register_divider(const char *name,
151 const char *parent_name, void __iomem *reg,
152 unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width,
153 u8 frac_width, spinlock_t *lock)
154{
155 struct tegra_clk_frac_div *divider;
156 struct clk *clk;
157 struct clk_init_data init;
158
159 divider = kzalloc(sizeof(*divider), GFP_KERNEL);
160 if (!divider) {
161 pr_err("%s: could not allocate fractional divider clk\n",
162 __func__);
163 return ERR_PTR(-ENOMEM);
164 }
165
166 init.name = name;
167 init.ops = &tegra_clk_frac_div_ops;
168 init.flags = flags;
169 init.parent_names = parent_name ? &parent_name : NULL;
170 init.num_parents = parent_name ? 1 : 0;
171
172 divider->reg = reg;
173 divider->shift = shift;
174 divider->width = width;
175 divider->frac_width = frac_width;
176 divider->lock = lock;
177 divider->flags = clk_divider_flags;
178
179 /* Data in .init is copied by clk_register(), so stack variable OK */
180 divider->hw.init = &init;
181
182 clk = clk_register(NULL, &divider->hw);
183 if (IS_ERR(clk))
184 kfree(divider);
185
186 return clk;
187}
diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c
new file mode 100644
index 000000000000..6dd533251e7b
--- /dev/null
+++ b/drivers/clk/tegra/clk-periph-gate.c
@@ -0,0 +1,179 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/clk.h>
18#include <linux/clk-provider.h>
19#include <linux/slab.h>
20#include <linux/io.h>
21#include <linux/delay.h>
22#include <linux/err.h>
23#include <linux/tegra-soc.h>
24
25#include "clk.h"
26
27static DEFINE_SPINLOCK(periph_ref_lock);
28
29/* Macros to assist peripheral gate clock */
30#define read_enb(gate) \
31 readl_relaxed(gate->clk_base + (gate->regs->enb_reg))
32#define write_enb_set(val, gate) \
33 writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg))
34#define write_enb_clr(val, gate) \
35 writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg))
36
37#define read_rst(gate) \
38 readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
39#define write_rst_set(val, gate) \
40 writel_relaxed(val, gate->clk_base + (gate->regs->rst_set_reg))
41#define write_rst_clr(val, gate) \
42 writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
43
44#define periph_clk_to_bit(periph) (1 << (gate->clk_num % 32))
45
46/* Peripheral gate clock ops */
47static int clk_periph_is_enabled(struct clk_hw *hw)
48{
49 struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
50 int state = 1;
51
52 if (!(read_enb(gate) & periph_clk_to_bit(gate)))
53 state = 0;
54
55 if (!(gate->flags & TEGRA_PERIPH_NO_RESET))
56 if (read_rst(gate) & periph_clk_to_bit(gate))
57 state = 0;
58
59 return state;
60}
61
62static int clk_periph_enable(struct clk_hw *hw)
63{
64 struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
65 unsigned long flags = 0;
66
67 spin_lock_irqsave(&periph_ref_lock, flags);
68
69 gate->enable_refcnt[gate->clk_num]++;
70 if (gate->enable_refcnt[gate->clk_num] > 1) {
71 spin_unlock_irqrestore(&periph_ref_lock, flags);
72 return 0;
73 }
74
75 write_enb_set(periph_clk_to_bit(gate), gate);
76 udelay(2);
77
78 if (!(gate->flags & TEGRA_PERIPH_NO_RESET) &&
79 !(gate->flags & TEGRA_PERIPH_MANUAL_RESET)) {
80 if (read_rst(gate) & periph_clk_to_bit(gate)) {
81 udelay(5); /* reset propogation delay */
82 write_rst_clr(periph_clk_to_bit(gate), gate);
83 }
84 }
85
86 spin_unlock_irqrestore(&periph_ref_lock, flags);
87
88 return 0;
89}
90
91static void clk_periph_disable(struct clk_hw *hw)
92{
93 struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
94 unsigned long flags = 0;
95
96 spin_lock_irqsave(&periph_ref_lock, flags);
97
98 gate->enable_refcnt[gate->clk_num]--;
99 if (gate->enable_refcnt[gate->clk_num] > 0) {
100 spin_unlock_irqrestore(&periph_ref_lock, flags);
101 return;
102 }
103
104 /*
105 * If peripheral is in the APB bus then read the APB bus to
106 * flush the write operation in apb bus. This will avoid the
107 * peripheral access after disabling clock
108 */
109 if (gate->flags & TEGRA_PERIPH_ON_APB)
110 tegra_read_chipid();
111
112 write_enb_clr(periph_clk_to_bit(gate), gate);
113
114 spin_unlock_irqrestore(&periph_ref_lock, flags);
115}
116
117void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert)
118{
119 if (gate->flags & TEGRA_PERIPH_NO_RESET)
120 return;
121
122 if (assert) {
123 /*
124 * If peripheral is in the APB bus then read the APB bus to
125 * flush the write operation in apb bus. This will avoid the
126 * peripheral access after disabling clock
127 */
128 if (gate->flags & TEGRA_PERIPH_ON_APB)
129 tegra_read_chipid();
130
131 write_rst_set(periph_clk_to_bit(gate), gate);
132 } else {
133 write_rst_clr(periph_clk_to_bit(gate), gate);
134 }
135}
136
137const struct clk_ops tegra_clk_periph_gate_ops = {
138 .is_enabled = clk_periph_is_enabled,
139 .enable = clk_periph_enable,
140 .disable = clk_periph_disable,
141};
142
143struct clk *tegra_clk_register_periph_gate(const char *name,
144 const char *parent_name, u8 gate_flags, void __iomem *clk_base,
145 unsigned long flags, int clk_num,
146 struct tegra_clk_periph_regs *pregs, int *enable_refcnt)
147{
148 struct tegra_clk_periph_gate *gate;
149 struct clk *clk;
150 struct clk_init_data init;
151
152 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
153 if (!gate) {
154 pr_err("%s: could not allocate periph gate clk\n", __func__);
155 return ERR_PTR(-ENOMEM);
156 }
157
158 init.name = name;
159 init.flags = flags;
160 init.parent_names = parent_name ? &parent_name : NULL;
161 init.num_parents = parent_name ? 1 : 0;
162 init.ops = &tegra_clk_periph_gate_ops;
163
164 gate->magic = TEGRA_CLK_PERIPH_GATE_MAGIC;
165 gate->clk_base = clk_base;
166 gate->clk_num = clk_num;
167 gate->flags = gate_flags;
168 gate->enable_refcnt = enable_refcnt;
169 gate->regs = pregs;
170
171 /* Data in .init is copied by clk_register(), so stack variable OK */
172 gate->hw.init = &init;
173
174 clk = clk_register(NULL, &gate->hw);
175 if (IS_ERR(clk))
176 kfree(gate);
177
178 return clk;
179}
diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c
new file mode 100644
index 000000000000..788486e6331a
--- /dev/null
+++ b/drivers/clk/tegra/clk-periph.c
@@ -0,0 +1,218 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/clk.h>
18#include <linux/clk-provider.h>
19#include <linux/slab.h>
20#include <linux/err.h>
21
22#include "clk.h"
23
24static u8 clk_periph_get_parent(struct clk_hw *hw)
25{
26 struct tegra_clk_periph *periph = to_clk_periph(hw);
27 const struct clk_ops *mux_ops = periph->mux_ops;
28 struct clk_hw *mux_hw = &periph->mux.hw;
29
30 mux_hw->clk = hw->clk;
31
32 return mux_ops->get_parent(mux_hw);
33}
34
35static int clk_periph_set_parent(struct clk_hw *hw, u8 index)
36{
37 struct tegra_clk_periph *periph = to_clk_periph(hw);
38 const struct clk_ops *mux_ops = periph->mux_ops;
39 struct clk_hw *mux_hw = &periph->mux.hw;
40
41 mux_hw->clk = hw->clk;
42
43 return mux_ops->set_parent(mux_hw, index);
44}
45
46static unsigned long clk_periph_recalc_rate(struct clk_hw *hw,
47 unsigned long parent_rate)
48{
49 struct tegra_clk_periph *periph = to_clk_periph(hw);
50 const struct clk_ops *div_ops = periph->div_ops;
51 struct clk_hw *div_hw = &periph->divider.hw;
52
53 div_hw->clk = hw->clk;
54
55 return div_ops->recalc_rate(div_hw, parent_rate);
56}
57
58static long clk_periph_round_rate(struct clk_hw *hw, unsigned long rate,
59 unsigned long *prate)
60{
61 struct tegra_clk_periph *periph = to_clk_periph(hw);
62 const struct clk_ops *div_ops = periph->div_ops;
63 struct clk_hw *div_hw = &periph->divider.hw;
64
65 div_hw->clk = hw->clk;
66
67 return div_ops->round_rate(div_hw, rate, prate);
68}
69
70static int clk_periph_set_rate(struct clk_hw *hw, unsigned long rate,
71 unsigned long parent_rate)
72{
73 struct tegra_clk_periph *periph = to_clk_periph(hw);
74 const struct clk_ops *div_ops = periph->div_ops;
75 struct clk_hw *div_hw = &periph->divider.hw;
76
77 div_hw->clk = hw->clk;
78
79 return div_ops->set_rate(div_hw, rate, parent_rate);
80}
81
82static int clk_periph_is_enabled(struct clk_hw *hw)
83{
84 struct tegra_clk_periph *periph = to_clk_periph(hw);
85 const struct clk_ops *gate_ops = periph->gate_ops;
86 struct clk_hw *gate_hw = &periph->gate.hw;
87
88 gate_hw->clk = hw->clk;
89
90 return gate_ops->is_enabled(gate_hw);
91}
92
93static int clk_periph_enable(struct clk_hw *hw)
94{
95 struct tegra_clk_periph *periph = to_clk_periph(hw);
96 const struct clk_ops *gate_ops = periph->gate_ops;
97 struct clk_hw *gate_hw = &periph->gate.hw;
98
99 gate_hw->clk = hw->clk;
100
101 return gate_ops->enable(gate_hw);
102}
103
104static void clk_periph_disable(struct clk_hw *hw)
105{
106 struct tegra_clk_periph *periph = to_clk_periph(hw);
107 const struct clk_ops *gate_ops = periph->gate_ops;
108 struct clk_hw *gate_hw = &periph->gate.hw;
109
110 gate_ops->disable(gate_hw);
111}
112
113void tegra_periph_reset_deassert(struct clk *c)
114{
115 struct clk_hw *hw = __clk_get_hw(c);
116 struct tegra_clk_periph *periph = to_clk_periph(hw);
117 struct tegra_clk_periph_gate *gate;
118
119 if (periph->magic != TEGRA_CLK_PERIPH_MAGIC) {
120 gate = to_clk_periph_gate(hw);
121 if (gate->magic != TEGRA_CLK_PERIPH_GATE_MAGIC) {
122 WARN_ON(1);
123 return;
124 }
125 } else {
126 gate = &periph->gate;
127 }
128
129 tegra_periph_reset(gate, 0);
130}
131
132void tegra_periph_reset_assert(struct clk *c)
133{
134 struct clk_hw *hw = __clk_get_hw(c);
135 struct tegra_clk_periph *periph = to_clk_periph(hw);
136 struct tegra_clk_periph_gate *gate;
137
138 if (periph->magic != TEGRA_CLK_PERIPH_MAGIC) {
139 gate = to_clk_periph_gate(hw);
140 if (gate->magic != TEGRA_CLK_PERIPH_GATE_MAGIC) {
141 WARN_ON(1);
142 return;
143 }
144 } else {
145 gate = &periph->gate;
146 }
147
148 tegra_periph_reset(gate, 1);
149}
150
151const struct clk_ops tegra_clk_periph_ops = {
152 .get_parent = clk_periph_get_parent,
153 .set_parent = clk_periph_set_parent,
154 .recalc_rate = clk_periph_recalc_rate,
155 .round_rate = clk_periph_round_rate,
156 .set_rate = clk_periph_set_rate,
157 .is_enabled = clk_periph_is_enabled,
158 .enable = clk_periph_enable,
159 .disable = clk_periph_disable,
160};
161
162const struct clk_ops tegra_clk_periph_nodiv_ops = {
163 .get_parent = clk_periph_get_parent,
164 .set_parent = clk_periph_set_parent,
165 .is_enabled = clk_periph_is_enabled,
166 .enable = clk_periph_enable,
167 .disable = clk_periph_disable,
168};
169
170static struct clk *_tegra_clk_register_periph(const char *name,
171 const char **parent_names, int num_parents,
172 struct tegra_clk_periph *periph,
173 void __iomem *clk_base, u32 offset, bool div)
174{
175 struct clk *clk;
176 struct clk_init_data init;
177
178 init.name = name;
179 init.ops = div ? &tegra_clk_periph_ops : &tegra_clk_periph_nodiv_ops;
180 init.flags = div ? 0 : CLK_SET_RATE_PARENT;
181 init.parent_names = parent_names;
182 init.num_parents = num_parents;
183
184 /* Data in .init is copied by clk_register(), so stack variable OK */
185 periph->hw.init = &init;
186 periph->magic = TEGRA_CLK_PERIPH_MAGIC;
187 periph->mux.reg = clk_base + offset;
188 periph->divider.reg = div ? (clk_base + offset) : NULL;
189 periph->gate.clk_base = clk_base;
190
191 clk = clk_register(NULL, &periph->hw);
192 if (IS_ERR(clk))
193 return clk;
194
195 periph->mux.hw.clk = clk;
196 periph->divider.hw.clk = div ? clk : NULL;
197 periph->gate.hw.clk = clk;
198
199 return clk;
200}
201
202struct clk *tegra_clk_register_periph(const char *name,
203 const char **parent_names, int num_parents,
204 struct tegra_clk_periph *periph, void __iomem *clk_base,
205 u32 offset)
206{
207 return _tegra_clk_register_periph(name, parent_names, num_parents,
208 periph, clk_base, offset, true);
209}
210
211struct clk *tegra_clk_register_periph_nodiv(const char *name,
212 const char **parent_names, int num_parents,
213 struct tegra_clk_periph *periph, void __iomem *clk_base,
214 u32 offset)
215{
216 return _tegra_clk_register_periph(name, parent_names, num_parents,
217 periph, clk_base, offset, false);
218}
diff --git a/drivers/clk/tegra/clk-pll-out.c b/drivers/clk/tegra/clk-pll-out.c
new file mode 100644
index 000000000000..3598987a451d
--- /dev/null
+++ b/drivers/clk/tegra/clk-pll-out.c
@@ -0,0 +1,123 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/kernel.h>
18#include <linux/io.h>
19#include <linux/err.h>
20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <linux/clk-provider.h>
23#include <linux/clk.h>
24
25#include "clk.h"
26
27#define pll_out_enb(p) (BIT(p->enb_bit_idx))
28#define pll_out_rst(p) (BIT(p->rst_bit_idx))
29
30static int clk_pll_out_is_enabled(struct clk_hw *hw)
31{
32 struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);
33 u32 val = readl_relaxed(pll_out->reg);
34 int state;
35
36 state = (val & pll_out_enb(pll_out)) ? 1 : 0;
37 if (!(val & (pll_out_rst(pll_out))))
38 state = 0;
39 return state;
40}
41
42static int clk_pll_out_enable(struct clk_hw *hw)
43{
44 struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);
45 unsigned long flags = 0;
46 u32 val;
47
48 if (pll_out->lock)
49 spin_lock_irqsave(pll_out->lock, flags);
50
51 val = readl_relaxed(pll_out->reg);
52
53 val |= (pll_out_enb(pll_out) | pll_out_rst(pll_out));
54
55 writel_relaxed(val, pll_out->reg);
56 udelay(2);
57
58 if (pll_out->lock)
59 spin_unlock_irqrestore(pll_out->lock, flags);
60
61 return 0;
62}
63
64static void clk_pll_out_disable(struct clk_hw *hw)
65{
66 struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);
67 unsigned long flags = 0;
68 u32 val;
69
70 if (pll_out->lock)
71 spin_lock_irqsave(pll_out->lock, flags);
72
73 val = readl_relaxed(pll_out->reg);
74
75 val &= ~(pll_out_enb(pll_out) | pll_out_rst(pll_out));
76
77 writel_relaxed(val, pll_out->reg);
78 udelay(2);
79
80 if (pll_out->lock)
81 spin_unlock_irqrestore(pll_out->lock, flags);
82}
83
84const struct clk_ops tegra_clk_pll_out_ops = {
85 .is_enabled = clk_pll_out_is_enabled,
86 .enable = clk_pll_out_enable,
87 .disable = clk_pll_out_disable,
88};
89
90struct clk *tegra_clk_register_pll_out(const char *name,
91 const char *parent_name, void __iomem *reg, u8 enb_bit_idx,
92 u8 rst_bit_idx, unsigned long flags, u8 pll_out_flags,
93 spinlock_t *lock)
94{
95 struct tegra_clk_pll_out *pll_out;
96 struct clk *clk;
97 struct clk_init_data init;
98
99 pll_out = kzalloc(sizeof(*pll_out), GFP_KERNEL);
100 if (!pll_out)
101 return ERR_PTR(-ENOMEM);
102
103 init.name = name;
104 init.ops = &tegra_clk_pll_out_ops;
105 init.parent_names = (parent_name ? &parent_name : NULL);
106 init.num_parents = (parent_name ? 1 : 0);
107 init.flags = flags;
108
109 pll_out->reg = reg;
110 pll_out->enb_bit_idx = enb_bit_idx;
111 pll_out->rst_bit_idx = rst_bit_idx;
112 pll_out->flags = pll_out_flags;
113 pll_out->lock = lock;
114
115 /* Data in .init is copied by clk_register(), so stack variable OK */
116 pll_out->hw.init = &init;
117
118 clk = clk_register(NULL, &pll_out->hw);
119 if (IS_ERR(clk))
120 kfree(pll_out);
121
122 return clk;
123}
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
new file mode 100644
index 000000000000..165f24734c1b
--- /dev/null
+++ b/drivers/clk/tegra/clk-pll.c
@@ -0,0 +1,648 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/slab.h>
18#include <linux/io.h>
19#include <linux/delay.h>
20#include <linux/err.h>
21#include <linux/clk-provider.h>
22#include <linux/clk.h>
23
24#include "clk.h"
25
26#define PLL_BASE_BYPASS BIT(31)
27#define PLL_BASE_ENABLE BIT(30)
28#define PLL_BASE_REF_ENABLE BIT(29)
29#define PLL_BASE_OVERRIDE BIT(28)
30
31#define PLL_BASE_DIVP_SHIFT 20
32#define PLL_BASE_DIVP_WIDTH 3
33#define PLL_BASE_DIVN_SHIFT 8
34#define PLL_BASE_DIVN_WIDTH 10
35#define PLL_BASE_DIVM_SHIFT 0
36#define PLL_BASE_DIVM_WIDTH 5
37#define PLLU_POST_DIVP_MASK 0x1
38
39#define PLL_MISC_DCCON_SHIFT 20
40#define PLL_MISC_CPCON_SHIFT 8
41#define PLL_MISC_CPCON_WIDTH 4
42#define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
43#define PLL_MISC_LFCON_SHIFT 4
44#define PLL_MISC_LFCON_WIDTH 4
45#define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
46#define PLL_MISC_VCOCON_SHIFT 0
47#define PLL_MISC_VCOCON_WIDTH 4
48#define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
49
50#define OUT_OF_TABLE_CPCON 8
51
52#define PMC_PLLP_WB0_OVERRIDE 0xf8
53#define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12)
54#define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11)
55
56#define PLL_POST_LOCK_DELAY 50
57
58#define PLLDU_LFCON_SET_DIVN 600
59
60#define PLLE_BASE_DIVCML_SHIFT 24
61#define PLLE_BASE_DIVCML_WIDTH 4
62#define PLLE_BASE_DIVP_SHIFT 16
63#define PLLE_BASE_DIVP_WIDTH 7
64#define PLLE_BASE_DIVN_SHIFT 8
65#define PLLE_BASE_DIVN_WIDTH 8
66#define PLLE_BASE_DIVM_SHIFT 0
67#define PLLE_BASE_DIVM_WIDTH 8
68
69#define PLLE_MISC_SETUP_BASE_SHIFT 16
70#define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
71#define PLLE_MISC_LOCK_ENABLE BIT(9)
72#define PLLE_MISC_READY BIT(15)
73#define PLLE_MISC_SETUP_EX_SHIFT 2
74#define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT)
75#define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK | \
76 PLLE_MISC_SETUP_EX_MASK)
77#define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT)
78
79#define PLLE_SS_CTRL 0x68
80#define PLLE_SS_DISABLE (7 << 10)
81
82#define PMC_SATA_PWRGT 0x1ac
83#define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
84#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
85
86#define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
87#define pll_readl_base(p) pll_readl(p->params->base_reg, p)
88#define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
89
90#define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
91#define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
92#define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
93
94#define mask(w) ((1 << (w)) - 1)
95#define divm_mask(p) mask(p->divm_width)
96#define divn_mask(p) mask(p->divn_width)
97#define divp_mask(p) (p->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK : \
98 mask(p->divp_width))
99
100#define divm_max(p) (divm_mask(p))
101#define divn_max(p) (divn_mask(p))
102#define divp_max(p) (1 << (divp_mask(p)))
103
104static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
105{
106 u32 val;
107
108 if (!(pll->flags & TEGRA_PLL_USE_LOCK))
109 return;
110
111 val = pll_readl_misc(pll);
112 val |= BIT(pll->params->lock_enable_bit_idx);
113 pll_writel_misc(val, pll);
114}
115
116static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll,
117 void __iomem *lock_addr, u32 lock_bit_idx)
118{
119 int i;
120 u32 val;
121
122 if (!(pll->flags & TEGRA_PLL_USE_LOCK)) {
123 udelay(pll->params->lock_delay);
124 return 0;
125 }
126
127 for (i = 0; i < pll->params->lock_delay; i++) {
128 val = readl_relaxed(lock_addr);
129 if (val & BIT(lock_bit_idx)) {
130 udelay(PLL_POST_LOCK_DELAY);
131 return 0;
132 }
133 udelay(2); /* timeout = 2 * lock time */
134 }
135
136 pr_err("%s: Timed out waiting for pll %s lock\n", __func__,
137 __clk_get_name(pll->hw.clk));
138
139 return -1;
140}
141
142static int clk_pll_is_enabled(struct clk_hw *hw)
143{
144 struct tegra_clk_pll *pll = to_clk_pll(hw);
145 u32 val;
146
147 if (pll->flags & TEGRA_PLLM) {
148 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
149 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)
150 return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0;
151 }
152
153 val = pll_readl_base(pll);
154
155 return val & PLL_BASE_ENABLE ? 1 : 0;
156}
157
158static int _clk_pll_enable(struct clk_hw *hw)
159{
160 struct tegra_clk_pll *pll = to_clk_pll(hw);
161 u32 val;
162
163 clk_pll_enable_lock(pll);
164
165 val = pll_readl_base(pll);
166 val &= ~PLL_BASE_BYPASS;
167 val |= PLL_BASE_ENABLE;
168 pll_writel_base(val, pll);
169
170 if (pll->flags & TEGRA_PLLM) {
171 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
172 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
173 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
174 }
175
176 clk_pll_wait_for_lock(pll, pll->clk_base + pll->params->base_reg,
177 pll->params->lock_bit_idx);
178
179 return 0;
180}
181
182static void _clk_pll_disable(struct clk_hw *hw)
183{
184 struct tegra_clk_pll *pll = to_clk_pll(hw);
185 u32 val;
186
187 val = pll_readl_base(pll);
188 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
189 pll_writel_base(val, pll);
190
191 if (pll->flags & TEGRA_PLLM) {
192 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
193 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
194 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
195 }
196}
197
198static int clk_pll_enable(struct clk_hw *hw)
199{
200 struct tegra_clk_pll *pll = to_clk_pll(hw);
201 unsigned long flags = 0;
202 int ret;
203
204 if (pll->lock)
205 spin_lock_irqsave(pll->lock, flags);
206
207 ret = _clk_pll_enable(hw);
208
209 if (pll->lock)
210 spin_unlock_irqrestore(pll->lock, flags);
211
212 return ret;
213}
214
215static void clk_pll_disable(struct clk_hw *hw)
216{
217 struct tegra_clk_pll *pll = to_clk_pll(hw);
218 unsigned long flags = 0;
219
220 if (pll->lock)
221 spin_lock_irqsave(pll->lock, flags);
222
223 _clk_pll_disable(hw);
224
225 if (pll->lock)
226 spin_unlock_irqrestore(pll->lock, flags);
227}
228
229static int _get_table_rate(struct clk_hw *hw,
230 struct tegra_clk_pll_freq_table *cfg,
231 unsigned long rate, unsigned long parent_rate)
232{
233 struct tegra_clk_pll *pll = to_clk_pll(hw);
234 struct tegra_clk_pll_freq_table *sel;
235
236 for (sel = pll->freq_table; sel->input_rate != 0; sel++)
237 if (sel->input_rate == parent_rate &&
238 sel->output_rate == rate)
239 break;
240
241 if (sel->input_rate == 0)
242 return -EINVAL;
243
244 BUG_ON(sel->p < 1);
245
246 cfg->input_rate = sel->input_rate;
247 cfg->output_rate = sel->output_rate;
248 cfg->m = sel->m;
249 cfg->n = sel->n;
250 cfg->p = sel->p;
251 cfg->cpcon = sel->cpcon;
252
253 return 0;
254}
255
256static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
257 unsigned long rate, unsigned long parent_rate)
258{
259 struct tegra_clk_pll *pll = to_clk_pll(hw);
260 unsigned long cfreq;
261 u32 p_div = 0;
262
263 switch (parent_rate) {
264 case 12000000:
265 case 26000000:
266 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
267 break;
268 case 13000000:
269 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
270 break;
271 case 16800000:
272 case 19200000:
273 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
274 break;
275 case 9600000:
276 case 28800000:
277 /*
278 * PLL_P_OUT1 rate is not listed in PLLA table
279 */
280 cfreq = parent_rate/(parent_rate/1000000);
281 break;
282 default:
283 pr_err("%s Unexpected reference rate %lu\n",
284 __func__, parent_rate);
285 BUG();
286 }
287
288 /* Raise VCO to guarantee 0.5% accuracy */
289 for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq;
290 cfg->output_rate <<= 1)
291 p_div++;
292
293 cfg->p = 1 << p_div;
294 cfg->m = parent_rate / cfreq;
295 cfg->n = cfg->output_rate / cfreq;
296 cfg->cpcon = OUT_OF_TABLE_CPCON;
297
298 if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
299 cfg->p > divp_max(pll) || cfg->output_rate > pll->params->vco_max) {
300 pr_err("%s: Failed to set %s rate %lu\n",
301 __func__, __clk_get_name(hw->clk), rate);
302 return -EINVAL;
303 }
304
305 return 0;
306}
307
308static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
309 unsigned long rate)
310{
311 struct tegra_clk_pll *pll = to_clk_pll(hw);
312 unsigned long flags = 0;
313 u32 divp, val, old_base;
314 int state;
315
316 divp = __ffs(cfg->p);
317
318 if (pll->flags & TEGRA_PLLU)
319 divp ^= 1;
320
321 if (pll->lock)
322 spin_lock_irqsave(pll->lock, flags);
323
324 old_base = val = pll_readl_base(pll);
325 val &= ~((divm_mask(pll) << pll->divm_shift) |
326 (divn_mask(pll) << pll->divn_shift) |
327 (divp_mask(pll) << pll->divp_shift));
328 val |= ((cfg->m << pll->divm_shift) |
329 (cfg->n << pll->divn_shift) |
330 (divp << pll->divp_shift));
331 if (val == old_base) {
332 if (pll->lock)
333 spin_unlock_irqrestore(pll->lock, flags);
334 return 0;
335 }
336
337 state = clk_pll_is_enabled(hw);
338
339 if (state) {
340 _clk_pll_disable(hw);
341 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
342 }
343 pll_writel_base(val, pll);
344
345 if (pll->flags & TEGRA_PLL_HAS_CPCON) {
346 val = pll_readl_misc(pll);
347 val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
348 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
349 if (pll->flags & TEGRA_PLL_SET_LFCON) {
350 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
351 if (cfg->n >= PLLDU_LFCON_SET_DIVN)
352 val |= 0x1 << PLL_MISC_LFCON_SHIFT;
353 } else if (pll->flags & TEGRA_PLL_SET_DCCON) {
354 val &= ~(0x1 << PLL_MISC_DCCON_SHIFT);
355 if (rate >= (pll->params->vco_max >> 1))
356 val |= 0x1 << PLL_MISC_DCCON_SHIFT;
357 }
358 pll_writel_misc(val, pll);
359 }
360
361 if (pll->lock)
362 spin_unlock_irqrestore(pll->lock, flags);
363
364 if (state)
365 clk_pll_enable(hw);
366
367 return 0;
368}
369
370static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
371 unsigned long parent_rate)
372{
373 struct tegra_clk_pll *pll = to_clk_pll(hw);
374 struct tegra_clk_pll_freq_table cfg;
375
376 if (pll->flags & TEGRA_PLL_FIXED) {
377 if (rate != pll->fixed_rate) {
378 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
379 __func__, __clk_get_name(hw->clk),
380 pll->fixed_rate, rate);
381 return -EINVAL;
382 }
383 return 0;
384 }
385
386 if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
387 _calc_rate(hw, &cfg, rate, parent_rate))
388 return -EINVAL;
389
390 return _program_pll(hw, &cfg, rate);
391}
392
393static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
394 unsigned long *prate)
395{
396 struct tegra_clk_pll *pll = to_clk_pll(hw);
397 struct tegra_clk_pll_freq_table cfg;
398 u64 output_rate = *prate;
399
400 if (pll->flags & TEGRA_PLL_FIXED)
401 return pll->fixed_rate;
402
403 /* PLLM is used for memory; we do not change rate */
404 if (pll->flags & TEGRA_PLLM)
405 return __clk_get_rate(hw->clk);
406
407 if (_get_table_rate(hw, &cfg, rate, *prate) &&
408 _calc_rate(hw, &cfg, rate, *prate))
409 return -EINVAL;
410
411 output_rate *= cfg.n;
412 do_div(output_rate, cfg.m * cfg.p);
413
414 return output_rate;
415}
416
417static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
418 unsigned long parent_rate)
419{
420 struct tegra_clk_pll *pll = to_clk_pll(hw);
421 u32 val = pll_readl_base(pll);
422 u32 divn = 0, divm = 0, divp = 0;
423 u64 rate = parent_rate;
424
425 if (val & PLL_BASE_BYPASS)
426 return parent_rate;
427
428 if ((pll->flags & TEGRA_PLL_FIXED) && !(val & PLL_BASE_OVERRIDE)) {
429 struct tegra_clk_pll_freq_table sel;
430 if (_get_table_rate(hw, &sel, pll->fixed_rate, parent_rate)) {
431 pr_err("Clock %s has unknown fixed frequency\n",
432 __clk_get_name(hw->clk));
433 BUG();
434 }
435 return pll->fixed_rate;
436 }
437
438 divp = (val >> pll->divp_shift) & (divp_mask(pll));
439 if (pll->flags & TEGRA_PLLU)
440 divp ^= 1;
441
442 divn = (val >> pll->divn_shift) & (divn_mask(pll));
443 divm = (val >> pll->divm_shift) & (divm_mask(pll));
444 divm *= (1 << divp);
445
446 rate *= divn;
447 do_div(rate, divm);
448 return rate;
449}
450
451static int clk_plle_training(struct tegra_clk_pll *pll)
452{
453 u32 val;
454 unsigned long timeout;
455
456 if (!pll->pmc)
457 return -ENOSYS;
458
459 /*
460 * PLLE is already disabled, and setup cleared;
461 * create falling edge on PLLE IDDQ input.
462 */
463 val = readl(pll->pmc + PMC_SATA_PWRGT);
464 val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
465 writel(val, pll->pmc + PMC_SATA_PWRGT);
466
467 val = readl(pll->pmc + PMC_SATA_PWRGT);
468 val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
469 writel(val, pll->pmc + PMC_SATA_PWRGT);
470
471 val = readl(pll->pmc + PMC_SATA_PWRGT);
472 val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
473 writel(val, pll->pmc + PMC_SATA_PWRGT);
474
475 val = pll_readl_misc(pll);
476
477 timeout = jiffies + msecs_to_jiffies(100);
478 while (1) {
479 val = pll_readl_misc(pll);
480 if (val & PLLE_MISC_READY)
481 break;
482 if (time_after(jiffies, timeout)) {
483 pr_err("%s: timeout waiting for PLLE\n", __func__);
484 return -EBUSY;
485 }
486 udelay(300);
487 }
488
489 return 0;
490}
491
492static int clk_plle_enable(struct clk_hw *hw)
493{
494 struct tegra_clk_pll *pll = to_clk_pll(hw);
495 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
496 struct tegra_clk_pll_freq_table sel;
497 u32 val;
498 int err;
499
500 if (_get_table_rate(hw, &sel, pll->fixed_rate, input_rate))
501 return -EINVAL;
502
503 clk_pll_disable(hw);
504
505 val = pll_readl_misc(pll);
506 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
507 pll_writel_misc(val, pll);
508
509 val = pll_readl_misc(pll);
510 if (!(val & PLLE_MISC_READY)) {
511 err = clk_plle_training(pll);
512 if (err)
513 return err;
514 }
515
516 if (pll->flags & TEGRA_PLLE_CONFIGURE) {
517 /* configure dividers */
518 val = pll_readl_base(pll);
519 val &= ~(divm_mask(pll) | divn_mask(pll) | divp_mask(pll));
520 val &= ~(PLLE_BASE_DIVCML_WIDTH << PLLE_BASE_DIVCML_SHIFT);
521 val |= sel.m << pll->divm_shift;
522 val |= sel.n << pll->divn_shift;
523 val |= sel.p << pll->divp_shift;
524 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
525 pll_writel_base(val, pll);
526 }
527
528 val = pll_readl_misc(pll);
529 val |= PLLE_MISC_SETUP_VALUE;
530 val |= PLLE_MISC_LOCK_ENABLE;
531 pll_writel_misc(val, pll);
532
533 val = readl(pll->clk_base + PLLE_SS_CTRL);
534 val |= PLLE_SS_DISABLE;
535 writel(val, pll->clk_base + PLLE_SS_CTRL);
536
537 val |= pll_readl_base(pll);
538 val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
539 pll_writel_base(val, pll);
540
541 clk_pll_wait_for_lock(pll, pll->clk_base + pll->params->misc_reg,
542 pll->params->lock_bit_idx);
543 return 0;
544}
545
546static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
547 unsigned long parent_rate)
548{
549 struct tegra_clk_pll *pll = to_clk_pll(hw);
550 u32 val = pll_readl_base(pll);
551 u32 divn = 0, divm = 0, divp = 0;
552 u64 rate = parent_rate;
553
554 divp = (val >> pll->divp_shift) & (divp_mask(pll));
555 divn = (val >> pll->divn_shift) & (divn_mask(pll));
556 divm = (val >> pll->divm_shift) & (divm_mask(pll));
557 divm *= divp;
558
559 rate *= divn;
560 do_div(rate, divm);
561 return rate;
562}
563
564const struct clk_ops tegra_clk_pll_ops = {
565 .is_enabled = clk_pll_is_enabled,
566 .enable = clk_pll_enable,
567 .disable = clk_pll_disable,
568 .recalc_rate = clk_pll_recalc_rate,
569 .round_rate = clk_pll_round_rate,
570 .set_rate = clk_pll_set_rate,
571};
572
573const struct clk_ops tegra_clk_plle_ops = {
574 .recalc_rate = clk_plle_recalc_rate,
575 .is_enabled = clk_pll_is_enabled,
576 .disable = clk_pll_disable,
577 .enable = clk_plle_enable,
578};
579
580static struct clk *_tegra_clk_register_pll(const char *name,
581 const char *parent_name, void __iomem *clk_base,
582 void __iomem *pmc, unsigned long flags,
583 unsigned long fixed_rate,
584 struct tegra_clk_pll_params *pll_params, u8 pll_flags,
585 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock,
586 const struct clk_ops *ops)
587{
588 struct tegra_clk_pll *pll;
589 struct clk *clk;
590 struct clk_init_data init;
591
592 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
593 if (!pll)
594 return ERR_PTR(-ENOMEM);
595
596 init.name = name;
597 init.ops = ops;
598 init.flags = flags;
599 init.parent_names = (parent_name ? &parent_name : NULL);
600 init.num_parents = (parent_name ? 1 : 0);
601
602 pll->clk_base = clk_base;
603 pll->pmc = pmc;
604
605 pll->freq_table = freq_table;
606 pll->params = pll_params;
607 pll->fixed_rate = fixed_rate;
608 pll->flags = pll_flags;
609 pll->lock = lock;
610
611 pll->divp_shift = PLL_BASE_DIVP_SHIFT;
612 pll->divp_width = PLL_BASE_DIVP_WIDTH;
613 pll->divn_shift = PLL_BASE_DIVN_SHIFT;
614 pll->divn_width = PLL_BASE_DIVN_WIDTH;
615 pll->divm_shift = PLL_BASE_DIVM_SHIFT;
616 pll->divm_width = PLL_BASE_DIVM_WIDTH;
617
618 /* Data in .init is copied by clk_register(), so stack variable OK */
619 pll->hw.init = &init;
620
621 clk = clk_register(NULL, &pll->hw);
622 if (IS_ERR(clk))
623 kfree(pll);
624
625 return clk;
626}
627
628struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
629 void __iomem *clk_base, void __iomem *pmc,
630 unsigned long flags, unsigned long fixed_rate,
631 struct tegra_clk_pll_params *pll_params, u8 pll_flags,
632 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
633{
634 return _tegra_clk_register_pll(name, parent_name, clk_base, pmc,
635 flags, fixed_rate, pll_params, pll_flags, freq_table,
636 lock, &tegra_clk_pll_ops);
637}
638
639struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
640 void __iomem *clk_base, void __iomem *pmc,
641 unsigned long flags, unsigned long fixed_rate,
642 struct tegra_clk_pll_params *pll_params, u8 pll_flags,
643 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
644{
645 return _tegra_clk_register_pll(name, parent_name, clk_base, pmc,
646 flags, fixed_rate, pll_params, pll_flags, freq_table,
647 lock, &tegra_clk_plle_ops);
648}
diff --git a/drivers/clk/tegra/clk-super.c b/drivers/clk/tegra/clk-super.c
new file mode 100644
index 000000000000..7ad48a832334
--- /dev/null
+++ b/drivers/clk/tegra/clk-super.c
@@ -0,0 +1,154 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/kernel.h>
18#include <linux/io.h>
19#include <linux/delay.h>
20#include <linux/err.h>
21#include <linux/slab.h>
22#include <linux/clk-provider.h>
23#include <linux/clk.h>
24
25#include "clk.h"
26
27#define SUPER_STATE_IDLE 0
28#define SUPER_STATE_RUN 1
29#define SUPER_STATE_IRQ 2
30#define SUPER_STATE_FIQ 3
31
32#define SUPER_STATE_SHIFT 28
33#define SUPER_STATE_MASK ((BIT(SUPER_STATE_IDLE) | BIT(SUPER_STATE_RUN) | \
34 BIT(SUPER_STATE_IRQ) | BIT(SUPER_STATE_FIQ)) \
35 << SUPER_STATE_SHIFT)
36
37#define SUPER_LP_DIV2_BYPASS (1 << 16)
38
39#define super_state(s) (BIT(s) << SUPER_STATE_SHIFT)
40#define super_state_to_src_shift(m, s) ((m->width * s))
41#define super_state_to_src_mask(m) (((1 << m->width) - 1))
42
43static u8 clk_super_get_parent(struct clk_hw *hw)
44{
45 struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);
46 u32 val, state;
47 u8 source, shift;
48
49 val = readl_relaxed(mux->reg);
50
51 state = val & SUPER_STATE_MASK;
52
53 BUG_ON((state != super_state(SUPER_STATE_RUN)) &&
54 (state != super_state(SUPER_STATE_IDLE)));
55 shift = (state == super_state(SUPER_STATE_IDLE)) ?
56 super_state_to_src_shift(mux, SUPER_STATE_IDLE) :
57 super_state_to_src_shift(mux, SUPER_STATE_RUN);
58
59 source = (val >> shift) & super_state_to_src_mask(mux);
60
61 /*
62 * If LP_DIV2_BYPASS is not set and PLLX is current parent then
63 * PLLX/2 is the input source to CCLKLP.
64 */
65 if ((mux->flags & TEGRA_DIVIDER_2) && !(val & SUPER_LP_DIV2_BYPASS) &&
66 (source == mux->pllx_index))
67 source = mux->div2_index;
68
69 return source;
70}
71
72static int clk_super_set_parent(struct clk_hw *hw, u8 index)
73{
74 struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);
75 u32 val, state;
76 u8 parent_index, shift;
77
78 val = readl_relaxed(mux->reg);
79 state = val & SUPER_STATE_MASK;
80 BUG_ON((state != super_state(SUPER_STATE_RUN)) &&
81 (state != super_state(SUPER_STATE_IDLE)));
82 shift = (state == super_state(SUPER_STATE_IDLE)) ?
83 super_state_to_src_shift(mux, SUPER_STATE_IDLE) :
84 super_state_to_src_shift(mux, SUPER_STATE_RUN);
85
86 /*
87 * For LP mode super-clock switch between PLLX direct
88 * and divided-by-2 outputs is allowed only when other
89 * than PLLX clock source is current parent.
90 */
91 if ((mux->flags & TEGRA_DIVIDER_2) && ((index == mux->div2_index) ||
92 (index == mux->pllx_index))) {
93 parent_index = clk_super_get_parent(hw);
94 if ((parent_index == mux->div2_index) ||
95 (parent_index == mux->pllx_index))
96 return -EINVAL;
97
98 val ^= SUPER_LP_DIV2_BYPASS;
99 writel_relaxed(val, mux->reg);
100 udelay(2);
101
102 if (index == mux->div2_index)
103 index = mux->pllx_index;
104 }
105 val &= ~((super_state_to_src_mask(mux)) << shift);
106 val |= (index & (super_state_to_src_mask(mux))) << shift;
107
108 writel_relaxed(val, mux->reg);
109 udelay(2);
110 return 0;
111}
112
113const struct clk_ops tegra_clk_super_ops = {
114 .get_parent = clk_super_get_parent,
115 .set_parent = clk_super_set_parent,
116};
117
118struct clk *tegra_clk_register_super_mux(const char *name,
119 const char **parent_names, u8 num_parents,
120 unsigned long flags, void __iomem *reg, u8 clk_super_flags,
121 u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock)
122{
123 struct tegra_clk_super_mux *super;
124 struct clk *clk;
125 struct clk_init_data init;
126
127 super = kzalloc(sizeof(*super), GFP_KERNEL);
128 if (!super) {
129 pr_err("%s: could not allocate super clk\n", __func__);
130 return ERR_PTR(-ENOMEM);
131 }
132
133 init.name = name;
134 init.ops = &tegra_clk_super_ops;
135 init.flags = flags;
136 init.parent_names = parent_names;
137 init.num_parents = num_parents;
138
139 super->reg = reg;
140 super->pllx_index = pllx_index;
141 super->div2_index = div2_index;
142 super->lock = lock;
143 super->width = width;
144 super->flags = clk_super_flags;
145
146 /* Data in .init is copied by clk_register(), so stack variable OK */
147 super->hw.init = &init;
148
149 clk = clk_register(NULL, &super->hw);
150 if (IS_ERR(clk))
151 kfree(super);
152
153 return clk;
154}
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
new file mode 100644
index 000000000000..077d5b9ffe22
--- /dev/null
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -0,0 +1,1256 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/clk-provider.h>
20#include <linux/clkdev.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/clk/tegra.h>
24
25#include "clk.h"
26
27#define RST_DEVICES_L 0x004
28#define RST_DEVICES_H 0x008
29#define RST_DEVICES_U 0x00c
30#define RST_DEVICES_SET_L 0x300
31#define RST_DEVICES_CLR_L 0x304
32#define RST_DEVICES_SET_H 0x308
33#define RST_DEVICES_CLR_H 0x30c
34#define RST_DEVICES_SET_U 0x310
35#define RST_DEVICES_CLR_U 0x314
36#define RST_DEVICES_NUM 3
37
38#define CLK_OUT_ENB_L 0x010
39#define CLK_OUT_ENB_H 0x014
40#define CLK_OUT_ENB_U 0x018
41#define CLK_OUT_ENB_SET_L 0x320
42#define CLK_OUT_ENB_CLR_L 0x324
43#define CLK_OUT_ENB_SET_H 0x328
44#define CLK_OUT_ENB_CLR_H 0x32c
45#define CLK_OUT_ENB_SET_U 0x330
46#define CLK_OUT_ENB_CLR_U 0x334
47#define CLK_OUT_ENB_NUM 3
48
49#define OSC_CTRL 0x50
50#define OSC_CTRL_OSC_FREQ_MASK (3<<30)
51#define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
52#define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)
53#define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
54#define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)
55#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
56
57#define OSC_CTRL_PLL_REF_DIV_MASK (3<<28)
58#define OSC_CTRL_PLL_REF_DIV_1 (0<<28)
59#define OSC_CTRL_PLL_REF_DIV_2 (1<<28)
60#define OSC_CTRL_PLL_REF_DIV_4 (2<<28)
61
62#define OSC_FREQ_DET 0x58
63#define OSC_FREQ_DET_TRIG (1<<31)
64
65#define OSC_FREQ_DET_STATUS 0x5c
66#define OSC_FREQ_DET_BUSY (1<<31)
67#define OSC_FREQ_DET_CNT_MASK 0xFFFF
68
69#define PLLS_BASE 0xf0
70#define PLLS_MISC 0xf4
71#define PLLC_BASE 0x80
72#define PLLC_MISC 0x8c
73#define PLLM_BASE 0x90
74#define PLLM_MISC 0x9c
75#define PLLP_BASE 0xa0
76#define PLLP_MISC 0xac
77#define PLLA_BASE 0xb0
78#define PLLA_MISC 0xbc
79#define PLLU_BASE 0xc0
80#define PLLU_MISC 0xcc
81#define PLLD_BASE 0xd0
82#define PLLD_MISC 0xdc
83#define PLLX_BASE 0xe0
84#define PLLX_MISC 0xe4
85#define PLLE_BASE 0xe8
86#define PLLE_MISC 0xec
87
88#define PLL_BASE_LOCK 27
89#define PLLE_MISC_LOCK 11
90
91#define PLL_MISC_LOCK_ENABLE 18
92#define PLLDU_MISC_LOCK_ENABLE 22
93#define PLLE_MISC_LOCK_ENABLE 9
94
95#define PLLC_OUT 0x84
96#define PLLM_OUT 0x94
97#define PLLP_OUTA 0xa4
98#define PLLP_OUTB 0xa8
99#define PLLA_OUT 0xb4
100
101#define CCLK_BURST_POLICY 0x20
102#define SUPER_CCLK_DIVIDER 0x24
103#define SCLK_BURST_POLICY 0x28
104#define SUPER_SCLK_DIVIDER 0x2c
105#define CLK_SYSTEM_RATE 0x30
106
107#define CLK_SOURCE_I2S1 0x100
108#define CLK_SOURCE_I2S2 0x104
109#define CLK_SOURCE_SPDIF_OUT 0x108
110#define CLK_SOURCE_SPDIF_IN 0x10c
111#define CLK_SOURCE_PWM 0x110
112#define CLK_SOURCE_SPI 0x114
113#define CLK_SOURCE_SBC1 0x134
114#define CLK_SOURCE_SBC2 0x118
115#define CLK_SOURCE_SBC3 0x11c
116#define CLK_SOURCE_SBC4 0x1b4
117#define CLK_SOURCE_XIO 0x120
118#define CLK_SOURCE_TWC 0x12c
119#define CLK_SOURCE_IDE 0x144
120#define CLK_SOURCE_NDFLASH 0x160
121#define CLK_SOURCE_VFIR 0x168
122#define CLK_SOURCE_SDMMC1 0x150
123#define CLK_SOURCE_SDMMC2 0x154
124#define CLK_SOURCE_SDMMC3 0x1bc
125#define CLK_SOURCE_SDMMC4 0x164
126#define CLK_SOURCE_CVE 0x140
127#define CLK_SOURCE_TVO 0x188
128#define CLK_SOURCE_TVDAC 0x194
129#define CLK_SOURCE_HDMI 0x18c
130#define CLK_SOURCE_DISP1 0x138
131#define CLK_SOURCE_DISP2 0x13c
132#define CLK_SOURCE_CSITE 0x1d4
133#define CLK_SOURCE_LA 0x1f8
134#define CLK_SOURCE_OWR 0x1cc
135#define CLK_SOURCE_NOR 0x1d0
136#define CLK_SOURCE_MIPI 0x174
137#define CLK_SOURCE_I2C1 0x124
138#define CLK_SOURCE_I2C2 0x198
139#define CLK_SOURCE_I2C3 0x1b8
140#define CLK_SOURCE_DVC 0x128
141#define CLK_SOURCE_UARTA 0x178
142#define CLK_SOURCE_UARTB 0x17c
143#define CLK_SOURCE_UARTC 0x1a0
144#define CLK_SOURCE_UARTD 0x1c0
145#define CLK_SOURCE_UARTE 0x1c4
146#define CLK_SOURCE_3D 0x158
147#define CLK_SOURCE_2D 0x15c
148#define CLK_SOURCE_MPE 0x170
149#define CLK_SOURCE_EPP 0x16c
150#define CLK_SOURCE_HOST1X 0x180
151#define CLK_SOURCE_VDE 0x1c8
152#define CLK_SOURCE_VI 0x148
153#define CLK_SOURCE_VI_SENSOR 0x1a8
154#define CLK_SOURCE_EMC 0x19c
155
156#define AUDIO_SYNC_CLK 0x38
157
158#define PMC_CTRL 0x0
159#define PMC_CTRL_BLINK_ENB 7
160#define PMC_DPD_PADS_ORIDE 0x1c
161#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
162#define PMC_BLINK_TIMER 0x40
163
164/* Tegra CPU clock and reset control regs */
165#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
166#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
167#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344
168
169#define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
170#define CPU_RESET(cpu) (0x1111ul << (cpu))
171
172static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
173
174static void __iomem *clk_base;
175static void __iomem *pmc_base;
176
177static DEFINE_SPINLOCK(pll_div_lock);
178
179#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \
180 _clk_num, _regs, _gate_flags, _clk_id) \
181 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
182 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
183 _regs, _clk_num, periph_clk_enb_refcnt, \
184 _gate_flags, _clk_id)
185
186#define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \
187 _clk_num, _regs, _gate_flags, _clk_id) \
188 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
189 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs, \
190 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
191 _clk_id)
192
193#define TEGRA_INIT_DATA_DIV16(_name, _con_id, _dev_id, _parents, _offset, \
194 _clk_num, _regs, _gate_flags, _clk_id) \
195 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
196 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, _regs, \
197 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
198 _clk_id)
199
200#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \
201 _mux_shift, _mux_width, _clk_num, _regs, \
202 _gate_flags, _clk_id) \
203 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
204 _mux_shift, _mux_width, 0, 0, 0, 0, 0, _regs, \
205 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
206 _clk_id)
207
208/* IDs assigned here must be in sync with DT bindings definition
209 * for Tegra20 clocks .
210 */
211enum tegra20_clk {
212 cpu, ac97 = 3, rtc, timer, uarta, gpio = 8, sdmmc2, i2s1 = 11, i2c1,
213 ndflash, sdmmc1, sdmmc4, twc, pwm, i2s2, epp, gr2d = 21, usbd, isp,
214 gr3d, ide, disp2, disp1, host1x, vcp, cache2 = 31, mem, ahbdma, apbdma,
215 kbc = 36, stat_mon, pmc, fuse, kfuse, sbc1, nor, spi, sbc2, xio, sbc3,
216 dvc, dsi, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2,
217 usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
218 pex, owr, afi, csite, pcie_xclk, avpucq = 75, la, irama = 84, iramb,
219 iramc, iramd, cram2, audio_2x, clk_d, csus = 92, cdev1, cdev2,
220 uartb = 96, vfir, spdif_in, spdif_out, vi, vi_sensor, tvo, cve,
221 osc, clk_32k, clk_m, sclk, cclk, hclk, pclk, blink, pll_a, pll_a_out0,
222 pll_c, pll_c_out1, pll_d, pll_d_out0, pll_e, pll_m, pll_m_out1,
223 pll_p, pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_u,
224 pll_x, audio, pll_ref, twd, clk_max,
225};
226
227static struct clk *clks[clk_max];
228static struct clk_onecell_data clk_data;
229
230static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
231 { 12000000, 600000000, 600, 12, 1, 8 },
232 { 13000000, 600000000, 600, 13, 1, 8 },
233 { 19200000, 600000000, 500, 16, 1, 6 },
234 { 26000000, 600000000, 600, 26, 1, 8 },
235 { 0, 0, 0, 0, 0, 0 },
236};
237
238static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
239 { 12000000, 666000000, 666, 12, 1, 8},
240 { 13000000, 666000000, 666, 13, 1, 8},
241 { 19200000, 666000000, 555, 16, 1, 8},
242 { 26000000, 666000000, 666, 26, 1, 8},
243 { 12000000, 600000000, 600, 12, 1, 8},
244 { 13000000, 600000000, 600, 13, 1, 8},
245 { 19200000, 600000000, 375, 12, 1, 6},
246 { 26000000, 600000000, 600, 26, 1, 8},
247 { 0, 0, 0, 0, 0, 0 },
248};
249
250static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
251 { 12000000, 216000000, 432, 12, 2, 8},
252 { 13000000, 216000000, 432, 13, 2, 8},
253 { 19200000, 216000000, 90, 4, 2, 1},
254 { 26000000, 216000000, 432, 26, 2, 8},
255 { 12000000, 432000000, 432, 12, 1, 8},
256 { 13000000, 432000000, 432, 13, 1, 8},
257 { 19200000, 432000000, 90, 4, 1, 1},
258 { 26000000, 432000000, 432, 26, 1, 8},
259 { 0, 0, 0, 0, 0, 0 },
260};
261
262static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
263 { 28800000, 56448000, 49, 25, 1, 1},
264 { 28800000, 73728000, 64, 25, 1, 1},
265 { 28800000, 24000000, 5, 6, 1, 1},
266 { 0, 0, 0, 0, 0, 0 },
267};
268
269static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
270 { 12000000, 216000000, 216, 12, 1, 4},
271 { 13000000, 216000000, 216, 13, 1, 4},
272 { 19200000, 216000000, 135, 12, 1, 3},
273 { 26000000, 216000000, 216, 26, 1, 4},
274
275 { 12000000, 594000000, 594, 12, 1, 8},
276 { 13000000, 594000000, 594, 13, 1, 8},
277 { 19200000, 594000000, 495, 16, 1, 8},
278 { 26000000, 594000000, 594, 26, 1, 8},
279
280 { 12000000, 1000000000, 1000, 12, 1, 12},
281 { 13000000, 1000000000, 1000, 13, 1, 12},
282 { 19200000, 1000000000, 625, 12, 1, 8},
283 { 26000000, 1000000000, 1000, 26, 1, 12},
284
285 { 0, 0, 0, 0, 0, 0 },
286};
287
288static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
289 { 12000000, 480000000, 960, 12, 2, 0},
290 { 13000000, 480000000, 960, 13, 2, 0},
291 { 19200000, 480000000, 200, 4, 2, 0},
292 { 26000000, 480000000, 960, 26, 2, 0},
293 { 0, 0, 0, 0, 0, 0 },
294};
295
296static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
297 /* 1 GHz */
298 { 12000000, 1000000000, 1000, 12, 1, 12},
299 { 13000000, 1000000000, 1000, 13, 1, 12},
300 { 19200000, 1000000000, 625, 12, 1, 8},
301 { 26000000, 1000000000, 1000, 26, 1, 12},
302
303 /* 912 MHz */
304 { 12000000, 912000000, 912, 12, 1, 12},
305 { 13000000, 912000000, 912, 13, 1, 12},
306 { 19200000, 912000000, 760, 16, 1, 8},
307 { 26000000, 912000000, 912, 26, 1, 12},
308
309 /* 816 MHz */
310 { 12000000, 816000000, 816, 12, 1, 12},
311 { 13000000, 816000000, 816, 13, 1, 12},
312 { 19200000, 816000000, 680, 16, 1, 8},
313 { 26000000, 816000000, 816, 26, 1, 12},
314
315 /* 760 MHz */
316 { 12000000, 760000000, 760, 12, 1, 12},
317 { 13000000, 760000000, 760, 13, 1, 12},
318 { 19200000, 760000000, 950, 24, 1, 8},
319 { 26000000, 760000000, 760, 26, 1, 12},
320
321 /* 750 MHz */
322 { 12000000, 750000000, 750, 12, 1, 12},
323 { 13000000, 750000000, 750, 13, 1, 12},
324 { 19200000, 750000000, 625, 16, 1, 8},
325 { 26000000, 750000000, 750, 26, 1, 12},
326
327 /* 608 MHz */
328 { 12000000, 608000000, 608, 12, 1, 12},
329 { 13000000, 608000000, 608, 13, 1, 12},
330 { 19200000, 608000000, 380, 12, 1, 8},
331 { 26000000, 608000000, 608, 26, 1, 12},
332
333 /* 456 MHz */
334 { 12000000, 456000000, 456, 12, 1, 12},
335 { 13000000, 456000000, 456, 13, 1, 12},
336 { 19200000, 456000000, 380, 16, 1, 8},
337 { 26000000, 456000000, 456, 26, 1, 12},
338
339 /* 312 MHz */
340 { 12000000, 312000000, 312, 12, 1, 12},
341 { 13000000, 312000000, 312, 13, 1, 12},
342 { 19200000, 312000000, 260, 16, 1, 8},
343 { 26000000, 312000000, 312, 26, 1, 12},
344
345 { 0, 0, 0, 0, 0, 0 },
346};
347
348static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
349 { 12000000, 100000000, 200, 24, 1, 0 },
350 { 0, 0, 0, 0, 0, 0 },
351};
352
353/* PLL parameters */
354static struct tegra_clk_pll_params pll_c_params = {
355 .input_min = 2000000,
356 .input_max = 31000000,
357 .cf_min = 1000000,
358 .cf_max = 6000000,
359 .vco_min = 20000000,
360 .vco_max = 1400000000,
361 .base_reg = PLLC_BASE,
362 .misc_reg = PLLC_MISC,
363 .lock_bit_idx = PLL_BASE_LOCK,
364 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
365 .lock_delay = 300,
366};
367
368static struct tegra_clk_pll_params pll_m_params = {
369 .input_min = 2000000,
370 .input_max = 31000000,
371 .cf_min = 1000000,
372 .cf_max = 6000000,
373 .vco_min = 20000000,
374 .vco_max = 1200000000,
375 .base_reg = PLLM_BASE,
376 .misc_reg = PLLM_MISC,
377 .lock_bit_idx = PLL_BASE_LOCK,
378 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
379 .lock_delay = 300,
380};
381
382static struct tegra_clk_pll_params pll_p_params = {
383 .input_min = 2000000,
384 .input_max = 31000000,
385 .cf_min = 1000000,
386 .cf_max = 6000000,
387 .vco_min = 20000000,
388 .vco_max = 1400000000,
389 .base_reg = PLLP_BASE,
390 .misc_reg = PLLP_MISC,
391 .lock_bit_idx = PLL_BASE_LOCK,
392 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
393 .lock_delay = 300,
394};
395
396static struct tegra_clk_pll_params pll_a_params = {
397 .input_min = 2000000,
398 .input_max = 31000000,
399 .cf_min = 1000000,
400 .cf_max = 6000000,
401 .vco_min = 20000000,
402 .vco_max = 1400000000,
403 .base_reg = PLLA_BASE,
404 .misc_reg = PLLA_MISC,
405 .lock_bit_idx = PLL_BASE_LOCK,
406 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
407 .lock_delay = 300,
408};
409
410static struct tegra_clk_pll_params pll_d_params = {
411 .input_min = 2000000,
412 .input_max = 40000000,
413 .cf_min = 1000000,
414 .cf_max = 6000000,
415 .vco_min = 40000000,
416 .vco_max = 1000000000,
417 .base_reg = PLLD_BASE,
418 .misc_reg = PLLD_MISC,
419 .lock_bit_idx = PLL_BASE_LOCK,
420 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
421 .lock_delay = 1000,
422};
423
424static struct tegra_clk_pll_params pll_u_params = {
425 .input_min = 2000000,
426 .input_max = 40000000,
427 .cf_min = 1000000,
428 .cf_max = 6000000,
429 .vco_min = 48000000,
430 .vco_max = 960000000,
431 .base_reg = PLLU_BASE,
432 .misc_reg = PLLU_MISC,
433 .lock_bit_idx = PLL_BASE_LOCK,
434 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
435 .lock_delay = 1000,
436};
437
438static struct tegra_clk_pll_params pll_x_params = {
439 .input_min = 2000000,
440 .input_max = 31000000,
441 .cf_min = 1000000,
442 .cf_max = 6000000,
443 .vco_min = 20000000,
444 .vco_max = 1200000000,
445 .base_reg = PLLX_BASE,
446 .misc_reg = PLLX_MISC,
447 .lock_bit_idx = PLL_BASE_LOCK,
448 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
449 .lock_delay = 300,
450};
451
452static struct tegra_clk_pll_params pll_e_params = {
453 .input_min = 12000000,
454 .input_max = 12000000,
455 .cf_min = 0,
456 .cf_max = 0,
457 .vco_min = 0,
458 .vco_max = 0,
459 .base_reg = PLLE_BASE,
460 .misc_reg = PLLE_MISC,
461 .lock_bit_idx = PLLE_MISC_LOCK,
462 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
463 .lock_delay = 0,
464};
465
466/* Peripheral clock registers */
467static struct tegra_clk_periph_regs periph_l_regs = {
468 .enb_reg = CLK_OUT_ENB_L,
469 .enb_set_reg = CLK_OUT_ENB_SET_L,
470 .enb_clr_reg = CLK_OUT_ENB_CLR_L,
471 .rst_reg = RST_DEVICES_L,
472 .rst_set_reg = RST_DEVICES_SET_L,
473 .rst_clr_reg = RST_DEVICES_CLR_L,
474};
475
476static struct tegra_clk_periph_regs periph_h_regs = {
477 .enb_reg = CLK_OUT_ENB_H,
478 .enb_set_reg = CLK_OUT_ENB_SET_H,
479 .enb_clr_reg = CLK_OUT_ENB_CLR_H,
480 .rst_reg = RST_DEVICES_H,
481 .rst_set_reg = RST_DEVICES_SET_H,
482 .rst_clr_reg = RST_DEVICES_CLR_H,
483};
484
485static struct tegra_clk_periph_regs periph_u_regs = {
486 .enb_reg = CLK_OUT_ENB_U,
487 .enb_set_reg = CLK_OUT_ENB_SET_U,
488 .enb_clr_reg = CLK_OUT_ENB_CLR_U,
489 .rst_reg = RST_DEVICES_U,
490 .rst_set_reg = RST_DEVICES_SET_U,
491 .rst_clr_reg = RST_DEVICES_CLR_U,
492};
493
494static unsigned long tegra20_clk_measure_input_freq(void)
495{
496 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL);
497 u32 auto_clk_control = osc_ctrl & OSC_CTRL_OSC_FREQ_MASK;
498 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
499 unsigned long input_freq;
500
501 switch (auto_clk_control) {
502 case OSC_CTRL_OSC_FREQ_12MHZ:
503 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
504 input_freq = 12000000;
505 break;
506 case OSC_CTRL_OSC_FREQ_13MHZ:
507 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
508 input_freq = 13000000;
509 break;
510 case OSC_CTRL_OSC_FREQ_19_2MHZ:
511 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
512 input_freq = 19200000;
513 break;
514 case OSC_CTRL_OSC_FREQ_26MHZ:
515 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
516 input_freq = 26000000;
517 break;
518 default:
519 pr_err("Unexpected clock autodetect value %d",
520 auto_clk_control);
521 BUG();
522 return 0;
523 }
524
525 return input_freq;
526}
527
528static unsigned int tegra20_get_pll_ref_div(void)
529{
530 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) &
531 OSC_CTRL_PLL_REF_DIV_MASK;
532
533 switch (pll_ref_div) {
534 case OSC_CTRL_PLL_REF_DIV_1:
535 return 1;
536 case OSC_CTRL_PLL_REF_DIV_2:
537 return 2;
538 case OSC_CTRL_PLL_REF_DIV_4:
539 return 4;
540 default:
541 pr_err("Invalied pll ref divider %d\n", pll_ref_div);
542 BUG();
543 }
544 return 0;
545}
546
547static void tegra20_pll_init(void)
548{
549 struct clk *clk;
550
551 /* PLLC */
552 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0,
553 0, &pll_c_params, TEGRA_PLL_HAS_CPCON,
554 pll_c_freq_table, NULL);
555 clk_register_clkdev(clk, "pll_c", NULL);
556 clks[pll_c] = clk;
557
558 /* PLLC_OUT1 */
559 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
560 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
561 8, 8, 1, NULL);
562 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
563 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
564 0, NULL);
565 clk_register_clkdev(clk, "pll_c_out1", NULL);
566 clks[pll_c_out1] = clk;
567
568 /* PLLP */
569 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, NULL, 0,
570 216000000, &pll_p_params, TEGRA_PLL_FIXED |
571 TEGRA_PLL_HAS_CPCON, pll_p_freq_table, NULL);
572 clk_register_clkdev(clk, "pll_p", NULL);
573 clks[pll_p] = clk;
574
575 /* PLLP_OUT1 */
576 clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p",
577 clk_base + PLLP_OUTA, 0,
578 TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP,
579 8, 8, 1, &pll_div_lock);
580 clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div",
581 clk_base + PLLP_OUTA, 1, 0,
582 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
583 &pll_div_lock);
584 clk_register_clkdev(clk, "pll_p_out1", NULL);
585 clks[pll_p_out1] = clk;
586
587 /* PLLP_OUT2 */
588 clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p",
589 clk_base + PLLP_OUTA, 0,
590 TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP,
591 24, 8, 1, &pll_div_lock);
592 clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div",
593 clk_base + PLLP_OUTA, 17, 16,
594 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
595 &pll_div_lock);
596 clk_register_clkdev(clk, "pll_p_out2", NULL);
597 clks[pll_p_out2] = clk;
598
599 /* PLLP_OUT3 */
600 clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p",
601 clk_base + PLLP_OUTB, 0,
602 TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP,
603 8, 8, 1, &pll_div_lock);
604 clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div",
605 clk_base + PLLP_OUTB, 1, 0,
606 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
607 &pll_div_lock);
608 clk_register_clkdev(clk, "pll_p_out3", NULL);
609 clks[pll_p_out3] = clk;
610
611 /* PLLP_OUT4 */
612 clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p",
613 clk_base + PLLP_OUTB, 0,
614 TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP,
615 24, 8, 1, &pll_div_lock);
616 clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div",
617 clk_base + PLLP_OUTB, 17, 16,
618 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
619 &pll_div_lock);
620 clk_register_clkdev(clk, "pll_p_out4", NULL);
621 clks[pll_p_out4] = clk;
622
623 /* PLLM */
624 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL,
625 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 0,
626 &pll_m_params, TEGRA_PLL_HAS_CPCON,
627 pll_m_freq_table, NULL);
628 clk_register_clkdev(clk, "pll_m", NULL);
629 clks[pll_m] = clk;
630
631 /* PLLM_OUT1 */
632 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
633 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
634 8, 8, 1, NULL);
635 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
636 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
637 CLK_SET_RATE_PARENT, 0, NULL);
638 clk_register_clkdev(clk, "pll_m_out1", NULL);
639 clks[pll_m_out1] = clk;
640
641 /* PLLX */
642 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0,
643 0, &pll_x_params, TEGRA_PLL_HAS_CPCON,
644 pll_x_freq_table, NULL);
645 clk_register_clkdev(clk, "pll_x", NULL);
646 clks[pll_x] = clk;
647
648 /* PLLU */
649 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0,
650 0, &pll_u_params, TEGRA_PLLU | TEGRA_PLL_HAS_CPCON,
651 pll_u_freq_table, NULL);
652 clk_register_clkdev(clk, "pll_u", NULL);
653 clks[pll_u] = clk;
654
655 /* PLLD */
656 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0,
657 0, &pll_d_params, TEGRA_PLL_HAS_CPCON,
658 pll_d_freq_table, NULL);
659 clk_register_clkdev(clk, "pll_d", NULL);
660 clks[pll_d] = clk;
661
662 /* PLLD_OUT0 */
663 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
664 CLK_SET_RATE_PARENT, 1, 2);
665 clk_register_clkdev(clk, "pll_d_out0", NULL);
666 clks[pll_d_out0] = clk;
667
668 /* PLLA */
669 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0,
670 0, &pll_a_params, TEGRA_PLL_HAS_CPCON,
671 pll_a_freq_table, NULL);
672 clk_register_clkdev(clk, "pll_a", NULL);
673 clks[pll_a] = clk;
674
675 /* PLLA_OUT0 */
676 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
677 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
678 8, 8, 1, NULL);
679 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
680 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
681 CLK_SET_RATE_PARENT, 0, NULL);
682 clk_register_clkdev(clk, "pll_a_out0", NULL);
683 clks[pll_a_out0] = clk;
684
685 /* PLLE */
686 clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, NULL,
687 0, 100000000, &pll_e_params,
688 0, pll_e_freq_table, NULL);
689 clk_register_clkdev(clk, "pll_e", NULL);
690 clks[pll_e] = clk;
691}
692
693static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
694 "pll_p_cclk", "pll_p_out4_cclk",
695 "pll_p_out3_cclk", "clk_d", "pll_x" };
696static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
697 "pll_p_out3", "pll_p_out2", "clk_d",
698 "clk_32k", "pll_m_out1" };
699
700static void tegra20_super_clk_init(void)
701{
702 struct clk *clk;
703
704 /*
705 * DIV_U71 dividers for CCLK, these dividers are used only
706 * if parent clock is fixed rate.
707 */
708
709 /*
710 * Clock input to cclk divided from pll_p using
711 * U71 divider of cclk.
712 */
713 clk = tegra_clk_register_divider("pll_p_cclk", "pll_p",
714 clk_base + SUPER_CCLK_DIVIDER, 0,
715 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
716 clk_register_clkdev(clk, "pll_p_cclk", NULL);
717
718 /*
719 * Clock input to cclk divided from pll_p_out3 using
720 * U71 divider of cclk.
721 */
722 clk = tegra_clk_register_divider("pll_p_out3_cclk", "pll_p_out3",
723 clk_base + SUPER_CCLK_DIVIDER, 0,
724 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
725 clk_register_clkdev(clk, "pll_p_out3_cclk", NULL);
726
727 /*
728 * Clock input to cclk divided from pll_p_out4 using
729 * U71 divider of cclk.
730 */
731 clk = tegra_clk_register_divider("pll_p_out4_cclk", "pll_p_out4",
732 clk_base + SUPER_CCLK_DIVIDER, 0,
733 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
734 clk_register_clkdev(clk, "pll_p_out4_cclk", NULL);
735
736 /* CCLK */
737 clk = tegra_clk_register_super_mux("cclk", cclk_parents,
738 ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT,
739 clk_base + CCLK_BURST_POLICY, 0, 4, 0, 0, NULL);
740 clk_register_clkdev(clk, "cclk", NULL);
741 clks[cclk] = clk;
742
743 /* SCLK */
744 clk = tegra_clk_register_super_mux("sclk", sclk_parents,
745 ARRAY_SIZE(sclk_parents), CLK_SET_RATE_PARENT,
746 clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL);
747 clk_register_clkdev(clk, "sclk", NULL);
748 clks[sclk] = clk;
749
750 /* HCLK */
751 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
752 clk_base + CLK_SYSTEM_RATE, 4, 2, 0, NULL);
753 clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT,
754 clk_base + CLK_SYSTEM_RATE, 7,
755 CLK_GATE_SET_TO_DISABLE, NULL);
756 clk_register_clkdev(clk, "hclk", NULL);
757 clks[hclk] = clk;
758
759 /* PCLK */
760 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
761 clk_base + CLK_SYSTEM_RATE, 0, 2, 0, NULL);
762 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT,
763 clk_base + CLK_SYSTEM_RATE, 3,
764 CLK_GATE_SET_TO_DISABLE, NULL);
765 clk_register_clkdev(clk, "pclk", NULL);
766 clks[pclk] = clk;
767
768 /* twd */
769 clk = clk_register_fixed_factor(NULL, "twd", "cclk", 0, 1, 4);
770 clk_register_clkdev(clk, "twd", NULL);
771 clks[twd] = clk;
772}
773
774static const char *audio_parents[] = {"spdif_in", "i2s1", "i2s2", "unused",
775 "pll_a_out0", "unused", "unused",
776 "unused"};
777
778static void __init tegra20_audio_clk_init(void)
779{
780 struct clk *clk;
781
782 /* audio */
783 clk = clk_register_mux(NULL, "audio_mux", audio_parents,
784 ARRAY_SIZE(audio_parents), 0,
785 clk_base + AUDIO_SYNC_CLK, 0, 3, 0, NULL);
786 clk = clk_register_gate(NULL, "audio", "audio_mux", 0,
787 clk_base + AUDIO_SYNC_CLK, 4,
788 CLK_GATE_SET_TO_DISABLE, NULL);
789 clk_register_clkdev(clk, "audio", NULL);
790 clks[audio] = clk;
791
792 /* audio_2x */
793 clk = clk_register_fixed_factor(NULL, "audio_doubler", "audio",
794 CLK_SET_RATE_PARENT, 2, 1);
795 clk = tegra_clk_register_periph_gate("audio_2x", "audio_doubler",
796 TEGRA_PERIPH_NO_RESET, clk_base,
797 CLK_SET_RATE_PARENT, 89, &periph_u_regs,
798 periph_clk_enb_refcnt);
799 clk_register_clkdev(clk, "audio_2x", NULL);
800 clks[audio_2x] = clk;
801
802}
803
804static const char *i2s1_parents[] = {"pll_a_out0", "audio_2x", "pll_p",
805 "clk_m"};
806static const char *i2s2_parents[] = {"pll_a_out0", "audio_2x", "pll_p",
807 "clk_m"};
808static const char *spdif_out_parents[] = {"pll_a_out0", "audio_2x", "pll_p",
809 "clk_m"};
810static const char *spdif_in_parents[] = {"pll_p", "pll_c", "pll_m"};
811static const char *pwm_parents[] = {"pll_p", "pll_c", "audio", "clk_m",
812 "clk_32k"};
813static const char *mux_pllpcm_clkm[] = {"pll_p", "pll_c", "pll_m", "clk_m"};
814static const char *mux_pllmcpa[] = {"pll_m", "pll_c", "pll_c", "pll_a"};
815static const char *mux_pllpdc_clkm[] = {"pll_p", "pll_d_out0", "pll_c",
816 "clk_m"};
817static const char *mux_pllmcp_clkm[] = {"pll_m", "pll_c", "pll_p", "clk_m"};
818
819static struct tegra_periph_init_data tegra_periph_clk_list[] = {
820 TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra20-i2s.0", i2s1_parents, CLK_SOURCE_I2S1, 11, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s1),
821 TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra20-i2s.1", i2s2_parents, CLK_SOURCE_I2S2, 18, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s2),
822 TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra20-spdif", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_out),
823 TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra20-spdif", spdif_in_parents, CLK_SOURCE_SPDIF_IN, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_in),
824 TEGRA_INIT_DATA_MUX("sbc1", NULL, "spi_tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1),
825 TEGRA_INIT_DATA_MUX("sbc2", NULL, "spi_tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SBC2, 44, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2),
826 TEGRA_INIT_DATA_MUX("sbc3", NULL, "spi_tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SBC3, 46, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3),
827 TEGRA_INIT_DATA_MUX("sbc4", NULL, "spi_tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SBC4, 68, &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4),
828 TEGRA_INIT_DATA_MUX("spi", NULL, "spi", mux_pllpcm_clkm, CLK_SOURCE_SPI, 43, &periph_h_regs, TEGRA_PERIPH_ON_APB, spi),
829 TEGRA_INIT_DATA_MUX("xio", NULL, "xio", mux_pllpcm_clkm, CLK_SOURCE_XIO, 45, &periph_h_regs, 0, xio),
830 TEGRA_INIT_DATA_MUX("twc", NULL, "twc", mux_pllpcm_clkm, CLK_SOURCE_TWC, 16, &periph_l_regs, TEGRA_PERIPH_ON_APB, twc),
831 TEGRA_INIT_DATA_MUX("ide", NULL, "ide", mux_pllpcm_clkm, CLK_SOURCE_XIO, 25, &periph_l_regs, 0, ide),
832 TEGRA_INIT_DATA_MUX("ndflash", NULL, "tegra_nand", mux_pllpcm_clkm, CLK_SOURCE_NDFLASH, 13, &periph_l_regs, 0, ndflash),
833 TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllpcm_clkm, CLK_SOURCE_VFIR, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, vfir),
834 TEGRA_INIT_DATA_MUX("csite", NULL, "csite", mux_pllpcm_clkm, CLK_SOURCE_CSITE, 73, &periph_u_regs, 0, csite),
835 TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllpcm_clkm, CLK_SOURCE_LA, 76, &periph_u_regs, 0, la),
836 TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllpcm_clkm, CLK_SOURCE_OWR, 71, &periph_u_regs, TEGRA_PERIPH_ON_APB, owr),
837 TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllpcm_clkm, CLK_SOURCE_MIPI, 50, &periph_h_regs, TEGRA_PERIPH_ON_APB, mipi),
838 TEGRA_INIT_DATA_MUX("vde", NULL, "vde", mux_pllpcm_clkm, CLK_SOURCE_VDE, 61, &periph_h_regs, 0, vde),
839 TEGRA_INIT_DATA_MUX("vi", "vi", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI, 20, &periph_l_regs, 0, vi),
840 TEGRA_INIT_DATA_MUX("epp", NULL, "epp", mux_pllmcpa, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, epp),
841 TEGRA_INIT_DATA_MUX("mpe", NULL, "mpe", mux_pllmcpa, CLK_SOURCE_MPE, 60, &periph_h_regs, 0, mpe),
842 TEGRA_INIT_DATA_MUX("host1x", NULL, "host1x", mux_pllmcpa, CLK_SOURCE_HOST1X, 28, &periph_l_regs, 0, host1x),
843 TEGRA_INIT_DATA_MUX("3d", NULL, "3d", mux_pllmcpa, CLK_SOURCE_3D, 24, &periph_l_regs, TEGRA_PERIPH_MANUAL_RESET, gr3d),
844 TEGRA_INIT_DATA_MUX("2d", NULL, "2d", mux_pllmcpa, CLK_SOURCE_2D, 21, &periph_l_regs, 0, gr2d),
845 TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllpcm_clkm, CLK_SOURCE_NOR, 42, &periph_h_regs, 0, nor),
846 TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SDMMC1, 14, &periph_l_regs, 0, sdmmc1),
847 TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SDMMC2, 9, &periph_l_regs, 0, sdmmc2),
848 TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SDMMC3, 69, &periph_u_regs, 0, sdmmc3),
849 TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SDMMC4, 15, &periph_l_regs, 0, sdmmc4),
850 TEGRA_INIT_DATA_MUX("cve", NULL, "cve", mux_pllpdc_clkm, CLK_SOURCE_CVE, 49, &periph_h_regs, 0, cve),
851 TEGRA_INIT_DATA_MUX("tvo", NULL, "tvo", mux_pllpdc_clkm, CLK_SOURCE_TVO, 49, &periph_h_regs, 0, tvo),
852 TEGRA_INIT_DATA_MUX("tvdac", NULL, "tvdac", mux_pllpdc_clkm, CLK_SOURCE_TVDAC, 53, &periph_h_regs, 0, tvdac),
853 TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor),
854 TEGRA_INIT_DATA_DIV16("i2c1", "div-clk", "tegra-i2c.0", mux_pllpcm_clkm, CLK_SOURCE_I2C1, 12, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2c1),
855 TEGRA_INIT_DATA_DIV16("i2c2", "div-clk", "tegra-i2c.1", mux_pllpcm_clkm, CLK_SOURCE_I2C2, 54, &periph_h_regs, TEGRA_PERIPH_ON_APB, i2c2),
856 TEGRA_INIT_DATA_DIV16("i2c3", "div-clk", "tegra-i2c.2", mux_pllpcm_clkm, CLK_SOURCE_I2C3, 67, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2c3),
857 TEGRA_INIT_DATA_DIV16("dvc", "div-clk", "tegra-i2c.3", mux_pllpcm_clkm, CLK_SOURCE_DVC, 47, &periph_h_regs, TEGRA_PERIPH_ON_APB, dvc),
858 TEGRA_INIT_DATA_MUX("hdmi", NULL, "hdmi", mux_pllpdc_clkm, CLK_SOURCE_HDMI, 51, &periph_h_regs, 0, hdmi),
859 TEGRA_INIT_DATA("pwm", NULL, "tegra-pwm", pwm_parents, CLK_SOURCE_PWM, 28, 3, 0, 0, 8, 1, 0, &periph_l_regs, 17, periph_clk_enb_refcnt, TEGRA_PERIPH_ON_APB, pwm),
860};
861
862static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
863 TEGRA_INIT_DATA_NODIV("uarta", NULL, "tegra_uart.0", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 30, 2, 6, &periph_l_regs, TEGRA_PERIPH_ON_APB, uarta),
864 TEGRA_INIT_DATA_NODIV("uartb", NULL, "tegra_uart.1", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 30, 2, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, uartb),
865 TEGRA_INIT_DATA_NODIV("uartc", NULL, "tegra_uart.2", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 30, 2, 55, &periph_h_regs, TEGRA_PERIPH_ON_APB, uartc),
866 TEGRA_INIT_DATA_NODIV("uartd", NULL, "tegra_uart.3", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 30, 2, 65, &periph_u_regs, TEGRA_PERIPH_ON_APB, uartd),
867 TEGRA_INIT_DATA_NODIV("uarte", NULL, "tegra_uart.4", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 30, 2, 66, &periph_u_regs, TEGRA_PERIPH_ON_APB, uarte),
868 TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllpdc_clkm, CLK_SOURCE_DISP1, 30, 2, 27, &periph_l_regs, 0, disp1),
869 TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2, 26, &periph_l_regs, 0, disp2),
870};
871
872static void __init tegra20_periph_clk_init(void)
873{
874 struct tegra_periph_init_data *data;
875 struct clk *clk;
876 int i;
877
878 /* apbdma */
879 clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base,
880 0, 34, &periph_h_regs,
881 periph_clk_enb_refcnt);
882 clk_register_clkdev(clk, NULL, "tegra-apbdma");
883 clks[apbdma] = clk;
884
885 /* rtc */
886 clk = tegra_clk_register_periph_gate("rtc", "clk_32k",
887 TEGRA_PERIPH_NO_RESET,
888 clk_base, 0, 4, &periph_l_regs,
889 periph_clk_enb_refcnt);
890 clk_register_clkdev(clk, NULL, "rtc-tegra");
891 clks[rtc] = clk;
892
893 /* timer */
894 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base,
895 0, 5, &periph_l_regs,
896 periph_clk_enb_refcnt);
897 clk_register_clkdev(clk, NULL, "timer");
898 clks[timer] = clk;
899
900 /* kbc */
901 clk = tegra_clk_register_periph_gate("kbc", "clk_32k",
902 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
903 clk_base, 0, 36, &periph_h_regs,
904 periph_clk_enb_refcnt);
905 clk_register_clkdev(clk, NULL, "tegra-kbc");
906 clks[kbc] = clk;
907
908 /* csus */
909 clk = tegra_clk_register_periph_gate("csus", "clk_m",
910 TEGRA_PERIPH_NO_RESET,
911 clk_base, 0, 92, &periph_u_regs,
912 periph_clk_enb_refcnt);
913 clk_register_clkdev(clk, "csus", "tengra_camera");
914 clks[csus] = clk;
915
916 /* vcp */
917 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0,
918 clk_base, 0, 29, &periph_l_regs,
919 periph_clk_enb_refcnt);
920 clk_register_clkdev(clk, "vcp", "tegra-avp");
921 clks[vcp] = clk;
922
923 /* bsea */
924 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0,
925 clk_base, 0, 62, &periph_h_regs,
926 periph_clk_enb_refcnt);
927 clk_register_clkdev(clk, "bsea", "tegra-avp");
928 clks[bsea] = clk;
929
930 /* bsev */
931 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0,
932 clk_base, 0, 63, &periph_h_regs,
933 periph_clk_enb_refcnt);
934 clk_register_clkdev(clk, "bsev", "tegra-aes");
935 clks[bsev] = clk;
936
937 /* emc */
938 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
939 ARRAY_SIZE(mux_pllmcp_clkm), 0,
940 clk_base + CLK_SOURCE_EMC,
941 30, 2, 0, NULL);
942 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
943 57, &periph_h_regs, periph_clk_enb_refcnt);
944 clk_register_clkdev(clk, "emc", NULL);
945 clks[emc] = clk;
946
947 /* usbd */
948 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, 0,
949 22, &periph_l_regs, periph_clk_enb_refcnt);
950 clk_register_clkdev(clk, NULL, "fsl-tegra-udc");
951 clks[usbd] = clk;
952
953 /* usb2 */
954 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, 0,
955 58, &periph_h_regs, periph_clk_enb_refcnt);
956 clk_register_clkdev(clk, NULL, "tegra-ehci.1");
957 clks[usb2] = clk;
958
959 /* usb3 */
960 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, 0,
961 59, &periph_h_regs, periph_clk_enb_refcnt);
962 clk_register_clkdev(clk, NULL, "tegra-ehci.2");
963 clks[usb3] = clk;
964
965 /* dsi */
966 clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0,
967 48, &periph_h_regs, periph_clk_enb_refcnt);
968 clk_register_clkdev(clk, NULL, "dsi");
969 clks[dsi] = clk;
970
971 /* csi */
972 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base,
973 0, 52, &periph_h_regs,
974 periph_clk_enb_refcnt);
975 clk_register_clkdev(clk, "csi", "tegra_camera");
976 clks[csi] = clk;
977
978 /* isp */
979 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, 23,
980 &periph_l_regs, periph_clk_enb_refcnt);
981 clk_register_clkdev(clk, "isp", "tegra_camera");
982 clks[isp] = clk;
983
984 /* pex */
985 clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70,
986 &periph_u_regs, periph_clk_enb_refcnt);
987 clk_register_clkdev(clk, "pex", NULL);
988 clks[pex] = clk;
989
990 /* afi */
991 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72,
992 &periph_u_regs, periph_clk_enb_refcnt);
993 clk_register_clkdev(clk, "afi", NULL);
994 clks[afi] = clk;
995
996 /* pcie_xclk */
997 clk = tegra_clk_register_periph_gate("pcie_xclk", "clk_m", 0, clk_base,
998 0, 74, &periph_u_regs,
999 periph_clk_enb_refcnt);
1000 clk_register_clkdev(clk, "pcie_xclk", NULL);
1001 clks[pcie_xclk] = clk;
1002
1003 /* cdev1 */
1004 clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, CLK_IS_ROOT,
1005 26000000);
1006 clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0,
1007 clk_base, 0, 94, &periph_u_regs,
1008 periph_clk_enb_refcnt);
1009 clk_register_clkdev(clk, "cdev1", NULL);
1010 clks[cdev1] = clk;
1011
1012 /* cdev2 */
1013 clk = clk_register_fixed_rate(NULL, "cdev2_fixed", NULL, CLK_IS_ROOT,
1014 26000000);
1015 clk = tegra_clk_register_periph_gate("cdev2", "cdev2_fixed", 0,
1016 clk_base, 0, 93, &periph_u_regs,
1017 periph_clk_enb_refcnt);
1018 clk_register_clkdev(clk, "cdev2", NULL);
1019 clks[cdev2] = clk;
1020
1021 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
1022 data = &tegra_periph_clk_list[i];
1023 clk = tegra_clk_register_periph(data->name, data->parent_names,
1024 data->num_parents, &data->periph,
1025 clk_base, data->offset);
1026 clk_register_clkdev(clk, data->con_id, data->dev_id);
1027 clks[data->clk_id] = clk;
1028 }
1029
1030 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
1031 data = &tegra_periph_nodiv_clk_list[i];
1032 clk = tegra_clk_register_periph_nodiv(data->name,
1033 data->parent_names,
1034 data->num_parents, &data->periph,
1035 clk_base, data->offset);
1036 clk_register_clkdev(clk, data->con_id, data->dev_id);
1037 clks[data->clk_id] = clk;
1038 }
1039}
1040
1041
1042static void __init tegra20_fixed_clk_init(void)
1043{
1044 struct clk *clk;
1045
1046 /* clk_32k */
1047 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT,
1048 32768);
1049 clk_register_clkdev(clk, "clk_32k", NULL);
1050 clks[clk_32k] = clk;
1051}
1052
1053static void __init tegra20_pmc_clk_init(void)
1054{
1055 struct clk *clk;
1056
1057 /* blink */
1058 writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
1059 clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
1060 pmc_base + PMC_DPD_PADS_ORIDE,
1061 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
1062 clk = clk_register_gate(NULL, "blink", "blink_override", 0,
1063 pmc_base + PMC_CTRL,
1064 PMC_CTRL_BLINK_ENB, 0, NULL);
1065 clk_register_clkdev(clk, "blink", NULL);
1066 clks[blink] = clk;
1067}
1068
1069static void __init tegra20_osc_clk_init(void)
1070{
1071 struct clk *clk;
1072 unsigned long input_freq;
1073 unsigned int pll_ref_div;
1074
1075 input_freq = tegra20_clk_measure_input_freq();
1076
1077 /* clk_m */
1078 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT |
1079 CLK_IGNORE_UNUSED, input_freq);
1080 clk_register_clkdev(clk, "clk_m", NULL);
1081 clks[clk_m] = clk;
1082
1083 /* pll_ref */
1084 pll_ref_div = tegra20_get_pll_ref_div();
1085 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
1086 CLK_SET_RATE_PARENT, 1, pll_ref_div);
1087 clk_register_clkdev(clk, "pll_ref", NULL);
1088 clks[pll_ref] = clk;
1089}
1090
1091/* Tegra20 CPU clock and reset control functions */
1092static void tegra20_wait_cpu_in_reset(u32 cpu)
1093{
1094 unsigned int reg;
1095
1096 do {
1097 reg = readl(clk_base +
1098 TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
1099 cpu_relax();
1100 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
1101
1102 return;
1103}
1104
1105static void tegra20_put_cpu_in_reset(u32 cpu)
1106{
1107 writel(CPU_RESET(cpu),
1108 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
1109 dmb();
1110}
1111
1112static void tegra20_cpu_out_of_reset(u32 cpu)
1113{
1114 writel(CPU_RESET(cpu),
1115 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
1116 wmb();
1117}
1118
1119static void tegra20_enable_cpu_clock(u32 cpu)
1120{
1121 unsigned int reg;
1122
1123 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1124 writel(reg & ~CPU_CLOCK(cpu),
1125 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1126 barrier();
1127 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1128}
1129
1130static void tegra20_disable_cpu_clock(u32 cpu)
1131{
1132 unsigned int reg;
1133
1134 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1135 writel(reg | CPU_CLOCK(cpu),
1136 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1137}
1138
1139static struct tegra_cpu_car_ops tegra20_cpu_car_ops = {
1140 .wait_for_reset = tegra20_wait_cpu_in_reset,
1141 .put_in_reset = tegra20_put_cpu_in_reset,
1142 .out_of_reset = tegra20_cpu_out_of_reset,
1143 .enable_clock = tegra20_enable_cpu_clock,
1144 .disable_clock = tegra20_disable_cpu_clock,
1145};
1146
1147static __initdata struct tegra_clk_init_table init_table[] = {
1148 {pll_p, clk_max, 216000000, 1},
1149 {pll_p_out1, clk_max, 28800000, 1},
1150 {pll_p_out2, clk_max, 48000000, 1},
1151 {pll_p_out3, clk_max, 72000000, 1},
1152 {pll_p_out4, clk_max, 24000000, 1},
1153 {pll_c, clk_max, 600000000, 1},
1154 {pll_c_out1, clk_max, 120000000, 1},
1155 {sclk, pll_c_out1, 0, 1},
1156 {hclk, clk_max, 0, 1},
1157 {pclk, clk_max, 60000000, 1},
1158 {csite, clk_max, 0, 1},
1159 {emc, clk_max, 0, 1},
1160 {cclk, clk_max, 0, 1},
1161 {uarta, pll_p, 0, 1},
1162 {uartd, pll_p, 0, 1},
1163 {usbd, clk_max, 12000000, 0},
1164 {usb2, clk_max, 12000000, 0},
1165 {usb3, clk_max, 12000000, 0},
1166 {pll_a, clk_max, 56448000, 1},
1167 {pll_a_out0, clk_max, 11289600, 1},
1168 {cdev1, clk_max, 0, 1},
1169 {blink, clk_max, 32768, 1},
1170 {i2s1, pll_a_out0, 11289600, 0},
1171 {i2s2, pll_a_out0, 11289600, 0},
1172 {sdmmc1, pll_p, 48000000, 0},
1173 {sdmmc3, pll_p, 48000000, 0},
1174 {sdmmc4, pll_p, 48000000, 0},
1175 {spi, pll_p, 20000000, 0},
1176 {sbc1, pll_p, 100000000, 0},
1177 {sbc2, pll_p, 100000000, 0},
1178 {sbc3, pll_p, 100000000, 0},
1179 {sbc4, pll_p, 100000000, 0},
1180 {host1x, pll_c, 150000000, 0},
1181 {disp1, pll_p, 600000000, 0},
1182 {disp2, pll_p, 600000000, 0},
1183 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry */
1184};
1185
1186/*
1187 * Some clocks may be used by different drivers depending on the board
1188 * configuration. List those here to register them twice in the clock lookup
1189 * table under two names.
1190 */
1191static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
1192 TEGRA_CLK_DUPLICATE(usbd, "utmip-pad", NULL),
1193 TEGRA_CLK_DUPLICATE(usbd, "tegra-ehci.0", NULL),
1194 TEGRA_CLK_DUPLICATE(usbd, "tegra-otg", NULL),
1195 TEGRA_CLK_DUPLICATE(cclk, NULL, "cpu"),
1196 TEGRA_CLK_DUPLICATE(twd, "smp_twd", NULL),
1197 TEGRA_CLK_DUPLICATE(clk_max, NULL, NULL), /* Must be the last entry */
1198};
1199
1200static const struct of_device_id pmc_match[] __initconst = {
1201 { .compatible = "nvidia,tegra20-pmc" },
1202 {},
1203};
1204
1205void __init tegra20_clock_init(struct device_node *np)
1206{
1207 int i;
1208 struct device_node *node;
1209
1210 clk_base = of_iomap(np, 0);
1211 if (!clk_base) {
1212 pr_err("Can't map CAR registers\n");
1213 BUG();
1214 }
1215
1216 node = of_find_matching_node(NULL, pmc_match);
1217 if (!node) {
1218 pr_err("Failed to find pmc node\n");
1219 BUG();
1220 }
1221
1222 pmc_base = of_iomap(node, 0);
1223 if (!pmc_base) {
1224 pr_err("Can't map pmc registers\n");
1225 BUG();
1226 }
1227
1228 tegra20_osc_clk_init();
1229 tegra20_pmc_clk_init();
1230 tegra20_fixed_clk_init();
1231 tegra20_pll_init();
1232 tegra20_super_clk_init();
1233 tegra20_periph_clk_init();
1234 tegra20_audio_clk_init();
1235
1236
1237 for (i = 0; i < ARRAY_SIZE(clks); i++) {
1238 if (IS_ERR(clks[i])) {
1239 pr_err("Tegra20 clk %d: register failed with %ld\n",
1240 i, PTR_ERR(clks[i]));
1241 BUG();
1242 }
1243 if (!clks[i])
1244 clks[i] = ERR_PTR(-EINVAL);
1245 }
1246
1247 tegra_init_dup_clks(tegra_clk_duplicates, clks, clk_max);
1248
1249 clk_data.clks = clks;
1250 clk_data.clk_num = ARRAY_SIZE(clks);
1251 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
1252
1253 tegra_init_from_table(init_table, clks, clk_max);
1254
1255 tegra_cpu_car_ops = &tegra20_cpu_car_ops;
1256}
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
new file mode 100644
index 000000000000..a1638129eba4
--- /dev/null
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -0,0 +1,1987 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/io.h>
18#include <linux/delay.h>
19#include <linux/clk.h>
20#include <linux/clk-provider.h>
21#include <linux/clkdev.h>
22#include <linux/of.h>
23#include <linux/of_address.h>
24#include <linux/clk/tegra.h>
25
26#include <mach/powergate.h>
27
28#include "clk.h"
29
30#define RST_DEVICES_L 0x004
31#define RST_DEVICES_H 0x008
32#define RST_DEVICES_U 0x00c
33#define RST_DEVICES_V 0x358
34#define RST_DEVICES_W 0x35c
35#define RST_DEVICES_SET_L 0x300
36#define RST_DEVICES_CLR_L 0x304
37#define RST_DEVICES_SET_H 0x308
38#define RST_DEVICES_CLR_H 0x30c
39#define RST_DEVICES_SET_U 0x310
40#define RST_DEVICES_CLR_U 0x314
41#define RST_DEVICES_SET_V 0x430
42#define RST_DEVICES_CLR_V 0x434
43#define RST_DEVICES_SET_W 0x438
44#define RST_DEVICES_CLR_W 0x43c
45#define RST_DEVICES_NUM 5
46
47#define CLK_OUT_ENB_L 0x010
48#define CLK_OUT_ENB_H 0x014
49#define CLK_OUT_ENB_U 0x018
50#define CLK_OUT_ENB_V 0x360
51#define CLK_OUT_ENB_W 0x364
52#define CLK_OUT_ENB_SET_L 0x320
53#define CLK_OUT_ENB_CLR_L 0x324
54#define CLK_OUT_ENB_SET_H 0x328
55#define CLK_OUT_ENB_CLR_H 0x32c
56#define CLK_OUT_ENB_SET_U 0x330
57#define CLK_OUT_ENB_CLR_U 0x334
58#define CLK_OUT_ENB_SET_V 0x440
59#define CLK_OUT_ENB_CLR_V 0x444
60#define CLK_OUT_ENB_SET_W 0x448
61#define CLK_OUT_ENB_CLR_W 0x44c
62#define CLK_OUT_ENB_NUM 5
63
64#define OSC_CTRL 0x50
65#define OSC_CTRL_OSC_FREQ_MASK (0xF<<28)
66#define OSC_CTRL_OSC_FREQ_13MHZ (0X0<<28)
67#define OSC_CTRL_OSC_FREQ_19_2MHZ (0X4<<28)
68#define OSC_CTRL_OSC_FREQ_12MHZ (0X8<<28)
69#define OSC_CTRL_OSC_FREQ_26MHZ (0XC<<28)
70#define OSC_CTRL_OSC_FREQ_16_8MHZ (0X1<<28)
71#define OSC_CTRL_OSC_FREQ_38_4MHZ (0X5<<28)
72#define OSC_CTRL_OSC_FREQ_48MHZ (0X9<<28)
73#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
74
75#define OSC_CTRL_PLL_REF_DIV_MASK (3<<26)
76#define OSC_CTRL_PLL_REF_DIV_1 (0<<26)
77#define OSC_CTRL_PLL_REF_DIV_2 (1<<26)
78#define OSC_CTRL_PLL_REF_DIV_4 (2<<26)
79
80#define OSC_FREQ_DET 0x58
81#define OSC_FREQ_DET_TRIG BIT(31)
82
83#define OSC_FREQ_DET_STATUS 0x5c
84#define OSC_FREQ_DET_BUSY BIT(31)
85#define OSC_FREQ_DET_CNT_MASK 0xffff
86
87#define CCLKG_BURST_POLICY 0x368
88#define SUPER_CCLKG_DIVIDER 0x36c
89#define CCLKLP_BURST_POLICY 0x370
90#define SUPER_CCLKLP_DIVIDER 0x374
91#define SCLK_BURST_POLICY 0x028
92#define SUPER_SCLK_DIVIDER 0x02c
93
94#define SYSTEM_CLK_RATE 0x030
95
96#define PLLC_BASE 0x80
97#define PLLC_MISC 0x8c
98#define PLLM_BASE 0x90
99#define PLLM_MISC 0x9c
100#define PLLP_BASE 0xa0
101#define PLLP_MISC 0xac
102#define PLLX_BASE 0xe0
103#define PLLX_MISC 0xe4
104#define PLLD_BASE 0xd0
105#define PLLD_MISC 0xdc
106#define PLLD2_BASE 0x4b8
107#define PLLD2_MISC 0x4bc
108#define PLLE_BASE 0xe8
109#define PLLE_MISC 0xec
110#define PLLA_BASE 0xb0
111#define PLLA_MISC 0xbc
112#define PLLU_BASE 0xc0
113#define PLLU_MISC 0xcc
114
115#define PLL_MISC_LOCK_ENABLE 18
116#define PLLDU_MISC_LOCK_ENABLE 22
117#define PLLE_MISC_LOCK_ENABLE 9
118
119#define PLL_BASE_LOCK 27
120#define PLLE_MISC_LOCK 11
121
122#define PLLE_AUX 0x48c
123#define PLLC_OUT 0x84
124#define PLLM_OUT 0x94
125#define PLLP_OUTA 0xa4
126#define PLLP_OUTB 0xa8
127#define PLLA_OUT 0xb4
128
129#define AUDIO_SYNC_CLK_I2S0 0x4a0
130#define AUDIO_SYNC_CLK_I2S1 0x4a4
131#define AUDIO_SYNC_CLK_I2S2 0x4a8
132#define AUDIO_SYNC_CLK_I2S3 0x4ac
133#define AUDIO_SYNC_CLK_I2S4 0x4b0
134#define AUDIO_SYNC_CLK_SPDIF 0x4b4
135
136#define PMC_CLK_OUT_CNTRL 0x1a8
137
138#define CLK_SOURCE_I2S0 0x1d8
139#define CLK_SOURCE_I2S1 0x100
140#define CLK_SOURCE_I2S2 0x104
141#define CLK_SOURCE_I2S3 0x3bc
142#define CLK_SOURCE_I2S4 0x3c0
143#define CLK_SOURCE_SPDIF_OUT 0x108
144#define CLK_SOURCE_SPDIF_IN 0x10c
145#define CLK_SOURCE_PWM 0x110
146#define CLK_SOURCE_D_AUDIO 0x3d0
147#define CLK_SOURCE_DAM0 0x3d8
148#define CLK_SOURCE_DAM1 0x3dc
149#define CLK_SOURCE_DAM2 0x3e0
150#define CLK_SOURCE_HDA 0x428
151#define CLK_SOURCE_HDA2CODEC_2X 0x3e4
152#define CLK_SOURCE_SBC1 0x134
153#define CLK_SOURCE_SBC2 0x118
154#define CLK_SOURCE_SBC3 0x11c
155#define CLK_SOURCE_SBC4 0x1b4
156#define CLK_SOURCE_SBC5 0x3c8
157#define CLK_SOURCE_SBC6 0x3cc
158#define CLK_SOURCE_SATA_OOB 0x420
159#define CLK_SOURCE_SATA 0x424
160#define CLK_SOURCE_NDFLASH 0x160
161#define CLK_SOURCE_NDSPEED 0x3f8
162#define CLK_SOURCE_VFIR 0x168
163#define CLK_SOURCE_SDMMC1 0x150
164#define CLK_SOURCE_SDMMC2 0x154
165#define CLK_SOURCE_SDMMC3 0x1bc
166#define CLK_SOURCE_SDMMC4 0x164
167#define CLK_SOURCE_VDE 0x1c8
168#define CLK_SOURCE_CSITE 0x1d4
169#define CLK_SOURCE_LA 0x1f8
170#define CLK_SOURCE_OWR 0x1cc
171#define CLK_SOURCE_NOR 0x1d0
172#define CLK_SOURCE_MIPI 0x174
173#define CLK_SOURCE_I2C1 0x124
174#define CLK_SOURCE_I2C2 0x198
175#define CLK_SOURCE_I2C3 0x1b8
176#define CLK_SOURCE_I2C4 0x3c4
177#define CLK_SOURCE_I2C5 0x128
178#define CLK_SOURCE_UARTA 0x178
179#define CLK_SOURCE_UARTB 0x17c
180#define CLK_SOURCE_UARTC 0x1a0
181#define CLK_SOURCE_UARTD 0x1c0
182#define CLK_SOURCE_UARTE 0x1c4
183#define CLK_SOURCE_VI 0x148
184#define CLK_SOURCE_VI_SENSOR 0x1a8
185#define CLK_SOURCE_3D 0x158
186#define CLK_SOURCE_3D2 0x3b0
187#define CLK_SOURCE_2D 0x15c
188#define CLK_SOURCE_EPP 0x16c
189#define CLK_SOURCE_MPE 0x170
190#define CLK_SOURCE_HOST1X 0x180
191#define CLK_SOURCE_CVE 0x140
192#define CLK_SOURCE_TVO 0x188
193#define CLK_SOURCE_DTV 0x1dc
194#define CLK_SOURCE_HDMI 0x18c
195#define CLK_SOURCE_TVDAC 0x194
196#define CLK_SOURCE_DISP1 0x138
197#define CLK_SOURCE_DISP2 0x13c
198#define CLK_SOURCE_DSIB 0xd0
199#define CLK_SOURCE_TSENSOR 0x3b8
200#define CLK_SOURCE_ACTMON 0x3e8
201#define CLK_SOURCE_EXTERN1 0x3ec
202#define CLK_SOURCE_EXTERN2 0x3f0
203#define CLK_SOURCE_EXTERN3 0x3f4
204#define CLK_SOURCE_I2CSLOW 0x3fc
205#define CLK_SOURCE_SE 0x42c
206#define CLK_SOURCE_MSELECT 0x3b4
207#define CLK_SOURCE_EMC 0x19c
208
209#define AUDIO_SYNC_DOUBLER 0x49c
210
211#define PMC_CTRL 0
212#define PMC_CTRL_BLINK_ENB 7
213
214#define PMC_DPD_PADS_ORIDE 0x1c
215#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
216#define PMC_BLINK_TIMER 0x40
217
218#define UTMIP_PLL_CFG2 0x488
219#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
220#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
221#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
222#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
223#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
224
225#define UTMIP_PLL_CFG1 0x484
226#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
227#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
228#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
229#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
230#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
231
232/* Tegra CPU clock and reset control regs */
233#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
234#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
235#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344
236#define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c
237#define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
238
239#define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
240#define CPU_RESET(cpu) (0x1111ul << (cpu))
241
242#define CLK_RESET_CCLK_BURST 0x20
243#define CLK_RESET_CCLK_DIVIDER 0x24
244#define CLK_RESET_PLLX_BASE 0xe0
245#define CLK_RESET_PLLX_MISC 0xe4
246
247#define CLK_RESET_SOURCE_CSITE 0x1d4
248
249#define CLK_RESET_CCLK_BURST_POLICY_SHIFT 28
250#define CLK_RESET_CCLK_RUN_POLICY_SHIFT 4
251#define CLK_RESET_CCLK_IDLE_POLICY_SHIFT 0
252#define CLK_RESET_CCLK_IDLE_POLICY 1
253#define CLK_RESET_CCLK_RUN_POLICY 2
254#define CLK_RESET_CCLK_BURST_POLICY_PLLX 8
255
256#ifdef CONFIG_PM_SLEEP
257static struct cpu_clk_suspend_context {
258 u32 pllx_misc;
259 u32 pllx_base;
260
261 u32 cpu_burst;
262 u32 clk_csite_src;
263 u32 cclk_divider;
264} tegra30_cpu_clk_sctx;
265#endif
266
267static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
268
269static void __iomem *clk_base;
270static void __iomem *pmc_base;
271static unsigned long input_freq;
272
273static DEFINE_SPINLOCK(clk_doubler_lock);
274static DEFINE_SPINLOCK(clk_out_lock);
275static DEFINE_SPINLOCK(pll_div_lock);
276static DEFINE_SPINLOCK(cml_lock);
277static DEFINE_SPINLOCK(pll_d_lock);
278
279#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \
280 _clk_num, _regs, _gate_flags, _clk_id) \
281 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
282 30, 2, 0, 0, 8, 1, 0, _regs, _clk_num, \
283 periph_clk_enb_refcnt, _gate_flags, _clk_id)
284
285#define TEGRA_INIT_DATA_DIV16(_name, _con_id, _dev_id, _parents, _offset, \
286 _clk_num, _regs, _gate_flags, _clk_id) \
287 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
288 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \
289 _regs, _clk_num, periph_clk_enb_refcnt, \
290 _gate_flags, _clk_id)
291
292#define TEGRA_INIT_DATA_MUX8(_name, _con_id, _dev_id, _parents, _offset, \
293 _clk_num, _regs, _gate_flags, _clk_id) \
294 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
295 29, 3, 0, 0, 8, 1, 0, _regs, _clk_num, \
296 periph_clk_enb_refcnt, _gate_flags, _clk_id)
297
298#define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \
299 _clk_num, _regs, _gate_flags, _clk_id) \
300 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
301 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs, \
302 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
303 _clk_id)
304
305#define TEGRA_INIT_DATA_UART(_name, _con_id, _dev_id, _parents, _offset,\
306 _clk_num, _regs, _clk_id) \
307 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
308 30, 2, 0, 0, 16, 1, TEGRA_DIVIDER_UART, _regs, \
309 _clk_num, periph_clk_enb_refcnt, 0, _clk_id)
310
311#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \
312 _mux_shift, _mux_width, _clk_num, _regs, \
313 _gate_flags, _clk_id) \
314 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
315 _mux_shift, _mux_width, 0, 0, 0, 0, 0, _regs, \
316 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
317 _clk_id)
318
319/*
320 * IDs assigned here must be in sync with DT bindings definition
321 * for Tegra30 clocks.
322 */
323enum tegra30_clk {
324 cpu, rtc = 4, timer, uarta, gpio = 8, sdmmc2, i2s1 = 11, i2c1, ndflash,
325 sdmmc1, sdmmc4, pwm = 17, i2s2, epp, gr2d = 21, usbd, isp, gr3d,
326 disp2 = 26, disp1, host1x, vcp, i2s0, cop_cache, mc, ahbdma, apbdma,
327 kbc = 36, statmon, pmc, kfuse = 40, sbc1, nor, sbc2 = 44, sbc3 = 46,
328 i2c5, dsia, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2,
329 usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
330 pcie, owr, afi, csite, pciex, avpucq, la, dtv = 79, ndspeed, i2c_slow,
331 dsib, irama = 84, iramb, iramc, iramd, cram2, audio_2x = 90, csus = 92,
332 cdev1, cdev2, cpu_g = 96, cpu_lp, gr3d2, mselect, tsensor, i2s3, i2s4,
333 i2c4, sbc5, sbc6, d_audio, apbif, dam0, dam1, dam2, hda2codec_2x,
334 atomics, audio0_2x, audio1_2x, audio2_2x, audio3_2x, audio4_2x,
335 spdif_2x, actmon, extern1, extern2, extern3, sata_oob, sata, hda, se,
336 hda2hdmi, sata_cold, uartb = 160, vfir, spdif_out, spdif_in, vi,
337 vi_sensor, fuse, fuse_burn, cve, tvo, clk_32k, clk_m, clk_m_div2,
338 clk_m_div4, pll_ref, pll_c, pll_c_out1, pll_m, pll_m_out1, pll_p,
339 pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_a, pll_a_out0,
340 pll_d, pll_d_out0, pll_d2, pll_d2_out0, pll_u, pll_x, pll_x_out0, pll_e,
341 spdif_in_sync, i2s0_sync, i2s1_sync, i2s2_sync, i2s3_sync, i2s4_sync,
342 vimclk_sync, audio0, audio1, audio2, audio3, audio4, spdif, clk_out_1,
343 clk_out_2, clk_out_3, sclk, blink, cclk_g, cclk_lp, twd, cml0, cml1,
344 i2cslow, hclk, pclk, clk_out_1_mux = 300, clk_max
345};
346
347static struct clk *clks[clk_max];
348static struct clk_onecell_data clk_data;
349
350/*
351 * Structure defining the fields for USB UTMI clocks Parameters.
352 */
353struct utmi_clk_param {
354 /* Oscillator Frequency in KHz */
355 u32 osc_frequency;
356 /* UTMIP PLL Enable Delay Count */
357 u8 enable_delay_count;
358 /* UTMIP PLL Stable count */
359 u8 stable_count;
360 /* UTMIP PLL Active delay count */
361 u8 active_delay_count;
362 /* UTMIP PLL Xtal frequency count */
363 u8 xtal_freq_count;
364};
365
366static const struct utmi_clk_param utmi_parameters[] = {
367/* OSC_FREQUENCY, ENABLE_DLY, STABLE_CNT, ACTIVE_DLY, XTAL_FREQ_CNT */
368 {13000000, 0x02, 0x33, 0x05, 0x7F},
369 {19200000, 0x03, 0x4B, 0x06, 0xBB},
370 {12000000, 0x02, 0x2F, 0x04, 0x76},
371 {26000000, 0x04, 0x66, 0x09, 0xFE},
372 {16800000, 0x03, 0x41, 0x0A, 0xA4},
373};
374
375static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
376 { 12000000, 1040000000, 520, 6, 1, 8},
377 { 13000000, 1040000000, 480, 6, 1, 8},
378 { 16800000, 1040000000, 495, 8, 1, 8}, /* actual: 1039.5 MHz */
379 { 19200000, 1040000000, 325, 6, 1, 6},
380 { 26000000, 1040000000, 520, 13, 1, 8},
381
382 { 12000000, 832000000, 416, 6, 1, 8},
383 { 13000000, 832000000, 832, 13, 1, 8},
384 { 16800000, 832000000, 396, 8, 1, 8}, /* actual: 831.6 MHz */
385 { 19200000, 832000000, 260, 6, 1, 8},
386 { 26000000, 832000000, 416, 13, 1, 8},
387
388 { 12000000, 624000000, 624, 12, 1, 8},
389 { 13000000, 624000000, 624, 13, 1, 8},
390 { 16800000, 600000000, 520, 14, 1, 8},
391 { 19200000, 624000000, 520, 16, 1, 8},
392 { 26000000, 624000000, 624, 26, 1, 8},
393
394 { 12000000, 600000000, 600, 12, 1, 8},
395 { 13000000, 600000000, 600, 13, 1, 8},
396 { 16800000, 600000000, 500, 14, 1, 8},
397 { 19200000, 600000000, 375, 12, 1, 6},
398 { 26000000, 600000000, 600, 26, 1, 8},
399
400 { 12000000, 520000000, 520, 12, 1, 8},
401 { 13000000, 520000000, 520, 13, 1, 8},
402 { 16800000, 520000000, 495, 16, 1, 8}, /* actual: 519.75 MHz */
403 { 19200000, 520000000, 325, 12, 1, 6},
404 { 26000000, 520000000, 520, 26, 1, 8},
405
406 { 12000000, 416000000, 416, 12, 1, 8},
407 { 13000000, 416000000, 416, 13, 1, 8},
408 { 16800000, 416000000, 396, 16, 1, 8}, /* actual: 415.8 MHz */
409 { 19200000, 416000000, 260, 12, 1, 6},
410 { 26000000, 416000000, 416, 26, 1, 8},
411 { 0, 0, 0, 0, 0, 0 },
412};
413
414static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
415 { 12000000, 666000000, 666, 12, 1, 8},
416 { 13000000, 666000000, 666, 13, 1, 8},
417 { 16800000, 666000000, 555, 14, 1, 8},
418 { 19200000, 666000000, 555, 16, 1, 8},
419 { 26000000, 666000000, 666, 26, 1, 8},
420 { 12000000, 600000000, 600, 12, 1, 8},
421 { 13000000, 600000000, 600, 13, 1, 8},
422 { 16800000, 600000000, 500, 14, 1, 8},
423 { 19200000, 600000000, 375, 12, 1, 6},
424 { 26000000, 600000000, 600, 26, 1, 8},
425 { 0, 0, 0, 0, 0, 0 },
426};
427
428static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
429 { 12000000, 216000000, 432, 12, 2, 8},
430 { 13000000, 216000000, 432, 13, 2, 8},
431 { 16800000, 216000000, 360, 14, 2, 8},
432 { 19200000, 216000000, 360, 16, 2, 8},
433 { 26000000, 216000000, 432, 26, 2, 8},
434 { 0, 0, 0, 0, 0, 0 },
435};
436
437static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
438 { 9600000, 564480000, 294, 5, 1, 4},
439 { 9600000, 552960000, 288, 5, 1, 4},
440 { 9600000, 24000000, 5, 2, 1, 1},
441
442 { 28800000, 56448000, 49, 25, 1, 1},
443 { 28800000, 73728000, 64, 25, 1, 1},
444 { 28800000, 24000000, 5, 6, 1, 1},
445 { 0, 0, 0, 0, 0, 0 },
446};
447
448static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
449 { 12000000, 216000000, 216, 12, 1, 4},
450 { 13000000, 216000000, 216, 13, 1, 4},
451 { 16800000, 216000000, 180, 14, 1, 4},
452 { 19200000, 216000000, 180, 16, 1, 4},
453 { 26000000, 216000000, 216, 26, 1, 4},
454
455 { 12000000, 594000000, 594, 12, 1, 8},
456 { 13000000, 594000000, 594, 13, 1, 8},
457 { 16800000, 594000000, 495, 14, 1, 8},
458 { 19200000, 594000000, 495, 16, 1, 8},
459 { 26000000, 594000000, 594, 26, 1, 8},
460
461 { 12000000, 1000000000, 1000, 12, 1, 12},
462 { 13000000, 1000000000, 1000, 13, 1, 12},
463 { 19200000, 1000000000, 625, 12, 1, 8},
464 { 26000000, 1000000000, 1000, 26, 1, 12},
465
466 { 0, 0, 0, 0, 0, 0 },
467};
468
469static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
470 { 12000000, 480000000, 960, 12, 2, 12},
471 { 13000000, 480000000, 960, 13, 2, 12},
472 { 16800000, 480000000, 400, 7, 2, 5},
473 { 19200000, 480000000, 200, 4, 2, 3},
474 { 26000000, 480000000, 960, 26, 2, 12},
475 { 0, 0, 0, 0, 0, 0 },
476};
477
478static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
479 /* 1.7 GHz */
480 { 12000000, 1700000000, 850, 6, 1, 8},
481 { 13000000, 1700000000, 915, 7, 1, 8}, /* actual: 1699.2 MHz */
482 { 16800000, 1700000000, 708, 7, 1, 8}, /* actual: 1699.2 MHz */
483 { 19200000, 1700000000, 885, 10, 1, 8}, /* actual: 1699.2 MHz */
484 { 26000000, 1700000000, 850, 13, 1, 8},
485
486 /* 1.6 GHz */
487 { 12000000, 1600000000, 800, 6, 1, 8},
488 { 13000000, 1600000000, 738, 6, 1, 8}, /* actual: 1599.0 MHz */
489 { 16800000, 1600000000, 857, 9, 1, 8}, /* actual: 1599.7 MHz */
490 { 19200000, 1600000000, 500, 6, 1, 8},
491 { 26000000, 1600000000, 800, 13, 1, 8},
492
493 /* 1.5 GHz */
494 { 12000000, 1500000000, 750, 6, 1, 8},
495 { 13000000, 1500000000, 923, 8, 1, 8}, /* actual: 1499.8 MHz */
496 { 16800000, 1500000000, 625, 7, 1, 8},
497 { 19200000, 1500000000, 625, 8, 1, 8},
498 { 26000000, 1500000000, 750, 13, 1, 8},
499
500 /* 1.4 GHz */
501 { 12000000, 1400000000, 700, 6, 1, 8},
502 { 13000000, 1400000000, 969, 9, 1, 8}, /* actual: 1399.7 MHz */
503 { 16800000, 1400000000, 1000, 12, 1, 8},
504 { 19200000, 1400000000, 875, 12, 1, 8},
505 { 26000000, 1400000000, 700, 13, 1, 8},
506
507 /* 1.3 GHz */
508 { 12000000, 1300000000, 975, 9, 1, 8},
509 { 13000000, 1300000000, 1000, 10, 1, 8},
510 { 16800000, 1300000000, 928, 12, 1, 8}, /* actual: 1299.2 MHz */
511 { 19200000, 1300000000, 812, 12, 1, 8}, /* actual: 1299.2 MHz */
512 { 26000000, 1300000000, 650, 13, 1, 8},
513
514 /* 1.2 GHz */
515 { 12000000, 1200000000, 1000, 10, 1, 8},
516 { 13000000, 1200000000, 923, 10, 1, 8}, /* actual: 1199.9 MHz */
517 { 16800000, 1200000000, 1000, 14, 1, 8},
518 { 19200000, 1200000000, 1000, 16, 1, 8},
519 { 26000000, 1200000000, 600, 13, 1, 8},
520
521 /* 1.1 GHz */
522 { 12000000, 1100000000, 825, 9, 1, 8},
523 { 13000000, 1100000000, 846, 10, 1, 8}, /* actual: 1099.8 MHz */
524 { 16800000, 1100000000, 982, 15, 1, 8}, /* actual: 1099.8 MHz */
525 { 19200000, 1100000000, 859, 15, 1, 8}, /* actual: 1099.5 MHz */
526 { 26000000, 1100000000, 550, 13, 1, 8},
527
528 /* 1 GHz */
529 { 12000000, 1000000000, 1000, 12, 1, 8},
530 { 13000000, 1000000000, 1000, 13, 1, 8},
531 { 16800000, 1000000000, 833, 14, 1, 8}, /* actual: 999.6 MHz */
532 { 19200000, 1000000000, 625, 12, 1, 8},
533 { 26000000, 1000000000, 1000, 26, 1, 8},
534
535 { 0, 0, 0, 0, 0, 0 },
536};
537
538static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
539 /* PLLE special case: use cpcon field to store cml divider value */
540 { 12000000, 100000000, 150, 1, 18, 11},
541 { 216000000, 100000000, 200, 18, 24, 13},
542 { 0, 0, 0, 0, 0, 0 },
543};
544
545/* PLL parameters */
546static struct tegra_clk_pll_params pll_c_params = {
547 .input_min = 2000000,
548 .input_max = 31000000,
549 .cf_min = 1000000,
550 .cf_max = 6000000,
551 .vco_min = 20000000,
552 .vco_max = 1400000000,
553 .base_reg = PLLC_BASE,
554 .misc_reg = PLLC_MISC,
555 .lock_bit_idx = PLL_BASE_LOCK,
556 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
557 .lock_delay = 300,
558};
559
560static struct tegra_clk_pll_params pll_m_params = {
561 .input_min = 2000000,
562 .input_max = 31000000,
563 .cf_min = 1000000,
564 .cf_max = 6000000,
565 .vco_min = 20000000,
566 .vco_max = 1200000000,
567 .base_reg = PLLM_BASE,
568 .misc_reg = PLLM_MISC,
569 .lock_bit_idx = PLL_BASE_LOCK,
570 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
571 .lock_delay = 300,
572};
573
574static struct tegra_clk_pll_params pll_p_params = {
575 .input_min = 2000000,
576 .input_max = 31000000,
577 .cf_min = 1000000,
578 .cf_max = 6000000,
579 .vco_min = 20000000,
580 .vco_max = 1400000000,
581 .base_reg = PLLP_BASE,
582 .misc_reg = PLLP_MISC,
583 .lock_bit_idx = PLL_BASE_LOCK,
584 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
585 .lock_delay = 300,
586};
587
588static struct tegra_clk_pll_params pll_a_params = {
589 .input_min = 2000000,
590 .input_max = 31000000,
591 .cf_min = 1000000,
592 .cf_max = 6000000,
593 .vco_min = 20000000,
594 .vco_max = 1400000000,
595 .base_reg = PLLA_BASE,
596 .misc_reg = PLLA_MISC,
597 .lock_bit_idx = PLL_BASE_LOCK,
598 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
599 .lock_delay = 300,
600};
601
602static struct tegra_clk_pll_params pll_d_params = {
603 .input_min = 2000000,
604 .input_max = 40000000,
605 .cf_min = 1000000,
606 .cf_max = 6000000,
607 .vco_min = 40000000,
608 .vco_max = 1000000000,
609 .base_reg = PLLD_BASE,
610 .misc_reg = PLLD_MISC,
611 .lock_bit_idx = PLL_BASE_LOCK,
612 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
613 .lock_delay = 1000,
614};
615
616static struct tegra_clk_pll_params pll_d2_params = {
617 .input_min = 2000000,
618 .input_max = 40000000,
619 .cf_min = 1000000,
620 .cf_max = 6000000,
621 .vco_min = 40000000,
622 .vco_max = 1000000000,
623 .base_reg = PLLD2_BASE,
624 .misc_reg = PLLD2_MISC,
625 .lock_bit_idx = PLL_BASE_LOCK,
626 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
627 .lock_delay = 1000,
628};
629
630static struct tegra_clk_pll_params pll_u_params = {
631 .input_min = 2000000,
632 .input_max = 40000000,
633 .cf_min = 1000000,
634 .cf_max = 6000000,
635 .vco_min = 48000000,
636 .vco_max = 960000000,
637 .base_reg = PLLU_BASE,
638 .misc_reg = PLLU_MISC,
639 .lock_bit_idx = PLL_BASE_LOCK,
640 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
641 .lock_delay = 1000,
642};
643
644static struct tegra_clk_pll_params pll_x_params = {
645 .input_min = 2000000,
646 .input_max = 31000000,
647 .cf_min = 1000000,
648 .cf_max = 6000000,
649 .vco_min = 20000000,
650 .vco_max = 1700000000,
651 .base_reg = PLLX_BASE,
652 .misc_reg = PLLX_MISC,
653 .lock_bit_idx = PLL_BASE_LOCK,
654 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
655 .lock_delay = 300,
656};
657
658static struct tegra_clk_pll_params pll_e_params = {
659 .input_min = 12000000,
660 .input_max = 216000000,
661 .cf_min = 12000000,
662 .cf_max = 12000000,
663 .vco_min = 1200000000,
664 .vco_max = 2400000000U,
665 .base_reg = PLLE_BASE,
666 .misc_reg = PLLE_MISC,
667 .lock_bit_idx = PLLE_MISC_LOCK,
668 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
669 .lock_delay = 300,
670};
671
672/* Peripheral clock registers */
673static struct tegra_clk_periph_regs periph_l_regs = {
674 .enb_reg = CLK_OUT_ENB_L,
675 .enb_set_reg = CLK_OUT_ENB_SET_L,
676 .enb_clr_reg = CLK_OUT_ENB_CLR_L,
677 .rst_reg = RST_DEVICES_L,
678 .rst_set_reg = RST_DEVICES_SET_L,
679 .rst_clr_reg = RST_DEVICES_CLR_L,
680};
681
682static struct tegra_clk_periph_regs periph_h_regs = {
683 .enb_reg = CLK_OUT_ENB_H,
684 .enb_set_reg = CLK_OUT_ENB_SET_H,
685 .enb_clr_reg = CLK_OUT_ENB_CLR_H,
686 .rst_reg = RST_DEVICES_H,
687 .rst_set_reg = RST_DEVICES_SET_H,
688 .rst_clr_reg = RST_DEVICES_CLR_H,
689};
690
691static struct tegra_clk_periph_regs periph_u_regs = {
692 .enb_reg = CLK_OUT_ENB_U,
693 .enb_set_reg = CLK_OUT_ENB_SET_U,
694 .enb_clr_reg = CLK_OUT_ENB_CLR_U,
695 .rst_reg = RST_DEVICES_U,
696 .rst_set_reg = RST_DEVICES_SET_U,
697 .rst_clr_reg = RST_DEVICES_CLR_U,
698};
699
700static struct tegra_clk_periph_regs periph_v_regs = {
701 .enb_reg = CLK_OUT_ENB_V,
702 .enb_set_reg = CLK_OUT_ENB_SET_V,
703 .enb_clr_reg = CLK_OUT_ENB_CLR_V,
704 .rst_reg = RST_DEVICES_V,
705 .rst_set_reg = RST_DEVICES_SET_V,
706 .rst_clr_reg = RST_DEVICES_CLR_V,
707};
708
709static struct tegra_clk_periph_regs periph_w_regs = {
710 .enb_reg = CLK_OUT_ENB_W,
711 .enb_set_reg = CLK_OUT_ENB_SET_W,
712 .enb_clr_reg = CLK_OUT_ENB_CLR_W,
713 .rst_reg = RST_DEVICES_W,
714 .rst_set_reg = RST_DEVICES_SET_W,
715 .rst_clr_reg = RST_DEVICES_CLR_W,
716};
717
718static void tegra30_clk_measure_input_freq(void)
719{
720 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL);
721 u32 auto_clk_control = osc_ctrl & OSC_CTRL_OSC_FREQ_MASK;
722 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
723
724 switch (auto_clk_control) {
725 case OSC_CTRL_OSC_FREQ_12MHZ:
726 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
727 input_freq = 12000000;
728 break;
729 case OSC_CTRL_OSC_FREQ_13MHZ:
730 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
731 input_freq = 13000000;
732 break;
733 case OSC_CTRL_OSC_FREQ_19_2MHZ:
734 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
735 input_freq = 19200000;
736 break;
737 case OSC_CTRL_OSC_FREQ_26MHZ:
738 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
739 input_freq = 26000000;
740 break;
741 case OSC_CTRL_OSC_FREQ_16_8MHZ:
742 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
743 input_freq = 16800000;
744 break;
745 case OSC_CTRL_OSC_FREQ_38_4MHZ:
746 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_2);
747 input_freq = 38400000;
748 break;
749 case OSC_CTRL_OSC_FREQ_48MHZ:
750 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4);
751 input_freq = 48000000;
752 break;
753 default:
754 pr_err("Unexpected auto clock control value %d",
755 auto_clk_control);
756 BUG();
757 return;
758 }
759}
760
761static unsigned int tegra30_get_pll_ref_div(void)
762{
763 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) &
764 OSC_CTRL_PLL_REF_DIV_MASK;
765
766 switch (pll_ref_div) {
767 case OSC_CTRL_PLL_REF_DIV_1:
768 return 1;
769 case OSC_CTRL_PLL_REF_DIV_2:
770 return 2;
771 case OSC_CTRL_PLL_REF_DIV_4:
772 return 4;
773 default:
774 pr_err("Invalid pll ref divider %d", pll_ref_div);
775 BUG();
776 }
777 return 0;
778}
779
780static void tegra30_utmi_param_configure(void)
781{
782 u32 reg;
783 int i;
784
785 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
786 if (input_freq == utmi_parameters[i].osc_frequency)
787 break;
788 }
789
790 if (i >= ARRAY_SIZE(utmi_parameters)) {
791 pr_err("%s: Unexpected input rate %lu\n", __func__, input_freq);
792 return;
793 }
794
795 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
796
797 /* Program UTMIP PLL stable and active counts */
798 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
799 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(
800 utmi_parameters[i].stable_count);
801
802 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
803
804 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(
805 utmi_parameters[i].active_delay_count);
806
807 /* Remove power downs from UTMIP PLL control bits */
808 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
809 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
810 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
811
812 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
813
814 /* Program UTMIP PLL delay and oscillator frequency counts */
815 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
816 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
817
818 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(
819 utmi_parameters[i].enable_delay_count);
820
821 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
822 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(
823 utmi_parameters[i].xtal_freq_count);
824
825 /* Remove power downs from UTMIP PLL control bits */
826 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
827 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
828 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
829
830 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
831}
832
833static const char *pll_e_parents[] = {"pll_ref", "pll_p"};
834
835static void __init tegra30_pll_init(void)
836{
837 struct clk *clk;
838
839 /* PLLC */
840 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0,
841 0, &pll_c_params,
842 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
843 pll_c_freq_table, NULL);
844 clk_register_clkdev(clk, "pll_c", NULL);
845 clks[pll_c] = clk;
846
847 /* PLLC_OUT1 */
848 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
849 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
850 8, 8, 1, NULL);
851 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
852 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
853 0, NULL);
854 clk_register_clkdev(clk, "pll_c_out1", NULL);
855 clks[pll_c_out1] = clk;
856
857 /* PLLP */
858 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, pmc_base, 0,
859 408000000, &pll_p_params,
860 TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON |
861 TEGRA_PLL_USE_LOCK, pll_p_freq_table, NULL);
862 clk_register_clkdev(clk, "pll_p", NULL);
863 clks[pll_p] = clk;
864
865 /* PLLP_OUT1 */
866 clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p",
867 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
868 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1,
869 &pll_div_lock);
870 clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div",
871 clk_base + PLLP_OUTA, 1, 0,
872 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
873 &pll_div_lock);
874 clk_register_clkdev(clk, "pll_p_out1", NULL);
875 clks[pll_p_out1] = clk;
876
877 /* PLLP_OUT2 */
878 clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p",
879 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
880 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
881 &pll_div_lock);
882 clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div",
883 clk_base + PLLP_OUTA, 17, 16,
884 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
885 &pll_div_lock);
886 clk_register_clkdev(clk, "pll_p_out2", NULL);
887 clks[pll_p_out2] = clk;
888
889 /* PLLP_OUT3 */
890 clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p",
891 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED |
892 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1,
893 &pll_div_lock);
894 clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div",
895 clk_base + PLLP_OUTB, 1, 0,
896 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
897 &pll_div_lock);
898 clk_register_clkdev(clk, "pll_p_out3", NULL);
899 clks[pll_p_out3] = clk;
900
901 /* PLLP_OUT4 */
902 clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p",
903 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED |
904 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
905 &pll_div_lock);
906 clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div",
907 clk_base + PLLP_OUTB, 17, 16,
908 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
909 &pll_div_lock);
910 clk_register_clkdev(clk, "pll_p_out4", NULL);
911 clks[pll_p_out4] = clk;
912
913 /* PLLM */
914 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base,
915 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 0,
916 &pll_m_params, TEGRA_PLLM | TEGRA_PLL_HAS_CPCON |
917 TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK,
918 pll_m_freq_table, NULL);
919 clk_register_clkdev(clk, "pll_m", NULL);
920 clks[pll_m] = clk;
921
922 /* PLLM_OUT1 */
923 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
924 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
925 8, 8, 1, NULL);
926 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
927 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
928 CLK_SET_RATE_PARENT, 0, NULL);
929 clk_register_clkdev(clk, "pll_m_out1", NULL);
930 clks[pll_m_out1] = clk;
931
932 /* PLLX */
933 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0,
934 0, &pll_x_params, TEGRA_PLL_HAS_CPCON |
935 TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK,
936 pll_x_freq_table, NULL);
937 clk_register_clkdev(clk, "pll_x", NULL);
938 clks[pll_x] = clk;
939
940 /* PLLX_OUT0 */
941 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
942 CLK_SET_RATE_PARENT, 1, 2);
943 clk_register_clkdev(clk, "pll_x_out0", NULL);
944 clks[pll_x_out0] = clk;
945
946 /* PLLU */
947 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc_base, 0,
948 0, &pll_u_params, TEGRA_PLLU | TEGRA_PLL_HAS_CPCON |
949 TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK,
950 pll_u_freq_table,
951 NULL);
952 clk_register_clkdev(clk, "pll_u", NULL);
953 clks[pll_u] = clk;
954
955 tegra30_utmi_param_configure();
956
957 /* PLLD */
958 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0,
959 0, &pll_d_params, TEGRA_PLL_HAS_CPCON |
960 TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK,
961 pll_d_freq_table, &pll_d_lock);
962 clk_register_clkdev(clk, "pll_d", NULL);
963 clks[pll_d] = clk;
964
965 /* PLLD_OUT0 */
966 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
967 CLK_SET_RATE_PARENT, 1, 2);
968 clk_register_clkdev(clk, "pll_d_out0", NULL);
969 clks[pll_d_out0] = clk;
970
971 /* PLLD2 */
972 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0,
973 0, &pll_d2_params, TEGRA_PLL_HAS_CPCON |
974 TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK,
975 pll_d_freq_table, NULL);
976 clk_register_clkdev(clk, "pll_d2", NULL);
977 clks[pll_d2] = clk;
978
979 /* PLLD2_OUT0 */
980 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
981 CLK_SET_RATE_PARENT, 1, 2);
982 clk_register_clkdev(clk, "pll_d2_out0", NULL);
983 clks[pll_d2_out0] = clk;
984
985 /* PLLA */
986 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, pmc_base,
987 0, 0, &pll_a_params, TEGRA_PLL_HAS_CPCON |
988 TEGRA_PLL_USE_LOCK, pll_a_freq_table, NULL);
989 clk_register_clkdev(clk, "pll_a", NULL);
990 clks[pll_a] = clk;
991
992 /* PLLA_OUT0 */
993 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
994 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
995 8, 8, 1, NULL);
996 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
997 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
998 CLK_SET_RATE_PARENT, 0, NULL);
999 clk_register_clkdev(clk, "pll_a_out0", NULL);
1000 clks[pll_a_out0] = clk;
1001
1002 /* PLLE */
1003 clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents,
1004 ARRAY_SIZE(pll_e_parents), 0,
1005 clk_base + PLLE_AUX, 2, 1, 0, NULL);
1006 clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base,
1007 CLK_GET_RATE_NOCACHE, 100000000, &pll_e_params,
1008 TEGRA_PLLE_CONFIGURE, pll_e_freq_table, NULL);
1009 clk_register_clkdev(clk, "pll_e", NULL);
1010 clks[pll_e] = clk;
1011}
1012
1013static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync",
1014 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",};
1015static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
1016 "clk_m_div4", "extern1", };
1017static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
1018 "clk_m_div4", "extern2", };
1019static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
1020 "clk_m_div4", "extern3", };
1021
1022static void __init tegra30_audio_clk_init(void)
1023{
1024 struct clk *clk;
1025
1026 /* spdif_in_sync */
1027 clk = tegra_clk_register_sync_source("spdif_in_sync", 24000000,
1028 24000000);
1029 clk_register_clkdev(clk, "spdif_in_sync", NULL);
1030 clks[spdif_in_sync] = clk;
1031
1032 /* i2s0_sync */
1033 clk = tegra_clk_register_sync_source("i2s0_sync", 24000000, 24000000);
1034 clk_register_clkdev(clk, "i2s0_sync", NULL);
1035 clks[i2s0_sync] = clk;
1036
1037 /* i2s1_sync */
1038 clk = tegra_clk_register_sync_source("i2s1_sync", 24000000, 24000000);
1039 clk_register_clkdev(clk, "i2s1_sync", NULL);
1040 clks[i2s1_sync] = clk;
1041
1042 /* i2s2_sync */
1043 clk = tegra_clk_register_sync_source("i2s2_sync", 24000000, 24000000);
1044 clk_register_clkdev(clk, "i2s2_sync", NULL);
1045 clks[i2s2_sync] = clk;
1046
1047 /* i2s3_sync */
1048 clk = tegra_clk_register_sync_source("i2s3_sync", 24000000, 24000000);
1049 clk_register_clkdev(clk, "i2s3_sync", NULL);
1050 clks[i2s3_sync] = clk;
1051
1052 /* i2s4_sync */
1053 clk = tegra_clk_register_sync_source("i2s4_sync", 24000000, 24000000);
1054 clk_register_clkdev(clk, "i2s4_sync", NULL);
1055 clks[i2s4_sync] = clk;
1056
1057 /* vimclk_sync */
1058 clk = tegra_clk_register_sync_source("vimclk_sync", 24000000, 24000000);
1059 clk_register_clkdev(clk, "vimclk_sync", NULL);
1060 clks[vimclk_sync] = clk;
1061
1062 /* audio0 */
1063 clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk,
1064 ARRAY_SIZE(mux_audio_sync_clk), 0,
1065 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0, NULL);
1066 clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0,
1067 clk_base + AUDIO_SYNC_CLK_I2S0, 4,
1068 CLK_GATE_SET_TO_DISABLE, NULL);
1069 clk_register_clkdev(clk, "audio0", NULL);
1070 clks[audio0] = clk;
1071
1072 /* audio1 */
1073 clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk,
1074 ARRAY_SIZE(mux_audio_sync_clk), 0,
1075 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0, NULL);
1076 clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0,
1077 clk_base + AUDIO_SYNC_CLK_I2S1, 4,
1078 CLK_GATE_SET_TO_DISABLE, NULL);
1079 clk_register_clkdev(clk, "audio1", NULL);
1080 clks[audio1] = clk;
1081
1082 /* audio2 */
1083 clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk,
1084 ARRAY_SIZE(mux_audio_sync_clk), 0,
1085 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0, NULL);
1086 clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0,
1087 clk_base + AUDIO_SYNC_CLK_I2S2, 4,
1088 CLK_GATE_SET_TO_DISABLE, NULL);
1089 clk_register_clkdev(clk, "audio2", NULL);
1090 clks[audio2] = clk;
1091
1092 /* audio3 */
1093 clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk,
1094 ARRAY_SIZE(mux_audio_sync_clk), 0,
1095 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0, NULL);
1096 clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0,
1097 clk_base + AUDIO_SYNC_CLK_I2S3, 4,
1098 CLK_GATE_SET_TO_DISABLE, NULL);
1099 clk_register_clkdev(clk, "audio3", NULL);
1100 clks[audio3] = clk;
1101
1102 /* audio4 */
1103 clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk,
1104 ARRAY_SIZE(mux_audio_sync_clk), 0,
1105 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0, NULL);
1106 clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0,
1107 clk_base + AUDIO_SYNC_CLK_I2S4, 4,
1108 CLK_GATE_SET_TO_DISABLE, NULL);
1109 clk_register_clkdev(clk, "audio4", NULL);
1110 clks[audio4] = clk;
1111
1112 /* spdif */
1113 clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk,
1114 ARRAY_SIZE(mux_audio_sync_clk), 0,
1115 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0, NULL);
1116 clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0,
1117 clk_base + AUDIO_SYNC_CLK_SPDIF, 4,
1118 CLK_GATE_SET_TO_DISABLE, NULL);
1119 clk_register_clkdev(clk, "spdif", NULL);
1120 clks[spdif] = clk;
1121
1122 /* audio0_2x */
1123 clk = clk_register_fixed_factor(NULL, "audio0_doubler", "audio0",
1124 CLK_SET_RATE_PARENT, 2, 1);
1125 clk = tegra_clk_register_divider("audio0_div", "audio0_doubler",
1126 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 24, 1, 0,
1127 &clk_doubler_lock);
1128 clk = tegra_clk_register_periph_gate("audio0_2x", "audio0_div",
1129 TEGRA_PERIPH_NO_RESET, clk_base,
1130 CLK_SET_RATE_PARENT, 113, &periph_v_regs,
1131 periph_clk_enb_refcnt);
1132 clk_register_clkdev(clk, "audio0_2x", NULL);
1133 clks[audio0_2x] = clk;
1134
1135 /* audio1_2x */
1136 clk = clk_register_fixed_factor(NULL, "audio1_doubler", "audio1",
1137 CLK_SET_RATE_PARENT, 2, 1);
1138 clk = tegra_clk_register_divider("audio1_div", "audio1_doubler",
1139 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 25, 1, 0,
1140 &clk_doubler_lock);
1141 clk = tegra_clk_register_periph_gate("audio1_2x", "audio1_div",
1142 TEGRA_PERIPH_NO_RESET, clk_base,
1143 CLK_SET_RATE_PARENT, 114, &periph_v_regs,
1144 periph_clk_enb_refcnt);
1145 clk_register_clkdev(clk, "audio1_2x", NULL);
1146 clks[audio1_2x] = clk;
1147
1148 /* audio2_2x */
1149 clk = clk_register_fixed_factor(NULL, "audio2_doubler", "audio2",
1150 CLK_SET_RATE_PARENT, 2, 1);
1151 clk = tegra_clk_register_divider("audio2_div", "audio2_doubler",
1152 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 26, 1, 0,
1153 &clk_doubler_lock);
1154 clk = tegra_clk_register_periph_gate("audio2_2x", "audio2_div",
1155 TEGRA_PERIPH_NO_RESET, clk_base,
1156 CLK_SET_RATE_PARENT, 115, &periph_v_regs,
1157 periph_clk_enb_refcnt);
1158 clk_register_clkdev(clk, "audio2_2x", NULL);
1159 clks[audio2_2x] = clk;
1160
1161 /* audio3_2x */
1162 clk = clk_register_fixed_factor(NULL, "audio3_doubler", "audio3",
1163 CLK_SET_RATE_PARENT, 2, 1);
1164 clk = tegra_clk_register_divider("audio3_div", "audio3_doubler",
1165 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 27, 1, 0,
1166 &clk_doubler_lock);
1167 clk = tegra_clk_register_periph_gate("audio3_2x", "audio3_div",
1168 TEGRA_PERIPH_NO_RESET, clk_base,
1169 CLK_SET_RATE_PARENT, 116, &periph_v_regs,
1170 periph_clk_enb_refcnt);
1171 clk_register_clkdev(clk, "audio3_2x", NULL);
1172 clks[audio3_2x] = clk;
1173
1174 /* audio4_2x */
1175 clk = clk_register_fixed_factor(NULL, "audio4_doubler", "audio4",
1176 CLK_SET_RATE_PARENT, 2, 1);
1177 clk = tegra_clk_register_divider("audio4_div", "audio4_doubler",
1178 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 28, 1, 0,
1179 &clk_doubler_lock);
1180 clk = tegra_clk_register_periph_gate("audio4_2x", "audio4_div",
1181 TEGRA_PERIPH_NO_RESET, clk_base,
1182 CLK_SET_RATE_PARENT, 117, &periph_v_regs,
1183 periph_clk_enb_refcnt);
1184 clk_register_clkdev(clk, "audio4_2x", NULL);
1185 clks[audio4_2x] = clk;
1186
1187 /* spdif_2x */
1188 clk = clk_register_fixed_factor(NULL, "spdif_doubler", "spdif",
1189 CLK_SET_RATE_PARENT, 2, 1);
1190 clk = tegra_clk_register_divider("spdif_div", "spdif_doubler",
1191 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 29, 1, 0,
1192 &clk_doubler_lock);
1193 clk = tegra_clk_register_periph_gate("spdif_2x", "spdif_div",
1194 TEGRA_PERIPH_NO_RESET, clk_base,
1195 CLK_SET_RATE_PARENT, 118, &periph_v_regs,
1196 periph_clk_enb_refcnt);
1197 clk_register_clkdev(clk, "spdif_2x", NULL);
1198 clks[spdif_2x] = clk;
1199}
1200
1201static void __init tegra30_pmc_clk_init(void)
1202{
1203 struct clk *clk;
1204
1205 /* clk_out_1 */
1206 clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents,
1207 ARRAY_SIZE(clk_out1_parents), 0,
1208 pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0,
1209 &clk_out_lock);
1210 clks[clk_out_1_mux] = clk;
1211 clk = clk_register_gate(NULL, "clk_out_1", "clk_out_1_mux", 0,
1212 pmc_base + PMC_CLK_OUT_CNTRL, 2, 0,
1213 &clk_out_lock);
1214 clk_register_clkdev(clk, "extern1", "clk_out_1");
1215 clks[clk_out_1] = clk;
1216
1217 /* clk_out_2 */
1218 clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
1219 ARRAY_SIZE(clk_out1_parents), 0,
1220 pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
1221 &clk_out_lock);
1222 clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0,
1223 pmc_base + PMC_CLK_OUT_CNTRL, 10, 0,
1224 &clk_out_lock);
1225 clk_register_clkdev(clk, "extern2", "clk_out_2");
1226 clks[clk_out_2] = clk;
1227
1228 /* clk_out_3 */
1229 clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
1230 ARRAY_SIZE(clk_out1_parents), 0,
1231 pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
1232 &clk_out_lock);
1233 clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0,
1234 pmc_base + PMC_CLK_OUT_CNTRL, 18, 0,
1235 &clk_out_lock);
1236 clk_register_clkdev(clk, "extern3", "clk_out_3");
1237 clks[clk_out_3] = clk;
1238
1239 /* blink */
1240 writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
1241 clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
1242 pmc_base + PMC_DPD_PADS_ORIDE,
1243 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
1244 clk = clk_register_gate(NULL, "blink", "blink_override", 0,
1245 pmc_base + PMC_CTRL,
1246 PMC_CTRL_BLINK_ENB, 0, NULL);
1247 clk_register_clkdev(clk, "blink", NULL);
1248 clks[blink] = clk;
1249
1250}
1251
1252const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
1253 "pll_p_cclkg", "pll_p_out4_cclkg",
1254 "pll_p_out3_cclkg", "unused", "pll_x" };
1255const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
1256 "pll_p_cclklp", "pll_p_out4_cclklp",
1257 "pll_p_out3_cclklp", "unused", "pll_x",
1258 "pll_x_out0" };
1259const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
1260 "pll_p_out3", "pll_p_out2", "unused",
1261 "clk_32k", "pll_m_out1" };
1262
1263static void __init tegra30_super_clk_init(void)
1264{
1265 struct clk *clk;
1266
1267 /*
1268 * Clock input to cclk_g divided from pll_p using
1269 * U71 divider of cclk_g.
1270 */
1271 clk = tegra_clk_register_divider("pll_p_cclkg", "pll_p",
1272 clk_base + SUPER_CCLKG_DIVIDER, 0,
1273 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1274 clk_register_clkdev(clk, "pll_p_cclkg", NULL);
1275
1276 /*
1277 * Clock input to cclk_g divided from pll_p_out3 using
1278 * U71 divider of cclk_g.
1279 */
1280 clk = tegra_clk_register_divider("pll_p_out3_cclkg", "pll_p_out3",
1281 clk_base + SUPER_CCLKG_DIVIDER, 0,
1282 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1283 clk_register_clkdev(clk, "pll_p_out3_cclkg", NULL);
1284
1285 /*
1286 * Clock input to cclk_g divided from pll_p_out4 using
1287 * U71 divider of cclk_g.
1288 */
1289 clk = tegra_clk_register_divider("pll_p_out4_cclkg", "pll_p_out4",
1290 clk_base + SUPER_CCLKG_DIVIDER, 0,
1291 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1292 clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL);
1293
1294 /* CCLKG */
1295 clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents,
1296 ARRAY_SIZE(cclk_g_parents),
1297 CLK_SET_RATE_PARENT,
1298 clk_base + CCLKG_BURST_POLICY,
1299 0, 4, 0, 0, NULL);
1300 clk_register_clkdev(clk, "cclk_g", NULL);
1301 clks[cclk_g] = clk;
1302
1303 /*
1304 * Clock input to cclk_lp divided from pll_p using
1305 * U71 divider of cclk_lp.
1306 */
1307 clk = tegra_clk_register_divider("pll_p_cclklp", "pll_p",
1308 clk_base + SUPER_CCLKLP_DIVIDER, 0,
1309 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1310 clk_register_clkdev(clk, "pll_p_cclklp", NULL);
1311
1312 /*
1313 * Clock input to cclk_lp divided from pll_p_out3 using
1314 * U71 divider of cclk_lp.
1315 */
1316 clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3",
1317 clk_base + SUPER_CCLKG_DIVIDER, 0,
1318 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1319 clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL);
1320
1321 /*
1322 * Clock input to cclk_lp divided from pll_p_out4 using
1323 * U71 divider of cclk_lp.
1324 */
1325 clk = tegra_clk_register_divider("pll_p_out4_cclklp", "pll_p_out4",
1326 clk_base + SUPER_CCLKLP_DIVIDER, 0,
1327 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1328 clk_register_clkdev(clk, "pll_p_out4_cclklp", NULL);
1329
1330 /* CCLKLP */
1331 clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents,
1332 ARRAY_SIZE(cclk_lp_parents),
1333 CLK_SET_RATE_PARENT,
1334 clk_base + CCLKLP_BURST_POLICY,
1335 TEGRA_DIVIDER_2, 4, 8, 9,
1336 NULL);
1337 clk_register_clkdev(clk, "cclk_lp", NULL);
1338 clks[cclk_lp] = clk;
1339
1340 /* SCLK */
1341 clk = tegra_clk_register_super_mux("sclk", sclk_parents,
1342 ARRAY_SIZE(sclk_parents),
1343 CLK_SET_RATE_PARENT,
1344 clk_base + SCLK_BURST_POLICY,
1345 0, 4, 0, 0, NULL);
1346 clk_register_clkdev(clk, "sclk", NULL);
1347 clks[sclk] = clk;
1348
1349 /* HCLK */
1350 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
1351 clk_base + SYSTEM_CLK_RATE, 4, 2, 0, NULL);
1352 clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT,
1353 clk_base + SYSTEM_CLK_RATE, 7,
1354 CLK_GATE_SET_TO_DISABLE, NULL);
1355 clk_register_clkdev(clk, "hclk", NULL);
1356 clks[hclk] = clk;
1357
1358 /* PCLK */
1359 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
1360 clk_base + SYSTEM_CLK_RATE, 0, 2, 0, NULL);
1361 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT,
1362 clk_base + SYSTEM_CLK_RATE, 3,
1363 CLK_GATE_SET_TO_DISABLE, NULL);
1364 clk_register_clkdev(clk, "pclk", NULL);
1365 clks[pclk] = clk;
1366
1367 /* twd */
1368 clk = clk_register_fixed_factor(NULL, "twd", "cclk_g",
1369 CLK_SET_RATE_PARENT, 1, 2);
1370 clk_register_clkdev(clk, "twd", NULL);
1371 clks[twd] = clk;
1372}
1373
1374static const char *mux_pllacp_clkm[] = { "pll_a_out0", "unused", "pll_p",
1375 "clk_m" };
1376static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" };
1377static const char *mux_pllmcp_clkm[] = { "pll_m", "pll_c", "pll_p", "clk_m" };
1378static const char *i2s0_parents[] = { "pll_a_out0", "audio0_2x", "pll_p",
1379 "clk_m" };
1380static const char *i2s1_parents[] = { "pll_a_out0", "audio1_2x", "pll_p",
1381 "clk_m" };
1382static const char *i2s2_parents[] = { "pll_a_out0", "audio2_2x", "pll_p",
1383 "clk_m" };
1384static const char *i2s3_parents[] = { "pll_a_out0", "audio3_2x", "pll_p",
1385 "clk_m" };
1386static const char *i2s4_parents[] = { "pll_a_out0", "audio4_2x", "pll_p",
1387 "clk_m" };
1388static const char *spdif_out_parents[] = { "pll_a_out0", "spdif_2x", "pll_p",
1389 "clk_m" };
1390static const char *spdif_in_parents[] = { "pll_p", "pll_c", "pll_m" };
1391static const char *mux_pllpc_clk32k_clkm[] = { "pll_p", "pll_c", "clk_32k",
1392 "clk_m" };
1393static const char *mux_pllpc_clkm_clk32k[] = { "pll_p", "pll_c", "clk_m",
1394 "clk_32k" };
1395static const char *mux_pllmcpa[] = { "pll_m", "pll_c", "pll_p", "pll_a_out0" };
1396static const char *mux_pllpdc_clkm[] = { "pll_p", "pll_d_out0", "pll_c",
1397 "clk_m" };
1398static const char *mux_pllp_clkm[] = { "pll_p", "unused", "unused", "clk_m" };
1399static const char *mux_pllpmdacd2_clkm[] = { "pll_p", "pll_m", "pll_d_out0",
1400 "pll_a_out0", "pll_c",
1401 "pll_d2_out0", "clk_m" };
1402static const char *mux_plla_clk32k_pllp_clkm_plle[] = { "pll_a_out0",
1403 "clk_32k", "pll_p",
1404 "clk_m", "pll_e" };
1405static const char *mux_plld_out0_plld2_out0[] = { "pll_d_out0",
1406 "pll_d2_out0" };
1407
1408static struct tegra_periph_init_data tegra_periph_clk_list[] = {
1409 TEGRA_INIT_DATA_MUX("i2s0", NULL, "tegra30-i2s.0", i2s0_parents, CLK_SOURCE_I2S0, 30, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s0),
1410 TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra30-i2s.1", i2s1_parents, CLK_SOURCE_I2S1, 11, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s1),
1411 TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra30-i2s.2", i2s2_parents, CLK_SOURCE_I2S2, 18, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s2),
1412 TEGRA_INIT_DATA_MUX("i2s3", NULL, "tegra30-i2s.3", i2s3_parents, CLK_SOURCE_I2S3, 101, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s3),
1413 TEGRA_INIT_DATA_MUX("i2s4", NULL, "tegra30-i2s.4", i2s4_parents, CLK_SOURCE_I2S4, 102, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s4),
1414 TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra30-spdif", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_out),
1415 TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra30-spdif", spdif_in_parents, CLK_SOURCE_SPDIF_IN, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_in),
1416 TEGRA_INIT_DATA_MUX("d_audio", "d_audio", "tegra30-ahub", mux_pllacp_clkm, CLK_SOURCE_D_AUDIO, 106, &periph_v_regs, 0, d_audio),
1417 TEGRA_INIT_DATA_MUX("dam0", NULL, "tegra30-dam.0", mux_pllacp_clkm, CLK_SOURCE_DAM0, 108, &periph_v_regs, 0, dam0),
1418 TEGRA_INIT_DATA_MUX("dam1", NULL, "tegra30-dam.1", mux_pllacp_clkm, CLK_SOURCE_DAM1, 109, &periph_v_regs, 0, dam1),
1419 TEGRA_INIT_DATA_MUX("dam2", NULL, "tegra30-dam.2", mux_pllacp_clkm, CLK_SOURCE_DAM2, 110, &periph_v_regs, 0, dam2),
1420 TEGRA_INIT_DATA_MUX("hda", "hda", "tegra30-hda", mux_pllpcm_clkm, CLK_SOURCE_HDA, 125, &periph_v_regs, 0, hda),
1421 TEGRA_INIT_DATA_MUX("hda2codec_2x", "hda2codec", "tegra30-hda", mux_pllpcm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, &periph_v_regs, 0, hda2codec_2x),
1422 TEGRA_INIT_DATA_MUX("sbc1", NULL, "spi_tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1),
1423 TEGRA_INIT_DATA_MUX("sbc2", NULL, "spi_tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SBC2, 44, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2),
1424 TEGRA_INIT_DATA_MUX("sbc3", NULL, "spi_tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SBC3, 46, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3),
1425 TEGRA_INIT_DATA_MUX("sbc4", NULL, "spi_tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SBC4, 68, &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4),
1426 TEGRA_INIT_DATA_MUX("sbc5", NULL, "spi_tegra.4", mux_pllpcm_clkm, CLK_SOURCE_SBC5, 104, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc5),
1427 TEGRA_INIT_DATA_MUX("sbc6", NULL, "spi_tegra.5", mux_pllpcm_clkm, CLK_SOURCE_SBC6, 105, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc6),
1428 TEGRA_INIT_DATA_MUX("sata_oob", NULL, "tegra_sata_oob", mux_pllpcm_clkm, CLK_SOURCE_SATA_OOB, 123, &periph_v_regs, TEGRA_PERIPH_ON_APB, sata_oob),
1429 TEGRA_INIT_DATA_MUX("sata", NULL, "tegra_sata", mux_pllpcm_clkm, CLK_SOURCE_SATA, 124, &periph_v_regs, TEGRA_PERIPH_ON_APB, sata),
1430 TEGRA_INIT_DATA_MUX("ndflash", NULL, "tegra_nand", mux_pllpcm_clkm, CLK_SOURCE_NDFLASH, 13, &periph_l_regs, TEGRA_PERIPH_ON_APB, ndflash),
1431 TEGRA_INIT_DATA_MUX("ndspeed", NULL, "tegra_nand_speed", mux_pllpcm_clkm, CLK_SOURCE_NDSPEED, 80, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed),
1432 TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllpcm_clkm, CLK_SOURCE_VFIR, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, vfir),
1433 TEGRA_INIT_DATA_MUX("csite", NULL, "csite", mux_pllpcm_clkm, CLK_SOURCE_CSITE, 73, &periph_u_regs, TEGRA_PERIPH_ON_APB, csite),
1434 TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllpcm_clkm, CLK_SOURCE_LA, 76, &periph_u_regs, TEGRA_PERIPH_ON_APB, la),
1435 TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllpcm_clkm, CLK_SOURCE_OWR, 71, &periph_u_regs, TEGRA_PERIPH_ON_APB, owr),
1436 TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllpcm_clkm, CLK_SOURCE_MIPI, 50, &periph_h_regs, TEGRA_PERIPH_ON_APB, mipi),
1437 TEGRA_INIT_DATA_MUX("tsensor", NULL, "tegra-tsensor", mux_pllpc_clkm_clk32k, CLK_SOURCE_TSENSOR, 100, &periph_v_regs, TEGRA_PERIPH_ON_APB, tsensor),
1438 TEGRA_INIT_DATA_MUX("i2cslow", NULL, "i2cslow", mux_pllpc_clk32k_clkm, CLK_SOURCE_I2CSLOW, 81, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2cslow),
1439 TEGRA_INIT_DATA_INT("vde", NULL, "vde", mux_pllpcm_clkm, CLK_SOURCE_VDE, 61, &periph_h_regs, 0, vde),
1440 TEGRA_INIT_DATA_INT("vi", "vi", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI, 20, &periph_l_regs, 0, vi),
1441 TEGRA_INIT_DATA_INT("epp", NULL, "epp", mux_pllmcpa, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, epp),
1442 TEGRA_INIT_DATA_INT("mpe", NULL, "mpe", mux_pllmcpa, CLK_SOURCE_MPE, 60, &periph_h_regs, 0, mpe),
1443 TEGRA_INIT_DATA_INT("host1x", NULL, "host1x", mux_pllmcpa, CLK_SOURCE_HOST1X, 28, &periph_l_regs, 0, host1x),
1444 TEGRA_INIT_DATA_INT("3d", NULL, "3d", mux_pllmcpa, CLK_SOURCE_3D, 24, &periph_l_regs, TEGRA_PERIPH_MANUAL_RESET, gr3d),
1445 TEGRA_INIT_DATA_INT("3d2", NULL, "3d2", mux_pllmcpa, CLK_SOURCE_3D2, 98, &periph_v_regs, TEGRA_PERIPH_MANUAL_RESET, gr3d2),
1446 TEGRA_INIT_DATA_INT("2d", NULL, "2d", mux_pllmcpa, CLK_SOURCE_2D, 21, &periph_l_regs, 0, gr2d),
1447 TEGRA_INIT_DATA_INT("se", NULL, "se", mux_pllpcm_clkm, CLK_SOURCE_SE, 127, &periph_v_regs, 0, se),
1448 TEGRA_INIT_DATA_MUX("mselect", NULL, "mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, &periph_v_regs, 0, mselect),
1449 TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllpcm_clkm, CLK_SOURCE_NOR, 42, &periph_h_regs, 0, nor),
1450 TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SDMMC1, 14, &periph_l_regs, 0, sdmmc1),
1451 TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SDMMC2, 9, &periph_l_regs, 0, sdmmc2),
1452 TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SDMMC3, 69, &periph_u_regs, 0, sdmmc3),
1453 TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SDMMC4, 15, &periph_l_regs, 0, sdmmc4),
1454 TEGRA_INIT_DATA_MUX("cve", NULL, "cve", mux_pllpdc_clkm, CLK_SOURCE_CVE, 49, &periph_h_regs, 0, cve),
1455 TEGRA_INIT_DATA_MUX("tvo", NULL, "tvo", mux_pllpdc_clkm, CLK_SOURCE_TVO, 49, &periph_h_regs, 0, tvo),
1456 TEGRA_INIT_DATA_MUX("tvdac", NULL, "tvdac", mux_pllpdc_clkm, CLK_SOURCE_TVDAC, 53, &periph_h_regs, 0, tvdac),
1457 TEGRA_INIT_DATA_MUX("actmon", NULL, "actmon", mux_pllpc_clk32k_clkm, CLK_SOURCE_ACTMON, 119, &periph_v_regs, 0, actmon),
1458 TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor),
1459 TEGRA_INIT_DATA_DIV16("i2c1", "div-clk", "tegra-i2c.0", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2c1),
1460 TEGRA_INIT_DATA_DIV16("i2c2", "div-clk", "tegra-i2c.1", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, &periph_h_regs, TEGRA_PERIPH_ON_APB, i2c2),
1461 TEGRA_INIT_DATA_DIV16("i2c3", "div-clk", "tegra-i2c.2", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2c3),
1462 TEGRA_INIT_DATA_DIV16("i2c4", "div-clk", "tegra-i2c.3", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2c4),
1463 TEGRA_INIT_DATA_DIV16("i2c5", "div-clk", "tegra-i2c.4", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, &periph_h_regs, TEGRA_PERIPH_ON_APB, i2c5),
1464 TEGRA_INIT_DATA_UART("uarta", NULL, "tegra_uart.0", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 6, &periph_l_regs, uarta),
1465 TEGRA_INIT_DATA_UART("uartb", NULL, "tegra_uart.1", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 7, &periph_l_regs, uartb),
1466 TEGRA_INIT_DATA_UART("uartc", NULL, "tegra_uart.2", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 55, &periph_h_regs, uartc),
1467 TEGRA_INIT_DATA_UART("uartd", NULL, "tegra_uart.3", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 65, &periph_u_regs, uartd),
1468 TEGRA_INIT_DATA_UART("uarte", NULL, "tegra_uart.4", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 66, &periph_u_regs, uarte),
1469 TEGRA_INIT_DATA_MUX8("hdmi", NULL, "hdmi", mux_pllpmdacd2_clkm, CLK_SOURCE_HDMI, 51, &periph_h_regs, 0, hdmi),
1470 TEGRA_INIT_DATA_MUX8("extern1", NULL, "extern1", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, &periph_v_regs, 0, extern1),
1471 TEGRA_INIT_DATA_MUX8("extern2", NULL, "extern2", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, &periph_v_regs, 0, extern2),
1472 TEGRA_INIT_DATA_MUX8("extern3", NULL, "extern3", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, &periph_v_regs, 0, extern3),
1473 TEGRA_INIT_DATA("pwm", NULL, "pwm", mux_pllpc_clk32k_clkm, CLK_SOURCE_PWM, 28, 2, 0, 0, 8, 1, 0, &periph_l_regs, 17, periph_clk_enb_refcnt, 0, pwm),
1474};
1475
1476static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
1477 TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllpmdacd2_clkm, CLK_SOURCE_DISP1, 29, 3, 27, &periph_l_regs, 0, disp1),
1478 TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllpmdacd2_clkm, CLK_SOURCE_DISP2, 29, 3, 26, &periph_l_regs, 0, disp2),
1479 TEGRA_INIT_DATA_NODIV("dsib", NULL, "tegradc.1", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB, 25, 1, 82, &periph_u_regs, 0, dsib),
1480};
1481
1482static void __init tegra30_periph_clk_init(void)
1483{
1484 struct tegra_periph_init_data *data;
1485 struct clk *clk;
1486 int i;
1487
1488 /* apbdma */
1489 clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base, 0, 34,
1490 &periph_h_regs, periph_clk_enb_refcnt);
1491 clk_register_clkdev(clk, NULL, "tegra-apbdma");
1492 clks[apbdma] = clk;
1493
1494 /* rtc */
1495 clk = tegra_clk_register_periph_gate("rtc", "clk_32k",
1496 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
1497 clk_base, 0, 4, &periph_l_regs,
1498 periph_clk_enb_refcnt);
1499 clk_register_clkdev(clk, NULL, "rtc-tegra");
1500 clks[rtc] = clk;
1501
1502 /* timer */
1503 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base, 0,
1504 5, &periph_l_regs, periph_clk_enb_refcnt);
1505 clk_register_clkdev(clk, NULL, "timer");
1506 clks[timer] = clk;
1507
1508 /* kbc */
1509 clk = tegra_clk_register_periph_gate("kbc", "clk_32k",
1510 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
1511 clk_base, 0, 36, &periph_h_regs,
1512 periph_clk_enb_refcnt);
1513 clk_register_clkdev(clk, NULL, "tegra-kbc");
1514 clks[kbc] = clk;
1515
1516 /* csus */
1517 clk = tegra_clk_register_periph_gate("csus", "clk_m",
1518 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
1519 clk_base, 0, 92, &periph_u_regs,
1520 periph_clk_enb_refcnt);
1521 clk_register_clkdev(clk, "csus", "tengra_camera");
1522 clks[csus] = clk;
1523
1524 /* vcp */
1525 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, clk_base, 0, 29,
1526 &periph_l_regs, periph_clk_enb_refcnt);
1527 clk_register_clkdev(clk, "vcp", "tegra-avp");
1528 clks[vcp] = clk;
1529
1530 /* bsea */
1531 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, clk_base, 0,
1532 62, &periph_h_regs, periph_clk_enb_refcnt);
1533 clk_register_clkdev(clk, "bsea", "tegra-avp");
1534 clks[bsea] = clk;
1535
1536 /* bsev */
1537 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, clk_base, 0,
1538 63, &periph_h_regs, periph_clk_enb_refcnt);
1539 clk_register_clkdev(clk, "bsev", "tegra-aes");
1540 clks[bsev] = clk;
1541
1542 /* usbd */
1543 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, 0,
1544 22, &periph_l_regs, periph_clk_enb_refcnt);
1545 clk_register_clkdev(clk, NULL, "fsl-tegra-udc");
1546 clks[usbd] = clk;
1547
1548 /* usb2 */
1549 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, 0,
1550 58, &periph_h_regs, periph_clk_enb_refcnt);
1551 clk_register_clkdev(clk, NULL, "tegra-ehci.1");
1552 clks[usb2] = clk;
1553
1554 /* usb3 */
1555 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, 0,
1556 59, &periph_h_regs, periph_clk_enb_refcnt);
1557 clk_register_clkdev(clk, NULL, "tegra-ehci.2");
1558 clks[usb3] = clk;
1559
1560 /* dsia */
1561 clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base,
1562 0, 48, &periph_h_regs,
1563 periph_clk_enb_refcnt);
1564 clk_register_clkdev(clk, "dsia", "tegradc.0");
1565 clks[dsia] = clk;
1566
1567 /* csi */
1568 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base,
1569 0, 52, &periph_h_regs,
1570 periph_clk_enb_refcnt);
1571 clk_register_clkdev(clk, "csi", "tegra_camera");
1572 clks[csi] = clk;
1573
1574 /* isp */
1575 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, 23,
1576 &periph_l_regs, periph_clk_enb_refcnt);
1577 clk_register_clkdev(clk, "isp", "tegra_camera");
1578 clks[isp] = clk;
1579
1580 /* pcie */
1581 clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0,
1582 70, &periph_u_regs, periph_clk_enb_refcnt);
1583 clk_register_clkdev(clk, "pcie", "tegra-pcie");
1584 clks[pcie] = clk;
1585
1586 /* afi */
1587 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72,
1588 &periph_u_regs, periph_clk_enb_refcnt);
1589 clk_register_clkdev(clk, "afi", "tegra-pcie");
1590 clks[afi] = clk;
1591
1592 /* kfuse */
1593 clk = tegra_clk_register_periph_gate("kfuse", "clk_m",
1594 TEGRA_PERIPH_ON_APB,
1595 clk_base, 0, 40, &periph_h_regs,
1596 periph_clk_enb_refcnt);
1597 clk_register_clkdev(clk, NULL, "kfuse-tegra");
1598 clks[kfuse] = clk;
1599
1600 /* fuse */
1601 clk = tegra_clk_register_periph_gate("fuse", "clk_m",
1602 TEGRA_PERIPH_ON_APB,
1603 clk_base, 0, 39, &periph_h_regs,
1604 periph_clk_enb_refcnt);
1605 clk_register_clkdev(clk, "fuse", "fuse-tegra");
1606 clks[fuse] = clk;
1607
1608 /* fuse_burn */
1609 clk = tegra_clk_register_periph_gate("fuse_burn", "clk_m",
1610 TEGRA_PERIPH_ON_APB,
1611 clk_base, 0, 39, &periph_h_regs,
1612 periph_clk_enb_refcnt);
1613 clk_register_clkdev(clk, "fuse_burn", "fuse-tegra");
1614 clks[fuse_burn] = clk;
1615
1616 /* apbif */
1617 clk = tegra_clk_register_periph_gate("apbif", "clk_m", 0,
1618 clk_base, 0, 107, &periph_v_regs,
1619 periph_clk_enb_refcnt);
1620 clk_register_clkdev(clk, "apbif", "tegra30-ahub");
1621 clks[apbif] = clk;
1622
1623 /* hda2hdmi */
1624 clk = tegra_clk_register_periph_gate("hda2hdmi", "clk_m",
1625 TEGRA_PERIPH_ON_APB,
1626 clk_base, 0, 128, &periph_w_regs,
1627 periph_clk_enb_refcnt);
1628 clk_register_clkdev(clk, "hda2hdmi", "tegra30-hda");
1629 clks[hda2hdmi] = clk;
1630
1631 /* sata_cold */
1632 clk = tegra_clk_register_periph_gate("sata_cold", "clk_m",
1633 TEGRA_PERIPH_ON_APB,
1634 clk_base, 0, 129, &periph_w_regs,
1635 periph_clk_enb_refcnt);
1636 clk_register_clkdev(clk, NULL, "tegra_sata_cold");
1637 clks[sata_cold] = clk;
1638
1639 /* dtv */
1640 clk = tegra_clk_register_periph_gate("dtv", "clk_m",
1641 TEGRA_PERIPH_ON_APB,
1642 clk_base, 0, 79, &periph_u_regs,
1643 periph_clk_enb_refcnt);
1644 clk_register_clkdev(clk, NULL, "dtv");
1645 clks[dtv] = clk;
1646
1647 /* emc */
1648 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
1649 ARRAY_SIZE(mux_pllmcp_clkm), 0,
1650 clk_base + CLK_SOURCE_EMC,
1651 30, 2, 0, NULL);
1652 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
1653 57, &periph_h_regs, periph_clk_enb_refcnt);
1654 clk_register_clkdev(clk, "emc", NULL);
1655 clks[emc] = clk;
1656
1657 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
1658 data = &tegra_periph_clk_list[i];
1659 clk = tegra_clk_register_periph(data->name, data->parent_names,
1660 data->num_parents, &data->periph,
1661 clk_base, data->offset);
1662 clk_register_clkdev(clk, data->con_id, data->dev_id);
1663 clks[data->clk_id] = clk;
1664 }
1665
1666 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
1667 data = &tegra_periph_nodiv_clk_list[i];
1668 clk = tegra_clk_register_periph_nodiv(data->name,
1669 data->parent_names,
1670 data->num_parents, &data->periph,
1671 clk_base, data->offset);
1672 clk_register_clkdev(clk, data->con_id, data->dev_id);
1673 clks[data->clk_id] = clk;
1674 }
1675}
1676
1677static void __init tegra30_fixed_clk_init(void)
1678{
1679 struct clk *clk;
1680
1681 /* clk_32k */
1682 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT,
1683 32768);
1684 clk_register_clkdev(clk, "clk_32k", NULL);
1685 clks[clk_32k] = clk;
1686
1687 /* clk_m_div2 */
1688 clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
1689 CLK_SET_RATE_PARENT, 1, 2);
1690 clk_register_clkdev(clk, "clk_m_div2", NULL);
1691 clks[clk_m_div2] = clk;
1692
1693 /* clk_m_div4 */
1694 clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
1695 CLK_SET_RATE_PARENT, 1, 4);
1696 clk_register_clkdev(clk, "clk_m_div4", NULL);
1697 clks[clk_m_div4] = clk;
1698
1699 /* cml0 */
1700 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
1701 0, 0, &cml_lock);
1702 clk_register_clkdev(clk, "cml0", NULL);
1703 clks[cml0] = clk;
1704
1705 /* cml1 */
1706 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
1707 1, 0, &cml_lock);
1708 clk_register_clkdev(clk, "cml1", NULL);
1709 clks[cml1] = clk;
1710
1711 /* pciex */
1712 clk = clk_register_fixed_rate(NULL, "pciex", "pll_e", 0, 100000000);
1713 clk_register_clkdev(clk, "pciex", NULL);
1714 clks[pciex] = clk;
1715}
1716
1717static void __init tegra30_osc_clk_init(void)
1718{
1719 struct clk *clk;
1720 unsigned int pll_ref_div;
1721
1722 tegra30_clk_measure_input_freq();
1723
1724 /* clk_m */
1725 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT,
1726 input_freq);
1727 clk_register_clkdev(clk, "clk_m", NULL);
1728 clks[clk_m] = clk;
1729
1730 /* pll_ref */
1731 pll_ref_div = tegra30_get_pll_ref_div();
1732 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
1733 CLK_SET_RATE_PARENT, 1, pll_ref_div);
1734 clk_register_clkdev(clk, "pll_ref", NULL);
1735 clks[pll_ref] = clk;
1736}
1737
1738/* Tegra30 CPU clock and reset control functions */
1739static void tegra30_wait_cpu_in_reset(u32 cpu)
1740{
1741 unsigned int reg;
1742
1743 do {
1744 reg = readl(clk_base +
1745 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1746 cpu_relax();
1747 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
1748
1749 return;
1750}
1751
1752static void tegra30_put_cpu_in_reset(u32 cpu)
1753{
1754 writel(CPU_RESET(cpu),
1755 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
1756 dmb();
1757}
1758
1759static void tegra30_cpu_out_of_reset(u32 cpu)
1760{
1761 writel(CPU_RESET(cpu),
1762 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
1763 wmb();
1764}
1765
1766
1767static void tegra30_enable_cpu_clock(u32 cpu)
1768{
1769 unsigned int reg;
1770
1771 writel(CPU_CLOCK(cpu),
1772 clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
1773 reg = readl(clk_base +
1774 TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
1775}
1776
1777static void tegra30_disable_cpu_clock(u32 cpu)
1778{
1779
1780 unsigned int reg;
1781
1782 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1783 writel(reg | CPU_CLOCK(cpu),
1784 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1785}
1786
1787#ifdef CONFIG_PM_SLEEP
1788static bool tegra30_cpu_rail_off_ready(void)
1789{
1790 unsigned int cpu_rst_status;
1791 int cpu_pwr_status;
1792
1793 cpu_rst_status = readl(clk_base +
1794 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1795 cpu_pwr_status = tegra_powergate_is_powered(TEGRA_POWERGATE_CPU1) ||
1796 tegra_powergate_is_powered(TEGRA_POWERGATE_CPU2) ||
1797 tegra_powergate_is_powered(TEGRA_POWERGATE_CPU3);
1798
1799 if (((cpu_rst_status & 0xE) != 0xE) || cpu_pwr_status)
1800 return false;
1801
1802 return true;
1803}
1804
1805static void tegra30_cpu_clock_suspend(void)
1806{
1807 /* switch coresite to clk_m, save off original source */
1808 tegra30_cpu_clk_sctx.clk_csite_src =
1809 readl(clk_base + CLK_RESET_SOURCE_CSITE);
1810 writel(3<<30, clk_base + CLK_RESET_SOURCE_CSITE);
1811
1812 tegra30_cpu_clk_sctx.cpu_burst =
1813 readl(clk_base + CLK_RESET_CCLK_BURST);
1814 tegra30_cpu_clk_sctx.pllx_base =
1815 readl(clk_base + CLK_RESET_PLLX_BASE);
1816 tegra30_cpu_clk_sctx.pllx_misc =
1817 readl(clk_base + CLK_RESET_PLLX_MISC);
1818 tegra30_cpu_clk_sctx.cclk_divider =
1819 readl(clk_base + CLK_RESET_CCLK_DIVIDER);
1820}
1821
1822static void tegra30_cpu_clock_resume(void)
1823{
1824 unsigned int reg, policy;
1825
1826 /* Is CPU complex already running on PLLX? */
1827 reg = readl(clk_base + CLK_RESET_CCLK_BURST);
1828 policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF;
1829
1830 if (policy == CLK_RESET_CCLK_IDLE_POLICY)
1831 reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF;
1832 else if (policy == CLK_RESET_CCLK_RUN_POLICY)
1833 reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF;
1834 else
1835 BUG();
1836
1837 if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) {
1838 /* restore PLLX settings if CPU is on different PLL */
1839 writel(tegra30_cpu_clk_sctx.pllx_misc,
1840 clk_base + CLK_RESET_PLLX_MISC);
1841 writel(tegra30_cpu_clk_sctx.pllx_base,
1842 clk_base + CLK_RESET_PLLX_BASE);
1843
1844 /* wait for PLL stabilization if PLLX was enabled */
1845 if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30))
1846 udelay(300);
1847 }
1848
1849 /*
1850 * Restore original burst policy setting for calls resulting from CPU
1851 * LP2 in idle or system suspend.
1852 */
1853 writel(tegra30_cpu_clk_sctx.cclk_divider,
1854 clk_base + CLK_RESET_CCLK_DIVIDER);
1855 writel(tegra30_cpu_clk_sctx.cpu_burst,
1856 clk_base + CLK_RESET_CCLK_BURST);
1857
1858 writel(tegra30_cpu_clk_sctx.clk_csite_src,
1859 clk_base + CLK_RESET_SOURCE_CSITE);
1860}
1861#endif
1862
1863static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
1864 .wait_for_reset = tegra30_wait_cpu_in_reset,
1865 .put_in_reset = tegra30_put_cpu_in_reset,
1866 .out_of_reset = tegra30_cpu_out_of_reset,
1867 .enable_clock = tegra30_enable_cpu_clock,
1868 .disable_clock = tegra30_disable_cpu_clock,
1869#ifdef CONFIG_PM_SLEEP
1870 .rail_off_ready = tegra30_cpu_rail_off_ready,
1871 .suspend = tegra30_cpu_clock_suspend,
1872 .resume = tegra30_cpu_clock_resume,
1873#endif
1874};
1875
1876static __initdata struct tegra_clk_init_table init_table[] = {
1877 {uarta, pll_p, 408000000, 1},
1878 {pll_a, clk_max, 564480000, 1},
1879 {pll_a_out0, clk_max, 11289600, 1},
1880 {extern1, pll_a_out0, 0, 1},
1881 {clk_out_1_mux, extern1, 0, 0},
1882 {clk_out_1, clk_max, 0, 1},
1883 {blink, clk_max, 0, 1},
1884 {i2s0, pll_a_out0, 11289600, 0},
1885 {i2s1, pll_a_out0, 11289600, 0},
1886 {i2s2, pll_a_out0, 11289600, 0},
1887 {i2s3, pll_a_out0, 11289600, 0},
1888 {i2s4, pll_a_out0, 11289600, 0},
1889 {sdmmc1, pll_p, 48000000, 0},
1890 {sdmmc2, pll_p, 48000000, 0},
1891 {sdmmc3, pll_p, 48000000, 0},
1892 {pll_m, clk_max, 0, 1},
1893 {pclk, clk_max, 0, 1},
1894 {csite, clk_max, 0, 1},
1895 {emc, clk_max, 0, 1},
1896 {mselect, clk_max, 0, 1},
1897 {sbc1, pll_p, 100000000, 0},
1898 {sbc2, pll_p, 100000000, 0},
1899 {sbc3, pll_p, 100000000, 0},
1900 {sbc4, pll_p, 100000000, 0},
1901 {sbc5, pll_p, 100000000, 0},
1902 {sbc6, pll_p, 100000000, 0},
1903 {host1x, pll_c, 150000000, 0},
1904 {disp1, pll_p, 600000000, 0},
1905 {disp2, pll_p, 600000000, 0},
1906 {twd, clk_max, 0, 1},
1907 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */
1908};
1909
1910/*
1911 * Some clocks may be used by different drivers depending on the board
1912 * configuration. List those here to register them twice in the clock lookup
1913 * table under two names.
1914 */
1915static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
1916 TEGRA_CLK_DUPLICATE(usbd, "utmip-pad", NULL),
1917 TEGRA_CLK_DUPLICATE(usbd, "tegra-ehci.0", NULL),
1918 TEGRA_CLK_DUPLICATE(usbd, "tegra-otg", NULL),
1919 TEGRA_CLK_DUPLICATE(bsev, "tegra-avp", "bsev"),
1920 TEGRA_CLK_DUPLICATE(bsev, "nvavp", "bsev"),
1921 TEGRA_CLK_DUPLICATE(vde, "tegra-aes", "vde"),
1922 TEGRA_CLK_DUPLICATE(bsea, "tegra-aes", "bsea"),
1923 TEGRA_CLK_DUPLICATE(bsea, "nvavp", "bsea"),
1924 TEGRA_CLK_DUPLICATE(cml1, "tegra_sata_cml", NULL),
1925 TEGRA_CLK_DUPLICATE(cml0, "tegra_pcie", "cml"),
1926 TEGRA_CLK_DUPLICATE(pciex, "tegra_pcie", "pciex"),
1927 TEGRA_CLK_DUPLICATE(twd, "smp_twd", NULL),
1928 TEGRA_CLK_DUPLICATE(vcp, "nvavp", "vcp"),
1929 TEGRA_CLK_DUPLICATE(clk_max, NULL, NULL), /* MUST be the last entry */
1930};
1931
1932static const struct of_device_id pmc_match[] __initconst = {
1933 { .compatible = "nvidia,tegra30-pmc" },
1934 {},
1935};
1936
1937void __init tegra30_clock_init(struct device_node *np)
1938{
1939 struct device_node *node;
1940 int i;
1941
1942 clk_base = of_iomap(np, 0);
1943 if (!clk_base) {
1944 pr_err("ioremap tegra30 CAR failed\n");
1945 return;
1946 }
1947
1948 node = of_find_matching_node(NULL, pmc_match);
1949 if (!node) {
1950 pr_err("Failed to find pmc node\n");
1951 BUG();
1952 }
1953
1954 pmc_base = of_iomap(node, 0);
1955 if (!pmc_base) {
1956 pr_err("Can't map pmc registers\n");
1957 BUG();
1958 }
1959
1960 tegra30_osc_clk_init();
1961 tegra30_fixed_clk_init();
1962 tegra30_pll_init();
1963 tegra30_super_clk_init();
1964 tegra30_periph_clk_init();
1965 tegra30_audio_clk_init();
1966 tegra30_pmc_clk_init();
1967
1968 for (i = 0; i < ARRAY_SIZE(clks); i++) {
1969 if (IS_ERR(clks[i])) {
1970 pr_err("Tegra30 clk %d: register failed with %ld\n",
1971 i, PTR_ERR(clks[i]));
1972 BUG();
1973 }
1974 if (!clks[i])
1975 clks[i] = ERR_PTR(-EINVAL);
1976 }
1977
1978 tegra_init_dup_clks(tegra_clk_duplicates, clks, clk_max);
1979
1980 clk_data.clks = clks;
1981 clk_data.clk_num = ARRAY_SIZE(clks);
1982 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
1983
1984 tegra_init_from_table(init_table, clks, clk_max);
1985
1986 tegra_cpu_car_ops = &tegra30_cpu_car_ops;
1987}
diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
new file mode 100644
index 000000000000..a603b9af0ad3
--- /dev/null
+++ b/drivers/clk/tegra/clk.c
@@ -0,0 +1,85 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/clk.h>
18#include <linux/clk-provider.h>
19#include <linux/of.h>
20#include <linux/clk/tegra.h>
21
22#include "clk.h"
23
24/* Global data of Tegra CPU CAR ops */
25struct tegra_cpu_car_ops *tegra_cpu_car_ops;
26
27void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
28 struct clk *clks[], int clk_max)
29{
30 struct clk *clk;
31
32 for (; dup_list->clk_id < clk_max; dup_list++) {
33 clk = clks[dup_list->clk_id];
34 dup_list->lookup.clk = clk;
35 clkdev_add(&dup_list->lookup);
36 }
37}
38
39void __init tegra_init_from_table(struct tegra_clk_init_table *tbl,
40 struct clk *clks[], int clk_max)
41{
42 struct clk *clk;
43
44 for (; tbl->clk_id < clk_max; tbl++) {
45 clk = clks[tbl->clk_id];
46 if (IS_ERR_OR_NULL(clk))
47 return;
48
49 if (tbl->parent_id < clk_max) {
50 struct clk *parent = clks[tbl->parent_id];
51 if (clk_set_parent(clk, parent)) {
52 pr_err("%s: Failed to set parent %s of %s\n",
53 __func__, __clk_get_name(parent),
54 __clk_get_name(clk));
55 WARN_ON(1);
56 }
57 }
58
59 if (tbl->rate)
60 if (clk_set_rate(clk, tbl->rate)) {
61 pr_err("%s: Failed to set rate %lu of %s\n",
62 __func__, tbl->rate,
63 __clk_get_name(clk));
64 WARN_ON(1);
65 }
66
67 if (tbl->state)
68 if (clk_prepare_enable(clk)) {
69 pr_err("%s: Failed to enable %s\n", __func__,
70 __clk_get_name(clk));
71 WARN_ON(1);
72 }
73 }
74}
75
76static const struct of_device_id tegra_dt_clk_match[] = {
77 { .compatible = "nvidia,tegra20-car", .data = tegra20_clock_init },
78 { .compatible = "nvidia,tegra30-car", .data = tegra30_clock_init },
79 { }
80};
81
82void __init tegra_clocks_init(void)
83{
84 of_clk_init(tegra_dt_clk_match);
85}
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
new file mode 100644
index 000000000000..0744731c6229
--- /dev/null
+++ b/drivers/clk/tegra/clk.h
@@ -0,0 +1,502 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef __TEGRA_CLK_H
18#define __TEGRA_CLK_H
19
20#include <linux/clk-provider.h>
21#include <linux/clkdev.h>
22
23/**
24 * struct tegra_clk_sync_source - external clock source from codec
25 *
26 * @hw: handle between common and hardware-specific interfaces
27 * @rate: input frequency from source
28 * @max_rate: max rate allowed
29 */
30struct tegra_clk_sync_source {
31 struct clk_hw hw;
32 unsigned long rate;
33 unsigned long max_rate;
34};
35
36#define to_clk_sync_source(_hw) \
37 container_of(_hw, struct tegra_clk_sync_source, hw)
38
39extern const struct clk_ops tegra_clk_sync_source_ops;
40struct clk *tegra_clk_register_sync_source(const char *name,
41 unsigned long fixed_rate, unsigned long max_rate);
42
43/**
44 * struct tegra_clk_frac_div - fractional divider clock
45 *
46 * @hw: handle between common and hardware-specific interfaces
47 * @reg: register containing divider
48 * @flags: hardware-specific flags
49 * @shift: shift to the divider bit field
50 * @width: width of the divider bit field
51 * @frac_width: width of the fractional bit field
52 * @lock: register lock
53 *
54 * Flags:
55 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
56 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
57 * flag indicates that this divider is for fixed rate PLL.
58 * TEGRA_DIVIDER_INT - Some modules can not cope with the duty cycle when
59 * fraction bit is set. This flags indicates to calculate divider for which
60 * fracton bit will be zero.
61 * TEGRA_DIVIDER_UART - UART module divider has additional enable bit which is
62 * set when divider value is not 0. This flags indicates that the divider
63 * is for UART module.
64 */
65struct tegra_clk_frac_div {
66 struct clk_hw hw;
67 void __iomem *reg;
68 u8 flags;
69 u8 shift;
70 u8 width;
71 u8 frac_width;
72 spinlock_t *lock;
73};
74
75#define to_clk_frac_div(_hw) container_of(_hw, struct tegra_clk_frac_div, hw)
76
77#define TEGRA_DIVIDER_ROUND_UP BIT(0)
78#define TEGRA_DIVIDER_FIXED BIT(1)
79#define TEGRA_DIVIDER_INT BIT(2)
80#define TEGRA_DIVIDER_UART BIT(3)
81
82extern const struct clk_ops tegra_clk_frac_div_ops;
83struct clk *tegra_clk_register_divider(const char *name,
84 const char *parent_name, void __iomem *reg,
85 unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width,
86 u8 frac_width, spinlock_t *lock);
87
88/*
89 * Tegra PLL:
90 *
91 * In general, there are 3 requirements for each PLL
92 * that SW needs to be comply with.
93 * (1) Input frequency range (REF).
94 * (2) Comparison frequency range (CF). CF = REF/DIVM.
95 * (3) VCO frequency range (VCO). VCO = CF * DIVN.
96 *
97 * The final PLL output frequency (FO) = VCO >> DIVP.
98 */
99
100/**
101 * struct tegra_clk_pll_freq_table - PLL frequecy table
102 *
103 * @input_rate: input rate from source
104 * @output_rate: output rate from PLL for the input rate
105 * @n: feedback divider
106 * @m: input divider
107 * @p: post divider
108 * @cpcon: charge pump current
109 */
110struct tegra_clk_pll_freq_table {
111 unsigned long input_rate;
112 unsigned long output_rate;
113 u16 n;
114 u16 m;
115 u8 p;
116 u8 cpcon;
117};
118
119/**
120 * struct clk_pll_params - PLL parameters
121 *
122 * @input_min: Minimum input frequency
123 * @input_max: Maximum input frequency
124 * @cf_min: Minimum comparison frequency
125 * @cf_max: Maximum comparison frequency
126 * @vco_min: Minimum VCO frequency
127 * @vco_max: Maximum VCO frequency
128 * @base_reg: PLL base reg offset
129 * @misc_reg: PLL misc reg offset
130 * @lock_reg: PLL lock reg offset
131 * @lock_bit_idx: Bit index for PLL lock status
132 * @lock_enable_bit_idx: Bit index to enable PLL lock
133 * @lock_delay: Delay in us if PLL lock is not used
134 */
135struct tegra_clk_pll_params {
136 unsigned long input_min;
137 unsigned long input_max;
138 unsigned long cf_min;
139 unsigned long cf_max;
140 unsigned long vco_min;
141 unsigned long vco_max;
142
143 u32 base_reg;
144 u32 misc_reg;
145 u32 lock_reg;
146 u32 lock_bit_idx;
147 u32 lock_enable_bit_idx;
148 int lock_delay;
149};
150
151/**
152 * struct tegra_clk_pll - Tegra PLL clock
153 *
154 * @hw: handle between common and hardware-specifix interfaces
155 * @clk_base: address of CAR controller
156 * @pmc: address of PMC, required to read override bits
157 * @freq_table: array of frequencies supported by PLL
158 * @params: PLL parameters
159 * @flags: PLL flags
160 * @fixed_rate: PLL rate if it is fixed
161 * @lock: register lock
162 * @divn_shift: shift to the feedback divider bit field
163 * @divn_width: width of the feedback divider bit field
164 * @divm_shift: shift to the input divider bit field
165 * @divm_width: width of the input divider bit field
166 * @divp_shift: shift to the post divider bit field
167 * @divp_width: width of the post divider bit field
168 *
169 * Flags:
170 * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
171 * PLL locking. If not set it will use lock_delay value to wait.
172 * TEGRA_PLL_HAS_CPCON - This flag indicates that CPCON value needs
173 * to be programmed to change output frequency of the PLL.
174 * TEGRA_PLL_SET_LFCON - This flag indicates that LFCON value needs
175 * to be programmed to change output frequency of the PLL.
176 * TEGRA_PLL_SET_DCCON - This flag indicates that DCCON value needs
177 * to be programmed to change output frequency of the PLL.
178 * TEGRA_PLLU - PLLU has inverted post divider. This flags indicated
179 * that it is PLLU and invert post divider value.
180 * TEGRA_PLLM - PLLM has additional override settings in PMC. This
181 * flag indicates that it is PLLM and use override settings.
182 * TEGRA_PLL_FIXED - We are not supposed to change output frequency
183 * of some plls.
184 * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling.
185 */
186struct tegra_clk_pll {
187 struct clk_hw hw;
188 void __iomem *clk_base;
189 void __iomem *pmc;
190 u8 flags;
191 unsigned long fixed_rate;
192 spinlock_t *lock;
193 u8 divn_shift;
194 u8 divn_width;
195 u8 divm_shift;
196 u8 divm_width;
197 u8 divp_shift;
198 u8 divp_width;
199 struct tegra_clk_pll_freq_table *freq_table;
200 struct tegra_clk_pll_params *params;
201};
202
203#define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw)
204
205#define TEGRA_PLL_USE_LOCK BIT(0)
206#define TEGRA_PLL_HAS_CPCON BIT(1)
207#define TEGRA_PLL_SET_LFCON BIT(2)
208#define TEGRA_PLL_SET_DCCON BIT(3)
209#define TEGRA_PLLU BIT(4)
210#define TEGRA_PLLM BIT(5)
211#define TEGRA_PLL_FIXED BIT(6)
212#define TEGRA_PLLE_CONFIGURE BIT(7)
213
214extern const struct clk_ops tegra_clk_pll_ops;
215extern const struct clk_ops tegra_clk_plle_ops;
216struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
217 void __iomem *clk_base, void __iomem *pmc,
218 unsigned long flags, unsigned long fixed_rate,
219 struct tegra_clk_pll_params *pll_params, u8 pll_flags,
220 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock);
221struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
222 void __iomem *clk_base, void __iomem *pmc,
223 unsigned long flags, unsigned long fixed_rate,
224 struct tegra_clk_pll_params *pll_params, u8 pll_flags,
225 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock);
226
227/**
228 * struct tegra_clk_pll_out - PLL divider down clock
229 *
230 * @hw: handle between common and hardware-specific interfaces
231 * @reg: register containing the PLL divider
232 * @enb_bit_idx: bit to enable/disable PLL divider
233 * @rst_bit_idx: bit to reset PLL divider
234 * @lock: register lock
235 * @flags: hardware-specific flags
236 */
237struct tegra_clk_pll_out {
238 struct clk_hw hw;
239 void __iomem *reg;
240 u8 enb_bit_idx;
241 u8 rst_bit_idx;
242 spinlock_t *lock;
243 u8 flags;
244};
245
246#define to_clk_pll_out(_hw) container_of(_hw, struct tegra_clk_pll_out, hw)
247
248extern const struct clk_ops tegra_clk_pll_out_ops;
249struct clk *tegra_clk_register_pll_out(const char *name,
250 const char *parent_name, void __iomem *reg, u8 enb_bit_idx,
251 u8 rst_bit_idx, unsigned long flags, u8 pll_div_flags,
252 spinlock_t *lock);
253
254/**
255 * struct tegra_clk_periph_regs - Registers controlling peripheral clock
256 *
257 * @enb_reg: read the enable status
258 * @enb_set_reg: write 1 to enable clock
259 * @enb_clr_reg: write 1 to disable clock
260 * @rst_reg: read the reset status
261 * @rst_set_reg: write 1 to assert the reset of peripheral
262 * @rst_clr_reg: write 1 to deassert the reset of peripheral
263 */
264struct tegra_clk_periph_regs {
265 u32 enb_reg;
266 u32 enb_set_reg;
267 u32 enb_clr_reg;
268 u32 rst_reg;
269 u32 rst_set_reg;
270 u32 rst_clr_reg;
271};
272
273/**
274 * struct tegra_clk_periph_gate - peripheral gate clock
275 *
276 * @magic: magic number to validate type
277 * @hw: handle between common and hardware-specific interfaces
278 * @clk_base: address of CAR controller
279 * @regs: Registers to control the peripheral
280 * @flags: hardware-specific flags
281 * @clk_num: Clock number
282 * @enable_refcnt: array to maintain reference count of the clock
283 *
284 * Flags:
285 * TEGRA_PERIPH_NO_RESET - This flag indicates that reset is not allowed
286 * for this module.
287 * TEGRA_PERIPH_MANUAL_RESET - This flag indicates not to reset module
288 * after clock enable and driver for the module is responsible for
289 * doing reset.
290 * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the
291 * bus to flush the write operation in apb bus. This flag indicates
292 * that this peripheral is in apb bus.
293 */
294struct tegra_clk_periph_gate {
295 u32 magic;
296 struct clk_hw hw;
297 void __iomem *clk_base;
298 u8 flags;
299 int clk_num;
300 int *enable_refcnt;
301 struct tegra_clk_periph_regs *regs;
302};
303
304#define to_clk_periph_gate(_hw) \
305 container_of(_hw, struct tegra_clk_periph_gate, hw)
306
307#define TEGRA_CLK_PERIPH_GATE_MAGIC 0x17760309
308
309#define TEGRA_PERIPH_NO_RESET BIT(0)
310#define TEGRA_PERIPH_MANUAL_RESET BIT(1)
311#define TEGRA_PERIPH_ON_APB BIT(2)
312
313void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert);
314extern const struct clk_ops tegra_clk_periph_gate_ops;
315struct clk *tegra_clk_register_periph_gate(const char *name,
316 const char *parent_name, u8 gate_flags, void __iomem *clk_base,
317 unsigned long flags, int clk_num,
318 struct tegra_clk_periph_regs *pregs, int *enable_refcnt);
319
320/**
321 * struct clk-periph - peripheral clock
322 *
323 * @magic: magic number to validate type
324 * @hw: handle between common and hardware-specific interfaces
325 * @mux: mux clock
326 * @divider: divider clock
327 * @gate: gate clock
328 * @mux_ops: mux clock ops
329 * @div_ops: divider clock ops
330 * @gate_ops: gate clock ops
331 */
332struct tegra_clk_periph {
333 u32 magic;
334 struct clk_hw hw;
335 struct clk_mux mux;
336 struct tegra_clk_frac_div divider;
337 struct tegra_clk_periph_gate gate;
338
339 const struct clk_ops *mux_ops;
340 const struct clk_ops *div_ops;
341 const struct clk_ops *gate_ops;
342};
343
344#define to_clk_periph(_hw) container_of(_hw, struct tegra_clk_periph, hw)
345
346#define TEGRA_CLK_PERIPH_MAGIC 0x18221223
347
348extern const struct clk_ops tegra_clk_periph_ops;
349struct clk *tegra_clk_register_periph(const char *name,
350 const char **parent_names, int num_parents,
351 struct tegra_clk_periph *periph, void __iomem *clk_base,
352 u32 offset);
353struct clk *tegra_clk_register_periph_nodiv(const char *name,
354 const char **parent_names, int num_parents,
355 struct tegra_clk_periph *periph, void __iomem *clk_base,
356 u32 offset);
357
358#define TEGRA_CLK_PERIPH(_mux_shift, _mux_width, _mux_flags, \
359 _div_shift, _div_width, _div_frac_width, \
360 _div_flags, _clk_num, _enb_refcnt, _regs, \
361 _gate_flags) \
362 { \
363 .mux = { \
364 .flags = _mux_flags, \
365 .shift = _mux_shift, \
366 .width = _mux_width, \
367 }, \
368 .divider = { \
369 .flags = _div_flags, \
370 .shift = _div_shift, \
371 .width = _div_width, \
372 .frac_width = _div_frac_width, \
373 }, \
374 .gate = { \
375 .flags = _gate_flags, \
376 .clk_num = _clk_num, \
377 .enable_refcnt = _enb_refcnt, \
378 .regs = _regs, \
379 }, \
380 .mux_ops = &clk_mux_ops, \
381 .div_ops = &tegra_clk_frac_div_ops, \
382 .gate_ops = &tegra_clk_periph_gate_ops, \
383 }
384
385struct tegra_periph_init_data {
386 const char *name;
387 int clk_id;
388 const char **parent_names;
389 int num_parents;
390 struct tegra_clk_periph periph;
391 u32 offset;
392 const char *con_id;
393 const char *dev_id;
394};
395
396#define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset, \
397 _mux_shift, _mux_width, _mux_flags, _div_shift, \
398 _div_width, _div_frac_width, _div_flags, _regs, \
399 _clk_num, _enb_refcnt, _gate_flags, _clk_id) \
400 { \
401 .name = _name, \
402 .clk_id = _clk_id, \
403 .parent_names = _parent_names, \
404 .num_parents = ARRAY_SIZE(_parent_names), \
405 .periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_width, \
406 _mux_flags, _div_shift, \
407 _div_width, _div_frac_width, \
408 _div_flags, _clk_num, \
409 _enb_refcnt, _regs, \
410 _gate_flags), \
411 .offset = _offset, \
412 .con_id = _con_id, \
413 .dev_id = _dev_id, \
414 }
415
416/**
417 * struct clk_super_mux - super clock
418 *
419 * @hw: handle between common and hardware-specific interfaces
420 * @reg: register controlling multiplexer
421 * @width: width of the multiplexer bit field
422 * @flags: hardware-specific flags
423 * @div2_index: bit controlling divide-by-2
424 * @pllx_index: PLLX index in the parent list
425 * @lock: register lock
426 *
427 * Flags:
428 * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates
429 * that this is LP cluster clock.
430 */
431struct tegra_clk_super_mux {
432 struct clk_hw hw;
433 void __iomem *reg;
434 u8 width;
435 u8 flags;
436 u8 div2_index;
437 u8 pllx_index;
438 spinlock_t *lock;
439};
440
441#define to_clk_super_mux(_hw) container_of(_hw, struct tegra_clk_super_mux, hw)
442
443#define TEGRA_DIVIDER_2 BIT(0)
444
445extern const struct clk_ops tegra_clk_super_ops;
446struct clk *tegra_clk_register_super_mux(const char *name,
447 const char **parent_names, u8 num_parents,
448 unsigned long flags, void __iomem *reg, u8 clk_super_flags,
449 u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock);
450
451/**
452 * struct clk_init_tabel - clock initialization table
453 * @clk_id: clock id as mentioned in device tree bindings
454 * @parent_id: parent clock id as mentioned in device tree bindings
455 * @rate: rate to set
456 * @state: enable/disable
457 */
458struct tegra_clk_init_table {
459 unsigned int clk_id;
460 unsigned int parent_id;
461 unsigned long rate;
462 int state;
463};
464
465/**
466 * struct clk_duplicate - duplicate clocks
467 * @clk_id: clock id as mentioned in device tree bindings
468 * @lookup: duplicate lookup entry for the clock
469 */
470struct tegra_clk_duplicate {
471 int clk_id;
472 struct clk_lookup lookup;
473};
474
475#define TEGRA_CLK_DUPLICATE(_clk_id, _dev, _con) \
476 { \
477 .clk_id = _clk_id, \
478 .lookup = { \
479 .dev_id = _dev, \
480 .con_id = _con, \
481 }, \
482 }
483
484void tegra_init_from_table(struct tegra_clk_init_table *tbl,
485 struct clk *clks[], int clk_max);
486
487void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
488 struct clk *clks[], int clk_max);
489
490#ifdef CONFIG_ARCH_TEGRA_2x_SOC
491void tegra20_clock_init(struct device_node *np);
492#else
493static inline void tegra20_clock_init(struct device_node *np) {}
494#endif /* CONFIG_ARCH_TEGRA_2x_SOC */
495
496#ifdef CONFIG_ARCH_TEGRA_3x_SOC
497void tegra30_clock_init(struct device_node *np);
498#else
499static inline void tegra30_clock_init(struct device_node *np) {}
500#endif /* CONFIG_ARCH_TEGRA_3x_SOC */
501
502#endif /* TEGRA_CLK_H */
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 440449c1ca21..596c45c2f192 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o
17obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o 17obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o
18obj-$(CONFIG_ARCH_BCM2835) += bcm2835_timer.o 18obj-$(CONFIG_ARCH_BCM2835) += bcm2835_timer.o
19obj-$(CONFIG_SUNXI_TIMER) += sunxi_timer.o 19obj-$(CONFIG_SUNXI_TIMER) += sunxi_timer.o
20obj-$(CONFIG_ARCH_TEGRA) += tegra20_timer.o
20obj-$(CONFIG_VT8500_TIMER) += vt8500_timer.o 21obj-$(CONFIG_VT8500_TIMER) += vt8500_timer.o
21 22
22obj-$(CONFIG_CLKSRC_ARM_GENERIC) += arm_generic.o 23obj-$(CONFIG_CLKSRC_ARM_GENERIC) += arm_generic.o
diff --git a/arch/arm/mach-tegra/timer.c b/drivers/clocksource/tegra20_timer.c
index eba0969ded19..0bde03feb095 100644
--- a/arch/arm/mach-tegra/timer.c
+++ b/drivers/clocksource/tegra20_timer.c
@@ -1,6 +1,4 @@
1/* 1/*
2 * arch/arch/mach-tegra/timer.c
3 *
4 * Copyright (C) 2010 Google, Inc. 2 * Copyright (C) 2010 Google, Inc.
5 * 3 *
6 * Author: 4 * Author:
@@ -33,8 +31,6 @@
33#include <asm/smp_twd.h> 31#include <asm/smp_twd.h>
34#include <asm/sched_clock.h> 32#include <asm/sched_clock.h>
35 33
36#include "board.h"
37
38#define RTC_SECONDS 0x08 34#define RTC_SECONDS 0x08
39#define RTC_SHADOW_SECONDS 0x0c 35#define RTC_SHADOW_SECONDS 0x0c
40#define RTC_MILLISECONDS 0x10 36#define RTC_MILLISECONDS 0x10
@@ -168,7 +164,7 @@ static const struct of_device_id rtc_match[] __initconst = {
168 {} 164 {}
169}; 165};
170 166
171void __init tegra_init_timer(void) 167static void __init tegra20_init_timer(void)
172{ 168{
173 struct device_node *np; 169 struct device_node *np;
174 struct clk *clk; 170 struct clk *clk;
@@ -183,7 +179,7 @@ void __init tegra_init_timer(void)
183 179
184 timer_reg_base = of_iomap(np, 0); 180 timer_reg_base = of_iomap(np, 0);
185 if (!timer_reg_base) { 181 if (!timer_reg_base) {
186 pr_err("Can't map timer registers"); 182 pr_err("Can't map timer registers\n");
187 BUG(); 183 BUG();
188 } 184 }
189 185
@@ -268,6 +264,7 @@ void __init tegra_init_timer(void)
268#endif 264#endif
269 register_persistent_clock(NULL, tegra_read_persistent_clock); 265 register_persistent_clock(NULL, tegra_read_persistent_clock);
270} 266}
267CLOCKSOURCE_OF_DECLARE(tegra20, "nvidia,tegra20-timer", tegra20_init_timer);
271 268
272#ifdef CONFIG_PM 269#ifdef CONFIG_PM
273static u32 usec_config; 270static u32 usec_config;
diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
index 3cad856fe67f..2a02c11890ec 100644
--- a/drivers/dma/tegra20-apb-dma.c
+++ b/drivers/dma/tegra20-apb-dma.c
@@ -31,8 +31,8 @@
31#include <linux/platform_device.h> 31#include <linux/platform_device.h>
32#include <linux/pm_runtime.h> 32#include <linux/pm_runtime.h>
33#include <linux/slab.h> 33#include <linux/slab.h>
34#include <linux/clk/tegra.h>
34 35
35#include <mach/clk.h>
36#include "dmaengine.h" 36#include "dmaengine.h"
37 37
38#define TEGRA_APBDMA_GENERAL 0x0 38#define TEGRA_APBDMA_GENERAL 0x0
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index 656b2e3334a6..56813f967c8f 100644
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -12,8 +12,7 @@
12#include <linux/module.h> 12#include <linux/module.h>
13#include <linux/of.h> 13#include <linux/of.h>
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15 15#include <linux/clk/tegra.h>
16#include <mach/clk.h>
17 16
18#include "drm.h" 17#include "drm.h"
19#include "dc.h" 18#include "dc.h"
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index 3a503c9e4686..d980dc75788c 100644
--- a/drivers/gpu/drm/tegra/drm.c
+++ b/drivers/gpu/drm/tegra/drm.c
@@ -11,7 +11,6 @@
11#include <linux/of_address.h> 11#include <linux/of_address.h>
12#include <linux/of_platform.h> 12#include <linux/of_platform.h>
13 13
14#include <mach/clk.h>
15#include <linux/dma-mapping.h> 14#include <linux/dma-mapping.h>
16#include <asm/dma-iommu.h> 15#include <asm/dma-iommu.h>
17 16
diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c
index e060c7e6434d..92ad276cc5e0 100644
--- a/drivers/gpu/drm/tegra/hdmi.c
+++ b/drivers/gpu/drm/tegra/hdmi.c
@@ -14,8 +14,7 @@
14#include <linux/of.h> 14#include <linux/of.h>
15#include <linux/platform_device.h> 15#include <linux/platform_device.h>
16#include <linux/regulator/consumer.h> 16#include <linux/regulator/consumer.h>
17 17#include <linux/clk/tegra.h>
18#include <mach/clk.h>
19 18
20#include "hdmi.h" 19#include "hdmi.h"
21#include "drm.h" 20#include "drm.h"
diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index 7b38877ffec1..c7aca35e38fd 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -29,11 +29,10 @@
29#include <linux/of_i2c.h> 29#include <linux/of_i2c.h>
30#include <linux/of_device.h> 30#include <linux/of_device.h>
31#include <linux/module.h> 31#include <linux/module.h>
32#include <linux/clk/tegra.h>
32 33
33#include <asm/unaligned.h> 34#include <asm/unaligned.h>
34 35
35#include <mach/clk.h>
36
37#define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000)) 36#define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
38#define BYTES_PER_FIFO_WORD 4 37#define BYTES_PER_FIFO_WORD 4
39 38
diff --git a/drivers/input/keyboard/tegra-kbc.c b/drivers/input/keyboard/tegra-kbc.c
index c76f96872d31..54ac1dc7d477 100644
--- a/drivers/input/keyboard/tegra-kbc.c
+++ b/drivers/input/keyboard/tegra-kbc.c
@@ -30,7 +30,7 @@
30#include <linux/clk.h> 30#include <linux/clk.h>
31#include <linux/slab.h> 31#include <linux/slab.h>
32#include <linux/input/tegra_kbc.h> 32#include <linux/input/tegra_kbc.h>
33#include <mach/clk.h> 33#include <linux/clk/tegra.h>
34 34
35#define KBC_MAX_DEBOUNCE_CNT 0x3ffu 35#define KBC_MAX_DEBOUNCE_CNT 0x3ffu
36 36
diff --git a/drivers/spi/spi-tegra20-sflash.c b/drivers/spi/spi-tegra20-sflash.c
index 448a8cc71df3..e5dce91b74ca 100644
--- a/drivers/spi/spi-tegra20-sflash.c
+++ b/drivers/spi/spi-tegra20-sflash.c
@@ -34,7 +34,7 @@
34#include <linux/of_device.h> 34#include <linux/of_device.h>
35#include <linux/spi/spi.h> 35#include <linux/spi/spi.h>
36#include <linux/spi/spi-tegra.h> 36#include <linux/spi/spi-tegra.h>
37#include <mach/clk.h> 37#include <linux/clk/tegra.h>
38 38
39#define SPI_COMMAND 0x000 39#define SPI_COMMAND 0x000
40#define SPI_GO BIT(30) 40#define SPI_GO BIT(30)
@@ -525,7 +525,7 @@ static int tegra_sflash_probe(struct platform_device *pdev)
525 goto exit_free_master; 525 goto exit_free_master;
526 } 526 }
527 527
528 tsd->clk = devm_clk_get(&pdev->dev, "spi"); 528 tsd->clk = devm_clk_get(&pdev->dev, NULL);
529 if (IS_ERR(tsd->clk)) { 529 if (IS_ERR(tsd->clk)) {
530 dev_err(&pdev->dev, "can not get clock\n"); 530 dev_err(&pdev->dev, "can not get clock\n");
531 ret = PTR_ERR(tsd->clk); 531 ret = PTR_ERR(tsd->clk);
diff --git a/drivers/spi/spi-tegra20-slink.c b/drivers/spi/spi-tegra20-slink.c
index 651167f2e0af..e255e7a35678 100644
--- a/drivers/spi/spi-tegra20-slink.c
+++ b/drivers/spi/spi-tegra20-slink.c
@@ -35,7 +35,7 @@
35#include <linux/of_device.h> 35#include <linux/of_device.h>
36#include <linux/spi/spi.h> 36#include <linux/spi/spi.h>
37#include <linux/spi/spi-tegra.h> 37#include <linux/spi/spi-tegra.h>
38#include <mach/clk.h> 38#include <linux/clk/tegra.h>
39 39
40#define SLINK_COMMAND 0x000 40#define SLINK_COMMAND 0x000
41#define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0) 41#define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0)
@@ -1191,7 +1191,7 @@ static int tegra_slink_probe(struct platform_device *pdev)
1191 goto exit_free_master; 1191 goto exit_free_master;
1192 } 1192 }
1193 1193
1194 tspi->clk = devm_clk_get(&pdev->dev, "slink"); 1194 tspi->clk = devm_clk_get(&pdev->dev, NULL);
1195 if (IS_ERR(tspi->clk)) { 1195 if (IS_ERR(tspi->clk)) {
1196 dev_err(&pdev->dev, "can not get clock\n"); 1196 dev_err(&pdev->dev, "can not get clock\n");
1197 ret = PTR_ERR(tspi->clk); 1197 ret = PTR_ERR(tspi->clk);
diff --git a/drivers/staging/nvec/TODO b/drivers/staging/nvec/TODO
index f950ab890e2e..e5ae42a0b44a 100644
--- a/drivers/staging/nvec/TODO
+++ b/drivers/staging/nvec/TODO
@@ -1,9 +1,5 @@
1ToDo list (incomplete, unordered) 1ToDo list (incomplete, unordered)
2 - add compile as module support 2 - add compile as module support
3 - fix clk usage
4 should not be using clk_get_sys(), but clk_get(&pdev->dev, conn)
5 where conn is either NULL if the device only has one clock, or
6 the device specific name if it has multiple clocks.
7 - move half of the nvec init stuff to i2c-tegra.c 3 - move half of the nvec init stuff to i2c-tegra.c
8 - move event handling to nvec_events 4 - move event handling to nvec_events
9 - finish suspend/resume support 5 - finish suspend/resume support
diff --git a/drivers/staging/nvec/nvec.c b/drivers/staging/nvec/nvec.c
index 2830946860d1..9417941974f7 100644
--- a/drivers/staging/nvec/nvec.c
+++ b/drivers/staging/nvec/nvec.c
@@ -37,8 +37,7 @@
37#include <linux/slab.h> 37#include <linux/slab.h>
38#include <linux/spinlock.h> 38#include <linux/spinlock.h>
39#include <linux/workqueue.h> 39#include <linux/workqueue.h>
40 40#include <linux/clk/tegra.h>
41#include <mach/clk.h>
42 41
43#include "nvec.h" 42#include "nvec.h"
44 43
@@ -771,7 +770,7 @@ static int tegra_nvec_probe(struct platform_device *pdev)
771 return -ENODEV; 770 return -ENODEV;
772 } 771 }
773 772
774 i2c_clk = clk_get_sys("tegra-i2c.2", "div-clk"); 773 i2c_clk = clk_get(&pdev->dev, "div-clk");
775 if (IS_ERR(i2c_clk)) { 774 if (IS_ERR(i2c_clk)) {
776 dev_err(nvec->dev, "failed to get controller clock\n"); 775 dev_err(nvec->dev, "failed to get controller clock\n");
777 return -ENODEV; 776 return -ENODEV;
diff --git a/arch/arm/mach-tegra/tegra_cpu_car.h b/include/linux/clk/tegra.h
index 9764d31032b7..404d6f940872 100644
--- a/arch/arm/mach-tegra/tegra_cpu_car.h
+++ b/include/linux/clk/tegra.h
@@ -14,8 +14,10 @@
14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */ 15 */
16 16
17#ifndef __MACH_TEGRA_CPU_CAR_H 17#ifndef __LINUX_CLK_TEGRA_H_
18#define __MACH_TEGRA_CPU_CAR_H 18#define __LINUX_CLK_TEGRA_H_
19
20#include <linux/clk.h>
19 21
20/* 22/*
21 * Tegra CPU clock and reset control ops 23 * Tegra CPU clock and reset control ops
@@ -118,7 +120,8 @@ static inline void tegra_cpu_clock_resume(void)
118} 120}
119#endif 121#endif
120 122
121void tegra20_cpu_car_ops_init(void); 123void tegra_periph_reset_deassert(struct clk *c);
122void tegra30_cpu_car_ops_init(void); 124void tegra_periph_reset_assert(struct clk *c);
125void tegra_clocks_init(void);
123 126
124#endif /* __MACH_TEGRA_CPU_CAR_H */ 127#endif /* __LINUX_CLK_TEGRA_H_ */
diff --git a/include/linux/tegra-soc.h b/include/linux/tegra-soc.h
new file mode 100644
index 000000000000..95f611d78f3a
--- /dev/null
+++ b/include/linux/tegra-soc.h
@@ -0,0 +1,22 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef __LINUX_TEGRA_SOC_H_
18#define __LINUX_TEGRA_SOC_H_
19
20u32 tegra_read_chipid(void);
21
22#endif /* __LINUX_TEGRA_SOC_H_ */
diff --git a/sound/soc/tegra/tegra30_ahub.c b/sound/soc/tegra/tegra30_ahub.c
index f354dc390a0b..2355630367f7 100644
--- a/sound/soc/tegra/tegra30_ahub.c
+++ b/sound/soc/tegra/tegra30_ahub.c
@@ -25,7 +25,7 @@
25#include <linux/pm_runtime.h> 25#include <linux/pm_runtime.h>
26#include <linux/regmap.h> 26#include <linux/regmap.h>
27#include <linux/slab.h> 27#include <linux/slab.h>
28#include <mach/clk.h> 28#include <linux/clk/tegra.h>
29#include <sound/soc.h> 29#include <sound/soc.h>
30#include "tegra30_ahub.h" 30#include "tegra30_ahub.h"
31 31
@@ -299,15 +299,6 @@ static const char * const configlink_clocks[] = {
299 "spdif_in", 299 "spdif_in",
300}; 300};
301 301
302struct of_dev_auxdata ahub_auxdata[] = {
303 OF_DEV_AUXDATA("nvidia,tegra30-i2s", 0x70080300, "tegra30-i2s.0", NULL),
304 OF_DEV_AUXDATA("nvidia,tegra30-i2s", 0x70080400, "tegra30-i2s.1", NULL),
305 OF_DEV_AUXDATA("nvidia,tegra30-i2s", 0x70080500, "tegra30-i2s.2", NULL),
306 OF_DEV_AUXDATA("nvidia,tegra30-i2s", 0x70080600, "tegra30-i2s.3", NULL),
307 OF_DEV_AUXDATA("nvidia,tegra30-i2s", 0x70080700, "tegra30-i2s.4", NULL),
308 {}
309};
310
311#define LAST_REG(name) \ 302#define LAST_REG(name) \
312 (TEGRA30_AHUB_##name + \ 303 (TEGRA30_AHUB_##name + \
313 (TEGRA30_AHUB_##name##_STRIDE * TEGRA30_AHUB_##name##_COUNT) - 4) 304 (TEGRA30_AHUB_##name##_STRIDE * TEGRA30_AHUB_##name##_COUNT) - 4)
@@ -451,7 +442,7 @@ static int tegra30_ahub_probe(struct platform_device *pdev)
451 * Ensure that here. 442 * Ensure that here.
452 */ 443 */
453 for (i = 0; i < ARRAY_SIZE(configlink_clocks); i++) { 444 for (i = 0; i < ARRAY_SIZE(configlink_clocks); i++) {
454 clk = clk_get_sys(NULL, configlink_clocks[i]); 445 clk = clk_get(&pdev->dev, configlink_clocks[i]);
455 if (IS_ERR(clk)) { 446 if (IS_ERR(clk)) {
456 dev_err(&pdev->dev, "Can't get clock %s\n", 447 dev_err(&pdev->dev, "Can't get clock %s\n",
457 configlink_clocks[i]); 448 configlink_clocks[i]);
@@ -569,8 +560,7 @@ static int tegra30_ahub_probe(struct platform_device *pdev)
569 goto err_pm_disable; 560 goto err_pm_disable;
570 } 561 }
571 562
572 of_platform_populate(pdev->dev.of_node, NULL, ahub_auxdata, 563 of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
573 &pdev->dev);
574 564
575 return 0; 565 return 0;
576 566
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-01 19:06:45 -0400