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path: root/drivers/char/agp/intel-gtt.c
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Diffstat (limited to 'drivers/char/agp/intel-gtt.c')
-rw-r--r--drivers/char/agp/intel-gtt.c63
1 files changed, 27 insertions, 36 deletions
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 75e0a3497888..6ea3bf6e5b1a 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -534,7 +534,7 @@ static void intel_i830_init_gtt_entries(void)
534 534
535 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); 535 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
536 536
537 if (IS_I965) { 537 if (IS_G33 || IS_I965) {
538 u32 pgetbl_ctl; 538 u32 pgetbl_ctl;
539 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); 539 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
540 540
@@ -567,22 +567,6 @@ static void intel_i830_init_gtt_entries(void)
567 size = 512; 567 size = 512;
568 } 568 }
569 size += 4; /* add in BIOS popup space */ 569 size += 4; /* add in BIOS popup space */
570 } else if (IS_G33 && !IS_PINEVIEW) {
571 /* G33's GTT size defined in gmch_ctrl */
572 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
573 case G33_PGETBL_SIZE_1M:
574 size = 1024;
575 break;
576 case G33_PGETBL_SIZE_2M:
577 size = 2048;
578 break;
579 default:
580 dev_info(&agp_bridge->dev->dev,
581 "unknown page table size 0x%x, assuming 512KB\n",
582 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
583 size = 512;
584 }
585 size += 4;
586 } else if (IS_G4X || IS_PINEVIEW) { 570 } else if (IS_G4X || IS_PINEVIEW) {
587 /* On 4 series hardware, GTT stolen is separate from graphics 571 /* On 4 series hardware, GTT stolen is separate from graphics
588 * stolen, ignore it in stolen gtt entries counting. However, 572 * stolen, ignore it in stolen gtt entries counting. However,
@@ -1257,24 +1241,31 @@ static int intel_i915_get_gtt_size(void)
1257 int size; 1241 int size;
1258 1242
1259 if (IS_G33) { 1243 if (IS_G33) {
1260 u16 gmch_ctrl; 1244 u32 pgetbl_ctl;
1245 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
1261 1246
1262 /* G33's GTT size defined in gmch_ctrl */ 1247 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
1263 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); 1248 case I965_PGETBL_SIZE_128KB:
1264 switch (gmch_ctrl & I830_GMCH_GMS_MASK) { 1249 size = 128;
1265 case I830_GMCH_GMS_STOLEN_512: 1250 break;
1251 case I965_PGETBL_SIZE_256KB:
1252 size = 256;
1253 break;
1254 case I965_PGETBL_SIZE_512KB:
1266 size = 512; 1255 size = 512;
1267 break; 1256 break;
1268 case I830_GMCH_GMS_STOLEN_1024: 1257 case I965_PGETBL_SIZE_1MB:
1269 size = 1024; 1258 size = 1024;
1270 break; 1259 break;
1271 case I830_GMCH_GMS_STOLEN_8192: 1260 case I965_PGETBL_SIZE_2MB:
1272 size = 8*1024; 1261 size = 2048;
1262 break;
1263 case I965_PGETBL_SIZE_1_5MB:
1264 size = 1024 + 512;
1273 break; 1265 break;
1274 default: 1266 default:
1275 dev_info(&agp_bridge->dev->dev, 1267 dev_info(&intel_private.pcidev->dev,
1276 "unknown page table size 0x%x, assuming 512KB\n", 1268 "unknown page table size, assuming 512KB\n");
1277 (gmch_ctrl & I830_GMCH_GMS_MASK));
1278 size = 512; 1269 size = 512;
1279 } 1270 }
1280 } else { 1271 } else {
@@ -1306,14 +1297,6 @@ static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1306 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); 1297 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1307 pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2); 1298 pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2);
1308 1299
1309 gtt_map_size = intel_i915_get_gtt_size();
1310
1311 intel_private.gtt = ioremap(temp2, gtt_map_size);
1312 if (!intel_private.gtt)
1313 return -ENOMEM;
1314
1315 intel_private.gtt_total_size = gtt_map_size / 4;
1316
1317 temp &= 0xfff80000; 1300 temp &= 0xfff80000;
1318 1301
1319 intel_private.registers = ioremap(temp, 128 * 4096); 1302 intel_private.registers = ioremap(temp, 128 * 4096);
@@ -1322,6 +1305,14 @@ static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1322 return -ENOMEM; 1305 return -ENOMEM;
1323 } 1306 }
1324 1307
1308 gtt_map_size = intel_i915_get_gtt_size();
1309
1310 intel_private.gtt = ioremap(temp2, gtt_map_size);
1311 if (!intel_private.gtt)
1312 return -ENOMEM;
1313
1314 intel_private.gtt_total_size = gtt_map_size / 4;
1315
1325 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 1316 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1326 global_cache_flush(); /* FIXME: ? */ 1317 global_cache_flush(); /* FIXME: ? */
1327 1318