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Diffstat (limited to 'drivers/ata/pata_cmd64x.c')
-rw-r--r--drivers/ata/pata_cmd64x.c38
1 files changed, 16 insertions, 22 deletions
diff --git a/drivers/ata/pata_cmd64x.c b/drivers/ata/pata_cmd64x.c
index f98dffedf4bc..4c81a71b8877 100644
--- a/drivers/ata/pata_cmd64x.c
+++ b/drivers/ata/pata_cmd64x.c
@@ -2,6 +2,7 @@
2 * pata_cmd64x.c - CMD64x PATA for new ATA layer 2 * pata_cmd64x.c - CMD64x PATA for new ATA layer
3 * (C) 2005 Red Hat Inc 3 * (C) 2005 Red Hat Inc
4 * Alan Cox <alan@lxorguk.ukuu.org.uk> 4 * Alan Cox <alan@lxorguk.ukuu.org.uk>
5 * (C) 2009-2010 Bartlomiej Zolnierkiewicz
5 * 6 *
6 * Based upon 7 * Based upon
7 * linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002 8 * linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002
@@ -39,11 +40,7 @@
39 40
40enum { 41enum {
41 CFR = 0x50, 42 CFR = 0x50,
42 CFR_INTR_CH0 = 0x02, 43 CFR_INTR_CH0 = 0x04,
43 CNTRL = 0x51,
44 CNTRL_DIS_RA0 = 0x40,
45 CNTRL_DIS_RA1 = 0x80,
46 CNTRL_ENA_2ND = 0x08,
47 CMDTIM = 0x52, 44 CMDTIM = 0x52,
48 ARTTIM0 = 0x53, 45 ARTTIM0 = 0x53,
49 DRWTIM0 = 0x54, 46 DRWTIM0 = 0x54,
@@ -53,9 +50,6 @@ enum {
53 ARTTIM23_DIS_RA2 = 0x04, 50 ARTTIM23_DIS_RA2 = 0x04,
54 ARTTIM23_DIS_RA3 = 0x08, 51 ARTTIM23_DIS_RA3 = 0x08,
55 ARTTIM23_INTR_CH1 = 0x10, 52 ARTTIM23_INTR_CH1 = 0x10,
56 ARTTIM2 = 0x57,
57 ARTTIM3 = 0x57,
58 DRWTIM23 = 0x58,
59 DRWTIM2 = 0x58, 53 DRWTIM2 = 0x58,
60 BRST = 0x59, 54 BRST = 0x59,
61 DRWTIM3 = 0x5b, 55 DRWTIM3 = 0x5b,
@@ -63,14 +57,11 @@ enum {
63 MRDMODE = 0x71, 57 MRDMODE = 0x71,
64 MRDMODE_INTR_CH0 = 0x04, 58 MRDMODE_INTR_CH0 = 0x04,
65 MRDMODE_INTR_CH1 = 0x08, 59 MRDMODE_INTR_CH1 = 0x08,
66 MRDMODE_BLK_CH0 = 0x10,
67 MRDMODE_BLK_CH1 = 0x20,
68 BMIDESR0 = 0x72, 60 BMIDESR0 = 0x72,
69 UDIDETCR0 = 0x73, 61 UDIDETCR0 = 0x73,
70 DTPR0 = 0x74, 62 DTPR0 = 0x74,
71 BMIDECR1 = 0x78, 63 BMIDECR1 = 0x78,
72 BMIDECSR = 0x79, 64 BMIDECSR = 0x79,
73 BMIDESR1 = 0x7A,
74 UDIDETCR1 = 0x7B, 65 UDIDETCR1 = 0x7B,
75 DTPR1 = 0x7C 66 DTPR1 = 0x7C
76}; 67};
@@ -130,8 +121,14 @@ static void cmd64x_set_timing(struct ata_port *ap, struct ata_device *adev, u8 m
130 121
131 if (pair) { 122 if (pair) {
132 struct ata_timing tp; 123 struct ata_timing tp;
124
133 ata_timing_compute(pair, pair->pio_mode, &tp, T, 0); 125 ata_timing_compute(pair, pair->pio_mode, &tp, T, 0);
134 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); 126 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
127 if (pair->dma_mode) {
128 ata_timing_compute(pair, pair->dma_mode,
129 &tp, T, 0);
130 ata_timing_merge(&tp, &t, &t, ATA_TIMING_SETUP);
131 }
135 } 132 }
136 } 133 }
137 134
@@ -147,7 +144,9 @@ static void cmd64x_set_timing(struct ata_port *ap, struct ata_device *adev, u8 m
147 /* Now convert the clocks into values we can actually stuff into 144 /* Now convert the clocks into values we can actually stuff into
148 the chip */ 145 the chip */
149 146
150 if (t.recover > 1) 147 if (t.recover == 16)
148 t.recover = 0;
149 else if (t.recover > 1)
151 t.recover--; 150 t.recover--;
152 else 151 else
153 t.recover = 15; 152 t.recover = 15;
@@ -219,7 +218,7 @@ static void cmd64x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
219 regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift; 218 regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift;
220 /* Merge the control bits */ 219 /* Merge the control bits */
221 regU |= 1 << adev->devno; /* UDMA on */ 220 regU |= 1 << adev->devno; /* UDMA on */
222 if (adev->dma_mode > 2) /* 15nS timing */ 221 if (adev->dma_mode > XFER_UDMA_2) /* 15nS timing */
223 regU |= 4 << adev->devno; 222 regU |= 4 << adev->devno;
224 } else { 223 } else {
225 regU &= ~ (1 << adev->devno); /* UDMA off */ 224 regU &= ~ (1 << adev->devno); /* UDMA off */
@@ -245,7 +244,7 @@ static void cmd648_bmdma_stop(struct ata_queued_cmd *qc)
245 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 244 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
246 u8 dma_intr; 245 u8 dma_intr;
247 int dma_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0; 246 int dma_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0;
248 int dma_reg = ap->port_no ? ARTTIM2 : CFR; 247 int dma_reg = ap->port_no ? ARTTIM23 : CFR;
249 248
250 ata_bmdma_stop(qc); 249 ata_bmdma_stop(qc);
251 250
@@ -294,8 +293,6 @@ static struct ata_port_operations cmd648_port_ops = {
294 293
295static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 294static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
296{ 295{
297 u32 class_rev;
298
299 static const struct ata_port_info cmd_info[6] = { 296 static const struct ata_port_info cmd_info[6] = {
300 { /* CMD 643 - no UDMA */ 297 { /* CMD 643 - no UDMA */
301 .flags = ATA_FLAG_SLAVE_POSS, 298 .flags = ATA_FLAG_SLAVE_POSS,
@@ -345,18 +342,15 @@ static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
345 if (rc) 342 if (rc)
346 return rc; 343 return rc;
347 344
348 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
349 class_rev &= 0xFF;
350
351 if (id->driver_data == 0) /* 643 */ 345 if (id->driver_data == 0) /* 643 */
352 ata_pci_bmdma_clear_simplex(pdev); 346 ata_pci_bmdma_clear_simplex(pdev);
353 347
354 if (pdev->device == PCI_DEVICE_ID_CMD_646) { 348 if (pdev->device == PCI_DEVICE_ID_CMD_646) {
355 /* Does UDMA work ? */ 349 /* Does UDMA work ? */
356 if (class_rev > 4) 350 if (pdev->revision > 4)
357 ppi[0] = &cmd_info[2]; 351 ppi[0] = &cmd_info[2];
358 /* Early rev with other problems ? */ 352 /* Early rev with other problems ? */
359 else if (class_rev == 1) 353 else if (pdev->revision == 1)
360 ppi[0] = &cmd_info[3]; 354 ppi[0] = &cmd_info[3];
361 } 355 }
362 356
@@ -373,7 +367,7 @@ static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
373 pci_write_config_byte(pdev, UDIDETCR0, 0xF0); 367 pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
374#endif 368#endif
375 369
376 return ata_pci_sff_init_one(pdev, ppi, &cmd64x_sht, NULL); 370 return ata_pci_sff_init_one(pdev, ppi, &cmd64x_sht, NULL, 0);
377} 371}
378 372
379#ifdef CONFIG_PM 373#ifdef CONFIG_PM