1 files changed, 316 insertions, 39 deletions

diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index a3241a1a710b..5326af28a410 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -42,6 +42,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/device.h>
 #include <linux/dmi.h>
+#include <linux/gfp.h>
 #include <scsi/scsi_host.h>
 #include <scsi/scsi_cmnd.h>
 #include <linux/libata.h>
@@ -93,6 +94,9 @@ enum {
         AHCI_CMD_TBL_AR_SZ      = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
         AHCI_PORT_PRIV_DMA_SZ   = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
                                   AHCI_RX_FIS_SZ,
+        AHCI_PORT_PRIV_FBS_DMA_SZ       = AHCI_CMD_SLOT_SZ +
+                                          AHCI_CMD_TBL_AR_SZ +
+                                          (AHCI_RX_FIS_SZ * 16),
         AHCI_IRQ_ON_SG          = (1 << 31),
         AHCI_CMD_ATAPI          = (1 << 5),
         AHCI_CMD_WRITE          = (1 << 6),
@@ -113,6 +117,7 @@ enum {
         board_ahci_mcp65        = 6,
         board_ahci_nopmp        = 7,
         board_ahci_yesncq       = 8,
+        board_ahci_nosntf       = 9,
 
         /* global controller registers */
         HOST_CAP                = 0x00, /* host capabilities */
@@ -169,6 +174,7 @@ enum {
         PORT_SCR_ERR            = 0x30, /* SATA phy register: SError */
         PORT_SCR_ACT            = 0x34, /* SATA phy register: SActive */
         PORT_SCR_NTF            = 0x3c, /* SATA phy register: SNotification */
+        PORT_FBS                = 0x40, /* FIS-based Switching */
 
         /* PORT_IRQ_{STAT,MASK} bits */
         PORT_IRQ_COLD_PRES      = (1 << 31), /* cold presence detect */
@@ -207,6 +213,7 @@ enum {
         PORT_CMD_ASP            = (1 << 27), /* Aggressive Slumber/Partial */
         PORT_CMD_ALPE           = (1 << 26), /* Aggressive Link PM enable */
         PORT_CMD_ATAPI          = (1 << 24), /* Device is ATAPI */
+        PORT_CMD_FBSCP          = (1 << 22), /* FBS Capable Port */
         PORT_CMD_PMP            = (1 << 17), /* PMP attached */
         PORT_CMD_LIST_ON        = (1 << 15), /* cmd list DMA engine running */
         PORT_CMD_FIS_ON         = (1 << 14), /* FIS DMA engine running */
@@ -221,6 +228,14 @@ enum {
         PORT_CMD_ICC_PARTIAL    = (0x2 << 28), /* Put i/f in partial state */
         PORT_CMD_ICC_SLUMBER    = (0x6 << 28), /* Put i/f in slumber state */
 
+        PORT_FBS_DWE_OFFSET     = 16, /* FBS device with error offset */
+        PORT_FBS_ADO_OFFSET     = 12, /* FBS active dev optimization offset */
+        PORT_FBS_DEV_OFFSET     = 8,  /* FBS device to issue offset */
+        PORT_FBS_DEV_MASK       = (0xf << PORT_FBS_DEV_OFFSET),  /* FBS.DEV */
+        PORT_FBS_SDE            = (1 << 2), /* FBS single device error */
+        PORT_FBS_DEC            = (1 << 1), /* FBS device error clear */
+        PORT_FBS_EN             = (1 << 0), /* Enable FBS */
+
         /* hpriv->flags bits */
         AHCI_HFLAG_NO_NCQ               = (1 << 0),
         AHCI_HFLAG_IGN_IRQ_IF_ERR       = (1 << 1), /* ignore IRQ_IF_ERR */
@@ -235,6 +250,7 @@ enum {
         AHCI_HFLAG_NO_SUSPEND           = (1 << 10), /* don't suspend */
         AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as
                                                         link offline */
+        AHCI_HFLAG_NO_SNTF              = (1 << 12), /* no sntf */
 
         /* ap->flags bits */
 
@@ -302,6 +318,9 @@ struct ahci_port_priv {
         unsigned int            ncq_saw_dmas:1;
         unsigned int            ncq_saw_sdb:1;
         u32                     intr_mask;      /* interrupts to enable */
+        bool                    fbs_supported;  /* set iff FBS is supported */
+        bool                    fbs_enabled;    /* set iff FBS is enabled */
+        int                     fbs_last_dev;   /* save FBS.DEV of last FIS */
         /* enclosure management info per PM slot */
         struct ahci_em_priv     em_priv[EM_MAX_SLOTS];
 };
@@ -313,9 +332,12 @@ static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
 static int ahci_port_start(struct ata_port *ap);
 static void ahci_port_stop(struct ata_port *ap);
+static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
 static void ahci_qc_prep(struct ata_queued_cmd *qc);
 static void ahci_freeze(struct ata_port *ap);
 static void ahci_thaw(struct ata_port *ap);
+static void ahci_enable_fbs(struct ata_port *ap);
+static void ahci_disable_fbs(struct ata_port *ap);
 static void ahci_pmp_attach(struct ata_port *ap);
 static void ahci_pmp_detach(struct ata_port *ap);
 static int ahci_softreset(struct ata_link *link, unsigned int *class,
@@ -354,10 +376,10 @@ static ssize_t ahci_show_host_version(struct device *dev,
 static ssize_t ahci_show_port_cmd(struct device *dev,
                                   struct device_attribute *attr, char *buf);
 
-DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
-DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
-DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
-DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
+static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
+static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
+static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
+static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
 
 static struct device_attribute *ahci_shost_attrs[] = {
         &dev_attr_link_power_management_policy,
@@ -388,7 +410,7 @@ static struct scsi_host_template ahci_sht = {
 static struct ata_port_operations ahci_ops = {
         .inherits               = &sata_pmp_port_ops,
 
-        .qc_defer               = sata_pmp_qc_defer_cmd_switch,
+        .qc_defer               = ahci_pmp_qc_defer,
         .qc_prep                = ahci_qc_prep,
         .qc_issue               = ahci_qc_issue,
         .qc_fill_rtf            = ahci_qc_fill_rtf,
@@ -508,7 +530,7 @@ static const struct ata_port_info ahci_port_info[] = {
                 .udma_mask      = ATA_UDMA6,
                 .port_ops       = &ahci_ops,
         },
-        /* board_ahci_yesncq */
+        [board_ahci_yesncq] =
         {
                 AHCI_HFLAGS     (AHCI_HFLAG_YES_NCQ),
                 .flags          = AHCI_FLAG_COMMON,
@@ -516,6 +538,14 @@ static const struct ata_port_info ahci_port_info[] = {
                 .udma_mask      = ATA_UDMA6,
                 .port_ops       = &ahci_ops,
         },
+        [board_ahci_nosntf] =
+        {
+                AHCI_HFLAGS     (AHCI_HFLAG_NO_SNTF),
+                .flags          = AHCI_FLAG_COMMON,
+                .pio_mask       = ATA_PIO4,
+                .udma_mask      = ATA_UDMA6,
+                .port_ops       = &ahci_ops,
+        },
 };
 
 static const struct pci_device_id ahci_pci_tbl[] = {
@@ -531,7 +561,7 @@ static const struct pci_device_id ahci_pci_tbl[] = {
         { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
         { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
         { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
-        { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
+        { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
         { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
         { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
         { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
@@ -560,6 +590,12 @@ static const struct pci_device_id ahci_pci_tbl[] = {
         { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
         { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
         { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
+        { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
+        { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
+        { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
+        { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
+        { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
+        { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
 
         /* JMicron 360/1/3/5/6, match class to avoid IDE function */
         { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
@@ -606,6 +642,21 @@ static const struct pci_device_id ahci_pci_tbl[] = {
         { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_yesncq },     /* MCP67 */
         { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_yesncq },     /* MCP67 */
         { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_yesncq },     /* Linux ID */
+        { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_yesncq },     /* Linux ID */
+        { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_yesncq },     /* Linux ID */
+        { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_yesncq },     /* Linux ID */
+        { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_yesncq },     /* Linux ID */
+        { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_yesncq },     /* Linux ID */
+        { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_yesncq },     /* Linux ID */
+        { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_yesncq },     /* Linux ID */
+        { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_yesncq },     /* Linux ID */
+        { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_yesncq },     /* Linux ID */
+        { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_yesncq },     /* Linux ID */
+        { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_yesncq },     /* Linux ID */
+        { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_yesncq },     /* Linux ID */
+        { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_yesncq },     /* Linux ID */
+        { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_yesncq },     /* Linux ID */
+        { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_yesncq },     /* Linux ID */
         { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_yesncq },     /* MCP73 */
         { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_yesncq },     /* MCP73 */
         { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_yesncq },     /* MCP73 */
@@ -849,6 +900,12 @@ static void ahci_save_initial_config(struct pci_dev *pdev,
                 cap &= ~HOST_CAP_PMP;
         }
 
+        if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
+                dev_printk(KERN_INFO, &pdev->dev,
+                           "controller can't do SNTF, turning off CAP_SNTF\n");
+                cap &= ~HOST_CAP_SNTF;
+        }
+
         if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 &&
             port_map != 1) {
                 dev_printk(KERN_INFO, &pdev->dev,
@@ -2029,6 +2086,17 @@ static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
         return si;
 }
 
+static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
+{
+        struct ata_port *ap = qc->ap;
+        struct ahci_port_priv *pp = ap->private_data;
+
+        if (!sata_pmp_attached(ap) || pp->fbs_enabled)
+                return ata_std_qc_defer(qc);
+        else
+                return sata_pmp_qc_defer_cmd_switch(qc);
+}
+
 static void ahci_qc_prep(struct ata_queued_cmd *qc)
 {
         struct ata_port *ap = qc->ap;
@@ -2067,6 +2135,31 @@ static void ahci_qc_prep(struct ata_queued_cmd *qc)
         ahci_fill_cmd_slot(pp, qc->tag, opts);
 }
 
+static void ahci_fbs_dec_intr(struct ata_port *ap)
+{
+        struct ahci_port_priv *pp = ap->private_data;
+        void __iomem *port_mmio = ahci_port_base(ap);
+        u32 fbs = readl(port_mmio + PORT_FBS);
+        int retries = 3;
+
+        DPRINTK("ENTER\n");
+        BUG_ON(!pp->fbs_enabled);
+
+        /* time to wait for DEC is not specified by AHCI spec,
+         * add a retry loop for safety.
+         */
+        writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
+        fbs = readl(port_mmio + PORT_FBS);
+        while ((fbs & PORT_FBS_DEC) && retries--) {
+                udelay(1);
+                fbs = readl(port_mmio + PORT_FBS);
+        }
+
+        if (fbs & PORT_FBS_DEC)
+                dev_printk(KERN_ERR, ap->host->dev,
+                           "failed to clear device error\n");
+}
+
 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
 {
         struct ahci_host_priv *hpriv = ap->host->private_data;
@@ -2075,12 +2168,26 @@ static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
         struct ata_link *link = NULL;
         struct ata_queued_cmd *active_qc;
         struct ata_eh_info *active_ehi;
+        bool fbs_need_dec = false;
         u32 serror;
 
-        /* determine active link */
-        ata_for_each_link(link, ap, EDGE)
-                if (ata_link_active(link))
-                        break;
+        /* determine active link with error */
+        if (pp->fbs_enabled) {
+                void __iomem *port_mmio = ahci_port_base(ap);
+                u32 fbs = readl(port_mmio + PORT_FBS);
+                int pmp = fbs >> PORT_FBS_DWE_OFFSET;
+
+                if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links) &&
+                    ata_link_online(&ap->pmp_link[pmp])) {
+                        link = &ap->pmp_link[pmp];
+                        fbs_need_dec = true;
+                }
+
+        } else
+                ata_for_each_link(link, ap, EDGE)
+                        if (ata_link_active(link))
+                                break;
+
         if (!link)
                 link = &ap->link;
 
@@ -2137,8 +2244,13 @@ static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
         }
 
         if (irq_stat & PORT_IRQ_IF_ERR) {
-                host_ehi->err_mask |= AC_ERR_ATA_BUS;
-                host_ehi->action |= ATA_EH_RESET;
+                if (fbs_need_dec)
+                        active_ehi->err_mask |= AC_ERR_DEV;
+                else {
+                        host_ehi->err_mask |= AC_ERR_ATA_BUS;
+                        host_ehi->action |= ATA_EH_RESET;
+                }
+
                 ata_ehi_push_desc(host_ehi, "interface fatal error");
         }
 
@@ -2153,7 +2265,10 @@ static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
 
         if (irq_stat & PORT_IRQ_FREEZE)
                 ata_port_freeze(ap);
-        else
+        else if (fbs_need_dec) {
+                ata_link_abort(link);
+                ahci_fbs_dec_intr(ap);
+        } else
                 ata_port_abort(ap);
 }
 
@@ -2164,7 +2279,7 @@ static void ahci_port_intr(struct ata_port *ap)
         struct ahci_port_priv *pp = ap->private_data;
         struct ahci_host_priv *hpriv = ap->host->private_data;
         int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
-        u32 status, qc_active;
+        u32 status, qc_active = 0;
         int rc;
 
         status = readl(port_mmio + PORT_IRQ_STAT);
@@ -2206,20 +2321,38 @@ static void ahci_port_intr(struct ata_port *ap)
                         /* If the 'N' bit in word 0 of the FIS is set,
                          * we just received asynchronous notification.
                          * Tell libata about it.
+                         *
+                         * Lack of SNotification should not appear in
+                         * ahci 1.2, so the workaround is unnecessary
+                         * when FBS is enabled.
                          */
-                        const __le32 *f = pp->rx_fis + RX_FIS_SDB;
-                        u32 f0 = le32_to_cpu(f[0]);
-
-                        if (f0 & (1 << 15))
-                                sata_async_notification(ap);
+                        if (pp->fbs_enabled)
+                                WARN_ON_ONCE(1);
+                        else {
+                                const __le32 *f = pp->rx_fis + RX_FIS_SDB;
+                                u32 f0 = le32_to_cpu(f[0]);
+                                if (f0 & (1 << 15))
+                                        sata_async_notification(ap);
+                        }
                 }
         }
 
-        /* pp->active_link is valid iff any command is in flight */
-        if (ap->qc_active && pp->active_link->sactive)
-                qc_active = readl(port_mmio + PORT_SCR_ACT);
-        else
-                qc_active = readl(port_mmio + PORT_CMD_ISSUE);
+        /* pp->active_link is not reliable once FBS is enabled, both
+         * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
+         * NCQ and non-NCQ commands may be in flight at the same time.
+         */
+        if (pp->fbs_enabled) {
+                if (ap->qc_active) {
+                        qc_active = readl(port_mmio + PORT_SCR_ACT);
+                        qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
+                }
+        } else {
+                /* pp->active_link is valid iff any command is in flight */
+                if (ap->qc_active && pp->active_link->sactive)
+                        qc_active = readl(port_mmio + PORT_SCR_ACT);
+                else
+                        qc_active = readl(port_mmio + PORT_CMD_ISSUE);
+        }
 
         rc = ata_qc_complete_multiple(ap, qc_active);
 
@@ -2305,6 +2438,15 @@ static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
 
         if (qc->tf.protocol == ATA_PROT_NCQ)
                 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
+
+        if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
+                u32 fbs = readl(port_mmio + PORT_FBS);
+                fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
+                fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
+                writel(fbs, port_mmio + PORT_FBS);
+                pp->fbs_last_dev = qc->dev->link->pmp;
+        }
+
         writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
 
         ahci_sw_activity(qc->dev->link);
@@ -2317,6 +2459,9 @@ static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
         struct ahci_port_priv *pp = qc->ap->private_data;
         u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
 
+        if (pp->fbs_enabled)
+                d2h_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
+
         ata_tf_from_fis(d2h_fis, &qc->result_tf);
         return true;
 }
@@ -2365,6 +2510,71 @@ static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
                 ahci_kick_engine(ap);
 }
 
+static void ahci_enable_fbs(struct ata_port *ap)
+{
+        struct ahci_port_priv *pp = ap->private_data;
+        void __iomem *port_mmio = ahci_port_base(ap);
+        u32 fbs;
+        int rc;
+
+        if (!pp->fbs_supported)
+                return;
+
+        fbs = readl(port_mmio + PORT_FBS);
+        if (fbs & PORT_FBS_EN) {
+                pp->fbs_enabled = true;
+                pp->fbs_last_dev = -1; /* initialization */
+                return;
+        }
+
+        rc = ahci_stop_engine(ap);
+        if (rc)
+                return;
+
+        writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
+        fbs = readl(port_mmio + PORT_FBS);
+        if (fbs & PORT_FBS_EN) {
+                dev_printk(KERN_INFO, ap->host->dev, "FBS is enabled.\n");
+                pp->fbs_enabled = true;
+                pp->fbs_last_dev = -1; /* initialization */
+        } else
+                dev_printk(KERN_ERR, ap->host->dev, "Failed to enable FBS\n");
+
+        ahci_start_engine(ap);
+}
+
+static void ahci_disable_fbs(struct ata_port *ap)
+{
+        struct ahci_port_priv *pp = ap->private_data;
+        void __iomem *port_mmio = ahci_port_base(ap);
+        u32 fbs;
+        int rc;
+
+        if (!pp->fbs_supported)
+                return;
+
+        fbs = readl(port_mmio + PORT_FBS);
+        if ((fbs & PORT_FBS_EN) == 0) {
+                pp->fbs_enabled = false;
+                return;
+        }
+
+        rc = ahci_stop_engine(ap);
+        if (rc)
+                return;
+
+        writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
+        fbs = readl(port_mmio + PORT_FBS);
+        if (fbs & PORT_FBS_EN)
+                dev_printk(KERN_ERR, ap->host->dev, "Failed to disable FBS\n");
+        else {
+                dev_printk(KERN_INFO, ap->host->dev, "FBS is disabled.\n");
+                pp->fbs_enabled = false;
+        }
+
+        ahci_start_engine(ap);
+}
+
 static void ahci_pmp_attach(struct ata_port *ap)
 {
         void __iomem *port_mmio = ahci_port_base(ap);
@@ -2375,6 +2585,8 @@ static void ahci_pmp_attach(struct ata_port *ap)
         cmd |= PORT_CMD_PMP;
         writel(cmd, port_mmio + PORT_CMD);
 
+        ahci_enable_fbs(ap);
+
         pp->intr_mask |= PORT_IRQ_BAD_PMP;
         writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
 }
@@ -2385,6 +2597,8 @@ static void ahci_pmp_detach(struct ata_port *ap)
         struct ahci_port_priv *pp = ap->private_data;
         u32 cmd;
 
+        ahci_disable_fbs(ap);
+
         cmd = readl(port_mmio + PORT_CMD);
         cmd &= ~PORT_CMD_PMP;
         writel(cmd, port_mmio + PORT_CMD);
@@ -2476,20 +2690,40 @@ static int ahci_pci_device_resume(struct pci_dev *pdev)
 
 static int ahci_port_start(struct ata_port *ap)
 {
+        struct ahci_host_priv *hpriv = ap->host->private_data;
         struct device *dev = ap->host->dev;
         struct ahci_port_priv *pp;
         void *mem;
         dma_addr_t mem_dma;
+        size_t dma_sz, rx_fis_sz;
 
         pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
         if (!pp)
                 return -ENOMEM;
 
-        mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
-                                  GFP_KERNEL);
+        /* check FBS capability */
+        if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
+                void __iomem *port_mmio = ahci_port_base(ap);
+                u32 cmd = readl(port_mmio + PORT_CMD);
+                if (cmd & PORT_CMD_FBSCP)
+                        pp->fbs_supported = true;
+                else
+                        dev_printk(KERN_WARNING, dev,
+                                   "The port is not capable of FBS\n");
+        }
+
+        if (pp->fbs_supported) {
+                dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
+                rx_fis_sz = AHCI_RX_FIS_SZ * 16;
+        } else {
+                dma_sz = AHCI_PORT_PRIV_DMA_SZ;
+                rx_fis_sz = AHCI_RX_FIS_SZ;
+        }
+
+        mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
         if (!mem)
                 return -ENOMEM;
-        memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
+        memset(mem, 0, dma_sz);
 
         /*
          * First item in chunk of DMA memory: 32-slot command table,
@@ -2507,8 +2741,8 @@ static int ahci_port_start(struct ata_port *ap)
         pp->rx_fis = mem;
         pp->rx_fis_dma = mem_dma;
 
-        mem += AHCI_RX_FIS_SZ;
-        mem_dma += AHCI_RX_FIS_SZ;
+        mem += rx_fis_sz;
+        mem_dma += rx_fis_sz;
 
         /*
          * Third item: data area for storing a single command
@@ -2815,6 +3049,14 @@ static bool ahci_broken_suspend(struct pci_dev *pdev)
                  * On HP dv[4-6] and HDX18 with earlier BIOSen, link
                  * to the harddisk doesn't become online after
                  * resuming from STR.  Warn and fail suspend.
+                 *
+                 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
+                 *
+                 * Use dates instead of versions to match as HP is
+                 * apparently recycling both product and version
+                 * strings.
+                 *
+                 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
                  */
                 {
                         .ident = "dv4",
@@ -2823,7 +3065,7 @@ static bool ahci_broken_suspend(struct pci_dev *pdev)
                                 DMI_MATCH(DMI_PRODUCT_NAME,
                                           "HP Pavilion dv4 Notebook PC"),
                         },
-                        .driver_data = "F.30", /* cutoff BIOS version */
+                        .driver_data = "20090105",      /* F.30 */
                 },
                 {
                         .ident = "dv5",
@@ -2832,7 +3074,7 @@ static bool ahci_broken_suspend(struct pci_dev *pdev)
                                 DMI_MATCH(DMI_PRODUCT_NAME,
                                           "HP Pavilion dv5 Notebook PC"),
                         },
-                        .driver_data = "F.16", /* cutoff BIOS version */
+                        .driver_data = "20090506",      /* F.16 */
                 },
                 {
                         .ident = "dv6",
@@ -2841,7 +3083,7 @@ static bool ahci_broken_suspend(struct pci_dev *pdev)
                                 DMI_MATCH(DMI_PRODUCT_NAME,
                                           "HP Pavilion dv6 Notebook PC"),
                         },
-                        .driver_data = "F.21",  /* cutoff BIOS version */
+                        .driver_data = "20090423",      /* F.21 */
                 },
                 {
                         .ident = "HDX18",
@@ -2850,19 +3092,38 @@ static bool ahci_broken_suspend(struct pci_dev *pdev)
                                 DMI_MATCH(DMI_PRODUCT_NAME,
                                           "HP HDX18 Notebook PC"),
                         },
-                        .driver_data = "F.23",  /* cutoff BIOS version */
+                        .driver_data = "20090430",      /* F.23 */
+                },
+                /*
+                 * Acer eMachines G725 has the same problem.  BIOS
+                 * V1.03 is known to be broken.  V3.04 is known to
+                 * work.  Inbetween, there are V1.06, V2.06 and V3.03
+                 * that we don't have much idea about.  For now,
+                 * blacklist anything older than V3.04.
+                 *
+                 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
+                 */
+                {
+                        .ident = "G725",
+                        .matches = {
+                                DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
+                                DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
+                        },
+                        .driver_data = "20091216",      /* V3.04 */
                 },
                 { }     /* terminate list */
         };
         const struct dmi_system_id *dmi = dmi_first_match(sysids);
-        const char *ver;
+        int year, month, date;
+        char buf[9];
 
         if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
                 return false;
 
-        ver = dmi_get_system_info(DMI_BIOS_VERSION);
+        dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
+        snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
 
-        return !ver || strcmp(ver, dmi->driver_data) < 0;
+        return strcmp(buf, dmi->driver_data) < 0;
 }
 
 static bool ahci_broken_online(struct pci_dev *pdev)
@@ -2988,6 +3249,14 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
         if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
                 return -ENODEV;
 
+        /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
+         * At the moment, we can only use the AHCI mode. Let the users know
+         * that for SAS drives they're out of luck.
+         */
+        if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
+                dev_printk(KERN_INFO, &pdev->dev, "PDC42819 "
+                           "can only drive SATA devices with this driver\n");
+
         /* acquire resources */
         rc = pcim_enable_device(pdev);
         if (rc)
@@ -3043,8 +3312,16 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
         ahci_save_initial_config(pdev, hpriv);
 
         /* prepare host */
-        if (hpriv->cap & HOST_CAP_NCQ)
-                pi.flags |= ATA_FLAG_NCQ | ATA_FLAG_FPDMA_AA;
+        if (hpriv->cap & HOST_CAP_NCQ) {
+                pi.flags |= ATA_FLAG_NCQ;
+                /* Auto-activate optimization is supposed to be supported on
+                   all AHCI controllers indicating NCQ support, but it seems
+                   to be broken at least on some NVIDIA MCP79 chipsets.
+                   Until we get info on which NVIDIA chipsets don't have this
+                   issue, if any, disable AA on all NVIDIA AHCIs. */
+                if (pdev->vendor != PCI_VENDOR_ID_NVIDIA)
+                        pi.flags |= ATA_FLAG_FPDMA_AA;
+        }
 
         if (hpriv->cap & HOST_CAP_PMP)
                 pi.flags |= ATA_FLAG_PMP;