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-rw-r--r--arch/arm/Kconfig2
-rw-r--r--arch/arm/boot/dts/Makefile44
-rw-r--r--arch/arm/boot/dts/at91sam9260.dtsi187
-rw-r--r--arch/arm/boot/dts/at91sam9263.dtsi173
-rw-r--r--arch/arm/boot/dts/at91sam9263ek.dts1
-rw-r--r--arch/arm/boot/dts/at91sam9g15.dtsi28
-rw-r--r--arch/arm/boot/dts/at91sam9g15ek.dts16
-rw-r--r--arch/arm/boot/dts/at91sam9g20ek_common.dtsi6
-rw-r--r--arch/arm/boot/dts/at91sam9g25.dtsi28
-rw-r--r--arch/arm/boot/dts/at91sam9g25ek.dts49
-rw-r--r--arch/arm/boot/dts/at91sam9g35.dtsi28
-rw-r--r--arch/arm/boot/dts/at91sam9g35ek.dts16
-rw-r--r--arch/arm/boot/dts/at91sam9g45.dtsi189
-rw-r--r--arch/arm/boot/dts/at91sam9m10g45ek.dts1
-rw-r--r--arch/arm/boot/dts/at91sam9n12.dtsi180
-rw-r--r--arch/arm/boot/dts/at91sam9x25.dtsi28
-rw-r--r--arch/arm/boot/dts/at91sam9x25ek.dts16
-rw-r--r--arch/arm/boot/dts/at91sam9x35.dtsi28
-rw-r--r--arch/arm/boot/dts/at91sam9x35ek.dts16
-rw-r--r--arch/arm/boot/dts/at91sam9x5.dtsi178
-rw-r--r--arch/arm/boot/dts/at91sam9x5ek.dtsi59
-rw-r--r--arch/arm/configs/at91_dt_defconfig1
-rw-r--r--arch/arm/mach-at91/at91rm9200.c4
-rw-r--r--arch/arm/mach-at91/at91sam9260.c7
-rw-r--r--arch/arm/mach-at91/at91sam9261.c4
-rw-r--r--arch/arm/mach-at91/at91sam9263.c9
-rw-r--r--arch/arm/mach-at91/at91sam9g45.c10
-rw-r--r--arch/arm/mach-at91/at91sam9n12.c15
-rw-r--r--arch/arm/mach-at91/at91sam9rl.c4
-rw-r--r--arch/arm/mach-at91/at91sam9x5.c19
-rw-r--r--arch/arm/mach-at91/board-dt.c2
-rw-r--r--arch/arm/mach-at91/gpio.c190
-rw-r--r--arch/arm/mach-at91/setup.c6
-rw-r--r--arch/arm/mach-at91/soc.h12
34 files changed, 1110 insertions, 446 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ade7e924bef5..a18cfefbee48 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -330,6 +330,8 @@ config ARCH_AT91
330 select IRQ_DOMAIN 330 select IRQ_DOMAIN
331 select NEED_MACH_GPIO_H 331 select NEED_MACH_GPIO_H
332 select NEED_MACH_IO_H if PCCARD 332 select NEED_MACH_IO_H if PCCARD
333 select PINCTRL
334 select PINCTRL_AT91 if USE_OF
333 help 335 help
334 This enables support for systems based on Atmel 336 This enables support for systems based on Atmel
335 AT91RM9200 and AT91SAM9* processors. 337 AT91RM9200 and AT91SAM9* processors.
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f37cf9fa5fa0..4ffed9ae7292 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1,21 +1,33 @@
1ifeq ($(CONFIG_OF),y) 1ifeq ($(CONFIG_OF),y)
2 2
3dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb \ 3# Keep at91 dtb files sorted alphabetically for each SoC
4 at91sam9263ek.dtb \ 4# sam9260
5 at91sam9g20ek_2mmc.dtb \ 5dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb
6 at91sam9g20ek.dtb \ 6dtb-$(CONFIG_ARCH_AT91) += ethernut5.dtb
7 at91sam9g25ek.dtb \ 7dtb-$(CONFIG_ARCH_AT91) += evk-pro3.dtb
8 at91sam9m10g45ek.dtb \ 8dtb-$(CONFIG_ARCH_AT91) += tny_a9260.dtb
9 at91sam9n12ek.dtb \ 9dtb-$(CONFIG_ARCH_AT91) += usb_a9260.dtb
10 ethernut5.dtb \ 10# sam9263
11 evk-pro3.dtb \ 11dtb-$(CONFIG_ARCH_AT91) += at91sam9263ek.dtb
12 kizbox.dtb \ 12dtb-$(CONFIG_ARCH_AT91) += tny_a9263.dtb
13 tny_a9260.dtb \ 13dtb-$(CONFIG_ARCH_AT91) += usb_a9263.dtb
14 tny_a9263.dtb \ 14# sam9g20
15 tny_a9g20.dtb \ 15dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek.dtb
16 usb_a9260.dtb \ 16dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek_2mmc.dtb
17 usb_a9263.dtb \ 17dtb-$(CONFIG_ARCH_AT91) += kizbox.dtb
18 usb_a9g20.dtb 18dtb-$(CONFIG_ARCH_AT91) += tny_a9g20.dtb
19dtb-$(CONFIG_ARCH_AT91) += usb_a9g20.dtb
20# sam9g45
21dtb-$(CONFIG_ARCH_AT91) += at91sam9m10g45ek.dtb
22# sam9n12
23dtb-$(CONFIG_ARCH_AT91) += at91sam9n12ek.dtb
24# sam9x5
25dtb-$(CONFIG_ARCH_AT91) += at91sam9g15ek.dtb
26dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb
27dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb
28dtb-$(CONFIG_ARCH_AT91) += at91sam9x25ek.dtb
29dtb-$(CONFIG_ARCH_AT91) += at91sam9x35ek.dtb
30
19dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb 31dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
20dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \ 32dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
21 dove-cubox.dtb \ 33 dove-cubox.dtb \
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index d410581a5a85..9a24ffbb7231 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -98,40 +98,161 @@
98 interrupts = <26 4 0 27 4 0 28 4 0>; 98 interrupts = <26 4 0 27 4 0 28 4 0>;
99 }; 99 };
100 100
101 pioA: gpio@fffff400 { 101 pinctrl@fffff400 {
102 compatible = "atmel,at91rm9200-gpio"; 102 #address-cells = <1>;
103 reg = <0xfffff400 0x100>; 103 #size-cells = <1>;
104 interrupts = <2 4 1>; 104 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
105 #gpio-cells = <2>; 105 ranges = <0xfffff400 0xfffff400 0x600>;
106 gpio-controller; 106
107 interrupt-controller; 107 atmel,mux-mask = <
108 #interrupt-cells = <2>; 108 /* A B */
109 }; 109 0xffffffff 0xffc00c3b /* pioA */
110 0xffffffff 0x7fff3ccf /* pioB */
111 0xffffffff 0x007fffff /* pioC */
112 >;
113
114 /* shared pinctrl settings */
115 dbgu {
116 pinctrl_dbgu: dbgu-0 {
117 atmel,pins =
118 <1 14 0x1 0x0 /* PB14 periph A */
119 1 15 0x1 0x1>; /* PB15 periph with pullup */
120 };
121 };
110 122
111 pioB: gpio@fffff600 { 123 uart0 {
112 compatible = "atmel,at91rm9200-gpio"; 124 pinctrl_uart0: uart0-0 {
113 reg = <0xfffff600 0x100>; 125 atmel,pins =
114 interrupts = <3 4 1>; 126 <1 4 0x1 0x0 /* PB4 periph A */
115 #gpio-cells = <2>; 127 1 5 0x1 0x0>; /* PB5 periph A */
116 gpio-controller; 128 };
117 interrupt-controller; 129
118 #interrupt-cells = <2>; 130 pinctrl_uart0_rts_cts: uart0_rts_cts-0 {
119 }; 131 atmel,pins =
132 <1 26 0x1 0x0 /* PB26 periph A */
133 1 27 0x1 0x0>; /* PB27 periph A */
134 };
135
136 pinctrl_uart0_dtr_dsr: uart0_dtr_dsr-0 {
137 atmel,pins =
138 <1 24 0x1 0x0 /* PB24 periph A */
139 1 22 0x1 0x0>; /* PB22 periph A */
140 };
141
142 pinctrl_uart0_dcd: uart0_dcd-0 {
143 atmel,pins =
144 <1 23 0x1 0x0>; /* PB23 periph A */
145 };
146
147 pinctrl_uart0_ri: uart0_ri-0 {
148 atmel,pins =
149 <1 25 0x1 0x0>; /* PB25 periph A */
150 };
151 };
120 152
121 pioC: gpio@fffff800 { 153 uart1 {
122 compatible = "atmel,at91rm9200-gpio"; 154 pinctrl_uart1: uart1-0 {
123 reg = <0xfffff800 0x100>; 155 atmel,pins =
124 interrupts = <4 4 1>; 156 <2 6 0x1 0x1 /* PB6 periph A with pullup */
125 #gpio-cells = <2>; 157 2 7 0x1 0x0>; /* PB7 periph A */
126 gpio-controller; 158 };
127 interrupt-controller; 159
128 #interrupt-cells = <2>; 160 pinctrl_uart1_rts_cts: uart1_rts_cts-0 {
161 atmel,pins =
162 <1 28 0x1 0x0 /* PB28 periph A */
163 1 29 0x1 0x0>; /* PB29 periph A */
164 };
165 };
166
167 uart2 {
168 pinctrl_uart2: uart2-0 {
169 atmel,pins =
170 <1 8 0x1 0x1 /* PB8 periph A with pullup */
171 1 9 0x1 0x0>; /* PB9 periph A */
172 };
173
174 pinctrl_uart2_rts_cts: uart2_rts_cts-0 {
175 atmel,pins =
176 <0 4 0x1 0x0 /* PA4 periph A */
177 0 5 0x1 0x0>; /* PA5 periph A */
178 };
179 };
180
181 uart3 {
182 pinctrl_uart3: uart3-0 {
183 atmel,pins =
184 <2 10 0x1 0x1 /* PB10 periph A with pullup */
185 2 11 0x1 0x0>; /* PB11 periph A */
186 };
187
188 pinctrl_uart3_rts_cts: uart3_rts_cts-0 {
189 atmel,pins =
190 <3 8 0x2 0x0 /* PB8 periph B */
191 3 10 0x2 0x0>; /* PB10 periph B */
192 };
193 };
194
195 uart4 {
196 pinctrl_uart4: uart4-0 {
197 atmel,pins =
198 <0 31 0x2 0x1 /* PA31 periph B with pullup */
199 0 30 0x2 0x0>; /* PA30 periph B */
200 };
201 };
202
203 uart5 {
204 pinctrl_uart5: uart5-0 {
205 atmel,pins =
206 <2 12 0x1 0x1 /* PB12 periph A with pullup */
207 2 13 0x1 0x0>; /* PB13 periph A */
208 };
209 };
210
211 nand {
212 pinctrl_nand: nand-0 {
213 atmel,pins =
214 <2 13 0x0 0x1 /* PC13 gpio RDY pin pull_up */
215 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
216 };
217 };
218
219 pioA: gpio@fffff400 {
220 compatible = "atmel,at91rm9200-gpio";
221 reg = <0xfffff400 0x200>;
222 interrupts = <2 4 1>;
223 #gpio-cells = <2>;
224 gpio-controller;
225 interrupt-controller;
226 #interrupt-cells = <2>;
227 };
228
229 pioB: gpio@fffff600 {
230 compatible = "atmel,at91rm9200-gpio";
231 reg = <0xfffff600 0x200>;
232 interrupts = <3 4 1>;
233 #gpio-cells = <2>;
234 gpio-controller;
235 interrupt-controller;
236 #interrupt-cells = <2>;
237 };
238
239 pioC: gpio@fffff800 {
240 compatible = "atmel,at91rm9200-gpio";
241 reg = <0xfffff800 0x200>;
242 interrupts = <4 4 1>;
243 #gpio-cells = <2>;
244 gpio-controller;
245 interrupt-controller;
246 #interrupt-cells = <2>;
247 };
129 }; 248 };
130 249
131 dbgu: serial@fffff200 { 250 dbgu: serial@fffff200 {
132 compatible = "atmel,at91sam9260-usart"; 251 compatible = "atmel,at91sam9260-usart";
133 reg = <0xfffff200 0x200>; 252 reg = <0xfffff200 0x200>;
134 interrupts = <1 4 7>; 253 interrupts = <1 4 7>;
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_dbgu>;
135 status = "disabled"; 256 status = "disabled";
136 }; 257 };
137 258
@@ -141,6 +262,8 @@
141 interrupts = <6 4 5>; 262 interrupts = <6 4 5>;
142 atmel,use-dma-rx; 263 atmel,use-dma-rx;
143 atmel,use-dma-tx; 264 atmel,use-dma-tx;
265 pinctrl-names = "default";
266 pinctrl-0 = <&pinctrl_uart0>;
144 status = "disabled"; 267 status = "disabled";
145 }; 268 };
146 269
@@ -150,6 +273,8 @@
150 interrupts = <7 4 5>; 273 interrupts = <7 4 5>;
151 atmel,use-dma-rx; 274 atmel,use-dma-rx;
152 atmel,use-dma-tx; 275 atmel,use-dma-tx;
276 pinctrl-names = "default";
277 pinctrl-0 = <&pinctrl_uart1>;
153 status = "disabled"; 278 status = "disabled";
154 }; 279 };
155 280
@@ -159,6 +284,8 @@
159 interrupts = <8 4 5>; 284 interrupts = <8 4 5>;
160 atmel,use-dma-rx; 285 atmel,use-dma-rx;
161 atmel,use-dma-tx; 286 atmel,use-dma-tx;
287 pinctrl-names = "default";
288 pinctrl-0 = <&pinctrl_uart2>;
162 status = "disabled"; 289 status = "disabled";
163 }; 290 };
164 291
@@ -168,6 +295,8 @@
168 interrupts = <23 4 5>; 295 interrupts = <23 4 5>;
169 atmel,use-dma-rx; 296 atmel,use-dma-rx;
170 atmel,use-dma-tx; 297 atmel,use-dma-tx;
298 pinctrl-names = "default";
299 pinctrl-0 = <&pinctrl_uart3>;
171 status = "disabled"; 300 status = "disabled";
172 }; 301 };
173 302
@@ -177,6 +306,8 @@
177 interrupts = <24 4 5>; 306 interrupts = <24 4 5>;
178 atmel,use-dma-rx; 307 atmel,use-dma-rx;
179 atmel,use-dma-tx; 308 atmel,use-dma-tx;
309 pinctrl-names = "default";
310 pinctrl-0 = <&pinctrl_uart4>;
180 status = "disabled"; 311 status = "disabled";
181 }; 312 };
182 313
@@ -186,6 +317,8 @@
186 interrupts = <25 4 5>; 317 interrupts = <25 4 5>;
187 atmel,use-dma-rx; 318 atmel,use-dma-rx;
188 atmel,use-dma-tx; 319 atmel,use-dma-tx;
320 pinctrl-names = "default";
321 pinctrl-0 = <&pinctrl_uart5>;
189 status = "disabled"; 322 status = "disabled";
190 }; 323 };
191 324
@@ -257,6 +390,8 @@
257 >; 390 >;
258 atmel,nand-addr-offset = <21>; 391 atmel,nand-addr-offset = <21>;
259 atmel,nand-cmd-offset = <22>; 392 atmel,nand-cmd-offset = <22>;
393 pinctrl-names = "default";
394 pinctrl-0 = <&pinctrl_nand>;
260 gpios = <&pioC 13 0 395 gpios = <&pioC 13 0
261 &pioC 14 0 396 &pioC 14 0
262 0 397 0
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 3e6e5c1abbf3..251ccec430a4 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -89,60 +89,137 @@
89 reg = <0xfffffd10 0x10>; 89 reg = <0xfffffd10 0x10>;
90 }; 90 };
91 91
92 pioA: gpio@fffff200 { 92 pinctrl@fffff200 {
93 compatible = "atmel,at91rm9200-gpio"; 93 #address-cells = <1>;
94 reg = <0xfffff200 0x100>; 94 #size-cells = <1>;
95 interrupts = <2 4 1>; 95 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
96 #gpio-cells = <2>; 96 ranges = <0xfffff200 0xfffff200 0xa00>;
97 gpio-controller;
98 interrupt-controller;
99 #interrupt-cells = <2>;
100 };
101 97
102 pioB: gpio@fffff400 { 98 atmel,mux-mask = <
103 compatible = "atmel,at91rm9200-gpio"; 99 /* A B */
104 reg = <0xfffff400 0x100>; 100 0xfffffffb 0xffffe07f /* pioA */
105 interrupts = <3 4 1>; 101 0x0007ffff 0x39072fff /* pioB */
106 #gpio-cells = <2>; 102 0xffffffff 0x3ffffff8 /* pioC */
107 gpio-controller; 103 0xfffffbff 0xffffffff /* pioD */
108 interrupt-controller; 104 0xffe00fff 0xfbfcff00 /* pioE */
109 #interrupt-cells = <2>; 105 >;
110 };
111 106
112 pioC: gpio@fffff600 { 107 /* shared pinctrl settings */
113 compatible = "atmel,at91rm9200-gpio"; 108 dbgu {
114 reg = <0xfffff600 0x100>; 109 pinctrl_dbgu: dbgu-0 {
115 interrupts = <4 4 1>; 110 atmel,pins =
116 #gpio-cells = <2>; 111 <2 30 0x1 0x0 /* PC30 periph A */
117 gpio-controller; 112 2 31 0x1 0x1>; /* PC31 periph with pullup */
118 interrupt-controller; 113 };
119 #interrupt-cells = <2>; 114 };
120 };
121 115
122 pioD: gpio@fffff800 { 116 uart0 {
123 compatible = "atmel,at91rm9200-gpio"; 117 pinctrl_uart0: uart0-0 {
124 reg = <0xfffff800 0x100>; 118 atmel,pins =
125 interrupts = <4 4 1>; 119 <0 26 0x1 0x1 /* PA26 periph A with pullup */
126 #gpio-cells = <2>; 120 0 27 0x1 0x0>; /* PA27 periph A */
127 gpio-controller; 121 };
128 interrupt-controller;
129 #interrupt-cells = <2>;
130 };
131 122
132 pioE: gpio@fffffa00 { 123 pinctrl_uart0_rts_cts: uart0_rts_cts-0 {
133 compatible = "atmel,at91rm9200-gpio"; 124 atmel,pins =
134 reg = <0xfffffa00 0x100>; 125 <0 28 0x1 0x0 /* PA28 periph A */
135 interrupts = <4 4 1>; 126 0 29 0x1 0x0>; /* PA29 periph A */
136 #gpio-cells = <2>; 127 };
137 gpio-controller; 128 };
138 interrupt-controller; 129
139 #interrupt-cells = <2>; 130 uart1 {
131 pinctrl_uart1: uart1-0 {
132 atmel,pins =
133 <3 0 0x1 0x1 /* PD0 periph A with pullup */
134 3 1 0x1 0x0>; /* PD1 periph A */
135 };
136
137 pinctrl_uart1_rts_cts: uart1_rts_cts-0 {
138 atmel,pins =
139 <3 7 0x2 0x0 /* PD7 periph B */
140 3 8 0x2 0x0>; /* PD8 periph B */
141 };
142 };
143
144 uart2 {
145 pinctrl_uart2: uart2-0 {
146 atmel,pins =
147 <3 2 0x1 0x1 /* PD2 periph A with pullup */
148 3 3 0x1 0x0>; /* PD3 periph A */
149 };
150
151 pinctrl_uart2_rts_cts: uart2_rts_cts-0 {
152 atmel,pins =
153 <3 5 0x2 0x0 /* PD5 periph B */
154 4 6 0x2 0x0>; /* PD6 periph B */
155 };
156 };
157
158 nand {
159 pinctrl_nand: nand-0 {
160 atmel,pins =
161 <0 22 0x0 0x1 /* PA22 gpio RDY pin pull_up*/
162 3 15 0x0 0x1>; /* PD15 gpio enable pin pull_up */
163 };
164 };
165
166 pioA: gpio@fffff200 {
167 compatible = "atmel,at91rm9200-gpio";
168 reg = <0xfffff200 0x200>;
169 interrupts = <2 4 1>;
170 #gpio-cells = <2>;
171 gpio-controller;
172 interrupt-controller;
173 #interrupt-cells = <2>;
174 };
175
176 pioB: gpio@fffff400 {
177 compatible = "atmel,at91rm9200-gpio";
178 reg = <0xfffff400 0x200>;
179 interrupts = <3 4 1>;
180 #gpio-cells = <2>;
181 gpio-controller;
182 interrupt-controller;
183 #interrupt-cells = <2>;
184 };
185
186 pioC: gpio@fffff600 {
187 compatible = "atmel,at91rm9200-gpio";
188 reg = <0xfffff600 0x200>;
189 interrupts = <4 4 1>;
190 #gpio-cells = <2>;
191 gpio-controller;
192 interrupt-controller;
193 #interrupt-cells = <2>;
194 };
195
196 pioD: gpio@fffff800 {
197 compatible = "atmel,at91rm9200-gpio";
198 reg = <0xfffff800 0x200>;
199 interrupts = <4 4 1>;
200 #gpio-cells = <2>;
201 gpio-controller;
202 interrupt-controller;
203 #interrupt-cells = <2>;
204 };
205
206 pioE: gpio@fffffa00 {
207 compatible = "atmel,at91rm9200-gpio";
208 reg = <0xfffffa00 0x200>;
209 interrupts = <4 4 1>;
210 #gpio-cells = <2>;
211 gpio-controller;
212 interrupt-controller;
213 #interrupt-cells = <2>;
214 };
140 }; 215 };
141 216
142 dbgu: serial@ffffee00 { 217 dbgu: serial@ffffee00 {
143 compatible = "atmel,at91sam9260-usart"; 218 compatible = "atmel,at91sam9260-usart";
144 reg = <0xffffee00 0x200>; 219 reg = <0xffffee00 0x200>;
145 interrupts = <1 4 7>; 220 interrupts = <1 4 7>;
221 pinctrl-names = "default";
222 pinctrl-0 = <&pinctrl_dbgu>;
146 status = "disabled"; 223 status = "disabled";
147 }; 224 };
148 225
@@ -152,6 +229,8 @@
152 interrupts = <7 4 5>; 229 interrupts = <7 4 5>;
153 atmel,use-dma-rx; 230 atmel,use-dma-rx;
154 atmel,use-dma-tx; 231 atmel,use-dma-tx;
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_uart0>;
155 status = "disabled"; 234 status = "disabled";
156 }; 235 };
157 236
@@ -161,6 +240,8 @@
161 interrupts = <8 4 5>; 240 interrupts = <8 4 5>;
162 atmel,use-dma-rx; 241 atmel,use-dma-rx;
163 atmel,use-dma-tx; 242 atmel,use-dma-tx;
243 pinctrl-names = "default";
244 pinctrl-0 = <&pinctrl_uart1>;
164 status = "disabled"; 245 status = "disabled";
165 }; 246 };
166 247
@@ -170,6 +251,8 @@
170 interrupts = <9 4 5>; 251 interrupts = <9 4 5>;
171 atmel,use-dma-rx; 252 atmel,use-dma-rx;
172 atmel,use-dma-tx; 253 atmel,use-dma-tx;
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_uart2>;
173 status = "disabled"; 256 status = "disabled";
174 }; 257 };
175 258
@@ -206,6 +289,8 @@
206 >; 289 >;
207 atmel,nand-addr-offset = <21>; 290 atmel,nand-addr-offset = <21>;
208 atmel,nand-cmd-offset = <22>; 291 atmel,nand-cmd-offset = <22>;
292 pinctrl-names = "default";
293 pinctrl-0 = <&pinctrl_nand>;
209 gpios = <&pioA 22 0 294 gpios = <&pioA 22 0
210 &pioD 15 0 295 &pioD 15 0
211 0 296 0
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
index f86ac4b609fc..7cfe9d521f12 100644
--- a/arch/arm/boot/dts/at91sam9263ek.dts
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -38,6 +38,7 @@
38 }; 38 };
39 39
40 usart0: serial@fff8c000 { 40 usart0: serial@fff8c000 {
41 pinctrl-0 = <&pinctrl_uart0 &pinctrl_uart0_rts_cts>;
41 status = "okay"; 42 status = "okay";
42 }; 43 };
43 44
diff --git a/arch/arm/boot/dts/at91sam9g15.dtsi b/arch/arm/boot/dts/at91sam9g15.dtsi
new file mode 100644
index 000000000000..fbe7a7089c2a
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g15.dtsi
@@ -0,0 +1,28 @@
1/*
2 * at91sam9g15.dtsi - Device Tree Include file for AT91SAM9G15 SoC
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8
9/include/ "at91sam9x5.dtsi"
10
11/ {
12 model = "Atmel AT91SAM9G15 SoC";
13 compatible = "atmel, at91sam9g15, atmel,at91sam9x5";
14
15 ahb {
16 apb {
17 pinctrl@fffff400 {
18 atmel,mux-mask = <
19 /* A B C */
20 0xffffffff 0xffe0399f 0x00000000 /* pioA */
21 0x00040000 0x00047e3f 0x00000000 /* pioB */
22 0xfdffffff 0x00000000 0xb83fffff /* pioC */
23 0x003fffff 0x003f8000 0x00000000 /* pioD */
24 >;
25 };
26 };
27 };
28};
diff --git a/arch/arm/boot/dts/at91sam9g15ek.dts b/arch/arm/boot/dts/at91sam9g15ek.dts
new file mode 100644
index 000000000000..86dd3f6d938f
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g15ek.dts
@@ -0,0 +1,16 @@
1/*
2 * at91sam9g15ek.dts - Device Tree file for AT91SAM9G15-EK board
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
10/include/ "at91sam9g15.dtsi"
11/include/ "at91sam9x5ek.dtsi"
12
13/ {
14 model = "Atmel AT91SAM9G25-EK";
15 compatible = "atmel,at91sam9g15ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
16};
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
index e6391a4e6649..689323d8e64c 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
@@ -35,6 +35,12 @@
35 }; 35 };
36 36
37 usart0: serial@fffb0000 { 37 usart0: serial@fffb0000 {
38 pinctrl-0 =
39 <&pinctrl_uart0
40 &pinctrl_uart0_rts_cts
41 &pinctrl_uart0_dtr_dsr
42 &pinctrl_uart0_dcd
43 &pinctrl_uart0_ri>;
38 status = "okay"; 44 status = "okay";
39 }; 45 };
40 46
diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/at91sam9g25.dtsi
new file mode 100644
index 000000000000..05a718fb83c4
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g25.dtsi
@@ -0,0 +1,28 @@
1/*
2 * at91sam9g25.dtsi - Device Tree Include file for AT91SAM9G25 SoC
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8
9/include/ "at91sam9x5.dtsi"
10
11/ {
12 model = "Atmel AT91SAM9G25 SoC";
13 compatible = "atmel, at91sam9g25, atmel,at91sam9x5";
14
15 ahb {
16 apb {
17 pinctrl@fffff400 {
18 atmel,mux-mask = <
19 /* A B C */
20 0xffffffff 0xffe0399f 0xc000001c /* pioA */
21 0x0007ffff 0x8000fe3f 0x00000000 /* pioB */
22 0x80000000 0x07c0ffff 0xb83fffff /* pioC */
23 0x003fffff 0x003f8000 0x00000000 /* pioD */
24 >;
25 };
26 };
27 };
28};
diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
index 877c08f06763..c5ab16fba059 100644
--- a/arch/arm/boot/dts/at91sam9g25ek.dts
+++ b/arch/arm/boot/dts/at91sam9g25ek.dts
@@ -7,55 +7,10 @@
7 * Licensed under GPLv2 or later. 7 * Licensed under GPLv2 or later.
8 */ 8 */
9/dts-v1/; 9/dts-v1/;
10/include/ "at91sam9x5.dtsi" 10/include/ "at91sam9g25.dtsi"
11/include/ "at91sam9x5cm.dtsi" 11/include/ "at91sam9x5ek.dtsi"
12 12
13/ { 13/ {
14 model = "Atmel AT91SAM9G25-EK"; 14 model = "Atmel AT91SAM9G25-EK";
15 compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; 15 compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
16
17 chosen {
18 bootargs = "console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
19 };
20
21 ahb {
22 apb {
23 dbgu: serial@fffff200 {
24 status = "okay";
25 };
26
27 usart0: serial@f801c000 {
28 status = "okay";
29 };
30
31 macb0: ethernet@f802c000 {
32 phy-mode = "rmii";
33 status = "okay";
34 };
35
36 i2c0: i2c@f8010000 {
37 status = "okay";
38 };
39
40 i2c1: i2c@f8014000 {
41 status = "okay";
42 };
43
44 i2c2: i2c@f8018000 {
45 status = "okay";
46 };
47 };
48
49 usb0: ohci@00600000 {
50 status = "okay";
51 num-ports = <2>;
52 atmel,vbus-gpio = <&pioD 19 1
53 &pioD 20 1
54 >;
55 };
56
57 usb1: ehci@00700000 {
58 status = "okay";
59 };
60 };
61}; 16};
diff --git a/arch/arm/boot/dts/at91sam9g35.dtsi b/arch/arm/boot/dts/at91sam9g35.dtsi
new file mode 100644
index 000000000000..f9d14a722794
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g35.dtsi
@@ -0,0 +1,28 @@
1/*
2 * at91sam9g35.dtsi - Device Tree Include file for AT91SAM9G35 SoC
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8
9/include/ "at91sam9x5.dtsi"
10
11/ {
12 model = "Atmel AT91SAM9G35 SoC";
13 compatible = "atmel, at91sam9g35, atmel,at91sam9x5";
14
15 ahb {
16 apb {
17 pinctrl@fffff400 {
18 atmel,mux-mask = <
19 /* A B C */
20 0xffffffff 0xffe0399f 0xc000000c /* pioA */
21 0x000406ff 0x00047e3f 0x00000000 /* pioB */
22 0xfdffffff 0x00000000 0xb83fffff /* pioC */
23 0x003fffff 0x003f8000 0x00000000 /* pioD */
24 >;
25 };
26 };
27 };
28};
diff --git a/arch/arm/boot/dts/at91sam9g35ek.dts b/arch/arm/boot/dts/at91sam9g35ek.dts
new file mode 100644
index 000000000000..95944bdd798d
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g35ek.dts
@@ -0,0 +1,16 @@
1/*
2 * at91sam9g35ek.dts - Device Tree file for AT91SAM9G35-EK board
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
10/include/ "at91sam9g35.dtsi"
11/include/ "at91sam9x5ek.dtsi"
12
13/ {
14 model = "Atmel AT91SAM9G35-EK";
15 compatible = "atmel,at91sam9g35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
16};
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 3add030d61f8..c340f6635d81 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -108,60 +108,151 @@
108 interrupts = <21 4 0>; 108 interrupts = <21 4 0>;
109 }; 109 };
110 110
111 pioA: gpio@fffff200 { 111 pinctrl@fffff200 {
112 compatible = "atmel,at91rm9200-gpio"; 112 #address-cells = <1>;
113 reg = <0xfffff200 0x100>; 113 #size-cells = <1>;
114 interrupts = <2 4 1>; 114 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
115 #gpio-cells = <2>; 115 ranges = <0xfffff200 0xfffff200 0xa00>;
116 gpio-controller; 116
117 interrupt-controller; 117 atmel,mux-mask = <
118 #interrupt-cells = <2>; 118 /* A B */
119 }; 119 0xffffffff 0xffc003ff /* pioA */
120 0xffffffff 0x800f8f00 /* pioB */
121 0xffffffff 0x00000e00 /* pioC */
122 0xffffffff 0xff0c1381 /* pioD */
123 0xffffffff 0x81ffff81 /* pioE */
124 >;
125
126 /* shared pinctrl settings */
127 dbgu {
128 pinctrl_dbgu: dbgu-0 {
129 atmel,pins =
130 <1 12 0x1 0x0 /* PB12 periph A */
131 1 13 0x1 0x0>; /* PB13 periph A */
132 };
133 };
120 134
121 pioB: gpio@fffff400 { 135 uart0 {
122 compatible = "atmel,at91rm9200-gpio"; 136 pinctrl_uart0: uart0-0 {
123 reg = <0xfffff400 0x100>; 137 atmel,pins =
124 interrupts = <3 4 1>; 138 <1 19 0x1 0x1 /* PB19 periph A with pullup */
125 #gpio-cells = <2>; 139 1 18 0x1 0x0>; /* PB18 periph A */
126 gpio-controller; 140 };
127 interrupt-controller; 141
128 #interrupt-cells = <2>; 142 pinctrl_uart0_rts_cts: uart0_rts_cts-0 {
129 }; 143 atmel,pins =
144 <1 17 0x2 0x0 /* PB17 periph B */
145 1 15 0x2 0x0>; /* PB15 periph B */
146 };
147 };
130 148
131 pioC: gpio@fffff600 { 149 uart1 {
132 compatible = "atmel,at91rm9200-gpio"; 150 pinctrl_uart1: uart1-0 {
133 reg = <0xfffff600 0x100>; 151 atmel,pins =
134 interrupts = <4 4 1>; 152 <1 4 0x1 0x1 /* PB4 periph A with pullup */
135 #gpio-cells = <2>; 153 1 5 0x1 0x0>; /* PB5 periph A */
136 gpio-controller; 154 };
137 interrupt-controller; 155
138 #interrupt-cells = <2>; 156 pinctrl_uart1_rts_cts: uart1_rts_cts-0 {
139 }; 157 atmel,pins =
158 <3 16 0x1 0x0 /* PD16 periph A */
159 3 17 0x1 0x0>; /* PD17 periph A */
160 };
161 };
140 162
141 pioD: gpio@fffff800 { 163 uart2 {
142 compatible = "atmel,at91rm9200-gpio"; 164 pinctrl_uart2: uart2-0 {
143 reg = <0xfffff800 0x100>; 165 atmel,pins =
144 interrupts = <5 4 1>; 166 <1 6 0x1 0x1 /* PB6 periph A with pullup */
145 #gpio-cells = <2>; 167 1 7 0x1 0x0>; /* PB7 periph A */
146 gpio-controller; 168 };
147 interrupt-controller; 169
148 #interrupt-cells = <2>; 170 pinctrl_uart2_rts_cts: uart2_rts_cts-0 {
149 }; 171 atmel,pins =
172 <2 9 0x2 0x0 /* PC9 periph B */
173 2 11 0x2 0x0>; /* PC11 periph B */
174 };
175 };
150 176
151 pioE: gpio@fffffa00 { 177 uart3 {
152 compatible = "atmel,at91rm9200-gpio"; 178 pinctrl_uart3: uart3-0 {
153 reg = <0xfffffa00 0x100>; 179 atmel,pins =
154 interrupts = <5 4 1>; 180 <1 8 0x1 0x1 /* PB9 periph A with pullup */
155 #gpio-cells = <2>; 181 1 9 0x1 0x0>; /* PB8 periph A */
156 gpio-controller; 182 };
157 interrupt-controller; 183
158 #interrupt-cells = <2>; 184 pinctrl_uart3_rts_cts: uart3_rts_cts-0 {
185 atmel,pins =
186 <0 23 0x2 0x0 /* PA23 periph B */
187 0 24 0x2 0x0>; /* PA24 periph B */
188 };
189 };
190
191 nand {
192 pinctrl_nand: nand-0 {
193 atmel,pins =
194 <2 8 0x0 0x1 /* PC8 gpio RDY pin pull_up*/
195 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
196 };
197 };
198
199 pioA: gpio@fffff200 {
200 compatible = "atmel,at91rm9200-gpio";
201 reg = <0xfffff200 0x200>;
202 interrupts = <2 4 1>;
203 #gpio-cells = <2>;
204 gpio-controller;
205 interrupt-controller;
206 #interrupt-cells = <2>;
207 };
208
209 pioB: gpio@fffff400 {
210 compatible = "atmel,at91rm9200-gpio";
211 reg = <0xfffff400 0x200>;
212 interrupts = <3 4 1>;
213 #gpio-cells = <2>;
214 gpio-controller;
215 interrupt-controller;
216 #interrupt-cells = <2>;
217 };
218
219 pioC: gpio@fffff600 {
220 compatible = "atmel,at91rm9200-gpio";
221 reg = <0xfffff600 0x200>;
222 interrupts = <4 4 1>;
223 #gpio-cells = <2>;
224 gpio-controller;
225 interrupt-controller;
226 #interrupt-cells = <2>;
227 };
228
229 pioD: gpio@fffff800 {
230 compatible = "atmel,at91rm9200-gpio";
231 reg = <0xfffff800 0x200>;
232 interrupts = <5 4 1>;
233 #gpio-cells = <2>;
234 gpio-controller;
235 interrupt-controller;
236 #interrupt-cells = <2>;
237 };
238
239 pioE: gpio@fffffa00 {
240 compatible = "atmel,at91rm9200-gpio";
241 reg = <0xfffffa00 0x200>;
242 interrupts = <5 4 1>;
243 #gpio-cells = <2>;
244 gpio-controller;
245 interrupt-controller;
246 #interrupt-cells = <2>;
247 };
159 }; 248 };
160 249
161 dbgu: serial@ffffee00 { 250 dbgu: serial@ffffee00 {
162 compatible = "atmel,at91sam9260-usart"; 251 compatible = "atmel,at91sam9260-usart";
163 reg = <0xffffee00 0x200>; 252 reg = <0xffffee00 0x200>;
164 interrupts = <1 4 7>; 253 interrupts = <1 4 7>;
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_dbgu>;
165 status = "disabled"; 256 status = "disabled";
166 }; 257 };
167 258
@@ -171,6 +262,8 @@
171 interrupts = <7 4 5>; 262 interrupts = <7 4 5>;
172 atmel,use-dma-rx; 263 atmel,use-dma-rx;
173 atmel,use-dma-tx; 264 atmel,use-dma-tx;
265 pinctrl-names = "default";
266 pinctrl-0 = <&pinctrl_uart0>;
174 status = "disabled"; 267 status = "disabled";
175 }; 268 };
176 269
@@ -180,6 +273,8 @@
180 interrupts = <8 4 5>; 273 interrupts = <8 4 5>;
181 atmel,use-dma-rx; 274 atmel,use-dma-rx;
182 atmel,use-dma-tx; 275 atmel,use-dma-tx;
276 pinctrl-names = "default";
277 pinctrl-0 = <&pinctrl_uart1>;
183 status = "disabled"; 278 status = "disabled";
184 }; 279 };
185 280
@@ -189,6 +284,8 @@
189 interrupts = <9 4 5>; 284 interrupts = <9 4 5>;
190 atmel,use-dma-rx; 285 atmel,use-dma-rx;
191 atmel,use-dma-tx; 286 atmel,use-dma-tx;
287 pinctrl-names = "default";
288 pinctrl-0 = <&pinctrl_uart2>;
192 status = "disabled"; 289 status = "disabled";
193 }; 290 };
194 291
@@ -198,6 +295,8 @@
198 interrupts = <10 4 5>; 295 interrupts = <10 4 5>;
199 atmel,use-dma-rx; 296 atmel,use-dma-rx;
200 atmel,use-dma-tx; 297 atmel,use-dma-tx;
298 pinctrl-names = "default";
299 pinctrl-0 = <&pinctrl_uart3>;
201 status = "disabled"; 300 status = "disabled";
202 }; 301 };
203 302
@@ -273,6 +372,8 @@
273 >; 372 >;
274 atmel,nand-addr-offset = <21>; 373 atmel,nand-addr-offset = <21>;
275 atmel,nand-cmd-offset = <22>; 374 atmel,nand-cmd-offset = <22>;
375 pinctrl-names = "default";
376 pinctrl-0 = <&pinctrl_nand>;
276 gpios = <&pioC 8 0 377 gpios = <&pioC 8 0
277 &pioC 14 0 378 &pioC 14 0
278 0 379 0
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index 15e1dd43f625..6aa28b941907 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -39,6 +39,7 @@
39 }; 39 };
40 40
41 usart1: serial@fff90000 { 41 usart1: serial@fff90000 {
42 pinctrl-0 = <&pinctrl_uart0 &pinctrl_uart1_rts_cts>;
42 status = "okay"; 43 status = "okay";
43 }; 44 };
44 45
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 82508d68aa7e..7b644c5b0bed 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -102,50 +102,150 @@
102 interrupts = <20 4 0>; 102 interrupts = <20 4 0>;
103 }; 103 };
104 104
105 pioA: gpio@fffff400 { 105 pinctrl@fffff400 {
106 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 106 #address-cells = <1>;
107 reg = <0xfffff400 0x100>; 107 #size-cells = <1>;
108 interrupts = <2 4 1>; 108 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
109 #gpio-cells = <2>; 109 ranges = <0xfffff400 0xfffff400 0x800>;
110 gpio-controller;
111 interrupt-controller;
112 #interrupt-cells = <2>;
113 };
114 110
115 pioB: gpio@fffff600 { 111 atmel,mux-mask = <
116 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 112 /* A B C */
117 reg = <0xfffff600 0x100>; 113 0xffffffff 0xffe07983 0x00000000 /* pioA */
118 interrupts = <2 4 1>; 114 0x00040000 0x00047e0f 0x00000000 /* pioB */
119 #gpio-cells = <2>; 115 0xfdffffff 0x07c00000 0xb83fffff /* pioC */
120 gpio-controller; 116 0x003fffff 0x003f8000 0x00000000 /* pioD */
121 interrupt-controller; 117 >;
122 #interrupt-cells = <2>;
123 };
124 118
125 pioC: gpio@fffff800 { 119 /* shared pinctrl settings */
126 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 120 dbgu {
127 reg = <0xfffff800 0x100>; 121 pinctrl_dbgu: dbgu-0 {
128 interrupts = <3 4 1>; 122 atmel,pins =
129 #gpio-cells = <2>; 123 <0 9 0x1 0x0 /* PA9 periph A */
130 gpio-controller; 124 0 10 0x1 0x1>; /* PA10 periph with pullup */
131 interrupt-controller; 125 };
132 #interrupt-cells = <2>; 126 };
133 };
134 127
135 pioD: gpio@fffffa00 { 128 uart0 {
136 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 129 pinctrl_uart0: uart0-0 {
137 reg = <0xfffffa00 0x100>; 130 atmel,pins =
138 interrupts = <3 4 1>; 131 <0 1 0x1 0x1 /* PA1 periph A with pullup */
139 #gpio-cells = <2>; 132 0 0 0x1 0x0>; /* PA0 periph A */
140 gpio-controller; 133 };
141 interrupt-controller; 134
142 #interrupt-cells = <2>; 135 pinctrl_uart0_rts_cts: uart0_rts_cts-0 {
136 atmel,pins =
137 <0 2 0x1 0x0 /* PA2 periph A */
138 0 3 0x1 0x0>; /* PA3 periph A */
139 };
140 };
141
142 uart1 {
143 pinctrl_uart1: uart1-0 {
144 atmel,pins =
145 <0 6 0x1 0x1 /* PA6 periph A with pullup */
146 0 5 0x1 0x0>; /* PA5 periph A */
147 };
148 };
149
150 uart2 {
151 pinctrl_uart2: uart2-0 {
152 atmel,pins =
153 <0 8 0x1 0x1 /* PA8 periph A with pullup */
154 0 7 0x1 0x0>; /* PA7 periph A */
155 };
156
157 pinctrl_uart2_rts_cts: uart2_rts_cts-0 {
158 atmel,pins =
159 <1 0 0x2 0x0 /* PB0 periph B */
160 1 1 0x2 0x0>; /* PB1 periph B */
161 };
162 };
163
164 uart3 {
165 pinctrl_uart3: uart3-0 {
166 atmel,pins =
167 <2 23 0x2 0x1 /* PC23 periph B with pullup */
168 2 22 0x2 0x0>; /* PC22 periph B */
169 };
170
171 pinctrl_uart3_rts_cts: uart3_rts_cts-0 {
172 atmel,pins =
173 <2 24 0x2 0x0 /* PC24 periph B */
174 2 25 0x2 0x0>; /* PC25 periph B */
175 };
176 };
177
178 usart0 {
179 pinctrl_usart0: usart0-0 {
180 atmel,pins =
181 <2 9 0x3 0x1 /* PC9 periph C with pullup */
182 2 8 0x3 0x0>; /* PC8 periph C */
183 };
184 };
185
186 usart1 {
187 pinctrl_usart1: usart1-0 {
188 atmel,pins =
189 <2 16 0x3 0x1 /* PC17 periph C with pullup */
190 2 17 0x3 0x0>; /* PC16 periph C */
191 };
192 };
193
194 nand {
195 pinctrl_nand: nand-0 {
196 atmel,pins =
197 <3 5 0x0 0x1 /* PD5 gpio RDY pin pull_up*/
198 3 4 0x0 0x1>; /* PD4 gpio enable pin pull_up */
199 };
200 };
201
202 pioA: gpio@fffff400 {
203 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
204 reg = <0xfffff400 0x200>;
205 interrupts = <2 4 1>;
206 #gpio-cells = <2>;
207 gpio-controller;
208 interrupt-controller;
209 #interrupt-cells = <2>;
210 };
211
212 pioB: gpio@fffff600 {
213 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
214 reg = <0xfffff600 0x200>;
215 interrupts = <2 4 1>;
216 #gpio-cells = <2>;
217 gpio-controller;
218 interrupt-controller;
219 #interrupt-cells = <2>;
220 };
221
222 pioC: gpio@fffff800 {
223 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
224 reg = <0xfffff800 0x200>;
225 interrupts = <3 4 1>;
226 #gpio-cells = <2>;
227 gpio-controller;
228 interrupt-controller;
229 #interrupt-cells = <2>;
230 };
231
232 pioD: gpio@fffffa00 {
233 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
234 reg = <0xfffffa00 0x200>;
235 interrupts = <3 4 1>;
236 #gpio-cells = <2>;
237 gpio-controller;
238 interrupt-controller;
239 #interrupt-cells = <2>;
240 };
143 }; 241 };
144 242
145 dbgu: serial@fffff200 { 243 dbgu: serial@fffff200 {
146 compatible = "atmel,at91sam9260-usart"; 244 compatible = "atmel,at91sam9260-usart";
147 reg = <0xfffff200 0x200>; 245 reg = <0xfffff200 0x200>;
148 interrupts = <1 4 7>; 246 interrupts = <1 4 7>;
247 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_dbgu>;
149 status = "disabled"; 249 status = "disabled";
150 }; 250 };
151 251
@@ -155,6 +255,8 @@
155 interrupts = <5 4 5>; 255 interrupts = <5 4 5>;
156 atmel,use-dma-rx; 256 atmel,use-dma-rx;
157 atmel,use-dma-tx; 257 atmel,use-dma-tx;
258 pinctrl-names = "default";
259 pinctrl-0 = <&pinctrl_uart0>;
158 status = "disabled"; 260 status = "disabled";
159 }; 261 };
160 262
@@ -164,6 +266,8 @@
164 interrupts = <6 4 5>; 266 interrupts = <6 4 5>;
165 atmel,use-dma-rx; 267 atmel,use-dma-rx;
166 atmel,use-dma-tx; 268 atmel,use-dma-tx;
269 pinctrl-names = "default";
270 pinctrl-0 = <&pinctrl_uart1>;
167 status = "disabled"; 271 status = "disabled";
168 }; 272 };
169 273
@@ -173,6 +277,8 @@
173 interrupts = <7 4 5>; 277 interrupts = <7 4 5>;
174 atmel,use-dma-rx; 278 atmel,use-dma-rx;
175 atmel,use-dma-tx; 279 atmel,use-dma-tx;
280 pinctrl-names = "default";
281 pinctrl-0 = <&pinctrl_uart2>;
176 status = "disabled"; 282 status = "disabled";
177 }; 283 };
178 284
@@ -182,6 +288,8 @@
182 interrupts = <8 4 5>; 288 interrupts = <8 4 5>;
183 atmel,use-dma-rx; 289 atmel,use-dma-rx;
184 atmel,use-dma-tx; 290 atmel,use-dma-tx;
291 pinctrl-names = "default";
292 pinctrl-0 = <&pinctrl_uart3>;
185 status = "disabled"; 293 status = "disabled";
186 }; 294 };
187 295
@@ -215,6 +323,8 @@
215 >; 323 >;
216 atmel,nand-addr-offset = <21>; 324 atmel,nand-addr-offset = <21>;
217 atmel,nand-cmd-offset = <22>; 325 atmel,nand-cmd-offset = <22>;
326 pinctrl-names = "default";
327 pinctrl-0 = <&pinctrl_nand>;
218 gpios = <&pioD 5 0 328 gpios = <&pioD 5 0
219 &pioD 4 0 329 &pioD 4 0
220 0 330 0
diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/at91sam9x25.dtsi
new file mode 100644
index 000000000000..956c65f7c39f
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x25.dtsi
@@ -0,0 +1,28 @@
1/*
2 * at91sam9x25.dtsi - Device Tree Include file for AT91SAM9X25 SoC
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8
9/include/ "at91sam9x5.dtsi"
10
11/ {
12 model = "Atmel AT91SAM9X25 SoC";
13 compatible = "atmel, at91sam9x25, atmel,at91sam9x5";
14
15 ahb {
16 apb {
17 pinctrl@fffff400 {
18 atmel,mux-mask = <
19 /* A B C */
20 0xffffffff 0xffe03fff 0xc000001c /* pioA */
21 0x0007ffff 0x00047e3f 0x00000000 /* pioB */
22 0x80000000 0xfffd0000 0xb83fffff /* pioC */
23 0x003fffff 0x003f8000 0x00000000 /* pioD */
24 >;
25 };
26 };
27 };
28};
diff --git a/arch/arm/boot/dts/at91sam9x25ek.dts b/arch/arm/boot/dts/at91sam9x25ek.dts
new file mode 100644
index 000000000000..af907eaa1f25
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x25ek.dts
@@ -0,0 +1,16 @@
1/*
2 * at91sam9x25ek.dts - Device Tree file for AT91SAM9X25-EK board
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
10/include/ "at91sam9x25.dtsi"
11/include/ "at91sam9x5ek.dtsi"
12
13/ {
14 model = "Atmel AT91SAM9G25-EK";
15 compatible = "atmel,at91sam9x25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
16};
diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi
new file mode 100644
index 000000000000..fb102d6126ce
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x35.dtsi
@@ -0,0 +1,28 @@
1/*
2 * at91sam9x35.dtsi - Device Tree Include file for AT91SAM9X35 SoC
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8
9/include/ "at91sam9x5.dtsi"
10
11/ {
12 model = "Atmel AT91SAM9X35 SoC";
13 compatible = "atmel, at91sam9x35, atmel,at91sam9x5";
14
15 ahb {
16 apb {
17 pinctrl@fffff400 {
18 atmel,mux-mask = <
19 /* A B C */
20 0xffffffff 0xffe03fff 0xc000000c /* pioA */
21 0x000406ff 0x00047e3f 0x00000000 /* pioB */
22 0xfdffffff 0x00000000 0xb83fffff /* pioC */
23 0x003fffff 0x003f8000 0x00000000 /* pioD */
24 >;
25 };
26 };
27 };
28};
diff --git a/arch/arm/boot/dts/at91sam9x35ek.dts b/arch/arm/boot/dts/at91sam9x35ek.dts
new file mode 100644
index 000000000000..5ccb607b5414
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x35ek.dts
@@ -0,0 +1,16 @@
1/*
2 * at91sam9x35ek.dts - Device Tree file for AT91SAM9X35-EK board
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
10/include/ "at91sam9x35.dtsi"
11/include/ "at91sam9x5ek.dtsi"
12
13/ {
14 model = "Atmel AT91SAM9X35-EK";
15 compatible = "atmel,at91sam9x35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
16};
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 03fc136421c5..6a40b777ea4c 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -111,50 +111,150 @@
111 interrupts = <21 4 0>; 111 interrupts = <21 4 0>;
112 }; 112 };
113 113
114 pioA: gpio@fffff400 { 114 pinctrl@fffff400 {
115 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 115 #address-cells = <1>;
116 reg = <0xfffff400 0x100>; 116 #size-cells = <1>;
117 interrupts = <2 4 1>; 117 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
118 #gpio-cells = <2>; 118 ranges = <0xfffff400 0xfffff400 0x800>;
119 gpio-controller; 119
120 interrupt-controller; 120 /* shared pinctrl settings */
121 #interrupt-cells = <2>; 121 dbgu {
122 }; 122 pinctrl_dbgu: dbgu-0 {
123 atmel,pins =
124 <0 9 0x1 0x0 /* PA9 periph A */
125 0 10 0x1 0x1>; /* PA10 periph A with pullup */
126 };
127 };
123 128
124 pioB: gpio@fffff600 { 129 uart0 {
125 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 130 pinctrl_uart0: uart0-0 {
126 reg = <0xfffff600 0x100>; 131 atmel,pins =
127 interrupts = <2 4 1>; 132 <0 0 0x1 0x1 /* PA0 periph A with pullup */
128 #gpio-cells = <2>; 133 0 1 0x1 0x0>; /* PA1 periph A */
129 gpio-controller; 134 };
130 interrupt-controller; 135
131 #interrupt-cells = <2>; 136 pinctrl_uart0_rts_cts: uart0_rts_cts-0 {
132 }; 137 atmel,pins =
138 <0 2 0x1 0x0 /* PA2 periph A */
139 0 3 0x1 0x0>; /* PA3 periph A */
140 };
141 };
133 142
134 pioC: gpio@fffff800 { 143 uart1 {
135 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 144 pinctrl_uart1: uart1-0 {
136 reg = <0xfffff800 0x100>; 145 atmel,pins =
137 interrupts = <3 4 1>; 146 <0 5 0x1 0x1 /* PA5 periph A with pullup */
138 #gpio-cells = <2>; 147 0 6 0x1 0x0>; /* PA6 periph A */
139 gpio-controller; 148 };
140 interrupt-controller; 149
141 #interrupt-cells = <2>; 150 pinctrl_uart1_rts_cts: uart1_rts_cts-0 {
142 }; 151 atmel,pins =
152 <3 27 0x3 0x0 /* PC27 periph C */
153 3 28 0x3 0x0>; /* PC28 periph C */
154 };
155 };
143 156
144 pioD: gpio@fffffa00 { 157 uart2 {
145 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 158 pinctrl_uart2: uart2-0 {
146 reg = <0xfffffa00 0x100>; 159 atmel,pins =
147 interrupts = <3 4 1>; 160 <0 7 0x1 0x1 /* PA7 periph A with pullup */
148 #gpio-cells = <2>; 161 0 8 0x1 0x0>; /* PA8 periph A */
149 gpio-controller; 162 };
150 interrupt-controller; 163
151 #interrupt-cells = <2>; 164 pinctrl_uart2_rts_cts: uart2_rts_cts-0 {
165 atmel,pins =
166 <0 0 0x2 0x0 /* PB0 periph B */
167 0 1 0x2 0x0>; /* PB1 periph B */
168 };
169 };
170
171 uart3 {
172 pinctrl_uart3: uart3-0 {
173 atmel,pins =
174 <3 23 0x2 0x1 /* PC22 periph B with pullup */
175 3 23 0x2 0x0>; /* PC23 periph B */
176 };
177
178 pinctrl_uart3_rts_cts: uart3_rts_cts-0 {
179 atmel,pins =
180 <3 24 0x2 0x0 /* PC24 periph B */
181 3 25 0x2 0x0>; /* PC25 periph B */
182 };
183 };
184
185 usart0 {
186 pinctrl_usart0: usart0-0 {
187 atmel,pins =
188 <3 8 0x3 0x0 /* PC8 periph C */
189 3 9 0x3 0x1>; /* PC9 periph C with pullup */
190 };
191 };
192
193 usart1 {
194 pinctrl_usart1: usart1-0 {
195 atmel,pins =
196 <3 16 0x3 0x0 /* PC16 periph C */
197 3 17 0x3 0x1>; /* PC17 periph C with pullup */
198 };
199 };
200
201 nand {
202 pinctrl_nand: nand-0 {
203 atmel,pins =
204 <3 4 0x0 0x1 /* PD5 gpio RDY pin pull_up */
205 3 5 0x0 0x1>; /* PD4 gpio enable pin pull_up */
206 };
207 };
208
209 pioA: gpio@fffff400 {
210 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
211 reg = <0xfffff400 0x200>;
212 interrupts = <2 4 1>;
213 #gpio-cells = <2>;
214 gpio-controller;
215 interrupt-controller;
216 #interrupt-cells = <2>;
217 };
218
219 pioB: gpio@fffff600 {
220 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
221 reg = <0xfffff600 0x200>;
222 interrupts = <2 4 1>;
223 #gpio-cells = <2>;
224 gpio-controller;
225 #gpio-lines = <19>;
226 interrupt-controller;
227 #interrupt-cells = <2>;
228 };
229
230 pioC: gpio@fffff800 {
231 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
232 reg = <0xfffff800 0x200>;
233 interrupts = <3 4 1>;
234 #gpio-cells = <2>;
235 gpio-controller;
236 interrupt-controller;
237 #interrupt-cells = <2>;
238 };
239
240 pioD: gpio@fffffa00 {
241 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
242 reg = <0xfffffa00 0x200>;
243 interrupts = <3 4 1>;
244 #gpio-cells = <2>;
245 gpio-controller;
246 #gpio-lines = <22>;
247 interrupt-controller;
248 #interrupt-cells = <2>;
249 };
152 }; 250 };
153 251
154 dbgu: serial@fffff200 { 252 dbgu: serial@fffff200 {
155 compatible = "atmel,at91sam9260-usart"; 253 compatible = "atmel,at91sam9260-usart";
156 reg = <0xfffff200 0x200>; 254 reg = <0xfffff200 0x200>;
157 interrupts = <1 4 7>; 255 interrupts = <1 4 7>;
256 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_dbgu>;
158 status = "disabled"; 258 status = "disabled";
159 }; 259 };
160 260
@@ -164,6 +264,8 @@
164 interrupts = <5 4 5>; 264 interrupts = <5 4 5>;
165 atmel,use-dma-rx; 265 atmel,use-dma-rx;
166 atmel,use-dma-tx; 266 atmel,use-dma-tx;
267 pinctrl-names = "default";
268 pinctrl-0 = <&pinctrl_uart0>;
167 status = "disabled"; 269 status = "disabled";
168 }; 270 };
169 271
@@ -173,6 +275,8 @@
173 interrupts = <6 4 5>; 275 interrupts = <6 4 5>;
174 atmel,use-dma-rx; 276 atmel,use-dma-rx;
175 atmel,use-dma-tx; 277 atmel,use-dma-tx;
278 pinctrl-names = "default";
279 pinctrl-0 = <&pinctrl_uart1>;
176 status = "disabled"; 280 status = "disabled";
177 }; 281 };
178 282
@@ -182,6 +286,8 @@
182 interrupts = <7 4 5>; 286 interrupts = <7 4 5>;
183 atmel,use-dma-rx; 287 atmel,use-dma-rx;
184 atmel,use-dma-tx; 288 atmel,use-dma-tx;
289 pinctrl-names = "default";
290 pinctrl-0 = <&pinctrl_uart2>;
185 status = "disabled"; 291 status = "disabled";
186 }; 292 };
187 293
@@ -273,6 +379,8 @@
273 >; 379 >;
274 atmel,nand-addr-offset = <21>; 380 atmel,nand-addr-offset = <21>;
275 atmel,nand-cmd-offset = <22>; 381 atmel,nand-cmd-offset = <22>;
382 pinctrl-names = "default";
383 pinctrl-0 = <&pinctrl_nand>;
276 gpios = <&pioD 5 0 384 gpios = <&pioD 5 0
277 &pioD 4 0 385 &pioD 4 0
278 0 386 0
diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi
new file mode 100644
index 000000000000..cc9730c60180
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi
@@ -0,0 +1,59 @@
1/*
2 * at91sam9x5ek.dtsi - Device Tree file for AT91SAM9x5CM Base board
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/include/ "at91sam9x5cm.dtsi"
10
11/ {
12 model = "Atmel AT91SAM9X5-EK";
13 compatible = "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
14
15 chosen {
16 bootargs = "128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
17 };
18
19 ahb {
20 apb {
21 dbgu: serial@fffff200 {
22 status = "okay";
23 };
24
25 usart0: serial@f801c000 {
26 status = "okay";
27 };
28
29 macb0: ethernet@f802c000 {
30 phy-mode = "rmii";
31 status = "okay";
32 };
33
34 i2c0: i2c@f8010000 {
35 status = "okay";
36 };
37
38 i2c1: i2c@f8014000 {
39 status = "okay";
40 };
41
42 i2c2: i2c@f8018000 {
43 status = "okay";
44 };
45 };
46
47 usb0: ohci@00600000 {
48 status = "okay";
49 num-ports = <2>;
50 atmel,vbus-gpio = <&pioD 19 1
51 &pioD 20 1
52 >;
53 };
54
55 usb1: ehci@00700000 {
56 status = "okay";
57 };
58 };
59};
diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index 67bc571ed0c3..b175577d7abb 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -111,6 +111,7 @@ CONFIG_I2C=y
111CONFIG_I2C_GPIO=y 111CONFIG_I2C_GPIO=y
112CONFIG_SPI=y 112CONFIG_SPI=y
113CONFIG_SPI_ATMEL=y 113CONFIG_SPI_ATMEL=y
114CONFIG_PINCTRL_AT91=y
114# CONFIG_HWMON is not set 115# CONFIG_HWMON is not set
115CONFIG_WATCHDOG=y 116CONFIG_WATCHDOG=y
116CONFIG_AT91SAM9X_WATCHDOG=y 117CONFIG_AT91SAM9X_WATCHDOG=y
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 5269825194a8..a3e4710d7352 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -361,10 +361,10 @@ static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
361 0 /* Advanced Interrupt Controller (IRQ6) */ 361 0 /* Advanced Interrupt Controller (IRQ6) */
362}; 362};
363 363
364struct at91_init_soc __initdata at91rm9200_soc = { 364AT91_SOC_START(rm9200)
365 .map_io = at91rm9200_map_io, 365 .map_io = at91rm9200_map_io,
366 .default_irq_priority = at91rm9200_default_irq_priority, 366 .default_irq_priority = at91rm9200_default_irq_priority,
367 .ioremap_registers = at91rm9200_ioremap_registers, 367 .ioremap_registers = at91rm9200_ioremap_registers,
368 .register_clocks = at91rm9200_register_clocks, 368 .register_clocks = at91rm9200_register_clocks,
369 .init = at91rm9200_initialize, 369 .init = at91rm9200_initialize,
370}; 370AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index f8202615f4a8..7aaa62cef4ac 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -235,6 +235,9 @@ static struct clk_lookup periph_clocks_lookups[] = {
235 CLKDEV_CON_ID("pioA", &pioA_clk), 235 CLKDEV_CON_ID("pioA", &pioA_clk),
236 CLKDEV_CON_ID("pioB", &pioB_clk), 236 CLKDEV_CON_ID("pioB", &pioB_clk),
237 CLKDEV_CON_ID("pioC", &pioC_clk), 237 CLKDEV_CON_ID("pioC", &pioC_clk),
238 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
239 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
240 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
238}; 241};
239 242
240static struct clk_lookup usart_clocks_lookups[] = { 243static struct clk_lookup usart_clocks_lookups[] = {
@@ -390,10 +393,10 @@ static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
390 0, /* Advanced Interrupt Controller */ 393 0, /* Advanced Interrupt Controller */
391}; 394};
392 395
393struct at91_init_soc __initdata at91sam9260_soc = { 396AT91_SOC_START(sam9260)
394 .map_io = at91sam9260_map_io, 397 .map_io = at91sam9260_map_io,
395 .default_irq_priority = at91sam9260_default_irq_priority, 398 .default_irq_priority = at91sam9260_default_irq_priority,
396 .ioremap_registers = at91sam9260_ioremap_registers, 399 .ioremap_registers = at91sam9260_ioremap_registers,
397 .register_clocks = at91sam9260_register_clocks, 400 .register_clocks = at91sam9260_register_clocks,
398 .init = at91sam9260_initialize, 401 .init = at91sam9260_initialize,
399}; 402AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 04295c04b3e0..4d262f346fd9 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -334,10 +334,10 @@ static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
334 0, /* Advanced Interrupt Controller */ 334 0, /* Advanced Interrupt Controller */
335}; 335};
336 336
337struct at91_init_soc __initdata at91sam9261_soc = { 337AT91_SOC_START(sam9261)
338 .map_io = at91sam9261_map_io, 338 .map_io = at91sam9261_map_io,
339 .default_irq_priority = at91sam9261_default_irq_priority, 339 .default_irq_priority = at91sam9261_default_irq_priority,
340 .ioremap_registers = at91sam9261_ioremap_registers, 340 .ioremap_registers = at91sam9261_ioremap_registers,
341 .register_clocks = at91sam9261_register_clocks, 341 .register_clocks = at91sam9261_register_clocks,
342 .init = at91sam9261_initialize, 342 .init = at91sam9261_initialize,
343}; 343AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index d6f9c23927c4..448fce1ada15 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -212,6 +212,11 @@ static struct clk_lookup periph_clocks_lookups[] = {
212 CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk), 212 CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
213 CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk), 213 CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
214 CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi_clk), 214 CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi_clk),
215 CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
216 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
217 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioCDE_clk),
218 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCDE_clk),
219 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCDE_clk),
215}; 220};
216 221
217static struct clk_lookup usart_clocks_lookups[] = { 222static struct clk_lookup usart_clocks_lookups[] = {
@@ -365,10 +370,10 @@ static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
365 0, /* Advanced Interrupt Controller (IRQ1) */ 370 0, /* Advanced Interrupt Controller (IRQ1) */
366}; 371};
367 372
368struct at91_init_soc __initdata at91sam9263_soc = { 373AT91_SOC_START(sam9263)
369 .map_io = at91sam9263_map_io, 374 .map_io = at91sam9263_map_io,
370 .default_irq_priority = at91sam9263_default_irq_priority, 375 .default_irq_priority = at91sam9263_default_irq_priority,
371 .ioremap_registers = at91sam9263_ioremap_registers, 376 .ioremap_registers = at91sam9263_ioremap_registers,
372 .register_clocks = at91sam9263_register_clocks, 377 .register_clocks = at91sam9263_register_clocks,
373 .init = at91sam9263_initialize, 378 .init = at91sam9263_initialize,
374}; 379AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 84af1b506d92..e6dd371d9f56 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -260,6 +260,12 @@ static struct clk_lookup periph_clocks_lookups[] = {
260 CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk), 260 CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
261 /* fake hclk clock */ 261 /* fake hclk clock */
262 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk), 262 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
263 CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
264 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
265 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk),
266 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioDE_clk),
267 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioDE_clk),
268
263 CLKDEV_CON_ID("pioA", &pioA_clk), 269 CLKDEV_CON_ID("pioA", &pioA_clk),
264 CLKDEV_CON_ID("pioB", &pioB_clk), 270 CLKDEV_CON_ID("pioB", &pioB_clk),
265 CLKDEV_CON_ID("pioC", &pioC_clk), 271 CLKDEV_CON_ID("pioC", &pioC_clk),
@@ -409,10 +415,10 @@ static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
409 0, /* Advanced Interrupt Controller (IRQ0) */ 415 0, /* Advanced Interrupt Controller (IRQ0) */
410}; 416};
411 417
412struct at91_init_soc __initdata at91sam9g45_soc = { 418AT91_SOC_START(sam9g45)
413 .map_io = at91sam9g45_map_io, 419 .map_io = at91sam9g45_map_io,
414 .default_irq_priority = at91sam9g45_default_irq_priority, 420 .default_irq_priority = at91sam9g45_default_irq_priority,
415 .ioremap_registers = at91sam9g45_ioremap_registers, 421 .ioremap_registers = at91sam9g45_ioremap_registers,
416 .register_clocks = at91sam9g45_register_clocks, 422 .register_clocks = at91sam9g45_register_clocks,
417 .init = at91sam9g45_initialize, 423 .init = at91sam9g45_initialize,
418}; 424AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index 732d3d3f4ec5..bf8a083a02ab 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -171,10 +171,10 @@ static struct clk_lookup periph_clocks_lookups[] = {
171 CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk), 171 CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk),
172 CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk), 172 CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
173 CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk), 173 CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
174 CLKDEV_CON_ID("pioA", &pioAB_clk), 174 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
175 CLKDEV_CON_ID("pioB", &pioAB_clk), 175 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
176 CLKDEV_CON_ID("pioC", &pioCD_clk), 176 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
177 CLKDEV_CON_ID("pioD", &pioCD_clk), 177 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCD_clk),
178 /* additional fake clock for macb_hclk */ 178 /* additional fake clock for macb_hclk */
179 CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &uhp_clk), 179 CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &uhp_clk),
180 CLKDEV_CON_DEV_ID("ohci_clk", "500000.ohci", &uhp_clk), 180 CLKDEV_CON_DEV_ID("ohci_clk", "500000.ohci", &uhp_clk),
@@ -223,13 +223,10 @@ static void __init at91sam9n12_map_io(void)
223void __init at91sam9n12_initialize(void) 223void __init at91sam9n12_initialize(void)
224{ 224{
225 at91_extern_irq = (1 << AT91SAM9N12_ID_IRQ0); 225 at91_extern_irq = (1 << AT91SAM9N12_ID_IRQ0);
226
227 /* Register GPIO subsystem (using DT) */
228 at91_gpio_init(NULL, 0);
229} 226}
230 227
231struct at91_init_soc __initdata at91sam9n12_soc = { 228AT91_SOC_START(sam9n12)
232 .map_io = at91sam9n12_map_io, 229 .map_io = at91sam9n12_map_io,
233 .register_clocks = at91sam9n12_register_clocks, 230 .register_clocks = at91sam9n12_register_clocks,
234 .init = at91sam9n12_initialize, 231 .init = at91sam9n12_initialize,
235}; 232AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index 72e908412222..cbe72e44c13f 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -338,10 +338,10 @@ static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
338 0, /* Advanced Interrupt Controller */ 338 0, /* Advanced Interrupt Controller */
339}; 339};
340 340
341struct at91_init_soc __initdata at91sam9rl_soc = { 341AT91_SOC_START(sam9rl)
342 .map_io = at91sam9rl_map_io, 342 .map_io = at91sam9rl_map_io,
343 .default_irq_priority = at91sam9rl_default_irq_priority, 343 .default_irq_priority = at91sam9rl_default_irq_priority,
344 .ioremap_registers = at91sam9rl_ioremap_registers, 344 .ioremap_registers = at91sam9rl_ioremap_registers,
345 .register_clocks = at91sam9rl_register_clocks, 345 .register_clocks = at91sam9rl_register_clocks,
346 .init = at91sam9rl_initialize, 346 .init = at91sam9rl_initialize,
347}; 347AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index e5035380dcbc..56d13a4950a7 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -234,10 +234,10 @@ static struct clk_lookup periph_clocks_lookups[] = {
234 CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk), 234 CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
235 CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk), 235 CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
236 CLKDEV_CON_DEV_ID(NULL, "f8018000.i2c", &twi2_clk), 236 CLKDEV_CON_DEV_ID(NULL, "f8018000.i2c", &twi2_clk),
237 CLKDEV_CON_ID("pioA", &pioAB_clk), 237 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
238 CLKDEV_CON_ID("pioB", &pioAB_clk), 238 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
239 CLKDEV_CON_ID("pioC", &pioCD_clk), 239 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
240 CLKDEV_CON_ID("pioD", &pioCD_clk), 240 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCD_clk),
241 /* additional fake clock for macb_hclk */ 241 /* additional fake clock for macb_hclk */
242 CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb0_clk), 242 CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb0_clk),
243 CLKDEV_CON_DEV_ID("hclk", "f8030000.ethernet", &macb1_clk), 243 CLKDEV_CON_DEV_ID("hclk", "f8030000.ethernet", &macb1_clk),
@@ -313,18 +313,11 @@ static void __init at91sam9x5_map_io(void)
313 at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE); 313 at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE);
314} 314}
315 315
316void __init at91sam9x5_initialize(void)
317{
318 /* Register GPIO subsystem (using DT) */
319 at91_gpio_init(NULL, 0);
320}
321
322/* -------------------------------------------------------------------- 316/* --------------------------------------------------------------------
323 * Interrupt initialization 317 * Interrupt initialization
324 * -------------------------------------------------------------------- */ 318 * -------------------------------------------------------------------- */
325 319
326struct at91_init_soc __initdata at91sam9x5_soc = { 320AT91_SOC_START(sam9x5)
327 .map_io = at91sam9x5_map_io, 321 .map_io = at91sam9x5_map_io,
328 .register_clocks = at91sam9x5_register_clocks, 322 .register_clocks = at91sam9x5_register_clocks,
329 .init = at91sam9x5_initialize, 323AT91_SOC_END
330};
diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c
index e8f45c4e0ea8..3b6a94820fa0 100644
--- a/arch/arm/mach-at91/board-dt.c
+++ b/arch/arm/mach-at91/board-dt.c
@@ -30,8 +30,6 @@
30static const struct of_device_id irq_of_match[] __initconst = { 30static const struct of_device_id irq_of_match[] __initconst = {
31 31
32 { .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init }, 32 { .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
33 { .compatible = "atmel,at91rm9200-gpio", .data = at91_gpio_of_irq_setup },
34 { .compatible = "atmel,at91sam9x5-gpio", .data = at91_gpio_of_irq_setup },
35 { /*sentinel*/ } 33 { /*sentinel*/ }
36}; 34};
37 35
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index be42cf0e74bd..c5d7e1e9d757 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -23,8 +23,6 @@
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/irqdomain.h> 24#include <linux/irqdomain.h>
25#include <linux/of_address.h> 25#include <linux/of_address.h>
26#include <linux/of_irq.h>
27#include <linux/of_gpio.h>
28 26
29#include <asm/mach/irq.h> 27#include <asm/mach/irq.h>
30 28
@@ -33,6 +31,8 @@
33 31
34#include "generic.h" 32#include "generic.h"
35 33
34#define MAX_NB_GPIO_PER_BANK 32
35
36struct at91_gpio_chip { 36struct at91_gpio_chip {
37 struct gpio_chip chip; 37 struct gpio_chip chip;
38 struct at91_gpio_chip *next; /* Bank sharing same clock */ 38 struct at91_gpio_chip *next; /* Bank sharing same clock */
@@ -46,6 +46,7 @@ struct at91_gpio_chip {
46 46
47#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip) 47#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
48 48
49static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset);
49static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip); 50static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip);
50static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val); 51static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val);
51static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset); 52static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset);
@@ -55,26 +56,27 @@ static int at91_gpiolib_direction_input(struct gpio_chip *chip,
55 unsigned offset); 56 unsigned offset);
56static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset); 57static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset);
57 58
58#define AT91_GPIO_CHIP(name, nr_gpio) \ 59#define AT91_GPIO_CHIP(name) \
59 { \ 60 { \
60 .chip = { \ 61 .chip = { \
61 .label = name, \ 62 .label = name, \
63 .request = at91_gpiolib_request, \
62 .direction_input = at91_gpiolib_direction_input, \ 64 .direction_input = at91_gpiolib_direction_input, \
63 .direction_output = at91_gpiolib_direction_output, \ 65 .direction_output = at91_gpiolib_direction_output, \
64 .get = at91_gpiolib_get, \ 66 .get = at91_gpiolib_get, \
65 .set = at91_gpiolib_set, \ 67 .set = at91_gpiolib_set, \
66 .dbg_show = at91_gpiolib_dbg_show, \ 68 .dbg_show = at91_gpiolib_dbg_show, \
67 .to_irq = at91_gpiolib_to_irq, \ 69 .to_irq = at91_gpiolib_to_irq, \
68 .ngpio = nr_gpio, \ 70 .ngpio = MAX_NB_GPIO_PER_BANK, \
69 }, \ 71 }, \
70 } 72 }
71 73
72static struct at91_gpio_chip gpio_chip[] = { 74static struct at91_gpio_chip gpio_chip[] = {
73 AT91_GPIO_CHIP("pioA", 32), 75 AT91_GPIO_CHIP("pioA"),
74 AT91_GPIO_CHIP("pioB", 32), 76 AT91_GPIO_CHIP("pioB"),
75 AT91_GPIO_CHIP("pioC", 32), 77 AT91_GPIO_CHIP("pioC"),
76 AT91_GPIO_CHIP("pioD", 32), 78 AT91_GPIO_CHIP("pioD"),
77 AT91_GPIO_CHIP("pioE", 32), 79 AT91_GPIO_CHIP("pioE"),
78}; 80};
79 81
80static int gpio_banks; 82static int gpio_banks;
@@ -89,7 +91,7 @@ static unsigned long at91_gpio_caps;
89 91
90static inline void __iomem *pin_to_controller(unsigned pin) 92static inline void __iomem *pin_to_controller(unsigned pin)
91{ 93{
92 pin /= 32; 94 pin /= MAX_NB_GPIO_PER_BANK;
93 if (likely(pin < gpio_banks)) 95 if (likely(pin < gpio_banks))
94 return gpio_chip[pin].regbase; 96 return gpio_chip[pin].regbase;
95 97
@@ -98,7 +100,7 @@ static inline void __iomem *pin_to_controller(unsigned pin)
98 100
99static inline unsigned pin_to_mask(unsigned pin) 101static inline unsigned pin_to_mask(unsigned pin)
100{ 102{
101 return 1 << (pin % 32); 103 return 1 << (pin % MAX_NB_GPIO_PER_BANK);
102} 104}
103 105
104 106
@@ -713,80 +715,6 @@ postcore_initcall(at91_gpio_debugfs_init);
713 */ 715 */
714static struct lock_class_key gpio_lock_class; 716static struct lock_class_key gpio_lock_class;
715 717
716#if defined(CONFIG_OF)
717static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq,
718 irq_hw_number_t hw)
719{
720 struct at91_gpio_chip *at91_gpio = h->host_data;
721
722 irq_set_lockdep_class(virq, &gpio_lock_class);
723
724 /*
725 * Can use the "simple" and not "edge" handler since it's
726 * shorter, and the AIC handles interrupts sanely.
727 */
728 irq_set_chip_and_handler(virq, &gpio_irqchip,
729 handle_simple_irq);
730 set_irq_flags(virq, IRQF_VALID);
731 irq_set_chip_data(virq, at91_gpio);
732
733 return 0;
734}
735
736static struct irq_domain_ops at91_gpio_ops = {
737 .map = at91_gpio_irq_map,
738 .xlate = irq_domain_xlate_twocell,
739};
740
741int __init at91_gpio_of_irq_setup(struct device_node *node,
742 struct device_node *parent)
743{
744 struct at91_gpio_chip *prev = NULL;
745 int alias_idx = of_alias_get_id(node, "gpio");
746 struct at91_gpio_chip *at91_gpio = &gpio_chip[alias_idx];
747
748 /* Setup proper .irq_set_type function */
749 if (has_pio3())
750 gpio_irqchip.irq_set_type = alt_gpio_irq_type;
751 else
752 gpio_irqchip.irq_set_type = gpio_irq_type;
753
754 /* Disable irqs of this PIO controller */
755 __raw_writel(~0, at91_gpio->regbase + PIO_IDR);
756
757 /* Setup irq domain */
758 at91_gpio->domain = irq_domain_add_linear(node, at91_gpio->chip.ngpio,
759 &at91_gpio_ops, at91_gpio);
760 if (!at91_gpio->domain)
761 panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n",
762 at91_gpio->pioc_idx);
763
764 /* Setup chained handler */
765 if (at91_gpio->pioc_idx)
766 prev = &gpio_chip[at91_gpio->pioc_idx - 1];
767
768 /* The toplevel handler handles one bank of GPIOs, except
769 * on some SoC it can handles up to three...
770 * We only set up the handler for the first of the list.
771 */
772 if (prev && prev->next == at91_gpio)
773 return 0;
774
775 at91_gpio->pioc_virq = irq_create_mapping(irq_find_host(parent),
776 at91_gpio->pioc_hwirq);
777 irq_set_chip_data(at91_gpio->pioc_virq, at91_gpio);
778 irq_set_chained_handler(at91_gpio->pioc_virq, gpio_irq_handler);
779
780 return 0;
781}
782#else
783int __init at91_gpio_of_irq_setup(struct device_node *node,
784 struct device_node *parent)
785{
786 return -EINVAL;
787}
788#endif
789
790/* 718/*
791 * irqdomain initialization: pile up irqdomains on top of AIC range 719 * irqdomain initialization: pile up irqdomains on top of AIC range
792 */ 720 */
@@ -862,6 +790,16 @@ void __init at91_gpio_irq_setup(void)
862} 790}
863 791
864/* gpiolib support */ 792/* gpiolib support */
793static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset)
794{
795 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
796 void __iomem *pio = at91_gpio->regbase;
797 unsigned mask = 1 << offset;
798
799 __raw_writel(mask, pio + PIO_PER);
800 return 0;
801}
802
865static int at91_gpiolib_direction_input(struct gpio_chip *chip, 803static int at91_gpiolib_direction_input(struct gpio_chip *chip,
866 unsigned offset) 804 unsigned offset)
867{ 805{
@@ -975,81 +913,11 @@ err:
975 return -EINVAL; 913 return -EINVAL;
976} 914}
977 915
978#ifdef CONFIG_OF_GPIO
979static void __init of_at91_gpio_init_one(struct device_node *np)
980{
981 int alias_idx;
982 struct at91_gpio_chip *at91_gpio;
983
984 if (!np)
985 return;
986
987 alias_idx = of_alias_get_id(np, "gpio");
988 if (alias_idx >= MAX_GPIO_BANKS) {
989 pr_err("at91_gpio, failed alias idx(%d) > MAX_GPIO_BANKS(%d), ignoring.\n",
990 alias_idx, MAX_GPIO_BANKS);
991 return;
992 }
993
994 at91_gpio = &gpio_chip[alias_idx];
995 at91_gpio->chip.base = alias_idx * at91_gpio->chip.ngpio;
996
997 at91_gpio->regbase = of_iomap(np, 0);
998 if (!at91_gpio->regbase) {
999 pr_err("at91_gpio.%d, failed to map registers, ignoring.\n",
1000 alias_idx);
1001 return;
1002 }
1003
1004 /* Get the interrupts property */
1005 if (of_property_read_u32(np, "interrupts", &at91_gpio->pioc_hwirq)) {
1006 pr_err("at91_gpio.%d, failed to get interrupts property, ignoring.\n",
1007 alias_idx);
1008 goto ioremap_err;
1009 }
1010
1011 /* Get capabilities from compatibility property */
1012 if (of_device_is_compatible(np, "atmel,at91sam9x5-gpio"))
1013 at91_gpio_caps |= AT91_GPIO_CAP_PIO3;
1014
1015 /* Setup clock */
1016 if (at91_gpio_setup_clk(alias_idx))
1017 goto ioremap_err;
1018
1019 at91_gpio->chip.of_node = np;
1020 gpio_banks = max(gpio_banks, alias_idx + 1);
1021 at91_gpio->pioc_idx = alias_idx;
1022 return;
1023
1024ioremap_err:
1025 iounmap(at91_gpio->regbase);
1026}
1027
1028static int __init of_at91_gpio_init(void)
1029{
1030 struct device_node *np = NULL;
1031
1032 /*
1033 * This isn't ideal, but it gets things hooked up until this
1034 * driver is converted into a platform_device
1035 */
1036 for_each_compatible_node(np, NULL, "atmel,at91rm9200-gpio")
1037 of_at91_gpio_init_one(np);
1038
1039 return gpio_banks > 0 ? 0 : -EINVAL;
1040}
1041#else
1042static int __init of_at91_gpio_init(void)
1043{
1044 return -EINVAL;
1045}
1046#endif
1047
1048static void __init at91_gpio_init_one(int idx, u32 regbase, int pioc_hwirq) 916static void __init at91_gpio_init_one(int idx, u32 regbase, int pioc_hwirq)
1049{ 917{
1050 struct at91_gpio_chip *at91_gpio = &gpio_chip[idx]; 918 struct at91_gpio_chip *at91_gpio = &gpio_chip[idx];
1051 919
1052 at91_gpio->chip.base = idx * at91_gpio->chip.ngpio; 920 at91_gpio->chip.base = idx * MAX_NB_GPIO_PER_BANK;
1053 at91_gpio->pioc_hwirq = pioc_hwirq; 921 at91_gpio->pioc_hwirq = pioc_hwirq;
1054 at91_gpio->pioc_idx = idx; 922 at91_gpio->pioc_idx = idx;
1055 923
@@ -1079,11 +947,11 @@ void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
1079 947
1080 BUG_ON(nr_banks > MAX_GPIO_BANKS); 948 BUG_ON(nr_banks > MAX_GPIO_BANKS);
1081 949
1082 if (of_at91_gpio_init() < 0) { 950 if (of_have_populated_dt())
1083 /* No GPIO controller found in device tree */ 951 return;
1084 for (i = 0; i < nr_banks; i++) 952
1085 at91_gpio_init_one(i, data[i].regbase, data[i].id); 953 for (i = 0; i < nr_banks; i++)
1086 } 954 at91_gpio_init_one(i, data[i].regbase, data[i].id);
1087 955
1088 for (i = 0; i < gpio_banks; i++) { 956 for (i = 0; i < gpio_banks; i++) {
1089 at91_gpio = &gpio_chip[i]; 957 at91_gpio = &gpio_chip[i];
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 0b32c81730a5..80f4bfd913b3 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -10,6 +10,7 @@
10#include <linux/mm.h> 10#include <linux/mm.h>
11#include <linux/pm.h> 11#include <linux/pm.h>
12#include <linux/of_address.h> 12#include <linux/of_address.h>
13#include <linux/pinctrl/machine.h>
13 14
14#include <asm/system_misc.h> 15#include <asm/system_misc.h>
15#include <asm/mach/map.h> 16#include <asm/mach/map.h>
@@ -448,7 +449,8 @@ void __init at91_dt_initialize(void)
448 /* Register the processor-specific clocks */ 449 /* Register the processor-specific clocks */
449 at91_boot_soc.register_clocks(); 450 at91_boot_soc.register_clocks();
450 451
451 at91_boot_soc.init(); 452 if (at91_boot_soc.init)
453 at91_boot_soc.init();
452} 454}
453#endif 455#endif
454 456
@@ -463,4 +465,6 @@ void __init at91_initialize(unsigned long main_clock)
463 at91_boot_soc.register_clocks(); 465 at91_boot_soc.register_clocks();
464 466
465 at91_boot_soc.init(); 467 at91_boot_soc.init();
468
469 pinctrl_provide_dummies();
466} 470}
diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h
index a9cfeb153719..9c6d3d4f9a23 100644
--- a/arch/arm/mach-at91/soc.h
+++ b/arch/arm/mach-at91/soc.h
@@ -5,6 +5,7 @@
5 */ 5 */
6 6
7struct at91_init_soc { 7struct at91_init_soc {
8 int builtin;
8 unsigned int *default_irq_priority; 9 unsigned int *default_irq_priority;
9 void (*map_io)(void); 10 void (*map_io)(void);
10 void (*ioremap_registers)(void); 11 void (*ioremap_registers)(void);
@@ -22,9 +23,18 @@ extern struct at91_init_soc at91sam9rl_soc;
22extern struct at91_init_soc at91sam9x5_soc; 23extern struct at91_init_soc at91sam9x5_soc;
23extern struct at91_init_soc at91sam9n12_soc; 24extern struct at91_init_soc at91sam9n12_soc;
24 25
26#define AT91_SOC_START(_name) \
27struct at91_init_soc __initdata at91##_name##_soc \
28 __used \
29 = { \
30 .builtin = 1, \
31
32#define AT91_SOC_END \
33};
34
25static inline int at91_soc_is_enabled(void) 35static inline int at91_soc_is_enabled(void)
26{ 36{
27 return at91_boot_soc.init != NULL; 37 return at91_boot_soc.builtin;
28} 38}
29 39
30#if !defined(CONFIG_SOC_AT91RM9200) 40#if !defined(CONFIG_SOC_AT91RM9200)
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-13 08:12:25 -0500