diff options
Diffstat (limited to 'arch')
135 files changed, 326 insertions, 322 deletions
diff --git a/arch/alpha/kernel/irq.c b/arch/alpha/kernel/irq.c index da677f829f76..ec9d243d42c9 100644 --- a/arch/alpha/kernel/irq.c +++ b/arch/alpha/kernel/irq.c | |||
@@ -49,7 +49,7 @@ select_smp_affinity(unsigned int irq) | |||
49 | static int last_cpu; | 49 | static int last_cpu; |
50 | int cpu = last_cpu + 1; | 50 | int cpu = last_cpu + 1; |
51 | 51 | ||
52 | if (!irq_desc[irq].handler->set_affinity || irq_user_affinity[irq]) | 52 | if (!irq_desc[irq].chip->set_affinity || irq_user_affinity[irq]) |
53 | return 1; | 53 | return 1; |
54 | 54 | ||
55 | while (!cpu_possible(cpu)) | 55 | while (!cpu_possible(cpu)) |
@@ -57,7 +57,7 @@ select_smp_affinity(unsigned int irq) | |||
57 | last_cpu = cpu; | 57 | last_cpu = cpu; |
58 | 58 | ||
59 | irq_affinity[irq] = cpumask_of_cpu(cpu); | 59 | irq_affinity[irq] = cpumask_of_cpu(cpu); |
60 | irq_desc[irq].handler->set_affinity(irq, cpumask_of_cpu(cpu)); | 60 | irq_desc[irq].chip->set_affinity(irq, cpumask_of_cpu(cpu)); |
61 | return 0; | 61 | return 0; |
62 | } | 62 | } |
63 | #endif /* CONFIG_SMP */ | 63 | #endif /* CONFIG_SMP */ |
@@ -93,7 +93,7 @@ show_interrupts(struct seq_file *p, void *v) | |||
93 | for_each_online_cpu(j) | 93 | for_each_online_cpu(j) |
94 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[irq]); | 94 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[irq]); |
95 | #endif | 95 | #endif |
96 | seq_printf(p, " %14s", irq_desc[irq].handler->typename); | 96 | seq_printf(p, " %14s", irq_desc[irq].chip->typename); |
97 | seq_printf(p, " %c%s", | 97 | seq_printf(p, " %c%s", |
98 | (action->flags & SA_INTERRUPT)?'+':' ', | 98 | (action->flags & SA_INTERRUPT)?'+':' ', |
99 | action->name); | 99 | action->name); |
diff --git a/arch/alpha/kernel/irq_alpha.c b/arch/alpha/kernel/irq_alpha.c index 9d34ce26e5ef..f20f2dff9c43 100644 --- a/arch/alpha/kernel/irq_alpha.c +++ b/arch/alpha/kernel/irq_alpha.c | |||
@@ -233,7 +233,7 @@ void __init | |||
233 | init_rtc_irq(void) | 233 | init_rtc_irq(void) |
234 | { | 234 | { |
235 | irq_desc[RTC_IRQ].status = IRQ_DISABLED; | 235 | irq_desc[RTC_IRQ].status = IRQ_DISABLED; |
236 | irq_desc[RTC_IRQ].handler = &rtc_irq_type; | 236 | irq_desc[RTC_IRQ].chip = &rtc_irq_type; |
237 | setup_irq(RTC_IRQ, &timer_irqaction); | 237 | setup_irq(RTC_IRQ, &timer_irqaction); |
238 | } | 238 | } |
239 | 239 | ||
diff --git a/arch/alpha/kernel/irq_i8259.c b/arch/alpha/kernel/irq_i8259.c index b188683b83fd..ac893bd48036 100644 --- a/arch/alpha/kernel/irq_i8259.c +++ b/arch/alpha/kernel/irq_i8259.c | |||
@@ -109,7 +109,7 @@ init_i8259a_irqs(void) | |||
109 | 109 | ||
110 | for (i = 0; i < 16; i++) { | 110 | for (i = 0; i < 16; i++) { |
111 | irq_desc[i].status = IRQ_DISABLED; | 111 | irq_desc[i].status = IRQ_DISABLED; |
112 | irq_desc[i].handler = &i8259a_irq_type; | 112 | irq_desc[i].chip = &i8259a_irq_type; |
113 | } | 113 | } |
114 | 114 | ||
115 | setup_irq(2, &cascade); | 115 | setup_irq(2, &cascade); |
diff --git a/arch/alpha/kernel/irq_pyxis.c b/arch/alpha/kernel/irq_pyxis.c index 146a20b9e3d5..3b581415bab0 100644 --- a/arch/alpha/kernel/irq_pyxis.c +++ b/arch/alpha/kernel/irq_pyxis.c | |||
@@ -120,7 +120,7 @@ init_pyxis_irqs(unsigned long ignore_mask) | |||
120 | if ((ignore_mask >> i) & 1) | 120 | if ((ignore_mask >> i) & 1) |
121 | continue; | 121 | continue; |
122 | irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; | 122 | irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; |
123 | irq_desc[i].handler = &pyxis_irq_type; | 123 | irq_desc[i].chip = &pyxis_irq_type; |
124 | } | 124 | } |
125 | 125 | ||
126 | setup_irq(16+7, &isa_cascade_irqaction); | 126 | setup_irq(16+7, &isa_cascade_irqaction); |
diff --git a/arch/alpha/kernel/irq_srm.c b/arch/alpha/kernel/irq_srm.c index 0a87e466918c..8e4d121f84cc 100644 --- a/arch/alpha/kernel/irq_srm.c +++ b/arch/alpha/kernel/irq_srm.c | |||
@@ -67,7 +67,7 @@ init_srm_irqs(long max, unsigned long ignore_mask) | |||
67 | if (i < 64 && ((ignore_mask >> i) & 1)) | 67 | if (i < 64 && ((ignore_mask >> i) & 1)) |
68 | continue; | 68 | continue; |
69 | irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; | 69 | irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; |
70 | irq_desc[i].handler = &srm_irq_type; | 70 | irq_desc[i].chip = &srm_irq_type; |
71 | } | 71 | } |
72 | } | 72 | } |
73 | 73 | ||
diff --git a/arch/alpha/kernel/sys_alcor.c b/arch/alpha/kernel/sys_alcor.c index d7f0e97fe56f..1a1a2c7a3d94 100644 --- a/arch/alpha/kernel/sys_alcor.c +++ b/arch/alpha/kernel/sys_alcor.c | |||
@@ -144,7 +144,7 @@ alcor_init_irq(void) | |||
144 | if (i >= 16+20 && i <= 16+30) | 144 | if (i >= 16+20 && i <= 16+30) |
145 | continue; | 145 | continue; |
146 | irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; | 146 | irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; |
147 | irq_desc[i].handler = &alcor_irq_type; | 147 | irq_desc[i].chip = &alcor_irq_type; |
148 | } | 148 | } |
149 | i8259a_irq_type.ack = alcor_isa_mask_and_ack_irq; | 149 | i8259a_irq_type.ack = alcor_isa_mask_and_ack_irq; |
150 | 150 | ||
diff --git a/arch/alpha/kernel/sys_cabriolet.c b/arch/alpha/kernel/sys_cabriolet.c index 8e3374d34c95..8c9e443d93ad 100644 --- a/arch/alpha/kernel/sys_cabriolet.c +++ b/arch/alpha/kernel/sys_cabriolet.c | |||
@@ -124,7 +124,7 @@ common_init_irq(void (*srm_dev_int)(unsigned long v, struct pt_regs *r)) | |||
124 | 124 | ||
125 | for (i = 16; i < 35; ++i) { | 125 | for (i = 16; i < 35; ++i) { |
126 | irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; | 126 | irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; |
127 | irq_desc[i].handler = &cabriolet_irq_type; | 127 | irq_desc[i].chip = &cabriolet_irq_type; |
128 | } | 128 | } |
129 | } | 129 | } |
130 | 130 | ||
diff --git a/arch/alpha/kernel/sys_dp264.c b/arch/alpha/kernel/sys_dp264.c index d5da6b1b28ee..b28c8f1c6e10 100644 --- a/arch/alpha/kernel/sys_dp264.c +++ b/arch/alpha/kernel/sys_dp264.c | |||
@@ -300,7 +300,7 @@ init_tsunami_irqs(struct hw_interrupt_type * ops, int imin, int imax) | |||
300 | long i; | 300 | long i; |
301 | for (i = imin; i <= imax; ++i) { | 301 | for (i = imin; i <= imax; ++i) { |
302 | irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; | 302 | irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; |
303 | irq_desc[i].handler = ops; | 303 | irq_desc[i].chip = ops; |
304 | } | 304 | } |
305 | } | 305 | } |
306 | 306 | ||
diff --git a/arch/alpha/kernel/sys_eb64p.c b/arch/alpha/kernel/sys_eb64p.c index 61a79c354f0b..aeb8e0277905 100644 --- a/arch/alpha/kernel/sys_eb64p.c +++ b/arch/alpha/kernel/sys_eb64p.c | |||
@@ -137,7 +137,7 @@ eb64p_init_irq(void) | |||
137 | 137 | ||
138 | for (i = 16; i < 32; ++i) { | 138 | for (i = 16; i < 32; ++i) { |
139 | irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; | 139 | irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; |
140 | irq_desc[i].handler = &eb64p_irq_type; | 140 | irq_desc[i].chip = &eb64p_irq_type; |
141 | } | 141 | } |
142 | 142 | ||
143 | common_init_isa_dma(); | 143 | common_init_isa_dma(); |
diff --git a/arch/alpha/kernel/sys_eiger.c b/arch/alpha/kernel/sys_eiger.c index bd6e5f0e43c7..64a785baf53a 100644 --- a/arch/alpha/kernel/sys_eiger.c +++ b/arch/alpha/kernel/sys_eiger.c | |||
@@ -154,7 +154,7 @@ eiger_init_irq(void) | |||
154 | 154 | ||
155 | for (i = 16; i < 128; ++i) { | 155 | for (i = 16; i < 128; ++i) { |
156 | irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; | 156 | irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; |
157 | irq_desc[i].handler = &eiger_irq_type; | 157 | irq_desc[i].chip = &eiger_irq_type; |
158 | } | 158 | } |
159 | } | 159 | } |
160 | 160 | ||
diff --git a/arch/alpha/kernel/sys_jensen.c b/arch/alpha/kernel/sys_jensen.c index fcabb7c96a16..0148e095638f 100644 --- a/arch/alpha/kernel/sys_jensen.c +++ b/arch/alpha/kernel/sys_jensen.c | |||
@@ -206,11 +206,11 @@ jensen_init_irq(void) | |||
206 | { | 206 | { |
207 | init_i8259a_irqs(); | 207 | init_i8259a_irqs(); |
208 | 208 | ||
209 | irq_desc[1].handler = &jensen_local_irq_type; | 209 | irq_desc[1].chip = &jensen_local_irq_type; |
210 | irq_desc[4].handler = &jensen_local_irq_type; | 210 | irq_desc[4].chip = &jensen_local_irq_type; |
211 | irq_desc[3].handler = &jensen_local_irq_type; | 211 | irq_desc[3].chip = &jensen_local_irq_type; |
212 | irq_desc[7].handler = &jensen_local_irq_type; | 212 | irq_desc[7].chip = &jensen_local_irq_type; |
213 | irq_desc[9].handler = &jensen_local_irq_type; | 213 | irq_desc[9].chip = &jensen_local_irq_type; |
214 | 214 | ||
215 | common_init_isa_dma(); | 215 | common_init_isa_dma(); |
216 | } | 216 | } |
diff --git a/arch/alpha/kernel/sys_marvel.c b/arch/alpha/kernel/sys_marvel.c index e32fee505220..36d215954376 100644 --- a/arch/alpha/kernel/sys_marvel.c +++ b/arch/alpha/kernel/sys_marvel.c | |||
@@ -303,7 +303,7 @@ init_io7_irqs(struct io7 *io7, | |||
303 | /* Set up the lsi irqs. */ | 303 | /* Set up the lsi irqs. */ |
304 | for (i = 0; i < 128; ++i) { | 304 | for (i = 0; i < 128; ++i) { |
305 | irq_desc[base + i].status = IRQ_DISABLED | IRQ_LEVEL; | 305 | irq_desc[base + i].status = IRQ_DISABLED | IRQ_LEVEL; |
306 | irq_desc[base + i].handler = lsi_ops; | 306 | irq_desc[base + i].chip = lsi_ops; |
307 | } | 307 | } |
308 | 308 | ||
309 | /* Disable the implemented irqs in hardware. */ | 309 | /* Disable the implemented irqs in hardware. */ |
@@ -317,7 +317,7 @@ init_io7_irqs(struct io7 *io7, | |||
317 | /* Set up the msi irqs. */ | 317 | /* Set up the msi irqs. */ |
318 | for (i = 128; i < (128 + 512); ++i) { | 318 | for (i = 128; i < (128 + 512); ++i) { |
319 | irq_desc[base + i].status = IRQ_DISABLED | IRQ_LEVEL; | 319 | irq_desc[base + i].status = IRQ_DISABLED | IRQ_LEVEL; |
320 | irq_desc[base + i].handler = msi_ops; | 320 | irq_desc[base + i].chip = msi_ops; |
321 | } | 321 | } |
322 | 322 | ||
323 | for (i = 0; i < 16; ++i) | 323 | for (i = 0; i < 16; ++i) |
@@ -335,7 +335,7 @@ marvel_init_irq(void) | |||
335 | /* Reserve the legacy irqs. */ | 335 | /* Reserve the legacy irqs. */ |
336 | for (i = 0; i < 16; ++i) { | 336 | for (i = 0; i < 16; ++i) { |
337 | irq_desc[i].status = IRQ_DISABLED; | 337 | irq_desc[i].status = IRQ_DISABLED; |
338 | irq_desc[i].handler = &marvel_legacy_irq_type; | 338 | irq_desc[i].chip = &marvel_legacy_irq_type; |
339 | } | 339 | } |
340 | 340 | ||
341 | /* Init the io7 irqs. */ | 341 | /* Init the io7 irqs. */ |
diff --git a/arch/alpha/kernel/sys_mikasa.c b/arch/alpha/kernel/sys_mikasa.c index d78a0daa6168..b741600e3761 100644 --- a/arch/alpha/kernel/sys_mikasa.c +++ b/arch/alpha/kernel/sys_mikasa.c | |||
@@ -117,7 +117,7 @@ mikasa_init_irq(void) | |||
117 | 117 | ||
118 | for (i = 16; i < 32; ++i) { | 118 | for (i = 16; i < 32; ++i) { |
119 | irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; | 119 | irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; |
120 | irq_desc[i].handler = &mikasa_irq_type; | 120 | irq_desc[i].chip = &mikasa_irq_type; |
121 | } | 121 | } |
122 | 122 | ||
123 | init_i8259a_irqs(); | 123 | init_i8259a_irqs(); |
diff --git a/arch/alpha/kernel/sys_noritake.c b/arch/alpha/kernel/sys_noritake.c index 65061f5d7410..55db02d318d7 100644 --- a/arch/alpha/kernel/sys_noritake.c +++ b/arch/alpha/kernel/sys_noritake.c | |||
@@ -139,7 +139,7 @@ noritake_init_irq(void) | |||
139 | 139 | ||
140 | for (i = 16; i < 48; ++i) { | 140 | for (i = 16; i < 48; ++i) { |
141 | irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; | 141 | irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; |
142 | irq_desc[i].handler = &noritake_irq_type; | 142 | irq_desc[i].chip = &noritake_irq_type; |
143 | } | 143 | } |
144 | 144 | ||
145 | init_i8259a_irqs(); | 145 | init_i8259a_irqs(); |
diff --git a/arch/alpha/kernel/sys_rawhide.c b/arch/alpha/kernel/sys_rawhide.c index 05888a02a604..949607e3d6fb 100644 --- a/arch/alpha/kernel/sys_rawhide.c +++ b/arch/alpha/kernel/sys_rawhide.c | |||
@@ -180,7 +180,7 @@ rawhide_init_irq(void) | |||
180 | 180 | ||
181 | for (i = 16; i < 128; ++i) { | 181 | for (i = 16; i < 128; ++i) { |
182 | irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; | 182 | irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; |
183 | irq_desc[i].handler = &rawhide_irq_type; | 183 | irq_desc[i].chip = &rawhide_irq_type; |
184 | } | 184 | } |
185 | 185 | ||
186 | init_i8259a_irqs(); | 186 | init_i8259a_irqs(); |
diff --git a/arch/alpha/kernel/sys_rx164.c b/arch/alpha/kernel/sys_rx164.c index 58404243057b..6ae506052635 100644 --- a/arch/alpha/kernel/sys_rx164.c +++ b/arch/alpha/kernel/sys_rx164.c | |||
@@ -117,7 +117,7 @@ rx164_init_irq(void) | |||
117 | rx164_update_irq_hw(0); | 117 | rx164_update_irq_hw(0); |
118 | for (i = 16; i < 40; ++i) { | 118 | for (i = 16; i < 40; ++i) { |
119 | irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; | 119 | irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; |
120 | irq_desc[i].handler = &rx164_irq_type; | 120 | irq_desc[i].chip = &rx164_irq_type; |
121 | } | 121 | } |
122 | 122 | ||
123 | init_i8259a_irqs(); | 123 | init_i8259a_irqs(); |
diff --git a/arch/alpha/kernel/sys_sable.c b/arch/alpha/kernel/sys_sable.c index a7ff84474ace..24dea40c9bfe 100644 --- a/arch/alpha/kernel/sys_sable.c +++ b/arch/alpha/kernel/sys_sable.c | |||
@@ -537,7 +537,7 @@ sable_lynx_init_irq(int nr_irqs) | |||
537 | 537 | ||
538 | for (i = 0; i < nr_irqs; ++i) { | 538 | for (i = 0; i < nr_irqs; ++i) { |
539 | irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; | 539 | irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; |
540 | irq_desc[i].handler = &sable_lynx_irq_type; | 540 | irq_desc[i].chip = &sable_lynx_irq_type; |
541 | } | 541 | } |
542 | 542 | ||
543 | common_init_isa_dma(); | 543 | common_init_isa_dma(); |
diff --git a/arch/alpha/kernel/sys_takara.c b/arch/alpha/kernel/sys_takara.c index 7955bdfc2db0..2c75cd1fd81a 100644 --- a/arch/alpha/kernel/sys_takara.c +++ b/arch/alpha/kernel/sys_takara.c | |||
@@ -154,7 +154,7 @@ takara_init_irq(void) | |||
154 | 154 | ||
155 | for (i = 16; i < 128; ++i) { | 155 | for (i = 16; i < 128; ++i) { |
156 | irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; | 156 | irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; |
157 | irq_desc[i].handler = &takara_irq_type; | 157 | irq_desc[i].chip = &takara_irq_type; |
158 | } | 158 | } |
159 | 159 | ||
160 | common_init_isa_dma(); | 160 | common_init_isa_dma(); |
diff --git a/arch/alpha/kernel/sys_titan.c b/arch/alpha/kernel/sys_titan.c index 2551fb49ae09..13f3ed8ed7ac 100644 --- a/arch/alpha/kernel/sys_titan.c +++ b/arch/alpha/kernel/sys_titan.c | |||
@@ -189,7 +189,7 @@ init_titan_irqs(struct hw_interrupt_type * ops, int imin, int imax) | |||
189 | long i; | 189 | long i; |
190 | for (i = imin; i <= imax; ++i) { | 190 | for (i = imin; i <= imax; ++i) { |
191 | irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; | 191 | irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; |
192 | irq_desc[i].handler = ops; | 192 | irq_desc[i].chip = ops; |
193 | } | 193 | } |
194 | } | 194 | } |
195 | 195 | ||
diff --git a/arch/alpha/kernel/sys_wildfire.c b/arch/alpha/kernel/sys_wildfire.c index 1553f470246e..22c5798fe083 100644 --- a/arch/alpha/kernel/sys_wildfire.c +++ b/arch/alpha/kernel/sys_wildfire.c | |||
@@ -199,14 +199,14 @@ wildfire_init_irq_per_pca(int qbbno, int pcano) | |||
199 | if (i == 2) | 199 | if (i == 2) |
200 | continue; | 200 | continue; |
201 | irq_desc[i+irq_bias].status = IRQ_DISABLED | IRQ_LEVEL; | 201 | irq_desc[i+irq_bias].status = IRQ_DISABLED | IRQ_LEVEL; |
202 | irq_desc[i+irq_bias].handler = &wildfire_irq_type; | 202 | irq_desc[i+irq_bias].chip = &wildfire_irq_type; |
203 | } | 203 | } |
204 | 204 | ||
205 | irq_desc[36+irq_bias].status = IRQ_DISABLED | IRQ_LEVEL; | 205 | irq_desc[36+irq_bias].status = IRQ_DISABLED | IRQ_LEVEL; |
206 | irq_desc[36+irq_bias].handler = &wildfire_irq_type; | 206 | irq_desc[36+irq_bias].chip = &wildfire_irq_type; |
207 | for (i = 40; i < 64; ++i) { | 207 | for (i = 40; i < 64; ++i) { |
208 | irq_desc[i+irq_bias].status = IRQ_DISABLED | IRQ_LEVEL; | 208 | irq_desc[i+irq_bias].status = IRQ_DISABLED | IRQ_LEVEL; |
209 | irq_desc[i+irq_bias].handler = &wildfire_irq_type; | 209 | irq_desc[i+irq_bias].chip = &wildfire_irq_type; |
210 | } | 210 | } |
211 | 211 | ||
212 | setup_irq(32+irq_bias, &isa_enable); | 212 | setup_irq(32+irq_bias, &isa_enable); |
diff --git a/arch/cris/arch-v10/kernel/irq.c b/arch/cris/arch-v10/kernel/irq.c index 4b368a122015..2d5be93b5197 100644 --- a/arch/cris/arch-v10/kernel/irq.c +++ b/arch/cris/arch-v10/kernel/irq.c | |||
@@ -172,7 +172,7 @@ init_IRQ(void) | |||
172 | 172 | ||
173 | /* Initialize IRQ handler descriptiors. */ | 173 | /* Initialize IRQ handler descriptiors. */ |
174 | for(i = 2; i < NR_IRQS; i++) { | 174 | for(i = 2; i < NR_IRQS; i++) { |
175 | irq_desc[i].handler = &crisv10_irq_type; | 175 | irq_desc[i].chip = &crisv10_irq_type; |
176 | set_int_vector(i, interrupt[i]); | 176 | set_int_vector(i, interrupt[i]); |
177 | } | 177 | } |
178 | 178 | ||
diff --git a/arch/cris/arch-v32/kernel/irq.c b/arch/cris/arch-v32/kernel/irq.c index c78cc2685133..06260874f018 100644 --- a/arch/cris/arch-v32/kernel/irq.c +++ b/arch/cris/arch-v32/kernel/irq.c | |||
@@ -369,7 +369,7 @@ init_IRQ(void) | |||
369 | 369 | ||
370 | /* Point all IRQ's to bad handlers. */ | 370 | /* Point all IRQ's to bad handlers. */ |
371 | for (i = FIRST_IRQ, j = 0; j < NR_IRQS; i++, j++) { | 371 | for (i = FIRST_IRQ, j = 0; j < NR_IRQS; i++, j++) { |
372 | irq_desc[j].handler = &crisv32_irq_type; | 372 | irq_desc[j].chip = &crisv32_irq_type; |
373 | set_exception_vector(i, interrupt[j]); | 373 | set_exception_vector(i, interrupt[j]); |
374 | } | 374 | } |
375 | 375 | ||
diff --git a/arch/cris/kernel/irq.c b/arch/cris/kernel/irq.c index b504def3e346..6547bb646364 100644 --- a/arch/cris/kernel/irq.c +++ b/arch/cris/kernel/irq.c | |||
@@ -69,7 +69,7 @@ int show_interrupts(struct seq_file *p, void *v) | |||
69 | for_each_online_cpu(j) | 69 | for_each_online_cpu(j) |
70 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); | 70 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); |
71 | #endif | 71 | #endif |
72 | seq_printf(p, " %14s", irq_desc[i].handler->typename); | 72 | seq_printf(p, " %14s", irq_desc[i].chip->typename); |
73 | seq_printf(p, " %s", action->name); | 73 | seq_printf(p, " %s", action->name); |
74 | 74 | ||
75 | for (action=action->next; action; action = action->next) | 75 | for (action=action->next; action; action = action->next) |
diff --git a/arch/i386/kernel/i8259.c b/arch/i386/kernel/i8259.c index c1a42feba286..3c6063671a9f 100644 --- a/arch/i386/kernel/i8259.c +++ b/arch/i386/kernel/i8259.c | |||
@@ -132,7 +132,7 @@ void make_8259A_irq(unsigned int irq) | |||
132 | { | 132 | { |
133 | disable_irq_nosync(irq); | 133 | disable_irq_nosync(irq); |
134 | io_apic_irqs &= ~(1<<irq); | 134 | io_apic_irqs &= ~(1<<irq); |
135 | irq_desc[irq].handler = &i8259A_irq_type; | 135 | irq_desc[irq].chip = &i8259A_irq_type; |
136 | enable_irq(irq); | 136 | enable_irq(irq); |
137 | } | 137 | } |
138 | 138 | ||
@@ -386,12 +386,12 @@ void __init init_ISA_irqs (void) | |||
386 | /* | 386 | /* |
387 | * 16 old-style INTA-cycle interrupts: | 387 | * 16 old-style INTA-cycle interrupts: |
388 | */ | 388 | */ |
389 | irq_desc[i].handler = &i8259A_irq_type; | 389 | irq_desc[i].chip = &i8259A_irq_type; |
390 | } else { | 390 | } else { |
391 | /* | 391 | /* |
392 | * 'high' PCI IRQs filled in on demand | 392 | * 'high' PCI IRQs filled in on demand |
393 | */ | 393 | */ |
394 | irq_desc[i].handler = &no_irq_type; | 394 | irq_desc[i].chip = &no_irq_type; |
395 | } | 395 | } |
396 | } | 396 | } |
397 | } | 397 | } |
diff --git a/arch/i386/kernel/io_apic.c b/arch/i386/kernel/io_apic.c index 72ae414e4d49..4a74b696c6a3 100644 --- a/arch/i386/kernel/io_apic.c +++ b/arch/i386/kernel/io_apic.c | |||
@@ -1205,15 +1205,17 @@ static struct hw_interrupt_type ioapic_edge_type; | |||
1205 | #define IOAPIC_EDGE 0 | 1205 | #define IOAPIC_EDGE 0 |
1206 | #define IOAPIC_LEVEL 1 | 1206 | #define IOAPIC_LEVEL 1 |
1207 | 1207 | ||
1208 | static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger) | 1208 | static void ioapic_register_intr(int irq, int vector, unsigned long trigger) |
1209 | { | 1209 | { |
1210 | unsigned idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq; | 1210 | unsigned idx; |
1211 | |||
1212 | idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq; | ||
1211 | 1213 | ||
1212 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || | 1214 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
1213 | trigger == IOAPIC_LEVEL) | 1215 | trigger == IOAPIC_LEVEL) |
1214 | irq_desc[idx].handler = &ioapic_level_type; | 1216 | irq_desc[idx].chip = &ioapic_level_type; |
1215 | else | 1217 | else |
1216 | irq_desc[idx].handler = &ioapic_edge_type; | 1218 | irq_desc[idx].chip = &ioapic_edge_type; |
1217 | set_intr_gate(vector, interrupt[idx]); | 1219 | set_intr_gate(vector, interrupt[idx]); |
1218 | } | 1220 | } |
1219 | 1221 | ||
@@ -1325,7 +1327,7 @@ static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, in | |||
1325 | * The timer IRQ doesn't have to know that behind the | 1327 | * The timer IRQ doesn't have to know that behind the |
1326 | * scene we have a 8259A-master in AEOI mode ... | 1328 | * scene we have a 8259A-master in AEOI mode ... |
1327 | */ | 1329 | */ |
1328 | irq_desc[0].handler = &ioapic_edge_type; | 1330 | irq_desc[0].chip = &ioapic_edge_type; |
1329 | 1331 | ||
1330 | /* | 1332 | /* |
1331 | * Add it to the IO-APIC irq-routing table: | 1333 | * Add it to the IO-APIC irq-routing table: |
@@ -2135,7 +2137,7 @@ static inline void init_IO_APIC_traps(void) | |||
2135 | make_8259A_irq(irq); | 2137 | make_8259A_irq(irq); |
2136 | else | 2138 | else |
2137 | /* Strange. Oh, well.. */ | 2139 | /* Strange. Oh, well.. */ |
2138 | irq_desc[irq].handler = &no_irq_type; | 2140 | irq_desc[irq].chip = &no_irq_type; |
2139 | } | 2141 | } |
2140 | } | 2142 | } |
2141 | } | 2143 | } |
@@ -2351,7 +2353,7 @@ static inline void check_timer(void) | |||
2351 | printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ..."); | 2353 | printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ..."); |
2352 | 2354 | ||
2353 | disable_8259A_irq(0); | 2355 | disable_8259A_irq(0); |
2354 | irq_desc[0].handler = &lapic_irq_type; | 2356 | irq_desc[0].chip = &lapic_irq_type; |
2355 | apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */ | 2357 | apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */ |
2356 | enable_8259A_irq(0); | 2358 | enable_8259A_irq(0); |
2357 | 2359 | ||
diff --git a/arch/i386/kernel/irq.c b/arch/i386/kernel/irq.c index 9eec9435318e..b942a5918dab 100644 --- a/arch/i386/kernel/irq.c +++ b/arch/i386/kernel/irq.c | |||
@@ -249,7 +249,7 @@ int show_interrupts(struct seq_file *p, void *v) | |||
249 | for_each_online_cpu(j) | 249 | for_each_online_cpu(j) |
250 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); | 250 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); |
251 | #endif | 251 | #endif |
252 | seq_printf(p, " %14s", irq_desc[i].handler->typename); | 252 | seq_printf(p, " %14s", irq_desc[i].chip->typename); |
253 | seq_printf(p, " %s", action->name); | 253 | seq_printf(p, " %s", action->name); |
254 | 254 | ||
255 | for (action=action->next; action; action = action->next) | 255 | for (action=action->next; action; action = action->next) |
@@ -296,8 +296,8 @@ void fixup_irqs(cpumask_t map) | |||
296 | printk("Breaking affinity for irq %i\n", irq); | 296 | printk("Breaking affinity for irq %i\n", irq); |
297 | mask = map; | 297 | mask = map; |
298 | } | 298 | } |
299 | if (irq_desc[irq].handler->set_affinity) | 299 | if (irq_desc[irq].chip->set_affinity) |
300 | irq_desc[irq].handler->set_affinity(irq, mask); | 300 | irq_desc[irq].chip->set_affinity(irq, mask); |
301 | else if (irq_desc[irq].action && !(warned++)) | 301 | else if (irq_desc[irq].action && !(warned++)) |
302 | printk("Cannot set affinity for irq %i\n", irq); | 302 | printk("Cannot set affinity for irq %i\n", irq); |
303 | } | 303 | } |
diff --git a/arch/i386/mach-visws/visws_apic.c b/arch/i386/mach-visws/visws_apic.c index 3e64fb721291..c418521dd554 100644 --- a/arch/i386/mach-visws/visws_apic.c +++ b/arch/i386/mach-visws/visws_apic.c | |||
@@ -278,22 +278,22 @@ void init_VISWS_APIC_irqs(void) | |||
278 | irq_desc[i].depth = 1; | 278 | irq_desc[i].depth = 1; |
279 | 279 | ||
280 | if (i == 0) { | 280 | if (i == 0) { |
281 | irq_desc[i].handler = &cobalt_irq_type; | 281 | irq_desc[i].chip = &cobalt_irq_type; |
282 | } | 282 | } |
283 | else if (i == CO_IRQ_IDE0) { | 283 | else if (i == CO_IRQ_IDE0) { |
284 | irq_desc[i].handler = &cobalt_irq_type; | 284 | irq_desc[i].chip = &cobalt_irq_type; |
285 | } | 285 | } |
286 | else if (i == CO_IRQ_IDE1) { | 286 | else if (i == CO_IRQ_IDE1) { |
287 | irq_desc[i].handler = &cobalt_irq_type; | 287 | irq_desc[i].chip = &cobalt_irq_type; |
288 | } | 288 | } |
289 | else if (i == CO_IRQ_8259) { | 289 | else if (i == CO_IRQ_8259) { |
290 | irq_desc[i].handler = &piix4_master_irq_type; | 290 | irq_desc[i].chip = &piix4_master_irq_type; |
291 | } | 291 | } |
292 | else if (i < CO_IRQ_APIC0) { | 292 | else if (i < CO_IRQ_APIC0) { |
293 | irq_desc[i].handler = &piix4_virtual_irq_type; | 293 | irq_desc[i].chip = &piix4_virtual_irq_type; |
294 | } | 294 | } |
295 | else if (IS_CO_APIC(i)) { | 295 | else if (IS_CO_APIC(i)) { |
296 | irq_desc[i].handler = &cobalt_irq_type; | 296 | irq_desc[i].chip = &cobalt_irq_type; |
297 | } | 297 | } |
298 | } | 298 | } |
299 | 299 | ||
diff --git a/arch/i386/mach-voyager/voyager_smp.c b/arch/i386/mach-voyager/voyager_smp.c index 8242af9ebc6f..5b8b579a079f 100644 --- a/arch/i386/mach-voyager/voyager_smp.c +++ b/arch/i386/mach-voyager/voyager_smp.c | |||
@@ -1419,7 +1419,7 @@ smp_intr_init(void) | |||
1419 | * This is for later: first 16 correspond to PC IRQs; next 16 | 1419 | * This is for later: first 16 correspond to PC IRQs; next 16 |
1420 | * are Primary MC IRQs and final 16 are Secondary MC IRQs */ | 1420 | * are Primary MC IRQs and final 16 are Secondary MC IRQs */ |
1421 | for(i = 0; i < 48; i++) | 1421 | for(i = 0; i < 48; i++) |
1422 | irq_desc[i].handler = &vic_irq_type; | 1422 | irq_desc[i].chip = &vic_irq_type; |
1423 | } | 1423 | } |
1424 | 1424 | ||
1425 | /* send a CPI at level cpi to a set of cpus in cpuset (set 1 bit per | 1425 | /* send a CPI at level cpi to a set of cpus in cpuset (set 1 bit per |
diff --git a/arch/ia64/kernel/iosapic.c b/arch/ia64/kernel/iosapic.c index d58c1c5c903a..abb4cb1c831e 100644 --- a/arch/ia64/kernel/iosapic.c +++ b/arch/ia64/kernel/iosapic.c | |||
@@ -660,13 +660,13 @@ register_intr (unsigned int gsi, int vector, unsigned char delivery, | |||
660 | irq_type = &irq_type_iosapic_level; | 660 | irq_type = &irq_type_iosapic_level; |
661 | 661 | ||
662 | idesc = irq_descp(vector); | 662 | idesc = irq_descp(vector); |
663 | if (idesc->handler != irq_type) { | 663 | if (idesc->chip != irq_type) { |
664 | if (idesc->handler != &no_irq_type) | 664 | if (idesc->chip != &no_irq_type) |
665 | printk(KERN_WARNING | 665 | printk(KERN_WARNING |
666 | "%s: changing vector %d from %s to %s\n", | 666 | "%s: changing vector %d from %s to %s\n", |
667 | __FUNCTION__, vector, | 667 | __FUNCTION__, vector, |
668 | idesc->handler->typename, irq_type->typename); | 668 | idesc->chip->typename, irq_type->typename); |
669 | idesc->handler = irq_type; | 669 | idesc->chip = irq_type; |
670 | } | 670 | } |
671 | return 0; | 671 | return 0; |
672 | } | 672 | } |
@@ -903,7 +903,7 @@ iosapic_unregister_intr (unsigned int gsi) | |||
903 | BUG_ON(iosapic_intr_info[vector].count); | 903 | BUG_ON(iosapic_intr_info[vector].count); |
904 | 904 | ||
905 | /* Clear the interrupt controller descriptor */ | 905 | /* Clear the interrupt controller descriptor */ |
906 | idesc->handler = &no_irq_type; | 906 | idesc->chip = &no_irq_type; |
907 | 907 | ||
908 | /* Clear the interrupt information */ | 908 | /* Clear the interrupt information */ |
909 | memset(&iosapic_intr_info[vector], 0, | 909 | memset(&iosapic_intr_info[vector], 0, |
diff --git a/arch/ia64/kernel/irq.c b/arch/ia64/kernel/irq.c index 9c72ea3f6432..2645153dba8a 100644 --- a/arch/ia64/kernel/irq.c +++ b/arch/ia64/kernel/irq.c | |||
@@ -76,7 +76,7 @@ int show_interrupts(struct seq_file *p, void *v) | |||
76 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); | 76 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); |
77 | } | 77 | } |
78 | #endif | 78 | #endif |
79 | seq_printf(p, " %14s", irq_desc[i].handler->typename); | 79 | seq_printf(p, " %14s", irq_desc[i].chip->typename); |
80 | seq_printf(p, " %s", action->name); | 80 | seq_printf(p, " %s", action->name); |
81 | 81 | ||
82 | for (action=action->next; action; action = action->next) | 82 | for (action=action->next; action; action = action->next) |
@@ -144,15 +144,15 @@ static void migrate_irqs(void) | |||
144 | /* | 144 | /* |
145 | * Al three are essential, currently WARN_ON.. maybe panic? | 145 | * Al three are essential, currently WARN_ON.. maybe panic? |
146 | */ | 146 | */ |
147 | if (desc->handler && desc->handler->disable && | 147 | if (desc->chip && desc->chip->disable && |
148 | desc->handler->enable && desc->handler->set_affinity) { | 148 | desc->chip->enable && desc->chip->set_affinity) { |
149 | desc->handler->disable(irq); | 149 | desc->chip->disable(irq); |
150 | desc->handler->set_affinity(irq, mask); | 150 | desc->chip->set_affinity(irq, mask); |
151 | desc->handler->enable(irq); | 151 | desc->chip->enable(irq); |
152 | } else { | 152 | } else { |
153 | WARN_ON((!(desc->handler) || !(desc->handler->disable) || | 153 | WARN_ON((!(desc->chip) || !(desc->chip->disable) || |
154 | !(desc->handler->enable) || | 154 | !(desc->chip->enable) || |
155 | !(desc->handler->set_affinity))); | 155 | !(desc->chip->set_affinity))); |
156 | } | 156 | } |
157 | } | 157 | } |
158 | } | 158 | } |
diff --git a/arch/ia64/kernel/irq_ia64.c b/arch/ia64/kernel/irq_ia64.c index ef9a2b49307a..6d8fc9498ed9 100644 --- a/arch/ia64/kernel/irq_ia64.c +++ b/arch/ia64/kernel/irq_ia64.c | |||
@@ -251,7 +251,7 @@ register_percpu_irq (ia64_vector vec, struct irqaction *action) | |||
251 | if (irq_to_vector(irq) == vec) { | 251 | if (irq_to_vector(irq) == vec) { |
252 | desc = irq_descp(irq); | 252 | desc = irq_descp(irq); |
253 | desc->status |= IRQ_PER_CPU; | 253 | desc->status |= IRQ_PER_CPU; |
254 | desc->handler = &irq_type_ia64_lsapic; | 254 | desc->chip = &irq_type_ia64_lsapic; |
255 | if (action) | 255 | if (action) |
256 | setup_irq(irq, action); | 256 | setup_irq(irq, action); |
257 | } | 257 | } |
diff --git a/arch/ia64/kernel/smpboot.c b/arch/ia64/kernel/smpboot.c index 44e9547878ac..d69288055599 100644 --- a/arch/ia64/kernel/smpboot.c +++ b/arch/ia64/kernel/smpboot.c | |||
@@ -684,9 +684,9 @@ int migrate_platform_irqs(unsigned int cpu) | |||
684 | * polling before making changes. | 684 | * polling before making changes. |
685 | */ | 685 | */ |
686 | if (desc) { | 686 | if (desc) { |
687 | desc->handler->disable(ia64_cpe_irq); | 687 | desc->chip->disable(ia64_cpe_irq); |
688 | desc->handler->set_affinity(ia64_cpe_irq, mask); | 688 | desc->chip->set_affinity(ia64_cpe_irq, mask); |
689 | desc->handler->enable(ia64_cpe_irq); | 689 | desc->chip->enable(ia64_cpe_irq); |
690 | printk ("Re-targetting CPEI to cpu %d\n", new_cpei_cpu); | 690 | printk ("Re-targetting CPEI to cpu %d\n", new_cpei_cpu); |
691 | } | 691 | } |
692 | } | 692 | } |
diff --git a/arch/ia64/sn/kernel/irq.c b/arch/ia64/sn/kernel/irq.c index 677c6c0fd661..7bb6ad188ba3 100644 --- a/arch/ia64/sn/kernel/irq.c +++ b/arch/ia64/sn/kernel/irq.c | |||
@@ -225,8 +225,8 @@ void sn_irq_init(void) | |||
225 | ia64_last_device_vector = IA64_SN2_LAST_DEVICE_VECTOR; | 225 | ia64_last_device_vector = IA64_SN2_LAST_DEVICE_VECTOR; |
226 | 226 | ||
227 | for (i = 0; i < NR_IRQS; i++) { | 227 | for (i = 0; i < NR_IRQS; i++) { |
228 | if (base_desc[i].handler == &no_irq_type) { | 228 | if (base_desc[i].chip == &no_irq_type) { |
229 | base_desc[i].handler = &irq_type_sn; | 229 | base_desc[i].chip = &irq_type_sn; |
230 | } | 230 | } |
231 | } | 231 | } |
232 | } | 232 | } |
diff --git a/arch/m32r/kernel/irq.c b/arch/m32r/kernel/irq.c index a4634b06f675..3841861df6a2 100644 --- a/arch/m32r/kernel/irq.c +++ b/arch/m32r/kernel/irq.c | |||
@@ -54,7 +54,7 @@ int show_interrupts(struct seq_file *p, void *v) | |||
54 | for_each_online_cpu(j) | 54 | for_each_online_cpu(j) |
55 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); | 55 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); |
56 | #endif | 56 | #endif |
57 | seq_printf(p, " %14s", irq_desc[i].handler->typename); | 57 | seq_printf(p, " %14s", irq_desc[i].chip->typename); |
58 | seq_printf(p, " %s", action->name); | 58 | seq_printf(p, " %s", action->name); |
59 | 59 | ||
60 | for (action=action->next; action; action = action->next) | 60 | for (action=action->next; action; action = action->next) |
diff --git a/arch/m32r/kernel/setup_m32104ut.c b/arch/m32r/kernel/setup_m32104ut.c index 6328e1357a80..f9f56c270195 100644 --- a/arch/m32r/kernel/setup_m32104ut.c +++ b/arch/m32r/kernel/setup_m32104ut.c | |||
@@ -87,7 +87,7 @@ void __init init_IRQ(void) | |||
87 | #if defined(CONFIG_SMC91X) | 87 | #if defined(CONFIG_SMC91X) |
88 | /* INT#0: LAN controller on M32104UT-LAN (SMC91C111)*/ | 88 | /* INT#0: LAN controller on M32104UT-LAN (SMC91C111)*/ |
89 | irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; | 89 | irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; |
90 | irq_desc[M32R_IRQ_INT0].handler = &m32104ut_irq_type; | 90 | irq_desc[M32R_IRQ_INT0].chip = &m32104ut_irq_type; |
91 | irq_desc[M32R_IRQ_INT0].action = 0; | 91 | irq_desc[M32R_IRQ_INT0].action = 0; |
92 | irq_desc[M32R_IRQ_INT0].depth = 1; | 92 | irq_desc[M32R_IRQ_INT0].depth = 1; |
93 | icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11; /* "H" level sense */ | 93 | icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11; /* "H" level sense */ |
@@ -96,7 +96,7 @@ void __init init_IRQ(void) | |||
96 | 96 | ||
97 | /* MFT2 : system timer */ | 97 | /* MFT2 : system timer */ |
98 | irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; | 98 | irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; |
99 | irq_desc[M32R_IRQ_MFT2].handler = &m32104ut_irq_type; | 99 | irq_desc[M32R_IRQ_MFT2].chip = &m32104ut_irq_type; |
100 | irq_desc[M32R_IRQ_MFT2].action = 0; | 100 | irq_desc[M32R_IRQ_MFT2].action = 0; |
101 | irq_desc[M32R_IRQ_MFT2].depth = 1; | 101 | irq_desc[M32R_IRQ_MFT2].depth = 1; |
102 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; | 102 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; |
@@ -105,7 +105,7 @@ void __init init_IRQ(void) | |||
105 | #ifdef CONFIG_SERIAL_M32R_SIO | 105 | #ifdef CONFIG_SERIAL_M32R_SIO |
106 | /* SIO0_R : uart receive data */ | 106 | /* SIO0_R : uart receive data */ |
107 | irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; | 107 | irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; |
108 | irq_desc[M32R_IRQ_SIO0_R].handler = &m32104ut_irq_type; | 108 | irq_desc[M32R_IRQ_SIO0_R].chip = &m32104ut_irq_type; |
109 | irq_desc[M32R_IRQ_SIO0_R].action = 0; | 109 | irq_desc[M32R_IRQ_SIO0_R].action = 0; |
110 | irq_desc[M32R_IRQ_SIO0_R].depth = 1; | 110 | irq_desc[M32R_IRQ_SIO0_R].depth = 1; |
111 | icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN; | 111 | icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN; |
@@ -113,7 +113,7 @@ void __init init_IRQ(void) | |||
113 | 113 | ||
114 | /* SIO0_S : uart send data */ | 114 | /* SIO0_S : uart send data */ |
115 | irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; | 115 | irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; |
116 | irq_desc[M32R_IRQ_SIO0_S].handler = &m32104ut_irq_type; | 116 | irq_desc[M32R_IRQ_SIO0_S].chip = &m32104ut_irq_type; |
117 | irq_desc[M32R_IRQ_SIO0_S].action = 0; | 117 | irq_desc[M32R_IRQ_SIO0_S].action = 0; |
118 | irq_desc[M32R_IRQ_SIO0_S].depth = 1; | 118 | irq_desc[M32R_IRQ_SIO0_S].depth = 1; |
119 | icu_data[M32R_IRQ_SIO0_S].icucr = M32R_ICUCR_IEN; | 119 | icu_data[M32R_IRQ_SIO0_S].icucr = M32R_ICUCR_IEN; |
diff --git a/arch/m32r/kernel/setup_m32700ut.c b/arch/m32r/kernel/setup_m32700ut.c index fad1fc99bb27..b6ab00eff580 100644 --- a/arch/m32r/kernel/setup_m32700ut.c +++ b/arch/m32r/kernel/setup_m32700ut.c | |||
@@ -301,7 +301,7 @@ void __init init_IRQ(void) | |||
301 | #if defined(CONFIG_SMC91X) | 301 | #if defined(CONFIG_SMC91X) |
302 | /* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/ | 302 | /* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/ |
303 | irq_desc[M32700UT_LAN_IRQ_LAN].status = IRQ_DISABLED; | 303 | irq_desc[M32700UT_LAN_IRQ_LAN].status = IRQ_DISABLED; |
304 | irq_desc[M32700UT_LAN_IRQ_LAN].handler = &m32700ut_lanpld_irq_type; | 304 | irq_desc[M32700UT_LAN_IRQ_LAN].chip = &m32700ut_lanpld_irq_type; |
305 | irq_desc[M32700UT_LAN_IRQ_LAN].action = 0; | 305 | irq_desc[M32700UT_LAN_IRQ_LAN].action = 0; |
306 | irq_desc[M32700UT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */ | 306 | irq_desc[M32700UT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */ |
307 | lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ | 307 | lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ |
@@ -310,7 +310,7 @@ void __init init_IRQ(void) | |||
310 | 310 | ||
311 | /* MFT2 : system timer */ | 311 | /* MFT2 : system timer */ |
312 | irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; | 312 | irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; |
313 | irq_desc[M32R_IRQ_MFT2].handler = &m32700ut_irq_type; | 313 | irq_desc[M32R_IRQ_MFT2].chip = &m32700ut_irq_type; |
314 | irq_desc[M32R_IRQ_MFT2].action = 0; | 314 | irq_desc[M32R_IRQ_MFT2].action = 0; |
315 | irq_desc[M32R_IRQ_MFT2].depth = 1; | 315 | irq_desc[M32R_IRQ_MFT2].depth = 1; |
316 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; | 316 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; |
@@ -318,7 +318,7 @@ void __init init_IRQ(void) | |||
318 | 318 | ||
319 | /* SIO0 : receive */ | 319 | /* SIO0 : receive */ |
320 | irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; | 320 | irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; |
321 | irq_desc[M32R_IRQ_SIO0_R].handler = &m32700ut_irq_type; | 321 | irq_desc[M32R_IRQ_SIO0_R].chip = &m32700ut_irq_type; |
322 | irq_desc[M32R_IRQ_SIO0_R].action = 0; | 322 | irq_desc[M32R_IRQ_SIO0_R].action = 0; |
323 | irq_desc[M32R_IRQ_SIO0_R].depth = 1; | 323 | irq_desc[M32R_IRQ_SIO0_R].depth = 1; |
324 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; | 324 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; |
@@ -326,7 +326,7 @@ void __init init_IRQ(void) | |||
326 | 326 | ||
327 | /* SIO0 : send */ | 327 | /* SIO0 : send */ |
328 | irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; | 328 | irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; |
329 | irq_desc[M32R_IRQ_SIO0_S].handler = &m32700ut_irq_type; | 329 | irq_desc[M32R_IRQ_SIO0_S].chip = &m32700ut_irq_type; |
330 | irq_desc[M32R_IRQ_SIO0_S].action = 0; | 330 | irq_desc[M32R_IRQ_SIO0_S].action = 0; |
331 | irq_desc[M32R_IRQ_SIO0_S].depth = 1; | 331 | irq_desc[M32R_IRQ_SIO0_S].depth = 1; |
332 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; | 332 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; |
@@ -334,7 +334,7 @@ void __init init_IRQ(void) | |||
334 | 334 | ||
335 | /* SIO1 : receive */ | 335 | /* SIO1 : receive */ |
336 | irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; | 336 | irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; |
337 | irq_desc[M32R_IRQ_SIO1_R].handler = &m32700ut_irq_type; | 337 | irq_desc[M32R_IRQ_SIO1_R].chip = &m32700ut_irq_type; |
338 | irq_desc[M32R_IRQ_SIO1_R].action = 0; | 338 | irq_desc[M32R_IRQ_SIO1_R].action = 0; |
339 | irq_desc[M32R_IRQ_SIO1_R].depth = 1; | 339 | irq_desc[M32R_IRQ_SIO1_R].depth = 1; |
340 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; | 340 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; |
@@ -342,7 +342,7 @@ void __init init_IRQ(void) | |||
342 | 342 | ||
343 | /* SIO1 : send */ | 343 | /* SIO1 : send */ |
344 | irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; | 344 | irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; |
345 | irq_desc[M32R_IRQ_SIO1_S].handler = &m32700ut_irq_type; | 345 | irq_desc[M32R_IRQ_SIO1_S].chip = &m32700ut_irq_type; |
346 | irq_desc[M32R_IRQ_SIO1_S].action = 0; | 346 | irq_desc[M32R_IRQ_SIO1_S].action = 0; |
347 | irq_desc[M32R_IRQ_SIO1_S].depth = 1; | 347 | irq_desc[M32R_IRQ_SIO1_S].depth = 1; |
348 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; | 348 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; |
@@ -350,7 +350,7 @@ void __init init_IRQ(void) | |||
350 | 350 | ||
351 | /* DMA1 : */ | 351 | /* DMA1 : */ |
352 | irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED; | 352 | irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED; |
353 | irq_desc[M32R_IRQ_DMA1].handler = &m32700ut_irq_type; | 353 | irq_desc[M32R_IRQ_DMA1].chip = &m32700ut_irq_type; |
354 | irq_desc[M32R_IRQ_DMA1].action = 0; | 354 | irq_desc[M32R_IRQ_DMA1].action = 0; |
355 | irq_desc[M32R_IRQ_DMA1].depth = 1; | 355 | irq_desc[M32R_IRQ_DMA1].depth = 1; |
356 | icu_data[M32R_IRQ_DMA1].icucr = 0; | 356 | icu_data[M32R_IRQ_DMA1].icucr = 0; |
@@ -359,7 +359,7 @@ void __init init_IRQ(void) | |||
359 | #ifdef CONFIG_SERIAL_M32R_PLDSIO | 359 | #ifdef CONFIG_SERIAL_M32R_PLDSIO |
360 | /* INT#1: SIO0 Receive on PLD */ | 360 | /* INT#1: SIO0 Receive on PLD */ |
361 | irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED; | 361 | irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED; |
362 | irq_desc[PLD_IRQ_SIO0_RCV].handler = &m32700ut_pld_irq_type; | 362 | irq_desc[PLD_IRQ_SIO0_RCV].chip = &m32700ut_pld_irq_type; |
363 | irq_desc[PLD_IRQ_SIO0_RCV].action = 0; | 363 | irq_desc[PLD_IRQ_SIO0_RCV].action = 0; |
364 | irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */ | 364 | irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */ |
365 | pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; | 365 | pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; |
@@ -367,7 +367,7 @@ void __init init_IRQ(void) | |||
367 | 367 | ||
368 | /* INT#1: SIO0 Send on PLD */ | 368 | /* INT#1: SIO0 Send on PLD */ |
369 | irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED; | 369 | irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED; |
370 | irq_desc[PLD_IRQ_SIO0_SND].handler = &m32700ut_pld_irq_type; | 370 | irq_desc[PLD_IRQ_SIO0_SND].chip = &m32700ut_pld_irq_type; |
371 | irq_desc[PLD_IRQ_SIO0_SND].action = 0; | 371 | irq_desc[PLD_IRQ_SIO0_SND].action = 0; |
372 | irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */ | 372 | irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */ |
373 | pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; | 373 | pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; |
@@ -376,7 +376,7 @@ void __init init_IRQ(void) | |||
376 | 376 | ||
377 | /* INT#1: CFC IREQ on PLD */ | 377 | /* INT#1: CFC IREQ on PLD */ |
378 | irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; | 378 | irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; |
379 | irq_desc[PLD_IRQ_CFIREQ].handler = &m32700ut_pld_irq_type; | 379 | irq_desc[PLD_IRQ_CFIREQ].chip = &m32700ut_pld_irq_type; |
380 | irq_desc[PLD_IRQ_CFIREQ].action = 0; | 380 | irq_desc[PLD_IRQ_CFIREQ].action = 0; |
381 | irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */ | 381 | irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */ |
382 | pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ | 382 | pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ |
@@ -384,7 +384,7 @@ void __init init_IRQ(void) | |||
384 | 384 | ||
385 | /* INT#1: CFC Insert on PLD */ | 385 | /* INT#1: CFC Insert on PLD */ |
386 | irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; | 386 | irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; |
387 | irq_desc[PLD_IRQ_CFC_INSERT].handler = &m32700ut_pld_irq_type; | 387 | irq_desc[PLD_IRQ_CFC_INSERT].chip = &m32700ut_pld_irq_type; |
388 | irq_desc[PLD_IRQ_CFC_INSERT].action = 0; | 388 | irq_desc[PLD_IRQ_CFC_INSERT].action = 0; |
389 | irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */ | 389 | irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */ |
390 | pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ | 390 | pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ |
@@ -392,7 +392,7 @@ void __init init_IRQ(void) | |||
392 | 392 | ||
393 | /* INT#1: CFC Eject on PLD */ | 393 | /* INT#1: CFC Eject on PLD */ |
394 | irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED; | 394 | irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED; |
395 | irq_desc[PLD_IRQ_CFC_EJECT].handler = &m32700ut_pld_irq_type; | 395 | irq_desc[PLD_IRQ_CFC_EJECT].chip = &m32700ut_pld_irq_type; |
396 | irq_desc[PLD_IRQ_CFC_EJECT].action = 0; | 396 | irq_desc[PLD_IRQ_CFC_EJECT].action = 0; |
397 | irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */ | 397 | irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */ |
398 | pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ | 398 | pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ |
@@ -416,7 +416,7 @@ void __init init_IRQ(void) | |||
416 | outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ | 416 | outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ |
417 | 417 | ||
418 | irq_desc[M32700UT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED; | 418 | irq_desc[M32700UT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED; |
419 | irq_desc[M32700UT_LCD_IRQ_USB_INT1].handler = &m32700ut_lcdpld_irq_type; | 419 | irq_desc[M32700UT_LCD_IRQ_USB_INT1].chip = &m32700ut_lcdpld_irq_type; |
420 | irq_desc[M32700UT_LCD_IRQ_USB_INT1].action = 0; | 420 | irq_desc[M32700UT_LCD_IRQ_USB_INT1].action = 0; |
421 | irq_desc[M32700UT_LCD_IRQ_USB_INT1].depth = 1; | 421 | irq_desc[M32700UT_LCD_IRQ_USB_INT1].depth = 1; |
422 | lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ | 422 | lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ |
@@ -434,7 +434,7 @@ void __init init_IRQ(void) | |||
434 | * INT3# is used for AR | 434 | * INT3# is used for AR |
435 | */ | 435 | */ |
436 | irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED; | 436 | irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED; |
437 | irq_desc[M32R_IRQ_INT3].handler = &m32700ut_irq_type; | 437 | irq_desc[M32R_IRQ_INT3].chip = &m32700ut_irq_type; |
438 | irq_desc[M32R_IRQ_INT3].action = 0; | 438 | irq_desc[M32R_IRQ_INT3].action = 0; |
439 | irq_desc[M32R_IRQ_INT3].depth = 1; | 439 | irq_desc[M32R_IRQ_INT3].depth = 1; |
440 | icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; | 440 | icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; |
diff --git a/arch/m32r/kernel/setup_mappi.c b/arch/m32r/kernel/setup_mappi.c index 00f253209cb3..c268044185f5 100644 --- a/arch/m32r/kernel/setup_mappi.c +++ b/arch/m32r/kernel/setup_mappi.c | |||
@@ -86,7 +86,7 @@ void __init init_IRQ(void) | |||
86 | #ifdef CONFIG_NE2000 | 86 | #ifdef CONFIG_NE2000 |
87 | /* INT0 : LAN controller (RTL8019AS) */ | 87 | /* INT0 : LAN controller (RTL8019AS) */ |
88 | irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; | 88 | irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; |
89 | irq_desc[M32R_IRQ_INT0].handler = &mappi_irq_type; | 89 | irq_desc[M32R_IRQ_INT0].chip = &mappi_irq_type; |
90 | irq_desc[M32R_IRQ_INT0].action = 0; | 90 | irq_desc[M32R_IRQ_INT0].action = 0; |
91 | irq_desc[M32R_IRQ_INT0].depth = 1; | 91 | irq_desc[M32R_IRQ_INT0].depth = 1; |
92 | icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; | 92 | icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; |
@@ -95,7 +95,7 @@ void __init init_IRQ(void) | |||
95 | 95 | ||
96 | /* MFT2 : system timer */ | 96 | /* MFT2 : system timer */ |
97 | irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; | 97 | irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; |
98 | irq_desc[M32R_IRQ_MFT2].handler = &mappi_irq_type; | 98 | irq_desc[M32R_IRQ_MFT2].chip = &mappi_irq_type; |
99 | irq_desc[M32R_IRQ_MFT2].action = 0; | 99 | irq_desc[M32R_IRQ_MFT2].action = 0; |
100 | irq_desc[M32R_IRQ_MFT2].depth = 1; | 100 | irq_desc[M32R_IRQ_MFT2].depth = 1; |
101 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; | 101 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; |
@@ -104,7 +104,7 @@ void __init init_IRQ(void) | |||
104 | #ifdef CONFIG_SERIAL_M32R_SIO | 104 | #ifdef CONFIG_SERIAL_M32R_SIO |
105 | /* SIO0_R : uart receive data */ | 105 | /* SIO0_R : uart receive data */ |
106 | irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; | 106 | irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; |
107 | irq_desc[M32R_IRQ_SIO0_R].handler = &mappi_irq_type; | 107 | irq_desc[M32R_IRQ_SIO0_R].chip = &mappi_irq_type; |
108 | irq_desc[M32R_IRQ_SIO0_R].action = 0; | 108 | irq_desc[M32R_IRQ_SIO0_R].action = 0; |
109 | irq_desc[M32R_IRQ_SIO0_R].depth = 1; | 109 | irq_desc[M32R_IRQ_SIO0_R].depth = 1; |
110 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; | 110 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; |
@@ -112,7 +112,7 @@ void __init init_IRQ(void) | |||
112 | 112 | ||
113 | /* SIO0_S : uart send data */ | 113 | /* SIO0_S : uart send data */ |
114 | irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; | 114 | irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; |
115 | irq_desc[M32R_IRQ_SIO0_S].handler = &mappi_irq_type; | 115 | irq_desc[M32R_IRQ_SIO0_S].chip = &mappi_irq_type; |
116 | irq_desc[M32R_IRQ_SIO0_S].action = 0; | 116 | irq_desc[M32R_IRQ_SIO0_S].action = 0; |
117 | irq_desc[M32R_IRQ_SIO0_S].depth = 1; | 117 | irq_desc[M32R_IRQ_SIO0_S].depth = 1; |
118 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; | 118 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; |
@@ -120,7 +120,7 @@ void __init init_IRQ(void) | |||
120 | 120 | ||
121 | /* SIO1_R : uart receive data */ | 121 | /* SIO1_R : uart receive data */ |
122 | irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; | 122 | irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; |
123 | irq_desc[M32R_IRQ_SIO1_R].handler = &mappi_irq_type; | 123 | irq_desc[M32R_IRQ_SIO1_R].chip = &mappi_irq_type; |
124 | irq_desc[M32R_IRQ_SIO1_R].action = 0; | 124 | irq_desc[M32R_IRQ_SIO1_R].action = 0; |
125 | irq_desc[M32R_IRQ_SIO1_R].depth = 1; | 125 | irq_desc[M32R_IRQ_SIO1_R].depth = 1; |
126 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; | 126 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; |
@@ -128,7 +128,7 @@ void __init init_IRQ(void) | |||
128 | 128 | ||
129 | /* SIO1_S : uart send data */ | 129 | /* SIO1_S : uart send data */ |
130 | irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; | 130 | irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; |
131 | irq_desc[M32R_IRQ_SIO1_S].handler = &mappi_irq_type; | 131 | irq_desc[M32R_IRQ_SIO1_S].chip = &mappi_irq_type; |
132 | irq_desc[M32R_IRQ_SIO1_S].action = 0; | 132 | irq_desc[M32R_IRQ_SIO1_S].action = 0; |
133 | irq_desc[M32R_IRQ_SIO1_S].depth = 1; | 133 | irq_desc[M32R_IRQ_SIO1_S].depth = 1; |
134 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; | 134 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; |
@@ -138,7 +138,7 @@ void __init init_IRQ(void) | |||
138 | #if defined(CONFIG_M32R_PCC) | 138 | #if defined(CONFIG_M32R_PCC) |
139 | /* INT1 : pccard0 interrupt */ | 139 | /* INT1 : pccard0 interrupt */ |
140 | irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED; | 140 | irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED; |
141 | irq_desc[M32R_IRQ_INT1].handler = &mappi_irq_type; | 141 | irq_desc[M32R_IRQ_INT1].chip = &mappi_irq_type; |
142 | irq_desc[M32R_IRQ_INT1].action = 0; | 142 | irq_desc[M32R_IRQ_INT1].action = 0; |
143 | irq_desc[M32R_IRQ_INT1].depth = 1; | 143 | irq_desc[M32R_IRQ_INT1].depth = 1; |
144 | icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; | 144 | icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; |
@@ -146,7 +146,7 @@ void __init init_IRQ(void) | |||
146 | 146 | ||
147 | /* INT2 : pccard1 interrupt */ | 147 | /* INT2 : pccard1 interrupt */ |
148 | irq_desc[M32R_IRQ_INT2].status = IRQ_DISABLED; | 148 | irq_desc[M32R_IRQ_INT2].status = IRQ_DISABLED; |
149 | irq_desc[M32R_IRQ_INT2].handler = &mappi_irq_type; | 149 | irq_desc[M32R_IRQ_INT2].chip = &mappi_irq_type; |
150 | irq_desc[M32R_IRQ_INT2].action = 0; | 150 | irq_desc[M32R_IRQ_INT2].action = 0; |
151 | irq_desc[M32R_IRQ_INT2].depth = 1; | 151 | irq_desc[M32R_IRQ_INT2].depth = 1; |
152 | icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; | 152 | icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; |
diff --git a/arch/m32r/kernel/setup_mappi2.c b/arch/m32r/kernel/setup_mappi2.c index eebc9d8b4e72..bd2327d5cca2 100644 --- a/arch/m32r/kernel/setup_mappi2.c +++ b/arch/m32r/kernel/setup_mappi2.c | |||
@@ -87,7 +87,7 @@ void __init init_IRQ(void) | |||
87 | #if defined(CONFIG_SMC91X) | 87 | #if defined(CONFIG_SMC91X) |
88 | /* INT0 : LAN controller (SMC91111) */ | 88 | /* INT0 : LAN controller (SMC91111) */ |
89 | irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; | 89 | irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; |
90 | irq_desc[M32R_IRQ_INT0].handler = &mappi2_irq_type; | 90 | irq_desc[M32R_IRQ_INT0].chip = &mappi2_irq_type; |
91 | irq_desc[M32R_IRQ_INT0].action = 0; | 91 | irq_desc[M32R_IRQ_INT0].action = 0; |
92 | irq_desc[M32R_IRQ_INT0].depth = 1; | 92 | irq_desc[M32R_IRQ_INT0].depth = 1; |
93 | icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; | 93 | icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; |
@@ -96,7 +96,7 @@ void __init init_IRQ(void) | |||
96 | 96 | ||
97 | /* MFT2 : system timer */ | 97 | /* MFT2 : system timer */ |
98 | irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; | 98 | irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; |
99 | irq_desc[M32R_IRQ_MFT2].handler = &mappi2_irq_type; | 99 | irq_desc[M32R_IRQ_MFT2].chip = &mappi2_irq_type; |
100 | irq_desc[M32R_IRQ_MFT2].action = 0; | 100 | irq_desc[M32R_IRQ_MFT2].action = 0; |
101 | irq_desc[M32R_IRQ_MFT2].depth = 1; | 101 | irq_desc[M32R_IRQ_MFT2].depth = 1; |
102 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; | 102 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; |
@@ -105,7 +105,7 @@ void __init init_IRQ(void) | |||
105 | #ifdef CONFIG_SERIAL_M32R_SIO | 105 | #ifdef CONFIG_SERIAL_M32R_SIO |
106 | /* SIO0_R : uart receive data */ | 106 | /* SIO0_R : uart receive data */ |
107 | irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; | 107 | irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; |
108 | irq_desc[M32R_IRQ_SIO0_R].handler = &mappi2_irq_type; | 108 | irq_desc[M32R_IRQ_SIO0_R].chip = &mappi2_irq_type; |
109 | irq_desc[M32R_IRQ_SIO0_R].action = 0; | 109 | irq_desc[M32R_IRQ_SIO0_R].action = 0; |
110 | irq_desc[M32R_IRQ_SIO0_R].depth = 1; | 110 | irq_desc[M32R_IRQ_SIO0_R].depth = 1; |
111 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; | 111 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; |
@@ -113,14 +113,14 @@ void __init init_IRQ(void) | |||
113 | 113 | ||
114 | /* SIO0_S : uart send data */ | 114 | /* SIO0_S : uart send data */ |
115 | irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; | 115 | irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; |
116 | irq_desc[M32R_IRQ_SIO0_S].handler = &mappi2_irq_type; | 116 | irq_desc[M32R_IRQ_SIO0_S].chip = &mappi2_irq_type; |
117 | irq_desc[M32R_IRQ_SIO0_S].action = 0; | 117 | irq_desc[M32R_IRQ_SIO0_S].action = 0; |
118 | irq_desc[M32R_IRQ_SIO0_S].depth = 1; | 118 | irq_desc[M32R_IRQ_SIO0_S].depth = 1; |
119 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; | 119 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; |
120 | disable_mappi2_irq(M32R_IRQ_SIO0_S); | 120 | disable_mappi2_irq(M32R_IRQ_SIO0_S); |
121 | /* SIO1_R : uart receive data */ | 121 | /* SIO1_R : uart receive data */ |
122 | irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; | 122 | irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; |
123 | irq_desc[M32R_IRQ_SIO1_R].handler = &mappi2_irq_type; | 123 | irq_desc[M32R_IRQ_SIO1_R].chip = &mappi2_irq_type; |
124 | irq_desc[M32R_IRQ_SIO1_R].action = 0; | 124 | irq_desc[M32R_IRQ_SIO1_R].action = 0; |
125 | irq_desc[M32R_IRQ_SIO1_R].depth = 1; | 125 | irq_desc[M32R_IRQ_SIO1_R].depth = 1; |
126 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; | 126 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; |
@@ -128,7 +128,7 @@ void __init init_IRQ(void) | |||
128 | 128 | ||
129 | /* SIO1_S : uart send data */ | 129 | /* SIO1_S : uart send data */ |
130 | irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; | 130 | irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; |
131 | irq_desc[M32R_IRQ_SIO1_S].handler = &mappi2_irq_type; | 131 | irq_desc[M32R_IRQ_SIO1_S].chip = &mappi2_irq_type; |
132 | irq_desc[M32R_IRQ_SIO1_S].action = 0; | 132 | irq_desc[M32R_IRQ_SIO1_S].action = 0; |
133 | irq_desc[M32R_IRQ_SIO1_S].depth = 1; | 133 | irq_desc[M32R_IRQ_SIO1_S].depth = 1; |
134 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; | 134 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; |
@@ -138,7 +138,7 @@ void __init init_IRQ(void) | |||
138 | #if defined(CONFIG_USB) | 138 | #if defined(CONFIG_USB) |
139 | /* INT1 : USB Host controller interrupt */ | 139 | /* INT1 : USB Host controller interrupt */ |
140 | irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED; | 140 | irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED; |
141 | irq_desc[M32R_IRQ_INT1].handler = &mappi2_irq_type; | 141 | irq_desc[M32R_IRQ_INT1].chip = &mappi2_irq_type; |
142 | irq_desc[M32R_IRQ_INT1].action = 0; | 142 | irq_desc[M32R_IRQ_INT1].action = 0; |
143 | irq_desc[M32R_IRQ_INT1].depth = 1; | 143 | irq_desc[M32R_IRQ_INT1].depth = 1; |
144 | icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; | 144 | icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; |
@@ -147,7 +147,7 @@ void __init init_IRQ(void) | |||
147 | 147 | ||
148 | /* ICUCR40: CFC IREQ */ | 148 | /* ICUCR40: CFC IREQ */ |
149 | irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; | 149 | irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; |
150 | irq_desc[PLD_IRQ_CFIREQ].handler = &mappi2_irq_type; | 150 | irq_desc[PLD_IRQ_CFIREQ].chip = &mappi2_irq_type; |
151 | irq_desc[PLD_IRQ_CFIREQ].action = 0; | 151 | irq_desc[PLD_IRQ_CFIREQ].action = 0; |
152 | irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */ | 152 | irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */ |
153 | icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; | 153 | icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; |
@@ -156,7 +156,7 @@ void __init init_IRQ(void) | |||
156 | #if defined(CONFIG_M32R_CFC) | 156 | #if defined(CONFIG_M32R_CFC) |
157 | /* ICUCR41: CFC Insert */ | 157 | /* ICUCR41: CFC Insert */ |
158 | irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; | 158 | irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; |
159 | irq_desc[PLD_IRQ_CFC_INSERT].handler = &mappi2_irq_type; | 159 | irq_desc[PLD_IRQ_CFC_INSERT].chip = &mappi2_irq_type; |
160 | irq_desc[PLD_IRQ_CFC_INSERT].action = 0; | 160 | irq_desc[PLD_IRQ_CFC_INSERT].action = 0; |
161 | irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */ | 161 | irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */ |
162 | icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; | 162 | icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; |
@@ -164,7 +164,7 @@ void __init init_IRQ(void) | |||
164 | 164 | ||
165 | /* ICUCR42: CFC Eject */ | 165 | /* ICUCR42: CFC Eject */ |
166 | irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED; | 166 | irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED; |
167 | irq_desc[PLD_IRQ_CFC_EJECT].handler = &mappi2_irq_type; | 167 | irq_desc[PLD_IRQ_CFC_EJECT].chip = &mappi2_irq_type; |
168 | irq_desc[PLD_IRQ_CFC_EJECT].action = 0; | 168 | irq_desc[PLD_IRQ_CFC_EJECT].action = 0; |
169 | irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */ | 169 | irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */ |
170 | icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; | 170 | icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; |
diff --git a/arch/m32r/kernel/setup_mappi3.c b/arch/m32r/kernel/setup_mappi3.c index d2ff021e2d3d..014b51d17505 100644 --- a/arch/m32r/kernel/setup_mappi3.c +++ b/arch/m32r/kernel/setup_mappi3.c | |||
@@ -87,7 +87,7 @@ void __init init_IRQ(void) | |||
87 | #if defined(CONFIG_SMC91X) | 87 | #if defined(CONFIG_SMC91X) |
88 | /* INT0 : LAN controller (SMC91111) */ | 88 | /* INT0 : LAN controller (SMC91111) */ |
89 | irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; | 89 | irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; |
90 | irq_desc[M32R_IRQ_INT0].handler = &mappi3_irq_type; | 90 | irq_desc[M32R_IRQ_INT0].chip = &mappi3_irq_type; |
91 | irq_desc[M32R_IRQ_INT0].action = 0; | 91 | irq_desc[M32R_IRQ_INT0].action = 0; |
92 | irq_desc[M32R_IRQ_INT0].depth = 1; | 92 | irq_desc[M32R_IRQ_INT0].depth = 1; |
93 | icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; | 93 | icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; |
@@ -96,7 +96,7 @@ void __init init_IRQ(void) | |||
96 | 96 | ||
97 | /* MFT2 : system timer */ | 97 | /* MFT2 : system timer */ |
98 | irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; | 98 | irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; |
99 | irq_desc[M32R_IRQ_MFT2].handler = &mappi3_irq_type; | 99 | irq_desc[M32R_IRQ_MFT2].chip = &mappi3_irq_type; |
100 | irq_desc[M32R_IRQ_MFT2].action = 0; | 100 | irq_desc[M32R_IRQ_MFT2].action = 0; |
101 | irq_desc[M32R_IRQ_MFT2].depth = 1; | 101 | irq_desc[M32R_IRQ_MFT2].depth = 1; |
102 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; | 102 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; |
@@ -105,7 +105,7 @@ void __init init_IRQ(void) | |||
105 | #ifdef CONFIG_SERIAL_M32R_SIO | 105 | #ifdef CONFIG_SERIAL_M32R_SIO |
106 | /* SIO0_R : uart receive data */ | 106 | /* SIO0_R : uart receive data */ |
107 | irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; | 107 | irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; |
108 | irq_desc[M32R_IRQ_SIO0_R].handler = &mappi3_irq_type; | 108 | irq_desc[M32R_IRQ_SIO0_R].chip = &mappi3_irq_type; |
109 | irq_desc[M32R_IRQ_SIO0_R].action = 0; | 109 | irq_desc[M32R_IRQ_SIO0_R].action = 0; |
110 | irq_desc[M32R_IRQ_SIO0_R].depth = 1; | 110 | irq_desc[M32R_IRQ_SIO0_R].depth = 1; |
111 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; | 111 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; |
@@ -113,14 +113,14 @@ void __init init_IRQ(void) | |||
113 | 113 | ||
114 | /* SIO0_S : uart send data */ | 114 | /* SIO0_S : uart send data */ |
115 | irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; | 115 | irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; |
116 | irq_desc[M32R_IRQ_SIO0_S].handler = &mappi3_irq_type; | 116 | irq_desc[M32R_IRQ_SIO0_S].chip = &mappi3_irq_type; |
117 | irq_desc[M32R_IRQ_SIO0_S].action = 0; | 117 | irq_desc[M32R_IRQ_SIO0_S].action = 0; |
118 | irq_desc[M32R_IRQ_SIO0_S].depth = 1; | 118 | irq_desc[M32R_IRQ_SIO0_S].depth = 1; |
119 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; | 119 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; |
120 | disable_mappi3_irq(M32R_IRQ_SIO0_S); | 120 | disable_mappi3_irq(M32R_IRQ_SIO0_S); |
121 | /* SIO1_R : uart receive data */ | 121 | /* SIO1_R : uart receive data */ |
122 | irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; | 122 | irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; |
123 | irq_desc[M32R_IRQ_SIO1_R].handler = &mappi3_irq_type; | 123 | irq_desc[M32R_IRQ_SIO1_R].chip = &mappi3_irq_type; |
124 | irq_desc[M32R_IRQ_SIO1_R].action = 0; | 124 | irq_desc[M32R_IRQ_SIO1_R].action = 0; |
125 | irq_desc[M32R_IRQ_SIO1_R].depth = 1; | 125 | irq_desc[M32R_IRQ_SIO1_R].depth = 1; |
126 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; | 126 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; |
@@ -128,7 +128,7 @@ void __init init_IRQ(void) | |||
128 | 128 | ||
129 | /* SIO1_S : uart send data */ | 129 | /* SIO1_S : uart send data */ |
130 | irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; | 130 | irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; |
131 | irq_desc[M32R_IRQ_SIO1_S].handler = &mappi3_irq_type; | 131 | irq_desc[M32R_IRQ_SIO1_S].chip = &mappi3_irq_type; |
132 | irq_desc[M32R_IRQ_SIO1_S].action = 0; | 132 | irq_desc[M32R_IRQ_SIO1_S].action = 0; |
133 | irq_desc[M32R_IRQ_SIO1_S].depth = 1; | 133 | irq_desc[M32R_IRQ_SIO1_S].depth = 1; |
134 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; | 134 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; |
@@ -138,7 +138,7 @@ void __init init_IRQ(void) | |||
138 | #if defined(CONFIG_USB) | 138 | #if defined(CONFIG_USB) |
139 | /* INT1 : USB Host controller interrupt */ | 139 | /* INT1 : USB Host controller interrupt */ |
140 | irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED; | 140 | irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED; |
141 | irq_desc[M32R_IRQ_INT1].handler = &mappi3_irq_type; | 141 | irq_desc[M32R_IRQ_INT1].chip = &mappi3_irq_type; |
142 | irq_desc[M32R_IRQ_INT1].action = 0; | 142 | irq_desc[M32R_IRQ_INT1].action = 0; |
143 | irq_desc[M32R_IRQ_INT1].depth = 1; | 143 | irq_desc[M32R_IRQ_INT1].depth = 1; |
144 | icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; | 144 | icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; |
@@ -147,7 +147,7 @@ void __init init_IRQ(void) | |||
147 | 147 | ||
148 | /* CFC IREQ */ | 148 | /* CFC IREQ */ |
149 | irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; | 149 | irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; |
150 | irq_desc[PLD_IRQ_CFIREQ].handler = &mappi3_irq_type; | 150 | irq_desc[PLD_IRQ_CFIREQ].chip = &mappi3_irq_type; |
151 | irq_desc[PLD_IRQ_CFIREQ].action = 0; | 151 | irq_desc[PLD_IRQ_CFIREQ].action = 0; |
152 | irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */ | 152 | irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */ |
153 | icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; | 153 | icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; |
@@ -156,7 +156,7 @@ void __init init_IRQ(void) | |||
156 | #if defined(CONFIG_M32R_CFC) | 156 | #if defined(CONFIG_M32R_CFC) |
157 | /* ICUCR41: CFC Insert & eject */ | 157 | /* ICUCR41: CFC Insert & eject */ |
158 | irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; | 158 | irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; |
159 | irq_desc[PLD_IRQ_CFC_INSERT].handler = &mappi3_irq_type; | 159 | irq_desc[PLD_IRQ_CFC_INSERT].chip = &mappi3_irq_type; |
160 | irq_desc[PLD_IRQ_CFC_INSERT].action = 0; | 160 | irq_desc[PLD_IRQ_CFC_INSERT].action = 0; |
161 | irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */ | 161 | irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */ |
162 | icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; | 162 | icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; |
@@ -166,7 +166,7 @@ void __init init_IRQ(void) | |||
166 | 166 | ||
167 | /* IDE IREQ */ | 167 | /* IDE IREQ */ |
168 | irq_desc[PLD_IRQ_IDEIREQ].status = IRQ_DISABLED; | 168 | irq_desc[PLD_IRQ_IDEIREQ].status = IRQ_DISABLED; |
169 | irq_desc[PLD_IRQ_IDEIREQ].handler = &mappi3_irq_type; | 169 | irq_desc[PLD_IRQ_IDEIREQ].chip = &mappi3_irq_type; |
170 | irq_desc[PLD_IRQ_IDEIREQ].action = 0; | 170 | irq_desc[PLD_IRQ_IDEIREQ].action = 0; |
171 | irq_desc[PLD_IRQ_IDEIREQ].depth = 1; /* disable nested irq */ | 171 | irq_desc[PLD_IRQ_IDEIREQ].depth = 1; /* disable nested irq */ |
172 | icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; | 172 | icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; |
diff --git a/arch/m32r/kernel/setup_oaks32r.c b/arch/m32r/kernel/setup_oaks32r.c index 0e9e63538c0f..ea64831aef7a 100644 --- a/arch/m32r/kernel/setup_oaks32r.c +++ b/arch/m32r/kernel/setup_oaks32r.c | |||
@@ -85,7 +85,7 @@ void __init init_IRQ(void) | |||
85 | #ifdef CONFIG_NE2000 | 85 | #ifdef CONFIG_NE2000 |
86 | /* INT3 : LAN controller (RTL8019AS) */ | 86 | /* INT3 : LAN controller (RTL8019AS) */ |
87 | irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED; | 87 | irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED; |
88 | irq_desc[M32R_IRQ_INT3].handler = &oaks32r_irq_type; | 88 | irq_desc[M32R_IRQ_INT3].chip = &oaks32r_irq_type; |
89 | irq_desc[M32R_IRQ_INT3].action = 0; | 89 | irq_desc[M32R_IRQ_INT3].action = 0; |
90 | irq_desc[M32R_IRQ_INT3].depth = 1; | 90 | irq_desc[M32R_IRQ_INT3].depth = 1; |
91 | icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; | 91 | icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; |
@@ -94,7 +94,7 @@ void __init init_IRQ(void) | |||
94 | 94 | ||
95 | /* MFT2 : system timer */ | 95 | /* MFT2 : system timer */ |
96 | irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; | 96 | irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; |
97 | irq_desc[M32R_IRQ_MFT2].handler = &oaks32r_irq_type; | 97 | irq_desc[M32R_IRQ_MFT2].chip = &oaks32r_irq_type; |
98 | irq_desc[M32R_IRQ_MFT2].action = 0; | 98 | irq_desc[M32R_IRQ_MFT2].action = 0; |
99 | irq_desc[M32R_IRQ_MFT2].depth = 1; | 99 | irq_desc[M32R_IRQ_MFT2].depth = 1; |
100 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; | 100 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; |
@@ -103,7 +103,7 @@ void __init init_IRQ(void) | |||
103 | #ifdef CONFIG_SERIAL_M32R_SIO | 103 | #ifdef CONFIG_SERIAL_M32R_SIO |
104 | /* SIO0_R : uart receive data */ | 104 | /* SIO0_R : uart receive data */ |
105 | irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; | 105 | irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; |
106 | irq_desc[M32R_IRQ_SIO0_R].handler = &oaks32r_irq_type; | 106 | irq_desc[M32R_IRQ_SIO0_R].chip = &oaks32r_irq_type; |
107 | irq_desc[M32R_IRQ_SIO0_R].action = 0; | 107 | irq_desc[M32R_IRQ_SIO0_R].action = 0; |
108 | irq_desc[M32R_IRQ_SIO0_R].depth = 1; | 108 | irq_desc[M32R_IRQ_SIO0_R].depth = 1; |
109 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; | 109 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; |
@@ -111,7 +111,7 @@ void __init init_IRQ(void) | |||
111 | 111 | ||
112 | /* SIO0_S : uart send data */ | 112 | /* SIO0_S : uart send data */ |
113 | irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; | 113 | irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; |
114 | irq_desc[M32R_IRQ_SIO0_S].handler = &oaks32r_irq_type; | 114 | irq_desc[M32R_IRQ_SIO0_S].chip = &oaks32r_irq_type; |
115 | irq_desc[M32R_IRQ_SIO0_S].action = 0; | 115 | irq_desc[M32R_IRQ_SIO0_S].action = 0; |
116 | irq_desc[M32R_IRQ_SIO0_S].depth = 1; | 116 | irq_desc[M32R_IRQ_SIO0_S].depth = 1; |
117 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; | 117 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; |
@@ -119,7 +119,7 @@ void __init init_IRQ(void) | |||
119 | 119 | ||
120 | /* SIO1_R : uart receive data */ | 120 | /* SIO1_R : uart receive data */ |
121 | irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; | 121 | irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; |
122 | irq_desc[M32R_IRQ_SIO1_R].handler = &oaks32r_irq_type; | 122 | irq_desc[M32R_IRQ_SIO1_R].chip = &oaks32r_irq_type; |
123 | irq_desc[M32R_IRQ_SIO1_R].action = 0; | 123 | irq_desc[M32R_IRQ_SIO1_R].action = 0; |
124 | irq_desc[M32R_IRQ_SIO1_R].depth = 1; | 124 | irq_desc[M32R_IRQ_SIO1_R].depth = 1; |
125 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; | 125 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; |
@@ -127,7 +127,7 @@ void __init init_IRQ(void) | |||
127 | 127 | ||
128 | /* SIO1_S : uart send data */ | 128 | /* SIO1_S : uart send data */ |
129 | irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; | 129 | irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; |
130 | irq_desc[M32R_IRQ_SIO1_S].handler = &oaks32r_irq_type; | 130 | irq_desc[M32R_IRQ_SIO1_S].chip = &oaks32r_irq_type; |
131 | irq_desc[M32R_IRQ_SIO1_S].action = 0; | 131 | irq_desc[M32R_IRQ_SIO1_S].action = 0; |
132 | irq_desc[M32R_IRQ_SIO1_S].depth = 1; | 132 | irq_desc[M32R_IRQ_SIO1_S].depth = 1; |
133 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; | 133 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; |
diff --git a/arch/m32r/kernel/setup_opsput.c b/arch/m32r/kernel/setup_opsput.c index 548e8fc7949b..55e8972d455a 100644 --- a/arch/m32r/kernel/setup_opsput.c +++ b/arch/m32r/kernel/setup_opsput.c | |||
@@ -302,7 +302,7 @@ void __init init_IRQ(void) | |||
302 | #if defined(CONFIG_SMC91X) | 302 | #if defined(CONFIG_SMC91X) |
303 | /* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/ | 303 | /* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/ |
304 | irq_desc[OPSPUT_LAN_IRQ_LAN].status = IRQ_DISABLED; | 304 | irq_desc[OPSPUT_LAN_IRQ_LAN].status = IRQ_DISABLED; |
305 | irq_desc[OPSPUT_LAN_IRQ_LAN].handler = &opsput_lanpld_irq_type; | 305 | irq_desc[OPSPUT_LAN_IRQ_LAN].chip = &opsput_lanpld_irq_type; |
306 | irq_desc[OPSPUT_LAN_IRQ_LAN].action = 0; | 306 | irq_desc[OPSPUT_LAN_IRQ_LAN].action = 0; |
307 | irq_desc[OPSPUT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */ | 307 | irq_desc[OPSPUT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */ |
308 | lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ | 308 | lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ |
@@ -311,7 +311,7 @@ void __init init_IRQ(void) | |||
311 | 311 | ||
312 | /* MFT2 : system timer */ | 312 | /* MFT2 : system timer */ |
313 | irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; | 313 | irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; |
314 | irq_desc[M32R_IRQ_MFT2].handler = &opsput_irq_type; | 314 | irq_desc[M32R_IRQ_MFT2].chip = &opsput_irq_type; |
315 | irq_desc[M32R_IRQ_MFT2].action = 0; | 315 | irq_desc[M32R_IRQ_MFT2].action = 0; |
316 | irq_desc[M32R_IRQ_MFT2].depth = 1; | 316 | irq_desc[M32R_IRQ_MFT2].depth = 1; |
317 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; | 317 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; |
@@ -319,7 +319,7 @@ void __init init_IRQ(void) | |||
319 | 319 | ||
320 | /* SIO0 : receive */ | 320 | /* SIO0 : receive */ |
321 | irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; | 321 | irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; |
322 | irq_desc[M32R_IRQ_SIO0_R].handler = &opsput_irq_type; | 322 | irq_desc[M32R_IRQ_SIO0_R].chip = &opsput_irq_type; |
323 | irq_desc[M32R_IRQ_SIO0_R].action = 0; | 323 | irq_desc[M32R_IRQ_SIO0_R].action = 0; |
324 | irq_desc[M32R_IRQ_SIO0_R].depth = 1; | 324 | irq_desc[M32R_IRQ_SIO0_R].depth = 1; |
325 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; | 325 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; |
@@ -327,7 +327,7 @@ void __init init_IRQ(void) | |||
327 | 327 | ||
328 | /* SIO0 : send */ | 328 | /* SIO0 : send */ |
329 | irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; | 329 | irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; |
330 | irq_desc[M32R_IRQ_SIO0_S].handler = &opsput_irq_type; | 330 | irq_desc[M32R_IRQ_SIO0_S].chip = &opsput_irq_type; |
331 | irq_desc[M32R_IRQ_SIO0_S].action = 0; | 331 | irq_desc[M32R_IRQ_SIO0_S].action = 0; |
332 | irq_desc[M32R_IRQ_SIO0_S].depth = 1; | 332 | irq_desc[M32R_IRQ_SIO0_S].depth = 1; |
333 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; | 333 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; |
@@ -335,7 +335,7 @@ void __init init_IRQ(void) | |||
335 | 335 | ||
336 | /* SIO1 : receive */ | 336 | /* SIO1 : receive */ |
337 | irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; | 337 | irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; |
338 | irq_desc[M32R_IRQ_SIO1_R].handler = &opsput_irq_type; | 338 | irq_desc[M32R_IRQ_SIO1_R].chip = &opsput_irq_type; |
339 | irq_desc[M32R_IRQ_SIO1_R].action = 0; | 339 | irq_desc[M32R_IRQ_SIO1_R].action = 0; |
340 | irq_desc[M32R_IRQ_SIO1_R].depth = 1; | 340 | irq_desc[M32R_IRQ_SIO1_R].depth = 1; |
341 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; | 341 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; |
@@ -343,7 +343,7 @@ void __init init_IRQ(void) | |||
343 | 343 | ||
344 | /* SIO1 : send */ | 344 | /* SIO1 : send */ |
345 | irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; | 345 | irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; |
346 | irq_desc[M32R_IRQ_SIO1_S].handler = &opsput_irq_type; | 346 | irq_desc[M32R_IRQ_SIO1_S].chip = &opsput_irq_type; |
347 | irq_desc[M32R_IRQ_SIO1_S].action = 0; | 347 | irq_desc[M32R_IRQ_SIO1_S].action = 0; |
348 | irq_desc[M32R_IRQ_SIO1_S].depth = 1; | 348 | irq_desc[M32R_IRQ_SIO1_S].depth = 1; |
349 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; | 349 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; |
@@ -351,7 +351,7 @@ void __init init_IRQ(void) | |||
351 | 351 | ||
352 | /* DMA1 : */ | 352 | /* DMA1 : */ |
353 | irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED; | 353 | irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED; |
354 | irq_desc[M32R_IRQ_DMA1].handler = &opsput_irq_type; | 354 | irq_desc[M32R_IRQ_DMA1].chip = &opsput_irq_type; |
355 | irq_desc[M32R_IRQ_DMA1].action = 0; | 355 | irq_desc[M32R_IRQ_DMA1].action = 0; |
356 | irq_desc[M32R_IRQ_DMA1].depth = 1; | 356 | irq_desc[M32R_IRQ_DMA1].depth = 1; |
357 | icu_data[M32R_IRQ_DMA1].icucr = 0; | 357 | icu_data[M32R_IRQ_DMA1].icucr = 0; |
@@ -360,7 +360,7 @@ void __init init_IRQ(void) | |||
360 | #ifdef CONFIG_SERIAL_M32R_PLDSIO | 360 | #ifdef CONFIG_SERIAL_M32R_PLDSIO |
361 | /* INT#1: SIO0 Receive on PLD */ | 361 | /* INT#1: SIO0 Receive on PLD */ |
362 | irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED; | 362 | irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED; |
363 | irq_desc[PLD_IRQ_SIO0_RCV].handler = &opsput_pld_irq_type; | 363 | irq_desc[PLD_IRQ_SIO0_RCV].chip = &opsput_pld_irq_type; |
364 | irq_desc[PLD_IRQ_SIO0_RCV].action = 0; | 364 | irq_desc[PLD_IRQ_SIO0_RCV].action = 0; |
365 | irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */ | 365 | irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */ |
366 | pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; | 366 | pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; |
@@ -368,7 +368,7 @@ void __init init_IRQ(void) | |||
368 | 368 | ||
369 | /* INT#1: SIO0 Send on PLD */ | 369 | /* INT#1: SIO0 Send on PLD */ |
370 | irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED; | 370 | irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED; |
371 | irq_desc[PLD_IRQ_SIO0_SND].handler = &opsput_pld_irq_type; | 371 | irq_desc[PLD_IRQ_SIO0_SND].chip = &opsput_pld_irq_type; |
372 | irq_desc[PLD_IRQ_SIO0_SND].action = 0; | 372 | irq_desc[PLD_IRQ_SIO0_SND].action = 0; |
373 | irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */ | 373 | irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */ |
374 | pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; | 374 | pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; |
@@ -378,7 +378,7 @@ void __init init_IRQ(void) | |||
378 | #if defined(CONFIG_M32R_CFC) | 378 | #if defined(CONFIG_M32R_CFC) |
379 | /* INT#1: CFC IREQ on PLD */ | 379 | /* INT#1: CFC IREQ on PLD */ |
380 | irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; | 380 | irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; |
381 | irq_desc[PLD_IRQ_CFIREQ].handler = &opsput_pld_irq_type; | 381 | irq_desc[PLD_IRQ_CFIREQ].chip = &opsput_pld_irq_type; |
382 | irq_desc[PLD_IRQ_CFIREQ].action = 0; | 382 | irq_desc[PLD_IRQ_CFIREQ].action = 0; |
383 | irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */ | 383 | irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */ |
384 | pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ | 384 | pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ |
@@ -386,7 +386,7 @@ void __init init_IRQ(void) | |||
386 | 386 | ||
387 | /* INT#1: CFC Insert on PLD */ | 387 | /* INT#1: CFC Insert on PLD */ |
388 | irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; | 388 | irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; |
389 | irq_desc[PLD_IRQ_CFC_INSERT].handler = &opsput_pld_irq_type; | 389 | irq_desc[PLD_IRQ_CFC_INSERT].chip = &opsput_pld_irq_type; |
390 | irq_desc[PLD_IRQ_CFC_INSERT].action = 0; | 390 | irq_desc[PLD_IRQ_CFC_INSERT].action = 0; |
391 | irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */ | 391 | irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */ |
392 | pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ | 392 | pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ |
@@ -394,7 +394,7 @@ void __init init_IRQ(void) | |||
394 | 394 | ||
395 | /* INT#1: CFC Eject on PLD */ | 395 | /* INT#1: CFC Eject on PLD */ |
396 | irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED; | 396 | irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED; |
397 | irq_desc[PLD_IRQ_CFC_EJECT].handler = &opsput_pld_irq_type; | 397 | irq_desc[PLD_IRQ_CFC_EJECT].chip = &opsput_pld_irq_type; |
398 | irq_desc[PLD_IRQ_CFC_EJECT].action = 0; | 398 | irq_desc[PLD_IRQ_CFC_EJECT].action = 0; |
399 | irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */ | 399 | irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */ |
400 | pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ | 400 | pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ |
@@ -420,7 +420,7 @@ void __init init_IRQ(void) | |||
420 | outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ | 420 | outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ |
421 | 421 | ||
422 | irq_desc[OPSPUT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED; | 422 | irq_desc[OPSPUT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED; |
423 | irq_desc[OPSPUT_LCD_IRQ_USB_INT1].handler = &opsput_lcdpld_irq_type; | 423 | irq_desc[OPSPUT_LCD_IRQ_USB_INT1].chip = &opsput_lcdpld_irq_type; |
424 | irq_desc[OPSPUT_LCD_IRQ_USB_INT1].action = 0; | 424 | irq_desc[OPSPUT_LCD_IRQ_USB_INT1].action = 0; |
425 | irq_desc[OPSPUT_LCD_IRQ_USB_INT1].depth = 1; | 425 | irq_desc[OPSPUT_LCD_IRQ_USB_INT1].depth = 1; |
426 | lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ | 426 | lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ |
@@ -438,7 +438,7 @@ void __init init_IRQ(void) | |||
438 | * INT3# is used for AR | 438 | * INT3# is used for AR |
439 | */ | 439 | */ |
440 | irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED; | 440 | irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED; |
441 | irq_desc[M32R_IRQ_INT3].handler = &opsput_irq_type; | 441 | irq_desc[M32R_IRQ_INT3].chip = &opsput_irq_type; |
442 | irq_desc[M32R_IRQ_INT3].action = 0; | 442 | irq_desc[M32R_IRQ_INT3].action = 0; |
443 | irq_desc[M32R_IRQ_INT3].depth = 1; | 443 | irq_desc[M32R_IRQ_INT3].depth = 1; |
444 | icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; | 444 | icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; |
diff --git a/arch/m32r/kernel/setup_usrv.c b/arch/m32r/kernel/setup_usrv.c index 64be659a23e7..7fa12d8f66b4 100644 --- a/arch/m32r/kernel/setup_usrv.c +++ b/arch/m32r/kernel/setup_usrv.c | |||
@@ -158,7 +158,7 @@ void __init init_IRQ(void) | |||
158 | 158 | ||
159 | /* MFT2 : system timer */ | 159 | /* MFT2 : system timer */ |
160 | irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; | 160 | irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; |
161 | irq_desc[M32R_IRQ_MFT2].handler = &mappi_irq_type; | 161 | irq_desc[M32R_IRQ_MFT2].chip = &mappi_irq_type; |
162 | irq_desc[M32R_IRQ_MFT2].action = 0; | 162 | irq_desc[M32R_IRQ_MFT2].action = 0; |
163 | irq_desc[M32R_IRQ_MFT2].depth = 1; | 163 | irq_desc[M32R_IRQ_MFT2].depth = 1; |
164 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; | 164 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; |
@@ -167,7 +167,7 @@ void __init init_IRQ(void) | |||
167 | #if defined(CONFIG_SERIAL_M32R_SIO) | 167 | #if defined(CONFIG_SERIAL_M32R_SIO) |
168 | /* SIO0_R : uart receive data */ | 168 | /* SIO0_R : uart receive data */ |
169 | irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; | 169 | irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; |
170 | irq_desc[M32R_IRQ_SIO0_R].handler = &mappi_irq_type; | 170 | irq_desc[M32R_IRQ_SIO0_R].chip = &mappi_irq_type; |
171 | irq_desc[M32R_IRQ_SIO0_R].action = 0; | 171 | irq_desc[M32R_IRQ_SIO0_R].action = 0; |
172 | irq_desc[M32R_IRQ_SIO0_R].depth = 1; | 172 | irq_desc[M32R_IRQ_SIO0_R].depth = 1; |
173 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; | 173 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; |
@@ -175,7 +175,7 @@ void __init init_IRQ(void) | |||
175 | 175 | ||
176 | /* SIO0_S : uart send data */ | 176 | /* SIO0_S : uart send data */ |
177 | irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; | 177 | irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; |
178 | irq_desc[M32R_IRQ_SIO0_S].handler = &mappi_irq_type; | 178 | irq_desc[M32R_IRQ_SIO0_S].chip = &mappi_irq_type; |
179 | irq_desc[M32R_IRQ_SIO0_S].action = 0; | 179 | irq_desc[M32R_IRQ_SIO0_S].action = 0; |
180 | irq_desc[M32R_IRQ_SIO0_S].depth = 1; | 180 | irq_desc[M32R_IRQ_SIO0_S].depth = 1; |
181 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; | 181 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; |
@@ -183,7 +183,7 @@ void __init init_IRQ(void) | |||
183 | 183 | ||
184 | /* SIO1_R : uart receive data */ | 184 | /* SIO1_R : uart receive data */ |
185 | irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; | 185 | irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; |
186 | irq_desc[M32R_IRQ_SIO1_R].handler = &mappi_irq_type; | 186 | irq_desc[M32R_IRQ_SIO1_R].chip = &mappi_irq_type; |
187 | irq_desc[M32R_IRQ_SIO1_R].action = 0; | 187 | irq_desc[M32R_IRQ_SIO1_R].action = 0; |
188 | irq_desc[M32R_IRQ_SIO1_R].depth = 1; | 188 | irq_desc[M32R_IRQ_SIO1_R].depth = 1; |
189 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; | 189 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; |
@@ -191,7 +191,7 @@ void __init init_IRQ(void) | |||
191 | 191 | ||
192 | /* SIO1_S : uart send data */ | 192 | /* SIO1_S : uart send data */ |
193 | irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; | 193 | irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; |
194 | irq_desc[M32R_IRQ_SIO1_S].handler = &mappi_irq_type; | 194 | irq_desc[M32R_IRQ_SIO1_S].chip = &mappi_irq_type; |
195 | irq_desc[M32R_IRQ_SIO1_S].action = 0; | 195 | irq_desc[M32R_IRQ_SIO1_S].action = 0; |
196 | irq_desc[M32R_IRQ_SIO1_S].depth = 1; | 196 | irq_desc[M32R_IRQ_SIO1_S].depth = 1; |
197 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; | 197 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; |
@@ -201,7 +201,7 @@ void __init init_IRQ(void) | |||
201 | /* INT#67-#71: CFC#0 IREQ on PLD */ | 201 | /* INT#67-#71: CFC#0 IREQ on PLD */ |
202 | for (i = 0 ; i < CONFIG_CFC_NUM ; i++ ) { | 202 | for (i = 0 ; i < CONFIG_CFC_NUM ; i++ ) { |
203 | irq_desc[PLD_IRQ_CF0 + i].status = IRQ_DISABLED; | 203 | irq_desc[PLD_IRQ_CF0 + i].status = IRQ_DISABLED; |
204 | irq_desc[PLD_IRQ_CF0 + i].handler = &m32700ut_pld_irq_type; | 204 | irq_desc[PLD_IRQ_CF0 + i].chip = &m32700ut_pld_irq_type; |
205 | irq_desc[PLD_IRQ_CF0 + i].action = 0; | 205 | irq_desc[PLD_IRQ_CF0 + i].action = 0; |
206 | irq_desc[PLD_IRQ_CF0 + i].depth = 1; /* disable nested irq */ | 206 | irq_desc[PLD_IRQ_CF0 + i].depth = 1; /* disable nested irq */ |
207 | pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr | 207 | pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr |
@@ -212,7 +212,7 @@ void __init init_IRQ(void) | |||
212 | #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) | 212 | #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) |
213 | /* INT#76: 16552D#0 IREQ on PLD */ | 213 | /* INT#76: 16552D#0 IREQ on PLD */ |
214 | irq_desc[PLD_IRQ_UART0].status = IRQ_DISABLED; | 214 | irq_desc[PLD_IRQ_UART0].status = IRQ_DISABLED; |
215 | irq_desc[PLD_IRQ_UART0].handler = &m32700ut_pld_irq_type; | 215 | irq_desc[PLD_IRQ_UART0].chip = &m32700ut_pld_irq_type; |
216 | irq_desc[PLD_IRQ_UART0].action = 0; | 216 | irq_desc[PLD_IRQ_UART0].action = 0; |
217 | irq_desc[PLD_IRQ_UART0].depth = 1; /* disable nested irq */ | 217 | irq_desc[PLD_IRQ_UART0].depth = 1; /* disable nested irq */ |
218 | pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr | 218 | pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr |
@@ -221,7 +221,7 @@ void __init init_IRQ(void) | |||
221 | 221 | ||
222 | /* INT#77: 16552D#1 IREQ on PLD */ | 222 | /* INT#77: 16552D#1 IREQ on PLD */ |
223 | irq_desc[PLD_IRQ_UART1].status = IRQ_DISABLED; | 223 | irq_desc[PLD_IRQ_UART1].status = IRQ_DISABLED; |
224 | irq_desc[PLD_IRQ_UART1].handler = &m32700ut_pld_irq_type; | 224 | irq_desc[PLD_IRQ_UART1].chip = &m32700ut_pld_irq_type; |
225 | irq_desc[PLD_IRQ_UART1].action = 0; | 225 | irq_desc[PLD_IRQ_UART1].action = 0; |
226 | irq_desc[PLD_IRQ_UART1].depth = 1; /* disable nested irq */ | 226 | irq_desc[PLD_IRQ_UART1].depth = 1; /* disable nested irq */ |
227 | pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr | 227 | pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr |
@@ -232,7 +232,7 @@ void __init init_IRQ(void) | |||
232 | #if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE) | 232 | #if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE) |
233 | /* INT#80: AK4524 IREQ on PLD */ | 233 | /* INT#80: AK4524 IREQ on PLD */ |
234 | irq_desc[PLD_IRQ_SNDINT].status = IRQ_DISABLED; | 234 | irq_desc[PLD_IRQ_SNDINT].status = IRQ_DISABLED; |
235 | irq_desc[PLD_IRQ_SNDINT].handler = &m32700ut_pld_irq_type; | 235 | irq_desc[PLD_IRQ_SNDINT].chip = &m32700ut_pld_irq_type; |
236 | irq_desc[PLD_IRQ_SNDINT].action = 0; | 236 | irq_desc[PLD_IRQ_SNDINT].action = 0; |
237 | irq_desc[PLD_IRQ_SNDINT].depth = 1; /* disable nested irq */ | 237 | irq_desc[PLD_IRQ_SNDINT].depth = 1; /* disable nested irq */ |
238 | pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr | 238 | pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr |
diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/au1000/common/irq.c index afe05ec12c27..da74ac21954b 100644 --- a/arch/mips/au1000/common/irq.c +++ b/arch/mips/au1000/common/irq.c | |||
@@ -333,31 +333,31 @@ static void setup_local_irq(unsigned int irq_nr, int type, int int_req) | |||
333 | au_writel(1<<(irq_nr-32), IC1_CFG2CLR); | 333 | au_writel(1<<(irq_nr-32), IC1_CFG2CLR); |
334 | au_writel(1<<(irq_nr-32), IC1_CFG1CLR); | 334 | au_writel(1<<(irq_nr-32), IC1_CFG1CLR); |
335 | au_writel(1<<(irq_nr-32), IC1_CFG0SET); | 335 | au_writel(1<<(irq_nr-32), IC1_CFG0SET); |
336 | irq_desc[irq_nr].handler = &rise_edge_irq_type; | 336 | irq_desc[irq_nr].chip = &rise_edge_irq_type; |
337 | break; | 337 | break; |
338 | case INTC_INT_FALL_EDGE: /* 0:1:0 */ | 338 | case INTC_INT_FALL_EDGE: /* 0:1:0 */ |
339 | au_writel(1<<(irq_nr-32), IC1_CFG2CLR); | 339 | au_writel(1<<(irq_nr-32), IC1_CFG2CLR); |
340 | au_writel(1<<(irq_nr-32), IC1_CFG1SET); | 340 | au_writel(1<<(irq_nr-32), IC1_CFG1SET); |
341 | au_writel(1<<(irq_nr-32), IC1_CFG0CLR); | 341 | au_writel(1<<(irq_nr-32), IC1_CFG0CLR); |
342 | irq_desc[irq_nr].handler = &fall_edge_irq_type; | 342 | irq_desc[irq_nr].chip = &fall_edge_irq_type; |
343 | break; | 343 | break; |
344 | case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ | 344 | case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ |
345 | au_writel(1<<(irq_nr-32), IC1_CFG2CLR); | 345 | au_writel(1<<(irq_nr-32), IC1_CFG2CLR); |
346 | au_writel(1<<(irq_nr-32), IC1_CFG1SET); | 346 | au_writel(1<<(irq_nr-32), IC1_CFG1SET); |
347 | au_writel(1<<(irq_nr-32), IC1_CFG0SET); | 347 | au_writel(1<<(irq_nr-32), IC1_CFG0SET); |
348 | irq_desc[irq_nr].handler = &either_edge_irq_type; | 348 | irq_desc[irq_nr].chip = &either_edge_irq_type; |
349 | break; | 349 | break; |
350 | case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ | 350 | case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ |
351 | au_writel(1<<(irq_nr-32), IC1_CFG2SET); | 351 | au_writel(1<<(irq_nr-32), IC1_CFG2SET); |
352 | au_writel(1<<(irq_nr-32), IC1_CFG1CLR); | 352 | au_writel(1<<(irq_nr-32), IC1_CFG1CLR); |
353 | au_writel(1<<(irq_nr-32), IC1_CFG0SET); | 353 | au_writel(1<<(irq_nr-32), IC1_CFG0SET); |
354 | irq_desc[irq_nr].handler = &level_irq_type; | 354 | irq_desc[irq_nr].chip = &level_irq_type; |
355 | break; | 355 | break; |
356 | case INTC_INT_LOW_LEVEL: /* 1:1:0 */ | 356 | case INTC_INT_LOW_LEVEL: /* 1:1:0 */ |
357 | au_writel(1<<(irq_nr-32), IC1_CFG2SET); | 357 | au_writel(1<<(irq_nr-32), IC1_CFG2SET); |
358 | au_writel(1<<(irq_nr-32), IC1_CFG1SET); | 358 | au_writel(1<<(irq_nr-32), IC1_CFG1SET); |
359 | au_writel(1<<(irq_nr-32), IC1_CFG0CLR); | 359 | au_writel(1<<(irq_nr-32), IC1_CFG0CLR); |
360 | irq_desc[irq_nr].handler = &level_irq_type; | 360 | irq_desc[irq_nr].chip = &level_irq_type; |
361 | break; | 361 | break; |
362 | case INTC_INT_DISABLED: /* 0:0:0 */ | 362 | case INTC_INT_DISABLED: /* 0:0:0 */ |
363 | au_writel(1<<(irq_nr-32), IC1_CFG0CLR); | 363 | au_writel(1<<(irq_nr-32), IC1_CFG0CLR); |
@@ -385,31 +385,31 @@ static void setup_local_irq(unsigned int irq_nr, int type, int int_req) | |||
385 | au_writel(1<<irq_nr, IC0_CFG2CLR); | 385 | au_writel(1<<irq_nr, IC0_CFG2CLR); |
386 | au_writel(1<<irq_nr, IC0_CFG1CLR); | 386 | au_writel(1<<irq_nr, IC0_CFG1CLR); |
387 | au_writel(1<<irq_nr, IC0_CFG0SET); | 387 | au_writel(1<<irq_nr, IC0_CFG0SET); |
388 | irq_desc[irq_nr].handler = &rise_edge_irq_type; | 388 | irq_desc[irq_nr].chip = &rise_edge_irq_type; |
389 | break; | 389 | break; |
390 | case INTC_INT_FALL_EDGE: /* 0:1:0 */ | 390 | case INTC_INT_FALL_EDGE: /* 0:1:0 */ |
391 | au_writel(1<<irq_nr, IC0_CFG2CLR); | 391 | au_writel(1<<irq_nr, IC0_CFG2CLR); |
392 | au_writel(1<<irq_nr, IC0_CFG1SET); | 392 | au_writel(1<<irq_nr, IC0_CFG1SET); |
393 | au_writel(1<<irq_nr, IC0_CFG0CLR); | 393 | au_writel(1<<irq_nr, IC0_CFG0CLR); |
394 | irq_desc[irq_nr].handler = &fall_edge_irq_type; | 394 | irq_desc[irq_nr].chip = &fall_edge_irq_type; |
395 | break; | 395 | break; |
396 | case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ | 396 | case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ |
397 | au_writel(1<<irq_nr, IC0_CFG2CLR); | 397 | au_writel(1<<irq_nr, IC0_CFG2CLR); |
398 | au_writel(1<<irq_nr, IC0_CFG1SET); | 398 | au_writel(1<<irq_nr, IC0_CFG1SET); |
399 | au_writel(1<<irq_nr, IC0_CFG0SET); | 399 | au_writel(1<<irq_nr, IC0_CFG0SET); |
400 | irq_desc[irq_nr].handler = &either_edge_irq_type; | 400 | irq_desc[irq_nr].chip = &either_edge_irq_type; |
401 | break; | 401 | break; |
402 | case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ | 402 | case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ |
403 | au_writel(1<<irq_nr, IC0_CFG2SET); | 403 | au_writel(1<<irq_nr, IC0_CFG2SET); |
404 | au_writel(1<<irq_nr, IC0_CFG1CLR); | 404 | au_writel(1<<irq_nr, IC0_CFG1CLR); |
405 | au_writel(1<<irq_nr, IC0_CFG0SET); | 405 | au_writel(1<<irq_nr, IC0_CFG0SET); |
406 | irq_desc[irq_nr].handler = &level_irq_type; | 406 | irq_desc[irq_nr].chip = &level_irq_type; |
407 | break; | 407 | break; |
408 | case INTC_INT_LOW_LEVEL: /* 1:1:0 */ | 408 | case INTC_INT_LOW_LEVEL: /* 1:1:0 */ |
409 | au_writel(1<<irq_nr, IC0_CFG2SET); | 409 | au_writel(1<<irq_nr, IC0_CFG2SET); |
410 | au_writel(1<<irq_nr, IC0_CFG1SET); | 410 | au_writel(1<<irq_nr, IC0_CFG1SET); |
411 | au_writel(1<<irq_nr, IC0_CFG0CLR); | 411 | au_writel(1<<irq_nr, IC0_CFG0CLR); |
412 | irq_desc[irq_nr].handler = &level_irq_type; | 412 | irq_desc[irq_nr].chip = &level_irq_type; |
413 | break; | 413 | break; |
414 | case INTC_INT_DISABLED: /* 0:0:0 */ | 414 | case INTC_INT_DISABLED: /* 0:0:0 */ |
415 | au_writel(1<<irq_nr, IC0_CFG0CLR); | 415 | au_writel(1<<irq_nr, IC0_CFG0CLR); |
diff --git a/arch/mips/au1000/pb1200/irqmap.c b/arch/mips/au1000/pb1200/irqmap.c index bacc0c6bfe67..5dd164fc1889 100644 --- a/arch/mips/au1000/pb1200/irqmap.c +++ b/arch/mips/au1000/pb1200/irqmap.c | |||
@@ -172,7 +172,7 @@ void _board_init_irq(void) | |||
172 | 172 | ||
173 | for (irq_nr = PB1200_INT_BEGIN; irq_nr <= PB1200_INT_END; irq_nr++) | 173 | for (irq_nr = PB1200_INT_BEGIN; irq_nr <= PB1200_INT_END; irq_nr++) |
174 | { | 174 | { |
175 | irq_desc[irq_nr].handler = &external_irq_type; | 175 | irq_desc[irq_nr].chip = &external_irq_type; |
176 | pb1200_disable_irq(irq_nr); | 176 | pb1200_disable_irq(irq_nr); |
177 | } | 177 | } |
178 | 178 | ||
diff --git a/arch/mips/ddb5xxx/ddb5477/irq_5477.c b/arch/mips/ddb5xxx/ddb5477/irq_5477.c index 5fcd5f070cdc..63c3d6534b3a 100644 --- a/arch/mips/ddb5xxx/ddb5477/irq_5477.c +++ b/arch/mips/ddb5xxx/ddb5477/irq_5477.c | |||
@@ -107,7 +107,7 @@ void __init vrc5477_irq_init(u32 irq_base) | |||
107 | irq_desc[i].status = IRQ_DISABLED; | 107 | irq_desc[i].status = IRQ_DISABLED; |
108 | irq_desc[i].action = NULL; | 108 | irq_desc[i].action = NULL; |
109 | irq_desc[i].depth = 1; | 109 | irq_desc[i].depth = 1; |
110 | irq_desc[i].handler = &vrc5477_irq_controller; | 110 | irq_desc[i].chip = &vrc5477_irq_controller; |
111 | } | 111 | } |
112 | 112 | ||
113 | vrc5477_irq_base = irq_base; | 113 | vrc5477_irq_base = irq_base; |
diff --git a/arch/mips/dec/ioasic-irq.c b/arch/mips/dec/ioasic-irq.c index d5bca5d233b6..da2dbb42f913 100644 --- a/arch/mips/dec/ioasic-irq.c +++ b/arch/mips/dec/ioasic-irq.c | |||
@@ -144,13 +144,13 @@ void __init init_ioasic_irqs(int base) | |||
144 | irq_desc[i].status = IRQ_DISABLED; | 144 | irq_desc[i].status = IRQ_DISABLED; |
145 | irq_desc[i].action = 0; | 145 | irq_desc[i].action = 0; |
146 | irq_desc[i].depth = 1; | 146 | irq_desc[i].depth = 1; |
147 | irq_desc[i].handler = &ioasic_irq_type; | 147 | irq_desc[i].chip = &ioasic_irq_type; |
148 | } | 148 | } |
149 | for (; i < base + IO_IRQ_LINES; i++) { | 149 | for (; i < base + IO_IRQ_LINES; i++) { |
150 | irq_desc[i].status = IRQ_DISABLED; | 150 | irq_desc[i].status = IRQ_DISABLED; |
151 | irq_desc[i].action = 0; | 151 | irq_desc[i].action = 0; |
152 | irq_desc[i].depth = 1; | 152 | irq_desc[i].depth = 1; |
153 | irq_desc[i].handler = &ioasic_dma_irq_type; | 153 | irq_desc[i].chip = &ioasic_dma_irq_type; |
154 | } | 154 | } |
155 | 155 | ||
156 | ioasic_irq_base = base; | 156 | ioasic_irq_base = base; |
diff --git a/arch/mips/dec/kn02-irq.c b/arch/mips/dec/kn02-irq.c index 898bed502a34..d44c00d9e80f 100644 --- a/arch/mips/dec/kn02-irq.c +++ b/arch/mips/dec/kn02-irq.c | |||
@@ -123,7 +123,7 @@ void __init init_kn02_irqs(int base) | |||
123 | irq_desc[i].status = IRQ_DISABLED; | 123 | irq_desc[i].status = IRQ_DISABLED; |
124 | irq_desc[i].action = 0; | 124 | irq_desc[i].action = 0; |
125 | irq_desc[i].depth = 1; | 125 | irq_desc[i].depth = 1; |
126 | irq_desc[i].handler = &kn02_irq_type; | 126 | irq_desc[i].chip = &kn02_irq_type; |
127 | } | 127 | } |
128 | 128 | ||
129 | kn02_irq_base = base; | 129 | kn02_irq_base = base; |
diff --git a/arch/mips/gt64120/ev64120/irq.c b/arch/mips/gt64120/ev64120/irq.c index 46c468b26b30..f489a8067a93 100644 --- a/arch/mips/gt64120/ev64120/irq.c +++ b/arch/mips/gt64120/ev64120/irq.c | |||
@@ -138,7 +138,7 @@ void __init arch_init_irq(void) | |||
138 | /* Let's initialize our IRQ descriptors */ | 138 | /* Let's initialize our IRQ descriptors */ |
139 | for (i = 0; i < NR_IRQS; i++) { | 139 | for (i = 0; i < NR_IRQS; i++) { |
140 | irq_desc[i].status = 0; | 140 | irq_desc[i].status = 0; |
141 | irq_desc[i].handler = &no_irq_type; | 141 | irq_desc[i].chip = &no_irq_type; |
142 | irq_desc[i].action = NULL; | 142 | irq_desc[i].action = NULL; |
143 | irq_desc[i].depth = 0; | 143 | irq_desc[i].depth = 0; |
144 | spin_lock_init(&irq_desc[i].lock); | 144 | spin_lock_init(&irq_desc[i].lock); |
diff --git a/arch/mips/ite-boards/generic/irq.c b/arch/mips/ite-boards/generic/irq.c index 77be7216bdd0..a6749c56fe38 100644 --- a/arch/mips/ite-boards/generic/irq.c +++ b/arch/mips/ite-boards/generic/irq.c | |||
@@ -208,10 +208,10 @@ void __init arch_init_irq(void) | |||
208 | #endif | 208 | #endif |
209 | 209 | ||
210 | for (i = 0; i <= IT8172_LAST_IRQ; i++) { | 210 | for (i = 0; i <= IT8172_LAST_IRQ; i++) { |
211 | irq_desc[i].handler = &it8172_irq_type; | 211 | irq_desc[i].chip = &it8172_irq_type; |
212 | spin_lock_init(&irq_desc[i].lock); | 212 | spin_lock_init(&irq_desc[i].lock); |
213 | } | 213 | } |
214 | irq_desc[MIPS_CPU_TIMER_IRQ].handler = &cp0_irq_type; | 214 | irq_desc[MIPS_CPU_TIMER_IRQ].chip = &cp0_irq_type; |
215 | set_c0_status(ALLINTS_NOTIMER); | 215 | set_c0_status(ALLINTS_NOTIMER); |
216 | } | 216 | } |
217 | 217 | ||
diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c index becc9accd495..478be9858a1e 100644 --- a/arch/mips/jazz/irq.c +++ b/arch/mips/jazz/irq.c | |||
@@ -73,7 +73,7 @@ void __init init_r4030_ints(void) | |||
73 | irq_desc[i].status = IRQ_DISABLED; | 73 | irq_desc[i].status = IRQ_DISABLED; |
74 | irq_desc[i].action = 0; | 74 | irq_desc[i].action = 0; |
75 | irq_desc[i].depth = 1; | 75 | irq_desc[i].depth = 1; |
76 | irq_desc[i].handler = &r4030_irq_type; | 76 | irq_desc[i].chip = &r4030_irq_type; |
77 | } | 77 | } |
78 | 78 | ||
79 | r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0); | 79 | r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0); |
diff --git a/arch/mips/jmr3927/rbhma3100/irq.c b/arch/mips/jmr3927/rbhma3100/irq.c index 11304d1354f4..380046ea1db5 100644 --- a/arch/mips/jmr3927/rbhma3100/irq.c +++ b/arch/mips/jmr3927/rbhma3100/irq.c | |||
@@ -435,7 +435,7 @@ void jmr3927_irq_init(u32 irq_base) | |||
435 | irq_desc[i].status = IRQ_DISABLED; | 435 | irq_desc[i].status = IRQ_DISABLED; |
436 | irq_desc[i].action = NULL; | 436 | irq_desc[i].action = NULL; |
437 | irq_desc[i].depth = 1; | 437 | irq_desc[i].depth = 1; |
438 | irq_desc[i].handler = &jmr3927_irq_controller; | 438 | irq_desc[i].chip = &jmr3927_irq_controller; |
439 | } | 439 | } |
440 | 440 | ||
441 | jmr3927_irq_base = irq_base; | 441 | jmr3927_irq_base = irq_base; |
diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c index 0cb8ed5662f3..91ffb1233cad 100644 --- a/arch/mips/kernel/i8259.c +++ b/arch/mips/kernel/i8259.c | |||
@@ -120,7 +120,7 @@ int i8259A_irq_pending(unsigned int irq) | |||
120 | void make_8259A_irq(unsigned int irq) | 120 | void make_8259A_irq(unsigned int irq) |
121 | { | 121 | { |
122 | disable_irq_nosync(irq); | 122 | disable_irq_nosync(irq); |
123 | irq_desc[irq].handler = &i8259A_irq_type; | 123 | irq_desc[irq].chip = &i8259A_irq_type; |
124 | enable_irq(irq); | 124 | enable_irq(irq); |
125 | } | 125 | } |
126 | 126 | ||
@@ -327,7 +327,7 @@ void __init init_i8259_irqs (void) | |||
327 | irq_desc[i].status = IRQ_DISABLED; | 327 | irq_desc[i].status = IRQ_DISABLED; |
328 | irq_desc[i].action = NULL; | 328 | irq_desc[i].action = NULL; |
329 | irq_desc[i].depth = 1; | 329 | irq_desc[i].depth = 1; |
330 | irq_desc[i].handler = &i8259A_irq_type; | 330 | irq_desc[i].chip = &i8259A_irq_type; |
331 | } | 331 | } |
332 | 332 | ||
333 | setup_irq(2, &irq2); | 333 | setup_irq(2, &irq2); |
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c index 97ebdc754b9e..f8cd1ac64d88 100644 --- a/arch/mips/kernel/irq-msc01.c +++ b/arch/mips/kernel/irq-msc01.c | |||
@@ -174,14 +174,14 @@ void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq) | |||
174 | 174 | ||
175 | switch (imp->im_type) { | 175 | switch (imp->im_type) { |
176 | case MSC01_IRQ_EDGE: | 176 | case MSC01_IRQ_EDGE: |
177 | irq_desc[base+n].handler = &msc_edgeirq_type; | 177 | irq_desc[base+n].chip = &msc_edgeirq_type; |
178 | if (cpu_has_veic) | 178 | if (cpu_has_veic) |
179 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); | 179 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); |
180 | else | 180 | else |
181 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); | 181 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); |
182 | break; | 182 | break; |
183 | case MSC01_IRQ_LEVEL: | 183 | case MSC01_IRQ_LEVEL: |
184 | irq_desc[base+n].handler = &msc_levelirq_type; | 184 | irq_desc[base+n].chip = &msc_levelirq_type; |
185 | if (cpu_has_veic) | 185 | if (cpu_has_veic) |
186 | MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); | 186 | MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); |
187 | else | 187 | else |
diff --git a/arch/mips/kernel/irq-mv6434x.c b/arch/mips/kernel/irq-mv6434x.c index 0613f1f36b1b..f9c763a65547 100644 --- a/arch/mips/kernel/irq-mv6434x.c +++ b/arch/mips/kernel/irq-mv6434x.c | |||
@@ -155,7 +155,7 @@ void __init mv64340_irq_init(unsigned int base) | |||
155 | irq_desc[i].status = IRQ_DISABLED; | 155 | irq_desc[i].status = IRQ_DISABLED; |
156 | irq_desc[i].action = 0; | 156 | irq_desc[i].action = 0; |
157 | irq_desc[i].depth = 2; | 157 | irq_desc[i].depth = 2; |
158 | irq_desc[i].handler = &mv64340_irq_type; | 158 | irq_desc[i].chip = &mv64340_irq_type; |
159 | } | 159 | } |
160 | 160 | ||
161 | irq_base = base; | 161 | irq_base = base; |
diff --git a/arch/mips/kernel/irq-rm7000.c b/arch/mips/kernel/irq-rm7000.c index 0b130c5ac5d9..121da385a94d 100644 --- a/arch/mips/kernel/irq-rm7000.c +++ b/arch/mips/kernel/irq-rm7000.c | |||
@@ -91,7 +91,7 @@ void __init rm7k_cpu_irq_init(int base) | |||
91 | irq_desc[i].status = IRQ_DISABLED; | 91 | irq_desc[i].status = IRQ_DISABLED; |
92 | irq_desc[i].action = NULL; | 92 | irq_desc[i].action = NULL; |
93 | irq_desc[i].depth = 1; | 93 | irq_desc[i].depth = 1; |
94 | irq_desc[i].handler = &rm7k_irq_controller; | 94 | irq_desc[i].chip = &rm7k_irq_controller; |
95 | } | 95 | } |
96 | 96 | ||
97 | irq_base = base; | 97 | irq_base = base; |
diff --git a/arch/mips/kernel/irq-rm9000.c b/arch/mips/kernel/irq-rm9000.c index 9b5f20c32acb..25109c103e44 100644 --- a/arch/mips/kernel/irq-rm9000.c +++ b/arch/mips/kernel/irq-rm9000.c | |||
@@ -139,11 +139,11 @@ void __init rm9k_cpu_irq_init(int base) | |||
139 | irq_desc[i].status = IRQ_DISABLED; | 139 | irq_desc[i].status = IRQ_DISABLED; |
140 | irq_desc[i].action = NULL; | 140 | irq_desc[i].action = NULL; |
141 | irq_desc[i].depth = 1; | 141 | irq_desc[i].depth = 1; |
142 | irq_desc[i].handler = &rm9k_irq_controller; | 142 | irq_desc[i].chip = &rm9k_irq_controller; |
143 | } | 143 | } |
144 | 144 | ||
145 | rm9000_perfcount_irq = base + 1; | 145 | rm9000_perfcount_irq = base + 1; |
146 | irq_desc[rm9000_perfcount_irq].handler = &rm9k_perfcounter_irq; | 146 | irq_desc[rm9000_perfcount_irq].chip = &rm9k_perfcounter_irq; |
147 | 147 | ||
148 | irq_base = base; | 148 | irq_base = base; |
149 | } | 149 | } |
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index 3dce742e716f..5c9dcd5eed59 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c | |||
@@ -95,7 +95,7 @@ int show_interrupts(struct seq_file *p, void *v) | |||
95 | for_each_online_cpu(j) | 95 | for_each_online_cpu(j) |
96 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); | 96 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); |
97 | #endif | 97 | #endif |
98 | seq_printf(p, " %14s", irq_desc[i].handler->typename); | 98 | seq_printf(p, " %14s", irq_desc[i].chip->typename); |
99 | seq_printf(p, " %s", action->name); | 99 | seq_printf(p, " %s", action->name); |
100 | 100 | ||
101 | for (action=action->next; action; action = action->next) | 101 | for (action=action->next; action; action = action->next) |
@@ -137,7 +137,7 @@ void __init init_IRQ(void) | |||
137 | irq_desc[i].status = IRQ_DISABLED; | 137 | irq_desc[i].status = IRQ_DISABLED; |
138 | irq_desc[i].action = NULL; | 138 | irq_desc[i].action = NULL; |
139 | irq_desc[i].depth = 1; | 139 | irq_desc[i].depth = 1; |
140 | irq_desc[i].handler = &no_irq_type; | 140 | irq_desc[i].chip = &no_irq_type; |
141 | spin_lock_init(&irq_desc[i].lock); | 141 | spin_lock_init(&irq_desc[i].lock); |
142 | #ifdef CONFIG_MIPS_MT_SMTC | 142 | #ifdef CONFIG_MIPS_MT_SMTC |
143 | irq_hwmask[i] = 0; | 143 | irq_hwmask[i] = 0; |
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c index 5db67e31ec1a..0e455a8ad860 100644 --- a/arch/mips/kernel/irq_cpu.c +++ b/arch/mips/kernel/irq_cpu.c | |||
@@ -167,14 +167,14 @@ void __init mips_cpu_irq_init(int irq_base) | |||
167 | irq_desc[i].status = IRQ_DISABLED; | 167 | irq_desc[i].status = IRQ_DISABLED; |
168 | irq_desc[i].action = NULL; | 168 | irq_desc[i].action = NULL; |
169 | irq_desc[i].depth = 1; | 169 | irq_desc[i].depth = 1; |
170 | irq_desc[i].handler = &mips_mt_cpu_irq_controller; | 170 | irq_desc[i].chip = &mips_mt_cpu_irq_controller; |
171 | } | 171 | } |
172 | 172 | ||
173 | for (i = irq_base + 2; i < irq_base + 8; i++) { | 173 | for (i = irq_base + 2; i < irq_base + 8; i++) { |
174 | irq_desc[i].status = IRQ_DISABLED; | 174 | irq_desc[i].status = IRQ_DISABLED; |
175 | irq_desc[i].action = NULL; | 175 | irq_desc[i].action = NULL; |
176 | irq_desc[i].depth = 1; | 176 | irq_desc[i].depth = 1; |
177 | irq_desc[i].handler = &mips_cpu_irq_controller; | 177 | irq_desc[i].chip = &mips_cpu_irq_controller; |
178 | } | 178 | } |
179 | 179 | ||
180 | mips_cpu_irq_base = irq_base; | 180 | mips_cpu_irq_base = irq_base; |
diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c index 2d3472b21ebb..9316a024a818 100644 --- a/arch/mips/lasat/interrupt.c +++ b/arch/mips/lasat/interrupt.c | |||
@@ -156,6 +156,6 @@ void __init arch_init_irq(void) | |||
156 | irq_desc[i].status = IRQ_DISABLED; | 156 | irq_desc[i].status = IRQ_DISABLED; |
157 | irq_desc[i].action = 0; | 157 | irq_desc[i].action = 0; |
158 | irq_desc[i].depth = 1; | 158 | irq_desc[i].depth = 1; |
159 | irq_desc[i].handler = &lasat_irq_type; | 159 | irq_desc[i].chip = &lasat_irq_type; |
160 | } | 160 | } |
161 | } | 161 | } |
diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c index db53950b7cfb..9dd6b8925581 100644 --- a/arch/mips/mips-boards/atlas/atlas_int.c +++ b/arch/mips/mips-boards/atlas/atlas_int.c | |||
@@ -215,7 +215,7 @@ void __init arch_init_irq(void) | |||
215 | irq_desc[i].status = IRQ_DISABLED; | 215 | irq_desc[i].status = IRQ_DISABLED; |
216 | irq_desc[i].action = 0; | 216 | irq_desc[i].action = 0; |
217 | irq_desc[i].depth = 1; | 217 | irq_desc[i].depth = 1; |
218 | irq_desc[i].handler = &atlas_irq_type; | 218 | irq_desc[i].chip = &atlas_irq_type; |
219 | spin_lock_init(&irq_desc[i].lock); | 219 | spin_lock_init(&irq_desc[i].lock); |
220 | } | 220 | } |
221 | } | 221 | } |
diff --git a/arch/mips/momentum/ocelot_c/cpci-irq.c b/arch/mips/momentum/ocelot_c/cpci-irq.c index bd885785e2f9..31d179c4673f 100644 --- a/arch/mips/momentum/ocelot_c/cpci-irq.c +++ b/arch/mips/momentum/ocelot_c/cpci-irq.c | |||
@@ -147,6 +147,6 @@ void cpci_irq_init(void) | |||
147 | irq_desc[i].status = IRQ_DISABLED; | 147 | irq_desc[i].status = IRQ_DISABLED; |
148 | irq_desc[i].action = 0; | 148 | irq_desc[i].action = 0; |
149 | irq_desc[i].depth = 2; | 149 | irq_desc[i].depth = 2; |
150 | irq_desc[i].handler = &cpci_irq_type; | 150 | irq_desc[i].chip = &cpci_irq_type; |
151 | } | 151 | } |
152 | } | 152 | } |
diff --git a/arch/mips/momentum/ocelot_c/uart-irq.c b/arch/mips/momentum/ocelot_c/uart-irq.c index 755bde5146be..852265026fd1 100644 --- a/arch/mips/momentum/ocelot_c/uart-irq.c +++ b/arch/mips/momentum/ocelot_c/uart-irq.c | |||
@@ -137,10 +137,10 @@ void uart_irq_init(void) | |||
137 | irq_desc[80].status = IRQ_DISABLED; | 137 | irq_desc[80].status = IRQ_DISABLED; |
138 | irq_desc[80].action = 0; | 138 | irq_desc[80].action = 0; |
139 | irq_desc[80].depth = 2; | 139 | irq_desc[80].depth = 2; |
140 | irq_desc[80].handler = &uart_irq_type; | 140 | irq_desc[80].chip = &uart_irq_type; |
141 | 141 | ||
142 | irq_desc[81].status = IRQ_DISABLED; | 142 | irq_desc[81].status = IRQ_DISABLED; |
143 | irq_desc[81].action = 0; | 143 | irq_desc[81].action = 0; |
144 | irq_desc[81].depth = 2; | 144 | irq_desc[81].depth = 2; |
145 | irq_desc[81].handler = &uart_irq_type; | 145 | irq_desc[81].chip = &uart_irq_type; |
146 | } | 146 | } |
diff --git a/arch/mips/philips/pnx8550/common/int.c b/arch/mips/philips/pnx8550/common/int.c index 39ee6314f627..8f18764a2359 100644 --- a/arch/mips/philips/pnx8550/common/int.c +++ b/arch/mips/philips/pnx8550/common/int.c | |||
@@ -236,7 +236,7 @@ void __init arch_init_irq(void) | |||
236 | int configPR; | 236 | int configPR; |
237 | 237 | ||
238 | for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) { | 238 | for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) { |
239 | irq_desc[i].handler = &level_irq_type; | 239 | irq_desc[i].chip = &level_irq_type; |
240 | pnx8550_ack(i); /* mask the irq just in case */ | 240 | pnx8550_ack(i); /* mask the irq just in case */ |
241 | } | 241 | } |
242 | 242 | ||
@@ -273,7 +273,7 @@ void __init arch_init_irq(void) | |||
273 | /* mask/priority is still 0 so we will not get any | 273 | /* mask/priority is still 0 so we will not get any |
274 | * interrupts until it is unmasked */ | 274 | * interrupts until it is unmasked */ |
275 | 275 | ||
276 | irq_desc[i].handler = &level_irq_type; | 276 | irq_desc[i].chip = &level_irq_type; |
277 | } | 277 | } |
278 | 278 | ||
279 | /* Priority level 0 */ | 279 | /* Priority level 0 */ |
@@ -282,12 +282,12 @@ void __init arch_init_irq(void) | |||
282 | /* Set int vector table address */ | 282 | /* Set int vector table address */ |
283 | PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0; | 283 | PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0; |
284 | 284 | ||
285 | irq_desc[MIPS_CPU_GIC_IRQ].handler = &level_irq_type; | 285 | irq_desc[MIPS_CPU_GIC_IRQ].chip = &level_irq_type; |
286 | setup_irq(MIPS_CPU_GIC_IRQ, &gic_action); | 286 | setup_irq(MIPS_CPU_GIC_IRQ, &gic_action); |
287 | 287 | ||
288 | /* init of Timer interrupts */ | 288 | /* init of Timer interrupts */ |
289 | for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++) { | 289 | for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++) { |
290 | irq_desc[i].handler = &level_irq_type; | 290 | irq_desc[i].chip = &level_irq_type; |
291 | } | 291 | } |
292 | 292 | ||
293 | /* Stop Timer 1-3 */ | 293 | /* Stop Timer 1-3 */ |
@@ -295,7 +295,7 @@ void __init arch_init_irq(void) | |||
295 | configPR |= 0x00000038; | 295 | configPR |= 0x00000038; |
296 | write_c0_config7(configPR); | 296 | write_c0_config7(configPR); |
297 | 297 | ||
298 | irq_desc[MIPS_CPU_TIMER_IRQ].handler = &level_irq_type; | 298 | irq_desc[MIPS_CPU_TIMER_IRQ].chip = &level_irq_type; |
299 | setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action); | 299 | setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action); |
300 | } | 300 | } |
301 | 301 | ||
diff --git a/arch/mips/sgi-ip22/ip22-eisa.c b/arch/mips/sgi-ip22/ip22-eisa.c index b19820110aa3..989167b49ce9 100644 --- a/arch/mips/sgi-ip22/ip22-eisa.c +++ b/arch/mips/sgi-ip22/ip22-eisa.c | |||
@@ -279,9 +279,9 @@ int __init ip22_eisa_init(void) | |||
279 | irq_desc[i].action = 0; | 279 | irq_desc[i].action = 0; |
280 | irq_desc[i].depth = 1; | 280 | irq_desc[i].depth = 1; |
281 | if (i < (SGINT_EISA + 8)) | 281 | if (i < (SGINT_EISA + 8)) |
282 | irq_desc[i].handler = &ip22_eisa1_irq_type; | 282 | irq_desc[i].chip = &ip22_eisa1_irq_type; |
283 | else | 283 | else |
284 | irq_desc[i].handler = &ip22_eisa2_irq_type; | 284 | irq_desc[i].chip = &ip22_eisa2_irq_type; |
285 | } | 285 | } |
286 | 286 | ||
287 | /* Cannot use request_irq because of kmalloc not being ready at such | 287 | /* Cannot use request_irq because of kmalloc not being ready at such |
diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c index fc6a7e2b189c..18906af69691 100644 --- a/arch/mips/sgi-ip22/ip22-int.c +++ b/arch/mips/sgi-ip22/ip22-int.c | |||
@@ -436,7 +436,7 @@ void __init arch_init_irq(void) | |||
436 | irq_desc[i].status = IRQ_DISABLED; | 436 | irq_desc[i].status = IRQ_DISABLED; |
437 | irq_desc[i].action = 0; | 437 | irq_desc[i].action = 0; |
438 | irq_desc[i].depth = 1; | 438 | irq_desc[i].depth = 1; |
439 | irq_desc[i].handler = handler; | 439 | irq_desc[i].chip = handler; |
440 | } | 440 | } |
441 | 441 | ||
442 | /* vector handler. this register the IRQ as non-sharable */ | 442 | /* vector handler. this register the IRQ as non-sharable */ |
diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c index 0b61a39ce2bb..869566c360ae 100644 --- a/arch/mips/sgi-ip27/ip27-irq.c +++ b/arch/mips/sgi-ip27/ip27-irq.c | |||
@@ -386,7 +386,7 @@ void __devinit register_bridge_irq(unsigned int irq) | |||
386 | irq_desc[irq].status = IRQ_DISABLED; | 386 | irq_desc[irq].status = IRQ_DISABLED; |
387 | irq_desc[irq].action = 0; | 387 | irq_desc[irq].action = 0; |
388 | irq_desc[irq].depth = 1; | 388 | irq_desc[irq].depth = 1; |
389 | irq_desc[irq].handler = &bridge_irq_type; | 389 | irq_desc[irq].chip = &bridge_irq_type; |
390 | } | 390 | } |
391 | 391 | ||
392 | int __devinit request_bridge_irq(struct bridge_controller *bc) | 392 | int __devinit request_bridge_irq(struct bridge_controller *bc) |
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c index 8ba08047d164..00b94aaf6371 100644 --- a/arch/mips/sgi-ip32/ip32-irq.c +++ b/arch/mips/sgi-ip32/ip32-irq.c | |||
@@ -591,7 +591,7 @@ void __init arch_init_irq(void) | |||
591 | irq_desc[irq].status = IRQ_DISABLED; | 591 | irq_desc[irq].status = IRQ_DISABLED; |
592 | irq_desc[irq].action = 0; | 592 | irq_desc[irq].action = 0; |
593 | irq_desc[irq].depth = 0; | 593 | irq_desc[irq].depth = 0; |
594 | irq_desc[irq].handler = controller; | 594 | irq_desc[irq].chip = controller; |
595 | } | 595 | } |
596 | setup_irq(CRIME_MEMERR_IRQ, &memerr_irq); | 596 | setup_irq(CRIME_MEMERR_IRQ, &memerr_irq); |
597 | setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq); | 597 | setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq); |
diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c index e61760b14d99..610df40cb820 100644 --- a/arch/mips/sibyte/bcm1480/irq.c +++ b/arch/mips/sibyte/bcm1480/irq.c | |||
@@ -276,10 +276,10 @@ void __init init_bcm1480_irqs(void) | |||
276 | irq_desc[i].action = 0; | 276 | irq_desc[i].action = 0; |
277 | irq_desc[i].depth = 1; | 277 | irq_desc[i].depth = 1; |
278 | if (i < BCM1480_NR_IRQS) { | 278 | if (i < BCM1480_NR_IRQS) { |
279 | irq_desc[i].handler = &bcm1480_irq_type; | 279 | irq_desc[i].chip = &bcm1480_irq_type; |
280 | bcm1480_irq_owner[i] = 0; | 280 | bcm1480_irq_owner[i] = 0; |
281 | } else { | 281 | } else { |
282 | irq_desc[i].handler = &no_irq_type; | 282 | irq_desc[i].chip = &no_irq_type; |
283 | } | 283 | } |
284 | } | 284 | } |
285 | } | 285 | } |
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c index f853c32f60a0..fcc61940f1ff 100644 --- a/arch/mips/sibyte/sb1250/irq.c +++ b/arch/mips/sibyte/sb1250/irq.c | |||
@@ -246,10 +246,10 @@ void __init init_sb1250_irqs(void) | |||
246 | irq_desc[i].action = 0; | 246 | irq_desc[i].action = 0; |
247 | irq_desc[i].depth = 1; | 247 | irq_desc[i].depth = 1; |
248 | if (i < SB1250_NR_IRQS) { | 248 | if (i < SB1250_NR_IRQS) { |
249 | irq_desc[i].handler = &sb1250_irq_type; | 249 | irq_desc[i].chip = &sb1250_irq_type; |
250 | sb1250_irq_owner[i] = 0; | 250 | sb1250_irq_owner[i] = 0; |
251 | } else { | 251 | } else { |
252 | irq_desc[i].handler = &no_irq_type; | 252 | irq_desc[i].chip = &no_irq_type; |
253 | } | 253 | } |
254 | } | 254 | } |
255 | } | 255 | } |
diff --git a/arch/mips/sni/irq.c b/arch/mips/sni/irq.c index 7365b4853ddb..c19e158ec402 100644 --- a/arch/mips/sni/irq.c +++ b/arch/mips/sni/irq.c | |||
@@ -203,7 +203,7 @@ void __init arch_init_irq(void) | |||
203 | irq_desc[i].status = IRQ_DISABLED; | 203 | irq_desc[i].status = IRQ_DISABLED; |
204 | irq_desc[i].action = 0; | 204 | irq_desc[i].action = 0; |
205 | irq_desc[i].depth = 1; | 205 | irq_desc[i].depth = 1; |
206 | irq_desc[i].handler = &pciasic_irq_type; | 206 | irq_desc[i].chip = &pciasic_irq_type; |
207 | } | 207 | } |
208 | 208 | ||
209 | change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ2|IE_IRQ3|IE_IRQ4); | 209 | change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ2|IE_IRQ3|IE_IRQ4); |
diff --git a/arch/mips/tx4927/common/tx4927_irq.c b/arch/mips/tx4927/common/tx4927_irq.c index 8ca68015cf40..a42be00483e6 100644 --- a/arch/mips/tx4927/common/tx4927_irq.c +++ b/arch/mips/tx4927/common/tx4927_irq.c | |||
@@ -227,7 +227,7 @@ static void __init tx4927_irq_cp0_init(void) | |||
227 | irq_desc[i].status = IRQ_DISABLED; | 227 | irq_desc[i].status = IRQ_DISABLED; |
228 | irq_desc[i].action = 0; | 228 | irq_desc[i].action = 0; |
229 | irq_desc[i].depth = 1; | 229 | irq_desc[i].depth = 1; |
230 | irq_desc[i].handler = &tx4927_irq_cp0_type; | 230 | irq_desc[i].chip = &tx4927_irq_cp0_type; |
231 | } | 231 | } |
232 | 232 | ||
233 | return; | 233 | return; |
@@ -435,7 +435,7 @@ static void __init tx4927_irq_pic_init(void) | |||
435 | irq_desc[i].status = IRQ_DISABLED; | 435 | irq_desc[i].status = IRQ_DISABLED; |
436 | irq_desc[i].action = 0; | 436 | irq_desc[i].action = 0; |
437 | irq_desc[i].depth = 2; | 437 | irq_desc[i].depth = 2; |
438 | irq_desc[i].handler = &tx4927_irq_pic_type; | 438 | irq_desc[i].chip = &tx4927_irq_pic_type; |
439 | } | 439 | } |
440 | 440 | ||
441 | setup_irq(TX4927_IRQ_NEST_PIC_ON_CP0, &tx4927_irq_pic_action); | 441 | setup_irq(TX4927_IRQ_NEST_PIC_ON_CP0, &tx4927_irq_pic_action); |
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c index aee07ff2212a..c67978b6dae4 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c +++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c | |||
@@ -368,7 +368,7 @@ static void __init toshiba_rbtx4927_irq_ioc_init(void) | |||
368 | irq_desc[i].status = IRQ_DISABLED; | 368 | irq_desc[i].status = IRQ_DISABLED; |
369 | irq_desc[i].action = 0; | 369 | irq_desc[i].action = 0; |
370 | irq_desc[i].depth = 3; | 370 | irq_desc[i].depth = 3; |
371 | irq_desc[i].handler = &toshiba_rbtx4927_irq_ioc_type; | 371 | irq_desc[i].chip = &toshiba_rbtx4927_irq_ioc_type; |
372 | } | 372 | } |
373 | 373 | ||
374 | setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC, | 374 | setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC, |
@@ -526,7 +526,7 @@ static void __init toshiba_rbtx4927_irq_isa_init(void) | |||
526 | irq_desc[i].action = 0; | 526 | irq_desc[i].action = 0; |
527 | irq_desc[i].depth = | 527 | irq_desc[i].depth = |
528 | ((i < TOSHIBA_RBTX4927_IRQ_ISA_MID) ? (4) : (5)); | 528 | ((i < TOSHIBA_RBTX4927_IRQ_ISA_MID) ? (4) : (5)); |
529 | irq_desc[i].handler = &toshiba_rbtx4927_irq_isa_type; | 529 | irq_desc[i].chip = &toshiba_rbtx4927_irq_isa_type; |
530 | } | 530 | } |
531 | 531 | ||
532 | setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC, | 532 | setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC, |
@@ -692,13 +692,13 @@ void toshiba_rbtx4927_irq_dump(char *key) | |||
692 | { | 692 | { |
693 | u32 i, j = 0; | 693 | u32 i, j = 0; |
694 | for (i = 0; i < NR_IRQS; i++) { | 694 | for (i = 0; i < NR_IRQS; i++) { |
695 | if (strcmp(irq_desc[i].handler->typename, "none") | 695 | if (strcmp(irq_desc[i].chip->typename, "none") |
696 | == 0) | 696 | == 0) |
697 | continue; | 697 | continue; |
698 | 698 | ||
699 | if ((i >= 1) | 699 | if ((i >= 1) |
700 | && (irq_desc[i - 1].handler->typename == | 700 | && (irq_desc[i - 1].chip->typename == |
701 | irq_desc[i].handler->typename)) { | 701 | irq_desc[i].chip->typename)) { |
702 | j++; | 702 | j++; |
703 | } else { | 703 | } else { |
704 | j = 0; | 704 | j = 0; |
@@ -707,12 +707,12 @@ void toshiba_rbtx4927_irq_dump(char *key) | |||
707 | (TOSHIBA_RBTX4927_IRQ_INFO, | 707 | (TOSHIBA_RBTX4927_IRQ_INFO, |
708 | "%s irq=0x%02x/%3d s=0x%08x h=0x%08x a=0x%08x ah=0x%08x d=%1d n=%s/%02d\n", | 708 | "%s irq=0x%02x/%3d s=0x%08x h=0x%08x a=0x%08x ah=0x%08x d=%1d n=%s/%02d\n", |
709 | key, i, i, irq_desc[i].status, | 709 | key, i, i, irq_desc[i].status, |
710 | (u32) irq_desc[i].handler, | 710 | (u32) irq_desc[i].chip, |
711 | (u32) irq_desc[i].action, | 711 | (u32) irq_desc[i].action, |
712 | (u32) (irq_desc[i].action ? irq_desc[i]. | 712 | (u32) (irq_desc[i].action ? irq_desc[i]. |
713 | action->handler : 0), | 713 | action->handler : 0), |
714 | irq_desc[i].depth, | 714 | irq_desc[i].depth, |
715 | irq_desc[i].handler->typename, j); | 715 | irq_desc[i].chip->typename, j); |
716 | } | 716 | } |
717 | } | 717 | } |
718 | #endif | 718 | #endif |
diff --git a/arch/mips/tx4938/common/irq.c b/arch/mips/tx4938/common/irq.c index 873805178d8e..0b2f8c849218 100644 --- a/arch/mips/tx4938/common/irq.c +++ b/arch/mips/tx4938/common/irq.c | |||
@@ -102,7 +102,7 @@ tx4938_irq_cp0_init(void) | |||
102 | irq_desc[i].status = IRQ_DISABLED; | 102 | irq_desc[i].status = IRQ_DISABLED; |
103 | irq_desc[i].action = 0; | 103 | irq_desc[i].action = 0; |
104 | irq_desc[i].depth = 1; | 104 | irq_desc[i].depth = 1; |
105 | irq_desc[i].handler = &tx4938_irq_cp0_type; | 105 | irq_desc[i].chip = &tx4938_irq_cp0_type; |
106 | } | 106 | } |
107 | 107 | ||
108 | return; | 108 | return; |
@@ -306,7 +306,7 @@ tx4938_irq_pic_init(void) | |||
306 | irq_desc[i].status = IRQ_DISABLED; | 306 | irq_desc[i].status = IRQ_DISABLED; |
307 | irq_desc[i].action = 0; | 307 | irq_desc[i].action = 0; |
308 | irq_desc[i].depth = 2; | 308 | irq_desc[i].depth = 2; |
309 | irq_desc[i].handler = &tx4938_irq_pic_type; | 309 | irq_desc[i].chip = &tx4938_irq_pic_type; |
310 | } | 310 | } |
311 | 311 | ||
312 | setup_irq(TX4938_IRQ_NEST_PIC_ON_CP0, &tx4938_irq_pic_action); | 312 | setup_irq(TX4938_IRQ_NEST_PIC_ON_CP0, &tx4938_irq_pic_action); |
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/irq.c b/arch/mips/tx4938/toshiba_rbtx4938/irq.c index 9cd9c0fe2265..3b8245dc5bd3 100644 --- a/arch/mips/tx4938/toshiba_rbtx4938/irq.c +++ b/arch/mips/tx4938/toshiba_rbtx4938/irq.c | |||
@@ -146,7 +146,7 @@ toshiba_rbtx4938_irq_ioc_init(void) | |||
146 | irq_desc[i].status = IRQ_DISABLED; | 146 | irq_desc[i].status = IRQ_DISABLED; |
147 | irq_desc[i].action = 0; | 147 | irq_desc[i].action = 0; |
148 | irq_desc[i].depth = 3; | 148 | irq_desc[i].depth = 3; |
149 | irq_desc[i].handler = &toshiba_rbtx4938_irq_ioc_type; | 149 | irq_desc[i].chip = &toshiba_rbtx4938_irq_ioc_type; |
150 | } | 150 | } |
151 | 151 | ||
152 | setup_irq(RBTX4938_IRQ_IOCINT, | 152 | setup_irq(RBTX4938_IRQ_IOCINT, |
diff --git a/arch/mips/vr41xx/common/icu.c b/arch/mips/vr41xx/common/icu.c index 07ae19cf0c29..b9323302cc4e 100644 --- a/arch/mips/vr41xx/common/icu.c +++ b/arch/mips/vr41xx/common/icu.c | |||
@@ -722,10 +722,10 @@ static int __init vr41xx_icu_init(void) | |||
722 | icu2_write(MGIUINTHREG, 0xffff); | 722 | icu2_write(MGIUINTHREG, 0xffff); |
723 | 723 | ||
724 | for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++) | 724 | for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++) |
725 | irq_desc[i].handler = &sysint1_irq_type; | 725 | irq_desc[i].chip = &sysint1_irq_type; |
726 | 726 | ||
727 | for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++) | 727 | for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++) |
728 | irq_desc[i].handler = &sysint2_irq_type; | 728 | irq_desc[i].chip = &sysint2_irq_type; |
729 | 729 | ||
730 | cascade_irq(INT0_IRQ, icu_get_irq); | 730 | cascade_irq(INT0_IRQ, icu_get_irq); |
731 | cascade_irq(INT1_IRQ, icu_get_irq); | 731 | cascade_irq(INT1_IRQ, icu_get_irq); |
diff --git a/arch/mips/vr41xx/common/irq.c b/arch/mips/vr41xx/common/irq.c index 86796bb63c3c..66aa50802deb 100644 --- a/arch/mips/vr41xx/common/irq.c +++ b/arch/mips/vr41xx/common/irq.c | |||
@@ -73,13 +73,13 @@ static void irq_dispatch(unsigned int irq, struct pt_regs *regs) | |||
73 | if (cascade->get_irq != NULL) { | 73 | if (cascade->get_irq != NULL) { |
74 | unsigned int source_irq = irq; | 74 | unsigned int source_irq = irq; |
75 | desc = irq_desc + source_irq; | 75 | desc = irq_desc + source_irq; |
76 | desc->handler->ack(source_irq); | 76 | desc->chip->ack(source_irq); |
77 | irq = cascade->get_irq(irq, regs); | 77 | irq = cascade->get_irq(irq, regs); |
78 | if (irq < 0) | 78 | if (irq < 0) |
79 | atomic_inc(&irq_err_count); | 79 | atomic_inc(&irq_err_count); |
80 | else | 80 | else |
81 | irq_dispatch(irq, regs); | 81 | irq_dispatch(irq, regs); |
82 | desc->handler->end(source_irq); | 82 | desc->chip->end(source_irq); |
83 | } else | 83 | } else |
84 | do_IRQ(irq, regs); | 84 | do_IRQ(irq, regs); |
85 | } | 85 | } |
diff --git a/arch/mips/vr41xx/common/vrc4173.c b/arch/mips/vr41xx/common/vrc4173.c index 3e31f8193d21..2d287b8893d9 100644 --- a/arch/mips/vr41xx/common/vrc4173.c +++ b/arch/mips/vr41xx/common/vrc4173.c | |||
@@ -483,7 +483,7 @@ static inline int vrc4173_icu_init(int cascade_irq) | |||
483 | vr41xx_set_irq_level(GIU_IRQ_TO_PIN(cascade_irq), LEVEL_LOW); | 483 | vr41xx_set_irq_level(GIU_IRQ_TO_PIN(cascade_irq), LEVEL_LOW); |
484 | 484 | ||
485 | for (i = VRC4173_IRQ_BASE; i <= VRC4173_IRQ_LAST; i++) | 485 | for (i = VRC4173_IRQ_BASE; i <= VRC4173_IRQ_LAST; i++) |
486 | irq_desc[i].handler = &vrc4173_irq_type; | 486 | irq_desc[i].chip = &vrc4173_irq_type; |
487 | 487 | ||
488 | return 0; | 488 | return 0; |
489 | } | 489 | } |
diff --git a/arch/mips/vr41xx/nec-cmbvr4133/irq.c b/arch/mips/vr41xx/nec-cmbvr4133/irq.c index 31db6b61a39e..7b2511ca0a61 100644 --- a/arch/mips/vr41xx/nec-cmbvr4133/irq.c +++ b/arch/mips/vr41xx/nec-cmbvr4133/irq.c | |||
@@ -104,7 +104,7 @@ void __init rockhopper_init_irq(void) | |||
104 | } | 104 | } |
105 | 105 | ||
106 | for (i = I8259_IRQ_BASE; i <= I8259_IRQ_LAST; i++) | 106 | for (i = I8259_IRQ_BASE; i <= I8259_IRQ_LAST; i++) |
107 | irq_desc[i].handler = &i8259_irq_type; | 107 | irq_desc[i].chip = &i8259_irq_type; |
108 | 108 | ||
109 | setup_irq(I8259_SLAVE_IRQ, &i8259_slave_cascade); | 109 | setup_irq(I8259_SLAVE_IRQ, &i8259_slave_cascade); |
110 | 110 | ||
diff --git a/arch/parisc/kernel/irq.c b/arch/parisc/kernel/irq.c index 197936d9359a..26e69f73fdb0 100644 --- a/arch/parisc/kernel/irq.c +++ b/arch/parisc/kernel/irq.c | |||
@@ -158,7 +158,7 @@ int show_interrupts(struct seq_file *p, void *v) | |||
158 | seq_printf(p, "%10u ", kstat_irqs(i)); | 158 | seq_printf(p, "%10u ", kstat_irqs(i)); |
159 | #endif | 159 | #endif |
160 | 160 | ||
161 | seq_printf(p, " %14s", irq_desc[i].handler->typename); | 161 | seq_printf(p, " %14s", irq_desc[i].chip->typename); |
162 | #ifndef PARISC_IRQ_CR16_COUNTS | 162 | #ifndef PARISC_IRQ_CR16_COUNTS |
163 | seq_printf(p, " %s", action->name); | 163 | seq_printf(p, " %s", action->name); |
164 | 164 | ||
@@ -210,12 +210,12 @@ int cpu_claim_irq(unsigned int irq, struct hw_interrupt_type *type, void *data) | |||
210 | { | 210 | { |
211 | if (irq_desc[irq].action) | 211 | if (irq_desc[irq].action) |
212 | return -EBUSY; | 212 | return -EBUSY; |
213 | if (irq_desc[irq].handler != &cpu_interrupt_type) | 213 | if (irq_desc[irq].chip != &cpu_interrupt_type) |
214 | return -EBUSY; | 214 | return -EBUSY; |
215 | 215 | ||
216 | if (type) { | 216 | if (type) { |
217 | irq_desc[irq].handler = type; | 217 | irq_desc[irq].chip = type; |
218 | irq_desc[irq].handler_data = data; | 218 | irq_desc[irq].chip_data = data; |
219 | cpu_interrupt_type.enable(irq); | 219 | cpu_interrupt_type.enable(irq); |
220 | } | 220 | } |
221 | return 0; | 221 | return 0; |
@@ -378,7 +378,7 @@ static void claim_cpu_irqs(void) | |||
378 | { | 378 | { |
379 | int i; | 379 | int i; |
380 | for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) { | 380 | for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) { |
381 | irq_desc[i].handler = &cpu_interrupt_type; | 381 | irq_desc[i].chip = &cpu_interrupt_type; |
382 | } | 382 | } |
383 | 383 | ||
384 | irq_desc[TIMER_IRQ].action = &timer_action; | 384 | irq_desc[TIMER_IRQ].action = &timer_action; |
diff --git a/arch/powerpc/kernel/crash.c b/arch/powerpc/kernel/crash.c index e253a45dcf10..1bfad7c2f8c8 100644 --- a/arch/powerpc/kernel/crash.c +++ b/arch/powerpc/kernel/crash.c | |||
@@ -193,10 +193,10 @@ void default_machine_crash_shutdown(struct pt_regs *regs) | |||
193 | struct irq_desc *desc = irq_descp(irq); | 193 | struct irq_desc *desc = irq_descp(irq); |
194 | 194 | ||
195 | if (desc->status & IRQ_INPROGRESS) | 195 | if (desc->status & IRQ_INPROGRESS) |
196 | desc->handler->end(irq); | 196 | desc->chip->end(irq); |
197 | 197 | ||
198 | if (!(desc->status & IRQ_DISABLED)) | 198 | if (!(desc->status & IRQ_DISABLED)) |
199 | desc->handler->disable(irq); | 199 | desc->chip->disable(irq); |
200 | } | 200 | } |
201 | 201 | ||
202 | if (ppc_md.kexec_cpu_down) | 202 | if (ppc_md.kexec_cpu_down) |
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c index 40d4c14fde8f..8cfc779d882d 100644 --- a/arch/powerpc/kernel/irq.c +++ b/arch/powerpc/kernel/irq.c | |||
@@ -120,8 +120,8 @@ int show_interrupts(struct seq_file *p, void *v) | |||
120 | #else | 120 | #else |
121 | seq_printf(p, "%10u ", kstat_irqs(i)); | 121 | seq_printf(p, "%10u ", kstat_irqs(i)); |
122 | #endif /* CONFIG_SMP */ | 122 | #endif /* CONFIG_SMP */ |
123 | if (desc->handler) | 123 | if (desc->chip) |
124 | seq_printf(p, " %s ", desc->handler->typename); | 124 | seq_printf(p, " %s ", desc->chip->typename); |
125 | else | 125 | else |
126 | seq_puts(p, " None "); | 126 | seq_puts(p, " None "); |
127 | seq_printf(p, "%s", (desc->status & IRQ_LEVEL) ? "Level " : "Edge "); | 127 | seq_printf(p, "%s", (desc->status & IRQ_LEVEL) ? "Level " : "Edge "); |
@@ -169,8 +169,8 @@ void fixup_irqs(cpumask_t map) | |||
169 | printk("Breaking affinity for irq %i\n", irq); | 169 | printk("Breaking affinity for irq %i\n", irq); |
170 | mask = map; | 170 | mask = map; |
171 | } | 171 | } |
172 | if (irq_desc[irq].handler->set_affinity) | 172 | if (irq_desc[irq].chip->set_affinity) |
173 | irq_desc[irq].handler->set_affinity(irq, mask); | 173 | irq_desc[irq].chip->set_affinity(irq, mask); |
174 | else if (irq_desc[irq].action && !(warned++)) | 174 | else if (irq_desc[irq].action && !(warned++)) |
175 | printk("Cannot set affinity for irq %i\n", irq); | 175 | printk("Cannot set affinity for irq %i\n", irq); |
176 | } | 176 | } |
diff --git a/arch/powerpc/platforms/cell/interrupt.c b/arch/powerpc/platforms/cell/interrupt.c index 1bbf822b4efc..7bff3cbc5723 100644 --- a/arch/powerpc/platforms/cell/interrupt.c +++ b/arch/powerpc/platforms/cell/interrupt.c | |||
@@ -307,7 +307,7 @@ static void iic_request_ipi(int ipi, const char *name) | |||
307 | irq = iic_ipi_to_irq(ipi); | 307 | irq = iic_ipi_to_irq(ipi); |
308 | /* IPIs are marked SA_INTERRUPT as they must run with irqs | 308 | /* IPIs are marked SA_INTERRUPT as they must run with irqs |
309 | * disabled */ | 309 | * disabled */ |
310 | get_irq_desc(irq)->handler = &iic_pic; | 310 | get_irq_desc(irq)->chip = &iic_pic; |
311 | get_irq_desc(irq)->status |= IRQ_PER_CPU; | 311 | get_irq_desc(irq)->status |= IRQ_PER_CPU; |
312 | request_irq(irq, iic_ipi_action, SA_INTERRUPT, name, NULL); | 312 | request_irq(irq, iic_ipi_action, SA_INTERRUPT, name, NULL); |
313 | } | 313 | } |
@@ -330,7 +330,7 @@ static void iic_setup_spe_handlers(void) | |||
330 | for (be=0; be < num_present_cpus() / 2; be++) { | 330 | for (be=0; be < num_present_cpus() / 2; be++) { |
331 | for (isrc = 0; isrc < IIC_CLASS_STRIDE * 3; isrc++) { | 331 | for (isrc = 0; isrc < IIC_CLASS_STRIDE * 3; isrc++) { |
332 | int irq = IIC_NODE_STRIDE * be + IIC_SPE_OFFSET + isrc; | 332 | int irq = IIC_NODE_STRIDE * be + IIC_SPE_OFFSET + isrc; |
333 | get_irq_desc(irq)->handler = &iic_pic; | 333 | get_irq_desc(irq)->chip = &iic_pic; |
334 | } | 334 | } |
335 | } | 335 | } |
336 | } | 336 | } |
diff --git a/arch/powerpc/platforms/cell/spider-pic.c b/arch/powerpc/platforms/cell/spider-pic.c index 55cbdd77a62d..7c3a0b6d34fd 100644 --- a/arch/powerpc/platforms/cell/spider-pic.c +++ b/arch/powerpc/platforms/cell/spider-pic.c | |||
@@ -162,7 +162,7 @@ void spider_init_IRQ_hardcoded(void) | |||
162 | spider_pics[node] = ioremap(spiderpic, 0x800); | 162 | spider_pics[node] = ioremap(spiderpic, 0x800); |
163 | for (n = 0; n < IIC_NUM_EXT; n++) { | 163 | for (n = 0; n < IIC_NUM_EXT; n++) { |
164 | int irq = n + IIC_EXT_OFFSET + node * IIC_NODE_STRIDE; | 164 | int irq = n + IIC_EXT_OFFSET + node * IIC_NODE_STRIDE; |
165 | get_irq_desc(irq)->handler = &spider_pic; | 165 | get_irq_desc(irq)->chip = &spider_pic; |
166 | } | 166 | } |
167 | 167 | ||
168 | /* do not mask any interrupts because of level */ | 168 | /* do not mask any interrupts because of level */ |
@@ -217,7 +217,7 @@ void spider_init_IRQ(void) | |||
217 | 217 | ||
218 | for (n = 0; n < IIC_NUM_EXT; n++) { | 218 | for (n = 0; n < IIC_NUM_EXT; n++) { |
219 | int irq = n + IIC_EXT_OFFSET + node * IIC_NODE_STRIDE; | 219 | int irq = n + IIC_EXT_OFFSET + node * IIC_NODE_STRIDE; |
220 | get_irq_desc(irq)->handler = &spider_pic; | 220 | get_irq_desc(irq)->chip = &spider_pic; |
221 | } | 221 | } |
222 | 222 | ||
223 | /* do not mask any interrupts because of level */ | 223 | /* do not mask any interrupts because of level */ |
diff --git a/arch/powerpc/platforms/iseries/irq.c b/arch/powerpc/platforms/iseries/irq.c index 62bbbcf5ded3..33bb4aa0e1e8 100644 --- a/arch/powerpc/platforms/iseries/irq.c +++ b/arch/powerpc/platforms/iseries/irq.c | |||
@@ -242,9 +242,9 @@ void __init iSeries_activate_IRQs() | |||
242 | for_each_irq (irq) { | 242 | for_each_irq (irq) { |
243 | irq_desc_t *desc = get_irq_desc(irq); | 243 | irq_desc_t *desc = get_irq_desc(irq); |
244 | 244 | ||
245 | if (desc && desc->handler && desc->handler->startup) { | 245 | if (desc && desc->chip && desc->chip->startup) { |
246 | spin_lock_irqsave(&desc->lock, flags); | 246 | spin_lock_irqsave(&desc->lock, flags); |
247 | desc->handler->startup(irq); | 247 | desc->chip->startup(irq); |
248 | spin_unlock_irqrestore(&desc->lock, flags); | 248 | spin_unlock_irqrestore(&desc->lock, flags); |
249 | } | 249 | } |
250 | } | 250 | } |
@@ -324,7 +324,7 @@ int __init iSeries_allocate_IRQ(HvBusNumber bus, | |||
324 | + function; | 324 | + function; |
325 | virtirq = virt_irq_create_mapping(realirq); | 325 | virtirq = virt_irq_create_mapping(realirq); |
326 | 326 | ||
327 | irq_desc[virtirq].handler = &iSeries_IRQ_handler; | 327 | irq_desc[virtirq].chip = &iSeries_IRQ_handler; |
328 | return virtirq; | 328 | return virtirq; |
329 | } | 329 | } |
330 | 330 | ||
diff --git a/arch/powerpc/platforms/powermac/pic.c b/arch/powerpc/platforms/powermac/pic.c index 18bf3011d1e3..9f6189af6dd6 100644 --- a/arch/powerpc/platforms/powermac/pic.c +++ b/arch/powerpc/platforms/powermac/pic.c | |||
@@ -446,7 +446,7 @@ static void __init pmac_pic_probe_oldstyle(void) | |||
446 | 446 | ||
447 | /* Set the handler for the main PIC */ | 447 | /* Set the handler for the main PIC */ |
448 | for ( i = 0; i < max_real_irqs ; i++ ) | 448 | for ( i = 0; i < max_real_irqs ; i++ ) |
449 | irq_desc[i].handler = &pmac_pic; | 449 | irq_desc[i].chip = &pmac_pic; |
450 | 450 | ||
451 | /* Get addresses of first controller if we have a node for it */ | 451 | /* Get addresses of first controller if we have a node for it */ |
452 | BUG_ON(of_address_to_resource(master, 0, &r)); | 452 | BUG_ON(of_address_to_resource(master, 0, &r)); |
@@ -493,7 +493,7 @@ static void __init pmac_pic_probe_oldstyle(void) | |||
493 | /* Setup handlers for secondary controller and hook cascade irq*/ | 493 | /* Setup handlers for secondary controller and hook cascade irq*/ |
494 | if (slave) { | 494 | if (slave) { |
495 | for ( i = max_real_irqs ; i < max_irqs ; i++ ) | 495 | for ( i = max_real_irqs ; i < max_irqs ; i++ ) |
496 | irq_desc[i].handler = &gatwick_pic; | 496 | irq_desc[i].chip = &gatwick_pic; |
497 | setup_irq(irq_cascade, &gatwick_cascade_action); | 497 | setup_irq(irq_cascade, &gatwick_cascade_action); |
498 | } | 498 | } |
499 | printk(KERN_INFO "irq: System has %d possible interrupts\n", max_irqs); | 499 | printk(KERN_INFO "irq: System has %d possible interrupts\n", max_irqs); |
diff --git a/arch/powerpc/platforms/pseries/xics.c b/arch/powerpc/platforms/pseries/xics.c index b14f9b5c114e..bdc9e26a93cf 100644 --- a/arch/powerpc/platforms/pseries/xics.c +++ b/arch/powerpc/platforms/pseries/xics.c | |||
@@ -558,7 +558,7 @@ nextnode: | |||
558 | } | 558 | } |
559 | 559 | ||
560 | for (i = irq_offset_value(); i < NR_IRQS; ++i) | 560 | for (i = irq_offset_value(); i < NR_IRQS; ++i) |
561 | get_irq_desc(i)->handler = &xics_pic; | 561 | get_irq_desc(i)->chip = &xics_pic; |
562 | 562 | ||
563 | xics_setup_cpu(); | 563 | xics_setup_cpu(); |
564 | 564 | ||
@@ -701,9 +701,9 @@ void xics_migrate_irqs_away(void) | |||
701 | continue; | 701 | continue; |
702 | 702 | ||
703 | /* We only need to migrate enabled IRQS */ | 703 | /* We only need to migrate enabled IRQS */ |
704 | if (desc == NULL || desc->handler == NULL | 704 | if (desc == NULL || desc->chip == NULL |
705 | || desc->action == NULL | 705 | || desc->action == NULL |
706 | || desc->handler->set_affinity == NULL) | 706 | || desc->chip->set_affinity == NULL) |
707 | continue; | 707 | continue; |
708 | 708 | ||
709 | spin_lock_irqsave(&desc->lock, flags); | 709 | spin_lock_irqsave(&desc->lock, flags); |
@@ -728,7 +728,7 @@ void xics_migrate_irqs_away(void) | |||
728 | virq, cpu); | 728 | virq, cpu); |
729 | 729 | ||
730 | /* Reset affinity to all cpus */ | 730 | /* Reset affinity to all cpus */ |
731 | desc->handler->set_affinity(virq, CPU_MASK_ALL); | 731 | desc->chip->set_affinity(virq, CPU_MASK_ALL); |
732 | irq_affinity[virq] = CPU_MASK_ALL; | 732 | irq_affinity[virq] = CPU_MASK_ALL; |
733 | unlock: | 733 | unlock: |
734 | spin_unlock_irqrestore(&desc->lock, flags); | 734 | spin_unlock_irqrestore(&desc->lock, flags); |
diff --git a/arch/powerpc/sysdev/i8259.c b/arch/powerpc/sysdev/i8259.c index b7ac32fdd776..2bff30f6d635 100644 --- a/arch/powerpc/sysdev/i8259.c +++ b/arch/powerpc/sysdev/i8259.c | |||
@@ -208,7 +208,7 @@ void __init i8259_init(unsigned long intack_addr, int offset) | |||
208 | spin_unlock_irqrestore(&i8259_lock, flags); | 208 | spin_unlock_irqrestore(&i8259_lock, flags); |
209 | 209 | ||
210 | for (i = 0; i < NUM_ISA_INTERRUPTS; ++i) | 210 | for (i = 0; i < NUM_ISA_INTERRUPTS; ++i) |
211 | irq_desc[offset + i].handler = &i8259_pic; | 211 | irq_desc[offset + i].chip = &i8259_pic; |
212 | 212 | ||
213 | /* reserve our resources */ | 213 | /* reserve our resources */ |
214 | setup_irq(offset + 2, &i8259_irqaction); | 214 | setup_irq(offset + 2, &i8259_irqaction); |
diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c index 8f01e0f1d847..46801f5ec03f 100644 --- a/arch/powerpc/sysdev/ipic.c +++ b/arch/powerpc/sysdev/ipic.c | |||
@@ -472,7 +472,7 @@ void __init ipic_init(phys_addr_t phys_addr, | |||
472 | ipic_write(primary_ipic->regs, IPIC_SEMSR, temp); | 472 | ipic_write(primary_ipic->regs, IPIC_SEMSR, temp); |
473 | 473 | ||
474 | for (i = 0 ; i < NR_IPIC_INTS ; i++) { | 474 | for (i = 0 ; i < NR_IPIC_INTS ; i++) { |
475 | irq_desc[i+irq_offset].handler = &ipic; | 475 | irq_desc[i+irq_offset].chip = &ipic; |
476 | irq_desc[i+irq_offset].status = IRQ_LEVEL; | 476 | irq_desc[i+irq_offset].status = IRQ_LEVEL; |
477 | } | 477 | } |
478 | 478 | ||
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c index bffe50d02c99..f4613ee6b7a2 100644 --- a/arch/powerpc/sysdev/mpic.c +++ b/arch/powerpc/sysdev/mpic.c | |||
@@ -379,14 +379,14 @@ static inline u32 mpic_physmask(u32 cpumask) | |||
379 | /* Get the mpic structure from the IPI number */ | 379 | /* Get the mpic structure from the IPI number */ |
380 | static inline struct mpic * mpic_from_ipi(unsigned int ipi) | 380 | static inline struct mpic * mpic_from_ipi(unsigned int ipi) |
381 | { | 381 | { |
382 | return container_of(irq_desc[ipi].handler, struct mpic, hc_ipi); | 382 | return container_of(irq_desc[ipi].chip, struct mpic, hc_ipi); |
383 | } | 383 | } |
384 | #endif | 384 | #endif |
385 | 385 | ||
386 | /* Get the mpic structure from the irq number */ | 386 | /* Get the mpic structure from the irq number */ |
387 | static inline struct mpic * mpic_from_irq(unsigned int irq) | 387 | static inline struct mpic * mpic_from_irq(unsigned int irq) |
388 | { | 388 | { |
389 | return container_of(irq_desc[irq].handler, struct mpic, hc_irq); | 389 | return container_of(irq_desc[irq].chip, struct mpic, hc_irq); |
390 | } | 390 | } |
391 | 391 | ||
392 | /* Send an EOI */ | 392 | /* Send an EOI */ |
@@ -752,7 +752,7 @@ void __init mpic_init(struct mpic *mpic) | |||
752 | if (!(mpic->flags & MPIC_PRIMARY)) | 752 | if (!(mpic->flags & MPIC_PRIMARY)) |
753 | continue; | 753 | continue; |
754 | irq_desc[mpic->ipi_offset+i].status |= IRQ_PER_CPU; | 754 | irq_desc[mpic->ipi_offset+i].status |= IRQ_PER_CPU; |
755 | irq_desc[mpic->ipi_offset+i].handler = &mpic->hc_ipi; | 755 | irq_desc[mpic->ipi_offset+i].chip = &mpic->hc_ipi; |
756 | #endif /* CONFIG_SMP */ | 756 | #endif /* CONFIG_SMP */ |
757 | } | 757 | } |
758 | 758 | ||
@@ -813,7 +813,7 @@ void __init mpic_init(struct mpic *mpic) | |||
813 | /* init linux descriptors */ | 813 | /* init linux descriptors */ |
814 | if (i < mpic->irq_count) { | 814 | if (i < mpic->irq_count) { |
815 | irq_desc[mpic->irq_offset+i].status = level ? IRQ_LEVEL : 0; | 815 | irq_desc[mpic->irq_offset+i].status = level ? IRQ_LEVEL : 0; |
816 | irq_desc[mpic->irq_offset+i].handler = &mpic->hc_irq; | 816 | irq_desc[mpic->irq_offset+i].chip = &mpic->hc_irq; |
817 | } | 817 | } |
818 | } | 818 | } |
819 | 819 | ||
diff --git a/arch/ppc/8xx_io/commproc.c b/arch/ppc/8xx_io/commproc.c index 12b84ca51327..9b3ace26280c 100644 --- a/arch/ppc/8xx_io/commproc.c +++ b/arch/ppc/8xx_io/commproc.c | |||
@@ -187,7 +187,7 @@ cpm_interrupt_init(void) | |||
187 | * interrupt vectors | 187 | * interrupt vectors |
188 | */ | 188 | */ |
189 | for ( i = CPM_IRQ_OFFSET ; i < CPM_IRQ_OFFSET + NR_CPM_INTS ; i++ ) | 189 | for ( i = CPM_IRQ_OFFSET ; i < CPM_IRQ_OFFSET + NR_CPM_INTS ; i++ ) |
190 | irq_desc[i].handler = &cpm_pic; | 190 | irq_desc[i].chip = &cpm_pic; |
191 | 191 | ||
192 | /* Set our interrupt handler with the core CPU. */ | 192 | /* Set our interrupt handler with the core CPU. */ |
193 | if (setup_irq(CPM_INTERRUPT, &cpm_interrupt_irqaction)) | 193 | if (setup_irq(CPM_INTERRUPT, &cpm_interrupt_irqaction)) |
diff --git a/arch/ppc/platforms/apus_setup.c b/arch/ppc/platforms/apus_setup.c index fe0cdc04d436..5c4118a459f3 100644 --- a/arch/ppc/platforms/apus_setup.c +++ b/arch/ppc/platforms/apus_setup.c | |||
@@ -734,9 +734,9 @@ void apus_init_IRQ(void) | |||
734 | for ( i = 0 ; i < AMI_IRQS; i++ ) { | 734 | for ( i = 0 ; i < AMI_IRQS; i++ ) { |
735 | irq_desc[i].status = IRQ_LEVEL; | 735 | irq_desc[i].status = IRQ_LEVEL; |
736 | if (i < IRQ_AMIGA_AUTO) { | 736 | if (i < IRQ_AMIGA_AUTO) { |
737 | irq_desc[i].handler = &amiga_irqctrl; | 737 | irq_desc[i].chip = &amiga_irqctrl; |
738 | } else { | 738 | } else { |
739 | irq_desc[i].handler = &amiga_sys_irqctrl; | 739 | irq_desc[i].chip = &amiga_sys_irqctrl; |
740 | action = &amiga_sys_irqaction[i-IRQ_AMIGA_AUTO]; | 740 | action = &amiga_sys_irqaction[i-IRQ_AMIGA_AUTO]; |
741 | if (action->name) | 741 | if (action->name) |
742 | setup_irq(i, action); | 742 | setup_irq(i, action); |
diff --git a/arch/ppc/platforms/sbc82xx.c b/arch/ppc/platforms/sbc82xx.c index 866807b4ad0b..41006d2b4b38 100644 --- a/arch/ppc/platforms/sbc82xx.c +++ b/arch/ppc/platforms/sbc82xx.c | |||
@@ -172,7 +172,7 @@ void __init sbc82xx_init_IRQ(void) | |||
172 | 172 | ||
173 | /* Set up the interrupt handlers for the i8259 IRQs */ | 173 | /* Set up the interrupt handlers for the i8259 IRQs */ |
174 | for (i = NR_SIU_INTS; i < NR_SIU_INTS + 8; i++) { | 174 | for (i = NR_SIU_INTS; i < NR_SIU_INTS + 8; i++) { |
175 | irq_desc[i].handler = &sbc82xx_i8259_ic; | 175 | irq_desc[i].chip = &sbc82xx_i8259_ic; |
176 | irq_desc[i].status |= IRQ_LEVEL; | 176 | irq_desc[i].status |= IRQ_LEVEL; |
177 | } | 177 | } |
178 | 178 | ||
diff --git a/arch/ppc/syslib/cpc700_pic.c b/arch/ppc/syslib/cpc700_pic.c index 5add0a919ef6..172aa215fdb0 100644 --- a/arch/ppc/syslib/cpc700_pic.c +++ b/arch/ppc/syslib/cpc700_pic.c | |||
@@ -140,12 +140,12 @@ cpc700_init_IRQ(void) | |||
140 | /* IRQ 0 is highest */ | 140 | /* IRQ 0 is highest */ |
141 | 141 | ||
142 | for (i = 0; i < 17; i++) { | 142 | for (i = 0; i < 17; i++) { |
143 | irq_desc[i].handler = &cpc700_pic; | 143 | irq_desc[i].chip = &cpc700_pic; |
144 | cpc700_pic_init_irq(i); | 144 | cpc700_pic_init_irq(i); |
145 | } | 145 | } |
146 | 146 | ||
147 | for (i = 20; i < 32; i++) { | 147 | for (i = 20; i < 32; i++) { |
148 | irq_desc[i].handler = &cpc700_pic; | 148 | irq_desc[i].chip = &cpc700_pic; |
149 | cpc700_pic_init_irq(i); | 149 | cpc700_pic_init_irq(i); |
150 | } | 150 | } |
151 | 151 | ||
diff --git a/arch/ppc/syslib/cpm2_pic.c b/arch/ppc/syslib/cpm2_pic.c index 29d95d415ceb..c0fee0beb815 100644 --- a/arch/ppc/syslib/cpm2_pic.c +++ b/arch/ppc/syslib/cpm2_pic.c | |||
@@ -171,7 +171,7 @@ void cpm2_init_IRQ(void) | |||
171 | /* Enable chaining to OpenPIC, and make everything level | 171 | /* Enable chaining to OpenPIC, and make everything level |
172 | */ | 172 | */ |
173 | for (i = 0; i < NR_CPM_INTS; i++) { | 173 | for (i = 0; i < NR_CPM_INTS; i++) { |
174 | irq_desc[i+CPM_IRQ_OFFSET].handler = &cpm2_pic; | 174 | irq_desc[i+CPM_IRQ_OFFSET].chip = &cpm2_pic; |
175 | irq_desc[i+CPM_IRQ_OFFSET].status |= IRQ_LEVEL; | 175 | irq_desc[i+CPM_IRQ_OFFSET].status |= IRQ_LEVEL; |
176 | } | 176 | } |
177 | } | 177 | } |
diff --git a/arch/ppc/syslib/gt64260_pic.c b/arch/ppc/syslib/gt64260_pic.c index dc3bd9ecbbf6..91096b38ae70 100644 --- a/arch/ppc/syslib/gt64260_pic.c +++ b/arch/ppc/syslib/gt64260_pic.c | |||
@@ -98,7 +98,7 @@ gt64260_init_irq(void) | |||
98 | 98 | ||
99 | /* use the gt64260 for all (possible) interrupt sources */ | 99 | /* use the gt64260 for all (possible) interrupt sources */ |
100 | for (i = gt64260_irq_base; i < (gt64260_irq_base + 96); i++) | 100 | for (i = gt64260_irq_base; i < (gt64260_irq_base + 96); i++) |
101 | irq_desc[i].handler = >64260_pic; | 101 | irq_desc[i].chip = >64260_pic; |
102 | 102 | ||
103 | if (ppc_md.progress) | 103 | if (ppc_md.progress) |
104 | ppc_md.progress("gt64260_init_irq: exit", 0x0); | 104 | ppc_md.progress("gt64260_init_irq: exit", 0x0); |
diff --git a/arch/ppc/syslib/m82xx_pci.c b/arch/ppc/syslib/m82xx_pci.c index 1941a8c7ca9a..63fa5b313396 100644 --- a/arch/ppc/syslib/m82xx_pci.c +++ b/arch/ppc/syslib/m82xx_pci.c | |||
@@ -159,7 +159,7 @@ pq2pci_init_irq(void) | |||
159 | immap->im_memctl.memc_or8 = 0xffff8010; | 159 | immap->im_memctl.memc_or8 = 0xffff8010; |
160 | #endif | 160 | #endif |
161 | for (irq = NR_CPM_INTS; irq < NR_CPM_INTS + 4; irq++) | 161 | for (irq = NR_CPM_INTS; irq < NR_CPM_INTS + 4; irq++) |
162 | irq_desc[irq].handler = &pq2pci_ic; | 162 | irq_desc[irq].chip = &pq2pci_ic; |
163 | 163 | ||
164 | /* make PCI IRQ level sensitive */ | 164 | /* make PCI IRQ level sensitive */ |
165 | immap->im_intctl.ic_siexr &= | 165 | immap->im_intctl.ic_siexr &= |
diff --git a/arch/ppc/syslib/m8xx_setup.c b/arch/ppc/syslib/m8xx_setup.c index dae9af78bde1..0c4c0de7c59f 100644 --- a/arch/ppc/syslib/m8xx_setup.c +++ b/arch/ppc/syslib/m8xx_setup.c | |||
@@ -347,13 +347,13 @@ m8xx_init_IRQ(void) | |||
347 | int i; | 347 | int i; |
348 | 348 | ||
349 | for (i = SIU_IRQ_OFFSET ; i < SIU_IRQ_OFFSET + NR_SIU_INTS ; i++) | 349 | for (i = SIU_IRQ_OFFSET ; i < SIU_IRQ_OFFSET + NR_SIU_INTS ; i++) |
350 | irq_desc[i].handler = &ppc8xx_pic; | 350 | irq_desc[i].chip = &ppc8xx_pic; |
351 | 351 | ||
352 | cpm_interrupt_init(); | 352 | cpm_interrupt_init(); |
353 | 353 | ||
354 | #if defined(CONFIG_PCI) | 354 | #if defined(CONFIG_PCI) |
355 | for (i = I8259_IRQ_OFFSET ; i < I8259_IRQ_OFFSET + NR_8259_INTS ; i++) | 355 | for (i = I8259_IRQ_OFFSET ; i < I8259_IRQ_OFFSET + NR_8259_INTS ; i++) |
356 | irq_desc[i].handler = &i8259_pic; | 356 | irq_desc[i].chip = &i8259_pic; |
357 | 357 | ||
358 | i8259_pic_irq_offset = I8259_IRQ_OFFSET; | 358 | i8259_pic_irq_offset = I8259_IRQ_OFFSET; |
359 | i8259_init(0); | 359 | i8259_init(0); |
diff --git a/arch/ppc/syslib/mpc52xx_pic.c b/arch/ppc/syslib/mpc52xx_pic.c index c4406f9dc6a3..6425b5cee7db 100644 --- a/arch/ppc/syslib/mpc52xx_pic.c +++ b/arch/ppc/syslib/mpc52xx_pic.c | |||
@@ -204,9 +204,9 @@ mpc52xx_init_irq(void) | |||
204 | out_be32(&intr->main_pri1, 0); | 204 | out_be32(&intr->main_pri1, 0); |
205 | out_be32(&intr->main_pri2, 0); | 205 | out_be32(&intr->main_pri2, 0); |
206 | 206 | ||
207 | /* Initialize irq_desc[i].handler's with mpc52xx_ic. */ | 207 | /* Initialize irq_desc[i].chip's with mpc52xx_ic. */ |
208 | for (i = 0; i < NR_IRQS; i++) { | 208 | for (i = 0; i < NR_IRQS; i++) { |
209 | irq_desc[i].handler = &mpc52xx_ic; | 209 | irq_desc[i].chip = &mpc52xx_ic; |
210 | irq_desc[i].status = IRQ_LEVEL; | 210 | irq_desc[i].status = IRQ_LEVEL; |
211 | } | 211 | } |
212 | 212 | ||
diff --git a/arch/ppc/syslib/mv64360_pic.c b/arch/ppc/syslib/mv64360_pic.c index 5a19697060f0..a4244d468381 100644 --- a/arch/ppc/syslib/mv64360_pic.c +++ b/arch/ppc/syslib/mv64360_pic.c | |||
@@ -119,7 +119,7 @@ mv64360_init_irq(void) | |||
119 | /* All interrupts are level interrupts */ | 119 | /* All interrupts are level interrupts */ |
120 | for (i = mv64360_irq_base; i < (mv64360_irq_base + 96); i++) { | 120 | for (i = mv64360_irq_base; i < (mv64360_irq_base + 96); i++) { |
121 | irq_desc[i].status |= IRQ_LEVEL; | 121 | irq_desc[i].status |= IRQ_LEVEL; |
122 | irq_desc[i].handler = &mv64360_pic; | 122 | irq_desc[i].chip = &mv64360_pic; |
123 | } | 123 | } |
124 | 124 | ||
125 | if (ppc_md.progress) | 125 | if (ppc_md.progress) |
diff --git a/arch/ppc/syslib/open_pic.c b/arch/ppc/syslib/open_pic.c index 70456c8f998c..822058c2983e 100644 --- a/arch/ppc/syslib/open_pic.c +++ b/arch/ppc/syslib/open_pic.c | |||
@@ -373,7 +373,7 @@ void __init openpic_init(int offset) | |||
373 | OPENPIC_VEC_IPI+i+offset); | 373 | OPENPIC_VEC_IPI+i+offset); |
374 | /* IPIs are per-CPU */ | 374 | /* IPIs are per-CPU */ |
375 | irq_desc[OPENPIC_VEC_IPI+i+offset].status |= IRQ_PER_CPU; | 375 | irq_desc[OPENPIC_VEC_IPI+i+offset].status |= IRQ_PER_CPU; |
376 | irq_desc[OPENPIC_VEC_IPI+i+offset].handler = &open_pic_ipi; | 376 | irq_desc[OPENPIC_VEC_IPI+i+offset].chip = &open_pic_ipi; |
377 | } | 377 | } |
378 | #endif | 378 | #endif |
379 | 379 | ||
@@ -408,7 +408,7 @@ void __init openpic_init(int offset) | |||
408 | 408 | ||
409 | /* Init descriptors */ | 409 | /* Init descriptors */ |
410 | for (i = offset; i < NumSources + offset; i++) | 410 | for (i = offset; i < NumSources + offset; i++) |
411 | irq_desc[i].handler = &open_pic; | 411 | irq_desc[i].chip = &open_pic; |
412 | 412 | ||
413 | /* Initialize the spurious interrupt */ | 413 | /* Initialize the spurious interrupt */ |
414 | if (ppc_md.progress) ppc_md.progress("openpic: spurious",0x3bd); | 414 | if (ppc_md.progress) ppc_md.progress("openpic: spurious",0x3bd); |
diff --git a/arch/ppc/syslib/open_pic2.c b/arch/ppc/syslib/open_pic2.c index bcbe40de26fe..b8154efff6ed 100644 --- a/arch/ppc/syslib/open_pic2.c +++ b/arch/ppc/syslib/open_pic2.c | |||
@@ -290,7 +290,7 @@ void __init openpic2_init(int offset) | |||
290 | 290 | ||
291 | /* Init descriptors */ | 291 | /* Init descriptors */ |
292 | for (i = offset; i < NumSources + offset; i++) | 292 | for (i = offset; i < NumSources + offset; i++) |
293 | irq_desc[i].handler = &open_pic2; | 293 | irq_desc[i].chip = &open_pic2; |
294 | 294 | ||
295 | /* Initialize the spurious interrupt */ | 295 | /* Initialize the spurious interrupt */ |
296 | if (ppc_md.progress) ppc_md.progress("openpic2: spurious",0x3bd); | 296 | if (ppc_md.progress) ppc_md.progress("openpic2: spurious",0x3bd); |
diff --git a/arch/ppc/syslib/ppc403_pic.c b/arch/ppc/syslib/ppc403_pic.c index c46043c47225..1584c8b1229f 100644 --- a/arch/ppc/syslib/ppc403_pic.c +++ b/arch/ppc/syslib/ppc403_pic.c | |||
@@ -121,5 +121,5 @@ ppc4xx_pic_init(void) | |||
121 | ppc_md.get_irq = ppc403_pic_get_irq; | 121 | ppc_md.get_irq = ppc403_pic_get_irq; |
122 | 122 | ||
123 | for (i = 0; i < NR_IRQS; i++) | 123 | for (i = 0; i < NR_IRQS; i++) |
124 | irq_desc[i].handler = &ppc403_aic; | 124 | irq_desc[i].chip = &ppc403_aic; |
125 | } | 125 | } |
diff --git a/arch/ppc/syslib/ppc4xx_pic.c b/arch/ppc/syslib/ppc4xx_pic.c index fd9af0fc0e9f..e669c1335d47 100644 --- a/arch/ppc/syslib/ppc4xx_pic.c +++ b/arch/ppc/syslib/ppc4xx_pic.c | |||
@@ -276,7 +276,7 @@ void __init ppc4xx_pic_init(void) | |||
276 | 276 | ||
277 | /* Attach low-level handlers */ | 277 | /* Attach low-level handlers */ |
278 | for (i = 0; i < (NR_UICS << 5); ++i) { | 278 | for (i = 0; i < (NR_UICS << 5); ++i) { |
279 | irq_desc[i].handler = &__uic[i >> 5].decl; | 279 | irq_desc[i].chip = &__uic[i >> 5].decl; |
280 | if (is_level_sensitive(i)) | 280 | if (is_level_sensitive(i)) |
281 | irq_desc[i].status |= IRQ_LEVEL; | 281 | irq_desc[i].status |= IRQ_LEVEL; |
282 | } | 282 | } |
diff --git a/arch/ppc/syslib/xilinx_pic.c b/arch/ppc/syslib/xilinx_pic.c index e672b600f315..39a93dc6375b 100644 --- a/arch/ppc/syslib/xilinx_pic.c +++ b/arch/ppc/syslib/xilinx_pic.c | |||
@@ -143,7 +143,7 @@ ppc4xx_pic_init(void) | |||
143 | ppc_md.get_irq = xilinx_pic_get_irq; | 143 | ppc_md.get_irq = xilinx_pic_get_irq; |
144 | 144 | ||
145 | for (i = 0; i < NR_IRQS; ++i) { | 145 | for (i = 0; i < NR_IRQS; ++i) { |
146 | irq_desc[i].handler = &xilinx_intc; | 146 | irq_desc[i].chip = &xilinx_intc; |
147 | 147 | ||
148 | if (XPAR_INTC_0_KIND_OF_INTR & (0x00000001 << i)) | 148 | if (XPAR_INTC_0_KIND_OF_INTR & (0x00000001 << i)) |
149 | irq_desc[i].status &= ~IRQ_LEVEL; | 149 | irq_desc[i].status &= ~IRQ_LEVEL; |
diff --git a/arch/sh/boards/adx/irq_maskreg.c b/arch/sh/boards/adx/irq_maskreg.c index c0973f8d57ba..357fab1bac2b 100644 --- a/arch/sh/boards/adx/irq_maskreg.c +++ b/arch/sh/boards/adx/irq_maskreg.c | |||
@@ -102,6 +102,6 @@ static void end_maskreg_irq(unsigned int irq) | |||
102 | void make_maskreg_irq(unsigned int irq) | 102 | void make_maskreg_irq(unsigned int irq) |
103 | { | 103 | { |
104 | disable_irq_nosync(irq); | 104 | disable_irq_nosync(irq); |
105 | irq_desc[irq].handler = &maskreg_irq_type; | 105 | irq_desc[irq].chip = &maskreg_irq_type; |
106 | disable_maskreg_irq(irq); | 106 | disable_maskreg_irq(irq); |
107 | } | 107 | } |
diff --git a/arch/sh/boards/bigsur/irq.c b/arch/sh/boards/bigsur/irq.c index 6ddbcc77244d..1d32425782c0 100644 --- a/arch/sh/boards/bigsur/irq.c +++ b/arch/sh/boards/bigsur/irq.c | |||
@@ -253,7 +253,7 @@ static void make_bigsur_l1isr(unsigned int irq) { | |||
253 | /* sanity check first */ | 253 | /* sanity check first */ |
254 | if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH) { | 254 | if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH) { |
255 | /* save the handler in the main description table */ | 255 | /* save the handler in the main description table */ |
256 | irq_desc[irq].handler = &bigsur_l1irq_type; | 256 | irq_desc[irq].chip = &bigsur_l1irq_type; |
257 | irq_desc[irq].status = IRQ_DISABLED; | 257 | irq_desc[irq].status = IRQ_DISABLED; |
258 | irq_desc[irq].action = 0; | 258 | irq_desc[irq].action = 0; |
259 | irq_desc[irq].depth = 1; | 259 | irq_desc[irq].depth = 1; |
@@ -270,7 +270,7 @@ static void make_bigsur_l2isr(unsigned int irq) { | |||
270 | /* sanity check first */ | 270 | /* sanity check first */ |
271 | if(irq >= BIGSUR_2NDLVL_IRQ_LOW && irq < BIGSUR_2NDLVL_IRQ_HIGH) { | 271 | if(irq >= BIGSUR_2NDLVL_IRQ_LOW && irq < BIGSUR_2NDLVL_IRQ_HIGH) { |
272 | /* save the handler in the main description table */ | 272 | /* save the handler in the main description table */ |
273 | irq_desc[irq].handler = &bigsur_l2irq_type; | 273 | irq_desc[irq].chip = &bigsur_l2irq_type; |
274 | irq_desc[irq].status = IRQ_DISABLED; | 274 | irq_desc[irq].status = IRQ_DISABLED; |
275 | irq_desc[irq].action = 0; | 275 | irq_desc[irq].action = 0; |
276 | irq_desc[irq].depth = 1; | 276 | irq_desc[irq].depth = 1; |
diff --git a/arch/sh/boards/cqreek/irq.c b/arch/sh/boards/cqreek/irq.c index d1da0d844567..2955adc52310 100644 --- a/arch/sh/boards/cqreek/irq.c +++ b/arch/sh/boards/cqreek/irq.c | |||
@@ -103,7 +103,7 @@ void __init init_cqreek_IRQ(void) | |||
103 | cqreek_irq_data[14].stat_port = BRIDGE_IDE_INTR_STAT; | 103 | cqreek_irq_data[14].stat_port = BRIDGE_IDE_INTR_STAT; |
104 | cqreek_irq_data[14].bit = 1; | 104 | cqreek_irq_data[14].bit = 1; |
105 | 105 | ||
106 | irq_desc[14].handler = &cqreek_irq_type; | 106 | irq_desc[14].chip = &cqreek_irq_type; |
107 | irq_desc[14].status = IRQ_DISABLED; | 107 | irq_desc[14].status = IRQ_DISABLED; |
108 | irq_desc[14].action = 0; | 108 | irq_desc[14].action = 0; |
109 | irq_desc[14].depth = 1; | 109 | irq_desc[14].depth = 1; |
@@ -117,7 +117,7 @@ void __init init_cqreek_IRQ(void) | |||
117 | cqreek_irq_data[10].bit = (1 << 10); | 117 | cqreek_irq_data[10].bit = (1 << 10); |
118 | 118 | ||
119 | /* XXX: Err... we may need demultiplexer for ISA irq... */ | 119 | /* XXX: Err... we may need demultiplexer for ISA irq... */ |
120 | irq_desc[10].handler = &cqreek_irq_type; | 120 | irq_desc[10].chip = &cqreek_irq_type; |
121 | irq_desc[10].status = IRQ_DISABLED; | 121 | irq_desc[10].status = IRQ_DISABLED; |
122 | irq_desc[10].action = 0; | 122 | irq_desc[10].action = 0; |
123 | irq_desc[10].depth = 1; | 123 | irq_desc[10].depth = 1; |
diff --git a/arch/sh/boards/dreamcast/setup.c b/arch/sh/boards/dreamcast/setup.c index 55dece35cde5..0027b80a2343 100644 --- a/arch/sh/boards/dreamcast/setup.c +++ b/arch/sh/boards/dreamcast/setup.c | |||
@@ -70,7 +70,7 @@ int __init platform_setup(void) | |||
70 | 70 | ||
71 | /* Assign all virtual IRQs to the System ASIC int. handler */ | 71 | /* Assign all virtual IRQs to the System ASIC int. handler */ |
72 | for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++) | 72 | for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++) |
73 | irq_desc[i].handler = &systemasic_int; | 73 | irq_desc[i].chip = &systemasic_int; |
74 | 74 | ||
75 | board_time_init = aica_time_init; | 75 | board_time_init = aica_time_init; |
76 | 76 | ||
diff --git a/arch/sh/boards/ec3104/setup.c b/arch/sh/boards/ec3104/setup.c index 5130ba2b6ff1..4b3ef16a0e96 100644 --- a/arch/sh/boards/ec3104/setup.c +++ b/arch/sh/boards/ec3104/setup.c | |||
@@ -63,7 +63,7 @@ int __init platform_setup(void) | |||
63 | str[i] = ctrl_readb(EC3104_BASE + i); | 63 | str[i] = ctrl_readb(EC3104_BASE + i); |
64 | 64 | ||
65 | for (i = EC3104_IRQBASE; i < EC3104_IRQBASE + 32; i++) | 65 | for (i = EC3104_IRQBASE; i < EC3104_IRQBASE + 32; i++) |
66 | irq_desc[i].handler = &ec3104_int; | 66 | irq_desc[i].chip = &ec3104_int; |
67 | 67 | ||
68 | printk("initializing EC3104 \"%.8s\" at %08x, IRQ %d, IRQ base %d\n", | 68 | printk("initializing EC3104 \"%.8s\" at %08x, IRQ %d, IRQ base %d\n", |
69 | str, EC3104_BASE, EC3104_IRQ, EC3104_IRQBASE); | 69 | str, EC3104_BASE, EC3104_IRQ, EC3104_IRQBASE); |
diff --git a/arch/sh/boards/harp/irq.c b/arch/sh/boards/harp/irq.c index 52d0ba39031b..701fa55d5297 100644 --- a/arch/sh/boards/harp/irq.c +++ b/arch/sh/boards/harp/irq.c | |||
@@ -114,7 +114,7 @@ static void enable_harp_irq(unsigned int irq) | |||
114 | static void __init make_harp_irq(unsigned int irq) | 114 | static void __init make_harp_irq(unsigned int irq) |
115 | { | 115 | { |
116 | disable_irq_nosync(irq); | 116 | disable_irq_nosync(irq); |
117 | irq_desc[irq].handler = &harp_irq_type; | 117 | irq_desc[irq].chip = &harp_irq_type; |
118 | disable_harp_irq(irq); | 118 | disable_harp_irq(irq); |
119 | } | 119 | } |
120 | 120 | ||
diff --git a/arch/sh/boards/mpc1211/setup.c b/arch/sh/boards/mpc1211/setup.c index 2bb581b91683..b72f009c52c2 100644 --- a/arch/sh/boards/mpc1211/setup.c +++ b/arch/sh/boards/mpc1211/setup.c | |||
@@ -194,7 +194,7 @@ static struct hw_interrupt_type mpc1211_irq_type = { | |||
194 | 194 | ||
195 | static void make_mpc1211_irq(unsigned int irq) | 195 | static void make_mpc1211_irq(unsigned int irq) |
196 | { | 196 | { |
197 | irq_desc[irq].handler = &mpc1211_irq_type; | 197 | irq_desc[irq].chip = &mpc1211_irq_type; |
198 | irq_desc[irq].status = IRQ_DISABLED; | 198 | irq_desc[irq].status = IRQ_DISABLED; |
199 | irq_desc[irq].action = 0; | 199 | irq_desc[irq].action = 0; |
200 | irq_desc[irq].depth = 1; | 200 | irq_desc[irq].depth = 1; |
diff --git a/arch/sh/boards/overdrive/irq.c b/arch/sh/boards/overdrive/irq.c index 715e8feb3a68..2c13a7de6b22 100644 --- a/arch/sh/boards/overdrive/irq.c +++ b/arch/sh/boards/overdrive/irq.c | |||
@@ -150,7 +150,7 @@ static void enable_od_irq(unsigned int irq) | |||
150 | static void __init make_od_irq(unsigned int irq) | 150 | static void __init make_od_irq(unsigned int irq) |
151 | { | 151 | { |
152 | disable_irq_nosync(irq); | 152 | disable_irq_nosync(irq); |
153 | irq_desc[irq].handler = &od_irq_type; | 153 | irq_desc[irq].chip = &od_irq_type; |
154 | disable_od_irq(irq); | 154 | disable_od_irq(irq); |
155 | } | 155 | } |
156 | 156 | ||
diff --git a/arch/sh/boards/renesas/hs7751rvoip/irq.c b/arch/sh/boards/renesas/hs7751rvoip/irq.c index ed4c5b50ea45..52a98b524e1f 100644 --- a/arch/sh/boards/renesas/hs7751rvoip/irq.c +++ b/arch/sh/boards/renesas/hs7751rvoip/irq.c | |||
@@ -86,7 +86,7 @@ static struct hw_interrupt_type hs7751rvoip_irq_type = { | |||
86 | static void make_hs7751rvoip_irq(unsigned int irq) | 86 | static void make_hs7751rvoip_irq(unsigned int irq) |
87 | { | 87 | { |
88 | disable_irq_nosync(irq); | 88 | disable_irq_nosync(irq); |
89 | irq_desc[irq].handler = &hs7751rvoip_irq_type; | 89 | irq_desc[irq].chip = &hs7751rvoip_irq_type; |
90 | disable_hs7751rvoip_irq(irq); | 90 | disable_hs7751rvoip_irq(irq); |
91 | } | 91 | } |
92 | 92 | ||
diff --git a/arch/sh/boards/renesas/rts7751r2d/irq.c b/arch/sh/boards/renesas/rts7751r2d/irq.c index d36c9374aed1..e16915d9cda4 100644 --- a/arch/sh/boards/renesas/rts7751r2d/irq.c +++ b/arch/sh/boards/renesas/rts7751r2d/irq.c | |||
@@ -100,7 +100,7 @@ static struct hw_interrupt_type rts7751r2d_irq_type = { | |||
100 | static void make_rts7751r2d_irq(unsigned int irq) | 100 | static void make_rts7751r2d_irq(unsigned int irq) |
101 | { | 101 | { |
102 | disable_irq_nosync(irq); | 102 | disable_irq_nosync(irq); |
103 | irq_desc[irq].handler = &rts7751r2d_irq_type; | 103 | irq_desc[irq].chip = &rts7751r2d_irq_type; |
104 | disable_rts7751r2d_irq(irq); | 104 | disable_rts7751r2d_irq(irq); |
105 | } | 105 | } |
106 | 106 | ||
diff --git a/arch/sh/boards/renesas/systemh/irq.c b/arch/sh/boards/renesas/systemh/irq.c index 7a2eb10edb56..845979181059 100644 --- a/arch/sh/boards/renesas/systemh/irq.c +++ b/arch/sh/boards/renesas/systemh/irq.c | |||
@@ -105,7 +105,7 @@ static void end_systemh_irq(unsigned int irq) | |||
105 | void make_systemh_irq(unsigned int irq) | 105 | void make_systemh_irq(unsigned int irq) |
106 | { | 106 | { |
107 | disable_irq_nosync(irq); | 107 | disable_irq_nosync(irq); |
108 | irq_desc[irq].handler = &systemh_irq_type; | 108 | irq_desc[irq].chip = &systemh_irq_type; |
109 | disable_systemh_irq(irq); | 109 | disable_systemh_irq(irq); |
110 | } | 110 | } |
111 | 111 | ||
diff --git a/arch/sh/boards/se/73180/irq.c b/arch/sh/boards/se/73180/irq.c index 70f04caad9a4..402735c7c898 100644 --- a/arch/sh/boards/se/73180/irq.c +++ b/arch/sh/boards/se/73180/irq.c | |||
@@ -85,7 +85,7 @@ void | |||
85 | make_intreq_irq(unsigned int irq) | 85 | make_intreq_irq(unsigned int irq) |
86 | { | 86 | { |
87 | disable_irq_nosync(irq); | 87 | disable_irq_nosync(irq); |
88 | irq_desc[irq].handler = &intreq_irq_type; | 88 | irq_desc[irq].chip = &intreq_irq_type; |
89 | disable_intreq_irq(irq); | 89 | disable_intreq_irq(irq); |
90 | } | 90 | } |
91 | 91 | ||
diff --git a/arch/sh/boards/superh/microdev/irq.c b/arch/sh/boards/superh/microdev/irq.c index efcbd86b7cd2..cb5999425d16 100644 --- a/arch/sh/boards/superh/microdev/irq.c +++ b/arch/sh/boards/superh/microdev/irq.c | |||
@@ -147,7 +147,7 @@ static void enable_microdev_irq(unsigned int irq) | |||
147 | static void __init make_microdev_irq(unsigned int irq) | 147 | static void __init make_microdev_irq(unsigned int irq) |
148 | { | 148 | { |
149 | disable_irq_nosync(irq); | 149 | disable_irq_nosync(irq); |
150 | irq_desc[irq].handler = µdev_irq_type; | 150 | irq_desc[irq].chip = µdev_irq_type; |
151 | disable_microdev_irq(irq); | 151 | disable_microdev_irq(irq); |
152 | } | 152 | } |
153 | 153 | ||
diff --git a/arch/sh/cchips/hd6446x/hd64461/setup.c b/arch/sh/cchips/hd6446x/hd64461/setup.c index f014b9bf6922..724db04cb392 100644 --- a/arch/sh/cchips/hd6446x/hd64461/setup.c +++ b/arch/sh/cchips/hd6446x/hd64461/setup.c | |||
@@ -154,7 +154,7 @@ int __init setup_hd64461(void) | |||
154 | outw(0xffff, HD64461_NIMR); | 154 | outw(0xffff, HD64461_NIMR); |
155 | 155 | ||
156 | for (i = HD64461_IRQBASE; i < HD64461_IRQBASE + 16; i++) { | 156 | for (i = HD64461_IRQBASE; i < HD64461_IRQBASE + 16; i++) { |
157 | irq_desc[i].handler = &hd64461_irq_type; | 157 | irq_desc[i].chip = &hd64461_irq_type; |
158 | } | 158 | } |
159 | 159 | ||
160 | setup_irq(CONFIG_HD64461_IRQ, &irq0); | 160 | setup_irq(CONFIG_HD64461_IRQ, &irq0); |
diff --git a/arch/sh/cchips/hd6446x/hd64465/setup.c b/arch/sh/cchips/hd6446x/hd64465/setup.c index 68e4c4e4283d..cf9142c620b7 100644 --- a/arch/sh/cchips/hd6446x/hd64465/setup.c +++ b/arch/sh/cchips/hd6446x/hd64465/setup.c | |||
@@ -182,7 +182,7 @@ static int __init setup_hd64465(void) | |||
182 | outw(0xffff, HD64465_REG_NIMR); /* mask all interrupts */ | 182 | outw(0xffff, HD64465_REG_NIMR); /* mask all interrupts */ |
183 | 183 | ||
184 | for (i = 0; i < HD64465_IRQ_NUM ; i++) { | 184 | for (i = 0; i < HD64465_IRQ_NUM ; i++) { |
185 | irq_desc[HD64465_IRQ_BASE + i].handler = &hd64465_irq_type; | 185 | irq_desc[HD64465_IRQ_BASE + i].chip = &hd64465_irq_type; |
186 | } | 186 | } |
187 | 187 | ||
188 | setup_irq(CONFIG_HD64465_IRQ, &irq0); | 188 | setup_irq(CONFIG_HD64465_IRQ, &irq0); |
diff --git a/arch/sh/cchips/voyagergx/irq.c b/arch/sh/cchips/voyagergx/irq.c index 2ee330b3c38f..892214bade19 100644 --- a/arch/sh/cchips/voyagergx/irq.c +++ b/arch/sh/cchips/voyagergx/irq.c | |||
@@ -191,7 +191,7 @@ void __init setup_voyagergx_irq(void) | |||
191 | flag = 1; | 191 | flag = 1; |
192 | } | 192 | } |
193 | if (flag == 1) | 193 | if (flag == 1) |
194 | irq_desc[VOYAGER_IRQ_BASE + i].handler = &voyagergx_irq_type; | 194 | irq_desc[VOYAGER_IRQ_BASE + i].chip = &voyagergx_irq_type; |
195 | } | 195 | } |
196 | 196 | ||
197 | setup_irq(IRQ_VOYAGER, &irq0); | 197 | setup_irq(IRQ_VOYAGER, &irq0); |
diff --git a/arch/sh/kernel/cpu/irq/imask.c b/arch/sh/kernel/cpu/irq/imask.c index baed9a550d39..a33ae3e0a5a5 100644 --- a/arch/sh/kernel/cpu/irq/imask.c +++ b/arch/sh/kernel/cpu/irq/imask.c | |||
@@ -105,6 +105,6 @@ static void shutdown_imask_irq(unsigned int irq) | |||
105 | void make_imask_irq(unsigned int irq) | 105 | void make_imask_irq(unsigned int irq) |
106 | { | 106 | { |
107 | disable_irq_nosync(irq); | 107 | disable_irq_nosync(irq); |
108 | irq_desc[irq].handler = &imask_irq_type; | 108 | irq_desc[irq].chip = &imask_irq_type; |
109 | enable_irq(irq); | 109 | enable_irq(irq); |
110 | } | 110 | } |
diff --git a/arch/sh/kernel/cpu/irq/intc2.c b/arch/sh/kernel/cpu/irq/intc2.c index 06e8afab32e4..30064bf6e154 100644 --- a/arch/sh/kernel/cpu/irq/intc2.c +++ b/arch/sh/kernel/cpu/irq/intc2.c | |||
@@ -137,7 +137,7 @@ void make_intc2_irq(unsigned int irq, | |||
137 | 137 | ||
138 | local_irq_restore(flags); | 138 | local_irq_restore(flags); |
139 | 139 | ||
140 | irq_desc[irq].handler = &intc2_irq_type; | 140 | irq_desc[irq].chip = &intc2_irq_type; |
141 | 141 | ||
142 | disable_intc2_irq(irq); | 142 | disable_intc2_irq(irq); |
143 | } | 143 | } |
diff --git a/arch/sh/kernel/cpu/irq/ipr.c b/arch/sh/kernel/cpu/irq/ipr.c index e55150ed0856..0373b65c77f9 100644 --- a/arch/sh/kernel/cpu/irq/ipr.c +++ b/arch/sh/kernel/cpu/irq/ipr.c | |||
@@ -115,7 +115,7 @@ void make_ipr_irq(unsigned int irq, unsigned int addr, int pos, int priority) | |||
115 | ipr_data[irq].shift = pos*4; /* POSition (0-3) x 4 means shift */ | 115 | ipr_data[irq].shift = pos*4; /* POSition (0-3) x 4 means shift */ |
116 | ipr_data[irq].priority = priority; | 116 | ipr_data[irq].priority = priority; |
117 | 117 | ||
118 | irq_desc[irq].handler = &ipr_irq_type; | 118 | irq_desc[irq].chip = &ipr_irq_type; |
119 | disable_ipr_irq(irq); | 119 | disable_ipr_irq(irq); |
120 | } | 120 | } |
121 | 121 | ||
diff --git a/arch/sh/kernel/cpu/irq/pint.c b/arch/sh/kernel/cpu/irq/pint.c index 95d6024fe1ae..714963a25bba 100644 --- a/arch/sh/kernel/cpu/irq/pint.c +++ b/arch/sh/kernel/cpu/irq/pint.c | |||
@@ -85,7 +85,7 @@ static void end_pint_irq(unsigned int irq) | |||
85 | void make_pint_irq(unsigned int irq) | 85 | void make_pint_irq(unsigned int irq) |
86 | { | 86 | { |
87 | disable_irq_nosync(irq); | 87 | disable_irq_nosync(irq); |
88 | irq_desc[irq].handler = &pint_irq_type; | 88 | irq_desc[irq].chip = &pint_irq_type; |
89 | disable_pint_irq(irq); | 89 | disable_pint_irq(irq); |
90 | } | 90 | } |
91 | 91 | ||
diff --git a/arch/sh/kernel/irq.c b/arch/sh/kernel/irq.c index b56e79632f24..c2e07f7f3496 100644 --- a/arch/sh/kernel/irq.c +++ b/arch/sh/kernel/irq.c | |||
@@ -47,7 +47,7 @@ int show_interrupts(struct seq_file *p, void *v) | |||
47 | goto unlock; | 47 | goto unlock; |
48 | seq_printf(p, "%3d: ",i); | 48 | seq_printf(p, "%3d: ",i); |
49 | seq_printf(p, "%10u ", kstat_irqs(i)); | 49 | seq_printf(p, "%10u ", kstat_irqs(i)); |
50 | seq_printf(p, " %14s", irq_desc[i].handler->typename); | 50 | seq_printf(p, " %14s", irq_desc[i].chip->typename); |
51 | seq_printf(p, " %s", action->name); | 51 | seq_printf(p, " %s", action->name); |
52 | 52 | ||
53 | for (action=action->next; action; action = action->next) | 53 | for (action=action->next; action; action = action->next) |
diff --git a/arch/sh64/kernel/irq.c b/arch/sh64/kernel/irq.c index d69879c0e063..675776a5477e 100644 --- a/arch/sh64/kernel/irq.c +++ b/arch/sh64/kernel/irq.c | |||
@@ -65,7 +65,7 @@ int show_interrupts(struct seq_file *p, void *v) | |||
65 | goto unlock; | 65 | goto unlock; |
66 | seq_printf(p, "%3d: ",i); | 66 | seq_printf(p, "%3d: ",i); |
67 | seq_printf(p, "%10u ", kstat_irqs(i)); | 67 | seq_printf(p, "%10u ", kstat_irqs(i)); |
68 | seq_printf(p, " %14s", irq_desc[i].handler->typename); | 68 | seq_printf(p, " %14s", irq_desc[i].chip->typename); |
69 | seq_printf(p, " %s", action->name); | 69 | seq_printf(p, " %s", action->name); |
70 | 70 | ||
71 | for (action=action->next; action; action = action->next) | 71 | for (action=action->next; action; action = action->next) |
diff --git a/arch/sh64/kernel/irq_intc.c b/arch/sh64/kernel/irq_intc.c index fc99bf4e362c..fa730f5fe2e6 100644 --- a/arch/sh64/kernel/irq_intc.c +++ b/arch/sh64/kernel/irq_intc.c | |||
@@ -178,7 +178,7 @@ static void end_intc_irq(unsigned int irq) | |||
178 | void make_intc_irq(unsigned int irq) | 178 | void make_intc_irq(unsigned int irq) |
179 | { | 179 | { |
180 | disable_irq_nosync(irq); | 180 | disable_irq_nosync(irq); |
181 | irq_desc[irq].handler = &intc_irq_type; | 181 | irq_desc[irq].chip = &intc_irq_type; |
182 | disable_intc_irq(irq); | 182 | disable_intc_irq(irq); |
183 | } | 183 | } |
184 | 184 | ||
@@ -208,7 +208,7 @@ void __init init_IRQ(void) | |||
208 | /* Set default: per-line enable/disable, priority driven ack/eoi */ | 208 | /* Set default: per-line enable/disable, priority driven ack/eoi */ |
209 | for (i = 0; i < NR_INTC_IRQS; i++) { | 209 | for (i = 0; i < NR_INTC_IRQS; i++) { |
210 | if (platform_int_priority[i] != NO_PRIORITY) { | 210 | if (platform_int_priority[i] != NO_PRIORITY) { |
211 | irq_desc[i].handler = &intc_irq_type; | 211 | irq_desc[i].chip = &intc_irq_type; |
212 | } | 212 | } |
213 | } | 213 | } |
214 | 214 | ||
diff --git a/arch/sh64/mach-cayman/irq.c b/arch/sh64/mach-cayman/irq.c index f797c84bfdd1..05eb7cdc26f0 100644 --- a/arch/sh64/mach-cayman/irq.c +++ b/arch/sh64/mach-cayman/irq.c | |||
@@ -187,7 +187,7 @@ void init_cayman_irq(void) | |||
187 | } | 187 | } |
188 | 188 | ||
189 | for (i=0; i<NR_EXT_IRQS; i++) { | 189 | for (i=0; i<NR_EXT_IRQS; i++) { |
190 | irq_desc[START_EXT_IRQS + i].handler = &cayman_irq_type; | 190 | irq_desc[START_EXT_IRQS + i].chip = &cayman_irq_type; |
191 | } | 191 | } |
192 | 192 | ||
193 | /* Setup the SMSC interrupt */ | 193 | /* Setup the SMSC interrupt */ |
diff --git a/arch/sparc64/kernel/irq.c b/arch/sparc64/kernel/irq.c index cc89b06d0178..5d7c821ab7f6 100644 --- a/arch/sparc64/kernel/irq.c +++ b/arch/sparc64/kernel/irq.c | |||
@@ -151,7 +151,7 @@ int show_interrupts(struct seq_file *p, void *v) | |||
151 | for_each_online_cpu(j) | 151 | for_each_online_cpu(j) |
152 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); | 152 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); |
153 | #endif | 153 | #endif |
154 | seq_printf(p, " %9s", irq_desc[i].handler->typename); | 154 | seq_printf(p, " %9s", irq_desc[i].chip->typename); |
155 | seq_printf(p, " %s", action->name); | 155 | seq_printf(p, " %s", action->name); |
156 | 156 | ||
157 | for (action=action->next; action; action = action->next) | 157 | for (action=action->next; action; action = action->next) |
@@ -414,8 +414,8 @@ void irq_install_pre_handler(int virt_irq, | |||
414 | data->pre_handler_arg1 = arg1; | 414 | data->pre_handler_arg1 = arg1; |
415 | data->pre_handler_arg2 = arg2; | 415 | data->pre_handler_arg2 = arg2; |
416 | 416 | ||
417 | desc->handler = (desc->handler == &sun4u_irq ? | 417 | desc->chip = (desc->chip == &sun4u_irq ? |
418 | &sun4u_irq_ack : &sun4v_irq_ack); | 418 | &sun4u_irq_ack : &sun4v_irq_ack); |
419 | } | 419 | } |
420 | 420 | ||
421 | unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap) | 421 | unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap) |
@@ -431,7 +431,7 @@ unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap) | |||
431 | bucket = &ivector_table[ino]; | 431 | bucket = &ivector_table[ino]; |
432 | if (!bucket->virt_irq) { | 432 | if (!bucket->virt_irq) { |
433 | bucket->virt_irq = virt_irq_alloc(__irq(bucket)); | 433 | bucket->virt_irq = virt_irq_alloc(__irq(bucket)); |
434 | irq_desc[bucket->virt_irq].handler = &sun4u_irq; | 434 | irq_desc[bucket->virt_irq].chip = &sun4u_irq; |
435 | } | 435 | } |
436 | 436 | ||
437 | desc = irq_desc + bucket->virt_irq; | 437 | desc = irq_desc + bucket->virt_irq; |
@@ -465,7 +465,7 @@ unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino) | |||
465 | bucket = &ivector_table[sysino]; | 465 | bucket = &ivector_table[sysino]; |
466 | if (!bucket->virt_irq) { | 466 | if (!bucket->virt_irq) { |
467 | bucket->virt_irq = virt_irq_alloc(__irq(bucket)); | 467 | bucket->virt_irq = virt_irq_alloc(__irq(bucket)); |
468 | irq_desc[bucket->virt_irq].handler = &sun4v_irq; | 468 | irq_desc[bucket->virt_irq].chip = &sun4v_irq; |
469 | } | 469 | } |
470 | 470 | ||
471 | desc = irq_desc + bucket->virt_irq; | 471 | desc = irq_desc + bucket->virt_irq; |
diff --git a/arch/um/kernel/irq.c b/arch/um/kernel/irq.c index 2ffda012385e..fae43a3054a0 100644 --- a/arch/um/kernel/irq.c +++ b/arch/um/kernel/irq.c | |||
@@ -63,7 +63,7 @@ int show_interrupts(struct seq_file *p, void *v) | |||
63 | for_each_online_cpu(j) | 63 | for_each_online_cpu(j) |
64 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); | 64 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); |
65 | #endif | 65 | #endif |
66 | seq_printf(p, " %14s", irq_desc[i].handler->typename); | 66 | seq_printf(p, " %14s", irq_desc[i].chip->typename); |
67 | seq_printf(p, " %s", action->name); | 67 | seq_printf(p, " %s", action->name); |
68 | 68 | ||
69 | for (action=action->next; action; action = action->next) | 69 | for (action=action->next; action; action = action->next) |
@@ -451,13 +451,13 @@ void __init init_IRQ(void) | |||
451 | irq_desc[TIMER_IRQ].status = IRQ_DISABLED; | 451 | irq_desc[TIMER_IRQ].status = IRQ_DISABLED; |
452 | irq_desc[TIMER_IRQ].action = NULL; | 452 | irq_desc[TIMER_IRQ].action = NULL; |
453 | irq_desc[TIMER_IRQ].depth = 1; | 453 | irq_desc[TIMER_IRQ].depth = 1; |
454 | irq_desc[TIMER_IRQ].handler = &SIGVTALRM_irq_type; | 454 | irq_desc[TIMER_IRQ].chip = &SIGVTALRM_irq_type; |
455 | enable_irq(TIMER_IRQ); | 455 | enable_irq(TIMER_IRQ); |
456 | for (i = 1; i < NR_IRQS; i++) { | 456 | for (i = 1; i < NR_IRQS; i++) { |
457 | irq_desc[i].status = IRQ_DISABLED; | 457 | irq_desc[i].status = IRQ_DISABLED; |
458 | irq_desc[i].action = NULL; | 458 | irq_desc[i].action = NULL; |
459 | irq_desc[i].depth = 1; | 459 | irq_desc[i].depth = 1; |
460 | irq_desc[i].handler = &normal_irq_type; | 460 | irq_desc[i].chip = &normal_irq_type; |
461 | enable_irq(i); | 461 | enable_irq(i); |
462 | } | 462 | } |
463 | } | 463 | } |
diff --git a/arch/v850/kernel/irq.c b/arch/v850/kernel/irq.c index 7a151c26f82e..858c45819aab 100644 --- a/arch/v850/kernel/irq.c +++ b/arch/v850/kernel/irq.c | |||
@@ -65,10 +65,10 @@ int show_interrupts(struct seq_file *p, void *v) | |||
65 | int j; | 65 | int j; |
66 | int count = 0; | 66 | int count = 0; |
67 | int num = -1; | 67 | int num = -1; |
68 | const char *type_name = irq_desc[irq].handler->typename; | 68 | const char *type_name = irq_desc[irq].chip->typename; |
69 | 69 | ||
70 | for (j = 0; j < NR_IRQS; j++) | 70 | for (j = 0; j < NR_IRQS; j++) |
71 | if (irq_desc[j].handler->typename == type_name){ | 71 | if (irq_desc[j].chip->typename == type_name){ |
72 | if (irq == j) | 72 | if (irq == j) |
73 | num = count; | 73 | num = count; |
74 | count++; | 74 | count++; |
@@ -117,7 +117,7 @@ init_irq_handlers (int base_irq, int num, int interval, | |||
117 | irq_desc[base_irq].status = IRQ_DISABLED; | 117 | irq_desc[base_irq].status = IRQ_DISABLED; |
118 | irq_desc[base_irq].action = NULL; | 118 | irq_desc[base_irq].action = NULL; |
119 | irq_desc[base_irq].depth = 1; | 119 | irq_desc[base_irq].depth = 1; |
120 | irq_desc[base_irq].handler = irq_type; | 120 | irq_desc[base_irq].chip = irq_type; |
121 | base_irq += interval; | 121 | base_irq += interval; |
122 | } | 122 | } |
123 | } | 123 | } |
diff --git a/arch/x86_64/kernel/i8259.c b/arch/x86_64/kernel/i8259.c index 86b2c1e197aa..3dd1659427dc 100644 --- a/arch/x86_64/kernel/i8259.c +++ b/arch/x86_64/kernel/i8259.c | |||
@@ -235,7 +235,7 @@ void make_8259A_irq(unsigned int irq) | |||
235 | { | 235 | { |
236 | disable_irq_nosync(irq); | 236 | disable_irq_nosync(irq); |
237 | io_apic_irqs &= ~(1<<irq); | 237 | io_apic_irqs &= ~(1<<irq); |
238 | irq_desc[irq].handler = &i8259A_irq_type; | 238 | irq_desc[irq].chip = &i8259A_irq_type; |
239 | enable_irq(irq); | 239 | enable_irq(irq); |
240 | } | 240 | } |
241 | 241 | ||
@@ -468,12 +468,12 @@ void __init init_ISA_irqs (void) | |||
468 | /* | 468 | /* |
469 | * 16 old-style INTA-cycle interrupts: | 469 | * 16 old-style INTA-cycle interrupts: |
470 | */ | 470 | */ |
471 | irq_desc[i].handler = &i8259A_irq_type; | 471 | irq_desc[i].chip = &i8259A_irq_type; |
472 | } else { | 472 | } else { |
473 | /* | 473 | /* |
474 | * 'high' PCI IRQs filled in on demand | 474 | * 'high' PCI IRQs filled in on demand |
475 | */ | 475 | */ |
476 | irq_desc[i].handler = &no_irq_type; | 476 | irq_desc[i].chip = &no_irq_type; |
477 | } | 477 | } |
478 | } | 478 | } |
479 | } | 479 | } |
diff --git a/arch/x86_64/kernel/io_apic.c b/arch/x86_64/kernel/io_apic.c index c768d8a036d0..88a8736eb8ce 100644 --- a/arch/x86_64/kernel/io_apic.c +++ b/arch/x86_64/kernel/io_apic.c | |||
@@ -876,15 +876,17 @@ static struct hw_interrupt_type ioapic_edge_type; | |||
876 | #define IOAPIC_EDGE 0 | 876 | #define IOAPIC_EDGE 0 |
877 | #define IOAPIC_LEVEL 1 | 877 | #define IOAPIC_LEVEL 1 |
878 | 878 | ||
879 | static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger) | 879 | static void ioapic_register_intr(int irq, int vector, unsigned long trigger) |
880 | { | 880 | { |
881 | unsigned idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq; | 881 | unsigned idx; |
882 | |||
883 | idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq; | ||
882 | 884 | ||
883 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || | 885 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
884 | trigger == IOAPIC_LEVEL) | 886 | trigger == IOAPIC_LEVEL) |
885 | irq_desc[idx].handler = &ioapic_level_type; | 887 | irq_desc[idx].chip = &ioapic_level_type; |
886 | else | 888 | else |
887 | irq_desc[idx].handler = &ioapic_edge_type; | 889 | irq_desc[idx].chip = &ioapic_edge_type; |
888 | set_intr_gate(vector, interrupt[idx]); | 890 | set_intr_gate(vector, interrupt[idx]); |
889 | } | 891 | } |
890 | 892 | ||
@@ -986,7 +988,7 @@ static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, in | |||
986 | * The timer IRQ doesn't have to know that behind the | 988 | * The timer IRQ doesn't have to know that behind the |
987 | * scene we have a 8259A-master in AEOI mode ... | 989 | * scene we have a 8259A-master in AEOI mode ... |
988 | */ | 990 | */ |
989 | irq_desc[0].handler = &ioapic_edge_type; | 991 | irq_desc[0].chip = &ioapic_edge_type; |
990 | 992 | ||
991 | /* | 993 | /* |
992 | * Add it to the IO-APIC irq-routing table: | 994 | * Add it to the IO-APIC irq-routing table: |
@@ -1683,7 +1685,7 @@ static inline void init_IO_APIC_traps(void) | |||
1683 | make_8259A_irq(irq); | 1685 | make_8259A_irq(irq); |
1684 | else | 1686 | else |
1685 | /* Strange. Oh, well.. */ | 1687 | /* Strange. Oh, well.. */ |
1686 | irq_desc[irq].handler = &no_irq_type; | 1688 | irq_desc[irq].chip = &no_irq_type; |
1687 | } | 1689 | } |
1688 | } | 1690 | } |
1689 | } | 1691 | } |
@@ -1900,7 +1902,7 @@ static inline void check_timer(void) | |||
1900 | apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ..."); | 1902 | apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ..."); |
1901 | 1903 | ||
1902 | disable_8259A_irq(0); | 1904 | disable_8259A_irq(0); |
1903 | irq_desc[0].handler = &lapic_irq_type; | 1905 | irq_desc[0].chip = &lapic_irq_type; |
1904 | apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */ | 1906 | apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */ |
1905 | enable_8259A_irq(0); | 1907 | enable_8259A_irq(0); |
1906 | 1908 | ||
diff --git a/arch/x86_64/kernel/irq.c b/arch/x86_64/kernel/irq.c index bfa82f52a5cc..0c2fb2c77bd0 100644 --- a/arch/x86_64/kernel/irq.c +++ b/arch/x86_64/kernel/irq.c | |||
@@ -79,7 +79,7 @@ int show_interrupts(struct seq_file *p, void *v) | |||
79 | for_each_online_cpu(j) | 79 | for_each_online_cpu(j) |
80 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); | 80 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); |
81 | #endif | 81 | #endif |
82 | seq_printf(p, " %14s", irq_desc[i].handler->typename); | 82 | seq_printf(p, " %14s", irq_desc[i].chip->typename); |
83 | 83 | ||
84 | seq_printf(p, " %s", action->name); | 84 | seq_printf(p, " %s", action->name); |
85 | for (action=action->next; action; action = action->next) | 85 | for (action=action->next; action; action = action->next) |
@@ -151,8 +151,8 @@ void fixup_irqs(cpumask_t map) | |||
151 | printk("Breaking affinity for irq %i\n", irq); | 151 | printk("Breaking affinity for irq %i\n", irq); |
152 | mask = map; | 152 | mask = map; |
153 | } | 153 | } |
154 | if (irq_desc[irq].handler->set_affinity) | 154 | if (irq_desc[irq].chip->set_affinity) |
155 | irq_desc[irq].handler->set_affinity(irq, mask); | 155 | irq_desc[irq].chip->set_affinity(irq, mask); |
156 | else if (irq_desc[irq].action && !(warned++)) | 156 | else if (irq_desc[irq].action && !(warned++)) |
157 | printk("Cannot set affinity for irq %i\n", irq); | 157 | printk("Cannot set affinity for irq %i\n", irq); |
158 | } | 158 | } |
diff --git a/arch/xtensa/kernel/irq.c b/arch/xtensa/kernel/irq.c index 51f9bed455fa..1cf744ee0959 100644 --- a/arch/xtensa/kernel/irq.c +++ b/arch/xtensa/kernel/irq.c | |||
@@ -100,7 +100,7 @@ int show_interrupts(struct seq_file *p, void *v) | |||
100 | for_each_online_cpu(j) | 100 | for_each_online_cpu(j) |
101 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); | 101 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); |
102 | #endif | 102 | #endif |
103 | seq_printf(p, " %14s", irq_desc[i].handler->typename); | 103 | seq_printf(p, " %14s", irq_desc[i].chip->typename); |
104 | seq_printf(p, " %s", action->name); | 104 | seq_printf(p, " %s", action->name); |
105 | 105 | ||
106 | for (action=action->next; action; action = action->next) | 106 | for (action=action->next; action; action = action->next) |
@@ -181,7 +181,7 @@ void __init init_IRQ(void) | |||
181 | int i; | 181 | int i; |
182 | 182 | ||
183 | for (i=0; i < XTENSA_NR_IRQS; i++) | 183 | for (i=0; i < XTENSA_NR_IRQS; i++) |
184 | irq_desc[i].handler = &xtensa_irq_type; | 184 | irq_desc[i].chip = &xtensa_irq_type; |
185 | 185 | ||
186 | cached_irq_mask = 0; | 186 | cached_irq_mask = 0; |
187 | 187 | ||