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Diffstat (limited to 'arch/m32r/kernel/setup_m32700ut.c')
-rw-r--r--arch/m32r/kernel/setup_m32700ut.c28
1 files changed, 14 insertions, 14 deletions
diff --git a/arch/m32r/kernel/setup_m32700ut.c b/arch/m32r/kernel/setup_m32700ut.c
index fad1fc99bb27..b6ab00eff580 100644
--- a/arch/m32r/kernel/setup_m32700ut.c
+++ b/arch/m32r/kernel/setup_m32700ut.c
@@ -301,7 +301,7 @@ void __init init_IRQ(void)
301#if defined(CONFIG_SMC91X) 301#if defined(CONFIG_SMC91X)
302 /* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/ 302 /* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/
303 irq_desc[M32700UT_LAN_IRQ_LAN].status = IRQ_DISABLED; 303 irq_desc[M32700UT_LAN_IRQ_LAN].status = IRQ_DISABLED;
304 irq_desc[M32700UT_LAN_IRQ_LAN].handler = &m32700ut_lanpld_irq_type; 304 irq_desc[M32700UT_LAN_IRQ_LAN].chip = &m32700ut_lanpld_irq_type;
305 irq_desc[M32700UT_LAN_IRQ_LAN].action = 0; 305 irq_desc[M32700UT_LAN_IRQ_LAN].action = 0;
306 irq_desc[M32700UT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */ 306 irq_desc[M32700UT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */
307 lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ 307 lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */
@@ -310,7 +310,7 @@ void __init init_IRQ(void)
310 310
311 /* MFT2 : system timer */ 311 /* MFT2 : system timer */
312 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 312 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
313 irq_desc[M32R_IRQ_MFT2].handler = &m32700ut_irq_type; 313 irq_desc[M32R_IRQ_MFT2].chip = &m32700ut_irq_type;
314 irq_desc[M32R_IRQ_MFT2].action = 0; 314 irq_desc[M32R_IRQ_MFT2].action = 0;
315 irq_desc[M32R_IRQ_MFT2].depth = 1; 315 irq_desc[M32R_IRQ_MFT2].depth = 1;
316 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 316 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
@@ -318,7 +318,7 @@ void __init init_IRQ(void)
318 318
319 /* SIO0 : receive */ 319 /* SIO0 : receive */
320 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 320 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
321 irq_desc[M32R_IRQ_SIO0_R].handler = &m32700ut_irq_type; 321 irq_desc[M32R_IRQ_SIO0_R].chip = &m32700ut_irq_type;
322 irq_desc[M32R_IRQ_SIO0_R].action = 0; 322 irq_desc[M32R_IRQ_SIO0_R].action = 0;
323 irq_desc[M32R_IRQ_SIO0_R].depth = 1; 323 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
324 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 324 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
@@ -326,7 +326,7 @@ void __init init_IRQ(void)
326 326
327 /* SIO0 : send */ 327 /* SIO0 : send */
328 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 328 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
329 irq_desc[M32R_IRQ_SIO0_S].handler = &m32700ut_irq_type; 329 irq_desc[M32R_IRQ_SIO0_S].chip = &m32700ut_irq_type;
330 irq_desc[M32R_IRQ_SIO0_S].action = 0; 330 irq_desc[M32R_IRQ_SIO0_S].action = 0;
331 irq_desc[M32R_IRQ_SIO0_S].depth = 1; 331 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
332 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 332 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
@@ -334,7 +334,7 @@ void __init init_IRQ(void)
334 334
335 /* SIO1 : receive */ 335 /* SIO1 : receive */
336 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; 336 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
337 irq_desc[M32R_IRQ_SIO1_R].handler = &m32700ut_irq_type; 337 irq_desc[M32R_IRQ_SIO1_R].chip = &m32700ut_irq_type;
338 irq_desc[M32R_IRQ_SIO1_R].action = 0; 338 irq_desc[M32R_IRQ_SIO1_R].action = 0;
339 irq_desc[M32R_IRQ_SIO1_R].depth = 1; 339 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
340 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 340 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
@@ -342,7 +342,7 @@ void __init init_IRQ(void)
342 342
343 /* SIO1 : send */ 343 /* SIO1 : send */
344 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; 344 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
345 irq_desc[M32R_IRQ_SIO1_S].handler = &m32700ut_irq_type; 345 irq_desc[M32R_IRQ_SIO1_S].chip = &m32700ut_irq_type;
346 irq_desc[M32R_IRQ_SIO1_S].action = 0; 346 irq_desc[M32R_IRQ_SIO1_S].action = 0;
347 irq_desc[M32R_IRQ_SIO1_S].depth = 1; 347 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
348 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 348 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
@@ -350,7 +350,7 @@ void __init init_IRQ(void)
350 350
351 /* DMA1 : */ 351 /* DMA1 : */
352 irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED; 352 irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED;
353 irq_desc[M32R_IRQ_DMA1].handler = &m32700ut_irq_type; 353 irq_desc[M32R_IRQ_DMA1].chip = &m32700ut_irq_type;
354 irq_desc[M32R_IRQ_DMA1].action = 0; 354 irq_desc[M32R_IRQ_DMA1].action = 0;
355 irq_desc[M32R_IRQ_DMA1].depth = 1; 355 irq_desc[M32R_IRQ_DMA1].depth = 1;
356 icu_data[M32R_IRQ_DMA1].icucr = 0; 356 icu_data[M32R_IRQ_DMA1].icucr = 0;
@@ -359,7 +359,7 @@ void __init init_IRQ(void)
359#ifdef CONFIG_SERIAL_M32R_PLDSIO 359#ifdef CONFIG_SERIAL_M32R_PLDSIO
360 /* INT#1: SIO0 Receive on PLD */ 360 /* INT#1: SIO0 Receive on PLD */
361 irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED; 361 irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED;
362 irq_desc[PLD_IRQ_SIO0_RCV].handler = &m32700ut_pld_irq_type; 362 irq_desc[PLD_IRQ_SIO0_RCV].chip = &m32700ut_pld_irq_type;
363 irq_desc[PLD_IRQ_SIO0_RCV].action = 0; 363 irq_desc[PLD_IRQ_SIO0_RCV].action = 0;
364 irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */ 364 irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */
365 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; 365 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
@@ -367,7 +367,7 @@ void __init init_IRQ(void)
367 367
368 /* INT#1: SIO0 Send on PLD */ 368 /* INT#1: SIO0 Send on PLD */
369 irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED; 369 irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED;
370 irq_desc[PLD_IRQ_SIO0_SND].handler = &m32700ut_pld_irq_type; 370 irq_desc[PLD_IRQ_SIO0_SND].chip = &m32700ut_pld_irq_type;
371 irq_desc[PLD_IRQ_SIO0_SND].action = 0; 371 irq_desc[PLD_IRQ_SIO0_SND].action = 0;
372 irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */ 372 irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */
373 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; 373 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
@@ -376,7 +376,7 @@ void __init init_IRQ(void)
376 376
377 /* INT#1: CFC IREQ on PLD */ 377 /* INT#1: CFC IREQ on PLD */
378 irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; 378 irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;
379 irq_desc[PLD_IRQ_CFIREQ].handler = &m32700ut_pld_irq_type; 379 irq_desc[PLD_IRQ_CFIREQ].chip = &m32700ut_pld_irq_type;
380 irq_desc[PLD_IRQ_CFIREQ].action = 0; 380 irq_desc[PLD_IRQ_CFIREQ].action = 0;
381 irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */ 381 irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
382 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ 382 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */
@@ -384,7 +384,7 @@ void __init init_IRQ(void)
384 384
385 /* INT#1: CFC Insert on PLD */ 385 /* INT#1: CFC Insert on PLD */
386 irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; 386 irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;
387 irq_desc[PLD_IRQ_CFC_INSERT].handler = &m32700ut_pld_irq_type; 387 irq_desc[PLD_IRQ_CFC_INSERT].chip = &m32700ut_pld_irq_type;
388 irq_desc[PLD_IRQ_CFC_INSERT].action = 0; 388 irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
389 irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */ 389 irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
390 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ 390 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
@@ -392,7 +392,7 @@ void __init init_IRQ(void)
392 392
393 /* INT#1: CFC Eject on PLD */ 393 /* INT#1: CFC Eject on PLD */
394 irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED; 394 irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED;
395 irq_desc[PLD_IRQ_CFC_EJECT].handler = &m32700ut_pld_irq_type; 395 irq_desc[PLD_IRQ_CFC_EJECT].chip = &m32700ut_pld_irq_type;
396 irq_desc[PLD_IRQ_CFC_EJECT].action = 0; 396 irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
397 irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */ 397 irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */
398 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ 398 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
@@ -416,7 +416,7 @@ void __init init_IRQ(void)
416 outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ 416 outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */
417 417
418 irq_desc[M32700UT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED; 418 irq_desc[M32700UT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED;
419 irq_desc[M32700UT_LCD_IRQ_USB_INT1].handler = &m32700ut_lcdpld_irq_type; 419 irq_desc[M32700UT_LCD_IRQ_USB_INT1].chip = &m32700ut_lcdpld_irq_type;
420 irq_desc[M32700UT_LCD_IRQ_USB_INT1].action = 0; 420 irq_desc[M32700UT_LCD_IRQ_USB_INT1].action = 0;
421 irq_desc[M32700UT_LCD_IRQ_USB_INT1].depth = 1; 421 irq_desc[M32700UT_LCD_IRQ_USB_INT1].depth = 1;
422 lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ 422 lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
@@ -434,7 +434,7 @@ void __init init_IRQ(void)
434 * INT3# is used for AR 434 * INT3# is used for AR
435 */ 435 */
436 irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED; 436 irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED;
437 irq_desc[M32R_IRQ_INT3].handler = &m32700ut_irq_type; 437 irq_desc[M32R_IRQ_INT3].chip = &m32700ut_irq_type;
438 irq_desc[M32R_IRQ_INT3].action = 0; 438 irq_desc[M32R_IRQ_INT3].action = 0;
439 irq_desc[M32R_IRQ_INT3].depth = 1; 439 irq_desc[M32R_IRQ_INT3].depth = 1;
440 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 440 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;